xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp (revision d4eeb02986980bf33dd56c41ceb9fc5f180c0d47) 
1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an Mips MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstPrinter.h"
14 #include "MipsInstrInfo.h"
15 #include "MipsMCExpr.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "asm-printer"
26 
27 #define PRINT_ALIAS_INSTR
28 #include "MipsGenAsmWriter.inc"
29 
30 template<unsigned R>
31 static bool isReg(const MCInst &MI, unsigned OpNo) {
32   assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33   return MI.getOperand(OpNo).getReg() == R;
34 }
35 
36 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
37   switch (CC) {
38   case FCOND_F:
39   case FCOND_T:   return "f";
40   case FCOND_UN:
41   case FCOND_OR:  return "un";
42   case FCOND_OEQ:
43   case FCOND_UNE: return "eq";
44   case FCOND_UEQ:
45   case FCOND_ONE: return "ueq";
46   case FCOND_OLT:
47   case FCOND_UGE: return "olt";
48   case FCOND_ULT:
49   case FCOND_OGE: return "ult";
50   case FCOND_OLE:
51   case FCOND_UGT: return "ole";
52   case FCOND_ULE:
53   case FCOND_OGT: return "ule";
54   case FCOND_SF:
55   case FCOND_ST:  return "sf";
56   case FCOND_NGLE:
57   case FCOND_GLE: return "ngle";
58   case FCOND_SEQ:
59   case FCOND_SNE: return "seq";
60   case FCOND_NGL:
61   case FCOND_GL:  return "ngl";
62   case FCOND_LT:
63   case FCOND_NLT: return "lt";
64   case FCOND_NGE:
65   case FCOND_GE:  return "nge";
66   case FCOND_LE:
67   case FCOND_NLE: return "le";
68   case FCOND_NGT:
69   case FCOND_GT:  return "ngt";
70   }
71   llvm_unreachable("Impossible condition code!");
72 }
73 
74 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
75   OS << '$' << StringRef(getRegisterName(RegNo)).lower();
76 }
77 
78 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
79                                 StringRef Annot, const MCSubtargetInfo &STI,
80                                 raw_ostream &O) {
81   switch (MI->getOpcode()) {
82   default:
83     break;
84   case Mips::RDHWR:
85   case Mips::RDHWR64:
86     O << "\t.set\tpush\n";
87     O << "\t.set\tmips32r2\n";
88     break;
89   case Mips::Save16:
90     O << "\tsave\t";
91     printSaveRestore(MI, O);
92     O << " # 16 bit inst\n";
93     return;
94   case Mips::SaveX16:
95     O << "\tsave\t";
96     printSaveRestore(MI, O);
97     O << "\n";
98     return;
99   case Mips::Restore16:
100     O << "\trestore\t";
101     printSaveRestore(MI, O);
102     O << " # 16 bit inst\n";
103     return;
104   case Mips::RestoreX16:
105     O << "\trestore\t";
106     printSaveRestore(MI, O);
107     O << "\n";
108     return;
109   }
110 
111   // Try to print any aliases first.
112   if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O))
113     printInstruction(MI, Address, O);
114   printAnnotation(O, Annot);
115 
116   switch (MI->getOpcode()) {
117   default:
118     break;
119   case Mips::RDHWR:
120   case Mips::RDHWR64:
121     O << "\n\t.set\tpop";
122   }
123 }
124 
125 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
126                                    raw_ostream &O) {
127   const MCOperand &Op = MI->getOperand(OpNo);
128   if (Op.isReg()) {
129     printRegName(O, Op.getReg());
130     return;
131   }
132 
133   if (Op.isImm()) {
134     O << formatImm(Op.getImm());
135     return;
136   }
137 
138   assert(Op.isExpr() && "unknown operand kind in printOperand");
139   Op.getExpr()->print(O, &MAI, true);
140 }
141 
142 template <unsigned Bits, unsigned Offset>
143 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
144   const MCOperand &MO = MI->getOperand(opNum);
145   if (MO.isImm()) {
146     uint64_t Imm = MO.getImm();
147     Imm -= Offset;
148     Imm &= (1 << Bits) - 1;
149     Imm += Offset;
150     O << formatImm(Imm);
151     return;
152   }
153 
154   printOperand(MI, opNum, O);
155 }
156 
157 void MipsInstPrinter::
158 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
159   // Load/Store memory operands -- imm($reg)
160   // If PIC target the target is loaded as the
161   // pattern lw $25,%call16($28)
162 
163   // opNum can be invalid if instruction had reglist as operand.
164   // MemOperand is always last operand of instruction (base + offset).
165   switch (MI->getOpcode()) {
166   default:
167     break;
168   case Mips::SWM32_MM:
169   case Mips::LWM32_MM:
170   case Mips::SWM16_MM:
171   case Mips::SWM16_MMR6:
172   case Mips::LWM16_MM:
173   case Mips::LWM16_MMR6:
174     opNum = MI->getNumOperands() - 2;
175     break;
176   }
177 
178   printOperand(MI, opNum+1, O);
179   O << "(";
180   printOperand(MI, opNum, O);
181   O << ")";
182 }
183 
184 void MipsInstPrinter::
185 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
186   // when using stack locations for not load/store instructions
187   // print the same way as all normal 3 operand instructions.
188   printOperand(MI, opNum, O);
189   O << ", ";
190   printOperand(MI, opNum+1, O);
191 }
192 
193 void MipsInstPrinter::
194 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
195   const MCOperand& MO = MI->getOperand(opNum);
196   O << MipsFCCToString((Mips::CondCode)MO.getImm());
197 }
198 
199 void MipsInstPrinter::
200 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
201   llvm_unreachable("TODO");
202 }
203 
204 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
205                                  unsigned OpNo, raw_ostream &OS) {
206   OS << "\t" << Str << "\t";
207   printOperand(&MI, OpNo, OS);
208   return true;
209 }
210 
211 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
212                                  unsigned OpNo0, unsigned OpNo1,
213                                  raw_ostream &OS) {
214   printAlias(Str, MI, OpNo0, OS);
215   OS << ", ";
216   printOperand(&MI, OpNo1, OS);
217   return true;
218 }
219 
220 bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
221   switch (MI.getOpcode()) {
222   case Mips::BEQ:
223   case Mips::BEQ_MM:
224     // beq $zero, $zero, $L2 => b $L2
225     // beq $r0, $zero, $L2 => beqz $r0, $L2
226     return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
227             printAlias("b", MI, 2, OS)) ||
228            (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
229   case Mips::BEQ64:
230     // beq $r0, $zero, $L2 => beqz $r0, $L2
231     return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
232   case Mips::BNE:
233   case Mips::BNE_MM:
234     // bne $r0, $zero, $L2 => bnez $r0, $L2
235     return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
236   case Mips::BNE64:
237     // bne $r0, $zero, $L2 => bnez $r0, $L2
238     return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
239   case Mips::BGEZAL:
240     // bgezal $zero, $L1 => bal $L1
241     return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
242   case Mips::BC1T:
243     // bc1t $fcc0, $L1 => bc1t $L1
244     return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
245   case Mips::BC1F:
246     // bc1f $fcc0, $L1 => bc1f $L1
247     return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
248   case Mips::JALR:
249     // jalr $ra, $r1 => jalr $r1
250     return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
251   case Mips::JALR64:
252     // jalr $ra, $r1 => jalr $r1
253     return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
254   case Mips::NOR:
255   case Mips::NOR_MM:
256   case Mips::NOR_MMR6:
257     // nor $r0, $r1, $zero => not $r0, $r1
258     return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
259   case Mips::NOR64:
260     // nor $r0, $r1, $zero => not $r0, $r1
261     return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
262   case Mips::OR:
263     // or $r0, $r1, $zero => move $r0, $r1
264     return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
265   default: return false;
266   }
267 }
268 
269 void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
270   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
271     if (i != 0) O << ", ";
272     if (MI->getOperand(i).isReg())
273       printRegName(O, MI->getOperand(i).getReg());
274     else
275       printUImm<16>(MI, i, O);
276   }
277 }
278 
279 void MipsInstPrinter::
280 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
281   // - 2 because register List is always first operand of instruction and it is
282   // always followed by memory operand (base + offset).
283   for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
284     if (i != opNum)
285       O << ", ";
286     printRegName(O, MI->getOperand(i).getReg());
287   }
288 }
289