1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Mips Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "Mips.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } 67 68 bool hasCOP3() const { 69 // Only present in MIPS-I and MIPS-II 70 return !hasMips32() && !hasMips3(); 71 } 72 73 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 74 ArrayRef<uint8_t> Bytes, uint64_t Address, 75 raw_ostream &VStream, 76 raw_ostream &CStream) const override; 77 }; 78 79 } // end anonymous namespace 80 81 // Forward declare these because the autogenerated code will reference them. 82 // Definitions are further down. 83 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 99 unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 114 unsigned Insn, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 129 unsigned RegNo, 130 uint64_t Address, 131 const void *Decoder); 132 133 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 134 unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder); 137 138 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 139 unsigned RegNo, 140 uint64_t Address, 141 const void *Decoder); 142 143 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 193 unsigned RegNo, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 198 unsigned RegNo, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 203 unsigned RegNo, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 213 unsigned Offset, 214 uint64_t Address, 215 const void *Decoder); 216 217 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 218 unsigned Insn, 219 uint64_t Address, 220 const void *Decoder); 221 222 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 223 unsigned Offset, 224 uint64_t Address, 225 const void *Decoder); 226 227 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 233 unsigned Offset, 234 uint64_t Address, 235 const void *Decoder); 236 237 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 238 // shifted left by 1 bit. 239 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 240 unsigned Offset, 241 uint64_t Address, 242 const void *Decoder); 243 244 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 245 // shifted left by 1 bit. 246 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 247 unsigned Offset, 248 uint64_t Address, 249 const void *Decoder); 250 251 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 252 // shifted left by 1 bit. 253 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 254 unsigned Offset, 255 uint64_t Address, 256 const void *Decoder); 257 258 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 259 // shifted left by 1 bit. 260 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 261 unsigned Offset, 262 uint64_t Address, 263 const void *Decoder); 264 265 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 266 // shifted left by 1 bit. 267 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeMem(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeMemEVA(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 291 unsigned Insn, 292 uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 296 unsigned Insn, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 301 unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodeSyncI(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeSynciR6(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 323 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 324 unsigned Insn, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 334 unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 354 unsigned Insn, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 359 uint64_t Address, 360 const void *Decoder); 361 362 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 363 uint64_t Address, 364 const void *Decoder); 365 366 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 370 const void *Decoder); 371 372 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 375 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 376 uint64_t Address, 377 const void *Decoder); 378 379 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 380 unsigned Insn, 381 uint64_t Address, 382 const void *Decoder); 383 384 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 385 unsigned Value, 386 uint64_t Address, 387 const void *Decoder); 388 389 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 390 unsigned Value, 391 uint64_t Address, 392 const void *Decoder); 393 394 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 395 unsigned Value, 396 uint64_t Address, 397 const void *Decoder); 398 399 template <unsigned Bits, int Offset, int Scale> 400 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 401 uint64_t Address, 402 const void *Decoder); 403 404 template <unsigned Bits, int Offset> 405 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 406 uint64_t Address, 407 const void *Decoder) { 408 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 409 Decoder); 410 } 411 412 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 413 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 414 uint64_t Address, 415 const void *Decoder); 416 417 static DecodeStatus DecodeInsSize(MCInst &Inst, 418 unsigned Insn, 419 uint64_t Address, 420 const void *Decoder); 421 422 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 423 uint64_t Address, const void *Decoder); 424 425 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 426 uint64_t Address, const void *Decoder); 427 428 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void *Decoder); 430 431 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 432 uint64_t Address, const void *Decoder); 433 434 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void *Decoder); 436 437 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 438 /// handle. 439 template <typename InsnType> 440 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 441 const void *Decoder); 442 443 template <typename InsnType> 444 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 445 const void *Decoder); 446 447 template <typename InsnType> 448 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 449 const void *Decoder); 450 451 template <typename InsnType> 452 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 453 const void *Decoder); 454 455 template <typename InsnType> 456 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 457 const void *Decoder); 458 459 template <typename InsnType> 460 static DecodeStatus 461 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 462 const void *Decoder); 463 464 template <typename InsnType> 465 static DecodeStatus 466 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 467 const void *Decoder); 468 469 template <typename InsnType> 470 static DecodeStatus 471 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 472 const void *Decoder); 473 474 template <typename InsnType> 475 static DecodeStatus 476 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 477 const void *Decoder); 478 479 template <typename InsnType> 480 static DecodeStatus 481 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 482 const void *Decoder); 483 484 template <typename InsnType> 485 static DecodeStatus 486 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 487 const void *Decoder); 488 489 template <typename InsnType> 490 static DecodeStatus 491 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 492 const void *Decoder); 493 494 template <typename InsnType> 495 static DecodeStatus 496 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 497 const void *Decoder); 498 499 template <typename InsnType> 500 static DecodeStatus 501 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 502 const void *Decoder); 503 504 template <typename InsnType> 505 static DecodeStatus 506 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 507 const void *Decoder); 508 509 template <typename InsnType> 510 static DecodeStatus 511 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 512 const void *Decoder); 513 514 template <typename InsnType> 515 static DecodeStatus 516 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 517 const void *Decoder); 518 519 template <typename InsnType> 520 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 521 const void *Decoder); 522 523 template <typename InsnType> 524 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 525 const void *Decoder); 526 527 template <typename InsnType> 528 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 529 const void *Decoder); 530 531 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 532 uint64_t Address, 533 const void *Decoder); 534 535 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 536 uint64_t Address, 537 const void *Decoder); 538 539 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 540 uint64_t Address, 541 const void *Decoder); 542 543 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 544 uint64_t Address, const void *Decoder); 545 546 static MCDisassembler *createMipsDisassembler( 547 const Target &T, 548 const MCSubtargetInfo &STI, 549 MCContext &Ctx) { 550 return new MipsDisassembler(STI, Ctx, true); 551 } 552 553 static MCDisassembler *createMipselDisassembler( 554 const Target &T, 555 const MCSubtargetInfo &STI, 556 MCContext &Ctx) { 557 return new MipsDisassembler(STI, Ctx, false); 558 } 559 560 extern "C" void LLVMInitializeMipsDisassembler() { 561 // Register the disassembler. 562 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 563 createMipsDisassembler); 564 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 565 createMipselDisassembler); 566 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 567 createMipsDisassembler); 568 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 569 createMipselDisassembler); 570 } 571 572 #include "MipsGenDisassemblerTables.inc" 573 574 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 575 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 576 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 577 return *(RegInfo->getRegClass(RC).begin() + RegNo); 578 } 579 580 template <typename InsnType> 581 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 582 const void *Decoder) { 583 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 584 585 // The size of the n field depends on the element size 586 // The register class also depends on this. 587 InsnType tmp = fieldFromInstruction(insn, 17, 5); 588 unsigned NSize = 0; 589 DecodeFN RegDecoder = nullptr; 590 if ((tmp & 0x18) == 0x00) { // INSVE_B 591 NSize = 4; 592 RegDecoder = DecodeMSA128BRegisterClass; 593 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 594 NSize = 3; 595 RegDecoder = DecodeMSA128HRegisterClass; 596 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 597 NSize = 2; 598 RegDecoder = DecodeMSA128WRegisterClass; 599 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 600 NSize = 1; 601 RegDecoder = DecodeMSA128DRegisterClass; 602 } else 603 llvm_unreachable("Invalid encoding"); 604 605 assert(NSize != 0 && RegDecoder != nullptr); 606 607 // $wd 608 tmp = fieldFromInstruction(insn, 6, 5); 609 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 610 return MCDisassembler::Fail; 611 // $wd_in 612 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 613 return MCDisassembler::Fail; 614 // $n 615 tmp = fieldFromInstruction(insn, 16, NSize); 616 MI.addOperand(MCOperand::createImm(tmp)); 617 // $ws 618 tmp = fieldFromInstruction(insn, 11, 5); 619 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 620 return MCDisassembler::Fail; 621 // $n2 622 MI.addOperand(MCOperand::createImm(0)); 623 624 return MCDisassembler::Success; 625 } 626 627 template <typename InsnType> 628 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 629 const void *Decoder) { 630 InsnType Rs = fieldFromInstruction(insn, 16, 5); 631 InsnType Imm = fieldFromInstruction(insn, 0, 16); 632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 633 Rs))); 634 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 635 Rs))); 636 MI.addOperand(MCOperand::createImm(Imm)); 637 638 return MCDisassembler::Success; 639 } 640 641 template <typename InsnType> 642 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 643 const void *Decoder) { 644 InsnType Rs = fieldFromInstruction(insn, 21, 5); 645 InsnType Imm = fieldFromInstruction(insn, 0, 16); 646 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 647 Rs))); 648 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 649 Rs))); 650 MI.addOperand(MCOperand::createImm(Imm)); 651 652 return MCDisassembler::Success; 653 } 654 655 template <typename InsnType> 656 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 657 uint64_t Address, 658 const void *Decoder) { 659 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 660 // (otherwise we would have matched the ADDI instruction from the earlier 661 // ISA's instead). 662 // 663 // We have: 664 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 665 // BOVC if rs >= rt 666 // BEQZALC if rs == 0 && rt != 0 667 // BEQC if rs < rt && rs != 0 668 669 InsnType Rs = fieldFromInstruction(insn, 21, 5); 670 InsnType Rt = fieldFromInstruction(insn, 16, 5); 671 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 672 bool HasRs = false; 673 674 if (Rs >= Rt) { 675 MI.setOpcode(Mips::BOVC); 676 HasRs = true; 677 } else if (Rs != 0 && Rs < Rt) { 678 MI.setOpcode(Mips::BEQC); 679 HasRs = true; 680 } else 681 MI.setOpcode(Mips::BEQZALC); 682 683 if (HasRs) 684 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 685 Rs))); 686 687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 688 Rt))); 689 MI.addOperand(MCOperand::createImm(Imm)); 690 691 return MCDisassembler::Success; 692 } 693 694 template <typename InsnType> 695 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 696 uint64_t Address, 697 const void *Decoder) { 698 InsnType Rt = fieldFromInstruction(insn, 21, 5); 699 InsnType Rs = fieldFromInstruction(insn, 16, 5); 700 int64_t Imm = 0; 701 702 if (Rs >= Rt) { 703 MI.setOpcode(Mips::BOVC_MMR6); 704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 705 Rt))); 706 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 707 Rs))); 708 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 709 } else if (Rs != 0 && Rs < Rt) { 710 MI.setOpcode(Mips::BEQC_MMR6); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rs))); 713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 714 Rt))); 715 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 716 } else { 717 MI.setOpcode(Mips::BEQZALC_MMR6); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rt))); 720 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 721 } 722 723 MI.addOperand(MCOperand::createImm(Imm)); 724 725 return MCDisassembler::Success; 726 } 727 728 template <typename InsnType> 729 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 730 uint64_t Address, 731 const void *Decoder) { 732 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 733 // (otherwise we would have matched the ADDI instruction from the earlier 734 // ISA's instead). 735 // 736 // We have: 737 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 738 // BNVC if rs >= rt 739 // BNEZALC if rs == 0 && rt != 0 740 // BNEC if rs < rt && rs != 0 741 742 InsnType Rs = fieldFromInstruction(insn, 21, 5); 743 InsnType Rt = fieldFromInstruction(insn, 16, 5); 744 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 745 bool HasRs = false; 746 747 if (Rs >= Rt) { 748 MI.setOpcode(Mips::BNVC); 749 HasRs = true; 750 } else if (Rs != 0 && Rs < Rt) { 751 MI.setOpcode(Mips::BNEC); 752 HasRs = true; 753 } else 754 MI.setOpcode(Mips::BNEZALC); 755 756 if (HasRs) 757 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 758 Rs))); 759 760 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 761 Rt))); 762 MI.addOperand(MCOperand::createImm(Imm)); 763 764 return MCDisassembler::Success; 765 } 766 767 template <typename InsnType> 768 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 769 uint64_t Address, 770 const void *Decoder) { 771 InsnType Rt = fieldFromInstruction(insn, 21, 5); 772 InsnType Rs = fieldFromInstruction(insn, 16, 5); 773 int64_t Imm = 0; 774 775 if (Rs >= Rt) { 776 MI.setOpcode(Mips::BNVC_MMR6); 777 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 778 Rt))); 779 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 780 Rs))); 781 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 782 } else if (Rs != 0 && Rs < Rt) { 783 MI.setOpcode(Mips::BNEC_MMR6); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rs))); 786 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 787 Rt))); 788 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 789 } else { 790 MI.setOpcode(Mips::BNEZALC_MMR6); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rt))); 793 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 794 } 795 796 MI.addOperand(MCOperand::createImm(Imm)); 797 798 return MCDisassembler::Success; 799 } 800 801 template <typename InsnType> 802 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 803 uint64_t Address, 804 const void *Decoder) { 805 // We have: 806 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 807 // Invalid if rt == 0 808 // BGTZC_MMR6 if rs == 0 && rt != 0 809 // BLTZC_MMR6 if rs == rt && rt != 0 810 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 811 812 InsnType Rt = fieldFromInstruction(insn, 21, 5); 813 InsnType Rs = fieldFromInstruction(insn, 16, 5); 814 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 815 bool HasRs = false; 816 817 if (Rt == 0) 818 return MCDisassembler::Fail; 819 else if (Rs == 0) 820 MI.setOpcode(Mips::BGTZC_MMR6); 821 else if (Rs == Rt) 822 MI.setOpcode(Mips::BLTZC_MMR6); 823 else { 824 MI.setOpcode(Mips::BLTC_MMR6); 825 HasRs = true; 826 } 827 828 if (HasRs) 829 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 830 Rs))); 831 832 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 833 Rt))); 834 835 MI.addOperand(MCOperand::createImm(Imm)); 836 837 return MCDisassembler::Success; 838 } 839 840 template <typename InsnType> 841 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 842 uint64_t Address, 843 const void *Decoder) { 844 // We have: 845 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 846 // Invalid if rt == 0 847 // BLEZC_MMR6 if rs == 0 && rt != 0 848 // BGEZC_MMR6 if rs == rt && rt != 0 849 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 850 851 InsnType Rt = fieldFromInstruction(insn, 21, 5); 852 InsnType Rs = fieldFromInstruction(insn, 16, 5); 853 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 854 bool HasRs = false; 855 856 if (Rt == 0) 857 return MCDisassembler::Fail; 858 else if (Rs == 0) 859 MI.setOpcode(Mips::BLEZC_MMR6); 860 else if (Rs == Rt) 861 MI.setOpcode(Mips::BGEZC_MMR6); 862 else { 863 HasRs = true; 864 MI.setOpcode(Mips::BGEC_MMR6); 865 } 866 867 if (HasRs) 868 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 869 Rs))); 870 871 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 872 Rt))); 873 874 MI.addOperand(MCOperand::createImm(Imm)); 875 876 return MCDisassembler::Success; 877 } 878 879 template <typename InsnType> 880 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 881 uint64_t Address, 882 const void *Decoder) { 883 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 884 // (otherwise we would have matched the BLEZL instruction from the earlier 885 // ISA's instead). 886 // 887 // We have: 888 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 889 // Invalid if rs == 0 890 // BLEZC if rs == 0 && rt != 0 891 // BGEZC if rs == rt && rt != 0 892 // BGEC if rs != rt && rs != 0 && rt != 0 893 894 InsnType Rs = fieldFromInstruction(insn, 21, 5); 895 InsnType Rt = fieldFromInstruction(insn, 16, 5); 896 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 897 bool HasRs = false; 898 899 if (Rt == 0) 900 return MCDisassembler::Fail; 901 else if (Rs == 0) 902 MI.setOpcode(Mips::BLEZC); 903 else if (Rs == Rt) 904 MI.setOpcode(Mips::BGEZC); 905 else { 906 HasRs = true; 907 MI.setOpcode(Mips::BGEC); 908 } 909 910 if (HasRs) 911 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 912 Rs))); 913 914 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 915 Rt))); 916 917 MI.addOperand(MCOperand::createImm(Imm)); 918 919 return MCDisassembler::Success; 920 } 921 922 template <typename InsnType> 923 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 924 uint64_t Address, 925 const void *Decoder) { 926 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 927 // (otherwise we would have matched the BGTZL instruction from the earlier 928 // ISA's instead). 929 // 930 // We have: 931 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 932 // Invalid if rs == 0 933 // BGTZC if rs == 0 && rt != 0 934 // BLTZC if rs == rt && rt != 0 935 // BLTC if rs != rt && rs != 0 && rt != 0 936 937 bool HasRs = false; 938 939 InsnType Rs = fieldFromInstruction(insn, 21, 5); 940 InsnType Rt = fieldFromInstruction(insn, 16, 5); 941 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 942 943 if (Rt == 0) 944 return MCDisassembler::Fail; 945 else if (Rs == 0) 946 MI.setOpcode(Mips::BGTZC); 947 else if (Rs == Rt) 948 MI.setOpcode(Mips::BLTZC); 949 else { 950 MI.setOpcode(Mips::BLTC); 951 HasRs = true; 952 } 953 954 if (HasRs) 955 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 956 Rs))); 957 958 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 959 Rt))); 960 961 MI.addOperand(MCOperand::createImm(Imm)); 962 963 return MCDisassembler::Success; 964 } 965 966 template <typename InsnType> 967 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 968 uint64_t Address, 969 const void *Decoder) { 970 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 971 // (otherwise we would have matched the BGTZ instruction from the earlier 972 // ISA's instead). 973 // 974 // We have: 975 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 976 // BGTZ if rt == 0 977 // BGTZALC if rs == 0 && rt != 0 978 // BLTZALC if rs != 0 && rs == rt 979 // BLTUC if rs != 0 && rs != rt 980 981 InsnType Rs = fieldFromInstruction(insn, 21, 5); 982 InsnType Rt = fieldFromInstruction(insn, 16, 5); 983 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 984 bool HasRs = false; 985 bool HasRt = false; 986 987 if (Rt == 0) { 988 MI.setOpcode(Mips::BGTZ); 989 HasRs = true; 990 } else if (Rs == 0) { 991 MI.setOpcode(Mips::BGTZALC); 992 HasRt = true; 993 } else if (Rs == Rt) { 994 MI.setOpcode(Mips::BLTZALC); 995 HasRs = true; 996 } else { 997 MI.setOpcode(Mips::BLTUC); 998 HasRs = true; 999 HasRt = true; 1000 } 1001 1002 if (HasRs) 1003 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1004 Rs))); 1005 1006 if (HasRt) 1007 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1008 Rt))); 1009 1010 MI.addOperand(MCOperand::createImm(Imm)); 1011 1012 return MCDisassembler::Success; 1013 } 1014 1015 template <typename InsnType> 1016 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1017 uint64_t Address, 1018 const void *Decoder) { 1019 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1020 // (otherwise we would have matched the BLEZL instruction from the earlier 1021 // ISA's instead). 1022 // 1023 // We have: 1024 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1025 // Invalid if rs == 0 1026 // BLEZALC if rs == 0 && rt != 0 1027 // BGEZALC if rs == rt && rt != 0 1028 // BGEUC if rs != rt && rs != 0 && rt != 0 1029 1030 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1031 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1032 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1033 bool HasRs = false; 1034 1035 if (Rt == 0) 1036 return MCDisassembler::Fail; 1037 else if (Rs == 0) 1038 MI.setOpcode(Mips::BLEZALC); 1039 else if (Rs == Rt) 1040 MI.setOpcode(Mips::BGEZALC); 1041 else { 1042 HasRs = true; 1043 MI.setOpcode(Mips::BGEUC); 1044 } 1045 1046 if (HasRs) 1047 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1048 Rs))); 1049 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1050 Rt))); 1051 1052 MI.addOperand(MCOperand::createImm(Imm)); 1053 1054 return MCDisassembler::Success; 1055 } 1056 1057 // Override the generated disassembler to produce DEXT all the time. This is 1058 // for feature / behaviour parity with binutils. 1059 template <typename InsnType> 1060 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1061 const void *Decoder) { 1062 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1063 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1064 unsigned Size = 0; 1065 unsigned Pos = 0; 1066 1067 switch (MI.getOpcode()) { 1068 case Mips::DEXT: 1069 Pos = Lsb; 1070 Size = Msbd + 1; 1071 break; 1072 case Mips::DEXTM: 1073 Pos = Lsb; 1074 Size = Msbd + 1 + 32; 1075 break; 1076 case Mips::DEXTU: 1077 Pos = Lsb + 32; 1078 Size = Msbd + 1; 1079 break; 1080 default: 1081 llvm_unreachable("Unknown DEXT instruction!"); 1082 } 1083 1084 MI.setOpcode(Mips::DEXT); 1085 1086 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1087 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1088 1089 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1090 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1091 MI.addOperand(MCOperand::createImm(Pos)); 1092 MI.addOperand(MCOperand::createImm(Size)); 1093 1094 return MCDisassembler::Success; 1095 } 1096 1097 // Override the generated disassembler to produce DINS all the time. This is 1098 // for feature / behaviour parity with binutils. 1099 template <typename InsnType> 1100 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1101 const void *Decoder) { 1102 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1103 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1104 unsigned Size = 0; 1105 unsigned Pos = 0; 1106 1107 switch (MI.getOpcode()) { 1108 case Mips::DINS: 1109 Pos = Lsb; 1110 Size = Msbd + 1 - Pos; 1111 break; 1112 case Mips::DINSM: 1113 Pos = Lsb; 1114 Size = Msbd + 33 - Pos; 1115 break; 1116 case Mips::DINSU: 1117 Pos = Lsb + 32; 1118 // mbsd = pos + size - 33 1119 // mbsd - pos + 33 = size 1120 Size = Msbd + 33 - Pos; 1121 break; 1122 default: 1123 llvm_unreachable("Unknown DINS instruction!"); 1124 } 1125 1126 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1127 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1128 1129 MI.setOpcode(Mips::DINS); 1130 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1131 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1132 MI.addOperand(MCOperand::createImm(Pos)); 1133 MI.addOperand(MCOperand::createImm(Size)); 1134 1135 return MCDisassembler::Success; 1136 } 1137 1138 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1139 template <typename InsnType> 1140 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1141 const void *Decoder) { 1142 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1143 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1144 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1145 Rt))); 1146 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1147 Rs))); 1148 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1149 Rt))); 1150 return MCDisassembler::Success; 1151 } 1152 1153 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1154 /// according to the given endianness. 1155 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1156 uint64_t &Size, uint32_t &Insn, 1157 bool IsBigEndian) { 1158 // We want to read exactly 2 Bytes of data. 1159 if (Bytes.size() < 2) { 1160 Size = 0; 1161 return MCDisassembler::Fail; 1162 } 1163 1164 if (IsBigEndian) { 1165 Insn = (Bytes[0] << 8) | Bytes[1]; 1166 } else { 1167 Insn = (Bytes[1] << 8) | Bytes[0]; 1168 } 1169 1170 return MCDisassembler::Success; 1171 } 1172 1173 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1174 /// according to the given endianness. 1175 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1176 uint64_t &Size, uint32_t &Insn, 1177 bool IsBigEndian, bool IsMicroMips) { 1178 // We want to read exactly 4 Bytes of data. 1179 if (Bytes.size() < 4) { 1180 Size = 0; 1181 return MCDisassembler::Fail; 1182 } 1183 1184 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1185 // always precede the low 16 bits in the instruction stream (that is, they 1186 // are placed at lower addresses in the instruction stream). 1187 // 1188 // microMIPS byte ordering: 1189 // Big-endian: 0 | 1 | 2 | 3 1190 // Little-endian: 1 | 0 | 3 | 2 1191 1192 if (IsBigEndian) { 1193 // Encoded as a big-endian 32-bit word in the stream. 1194 Insn = 1195 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1196 } else { 1197 if (IsMicroMips) { 1198 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1199 (Bytes[1] << 24); 1200 } else { 1201 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1202 (Bytes[3] << 24); 1203 } 1204 } 1205 1206 return MCDisassembler::Success; 1207 } 1208 1209 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1210 ArrayRef<uint8_t> Bytes, 1211 uint64_t Address, 1212 raw_ostream &VStream, 1213 raw_ostream &CStream) const { 1214 uint32_t Insn; 1215 DecodeStatus Result; 1216 Size = 0; 1217 1218 if (IsMicroMips) { 1219 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1220 if (Result == MCDisassembler::Fail) 1221 return MCDisassembler::Fail; 1222 1223 if (hasMips32r6()) { 1224 LLVM_DEBUG( 1225 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1226 // Calling the auto-generated decoder function for microMIPS32R6 1227 // 16-bit instructions. 1228 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1229 Address, this, STI); 1230 if (Result != MCDisassembler::Fail) { 1231 Size = 2; 1232 return Result; 1233 } 1234 } 1235 1236 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1237 // Calling the auto-generated decoder function for microMIPS 16-bit 1238 // instructions. 1239 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1240 this, STI); 1241 if (Result != MCDisassembler::Fail) { 1242 Size = 2; 1243 return Result; 1244 } 1245 1246 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1247 if (Result == MCDisassembler::Fail) 1248 return MCDisassembler::Fail; 1249 1250 if (hasMips32r6()) { 1251 LLVM_DEBUG( 1252 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1253 // Calling the auto-generated decoder function. 1254 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1255 this, STI); 1256 if (Result != MCDisassembler::Fail) { 1257 Size = 4; 1258 return Result; 1259 } 1260 } 1261 1262 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1263 // Calling the auto-generated decoder function. 1264 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1265 this, STI); 1266 if (Result != MCDisassembler::Fail) { 1267 Size = 4; 1268 return Result; 1269 } 1270 1271 if (isFP64()) { 1272 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1273 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1274 Address, this, STI); 1275 if (Result != MCDisassembler::Fail) { 1276 Size = 4; 1277 return Result; 1278 } 1279 } 1280 1281 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1282 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1283 // could form a valid instruction. The two bytes we rejected as an 1284 // instruction could have actually beeen an inline constant pool that is 1285 // unconditionally branched over. 1286 Size = 2; 1287 return MCDisassembler::Fail; 1288 } 1289 1290 // Attempt to read the instruction so that we can attempt to decode it. If 1291 // the buffer is not 4 bytes long, let the higher level logic figure out 1292 // what to do with a size of zero and MCDisassembler::Fail. 1293 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1294 if (Result == MCDisassembler::Fail) 1295 return MCDisassembler::Fail; 1296 1297 // The only instruction size for standard encoded MIPS. 1298 Size = 4; 1299 1300 if (hasCOP3()) { 1301 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1302 Result = 1303 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1304 if (Result != MCDisassembler::Fail) 1305 return Result; 1306 } 1307 1308 if (hasMips32r6() && isGP64()) { 1309 LLVM_DEBUG( 1310 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1311 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1312 Address, this, STI); 1313 if (Result != MCDisassembler::Fail) 1314 return Result; 1315 } 1316 1317 if (hasMips32r6() && isPTR64()) { 1318 LLVM_DEBUG( 1319 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1320 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1321 Address, this, STI); 1322 if (Result != MCDisassembler::Fail) 1323 return Result; 1324 } 1325 1326 if (hasMips32r6()) { 1327 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1328 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1329 Address, this, STI); 1330 if (Result != MCDisassembler::Fail) 1331 return Result; 1332 } 1333 1334 if (hasMips2() && isPTR64()) { 1335 LLVM_DEBUG( 1336 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1337 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1338 Address, this, STI); 1339 if (Result != MCDisassembler::Fail) 1340 return Result; 1341 } 1342 1343 if (hasCnMips()) { 1344 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1345 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1346 Address, this, STI); 1347 if (Result != MCDisassembler::Fail) 1348 return Result; 1349 } 1350 1351 if (hasCnMipsP()) { 1352 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); 1353 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, 1354 Address, this, STI); 1355 if (Result != MCDisassembler::Fail) 1356 return Result; 1357 } 1358 1359 if (isGP64()) { 1360 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1361 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1362 Address, this, STI); 1363 if (Result != MCDisassembler::Fail) 1364 return Result; 1365 } 1366 1367 if (isFP64()) { 1368 LLVM_DEBUG( 1369 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1370 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1371 Address, this, STI); 1372 if (Result != MCDisassembler::Fail) 1373 return Result; 1374 } 1375 1376 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1377 // Calling the auto-generated decoder function. 1378 Result = 1379 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1380 if (Result != MCDisassembler::Fail) 1381 return Result; 1382 1383 return MCDisassembler::Fail; 1384 } 1385 1386 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1387 unsigned RegNo, 1388 uint64_t Address, 1389 const void *Decoder) { 1390 return MCDisassembler::Fail; 1391 } 1392 1393 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1394 unsigned RegNo, 1395 uint64_t Address, 1396 const void *Decoder) { 1397 if (RegNo > 31) 1398 return MCDisassembler::Fail; 1399 1400 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1401 Inst.addOperand(MCOperand::createReg(Reg)); 1402 return MCDisassembler::Success; 1403 } 1404 1405 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1406 unsigned RegNo, 1407 uint64_t Address, 1408 const void *Decoder) { 1409 if (RegNo > 7) 1410 return MCDisassembler::Fail; 1411 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1412 Inst.addOperand(MCOperand::createReg(Reg)); 1413 return MCDisassembler::Success; 1414 } 1415 1416 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1417 unsigned RegNo, 1418 uint64_t Address, 1419 const void *Decoder) { 1420 if (RegNo > 7) 1421 return MCDisassembler::Fail; 1422 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1423 Inst.addOperand(MCOperand::createReg(Reg)); 1424 return MCDisassembler::Success; 1425 } 1426 1427 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1428 unsigned RegNo, 1429 uint64_t Address, 1430 const void *Decoder) { 1431 if (RegNo > 7) 1432 return MCDisassembler::Fail; 1433 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1434 Inst.addOperand(MCOperand::createReg(Reg)); 1435 return MCDisassembler::Success; 1436 } 1437 1438 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1439 unsigned RegNo, 1440 uint64_t Address, 1441 const void *Decoder) { 1442 if (RegNo > 31) 1443 return MCDisassembler::Fail; 1444 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1445 Inst.addOperand(MCOperand::createReg(Reg)); 1446 return MCDisassembler::Success; 1447 } 1448 1449 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1450 unsigned RegNo, 1451 uint64_t Address, 1452 const void *Decoder) { 1453 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1454 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1455 1456 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1457 } 1458 1459 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1460 unsigned RegNo, 1461 uint64_t Address, 1462 const void *Decoder) { 1463 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1464 } 1465 1466 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1467 unsigned RegNo, 1468 uint64_t Address, 1469 const void *Decoder) { 1470 if (RegNo > 31) 1471 return MCDisassembler::Fail; 1472 1473 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1474 Inst.addOperand(MCOperand::createReg(Reg)); 1475 return MCDisassembler::Success; 1476 } 1477 1478 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1479 unsigned RegNo, 1480 uint64_t Address, 1481 const void *Decoder) { 1482 if (RegNo > 31) 1483 return MCDisassembler::Fail; 1484 1485 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1486 Inst.addOperand(MCOperand::createReg(Reg)); 1487 return MCDisassembler::Success; 1488 } 1489 1490 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1491 unsigned RegNo, 1492 uint64_t Address, 1493 const void *Decoder) { 1494 if (RegNo > 31) 1495 return MCDisassembler::Fail; 1496 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1497 Inst.addOperand(MCOperand::createReg(Reg)); 1498 return MCDisassembler::Success; 1499 } 1500 1501 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1502 unsigned RegNo, 1503 uint64_t Address, 1504 const void *Decoder) { 1505 if (RegNo > 7) 1506 return MCDisassembler::Fail; 1507 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1508 Inst.addOperand(MCOperand::createReg(Reg)); 1509 return MCDisassembler::Success; 1510 } 1511 1512 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1513 uint64_t Address, 1514 const void *Decoder) { 1515 if (RegNo > 31) 1516 return MCDisassembler::Fail; 1517 1518 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1519 Inst.addOperand(MCOperand::createReg(Reg)); 1520 return MCDisassembler::Success; 1521 } 1522 1523 static DecodeStatus DecodeMem(MCInst &Inst, 1524 unsigned Insn, 1525 uint64_t Address, 1526 const void *Decoder) { 1527 int Offset = SignExtend32<16>(Insn & 0xffff); 1528 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1529 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1530 1531 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1532 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1533 1534 if (Inst.getOpcode() == Mips::SC || 1535 Inst.getOpcode() == Mips::SCD) 1536 Inst.addOperand(MCOperand::createReg(Reg)); 1537 1538 Inst.addOperand(MCOperand::createReg(Reg)); 1539 Inst.addOperand(MCOperand::createReg(Base)); 1540 Inst.addOperand(MCOperand::createImm(Offset)); 1541 1542 return MCDisassembler::Success; 1543 } 1544 1545 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1546 unsigned Insn, 1547 uint64_t Address, 1548 const void *Decoder) { 1549 int Offset = SignExtend32<9>(Insn >> 7); 1550 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1551 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1552 1553 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1554 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1555 1556 if (Inst.getOpcode() == Mips::SCE) 1557 Inst.addOperand(MCOperand::createReg(Reg)); 1558 1559 Inst.addOperand(MCOperand::createReg(Reg)); 1560 Inst.addOperand(MCOperand::createReg(Base)); 1561 Inst.addOperand(MCOperand::createImm(Offset)); 1562 1563 return MCDisassembler::Success; 1564 } 1565 1566 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1567 unsigned Insn, 1568 uint64_t Address, 1569 const void *Decoder) { 1570 int Offset = SignExtend32<16>(Insn & 0xffff); 1571 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1572 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1573 1574 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1575 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1576 1577 Inst.addOperand(MCOperand::createReg(Reg)); 1578 Inst.addOperand(MCOperand::createReg(Base)); 1579 Inst.addOperand(MCOperand::createImm(Offset)); 1580 1581 return MCDisassembler::Success; 1582 } 1583 1584 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1585 unsigned Insn, 1586 uint64_t Address, 1587 const void *Decoder) { 1588 int Offset = SignExtend32<16>(Insn & 0xffff); 1589 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1590 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1591 1592 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1593 1594 Inst.addOperand(MCOperand::createReg(Base)); 1595 Inst.addOperand(MCOperand::createImm(Offset)); 1596 Inst.addOperand(MCOperand::createImm(Hint)); 1597 1598 return MCDisassembler::Success; 1599 } 1600 1601 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1602 unsigned Insn, 1603 uint64_t Address, 1604 const void *Decoder) { 1605 int Offset = SignExtend32<12>(Insn & 0xfff); 1606 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1607 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1608 1609 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1610 1611 Inst.addOperand(MCOperand::createReg(Base)); 1612 Inst.addOperand(MCOperand::createImm(Offset)); 1613 Inst.addOperand(MCOperand::createImm(Hint)); 1614 1615 return MCDisassembler::Success; 1616 } 1617 1618 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1619 unsigned Insn, 1620 uint64_t Address, 1621 const void *Decoder) { 1622 int Offset = SignExtend32<9>(Insn & 0x1ff); 1623 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1624 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1625 1626 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1627 1628 Inst.addOperand(MCOperand::createReg(Base)); 1629 Inst.addOperand(MCOperand::createImm(Offset)); 1630 Inst.addOperand(MCOperand::createImm(Hint)); 1631 1632 return MCDisassembler::Success; 1633 } 1634 1635 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1636 unsigned Insn, 1637 uint64_t Address, 1638 const void *Decoder) { 1639 int Offset = SignExtend32<9>(Insn >> 7); 1640 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1641 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1642 1643 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1644 1645 Inst.addOperand(MCOperand::createReg(Base)); 1646 Inst.addOperand(MCOperand::createImm(Offset)); 1647 Inst.addOperand(MCOperand::createImm(Hint)); 1648 1649 return MCDisassembler::Success; 1650 } 1651 1652 static DecodeStatus DecodeSyncI(MCInst &Inst, 1653 unsigned Insn, 1654 uint64_t Address, 1655 const void *Decoder) { 1656 int Offset = SignExtend32<16>(Insn & 0xffff); 1657 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1658 1659 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1660 1661 Inst.addOperand(MCOperand::createReg(Base)); 1662 Inst.addOperand(MCOperand::createImm(Offset)); 1663 1664 return MCDisassembler::Success; 1665 } 1666 1667 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1668 uint64_t Address, const void *Decoder) { 1669 int Offset = SignExtend32<16>(Insn & 0xffff); 1670 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1671 1672 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1673 1674 Inst.addOperand(MCOperand::createReg(Base)); 1675 Inst.addOperand(MCOperand::createImm(Offset)); 1676 1677 return MCDisassembler::Success; 1678 } 1679 1680 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1681 unsigned Insn, 1682 uint64_t Address, 1683 const void *Decoder) { 1684 int Immediate = SignExtend32<16>(Insn & 0xffff); 1685 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1686 1687 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1688 1689 Inst.addOperand(MCOperand::createReg(Base)); 1690 Inst.addOperand(MCOperand::createImm(Immediate)); 1691 1692 return MCDisassembler::Success; 1693 } 1694 1695 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1696 uint64_t Address, const void *Decoder) { 1697 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1698 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1699 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1700 1701 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1702 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1703 1704 Inst.addOperand(MCOperand::createReg(Reg)); 1705 Inst.addOperand(MCOperand::createReg(Base)); 1706 1707 // The immediate field of an LD/ST instruction is scaled which means it must 1708 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1709 // data format. 1710 // .b - 1 byte 1711 // .h - 2 bytes 1712 // .w - 4 bytes 1713 // .d - 8 bytes 1714 switch(Inst.getOpcode()) 1715 { 1716 default: 1717 assert(false && "Unexpected instruction"); 1718 return MCDisassembler::Fail; 1719 break; 1720 case Mips::LD_B: 1721 case Mips::ST_B: 1722 Inst.addOperand(MCOperand::createImm(Offset)); 1723 break; 1724 case Mips::LD_H: 1725 case Mips::ST_H: 1726 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1727 break; 1728 case Mips::LD_W: 1729 case Mips::ST_W: 1730 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1731 break; 1732 case Mips::LD_D: 1733 case Mips::ST_D: 1734 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1735 break; 1736 } 1737 1738 return MCDisassembler::Success; 1739 } 1740 1741 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1742 unsigned Insn, 1743 uint64_t Address, 1744 const void *Decoder) { 1745 unsigned Offset = Insn & 0xf; 1746 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1747 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1748 1749 switch (Inst.getOpcode()) { 1750 case Mips::LBU16_MM: 1751 case Mips::LHU16_MM: 1752 case Mips::LW16_MM: 1753 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1754 == MCDisassembler::Fail) 1755 return MCDisassembler::Fail; 1756 break; 1757 case Mips::SB16_MM: 1758 case Mips::SB16_MMR6: 1759 case Mips::SH16_MM: 1760 case Mips::SH16_MMR6: 1761 case Mips::SW16_MM: 1762 case Mips::SW16_MMR6: 1763 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1764 == MCDisassembler::Fail) 1765 return MCDisassembler::Fail; 1766 break; 1767 } 1768 1769 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1770 == MCDisassembler::Fail) 1771 return MCDisassembler::Fail; 1772 1773 switch (Inst.getOpcode()) { 1774 case Mips::LBU16_MM: 1775 if (Offset == 0xf) 1776 Inst.addOperand(MCOperand::createImm(-1)); 1777 else 1778 Inst.addOperand(MCOperand::createImm(Offset)); 1779 break; 1780 case Mips::SB16_MM: 1781 case Mips::SB16_MMR6: 1782 Inst.addOperand(MCOperand::createImm(Offset)); 1783 break; 1784 case Mips::LHU16_MM: 1785 case Mips::SH16_MM: 1786 case Mips::SH16_MMR6: 1787 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1788 break; 1789 case Mips::LW16_MM: 1790 case Mips::SW16_MM: 1791 case Mips::SW16_MMR6: 1792 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1793 break; 1794 } 1795 1796 return MCDisassembler::Success; 1797 } 1798 1799 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1800 unsigned Insn, 1801 uint64_t Address, 1802 const void *Decoder) { 1803 unsigned Offset = Insn & 0x1F; 1804 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1805 1806 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1807 1808 Inst.addOperand(MCOperand::createReg(Reg)); 1809 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1810 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1811 1812 return MCDisassembler::Success; 1813 } 1814 1815 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1816 unsigned Insn, 1817 uint64_t Address, 1818 const void *Decoder) { 1819 unsigned Offset = Insn & 0x7F; 1820 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1821 1822 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1823 1824 Inst.addOperand(MCOperand::createReg(Reg)); 1825 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1826 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1827 1828 return MCDisassembler::Success; 1829 } 1830 1831 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1832 unsigned Insn, 1833 uint64_t Address, 1834 const void *Decoder) { 1835 int Offset; 1836 switch (Inst.getOpcode()) { 1837 case Mips::LWM16_MMR6: 1838 case Mips::SWM16_MMR6: 1839 Offset = fieldFromInstruction(Insn, 4, 4); 1840 break; 1841 default: 1842 Offset = SignExtend32<4>(Insn & 0xf); 1843 break; 1844 } 1845 1846 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1847 == MCDisassembler::Fail) 1848 return MCDisassembler::Fail; 1849 1850 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1851 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1852 1853 return MCDisassembler::Success; 1854 } 1855 1856 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1857 unsigned Insn, 1858 uint64_t Address, 1859 const void *Decoder) { 1860 int Offset = SignExtend32<9>(Insn & 0x1ff); 1861 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1862 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1863 1864 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1865 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1866 1867 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) 1868 Inst.addOperand(MCOperand::createReg(Reg)); 1869 1870 Inst.addOperand(MCOperand::createReg(Reg)); 1871 Inst.addOperand(MCOperand::createReg(Base)); 1872 Inst.addOperand(MCOperand::createImm(Offset)); 1873 1874 return MCDisassembler::Success; 1875 } 1876 1877 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1878 unsigned Insn, 1879 uint64_t Address, 1880 const void *Decoder) { 1881 int Offset = SignExtend32<12>(Insn & 0x0fff); 1882 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1883 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1884 1885 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1886 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1887 1888 switch (Inst.getOpcode()) { 1889 case Mips::SWM32_MM: 1890 case Mips::LWM32_MM: 1891 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1892 == MCDisassembler::Fail) 1893 return MCDisassembler::Fail; 1894 Inst.addOperand(MCOperand::createReg(Base)); 1895 Inst.addOperand(MCOperand::createImm(Offset)); 1896 break; 1897 case Mips::SC_MM: 1898 Inst.addOperand(MCOperand::createReg(Reg)); 1899 LLVM_FALLTHROUGH; 1900 default: 1901 Inst.addOperand(MCOperand::createReg(Reg)); 1902 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1903 Inst.addOperand(MCOperand::createReg(Reg+1)); 1904 1905 Inst.addOperand(MCOperand::createReg(Base)); 1906 Inst.addOperand(MCOperand::createImm(Offset)); 1907 } 1908 1909 return MCDisassembler::Success; 1910 } 1911 1912 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1913 unsigned Insn, 1914 uint64_t Address, 1915 const void *Decoder) { 1916 int Offset = SignExtend32<16>(Insn & 0xffff); 1917 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1918 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1919 1920 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1921 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1922 1923 Inst.addOperand(MCOperand::createReg(Reg)); 1924 Inst.addOperand(MCOperand::createReg(Base)); 1925 Inst.addOperand(MCOperand::createImm(Offset)); 1926 1927 return MCDisassembler::Success; 1928 } 1929 1930 static DecodeStatus DecodeFMem(MCInst &Inst, 1931 unsigned Insn, 1932 uint64_t Address, 1933 const void *Decoder) { 1934 int Offset = SignExtend32<16>(Insn & 0xffff); 1935 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1936 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1937 1938 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1939 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1940 1941 Inst.addOperand(MCOperand::createReg(Reg)); 1942 Inst.addOperand(MCOperand::createReg(Base)); 1943 Inst.addOperand(MCOperand::createImm(Offset)); 1944 1945 return MCDisassembler::Success; 1946 } 1947 1948 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1949 uint64_t Address, const void *Decoder) { 1950 // This function is the same as DecodeFMem but with the Reg and Base fields 1951 // swapped according to microMIPS spec. 1952 int Offset = SignExtend32<16>(Insn & 0xffff); 1953 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1954 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1955 1956 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1957 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1958 1959 Inst.addOperand(MCOperand::createReg(Reg)); 1960 Inst.addOperand(MCOperand::createReg(Base)); 1961 Inst.addOperand(MCOperand::createImm(Offset)); 1962 1963 return MCDisassembler::Success; 1964 } 1965 1966 static DecodeStatus DecodeFMem2(MCInst &Inst, 1967 unsigned Insn, 1968 uint64_t Address, 1969 const void *Decoder) { 1970 int Offset = SignExtend32<16>(Insn & 0xffff); 1971 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1972 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1973 1974 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1975 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1976 1977 Inst.addOperand(MCOperand::createReg(Reg)); 1978 Inst.addOperand(MCOperand::createReg(Base)); 1979 Inst.addOperand(MCOperand::createImm(Offset)); 1980 1981 return MCDisassembler::Success; 1982 } 1983 1984 static DecodeStatus DecodeFMem3(MCInst &Inst, 1985 unsigned Insn, 1986 uint64_t Address, 1987 const void *Decoder) { 1988 int Offset = SignExtend32<16>(Insn & 0xffff); 1989 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1990 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1991 1992 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1993 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1994 1995 Inst.addOperand(MCOperand::createReg(Reg)); 1996 Inst.addOperand(MCOperand::createReg(Base)); 1997 Inst.addOperand(MCOperand::createImm(Offset)); 1998 1999 return MCDisassembler::Success; 2000 } 2001 2002 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2003 unsigned Insn, 2004 uint64_t Address, 2005 const void *Decoder) { 2006 int Offset = SignExtend32<11>(Insn & 0x07ff); 2007 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2008 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2009 2010 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2011 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2012 2013 Inst.addOperand(MCOperand::createReg(Reg)); 2014 Inst.addOperand(MCOperand::createReg(Base)); 2015 Inst.addOperand(MCOperand::createImm(Offset)); 2016 2017 return MCDisassembler::Success; 2018 } 2019 2020 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2021 uint64_t Address, const void *Decoder) { 2022 int Offset = SignExtend32<11>(Insn & 0x07ff); 2023 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2024 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2025 2026 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2027 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2028 2029 Inst.addOperand(MCOperand::createReg(Reg)); 2030 Inst.addOperand(MCOperand::createReg(Base)); 2031 Inst.addOperand(MCOperand::createImm(Offset)); 2032 2033 return MCDisassembler::Success; 2034 } 2035 2036 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2037 unsigned Insn, 2038 uint64_t Address, 2039 const void *Decoder) { 2040 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2041 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2042 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2043 2044 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2045 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2046 2047 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2048 Inst.addOperand(MCOperand::createReg(Rt)); 2049 } 2050 2051 Inst.addOperand(MCOperand::createReg(Rt)); 2052 Inst.addOperand(MCOperand::createReg(Base)); 2053 Inst.addOperand(MCOperand::createImm(Offset)); 2054 2055 return MCDisassembler::Success; 2056 } 2057 2058 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2059 unsigned RegNo, 2060 uint64_t Address, 2061 const void *Decoder) { 2062 // Currently only hardware register 29 is supported. 2063 if (RegNo != 29) 2064 return MCDisassembler::Fail; 2065 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2066 return MCDisassembler::Success; 2067 } 2068 2069 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2070 unsigned RegNo, 2071 uint64_t Address, 2072 const void *Decoder) { 2073 if (RegNo > 30 || RegNo %2) 2074 return MCDisassembler::Fail; 2075 2076 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2077 Inst.addOperand(MCOperand::createReg(Reg)); 2078 return MCDisassembler::Success; 2079 } 2080 2081 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2082 unsigned RegNo, 2083 uint64_t Address, 2084 const void *Decoder) { 2085 if (RegNo >= 4) 2086 return MCDisassembler::Fail; 2087 2088 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2089 Inst.addOperand(MCOperand::createReg(Reg)); 2090 return MCDisassembler::Success; 2091 } 2092 2093 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2094 unsigned RegNo, 2095 uint64_t Address, 2096 const void *Decoder) { 2097 if (RegNo >= 4) 2098 return MCDisassembler::Fail; 2099 2100 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2101 Inst.addOperand(MCOperand::createReg(Reg)); 2102 return MCDisassembler::Success; 2103 } 2104 2105 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2106 unsigned RegNo, 2107 uint64_t Address, 2108 const void *Decoder) { 2109 if (RegNo >= 4) 2110 return MCDisassembler::Fail; 2111 2112 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2113 Inst.addOperand(MCOperand::createReg(Reg)); 2114 return MCDisassembler::Success; 2115 } 2116 2117 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2118 unsigned RegNo, 2119 uint64_t Address, 2120 const void *Decoder) { 2121 if (RegNo > 31) 2122 return MCDisassembler::Fail; 2123 2124 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2125 Inst.addOperand(MCOperand::createReg(Reg)); 2126 return MCDisassembler::Success; 2127 } 2128 2129 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2130 unsigned RegNo, 2131 uint64_t Address, 2132 const void *Decoder) { 2133 if (RegNo > 31) 2134 return MCDisassembler::Fail; 2135 2136 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2137 Inst.addOperand(MCOperand::createReg(Reg)); 2138 return MCDisassembler::Success; 2139 } 2140 2141 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2142 unsigned RegNo, 2143 uint64_t Address, 2144 const void *Decoder) { 2145 if (RegNo > 31) 2146 return MCDisassembler::Fail; 2147 2148 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2149 Inst.addOperand(MCOperand::createReg(Reg)); 2150 return MCDisassembler::Success; 2151 } 2152 2153 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2154 unsigned RegNo, 2155 uint64_t Address, 2156 const void *Decoder) { 2157 if (RegNo > 31) 2158 return MCDisassembler::Fail; 2159 2160 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2161 Inst.addOperand(MCOperand::createReg(Reg)); 2162 return MCDisassembler::Success; 2163 } 2164 2165 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2166 unsigned RegNo, 2167 uint64_t Address, 2168 const void *Decoder) { 2169 if (RegNo > 7) 2170 return MCDisassembler::Fail; 2171 2172 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2173 Inst.addOperand(MCOperand::createReg(Reg)); 2174 return MCDisassembler::Success; 2175 } 2176 2177 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2178 unsigned RegNo, 2179 uint64_t Address, 2180 const void *Decoder) { 2181 if (RegNo > 31) 2182 return MCDisassembler::Fail; 2183 2184 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2185 Inst.addOperand(MCOperand::createReg(Reg)); 2186 return MCDisassembler::Success; 2187 } 2188 2189 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2190 unsigned RegNo, 2191 uint64_t Address, 2192 const void *Decoder) { 2193 if (RegNo > 31) 2194 return MCDisassembler::Fail; 2195 2196 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2197 Inst.addOperand(MCOperand::createReg(Reg)); 2198 return MCDisassembler::Success; 2199 } 2200 2201 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2202 unsigned Offset, 2203 uint64_t Address, 2204 const void *Decoder) { 2205 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2206 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2207 return MCDisassembler::Success; 2208 } 2209 2210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2211 unsigned Offset, 2212 uint64_t Address, 2213 const void *Decoder) { 2214 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2215 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2216 return MCDisassembler::Success; 2217 } 2218 2219 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2220 unsigned Insn, 2221 uint64_t Address, 2222 const void *Decoder) { 2223 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2224 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2225 return MCDisassembler::Success; 2226 } 2227 2228 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2229 unsigned Offset, 2230 uint64_t Address, 2231 const void *Decoder) { 2232 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2233 2234 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2235 return MCDisassembler::Success; 2236 } 2237 2238 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2239 unsigned Offset, 2240 uint64_t Address, 2241 const void *Decoder) { 2242 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2243 2244 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2245 return MCDisassembler::Success; 2246 } 2247 2248 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2249 unsigned Offset, 2250 uint64_t Address, 2251 const void *Decoder) { 2252 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2253 2254 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2255 return MCDisassembler::Success; 2256 } 2257 2258 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2259 unsigned Offset, 2260 uint64_t Address, 2261 const void *Decoder) { 2262 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2263 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2264 return MCDisassembler::Success; 2265 } 2266 2267 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2268 unsigned Offset, 2269 uint64_t Address, 2270 const void *Decoder) { 2271 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2272 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2273 return MCDisassembler::Success; 2274 } 2275 2276 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2277 unsigned Offset, 2278 uint64_t Address, 2279 const void *Decoder) { 2280 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2281 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2282 return MCDisassembler::Success; 2283 } 2284 2285 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2286 unsigned Offset, 2287 uint64_t Address, 2288 const void *Decoder) { 2289 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2290 2291 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2292 return MCDisassembler::Success; 2293 } 2294 2295 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2296 unsigned Insn, 2297 uint64_t Address, 2298 const void *Decoder) { 2299 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2300 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2301 return MCDisassembler::Success; 2302 } 2303 2304 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2305 unsigned Value, 2306 uint64_t Address, 2307 const void *Decoder) { 2308 if (Value == 0) 2309 Inst.addOperand(MCOperand::createImm(1)); 2310 else if (Value == 0x7) 2311 Inst.addOperand(MCOperand::createImm(-1)); 2312 else 2313 Inst.addOperand(MCOperand::createImm(Value << 2)); 2314 return MCDisassembler::Success; 2315 } 2316 2317 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2318 unsigned Value, 2319 uint64_t Address, 2320 const void *Decoder) { 2321 if (Value == 0x7F) 2322 Inst.addOperand(MCOperand::createImm(-1)); 2323 else 2324 Inst.addOperand(MCOperand::createImm(Value)); 2325 return MCDisassembler::Success; 2326 } 2327 2328 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2329 unsigned Value, 2330 uint64_t Address, 2331 const void *Decoder) { 2332 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2333 return MCDisassembler::Success; 2334 } 2335 2336 template <unsigned Bits, int Offset, int Scale> 2337 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2338 uint64_t Address, 2339 const void *Decoder) { 2340 Value &= ((1 << Bits) - 1); 2341 Value *= Scale; 2342 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2343 return MCDisassembler::Success; 2344 } 2345 2346 template <unsigned Bits, int Offset, int ScaleBy> 2347 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2348 uint64_t Address, 2349 const void *Decoder) { 2350 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2351 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2352 return MCDisassembler::Success; 2353 } 2354 2355 static DecodeStatus DecodeInsSize(MCInst &Inst, 2356 unsigned Insn, 2357 uint64_t Address, 2358 const void *Decoder) { 2359 // First we need to grab the pos(lsb) from MCInst. 2360 // This function only handles the 32 bit variants of ins, as dins 2361 // variants are handled differently. 2362 int Pos = Inst.getOperand(2).getImm(); 2363 int Size = (int) Insn - Pos + 1; 2364 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2365 return MCDisassembler::Success; 2366 } 2367 2368 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2369 uint64_t Address, const void *Decoder) { 2370 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2371 return MCDisassembler::Success; 2372 } 2373 2374 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2375 uint64_t Address, const void *Decoder) { 2376 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2377 return MCDisassembler::Success; 2378 } 2379 2380 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2381 uint64_t Address, const void *Decoder) { 2382 int32_t DecodedValue; 2383 switch (Insn) { 2384 case 0: DecodedValue = 256; break; 2385 case 1: DecodedValue = 257; break; 2386 case 510: DecodedValue = -258; break; 2387 case 511: DecodedValue = -257; break; 2388 default: DecodedValue = SignExtend32<9>(Insn); break; 2389 } 2390 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2391 return MCDisassembler::Success; 2392 } 2393 2394 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2395 uint64_t Address, const void *Decoder) { 2396 // Insn must be >= 0, since it is unsigned that condition is always true. 2397 assert(Insn < 16); 2398 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2399 255, 32768, 65535}; 2400 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2401 return MCDisassembler::Success; 2402 } 2403 2404 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2405 unsigned Insn, 2406 uint64_t Address, 2407 const void *Decoder) { 2408 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2409 Mips::S6, Mips::S7, Mips::FP}; 2410 unsigned RegNum; 2411 2412 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2413 2414 // Empty register lists are not allowed. 2415 if (RegLst == 0) 2416 return MCDisassembler::Fail; 2417 2418 RegNum = RegLst & 0xf; 2419 2420 // RegLst values 10-15, and 26-31 are reserved. 2421 if (RegNum > 9) 2422 return MCDisassembler::Fail; 2423 2424 for (unsigned i = 0; i < RegNum; i++) 2425 Inst.addOperand(MCOperand::createReg(Regs[i])); 2426 2427 if (RegLst & 0x10) 2428 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2429 2430 return MCDisassembler::Success; 2431 } 2432 2433 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2434 uint64_t Address, 2435 const void *Decoder) { 2436 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2437 unsigned RegLst; 2438 switch(Inst.getOpcode()) { 2439 default: 2440 RegLst = fieldFromInstruction(Insn, 4, 2); 2441 break; 2442 case Mips::LWM16_MMR6: 2443 case Mips::SWM16_MMR6: 2444 RegLst = fieldFromInstruction(Insn, 8, 2); 2445 break; 2446 } 2447 unsigned RegNum = RegLst & 0x3; 2448 2449 for (unsigned i = 0; i <= RegNum; i++) 2450 Inst.addOperand(MCOperand::createReg(Regs[i])); 2451 2452 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2453 2454 return MCDisassembler::Success; 2455 } 2456 2457 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 2458 uint64_t Address, 2459 const void *Decoder) { 2460 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2461 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == 2462 MCDisassembler::Fail) 2463 return MCDisassembler::Fail; 2464 2465 unsigned RegRs; 2466 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) 2467 RegRs = fieldFromInstruction(Insn, 0, 2) | 2468 (fieldFromInstruction(Insn, 3, 1) << 2); 2469 else 2470 RegRs = fieldFromInstruction(Insn, 1, 3); 2471 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == 2472 MCDisassembler::Fail) 2473 return MCDisassembler::Fail; 2474 2475 unsigned RegRt = fieldFromInstruction(Insn, 4, 3); 2476 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == 2477 MCDisassembler::Fail) 2478 return MCDisassembler::Fail; 2479 2480 return MCDisassembler::Success; 2481 } 2482 2483 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2484 uint64_t Address, const void *Decoder) { 2485 switch (RegPair) { 2486 default: 2487 return MCDisassembler::Fail; 2488 case 0: 2489 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2490 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2491 break; 2492 case 1: 2493 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2494 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2495 break; 2496 case 2: 2497 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2498 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2499 break; 2500 case 3: 2501 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2502 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2503 break; 2504 case 4: 2505 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2506 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2507 break; 2508 case 5: 2509 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2510 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2511 break; 2512 case 6: 2513 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2514 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2515 break; 2516 case 7: 2517 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2518 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2519 break; 2520 } 2521 2522 return MCDisassembler::Success; 2523 } 2524 2525 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2526 uint64_t Address, const void *Decoder) { 2527 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2528 return MCDisassembler::Success; 2529 } 2530 2531 template <typename InsnType> 2532 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2533 uint64_t Address, 2534 const void *Decoder) { 2535 // We have: 2536 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2537 // Invalid if rt == 0 2538 // BGTZALC_MMR6 if rs == 0 && rt != 0 2539 // BLTZALC_MMR6 if rs != 0 && rs == rt 2540 // BLTUC_MMR6 if rs != 0 && rs != rt 2541 2542 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2543 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2544 InsnType Imm = 0; 2545 bool HasRs = false; 2546 bool HasRt = false; 2547 2548 if (Rt == 0) 2549 return MCDisassembler::Fail; 2550 else if (Rs == 0) { 2551 MI.setOpcode(Mips::BGTZALC_MMR6); 2552 HasRt = true; 2553 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2554 } 2555 else if (Rs == Rt) { 2556 MI.setOpcode(Mips::BLTZALC_MMR6); 2557 HasRs = true; 2558 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2559 } 2560 else { 2561 MI.setOpcode(Mips::BLTUC_MMR6); 2562 HasRs = true; 2563 HasRt = true; 2564 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2565 } 2566 2567 if (HasRs) 2568 MI.addOperand( 2569 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2570 2571 if (HasRt) 2572 MI.addOperand( 2573 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2574 2575 MI.addOperand(MCOperand::createImm(Imm)); 2576 2577 return MCDisassembler::Success; 2578 } 2579 2580 template <typename InsnType> 2581 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2582 uint64_t Address, 2583 const void *Decoder) { 2584 // We have: 2585 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2586 // Invalid if rt == 0 2587 // BLEZALC_MMR6 if rs == 0 && rt != 0 2588 // BGEZALC_MMR6 if rs == rt && rt != 0 2589 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2590 2591 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2592 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2593 InsnType Imm = 0; 2594 bool HasRs = false; 2595 2596 if (Rt == 0) 2597 return MCDisassembler::Fail; 2598 else if (Rs == 0) { 2599 MI.setOpcode(Mips::BLEZALC_MMR6); 2600 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2601 } 2602 else if (Rs == Rt) { 2603 MI.setOpcode(Mips::BGEZALC_MMR6); 2604 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2605 } 2606 else { 2607 HasRs = true; 2608 MI.setOpcode(Mips::BGEUC_MMR6); 2609 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2610 } 2611 2612 if (HasRs) 2613 MI.addOperand( 2614 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2615 MI.addOperand( 2616 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2617 2618 MI.addOperand(MCOperand::createImm(Imm)); 2619 2620 return MCDisassembler::Success; 2621 } 2622