1//===-- MSP430InstrInfo.td - MSP430 Instruction defs -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the MSP430 instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13include "MSP430InstrFormats.td" 14 15//===----------------------------------------------------------------------===// 16// Type Constraints. 17//===----------------------------------------------------------------------===// 18class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; 19class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; 20 21//===----------------------------------------------------------------------===// 22// Type Profiles. 23//===----------------------------------------------------------------------===// 24def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 25def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, 26 SDTCisVT<1, i16>]>; 27def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 28def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 29 SDTCisPtrTy<0>]>; 30def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 31def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, 32 SDTCisVT<1, i8>]>; 33def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 34 SDTCisSameAs<1, 2>, 35 SDTCisVT<3, i8>]>; 36def SDT_MSP430DAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>, 38 SDTCisInt<0>]>; 39 40//===----------------------------------------------------------------------===// 41// MSP430 Specific Node Definitions. 42//===----------------------------------------------------------------------===// 43def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone, 44 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 45def MSP430retiflag : SDNode<"MSP430ISD::RETI_FLAG", SDTNone, 46 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 47 48def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>; 49def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>; 50def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>; 51def MSP430rrcl : SDNode<"MSP430ISD::RRCL", SDTIntUnaryOp, []>; 52 53def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; 55def MSP430callseq_start : 56 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart, 57 [SDNPHasChain, SDNPOutGlue]>; 58def MSP430callseq_end : 59 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd, 60 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 61def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; 62def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutGlue]>; 63def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, 64 [SDNPHasChain, SDNPInGlue]>; 65def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, 66 [SDNPInGlue]>; 67def MSP430dadd : SDNode<"MSP430ISD::DADD", SDT_MSP430DAdd, []>; 68 69//===----------------------------------------------------------------------===// 70// MSP430 Operand Definitions. 71//===----------------------------------------------------------------------===// 72 73def MemAsmOperand : AsmOperandClass { 74 let Name = "Mem"; 75} 76 77// Address operands 78def memsrc : Operand<i16> { 79 let PrintMethod = "printSrcMemOperand"; 80 let MIOperandInfo = (ops GR16, i16imm); 81 let ParserMatchClass = MemAsmOperand; 82 let EncoderMethod = "getMemOpValue"; 83 let DecoderMethod = "DecodeMemOperand"; 84} 85 86def memdst : Operand<i16> { 87 let PrintMethod = "printSrcMemOperand"; 88 let MIOperandInfo = (ops GR16, i16imm); 89 let ParserMatchClass = MemAsmOperand; 90 let EncoderMethod = "getMemOpValue"; 91 let DecoderMethod = "DecodeMemOperand"; 92} 93 94def IndRegAsmOperand : AsmOperandClass { 95 let Name = "IndReg"; 96 let RenderMethod = "addRegOperands"; 97} 98 99def indreg : Operand<i16> { 100 let PrintMethod = "printIndRegOperand"; 101 let MIOperandInfo = (ops GR16); 102 let ParserMatchClass = IndRegAsmOperand; 103 let DecoderMethod = "DecodeGR16RegisterClass"; 104} 105 106def PostIndRegAsmOperand : AsmOperandClass { 107 let Name = "PostIndReg"; 108 let RenderMethod = "addRegOperands"; 109} 110 111def postreg : Operand<i16> { 112 let PrintMethod = "printPostIndRegOperand"; 113 let MIOperandInfo = (ops GR16); 114 let ParserMatchClass = PostIndRegAsmOperand; 115 let DecoderMethod = "DecodeGR16RegisterClass"; 116} 117 118// Short jump targets have OtherVT type and are printed as pcrel imm values. 119def jmptarget : Operand<OtherVT> { 120 let PrintMethod = "printPCRelImmOperand"; 121 let EncoderMethod = "getPCRelImmOpValue"; 122} 123 124// Operand for printing out a condition code. 125def cc : Operand<i8> { 126 let PrintMethod = "printCCOperand"; 127 let EncoderMethod = "getCCOpValue"; 128} 129 130def CGImmAsmOperand : AsmOperandClass { 131 let Name = "CGImm"; 132 let RenderMethod = "addImmOperands"; 133} 134 135def cg8imm : Operand<i8>, 136 ImmLeaf<i8, [{return Imm == 0 || Imm == 1 || Imm == 2 || 137 Imm == 4 || Imm == 8 || Imm == -1;}]> { 138 let ParserMatchClass = CGImmAsmOperand; 139 let EncoderMethod = "getCGImmOpValue"; 140 let DecoderMethod = "DecodeCGImm"; 141} 142 143def cg16imm : Operand<i16>, 144 ImmLeaf<i16, [{return Imm == 0 || Imm == 1 || Imm == 2 || 145 Imm == 4 || Imm == 8 || Imm == -1;}]> { 146 let ParserMatchClass = CGImmAsmOperand; 147 let EncoderMethod = "getCGImmOpValue"; 148 let DecoderMethod = "DecodeCGImm"; 149} 150 151//===----------------------------------------------------------------------===// 152// MSP430 Complex Pattern Definitions. 153//===----------------------------------------------------------------------===// 154 155def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>; 156 157//===----------------------------------------------------------------------===// 158// Pattern Fragments 159def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 160def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>; 161def bic : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, (not node:$rhs))>; 162def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 163 return N->hasOneUse(); 164}]>; 165//===----------------------------------------------------------------------===// 166// Instruction list.. 167 168// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into 169// a stack adjustment and the codegen must know that they may modify the stack 170// pointer before prolog-epilog rewriting occurs. 171// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 172// sub / add which can clobber SR. 173let isCodeGenOnly = 1, Defs = [SP, SR], Uses = [SP] in { 174def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), 175 "#ADJCALLSTACKDOWN $amt1 $amt2", 176 [(MSP430callseq_start timm:$amt1, timm:$amt2)]>; 177def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), 178 "#ADJCALLSTACKUP $amt1 $amt2", 179 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>; 180} 181 182let isCodeGenOnly = 1, Defs = [SR], Uses = [SP] in { 183def ADDframe : Pseudo<(outs GR16:$dst), (ins i16imm:$base, i16imm:$offset), 184 "# ADDframe PSEUDO", []>; 185} 186 187let isCodeGenOnly = 1, usesCustomInserter = 1 in { 188 let Uses = [SR] in { 189 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc), 190 "# Select8 PSEUDO", 191 [(set GR8:$dst, 192 (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>; 193 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc), 194 "# Select16 PSEUDO", 195 [(set GR16:$dst, 196 (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>; 197 } 198 let Defs = [SR] in { 199 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 200 "# Shl8 PSEUDO", 201 [(set GR8:$dst, (shl GR8:$src, GR8:$cnt))]>; 202 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 203 "# Shl16 PSEUDO", 204 [(set GR16:$dst, (shl GR16:$src, GR8:$cnt))]>; 205 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 206 "# Sra8 PSEUDO", 207 [(set GR8:$dst, (sra GR8:$src, GR8:$cnt))]>; 208 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 209 "# Sra16 PSEUDO", 210 [(set GR16:$dst, (sra GR16:$src, GR8:$cnt))]>; 211 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 212 "# Srl8 PSEUDO", 213 [(set GR8:$dst, (srl GR8:$src, GR8:$cnt))]>; 214 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 215 "# Srl16 PSEUDO", 216 [(set GR16:$dst, (srl GR16:$src, GR8:$cnt))]>; 217 def Rrcl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src), "", 218 [(set GR8:$dst, (MSP430rrcl GR8:$src))]>; 219 def Rrcl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src), "", 220 [(set GR16:$dst, (MSP430rrcl GR16:$src))]>; 221 } 222} 223 224//===----------------------------------------------------------------------===// 225// Control Flow Instructions... 226// 227 228let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 229 def RET : IForm16<0b0100, DstReg, SrcPostInc, 2, 230 (outs), (ins), "ret", [(MSP430retflag)]> { 231 let DecoderNamespace = "Delta"; 232 let rs = 1; 233 let rd = 0; 234 } 235 def RETI : IIForm16<0b110, SrcReg, 2, 236 (outs), (ins), "reti", [(MSP430retiflag)]> { 237 let rs = 0; 238 } 239} 240 241let isBranch = 1, isTerminator = 1 in { 242 243// FIXME: expand opcode & cond field for branches! 244 245// Direct branch 246let isBarrier = 1 in { 247 // Short branch 248 def JMP : CJForm<(outs), (ins jmptarget:$dst), 249 "jmp\t$dst", 250 [(br bb:$dst)]> { 251 let cond = 0b111; 252 } 253 let isIndirectBranch = 1, rd = 0 in { 254 // Long branches 255 def Bi : I16ri<0b0100, (outs), (ins i16imm:$imm), 256 "br\t$imm", 257 [(brind tblockaddress:$imm)]>; 258 def Br : I16rr<0b0100, (outs), (ins GR16:$rs), 259 "br\t$rs", 260 [(brind GR16:$rs)]>; 261 def Bm : I16rm<0b0100, (outs), (ins memsrc:$src), 262 "br\t$src", 263 [(brind (load addr:$src))]>; 264 } 265} 266 267// Conditional branches 268let Uses = [SR] in 269 def JCC : CJForm<(outs), (ins jmptarget:$dst, cc:$cond), 270 "j$cond\t$dst", 271 [(MSP430brcc bb:$dst, imm:$cond)]>; 272} // isBranch, isTerminator 273 274//===----------------------------------------------------------------------===// 275// Call Instructions... 276// 277// All calls clobber the non-callee saved registers. SPW is marked as 278// a use to prevent stack-pointer assignments that appear immediately 279// before calls from potentially appearing dead. Uses for argument 280// registers are added manually. 281let isCall = 1, 282 Defs = [R11, R12, R13, R14, R15, SR], 283 Uses = [SP] in { 284 def CALLi : II16i<0b101, 285 (outs), (ins i16imm:$imm), 286 "call\t$imm", [(MSP430call imm:$imm)]>; 287 def CALLr : II16r<0b101, 288 (outs), (ins GR16:$rs), 289 "call\t$rs", [(MSP430call GR16:$rs)]>; 290 def CALLm : II16m<0b101, 291 (outs), (ins memsrc:$src), 292 "call\t$src", [(MSP430call (load addr:$src))]>; 293 def CALLn : II16n<0b101, (outs), (ins indreg:$rs), "call\t$rs", []>; 294 def CALLp : II16p<0b101, (outs), (ins postreg:$rs), "call\t$rs", []>; 295} 296 297//===----------------------------------------------------------------------===// 298// Miscellaneous Instructions... 299// 300let Defs = [SP], Uses = [SP], hasSideEffects = 0 in { 301let mayLoad = 1 in 302def POP16r : IForm16<0b0100, DstReg, SrcPostInc, 2, 303 (outs GR16:$rd), (ins), "pop\t$rd", []> { 304 let DecoderNamespace = "Delta"; 305 let rs = 1; 306} 307 308let mayStore = 1 in 309def PUSH8r : II8r<0b100, (outs), (ins GR8:$rs), "push.b\t$rs", []>; 310def PUSH16r : II16r<0b100, (outs), (ins GR16:$rs), "push\t$rs", []>; 311def PUSH16c : II16c<0b100, (outs), (ins cg16imm:$imm), "push\t$imm", []>; 312def PUSH16i : II16i<0b100, (outs), (ins i16imm:$imm), "push\t$imm", []>; 313} 314 315//===----------------------------------------------------------------------===// 316// Move Instructions 317 318let hasSideEffects = 0 in { 319def MOV8rr : I8rr<0b0100, 320 (outs GR8:$rd), (ins GR8:$rs), 321 "mov.b\t{$rs, $rd}", 322 []>; 323def MOV16rr : I16rr<0b0100, 324 (outs GR16:$rd), (ins GR16:$rs), 325 "mov\t{$rs, $rd}", 326 []>; 327} 328 329let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 330def MOV8rc : I8rc<0b0100, 331 (outs GR8:$rd), (ins cg8imm:$imm), 332 "mov.b\t$imm, $rd", 333 [(set GR8:$rd, cg8imm:$imm)]>; 334def MOV16rc : I16rc<0b0100, 335 (outs GR16:$rd), (ins cg16imm:$imm), 336 "mov\t$imm, $rd", 337 [(set GR16:$rd, cg16imm:$imm)]>; 338def MOV8ri : I8ri<0b0100, 339 (outs GR8:$rd), (ins i8imm:$imm), 340 "mov.b\t{$imm, $rd}", 341 [(set GR8:$rd, imm:$imm)]>; 342def MOV16ri : I16ri<0b0100, 343 (outs GR16:$rd), (ins i16imm:$imm), 344 "mov\t{$imm, $rd}", 345 [(set GR16:$rd, imm:$imm)]>; 346} 347 348let canFoldAsLoad = 1, isReMaterializable = 1 in { 349def MOV8rm : I8rm<0b0100, 350 (outs GR8:$rd), (ins memsrc:$src), 351 "mov.b\t{$src, $rd}", 352 [(set GR8:$rd, (load addr:$src))]>; 353def MOV16rm : I16rm<0b0100, 354 (outs GR16:$rd), (ins memsrc:$src), 355 "mov\t{$src, $rd}", 356 [(set GR16:$rd, (load addr:$src))]>; 357def MOV8rn : I8rn<0b0100, 358 (outs GR8:$rd), (ins indreg:$rs), 359 "mov.b\t{$rs, $rd}", 360 [(set GR8:$rd, (load addr:$rs))]>; 361def MOV16rn : I16rn<0b0100, 362 (outs GR16:$rd), (ins indreg:$rs), 363 "mov\t{$rs, $rd}", 364 [(set GR16:$rd, (load addr:$rs))]>; 365} 366 367let isCodeGenOnly = 1 in { 368def MOVZX16rr8 : I8rr<0b0100, 369 (outs GR16:$rd), (ins GR8:$rs), 370 "mov.b\t{$rs, $rd}", 371 [(set GR16:$rd, (zext GR8:$rs))]>; 372def MOVZX16rm8 : I8rm<0b0100, 373 (outs GR16:$rd), (ins memsrc:$src), 374 "mov.b\t{$src, $rd}", 375 [(set GR16:$rd, (zextloadi16i8 addr:$src))]>; 376} 377 378let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$rs = $wb" in { 379def MOV8rp : I8rp<0b0100, 380 (outs GR8:$rd, GR16:$wb), (ins postreg:$rs), 381 "mov.b\t{$rs, $rd}", []>; 382def MOV16rp : I16rp<0b0100, 383 (outs GR16:$rd, GR16:$wb), (ins postreg:$rs), 384 "mov\t{$rs, $rd}", []>; 385} 386 387// Any instruction that defines a 8-bit result leaves the high half of the 388// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may 389// be copying from a truncate, but any other 8-bit operation will zero-extend 390// up to 16 bits. 391def def8 : PatLeaf<(i8 GR8:$src), [{ 392 return N->getOpcode() != ISD::TRUNCATE && 393 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 394 N->getOpcode() != ISD::CopyFromReg; 395}]>; 396 397// In the case of a 8-bit def that is known to implicitly zero-extend, 398// we can use a SUBREG_TO_REG. 399def : Pat<(i16 (zext def8:$src)), 400 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; 401 402def MOV8mc : I8mc<0b0100, 403 (outs), (ins memdst:$dst, cg8imm:$imm), 404 "mov.b\t{$imm, $dst}", 405 [(store (i8 cg8imm:$imm), addr:$dst)]>; 406def MOV16mc : I16mc<0b0100, 407 (outs), (ins memdst:$dst, cg16imm:$imm), 408 "mov\t{$imm, $dst}", 409 [(store (i16 cg16imm:$imm), addr:$dst)]>; 410 411def MOV8mi : I8mi<0b0100, 412 (outs), (ins memdst:$dst, i8imm:$imm), 413 "mov.b\t{$imm, $dst}", 414 [(store (i8 imm:$imm), addr:$dst)]>; 415def MOV16mi : I16mi<0b0100, 416 (outs), (ins memdst:$dst, i16imm:$imm), 417 "mov\t{$imm, $dst}", 418 [(store (i16 imm:$imm), addr:$dst)]>; 419 420def MOV8mr : I8mr<0b0100, 421 (outs), (ins memdst:$dst, GR8:$rs), 422 "mov.b\t{$rs, $dst}", 423 [(store GR8:$rs, addr:$dst)]>; 424def MOV16mr : I16mr<0b0100, 425 (outs), (ins memdst:$dst, GR16:$rs), 426 "mov\t{$rs, $dst}", 427 [(store GR16:$rs, addr:$dst)]>; 428 429def MOV8mm : I8mm<0b0100, 430 (outs), (ins memdst:$dst, memsrc:$src), 431 "mov.b\t{$src, $dst}", 432 [(store (i8 (load addr:$src)), addr:$dst)]>; 433def MOV16mm : I16mm<0b0100, 434 (outs), (ins memdst:$dst, memsrc:$src), 435 "mov\t{$src, $dst}", 436 [(store (i16 (load addr:$src)), addr:$dst)]>; 437 438def MOV8mn : I8mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs), 439 "mov.b\t{$rs, $dst}", []>; 440def MOV16mn : I16mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs), 441 "mov\t{$rs, $dst}", []>; 442 443//===----------------------------------------------------------------------===// 444// Arithmetic Instructions 445 446multiclass Arith<bits<4> opcode, string asmstring, SDNode node, 447 bit commutes, list<Register> uses> { 448 let Defs = [SR], Uses = uses in { 449 let Constraints = "$src2 = $rd" in { 450 let isCommutable = commutes in { 451 def 8rr : I8rr<opcode, (outs GR8:$rd), (ins GR8:$src2, GR8:$rs), 452 !strconcat(asmstring, ".b\t$rs, $rd"), 453 [(set GR8:$rd, (node GR8:$src2, GR8:$rs)), 454 (implicit SR)]>; 455 def 16rr : I16rr<opcode, (outs GR16:$rd), (ins GR16:$src2, GR16:$rs), 456 !strconcat(asmstring, "\t$rs, $rd"), 457 [(set GR16:$rd, (node GR16:$src2, GR16:$rs)), 458 (implicit SR)]>; 459 } 460 def 8rm : I8rm<opcode, (outs GR8:$rd), (ins GR8:$src2, memsrc:$src), 461 !strconcat(asmstring, ".b\t$src, $rd"), 462 [(set GR8:$rd, (node GR8:$src2, (load addr:$src))), 463 (implicit SR)]>; 464 def 16rm : I16rm<opcode, (outs GR16:$rd), (ins GR16:$src2, memsrc:$src), 465 !strconcat(asmstring, "\t$src, $rd"), 466 [(set GR16:$rd, (node GR16:$src2, (load addr:$src))), 467 (implicit SR)]>; 468 def 8rn : I8rn<opcode, (outs GR8:$rd), (ins GR8:$src2, indreg:$rs), 469 !strconcat(asmstring, ".b\t$rs, $rd"), []>; 470 def 16rn : I16rn<opcode, (outs GR16:$rd), (ins GR16:$src2, indreg:$rs), 471 !strconcat(asmstring, "\t$rs, $rd"), []>; 472 let mayLoad = 1, 473 hasExtraDefRegAllocReq = 1, 474 Constraints = "$rs = $wb, $src2 = $rd" in { 475 def 8rp : I8rp<opcode, (outs GR8:$rd, GR16:$wb), (ins GR8:$src2, postreg:$rs), 476 !strconcat(asmstring, ".b\t$rs, $rd"), []>; 477 def 16rp : I16rp<opcode, (outs GR16:$rd, GR16:$wb), (ins GR16:$src2, postreg:$rs), 478 !strconcat(asmstring, "\t$rs, $rd"), []>; 479 } 480 def 8rc : I8rc<opcode, (outs GR8:$rd), (ins GR8:$src2, cg8imm:$imm), 481 !strconcat(asmstring, ".b\t$imm, $rd"), 482 [(set GR8:$rd, (node GR8:$src2, cg8imm:$imm)), 483 (implicit SR)]>; 484 def 16rc : I16rc<opcode, (outs GR16:$rd), (ins GR16:$src2, cg16imm:$imm), 485 !strconcat(asmstring, "\t$imm, $rd"), 486 [(set GR16:$rd, (node GR16:$src2, cg16imm:$imm)), 487 (implicit SR)]>; 488 def 8ri : I8ri<opcode, (outs GR8:$rd), (ins GR8:$src2, i8imm:$imm), 489 !strconcat(asmstring, ".b\t$imm, $rd"), 490 [(set GR8:$rd, (node GR8:$src2, imm:$imm)), 491 (implicit SR)]>; 492 def 16ri : I16ri<opcode, (outs GR16:$rd), (ins GR16:$src2, i16imm:$imm), 493 !strconcat(asmstring, "\t$imm, $rd"), 494 [(set GR16:$rd, (node GR16:$src2, imm:$imm)), 495 (implicit SR)]>; 496 } 497 def 8mr : I8mr<opcode, (outs), (ins memdst:$dst, GR8:$rs), 498 !strconcat(asmstring, ".b\t$rs, $dst"), 499 [(store (node (load addr:$dst), GR8:$rs), addr:$dst), 500 (implicit SR)]>; 501 def 16mr : I16mr<opcode, (outs), (ins memdst:$dst, GR16:$rs), 502 !strconcat(asmstring, "\t$rs, $dst"), 503 [(store (node (load addr:$dst), GR16:$rs), addr:$dst), 504 (implicit SR)]>; 505 def 8mc : I8mc<opcode, (outs), (ins memdst:$dst, cg8imm:$imm), 506 !strconcat(asmstring, ".b\t$imm, $dst"), 507 [(store (node (load addr:$dst), (i8 cg8imm:$imm)), addr:$dst), 508 (implicit SR)]>; 509 def 16mc : I16mc<opcode, (outs), (ins memdst:$dst, cg16imm:$imm), 510 !strconcat(asmstring, "\t$imm, $dst"), 511 [(store (node (load addr:$dst), (i16 cg16imm:$imm)), addr:$dst), 512 (implicit SR)]>; 513 def 8mi : I8mi<opcode, (outs), (ins memdst:$dst, i8imm:$imm), 514 !strconcat(asmstring, ".b\t$imm, $dst"), 515 [(store (node (load addr:$dst), (i8 imm:$imm)), addr:$dst), 516 (implicit SR)]>; 517 def 16mi : I16mi<opcode, (outs), (ins memdst:$dst, i16imm:$imm), 518 !strconcat(asmstring, "\t$imm, $dst"), 519 [(store (node (load addr:$dst), (i16 imm:$imm)), addr:$dst), 520 (implicit SR)]>; 521 def 8mm : I8mm<opcode, (outs), (ins memdst:$dst, memsrc:$src), 522 !strconcat(asmstring, ".b\t$src, $dst"), 523 [(store (node (load addr:$dst), 524 (i8 (load addr:$src))), addr:$dst), 525 (implicit SR)]>; 526 def 16mm : I16mm<opcode, (outs), (ins memdst:$dst, memsrc:$src), 527 !strconcat(asmstring, "\t$src, $dst"), 528 [(store (node (load addr:$dst), 529 (i16 (load addr:$src))), addr:$dst), 530 (implicit SR)]>; 531 def 8mn : I8mn<opcode, (outs), (ins memdst:$dst, indreg:$rs), 532 !strconcat(asmstring, ".b\t$rs, $dst"), []>; 533 def 16mn : I16mn<opcode, (outs), (ins memdst:$dst, indreg:$rs), 534 !strconcat(asmstring, "\t$rs, $dst"), []>; 535 def 8mp : I8mp<opcode, (outs), (ins memdst:$dst, postreg:$rs), 536 !strconcat(asmstring, ".b\t$rs, $dst"), []>; 537 def 16mp : I16mp<opcode, (outs), (ins memdst:$dst, postreg:$rs), 538 !strconcat(asmstring, "\t$rs, $dst"), []>; 539 } 540} 541 542defm ADD : Arith<0b0101, "add", add, 1, []>; 543defm ADDC : Arith<0b0110, "addc", adde, 1, [SR]>; 544defm AND : Arith<0b1111, "and", and, 1, []>; 545defm BIS : Arith<0b1101, "bis", or, 1, []>; 546defm BIC : Arith<0b1100, "bic", bic, 0, []>; 547defm XOR : Arith<0b1110, "xor", xor, 1, []>; 548defm SUB : Arith<0b1000, "sub", sub, 0, []>; 549defm SUBC : Arith<0b0111, "subc", sube, 0, [SR]>; 550defm DADD : Arith<0b1010, "dadd", MSP430dadd, 1, [SR]>; 551 552def ADC8r : InstAlias<"adc.b\t$dst", (ADDC8rc GR8:$dst, 0)>; 553def ADC16r : InstAlias<"adc\t$dst", (ADDC16rc GR16:$dst, 0)>; 554def ADC8m : InstAlias<"adc.b\t$dst", (ADDC8mc memdst:$dst, 0)>; 555def ADC16m : InstAlias<"adc\t$dst", (ADDC16mc memdst:$dst, 0)>; 556 557def DADC8r : InstAlias<"dadc.b\t$dst", (DADD8rc GR8:$dst, 0)>; 558def DADC16r : InstAlias<"dadc\t$dst", (DADD16rc GR16:$dst, 0)>; 559def DADC8m : InstAlias<"dadc.b\t$dst", (DADD8mc memdst:$dst, 0)>; 560def DADC16m : InstAlias<"dadc\t$dst", (DADD16mc memdst:$dst, 0)>; 561 562def DEC8r : InstAlias<"dec.b\t$dst", (SUB8rc GR8:$dst, 1)>; 563def DEC16r : InstAlias<"dec\t$dst", (SUB16rc GR16:$dst, 1)>; 564def DEC8m : InstAlias<"dec.b\t$dst", (SUB8mc memdst:$dst, 1)>; 565def DEC16m : InstAlias<"dec\t$dst", (SUB16mc memdst:$dst, 1)>; 566 567def DECD8r : InstAlias<"decd.b\t$dst", (SUB8rc GR8:$dst, 2)>; 568def DECD16r : InstAlias<"decd\t$dst", (SUB16rc GR16:$dst, 2)>; 569def DECD8m : InstAlias<"decd.b\t$dst", (SUB8mc memdst:$dst, 2)>; 570def DECD16m : InstAlias<"decd\t$dst", (SUB16mc memdst:$dst, 2)>; 571 572def INC8r : InstAlias<"inc.b\t$dst", (ADD8rc GR8:$dst, 1)>; 573def INC16r : InstAlias<"inc\t$dst", (ADD16rc GR16:$dst, 1)>; 574def INC8m : InstAlias<"inc.b\t$dst", (ADD8mc memdst:$dst, 1)>; 575def INC16m : InstAlias<"inc\t$dst", (ADD16mc memdst:$dst, 1)>; 576 577def INCD8r : InstAlias<"incd.b\t$dst", (ADD8rc GR8:$dst, 2)>; 578def INCD16r : InstAlias<"incd\t$dst", (ADD16rc GR16:$dst, 2)>; 579def INCD8m : InstAlias<"incd.b\t$dst", (ADD8mc memdst:$dst, 2)>; 580def INCD16m : InstAlias<"incd\t$dst", (ADD16mc memdst:$dst, 2)>; 581 582def SBC8r : InstAlias<"sbc.b\t$dst", (SUBC8rc GR8:$dst, 0)>; 583def SBC16r : InstAlias<"sbc\t$dst", (SUBC16rc GR16:$dst, 0)>; 584def SBC8m : InstAlias<"sbc.b\t$dst", (SUBC8mc memdst:$dst, 0)>; 585def SBC16m : InstAlias<"sbc\t$dst", (SUBC16mc memdst:$dst, 0)>; 586 587def INV8r : InstAlias<"inv.b\t$dst", (XOR8rc GR8:$dst, -1)>; 588def INV16r : InstAlias<"inv\t$dst", (XOR16rc GR16:$dst, -1)>; 589def INV8m : InstAlias<"inv.b\t$dst", (XOR8mc memdst:$dst, -1)>; 590def INV16m : InstAlias<"inv\t$dst", (XOR16mc memdst:$dst, -1)>; 591 592// printAliasInstr() doesn't check $dst operands are actually equal 593// for RLA and RLC aliases below, so disable printing aliases. 594 595def RLA8r : InstAlias<"rla.b\t$dst", (ADD8rr GR8:$dst, GR8:$dst), 0>; 596def RLA16r : InstAlias<"rla\t$dst", (ADD16rr GR16:$dst, GR16:$dst), 0>; 597def RLA8m : InstAlias<"rla.b\t$dst", (ADD8mm memdst:$dst, memdst:$dst), 0>; 598def RLA16m : InstAlias<"rla\t$dst", (ADD16mm memdst:$dst, memdst:$dst), 0>; 599 600def RLC8r : InstAlias<"rlc.b\t$dst", (ADDC8rr GR8:$dst, GR8:$dst), 0>; 601def RLC16r : InstAlias<"rlc\t$dst", (ADDC16rr GR16:$dst, GR16:$dst), 0>; 602def RLC8m : InstAlias<"rlc.b\t$dst", (ADDC8mm memdst:$dst, memdst:$dst), 0>; 603def RLC16m : InstAlias<"rlc\t$dst", (ADDC16mm memdst:$dst, memdst:$dst), 0>; 604 605def DINT : InstAlias<"dint", (BIC16rc SR, 8)>; 606def EINT : InstAlias<"eint", (BIS16rc SR, 8)>; 607 608def NOP : InstAlias<"nop", (MOV16rc CG, 0)>; 609 610def CLR8r : InstAlias<"clr.b\t$dst", (MOV8rc GR8:$dst, 0)>; 611def CLR16r : InstAlias<"clr\t$dst", (MOV16rc GR16:$dst, 0)>; 612def CLR8m : InstAlias<"clr.b\t$dst", (MOV8mc memdst:$dst, 0)>; 613def CLR16m : InstAlias<"clr\t$dst", (MOV16mc memdst:$dst, 0)>; 614 615def CLRC : InstAlias<"clrc", (BIC16rc SR, 1)>; 616def CLRN : InstAlias<"clrn", (BIC16rc SR, 4)>; 617def CLRZ : InstAlias<"clrz", (BIC16rc SR, 2)>; 618def SETC : InstAlias<"setc", (BIS16rc SR, 1)>; 619def SETN : InstAlias<"setn", (BIS16rc SR, 4)>; 620def SETZ : InstAlias<"setz", (BIS16rc SR, 2)>; 621 622def : Pat<(MSP430rla GR8:$dst), (ADD8rr $dst, $dst)>; 623def : Pat<(MSP430rla GR16:$dst), (ADD16rr $dst, $dst)>; 624 625// Format-II (Single Operand) Instruction 626// Register mode 627let Constraints = "$rs = $rd" in { 628 629let Defs = [SR] in { 630def RRA8r : II8r<0b010, 631 (outs GR8:$rd), (ins GR8:$rs), 632 "rra.b\t$rd", 633 [(set GR8:$rd, (MSP430rra GR8:$rs)), 634 (implicit SR)]>; 635def RRA16r : II16r<0b010, 636 (outs GR16:$rd), (ins GR16:$rs), 637 "rra\t$rd", 638 [(set GR16:$rd, (MSP430rra GR16:$rs)), 639 (implicit SR)]>; 640 641let Uses = [SR] in { 642def RRC8r : II8r<0b000, 643 (outs GR8:$rd), (ins GR8:$rs), 644 "rrc.b\t$rd", 645 [(set GR8:$rd, (MSP430rrc GR8:$rs)), 646 (implicit SR)]>; 647def RRC16r : II16r<0b000, 648 (outs GR16:$rd), (ins GR16:$rs), 649 "rrc\t$rd", 650 [(set GR16:$rd, (MSP430rrc GR16:$rs)), 651 (implicit SR)]>; 652} // Uses = [SR] 653 654def SEXT16r : II16r<0b011, 655 (outs GR16:$rd), (ins GR16:$rs), 656 "sxt\t$rd", 657 [(set GR16:$rd, (sext_inreg GR16:$rs, i8)), 658 (implicit SR)]>; 659 660} // Defs = [SR] 661 662let isCodeGenOnly = 1 in 663def ZEXT16r : I8rr<0b0100, 664 (outs GR16:$rd), (ins GR16:$rs), 665 "mov.b\t{$rs, $rd}", 666 [(set GR16:$rd, (zext (trunc GR16:$rs)))]>; 667 668def SWPB16r : II16r<0b001, 669 (outs GR16:$rd), (ins GR16:$rs), 670 "swpb\t$rd", 671 [(set GR16:$rd, (bswap GR16:$rs))]>; 672 673} // Constraints = "$src = $dst" 674 675// Indexed, indirect register and indirect autoincrement modes 676let Defs = [SR] in { 677def RRA8m : II8m<0b010, 678 (outs), (ins memsrc:$src), 679 "rra.b\t$src", 680 [(store (MSP430rra (i8 (load addr:$src))), addr:$src), 681 (implicit SR)]>; 682def RRA16m : II16m<0b010, 683 (outs), (ins memsrc:$src), 684 "rra\t$src", 685 [(store (MSP430rra (i16 (load addr:$src))), addr:$src), 686 (implicit SR)]>; 687 688def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>; 689def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>; 690def RRA8p : II8p<0b010, (outs), (ins postreg:$rs), "rra.b\t$rs", []>; 691def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>; 692 693let Uses = [SR] in { 694def RRC8m : II8m<0b000, 695 (outs), (ins memsrc:$src), 696 "rrc.b\t$src", 697 [(store (MSP430rrc (i8 (load addr:$src))), addr:$src), 698 (implicit SR)]>; 699def RRC16m : II16m<0b000, 700 (outs), (ins memsrc:$src), 701 "rrc\t$src", 702 [(store (MSP430rrc (i16 (load addr:$src))), addr:$src), 703 (implicit SR)]>; 704 705def RRC8n : II8n<0b000, (outs), (ins indreg:$rs), "rrc.b\t$rs", []>; 706def RRC16n : II16n<0b000, (outs), (ins indreg:$rs), "rrc\t$rs", []>; 707def RRC8p : II8p<0b000, (outs), (ins postreg:$rs), "rrc.b\t$rs", []>; 708def RRC16p : II16p<0b000, (outs), (ins postreg:$rs), "rrc\t$rs", []>; 709 710} // Uses = [SR] 711 712def SEXT16m : II16m<0b011, 713 (outs), (ins memsrc:$src), 714 "sxt\t$src", 715 [(store (sext_inreg (extloadi16i8 addr:$src), i8), 716 addr:$src), 717 (implicit SR)]>; 718def SEXT16n : II16n<0b011, (outs), (ins indreg:$rs), "sxt\t$rs", []>; 719def SEXT16p : II16p<0b011, (outs), (ins postreg:$rs), "sxt\t$rs", []>; 720 721} // Defs = [SR] 722 723def SWPB16m : II16m<0b001, 724 (outs), (ins memsrc:$src), 725 "swpb\t$src", 726 [(store (bswap (i16 (load addr:$src))), addr:$src)]>; 727def SWPB16n : II16n<0b001, (outs), (ins indreg:$rs), "swpb\t$rs", []>; 728def SWPB16p : II16p<0b001, (outs), (ins postreg:$rs), "swpb\t$rs", []>; 729 730// Integer comparisons 731let Defs = [SR] in { 732def CMP8rr : I8rr<0b1001, 733 (outs), (ins GR8:$rd, GR8:$rs), 734 "cmp.b\t$rs, $rd", 735 [(MSP430cmp GR8:$rd, GR8:$rs), (implicit SR)]>; 736def CMP16rr : I16rr<0b1001, 737 (outs), (ins GR16:$rd, GR16:$rs), 738 "cmp\t$rs, $rd", 739 [(MSP430cmp GR16:$rd, GR16:$rs), (implicit SR)]>; 740 741def CMP8rc : I8rc<0b1001, 742 (outs), (ins GR8:$rd, cg8imm:$imm), 743 "cmp.b\t$imm, $rd", 744 [(MSP430cmp GR8:$rd, cg8imm:$imm), (implicit SR)]>; 745def CMP16rc : I16rc<0b1001, 746 (outs), (ins GR16:$rd, cg16imm:$imm), 747 "cmp\t$imm, $rd", 748 [(MSP430cmp GR16:$rd, cg16imm:$imm), (implicit SR)]>; 749 750def CMP8ri : I8ri<0b1001, 751 (outs), (ins GR8:$rd, i8imm:$imm), 752 "cmp.b\t$imm, $rd", 753 [(MSP430cmp GR8:$rd, imm:$imm), (implicit SR)]>; 754def CMP16ri : I16ri<0b1001, 755 (outs), (ins GR16:$rd, i16imm:$imm), 756 "cmp\t$imm, $rd", 757 [(MSP430cmp GR16:$rd, imm:$imm), (implicit SR)]>; 758 759def CMP8mc : I8mc<0b1001, 760 (outs), (ins memsrc:$dst, cg8imm:$imm), 761 "cmp.b\t$imm, $dst", 762 [(MSP430cmp (load addr:$dst), (i8 cg8imm:$imm)), 763 (implicit SR)]>; 764def CMP16mc : I16mc<0b1001, 765 (outs), (ins memsrc:$dst, cg16imm:$imm), 766 "cmp\t$imm, $dst", 767 [(MSP430cmp (load addr:$dst), (i16 cg16imm:$imm)), 768 (implicit SR)]>; 769 770def CMP8mi : I8mi<0b1001, 771 (outs), (ins memsrc:$dst, i8imm:$imm), 772 "cmp.b\t$imm, $dst", 773 [(MSP430cmp (load addr:$dst), 774 (i8 imm:$imm)), (implicit SR)]>; 775def CMP16mi : I16mi<0b1001, 776 (outs), (ins memsrc:$dst, i16imm:$imm), 777 "cmp\t$imm, $dst", 778 [(MSP430cmp (load addr:$dst), 779 (i16 imm:$imm)), (implicit SR)]>; 780 781def CMP8rm : I8rm<0b1001, 782 (outs), (ins GR8:$rd, memsrc:$src), 783 "cmp.b\t$src, $rd", 784 [(MSP430cmp GR8:$rd, (load addr:$src)), 785 (implicit SR)]>; 786def CMP16rm : I16rm<0b1001, 787 (outs), (ins GR16:$rd, memsrc:$src), 788 "cmp\t$src, $rd", 789 [(MSP430cmp GR16:$rd, (load addr:$src)), 790 (implicit SR)]>; 791 792def CMP8rn : I8rn<0b1001, 793 (outs), (ins GR8:$rd, indreg:$rs), "cmp.b\t$rs, $rd", []>; 794def CMP16rn : I16rn<0b1001, 795 (outs), (ins GR16:$rd, indreg:$rs), "cmp\t$rs, $rd", []>; 796 797def CMP8rp : I8rp<0b1001, 798 (outs), (ins GR8:$rd, postreg:$rs), "cmp.b\t$rs, $rd", []>; 799def CMP16rp : I16rp<0b1001, 800 (outs), (ins GR16:$rd, postreg:$rs), "cmp\t$rs, $rd", []>; 801 802def CMP8mr : I8mr<0b1001, 803 (outs), (ins memsrc:$dst, GR8:$rs), 804 "cmp.b\t$rs, $dst", 805 [(MSP430cmp (load addr:$dst), GR8:$rs), 806 (implicit SR)]>; 807def CMP16mr : I16mr<0b1001, 808 (outs), (ins memsrc:$dst, GR16:$rs), 809 "cmp\t$rs, $dst", 810 [(MSP430cmp (load addr:$dst), GR16:$rs), 811 (implicit SR)]>; 812def CMP8mm : I8mm<0b1001, 813 (outs), (ins memdst:$dst, memsrc:$src), 814 "cmp.b\t$src, $dst", 815 [(MSP430cmp (load addr:$dst), (i8 (load addr:$src))), 816 (implicit SR)]>; 817def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src), 818 "cmp\t$src, $dst", 819 [(MSP430cmp (load addr:$dst), (i16 (load addr:$src))), 820 (implicit SR)]>; 821 822def CMP8mn : I8mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs), 823 "cmp.b\t$rs, $dst", []>; 824def CMP16mn : I16mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs), 825 "cmp\t$rs, $dst", []>; 826 827def CMP8mp : I8mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs), 828 "cmp.b\t$rs, $dst", []>; 829def CMP16mp : I16mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs), 830 "cmp\t$rs, $dst", []>; 831 832// BIT TESTS, just sets condition codes 833// Note that the C condition is set differently than when using CMP. 834let isCommutable = 1 in { 835def BIT8rr : I8rr<0b1011, 836 (outs), (ins GR8:$rd, GR8:$rs), 837 "bit.b\t$rs, $rd", 838 [(MSP430cmp (and_su GR8:$rd, GR8:$rs), 0), 839 (implicit SR)]>; 840def BIT16rr : I16rr<0b1011, 841 (outs), (ins GR16:$rd, GR16:$rs), 842 "bit\t$rs, $rd", 843 [(MSP430cmp (and_su GR16:$rd, GR16:$rs), 0), 844 (implicit SR)]>; 845} 846def BIT8rc : I8rc<0b1011, 847 (outs), (ins GR8:$rd, cg8imm:$imm), 848 "bit.b\t$imm, $rd", 849 [(MSP430cmp (and_su GR8:$rd, cg8imm:$imm), 0), 850 (implicit SR)]>; 851def BIT16rc : I16rc<0b1011, 852 (outs), (ins GR16:$rd, cg16imm:$imm), 853 "bit\t$imm, $rd", 854 [(MSP430cmp (and_su GR16:$rd, cg16imm:$imm), 0), 855 (implicit SR)]>; 856 857def BIT8ri : I8ri<0b1011, 858 (outs), (ins GR8:$rd, i8imm:$imm), 859 "bit.b\t$imm, $rd", 860 [(MSP430cmp (and_su GR8:$rd, imm:$imm), 0), 861 (implicit SR)]>; 862def BIT16ri : I16ri<0b1011, 863 (outs), (ins GR16:$rd, i16imm:$imm), 864 "bit\t$imm, $rd", 865 [(MSP430cmp (and_su GR16:$rd, imm:$imm), 0), 866 (implicit SR)]>; 867 868def BIT8rm : I8rm<0b1011, 869 (outs), (ins GR8:$rd, memdst:$src), 870 "bit.b\t$src, $rd", 871 [(MSP430cmp (and_su GR8:$rd, (load addr:$src)), 0), 872 (implicit SR)]>; 873def BIT16rm : I16rm<0b1011, 874 (outs), (ins GR16:$rd, memdst:$src), 875 "bit\t$src, $rd", 876 [(MSP430cmp (and_su GR16:$rd, (load addr:$src)), 0), 877 (implicit SR)]>; 878 879def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs), 880 "bit.b\t$rs, $rd", []>; 881def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs), 882 "bit\t$rs, $rd", []>; 883 884def BIT8rp : I8rp<0b1011, (outs), (ins GR8:$rd, postreg:$rs), 885 "bit.b\t$rs, $rd", []>; 886def BIT16rp : I16rp<0b1011, (outs), (ins GR16:$rd, postreg:$rs), 887 "bit\t$rs, $rd", []>; 888 889def BIT8mr : I8mr<0b1011, 890 (outs), (ins memsrc:$dst, GR8:$rs), 891 "bit.b\t$rs, $dst", 892 [(MSP430cmp (and_su (load addr:$dst), GR8:$rs), 0), 893 (implicit SR)]>; 894def BIT16mr : I16mr<0b1011, 895 (outs), (ins memsrc:$dst, GR16:$rs), 896 "bit\t$rs, $dst", 897 [(MSP430cmp (and_su (load addr:$dst), GR16:$rs), 0), 898 (implicit SR)]>; 899 900def BIT8mc : I8mc<0b1011, 901 (outs), (ins memsrc:$dst, cg8imm:$imm), 902 "bit.b\t$imm, $dst", 903 [(MSP430cmp (and_su (load addr:$dst), (i8 cg8imm:$imm)), 0), 904 (implicit SR)]>; 905def BIT16mc : I16mc<0b1011, 906 (outs), (ins memdst:$dst, cg16imm:$imm), 907 "bit\t$imm, $dst", 908 [(MSP430cmp (and_su (load addr:$dst), (i16 cg16imm:$imm)), 0), 909 (implicit SR)]>; 910 911def BIT8mi : I8mi<0b1011, 912 (outs), (ins memsrc:$dst, i8imm:$imm), 913 "bit.b\t$imm, $dst", 914 [(MSP430cmp (and_su (load addr:$dst), (i8 imm:$imm)), 0), 915 (implicit SR)]>; 916def BIT16mi : I16mi<0b1011, 917 (outs), (ins memsrc:$dst, i16imm:$imm), 918 "bit\t$imm, $dst", 919 [(MSP430cmp (and_su (load addr:$dst), (i16 imm:$imm)), 0), 920 (implicit SR)]>; 921 922def BIT8mm : I8mm<0b1011, 923 (outs), (ins memsrc:$dst, memsrc:$src), 924 "bit.b\t$src, $dst", 925 [(MSP430cmp (and_su (i8 (load addr:$dst)), 926 (load addr:$src)), 927 0), 928 (implicit SR)]>; 929def BIT16mm : I16mm<0b1011, 930 (outs), (ins memsrc:$dst, memsrc:$src), 931 "bit\t$src, $dst", 932 [(MSP430cmp (and_su (i16 (load addr:$dst)), 933 (load addr:$src)), 934 0), 935 (implicit SR)]>; 936def BIT8mn : I8mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs), 937 "bit.b\t$rs, $dst", []>; 938def BIT16mn : I16mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs), 939 "bit\t$rs, $dst", []>; 940 941def BIT8mp : I8mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs), 942 "bit.b\t$rs, $dst", []>; 943def BIT16mp : I16mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs), 944 "bit\t$rs, $dst", []>; 945 946} // Defs = [SR] 947 948def TST8r : InstAlias<"tst.b\t$dst", (CMP8rc GR8:$dst, 0)>; 949def TST16r : InstAlias<"tst\t$dst", (CMP16rc GR16:$dst, 0)>; 950def TST8m : InstAlias<"tst.b\t$dst", (CMP8mc memdst:$dst, 0)>; 951def TST16m : InstAlias<"tst\t$dst", (CMP16mc memdst:$dst, 0)>; 952 953//===----------------------------------------------------------------------===// 954// Non-Instruction Patterns 955 956// extload 957def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 958 959// anyext 960def : Pat<(i16 (anyext GR8:$src)), 961 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; 962 963// truncs 964def : Pat<(i8 (trunc GR16:$src)), 965 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>; 966 967// GlobalAddress, ExternalSymbol 968def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>; 969def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>; 970def : Pat<(i16 (MSP430Wrapper tblockaddress:$dst)), (MOV16ri tblockaddress:$dst)>; 971 972def : Pat<(add GR16:$src, (MSP430Wrapper tglobaladdr :$src2)), 973 (ADD16ri GR16:$src, tglobaladdr:$src2)>; 974def : Pat<(add GR16:$src, (MSP430Wrapper texternalsym:$src2)), 975 (ADD16ri GR16:$src, texternalsym:$src2)>; 976def : Pat<(add GR16:$src, (MSP430Wrapper tblockaddress:$src2)), 977 (ADD16ri GR16:$src, tblockaddress:$src2)>; 978 979def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst), 980 (MOV16mi addr:$dst, tglobaladdr:$src)>; 981def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst), 982 (MOV16mi addr:$dst, texternalsym:$src)>; 983def : Pat<(store (i16 (MSP430Wrapper tblockaddress:$src)), addr:$dst), 984 (MOV16mi addr:$dst, tblockaddress:$src)>; 985 986// calls 987def : Pat<(MSP430call (i16 tglobaladdr:$dst)), 988 (CALLi tglobaladdr:$dst)>; 989def : Pat<(MSP430call (i16 texternalsym:$dst)), 990 (CALLi texternalsym:$dst)>; 991 992// add and sub always produce carry 993def : Pat<(addc GR16:$src, GR16:$src2), 994 (ADD16rr GR16:$src, GR16:$src2)>; 995def : Pat<(addc GR16:$src, (load addr:$src2)), 996 (ADD16rm GR16:$src, addr:$src2)>; 997def : Pat<(addc GR16:$src, imm:$src2), 998 (ADD16ri GR16:$src, imm:$src2)>; 999def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst), 1000 (ADD16mr addr:$dst, GR16:$src)>; 1001def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), 1002 (ADD16mm addr:$dst, addr:$src)>; 1003 1004def : Pat<(addc GR8:$src, GR8:$src2), 1005 (ADD8rr GR8:$src, GR8:$src2)>; 1006def : Pat<(addc GR8:$src, (load addr:$src2)), 1007 (ADD8rm GR8:$src, addr:$src2)>; 1008def : Pat<(addc GR8:$src, imm:$src2), 1009 (ADD8ri GR8:$src, imm:$src2)>; 1010def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst), 1011 (ADD8mr addr:$dst, GR8:$src)>; 1012def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), 1013 (ADD8mm addr:$dst, addr:$src)>; 1014 1015def : Pat<(subc GR16:$src, GR16:$src2), 1016 (SUB16rr GR16:$src, GR16:$src2)>; 1017def : Pat<(subc GR16:$src, (load addr:$src2)), 1018 (SUB16rm GR16:$src, addr:$src2)>; 1019def : Pat<(subc GR16:$src, imm:$src2), 1020 (SUB16ri GR16:$src, imm:$src2)>; 1021def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst), 1022 (SUB16mr addr:$dst, GR16:$src)>; 1023def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), 1024 (SUB16mm addr:$dst, addr:$src)>; 1025 1026def : Pat<(subc GR8:$src, GR8:$src2), 1027 (SUB8rr GR8:$src, GR8:$src2)>; 1028def : Pat<(subc GR8:$src, (load addr:$src2)), 1029 (SUB8rm GR8:$src, addr:$src2)>; 1030def : Pat<(subc GR8:$src, imm:$src2), 1031 (SUB8ri GR8:$src, imm:$src2)>; 1032def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst), 1033 (SUB8mr addr:$dst, GR8:$src)>; 1034def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), 1035 (SUB8mm addr:$dst, addr:$src)>; 1036 1037// peephole patterns 1038def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>; 1039def : Pat<(MSP430cmp (trunc (and_su GR16:$src, GR16:$src2)), 0), 1040 (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit), 1041 (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>; 1042