xref: /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp (revision 4d3fc8b0570b29fb0d6ee9525f104d52176ff0d4)
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the MSP430TargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MSP430ISelLowering.h"
14 #include "MSP430.h"
15 #include "MSP430MachineFunctionInfo.h"
16 #include "MSP430Subtarget.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalAlias.h"
29 #include "llvm/IR/GlobalVariable.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "msp430-lower"
38 
39 static cl::opt<bool>MSP430NoLegalImmediate(
40   "msp430-no-legal-immediate", cl::Hidden,
41   cl::desc("Enable non legal immediates (for testing purposes only)"),
42   cl::init(false));
43 
44 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
45                                            const MSP430Subtarget &STI)
46     : TargetLowering(TM) {
47 
48   // Set up the register classes.
49   addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
50   addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
51 
52   // Compute derived properties from the register classes
53   computeRegisterProperties(STI.getRegisterInfo());
54 
55   // Provide all sorts of operation actions
56   setStackPointerRegisterToSaveRestore(MSP430::SP);
57   setBooleanContents(ZeroOrOneBooleanContent);
58   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
59 
60   // We have post-incremented loads / stores.
61   setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
62   setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
63 
64   for (MVT VT : MVT::integer_valuetypes()) {
65     setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
66     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
67     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
68     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8,  Expand);
69     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
70   }
71 
72   // We don't have any truncstores
73   setTruncStoreAction(MVT::i16, MVT::i8, Expand);
74 
75   setOperationAction(ISD::SRA,              MVT::i8,    Custom);
76   setOperationAction(ISD::SHL,              MVT::i8,    Custom);
77   setOperationAction(ISD::SRL,              MVT::i8,    Custom);
78   setOperationAction(ISD::SRA,              MVT::i16,   Custom);
79   setOperationAction(ISD::SHL,              MVT::i16,   Custom);
80   setOperationAction(ISD::SRL,              MVT::i16,   Custom);
81   setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
82   setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
83   setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
84   setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
85   setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
86   setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
87   setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
88   setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
89   setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
90   setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
91   setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
92   setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
93   setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
94   setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
95   setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
96   setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
97   setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
98   setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
99   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
100   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
101   setOperationAction(ISD::STACKSAVE,        MVT::Other, Expand);
102   setOperationAction(ISD::STACKRESTORE,     MVT::Other, Expand);
103 
104   setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
105   setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
106   setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
107   setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
108   setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
109   setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
110 
111   setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
112   setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
113   setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
114   setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
115   setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
116   setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
117 
118   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
119 
120   // FIXME: Implement efficiently multiplication by a constant
121   setOperationAction(ISD::MUL,              MVT::i8,    Promote);
122   setOperationAction(ISD::MULHS,            MVT::i8,    Promote);
123   setOperationAction(ISD::MULHU,            MVT::i8,    Promote);
124   setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Promote);
125   setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Promote);
126   setOperationAction(ISD::MUL,              MVT::i16,   LibCall);
127   setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
128   setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
129   setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
130   setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
131 
132   setOperationAction(ISD::UDIV,             MVT::i8,    Promote);
133   setOperationAction(ISD::UDIVREM,          MVT::i8,    Promote);
134   setOperationAction(ISD::UREM,             MVT::i8,    Promote);
135   setOperationAction(ISD::SDIV,             MVT::i8,    Promote);
136   setOperationAction(ISD::SDIVREM,          MVT::i8,    Promote);
137   setOperationAction(ISD::SREM,             MVT::i8,    Promote);
138   setOperationAction(ISD::UDIV,             MVT::i16,   LibCall);
139   setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
140   setOperationAction(ISD::UREM,             MVT::i16,   LibCall);
141   setOperationAction(ISD::SDIV,             MVT::i16,   LibCall);
142   setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
143   setOperationAction(ISD::SREM,             MVT::i16,   LibCall);
144 
145   // varargs support
146   setOperationAction(ISD::VASTART,          MVT::Other, Custom);
147   setOperationAction(ISD::VAARG,            MVT::Other, Expand);
148   setOperationAction(ISD::VAEND,            MVT::Other, Expand);
149   setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
150   setOperationAction(ISD::JumpTable,        MVT::i16,   Custom);
151 
152   // EABI Libcalls - EABI Section 6.2
153   const struct {
154     const RTLIB::Libcall Op;
155     const char * const Name;
156     const ISD::CondCode Cond;
157   } LibraryCalls[] = {
158     // Floating point conversions - EABI Table 6
159     { RTLIB::FPROUND_F64_F32,   "__mspabi_cvtdf",   ISD::SETCC_INVALID },
160     { RTLIB::FPEXT_F32_F64,     "__mspabi_cvtfd",   ISD::SETCC_INVALID },
161     // The following is NOT implemented in libgcc
162     //{ RTLIB::FPTOSINT_F64_I16,  "__mspabi_fixdi", ISD::SETCC_INVALID },
163     { RTLIB::FPTOSINT_F64_I32,  "__mspabi_fixdli",  ISD::SETCC_INVALID },
164     { RTLIB::FPTOSINT_F64_I64,  "__mspabi_fixdlli", ISD::SETCC_INVALID },
165     // The following is NOT implemented in libgcc
166     //{ RTLIB::FPTOUINT_F64_I16,  "__mspabi_fixdu", ISD::SETCC_INVALID },
167     { RTLIB::FPTOUINT_F64_I32,  "__mspabi_fixdul",  ISD::SETCC_INVALID },
168     { RTLIB::FPTOUINT_F64_I64,  "__mspabi_fixdull", ISD::SETCC_INVALID },
169     // The following is NOT implemented in libgcc
170     //{ RTLIB::FPTOSINT_F32_I16,  "__mspabi_fixfi", ISD::SETCC_INVALID },
171     { RTLIB::FPTOSINT_F32_I32,  "__mspabi_fixfli",  ISD::SETCC_INVALID },
172     { RTLIB::FPTOSINT_F32_I64,  "__mspabi_fixflli", ISD::SETCC_INVALID },
173     // The following is NOT implemented in libgcc
174     //{ RTLIB::FPTOUINT_F32_I16,  "__mspabi_fixfu", ISD::SETCC_INVALID },
175     { RTLIB::FPTOUINT_F32_I32,  "__mspabi_fixful",  ISD::SETCC_INVALID },
176     { RTLIB::FPTOUINT_F32_I64,  "__mspabi_fixfull", ISD::SETCC_INVALID },
177     // TODO The following IS implemented in libgcc
178     //{ RTLIB::SINTTOFP_I16_F64,  "__mspabi_fltid", ISD::SETCC_INVALID },
179     { RTLIB::SINTTOFP_I32_F64,  "__mspabi_fltlid",  ISD::SETCC_INVALID },
180     // TODO The following IS implemented in libgcc but is not in the EABI
181     { RTLIB::SINTTOFP_I64_F64,  "__mspabi_fltllid", ISD::SETCC_INVALID },
182     // TODO The following IS implemented in libgcc
183     //{ RTLIB::UINTTOFP_I16_F64,  "__mspabi_fltud", ISD::SETCC_INVALID },
184     { RTLIB::UINTTOFP_I32_F64,  "__mspabi_fltuld",  ISD::SETCC_INVALID },
185     // The following IS implemented in libgcc but is not in the EABI
186     { RTLIB::UINTTOFP_I64_F64,  "__mspabi_fltulld", ISD::SETCC_INVALID },
187     // TODO The following IS implemented in libgcc
188     //{ RTLIB::SINTTOFP_I16_F32,  "__mspabi_fltif", ISD::SETCC_INVALID },
189     { RTLIB::SINTTOFP_I32_F32,  "__mspabi_fltlif",  ISD::SETCC_INVALID },
190     // TODO The following IS implemented in libgcc but is not in the EABI
191     { RTLIB::SINTTOFP_I64_F32,  "__mspabi_fltllif", ISD::SETCC_INVALID },
192     // TODO The following IS implemented in libgcc
193     //{ RTLIB::UINTTOFP_I16_F32,  "__mspabi_fltuf", ISD::SETCC_INVALID },
194     { RTLIB::UINTTOFP_I32_F32,  "__mspabi_fltulf",  ISD::SETCC_INVALID },
195     // The following IS implemented in libgcc but is not in the EABI
196     { RTLIB::UINTTOFP_I64_F32,  "__mspabi_fltullf", ISD::SETCC_INVALID },
197 
198     // Floating point comparisons - EABI Table 7
199     { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
200     { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
201     { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
202     { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
203     { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
204     { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
205     { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
206     { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
207     { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
208     { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
209     { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
210     { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
211 
212     // Floating point arithmetic - EABI Table 8
213     { RTLIB::ADD_F64,  "__mspabi_addd", ISD::SETCC_INVALID },
214     { RTLIB::ADD_F32,  "__mspabi_addf", ISD::SETCC_INVALID },
215     { RTLIB::DIV_F64,  "__mspabi_divd", ISD::SETCC_INVALID },
216     { RTLIB::DIV_F32,  "__mspabi_divf", ISD::SETCC_INVALID },
217     { RTLIB::MUL_F64,  "__mspabi_mpyd", ISD::SETCC_INVALID },
218     { RTLIB::MUL_F32,  "__mspabi_mpyf", ISD::SETCC_INVALID },
219     { RTLIB::SUB_F64,  "__mspabi_subd", ISD::SETCC_INVALID },
220     { RTLIB::SUB_F32,  "__mspabi_subf", ISD::SETCC_INVALID },
221     // The following are NOT implemented in libgcc
222     // { RTLIB::NEG_F64,  "__mspabi_negd", ISD::SETCC_INVALID },
223     // { RTLIB::NEG_F32,  "__mspabi_negf", ISD::SETCC_INVALID },
224 
225     // Universal Integer Operations - EABI Table 9
226     { RTLIB::SDIV_I16,   "__mspabi_divi", ISD::SETCC_INVALID },
227     { RTLIB::SDIV_I32,   "__mspabi_divli", ISD::SETCC_INVALID },
228     { RTLIB::SDIV_I64,   "__mspabi_divlli", ISD::SETCC_INVALID },
229     { RTLIB::UDIV_I16,   "__mspabi_divu", ISD::SETCC_INVALID },
230     { RTLIB::UDIV_I32,   "__mspabi_divul", ISD::SETCC_INVALID },
231     { RTLIB::UDIV_I64,   "__mspabi_divull", ISD::SETCC_INVALID },
232     { RTLIB::SREM_I16,   "__mspabi_remi", ISD::SETCC_INVALID },
233     { RTLIB::SREM_I32,   "__mspabi_remli", ISD::SETCC_INVALID },
234     { RTLIB::SREM_I64,   "__mspabi_remlli", ISD::SETCC_INVALID },
235     { RTLIB::UREM_I16,   "__mspabi_remu", ISD::SETCC_INVALID },
236     { RTLIB::UREM_I32,   "__mspabi_remul", ISD::SETCC_INVALID },
237     { RTLIB::UREM_I64,   "__mspabi_remull", ISD::SETCC_INVALID },
238 
239     // Bitwise Operations - EABI Table 10
240     // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
241     { RTLIB::SRL_I32,    "__mspabi_srll", ISD::SETCC_INVALID },
242     { RTLIB::SRA_I32,    "__mspabi_sral", ISD::SETCC_INVALID },
243     { RTLIB::SHL_I32,    "__mspabi_slll", ISD::SETCC_INVALID },
244     // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
245 
246   };
247 
248   for (const auto &LC : LibraryCalls) {
249     setLibcallName(LC.Op, LC.Name);
250     if (LC.Cond != ISD::SETCC_INVALID)
251       setCmpLibcallCC(LC.Op, LC.Cond);
252   }
253 
254   if (STI.hasHWMult16()) {
255     const struct {
256       const RTLIB::Libcall Op;
257       const char * const Name;
258     } LibraryCalls[] = {
259       // Integer Multiply - EABI Table 9
260       { RTLIB::MUL_I16,   "__mspabi_mpyi_hw" },
261       { RTLIB::MUL_I32,   "__mspabi_mpyl_hw" },
262       { RTLIB::MUL_I64,   "__mspabi_mpyll_hw" },
263       // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
264       // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
265     };
266     for (const auto &LC : LibraryCalls) {
267       setLibcallName(LC.Op, LC.Name);
268     }
269   } else if (STI.hasHWMult32()) {
270     const struct {
271       const RTLIB::Libcall Op;
272       const char * const Name;
273     } LibraryCalls[] = {
274       // Integer Multiply - EABI Table 9
275       { RTLIB::MUL_I16,   "__mspabi_mpyi_hw" },
276       { RTLIB::MUL_I32,   "__mspabi_mpyl_hw32" },
277       { RTLIB::MUL_I64,   "__mspabi_mpyll_hw32" },
278       // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
279       // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
280     };
281     for (const auto &LC : LibraryCalls) {
282       setLibcallName(LC.Op, LC.Name);
283     }
284   } else if (STI.hasHWMultF5()) {
285     const struct {
286       const RTLIB::Libcall Op;
287       const char * const Name;
288     } LibraryCalls[] = {
289       // Integer Multiply - EABI Table 9
290       { RTLIB::MUL_I16,   "__mspabi_mpyi_f5hw" },
291       { RTLIB::MUL_I32,   "__mspabi_mpyl_f5hw" },
292       { RTLIB::MUL_I64,   "__mspabi_mpyll_f5hw" },
293       // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
294       // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
295     };
296     for (const auto &LC : LibraryCalls) {
297       setLibcallName(LC.Op, LC.Name);
298     }
299   } else { // NoHWMult
300     const struct {
301       const RTLIB::Libcall Op;
302       const char * const Name;
303     } LibraryCalls[] = {
304       // Integer Multiply - EABI Table 9
305       { RTLIB::MUL_I16,   "__mspabi_mpyi" },
306       { RTLIB::MUL_I32,   "__mspabi_mpyl" },
307       { RTLIB::MUL_I64,   "__mspabi_mpyll" },
308       // The __mspabi_mpysl* functions are NOT implemented in libgcc
309       // The __mspabi_mpyul* functions are NOT implemented in libgcc
310     };
311     for (const auto &LC : LibraryCalls) {
312       setLibcallName(LC.Op, LC.Name);
313     }
314     setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::MSP430_BUILTIN);
315   }
316 
317   // Several of the runtime library functions use a special calling conv
318   setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::MSP430_BUILTIN);
319   setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::MSP430_BUILTIN);
320   setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::MSP430_BUILTIN);
321   setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::MSP430_BUILTIN);
322   setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::MSP430_BUILTIN);
323   setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::MSP430_BUILTIN);
324   setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::MSP430_BUILTIN);
325   setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::MSP430_BUILTIN);
326   setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::MSP430_BUILTIN);
327   setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::MSP430_BUILTIN);
328   setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::MSP430_BUILTIN);
329   setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::MSP430_BUILTIN);
330   setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::MSP430_BUILTIN);
331   setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN);
332   // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
333 
334   setMinFunctionAlignment(Align(2));
335   setPrefFunctionAlignment(Align(2));
336 }
337 
338 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
339                                              SelectionDAG &DAG) const {
340   switch (Op.getOpcode()) {
341   case ISD::SHL: // FALLTHROUGH
342   case ISD::SRL:
343   case ISD::SRA:              return LowerShifts(Op, DAG);
344   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
345   case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
346   case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
347   case ISD::SETCC:            return LowerSETCC(Op, DAG);
348   case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
349   case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
350   case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
351   case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
352   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
353   case ISD::VASTART:          return LowerVASTART(Op, DAG);
354   case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
355   default:
356     llvm_unreachable("unimplemented operand");
357   }
358 }
359 
360 // Define non profitable transforms into shifts
361 bool MSP430TargetLowering::shouldAvoidTransformToShift(EVT VT,
362                                                        unsigned Amount) const {
363   return !(Amount == 8 || Amount == 9 || Amount<=2);
364 }
365 
366 // Implemented to verify test case assertions in
367 // tests/codegen/msp430/shift-amount-threshold-b.ll
368 bool MSP430TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
369   if (MSP430NoLegalImmediate)
370     return Immed >= -32 && Immed < 32;
371   return TargetLowering::isLegalICmpImmediate(Immed);
372 }
373 
374 //===----------------------------------------------------------------------===//
375 //                       MSP430 Inline Assembly Support
376 //===----------------------------------------------------------------------===//
377 
378 /// getConstraintType - Given a constraint letter, return the type of
379 /// constraint it is for this target.
380 TargetLowering::ConstraintType
381 MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
382   if (Constraint.size() == 1) {
383     switch (Constraint[0]) {
384     case 'r':
385       return C_RegisterClass;
386     default:
387       break;
388     }
389   }
390   return TargetLowering::getConstraintType(Constraint);
391 }
392 
393 std::pair<unsigned, const TargetRegisterClass *>
394 MSP430TargetLowering::getRegForInlineAsmConstraint(
395     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
396   if (Constraint.size() == 1) {
397     // GCC Constraint Letters
398     switch (Constraint[0]) {
399     default: break;
400     case 'r':   // GENERAL_REGS
401       if (VT == MVT::i8)
402         return std::make_pair(0U, &MSP430::GR8RegClass);
403 
404       return std::make_pair(0U, &MSP430::GR16RegClass);
405     }
406   }
407 
408   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
409 }
410 
411 //===----------------------------------------------------------------------===//
412 //                      Calling Convention Implementation
413 //===----------------------------------------------------------------------===//
414 
415 #include "MSP430GenCallingConv.inc"
416 
417 /// For each argument in a function store the number of pieces it is composed
418 /// of.
419 template<typename ArgT>
420 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
421                               SmallVectorImpl<unsigned> &Out) {
422   unsigned CurrentArgIndex;
423 
424   if (Args.empty())
425     return;
426 
427   CurrentArgIndex = Args[0].OrigArgIndex;
428   Out.push_back(0);
429 
430   for (auto &Arg : Args) {
431     if (CurrentArgIndex == Arg.OrigArgIndex) {
432       Out.back() += 1;
433     } else {
434       Out.push_back(1);
435       CurrentArgIndex = Arg.OrigArgIndex;
436     }
437   }
438 }
439 
440 static void AnalyzeVarArgs(CCState &State,
441                            const SmallVectorImpl<ISD::OutputArg> &Outs) {
442   State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
443 }
444 
445 static void AnalyzeVarArgs(CCState &State,
446                            const SmallVectorImpl<ISD::InputArg> &Ins) {
447   State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
448 }
449 
450 /// Analyze incoming and outgoing function arguments. We need custom C++ code
451 /// to handle special constraints in the ABI like reversing the order of the
452 /// pieces of splitted arguments. In addition, all pieces of a certain argument
453 /// have to be passed either using registers or the stack but never mixing both.
454 template<typename ArgT>
455 static void AnalyzeArguments(CCState &State,
456                              SmallVectorImpl<CCValAssign> &ArgLocs,
457                              const SmallVectorImpl<ArgT> &Args) {
458   static const MCPhysReg CRegList[] = {
459     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
460   };
461   static const unsigned CNbRegs = array_lengthof(CRegList);
462   static const MCPhysReg BuiltinRegList[] = {
463     MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
464     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
465   };
466   static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
467 
468   ArrayRef<MCPhysReg> RegList;
469   unsigned NbRegs;
470 
471   bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
472   if (Builtin) {
473     RegList = BuiltinRegList;
474     NbRegs = BuiltinNbRegs;
475   } else {
476     RegList = CRegList;
477     NbRegs = CNbRegs;
478   }
479 
480   if (State.isVarArg()) {
481     AnalyzeVarArgs(State, Args);
482     return;
483   }
484 
485   SmallVector<unsigned, 4> ArgsParts;
486   ParseFunctionArgs(Args, ArgsParts);
487 
488   if (Builtin) {
489     assert(ArgsParts.size() == 2 &&
490         "Builtin calling convention requires two arguments");
491   }
492 
493   unsigned RegsLeft = NbRegs;
494   bool UsedStack = false;
495   unsigned ValNo = 0;
496 
497   for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
498     MVT ArgVT = Args[ValNo].VT;
499     ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
500     MVT LocVT = ArgVT;
501     CCValAssign::LocInfo LocInfo = CCValAssign::Full;
502 
503     // Promote i8 to i16
504     if (LocVT == MVT::i8) {
505       LocVT = MVT::i16;
506       if (ArgFlags.isSExt())
507           LocInfo = CCValAssign::SExt;
508       else if (ArgFlags.isZExt())
509           LocInfo = CCValAssign::ZExt;
510       else
511           LocInfo = CCValAssign::AExt;
512     }
513 
514     // Handle byval arguments
515     if (ArgFlags.isByVal()) {
516       State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, Align(2), ArgFlags);
517       continue;
518     }
519 
520     unsigned Parts = ArgsParts[i];
521 
522     if (Builtin) {
523       assert(Parts == 4 &&
524           "Builtin calling convention requires 64-bit arguments");
525     }
526 
527     if (!UsedStack && Parts == 2 && RegsLeft == 1) {
528       // Special case for 32-bit register split, see EABI section 3.3.3
529       unsigned Reg = State.AllocateReg(RegList);
530       State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
531       RegsLeft -= 1;
532 
533       UsedStack = true;
534       CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
535     } else if (Parts <= RegsLeft) {
536       for (unsigned j = 0; j < Parts; j++) {
537         unsigned Reg = State.AllocateReg(RegList);
538         State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
539         RegsLeft--;
540       }
541     } else {
542       UsedStack = true;
543       for (unsigned j = 0; j < Parts; j++)
544         CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
545     }
546   }
547 }
548 
549 static void AnalyzeRetResult(CCState &State,
550                              const SmallVectorImpl<ISD::InputArg> &Ins) {
551   State.AnalyzeCallResult(Ins, RetCC_MSP430);
552 }
553 
554 static void AnalyzeRetResult(CCState &State,
555                              const SmallVectorImpl<ISD::OutputArg> &Outs) {
556   State.AnalyzeReturn(Outs, RetCC_MSP430);
557 }
558 
559 template<typename ArgT>
560 static void AnalyzeReturnValues(CCState &State,
561                                 SmallVectorImpl<CCValAssign> &RVLocs,
562                                 const SmallVectorImpl<ArgT> &Args) {
563   AnalyzeRetResult(State, Args);
564 }
565 
566 SDValue MSP430TargetLowering::LowerFormalArguments(
567     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
568     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
569     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
570 
571   switch (CallConv) {
572   default:
573     report_fatal_error("Unsupported calling convention");
574   case CallingConv::C:
575   case CallingConv::Fast:
576     return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
577   case CallingConv::MSP430_INTR:
578     if (Ins.empty())
579       return Chain;
580     report_fatal_error("ISRs cannot have arguments");
581   }
582 }
583 
584 SDValue
585 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
586                                 SmallVectorImpl<SDValue> &InVals) const {
587   SelectionDAG &DAG                     = CLI.DAG;
588   SDLoc &dl                             = CLI.DL;
589   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
590   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
591   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
592   SDValue Chain                         = CLI.Chain;
593   SDValue Callee                        = CLI.Callee;
594   bool &isTailCall                      = CLI.IsTailCall;
595   CallingConv::ID CallConv              = CLI.CallConv;
596   bool isVarArg                         = CLI.IsVarArg;
597 
598   // MSP430 target does not yet support tail call optimization.
599   isTailCall = false;
600 
601   switch (CallConv) {
602   default:
603     report_fatal_error("Unsupported calling convention");
604   case CallingConv::MSP430_BUILTIN:
605   case CallingConv::Fast:
606   case CallingConv::C:
607     return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
608                           Outs, OutVals, Ins, dl, DAG, InVals);
609   case CallingConv::MSP430_INTR:
610     report_fatal_error("ISRs cannot be called directly");
611   }
612 }
613 
614 /// LowerCCCArguments - transform physical registers into virtual registers and
615 /// generate load operations for arguments places on the stack.
616 // FIXME: struct return stuff
617 SDValue MSP430TargetLowering::LowerCCCArguments(
618     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
619     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
620     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
621   MachineFunction &MF = DAG.getMachineFunction();
622   MachineFrameInfo &MFI = MF.getFrameInfo();
623   MachineRegisterInfo &RegInfo = MF.getRegInfo();
624   MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
625 
626   // Assign locations to all of the incoming arguments.
627   SmallVector<CCValAssign, 16> ArgLocs;
628   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
629                  *DAG.getContext());
630   AnalyzeArguments(CCInfo, ArgLocs, Ins);
631 
632   // Create frame index for the start of the first vararg value
633   if (isVarArg) {
634     unsigned Offset = CCInfo.getNextStackOffset();
635     FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
636   }
637 
638   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
639     CCValAssign &VA = ArgLocs[i];
640     if (VA.isRegLoc()) {
641       // Arguments passed in registers
642       EVT RegVT = VA.getLocVT();
643       switch (RegVT.getSimpleVT().SimpleTy) {
644       default:
645         {
646 #ifndef NDEBUG
647           errs() << "LowerFormalArguments Unhandled argument type: "
648                << RegVT.getEVTString() << "\n";
649 #endif
650           llvm_unreachable(nullptr);
651         }
652       case MVT::i16:
653         Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
654         RegInfo.addLiveIn(VA.getLocReg(), VReg);
655         SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
656 
657         // If this is an 8-bit value, it is really passed promoted to 16
658         // bits. Insert an assert[sz]ext to capture this, then truncate to the
659         // right size.
660         if (VA.getLocInfo() == CCValAssign::SExt)
661           ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
662                                  DAG.getValueType(VA.getValVT()));
663         else if (VA.getLocInfo() == CCValAssign::ZExt)
664           ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
665                                  DAG.getValueType(VA.getValVT()));
666 
667         if (VA.getLocInfo() != CCValAssign::Full)
668           ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
669 
670         InVals.push_back(ArgValue);
671       }
672     } else {
673       // Only arguments passed on the stack should make it here.
674       assert(VA.isMemLoc());
675 
676       SDValue InVal;
677       ISD::ArgFlagsTy Flags = Ins[i].Flags;
678 
679       if (Flags.isByVal()) {
680         MVT PtrVT = VA.getLocVT();
681         int FI = MFI.CreateFixedObject(Flags.getByValSize(),
682                                        VA.getLocMemOffset(), true);
683         InVal = DAG.getFrameIndex(FI, PtrVT);
684       } else {
685         // Load the argument to a virtual register
686         unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
687         if (ObjSize > 2) {
688             errs() << "LowerFormalArguments Unhandled argument type: "
689                 << EVT(VA.getLocVT()).getEVTString()
690                 << "\n";
691         }
692         // Create the frame index object for this incoming parameter...
693         int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
694 
695         // Create the SelectionDAG nodes corresponding to a load
696         //from this parameter
697         SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
698         InVal = DAG.getLoad(
699             VA.getLocVT(), dl, Chain, FIN,
700             MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
701       }
702 
703       InVals.push_back(InVal);
704     }
705   }
706 
707   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
708     if (Ins[i].Flags.isSRet()) {
709       Register Reg = FuncInfo->getSRetReturnReg();
710       if (!Reg) {
711         Reg = MF.getRegInfo().createVirtualRegister(
712             getRegClassFor(MVT::i16));
713         FuncInfo->setSRetReturnReg(Reg);
714       }
715       SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
716       Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
717     }
718   }
719 
720   return Chain;
721 }
722 
723 bool
724 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
725                                      MachineFunction &MF,
726                                      bool IsVarArg,
727                                      const SmallVectorImpl<ISD::OutputArg> &Outs,
728                                      LLVMContext &Context) const {
729   SmallVector<CCValAssign, 16> RVLocs;
730   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
731   return CCInfo.CheckReturn(Outs, RetCC_MSP430);
732 }
733 
734 SDValue
735 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
736                                   bool isVarArg,
737                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
738                                   const SmallVectorImpl<SDValue> &OutVals,
739                                   const SDLoc &dl, SelectionDAG &DAG) const {
740 
741   MachineFunction &MF = DAG.getMachineFunction();
742 
743   // CCValAssign - represent the assignment of the return value to a location
744   SmallVector<CCValAssign, 16> RVLocs;
745 
746   // ISRs cannot return any value.
747   if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
748     report_fatal_error("ISRs cannot return any value");
749 
750   // CCState - Info about the registers and stack slot.
751   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
752                  *DAG.getContext());
753 
754   // Analize return values.
755   AnalyzeReturnValues(CCInfo, RVLocs, Outs);
756 
757   SDValue Flag;
758   SmallVector<SDValue, 4> RetOps(1, Chain);
759 
760   // Copy the result values into the output registers.
761   for (unsigned i = 0; i != RVLocs.size(); ++i) {
762     CCValAssign &VA = RVLocs[i];
763     assert(VA.isRegLoc() && "Can only return in registers!");
764 
765     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
766                              OutVals[i], Flag);
767 
768     // Guarantee that all emitted copies are stuck together,
769     // avoiding something bad.
770     Flag = Chain.getValue(1);
771     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
772   }
773 
774   if (MF.getFunction().hasStructRetAttr()) {
775     MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
776     Register Reg = FuncInfo->getSRetReturnReg();
777 
778     if (!Reg)
779       llvm_unreachable("sret virtual register not created in entry block");
780 
781     MVT PtrVT = getFrameIndexTy(DAG.getDataLayout());
782     SDValue Val =
783       DAG.getCopyFromReg(Chain, dl, Reg, PtrVT);
784     unsigned R12 = MSP430::R12;
785 
786     Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
787     Flag = Chain.getValue(1);
788     RetOps.push_back(DAG.getRegister(R12, PtrVT));
789   }
790 
791   unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
792                   MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
793 
794   RetOps[0] = Chain;  // Update chain.
795 
796   // Add the flag if we have it.
797   if (Flag.getNode())
798     RetOps.push_back(Flag);
799 
800   return DAG.getNode(Opc, dl, MVT::Other, RetOps);
801 }
802 
803 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
804 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
805 SDValue MSP430TargetLowering::LowerCCCCallTo(
806     SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
807     bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
808     const SmallVectorImpl<SDValue> &OutVals,
809     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
810     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
811   // Analyze operands of the call, assigning locations to each operand.
812   SmallVector<CCValAssign, 16> ArgLocs;
813   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
814                  *DAG.getContext());
815   AnalyzeArguments(CCInfo, ArgLocs, Outs);
816 
817   // Get a count of how many bytes are to be pushed on the stack.
818   unsigned NumBytes = CCInfo.getNextStackOffset();
819   MVT PtrVT = getFrameIndexTy(DAG.getDataLayout());
820 
821   Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
822 
823   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
824   SmallVector<SDValue, 12> MemOpChains;
825   SDValue StackPtr;
826 
827   // Walk the register/memloc assignments, inserting copies/loads.
828   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
829     CCValAssign &VA = ArgLocs[i];
830 
831     SDValue Arg = OutVals[i];
832 
833     // Promote the value if needed.
834     switch (VA.getLocInfo()) {
835       default: llvm_unreachable("Unknown loc info!");
836       case CCValAssign::Full: break;
837       case CCValAssign::SExt:
838         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
839         break;
840       case CCValAssign::ZExt:
841         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
842         break;
843       case CCValAssign::AExt:
844         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
845         break;
846     }
847 
848     // Arguments that can be passed on register must be kept at RegsToPass
849     // vector
850     if (VA.isRegLoc()) {
851       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
852     } else {
853       assert(VA.isMemLoc());
854 
855       if (!StackPtr.getNode())
856         StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
857 
858       SDValue PtrOff =
859           DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
860                       DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
861 
862       SDValue MemOp;
863       ISD::ArgFlagsTy Flags = Outs[i].Flags;
864 
865       if (Flags.isByVal()) {
866         SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
867         MemOp = DAG.getMemcpy(
868             Chain, dl, PtrOff, Arg, SizeNode, Flags.getNonZeroByValAlign(),
869             /*isVolatile*/ false,
870             /*AlwaysInline=*/true,
871             /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
872       } else {
873         MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
874       }
875 
876       MemOpChains.push_back(MemOp);
877     }
878   }
879 
880   // Transform all store nodes into one single node because all store nodes are
881   // independent of each other.
882   if (!MemOpChains.empty())
883     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
884 
885   // Build a sequence of copy-to-reg nodes chained together with token chain and
886   // flag operands which copy the outgoing args into registers.  The InFlag in
887   // necessary since all emitted instructions must be stuck together.
888   SDValue InFlag;
889   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
890     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
891                              RegsToPass[i].second, InFlag);
892     InFlag = Chain.getValue(1);
893   }
894 
895   // If the callee is a GlobalAddress node (quite common, every direct call is)
896   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
897   // Likewise ExternalSymbol -> TargetExternalSymbol.
898   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
899     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
900   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
901     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
902 
903   // Returns a chain & a flag for retval copy to use.
904   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
905   SmallVector<SDValue, 8> Ops;
906   Ops.push_back(Chain);
907   Ops.push_back(Callee);
908 
909   // Add argument registers to the end of the list so that they are
910   // known live into the call.
911   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
912     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
913                                   RegsToPass[i].second.getValueType()));
914 
915   if (InFlag.getNode())
916     Ops.push_back(InFlag);
917 
918   Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
919   InFlag = Chain.getValue(1);
920 
921   // Create the CALLSEQ_END node.
922   Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
923                              DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
924   InFlag = Chain.getValue(1);
925 
926   // Handle result values, copying them out of physregs into vregs that we
927   // return.
928   return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
929                          DAG, InVals);
930 }
931 
932 /// LowerCallResult - Lower the result values of a call into the
933 /// appropriate copies out of appropriate physical registers.
934 ///
935 SDValue MSP430TargetLowering::LowerCallResult(
936     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
937     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
938     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
939 
940   // Assign locations to each value returned by this call.
941   SmallVector<CCValAssign, 16> RVLocs;
942   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
943                  *DAG.getContext());
944 
945   AnalyzeReturnValues(CCInfo, RVLocs, Ins);
946 
947   // Copy all of the result registers out of their specified physreg.
948   for (unsigned i = 0; i != RVLocs.size(); ++i) {
949     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
950                                RVLocs[i].getValVT(), InFlag).getValue(1);
951     InFlag = Chain.getValue(2);
952     InVals.push_back(Chain.getValue(0));
953   }
954 
955   return Chain;
956 }
957 
958 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
959                                           SelectionDAG &DAG) const {
960   unsigned Opc = Op.getOpcode();
961   SDNode* N = Op.getNode();
962   EVT VT = Op.getValueType();
963   SDLoc dl(N);
964 
965   // Expand non-constant shifts to loops:
966   if (!isa<ConstantSDNode>(N->getOperand(1)))
967     return Op;
968 
969   uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
970 
971   // Expand the stuff into sequence of shifts.
972   SDValue Victim = N->getOperand(0);
973 
974   if (ShiftAmount >= 8) {
975     assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
976     switch(Opc) {
977     default:
978       llvm_unreachable("Unknown shift");
979     case ISD::SHL:
980       // foo << (8 + N) => swpb(zext(foo)) << N
981       Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
982       Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
983       break;
984     case ISD::SRA:
985     case ISD::SRL:
986       // foo >> (8 + N) => sxt(swpb(foo)) >> N
987       Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
988       Victim = (Opc == ISD::SRA)
989                    ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
990                                  DAG.getValueType(MVT::i8))
991                    : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
992       break;
993     }
994     ShiftAmount -= 8;
995   }
996 
997   if (Opc == ISD::SRL && ShiftAmount) {
998     // Emit a special goodness here:
999     // srl A, 1 => clrc; rrc A
1000     Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
1001     ShiftAmount -= 1;
1002   }
1003 
1004   while (ShiftAmount--)
1005     Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
1006                          dl, VT, Victim);
1007 
1008   return Victim;
1009 }
1010 
1011 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
1012                                                  SelectionDAG &DAG) const {
1013   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1014   int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1015   EVT PtrVT = Op.getValueType();
1016 
1017   // Create the TargetGlobalAddress node, folding in the constant offset.
1018   SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1019   return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1020 }
1021 
1022 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
1023                                                   SelectionDAG &DAG) const {
1024   SDLoc dl(Op);
1025   const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1026   EVT PtrVT = Op.getValueType();
1027   SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1028 
1029   return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1030 }
1031 
1032 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
1033                                                 SelectionDAG &DAG) const {
1034   SDLoc dl(Op);
1035   const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1036   EVT PtrVT = Op.getValueType();
1037   SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1038 
1039   return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1040 }
1041 
1042 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1043                        ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1044   // FIXME: Handle bittests someday
1045   assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1046 
1047   // FIXME: Handle jump negative someday
1048   MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
1049   switch (CC) {
1050   default: llvm_unreachable("Invalid integer condition!");
1051   case ISD::SETEQ:
1052     TCC = MSP430CC::COND_E;     // aka COND_Z
1053     // Minor optimization: if LHS is a constant, swap operands, then the
1054     // constant can be folded into comparison.
1055     if (LHS.getOpcode() == ISD::Constant)
1056       std::swap(LHS, RHS);
1057     break;
1058   case ISD::SETNE:
1059     TCC = MSP430CC::COND_NE;    // aka COND_NZ
1060     // Minor optimization: if LHS is a constant, swap operands, then the
1061     // constant can be folded into comparison.
1062     if (LHS.getOpcode() == ISD::Constant)
1063       std::swap(LHS, RHS);
1064     break;
1065   case ISD::SETULE:
1066     std::swap(LHS, RHS);
1067     LLVM_FALLTHROUGH;
1068   case ISD::SETUGE:
1069     // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1070     // fold constant into instruction.
1071     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1072       LHS = RHS;
1073       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1074       TCC = MSP430CC::COND_LO;
1075       break;
1076     }
1077     TCC = MSP430CC::COND_HS;    // aka COND_C
1078     break;
1079   case ISD::SETUGT:
1080     std::swap(LHS, RHS);
1081     LLVM_FALLTHROUGH;
1082   case ISD::SETULT:
1083     // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1084     // fold constant into instruction.
1085     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1086       LHS = RHS;
1087       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1088       TCC = MSP430CC::COND_HS;
1089       break;
1090     }
1091     TCC = MSP430CC::COND_LO;    // aka COND_NC
1092     break;
1093   case ISD::SETLE:
1094     std::swap(LHS, RHS);
1095     LLVM_FALLTHROUGH;
1096   case ISD::SETGE:
1097     // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1098     // fold constant into instruction.
1099     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1100       LHS = RHS;
1101       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1102       TCC = MSP430CC::COND_L;
1103       break;
1104     }
1105     TCC = MSP430CC::COND_GE;
1106     break;
1107   case ISD::SETGT:
1108     std::swap(LHS, RHS);
1109     LLVM_FALLTHROUGH;
1110   case ISD::SETLT:
1111     // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1112     // fold constant into instruction.
1113     if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1114       LHS = RHS;
1115       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1116       TCC = MSP430CC::COND_GE;
1117       break;
1118     }
1119     TCC = MSP430CC::COND_L;
1120     break;
1121   }
1122 
1123   TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1124   return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1125 }
1126 
1127 
1128 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1129   SDValue Chain = Op.getOperand(0);
1130   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1131   SDValue LHS   = Op.getOperand(2);
1132   SDValue RHS   = Op.getOperand(3);
1133   SDValue Dest  = Op.getOperand(4);
1134   SDLoc dl  (Op);
1135 
1136   SDValue TargetCC;
1137   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1138 
1139   return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1140                      Chain, Dest, TargetCC, Flag);
1141 }
1142 
1143 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1144   SDValue LHS   = Op.getOperand(0);
1145   SDValue RHS   = Op.getOperand(1);
1146   SDLoc dl  (Op);
1147 
1148   // If we are doing an AND and testing against zero, then the CMP
1149   // will not be generated.  The AND (or BIT) will generate the condition codes,
1150   // but they are different from CMP.
1151   // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1152   // lowering & isel wouldn't diverge.
1153   bool andCC = false;
1154   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1155     if (RHSC->isZero() && LHS.hasOneUse() &&
1156         (LHS.getOpcode() == ISD::AND ||
1157          (LHS.getOpcode() == ISD::TRUNCATE &&
1158           LHS.getOperand(0).getOpcode() == ISD::AND))) {
1159       andCC = true;
1160     }
1161   }
1162   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1163   SDValue TargetCC;
1164   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1165 
1166   // Get the condition codes directly from the status register, if its easy.
1167   // Otherwise a branch will be generated.  Note that the AND and BIT
1168   // instructions generate different flags than CMP, the carry bit can be used
1169   // for NE/EQ.
1170   bool Invert = false;
1171   bool Shift = false;
1172   bool Convert = true;
1173   switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1174    default:
1175     Convert = false;
1176     break;
1177    case MSP430CC::COND_HS:
1178      // Res = SR & 1, no processing is required
1179      break;
1180    case MSP430CC::COND_LO:
1181      // Res = ~(SR & 1)
1182      Invert = true;
1183      break;
1184    case MSP430CC::COND_NE:
1185      if (andCC) {
1186        // C = ~Z, thus Res = SR & 1, no processing is required
1187      } else {
1188        // Res = ~((SR >> 1) & 1)
1189        Shift = true;
1190        Invert = true;
1191      }
1192      break;
1193    case MSP430CC::COND_E:
1194      Shift = true;
1195      // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1196      // Res = (SR >> 1) & 1 is 1 word shorter.
1197      break;
1198   }
1199   EVT VT = Op.getValueType();
1200   SDValue One  = DAG.getConstant(1, dl, VT);
1201   if (Convert) {
1202     SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1203                                     MVT::i16, Flag);
1204     if (Shift)
1205       // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1206       SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1207     SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1208     if (Invert)
1209       SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1210     return SR;
1211   } else {
1212     SDValue Zero = DAG.getConstant(0, dl, VT);
1213     SDValue Ops[] = {One, Zero, TargetCC, Flag};
1214     return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);
1215   }
1216 }
1217 
1218 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
1219                                              SelectionDAG &DAG) const {
1220   SDValue LHS    = Op.getOperand(0);
1221   SDValue RHS    = Op.getOperand(1);
1222   SDValue TrueV  = Op.getOperand(2);
1223   SDValue FalseV = Op.getOperand(3);
1224   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1225   SDLoc dl   (Op);
1226 
1227   SDValue TargetCC;
1228   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1229 
1230   SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1231 
1232   return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);
1233 }
1234 
1235 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1236                                                SelectionDAG &DAG) const {
1237   SDValue Val = Op.getOperand(0);
1238   EVT VT      = Op.getValueType();
1239   SDLoc dl(Op);
1240 
1241   assert(VT == MVT::i16 && "Only support i16 for now!");
1242 
1243   return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1244                      DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1245                      DAG.getValueType(Val.getValueType()));
1246 }
1247 
1248 SDValue
1249 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1250   MachineFunction &MF = DAG.getMachineFunction();
1251   MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1252   int ReturnAddrIndex = FuncInfo->getRAIndex();
1253   MVT PtrVT = getFrameIndexTy(MF.getDataLayout());
1254 
1255   if (ReturnAddrIndex == 0) {
1256     // Set up a frame object for the return address.
1257     uint64_t SlotSize = PtrVT.getStoreSize();
1258     ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1259                                                            true);
1260     FuncInfo->setRAIndex(ReturnAddrIndex);
1261   }
1262 
1263   return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1264 }
1265 
1266 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1267                                               SelectionDAG &DAG) const {
1268   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1269   MFI.setReturnAddressIsTaken(true);
1270 
1271   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1272     return SDValue();
1273 
1274   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1275   SDLoc dl(Op);
1276   EVT PtrVT = Op.getValueType();
1277 
1278   if (Depth > 0) {
1279     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1280     SDValue Offset =
1281       DAG.getConstant(PtrVT.getStoreSize(), dl, MVT::i16);
1282     return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1283                        DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1284                        MachinePointerInfo());
1285   }
1286 
1287   // Just load the return address.
1288   SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1289   return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1290                      MachinePointerInfo());
1291 }
1292 
1293 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1294                                              SelectionDAG &DAG) const {
1295   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1296   MFI.setFrameAddressIsTaken(true);
1297 
1298   EVT VT = Op.getValueType();
1299   SDLoc dl(Op);  // FIXME probably not meaningful
1300   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1301   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1302                                          MSP430::R4, VT);
1303   while (Depth--)
1304     FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1305                             MachinePointerInfo());
1306   return FrameAddr;
1307 }
1308 
1309 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1310                                            SelectionDAG &DAG) const {
1311   MachineFunction &MF = DAG.getMachineFunction();
1312   MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1313 
1314   SDValue Ptr = Op.getOperand(1);
1315   EVT PtrVT = Ptr.getValueType();
1316 
1317   // Frame index of first vararg argument
1318   SDValue FrameIndex =
1319       DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1320   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1321 
1322   // Create a store of the frame index to the location operand
1323   return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Ptr,
1324                       MachinePointerInfo(SV));
1325 }
1326 
1327 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1328                                              SelectionDAG &DAG) const {
1329     JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1330     EVT PtrVT = Op.getValueType();
1331     SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1332     return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1333 }
1334 
1335 /// getPostIndexedAddressParts - returns true by value, base pointer and
1336 /// offset pointer and addressing mode by reference if this node can be
1337 /// combined with a load / store to form a post-indexed load / store.
1338 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1339                                                       SDValue &Base,
1340                                                       SDValue &Offset,
1341                                                       ISD::MemIndexedMode &AM,
1342                                                       SelectionDAG &DAG) const {
1343 
1344   LoadSDNode *LD = cast<LoadSDNode>(N);
1345   if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1346     return false;
1347 
1348   EVT VT = LD->getMemoryVT();
1349   if (VT != MVT::i8 && VT != MVT::i16)
1350     return false;
1351 
1352   if (Op->getOpcode() != ISD::ADD)
1353     return false;
1354 
1355   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1356     uint64_t RHSC = RHS->getZExtValue();
1357     if ((VT == MVT::i16 && RHSC != 2) ||
1358         (VT == MVT::i8 && RHSC != 1))
1359       return false;
1360 
1361     Base = Op->getOperand(0);
1362     Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1363     AM = ISD::POST_INC;
1364     return true;
1365   }
1366 
1367   return false;
1368 }
1369 
1370 
1371 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1372   switch ((MSP430ISD::NodeType)Opcode) {
1373   case MSP430ISD::FIRST_NUMBER:       break;
1374   case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1375   case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1376   case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1377   case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1378   case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1379   case MSP430ISD::RRCL:               return "MSP430ISD::RRCL";
1380   case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1381   case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1382   case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1383   case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1384   case MSP430ISD::SETCC:              return "MSP430ISD::SETCC";
1385   case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1386   case MSP430ISD::DADD:               return "MSP430ISD::DADD";
1387   }
1388   return nullptr;
1389 }
1390 
1391 bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1392                                           Type *Ty2) const {
1393   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1394     return false;
1395 
1396   return (Ty1->getPrimitiveSizeInBits().getFixedSize() >
1397           Ty2->getPrimitiveSizeInBits().getFixedSize());
1398 }
1399 
1400 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1401   if (!VT1.isInteger() || !VT2.isInteger())
1402     return false;
1403 
1404   return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits());
1405 }
1406 
1407 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1408   // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1409   return false && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1410 }
1411 
1412 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1413   // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1414   return false && VT1 == MVT::i8 && VT2 == MVT::i16;
1415 }
1416 
1417 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1418   return isZExtFree(Val.getValueType(), VT2);
1419 }
1420 
1421 //===----------------------------------------------------------------------===//
1422 //  Other Lowering Code
1423 //===----------------------------------------------------------------------===//
1424 
1425 MachineBasicBlock *
1426 MSP430TargetLowering::EmitShiftInstr(MachineInstr &MI,
1427                                      MachineBasicBlock *BB) const {
1428   MachineFunction *F = BB->getParent();
1429   MachineRegisterInfo &RI = F->getRegInfo();
1430   DebugLoc dl = MI.getDebugLoc();
1431   const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1432 
1433   unsigned Opc;
1434   bool ClearCarry = false;
1435   const TargetRegisterClass * RC;
1436   switch (MI.getOpcode()) {
1437   default: llvm_unreachable("Invalid shift opcode!");
1438   case MSP430::Shl8:
1439     Opc = MSP430::ADD8rr;
1440     RC = &MSP430::GR8RegClass;
1441     break;
1442   case MSP430::Shl16:
1443     Opc = MSP430::ADD16rr;
1444     RC = &MSP430::GR16RegClass;
1445     break;
1446   case MSP430::Sra8:
1447     Opc = MSP430::RRA8r;
1448     RC = &MSP430::GR8RegClass;
1449     break;
1450   case MSP430::Sra16:
1451     Opc = MSP430::RRA16r;
1452     RC = &MSP430::GR16RegClass;
1453     break;
1454   case MSP430::Srl8:
1455     ClearCarry = true;
1456     Opc = MSP430::RRC8r;
1457     RC = &MSP430::GR8RegClass;
1458     break;
1459   case MSP430::Srl16:
1460     ClearCarry = true;
1461     Opc = MSP430::RRC16r;
1462     RC = &MSP430::GR16RegClass;
1463     break;
1464   case MSP430::Rrcl8:
1465   case MSP430::Rrcl16: {
1466     BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1467       .addReg(MSP430::SR).addImm(1);
1468     Register SrcReg = MI.getOperand(1).getReg();
1469     Register DstReg = MI.getOperand(0).getReg();
1470     unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1471                     ? MSP430::RRC16r : MSP430::RRC8r;
1472     BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1473       .addReg(SrcReg);
1474     MI.eraseFromParent(); // The pseudo instruction is gone now.
1475     return BB;
1476   }
1477   }
1478 
1479   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1480   MachineFunction::iterator I = ++BB->getIterator();
1481 
1482   // Create loop block
1483   MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1484   MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1485 
1486   F->insert(I, LoopBB);
1487   F->insert(I, RemBB);
1488 
1489   // Update machine-CFG edges by transferring all successors of the current
1490   // block to the block containing instructions after shift.
1491   RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1492                 BB->end());
1493   RemBB->transferSuccessorsAndUpdatePHIs(BB);
1494 
1495   // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1496   BB->addSuccessor(LoopBB);
1497   BB->addSuccessor(RemBB);
1498   LoopBB->addSuccessor(RemBB);
1499   LoopBB->addSuccessor(LoopBB);
1500 
1501   Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1502   Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1503   Register ShiftReg = RI.createVirtualRegister(RC);
1504   Register ShiftReg2 = RI.createVirtualRegister(RC);
1505   Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1506   Register SrcReg = MI.getOperand(1).getReg();
1507   Register DstReg = MI.getOperand(0).getReg();
1508 
1509   // BB:
1510   // cmp 0, N
1511   // je RemBB
1512   BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1513     .addReg(ShiftAmtSrcReg).addImm(0);
1514   BuildMI(BB, dl, TII.get(MSP430::JCC))
1515     .addMBB(RemBB)
1516     .addImm(MSP430CC::COND_E);
1517 
1518   // LoopBB:
1519   // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1520   // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1521   // ShiftReg2 = shift ShiftReg
1522   // ShiftAmt2 = ShiftAmt - 1;
1523   BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1524     .addReg(SrcReg).addMBB(BB)
1525     .addReg(ShiftReg2).addMBB(LoopBB);
1526   BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1527     .addReg(ShiftAmtSrcReg).addMBB(BB)
1528     .addReg(ShiftAmtReg2).addMBB(LoopBB);
1529   if (ClearCarry)
1530     BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1531       .addReg(MSP430::SR).addImm(1);
1532   if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1533     BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1534       .addReg(ShiftReg)
1535       .addReg(ShiftReg);
1536   else
1537     BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1538       .addReg(ShiftReg);
1539   BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1540     .addReg(ShiftAmtReg).addImm(1);
1541   BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1542     .addMBB(LoopBB)
1543     .addImm(MSP430CC::COND_NE);
1544 
1545   // RemBB:
1546   // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1547   BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1548     .addReg(SrcReg).addMBB(BB)
1549     .addReg(ShiftReg2).addMBB(LoopBB);
1550 
1551   MI.eraseFromParent(); // The pseudo instruction is gone now.
1552   return RemBB;
1553 }
1554 
1555 MachineBasicBlock *
1556 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1557                                                   MachineBasicBlock *BB) const {
1558   unsigned Opc = MI.getOpcode();
1559 
1560   if (Opc == MSP430::Shl8  || Opc == MSP430::Shl16 ||
1561       Opc == MSP430::Sra8  || Opc == MSP430::Sra16 ||
1562       Opc == MSP430::Srl8  || Opc == MSP430::Srl16 ||
1563       Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1564     return EmitShiftInstr(MI, BB);
1565 
1566   const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1567   DebugLoc dl = MI.getDebugLoc();
1568 
1569   assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1570          "Unexpected instr type to insert");
1571 
1572   // To "insert" a SELECT instruction, we actually have to insert the diamond
1573   // control-flow pattern.  The incoming instruction knows the destination vreg
1574   // to set, the condition code register to branch on, the true/false values to
1575   // select between, and a branch opcode to use.
1576   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1577   MachineFunction::iterator I = ++BB->getIterator();
1578 
1579   //  thisMBB:
1580   //  ...
1581   //   TrueVal = ...
1582   //   cmpTY ccX, r1, r2
1583   //   jCC copy1MBB
1584   //   fallthrough --> copy0MBB
1585   MachineBasicBlock *thisMBB = BB;
1586   MachineFunction *F = BB->getParent();
1587   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1588   MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1589   F->insert(I, copy0MBB);
1590   F->insert(I, copy1MBB);
1591   // Update machine-CFG edges by transferring all successors of the current
1592   // block to the new block which will contain the Phi node for the select.
1593   copy1MBB->splice(copy1MBB->begin(), BB,
1594                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
1595   copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1596   // Next, add the true and fallthrough blocks as its successors.
1597   BB->addSuccessor(copy0MBB);
1598   BB->addSuccessor(copy1MBB);
1599 
1600   BuildMI(BB, dl, TII.get(MSP430::JCC))
1601       .addMBB(copy1MBB)
1602       .addImm(MI.getOperand(3).getImm());
1603 
1604   //  copy0MBB:
1605   //   %FalseValue = ...
1606   //   # fallthrough to copy1MBB
1607   BB = copy0MBB;
1608 
1609   // Update machine-CFG edges
1610   BB->addSuccessor(copy1MBB);
1611 
1612   //  copy1MBB:
1613   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1614   //  ...
1615   BB = copy1MBB;
1616   BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1617       .addReg(MI.getOperand(2).getReg())
1618       .addMBB(copy0MBB)
1619       .addReg(MI.getOperand(1).getReg())
1620       .addMBB(thisMBB);
1621 
1622   MI.eraseFromParent(); // The pseudo instruction is gone now.
1623   return BB;
1624 }
1625