1//===-- M68kInstrArithmetic.td - Integer Arith Instrs ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// This file describes the integer arithmetic instructions in the M68k 11/// architecture. Here is the current status of the file: 12/// 13/// Machine: 14/// 15/// ADD [~] ADDA [~] ADDI [~] ADDQ [ ] ADDX [~] 16/// CLR [ ] CMP [~] CMPA [~] CMPI [~] CMPM [ ] 17/// CMP2 [ ] DIVS/DIVU [~] DIVSL/DIVUL [ ] EXT [~] EXTB [ ] 18/// MULS/MULU [~] NEG [~] NEGX [~] SUB [~] SUBA [~] 19/// SUBI [~] SUBQ [ ] SUBX [~] 20/// 21/// Map: 22/// 23/// [ ] - was not touched at all 24/// [!] - requires extarnal stuff implemented 25/// [~] - functional implementation 26/// [X] - complete implementation 27/// 28//===----------------------------------------------------------------------===// 29 30//===----------------------------------------------------------------------===// 31// OPMODE Encoding 32//===----------------------------------------------------------------------===// 33class MxOpModeEncoding<bits<3> encoding> { 34 bits<3> Value = encoding; 35} 36 37// op EA, Dn 38def MxOpMode8_d_EA : MxOpModeEncoding<0b000>; 39def MxOpMode16_d_EA : MxOpModeEncoding<0b001>; 40def MxOpMode32_d_EA : MxOpModeEncoding<0b010>; 41 42// op Dn, EA 43def MxOpMode8_EA_d : MxOpModeEncoding<0b100>; 44def MxOpMode16_EA_d : MxOpModeEncoding<0b101>; 45def MxOpMode32_EA_d : MxOpModeEncoding<0b110>; 46 47// op EA, An 48def MxOpMode16_a_EA : MxOpModeEncoding<0b011>; 49def MxOpMode32_a_EA : MxOpModeEncoding<0b111>; 50 51 52//===----------------------------------------------------------------------===// 53// Encoding 54//===----------------------------------------------------------------------===// 55 56let Defs = [CCR] in { 57let Constraints = "$src = $dst" in { 58 59/// Encoding for Normal forms 60/// ---------------------------------------------------- 61/// F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 62/// ---------------------------------------------------- 63/// | | | EFFECTIVE ADDRESS 64/// x x x x | REG | OP MODE | MODE | REG 65/// ---------------------------------------------------- 66 67// $reg, $ccr <- $reg op $reg 68class MxBiArOp_R_RR_xEA<string MN, SDNode NODE, MxType DST_TYPE, MxType SRC_TYPE, 69 bits<4> CMD> 70 : MxInst<(outs DST_TYPE.ROp:$dst), (ins DST_TYPE.ROp:$src, SRC_TYPE.ROp:$opd), 71 MN#"."#DST_TYPE.Prefix#"\t$opd, $dst", 72 [(set DST_TYPE.VT:$dst, CCR, (NODE DST_TYPE.VT:$src, SRC_TYPE.VT:$opd))]> { 73 let Inst = (descend 74 CMD, (operand "$dst", 3), 75 !cast<MxOpModeEncoding>("MxOpMode"#DST_TYPE.Size#"_"#DST_TYPE.RLet#"_EA").Value, 76 !cond( 77 !eq(SRC_TYPE.RLet, "r") : (descend 0b00, (operand "$opd", 4)), 78 !eq(SRC_TYPE.RLet, "d") : (descend 0b000, (operand "$opd", 3)) 79 ) 80 ); 81} 82 83/// This Op is similar to the one above except it uses reversed opmode, some 84/// commands(e.g. eor) do not support dEA or rEA modes and require EAd for 85/// register only operations. 86/// NOTE when using dd commands it is irrelevant which opmode to use(as it seems) 87/// but some opcodes support address register and some do not which creates this 88/// mess. 89class MxBiArOp_R_RR_EAd<string MN, SDNode NODE, MxType TYPE, bits<4> CMD> 90 : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd), 91 MN#"."#TYPE.Prefix#"\t$opd, $dst", 92 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))]> { 93 let Inst = (descend 94 CMD, (operand "$opd", 3), 95 !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_EA_"#TYPE.RLet).Value, 96 /*Destination can only be a data register*/ 97 /*MODE*/0b000, 98 /*REGISTER*/(operand "$dst", 3)); 99} 100 101let mayLoad = 1 in 102class MxBiArOp_R_RM<string MN, SDNode NODE, MxType TYPE, MxOperand OPD, ComplexPattern PAT, 103 bits<4> CMD, MxEncMemOp SRC_ENC> 104 : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, OPD:$opd), 105 MN#"."#TYPE.Prefix#"\t$opd, $dst", 106 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))]> { 107 let Inst = (ascend 108 (descend CMD, (operand "$dst", 3), 109 !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_"#TYPE.RLet#"_EA").Value, 110 SRC_ENC.EA), 111 SRC_ENC.Supplement 112 ); 113} 114 115/// Encoding for Immediate forms 116/// --------------------------------------------------- 117/// F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 118/// --------------------------------------------------- 119/// | | EFFECTIVE ADDRESS 120/// x x x x x x x x | SIZE | MODE | REG 121/// --------------------------------------------------- 122/// 16-BIT WORD DATA | 8-BIT BYTE DATA 123/// --------------------------------------------------- 124/// 32-BIT LONG DATA 125/// --------------------------------------------------- 126/// NOTE It is used to store an immediate to memory, imm-to-reg are handled with 127/// normal version 128 129// $reg <- $reg op $imm 130class MxBiArOp_R_RI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD> 131 : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd), 132 MN#"."#TYPE.Prefix#"\t$opd, $dst", 133 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> { 134 let Inst = (ascend 135 (descend CMD, (operand "$dst", 3), 136 !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_"#TYPE.RLet#"_EA").Value, 137 MxEncAddrMode_i<"opd", TYPE.Size>.EA), 138 MxEncAddrMode_i<"opd", TYPE.Size>.Supplement 139 ); 140} 141 142// Again, there are two ways to write an immediate to Dn register either dEA 143// opmode or using *I encoding, and again some instructions also support address 144// registers some do not. 145class MxBiArOp_R_RI<string MN, SDNode NODE, MxType TYPE, bits<4> CMD> 146 : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd), 147 MN#"i."#TYPE.Prefix#"\t$opd, $dst", 148 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> { 149 let Inst = (ascend 150 (descend 0b0000, CMD, 151 !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value, 152 // The destination cannot be address register, so it's always 153 // the MODE for data register direct mode. 154 /*MODE*/0b000, 155 /*REGISTER*/(operand "$dst", 3)), 156 // Source (i.e. immediate value) encoding 157 MxEncAddrMode_i<"opd", TYPE.Size>.Supplement 158 ); 159} 160} // Constraints 161 162let mayLoad = 1, mayStore = 1 in { 163 164// FIXME MxBiArOp_FMR/FMI cannot consume CCR from MxAdd/MxSub which leads for 165// MxAdd to survive the match and subsequent mismatch. 166class MxBiArOp_MR<string MN, MxType TYPE, 167 MxOperand MEMOpd, bits<4> CMD, MxEncMemOp DST_ENC> 168 : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$opd), 169 MN#"."#TYPE.Prefix#"\t$opd, $dst", []> { 170 let Inst = (ascend 171 (descend CMD, (operand "$opd", 3), 172 !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_EA_"#TYPE.RLet).Value, 173 DST_ENC.EA), 174 DST_ENC.Supplement 175 ); 176} 177 178class MxBiArOp_MI<string MN, MxType TYPE, 179 MxOperand MEMOpd, bits<4> CMD, MxEncMemOp DST_ENC> 180 : MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$opd), 181 MN#"."#TYPE.Prefix#"\t$opd, $dst", []> { 182 let Inst = (ascend 183 (descend 0b0000, CMD, 184 !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value, 185 DST_ENC.EA), 186 // Source (i.e. immediate value) encoding 187 MxEncAddrMode_i<"opd", TYPE.Size>.Supplement, 188 // Destination encoding 189 DST_ENC.Supplement 190 ); 191} 192} // mayLoad, mayStore 193} // Defs = [CCR] 194 195multiclass MxBiArOp_DF<string MN, SDNode NODE, bit isComm, 196 bits<4> CMD, bits<4> CMDI> { 197 198 foreach SZ = [8, 16, 32] in { 199 // op $mem, $reg 200 def NAME#SZ#"dk" : MxBiArOp_R_RM<MN, NODE, 201 !cast<MxType>("MxType"#SZ#"d"), 202 !cast<MxType>("MxType"#SZ).KOp, 203 !cast<MxType>("MxType"#SZ).KPat, 204 CMD, MxEncAddrMode_k<"opd">>; 205 206 def NAME#SZ#"dq" : MxBiArOp_R_RM<MN, NODE, 207 !cast<MxType>("MxType"#SZ#"d"), 208 !cast<MxType>("MxType"#SZ).QOp, 209 !cast<MxType>("MxType"#SZ).QPat, 210 CMD, MxEncAddrMode_q<"opd">>; 211 212 def NAME#SZ#"dp" : MxBiArOp_R_RM<MN, NODE, 213 !cast<MxType>("MxType"#SZ#"d"), 214 !cast<MxType>("MxType"#SZ).POp, 215 !cast<MxType>("MxType"#SZ).PPat, 216 CMD, MxEncAddrMode_p<"opd">>; 217 218 def NAME#SZ#"df" : MxBiArOp_R_RM<MN, NODE, 219 !cast<MxType>("MxType"#SZ#"d"), 220 !cast<MxType>("MxType"#SZ).FOp, 221 !cast<MxType>("MxType"#SZ).FPat, 222 CMD, MxEncAddrMode_f<"opd">>; 223 224 def NAME#SZ#"dj" : MxBiArOp_R_RM<MN, NODE, 225 !cast<MxType>("MxType"#SZ#"d"), 226 !cast<MxType>("MxType"#SZ).JOp, 227 !cast<MxType>("MxType"#SZ).JPat, 228 CMD, MxEncAddrMode_j<"opd">>; 229 // op $imm, $reg 230 def NAME#SZ#"di" : MxBiArOp_R_RI_xEA<MN, NODE, 231 !cast<MxType>("MxType"#SZ#"d"), 232 CMD>; 233 // op $reg, $mem 234 def NAME#SZ#"pd" : MxBiArOp_MR<MN, 235 !cast<MxType>("MxType"#SZ#"d"), 236 !cast<MxType>("MxType"#SZ).POp, 237 CMD, MxEncAddrMode_p<"dst">>; 238 239 def NAME#SZ#"fd" : MxBiArOp_MR<MN, 240 !cast<MxType>("MxType"#SZ#"d"), 241 !cast<MxType>("MxType"#SZ).FOp, 242 CMD, MxEncAddrMode_f<"dst">>; 243 244 def NAME#SZ#"jd" : MxBiArOp_MR<MN, 245 !cast<MxType>("MxType"#SZ#"d"), 246 !cast<MxType>("MxType"#SZ).JOp, 247 CMD, MxEncAddrMode_j<"dst">>; 248 // op $imm, $mem 249 def NAME#SZ#"pi" : MxBiArOp_MI<MN, 250 !cast<MxType>("MxType"#SZ), 251 !cast<MxType>("MxType"#SZ).POp, 252 CMDI, MxEncAddrMode_p<"dst">>; 253 254 def NAME#SZ#"fi" : MxBiArOp_MI<MN, 255 !cast<MxType>("MxType"#SZ), 256 !cast<MxType>("MxType"#SZ).FOp, 257 CMDI, MxEncAddrMode_f<"dst">>; 258 259 def NAME#SZ#"ji" : MxBiArOp_MI<MN, 260 !cast<MxType>("MxType"#SZ), 261 !cast<MxType>("MxType"#SZ).JOp, 262 CMDI, MxEncAddrMode_j<"dst">>; 263 // op $reg, $reg 264 let isCommutable = isComm in 265 def NAME#SZ#"dd" : MxBiArOp_R_RR_xEA<MN, NODE, 266 !cast<MxType>("MxType"#SZ#"d"), 267 !cast<MxType>("MxType"#SZ#"d"), 268 CMD>; 269 } // foreach SZ 270 271 foreach SZ = [16, 32] in 272 def NAME#SZ#"dr" : MxBiArOp_R_RR_xEA<MN, NODE, 273 !cast<MxType>("MxType"#SZ#"d"), 274 !cast<MxType>("MxType"#SZ#"r"), 275 CMD>; 276 277} // MxBiArOp_DF 278 279 280// These special snowflakes allowed to match address registers but since *A 281// operations do not produce CCR we should not match them against Mx nodes that 282// produce it. 283let Pattern = [(null_frag)] in 284multiclass MxBiArOp_AF<string MN, SDNode NODE, bits<4> CMD> { 285 286 def NAME#"32ak" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.KOp, MxType32.KPat, 287 CMD, MxEncAddrMode_k<"opd">>; 288 def NAME#"32aq" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.QOp, MxType32.QPat, 289 CMD, MxEncAddrMode_q<"opd">>; 290 def NAME#"32af" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.FOp, MxType32.FPat, 291 CMD, MxEncAddrMode_f<"opd">>; 292 def NAME#"32ap" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.POp, MxType32.PPat, 293 CMD, MxEncAddrMode_p<"opd">>; 294 def NAME#"32aj" : MxBiArOp_R_RM<MN, NODE, MxType32a, MxType32.JOp, MxType32.JPat, 295 CMD, MxEncAddrMode_j<"opd">>; 296 def NAME#"32ai" : MxBiArOp_R_RI_xEA<MN, NODE, MxType32a, CMD>; 297 298 def NAME#"32ar" : MxBiArOp_R_RR_xEA<MN, NODE, MxType32a, MxType32r, CMD>; 299 300} // MxBiArOp_AF 301 302// NOTE These naturally produce CCR 303 304//===----------------------------------------------------------------------===// 305// Add/Sub 306//===----------------------------------------------------------------------===// 307 308defm ADD : MxBiArOp_DF<"add", MxAdd, 1, 0xD, 0x6>; 309defm ADD : MxBiArOp_AF<"adda", MxAdd, 0xD>; 310defm SUB : MxBiArOp_DF<"sub", MxSub, 0, 0x9, 0x4>; 311defm SUB : MxBiArOp_AF<"suba", MxSub, 0x9>; 312 313 314let Uses = [CCR], Defs = [CCR] in { 315let Constraints = "$src = $dst" in { 316 317/// Encoding for Extended forms 318/// ------------------------------------------------------ 319/// F E D C | B A 9 | 8 | 7 6 | 5 4 | 3 | 2 1 0 320/// ------------------------------------------------------ 321/// x x x x | REG Rx | 1 | SIZE | 0 0 | M | REG Ry 322/// ------------------------------------------------------ 323/// Rx - destination 324/// Ry - source 325/// M - address mode switch 326 327// $reg, ccr <- $reg op $reg op ccr 328class MxBiArOp_R_RRX<string MN, SDNode NODE, MxType TYPE, bits<4> CMD> 329 : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd), 330 MN#"."#TYPE.Prefix#"\t$opd, $dst", 331 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd, CCR))]> { 332 let Inst = (descend CMD, 333 // Destination register 334 (operand "$dst", 3), 335 0b1, 336 // SIZE 337 !cond(!eq(TYPE.Size, 8): 0b00, 338 !eq(TYPE.Size, 16): 0b01, 339 !eq(TYPE.Size, 32): 0b10), 340 0b00, /*R/M*/0b0, 341 // Source register 342 (operand "$opd", 3) 343 ); 344} 345} // Constraints 346} // Uses, Defs 347 348multiclass MxBiArOp_RFF<string MN, SDNode NODE, bit isComm, bits<4> CMD> { 349 350let isCommutable = isComm in { 351 foreach SZ = [8, 16, 32] in 352 def NAME#SZ#"dd" : MxBiArOp_R_RRX<MN, NODE, !cast<MxType>("MxType"#SZ#"d"), CMD>; 353} // isComm 354 355} // MxBiArOp_RFF 356 357// NOTE These consume and produce CCR 358defm ADDX : MxBiArOp_RFF<"addx", MxAddX, 1, 0xD>; 359defm SUBX : MxBiArOp_RFF<"subx", MxSubX, 0, 0x9>; 360 361 362//===----------------------------------------------------------------------===// 363// And/Xor/Or 364//===----------------------------------------------------------------------===// 365 366defm AND : MxBiArOp_DF<"and", MxAnd, 1, 0xC, 0x2>; 367defm OR : MxBiArOp_DF<"or", MxOr, 1, 0x8, 0x0>; 368 369multiclass MxBiArOp_DF_EAd<string MN, SDNode NODE, bits<4> CMD, bits<4> CMDI> { 370 foreach SZ = [8, 16, 32] in { 371 let isCommutable = 1 in 372 def NAME#SZ#"dd" : MxBiArOp_R_RR_EAd<MN, NODE, 373 !cast<MxType>("MxType"#SZ#"d"), 374 CMD>; 375 376 def NAME#SZ#"di" : MxBiArOp_R_RI<MN, NODE, 377 !cast<MxType>("MxType"#SZ#"d"), 378 CMDI>; 379 } // foreach SZ 380} // MxBiArOp_DF_EAd 381 382defm XOR : MxBiArOp_DF_EAd<"eor", MxXor, 0xB, 0xA>; 383 384 385//===----------------------------------------------------------------------===// 386// CMP 387//===----------------------------------------------------------------------===// 388 389let Defs = [CCR] in { 390class MxCmp_RR<MxType LHS_TYPE, MxType RHS_TYPE = LHS_TYPE> 391 : MxInst<(outs), (ins LHS_TYPE.ROp:$lhs, RHS_TYPE.ROp:$rhs), 392 "cmp."#RHS_TYPE.Prefix#"\t$lhs, $rhs", 393 [(set CCR, (MxCmp LHS_TYPE.VT:$lhs, RHS_TYPE.VT:$rhs))]> { 394 let Inst = (descend 0b1011, 395 // REGISTER 396 (operand "$rhs", 3), 397 // OPMODE 398 !cast<MxOpModeEncoding>("MxOpMode"#RHS_TYPE.Size#"_"#RHS_TYPE.RLet#"_EA").Value, 399 // MODE without last bit 400 0b00, 401 // REGISTER prefixed by D/A bit 402 (operand "$lhs", 4) 403 ); 404} 405 406class MxCmp_RI<MxType TYPE> 407 : MxInst<(outs), (ins TYPE.IOp:$imm, TYPE.ROp:$reg), 408 "cmpi."#TYPE.Prefix#"\t$imm, $reg", 409 [(set CCR, (MxCmp TYPE.IPat:$imm, TYPE.VT:$reg))]> { 410 let Inst = (ascend 411 (descend 0b00001100, 412 !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value, 413 // The destination cannot be address register, so it's always 414 // the MODE for data register direct mode. 415 /*MODE*/0b000, 416 /*REGISTER*/(operand "$reg", 3)), 417 // Source (i.e. immediate value) encoding 418 MxEncAddrMode_i<"imm", TYPE.Size>.Supplement 419 ); 420} 421 422let mayLoad = 1 in { 423 424class MxCmp_MI<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat, 425 MxEncMemOp MEM_ENC> 426 : MxInst<(outs), (ins TYPE.IOp:$imm, MEMOpd:$mem), 427 "cmpi."#TYPE.Prefix#"\t$imm, $mem", 428 [(set CCR, (MxCmp TYPE.IPat:$imm, (load MEMPat:$mem)))]> { 429 let Inst = (ascend 430 (descend 0b00001100, 431 !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value, 432 MEM_ENC.EA), 433 // Source (i.e. immediate value) encoding 434 MxEncAddrMode_i<"imm", TYPE.Size>.Supplement, 435 // Destination (i.e. memory operand) encoding 436 MEM_ENC.Supplement 437 ); 438} 439 440// FIXME: What about abs.W? 441class MxCmp_BI<MxType TYPE> 442 : MxInst<(outs), (ins TYPE.IOp:$imm, MxAL32:$abs), 443 "cmpi."#TYPE.Prefix#"\t$imm, $abs", 444 [(set CCR, (MxCmp TYPE.IPat:$imm, 445 (load (i32 (MxWrapper tglobaladdr:$abs)))))]> { 446 defvar AbsEncoding = MxEncAddrMode_abs<"abs", true>; 447 let Inst = (ascend 448 (descend 0b00001100, 449 !cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value, 450 AbsEncoding.EA), 451 // Source (i.e. immediate value) encoding 452 MxEncAddrMode_i<"imm", TYPE.Size>.Supplement, 453 // Destination (i.e. memory operand) encoding 454 AbsEncoding.Supplement 455 ); 456} 457 458class MxCmp_RM<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat, 459 MxEncMemOp MEM_ENC> 460 : MxInst<(outs), (ins TYPE.ROp:$reg, MEMOpd:$mem), 461 "cmp."#TYPE.Prefix#"\t$mem, $reg", 462 [(set CCR, (MxCmp (load MEMPat:$mem), TYPE.ROp:$reg))]> { 463 let Inst = (ascend 464 (descend 0b1011, 465 // REGISTER 466 (operand "$reg", 3), 467 // OPMODE 468 !cast<MxOpModeEncoding>("MxOpMode"#TYPE.Size#"_d_EA").Value, 469 MEM_ENC.EA), 470 MEM_ENC.Supplement 471 ); 472} 473} // let mayLoad = 1 474 475} // let Defs = [CCR] 476 477multiclass MMxCmp_RM<MxType TYPE> { 478 def NAME#TYPE.KOp.Letter : MxCmp_RM<TYPE, TYPE.KOp, TYPE.KPat, MxEncAddrMode_k<"mem">>; 479 def NAME#TYPE.QOp.Letter : MxCmp_RM<TYPE, TYPE.QOp, TYPE.QPat, MxEncAddrMode_q<"mem">>; 480 def NAME#TYPE.POp.Letter : MxCmp_RM<TYPE, TYPE.POp, TYPE.PPat, MxEncAddrMode_p<"mem">>; 481 def NAME#TYPE.FOp.Letter : MxCmp_RM<TYPE, TYPE.FOp, TYPE.FPat, MxEncAddrMode_f<"mem">>; 482 def NAME#TYPE.JOp.Letter : MxCmp_RM<TYPE, TYPE.JOp, TYPE.JPat, MxEncAddrMode_j<"mem">>; 483} 484 485multiclass MMxCmp_MI<MxType TYPE> { 486 def NAME#TYPE.KOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.KOp, TYPE.KPat, 487 MxEncAddrMode_k<"mem">>; 488 def NAME#TYPE.QOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.QOp, TYPE.QPat, 489 MxEncAddrMode_q<"mem">>; 490 def NAME#TYPE.POp.Letter#"i" : MxCmp_MI<TYPE, TYPE.POp, TYPE.PPat, 491 MxEncAddrMode_p<"mem">>; 492 def NAME#TYPE.FOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.FOp, TYPE.FPat, 493 MxEncAddrMode_f<"mem">>; 494 def NAME#TYPE.JOp.Letter#"i" : MxCmp_MI<TYPE, TYPE.JOp, TYPE.JPat, 495 MxEncAddrMode_j<"mem">>; 496} 497 498foreach S = [8, 16, 32] in { 499 def CMP#S#di : MxCmp_RI<!cast<MxType>("MxType"#S#"d")>; 500 def CMP#S#bi : MxCmp_BI<!cast<MxType>("MxType"#S#"d")>; 501} // foreach 502 503def CMP8dd : MxCmp_RR<MxType8d>; 504foreach S = [16, 32] in { 505 def CMP#S#dr : MxCmp_RR<!cast<MxType>("MxType"#S#"r"), 506 !cast<MxType>("MxType"#S#"d")>; 507} 508 509// cmp mem, Dn 510defm CMP8d : MMxCmp_RM<MxType8d>; 511defm CMP16d : MMxCmp_RM<MxType16d>; 512defm CMP32d : MMxCmp_RM<MxType32d>; 513 514// cmp #imm, mem 515defm CMP8 : MMxCmp_MI<MxType8d>; 516defm CMP16 : MMxCmp_MI<MxType16d>; 517defm CMP32 : MMxCmp_MI<MxType32d>; 518 519 520//===----------------------------------------------------------------------===// 521// EXT 522//===----------------------------------------------------------------------===// 523 524/// --------------------------------------------------- 525/// F E D C B A 9 | 8 7 6 | 5 4 3 | 2 1 0 526/// --------------------------------------------------- 527/// 0 1 0 0 1 0 0 | OPMODE | 0 0 0 | REG 528/// --------------------------------------------------- 529let Defs = [CCR] in 530let Constraints = "$src = $dst" in 531class MxExt<MxType TO, MxType FROM> 532 : MxInst<(outs TO.ROp:$dst), (ins TO.ROp:$src), 533 "ext."#TO.Prefix#"\t$src", []> { 534 let Inst = (descend 0b0100100, 535 // OPMODE 536 !cond( 537 // byte -> word 538 !and(!eq(FROM.Size, 8), !eq(TO.Size, 16)): 0b010, 539 // word -> long 540 !and(!eq(FROM.Size, 16), !eq(TO.Size, 32)): 0b011, 541 // byte -> long 542 !and(!eq(FROM.Size, 8), !eq(TO.Size, 32)): 0b111 543 ), 544 0b000, 545 // REGISTER 546 (operand "$src", 3) 547 ); 548} 549 550def EXT16 : MxExt<MxType16d, MxType8d>; 551def EXT32 : MxExt<MxType32d, MxType16d>; 552 553def : Pat<(sext_inreg i16:$src, i8), (EXT16 $src)>; 554def : Pat<(sext_inreg i32:$src, i16), (EXT32 $src)>; 555def : Pat<(sext_inreg i32:$src, i8), 556 (EXT32 (MOVXd32d16 (EXT16 (EXTRACT_SUBREG $src, MxSubRegIndex16Lo))))>; 557 558 559//===----------------------------------------------------------------------===// 560// DIV/MUL 561//===----------------------------------------------------------------------===// 562 563/// Word operation: 564/// ---------------------------------------------------- 565/// F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 566/// ---------------------------------------------------- 567/// | | | EFFECTIVE ADDRESS 568/// x x x x | REG | OP MODE | MODE | REG 569/// ---------------------------------------------------- 570let Defs = [CCR] in { 571let Constraints = "$src = $dst" in { 572// $dreg <- $dreg op $dreg 573class MxDiMuOp_DD<string MN, bits<4> CMD, bit SIGNED = false, 574 MxOperand DST, MxOperand OPD> 575 : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", []> { 576 let Inst = (descend CMD, 577 // REGISTER 578 (operand "$dst", 3), 579 !if(SIGNED, 0b111, 0b011), 580 /*MODE*/0b000, /*REGISTER*/(operand "$opd", 3) 581 ); 582} 583 584// $reg <- $reg op $imm 585class MxDiMuOp_DI<string MN, bits<4> CMD, bit SIGNED = false, 586 MxOperand DST, MxOperand OPD> 587 : MxInst<(outs DST:$dst), (ins DST:$src, OPD:$opd), MN#"\t$opd, $dst", []> { 588 // FIXME: Support immediates with different widths. 589 defvar ImmEnc = MxEncAddrMode_i<"opd", 16>; 590 let Inst = (ascend 591 (descend CMD, 592 // REGISTER 593 (operand "$dst", 3), 594 !if(SIGNED, 0b111, 0b011), ImmEnc.EA), 595 ImmEnc.Supplement 596 ); 597} 598} // let Constraints 599} // Defs = [CCR] 600 601multiclass MxDiMuOp<string MN, bits<4> CMD, bit isComm = 0> { 602 let isCommutable = isComm in { 603 def "S"#NAME#"d32d16" : MxDiMuOp_DD<MN#"s", CMD, /*SIGNED*/true, MxDRD32, MxDRD16>; 604 def "U"#NAME#"d32d16" : MxDiMuOp_DD<MN#"u", CMD, /*SIGNED*/false, MxDRD32, MxDRD16>; 605 } 606 607 def "S"#NAME#"d32i16" : MxDiMuOp_DI<MN#"s", CMD, /*SIGNED*/true, MxDRD32, Mxi16imm>; 608 def "U"#NAME#"d32i16" : MxDiMuOp_DI<MN#"u", CMD, /*SIGNED*/false, MxDRD32, Mxi16imm>; 609} 610 611defm DIV : MxDiMuOp<"div", 0x8>; 612 613// This is used to cast immediates to 16-bits for operations which don't 614// support smaller immediate sizes. 615def as_i16imm : SDNodeXForm<imm, [{ 616 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16); 617}]>; 618 619// RR i8 620def : Pat<(sdiv i8:$dst, i8:$opd), 621 (EXTRACT_SUBREG 622 (SDIVd32d16 (MOVSXd32d8 $dst), (MOVSXd16d8 $opd)), 623 MxSubRegIndex8Lo)>; 624 625def : Pat<(udiv i8:$dst, i8:$opd), 626 (EXTRACT_SUBREG 627 (UDIVd32d16 (MOVZXd32d8 $dst), (MOVZXd16d8 $opd)), 628 MxSubRegIndex8Lo)>; 629 630def : Pat<(srem i8:$dst, i8:$opd), 631 (EXTRACT_SUBREG 632 (ASR32di (ASR32di (SDIVd32d16 (MOVSXd32d8 $dst), (MOVSXd16d8 $opd)), 8), 8), 633 MxSubRegIndex8Lo)>; 634 635def : Pat<(urem i8:$dst, i8:$opd), 636 (EXTRACT_SUBREG 637 (LSR32di (LSR32di (UDIVd32d16 (MOVZXd32d8 $dst), (MOVZXd16d8 $opd)), 8), 8), 638 MxSubRegIndex8Lo)>; 639 640// RR i16 641def : Pat<(sdiv i16:$dst, i16:$opd), 642 (EXTRACT_SUBREG 643 (SDIVd32d16 (MOVSXd32d16 $dst), $opd), 644 MxSubRegIndex16Lo)>; 645 646def : Pat<(udiv i16:$dst, i16:$opd), 647 (EXTRACT_SUBREG 648 (UDIVd32d16 (MOVZXd32d16 $dst), $opd), 649 MxSubRegIndex16Lo)>; 650 651def : Pat<(srem i16:$dst, i16:$opd), 652 (EXTRACT_SUBREG 653 (ASR32di (ASR32di (SDIVd32d16 (MOVSXd32d16 $dst), $opd), 8), 8), 654 MxSubRegIndex16Lo)>; 655 656def : Pat<(urem i16:$dst, i16:$opd), 657 (EXTRACT_SUBREG 658 (LSR32di (LSR32di (UDIVd32d16 (MOVZXd32d16 $dst), $opd), 8), 8), 659 MxSubRegIndex16Lo)>; 660 661 662// RI i8 663def : Pat<(sdiv i8:$dst, MximmSExt8:$opd), 664 (EXTRACT_SUBREG 665 (SDIVd32i16 (MOVSXd32d8 $dst), (as_i16imm $opd)), 666 MxSubRegIndex8Lo)>; 667 668def : Pat<(udiv i8:$dst, MximmSExt8:$opd), 669 (EXTRACT_SUBREG 670 (UDIVd32i16 (MOVZXd32d8 $dst), (as_i16imm $opd)), 671 MxSubRegIndex8Lo)>; 672 673def : Pat<(srem i8:$dst, MximmSExt8:$opd), 674 (EXTRACT_SUBREG 675 (ASR32di (ASR32di (SDIVd32i16 (MOVSXd32d8 $dst), (as_i16imm $opd)), 8), 8), 676 MxSubRegIndex8Lo)>; 677 678def : Pat<(urem i8:$dst, MximmSExt8:$opd), 679 (EXTRACT_SUBREG 680 (LSR32di (LSR32di (UDIVd32i16 (MOVZXd32d8 $dst), (as_i16imm $opd)), 8), 8), 681 MxSubRegIndex8Lo)>; 682 683// RI i16 684def : Pat<(sdiv i16:$dst, MximmSExt16:$opd), 685 (EXTRACT_SUBREG 686 (SDIVd32i16 (MOVSXd32d16 $dst), imm:$opd), 687 MxSubRegIndex16Lo)>; 688 689def : Pat<(udiv i16:$dst, MximmSExt16:$opd), 690 (EXTRACT_SUBREG 691 (UDIVd32i16 (MOVZXd32d16 $dst), imm:$opd), 692 MxSubRegIndex16Lo)>; 693 694def : Pat<(srem i16:$dst, MximmSExt16:$opd), 695 (EXTRACT_SUBREG 696 (ASR32di (ASR32di (SDIVd32i16 (MOVSXd32d16 $dst), imm:$opd), 8), 8), 697 MxSubRegIndex16Lo)>; 698 699def : Pat<(urem i16:$dst, MximmSExt16:$opd), 700 (EXTRACT_SUBREG 701 (LSR32di (LSR32di (UDIVd32i16 (MOVZXd32d16 $dst), imm:$opd), 8), 8), 702 MxSubRegIndex16Lo)>; 703 704 705defm MUL : MxDiMuOp<"mul", 0xC, 1>; 706 707// RR 708def : Pat<(mul i16:$dst, i16:$opd), 709 (EXTRACT_SUBREG 710 (SMULd32d16 (MOVXd32d16 $dst), $opd), 711 MxSubRegIndex16Lo)>; 712 713def : Pat<(mulhs i16:$dst, i16:$opd), 714 (EXTRACT_SUBREG 715 (ASR32di (ASR32di (SMULd32d16 (MOVXd32d16 $dst), $opd), 8), 8), 716 MxSubRegIndex16Lo)>; 717 718def : Pat<(mulhu i16:$dst, i16:$opd), 719 (EXTRACT_SUBREG 720 (LSR32di (LSR32di (UMULd32d16 (MOVXd32d16 $dst), $opd), 8), 8), 721 MxSubRegIndex16Lo)>; 722 723 724// RI 725def : Pat<(mul i16:$dst, MximmSExt16:$opd), 726 (EXTRACT_SUBREG 727 (SMULd32i16 (MOVXd32d16 $dst), imm:$opd), 728 MxSubRegIndex16Lo)>; 729 730def : Pat<(mulhs i16:$dst, MximmSExt16:$opd), 731 (EXTRACT_SUBREG 732 (ASR32di (ASR32di (SMULd32i16 (MOVXd32d16 $dst), imm:$opd), 8), 8), 733 MxSubRegIndex16Lo)>; 734 735def : Pat<(mulhu i16:$dst, MximmSExt16:$opd), 736 (EXTRACT_SUBREG 737 (LSR32di (LSR32di (UMULd32i16 (MOVXd32d16 $dst), imm:$opd), 8), 8), 738 MxSubRegIndex16Lo)>; 739 740 741//===----------------------------------------------------------------------===// 742// NEG/NEGX 743//===----------------------------------------------------------------------===// 744 745/// ------------+------------+------+---------+--------- 746/// F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0 747/// ------------+------------+------+------------------- 748/// | | | EFFECTIVE ADDRESS 749/// 0 1 0 0 | x x x x | SIZE | MODE | REG 750/// ------------+------------+------+---------+--------- 751let Defs = [CCR] in { 752let Constraints = "$src = $dst" in { 753 754class MxNeg_D<MxType TYPE> 755 : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src), 756 "neg."#TYPE.Prefix#"\t$dst", 757 [(set TYPE.VT:$dst, (ineg TYPE.VT:$src))]> { 758 let Inst = (descend 0b01000100, 759 /*SIZE*/!cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value, 760 //MODE without last bit 761 0b00, 762 //REGISTER prefixed by D/A bit 763 (operand "$dst", 4) 764 ); 765} 766 767let Uses = [CCR] in { 768class MxNegX_D<MxType TYPE> 769 : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src), 770 "negx."#TYPE.Prefix#"\t$dst", 771 [(set TYPE.VT:$dst, (MxSubX 0, TYPE.VT:$src, CCR))]> { 772 let Inst = (descend 0b01000000, 773 /*SIZE*/!cast<MxNewEncSize>("MxNewEncSize"#TYPE.Size).Value, 774 //MODE without last bit 775 0b00, 776 //REGISTER prefixed by D/A bit 777 (operand "$dst", 4) 778 ); 779} 780} 781 782} // let Constraints 783} // let Defs = [CCR] 784 785foreach S = [8, 16, 32] in { 786 def NEG#S#d : MxNeg_D<!cast<MxType>("MxType"#S#"d")>; 787 def NEGX#S#d : MxNegX_D<!cast<MxType>("MxType"#S#"d")>; 788} 789 790def : Pat<(MxSub 0, i8 :$src), (NEG8d MxDRD8 :$src)>; 791def : Pat<(MxSub 0, i16:$src), (NEG16d MxDRD16:$src)>; 792def : Pat<(MxSub 0, i32:$src), (NEG32d MxDRD32:$src)>; 793 794//===----------------------------------------------------------------------===// 795// no-CCR Patterns 796//===----------------------------------------------------------------------===// 797 798/// Basically the reason for this stuff is that add and addc share the same 799/// operand types constraints for whatever reasons and I had to define a common 800/// MxAdd and MxSub instructions that produce CCR and then pattern-map add and addc 801/// to it. 802/// NOTE On the other hand I see no reason why I cannot just drop explicit CCR 803/// result. Anyway works for now, hopefully I will better understand how this stuff 804/// is designed later 805foreach N = ["add", "addc"] in { 806 807 // add reg, reg 808 def : Pat<(!cast<SDNode>(N) i8 :$src, i8 :$opd), 809 (ADD8dd MxDRD8 :$src, MxDRD8 :$opd)>; 810 def : Pat<(!cast<SDNode>(N) i16:$src, i16:$opd), 811 (ADD16dr MxXRD16:$src, MxDRD16:$opd)>; 812 def : Pat<(!cast<SDNode>(N) i32:$src, i32:$opd), 813 (ADD32dr MxXRD32:$src, MxDRD32:$opd)>; 814 815 // add (An), reg 816 def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.JPat:$opd)), 817 (ADD8dj MxDRD8:$src, MxType8.JOp:$opd)>; 818 def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.JPat:$opd)), 819 (ADD16dj MxDRD16:$src, MxType16.JOp:$opd)>; 820 def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.JPat:$opd)), 821 (ADD32dj MxDRD32:$src, MxType32.JOp:$opd)>; 822 823 // add (i,An), reg 824 def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.PPat:$opd)), 825 (ADD8dp MxDRD8:$src, MxType8.POp:$opd)>; 826 def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.PPat:$opd)), 827 (ADD16dp MxDRD16:$src, MxType16.POp:$opd)>; 828 def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.PPat:$opd)), 829 (ADD32dp MxDRD32:$src, MxType32.POp:$opd)>; 830 831 // add (i,An,Xn), reg 832 def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.FPat:$opd)), 833 (ADD8df MxDRD8:$src, MxType8.FOp:$opd)>; 834 def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.FPat:$opd)), 835 (ADD16df MxDRD16:$src, MxType16.FOp:$opd)>; 836 def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.FPat:$opd)), 837 (ADD32df MxDRD32:$src, MxType32.FOp:$opd)>; 838 839 // add reg, imm 840 def : Pat<(!cast<SDNode>(N) i8: $src, MximmSExt8:$opd), 841 (ADD8di MxDRD8 :$src, imm:$opd)>; 842 def : Pat<(!cast<SDNode>(N) i16:$src, MximmSExt16:$opd), 843 (ADD16di MxDRD16:$src, imm:$opd)>; 844 845 // LEAp is more complex and thus will be selected over normal ADD32ri but it cannot 846 // be used with data registers, here by adding complexity to a simple ADD32ri insts 847 // we make sure it will be selected over LEAp 848 let AddedComplexity = 15 in { 849 def : Pat<(!cast<SDNode>(N) i32:$src, MximmSExt32:$opd), 850 (ADD32di MxDRD32:$src, imm:$opd)>; 851 } // AddedComplexity = 15 852 853 // add imm, (An) 854 def : Pat<(store (!cast<SDNode>(N) (load MxType8.JPat:$dst), MxType8.IPat:$opd), 855 MxType8.JPat:$dst), 856 (ADD8ji MxType8.JOp:$dst, imm:$opd)>; 857 def : Pat<(store (!cast<SDNode>(N) (load MxType16.JPat:$dst), MxType16.IPat:$opd), 858 MxType16.JPat:$dst), 859 (ADD16ji MxType16.JOp:$dst, imm:$opd)>; 860 def : Pat<(store (!cast<SDNode>(N) (load MxType32.JPat:$dst), MxType32.IPat:$opd), 861 MxType32.JPat:$dst), 862 (ADD32ji MxType32.JOp:$dst, imm:$opd)>; 863 864} // foreach add, addc 865 866def : Pat<(adde i8 :$src, i8 :$opd), (ADDX8dd MxDRD8 :$src, MxDRD8 :$opd)>; 867def : Pat<(adde i16:$src, i16:$opd), (ADDX16dd MxDRD16:$src, MxDRD16:$opd)>; 868def : Pat<(adde i32:$src, i32:$opd), (ADDX32dd MxDRD32:$src, MxDRD32:$opd)>; 869 870 871 872foreach N = ["sub", "subc"] in { 873 874 // sub reg, reg 875 def : Pat<(!cast<SDNode>(N) i8 :$src, i8 :$opd), 876 (SUB8dd MxDRD8 :$src, MxDRD8 :$opd)>; 877 def : Pat<(!cast<SDNode>(N) i16:$src, i16:$opd), 878 (SUB16dd MxDRD16:$src, MxDRD16:$opd)>; 879 def : Pat<(!cast<SDNode>(N) i32:$src, i32:$opd), 880 (SUB32dd MxDRD32:$src, MxDRD32:$opd)>; 881 882 883 // sub (An), reg 884 def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.JPat:$opd)), 885 (SUB8dj MxDRD8:$src, MxType8.JOp:$opd)>; 886 def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.JPat:$opd)), 887 (SUB16dj MxDRD16:$src, MxType16.JOp:$opd)>; 888 def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.JPat:$opd)), 889 (SUB32dj MxDRD32:$src, MxType32.JOp:$opd)>; 890 891 // sub (i,An), reg 892 def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.PPat:$opd)), 893 (SUB8dp MxDRD8:$src, MxType8.POp:$opd)>; 894 def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.PPat:$opd)), 895 (SUB16dp MxDRD16:$src, MxType16.POp:$opd)>; 896 def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.PPat:$opd)), 897 (SUB32dp MxDRD32:$src, MxType32.POp:$opd)>; 898 899 // sub (i,An,Xn), reg 900 def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.FPat:$opd)), 901 (SUB8df MxDRD8:$src, MxType8.FOp:$opd)>; 902 def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.FPat:$opd)), 903 (SUB16df MxDRD16:$src, MxType16.FOp:$opd)>; 904 def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.FPat:$opd)), 905 (SUB32df MxDRD32:$src, MxType32.FOp:$opd)>; 906 907 // sub reg, imm 908 def : Pat<(!cast<SDNode>(N) i8 :$src, MximmSExt8 :$opd), 909 (SUB8di MxDRD8 :$src, imm:$opd)>; 910 def : Pat<(!cast<SDNode>(N) i16:$src, MximmSExt16:$opd), 911 (SUB16di MxDRD16:$src, imm:$opd)>; 912 def : Pat<(!cast<SDNode>(N) i32:$src, MximmSExt32:$opd), 913 (SUB32di MxDRD32:$src, imm:$opd)>; 914 915 // sub imm, (An) 916 def : Pat<(store (!cast<SDNode>(N) (load MxType8.JPat:$dst), MxType8.IPat:$opd), 917 MxType8.JPat:$dst), 918 (SUB8ji MxType8.JOp:$dst, imm:$opd)>; 919 def : Pat<(store (!cast<SDNode>(N) (load MxType16.JPat:$dst), MxType16.IPat:$opd), 920 MxType16.JPat:$dst), 921 (SUB16ji MxType16.JOp:$dst, imm:$opd)>; 922 def : Pat<(store (!cast<SDNode>(N) (load MxType32.JPat:$dst), MxType32.IPat:$opd), 923 MxType32.JPat:$dst), 924 (SUB32ji MxType32.JOp:$dst, imm:$opd)>; 925 926} // foreach sub, subx 927 928def : Pat<(sube i8 :$src, i8 :$opd), (SUBX8dd MxDRD8 :$src, MxDRD8 :$opd)>; 929def : Pat<(sube i16:$src, i16:$opd), (SUBX16dd MxDRD16:$src, MxDRD16:$opd)>; 930def : Pat<(sube i32:$src, i32:$opd), (SUBX32dd MxDRD32:$src, MxDRD32:$opd)>; 931 932multiclass BitwisePat<string INST, SDNode OP> { 933 // op reg, reg 934 def : Pat<(OP i8 :$src, i8 :$opd), 935 (!cast<MxInst>(INST#"8dd") MxDRD8 :$src, MxDRD8 :$opd)>; 936 def : Pat<(OP i16:$src, i16:$opd), 937 (!cast<MxInst>(INST#"16dd") MxDRD16:$src, MxDRD16:$opd)>; 938 def : Pat<(OP i32:$src, i32:$opd), 939 (!cast<MxInst>(INST#"32dd") MxDRD32:$src, MxDRD32:$opd)>; 940 // op reg, imm 941 def : Pat<(OP i8: $src, MximmSExt8 :$opd), 942 (!cast<MxInst>(INST#"8di") MxDRD8 :$src, imm:$opd)>; 943 def : Pat<(OP i16:$src, MximmSExt16:$opd), 944 (!cast<MxInst>(INST#"16di") MxDRD16:$src, imm:$opd)>; 945 def : Pat<(OP i32:$src, MximmSExt32:$opd), 946 (!cast<MxInst>(INST#"32di") MxDRD32:$src, imm:$opd)>; 947} 948 949defm : BitwisePat<"AND", and>; 950defm : BitwisePat<"OR", or>; 951defm : BitwisePat<"XOR", xor>; 952