1*fe6060f1SDimitry Andric//===-- M68k.td - Motorola 680x0 target definitions ------*- tablegen -*-===// 2*fe6060f1SDimitry Andric// 3*fe6060f1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*fe6060f1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*fe6060f1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*fe6060f1SDimitry Andric// 7*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 8*fe6060f1SDimitry Andric/// 9*fe6060f1SDimitry Andric/// \file 10*fe6060f1SDimitry Andric/// This is a target description file for the Motorola 680x0 family, referred 11*fe6060f1SDimitry Andric/// to here as the "M68k" architecture. 12*fe6060f1SDimitry Andric/// 13*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 14*fe6060f1SDimitry Andric 15*fe6060f1SDimitry Andricinclude "llvm/Target/Target.td" 16*fe6060f1SDimitry Andric 17*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 18*fe6060f1SDimitry Andric// M68k Subtarget features 19*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 20*fe6060f1SDimitry Andric 21*fe6060f1SDimitry Andricdef FeatureISA00 22*fe6060f1SDimitry Andric : SubtargetFeature<"isa-68000", "SubtargetKind", "M00", 23*fe6060f1SDimitry Andric "Is M68000 ISA supported">; 24*fe6060f1SDimitry Andric 25*fe6060f1SDimitry Andricdef FeatureISA10 26*fe6060f1SDimitry Andric : SubtargetFeature<"isa-68010", "SubtargetKind", "M10", 27*fe6060f1SDimitry Andric "Is M68010 ISA supported", 28*fe6060f1SDimitry Andric [ FeatureISA00 ]>; 29*fe6060f1SDimitry Andric 30*fe6060f1SDimitry Andricdef FeatureISA20 31*fe6060f1SDimitry Andric : SubtargetFeature<"isa-68020", "SubtargetKind", "M20", 32*fe6060f1SDimitry Andric "Is M68020 ISA supported", 33*fe6060f1SDimitry Andric [ FeatureISA10 ]>; 34*fe6060f1SDimitry Andric 35*fe6060f1SDimitry Andricdef FeatureISA30 36*fe6060f1SDimitry Andric : SubtargetFeature<"isa-68030", "SubtargetKind", "M30", 37*fe6060f1SDimitry Andric "Is M68030 ISA supported", 38*fe6060f1SDimitry Andric [ FeatureISA20 ]>; 39*fe6060f1SDimitry Andric 40*fe6060f1SDimitry Andricdef FeatureISA40 41*fe6060f1SDimitry Andric : SubtargetFeature<"isa-68040", "SubtargetKind", "M40", 42*fe6060f1SDimitry Andric "Is M68040 ISA supported", 43*fe6060f1SDimitry Andric [ FeatureISA30 ]>; 44*fe6060f1SDimitry Andric 45*fe6060f1SDimitry Andricdef FeatureISA60 46*fe6060f1SDimitry Andric : SubtargetFeature<"isa-68060", "SubtargetKind", "M60", 47*fe6060f1SDimitry Andric "Is M68060 ISA supported", 48*fe6060f1SDimitry Andric [ FeatureISA40 ]>; 49*fe6060f1SDimitry Andric 50*fe6060f1SDimitry Andricforeach i = {0-6} in 51*fe6060f1SDimitry Andric def FeatureReserveA#i : 52*fe6060f1SDimitry Andric SubtargetFeature<"reserve-a"#i, "UserReservedRegister[M68k::A"#i#"]", 53*fe6060f1SDimitry Andric "true", "Reserve A"#i#" register">; 54*fe6060f1SDimitry Andricforeach i = {0-7} in 55*fe6060f1SDimitry Andric def FeatureReserveD#i : 56*fe6060f1SDimitry Andric SubtargetFeature<"reserve-d"#i, "UserReservedRegister[M68k::D"#i#"]", 57*fe6060f1SDimitry Andric "true", "Reserve D"#i#" register">; 58*fe6060f1SDimitry Andric 59*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 60*fe6060f1SDimitry Andric// M68k processors supported. 61*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 62*fe6060f1SDimitry Andric 63*fe6060f1SDimitry Andricinclude "M68kSchedule.td" 64*fe6060f1SDimitry Andric 65*fe6060f1SDimitry Andricclass Proc<string Name, list<SubtargetFeature> Features> 66*fe6060f1SDimitry Andric : ProcessorModel<Name, GenericM68kModel, Features>; 67*fe6060f1SDimitry Andric 68*fe6060f1SDimitry Andricdef : Proc<"generic", [ FeatureISA00 ]>; 69*fe6060f1SDimitry Andricdef : Proc<"M68000", [ FeatureISA00 ]>; 70*fe6060f1SDimitry Andricdef : Proc<"M68010", [ FeatureISA10 ]>; 71*fe6060f1SDimitry Andricdef : Proc<"M68020", [ FeatureISA20 ]>; 72*fe6060f1SDimitry Andricdef : Proc<"M68030", [ FeatureISA30 ]>; 73*fe6060f1SDimitry Andricdef : Proc<"M68040", [ FeatureISA40 ]>; 74*fe6060f1SDimitry Andricdef : Proc<"M68060", [ FeatureISA60 ]>; 75*fe6060f1SDimitry Andric 76*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 77*fe6060f1SDimitry Andric// Register File Description 78*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 79*fe6060f1SDimitry Andric 80*fe6060f1SDimitry Andricinclude "M68kRegisterInfo.td" 81*fe6060f1SDimitry Andricinclude "GlSel/M68kRegisterBanks.td" 82*fe6060f1SDimitry Andric 83*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 84*fe6060f1SDimitry Andric// Instruction Descriptions 85*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 86*fe6060f1SDimitry Andric 87*fe6060f1SDimitry Andricinclude "M68kInstrInfo.td" 88*fe6060f1SDimitry Andric 89*fe6060f1SDimitry Andricdef M68kInstrInfo : InstrInfo; 90*fe6060f1SDimitry Andric 91*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 92*fe6060f1SDimitry Andric// Calling Conventions 93*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 94*fe6060f1SDimitry Andric 95*fe6060f1SDimitry Andricinclude "M68kCallingConv.td" 96*fe6060f1SDimitry Andric 97*fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 98*fe6060f1SDimitry Andric// Assembly Printers 99*fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 100*fe6060f1SDimitry Andric 101*fe6060f1SDimitry Andricdef M68kAsmWriter : AsmWriter { 102*fe6060f1SDimitry Andric string AsmWriterClassName = "InstPrinter"; 103*fe6060f1SDimitry Andric bit isMCAsmWriter = 1; 104*fe6060f1SDimitry Andric} 105*fe6060f1SDimitry Andric 106*fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 107*fe6060f1SDimitry Andric// Assembly Parsers 108*fe6060f1SDimitry Andric//===---------------------------------------------------------------------===// 109*fe6060f1SDimitry Andric 110*fe6060f1SDimitry Andricdef M68kAsmParser : AsmParser { 111*fe6060f1SDimitry Andric let ShouldEmitMatchRegisterName = 0; 112*fe6060f1SDimitry Andric let ShouldEmitMatchRegisterAltName = 0; 113*fe6060f1SDimitry Andric} 114*fe6060f1SDimitry Andric 115*fe6060f1SDimitry Andricdef M68kAsmParserVariant : AsmParserVariant { 116*fe6060f1SDimitry Andric int Variant = 0; 117*fe6060f1SDimitry Andric} 118*fe6060f1SDimitry Andric 119*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 120*fe6060f1SDimitry Andric// Target 121*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 122*fe6060f1SDimitry Andric 123*fe6060f1SDimitry Andricdef M68k : Target { 124*fe6060f1SDimitry Andric let InstructionSet = M68kInstrInfo; 125*fe6060f1SDimitry Andric let AssemblyParsers = [M68kAsmParser]; 126*fe6060f1SDimitry Andric let AssemblyWriters = [M68kAsmWriter]; 127*fe6060f1SDimitry Andric} 128