181ad6265SDimitry Andric //===-- LoongArchSubtarget.cpp - LoongArch Subtarget Information -*- C++ -*--=// 281ad6265SDimitry Andric // 381ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric // 781ad6265SDimitry Andric //===----------------------------------------------------------------------===// 881ad6265SDimitry Andric // 981ad6265SDimitry Andric // This file implements the LoongArch specific subclass of TargetSubtargetInfo. 1081ad6265SDimitry Andric // 1181ad6265SDimitry Andric //===----------------------------------------------------------------------===// 1281ad6265SDimitry Andric 1381ad6265SDimitry Andric #include "LoongArchSubtarget.h" 1481ad6265SDimitry Andric #include "LoongArchFrameLowering.h" 15*06c3fb27SDimitry Andric #include "MCTargetDesc/LoongArchBaseInfo.h" 1681ad6265SDimitry Andric 1781ad6265SDimitry Andric using namespace llvm; 1881ad6265SDimitry Andric 1981ad6265SDimitry Andric #define DEBUG_TYPE "loongarch-subtarget" 2081ad6265SDimitry Andric 2181ad6265SDimitry Andric #define GET_SUBTARGETINFO_TARGET_DESC 2281ad6265SDimitry Andric #define GET_SUBTARGETINFO_CTOR 2381ad6265SDimitry Andric #include "LoongArchGenSubtargetInfo.inc" 2481ad6265SDimitry Andric 2581ad6265SDimitry Andric void LoongArchSubtarget::anchor() {} 2681ad6265SDimitry Andric 2781ad6265SDimitry Andric LoongArchSubtarget &LoongArchSubtarget::initializeSubtargetDependencies( 2881ad6265SDimitry Andric const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, 2981ad6265SDimitry Andric StringRef ABIName) { 3081ad6265SDimitry Andric bool Is64Bit = TT.isArch64Bit(); 31bdd1243dSDimitry Andric if (CPU.empty() || CPU == "generic") 3281ad6265SDimitry Andric CPU = Is64Bit ? "generic-la64" : "generic-la32"; 3381ad6265SDimitry Andric 3481ad6265SDimitry Andric if (TuneCPU.empty()) 3581ad6265SDimitry Andric TuneCPU = CPU; 3681ad6265SDimitry Andric 3781ad6265SDimitry Andric ParseSubtargetFeatures(CPU, TuneCPU, FS); 38*06c3fb27SDimitry Andric initializeProperties(TuneCPU); 3981ad6265SDimitry Andric if (Is64Bit) { 4081ad6265SDimitry Andric GRLenVT = MVT::i64; 4181ad6265SDimitry Andric GRLen = 64; 4281ad6265SDimitry Andric } 4381ad6265SDimitry Andric 44bdd1243dSDimitry Andric if (HasLA32 == HasLA64) 45bdd1243dSDimitry Andric report_fatal_error("Please use one feature of 32bit and 64bit."); 46bdd1243dSDimitry Andric 47bdd1243dSDimitry Andric if (Is64Bit && HasLA32) 48bdd1243dSDimitry Andric report_fatal_error("Feature 32bit should be used for loongarch32 target."); 49bdd1243dSDimitry Andric 50bdd1243dSDimitry Andric if (!Is64Bit && HasLA64) 51bdd1243dSDimitry Andric report_fatal_error("Feature 64bit should be used for loongarch64 target."); 52bdd1243dSDimitry Andric 53*06c3fb27SDimitry Andric TargetABI = LoongArchABI::computeTargetABI(TT, ABIName); 54*06c3fb27SDimitry Andric 5581ad6265SDimitry Andric return *this; 5681ad6265SDimitry Andric } 5781ad6265SDimitry Andric 58*06c3fb27SDimitry Andric void LoongArchSubtarget::initializeProperties(StringRef TuneCPU) { 59*06c3fb27SDimitry Andric // Initialize CPU specific properties. We should add a tablegen feature for 60*06c3fb27SDimitry Andric // this in the future so we can specify it together with the subtarget 61*06c3fb27SDimitry Andric // features. 62*06c3fb27SDimitry Andric 63*06c3fb27SDimitry Andric // TODO: Check TuneCPU and override defaults (that are for LA464) once we 64*06c3fb27SDimitry Andric // support optimizing for more uarchs. 65*06c3fb27SDimitry Andric 66*06c3fb27SDimitry Andric // Default to the alignment settings empirically confirmed to perform best 67*06c3fb27SDimitry Andric // on LA464, with 4-wide instruction fetch and decode stages. These settings 68*06c3fb27SDimitry Andric // can also be overridden in initializeProperties. 69*06c3fb27SDimitry Andric // 70*06c3fb27SDimitry Andric // We default to such higher-than-minimum alignments because we assume that: 71*06c3fb27SDimitry Andric // 72*06c3fb27SDimitry Andric // * these settings should benefit most existing uarchs/users, 73*06c3fb27SDimitry Andric // * future general-purpose LoongArch cores are likely to have issue widths 74*06c3fb27SDimitry Andric // equal to or wider than 4, 75*06c3fb27SDimitry Andric // * instruction sequences best for LA464 should not pessimize other future 76*06c3fb27SDimitry Andric // uarchs, and 77*06c3fb27SDimitry Andric // * narrower cores would not suffer much (aside from slightly increased 78*06c3fb27SDimitry Andric // ICache footprint maybe), compared to the gains everywhere else. 79*06c3fb27SDimitry Andric PrefFunctionAlignment = Align(32); 80*06c3fb27SDimitry Andric PrefLoopAlignment = Align(16); 81*06c3fb27SDimitry Andric MaxBytesForAlignment = 16; 82*06c3fb27SDimitry Andric } 83*06c3fb27SDimitry Andric 8481ad6265SDimitry Andric LoongArchSubtarget::LoongArchSubtarget(const Triple &TT, StringRef CPU, 8581ad6265SDimitry Andric StringRef TuneCPU, StringRef FS, 8681ad6265SDimitry Andric StringRef ABIName, 8781ad6265SDimitry Andric const TargetMachine &TM) 8881ad6265SDimitry Andric : LoongArchGenSubtargetInfo(TT, CPU, TuneCPU, FS), 8981ad6265SDimitry Andric FrameLowering( 9081ad6265SDimitry Andric initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), 9181ad6265SDimitry Andric InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {} 92