1//===- LoongArchLSXInstrInfo.td - LoongArch LSX instructions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the SIMD extension instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 14 SDTCisInt<1>, SDTCisVec<1>, 15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>; 16def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 17 18def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>, 19 SDTCisInt<1>, SDTCisVec<1>, 20 SDTCisSameAs<0, 2>, 21 SDTCisSameAs<2, 3>]>; 22def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>, 23 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 24def SDT_loongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>, 25 SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>; 26 27// Target nodes. 28def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>; 29def loongarch_vall_nonzero : SDNode<"LoongArchISD::VALL_NONZERO", 30 SDT_LoongArchVecCond>; 31def loongarch_vany_nonzero : SDNode<"LoongArchISD::VANY_NONZERO", 32 SDT_LoongArchVecCond>; 33def loongarch_vall_zero : SDNode<"LoongArchISD::VALL_ZERO", 34 SDT_LoongArchVecCond>; 35def loongarch_vany_zero : SDNode<"LoongArchISD::VANY_ZERO", 36 SDT_LoongArchVecCond>; 37 38def loongarch_vpick_sext_elt : SDNode<"LoongArchISD::VPICK_SEXT_ELT", 39 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 40def loongarch_vpick_zext_elt : SDNode<"LoongArchISD::VPICK_ZEXT_ELT", 41 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 42 43def loongarch_vshuf: SDNode<"LoongArchISD::VSHUF", SDT_LoongArchVShuf>; 44def loongarch_vpickev: SDNode<"LoongArchISD::VPICKEV", SDT_LoongArchV2R>; 45def loongarch_vpickod: SDNode<"LoongArchISD::VPICKOD", SDT_LoongArchV2R>; 46def loongarch_vpackev: SDNode<"LoongArchISD::VPACKEV", SDT_LoongArchV2R>; 47def loongarch_vpackod: SDNode<"LoongArchISD::VPACKOD", SDT_LoongArchV2R>; 48def loongarch_vilvl: SDNode<"LoongArchISD::VILVL", SDT_LoongArchV2R>; 49def loongarch_vilvh: SDNode<"LoongArchISD::VILVH", SDT_LoongArchV2R>; 50 51def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_loongArchV1RUimm>; 52def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_loongArchV1RUimm>; 53 54def immZExt1 : ImmLeaf<i64, [{return isUInt<1>(Imm);}]>; 55def immZExt2 : ImmLeaf<i64, [{return isUInt<2>(Imm);}]>; 56def immZExt3 : ImmLeaf<i64, [{return isUInt<3>(Imm);}]>; 57def immZExt4 : ImmLeaf<i64, [{return isUInt<4>(Imm);}]>; 58def immZExt8 : ImmLeaf<i64, [{return isUInt<8>(Imm);}]>; 59 60class VecCond<SDPatternOperator OpNode, ValueType TyNode, 61 RegisterClass RC = LSX128> 62 : Pseudo<(outs GPR:$rd), (ins RC:$vj), 63 [(set GPR:$rd, (OpNode (TyNode RC:$vj)))]> { 64 let hasSideEffects = 0; 65 let mayLoad = 0; 66 let mayStore = 0; 67 let usesCustomInserter = 1; 68} 69 70def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector)], [{ 71 APInt Imm; 72 EVT EltTy = N->getValueType(0).getVectorElementType(); 73 74 if (N->getOpcode() == ISD::BITCAST) 75 N = N->getOperand(0).getNode(); 76 77 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 78 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 79}]>; 80 81def vsplati8_imm_eq_7 : PatFrags<(ops), [(build_vector)], [{ 82 APInt Imm; 83 EVT EltTy = N->getValueType(0).getVectorElementType(); 84 85 if (N->getOpcode() == ISD::BITCAST) 86 N = N->getOperand(0).getNode(); 87 88 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 89 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 7; 90}]>; 91def vsplati16_imm_eq_15 : PatFrags<(ops), [(build_vector)], [{ 92 APInt Imm; 93 EVT EltTy = N->getValueType(0).getVectorElementType(); 94 95 if (N->getOpcode() == ISD::BITCAST) 96 N = N->getOperand(0).getNode(); 97 98 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 99 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 15; 100}]>; 101def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{ 102 APInt Imm; 103 EVT EltTy = N->getValueType(0).getVectorElementType(); 104 105 if (N->getOpcode() == ISD::BITCAST) 106 N = N->getOperand(0).getNode(); 107 108 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 109 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31; 110}]>; 111def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector)], [{ 112 APInt Imm; 113 EVT EltTy = N->getValueType(0).getVectorElementType(); 114 115 if (N->getOpcode() == ISD::BITCAST) 116 N = N->getOperand(0).getNode(); 117 118 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 119 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 120}]>; 121 122def vsplatf32_fpimm_eq_1 123 : PatFrags<(ops), [(bitconvert (v4i32 (build_vector))), 124 (bitconvert (v8i32 (build_vector)))], [{ 125 APInt Imm; 126 EVT EltTy = N->getValueType(0).getVectorElementType(); 127 N = N->getOperand(0).getNode(); 128 129 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 130 Imm.getBitWidth() == EltTy.getSizeInBits() && 131 Imm == APFloat(+1.0f).bitcastToAPInt(); 132}]>; 133def vsplatf64_fpimm_eq_1 134 : PatFrags<(ops), [(bitconvert (v2i64 (build_vector))), 135 (bitconvert (v4i64 (build_vector)))], [{ 136 APInt Imm; 137 EVT EltTy = N->getValueType(0).getVectorElementType(); 138 N = N->getOperand(0).getNode(); 139 140 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 141 Imm.getBitWidth() == EltTy.getSizeInBits() && 142 Imm == APFloat(+1.0).bitcastToAPInt(); 143}]>; 144 145def vsplati8imm7 : PatFrag<(ops node:$reg), 146 (and node:$reg, vsplati8_imm_eq_7)>; 147def vsplati16imm15 : PatFrag<(ops node:$reg), 148 (and node:$reg, vsplati16_imm_eq_15)>; 149def vsplati32imm31 : PatFrag<(ops node:$reg), 150 (and node:$reg, vsplati32_imm_eq_31)>; 151def vsplati64imm63 : PatFrag<(ops node:$reg), 152 (and node:$reg, vsplati64_imm_eq_63)>; 153 154foreach N = [3, 4, 5, 6, 8] in 155 def SplatPat_uimm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#">", 156 [build_vector, bitconvert], [], 2>; 157 158foreach N = [5] in 159 def SplatPat_simm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#", true>", 160 [build_vector, bitconvert]>; 161 162def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 163 [build_vector, bitconvert]>; 164 165def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 166 [build_vector, bitconvert]>; 167 168def muladd : PatFrag<(ops node:$vd, node:$vj, node:$vk), 169 (add node:$vd, (mul node:$vj, node:$vk))>; 170 171def mulsub : PatFrag<(ops node:$vd, node:$vj, node:$vk), 172 (sub node:$vd, (mul node:$vj, node:$vk))>; 173 174def lsxsplati8 : PatFrag<(ops node:$e0), 175 (v16i8 (build_vector node:$e0, node:$e0, 176 node:$e0, node:$e0, 177 node:$e0, node:$e0, 178 node:$e0, node:$e0, 179 node:$e0, node:$e0, 180 node:$e0, node:$e0, 181 node:$e0, node:$e0, 182 node:$e0, node:$e0))>; 183def lsxsplati16 : PatFrag<(ops node:$e0), 184 (v8i16 (build_vector node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0, 187 node:$e0, node:$e0))>; 188def lsxsplati32 : PatFrag<(ops node:$e0), 189 (v4i32 (build_vector node:$e0, node:$e0, 190 node:$e0, node:$e0))>; 191def lsxsplati64 : PatFrag<(ops node:$e0), 192 (v2i64 (build_vector node:$e0, node:$e0))>; 193def lsxsplatf32 : PatFrag<(ops node:$e0), 194 (v4f32 (build_vector node:$e0, node:$e0, 195 node:$e0, node:$e0))>; 196def lsxsplatf64 : PatFrag<(ops node:$e0), 197 (v2f64 (build_vector node:$e0, node:$e0))>; 198 199def to_valid_timm : SDNodeXForm<timm, [{ 200 auto CN = cast<ConstantSDNode>(N); 201 return CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(N), Subtarget->getGRLenVT()); 202}]>; 203 204//===----------------------------------------------------------------------===// 205// Instruction class templates 206//===----------------------------------------------------------------------===// 207 208class LSX1RI13_VI<bits<32> op, Operand ImmOpnd = simm13> 209 : Fmt1RI13_VI<op, (outs LSX128:$vd), (ins ImmOpnd:$imm13), "$vd, $imm13">; 210 211class LSX2R_VV<bits<32> op> 212 : Fmt2R_VV<op, (outs LSX128:$vd), (ins LSX128:$vj), "$vd, $vj">; 213 214class LSX2R_VR<bits<32> op> 215 : Fmt2R_VR<op, (outs LSX128:$vd), (ins GPR:$rj), "$vd, $rj">; 216 217class LSX2R_CV<bits<32> op> 218 : Fmt2R_CV<op, (outs CFR:$cd), (ins LSX128:$vj), "$cd, $vj">; 219 220class LSX2RI1_VVI<bits<32> op, Operand ImmOpnd = uimm1> 221 : Fmt2RI1_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm1), 222 "$vd, $vj, $imm1">; 223 224class LSX2RI1_RVI<bits<32> op, Operand ImmOpnd = uimm1> 225 : Fmt2RI1_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm1), 226 "$rd, $vj, $imm1">; 227 228class LSX2RI2_VVI<bits<32> op, Operand ImmOpnd = uimm2> 229 : Fmt2RI2_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm2), 230 "$vd, $vj, $imm2">; 231 232class LSX2RI2_RVI<bits<32> op, Operand ImmOpnd = uimm2> 233 : Fmt2RI2_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm2), 234 "$rd, $vj, $imm2">; 235 236class LSX2RI3_VVI<bits<32> op, Operand ImmOpnd = uimm3> 237 : Fmt2RI3_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm3), 238 "$vd, $vj, $imm3">; 239 240class LSX2RI3_RVI<bits<32> op, Operand ImmOpnd = uimm3> 241 : Fmt2RI3_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm3), 242 "$rd, $vj, $imm3">; 243 244class LSX2RI4_VVI<bits<32> op, Operand ImmOpnd = uimm4> 245 : Fmt2RI4_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm4), 246 "$vd, $vj, $imm4">; 247 248class LSX2RI4_RVI<bits<32> op, Operand ImmOpnd = uimm4> 249 : Fmt2RI4_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm4), 250 "$rd, $vj, $imm4">; 251 252class LSX2RI5_VVI<bits<32> op, Operand ImmOpnd = uimm5> 253 : Fmt2RI5_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm5), 254 "$vd, $vj, $imm5">; 255 256class LSX2RI6_VVI<bits<32> op, Operand ImmOpnd = uimm6> 257 : Fmt2RI6_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm6), 258 "$vd, $vj, $imm6">; 259 260class LSX2RI8_VVI<bits<32> op, Operand ImmOpnd = uimm8> 261 : Fmt2RI8_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm8), 262 "$vd, $vj, $imm8">; 263 264class LSX2RI8I1_VRII<bits<32> op, Operand ImmOpnd = simm8, 265 Operand IdxOpnd = uimm1> 266 : Fmt2RI8I1_VRII<op, (outs), 267 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm1), 268 "$vd, $rj, $imm8, $imm1">; 269class LSX2RI8I2_VRII<bits<32> op, Operand ImmOpnd = simm8, 270 Operand IdxOpnd = uimm2> 271 : Fmt2RI8I2_VRII<op, (outs), 272 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2), 273 "$vd, $rj, $imm8, $imm2">; 274class LSX2RI8I3_VRII<bits<32> op, Operand ImmOpnd = simm8, 275 Operand IdxOpnd = uimm3> 276 : Fmt2RI8I3_VRII<op, (outs), 277 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3), 278 "$vd, $rj, $imm8, $imm3">; 279class LSX2RI8I4_VRII<bits<32> op, Operand ImmOpnd = simm8, 280 Operand IdxOpnd = uimm4> 281 : Fmt2RI8I4_VRII<op, (outs), 282 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4), 283 "$vd, $rj, $imm8, $imm4">; 284 285class LSX3R_VVV<bits<32> op> 286 : Fmt3R_VVV<op, (outs LSX128:$vd), (ins LSX128:$vj, LSX128:$vk), 287 "$vd, $vj, $vk">; 288 289class LSX3R_VVR<bits<32> op> 290 : Fmt3R_VVR<op, (outs LSX128:$vd), (ins LSX128:$vj, GPR:$rk), 291 "$vd, $vj, $rk">; 292 293class LSX4R_VVVV<bits<32> op> 294 : Fmt4R_VVVV<op, (outs LSX128:$vd), 295 (ins LSX128:$vj, LSX128:$vk, LSX128:$va), 296 "$vd, $vj, $vk, $va">; 297 298let Constraints = "$vd = $dst" in { 299 300class LSX2RI1_VVRI<bits<32> op, Operand ImmOpnd = uimm1> 301 : Fmt2RI1_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm1), 302 "$vd, $rj, $imm1">; 303class LSX2RI2_VVRI<bits<32> op, Operand ImmOpnd = uimm2> 304 : Fmt2RI2_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm2), 305 "$vd, $rj, $imm2">; 306class LSX2RI3_VVRI<bits<32> op, Operand ImmOpnd = uimm3> 307 : Fmt2RI3_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm3), 308 "$vd, $rj, $imm3">; 309class LSX2RI4_VVRI<bits<32> op, Operand ImmOpnd = uimm4> 310 : Fmt2RI4_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm4), 311 "$vd, $rj, $imm4">; 312 313class LSX2RI4_VVVI<bits<32> op, Operand ImmOpnd = uimm4> 314 : Fmt2RI4_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm4), 315 "$vd, $vj, $imm4">; 316class LSX2RI5_VVVI<bits<32> op, Operand ImmOpnd = uimm5> 317 : Fmt2RI5_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm5), 318 "$vd, $vj, $imm5">; 319class LSX2RI6_VVVI<bits<32> op, Operand ImmOpnd = uimm6> 320 : Fmt2RI6_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm6), 321 "$vd, $vj, $imm6">; 322class LSX2RI7_VVVI<bits<32> op, Operand ImmOpnd = uimm7> 323 : Fmt2RI7_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm7), 324 "$vd, $vj, $imm7">; 325 326class LSX2RI8_VVVI<bits<32> op, Operand ImmOpnd = uimm8> 327 : Fmt2RI8_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm8), 328 "$vd, $vj, $imm8">; 329 330class LSX3R_VVVV<bits<32> op> 331 : Fmt3R_VVV<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, LSX128:$vk), 332 "$vd, $vj, $vk">; 333 334} // Constraints = "$vd = $dst" 335 336class LSX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3> 337 : Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9), 338 "$vd, $rj, $imm9">; 339class LSX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2> 340 : Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10), 341 "$vd, $rj, $imm10">; 342class LSX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1> 343 : Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11), 344 "$vd, $rj, $imm11">; 345class LSX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12> 346 : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12), 347 "$vd, $rj, $imm12">; 348class LSX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12> 349 : Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12), 350 "$vd, $rj, $imm12">; 351 352class LSX3R_Load<bits<32> op> 353 : Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk), 354 "$vd, $rj, $rk">; 355class LSX3R_Store<bits<32> op> 356 : Fmt3R_VRR<op, (outs), (ins LSX128:$vd, GPR:$rj, GPR:$rk), 357 "$vd, $rj, $rk">; 358 359//===----------------------------------------------------------------------===// 360// Instructions 361//===----------------------------------------------------------------------===// 362 363let hasSideEffects = 0, Predicates = [HasExtLSX] in { 364 365let mayLoad = 0, mayStore = 0 in { 366 367def VADD_B : LSX3R_VVV<0x700a0000>; 368def VADD_H : LSX3R_VVV<0x700a8000>; 369def VADD_W : LSX3R_VVV<0x700b0000>; 370def VADD_D : LSX3R_VVV<0x700b8000>; 371def VADD_Q : LSX3R_VVV<0x712d0000>; 372 373def VSUB_B : LSX3R_VVV<0x700c0000>; 374def VSUB_H : LSX3R_VVV<0x700c8000>; 375def VSUB_W : LSX3R_VVV<0x700d0000>; 376def VSUB_D : LSX3R_VVV<0x700d8000>; 377def VSUB_Q : LSX3R_VVV<0x712d8000>; 378 379def VADDI_BU : LSX2RI5_VVI<0x728a0000>; 380def VADDI_HU : LSX2RI5_VVI<0x728a8000>; 381def VADDI_WU : LSX2RI5_VVI<0x728b0000>; 382def VADDI_DU : LSX2RI5_VVI<0x728b8000>; 383 384def VSUBI_BU : LSX2RI5_VVI<0x728c0000>; 385def VSUBI_HU : LSX2RI5_VVI<0x728c8000>; 386def VSUBI_WU : LSX2RI5_VVI<0x728d0000>; 387def VSUBI_DU : LSX2RI5_VVI<0x728d8000>; 388 389def VNEG_B : LSX2R_VV<0x729c3000>; 390def VNEG_H : LSX2R_VV<0x729c3400>; 391def VNEG_W : LSX2R_VV<0x729c3800>; 392def VNEG_D : LSX2R_VV<0x729c3c00>; 393 394def VSADD_B : LSX3R_VVV<0x70460000>; 395def VSADD_H : LSX3R_VVV<0x70468000>; 396def VSADD_W : LSX3R_VVV<0x70470000>; 397def VSADD_D : LSX3R_VVV<0x70478000>; 398def VSADD_BU : LSX3R_VVV<0x704a0000>; 399def VSADD_HU : LSX3R_VVV<0x704a8000>; 400def VSADD_WU : LSX3R_VVV<0x704b0000>; 401def VSADD_DU : LSX3R_VVV<0x704b8000>; 402 403def VSSUB_B : LSX3R_VVV<0x70480000>; 404def VSSUB_H : LSX3R_VVV<0x70488000>; 405def VSSUB_W : LSX3R_VVV<0x70490000>; 406def VSSUB_D : LSX3R_VVV<0x70498000>; 407def VSSUB_BU : LSX3R_VVV<0x704c0000>; 408def VSSUB_HU : LSX3R_VVV<0x704c8000>; 409def VSSUB_WU : LSX3R_VVV<0x704d0000>; 410def VSSUB_DU : LSX3R_VVV<0x704d8000>; 411 412def VHADDW_H_B : LSX3R_VVV<0x70540000>; 413def VHADDW_W_H : LSX3R_VVV<0x70548000>; 414def VHADDW_D_W : LSX3R_VVV<0x70550000>; 415def VHADDW_Q_D : LSX3R_VVV<0x70558000>; 416def VHADDW_HU_BU : LSX3R_VVV<0x70580000>; 417def VHADDW_WU_HU : LSX3R_VVV<0x70588000>; 418def VHADDW_DU_WU : LSX3R_VVV<0x70590000>; 419def VHADDW_QU_DU : LSX3R_VVV<0x70598000>; 420 421def VHSUBW_H_B : LSX3R_VVV<0x70560000>; 422def VHSUBW_W_H : LSX3R_VVV<0x70568000>; 423def VHSUBW_D_W : LSX3R_VVV<0x70570000>; 424def VHSUBW_Q_D : LSX3R_VVV<0x70578000>; 425def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>; 426def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>; 427def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>; 428def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>; 429 430def VADDWEV_H_B : LSX3R_VVV<0x701e0000>; 431def VADDWEV_W_H : LSX3R_VVV<0x701e8000>; 432def VADDWEV_D_W : LSX3R_VVV<0x701f0000>; 433def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>; 434def VADDWOD_H_B : LSX3R_VVV<0x70220000>; 435def VADDWOD_W_H : LSX3R_VVV<0x70228000>; 436def VADDWOD_D_W : LSX3R_VVV<0x70230000>; 437def VADDWOD_Q_D : LSX3R_VVV<0x70238000>; 438 439def VSUBWEV_H_B : LSX3R_VVV<0x70200000>; 440def VSUBWEV_W_H : LSX3R_VVV<0x70208000>; 441def VSUBWEV_D_W : LSX3R_VVV<0x70210000>; 442def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>; 443def VSUBWOD_H_B : LSX3R_VVV<0x70240000>; 444def VSUBWOD_W_H : LSX3R_VVV<0x70248000>; 445def VSUBWOD_D_W : LSX3R_VVV<0x70250000>; 446def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>; 447 448def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>; 449def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>; 450def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>; 451def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>; 452def VADDWOD_H_BU : LSX3R_VVV<0x70320000>; 453def VADDWOD_W_HU : LSX3R_VVV<0x70328000>; 454def VADDWOD_D_WU : LSX3R_VVV<0x70330000>; 455def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>; 456 457def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>; 458def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>; 459def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>; 460def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>; 461def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>; 462def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>; 463def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>; 464def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>; 465 466def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>; 467def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>; 468def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>; 469def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>; 470def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>; 471def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>; 472def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>; 473def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>; 474 475def VAVG_B : LSX3R_VVV<0x70640000>; 476def VAVG_H : LSX3R_VVV<0x70648000>; 477def VAVG_W : LSX3R_VVV<0x70650000>; 478def VAVG_D : LSX3R_VVV<0x70658000>; 479def VAVG_BU : LSX3R_VVV<0x70660000>; 480def VAVG_HU : LSX3R_VVV<0x70668000>; 481def VAVG_WU : LSX3R_VVV<0x70670000>; 482def VAVG_DU : LSX3R_VVV<0x70678000>; 483def VAVGR_B : LSX3R_VVV<0x70680000>; 484def VAVGR_H : LSX3R_VVV<0x70688000>; 485def VAVGR_W : LSX3R_VVV<0x70690000>; 486def VAVGR_D : LSX3R_VVV<0x70698000>; 487def VAVGR_BU : LSX3R_VVV<0x706a0000>; 488def VAVGR_HU : LSX3R_VVV<0x706a8000>; 489def VAVGR_WU : LSX3R_VVV<0x706b0000>; 490def VAVGR_DU : LSX3R_VVV<0x706b8000>; 491 492def VABSD_B : LSX3R_VVV<0x70600000>; 493def VABSD_H : LSX3R_VVV<0x70608000>; 494def VABSD_W : LSX3R_VVV<0x70610000>; 495def VABSD_D : LSX3R_VVV<0x70618000>; 496def VABSD_BU : LSX3R_VVV<0x70620000>; 497def VABSD_HU : LSX3R_VVV<0x70628000>; 498def VABSD_WU : LSX3R_VVV<0x70630000>; 499def VABSD_DU : LSX3R_VVV<0x70638000>; 500 501def VADDA_B : LSX3R_VVV<0x705c0000>; 502def VADDA_H : LSX3R_VVV<0x705c8000>; 503def VADDA_W : LSX3R_VVV<0x705d0000>; 504def VADDA_D : LSX3R_VVV<0x705d8000>; 505 506def VMAX_B : LSX3R_VVV<0x70700000>; 507def VMAX_H : LSX3R_VVV<0x70708000>; 508def VMAX_W : LSX3R_VVV<0x70710000>; 509def VMAX_D : LSX3R_VVV<0x70718000>; 510def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>; 511def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>; 512def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>; 513def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>; 514def VMAX_BU : LSX3R_VVV<0x70740000>; 515def VMAX_HU : LSX3R_VVV<0x70748000>; 516def VMAX_WU : LSX3R_VVV<0x70750000>; 517def VMAX_DU : LSX3R_VVV<0x70758000>; 518def VMAXI_BU : LSX2RI5_VVI<0x72940000>; 519def VMAXI_HU : LSX2RI5_VVI<0x72948000>; 520def VMAXI_WU : LSX2RI5_VVI<0x72950000>; 521def VMAXI_DU : LSX2RI5_VVI<0x72958000>; 522 523def VMIN_B : LSX3R_VVV<0x70720000>; 524def VMIN_H : LSX3R_VVV<0x70728000>; 525def VMIN_W : LSX3R_VVV<0x70730000>; 526def VMIN_D : LSX3R_VVV<0x70738000>; 527def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>; 528def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>; 529def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>; 530def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>; 531def VMIN_BU : LSX3R_VVV<0x70760000>; 532def VMIN_HU : LSX3R_VVV<0x70768000>; 533def VMIN_WU : LSX3R_VVV<0x70770000>; 534def VMIN_DU : LSX3R_VVV<0x70778000>; 535def VMINI_BU : LSX2RI5_VVI<0x72960000>; 536def VMINI_HU : LSX2RI5_VVI<0x72968000>; 537def VMINI_WU : LSX2RI5_VVI<0x72970000>; 538def VMINI_DU : LSX2RI5_VVI<0x72978000>; 539 540def VMUL_B : LSX3R_VVV<0x70840000>; 541def VMUL_H : LSX3R_VVV<0x70848000>; 542def VMUL_W : LSX3R_VVV<0x70850000>; 543def VMUL_D : LSX3R_VVV<0x70858000>; 544 545def VMUH_B : LSX3R_VVV<0x70860000>; 546def VMUH_H : LSX3R_VVV<0x70868000>; 547def VMUH_W : LSX3R_VVV<0x70870000>; 548def VMUH_D : LSX3R_VVV<0x70878000>; 549def VMUH_BU : LSX3R_VVV<0x70880000>; 550def VMUH_HU : LSX3R_VVV<0x70888000>; 551def VMUH_WU : LSX3R_VVV<0x70890000>; 552def VMUH_DU : LSX3R_VVV<0x70898000>; 553 554def VMULWEV_H_B : LSX3R_VVV<0x70900000>; 555def VMULWEV_W_H : LSX3R_VVV<0x70908000>; 556def VMULWEV_D_W : LSX3R_VVV<0x70910000>; 557def VMULWEV_Q_D : LSX3R_VVV<0x70918000>; 558def VMULWOD_H_B : LSX3R_VVV<0x70920000>; 559def VMULWOD_W_H : LSX3R_VVV<0x70928000>; 560def VMULWOD_D_W : LSX3R_VVV<0x70930000>; 561def VMULWOD_Q_D : LSX3R_VVV<0x70938000>; 562def VMULWEV_H_BU : LSX3R_VVV<0x70980000>; 563def VMULWEV_W_HU : LSX3R_VVV<0x70988000>; 564def VMULWEV_D_WU : LSX3R_VVV<0x70990000>; 565def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>; 566def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>; 567def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>; 568def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>; 569def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>; 570def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>; 571def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>; 572def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>; 573def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>; 574def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>; 575def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>; 576def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>; 577def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>; 578 579def VMADD_B : LSX3R_VVVV<0x70a80000>; 580def VMADD_H : LSX3R_VVVV<0x70a88000>; 581def VMADD_W : LSX3R_VVVV<0x70a90000>; 582def VMADD_D : LSX3R_VVVV<0x70a98000>; 583 584def VMSUB_B : LSX3R_VVVV<0x70aa0000>; 585def VMSUB_H : LSX3R_VVVV<0x70aa8000>; 586def VMSUB_W : LSX3R_VVVV<0x70ab0000>; 587def VMSUB_D : LSX3R_VVVV<0x70ab8000>; 588 589def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>; 590def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>; 591def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>; 592def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>; 593def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>; 594def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>; 595def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>; 596def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>; 597def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>; 598def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>; 599def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>; 600def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>; 601def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>; 602def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>; 603def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>; 604def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>; 605def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>; 606def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>; 607def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>; 608def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>; 609def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>; 610def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>; 611def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>; 612def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>; 613 614def VDIV_B : LSX3R_VVV<0x70e00000>; 615def VDIV_H : LSX3R_VVV<0x70e08000>; 616def VDIV_W : LSX3R_VVV<0x70e10000>; 617def VDIV_D : LSX3R_VVV<0x70e18000>; 618def VDIV_BU : LSX3R_VVV<0x70e40000>; 619def VDIV_HU : LSX3R_VVV<0x70e48000>; 620def VDIV_WU : LSX3R_VVV<0x70e50000>; 621def VDIV_DU : LSX3R_VVV<0x70e58000>; 622 623def VMOD_B : LSX3R_VVV<0x70e20000>; 624def VMOD_H : LSX3R_VVV<0x70e28000>; 625def VMOD_W : LSX3R_VVV<0x70e30000>; 626def VMOD_D : LSX3R_VVV<0x70e38000>; 627def VMOD_BU : LSX3R_VVV<0x70e60000>; 628def VMOD_HU : LSX3R_VVV<0x70e68000>; 629def VMOD_WU : LSX3R_VVV<0x70e70000>; 630def VMOD_DU : LSX3R_VVV<0x70e78000>; 631 632def VSAT_B : LSX2RI3_VVI<0x73242000>; 633def VSAT_H : LSX2RI4_VVI<0x73244000>; 634def VSAT_W : LSX2RI5_VVI<0x73248000>; 635def VSAT_D : LSX2RI6_VVI<0x73250000>; 636def VSAT_BU : LSX2RI3_VVI<0x73282000>; 637def VSAT_HU : LSX2RI4_VVI<0x73284000>; 638def VSAT_WU : LSX2RI5_VVI<0x73288000>; 639def VSAT_DU : LSX2RI6_VVI<0x73290000>; 640 641def VEXTH_H_B : LSX2R_VV<0x729ee000>; 642def VEXTH_W_H : LSX2R_VV<0x729ee400>; 643def VEXTH_D_W : LSX2R_VV<0x729ee800>; 644def VEXTH_Q_D : LSX2R_VV<0x729eec00>; 645def VEXTH_HU_BU : LSX2R_VV<0x729ef000>; 646def VEXTH_WU_HU : LSX2R_VV<0x729ef400>; 647def VEXTH_DU_WU : LSX2R_VV<0x729ef800>; 648def VEXTH_QU_DU : LSX2R_VV<0x729efc00>; 649 650def VSIGNCOV_B : LSX3R_VVV<0x712e0000>; 651def VSIGNCOV_H : LSX3R_VVV<0x712e8000>; 652def VSIGNCOV_W : LSX3R_VVV<0x712f0000>; 653def VSIGNCOV_D : LSX3R_VVV<0x712f8000>; 654 655def VMSKLTZ_B : LSX2R_VV<0x729c4000>; 656def VMSKLTZ_H : LSX2R_VV<0x729c4400>; 657def VMSKLTZ_W : LSX2R_VV<0x729c4800>; 658def VMSKLTZ_D : LSX2R_VV<0x729c4c00>; 659 660def VMSKGEZ_B : LSX2R_VV<0x729c5000>; 661 662def VMSKNZ_B : LSX2R_VV<0x729c6000>; 663 664def VLDI : LSX1RI13_VI<0x73e00000>; 665 666def VAND_V : LSX3R_VVV<0x71260000>; 667def VOR_V : LSX3R_VVV<0x71268000>; 668def VXOR_V : LSX3R_VVV<0x71270000>; 669def VNOR_V : LSX3R_VVV<0x71278000>; 670def VANDN_V : LSX3R_VVV<0x71280000>; 671def VORN_V : LSX3R_VVV<0x71288000>; 672 673def VANDI_B : LSX2RI8_VVI<0x73d00000>; 674def VORI_B : LSX2RI8_VVI<0x73d40000>; 675def VXORI_B : LSX2RI8_VVI<0x73d80000>; 676def VNORI_B : LSX2RI8_VVI<0x73dc0000>; 677 678def VSLL_B : LSX3R_VVV<0x70e80000>; 679def VSLL_H : LSX3R_VVV<0x70e88000>; 680def VSLL_W : LSX3R_VVV<0x70e90000>; 681def VSLL_D : LSX3R_VVV<0x70e98000>; 682def VSLLI_B : LSX2RI3_VVI<0x732c2000>; 683def VSLLI_H : LSX2RI4_VVI<0x732c4000>; 684def VSLLI_W : LSX2RI5_VVI<0x732c8000>; 685def VSLLI_D : LSX2RI6_VVI<0x732d0000>; 686 687def VSRL_B : LSX3R_VVV<0x70ea0000>; 688def VSRL_H : LSX3R_VVV<0x70ea8000>; 689def VSRL_W : LSX3R_VVV<0x70eb0000>; 690def VSRL_D : LSX3R_VVV<0x70eb8000>; 691def VSRLI_B : LSX2RI3_VVI<0x73302000>; 692def VSRLI_H : LSX2RI4_VVI<0x73304000>; 693def VSRLI_W : LSX2RI5_VVI<0x73308000>; 694def VSRLI_D : LSX2RI6_VVI<0x73310000>; 695 696def VSRA_B : LSX3R_VVV<0x70ec0000>; 697def VSRA_H : LSX3R_VVV<0x70ec8000>; 698def VSRA_W : LSX3R_VVV<0x70ed0000>; 699def VSRA_D : LSX3R_VVV<0x70ed8000>; 700def VSRAI_B : LSX2RI3_VVI<0x73342000>; 701def VSRAI_H : LSX2RI4_VVI<0x73344000>; 702def VSRAI_W : LSX2RI5_VVI<0x73348000>; 703def VSRAI_D : LSX2RI6_VVI<0x73350000>; 704 705def VROTR_B : LSX3R_VVV<0x70ee0000>; 706def VROTR_H : LSX3R_VVV<0x70ee8000>; 707def VROTR_W : LSX3R_VVV<0x70ef0000>; 708def VROTR_D : LSX3R_VVV<0x70ef8000>; 709def VROTRI_B : LSX2RI3_VVI<0x72a02000>; 710def VROTRI_H : LSX2RI4_VVI<0x72a04000>; 711def VROTRI_W : LSX2RI5_VVI<0x72a08000>; 712def VROTRI_D : LSX2RI6_VVI<0x72a10000>; 713 714def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>; 715def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>; 716def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>; 717def VEXTL_Q_D : LSX2R_VV<0x73090000>; 718def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>; 719def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>; 720def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>; 721def VEXTL_QU_DU : LSX2R_VV<0x730d0000>; 722 723def VSRLR_B : LSX3R_VVV<0x70f00000>; 724def VSRLR_H : LSX3R_VVV<0x70f08000>; 725def VSRLR_W : LSX3R_VVV<0x70f10000>; 726def VSRLR_D : LSX3R_VVV<0x70f18000>; 727def VSRLRI_B : LSX2RI3_VVI<0x72a42000>; 728def VSRLRI_H : LSX2RI4_VVI<0x72a44000>; 729def VSRLRI_W : LSX2RI5_VVI<0x72a48000>; 730def VSRLRI_D : LSX2RI6_VVI<0x72a50000>; 731 732def VSRAR_B : LSX3R_VVV<0x70f20000>; 733def VSRAR_H : LSX3R_VVV<0x70f28000>; 734def VSRAR_W : LSX3R_VVV<0x70f30000>; 735def VSRAR_D : LSX3R_VVV<0x70f38000>; 736def VSRARI_B : LSX2RI3_VVI<0x72a82000>; 737def VSRARI_H : LSX2RI4_VVI<0x72a84000>; 738def VSRARI_W : LSX2RI5_VVI<0x72a88000>; 739def VSRARI_D : LSX2RI6_VVI<0x72a90000>; 740 741def VSRLN_B_H : LSX3R_VVV<0x70f48000>; 742def VSRLN_H_W : LSX3R_VVV<0x70f50000>; 743def VSRLN_W_D : LSX3R_VVV<0x70f58000>; 744def VSRAN_B_H : LSX3R_VVV<0x70f68000>; 745def VSRAN_H_W : LSX3R_VVV<0x70f70000>; 746def VSRAN_W_D : LSX3R_VVV<0x70f78000>; 747 748def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>; 749def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>; 750def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>; 751def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>; 752def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>; 753def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>; 754def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>; 755def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>; 756 757def VSRLRN_B_H : LSX3R_VVV<0x70f88000>; 758def VSRLRN_H_W : LSX3R_VVV<0x70f90000>; 759def VSRLRN_W_D : LSX3R_VVV<0x70f98000>; 760def VSRARN_B_H : LSX3R_VVV<0x70fa8000>; 761def VSRARN_H_W : LSX3R_VVV<0x70fb0000>; 762def VSRARN_W_D : LSX3R_VVV<0x70fb8000>; 763 764def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>; 765def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>; 766def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>; 767def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>; 768def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>; 769def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>; 770def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>; 771def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>; 772 773def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>; 774def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>; 775def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>; 776def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>; 777def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>; 778def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>; 779def VSSRLN_BU_H : LSX3R_VVV<0x71048000>; 780def VSSRLN_HU_W : LSX3R_VVV<0x71050000>; 781def VSSRLN_WU_D : LSX3R_VVV<0x71058000>; 782def VSSRAN_BU_H : LSX3R_VVV<0x71068000>; 783def VSSRAN_HU_W : LSX3R_VVV<0x71070000>; 784def VSSRAN_WU_D : LSX3R_VVV<0x71078000>; 785 786def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>; 787def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>; 788def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>; 789def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>; 790def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>; 791def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>; 792def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>; 793def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>; 794def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>; 795def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>; 796def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>; 797def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>; 798def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>; 799def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>; 800def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>; 801def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>; 802 803def VSSRLRN_B_H : LSX3R_VVV<0x71008000>; 804def VSSRLRN_H_W : LSX3R_VVV<0x71010000>; 805def VSSRLRN_W_D : LSX3R_VVV<0x71018000>; 806def VSSRARN_B_H : LSX3R_VVV<0x71028000>; 807def VSSRARN_H_W : LSX3R_VVV<0x71030000>; 808def VSSRARN_W_D : LSX3R_VVV<0x71038000>; 809def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>; 810def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>; 811def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>; 812def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>; 813def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>; 814def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>; 815 816def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>; 817def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>; 818def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>; 819def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>; 820def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>; 821def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>; 822def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>; 823def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>; 824def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>; 825def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>; 826def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>; 827def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>; 828def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>; 829def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>; 830def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>; 831def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>; 832 833def VCLO_B : LSX2R_VV<0x729c0000>; 834def VCLO_H : LSX2R_VV<0x729c0400>; 835def VCLO_W : LSX2R_VV<0x729c0800>; 836def VCLO_D : LSX2R_VV<0x729c0c00>; 837def VCLZ_B : LSX2R_VV<0x729c1000>; 838def VCLZ_H : LSX2R_VV<0x729c1400>; 839def VCLZ_W : LSX2R_VV<0x729c1800>; 840def VCLZ_D : LSX2R_VV<0x729c1c00>; 841 842def VPCNT_B : LSX2R_VV<0x729c2000>; 843def VPCNT_H : LSX2R_VV<0x729c2400>; 844def VPCNT_W : LSX2R_VV<0x729c2800>; 845def VPCNT_D : LSX2R_VV<0x729c2c00>; 846 847def VBITCLR_B : LSX3R_VVV<0x710c0000>; 848def VBITCLR_H : LSX3R_VVV<0x710c8000>; 849def VBITCLR_W : LSX3R_VVV<0x710d0000>; 850def VBITCLR_D : LSX3R_VVV<0x710d8000>; 851def VBITCLRI_B : LSX2RI3_VVI<0x73102000>; 852def VBITCLRI_H : LSX2RI4_VVI<0x73104000>; 853def VBITCLRI_W : LSX2RI5_VVI<0x73108000>; 854def VBITCLRI_D : LSX2RI6_VVI<0x73110000>; 855 856def VBITSET_B : LSX3R_VVV<0x710e0000>; 857def VBITSET_H : LSX3R_VVV<0x710e8000>; 858def VBITSET_W : LSX3R_VVV<0x710f0000>; 859def VBITSET_D : LSX3R_VVV<0x710f8000>; 860def VBITSETI_B : LSX2RI3_VVI<0x73142000>; 861def VBITSETI_H : LSX2RI4_VVI<0x73144000>; 862def VBITSETI_W : LSX2RI5_VVI<0x73148000>; 863def VBITSETI_D : LSX2RI6_VVI<0x73150000>; 864 865def VBITREV_B : LSX3R_VVV<0x71100000>; 866def VBITREV_H : LSX3R_VVV<0x71108000>; 867def VBITREV_W : LSX3R_VVV<0x71110000>; 868def VBITREV_D : LSX3R_VVV<0x71118000>; 869def VBITREVI_B : LSX2RI3_VVI<0x73182000>; 870def VBITREVI_H : LSX2RI4_VVI<0x73184000>; 871def VBITREVI_W : LSX2RI5_VVI<0x73188000>; 872def VBITREVI_D : LSX2RI6_VVI<0x73190000>; 873 874def VFRSTP_B : LSX3R_VVVV<0x712b0000>; 875def VFRSTP_H : LSX3R_VVVV<0x712b8000>; 876def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>; 877def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>; 878 879def VFADD_S : LSX3R_VVV<0x71308000>; 880def VFADD_D : LSX3R_VVV<0x71310000>; 881def VFSUB_S : LSX3R_VVV<0x71328000>; 882def VFSUB_D : LSX3R_VVV<0x71330000>; 883def VFMUL_S : LSX3R_VVV<0x71388000>; 884def VFMUL_D : LSX3R_VVV<0x71390000>; 885def VFDIV_S : LSX3R_VVV<0x713a8000>; 886def VFDIV_D : LSX3R_VVV<0x713b0000>; 887 888def VFMADD_S : LSX4R_VVVV<0x09100000>; 889def VFMADD_D : LSX4R_VVVV<0x09200000>; 890def VFMSUB_S : LSX4R_VVVV<0x09500000>; 891def VFMSUB_D : LSX4R_VVVV<0x09600000>; 892def VFNMADD_S : LSX4R_VVVV<0x09900000>; 893def VFNMADD_D : LSX4R_VVVV<0x09a00000>; 894def VFNMSUB_S : LSX4R_VVVV<0x09d00000>; 895def VFNMSUB_D : LSX4R_VVVV<0x09e00000>; 896 897def VFMAX_S : LSX3R_VVV<0x713c8000>; 898def VFMAX_D : LSX3R_VVV<0x713d0000>; 899def VFMIN_S : LSX3R_VVV<0x713e8000>; 900def VFMIN_D : LSX3R_VVV<0x713f0000>; 901 902def VFMAXA_S : LSX3R_VVV<0x71408000>; 903def VFMAXA_D : LSX3R_VVV<0x71410000>; 904def VFMINA_S : LSX3R_VVV<0x71428000>; 905def VFMINA_D : LSX3R_VVV<0x71430000>; 906 907def VFLOGB_S : LSX2R_VV<0x729cc400>; 908def VFLOGB_D : LSX2R_VV<0x729cc800>; 909 910def VFCLASS_S : LSX2R_VV<0x729cd400>; 911def VFCLASS_D : LSX2R_VV<0x729cd800>; 912 913def VFSQRT_S : LSX2R_VV<0x729ce400>; 914def VFSQRT_D : LSX2R_VV<0x729ce800>; 915def VFRECIP_S : LSX2R_VV<0x729cf400>; 916def VFRECIP_D : LSX2R_VV<0x729cf800>; 917def VFRSQRT_S : LSX2R_VV<0x729d0400>; 918def VFRSQRT_D : LSX2R_VV<0x729d0800>; 919def VFRECIPE_S : LSX2R_VV<0x729d1400>; 920def VFRECIPE_D : LSX2R_VV<0x729d1800>; 921def VFRSQRTE_S : LSX2R_VV<0x729d2400>; 922def VFRSQRTE_D : LSX2R_VV<0x729d2800>; 923 924def VFCVTL_S_H : LSX2R_VV<0x729de800>; 925def VFCVTH_S_H : LSX2R_VV<0x729dec00>; 926def VFCVTL_D_S : LSX2R_VV<0x729df000>; 927def VFCVTH_D_S : LSX2R_VV<0x729df400>; 928def VFCVT_H_S : LSX3R_VVV<0x71460000>; 929def VFCVT_S_D : LSX3R_VVV<0x71468000>; 930 931def VFRINTRNE_S : LSX2R_VV<0x729d7400>; 932def VFRINTRNE_D : LSX2R_VV<0x729d7800>; 933def VFRINTRZ_S : LSX2R_VV<0x729d6400>; 934def VFRINTRZ_D : LSX2R_VV<0x729d6800>; 935def VFRINTRP_S : LSX2R_VV<0x729d5400>; 936def VFRINTRP_D : LSX2R_VV<0x729d5800>; 937def VFRINTRM_S : LSX2R_VV<0x729d4400>; 938def VFRINTRM_D : LSX2R_VV<0x729d4800>; 939def VFRINT_S : LSX2R_VV<0x729d3400>; 940def VFRINT_D : LSX2R_VV<0x729d3800>; 941 942def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>; 943def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>; 944def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>; 945def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>; 946def VFTINTRP_W_S : LSX2R_VV<0x729e4000>; 947def VFTINTRP_L_D : LSX2R_VV<0x729e4400>; 948def VFTINTRM_W_S : LSX2R_VV<0x729e3800>; 949def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>; 950def VFTINT_W_S : LSX2R_VV<0x729e3000>; 951def VFTINT_L_D : LSX2R_VV<0x729e3400>; 952def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>; 953def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>; 954def VFTINT_WU_S : LSX2R_VV<0x729e5800>; 955def VFTINT_LU_D : LSX2R_VV<0x729e5c00>; 956 957def VFTINTRNE_W_D : LSX3R_VVV<0x714b8000>; 958def VFTINTRZ_W_D : LSX3R_VVV<0x714b0000>; 959def VFTINTRP_W_D : LSX3R_VVV<0x714a8000>; 960def VFTINTRM_W_D : LSX3R_VVV<0x714a0000>; 961def VFTINT_W_D : LSX3R_VVV<0x71498000>; 962 963def VFTINTRNEL_L_S : LSX2R_VV<0x729ea000>; 964def VFTINTRNEH_L_S : LSX2R_VV<0x729ea400>; 965def VFTINTRZL_L_S : LSX2R_VV<0x729e9800>; 966def VFTINTRZH_L_S : LSX2R_VV<0x729e9c00>; 967def VFTINTRPL_L_S : LSX2R_VV<0x729e9000>; 968def VFTINTRPH_L_S : LSX2R_VV<0x729e9400>; 969def VFTINTRML_L_S : LSX2R_VV<0x729e8800>; 970def VFTINTRMH_L_S : LSX2R_VV<0x729e8c00>; 971def VFTINTL_L_S : LSX2R_VV<0x729e8000>; 972def VFTINTH_L_S : LSX2R_VV<0x729e8400>; 973 974def VFFINT_S_W : LSX2R_VV<0x729e0000>; 975def VFFINT_D_L : LSX2R_VV<0x729e0800>; 976def VFFINT_S_WU : LSX2R_VV<0x729e0400>; 977def VFFINT_D_LU : LSX2R_VV<0x729e0c00>; 978def VFFINTL_D_W : LSX2R_VV<0x729e1000>; 979def VFFINTH_D_W : LSX2R_VV<0x729e1400>; 980def VFFINT_S_L : LSX3R_VVV<0x71480000>; 981 982def VSEQ_B : LSX3R_VVV<0x70000000>; 983def VSEQ_H : LSX3R_VVV<0x70008000>; 984def VSEQ_W : LSX3R_VVV<0x70010000>; 985def VSEQ_D : LSX3R_VVV<0x70018000>; 986def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>; 987def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>; 988def VSEQI_W : LSX2RI5_VVI<0x72810000, simm5>; 989def VSEQI_D : LSX2RI5_VVI<0x72818000, simm5>; 990 991def VSLE_B : LSX3R_VVV<0x70020000>; 992def VSLE_H : LSX3R_VVV<0x70028000>; 993def VSLE_W : LSX3R_VVV<0x70030000>; 994def VSLE_D : LSX3R_VVV<0x70038000>; 995def VSLEI_B : LSX2RI5_VVI<0x72820000, simm5>; 996def VSLEI_H : LSX2RI5_VVI<0x72828000, simm5>; 997def VSLEI_W : LSX2RI5_VVI<0x72830000, simm5>; 998def VSLEI_D : LSX2RI5_VVI<0x72838000, simm5>; 999 1000def VSLE_BU : LSX3R_VVV<0x70040000>; 1001def VSLE_HU : LSX3R_VVV<0x70048000>; 1002def VSLE_WU : LSX3R_VVV<0x70050000>; 1003def VSLE_DU : LSX3R_VVV<0x70058000>; 1004def VSLEI_BU : LSX2RI5_VVI<0x72840000>; 1005def VSLEI_HU : LSX2RI5_VVI<0x72848000>; 1006def VSLEI_WU : LSX2RI5_VVI<0x72850000>; 1007def VSLEI_DU : LSX2RI5_VVI<0x72858000>; 1008 1009def VSLT_B : LSX3R_VVV<0x70060000>; 1010def VSLT_H : LSX3R_VVV<0x70068000>; 1011def VSLT_W : LSX3R_VVV<0x70070000>; 1012def VSLT_D : LSX3R_VVV<0x70078000>; 1013def VSLTI_B : LSX2RI5_VVI<0x72860000, simm5>; 1014def VSLTI_H : LSX2RI5_VVI<0x72868000, simm5>; 1015def VSLTI_W : LSX2RI5_VVI<0x72870000, simm5>; 1016def VSLTI_D : LSX2RI5_VVI<0x72878000, simm5>; 1017 1018def VSLT_BU : LSX3R_VVV<0x70080000>; 1019def VSLT_HU : LSX3R_VVV<0x70088000>; 1020def VSLT_WU : LSX3R_VVV<0x70090000>; 1021def VSLT_DU : LSX3R_VVV<0x70098000>; 1022def VSLTI_BU : LSX2RI5_VVI<0x72880000>; 1023def VSLTI_HU : LSX2RI5_VVI<0x72888000>; 1024def VSLTI_WU : LSX2RI5_VVI<0x72890000>; 1025def VSLTI_DU : LSX2RI5_VVI<0x72898000>; 1026 1027def VFCMP_CAF_S : LSX3R_VVV<0x0c500000>; 1028def VFCMP_SAF_S : LSX3R_VVV<0x0c508000>; 1029def VFCMP_CLT_S : LSX3R_VVV<0x0c510000>; 1030def VFCMP_SLT_S : LSX3R_VVV<0x0c518000>; 1031def VFCMP_CEQ_S : LSX3R_VVV<0x0c520000>; 1032def VFCMP_SEQ_S : LSX3R_VVV<0x0c528000>; 1033def VFCMP_CLE_S : LSX3R_VVV<0x0c530000>; 1034def VFCMP_SLE_S : LSX3R_VVV<0x0c538000>; 1035def VFCMP_CUN_S : LSX3R_VVV<0x0c540000>; 1036def VFCMP_SUN_S : LSX3R_VVV<0x0c548000>; 1037def VFCMP_CULT_S : LSX3R_VVV<0x0c550000>; 1038def VFCMP_SULT_S : LSX3R_VVV<0x0c558000>; 1039def VFCMP_CUEQ_S : LSX3R_VVV<0x0c560000>; 1040def VFCMP_SUEQ_S : LSX3R_VVV<0x0c568000>; 1041def VFCMP_CULE_S : LSX3R_VVV<0x0c570000>; 1042def VFCMP_SULE_S : LSX3R_VVV<0x0c578000>; 1043def VFCMP_CNE_S : LSX3R_VVV<0x0c580000>; 1044def VFCMP_SNE_S : LSX3R_VVV<0x0c588000>; 1045def VFCMP_COR_S : LSX3R_VVV<0x0c5a0000>; 1046def VFCMP_SOR_S : LSX3R_VVV<0x0c5a8000>; 1047def VFCMP_CUNE_S : LSX3R_VVV<0x0c5c0000>; 1048def VFCMP_SUNE_S : LSX3R_VVV<0x0c5c8000>; 1049 1050def VFCMP_CAF_D : LSX3R_VVV<0x0c600000>; 1051def VFCMP_SAF_D : LSX3R_VVV<0x0c608000>; 1052def VFCMP_CLT_D : LSX3R_VVV<0x0c610000>; 1053def VFCMP_SLT_D : LSX3R_VVV<0x0c618000>; 1054def VFCMP_CEQ_D : LSX3R_VVV<0x0c620000>; 1055def VFCMP_SEQ_D : LSX3R_VVV<0x0c628000>; 1056def VFCMP_CLE_D : LSX3R_VVV<0x0c630000>; 1057def VFCMP_SLE_D : LSX3R_VVV<0x0c638000>; 1058def VFCMP_CUN_D : LSX3R_VVV<0x0c640000>; 1059def VFCMP_SUN_D : LSX3R_VVV<0x0c648000>; 1060def VFCMP_CULT_D : LSX3R_VVV<0x0c650000>; 1061def VFCMP_SULT_D : LSX3R_VVV<0x0c658000>; 1062def VFCMP_CUEQ_D : LSX3R_VVV<0x0c660000>; 1063def VFCMP_SUEQ_D : LSX3R_VVV<0x0c668000>; 1064def VFCMP_CULE_D : LSX3R_VVV<0x0c670000>; 1065def VFCMP_SULE_D : LSX3R_VVV<0x0c678000>; 1066def VFCMP_CNE_D : LSX3R_VVV<0x0c680000>; 1067def VFCMP_SNE_D : LSX3R_VVV<0x0c688000>; 1068def VFCMP_COR_D : LSX3R_VVV<0x0c6a0000>; 1069def VFCMP_SOR_D : LSX3R_VVV<0x0c6a8000>; 1070def VFCMP_CUNE_D : LSX3R_VVV<0x0c6c0000>; 1071def VFCMP_SUNE_D : LSX3R_VVV<0x0c6c8000>; 1072 1073def VBITSEL_V : LSX4R_VVVV<0x0d100000>; 1074 1075def VBITSELI_B : LSX2RI8_VVVI<0x73c40000>; 1076 1077def VSETEQZ_V : LSX2R_CV<0x729c9800>; 1078def VSETNEZ_V : LSX2R_CV<0x729c9c00>; 1079def VSETANYEQZ_B : LSX2R_CV<0x729ca000>; 1080def VSETANYEQZ_H : LSX2R_CV<0x729ca400>; 1081def VSETANYEQZ_W : LSX2R_CV<0x729ca800>; 1082def VSETANYEQZ_D : LSX2R_CV<0x729cac00>; 1083def VSETALLNEZ_B : LSX2R_CV<0x729cb000>; 1084def VSETALLNEZ_H : LSX2R_CV<0x729cb400>; 1085def VSETALLNEZ_W : LSX2R_CV<0x729cb800>; 1086def VSETALLNEZ_D : LSX2R_CV<0x729cbc00>; 1087 1088def VINSGR2VR_B : LSX2RI4_VVRI<0x72eb8000>; 1089def VINSGR2VR_H : LSX2RI3_VVRI<0x72ebc000>; 1090def VINSGR2VR_W : LSX2RI2_VVRI<0x72ebe000>; 1091def VINSGR2VR_D : LSX2RI1_VVRI<0x72ebf000>; 1092def VPICKVE2GR_B : LSX2RI4_RVI<0x72ef8000>; 1093def VPICKVE2GR_H : LSX2RI3_RVI<0x72efc000>; 1094def VPICKVE2GR_W : LSX2RI2_RVI<0x72efe000>; 1095def VPICKVE2GR_D : LSX2RI1_RVI<0x72eff000>; 1096def VPICKVE2GR_BU : LSX2RI4_RVI<0x72f38000>; 1097def VPICKVE2GR_HU : LSX2RI3_RVI<0x72f3c000>; 1098def VPICKVE2GR_WU : LSX2RI2_RVI<0x72f3e000>; 1099def VPICKVE2GR_DU : LSX2RI1_RVI<0x72f3f000>; 1100 1101def VREPLGR2VR_B : LSX2R_VR<0x729f0000>; 1102def VREPLGR2VR_H : LSX2R_VR<0x729f0400>; 1103def VREPLGR2VR_W : LSX2R_VR<0x729f0800>; 1104def VREPLGR2VR_D : LSX2R_VR<0x729f0c00>; 1105 1106def VREPLVE_B : LSX3R_VVR<0x71220000>; 1107def VREPLVE_H : LSX3R_VVR<0x71228000>; 1108def VREPLVE_W : LSX3R_VVR<0x71230000>; 1109def VREPLVE_D : LSX3R_VVR<0x71238000>; 1110def VREPLVEI_B : LSX2RI4_VVI<0x72f78000>; 1111def VREPLVEI_H : LSX2RI3_VVI<0x72f7c000>; 1112def VREPLVEI_W : LSX2RI2_VVI<0x72f7e000>; 1113def VREPLVEI_D : LSX2RI1_VVI<0x72f7f000>; 1114 1115def VBSLL_V : LSX2RI5_VVI<0x728e0000>; 1116def VBSRL_V : LSX2RI5_VVI<0x728e8000>; 1117 1118def VPACKEV_B : LSX3R_VVV<0x71160000>; 1119def VPACKEV_H : LSX3R_VVV<0x71168000>; 1120def VPACKEV_W : LSX3R_VVV<0x71170000>; 1121def VPACKEV_D : LSX3R_VVV<0x71178000>; 1122def VPACKOD_B : LSX3R_VVV<0x71180000>; 1123def VPACKOD_H : LSX3R_VVV<0x71188000>; 1124def VPACKOD_W : LSX3R_VVV<0x71190000>; 1125def VPACKOD_D : LSX3R_VVV<0x71198000>; 1126 1127def VPICKEV_B : LSX3R_VVV<0x711e0000>; 1128def VPICKEV_H : LSX3R_VVV<0x711e8000>; 1129def VPICKEV_W : LSX3R_VVV<0x711f0000>; 1130def VPICKEV_D : LSX3R_VVV<0x711f8000>; 1131def VPICKOD_B : LSX3R_VVV<0x71200000>; 1132def VPICKOD_H : LSX3R_VVV<0x71208000>; 1133def VPICKOD_W : LSX3R_VVV<0x71210000>; 1134def VPICKOD_D : LSX3R_VVV<0x71218000>; 1135 1136def VILVL_B : LSX3R_VVV<0x711a0000>; 1137def VILVL_H : LSX3R_VVV<0x711a8000>; 1138def VILVL_W : LSX3R_VVV<0x711b0000>; 1139def VILVL_D : LSX3R_VVV<0x711b8000>; 1140def VILVH_B : LSX3R_VVV<0x711c0000>; 1141def VILVH_H : LSX3R_VVV<0x711c8000>; 1142def VILVH_W : LSX3R_VVV<0x711d0000>; 1143def VILVH_D : LSX3R_VVV<0x711d8000>; 1144 1145def VSHUF_B : LSX4R_VVVV<0x0d500000>; 1146 1147def VSHUF_H : LSX3R_VVVV<0x717a8000>; 1148def VSHUF_W : LSX3R_VVVV<0x717b0000>; 1149def VSHUF_D : LSX3R_VVVV<0x717b8000>; 1150 1151def VSHUF4I_B : LSX2RI8_VVI<0x73900000>; 1152def VSHUF4I_H : LSX2RI8_VVI<0x73940000>; 1153def VSHUF4I_W : LSX2RI8_VVI<0x73980000>; 1154def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>; 1155 1156def VPERMI_W : LSX2RI8_VVVI<0x73e40000>; 1157 1158def VEXTRINS_D : LSX2RI8_VVVI<0x73800000>; 1159def VEXTRINS_W : LSX2RI8_VVVI<0x73840000>; 1160def VEXTRINS_H : LSX2RI8_VVVI<0x73880000>; 1161def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>; 1162} // mayLoad = 0, mayStore = 0 1163 1164let mayLoad = 1, mayStore = 0 in { 1165def VLD : LSX2RI12_Load<0x2c000000>; 1166def VLDX : LSX3R_Load<0x38400000>; 1167 1168def VLDREPL_B : LSX2RI12_Load<0x30800000>; 1169def VLDREPL_H : LSX2RI11_Load<0x30400000>; 1170def VLDREPL_W : LSX2RI10_Load<0x30200000>; 1171def VLDREPL_D : LSX2RI9_Load<0x30100000>; 1172} // mayLoad = 1, mayStore = 0 1173 1174let mayLoad = 0, mayStore = 1 in { 1175def VST : LSX2RI12_Store<0x2c400000>; 1176def VSTX : LSX3R_Store<0x38440000>; 1177 1178def VSTELM_B : LSX2RI8I4_VRII<0x31800000>; 1179def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>; 1180def VSTELM_W : LSX2RI8I2_VRII<0x31200000, simm8_lsl2>; 1181def VSTELM_D : LSX2RI8I1_VRII<0x31100000, simm8_lsl3>; 1182} // mayLoad = 0, mayStore = 1 1183 1184} // hasSideEffects = 0, Predicates = [HasExtLSX] 1185 1186/// Pseudo-instructions 1187 1188let Predicates = [HasExtLSX] in { 1189 1190let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, 1191 isAsmParserOnly = 1 in { 1192def PseudoVREPLI_B : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1193 "vrepli.b", "$vd, $imm">; 1194def PseudoVREPLI_H : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1195 "vrepli.h", "$vd, $imm">; 1196def PseudoVREPLI_W : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1197 "vrepli.w", "$vd, $imm">; 1198def PseudoVREPLI_D : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1199 "vrepli.d", "$vd, $imm">; 1200} 1201 1202def PseudoVBNZ_B : VecCond<loongarch_vall_nonzero, v16i8>; 1203def PseudoVBNZ_H : VecCond<loongarch_vall_nonzero, v8i16>; 1204def PseudoVBNZ_W : VecCond<loongarch_vall_nonzero, v4i32>; 1205def PseudoVBNZ_D : VecCond<loongarch_vall_nonzero, v2i64>; 1206def PseudoVBNZ : VecCond<loongarch_vany_nonzero, v16i8>; 1207 1208def PseudoVBZ_B : VecCond<loongarch_vall_zero, v16i8>; 1209def PseudoVBZ_H : VecCond<loongarch_vall_zero, v8i16>; 1210def PseudoVBZ_W : VecCond<loongarch_vall_zero, v4i32>; 1211def PseudoVBZ_D : VecCond<loongarch_vall_zero, v2i64>; 1212def PseudoVBZ : VecCond<loongarch_vany_zero, v16i8>; 1213 1214} // Predicates = [HasExtLSX] 1215 1216multiclass PatVr<SDPatternOperator OpNode, string Inst> { 1217 def : Pat<(v16i8 (OpNode (v16i8 LSX128:$vj))), 1218 (!cast<LAInst>(Inst#"_B") LSX128:$vj)>; 1219 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))), 1220 (!cast<LAInst>(Inst#"_H") LSX128:$vj)>; 1221 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))), 1222 (!cast<LAInst>(Inst#"_W") LSX128:$vj)>; 1223 def : Pat<(v2i64 (OpNode (v2i64 LSX128:$vj))), 1224 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1225} 1226 1227multiclass PatVrF<SDPatternOperator OpNode, string Inst> { 1228 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))), 1229 (!cast<LAInst>(Inst#"_S") LSX128:$vj)>; 1230 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))), 1231 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1232} 1233 1234multiclass PatVrVr<SDPatternOperator OpNode, string Inst> { 1235 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1236 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1237 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1238 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1239 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1240 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1241 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1242 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1243} 1244 1245multiclass PatVrVrF<SDPatternOperator OpNode, string Inst> { 1246 def : Pat<(OpNode (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 1247 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1248 def : Pat<(OpNode (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 1249 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1250} 1251 1252multiclass PatVrVrU<SDPatternOperator OpNode, string Inst> { 1253 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1254 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1255 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1256 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1257 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1258 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1259 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1260 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1261} 1262 1263multiclass PatVrSimm5<SDPatternOperator OpNode, string Inst> { 1264 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_simm5 simm5:$imm))), 1265 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1266 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_simm5 simm5:$imm))), 1267 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1268 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_simm5 simm5:$imm))), 1269 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1270 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_simm5 simm5:$imm))), 1271 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1272} 1273 1274multiclass PatVrUimm5<SDPatternOperator OpNode, string Inst> { 1275 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm5 uimm5:$imm))), 1276 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1277 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm5 uimm5:$imm))), 1278 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1279 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1280 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1281 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm5 uimm5:$imm))), 1282 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1283} 1284 1285multiclass PatVrVrVr<SDPatternOperator OpNode, string Inst> { 1286 def : Pat<(OpNode (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1287 (!cast<LAInst>(Inst#"_B") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1288 def : Pat<(OpNode (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1289 (!cast<LAInst>(Inst#"_H") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1290 def : Pat<(OpNode (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1291 (!cast<LAInst>(Inst#"_W") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1292 def : Pat<(OpNode (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1293 (!cast<LAInst>(Inst#"_D") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1294} 1295 1296multiclass PatShiftVrVr<SDPatternOperator OpNode, string Inst> { 1297 def : Pat<(OpNode (v16i8 LSX128:$vj), (and vsplati8_imm_eq_7, 1298 (v16i8 LSX128:$vk))), 1299 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1300 def : Pat<(OpNode (v8i16 LSX128:$vj), (and vsplati16_imm_eq_15, 1301 (v8i16 LSX128:$vk))), 1302 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1303 def : Pat<(OpNode (v4i32 LSX128:$vj), (and vsplati32_imm_eq_31, 1304 (v4i32 LSX128:$vk))), 1305 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1306 def : Pat<(OpNode (v2i64 LSX128:$vj), (and vsplati64_imm_eq_63, 1307 (v2i64 LSX128:$vk))), 1308 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1309} 1310 1311multiclass PatShiftVrUimm<SDPatternOperator OpNode, string Inst> { 1312 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm3 uimm3:$imm))), 1313 (!cast<LAInst>(Inst#"_B") LSX128:$vj, uimm3:$imm)>; 1314 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm4 uimm4:$imm))), 1315 (!cast<LAInst>(Inst#"_H") LSX128:$vj, uimm4:$imm)>; 1316 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1317 (!cast<LAInst>(Inst#"_W") LSX128:$vj, uimm5:$imm)>; 1318 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm6 uimm6:$imm))), 1319 (!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>; 1320} 1321 1322multiclass PatCCVrSimm5<CondCode CC, string Inst> { 1323 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1324 (v16i8 (SplatPat_simm5 simm5:$imm)), CC)), 1325 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1326 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1327 (v8i16 (SplatPat_simm5 simm5:$imm)), CC)), 1328 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1329 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1330 (v4i32 (SplatPat_simm5 simm5:$imm)), CC)), 1331 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1332 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1333 (v2i64 (SplatPat_simm5 simm5:$imm)), CC)), 1334 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1335} 1336 1337multiclass PatCCVrUimm5<CondCode CC, string Inst> { 1338 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1339 (v16i8 (SplatPat_uimm5 uimm5:$imm)), CC)), 1340 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1341 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1342 (v8i16 (SplatPat_uimm5 uimm5:$imm)), CC)), 1343 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1344 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1345 (v4i32 (SplatPat_uimm5 uimm5:$imm)), CC)), 1346 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1347 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1348 (v2i64 (SplatPat_uimm5 uimm5:$imm)), CC)), 1349 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1350} 1351 1352multiclass PatCCVrVr<CondCode CC, string Inst> { 1353 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1354 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1355 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1356 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1357 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1358 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1359 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1360 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1361} 1362 1363multiclass PatCCVrVrU<CondCode CC, string Inst> { 1364 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1365 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1366 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1367 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1368 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1369 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1370 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1371 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1372} 1373 1374multiclass PatCCVrVrF<CondCode CC, string Inst> { 1375 def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)), 1376 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1377 def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)), 1378 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1379} 1380 1381let Predicates = [HasExtLSX] in { 1382 1383// VADD_{B/H/W/D} 1384defm : PatVrVr<add, "VADD">; 1385// VSUB_{B/H/W/D} 1386defm : PatVrVr<sub, "VSUB">; 1387 1388// VADDI_{B/H/W/D}U 1389defm : PatVrUimm5<add, "VADDI">; 1390// VSUBI_{B/H/W/D}U 1391defm : PatVrUimm5<sub, "VSUBI">; 1392 1393// VNEG_{B/H/W/D} 1394def : Pat<(sub immAllZerosV, (v16i8 LSX128:$vj)), (VNEG_B LSX128:$vj)>; 1395def : Pat<(sub immAllZerosV, (v8i16 LSX128:$vj)), (VNEG_H LSX128:$vj)>; 1396def : Pat<(sub immAllZerosV, (v4i32 LSX128:$vj)), (VNEG_W LSX128:$vj)>; 1397def : Pat<(sub immAllZerosV, (v2i64 LSX128:$vj)), (VNEG_D LSX128:$vj)>; 1398 1399// VMAX[I]_{B/H/W/D}[U] 1400defm : PatVrVr<smax, "VMAX">; 1401defm : PatVrVrU<umax, "VMAX">; 1402defm : PatVrSimm5<smax, "VMAXI">; 1403defm : PatVrUimm5<umax, "VMAXI">; 1404 1405// VMIN[I]_{B/H/W/D}[U] 1406defm : PatVrVr<smin, "VMIN">; 1407defm : PatVrVrU<umin, "VMIN">; 1408defm : PatVrSimm5<smin, "VMINI">; 1409defm : PatVrUimm5<umin, "VMINI">; 1410 1411// VMUL_{B/H/W/D} 1412defm : PatVrVr<mul, "VMUL">; 1413 1414// VMUH_{B/H/W/D}[U] 1415defm : PatVrVr<mulhs, "VMUH">; 1416defm : PatVrVrU<mulhu, "VMUH">; 1417 1418// VMADD_{B/H/W/D} 1419defm : PatVrVrVr<muladd, "VMADD">; 1420// VMSUB_{B/H/W/D} 1421defm : PatVrVrVr<mulsub, "VMSUB">; 1422 1423// VDIV_{B/H/W/D}[U] 1424defm : PatVrVr<sdiv, "VDIV">; 1425defm : PatVrVrU<udiv, "VDIV">; 1426 1427// VMOD_{B/H/W/D}[U] 1428defm : PatVrVr<srem, "VMOD">; 1429defm : PatVrVrU<urem, "VMOD">; 1430 1431// VAND_V 1432foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1433def : Pat<(and (vt LSX128:$vj), (vt LSX128:$vk)), 1434 (VAND_V LSX128:$vj, LSX128:$vk)>; 1435// VOR_V 1436foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1437def : Pat<(or (vt LSX128:$vj), (vt LSX128:$vk)), 1438 (VOR_V LSX128:$vj, LSX128:$vk)>; 1439// VXOR_V 1440foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1441def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)), 1442 (VXOR_V LSX128:$vj, LSX128:$vk)>; 1443// VNOR_V 1444foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1445def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))), 1446 (VNOR_V LSX128:$vj, LSX128:$vk)>; 1447 1448// VANDI_B 1449def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1450 (VANDI_B LSX128:$vj, uimm8:$imm)>; 1451// VORI_B 1452def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1453 (VORI_B LSX128:$vj, uimm8:$imm)>; 1454 1455// VXORI_B 1456def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1457 (VXORI_B LSX128:$vj, uimm8:$imm)>; 1458 1459// VSLL[I]_{B/H/W/D} 1460defm : PatVrVr<shl, "VSLL">; 1461defm : PatShiftVrVr<shl, "VSLL">; 1462defm : PatShiftVrUimm<shl, "VSLLI">; 1463 1464// VSRL[I]_{B/H/W/D} 1465defm : PatVrVr<srl, "VSRL">; 1466defm : PatShiftVrVr<srl, "VSRL">; 1467defm : PatShiftVrUimm<srl, "VSRLI">; 1468 1469// VSRA[I]_{B/H/W/D} 1470defm : PatVrVr<sra, "VSRA">; 1471defm : PatShiftVrVr<sra, "VSRA">; 1472defm : PatShiftVrUimm<sra, "VSRAI">; 1473 1474// VCLZ_{B/H/W/D} 1475defm : PatVr<ctlz, "VCLZ">; 1476 1477// VPCNT_{B/H/W/D} 1478defm : PatVr<ctpop, "VPCNT">; 1479 1480// VBITCLR_{B/H/W/D} 1481def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, v16i8:$vk))), 1482 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1483def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, v8i16:$vk))), 1484 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1485def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, v4i32:$vk))), 1486 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1487def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, v2i64:$vk))), 1488 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1489def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, 1490 (vsplati8imm7 v16i8:$vk)))), 1491 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1492def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, 1493 (vsplati16imm15 v8i16:$vk)))), 1494 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1495def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, 1496 (vsplati32imm31 v4i32:$vk)))), 1497 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1498def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, 1499 (vsplati64imm63 v2i64:$vk)))), 1500 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1501 1502// VBITCLRI_{B/H/W/D} 1503def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_inv_pow2 uimm3:$imm))), 1504 (VBITCLRI_B LSX128:$vj, uimm3:$imm)>; 1505def : Pat<(and (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_inv_pow2 uimm4:$imm))), 1506 (VBITCLRI_H LSX128:$vj, uimm4:$imm)>; 1507def : Pat<(and (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_inv_pow2 uimm5:$imm))), 1508 (VBITCLRI_W LSX128:$vj, uimm5:$imm)>; 1509def : Pat<(and (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_inv_pow2 uimm6:$imm))), 1510 (VBITCLRI_D LSX128:$vj, uimm6:$imm)>; 1511 1512// VBITSET_{B/H/W/D} 1513def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1514 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1515def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1516 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1517def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1518 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1519def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1520 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1521def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1522 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1523def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1524 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1525def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1526 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1527def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1528 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1529 1530// VBITSETI_{B/H/W/D} 1531def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1532 (VBITSETI_B LSX128:$vj, uimm3:$imm)>; 1533def : Pat<(or (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1534 (VBITSETI_H LSX128:$vj, uimm4:$imm)>; 1535def : Pat<(or (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1536 (VBITSETI_W LSX128:$vj, uimm5:$imm)>; 1537def : Pat<(or (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1538 (VBITSETI_D LSX128:$vj, uimm6:$imm)>; 1539 1540// VBITREV_{B/H/W/D} 1541def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1542 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1543def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1544 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1545def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1546 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1547def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1548 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1549def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1550 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1551def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1552 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1553def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1554 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1555def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1556 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1557 1558// VBITREVI_{B/H/W/D} 1559def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1560 (VBITREVI_B LSX128:$vj, uimm3:$imm)>; 1561def : Pat<(xor (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1562 (VBITREVI_H LSX128:$vj, uimm4:$imm)>; 1563def : Pat<(xor (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1564 (VBITREVI_W LSX128:$vj, uimm5:$imm)>; 1565def : Pat<(xor (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1566 (VBITREVI_D LSX128:$vj, uimm6:$imm)>; 1567 1568// VFADD_{S/D} 1569defm : PatVrVrF<fadd, "VFADD">; 1570 1571// VFSUB_{S/D} 1572defm : PatVrVrF<fsub, "VFSUB">; 1573 1574// VFMUL_{S/D} 1575defm : PatVrVrF<fmul, "VFMUL">; 1576 1577// VFDIV_{S/D} 1578defm : PatVrVrF<fdiv, "VFDIV">; 1579 1580// VFMADD_{S/D} 1581def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va), 1582 (VFMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1583def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va), 1584 (VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1585 1586// VFMSUB_{S/D} 1587def : Pat<(fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va)), 1588 (VFMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1589def : Pat<(fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va)), 1590 (VFMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1591 1592// VFNMADD_{S/D} 1593def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, v4f32:$va)), 1594 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1595def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, v2f64:$va)), 1596 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1597def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, (fneg v4f32:$va)), 1598 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1599def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, (fneg v2f64:$va)), 1600 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1601 1602// VFNMSUB_{S/D} 1603def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va))), 1604 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1605def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va))), 1606 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1607def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, v4f32:$va), 1608 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1609def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, v2f64:$va), 1610 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1611 1612// VFSQRT_{S/D} 1613defm : PatVrF<fsqrt, "VFSQRT">; 1614 1615// VFRECIP_{S/D} 1616def : Pat<(fdiv vsplatf32_fpimm_eq_1, v4f32:$vj), 1617 (VFRECIP_S v4f32:$vj)>; 1618def : Pat<(fdiv vsplatf64_fpimm_eq_1, v2f64:$vj), 1619 (VFRECIP_D v2f64:$vj)>; 1620 1621// VFRSQRT_{S/D} 1622def : Pat<(fdiv vsplatf32_fpimm_eq_1, (fsqrt v4f32:$vj)), 1623 (VFRSQRT_S v4f32:$vj)>; 1624def : Pat<(fdiv vsplatf64_fpimm_eq_1, (fsqrt v2f64:$vj)), 1625 (VFRSQRT_D v2f64:$vj)>; 1626 1627// VSEQ[I]_{B/H/W/D} 1628defm : PatCCVrSimm5<SETEQ, "VSEQI">; 1629defm : PatCCVrVr<SETEQ, "VSEQ">; 1630 1631// VSLE[I]_{B/H/W/D}[U] 1632defm : PatCCVrSimm5<SETLE, "VSLEI">; 1633defm : PatCCVrUimm5<SETULE, "VSLEI">; 1634defm : PatCCVrVr<SETLE, "VSLE">; 1635defm : PatCCVrVrU<SETULE, "VSLE">; 1636 1637// VSLT[I]_{B/H/W/D}[U] 1638defm : PatCCVrSimm5<SETLT, "VSLTI">; 1639defm : PatCCVrUimm5<SETULT, "VSLTI">; 1640defm : PatCCVrVr<SETLT, "VSLT">; 1641defm : PatCCVrVrU<SETULT, "VSLT">; 1642 1643// VFCMP.cond.{S/D} 1644defm : PatCCVrVrF<SETEQ, "VFCMP_CEQ">; 1645defm : PatCCVrVrF<SETOEQ, "VFCMP_CEQ">; 1646defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">; 1647 1648defm : PatCCVrVrF<SETLE, "VFCMP_CLE">; 1649defm : PatCCVrVrF<SETOLE, "VFCMP_CLE">; 1650defm : PatCCVrVrF<SETULE, "VFCMP_CULE">; 1651 1652defm : PatCCVrVrF<SETLT, "VFCMP_CLT">; 1653defm : PatCCVrVrF<SETOLT, "VFCMP_CLT">; 1654defm : PatCCVrVrF<SETULT, "VFCMP_CULT">; 1655 1656defm : PatCCVrVrF<SETNE, "VFCMP_CNE">; 1657defm : PatCCVrVrF<SETONE, "VFCMP_CNE">; 1658defm : PatCCVrVrF<SETUNE, "VFCMP_CUNE">; 1659 1660defm : PatCCVrVrF<SETO, "VFCMP_COR">; 1661defm : PatCCVrVrF<SETUO, "VFCMP_CUN">; 1662 1663// VINSGR2VR_{B/H/W/D} 1664def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm), 1665 (VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>; 1666def : Pat<(vector_insert v8i16:$vd, GRLenVT:$rj, uimm3:$imm), 1667 (VINSGR2VR_H v8i16:$vd, GRLenVT:$rj, uimm3:$imm)>; 1668def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm), 1669 (VINSGR2VR_W v4i32:$vd, GRLenVT:$rj, uimm2:$imm)>; 1670def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm), 1671 (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>; 1672 1673def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm), 1674 (VINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm2:$imm)>; 1675def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm), 1676 (VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>; 1677 1678// VPICKVE2GR_{B/H/W}[U] 1679def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8), 1680 (VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>; 1681def : Pat<(loongarch_vpick_sext_elt v8i16:$vd, uimm3:$imm, i16), 1682 (VPICKVE2GR_H v8i16:$vd, uimm3:$imm)>; 1683def : Pat<(loongarch_vpick_sext_elt v4i32:$vd, uimm2:$imm, i32), 1684 (VPICKVE2GR_W v4i32:$vd, uimm2:$imm)>; 1685 1686def : Pat<(loongarch_vpick_zext_elt v16i8:$vd, uimm4:$imm, i8), 1687 (VPICKVE2GR_BU v16i8:$vd, uimm4:$imm)>; 1688def : Pat<(loongarch_vpick_zext_elt v8i16:$vd, uimm3:$imm, i16), 1689 (VPICKVE2GR_HU v8i16:$vd, uimm3:$imm)>; 1690def : Pat<(loongarch_vpick_zext_elt v4i32:$vd, uimm2:$imm, i32), 1691 (VPICKVE2GR_WU v4i32:$vd, uimm2:$imm)>; 1692 1693// VREPLGR2VR_{B/H/W/D} 1694def : Pat<(lsxsplati8 GPR:$rj), (VREPLGR2VR_B GPR:$rj)>; 1695def : Pat<(lsxsplati16 GPR:$rj), (VREPLGR2VR_H GPR:$rj)>; 1696def : Pat<(lsxsplati32 GPR:$rj), (VREPLGR2VR_W GPR:$rj)>; 1697def : Pat<(lsxsplati64 GPR:$rj), (VREPLGR2VR_D GPR:$rj)>; 1698 1699// VREPLVE_{B/H/W/D} 1700def : Pat<(loongarch_vreplve v16i8:$vj, GRLenVT:$rk), 1701 (VREPLVE_B v16i8:$vj, GRLenVT:$rk)>; 1702def : Pat<(loongarch_vreplve v8i16:$vj, GRLenVT:$rk), 1703 (VREPLVE_H v8i16:$vj, GRLenVT:$rk)>; 1704def : Pat<(loongarch_vreplve v4i32:$vj, GRLenVT:$rk), 1705 (VREPLVE_W v4i32:$vj, GRLenVT:$rk)>; 1706def : Pat<(loongarch_vreplve v2i64:$vj, GRLenVT:$rk), 1707 (VREPLVE_D v2i64:$vj, GRLenVT:$rk)>; 1708 1709// VSHUF_{B/H/W/D} 1710def : Pat<(loongarch_vshuf v16i8:$va, v16i8:$vj, v16i8:$vk), 1711 (VSHUF_B v16i8:$vj, v16i8:$vk, v16i8:$va)>; 1712def : Pat<(loongarch_vshuf v8i16:$vd, v8i16:$vj, v8i16:$vk), 1713 (VSHUF_H v8i16:$vd, v8i16:$vj, v8i16:$vk)>; 1714def : Pat<(loongarch_vshuf v4i32:$vd, v4i32:$vj, v4i32:$vk), 1715 (VSHUF_W v4i32:$vd, v4i32:$vj, v4i32:$vk)>; 1716def : Pat<(loongarch_vshuf v2i64:$vd, v2i64:$vj, v2i64:$vk), 1717 (VSHUF_D v2i64:$vd, v2i64:$vj, v2i64:$vk)>; 1718def : Pat<(loongarch_vshuf v4i32:$vd, v4f32:$vj, v4f32:$vk), 1719 (VSHUF_W v4i32:$vd, v4f32:$vj, v4f32:$vk)>; 1720def : Pat<(loongarch_vshuf v2i64:$vd, v2f64:$vj, v2f64:$vk), 1721 (VSHUF_D v2i64:$vd, v2f64:$vj, v2f64:$vk)>; 1722 1723// VPICKEV_{B/H/W/D} 1724def : Pat<(loongarch_vpickev v16i8:$vj, v16i8:$vk), 1725 (VPICKEV_B v16i8:$vj, v16i8:$vk)>; 1726def : Pat<(loongarch_vpickev v8i16:$vj, v8i16:$vk), 1727 (VPICKEV_H v8i16:$vj, v8i16:$vk)>; 1728def : Pat<(loongarch_vpickev v4i32:$vj, v4i32:$vk), 1729 (VPICKEV_W v4i32:$vj, v4i32:$vk)>; 1730def : Pat<(loongarch_vpickev v2i64:$vj, v2i64:$vk), 1731 (VPICKEV_D v2i64:$vj, v2i64:$vk)>; 1732def : Pat<(loongarch_vpickev v4f32:$vj, v4f32:$vk), 1733 (VPICKEV_W v4f32:$vj, v4f32:$vk)>; 1734def : Pat<(loongarch_vpickev v2f64:$vj, v2f64:$vk), 1735 (VPICKEV_D v2f64:$vj, v2f64:$vk)>; 1736 1737// VPICKOD_{B/H/W/D} 1738def : Pat<(loongarch_vpickod v16i8:$vj, v16i8:$vk), 1739 (VPICKOD_B v16i8:$vj, v16i8:$vk)>; 1740def : Pat<(loongarch_vpickod v8i16:$vj, v8i16:$vk), 1741 (VPICKOD_H v8i16:$vj, v8i16:$vk)>; 1742def : Pat<(loongarch_vpickod v4i32:$vj, v4i32:$vk), 1743 (VPICKOD_W v4i32:$vj, v4i32:$vk)>; 1744def : Pat<(loongarch_vpickod v2i64:$vj, v2i64:$vk), 1745 (VPICKOD_D v2i64:$vj, v2i64:$vk)>; 1746def : Pat<(loongarch_vpickod v4f32:$vj, v4f32:$vk), 1747 (VPICKOD_W v4f32:$vj, v4f32:$vk)>; 1748def : Pat<(loongarch_vpickod v2f64:$vj, v2f64:$vk), 1749 (VPICKOD_D v2f64:$vj, v2f64:$vk)>; 1750 1751// VPACKEV_{B/H/W/D} 1752def : Pat<(loongarch_vpackev v16i8:$vj, v16i8:$vk), 1753 (VPACKEV_B v16i8:$vj, v16i8:$vk)>; 1754def : Pat<(loongarch_vpackev v8i16:$vj, v8i16:$vk), 1755 (VPACKEV_H v8i16:$vj, v8i16:$vk)>; 1756def : Pat<(loongarch_vpackev v4i32:$vj, v4i32:$vk), 1757 (VPACKEV_W v4i32:$vj, v4i32:$vk)>; 1758def : Pat<(loongarch_vpackev v2i64:$vj, v2i64:$vk), 1759 (VPACKEV_D v2i64:$vj, v2i64:$vk)>; 1760def : Pat<(loongarch_vpackev v4f32:$vj, v4f32:$vk), 1761 (VPACKEV_W v4f32:$vj, v4f32:$vk)>; 1762def : Pat<(loongarch_vpackev v2f64:$vj, v2f64:$vk), 1763 (VPACKEV_D v2f64:$vj, v2f64:$vk)>; 1764 1765// VPACKOD_{B/H/W/D} 1766def : Pat<(loongarch_vpackod v16i8:$vj, v16i8:$vk), 1767 (VPACKOD_B v16i8:$vj, v16i8:$vk)>; 1768def : Pat<(loongarch_vpackod v8i16:$vj, v8i16:$vk), 1769 (VPACKOD_H v8i16:$vj, v8i16:$vk)>; 1770def : Pat<(loongarch_vpackod v4i32:$vj, v4i32:$vk), 1771 (VPACKOD_W v4i32:$vj, v4i32:$vk)>; 1772def : Pat<(loongarch_vpackod v2i64:$vj, v2i64:$vk), 1773 (VPACKOD_D v2i64:$vj, v2i64:$vk)>; 1774def : Pat<(loongarch_vpackod v4f32:$vj, v4f32:$vk), 1775 (VPACKOD_W v4f32:$vj, v4f32:$vk)>; 1776def : Pat<(loongarch_vpackod v2f64:$vj, v2f64:$vk), 1777 (VPACKOD_D v2f64:$vj, v2f64:$vk)>; 1778 1779// VILVL_{B/H/W/D} 1780def : Pat<(loongarch_vilvl v16i8:$vj, v16i8:$vk), 1781 (VILVL_B v16i8:$vj, v16i8:$vk)>; 1782def : Pat<(loongarch_vilvl v8i16:$vj, v8i16:$vk), 1783 (VILVL_H v8i16:$vj, v8i16:$vk)>; 1784def : Pat<(loongarch_vilvl v4i32:$vj, v4i32:$vk), 1785 (VILVL_W v4i32:$vj, v4i32:$vk)>; 1786def : Pat<(loongarch_vilvl v2i64:$vj, v2i64:$vk), 1787 (VILVL_D v2i64:$vj, v2i64:$vk)>; 1788def : Pat<(loongarch_vilvl v4f32:$vj, v4f32:$vk), 1789 (VILVL_W v4f32:$vj, v4f32:$vk)>; 1790def : Pat<(loongarch_vilvl v2f64:$vj, v2f64:$vk), 1791 (VILVL_D v2f64:$vj, v2f64:$vk)>; 1792 1793// VILVH_{B/H/W/D} 1794def : Pat<(loongarch_vilvh v16i8:$vj, v16i8:$vk), 1795 (VILVH_B v16i8:$vj, v16i8:$vk)>; 1796def : Pat<(loongarch_vilvh v8i16:$vj, v8i16:$vk), 1797 (VILVH_H v8i16:$vj, v8i16:$vk)>; 1798def : Pat<(loongarch_vilvh v4i32:$vj, v4i32:$vk), 1799 (VILVH_W v4i32:$vj, v4i32:$vk)>; 1800def : Pat<(loongarch_vilvh v2i64:$vj, v2i64:$vk), 1801 (VILVH_D v2i64:$vj, v2i64:$vk)>; 1802def : Pat<(loongarch_vilvh v4f32:$vj, v4f32:$vk), 1803 (VILVH_W v4f32:$vj, v4f32:$vk)>; 1804def : Pat<(loongarch_vilvh v2f64:$vj, v2f64:$vk), 1805 (VILVH_D v2f64:$vj, v2f64:$vk)>; 1806 1807// VSHUF4I_{B/H/W} 1808def : Pat<(loongarch_vshuf4i v16i8:$vj, immZExt8:$ui8), 1809 (VSHUF4I_B v16i8:$vj, immZExt8:$ui8)>; 1810def : Pat<(loongarch_vshuf4i v8i16:$vj, immZExt8:$ui8), 1811 (VSHUF4I_H v8i16:$vj, immZExt8:$ui8)>; 1812def : Pat<(loongarch_vshuf4i v4i32:$vj, immZExt8:$ui8), 1813 (VSHUF4I_W v4i32:$vj, immZExt8:$ui8)>; 1814def : Pat<(loongarch_vshuf4i v4f32:$vj, immZExt8:$ui8), 1815 (VSHUF4I_W v4f32:$vj, immZExt8:$ui8)>; 1816 1817// VREPLVEI_{B/H/W/D} 1818def : Pat<(loongarch_vreplvei v16i8:$vj, immZExt4:$ui4), 1819 (VREPLVEI_B v16i8:$vj, immZExt4:$ui4)>; 1820def : Pat<(loongarch_vreplvei v8i16:$vj, immZExt3:$ui3), 1821 (VREPLVEI_H v8i16:$vj, immZExt3:$ui3)>; 1822def : Pat<(loongarch_vreplvei v4i32:$vj, immZExt2:$ui2), 1823 (VREPLVEI_W v4i32:$vj, immZExt2:$ui2)>; 1824def : Pat<(loongarch_vreplvei v2i64:$vj, immZExt1:$ui1), 1825 (VREPLVEI_D v2i64:$vj, immZExt1:$ui1)>; 1826def : Pat<(loongarch_vreplvei v4f32:$vj, immZExt2:$ui2), 1827 (VREPLVEI_W v4f32:$vj, immZExt2:$ui2)>; 1828def : Pat<(loongarch_vreplvei v2f64:$vj, immZExt1:$ui1), 1829 (VREPLVEI_D v2f64:$vj, immZExt1:$ui1)>; 1830 1831// VREPLVEI_{W/D} 1832def : Pat<(lsxsplatf32 FPR32:$fj), 1833 (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; 1834def : Pat<(lsxsplatf64 FPR64:$fj), 1835 (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; 1836 1837// Loads/Stores 1838foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 1839 defm : LdPat<load, VLD, vt>; 1840 def : RegRegLdPat<load, VLDX, vt>; 1841 defm : StPat<store, VST, LSX128, vt>; 1842 def : RegRegStPat<store, VSTX, LSX128, vt>; 1843} 1844 1845// Vector extraction with constant index. 1846def : Pat<(i64 (vector_extract v16i8:$vj, uimm4:$imm)), 1847 (VPICKVE2GR_B v16i8:$vj, uimm4:$imm)>; 1848def : Pat<(i64 (vector_extract v8i16:$vj, uimm3:$imm)), 1849 (VPICKVE2GR_H v8i16:$vj, uimm3:$imm)>; 1850def : Pat<(i64 (vector_extract v4i32:$vj, uimm2:$imm)), 1851 (VPICKVE2GR_W v4i32:$vj, uimm2:$imm)>; 1852def : Pat<(i64 (vector_extract v2i64:$vj, uimm1:$imm)), 1853 (VPICKVE2GR_D v2i64:$vj, uimm1:$imm)>; 1854def : Pat<(f32 (vector_extract v4f32:$vj, uimm2:$imm)), 1855 (f32 (EXTRACT_SUBREG (VREPLVEI_W v4f32:$vj, uimm2:$imm), sub_32))>; 1856def : Pat<(f64 (vector_extract v2f64:$vj, uimm1:$imm)), 1857 (f64 (EXTRACT_SUBREG (VREPLVEI_D v2f64:$vj, uimm1:$imm), sub_64))>; 1858 1859// Vector extraction with variable index. 1860def : Pat<(i64 (vector_extract v16i8:$vj, i64:$rk)), 1861 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_B v16i8:$vj, 1862 i64:$rk), 1863 sub_32)), 1864 GPR), (i64 24))>; 1865def : Pat<(i64 (vector_extract v8i16:$vj, i64:$rk)), 1866 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_H v8i16:$vj, 1867 i64:$rk), 1868 sub_32)), 1869 GPR), (i64 16))>; 1870def : Pat<(i64 (vector_extract v4i32:$vj, i64:$rk)), 1871 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_W v4i32:$vj, i64:$rk), 1872 sub_32)), 1873 GPR)>; 1874def : Pat<(i64 (vector_extract v2i64:$vj, i64:$rk)), 1875 (COPY_TO_REGCLASS (f64 (EXTRACT_SUBREG (VREPLVE_D v2i64:$vj, i64:$rk), 1876 sub_64)), 1877 GPR)>; 1878def : Pat<(f32 (vector_extract v4f32:$vj, i64:$rk)), 1879 (f32 (EXTRACT_SUBREG (VREPLVE_W v4f32:$vj, i64:$rk), sub_32))>; 1880def : Pat<(f64 (vector_extract v2f64:$vj, i64:$rk)), 1881 (f64 (EXTRACT_SUBREG (VREPLVE_D v2f64:$vj, i64:$rk), sub_64))>; 1882 1883// vselect 1884def : Pat<(v16i8 (vselect LSX128:$vd, (v16i8 (SplatPat_uimm8 uimm8:$imm)), 1885 LSX128:$vj)), 1886 (VBITSELI_B LSX128:$vd, LSX128:$vj, uimm8:$imm)>; 1887foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 1888 def : Pat<(vt (vselect LSX128:$va, LSX128:$vk, LSX128:$vj)), 1889 (VBITSEL_V LSX128:$vj, LSX128:$vk, LSX128:$va)>; 1890 1891// fneg 1892def : Pat<(fneg (v4f32 LSX128:$vj)), (VBITREVI_W LSX128:$vj, 31)>; 1893def : Pat<(fneg (v2f64 LSX128:$vj)), (VBITREVI_D LSX128:$vj, 63)>; 1894 1895// VFFINT_{S_W/D_L} 1896def : Pat<(v4f32 (sint_to_fp v4i32:$vj)), (VFFINT_S_W v4i32:$vj)>; 1897def : Pat<(v2f64 (sint_to_fp v2i64:$vj)), (VFFINT_D_L v2i64:$vj)>; 1898 1899// VFFINT_{S_WU/D_LU} 1900def : Pat<(v4f32 (uint_to_fp v4i32:$vj)), (VFFINT_S_WU v4i32:$vj)>; 1901def : Pat<(v2f64 (uint_to_fp v2i64:$vj)), (VFFINT_D_LU v2i64:$vj)>; 1902 1903// VFTINTRZ_{W_S/L_D} 1904def : Pat<(v4i32 (fp_to_sint v4f32:$vj)), (VFTINTRZ_W_S v4f32:$vj)>; 1905def : Pat<(v2i64 (fp_to_sint v2f64:$vj)), (VFTINTRZ_L_D v2f64:$vj)>; 1906 1907// VFTINTRZ_{W_SU/L_DU} 1908def : Pat<(v4i32 (fp_to_uint v4f32:$vj)), (VFTINTRZ_WU_S v4f32:$vj)>; 1909def : Pat<(v2i64 (fp_to_uint v2f64:$vj)), (VFTINTRZ_LU_D v2f64:$vj)>; 1910 1911} // Predicates = [HasExtLSX] 1912 1913/// Intrinsic pattern 1914 1915class deriveLSXIntrinsic<string Inst> { 1916 Intrinsic ret = !cast<Intrinsic>(!tolower("int_loongarch_lsx_"#Inst)); 1917} 1918 1919let Predicates = [HasExtLSX] in { 1920 1921// vty: v16i8/v8i16/v4i32/v2i64 1922// Pat<(Intrinsic vty:$vj, vty:$vk), 1923// (LAInst vty:$vj, vty:$vk)>; 1924foreach Inst = ["VSADD_B", "VSADD_BU", "VSSUB_B", "VSSUB_BU", 1925 "VHADDW_H_B", "VHADDW_HU_BU", "VHSUBW_H_B", "VHSUBW_HU_BU", 1926 "VADDWEV_H_B", "VADDWOD_H_B", "VSUBWEV_H_B", "VSUBWOD_H_B", 1927 "VADDWEV_H_BU", "VADDWOD_H_BU", "VSUBWEV_H_BU", "VSUBWOD_H_BU", 1928 "VADDWEV_H_BU_B", "VADDWOD_H_BU_B", 1929 "VAVG_B", "VAVG_BU", "VAVGR_B", "VAVGR_BU", 1930 "VABSD_B", "VABSD_BU", "VADDA_B", "VMUH_B", "VMUH_BU", 1931 "VMULWEV_H_B", "VMULWOD_H_B", "VMULWEV_H_BU", "VMULWOD_H_BU", 1932 "VMULWEV_H_BU_B", "VMULWOD_H_BU_B", "VSIGNCOV_B", 1933 "VANDN_V", "VORN_V", "VROTR_B", "VSRLR_B", "VSRAR_B", 1934 "VSEQ_B", "VSLE_B", "VSLE_BU", "VSLT_B", "VSLT_BU", 1935 "VPACKEV_B", "VPACKOD_B", "VPICKEV_B", "VPICKOD_B", 1936 "VILVL_B", "VILVH_B"] in 1937 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1938 (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1939 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1940foreach Inst = ["VSADD_H", "VSADD_HU", "VSSUB_H", "VSSUB_HU", 1941 "VHADDW_W_H", "VHADDW_WU_HU", "VHSUBW_W_H", "VHSUBW_WU_HU", 1942 "VADDWEV_W_H", "VADDWOD_W_H", "VSUBWEV_W_H", "VSUBWOD_W_H", 1943 "VADDWEV_W_HU", "VADDWOD_W_HU", "VSUBWEV_W_HU", "VSUBWOD_W_HU", 1944 "VADDWEV_W_HU_H", "VADDWOD_W_HU_H", 1945 "VAVG_H", "VAVG_HU", "VAVGR_H", "VAVGR_HU", 1946 "VABSD_H", "VABSD_HU", "VADDA_H", "VMUH_H", "VMUH_HU", 1947 "VMULWEV_W_H", "VMULWOD_W_H", "VMULWEV_W_HU", "VMULWOD_W_HU", 1948 "VMULWEV_W_HU_H", "VMULWOD_W_HU_H", "VSIGNCOV_H", "VROTR_H", 1949 "VSRLR_H", "VSRAR_H", "VSRLN_B_H", "VSRAN_B_H", "VSRLRN_B_H", 1950 "VSRARN_B_H", "VSSRLN_B_H", "VSSRAN_B_H", "VSSRLN_BU_H", 1951 "VSSRAN_BU_H", "VSSRLRN_B_H", "VSSRARN_B_H", "VSSRLRN_BU_H", 1952 "VSSRARN_BU_H", 1953 "VSEQ_H", "VSLE_H", "VSLE_HU", "VSLT_H", "VSLT_HU", 1954 "VPACKEV_H", "VPACKOD_H", "VPICKEV_H", "VPICKOD_H", 1955 "VILVL_H", "VILVH_H"] in 1956 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1957 (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1958 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1959foreach Inst = ["VSADD_W", "VSADD_WU", "VSSUB_W", "VSSUB_WU", 1960 "VHADDW_D_W", "VHADDW_DU_WU", "VHSUBW_D_W", "VHSUBW_DU_WU", 1961 "VADDWEV_D_W", "VADDWOD_D_W", "VSUBWEV_D_W", "VSUBWOD_D_W", 1962 "VADDWEV_D_WU", "VADDWOD_D_WU", "VSUBWEV_D_WU", "VSUBWOD_D_WU", 1963 "VADDWEV_D_WU_W", "VADDWOD_D_WU_W", 1964 "VAVG_W", "VAVG_WU", "VAVGR_W", "VAVGR_WU", 1965 "VABSD_W", "VABSD_WU", "VADDA_W", "VMUH_W", "VMUH_WU", 1966 "VMULWEV_D_W", "VMULWOD_D_W", "VMULWEV_D_WU", "VMULWOD_D_WU", 1967 "VMULWEV_D_WU_W", "VMULWOD_D_WU_W", "VSIGNCOV_W", "VROTR_W", 1968 "VSRLR_W", "VSRAR_W", "VSRLN_H_W", "VSRAN_H_W", "VSRLRN_H_W", 1969 "VSRARN_H_W", "VSSRLN_H_W", "VSSRAN_H_W", "VSSRLN_HU_W", 1970 "VSSRAN_HU_W", "VSSRLRN_H_W", "VSSRARN_H_W", "VSSRLRN_HU_W", 1971 "VSSRARN_HU_W", 1972 "VSEQ_W", "VSLE_W", "VSLE_WU", "VSLT_W", "VSLT_WU", 1973 "VPACKEV_W", "VPACKOD_W", "VPICKEV_W", "VPICKOD_W", 1974 "VILVL_W", "VILVH_W"] in 1975 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1976 (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1977 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1978foreach Inst = ["VADD_Q", "VSUB_Q", 1979 "VSADD_D", "VSADD_DU", "VSSUB_D", "VSSUB_DU", 1980 "VHADDW_Q_D", "VHADDW_QU_DU", "VHSUBW_Q_D", "VHSUBW_QU_DU", 1981 "VADDWEV_Q_D", "VADDWOD_Q_D", "VSUBWEV_Q_D", "VSUBWOD_Q_D", 1982 "VADDWEV_Q_DU", "VADDWOD_Q_DU", "VSUBWEV_Q_DU", "VSUBWOD_Q_DU", 1983 "VADDWEV_Q_DU_D", "VADDWOD_Q_DU_D", 1984 "VAVG_D", "VAVG_DU", "VAVGR_D", "VAVGR_DU", 1985 "VABSD_D", "VABSD_DU", "VADDA_D", "VMUH_D", "VMUH_DU", 1986 "VMULWEV_Q_D", "VMULWOD_Q_D", "VMULWEV_Q_DU", "VMULWOD_Q_DU", 1987 "VMULWEV_Q_DU_D", "VMULWOD_Q_DU_D", "VSIGNCOV_D", "VROTR_D", 1988 "VSRLR_D", "VSRAR_D", "VSRLN_W_D", "VSRAN_W_D", "VSRLRN_W_D", 1989 "VSRARN_W_D", "VSSRLN_W_D", "VSSRAN_W_D", "VSSRLN_WU_D", 1990 "VSSRAN_WU_D", "VSSRLRN_W_D", "VSSRARN_W_D", "VSSRLRN_WU_D", 1991 "VSSRARN_WU_D", "VFFINT_S_L", 1992 "VSEQ_D", "VSLE_D", "VSLE_DU", "VSLT_D", "VSLT_DU", 1993 "VPACKEV_D", "VPACKOD_D", "VPICKEV_D", "VPICKOD_D", 1994 "VILVL_D", "VILVH_D"] in 1995 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1996 (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1997 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1998 1999// vty: v16i8/v8i16/v4i32/v2i64 2000// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 2001// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 2002foreach Inst = ["VMADDWEV_H_B", "VMADDWOD_H_B", "VMADDWEV_H_BU", 2003 "VMADDWOD_H_BU", "VMADDWEV_H_BU_B", "VMADDWOD_H_BU_B"] in 2004 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2005 (v8i16 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 2006 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2007foreach Inst = ["VMADDWEV_W_H", "VMADDWOD_W_H", "VMADDWEV_W_HU", 2008 "VMADDWOD_W_HU", "VMADDWEV_W_HU_H", "VMADDWOD_W_HU_H"] in 2009 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2010 (v4i32 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 2011 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2012foreach Inst = ["VMADDWEV_D_W", "VMADDWOD_D_W", "VMADDWEV_D_WU", 2013 "VMADDWOD_D_WU", "VMADDWEV_D_WU_W", "VMADDWOD_D_WU_W"] in 2014 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2015 (v2i64 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 2016 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2017foreach Inst = ["VMADDWEV_Q_D", "VMADDWOD_Q_D", "VMADDWEV_Q_DU", 2018 "VMADDWOD_Q_DU", "VMADDWEV_Q_DU_D", "VMADDWOD_Q_DU_D"] in 2019 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2020 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 2021 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2022 2023// vty: v16i8/v8i16/v4i32/v2i64 2024// Pat<(Intrinsic vty:$vj), 2025// (LAInst vty:$vj)>; 2026foreach Inst = ["VEXTH_H_B", "VEXTH_HU_BU", 2027 "VMSKLTZ_B", "VMSKGEZ_B", "VMSKNZ_B", 2028 "VCLO_B"] in 2029 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj)), 2030 (!cast<LAInst>(Inst) LSX128:$vj)>; 2031foreach Inst = ["VEXTH_W_H", "VEXTH_WU_HU", "VMSKLTZ_H", 2032 "VCLO_H", "VFCVTL_S_H", "VFCVTH_S_H"] in 2033 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj)), 2034 (!cast<LAInst>(Inst) LSX128:$vj)>; 2035foreach Inst = ["VEXTH_D_W", "VEXTH_DU_WU", "VMSKLTZ_W", 2036 "VCLO_W", "VFFINT_S_W", "VFFINT_S_WU", 2037 "VFFINTL_D_W", "VFFINTH_D_W"] in 2038 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj)), 2039 (!cast<LAInst>(Inst) LSX128:$vj)>; 2040foreach Inst = ["VEXTH_Q_D", "VEXTH_QU_DU", "VMSKLTZ_D", 2041 "VEXTL_Q_D", "VEXTL_QU_DU", 2042 "VCLO_D", "VFFINT_D_L", "VFFINT_D_LU"] in 2043 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj)), 2044 (!cast<LAInst>(Inst) LSX128:$vj)>; 2045 2046// Pat<(Intrinsic timm:$imm) 2047// (LAInst timm:$imm)>; 2048def : Pat<(int_loongarch_lsx_vldi timm:$imm), 2049 (VLDI (to_valid_timm timm:$imm))>; 2050foreach Inst = ["VREPLI_B", "VREPLI_H", "VREPLI_W", "VREPLI_D"] in 2051 def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm), 2052 (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>; 2053 2054// vty: v16i8/v8i16/v4i32/v2i64 2055// Pat<(Intrinsic vty:$vj, timm:$imm) 2056// (LAInst vty:$vj, timm:$imm)>; 2057foreach Inst = ["VSAT_B", "VSAT_BU", "VNORI_B", "VROTRI_B", "VSLLWIL_H_B", 2058 "VSLLWIL_HU_BU", "VSRLRI_B", "VSRARI_B", 2059 "VSEQI_B", "VSLEI_B", "VSLEI_BU", "VSLTI_B", "VSLTI_BU", 2060 "VREPLVEI_B", "VBSLL_V", "VBSRL_V", "VSHUF4I_B"] in 2061 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm), 2062 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2063foreach Inst = ["VSAT_H", "VSAT_HU", "VROTRI_H", "VSLLWIL_W_H", 2064 "VSLLWIL_WU_HU", "VSRLRI_H", "VSRARI_H", 2065 "VSEQI_H", "VSLEI_H", "VSLEI_HU", "VSLTI_H", "VSLTI_HU", 2066 "VREPLVEI_H", "VSHUF4I_H"] in 2067 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj), timm:$imm), 2068 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2069foreach Inst = ["VSAT_W", "VSAT_WU", "VROTRI_W", "VSLLWIL_D_W", 2070 "VSLLWIL_DU_WU", "VSRLRI_W", "VSRARI_W", 2071 "VSEQI_W", "VSLEI_W", "VSLEI_WU", "VSLTI_W", "VSLTI_WU", 2072 "VREPLVEI_W", "VSHUF4I_W"] in 2073 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj), timm:$imm), 2074 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2075foreach Inst = ["VSAT_D", "VSAT_DU", "VROTRI_D", "VSRLRI_D", "VSRARI_D", 2076 "VSEQI_D", "VSLEI_D", "VSLEI_DU", "VSLTI_D", "VSLTI_DU", 2077 "VPICKVE2GR_D", "VPICKVE2GR_DU", 2078 "VREPLVEI_D"] in 2079 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj), timm:$imm), 2080 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2081 2082// vty: v16i8/v8i16/v4i32/v2i64 2083// Pat<(Intrinsic vty:$vd, vty:$vj, timm:$imm) 2084// (LAInst vty:$vd, vty:$vj, timm:$imm)>; 2085foreach Inst = ["VSRLNI_B_H", "VSRANI_B_H", "VSRLRNI_B_H", "VSRARNI_B_H", 2086 "VSSRLNI_B_H", "VSSRANI_B_H", "VSSRLNI_BU_H", "VSSRANI_BU_H", 2087 "VSSRLRNI_B_H", "VSSRARNI_B_H", "VSSRLRNI_BU_H", "VSSRARNI_BU_H", 2088 "VFRSTPI_B", "VBITSELI_B", "VEXTRINS_B"] in 2089 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2090 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), timm:$imm), 2091 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2092 (to_valid_timm timm:$imm))>; 2093foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W", 2094 "VSSRLNI_H_W", "VSSRANI_H_W", "VSSRLNI_HU_W", "VSSRANI_HU_W", 2095 "VSSRLRNI_H_W", "VSSRARNI_H_W", "VSSRLRNI_HU_W", "VSSRARNI_HU_W", 2096 "VFRSTPI_H", "VEXTRINS_H"] in 2097 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2098 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), timm:$imm), 2099 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2100 (to_valid_timm timm:$imm))>; 2101foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D", 2102 "VSSRLNI_W_D", "VSSRANI_W_D", "VSSRLNI_WU_D", "VSSRANI_WU_D", 2103 "VSSRLRNI_W_D", "VSSRARNI_W_D", "VSSRLRNI_WU_D", "VSSRARNI_WU_D", 2104 "VPERMI_W", "VEXTRINS_W"] in 2105 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2106 (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), timm:$imm), 2107 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2108 (to_valid_timm timm:$imm))>; 2109foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q", 2110 "VSSRLNI_D_Q", "VSSRANI_D_Q", "VSSRLNI_DU_Q", "VSSRANI_DU_Q", 2111 "VSSRLRNI_D_Q", "VSSRARNI_D_Q", "VSSRLRNI_DU_Q", "VSSRARNI_DU_Q", 2112 "VSHUF4I_D", "VEXTRINS_D"] in 2113 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2114 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), timm:$imm), 2115 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2116 (to_valid_timm timm:$imm))>; 2117 2118// vty: v16i8/v8i16/v4i32/v2i64 2119// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 2120// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 2121foreach Inst = ["VFRSTP_B", "VBITSEL_V", "VSHUF_B"] in 2122 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2123 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 2124 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2125foreach Inst = ["VFRSTP_H", "VSHUF_H"] in 2126 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2127 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 2128 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2129def : Pat<(int_loongarch_lsx_vshuf_w (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), 2130 (v4i32 LSX128:$vk)), 2131 (VSHUF_W LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2132def : Pat<(int_loongarch_lsx_vshuf_d (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), 2133 (v2i64 LSX128:$vk)), 2134 (VSHUF_D LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2135 2136// vty: v4f32/v2f64 2137// Pat<(Intrinsic vty:$vj, vty:$vk, vty:$va), 2138// (LAInst vty:$vj, vty:$vk, vty:$va)>; 2139foreach Inst = ["VFMSUB_S", "VFNMADD_S", "VFNMSUB_S"] in 2140 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2141 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), (v4f32 LSX128:$va)), 2142 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 2143foreach Inst = ["VFMSUB_D", "VFNMADD_D", "VFNMSUB_D"] in 2144 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2145 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), (v2f64 LSX128:$va)), 2146 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 2147 2148// vty: v4f32/v2f64 2149// Pat<(Intrinsic vty:$vj, vty:$vk), 2150// (LAInst vty:$vj, vty:$vk)>; 2151foreach Inst = ["VFMAX_S", "VFMIN_S", "VFMAXA_S", "VFMINA_S", "VFCVT_H_S", 2152 "VFCMP_CAF_S", "VFCMP_CUN_S", "VFCMP_CEQ_S", "VFCMP_CUEQ_S", 2153 "VFCMP_CLT_S", "VFCMP_CULT_S", "VFCMP_CLE_S", "VFCMP_CULE_S", 2154 "VFCMP_CNE_S", "VFCMP_COR_S", "VFCMP_CUNE_S", 2155 "VFCMP_SAF_S", "VFCMP_SUN_S", "VFCMP_SEQ_S", "VFCMP_SUEQ_S", 2156 "VFCMP_SLT_S", "VFCMP_SULT_S", "VFCMP_SLE_S", "VFCMP_SULE_S", 2157 "VFCMP_SNE_S", "VFCMP_SOR_S", "VFCMP_SUNE_S"] in 2158 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2159 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 2160 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2161foreach Inst = ["VFMAX_D", "VFMIN_D", "VFMAXA_D", "VFMINA_D", "VFCVT_S_D", 2162 "VFTINTRNE_W_D", "VFTINTRZ_W_D", "VFTINTRP_W_D", "VFTINTRM_W_D", 2163 "VFTINT_W_D", 2164 "VFCMP_CAF_D", "VFCMP_CUN_D", "VFCMP_CEQ_D", "VFCMP_CUEQ_D", 2165 "VFCMP_CLT_D", "VFCMP_CULT_D", "VFCMP_CLE_D", "VFCMP_CULE_D", 2166 "VFCMP_CNE_D", "VFCMP_COR_D", "VFCMP_CUNE_D", 2167 "VFCMP_SAF_D", "VFCMP_SUN_D", "VFCMP_SEQ_D", "VFCMP_SUEQ_D", 2168 "VFCMP_SLT_D", "VFCMP_SULT_D", "VFCMP_SLE_D", "VFCMP_SULE_D", 2169 "VFCMP_SNE_D", "VFCMP_SOR_D", "VFCMP_SUNE_D"] in 2170 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2171 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 2172 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2173 2174// vty: v4f32/v2f64 2175// Pat<(Intrinsic vty:$vj), 2176// (LAInst vty:$vj)>; 2177foreach Inst = ["VFLOGB_S", "VFCLASS_S", "VFSQRT_S", "VFRECIP_S", "VFRSQRT_S", 2178 "VFRINT_S", "VFCVTL_D_S", "VFCVTH_D_S", 2179 "VFRINTRNE_S", "VFRINTRZ_S", "VFRINTRP_S", "VFRINTRM_S", 2180 "VFTINTRNE_W_S", "VFTINTRZ_W_S", "VFTINTRP_W_S", "VFTINTRM_W_S", 2181 "VFTINT_W_S", "VFTINTRZ_WU_S", "VFTINT_WU_S", 2182 "VFTINTRNEL_L_S", "VFTINTRNEH_L_S", "VFTINTRZL_L_S", 2183 "VFTINTRZH_L_S", "VFTINTRPL_L_S", "VFTINTRPH_L_S", 2184 "VFTINTRML_L_S", "VFTINTRMH_L_S", "VFTINTL_L_S", 2185 "VFTINTH_L_S"] in 2186 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)), 2187 (!cast<LAInst>(Inst) LSX128:$vj)>; 2188foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D", 2189 "VFRINT_D", 2190 "VFRINTRNE_D", "VFRINTRZ_D", "VFRINTRP_D", "VFRINTRM_D", 2191 "VFTINTRNE_L_D", "VFTINTRZ_L_D", "VFTINTRP_L_D", "VFTINTRM_L_D", 2192 "VFTINT_L_D", "VFTINTRZ_LU_D", "VFTINT_LU_D"] in 2193 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)), 2194 (!cast<LAInst>(Inst) LSX128:$vj)>; 2195 2196// 128-Bit vector FP approximate reciprocal operation 2197let Predicates = [HasFrecipe] in { 2198foreach Inst = ["VFRECIPE_S", "VFRSQRTE_S"] in 2199 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)), 2200 (!cast<LAInst>(Inst) LSX128:$vj)>; 2201foreach Inst = ["VFRECIPE_D", "VFRSQRTE_D"] in 2202 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)), 2203 (!cast<LAInst>(Inst) LSX128:$vj)>; 2204} 2205 2206// load 2207def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm), 2208 (VLD GPR:$rj, (to_valid_timm timm:$imm))>; 2209def : Pat<(int_loongarch_lsx_vldx GPR:$rj, GPR:$rk), 2210 (VLDX GPR:$rj, GPR:$rk)>; 2211 2212def : Pat<(int_loongarch_lsx_vldrepl_b GPR:$rj, timm:$imm), 2213 (VLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>; 2214def : Pat<(int_loongarch_lsx_vldrepl_h GPR:$rj, timm:$imm), 2215 (VLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>; 2216def : Pat<(int_loongarch_lsx_vldrepl_w GPR:$rj, timm:$imm), 2217 (VLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>; 2218def : Pat<(int_loongarch_lsx_vldrepl_d GPR:$rj, timm:$imm), 2219 (VLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>; 2220 2221// store 2222def : Pat<(int_loongarch_lsx_vst LSX128:$vd, GPR:$rj, timm:$imm), 2223 (VST LSX128:$vd, GPR:$rj, (to_valid_timm timm:$imm))>; 2224def : Pat<(int_loongarch_lsx_vstx LSX128:$vd, GPR:$rj, GPR:$rk), 2225 (VSTX LSX128:$vd, GPR:$rj, GPR:$rk)>; 2226 2227def : Pat<(int_loongarch_lsx_vstelm_b v16i8:$vd, GPR:$rj, timm:$imm, timm:$idx), 2228 (VSTELM_B v16i8:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2229 (to_valid_timm timm:$idx))>; 2230def : Pat<(int_loongarch_lsx_vstelm_h v8i16:$vd, GPR:$rj, timm:$imm, timm:$idx), 2231 (VSTELM_H v8i16:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2232 (to_valid_timm timm:$idx))>; 2233def : Pat<(int_loongarch_lsx_vstelm_w v4i32:$vd, GPR:$rj, timm:$imm, timm:$idx), 2234 (VSTELM_W v4i32:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2235 (to_valid_timm timm:$idx))>; 2236def : Pat<(int_loongarch_lsx_vstelm_d v2i64:$vd, GPR:$rj, timm:$imm, timm:$idx), 2237 (VSTELM_D v2i64:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2238 (to_valid_timm timm:$idx))>; 2239 2240} // Predicates = [HasExtLSX] 2241