1//===- LoongArchLSXInstrInfo.td - LoongArch LSX instructions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the SIMD extension instructions. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 14 SDTCisInt<1>, SDTCisVec<1>, 15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>; 16def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 17 18def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>, 19 SDTCisInt<1>, SDTCisVec<1>, 20 SDTCisSameAs<0, 2>, 21 SDTCisSameAs<2, 3>]>; 22def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>, 23 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 24def SDT_loongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>, 25 SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>; 26 27// Target nodes. 28def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>; 29def loongarch_vall_nonzero : SDNode<"LoongArchISD::VALL_NONZERO", 30 SDT_LoongArchVecCond>; 31def loongarch_vany_nonzero : SDNode<"LoongArchISD::VANY_NONZERO", 32 SDT_LoongArchVecCond>; 33def loongarch_vall_zero : SDNode<"LoongArchISD::VALL_ZERO", 34 SDT_LoongArchVecCond>; 35def loongarch_vany_zero : SDNode<"LoongArchISD::VANY_ZERO", 36 SDT_LoongArchVecCond>; 37 38def loongarch_vpick_sext_elt : SDNode<"LoongArchISD::VPICK_SEXT_ELT", 39 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 40def loongarch_vpick_zext_elt : SDNode<"LoongArchISD::VPICK_ZEXT_ELT", 41 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>; 42 43def loongarch_vshuf: SDNode<"LoongArchISD::VSHUF", SDT_LoongArchVShuf>; 44def loongarch_vpickev: SDNode<"LoongArchISD::VPICKEV", SDT_LoongArchV2R>; 45def loongarch_vpickod: SDNode<"LoongArchISD::VPICKOD", SDT_LoongArchV2R>; 46def loongarch_vpackev: SDNode<"LoongArchISD::VPACKEV", SDT_LoongArchV2R>; 47def loongarch_vpackod: SDNode<"LoongArchISD::VPACKOD", SDT_LoongArchV2R>; 48def loongarch_vilvl: SDNode<"LoongArchISD::VILVL", SDT_LoongArchV2R>; 49def loongarch_vilvh: SDNode<"LoongArchISD::VILVH", SDT_LoongArchV2R>; 50 51def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_loongArchV1RUimm>; 52def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_loongArchV1RUimm>; 53 54def immZExt1 : ImmLeaf<i64, [{return isUInt<1>(Imm);}]>; 55def immZExt2 : ImmLeaf<i64, [{return isUInt<2>(Imm);}]>; 56def immZExt3 : ImmLeaf<i64, [{return isUInt<3>(Imm);}]>; 57def immZExt4 : ImmLeaf<i64, [{return isUInt<4>(Imm);}]>; 58def immZExt8 : ImmLeaf<i64, [{return isUInt<8>(Imm);}]>; 59 60class VecCond<SDPatternOperator OpNode, ValueType TyNode, 61 RegisterClass RC = LSX128> 62 : Pseudo<(outs GPR:$rd), (ins RC:$vj), 63 [(set GPR:$rd, (OpNode (TyNode RC:$vj)))]> { 64 let hasSideEffects = 0; 65 let mayLoad = 0; 66 let mayStore = 0; 67 let usesCustomInserter = 1; 68} 69 70def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector), 71 (bitconvert (v4i32 (build_vector)))], [{ 72 APInt Imm; 73 EVT EltTy = N->getValueType(0).getVectorElementType(); 74 75 if (N->getOpcode() == ISD::BITCAST) 76 N = N->getOperand(0).getNode(); 77 78 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 79 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 80}]>; 81 82def vsplati8_imm_eq_7 : PatFrags<(ops), [(build_vector)], [{ 83 APInt Imm; 84 EVT EltTy = N->getValueType(0).getVectorElementType(); 85 86 if (N->getOpcode() == ISD::BITCAST) 87 N = N->getOperand(0).getNode(); 88 89 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 90 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 7; 91}]>; 92def vsplati16_imm_eq_15 : PatFrags<(ops), [(build_vector)], [{ 93 APInt Imm; 94 EVT EltTy = N->getValueType(0).getVectorElementType(); 95 96 if (N->getOpcode() == ISD::BITCAST) 97 N = N->getOperand(0).getNode(); 98 99 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 100 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 15; 101}]>; 102def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{ 103 APInt Imm; 104 EVT EltTy = N->getValueType(0).getVectorElementType(); 105 106 if (N->getOpcode() == ISD::BITCAST) 107 N = N->getOperand(0).getNode(); 108 109 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 110 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31; 111}]>; 112def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector), 113 (bitconvert (v4i32 (build_vector)))], [{ 114 APInt Imm; 115 EVT EltTy = N->getValueType(0).getVectorElementType(); 116 117 if (N->getOpcode() == ISD::BITCAST) 118 N = N->getOperand(0).getNode(); 119 120 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 121 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 122}]>; 123 124def vsplatf32_fpimm_eq_1 125 : PatFrags<(ops), [(bitconvert (v4i32 (build_vector))), 126 (bitconvert (v8i32 (build_vector)))], [{ 127 APInt Imm; 128 EVT EltTy = N->getValueType(0).getVectorElementType(); 129 N = N->getOperand(0).getNode(); 130 131 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 132 Imm.getBitWidth() == EltTy.getSizeInBits() && 133 Imm == APFloat(+1.0f).bitcastToAPInt(); 134}]>; 135def vsplatf64_fpimm_eq_1 136 : PatFrags<(ops), [(bitconvert (v2i64 (build_vector))), 137 (bitconvert (v4i64 (build_vector)))], [{ 138 APInt Imm; 139 EVT EltTy = N->getValueType(0).getVectorElementType(); 140 N = N->getOperand(0).getNode(); 141 142 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 143 Imm.getBitWidth() == EltTy.getSizeInBits() && 144 Imm == APFloat(+1.0).bitcastToAPInt(); 145}]>; 146 147def vsplati8imm7 : PatFrag<(ops node:$reg), 148 (and node:$reg, vsplati8_imm_eq_7)>; 149def vsplati16imm15 : PatFrag<(ops node:$reg), 150 (and node:$reg, vsplati16_imm_eq_15)>; 151def vsplati32imm31 : PatFrag<(ops node:$reg), 152 (and node:$reg, vsplati32_imm_eq_31)>; 153def vsplati64imm63 : PatFrag<(ops node:$reg), 154 (and node:$reg, vsplati64_imm_eq_63)>; 155 156foreach N = [3, 4, 5, 6, 8] in 157 def SplatPat_uimm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#">", 158 [build_vector, bitconvert], [], 2>; 159 160foreach N = [5] in 161 def SplatPat_simm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#", true>", 162 [build_vector, bitconvert]>; 163 164def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 165 [build_vector, bitconvert]>; 166 167def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 168 [build_vector, bitconvert]>; 169 170def muladd : PatFrag<(ops node:$vd, node:$vj, node:$vk), 171 (add node:$vd, (mul node:$vj, node:$vk))>; 172 173def mulsub : PatFrag<(ops node:$vd, node:$vj, node:$vk), 174 (sub node:$vd, (mul node:$vj, node:$vk))>; 175 176def lsxsplati8 : PatFrag<(ops node:$e0), 177 (v16i8 (build_vector node:$e0, node:$e0, 178 node:$e0, node:$e0, 179 node:$e0, node:$e0, 180 node:$e0, node:$e0, 181 node:$e0, node:$e0, 182 node:$e0, node:$e0, 183 node:$e0, node:$e0, 184 node:$e0, node:$e0))>; 185def lsxsplati16 : PatFrag<(ops node:$e0), 186 (v8i16 (build_vector node:$e0, node:$e0, 187 node:$e0, node:$e0, 188 node:$e0, node:$e0, 189 node:$e0, node:$e0))>; 190def lsxsplati32 : PatFrag<(ops node:$e0), 191 (v4i32 (build_vector node:$e0, node:$e0, 192 node:$e0, node:$e0))>; 193def lsxsplati64 : PatFrag<(ops node:$e0), 194 (v2i64 (build_vector node:$e0, node:$e0))>; 195def lsxsplatf32 : PatFrag<(ops node:$e0), 196 (v4f32 (build_vector node:$e0, node:$e0, 197 node:$e0, node:$e0))>; 198def lsxsplatf64 : PatFrag<(ops node:$e0), 199 (v2f64 (build_vector node:$e0, node:$e0))>; 200 201def to_valid_timm : SDNodeXForm<timm, [{ 202 auto CN = cast<ConstantSDNode>(N); 203 return CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(N), Subtarget->getGRLenVT()); 204}]>; 205 206//===----------------------------------------------------------------------===// 207// Instruction class templates 208//===----------------------------------------------------------------------===// 209 210class LSX1RI13_VI<bits<32> op, Operand ImmOpnd = simm13> 211 : Fmt1RI13_VI<op, (outs LSX128:$vd), (ins ImmOpnd:$imm13), "$vd, $imm13">; 212 213class LSX2R_VV<bits<32> op> 214 : Fmt2R_VV<op, (outs LSX128:$vd), (ins LSX128:$vj), "$vd, $vj">; 215 216class LSX2R_VR<bits<32> op> 217 : Fmt2R_VR<op, (outs LSX128:$vd), (ins GPR:$rj), "$vd, $rj">; 218 219class LSX2R_CV<bits<32> op> 220 : Fmt2R_CV<op, (outs CFR:$cd), (ins LSX128:$vj), "$cd, $vj">; 221 222class LSX2RI1_VVI<bits<32> op, Operand ImmOpnd = uimm1> 223 : Fmt2RI1_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm1), 224 "$vd, $vj, $imm1">; 225 226class LSX2RI1_RVI<bits<32> op, Operand ImmOpnd = uimm1> 227 : Fmt2RI1_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm1), 228 "$rd, $vj, $imm1">; 229 230class LSX2RI2_VVI<bits<32> op, Operand ImmOpnd = uimm2> 231 : Fmt2RI2_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm2), 232 "$vd, $vj, $imm2">; 233 234class LSX2RI2_RVI<bits<32> op, Operand ImmOpnd = uimm2> 235 : Fmt2RI2_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm2), 236 "$rd, $vj, $imm2">; 237 238class LSX2RI3_VVI<bits<32> op, Operand ImmOpnd = uimm3> 239 : Fmt2RI3_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm3), 240 "$vd, $vj, $imm3">; 241 242class LSX2RI3_RVI<bits<32> op, Operand ImmOpnd = uimm3> 243 : Fmt2RI3_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm3), 244 "$rd, $vj, $imm3">; 245 246class LSX2RI4_VVI<bits<32> op, Operand ImmOpnd = uimm4> 247 : Fmt2RI4_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm4), 248 "$vd, $vj, $imm4">; 249 250class LSX2RI4_RVI<bits<32> op, Operand ImmOpnd = uimm4> 251 : Fmt2RI4_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm4), 252 "$rd, $vj, $imm4">; 253 254class LSX2RI5_VVI<bits<32> op, Operand ImmOpnd = uimm5> 255 : Fmt2RI5_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm5), 256 "$vd, $vj, $imm5">; 257 258class LSX2RI6_VVI<bits<32> op, Operand ImmOpnd = uimm6> 259 : Fmt2RI6_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm6), 260 "$vd, $vj, $imm6">; 261 262class LSX2RI8_VVI<bits<32> op, Operand ImmOpnd = uimm8> 263 : Fmt2RI8_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm8), 264 "$vd, $vj, $imm8">; 265 266class LSX2RI8I1_VRII<bits<32> op, Operand ImmOpnd = simm8, 267 Operand IdxOpnd = uimm1> 268 : Fmt2RI8I1_VRII<op, (outs), 269 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm1), 270 "$vd, $rj, $imm8, $imm1">; 271class LSX2RI8I2_VRII<bits<32> op, Operand ImmOpnd = simm8, 272 Operand IdxOpnd = uimm2> 273 : Fmt2RI8I2_VRII<op, (outs), 274 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2), 275 "$vd, $rj, $imm8, $imm2">; 276class LSX2RI8I3_VRII<bits<32> op, Operand ImmOpnd = simm8, 277 Operand IdxOpnd = uimm3> 278 : Fmt2RI8I3_VRII<op, (outs), 279 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3), 280 "$vd, $rj, $imm8, $imm3">; 281class LSX2RI8I4_VRII<bits<32> op, Operand ImmOpnd = simm8, 282 Operand IdxOpnd = uimm4> 283 : Fmt2RI8I4_VRII<op, (outs), 284 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4), 285 "$vd, $rj, $imm8, $imm4">; 286 287class LSX3R_VVV<bits<32> op> 288 : Fmt3R_VVV<op, (outs LSX128:$vd), (ins LSX128:$vj, LSX128:$vk), 289 "$vd, $vj, $vk">; 290 291class LSX3R_VVR<bits<32> op> 292 : Fmt3R_VVR<op, (outs LSX128:$vd), (ins LSX128:$vj, GPR:$rk), 293 "$vd, $vj, $rk">; 294 295class LSX4R_VVVV<bits<32> op> 296 : Fmt4R_VVVV<op, (outs LSX128:$vd), 297 (ins LSX128:$vj, LSX128:$vk, LSX128:$va), 298 "$vd, $vj, $vk, $va">; 299 300let Constraints = "$vd = $dst" in { 301 302class LSX2RI1_VVRI<bits<32> op, Operand ImmOpnd = uimm1> 303 : Fmt2RI1_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm1), 304 "$vd, $rj, $imm1">; 305class LSX2RI2_VVRI<bits<32> op, Operand ImmOpnd = uimm2> 306 : Fmt2RI2_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm2), 307 "$vd, $rj, $imm2">; 308class LSX2RI3_VVRI<bits<32> op, Operand ImmOpnd = uimm3> 309 : Fmt2RI3_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm3), 310 "$vd, $rj, $imm3">; 311class LSX2RI4_VVRI<bits<32> op, Operand ImmOpnd = uimm4> 312 : Fmt2RI4_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm4), 313 "$vd, $rj, $imm4">; 314 315class LSX2RI4_VVVI<bits<32> op, Operand ImmOpnd = uimm4> 316 : Fmt2RI4_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm4), 317 "$vd, $vj, $imm4">; 318class LSX2RI5_VVVI<bits<32> op, Operand ImmOpnd = uimm5> 319 : Fmt2RI5_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm5), 320 "$vd, $vj, $imm5">; 321class LSX2RI6_VVVI<bits<32> op, Operand ImmOpnd = uimm6> 322 : Fmt2RI6_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm6), 323 "$vd, $vj, $imm6">; 324class LSX2RI7_VVVI<bits<32> op, Operand ImmOpnd = uimm7> 325 : Fmt2RI7_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm7), 326 "$vd, $vj, $imm7">; 327 328class LSX2RI8_VVVI<bits<32> op, Operand ImmOpnd = uimm8> 329 : Fmt2RI8_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm8), 330 "$vd, $vj, $imm8">; 331 332class LSX3R_VVVV<bits<32> op> 333 : Fmt3R_VVV<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, LSX128:$vk), 334 "$vd, $vj, $vk">; 335 336} // Constraints = "$vd = $dst" 337 338class LSX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3> 339 : Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9), 340 "$vd, $rj, $imm9">; 341class LSX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2> 342 : Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10), 343 "$vd, $rj, $imm10">; 344class LSX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1> 345 : Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11), 346 "$vd, $rj, $imm11">; 347class LSX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12> 348 : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12), 349 "$vd, $rj, $imm12">; 350class LSX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12> 351 : Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12), 352 "$vd, $rj, $imm12">; 353 354class LSX3R_Load<bits<32> op> 355 : Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk), 356 "$vd, $rj, $rk">; 357class LSX3R_Store<bits<32> op> 358 : Fmt3R_VRR<op, (outs), (ins LSX128:$vd, GPR:$rj, GPR:$rk), 359 "$vd, $rj, $rk">; 360 361//===----------------------------------------------------------------------===// 362// Instructions 363//===----------------------------------------------------------------------===// 364 365let hasSideEffects = 0, Predicates = [HasExtLSX] in { 366 367let mayLoad = 0, mayStore = 0 in { 368 369def VADD_B : LSX3R_VVV<0x700a0000>; 370def VADD_H : LSX3R_VVV<0x700a8000>; 371def VADD_W : LSX3R_VVV<0x700b0000>; 372def VADD_D : LSX3R_VVV<0x700b8000>; 373def VADD_Q : LSX3R_VVV<0x712d0000>; 374 375def VSUB_B : LSX3R_VVV<0x700c0000>; 376def VSUB_H : LSX3R_VVV<0x700c8000>; 377def VSUB_W : LSX3R_VVV<0x700d0000>; 378def VSUB_D : LSX3R_VVV<0x700d8000>; 379def VSUB_Q : LSX3R_VVV<0x712d8000>; 380 381def VADDI_BU : LSX2RI5_VVI<0x728a0000>; 382def VADDI_HU : LSX2RI5_VVI<0x728a8000>; 383def VADDI_WU : LSX2RI5_VVI<0x728b0000>; 384def VADDI_DU : LSX2RI5_VVI<0x728b8000>; 385 386def VSUBI_BU : LSX2RI5_VVI<0x728c0000>; 387def VSUBI_HU : LSX2RI5_VVI<0x728c8000>; 388def VSUBI_WU : LSX2RI5_VVI<0x728d0000>; 389def VSUBI_DU : LSX2RI5_VVI<0x728d8000>; 390 391def VNEG_B : LSX2R_VV<0x729c3000>; 392def VNEG_H : LSX2R_VV<0x729c3400>; 393def VNEG_W : LSX2R_VV<0x729c3800>; 394def VNEG_D : LSX2R_VV<0x729c3c00>; 395 396def VSADD_B : LSX3R_VVV<0x70460000>; 397def VSADD_H : LSX3R_VVV<0x70468000>; 398def VSADD_W : LSX3R_VVV<0x70470000>; 399def VSADD_D : LSX3R_VVV<0x70478000>; 400def VSADD_BU : LSX3R_VVV<0x704a0000>; 401def VSADD_HU : LSX3R_VVV<0x704a8000>; 402def VSADD_WU : LSX3R_VVV<0x704b0000>; 403def VSADD_DU : LSX3R_VVV<0x704b8000>; 404 405def VSSUB_B : LSX3R_VVV<0x70480000>; 406def VSSUB_H : LSX3R_VVV<0x70488000>; 407def VSSUB_W : LSX3R_VVV<0x70490000>; 408def VSSUB_D : LSX3R_VVV<0x70498000>; 409def VSSUB_BU : LSX3R_VVV<0x704c0000>; 410def VSSUB_HU : LSX3R_VVV<0x704c8000>; 411def VSSUB_WU : LSX3R_VVV<0x704d0000>; 412def VSSUB_DU : LSX3R_VVV<0x704d8000>; 413 414def VHADDW_H_B : LSX3R_VVV<0x70540000>; 415def VHADDW_W_H : LSX3R_VVV<0x70548000>; 416def VHADDW_D_W : LSX3R_VVV<0x70550000>; 417def VHADDW_Q_D : LSX3R_VVV<0x70558000>; 418def VHADDW_HU_BU : LSX3R_VVV<0x70580000>; 419def VHADDW_WU_HU : LSX3R_VVV<0x70588000>; 420def VHADDW_DU_WU : LSX3R_VVV<0x70590000>; 421def VHADDW_QU_DU : LSX3R_VVV<0x70598000>; 422 423def VHSUBW_H_B : LSX3R_VVV<0x70560000>; 424def VHSUBW_W_H : LSX3R_VVV<0x70568000>; 425def VHSUBW_D_W : LSX3R_VVV<0x70570000>; 426def VHSUBW_Q_D : LSX3R_VVV<0x70578000>; 427def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>; 428def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>; 429def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>; 430def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>; 431 432def VADDWEV_H_B : LSX3R_VVV<0x701e0000>; 433def VADDWEV_W_H : LSX3R_VVV<0x701e8000>; 434def VADDWEV_D_W : LSX3R_VVV<0x701f0000>; 435def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>; 436def VADDWOD_H_B : LSX3R_VVV<0x70220000>; 437def VADDWOD_W_H : LSX3R_VVV<0x70228000>; 438def VADDWOD_D_W : LSX3R_VVV<0x70230000>; 439def VADDWOD_Q_D : LSX3R_VVV<0x70238000>; 440 441def VSUBWEV_H_B : LSX3R_VVV<0x70200000>; 442def VSUBWEV_W_H : LSX3R_VVV<0x70208000>; 443def VSUBWEV_D_W : LSX3R_VVV<0x70210000>; 444def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>; 445def VSUBWOD_H_B : LSX3R_VVV<0x70240000>; 446def VSUBWOD_W_H : LSX3R_VVV<0x70248000>; 447def VSUBWOD_D_W : LSX3R_VVV<0x70250000>; 448def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>; 449 450def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>; 451def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>; 452def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>; 453def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>; 454def VADDWOD_H_BU : LSX3R_VVV<0x70320000>; 455def VADDWOD_W_HU : LSX3R_VVV<0x70328000>; 456def VADDWOD_D_WU : LSX3R_VVV<0x70330000>; 457def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>; 458 459def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>; 460def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>; 461def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>; 462def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>; 463def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>; 464def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>; 465def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>; 466def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>; 467 468def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>; 469def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>; 470def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>; 471def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>; 472def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>; 473def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>; 474def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>; 475def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>; 476 477def VAVG_B : LSX3R_VVV<0x70640000>; 478def VAVG_H : LSX3R_VVV<0x70648000>; 479def VAVG_W : LSX3R_VVV<0x70650000>; 480def VAVG_D : LSX3R_VVV<0x70658000>; 481def VAVG_BU : LSX3R_VVV<0x70660000>; 482def VAVG_HU : LSX3R_VVV<0x70668000>; 483def VAVG_WU : LSX3R_VVV<0x70670000>; 484def VAVG_DU : LSX3R_VVV<0x70678000>; 485def VAVGR_B : LSX3R_VVV<0x70680000>; 486def VAVGR_H : LSX3R_VVV<0x70688000>; 487def VAVGR_W : LSX3R_VVV<0x70690000>; 488def VAVGR_D : LSX3R_VVV<0x70698000>; 489def VAVGR_BU : LSX3R_VVV<0x706a0000>; 490def VAVGR_HU : LSX3R_VVV<0x706a8000>; 491def VAVGR_WU : LSX3R_VVV<0x706b0000>; 492def VAVGR_DU : LSX3R_VVV<0x706b8000>; 493 494def VABSD_B : LSX3R_VVV<0x70600000>; 495def VABSD_H : LSX3R_VVV<0x70608000>; 496def VABSD_W : LSX3R_VVV<0x70610000>; 497def VABSD_D : LSX3R_VVV<0x70618000>; 498def VABSD_BU : LSX3R_VVV<0x70620000>; 499def VABSD_HU : LSX3R_VVV<0x70628000>; 500def VABSD_WU : LSX3R_VVV<0x70630000>; 501def VABSD_DU : LSX3R_VVV<0x70638000>; 502 503def VADDA_B : LSX3R_VVV<0x705c0000>; 504def VADDA_H : LSX3R_VVV<0x705c8000>; 505def VADDA_W : LSX3R_VVV<0x705d0000>; 506def VADDA_D : LSX3R_VVV<0x705d8000>; 507 508def VMAX_B : LSX3R_VVV<0x70700000>; 509def VMAX_H : LSX3R_VVV<0x70708000>; 510def VMAX_W : LSX3R_VVV<0x70710000>; 511def VMAX_D : LSX3R_VVV<0x70718000>; 512def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>; 513def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>; 514def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>; 515def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>; 516def VMAX_BU : LSX3R_VVV<0x70740000>; 517def VMAX_HU : LSX3R_VVV<0x70748000>; 518def VMAX_WU : LSX3R_VVV<0x70750000>; 519def VMAX_DU : LSX3R_VVV<0x70758000>; 520def VMAXI_BU : LSX2RI5_VVI<0x72940000>; 521def VMAXI_HU : LSX2RI5_VVI<0x72948000>; 522def VMAXI_WU : LSX2RI5_VVI<0x72950000>; 523def VMAXI_DU : LSX2RI5_VVI<0x72958000>; 524 525def VMIN_B : LSX3R_VVV<0x70720000>; 526def VMIN_H : LSX3R_VVV<0x70728000>; 527def VMIN_W : LSX3R_VVV<0x70730000>; 528def VMIN_D : LSX3R_VVV<0x70738000>; 529def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>; 530def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>; 531def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>; 532def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>; 533def VMIN_BU : LSX3R_VVV<0x70760000>; 534def VMIN_HU : LSX3R_VVV<0x70768000>; 535def VMIN_WU : LSX3R_VVV<0x70770000>; 536def VMIN_DU : LSX3R_VVV<0x70778000>; 537def VMINI_BU : LSX2RI5_VVI<0x72960000>; 538def VMINI_HU : LSX2RI5_VVI<0x72968000>; 539def VMINI_WU : LSX2RI5_VVI<0x72970000>; 540def VMINI_DU : LSX2RI5_VVI<0x72978000>; 541 542def VMUL_B : LSX3R_VVV<0x70840000>; 543def VMUL_H : LSX3R_VVV<0x70848000>; 544def VMUL_W : LSX3R_VVV<0x70850000>; 545def VMUL_D : LSX3R_VVV<0x70858000>; 546 547def VMUH_B : LSX3R_VVV<0x70860000>; 548def VMUH_H : LSX3R_VVV<0x70868000>; 549def VMUH_W : LSX3R_VVV<0x70870000>; 550def VMUH_D : LSX3R_VVV<0x70878000>; 551def VMUH_BU : LSX3R_VVV<0x70880000>; 552def VMUH_HU : LSX3R_VVV<0x70888000>; 553def VMUH_WU : LSX3R_VVV<0x70890000>; 554def VMUH_DU : LSX3R_VVV<0x70898000>; 555 556def VMULWEV_H_B : LSX3R_VVV<0x70900000>; 557def VMULWEV_W_H : LSX3R_VVV<0x70908000>; 558def VMULWEV_D_W : LSX3R_VVV<0x70910000>; 559def VMULWEV_Q_D : LSX3R_VVV<0x70918000>; 560def VMULWOD_H_B : LSX3R_VVV<0x70920000>; 561def VMULWOD_W_H : LSX3R_VVV<0x70928000>; 562def VMULWOD_D_W : LSX3R_VVV<0x70930000>; 563def VMULWOD_Q_D : LSX3R_VVV<0x70938000>; 564def VMULWEV_H_BU : LSX3R_VVV<0x70980000>; 565def VMULWEV_W_HU : LSX3R_VVV<0x70988000>; 566def VMULWEV_D_WU : LSX3R_VVV<0x70990000>; 567def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>; 568def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>; 569def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>; 570def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>; 571def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>; 572def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>; 573def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>; 574def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>; 575def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>; 576def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>; 577def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>; 578def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>; 579def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>; 580 581def VMADD_B : LSX3R_VVVV<0x70a80000>; 582def VMADD_H : LSX3R_VVVV<0x70a88000>; 583def VMADD_W : LSX3R_VVVV<0x70a90000>; 584def VMADD_D : LSX3R_VVVV<0x70a98000>; 585 586def VMSUB_B : LSX3R_VVVV<0x70aa0000>; 587def VMSUB_H : LSX3R_VVVV<0x70aa8000>; 588def VMSUB_W : LSX3R_VVVV<0x70ab0000>; 589def VMSUB_D : LSX3R_VVVV<0x70ab8000>; 590 591def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>; 592def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>; 593def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>; 594def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>; 595def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>; 596def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>; 597def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>; 598def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>; 599def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>; 600def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>; 601def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>; 602def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>; 603def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>; 604def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>; 605def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>; 606def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>; 607def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>; 608def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>; 609def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>; 610def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>; 611def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>; 612def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>; 613def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>; 614def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>; 615 616def VDIV_B : LSX3R_VVV<0x70e00000>; 617def VDIV_H : LSX3R_VVV<0x70e08000>; 618def VDIV_W : LSX3R_VVV<0x70e10000>; 619def VDIV_D : LSX3R_VVV<0x70e18000>; 620def VDIV_BU : LSX3R_VVV<0x70e40000>; 621def VDIV_HU : LSX3R_VVV<0x70e48000>; 622def VDIV_WU : LSX3R_VVV<0x70e50000>; 623def VDIV_DU : LSX3R_VVV<0x70e58000>; 624 625def VMOD_B : LSX3R_VVV<0x70e20000>; 626def VMOD_H : LSX3R_VVV<0x70e28000>; 627def VMOD_W : LSX3R_VVV<0x70e30000>; 628def VMOD_D : LSX3R_VVV<0x70e38000>; 629def VMOD_BU : LSX3R_VVV<0x70e60000>; 630def VMOD_HU : LSX3R_VVV<0x70e68000>; 631def VMOD_WU : LSX3R_VVV<0x70e70000>; 632def VMOD_DU : LSX3R_VVV<0x70e78000>; 633 634def VSAT_B : LSX2RI3_VVI<0x73242000>; 635def VSAT_H : LSX2RI4_VVI<0x73244000>; 636def VSAT_W : LSX2RI5_VVI<0x73248000>; 637def VSAT_D : LSX2RI6_VVI<0x73250000>; 638def VSAT_BU : LSX2RI3_VVI<0x73282000>; 639def VSAT_HU : LSX2RI4_VVI<0x73284000>; 640def VSAT_WU : LSX2RI5_VVI<0x73288000>; 641def VSAT_DU : LSX2RI6_VVI<0x73290000>; 642 643def VEXTH_H_B : LSX2R_VV<0x729ee000>; 644def VEXTH_W_H : LSX2R_VV<0x729ee400>; 645def VEXTH_D_W : LSX2R_VV<0x729ee800>; 646def VEXTH_Q_D : LSX2R_VV<0x729eec00>; 647def VEXTH_HU_BU : LSX2R_VV<0x729ef000>; 648def VEXTH_WU_HU : LSX2R_VV<0x729ef400>; 649def VEXTH_DU_WU : LSX2R_VV<0x729ef800>; 650def VEXTH_QU_DU : LSX2R_VV<0x729efc00>; 651 652def VSIGNCOV_B : LSX3R_VVV<0x712e0000>; 653def VSIGNCOV_H : LSX3R_VVV<0x712e8000>; 654def VSIGNCOV_W : LSX3R_VVV<0x712f0000>; 655def VSIGNCOV_D : LSX3R_VVV<0x712f8000>; 656 657def VMSKLTZ_B : LSX2R_VV<0x729c4000>; 658def VMSKLTZ_H : LSX2R_VV<0x729c4400>; 659def VMSKLTZ_W : LSX2R_VV<0x729c4800>; 660def VMSKLTZ_D : LSX2R_VV<0x729c4c00>; 661 662def VMSKGEZ_B : LSX2R_VV<0x729c5000>; 663 664def VMSKNZ_B : LSX2R_VV<0x729c6000>; 665 666def VLDI : LSX1RI13_VI<0x73e00000>; 667 668def VAND_V : LSX3R_VVV<0x71260000>; 669def VOR_V : LSX3R_VVV<0x71268000>; 670def VXOR_V : LSX3R_VVV<0x71270000>; 671def VNOR_V : LSX3R_VVV<0x71278000>; 672def VANDN_V : LSX3R_VVV<0x71280000>; 673def VORN_V : LSX3R_VVV<0x71288000>; 674 675def VANDI_B : LSX2RI8_VVI<0x73d00000>; 676def VORI_B : LSX2RI8_VVI<0x73d40000>; 677def VXORI_B : LSX2RI8_VVI<0x73d80000>; 678def VNORI_B : LSX2RI8_VVI<0x73dc0000>; 679 680def VSLL_B : LSX3R_VVV<0x70e80000>; 681def VSLL_H : LSX3R_VVV<0x70e88000>; 682def VSLL_W : LSX3R_VVV<0x70e90000>; 683def VSLL_D : LSX3R_VVV<0x70e98000>; 684def VSLLI_B : LSX2RI3_VVI<0x732c2000>; 685def VSLLI_H : LSX2RI4_VVI<0x732c4000>; 686def VSLLI_W : LSX2RI5_VVI<0x732c8000>; 687def VSLLI_D : LSX2RI6_VVI<0x732d0000>; 688 689def VSRL_B : LSX3R_VVV<0x70ea0000>; 690def VSRL_H : LSX3R_VVV<0x70ea8000>; 691def VSRL_W : LSX3R_VVV<0x70eb0000>; 692def VSRL_D : LSX3R_VVV<0x70eb8000>; 693def VSRLI_B : LSX2RI3_VVI<0x73302000>; 694def VSRLI_H : LSX2RI4_VVI<0x73304000>; 695def VSRLI_W : LSX2RI5_VVI<0x73308000>; 696def VSRLI_D : LSX2RI6_VVI<0x73310000>; 697 698def VSRA_B : LSX3R_VVV<0x70ec0000>; 699def VSRA_H : LSX3R_VVV<0x70ec8000>; 700def VSRA_W : LSX3R_VVV<0x70ed0000>; 701def VSRA_D : LSX3R_VVV<0x70ed8000>; 702def VSRAI_B : LSX2RI3_VVI<0x73342000>; 703def VSRAI_H : LSX2RI4_VVI<0x73344000>; 704def VSRAI_W : LSX2RI5_VVI<0x73348000>; 705def VSRAI_D : LSX2RI6_VVI<0x73350000>; 706 707def VROTR_B : LSX3R_VVV<0x70ee0000>; 708def VROTR_H : LSX3R_VVV<0x70ee8000>; 709def VROTR_W : LSX3R_VVV<0x70ef0000>; 710def VROTR_D : LSX3R_VVV<0x70ef8000>; 711def VROTRI_B : LSX2RI3_VVI<0x72a02000>; 712def VROTRI_H : LSX2RI4_VVI<0x72a04000>; 713def VROTRI_W : LSX2RI5_VVI<0x72a08000>; 714def VROTRI_D : LSX2RI6_VVI<0x72a10000>; 715 716def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>; 717def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>; 718def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>; 719def VEXTL_Q_D : LSX2R_VV<0x73090000>; 720def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>; 721def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>; 722def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>; 723def VEXTL_QU_DU : LSX2R_VV<0x730d0000>; 724 725def VSRLR_B : LSX3R_VVV<0x70f00000>; 726def VSRLR_H : LSX3R_VVV<0x70f08000>; 727def VSRLR_W : LSX3R_VVV<0x70f10000>; 728def VSRLR_D : LSX3R_VVV<0x70f18000>; 729def VSRLRI_B : LSX2RI3_VVI<0x72a42000>; 730def VSRLRI_H : LSX2RI4_VVI<0x72a44000>; 731def VSRLRI_W : LSX2RI5_VVI<0x72a48000>; 732def VSRLRI_D : LSX2RI6_VVI<0x72a50000>; 733 734def VSRAR_B : LSX3R_VVV<0x70f20000>; 735def VSRAR_H : LSX3R_VVV<0x70f28000>; 736def VSRAR_W : LSX3R_VVV<0x70f30000>; 737def VSRAR_D : LSX3R_VVV<0x70f38000>; 738def VSRARI_B : LSX2RI3_VVI<0x72a82000>; 739def VSRARI_H : LSX2RI4_VVI<0x72a84000>; 740def VSRARI_W : LSX2RI5_VVI<0x72a88000>; 741def VSRARI_D : LSX2RI6_VVI<0x72a90000>; 742 743def VSRLN_B_H : LSX3R_VVV<0x70f48000>; 744def VSRLN_H_W : LSX3R_VVV<0x70f50000>; 745def VSRLN_W_D : LSX3R_VVV<0x70f58000>; 746def VSRAN_B_H : LSX3R_VVV<0x70f68000>; 747def VSRAN_H_W : LSX3R_VVV<0x70f70000>; 748def VSRAN_W_D : LSX3R_VVV<0x70f78000>; 749 750def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>; 751def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>; 752def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>; 753def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>; 754def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>; 755def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>; 756def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>; 757def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>; 758 759def VSRLRN_B_H : LSX3R_VVV<0x70f88000>; 760def VSRLRN_H_W : LSX3R_VVV<0x70f90000>; 761def VSRLRN_W_D : LSX3R_VVV<0x70f98000>; 762def VSRARN_B_H : LSX3R_VVV<0x70fa8000>; 763def VSRARN_H_W : LSX3R_VVV<0x70fb0000>; 764def VSRARN_W_D : LSX3R_VVV<0x70fb8000>; 765 766def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>; 767def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>; 768def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>; 769def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>; 770def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>; 771def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>; 772def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>; 773def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>; 774 775def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>; 776def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>; 777def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>; 778def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>; 779def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>; 780def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>; 781def VSSRLN_BU_H : LSX3R_VVV<0x71048000>; 782def VSSRLN_HU_W : LSX3R_VVV<0x71050000>; 783def VSSRLN_WU_D : LSX3R_VVV<0x71058000>; 784def VSSRAN_BU_H : LSX3R_VVV<0x71068000>; 785def VSSRAN_HU_W : LSX3R_VVV<0x71070000>; 786def VSSRAN_WU_D : LSX3R_VVV<0x71078000>; 787 788def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>; 789def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>; 790def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>; 791def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>; 792def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>; 793def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>; 794def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>; 795def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>; 796def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>; 797def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>; 798def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>; 799def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>; 800def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>; 801def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>; 802def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>; 803def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>; 804 805def VSSRLRN_B_H : LSX3R_VVV<0x71008000>; 806def VSSRLRN_H_W : LSX3R_VVV<0x71010000>; 807def VSSRLRN_W_D : LSX3R_VVV<0x71018000>; 808def VSSRARN_B_H : LSX3R_VVV<0x71028000>; 809def VSSRARN_H_W : LSX3R_VVV<0x71030000>; 810def VSSRARN_W_D : LSX3R_VVV<0x71038000>; 811def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>; 812def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>; 813def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>; 814def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>; 815def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>; 816def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>; 817 818def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>; 819def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>; 820def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>; 821def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>; 822def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>; 823def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>; 824def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>; 825def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>; 826def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>; 827def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>; 828def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>; 829def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>; 830def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>; 831def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>; 832def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>; 833def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>; 834 835def VCLO_B : LSX2R_VV<0x729c0000>; 836def VCLO_H : LSX2R_VV<0x729c0400>; 837def VCLO_W : LSX2R_VV<0x729c0800>; 838def VCLO_D : LSX2R_VV<0x729c0c00>; 839def VCLZ_B : LSX2R_VV<0x729c1000>; 840def VCLZ_H : LSX2R_VV<0x729c1400>; 841def VCLZ_W : LSX2R_VV<0x729c1800>; 842def VCLZ_D : LSX2R_VV<0x729c1c00>; 843 844def VPCNT_B : LSX2R_VV<0x729c2000>; 845def VPCNT_H : LSX2R_VV<0x729c2400>; 846def VPCNT_W : LSX2R_VV<0x729c2800>; 847def VPCNT_D : LSX2R_VV<0x729c2c00>; 848 849def VBITCLR_B : LSX3R_VVV<0x710c0000>; 850def VBITCLR_H : LSX3R_VVV<0x710c8000>; 851def VBITCLR_W : LSX3R_VVV<0x710d0000>; 852def VBITCLR_D : LSX3R_VVV<0x710d8000>; 853def VBITCLRI_B : LSX2RI3_VVI<0x73102000>; 854def VBITCLRI_H : LSX2RI4_VVI<0x73104000>; 855def VBITCLRI_W : LSX2RI5_VVI<0x73108000>; 856def VBITCLRI_D : LSX2RI6_VVI<0x73110000>; 857 858def VBITSET_B : LSX3R_VVV<0x710e0000>; 859def VBITSET_H : LSX3R_VVV<0x710e8000>; 860def VBITSET_W : LSX3R_VVV<0x710f0000>; 861def VBITSET_D : LSX3R_VVV<0x710f8000>; 862def VBITSETI_B : LSX2RI3_VVI<0x73142000>; 863def VBITSETI_H : LSX2RI4_VVI<0x73144000>; 864def VBITSETI_W : LSX2RI5_VVI<0x73148000>; 865def VBITSETI_D : LSX2RI6_VVI<0x73150000>; 866 867def VBITREV_B : LSX3R_VVV<0x71100000>; 868def VBITREV_H : LSX3R_VVV<0x71108000>; 869def VBITREV_W : LSX3R_VVV<0x71110000>; 870def VBITREV_D : LSX3R_VVV<0x71118000>; 871def VBITREVI_B : LSX2RI3_VVI<0x73182000>; 872def VBITREVI_H : LSX2RI4_VVI<0x73184000>; 873def VBITREVI_W : LSX2RI5_VVI<0x73188000>; 874def VBITREVI_D : LSX2RI6_VVI<0x73190000>; 875 876def VFRSTP_B : LSX3R_VVVV<0x712b0000>; 877def VFRSTP_H : LSX3R_VVVV<0x712b8000>; 878def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>; 879def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>; 880 881def VFADD_S : LSX3R_VVV<0x71308000>; 882def VFADD_D : LSX3R_VVV<0x71310000>; 883def VFSUB_S : LSX3R_VVV<0x71328000>; 884def VFSUB_D : LSX3R_VVV<0x71330000>; 885def VFMUL_S : LSX3R_VVV<0x71388000>; 886def VFMUL_D : LSX3R_VVV<0x71390000>; 887def VFDIV_S : LSX3R_VVV<0x713a8000>; 888def VFDIV_D : LSX3R_VVV<0x713b0000>; 889 890def VFMADD_S : LSX4R_VVVV<0x09100000>; 891def VFMADD_D : LSX4R_VVVV<0x09200000>; 892def VFMSUB_S : LSX4R_VVVV<0x09500000>; 893def VFMSUB_D : LSX4R_VVVV<0x09600000>; 894def VFNMADD_S : LSX4R_VVVV<0x09900000>; 895def VFNMADD_D : LSX4R_VVVV<0x09a00000>; 896def VFNMSUB_S : LSX4R_VVVV<0x09d00000>; 897def VFNMSUB_D : LSX4R_VVVV<0x09e00000>; 898 899def VFMAX_S : LSX3R_VVV<0x713c8000>; 900def VFMAX_D : LSX3R_VVV<0x713d0000>; 901def VFMIN_S : LSX3R_VVV<0x713e8000>; 902def VFMIN_D : LSX3R_VVV<0x713f0000>; 903 904def VFMAXA_S : LSX3R_VVV<0x71408000>; 905def VFMAXA_D : LSX3R_VVV<0x71410000>; 906def VFMINA_S : LSX3R_VVV<0x71428000>; 907def VFMINA_D : LSX3R_VVV<0x71430000>; 908 909def VFLOGB_S : LSX2R_VV<0x729cc400>; 910def VFLOGB_D : LSX2R_VV<0x729cc800>; 911 912def VFCLASS_S : LSX2R_VV<0x729cd400>; 913def VFCLASS_D : LSX2R_VV<0x729cd800>; 914 915def VFSQRT_S : LSX2R_VV<0x729ce400>; 916def VFSQRT_D : LSX2R_VV<0x729ce800>; 917def VFRECIP_S : LSX2R_VV<0x729cf400>; 918def VFRECIP_D : LSX2R_VV<0x729cf800>; 919def VFRSQRT_S : LSX2R_VV<0x729d0400>; 920def VFRSQRT_D : LSX2R_VV<0x729d0800>; 921def VFRECIPE_S : LSX2R_VV<0x729d1400>; 922def VFRECIPE_D : LSX2R_VV<0x729d1800>; 923def VFRSQRTE_S : LSX2R_VV<0x729d2400>; 924def VFRSQRTE_D : LSX2R_VV<0x729d2800>; 925 926def VFCVTL_S_H : LSX2R_VV<0x729de800>; 927def VFCVTH_S_H : LSX2R_VV<0x729dec00>; 928def VFCVTL_D_S : LSX2R_VV<0x729df000>; 929def VFCVTH_D_S : LSX2R_VV<0x729df400>; 930def VFCVT_H_S : LSX3R_VVV<0x71460000>; 931def VFCVT_S_D : LSX3R_VVV<0x71468000>; 932 933def VFRINTRNE_S : LSX2R_VV<0x729d7400>; 934def VFRINTRNE_D : LSX2R_VV<0x729d7800>; 935def VFRINTRZ_S : LSX2R_VV<0x729d6400>; 936def VFRINTRZ_D : LSX2R_VV<0x729d6800>; 937def VFRINTRP_S : LSX2R_VV<0x729d5400>; 938def VFRINTRP_D : LSX2R_VV<0x729d5800>; 939def VFRINTRM_S : LSX2R_VV<0x729d4400>; 940def VFRINTRM_D : LSX2R_VV<0x729d4800>; 941def VFRINT_S : LSX2R_VV<0x729d3400>; 942def VFRINT_D : LSX2R_VV<0x729d3800>; 943 944def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>; 945def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>; 946def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>; 947def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>; 948def VFTINTRP_W_S : LSX2R_VV<0x729e4000>; 949def VFTINTRP_L_D : LSX2R_VV<0x729e4400>; 950def VFTINTRM_W_S : LSX2R_VV<0x729e3800>; 951def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>; 952def VFTINT_W_S : LSX2R_VV<0x729e3000>; 953def VFTINT_L_D : LSX2R_VV<0x729e3400>; 954def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>; 955def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>; 956def VFTINT_WU_S : LSX2R_VV<0x729e5800>; 957def VFTINT_LU_D : LSX2R_VV<0x729e5c00>; 958 959def VFTINTRNE_W_D : LSX3R_VVV<0x714b8000>; 960def VFTINTRZ_W_D : LSX3R_VVV<0x714b0000>; 961def VFTINTRP_W_D : LSX3R_VVV<0x714a8000>; 962def VFTINTRM_W_D : LSX3R_VVV<0x714a0000>; 963def VFTINT_W_D : LSX3R_VVV<0x71498000>; 964 965def VFTINTRNEL_L_S : LSX2R_VV<0x729ea000>; 966def VFTINTRNEH_L_S : LSX2R_VV<0x729ea400>; 967def VFTINTRZL_L_S : LSX2R_VV<0x729e9800>; 968def VFTINTRZH_L_S : LSX2R_VV<0x729e9c00>; 969def VFTINTRPL_L_S : LSX2R_VV<0x729e9000>; 970def VFTINTRPH_L_S : LSX2R_VV<0x729e9400>; 971def VFTINTRML_L_S : LSX2R_VV<0x729e8800>; 972def VFTINTRMH_L_S : LSX2R_VV<0x729e8c00>; 973def VFTINTL_L_S : LSX2R_VV<0x729e8000>; 974def VFTINTH_L_S : LSX2R_VV<0x729e8400>; 975 976def VFFINT_S_W : LSX2R_VV<0x729e0000>; 977def VFFINT_D_L : LSX2R_VV<0x729e0800>; 978def VFFINT_S_WU : LSX2R_VV<0x729e0400>; 979def VFFINT_D_LU : LSX2R_VV<0x729e0c00>; 980def VFFINTL_D_W : LSX2R_VV<0x729e1000>; 981def VFFINTH_D_W : LSX2R_VV<0x729e1400>; 982def VFFINT_S_L : LSX3R_VVV<0x71480000>; 983 984def VSEQ_B : LSX3R_VVV<0x70000000>; 985def VSEQ_H : LSX3R_VVV<0x70008000>; 986def VSEQ_W : LSX3R_VVV<0x70010000>; 987def VSEQ_D : LSX3R_VVV<0x70018000>; 988def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>; 989def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>; 990def VSEQI_W : LSX2RI5_VVI<0x72810000, simm5>; 991def VSEQI_D : LSX2RI5_VVI<0x72818000, simm5>; 992 993def VSLE_B : LSX3R_VVV<0x70020000>; 994def VSLE_H : LSX3R_VVV<0x70028000>; 995def VSLE_W : LSX3R_VVV<0x70030000>; 996def VSLE_D : LSX3R_VVV<0x70038000>; 997def VSLEI_B : LSX2RI5_VVI<0x72820000, simm5>; 998def VSLEI_H : LSX2RI5_VVI<0x72828000, simm5>; 999def VSLEI_W : LSX2RI5_VVI<0x72830000, simm5>; 1000def VSLEI_D : LSX2RI5_VVI<0x72838000, simm5>; 1001 1002def VSLE_BU : LSX3R_VVV<0x70040000>; 1003def VSLE_HU : LSX3R_VVV<0x70048000>; 1004def VSLE_WU : LSX3R_VVV<0x70050000>; 1005def VSLE_DU : LSX3R_VVV<0x70058000>; 1006def VSLEI_BU : LSX2RI5_VVI<0x72840000>; 1007def VSLEI_HU : LSX2RI5_VVI<0x72848000>; 1008def VSLEI_WU : LSX2RI5_VVI<0x72850000>; 1009def VSLEI_DU : LSX2RI5_VVI<0x72858000>; 1010 1011def VSLT_B : LSX3R_VVV<0x70060000>; 1012def VSLT_H : LSX3R_VVV<0x70068000>; 1013def VSLT_W : LSX3R_VVV<0x70070000>; 1014def VSLT_D : LSX3R_VVV<0x70078000>; 1015def VSLTI_B : LSX2RI5_VVI<0x72860000, simm5>; 1016def VSLTI_H : LSX2RI5_VVI<0x72868000, simm5>; 1017def VSLTI_W : LSX2RI5_VVI<0x72870000, simm5>; 1018def VSLTI_D : LSX2RI5_VVI<0x72878000, simm5>; 1019 1020def VSLT_BU : LSX3R_VVV<0x70080000>; 1021def VSLT_HU : LSX3R_VVV<0x70088000>; 1022def VSLT_WU : LSX3R_VVV<0x70090000>; 1023def VSLT_DU : LSX3R_VVV<0x70098000>; 1024def VSLTI_BU : LSX2RI5_VVI<0x72880000>; 1025def VSLTI_HU : LSX2RI5_VVI<0x72888000>; 1026def VSLTI_WU : LSX2RI5_VVI<0x72890000>; 1027def VSLTI_DU : LSX2RI5_VVI<0x72898000>; 1028 1029def VFCMP_CAF_S : LSX3R_VVV<0x0c500000>; 1030def VFCMP_SAF_S : LSX3R_VVV<0x0c508000>; 1031def VFCMP_CLT_S : LSX3R_VVV<0x0c510000>; 1032def VFCMP_SLT_S : LSX3R_VVV<0x0c518000>; 1033def VFCMP_CEQ_S : LSX3R_VVV<0x0c520000>; 1034def VFCMP_SEQ_S : LSX3R_VVV<0x0c528000>; 1035def VFCMP_CLE_S : LSX3R_VVV<0x0c530000>; 1036def VFCMP_SLE_S : LSX3R_VVV<0x0c538000>; 1037def VFCMP_CUN_S : LSX3R_VVV<0x0c540000>; 1038def VFCMP_SUN_S : LSX3R_VVV<0x0c548000>; 1039def VFCMP_CULT_S : LSX3R_VVV<0x0c550000>; 1040def VFCMP_SULT_S : LSX3R_VVV<0x0c558000>; 1041def VFCMP_CUEQ_S : LSX3R_VVV<0x0c560000>; 1042def VFCMP_SUEQ_S : LSX3R_VVV<0x0c568000>; 1043def VFCMP_CULE_S : LSX3R_VVV<0x0c570000>; 1044def VFCMP_SULE_S : LSX3R_VVV<0x0c578000>; 1045def VFCMP_CNE_S : LSX3R_VVV<0x0c580000>; 1046def VFCMP_SNE_S : LSX3R_VVV<0x0c588000>; 1047def VFCMP_COR_S : LSX3R_VVV<0x0c5a0000>; 1048def VFCMP_SOR_S : LSX3R_VVV<0x0c5a8000>; 1049def VFCMP_CUNE_S : LSX3R_VVV<0x0c5c0000>; 1050def VFCMP_SUNE_S : LSX3R_VVV<0x0c5c8000>; 1051 1052def VFCMP_CAF_D : LSX3R_VVV<0x0c600000>; 1053def VFCMP_SAF_D : LSX3R_VVV<0x0c608000>; 1054def VFCMP_CLT_D : LSX3R_VVV<0x0c610000>; 1055def VFCMP_SLT_D : LSX3R_VVV<0x0c618000>; 1056def VFCMP_CEQ_D : LSX3R_VVV<0x0c620000>; 1057def VFCMP_SEQ_D : LSX3R_VVV<0x0c628000>; 1058def VFCMP_CLE_D : LSX3R_VVV<0x0c630000>; 1059def VFCMP_SLE_D : LSX3R_VVV<0x0c638000>; 1060def VFCMP_CUN_D : LSX3R_VVV<0x0c640000>; 1061def VFCMP_SUN_D : LSX3R_VVV<0x0c648000>; 1062def VFCMP_CULT_D : LSX3R_VVV<0x0c650000>; 1063def VFCMP_SULT_D : LSX3R_VVV<0x0c658000>; 1064def VFCMP_CUEQ_D : LSX3R_VVV<0x0c660000>; 1065def VFCMP_SUEQ_D : LSX3R_VVV<0x0c668000>; 1066def VFCMP_CULE_D : LSX3R_VVV<0x0c670000>; 1067def VFCMP_SULE_D : LSX3R_VVV<0x0c678000>; 1068def VFCMP_CNE_D : LSX3R_VVV<0x0c680000>; 1069def VFCMP_SNE_D : LSX3R_VVV<0x0c688000>; 1070def VFCMP_COR_D : LSX3R_VVV<0x0c6a0000>; 1071def VFCMP_SOR_D : LSX3R_VVV<0x0c6a8000>; 1072def VFCMP_CUNE_D : LSX3R_VVV<0x0c6c0000>; 1073def VFCMP_SUNE_D : LSX3R_VVV<0x0c6c8000>; 1074 1075def VBITSEL_V : LSX4R_VVVV<0x0d100000>; 1076 1077def VBITSELI_B : LSX2RI8_VVVI<0x73c40000>; 1078 1079def VSETEQZ_V : LSX2R_CV<0x729c9800>; 1080def VSETNEZ_V : LSX2R_CV<0x729c9c00>; 1081def VSETANYEQZ_B : LSX2R_CV<0x729ca000>; 1082def VSETANYEQZ_H : LSX2R_CV<0x729ca400>; 1083def VSETANYEQZ_W : LSX2R_CV<0x729ca800>; 1084def VSETANYEQZ_D : LSX2R_CV<0x729cac00>; 1085def VSETALLNEZ_B : LSX2R_CV<0x729cb000>; 1086def VSETALLNEZ_H : LSX2R_CV<0x729cb400>; 1087def VSETALLNEZ_W : LSX2R_CV<0x729cb800>; 1088def VSETALLNEZ_D : LSX2R_CV<0x729cbc00>; 1089 1090def VINSGR2VR_B : LSX2RI4_VVRI<0x72eb8000>; 1091def VINSGR2VR_H : LSX2RI3_VVRI<0x72ebc000>; 1092def VINSGR2VR_W : LSX2RI2_VVRI<0x72ebe000>; 1093def VINSGR2VR_D : LSX2RI1_VVRI<0x72ebf000>; 1094def VPICKVE2GR_B : LSX2RI4_RVI<0x72ef8000>; 1095def VPICKVE2GR_H : LSX2RI3_RVI<0x72efc000>; 1096def VPICKVE2GR_W : LSX2RI2_RVI<0x72efe000>; 1097def VPICKVE2GR_D : LSX2RI1_RVI<0x72eff000>; 1098def VPICKVE2GR_BU : LSX2RI4_RVI<0x72f38000>; 1099def VPICKVE2GR_HU : LSX2RI3_RVI<0x72f3c000>; 1100def VPICKVE2GR_WU : LSX2RI2_RVI<0x72f3e000>; 1101def VPICKVE2GR_DU : LSX2RI1_RVI<0x72f3f000>; 1102 1103def VREPLGR2VR_B : LSX2R_VR<0x729f0000>; 1104def VREPLGR2VR_H : LSX2R_VR<0x729f0400>; 1105def VREPLGR2VR_W : LSX2R_VR<0x729f0800>; 1106def VREPLGR2VR_D : LSX2R_VR<0x729f0c00>; 1107 1108def VREPLVE_B : LSX3R_VVR<0x71220000>; 1109def VREPLVE_H : LSX3R_VVR<0x71228000>; 1110def VREPLVE_W : LSX3R_VVR<0x71230000>; 1111def VREPLVE_D : LSX3R_VVR<0x71238000>; 1112def VREPLVEI_B : LSX2RI4_VVI<0x72f78000>; 1113def VREPLVEI_H : LSX2RI3_VVI<0x72f7c000>; 1114def VREPLVEI_W : LSX2RI2_VVI<0x72f7e000>; 1115def VREPLVEI_D : LSX2RI1_VVI<0x72f7f000>; 1116 1117def VBSLL_V : LSX2RI5_VVI<0x728e0000>; 1118def VBSRL_V : LSX2RI5_VVI<0x728e8000>; 1119 1120def VPACKEV_B : LSX3R_VVV<0x71160000>; 1121def VPACKEV_H : LSX3R_VVV<0x71168000>; 1122def VPACKEV_W : LSX3R_VVV<0x71170000>; 1123def VPACKEV_D : LSX3R_VVV<0x71178000>; 1124def VPACKOD_B : LSX3R_VVV<0x71180000>; 1125def VPACKOD_H : LSX3R_VVV<0x71188000>; 1126def VPACKOD_W : LSX3R_VVV<0x71190000>; 1127def VPACKOD_D : LSX3R_VVV<0x71198000>; 1128 1129def VPICKEV_B : LSX3R_VVV<0x711e0000>; 1130def VPICKEV_H : LSX3R_VVV<0x711e8000>; 1131def VPICKEV_W : LSX3R_VVV<0x711f0000>; 1132def VPICKEV_D : LSX3R_VVV<0x711f8000>; 1133def VPICKOD_B : LSX3R_VVV<0x71200000>; 1134def VPICKOD_H : LSX3R_VVV<0x71208000>; 1135def VPICKOD_W : LSX3R_VVV<0x71210000>; 1136def VPICKOD_D : LSX3R_VVV<0x71218000>; 1137 1138def VILVL_B : LSX3R_VVV<0x711a0000>; 1139def VILVL_H : LSX3R_VVV<0x711a8000>; 1140def VILVL_W : LSX3R_VVV<0x711b0000>; 1141def VILVL_D : LSX3R_VVV<0x711b8000>; 1142def VILVH_B : LSX3R_VVV<0x711c0000>; 1143def VILVH_H : LSX3R_VVV<0x711c8000>; 1144def VILVH_W : LSX3R_VVV<0x711d0000>; 1145def VILVH_D : LSX3R_VVV<0x711d8000>; 1146 1147def VSHUF_B : LSX4R_VVVV<0x0d500000>; 1148 1149def VSHUF_H : LSX3R_VVVV<0x717a8000>; 1150def VSHUF_W : LSX3R_VVVV<0x717b0000>; 1151def VSHUF_D : LSX3R_VVVV<0x717b8000>; 1152 1153def VSHUF4I_B : LSX2RI8_VVI<0x73900000>; 1154def VSHUF4I_H : LSX2RI8_VVI<0x73940000>; 1155def VSHUF4I_W : LSX2RI8_VVI<0x73980000>; 1156def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>; 1157 1158def VPERMI_W : LSX2RI8_VVVI<0x73e40000>; 1159 1160def VEXTRINS_D : LSX2RI8_VVVI<0x73800000>; 1161def VEXTRINS_W : LSX2RI8_VVVI<0x73840000>; 1162def VEXTRINS_H : LSX2RI8_VVVI<0x73880000>; 1163def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>; 1164} // mayLoad = 0, mayStore = 0 1165 1166let mayLoad = 1, mayStore = 0 in { 1167def VLD : LSX2RI12_Load<0x2c000000>; 1168def VLDX : LSX3R_Load<0x38400000>; 1169 1170def VLDREPL_B : LSX2RI12_Load<0x30800000>; 1171def VLDREPL_H : LSX2RI11_Load<0x30400000>; 1172def VLDREPL_W : LSX2RI10_Load<0x30200000>; 1173def VLDREPL_D : LSX2RI9_Load<0x30100000>; 1174} // mayLoad = 1, mayStore = 0 1175 1176let mayLoad = 0, mayStore = 1 in { 1177def VST : LSX2RI12_Store<0x2c400000>; 1178def VSTX : LSX3R_Store<0x38440000>; 1179 1180def VSTELM_B : LSX2RI8I4_VRII<0x31800000>; 1181def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>; 1182def VSTELM_W : LSX2RI8I2_VRII<0x31200000, simm8_lsl2>; 1183def VSTELM_D : LSX2RI8I1_VRII<0x31100000, simm8_lsl3>; 1184} // mayLoad = 0, mayStore = 1 1185 1186} // hasSideEffects = 0, Predicates = [HasExtLSX] 1187 1188/// Pseudo-instructions 1189 1190let Predicates = [HasExtLSX] in { 1191 1192let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, 1193 isAsmParserOnly = 1 in { 1194def PseudoVREPLI_B : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1195 "vrepli.b", "$vd, $imm">; 1196def PseudoVREPLI_H : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1197 "vrepli.h", "$vd, $imm">; 1198def PseudoVREPLI_W : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1199 "vrepli.w", "$vd, $imm">; 1200def PseudoVREPLI_D : Pseudo<(outs LSX128:$vd), (ins simm10:$imm), [], 1201 "vrepli.d", "$vd, $imm">; 1202} 1203 1204def PseudoVBNZ_B : VecCond<loongarch_vall_nonzero, v16i8>; 1205def PseudoVBNZ_H : VecCond<loongarch_vall_nonzero, v8i16>; 1206def PseudoVBNZ_W : VecCond<loongarch_vall_nonzero, v4i32>; 1207def PseudoVBNZ_D : VecCond<loongarch_vall_nonzero, v2i64>; 1208def PseudoVBNZ : VecCond<loongarch_vany_nonzero, v16i8>; 1209 1210def PseudoVBZ_B : VecCond<loongarch_vall_zero, v16i8>; 1211def PseudoVBZ_H : VecCond<loongarch_vall_zero, v8i16>; 1212def PseudoVBZ_W : VecCond<loongarch_vall_zero, v4i32>; 1213def PseudoVBZ_D : VecCond<loongarch_vall_zero, v2i64>; 1214def PseudoVBZ : VecCond<loongarch_vany_zero, v16i8>; 1215 1216} // Predicates = [HasExtLSX] 1217 1218multiclass PatVr<SDPatternOperator OpNode, string Inst> { 1219 def : Pat<(v16i8 (OpNode (v16i8 LSX128:$vj))), 1220 (!cast<LAInst>(Inst#"_B") LSX128:$vj)>; 1221 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))), 1222 (!cast<LAInst>(Inst#"_H") LSX128:$vj)>; 1223 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))), 1224 (!cast<LAInst>(Inst#"_W") LSX128:$vj)>; 1225 def : Pat<(v2i64 (OpNode (v2i64 LSX128:$vj))), 1226 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1227} 1228 1229multiclass PatVrF<SDPatternOperator OpNode, string Inst> { 1230 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))), 1231 (!cast<LAInst>(Inst#"_S") LSX128:$vj)>; 1232 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))), 1233 (!cast<LAInst>(Inst#"_D") LSX128:$vj)>; 1234} 1235 1236multiclass PatVrVr<SDPatternOperator OpNode, string Inst> { 1237 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1238 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1239 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1240 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1241 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1242 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1243 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1244 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1245} 1246 1247multiclass PatVrVrF<SDPatternOperator OpNode, string Inst> { 1248 def : Pat<(OpNode (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 1249 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1250 def : Pat<(OpNode (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 1251 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1252} 1253 1254multiclass PatVrVrU<SDPatternOperator OpNode, string Inst> { 1255 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1256 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1257 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1258 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1259 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1260 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1261 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1262 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1263} 1264 1265multiclass PatVrSimm5<SDPatternOperator OpNode, string Inst> { 1266 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_simm5 simm5:$imm))), 1267 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1268 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_simm5 simm5:$imm))), 1269 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1270 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_simm5 simm5:$imm))), 1271 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1272 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_simm5 simm5:$imm))), 1273 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1274} 1275 1276multiclass PatVrUimm5<SDPatternOperator OpNode, string Inst> { 1277 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm5 uimm5:$imm))), 1278 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1279 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm5 uimm5:$imm))), 1280 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1281 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1282 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1283 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm5 uimm5:$imm))), 1284 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1285} 1286 1287multiclass PatVrVrVr<SDPatternOperator OpNode, string Inst> { 1288 def : Pat<(OpNode (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1289 (!cast<LAInst>(Inst#"_B") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1290 def : Pat<(OpNode (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1291 (!cast<LAInst>(Inst#"_H") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1292 def : Pat<(OpNode (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1293 (!cast<LAInst>(Inst#"_W") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1294 def : Pat<(OpNode (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1295 (!cast<LAInst>(Inst#"_D") LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 1296} 1297 1298multiclass PatShiftVrVr<SDPatternOperator OpNode, string Inst> { 1299 def : Pat<(OpNode (v16i8 LSX128:$vj), (and vsplati8_imm_eq_7, 1300 (v16i8 LSX128:$vk))), 1301 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1302 def : Pat<(OpNode (v8i16 LSX128:$vj), (and vsplati16_imm_eq_15, 1303 (v8i16 LSX128:$vk))), 1304 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1305 def : Pat<(OpNode (v4i32 LSX128:$vj), (and vsplati32_imm_eq_31, 1306 (v4i32 LSX128:$vk))), 1307 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1308 def : Pat<(OpNode (v2i64 LSX128:$vj), (and vsplati64_imm_eq_63, 1309 (v2i64 LSX128:$vk))), 1310 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1311} 1312 1313multiclass PatShiftVrUimm<SDPatternOperator OpNode, string Inst> { 1314 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm3 uimm3:$imm))), 1315 (!cast<LAInst>(Inst#"_B") LSX128:$vj, uimm3:$imm)>; 1316 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm4 uimm4:$imm))), 1317 (!cast<LAInst>(Inst#"_H") LSX128:$vj, uimm4:$imm)>; 1318 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 (SplatPat_uimm5 uimm5:$imm))), 1319 (!cast<LAInst>(Inst#"_W") LSX128:$vj, uimm5:$imm)>; 1320 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 (SplatPat_uimm6 uimm6:$imm))), 1321 (!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>; 1322} 1323 1324multiclass PatCCVrSimm5<CondCode CC, string Inst> { 1325 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1326 (v16i8 (SplatPat_simm5 simm5:$imm)), CC)), 1327 (!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>; 1328 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1329 (v8i16 (SplatPat_simm5 simm5:$imm)), CC)), 1330 (!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>; 1331 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1332 (v4i32 (SplatPat_simm5 simm5:$imm)), CC)), 1333 (!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>; 1334 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1335 (v2i64 (SplatPat_simm5 simm5:$imm)), CC)), 1336 (!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>; 1337} 1338 1339multiclass PatCCVrUimm5<CondCode CC, string Inst> { 1340 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), 1341 (v16i8 (SplatPat_uimm5 uimm5:$imm)), CC)), 1342 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>; 1343 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), 1344 (v8i16 (SplatPat_uimm5 uimm5:$imm)), CC)), 1345 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>; 1346 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), 1347 (v4i32 (SplatPat_uimm5 uimm5:$imm)), CC)), 1348 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>; 1349 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), 1350 (v2i64 (SplatPat_uimm5 uimm5:$imm)), CC)), 1351 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>; 1352} 1353 1354multiclass PatCCVrVr<CondCode CC, string Inst> { 1355 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1356 (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>; 1357 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1358 (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>; 1359 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1360 (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>; 1361 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1362 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1363} 1364 1365multiclass PatCCVrVrU<CondCode CC, string Inst> { 1366 def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)), 1367 (!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>; 1368 def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)), 1369 (!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>; 1370 def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)), 1371 (!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>; 1372 def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)), 1373 (!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>; 1374} 1375 1376multiclass PatCCVrVrF<CondCode CC, string Inst> { 1377 def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)), 1378 (!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>; 1379 def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)), 1380 (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>; 1381} 1382 1383let Predicates = [HasExtLSX] in { 1384 1385// VADD_{B/H/W/D} 1386defm : PatVrVr<add, "VADD">; 1387// VSUB_{B/H/W/D} 1388defm : PatVrVr<sub, "VSUB">; 1389 1390// VADDI_{B/H/W/D}U 1391defm : PatVrUimm5<add, "VADDI">; 1392// VSUBI_{B/H/W/D}U 1393defm : PatVrUimm5<sub, "VSUBI">; 1394 1395// VNEG_{B/H/W/D} 1396def : Pat<(sub immAllZerosV, (v16i8 LSX128:$vj)), (VNEG_B LSX128:$vj)>; 1397def : Pat<(sub immAllZerosV, (v8i16 LSX128:$vj)), (VNEG_H LSX128:$vj)>; 1398def : Pat<(sub immAllZerosV, (v4i32 LSX128:$vj)), (VNEG_W LSX128:$vj)>; 1399def : Pat<(sub immAllZerosV, (v2i64 LSX128:$vj)), (VNEG_D LSX128:$vj)>; 1400 1401// VMAX[I]_{B/H/W/D}[U] 1402defm : PatVrVr<smax, "VMAX">; 1403defm : PatVrVrU<umax, "VMAX">; 1404defm : PatVrSimm5<smax, "VMAXI">; 1405defm : PatVrUimm5<umax, "VMAXI">; 1406 1407// VMIN[I]_{B/H/W/D}[U] 1408defm : PatVrVr<smin, "VMIN">; 1409defm : PatVrVrU<umin, "VMIN">; 1410defm : PatVrSimm5<smin, "VMINI">; 1411defm : PatVrUimm5<umin, "VMINI">; 1412 1413// VMUL_{B/H/W/D} 1414defm : PatVrVr<mul, "VMUL">; 1415 1416// VMUH_{B/H/W/D}[U] 1417defm : PatVrVr<mulhs, "VMUH">; 1418defm : PatVrVrU<mulhu, "VMUH">; 1419 1420// VMADD_{B/H/W/D} 1421defm : PatVrVrVr<muladd, "VMADD">; 1422// VMSUB_{B/H/W/D} 1423defm : PatVrVrVr<mulsub, "VMSUB">; 1424 1425// VDIV_{B/H/W/D}[U] 1426defm : PatVrVr<sdiv, "VDIV">; 1427defm : PatVrVrU<udiv, "VDIV">; 1428 1429// VMOD_{B/H/W/D}[U] 1430defm : PatVrVr<srem, "VMOD">; 1431defm : PatVrVrU<urem, "VMOD">; 1432 1433// VAND_V 1434foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1435def : Pat<(and (vt LSX128:$vj), (vt LSX128:$vk)), 1436 (VAND_V LSX128:$vj, LSX128:$vk)>; 1437// VOR_V 1438foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1439def : Pat<(or (vt LSX128:$vj), (vt LSX128:$vk)), 1440 (VOR_V LSX128:$vj, LSX128:$vk)>; 1441// VXOR_V 1442foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1443def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)), 1444 (VXOR_V LSX128:$vj, LSX128:$vk)>; 1445// VNOR_V 1446foreach vt = [v16i8, v8i16, v4i32, v2i64] in 1447def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))), 1448 (VNOR_V LSX128:$vj, LSX128:$vk)>; 1449 1450// VANDI_B 1451def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1452 (VANDI_B LSX128:$vj, uimm8:$imm)>; 1453// VORI_B 1454def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1455 (VORI_B LSX128:$vj, uimm8:$imm)>; 1456 1457// VXORI_B 1458def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), 1459 (VXORI_B LSX128:$vj, uimm8:$imm)>; 1460 1461// VSLL[I]_{B/H/W/D} 1462defm : PatVrVr<shl, "VSLL">; 1463defm : PatShiftVrVr<shl, "VSLL">; 1464defm : PatShiftVrUimm<shl, "VSLLI">; 1465 1466// VSRL[I]_{B/H/W/D} 1467defm : PatVrVr<srl, "VSRL">; 1468defm : PatShiftVrVr<srl, "VSRL">; 1469defm : PatShiftVrUimm<srl, "VSRLI">; 1470 1471// VSRA[I]_{B/H/W/D} 1472defm : PatVrVr<sra, "VSRA">; 1473defm : PatShiftVrVr<sra, "VSRA">; 1474defm : PatShiftVrUimm<sra, "VSRAI">; 1475 1476// VCLZ_{B/H/W/D} 1477defm : PatVr<ctlz, "VCLZ">; 1478 1479// VPCNT_{B/H/W/D} 1480defm : PatVr<ctpop, "VPCNT">; 1481 1482// VBITCLR_{B/H/W/D} 1483def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, v16i8:$vk))), 1484 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1485def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, v8i16:$vk))), 1486 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1487def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, v4i32:$vk))), 1488 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1489def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, v2i64:$vk))), 1490 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1491def : Pat<(and v16i8:$vj, (vnot (shl vsplat_imm_eq_1, 1492 (vsplati8imm7 v16i8:$vk)))), 1493 (v16i8 (VBITCLR_B v16i8:$vj, v16i8:$vk))>; 1494def : Pat<(and v8i16:$vj, (vnot (shl vsplat_imm_eq_1, 1495 (vsplati16imm15 v8i16:$vk)))), 1496 (v8i16 (VBITCLR_H v8i16:$vj, v8i16:$vk))>; 1497def : Pat<(and v4i32:$vj, (vnot (shl vsplat_imm_eq_1, 1498 (vsplati32imm31 v4i32:$vk)))), 1499 (v4i32 (VBITCLR_W v4i32:$vj, v4i32:$vk))>; 1500def : Pat<(and v2i64:$vj, (vnot (shl vsplat_imm_eq_1, 1501 (vsplati64imm63 v2i64:$vk)))), 1502 (v2i64 (VBITCLR_D v2i64:$vj, v2i64:$vk))>; 1503 1504// VBITCLRI_{B/H/W/D} 1505def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_inv_pow2 uimm3:$imm))), 1506 (VBITCLRI_B LSX128:$vj, uimm3:$imm)>; 1507def : Pat<(and (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_inv_pow2 uimm4:$imm))), 1508 (VBITCLRI_H LSX128:$vj, uimm4:$imm)>; 1509def : Pat<(and (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_inv_pow2 uimm5:$imm))), 1510 (VBITCLRI_W LSX128:$vj, uimm5:$imm)>; 1511def : Pat<(and (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_inv_pow2 uimm6:$imm))), 1512 (VBITCLRI_D LSX128:$vj, uimm6:$imm)>; 1513 1514// VBITSET_{B/H/W/D} 1515def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1516 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1517def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1518 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1519def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1520 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1521def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1522 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1523def : Pat<(or v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1524 (v16i8 (VBITSET_B v16i8:$vj, v16i8:$vk))>; 1525def : Pat<(or v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1526 (v8i16 (VBITSET_H v8i16:$vj, v8i16:$vk))>; 1527def : Pat<(or v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1528 (v4i32 (VBITSET_W v4i32:$vj, v4i32:$vk))>; 1529def : Pat<(or v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1530 (v2i64 (VBITSET_D v2i64:$vj, v2i64:$vk))>; 1531 1532// VBITSETI_{B/H/W/D} 1533def : Pat<(or (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1534 (VBITSETI_B LSX128:$vj, uimm3:$imm)>; 1535def : Pat<(or (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1536 (VBITSETI_H LSX128:$vj, uimm4:$imm)>; 1537def : Pat<(or (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1538 (VBITSETI_W LSX128:$vj, uimm5:$imm)>; 1539def : Pat<(or (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1540 (VBITSETI_D LSX128:$vj, uimm6:$imm)>; 1541 1542// VBITREV_{B/H/W/D} 1543def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, v16i8:$vk)), 1544 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1545def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, v8i16:$vk)), 1546 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1547def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, v4i32:$vk)), 1548 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1549def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, v2i64:$vk)), 1550 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1551def : Pat<(xor v16i8:$vj, (shl vsplat_imm_eq_1, (vsplati8imm7 v16i8:$vk))), 1552 (v16i8 (VBITREV_B v16i8:$vj, v16i8:$vk))>; 1553def : Pat<(xor v8i16:$vj, (shl vsplat_imm_eq_1, (vsplati16imm15 v8i16:$vk))), 1554 (v8i16 (VBITREV_H v8i16:$vj, v8i16:$vk))>; 1555def : Pat<(xor v4i32:$vj, (shl vsplat_imm_eq_1, (vsplati32imm31 v4i32:$vk))), 1556 (v4i32 (VBITREV_W v4i32:$vj, v4i32:$vk))>; 1557def : Pat<(xor v2i64:$vj, (shl vsplat_imm_eq_1, (vsplati64imm63 v2i64:$vk))), 1558 (v2i64 (VBITREV_D v2i64:$vj, v2i64:$vk))>; 1559 1560// VBITREVI_{B/H/W/D} 1561def : Pat<(xor (v16i8 LSX128:$vj), (v16i8 (vsplat_uimm_pow2 uimm3:$imm))), 1562 (VBITREVI_B LSX128:$vj, uimm3:$imm)>; 1563def : Pat<(xor (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))), 1564 (VBITREVI_H LSX128:$vj, uimm4:$imm)>; 1565def : Pat<(xor (v4i32 LSX128:$vj), (v4i32 (vsplat_uimm_pow2 uimm5:$imm))), 1566 (VBITREVI_W LSX128:$vj, uimm5:$imm)>; 1567def : Pat<(xor (v2i64 LSX128:$vj), (v2i64 (vsplat_uimm_pow2 uimm6:$imm))), 1568 (VBITREVI_D LSX128:$vj, uimm6:$imm)>; 1569 1570// VFADD_{S/D} 1571defm : PatVrVrF<fadd, "VFADD">; 1572 1573// VFSUB_{S/D} 1574defm : PatVrVrF<fsub, "VFSUB">; 1575 1576// VFMUL_{S/D} 1577defm : PatVrVrF<fmul, "VFMUL">; 1578 1579// VFDIV_{S/D} 1580defm : PatVrVrF<fdiv, "VFDIV">; 1581 1582// VFMADD_{S/D} 1583def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va), 1584 (VFMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1585def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va), 1586 (VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1587 1588// VFMSUB_{S/D} 1589def : Pat<(fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va)), 1590 (VFMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1591def : Pat<(fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va)), 1592 (VFMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1593 1594// VFNMADD_{S/D} 1595def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, v4f32:$va)), 1596 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1597def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, v2f64:$va)), 1598 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1599def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, (fneg v4f32:$va)), 1600 (VFNMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1601def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, (fneg v2f64:$va)), 1602 (VFNMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1603 1604// VFNMSUB_{S/D} 1605def : Pat<(fneg (fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va))), 1606 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1607def : Pat<(fneg (fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va))), 1608 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1609def : Pat<(fma_nsz (fneg v4f32:$vj), v4f32:$vk, v4f32:$va), 1610 (VFNMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>; 1611def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, v2f64:$va), 1612 (VFNMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>; 1613 1614// VFSQRT_{S/D} 1615defm : PatVrF<fsqrt, "VFSQRT">; 1616 1617// VFRECIP_{S/D} 1618def : Pat<(fdiv vsplatf32_fpimm_eq_1, v4f32:$vj), 1619 (VFRECIP_S v4f32:$vj)>; 1620def : Pat<(fdiv vsplatf64_fpimm_eq_1, v2f64:$vj), 1621 (VFRECIP_D v2f64:$vj)>; 1622 1623// VFRSQRT_{S/D} 1624def : Pat<(fdiv vsplatf32_fpimm_eq_1, (fsqrt v4f32:$vj)), 1625 (VFRSQRT_S v4f32:$vj)>; 1626def : Pat<(fdiv vsplatf64_fpimm_eq_1, (fsqrt v2f64:$vj)), 1627 (VFRSQRT_D v2f64:$vj)>; 1628 1629// VSEQ[I]_{B/H/W/D} 1630defm : PatCCVrSimm5<SETEQ, "VSEQI">; 1631defm : PatCCVrVr<SETEQ, "VSEQ">; 1632 1633// VSLE[I]_{B/H/W/D}[U] 1634defm : PatCCVrSimm5<SETLE, "VSLEI">; 1635defm : PatCCVrUimm5<SETULE, "VSLEI">; 1636defm : PatCCVrVr<SETLE, "VSLE">; 1637defm : PatCCVrVrU<SETULE, "VSLE">; 1638 1639// VSLT[I]_{B/H/W/D}[U] 1640defm : PatCCVrSimm5<SETLT, "VSLTI">; 1641defm : PatCCVrUimm5<SETULT, "VSLTI">; 1642defm : PatCCVrVr<SETLT, "VSLT">; 1643defm : PatCCVrVrU<SETULT, "VSLT">; 1644 1645// VFCMP.cond.{S/D} 1646defm : PatCCVrVrF<SETEQ, "VFCMP_CEQ">; 1647defm : PatCCVrVrF<SETOEQ, "VFCMP_CEQ">; 1648defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">; 1649 1650defm : PatCCVrVrF<SETLE, "VFCMP_CLE">; 1651defm : PatCCVrVrF<SETOLE, "VFCMP_CLE">; 1652defm : PatCCVrVrF<SETULE, "VFCMP_CULE">; 1653 1654defm : PatCCVrVrF<SETLT, "VFCMP_CLT">; 1655defm : PatCCVrVrF<SETOLT, "VFCMP_CLT">; 1656defm : PatCCVrVrF<SETULT, "VFCMP_CULT">; 1657 1658defm : PatCCVrVrF<SETNE, "VFCMP_CNE">; 1659defm : PatCCVrVrF<SETONE, "VFCMP_CNE">; 1660defm : PatCCVrVrF<SETUNE, "VFCMP_CUNE">; 1661 1662defm : PatCCVrVrF<SETO, "VFCMP_COR">; 1663defm : PatCCVrVrF<SETUO, "VFCMP_CUN">; 1664 1665// VINSGR2VR_{B/H/W/D} 1666def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm), 1667 (VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>; 1668def : Pat<(vector_insert v8i16:$vd, GRLenVT:$rj, uimm3:$imm), 1669 (VINSGR2VR_H v8i16:$vd, GRLenVT:$rj, uimm3:$imm)>; 1670def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm), 1671 (VINSGR2VR_W v4i32:$vd, GRLenVT:$rj, uimm2:$imm)>; 1672def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm), 1673 (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>; 1674 1675def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm), 1676 (VINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm2:$imm)>; 1677def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm), 1678 (VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>; 1679 1680// VPICKVE2GR_{B/H/W}[U] 1681def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8), 1682 (VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>; 1683def : Pat<(loongarch_vpick_sext_elt v8i16:$vd, uimm3:$imm, i16), 1684 (VPICKVE2GR_H v8i16:$vd, uimm3:$imm)>; 1685def : Pat<(loongarch_vpick_sext_elt v4i32:$vd, uimm2:$imm, i32), 1686 (VPICKVE2GR_W v4i32:$vd, uimm2:$imm)>; 1687 1688def : Pat<(loongarch_vpick_zext_elt v16i8:$vd, uimm4:$imm, i8), 1689 (VPICKVE2GR_BU v16i8:$vd, uimm4:$imm)>; 1690def : Pat<(loongarch_vpick_zext_elt v8i16:$vd, uimm3:$imm, i16), 1691 (VPICKVE2GR_HU v8i16:$vd, uimm3:$imm)>; 1692def : Pat<(loongarch_vpick_zext_elt v4i32:$vd, uimm2:$imm, i32), 1693 (VPICKVE2GR_WU v4i32:$vd, uimm2:$imm)>; 1694 1695// VREPLGR2VR_{B/H/W/D} 1696def : Pat<(lsxsplati8 GPR:$rj), (VREPLGR2VR_B GPR:$rj)>; 1697def : Pat<(lsxsplati16 GPR:$rj), (VREPLGR2VR_H GPR:$rj)>; 1698def : Pat<(lsxsplati32 GPR:$rj), (VREPLGR2VR_W GPR:$rj)>; 1699def : Pat<(lsxsplati64 GPR:$rj), (VREPLGR2VR_D GPR:$rj)>; 1700 1701// VREPLVE_{B/H/W/D} 1702def : Pat<(loongarch_vreplve v16i8:$vj, GRLenVT:$rk), 1703 (VREPLVE_B v16i8:$vj, GRLenVT:$rk)>; 1704def : Pat<(loongarch_vreplve v8i16:$vj, GRLenVT:$rk), 1705 (VREPLVE_H v8i16:$vj, GRLenVT:$rk)>; 1706def : Pat<(loongarch_vreplve v4i32:$vj, GRLenVT:$rk), 1707 (VREPLVE_W v4i32:$vj, GRLenVT:$rk)>; 1708def : Pat<(loongarch_vreplve v2i64:$vj, GRLenVT:$rk), 1709 (VREPLVE_D v2i64:$vj, GRLenVT:$rk)>; 1710 1711// VSHUF_{B/H/W/D} 1712def : Pat<(loongarch_vshuf v16i8:$va, v16i8:$vj, v16i8:$vk), 1713 (VSHUF_B v16i8:$vj, v16i8:$vk, v16i8:$va)>; 1714def : Pat<(loongarch_vshuf v8i16:$vd, v8i16:$vj, v8i16:$vk), 1715 (VSHUF_H v8i16:$vd, v8i16:$vj, v8i16:$vk)>; 1716def : Pat<(loongarch_vshuf v4i32:$vd, v4i32:$vj, v4i32:$vk), 1717 (VSHUF_W v4i32:$vd, v4i32:$vj, v4i32:$vk)>; 1718def : Pat<(loongarch_vshuf v2i64:$vd, v2i64:$vj, v2i64:$vk), 1719 (VSHUF_D v2i64:$vd, v2i64:$vj, v2i64:$vk)>; 1720def : Pat<(loongarch_vshuf v4i32:$vd, v4f32:$vj, v4f32:$vk), 1721 (VSHUF_W v4i32:$vd, v4f32:$vj, v4f32:$vk)>; 1722def : Pat<(loongarch_vshuf v2i64:$vd, v2f64:$vj, v2f64:$vk), 1723 (VSHUF_D v2i64:$vd, v2f64:$vj, v2f64:$vk)>; 1724 1725// VPICKEV_{B/H/W/D} 1726def : Pat<(loongarch_vpickev v16i8:$vj, v16i8:$vk), 1727 (VPICKEV_B v16i8:$vj, v16i8:$vk)>; 1728def : Pat<(loongarch_vpickev v8i16:$vj, v8i16:$vk), 1729 (VPICKEV_H v8i16:$vj, v8i16:$vk)>; 1730def : Pat<(loongarch_vpickev v4i32:$vj, v4i32:$vk), 1731 (VPICKEV_W v4i32:$vj, v4i32:$vk)>; 1732def : Pat<(loongarch_vpickev v2i64:$vj, v2i64:$vk), 1733 (VPICKEV_D v2i64:$vj, v2i64:$vk)>; 1734def : Pat<(loongarch_vpickev v4f32:$vj, v4f32:$vk), 1735 (VPICKEV_W v4f32:$vj, v4f32:$vk)>; 1736def : Pat<(loongarch_vpickev v2f64:$vj, v2f64:$vk), 1737 (VPICKEV_D v2f64:$vj, v2f64:$vk)>; 1738 1739// VPICKOD_{B/H/W/D} 1740def : Pat<(loongarch_vpickod v16i8:$vj, v16i8:$vk), 1741 (VPICKOD_B v16i8:$vj, v16i8:$vk)>; 1742def : Pat<(loongarch_vpickod v8i16:$vj, v8i16:$vk), 1743 (VPICKOD_H v8i16:$vj, v8i16:$vk)>; 1744def : Pat<(loongarch_vpickod v4i32:$vj, v4i32:$vk), 1745 (VPICKOD_W v4i32:$vj, v4i32:$vk)>; 1746def : Pat<(loongarch_vpickod v2i64:$vj, v2i64:$vk), 1747 (VPICKOD_D v2i64:$vj, v2i64:$vk)>; 1748def : Pat<(loongarch_vpickod v4f32:$vj, v4f32:$vk), 1749 (VPICKOD_W v4f32:$vj, v4f32:$vk)>; 1750def : Pat<(loongarch_vpickod v2f64:$vj, v2f64:$vk), 1751 (VPICKOD_D v2f64:$vj, v2f64:$vk)>; 1752 1753// VPACKEV_{B/H/W/D} 1754def : Pat<(loongarch_vpackev v16i8:$vj, v16i8:$vk), 1755 (VPACKEV_B v16i8:$vj, v16i8:$vk)>; 1756def : Pat<(loongarch_vpackev v8i16:$vj, v8i16:$vk), 1757 (VPACKEV_H v8i16:$vj, v8i16:$vk)>; 1758def : Pat<(loongarch_vpackev v4i32:$vj, v4i32:$vk), 1759 (VPACKEV_W v4i32:$vj, v4i32:$vk)>; 1760def : Pat<(loongarch_vpackev v2i64:$vj, v2i64:$vk), 1761 (VPACKEV_D v2i64:$vj, v2i64:$vk)>; 1762def : Pat<(loongarch_vpackev v4f32:$vj, v4f32:$vk), 1763 (VPACKEV_W v4f32:$vj, v4f32:$vk)>; 1764def : Pat<(loongarch_vpackev v2f64:$vj, v2f64:$vk), 1765 (VPACKEV_D v2f64:$vj, v2f64:$vk)>; 1766 1767// VPACKOD_{B/H/W/D} 1768def : Pat<(loongarch_vpackod v16i8:$vj, v16i8:$vk), 1769 (VPACKOD_B v16i8:$vj, v16i8:$vk)>; 1770def : Pat<(loongarch_vpackod v8i16:$vj, v8i16:$vk), 1771 (VPACKOD_H v8i16:$vj, v8i16:$vk)>; 1772def : Pat<(loongarch_vpackod v4i32:$vj, v4i32:$vk), 1773 (VPACKOD_W v4i32:$vj, v4i32:$vk)>; 1774def : Pat<(loongarch_vpackod v2i64:$vj, v2i64:$vk), 1775 (VPACKOD_D v2i64:$vj, v2i64:$vk)>; 1776def : Pat<(loongarch_vpackod v4f32:$vj, v4f32:$vk), 1777 (VPACKOD_W v4f32:$vj, v4f32:$vk)>; 1778def : Pat<(loongarch_vpackod v2f64:$vj, v2f64:$vk), 1779 (VPACKOD_D v2f64:$vj, v2f64:$vk)>; 1780 1781// VILVL_{B/H/W/D} 1782def : Pat<(loongarch_vilvl v16i8:$vj, v16i8:$vk), 1783 (VILVL_B v16i8:$vj, v16i8:$vk)>; 1784def : Pat<(loongarch_vilvl v8i16:$vj, v8i16:$vk), 1785 (VILVL_H v8i16:$vj, v8i16:$vk)>; 1786def : Pat<(loongarch_vilvl v4i32:$vj, v4i32:$vk), 1787 (VILVL_W v4i32:$vj, v4i32:$vk)>; 1788def : Pat<(loongarch_vilvl v2i64:$vj, v2i64:$vk), 1789 (VILVL_D v2i64:$vj, v2i64:$vk)>; 1790def : Pat<(loongarch_vilvl v4f32:$vj, v4f32:$vk), 1791 (VILVL_W v4f32:$vj, v4f32:$vk)>; 1792def : Pat<(loongarch_vilvl v2f64:$vj, v2f64:$vk), 1793 (VILVL_D v2f64:$vj, v2f64:$vk)>; 1794 1795// VILVH_{B/H/W/D} 1796def : Pat<(loongarch_vilvh v16i8:$vj, v16i8:$vk), 1797 (VILVH_B v16i8:$vj, v16i8:$vk)>; 1798def : Pat<(loongarch_vilvh v8i16:$vj, v8i16:$vk), 1799 (VILVH_H v8i16:$vj, v8i16:$vk)>; 1800def : Pat<(loongarch_vilvh v4i32:$vj, v4i32:$vk), 1801 (VILVH_W v4i32:$vj, v4i32:$vk)>; 1802def : Pat<(loongarch_vilvh v2i64:$vj, v2i64:$vk), 1803 (VILVH_D v2i64:$vj, v2i64:$vk)>; 1804def : Pat<(loongarch_vilvh v4f32:$vj, v4f32:$vk), 1805 (VILVH_W v4f32:$vj, v4f32:$vk)>; 1806def : Pat<(loongarch_vilvh v2f64:$vj, v2f64:$vk), 1807 (VILVH_D v2f64:$vj, v2f64:$vk)>; 1808 1809// VSHUF4I_{B/H/W} 1810def : Pat<(loongarch_vshuf4i v16i8:$vj, immZExt8:$ui8), 1811 (VSHUF4I_B v16i8:$vj, immZExt8:$ui8)>; 1812def : Pat<(loongarch_vshuf4i v8i16:$vj, immZExt8:$ui8), 1813 (VSHUF4I_H v8i16:$vj, immZExt8:$ui8)>; 1814def : Pat<(loongarch_vshuf4i v4i32:$vj, immZExt8:$ui8), 1815 (VSHUF4I_W v4i32:$vj, immZExt8:$ui8)>; 1816def : Pat<(loongarch_vshuf4i v4f32:$vj, immZExt8:$ui8), 1817 (VSHUF4I_W v4f32:$vj, immZExt8:$ui8)>; 1818 1819// VREPLVEI_{B/H/W/D} 1820def : Pat<(loongarch_vreplvei v16i8:$vj, immZExt4:$ui4), 1821 (VREPLVEI_B v16i8:$vj, immZExt4:$ui4)>; 1822def : Pat<(loongarch_vreplvei v8i16:$vj, immZExt3:$ui3), 1823 (VREPLVEI_H v8i16:$vj, immZExt3:$ui3)>; 1824def : Pat<(loongarch_vreplvei v4i32:$vj, immZExt2:$ui2), 1825 (VREPLVEI_W v4i32:$vj, immZExt2:$ui2)>; 1826def : Pat<(loongarch_vreplvei v2i64:$vj, immZExt1:$ui1), 1827 (VREPLVEI_D v2i64:$vj, immZExt1:$ui1)>; 1828def : Pat<(loongarch_vreplvei v4f32:$vj, immZExt2:$ui2), 1829 (VREPLVEI_W v4f32:$vj, immZExt2:$ui2)>; 1830def : Pat<(loongarch_vreplvei v2f64:$vj, immZExt1:$ui1), 1831 (VREPLVEI_D v2f64:$vj, immZExt1:$ui1)>; 1832 1833// VREPLVEI_{W/D} 1834def : Pat<(lsxsplatf32 FPR32:$fj), 1835 (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; 1836def : Pat<(lsxsplatf64 FPR64:$fj), 1837 (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; 1838 1839// Loads/Stores 1840foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 1841 defm : LdPat<load, VLD, vt>; 1842 def : RegRegLdPat<load, VLDX, vt>; 1843 defm : StPat<store, VST, LSX128, vt>; 1844 def : RegRegStPat<store, VSTX, LSX128, vt>; 1845} 1846 1847// Vector extraction with constant index. 1848def : Pat<(i64 (vector_extract v16i8:$vj, uimm4:$imm)), 1849 (VPICKVE2GR_B v16i8:$vj, uimm4:$imm)>; 1850def : Pat<(i64 (vector_extract v8i16:$vj, uimm3:$imm)), 1851 (VPICKVE2GR_H v8i16:$vj, uimm3:$imm)>; 1852def : Pat<(i64 (vector_extract v4i32:$vj, uimm2:$imm)), 1853 (VPICKVE2GR_W v4i32:$vj, uimm2:$imm)>; 1854def : Pat<(i64 (vector_extract v2i64:$vj, uimm1:$imm)), 1855 (VPICKVE2GR_D v2i64:$vj, uimm1:$imm)>; 1856def : Pat<(f32 (vector_extract v4f32:$vj, uimm2:$imm)), 1857 (f32 (EXTRACT_SUBREG (VREPLVEI_W v4f32:$vj, uimm2:$imm), sub_32))>; 1858def : Pat<(f64 (vector_extract v2f64:$vj, uimm1:$imm)), 1859 (f64 (EXTRACT_SUBREG (VREPLVEI_D v2f64:$vj, uimm1:$imm), sub_64))>; 1860 1861// Vector extraction with variable index. 1862def : Pat<(i64 (vector_extract v16i8:$vj, i64:$rk)), 1863 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_B v16i8:$vj, 1864 i64:$rk), 1865 sub_32)), 1866 GPR), (i64 24))>; 1867def : Pat<(i64 (vector_extract v8i16:$vj, i64:$rk)), 1868 (SRAI_W (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_H v8i16:$vj, 1869 i64:$rk), 1870 sub_32)), 1871 GPR), (i64 16))>; 1872def : Pat<(i64 (vector_extract v4i32:$vj, i64:$rk)), 1873 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (VREPLVE_W v4i32:$vj, i64:$rk), 1874 sub_32)), 1875 GPR)>; 1876def : Pat<(i64 (vector_extract v2i64:$vj, i64:$rk)), 1877 (COPY_TO_REGCLASS (f64 (EXTRACT_SUBREG (VREPLVE_D v2i64:$vj, i64:$rk), 1878 sub_64)), 1879 GPR)>; 1880def : Pat<(f32 (vector_extract v4f32:$vj, i64:$rk)), 1881 (f32 (EXTRACT_SUBREG (VREPLVE_W v4f32:$vj, i64:$rk), sub_32))>; 1882def : Pat<(f64 (vector_extract v2f64:$vj, i64:$rk)), 1883 (f64 (EXTRACT_SUBREG (VREPLVE_D v2f64:$vj, i64:$rk), sub_64))>; 1884 1885// vselect 1886def : Pat<(v16i8 (vselect LSX128:$vd, (v16i8 (SplatPat_uimm8 uimm8:$imm)), 1887 LSX128:$vj)), 1888 (VBITSELI_B LSX128:$vd, LSX128:$vj, uimm8:$imm)>; 1889foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 1890 def : Pat<(vt (vselect LSX128:$va, LSX128:$vk, LSX128:$vj)), 1891 (VBITSEL_V LSX128:$vj, LSX128:$vk, LSX128:$va)>; 1892 1893// fneg 1894def : Pat<(fneg (v4f32 LSX128:$vj)), (VBITREVI_W LSX128:$vj, 31)>; 1895def : Pat<(fneg (v2f64 LSX128:$vj)), (VBITREVI_D LSX128:$vj, 63)>; 1896 1897// VFFINT_{S_W/D_L} 1898def : Pat<(v4f32 (sint_to_fp v4i32:$vj)), (VFFINT_S_W v4i32:$vj)>; 1899def : Pat<(v2f64 (sint_to_fp v2i64:$vj)), (VFFINT_D_L v2i64:$vj)>; 1900 1901// VFFINT_{S_WU/D_LU} 1902def : Pat<(v4f32 (uint_to_fp v4i32:$vj)), (VFFINT_S_WU v4i32:$vj)>; 1903def : Pat<(v2f64 (uint_to_fp v2i64:$vj)), (VFFINT_D_LU v2i64:$vj)>; 1904 1905// VFTINTRZ_{W_S/L_D} 1906def : Pat<(v4i32 (fp_to_sint v4f32:$vj)), (VFTINTRZ_W_S v4f32:$vj)>; 1907def : Pat<(v2i64 (fp_to_sint v2f64:$vj)), (VFTINTRZ_L_D v2f64:$vj)>; 1908 1909// VFTINTRZ_{W_SU/L_DU} 1910def : Pat<(v4i32 (fp_to_uint v4f32:$vj)), (VFTINTRZ_WU_S v4f32:$vj)>; 1911def : Pat<(v2i64 (fp_to_uint v2f64:$vj)), (VFTINTRZ_LU_D v2f64:$vj)>; 1912 1913} // Predicates = [HasExtLSX] 1914 1915/// Intrinsic pattern 1916 1917class deriveLSXIntrinsic<string Inst> { 1918 Intrinsic ret = !cast<Intrinsic>(!tolower("int_loongarch_lsx_"#Inst)); 1919} 1920 1921let Predicates = [HasExtLSX] in { 1922 1923// vty: v16i8/v8i16/v4i32/v2i64 1924// Pat<(Intrinsic vty:$vj, vty:$vk), 1925// (LAInst vty:$vj, vty:$vk)>; 1926foreach Inst = ["VSADD_B", "VSADD_BU", "VSSUB_B", "VSSUB_BU", 1927 "VHADDW_H_B", "VHADDW_HU_BU", "VHSUBW_H_B", "VHSUBW_HU_BU", 1928 "VADDWEV_H_B", "VADDWOD_H_B", "VSUBWEV_H_B", "VSUBWOD_H_B", 1929 "VADDWEV_H_BU", "VADDWOD_H_BU", "VSUBWEV_H_BU", "VSUBWOD_H_BU", 1930 "VADDWEV_H_BU_B", "VADDWOD_H_BU_B", 1931 "VAVG_B", "VAVG_BU", "VAVGR_B", "VAVGR_BU", 1932 "VABSD_B", "VABSD_BU", "VADDA_B", "VMUH_B", "VMUH_BU", 1933 "VMULWEV_H_B", "VMULWOD_H_B", "VMULWEV_H_BU", "VMULWOD_H_BU", 1934 "VMULWEV_H_BU_B", "VMULWOD_H_BU_B", "VSIGNCOV_B", 1935 "VANDN_V", "VORN_V", "VROTR_B", "VSRLR_B", "VSRAR_B", 1936 "VSEQ_B", "VSLE_B", "VSLE_BU", "VSLT_B", "VSLT_BU", 1937 "VPACKEV_B", "VPACKOD_B", "VPICKEV_B", "VPICKOD_B", 1938 "VILVL_B", "VILVH_B"] in 1939 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1940 (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 1941 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1942foreach Inst = ["VSADD_H", "VSADD_HU", "VSSUB_H", "VSSUB_HU", 1943 "VHADDW_W_H", "VHADDW_WU_HU", "VHSUBW_W_H", "VHSUBW_WU_HU", 1944 "VADDWEV_W_H", "VADDWOD_W_H", "VSUBWEV_W_H", "VSUBWOD_W_H", 1945 "VADDWEV_W_HU", "VADDWOD_W_HU", "VSUBWEV_W_HU", "VSUBWOD_W_HU", 1946 "VADDWEV_W_HU_H", "VADDWOD_W_HU_H", 1947 "VAVG_H", "VAVG_HU", "VAVGR_H", "VAVGR_HU", 1948 "VABSD_H", "VABSD_HU", "VADDA_H", "VMUH_H", "VMUH_HU", 1949 "VMULWEV_W_H", "VMULWOD_W_H", "VMULWEV_W_HU", "VMULWOD_W_HU", 1950 "VMULWEV_W_HU_H", "VMULWOD_W_HU_H", "VSIGNCOV_H", "VROTR_H", 1951 "VSRLR_H", "VSRAR_H", "VSRLN_B_H", "VSRAN_B_H", "VSRLRN_B_H", 1952 "VSRARN_B_H", "VSSRLN_B_H", "VSSRAN_B_H", "VSSRLN_BU_H", 1953 "VSSRAN_BU_H", "VSSRLRN_B_H", "VSSRARN_B_H", "VSSRLRN_BU_H", 1954 "VSSRARN_BU_H", 1955 "VSEQ_H", "VSLE_H", "VSLE_HU", "VSLT_H", "VSLT_HU", 1956 "VPACKEV_H", "VPACKOD_H", "VPICKEV_H", "VPICKOD_H", 1957 "VILVL_H", "VILVH_H"] in 1958 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1959 (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 1960 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1961foreach Inst = ["VSADD_W", "VSADD_WU", "VSSUB_W", "VSSUB_WU", 1962 "VHADDW_D_W", "VHADDW_DU_WU", "VHSUBW_D_W", "VHSUBW_DU_WU", 1963 "VADDWEV_D_W", "VADDWOD_D_W", "VSUBWEV_D_W", "VSUBWOD_D_W", 1964 "VADDWEV_D_WU", "VADDWOD_D_WU", "VSUBWEV_D_WU", "VSUBWOD_D_WU", 1965 "VADDWEV_D_WU_W", "VADDWOD_D_WU_W", 1966 "VAVG_W", "VAVG_WU", "VAVGR_W", "VAVGR_WU", 1967 "VABSD_W", "VABSD_WU", "VADDA_W", "VMUH_W", "VMUH_WU", 1968 "VMULWEV_D_W", "VMULWOD_D_W", "VMULWEV_D_WU", "VMULWOD_D_WU", 1969 "VMULWEV_D_WU_W", "VMULWOD_D_WU_W", "VSIGNCOV_W", "VROTR_W", 1970 "VSRLR_W", "VSRAR_W", "VSRLN_H_W", "VSRAN_H_W", "VSRLRN_H_W", 1971 "VSRARN_H_W", "VSSRLN_H_W", "VSSRAN_H_W", "VSSRLN_HU_W", 1972 "VSSRAN_HU_W", "VSSRLRN_H_W", "VSSRARN_H_W", "VSSRLRN_HU_W", 1973 "VSSRARN_HU_W", 1974 "VSEQ_W", "VSLE_W", "VSLE_WU", "VSLT_W", "VSLT_WU", 1975 "VPACKEV_W", "VPACKOD_W", "VPICKEV_W", "VPICKOD_W", 1976 "VILVL_W", "VILVH_W"] in 1977 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1978 (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 1979 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 1980foreach Inst = ["VADD_Q", "VSUB_Q", 1981 "VSADD_D", "VSADD_DU", "VSSUB_D", "VSSUB_DU", 1982 "VHADDW_Q_D", "VHADDW_QU_DU", "VHSUBW_Q_D", "VHSUBW_QU_DU", 1983 "VADDWEV_Q_D", "VADDWOD_Q_D", "VSUBWEV_Q_D", "VSUBWOD_Q_D", 1984 "VADDWEV_Q_DU", "VADDWOD_Q_DU", "VSUBWEV_Q_DU", "VSUBWOD_Q_DU", 1985 "VADDWEV_Q_DU_D", "VADDWOD_Q_DU_D", 1986 "VAVG_D", "VAVG_DU", "VAVGR_D", "VAVGR_DU", 1987 "VABSD_D", "VABSD_DU", "VADDA_D", "VMUH_D", "VMUH_DU", 1988 "VMULWEV_Q_D", "VMULWOD_Q_D", "VMULWEV_Q_DU", "VMULWOD_Q_DU", 1989 "VMULWEV_Q_DU_D", "VMULWOD_Q_DU_D", "VSIGNCOV_D", "VROTR_D", 1990 "VSRLR_D", "VSRAR_D", "VSRLN_W_D", "VSRAN_W_D", "VSRLRN_W_D", 1991 "VSRARN_W_D", "VSSRLN_W_D", "VSSRAN_W_D", "VSSRLN_WU_D", 1992 "VSSRAN_WU_D", "VSSRLRN_W_D", "VSSRARN_W_D", "VSSRLRN_WU_D", 1993 "VSSRARN_WU_D", "VFFINT_S_L", 1994 "VSEQ_D", "VSLE_D", "VSLE_DU", "VSLT_D", "VSLT_DU", 1995 "VPACKEV_D", "VPACKOD_D", "VPICKEV_D", "VPICKOD_D", 1996 "VILVL_D", "VILVH_D"] in 1997 def : Pat<(deriveLSXIntrinsic<Inst>.ret 1998 (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 1999 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2000 2001// vty: v16i8/v8i16/v4i32/v2i64 2002// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 2003// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 2004foreach Inst = ["VMADDWEV_H_B", "VMADDWOD_H_B", "VMADDWEV_H_BU", 2005 "VMADDWOD_H_BU", "VMADDWEV_H_BU_B", "VMADDWOD_H_BU_B"] in 2006 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2007 (v8i16 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 2008 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2009foreach Inst = ["VMADDWEV_W_H", "VMADDWOD_W_H", "VMADDWEV_W_HU", 2010 "VMADDWOD_W_HU", "VMADDWEV_W_HU_H", "VMADDWOD_W_HU_H"] in 2011 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2012 (v4i32 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 2013 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2014foreach Inst = ["VMADDWEV_D_W", "VMADDWOD_D_W", "VMADDWEV_D_WU", 2015 "VMADDWOD_D_WU", "VMADDWEV_D_WU_W", "VMADDWOD_D_WU_W"] in 2016 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2017 (v2i64 LSX128:$vd), (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)), 2018 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2019foreach Inst = ["VMADDWEV_Q_D", "VMADDWOD_Q_D", "VMADDWEV_Q_DU", 2020 "VMADDWOD_Q_DU", "VMADDWEV_Q_DU_D", "VMADDWOD_Q_DU_D"] in 2021 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2022 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)), 2023 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2024 2025// vty: v16i8/v8i16/v4i32/v2i64 2026// Pat<(Intrinsic vty:$vj), 2027// (LAInst vty:$vj)>; 2028foreach Inst = ["VEXTH_H_B", "VEXTH_HU_BU", 2029 "VMSKLTZ_B", "VMSKGEZ_B", "VMSKNZ_B", 2030 "VCLO_B"] in 2031 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj)), 2032 (!cast<LAInst>(Inst) LSX128:$vj)>; 2033foreach Inst = ["VEXTH_W_H", "VEXTH_WU_HU", "VMSKLTZ_H", 2034 "VCLO_H", "VFCVTL_S_H", "VFCVTH_S_H"] in 2035 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj)), 2036 (!cast<LAInst>(Inst) LSX128:$vj)>; 2037foreach Inst = ["VEXTH_D_W", "VEXTH_DU_WU", "VMSKLTZ_W", 2038 "VCLO_W", "VFFINT_S_W", "VFFINT_S_WU", 2039 "VFFINTL_D_W", "VFFINTH_D_W"] in 2040 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj)), 2041 (!cast<LAInst>(Inst) LSX128:$vj)>; 2042foreach Inst = ["VEXTH_Q_D", "VEXTH_QU_DU", "VMSKLTZ_D", 2043 "VEXTL_Q_D", "VEXTL_QU_DU", 2044 "VCLO_D", "VFFINT_D_L", "VFFINT_D_LU"] in 2045 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj)), 2046 (!cast<LAInst>(Inst) LSX128:$vj)>; 2047 2048// Pat<(Intrinsic timm:$imm) 2049// (LAInst timm:$imm)>; 2050def : Pat<(int_loongarch_lsx_vldi timm:$imm), 2051 (VLDI (to_valid_timm timm:$imm))>; 2052foreach Inst = ["VREPLI_B", "VREPLI_H", "VREPLI_W", "VREPLI_D"] in 2053 def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm), 2054 (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>; 2055 2056// vty: v16i8/v8i16/v4i32/v2i64 2057// Pat<(Intrinsic vty:$vj, timm:$imm) 2058// (LAInst vty:$vj, timm:$imm)>; 2059foreach Inst = ["VSAT_B", "VSAT_BU", "VNORI_B", "VROTRI_B", "VSLLWIL_H_B", 2060 "VSLLWIL_HU_BU", "VSRLRI_B", "VSRARI_B", 2061 "VSEQI_B", "VSLEI_B", "VSLEI_BU", "VSLTI_B", "VSLTI_BU", 2062 "VREPLVEI_B", "VBSLL_V", "VBSRL_V", "VSHUF4I_B"] in 2063 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm), 2064 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2065foreach Inst = ["VSAT_H", "VSAT_HU", "VROTRI_H", "VSLLWIL_W_H", 2066 "VSLLWIL_WU_HU", "VSRLRI_H", "VSRARI_H", 2067 "VSEQI_H", "VSLEI_H", "VSLEI_HU", "VSLTI_H", "VSLTI_HU", 2068 "VREPLVEI_H", "VSHUF4I_H"] in 2069 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj), timm:$imm), 2070 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2071foreach Inst = ["VSAT_W", "VSAT_WU", "VROTRI_W", "VSLLWIL_D_W", 2072 "VSLLWIL_DU_WU", "VSRLRI_W", "VSRARI_W", 2073 "VSEQI_W", "VSLEI_W", "VSLEI_WU", "VSLTI_W", "VSLTI_WU", 2074 "VREPLVEI_W", "VSHUF4I_W"] in 2075 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj), timm:$imm), 2076 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2077foreach Inst = ["VSAT_D", "VSAT_DU", "VROTRI_D", "VSRLRI_D", "VSRARI_D", 2078 "VSEQI_D", "VSLEI_D", "VSLEI_DU", "VSLTI_D", "VSLTI_DU", 2079 "VPICKVE2GR_D", "VPICKVE2GR_DU", 2080 "VREPLVEI_D"] in 2081 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj), timm:$imm), 2082 (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>; 2083 2084// vty: v16i8/v8i16/v4i32/v2i64 2085// Pat<(Intrinsic vty:$vd, vty:$vj, timm:$imm) 2086// (LAInst vty:$vd, vty:$vj, timm:$imm)>; 2087foreach Inst = ["VSRLNI_B_H", "VSRANI_B_H", "VSRLRNI_B_H", "VSRARNI_B_H", 2088 "VSSRLNI_B_H", "VSSRANI_B_H", "VSSRLNI_BU_H", "VSSRANI_BU_H", 2089 "VSSRLRNI_B_H", "VSSRARNI_B_H", "VSSRLRNI_BU_H", "VSSRARNI_BU_H", 2090 "VFRSTPI_B", "VBITSELI_B", "VEXTRINS_B"] in 2091 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2092 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), timm:$imm), 2093 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2094 (to_valid_timm timm:$imm))>; 2095foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W", 2096 "VSSRLNI_H_W", "VSSRANI_H_W", "VSSRLNI_HU_W", "VSSRANI_HU_W", 2097 "VSSRLRNI_H_W", "VSSRARNI_H_W", "VSSRLRNI_HU_W", "VSSRARNI_HU_W", 2098 "VFRSTPI_H", "VEXTRINS_H"] in 2099 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2100 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), timm:$imm), 2101 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2102 (to_valid_timm timm:$imm))>; 2103foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D", 2104 "VSSRLNI_W_D", "VSSRANI_W_D", "VSSRLNI_WU_D", "VSSRANI_WU_D", 2105 "VSSRLRNI_W_D", "VSSRARNI_W_D", "VSSRLRNI_WU_D", "VSSRARNI_WU_D", 2106 "VPERMI_W", "VEXTRINS_W"] in 2107 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2108 (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), timm:$imm), 2109 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2110 (to_valid_timm timm:$imm))>; 2111foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q", 2112 "VSSRLNI_D_Q", "VSSRANI_D_Q", "VSSRLNI_DU_Q", "VSSRANI_DU_Q", 2113 "VSSRLRNI_D_Q", "VSSRARNI_D_Q", "VSSRLRNI_DU_Q", "VSSRARNI_DU_Q", 2114 "VSHUF4I_D", "VEXTRINS_D"] in 2115 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2116 (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), timm:$imm), 2117 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, 2118 (to_valid_timm timm:$imm))>; 2119 2120// vty: v16i8/v8i16/v4i32/v2i64 2121// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk), 2122// (LAInst vty:$vd, vty:$vj, vty:$vk)>; 2123foreach Inst = ["VFRSTP_B", "VBITSEL_V", "VSHUF_B"] in 2124 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2125 (v16i8 LSX128:$vd), (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)), 2126 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2127foreach Inst = ["VFRSTP_H", "VSHUF_H"] in 2128 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2129 (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)), 2130 (!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2131def : Pat<(int_loongarch_lsx_vshuf_w (v4i32 LSX128:$vd), (v4i32 LSX128:$vj), 2132 (v4i32 LSX128:$vk)), 2133 (VSHUF_W LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2134def : Pat<(int_loongarch_lsx_vshuf_d (v2i64 LSX128:$vd), (v2i64 LSX128:$vj), 2135 (v2i64 LSX128:$vk)), 2136 (VSHUF_D LSX128:$vd, LSX128:$vj, LSX128:$vk)>; 2137 2138// vty: v4f32/v2f64 2139// Pat<(Intrinsic vty:$vj, vty:$vk, vty:$va), 2140// (LAInst vty:$vj, vty:$vk, vty:$va)>; 2141foreach Inst = ["VFMSUB_S", "VFNMADD_S", "VFNMSUB_S"] in 2142 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2143 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), (v4f32 LSX128:$va)), 2144 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 2145foreach Inst = ["VFMSUB_D", "VFNMADD_D", "VFNMSUB_D"] in 2146 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2147 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), (v2f64 LSX128:$va)), 2148 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk, LSX128:$va)>; 2149 2150// vty: v4f32/v2f64 2151// Pat<(Intrinsic vty:$vj, vty:$vk), 2152// (LAInst vty:$vj, vty:$vk)>; 2153foreach Inst = ["VFMAX_S", "VFMIN_S", "VFMAXA_S", "VFMINA_S", "VFCVT_H_S", 2154 "VFCMP_CAF_S", "VFCMP_CUN_S", "VFCMP_CEQ_S", "VFCMP_CUEQ_S", 2155 "VFCMP_CLT_S", "VFCMP_CULT_S", "VFCMP_CLE_S", "VFCMP_CULE_S", 2156 "VFCMP_CNE_S", "VFCMP_COR_S", "VFCMP_CUNE_S", 2157 "VFCMP_SAF_S", "VFCMP_SUN_S", "VFCMP_SEQ_S", "VFCMP_SUEQ_S", 2158 "VFCMP_SLT_S", "VFCMP_SULT_S", "VFCMP_SLE_S", "VFCMP_SULE_S", 2159 "VFCMP_SNE_S", "VFCMP_SOR_S", "VFCMP_SUNE_S"] in 2160 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2161 (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)), 2162 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2163foreach Inst = ["VFMAX_D", "VFMIN_D", "VFMAXA_D", "VFMINA_D", "VFCVT_S_D", 2164 "VFTINTRNE_W_D", "VFTINTRZ_W_D", "VFTINTRP_W_D", "VFTINTRM_W_D", 2165 "VFTINT_W_D", 2166 "VFCMP_CAF_D", "VFCMP_CUN_D", "VFCMP_CEQ_D", "VFCMP_CUEQ_D", 2167 "VFCMP_CLT_D", "VFCMP_CULT_D", "VFCMP_CLE_D", "VFCMP_CULE_D", 2168 "VFCMP_CNE_D", "VFCMP_COR_D", "VFCMP_CUNE_D", 2169 "VFCMP_SAF_D", "VFCMP_SUN_D", "VFCMP_SEQ_D", "VFCMP_SUEQ_D", 2170 "VFCMP_SLT_D", "VFCMP_SULT_D", "VFCMP_SLE_D", "VFCMP_SULE_D", 2171 "VFCMP_SNE_D", "VFCMP_SOR_D", "VFCMP_SUNE_D"] in 2172 def : Pat<(deriveLSXIntrinsic<Inst>.ret 2173 (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)), 2174 (!cast<LAInst>(Inst) LSX128:$vj, LSX128:$vk)>; 2175 2176// vty: v4f32/v2f64 2177// Pat<(Intrinsic vty:$vj), 2178// (LAInst vty:$vj)>; 2179foreach Inst = ["VFLOGB_S", "VFCLASS_S", "VFSQRT_S", "VFRECIP_S", "VFRSQRT_S", 2180 "VFRINT_S", "VFCVTL_D_S", "VFCVTH_D_S", 2181 "VFRINTRNE_S", "VFRINTRZ_S", "VFRINTRP_S", "VFRINTRM_S", 2182 "VFTINTRNE_W_S", "VFTINTRZ_W_S", "VFTINTRP_W_S", "VFTINTRM_W_S", 2183 "VFTINT_W_S", "VFTINTRZ_WU_S", "VFTINT_WU_S", 2184 "VFTINTRNEL_L_S", "VFTINTRNEH_L_S", "VFTINTRZL_L_S", 2185 "VFTINTRZH_L_S", "VFTINTRPL_L_S", "VFTINTRPH_L_S", 2186 "VFTINTRML_L_S", "VFTINTRMH_L_S", "VFTINTL_L_S", 2187 "VFTINTH_L_S"] in 2188 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)), 2189 (!cast<LAInst>(Inst) LSX128:$vj)>; 2190foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D", 2191 "VFRINT_D", 2192 "VFRINTRNE_D", "VFRINTRZ_D", "VFRINTRP_D", "VFRINTRM_D", 2193 "VFTINTRNE_L_D", "VFTINTRZ_L_D", "VFTINTRP_L_D", "VFTINTRM_L_D", 2194 "VFTINT_L_D", "VFTINTRZ_LU_D", "VFTINT_LU_D"] in 2195 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)), 2196 (!cast<LAInst>(Inst) LSX128:$vj)>; 2197 2198// 128-Bit vector FP approximate reciprocal operation 2199let Predicates = [HasFrecipe] in { 2200foreach Inst = ["VFRECIPE_S", "VFRSQRTE_S"] in 2201 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4f32 LSX128:$vj)), 2202 (!cast<LAInst>(Inst) LSX128:$vj)>; 2203foreach Inst = ["VFRECIPE_D", "VFRSQRTE_D"] in 2204 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2f64 LSX128:$vj)), 2205 (!cast<LAInst>(Inst) LSX128:$vj)>; 2206} 2207 2208// load 2209def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm), 2210 (VLD GPR:$rj, (to_valid_timm timm:$imm))>; 2211def : Pat<(int_loongarch_lsx_vldx GPR:$rj, GPR:$rk), 2212 (VLDX GPR:$rj, GPR:$rk)>; 2213 2214def : Pat<(int_loongarch_lsx_vldrepl_b GPR:$rj, timm:$imm), 2215 (VLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>; 2216def : Pat<(int_loongarch_lsx_vldrepl_h GPR:$rj, timm:$imm), 2217 (VLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>; 2218def : Pat<(int_loongarch_lsx_vldrepl_w GPR:$rj, timm:$imm), 2219 (VLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>; 2220def : Pat<(int_loongarch_lsx_vldrepl_d GPR:$rj, timm:$imm), 2221 (VLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>; 2222 2223// store 2224def : Pat<(int_loongarch_lsx_vst LSX128:$vd, GPR:$rj, timm:$imm), 2225 (VST LSX128:$vd, GPR:$rj, (to_valid_timm timm:$imm))>; 2226def : Pat<(int_loongarch_lsx_vstx LSX128:$vd, GPR:$rj, GPR:$rk), 2227 (VSTX LSX128:$vd, GPR:$rj, GPR:$rk)>; 2228 2229def : Pat<(int_loongarch_lsx_vstelm_b v16i8:$vd, GPR:$rj, timm:$imm, timm:$idx), 2230 (VSTELM_B v16i8:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2231 (to_valid_timm timm:$idx))>; 2232def : Pat<(int_loongarch_lsx_vstelm_h v8i16:$vd, GPR:$rj, timm:$imm, timm:$idx), 2233 (VSTELM_H v8i16:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2234 (to_valid_timm timm:$idx))>; 2235def : Pat<(int_loongarch_lsx_vstelm_w v4i32:$vd, GPR:$rj, timm:$imm, timm:$idx), 2236 (VSTELM_W v4i32:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2237 (to_valid_timm timm:$idx))>; 2238def : Pat<(int_loongarch_lsx_vstelm_d v2i64:$vd, GPR:$rj, timm:$imm, timm:$idx), 2239 (VSTELM_D v2i64:$vd, GPR:$rj, (to_valid_timm timm:$imm), 2240 (to_valid_timm timm:$idx))>; 2241 2242} // Predicates = [HasExtLSX] 2243