1 //=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the LoongArch implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H 14 #define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H 15 16 #include "LoongArchRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "LoongArchGenInstrInfo.inc" 21 22 namespace llvm { 23 24 class LoongArchSubtarget; 25 26 class LoongArchInstrInfo : public LoongArchGenInstrInfo { 27 public: 28 explicit LoongArchInstrInfo(LoongArchSubtarget &STI); 29 30 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 31 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, 32 bool KillSrc) const override; 33 34 void storeRegToStackSlot(MachineBasicBlock &MBB, 35 MachineBasicBlock::iterator MBBI, Register SrcReg, 36 bool IsKill, int FrameIndex, 37 const TargetRegisterClass *RC, 38 const TargetRegisterInfo *TRI, 39 Register VReg) const override; 40 void loadRegFromStackSlot(MachineBasicBlock &MBB, 41 MachineBasicBlock::iterator MBBI, Register DstReg, 42 int FrameIndex, const TargetRegisterClass *RC, 43 const TargetRegisterInfo *TRI, 44 Register VReg) const override; 45 46 // Materializes the given integer Val into DstReg. 47 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 48 const DebugLoc &DL, Register DstReg, uint64_t Val, 49 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 50 51 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 52 53 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 54 55 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 56 MachineBasicBlock *&FBB, 57 SmallVectorImpl<MachineOperand> &Cond, 58 bool AllowModify) const override; 59 60 bool isBranchOffsetInRange(unsigned BranchOpc, 61 int64_t BrOffset) const override; 62 63 unsigned removeBranch(MachineBasicBlock &MBB, 64 int *BytesRemoved = nullptr) const override; 65 66 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 67 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 68 const DebugLoc &dl, 69 int *BytesAdded = nullptr) const override; 70 71 void insertIndirectBranch(MachineBasicBlock &MBB, 72 MachineBasicBlock &NewDestBB, 73 MachineBasicBlock &RestoreBB, const DebugLoc &DL, 74 int64_t BrOffset, RegScavenger *RS) const override; 75 76 bool 77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 78 79 std::pair<unsigned, unsigned> 80 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 81 82 ArrayRef<std::pair<unsigned, const char *>> 83 getSerializableDirectMachineOperandTargetFlags() const override; 84 85 protected: 86 const LoongArchSubtarget &STI; 87 }; 88 89 } // end namespace llvm 90 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H 91