1*81ad6265SDimitry Andric //=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===// 2*81ad6265SDimitry Andric // 3*81ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*81ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*81ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*81ad6265SDimitry Andric // 7*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 8*81ad6265SDimitry Andric // 9*81ad6265SDimitry Andric // This file contains the LoongArch implementation of the TargetInstrInfo class. 10*81ad6265SDimitry Andric // 11*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 12*81ad6265SDimitry Andric 13*81ad6265SDimitry Andric #include "LoongArchInstrInfo.h" 14*81ad6265SDimitry Andric #include "LoongArch.h" 15*81ad6265SDimitry Andric 16*81ad6265SDimitry Andric using namespace llvm; 17*81ad6265SDimitry Andric 18*81ad6265SDimitry Andric #define GET_INSTRINFO_CTOR_DTOR 19*81ad6265SDimitry Andric #include "LoongArchGenInstrInfo.inc" 20*81ad6265SDimitry Andric 21*81ad6265SDimitry Andric LoongArchInstrInfo::LoongArchInstrInfo(LoongArchSubtarget &STI) 22*81ad6265SDimitry Andric // FIXME: add CFSetup and CFDestroy Inst when we implement function call. 23*81ad6265SDimitry Andric : LoongArchGenInstrInfo() {} 24*81ad6265SDimitry Andric 25*81ad6265SDimitry Andric void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 26*81ad6265SDimitry Andric MachineBasicBlock::iterator MBBI, 27*81ad6265SDimitry Andric const DebugLoc &DL, MCRegister DstReg, 28*81ad6265SDimitry Andric MCRegister SrcReg, bool KillSrc) const { 29*81ad6265SDimitry Andric if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { 30*81ad6265SDimitry Andric BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) 31*81ad6265SDimitry Andric .addReg(SrcReg, getKillRegState(KillSrc)) 32*81ad6265SDimitry Andric .addReg(LoongArch::R0); 33*81ad6265SDimitry Andric return; 34*81ad6265SDimitry Andric } 35*81ad6265SDimitry Andric 36*81ad6265SDimitry Andric // FPR->FPR copies. 37*81ad6265SDimitry Andric unsigned Opc; 38*81ad6265SDimitry Andric if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) { 39*81ad6265SDimitry Andric Opc = LoongArch::FMOV_S; 40*81ad6265SDimitry Andric } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) { 41*81ad6265SDimitry Andric Opc = LoongArch::FMOV_D; 42*81ad6265SDimitry Andric } else { 43*81ad6265SDimitry Andric // TODO: support other copies. 44*81ad6265SDimitry Andric llvm_unreachable("Impossible reg-to-reg copy"); 45*81ad6265SDimitry Andric } 46*81ad6265SDimitry Andric 47*81ad6265SDimitry Andric BuildMI(MBB, MBBI, DL, get(Opc), DstReg) 48*81ad6265SDimitry Andric .addReg(SrcReg, getKillRegState(KillSrc)); 49*81ad6265SDimitry Andric } 50