1//===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Describe LoongArch instructions format 11// 12// opcode - operation code. 13// rd - destination register operand. 14// r{j/k} - source register operand. 15// immN - immediate data operand. 16// 17//===----------------------------------------------------------------------===// 18 19class LAInst<dag outs, dag ins, string opcstr, string opnstr, 20 list<dag> pattern = []> 21 : Instruction { 22 field bits<32> Inst; 23 // SoftFail is a field the disassembler can use to provide a way for 24 // instructions to not match without killing the whole decode process. It is 25 // mainly used for ARM, but Tablegen expects this field to exist or it fails 26 // to build the decode table. 27 field bits<32> SoftFail = 0; 28 29 let Namespace = "LoongArch"; 30 let Size = 4; 31 let OutOperandList = outs; 32 let InOperandList = ins; 33 let AsmString = opcstr # "\t" # opnstr; 34 let Pattern = pattern; 35} 36 37// Pseudo instructions 38class Pseudo<dag outs, dag ins, list<dag> pattern = [], string opcstr = "", 39 string opnstr = ""> 40 : LAInst<outs, ins, opcstr, opnstr, pattern> { 41 let isPseudo = 1; 42 let isCodeGenOnly = 1; 43} 44 45// 2R-type 46// <opcode | rj | rd> 47class Fmt2R<bits<22> op, dag outs, dag ins, string opcstr, string opnstr, 48 list<dag> pattern = []> 49 : LAInst<outs, ins, opcstr, opnstr, pattern> { 50 bits<5> rj; 51 bits<5> rd; 52 53 let Inst{31-10} = op; 54 let Inst{9-5} = rj; 55 let Inst{4-0} = rd; 56} 57 58// 3R-type 59// <opcode | rk | rj | rd> 60class Fmt3R<bits<17> op, dag outs, dag ins, string opcstr, string opnstr, 61 list<dag> pattern = []> 62 : LAInst<outs, ins, opcstr, opnstr, pattern> { 63 bits<5> rk; 64 bits<5> rj; 65 bits<5> rd; 66 67 let Inst{31-15} = op; 68 let Inst{14-10} = rk; 69 let Inst{9-5} = rj; 70 let Inst{4-0} = rd; 71} 72 73// 3RI2-type 74// <opcode | I2 | rk | rj | rd> 75class Fmt3RI2<bits<15> op, dag outs, dag ins, string opcstr, string opnstr, 76 list<dag> pattern = []> 77 : LAInst<outs, ins, opcstr, opnstr, pattern> { 78 bits<2> imm2; 79 bits<5> rk; 80 bits<5> rj; 81 bits<5> rd; 82 83 let Inst{31-17} = op; 84 let Inst{16-15} = imm2; 85 let Inst{14-10} = rk; 86 let Inst{9-5} = rj; 87 let Inst{4-0} = rd; 88} 89 90// 3RI3-type 91// <opcode | I3 | rk | rj | rd> 92class Fmt3RI3<bits<14> op, dag outs, dag ins, string opcstr, string opnstr, 93 list<dag> pattern = []> 94 : LAInst<outs, ins, opcstr, opnstr, pattern> { 95 bits<3> imm3; 96 bits<5> rk; 97 bits<5> rj; 98 bits<5> rd; 99 100 let Inst{31-18} = op; 101 let Inst{17-15} = imm3; 102 let Inst{14-10} = rk; 103 let Inst{9-5} = rj; 104 let Inst{4-0} = rd; 105} 106 107// 2RI5-type 108// <opcode | I5 | rj | rd> 109class Fmt2RI5<bits<17> op, dag outs, dag ins, string opcstr, string opnstr, 110 list<dag> pattern = []> 111 : LAInst<outs, ins, opcstr, opnstr, pattern> { 112 bits<5> imm5; 113 bits<5> rj; 114 bits<5> rd; 115 116 let Inst{31-15} = op; 117 let Inst{14-10} = imm5; 118 let Inst{9-5} = rj; 119 let Inst{4-0} = rd; 120} 121 122// 2RI6-type 123// <opcode | I6 | rj | rd> 124class Fmt2RI6<bits<16> op, dag outs, dag ins, string opcstr, string opnstr, 125 list<dag> pattern = []> 126 : LAInst<outs, ins, opcstr, opnstr, pattern> { 127 bits<6> imm6; 128 bits<5> rj; 129 bits<5> rd; 130 131 let Inst{31-16} = op; 132 let Inst{15-10} = imm6; 133 let Inst{9-5} = rj; 134 let Inst{4-0} = rd; 135} 136 137// 2RI8-type 138// <opcode | I8 | rj | rd> 139class Fmt2RI8<bits<14> op, dag outs, dag ins, string opcstr, string opnstr, 140 list<dag> pattern = []> 141 : LAInst<outs, ins, opcstr, opnstr, pattern> { 142 bits<8> imm8; 143 bits<5> rj; 144 bits<5> rd; 145 146 let Inst{31-18} = op; 147 let Inst{17-10} = imm8; 148 let Inst{9-5} = rj; 149 let Inst{4-0} = rd; 150} 151 152// 2RI12-type 153// <opcode | I12 | rj | rd> 154class Fmt2RI12<bits<10> op, dag outs, dag ins, string opcstr, string opnstr, 155 list<dag> pattern = []> 156 : LAInst<outs, ins, opcstr, opnstr, pattern> { 157 bits<12> imm12; 158 bits<5> rj; 159 bits<5> rd; 160 161 let Inst{31-22} = op; 162 let Inst{21-10} = imm12; 163 let Inst{9-5} = rj; 164 let Inst{4-0} = rd; 165} 166 167// 2RI14-type 168// <opcode | I14 | rj | rd> 169class Fmt2RI14<bits<8> op, dag outs, dag ins, string opcstr, string opnstr, 170 list<dag> pattern = []> 171 : LAInst<outs, ins, opcstr, opnstr, pattern> { 172 bits<14> imm14; 173 bits<5> rj; 174 bits<5> rd; 175 176 let Inst{31-24} = op; 177 let Inst{23-10} = imm14; 178 let Inst{9-5} = rj; 179 let Inst{4-0} = rd; 180} 181 182// 2RI16-type 183// <opcode | I16 | rj | rd> 184class Fmt2RI16<bits<6> op, dag outs, dag ins, string opcstr, string opnstr, 185 list<dag> pattern = []> 186 : LAInst<outs, ins, opcstr, opnstr, pattern> { 187 bits<16> imm16; 188 bits<5> rj; 189 bits<5> rd; 190 191 let Inst{31-26} = op; 192 let Inst{25-10} = imm16; 193 let Inst{9-5} = rj; 194 let Inst{4-0} = rd; 195} 196 197// 1RI20-type 198// <opcode | I20 | rd> 199class Fmt1RI20<bits<7> op, dag outs, dag ins, string opcstr, string opnstr, 200 list<dag> pattern = []> 201 : LAInst<outs, ins, opcstr, opnstr, pattern> { 202 bits<20> imm20; 203 bits<5> rd; 204 205 let Inst{31-25} = op; 206 let Inst{24-5} = imm20; 207 let Inst{4-0} = rd; 208} 209 210// 1RI21-type 211// <opcode | I21[15:0] | rj | I21[20:16]> 212class Fmt1RI21<bits<6> op, dag outs, dag ins, string opcstr, string opnstr, 213 list<dag> pattern = []> 214 : LAInst<outs, ins, opcstr, opnstr, pattern> { 215 bits<21> imm21; 216 bits<5> rj; 217 218 let Inst{31-26} = op; 219 let Inst{25-10} = imm21{15-0}; 220 let Inst{9-5} = rj; 221 let Inst{4-0} = imm21{20-16}; 222} 223 224// I15-type 225// <opcode | I15> 226class FmtI15<bits<17> op, dag outs, dag ins, string opcstr, string opnstr, 227 list<dag> pattern = []> 228 : LAInst<outs, ins, opcstr, opnstr, pattern> { 229 bits<15> imm15; 230 231 let Inst{31-15} = op; 232 let Inst{14-0} = imm15; 233} 234 235// I26-type 236// <opcode | I26[15:0] | I26[25:16]> 237class FmtI26<bits<6> op, dag outs, dag ins, string opcstr, string opnstr, 238 list<dag> pattern = []> 239 : LAInst<outs, ins, opcstr, opnstr, pattern> { 240 bits<26> imm26; 241 242 let Inst{31-26} = op; 243 let Inst{25-10} = imm26{15-0}; 244 let Inst{9-0} = imm26{25-16}; 245} 246 247// FmtBSTR_W 248// <opcode[11:1] | msbw | opcode[0] | lsbw | rj | rd> 249class FmtBSTR_W<bits<12> op, dag outs, dag ins, string opcstr, string opnstr, 250 list<dag> pattern = []> 251 : LAInst<outs, ins, opcstr, opnstr, pattern> { 252 bits<5> msbw; 253 bits<5> lsbw; 254 bits<5> rj; 255 bits<5> rd; 256 257 let Inst{31-21} = op{11-1}; 258 let Inst{20-16} = msbw; 259 let Inst{15} = op{0}; 260 let Inst{14-10} = lsbw; 261 let Inst{9-5} = rj; 262 let Inst{4-0} = rd; 263} 264 265// FmtBSTR_D 266// <opcode | msbd | lsbd | rj | rd> 267class FmtBSTR_D<bits<10> op, dag outs, dag ins, string opcstr, string opnstr, 268 list<dag> pattern = []> 269 : LAInst<outs, ins, opcstr, opnstr, pattern> { 270 bits<6> msbd; 271 bits<6> lsbd; 272 bits<5> rj; 273 bits<5> rd; 274 275 let Inst{31-22} = op; 276 let Inst{21-16} = msbd; 277 let Inst{15-10} = lsbd; 278 let Inst{9-5} = rj; 279 let Inst{4-0} = rd; 280} 281 282// FmtASRT 283// <opcode | rk | rj | 0x0> 284class FmtASRT<bits<17> op, dag outs, dag ins, string opcstr, string opnstr, 285 list<dag> pattern = []> 286 : LAInst<outs, ins, opcstr, opnstr, pattern> { 287 bits<5> rk; 288 bits<5> rj; 289 290 let Inst{31-15} = op; 291 let Inst{14-10} = rk; 292 let Inst{9-5} = rj; 293 let Inst{4-0} = 0x0; 294} 295 296// FmtPRELD 297// < 0b0010101011 | I12 | rj | I5> 298class FmtPRELD<dag outs, dag ins, string opcstr, string opnstr, 299 list<dag> pattern = []> 300 : LAInst<outs, ins, opcstr, opnstr, pattern> { 301 bits<12> imm12; 302 bits<5> rj; 303 bits<5> imm5; 304 305 let Inst{31-22} = 0b0010101011; 306 let Inst{21-10} = imm12; 307 let Inst{9-5} = rj; 308 let Inst{4-0} = imm5; 309} 310 311// FmtPRELDX 312// < 0b00111000001011000 | rk | rj | I5> 313class FmtPRELDX<dag outs, dag ins, string opcstr, string opnstr, 314 list<dag> pattern = []> 315 : LAInst<outs, ins, opcstr, opnstr, pattern> { 316 bits<5> rk; 317 bits<5> rj; 318 bits<5> imm5; 319 320 let Inst{31-15} = 0b00111000001011000; 321 let Inst{14-10} = rk; 322 let Inst{9-5} = rj; 323 let Inst{4-0} = imm5; 324} 325 326// FmtCSR 327// <opcode[12:5] | csr_num | opcode[4:0] | rd> 328class FmtCSR<bits<13> op, dag outs, dag ins, string opcstr, string opnstr, 329 list<dag> pattern = []> 330 : LAInst<outs, ins, opcstr, opnstr, pattern> { 331 bits<14> csr_num; 332 bits<5> rd; 333 334 let Inst{31-24} = op{12-5}; 335 let Inst{23-10} = csr_num; 336 let Inst{9-5} = op{4-0}; 337 let Inst{4-0} = rd; 338} 339 340// FmtCSRXCHG 341// <opcode | csr_num | rj | rd> 342class FmtCSRXCHG<bits<8> op, dag outs, dag ins, string opcstr, string opnstr, 343 list<dag> pattern = []> 344 : LAInst<outs, ins, opcstr, opnstr, pattern> { 345 bits<14> csr_num; 346 bits<5> rj; 347 bits<5> rd; 348 349 let Inst{31-24} = op; 350 let Inst{23-10} = csr_num; 351 let Inst{9-5} = rj; 352 let Inst{4-0} = rd; 353} 354 355// FmtCACOP 356// <0b0000011000 | I12 | rj | I5> 357class FmtCACOP<dag outs, dag ins, string opcstr, string opnstr, 358 list<dag> pattern = []> 359 : LAInst<outs, ins, opcstr, opnstr, pattern> { 360 bits<12> imm12; 361 bits<5> rj; 362 bits<5> op; 363 364 let Inst{31-22} = 0b0000011000; 365 let Inst{21-10} = imm12; 366 let Inst{9-5} = rj; 367 let Inst{4-0} = op; 368} 369 370// FmtIMM32 371// <I32> 372class FmtI32<bits<32> op, string opstr, list<dag> pattern = []> 373 : LAInst<(outs), (ins), opstr, "", pattern> { 374 let Inst{31-0} = op; 375} 376 377// FmtINVTLB 378// <0b00000110010010011 | rk | rj | I5> 379class FmtINVTLB<dag outs, dag ins, string opcstr, string opnstr, 380 list<dag> pattern = []> 381 : LAInst<outs, ins, opcstr, opnstr, pattern> { 382 bits<5> rk; 383 bits<5> rj; 384 bits<5> op; 385 386 let Inst{31-15} = 0b00000110010010011; 387 let Inst{14-10} = rk; 388 let Inst{9-5} = rj; 389 let Inst{4-0} = op; 390} 391 392// FmtLDPTE 393// <0b00000110010001 | seq | rj | 00000> 394class FmtLDPTE<dag outs, dag ins, string opcstr, string opnstr, 395 list<dag> pattern = []> 396 : LAInst<outs, ins, opcstr, opnstr, pattern> { 397 bits<8> seq; 398 bits<5> rj; 399 400 let Inst{31-18} = 0b00000110010001; 401 let Inst{17-10} = seq; 402 let Inst{9-5} = rj; 403 let Inst{4-0} = 0b00000; 404} 405