1// LoongArchFloat32InstrInfo.td - Single-Precision Float instr --*- tablegen -*- 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the baisc single-precision floating-point instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// LoongArch specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17def SDT_LoongArchMOVGR2FR_W_LA64 18 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 19def SDT_LoongArchMOVFR2GR_S_LA64 20 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 21def SDT_LoongArchFTINT : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 22 23def loongarch_movgr2fr_w_la64 24 : SDNode<"LoongArchISD::MOVGR2FR_W_LA64", SDT_LoongArchMOVGR2FR_W_LA64>; 25def loongarch_movfr2gr_s_la64 26 : SDNode<"LoongArchISD::MOVFR2GR_S_LA64", SDT_LoongArchMOVFR2GR_S_LA64>; 27def loongarch_ftint : SDNode<"LoongArchISD::FTINT", SDT_LoongArchFTINT>; 28 29//===----------------------------------------------------------------------===// 30// Instructions 31//===----------------------------------------------------------------------===// 32 33let Predicates = [HasBasicF] in { 34 35// Arithmetic Operation Instructions 36def FADD_S : FP_ALU_3R<0x01008000>; 37def FSUB_S : FP_ALU_3R<0x01028000>; 38def FMUL_S : FP_ALU_3R<0x01048000>; 39def FDIV_S : FP_ALU_3R<0x01068000>; 40def FMADD_S : FP_ALU_4R<0x08100000>; 41def FMSUB_S : FP_ALU_4R<0x08500000>; 42def FNMADD_S : FP_ALU_4R<0x08900000>; 43def FNMSUB_S : FP_ALU_4R<0x08d00000>; 44def FMAX_S : FP_ALU_3R<0x01088000>; 45def FMIN_S : FP_ALU_3R<0x010a8000>; 46def FMAXA_S : FP_ALU_3R<0x010c8000>; 47def FMINA_S : FP_ALU_3R<0x010e8000>; 48def FABS_S : FP_ALU_2R<0x01140400>; 49def FNEG_S : FP_ALU_2R<0x01141400>; 50def FSQRT_S : FP_ALU_2R<0x01144400>; 51def FRECIP_S : FP_ALU_2R<0x01145400>; 52def FRSQRT_S : FP_ALU_2R<0x01146400>; 53def FSCALEB_S : FP_ALU_3R<0x01108000>; 54def FLOGB_S : FP_ALU_2R<0x01142400>; 55def FCOPYSIGN_S : FP_ALU_3R<0x01128000>; 56def FCLASS_S : FP_ALU_2R<0x01143400>; 57 58 59// Comparison Instructions 60def FCMP_CAF_S : FP_CMP<0x0c100000>; 61def FCMP_CUN_S : FP_CMP<0x0c140000>; 62def FCMP_CEQ_S : FP_CMP<0x0c120000>; 63def FCMP_CUEQ_S : FP_CMP<0x0c160000>; 64def FCMP_CLT_S : FP_CMP<0x0c110000>; 65def FCMP_CULT_S : FP_CMP<0x0c150000>; 66def FCMP_CLE_S : FP_CMP<0x0c130000>; 67def FCMP_CULE_S : FP_CMP<0x0c170000>; 68def FCMP_CNE_S : FP_CMP<0x0c180000>; 69def FCMP_COR_S : FP_CMP<0x0c1a0000>; 70def FCMP_CUNE_S : FP_CMP<0x0c1c0000>; 71def FCMP_SAF_S : FP_CMP<0x0c108000>; 72def FCMP_SUN_S : FP_CMP<0x0c148000>; 73def FCMP_SEQ_S : FP_CMP<0x0c128000>; 74def FCMP_SUEQ_S : FP_CMP<0x0c168000>; 75def FCMP_SLT_S : FP_CMP<0x0c118000>; 76def FCMP_SULT_S : FP_CMP<0x0c158000>; 77def FCMP_SLE_S : FP_CMP<0x0c138000>; 78def FCMP_SULE_S : FP_CMP<0x0c178000>; 79def FCMP_SNE_S : FP_CMP<0x0c188000>; 80def FCMP_SOR_S : FP_CMP<0x0c1a8000>; 81def FCMP_SUNE_S : FP_CMP<0x0c1c8000>; 82 83// Conversion Instructions 84def FFINT_S_W : FP_CONV<0x011d1000>; 85def FTINT_W_S : FP_CONV<0x011b0400>; 86def FTINTRM_W_S : FP_CONV<0x011a0400>; 87def FTINTRP_W_S : FP_CONV<0x011a4400>; 88def FTINTRZ_W_S : FP_CONV<0x011a8400>; 89def FTINTRNE_W_S : FP_CONV<0x011ac400>; 90def FRINT_S : FP_CONV<0x011e4400>; 91 92// Move Instructions 93def FSEL_xS : FP_SEL<0x0d000000>; 94def FMOV_S : FP_MOV<0x01149400>; 95def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>; 96def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>; 97let hasSideEffects = 1 in { 98def MOVGR2FCSR : FP_MOV<0x0114c000, FCSR, GPR>; 99def MOVFCSR2GR : FP_MOV<0x0114c800, GPR, FCSR>; 100} // hasSideEffects = 1 101def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>; 102def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>; 103def MOVGR2CF : FP_MOV<0x0114d800, CFR, GPR>; 104def MOVCF2GR : FP_MOV<0x0114dc00, GPR, CFR>; 105 106// Branch Instructions 107def BCEQZ : FP_BRANCH<0x48000000>; 108def BCNEZ : FP_BRANCH<0x48000100>; 109 110// Common Memory Access Instructions 111def FLD_S : FP_LOAD_2RI12<0x2b000000>; 112def FST_S : FP_STORE_2RI12<0x2b400000>; 113def FLDX_S : FP_LOAD_3R<0x38300000>; 114def FSTX_S : FP_STORE_3R<0x38380000>; 115 116// Bound Check Memory Access Instructions 117def FLDGT_S : FP_LOAD_3R<0x38740000>; 118def FLDLE_S : FP_LOAD_3R<0x38750000>; 119def FSTGT_S : FP_STORE_3R<0x38760000>; 120def FSTLE_S : FP_STORE_3R<0x38770000>; 121 122// Pseudo instructions for spill/reload CFRs. 123let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 124def PseudoST_CFR : Pseudo<(outs), 125 (ins CFR:$ccd, GPR:$rj, grlenimm:$imm)>; 126let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 127def PseudoLD_CFR : Pseudo<(outs CFR:$ccd), 128 (ins GPR:$rj, grlenimm:$imm)>; 129 130// SET_CFR_{FALSE,TRUE} 131// These instructions are defined in order to avoid expensive check error if 132// regular instruction patterns are used. 133// fcmp.caf.s $dst, $fa0, $fa0 134def SET_CFR_FALSE : SET_CFR<0x0c100000, "fcmp.caf.s">; 135// fcmp.cueq.s $dst, $fa0, $fa0 136def SET_CFR_TRUE : SET_CFR<0x0c160000, "fcmp.cueq.s">; 137 138// Pseudo instruction for copying CFRs. 139def PseudoCopyCFR : Pseudo<(outs CFR:$dst), (ins CFR:$src)> { 140 let mayLoad = 0; 141 let mayStore = 0; 142 let hasSideEffects = 0; 143 let Size = 12; 144} 145 146} // Predicates = [HasBasicF] 147 148//===----------------------------------------------------------------------===// 149// Pseudo-instructions and codegen patterns 150//===----------------------------------------------------------------------===// 151 152/// Generic pattern classes 153 154class PatFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy> 155 : Pat<(OpNode RegTy:$fj), (Inst $fj)>; 156class PatFprFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy> 157 : Pat<(OpNode RegTy:$fj, RegTy:$fk), (Inst $fj, $fk)>; 158 159let Predicates = [HasBasicF] in { 160 161/// Float arithmetic operations 162 163def : PatFprFpr<fadd, FADD_S, FPR32>; 164def : PatFprFpr<fsub, FSUB_S, FPR32>; 165def : PatFprFpr<fmul, FMUL_S, FPR32>; 166def : PatFprFpr<fdiv, FDIV_S, FPR32>; 167def : PatFprFpr<fcopysign, FCOPYSIGN_S, FPR32>; 168def : PatFprFpr<fmaxnum_ieee, FMAX_S, FPR32>; 169def : PatFprFpr<fminnum_ieee, FMIN_S, FPR32>; 170def : PatFpr<fneg, FNEG_S, FPR32>; 171def : PatFpr<fabs, FABS_S, FPR32>; 172def : PatFpr<fsqrt, FSQRT_S, FPR32>; 173 174def : Pat<(fdiv fpimm1, (fsqrt FPR32:$fj)), (FRSQRT_S FPR32:$fj)>; 175 176def : Pat<(fcanonicalize FPR32:$fj), (FMAX_S $fj, $fj)>; 177 178/// Setcc 179 180// Match non-signaling comparison 181 182class PatFPSetcc<CondCode cc, LAInst CmpInst, RegisterClass RegTy> 183 : Pat<(any_fsetcc RegTy:$fj, RegTy:$fk, cc), 184 (CmpInst RegTy:$fj, RegTy:$fk)>; 185// SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into 186// SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT. 187def : PatFPSetcc<SETOEQ, FCMP_CEQ_S, FPR32>; 188def : PatFPSetcc<SETEQ, FCMP_CEQ_S, FPR32>; 189def : PatFPSetcc<SETOLT, FCMP_CLT_S, FPR32>; 190def : PatFPSetcc<SETOLE, FCMP_CLE_S, FPR32>; 191def : PatFPSetcc<SETLE, FCMP_CLE_S, FPR32>; 192def : PatFPSetcc<SETONE, FCMP_CNE_S, FPR32>; 193def : PatFPSetcc<SETO, FCMP_COR_S, FPR32>; 194def : PatFPSetcc<SETUEQ, FCMP_CUEQ_S, FPR32>; 195def : PatFPSetcc<SETULT, FCMP_CULT_S, FPR32>; 196def : PatFPSetcc<SETULE, FCMP_CULE_S, FPR32>; 197def : PatFPSetcc<SETUNE, FCMP_CUNE_S, FPR32>; 198def : PatFPSetcc<SETUO, FCMP_CUN_S, FPR32>; 199def : PatFPSetcc<SETLT, FCMP_CLT_S, FPR32>; 200 201multiclass PatFPBrcond<CondCode cc, LAInst CmpInst, RegisterClass RegTy> { 202 def : Pat<(brcond (xor (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), -1), 203 bb:$imm21), 204 (BCEQZ (CmpInst RegTy:$fj, RegTy:$fk), bb:$imm21)>; 205 def : Pat<(brcond (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), bb:$imm21), 206 (BCNEZ (CmpInst RegTy:$fj, RegTy:$fk), bb:$imm21)>; 207} 208 209defm : PatFPBrcond<SETOEQ, FCMP_CEQ_S, FPR32>; 210defm : PatFPBrcond<SETOLT, FCMP_CLT_S, FPR32>; 211defm : PatFPBrcond<SETOLE, FCMP_CLE_S, FPR32>; 212defm : PatFPBrcond<SETONE, FCMP_CNE_S, FPR32>; 213defm : PatFPBrcond<SETO, FCMP_COR_S, FPR32>; 214defm : PatFPBrcond<SETUEQ, FCMP_CUEQ_S, FPR32>; 215defm : PatFPBrcond<SETULT, FCMP_CULT_S, FPR32>; 216defm : PatFPBrcond<SETULE, FCMP_CULE_S, FPR32>; 217defm : PatFPBrcond<SETUNE, FCMP_CUNE_S, FPR32>; 218defm : PatFPBrcond<SETUO, FCMP_CUN_S, FPR32>; 219defm : PatFPBrcond<SETLT, FCMP_CLT_S, FPR32>; 220 221// Match signaling comparison 222 223class PatStrictFsetccs<CondCode cc, LAInst CmpInst, RegisterClass RegTy> 224 : Pat<(strict_fsetccs RegTy:$fj, RegTy:$fk, cc), 225 (CmpInst RegTy:$fj, RegTy:$fk)>; 226def : PatStrictFsetccs<SETOEQ, FCMP_SEQ_S, FPR32>; 227def : PatStrictFsetccs<SETOLT, FCMP_SLT_S, FPR32>; 228def : PatStrictFsetccs<SETOLE, FCMP_SLE_S, FPR32>; 229def : PatStrictFsetccs<SETONE, FCMP_SNE_S, FPR32>; 230def : PatStrictFsetccs<SETO, FCMP_SOR_S, FPR32>; 231def : PatStrictFsetccs<SETUEQ, FCMP_SUEQ_S, FPR32>; 232def : PatStrictFsetccs<SETULT, FCMP_SULT_S, FPR32>; 233def : PatStrictFsetccs<SETULE, FCMP_SULE_S, FPR32>; 234def : PatStrictFsetccs<SETUNE, FCMP_SUNE_S, FPR32>; 235def : PatStrictFsetccs<SETUO, FCMP_SUN_S, FPR32>; 236def : PatStrictFsetccs<SETLT, FCMP_SLT_S, FPR32>; 237 238/// Select 239 240def : Pat<(select CFR:$cc, FPR32:$fk, FPR32:$fj), 241 (FSEL_xS FPR32:$fj, FPR32:$fk, CFR:$cc)>; 242 243/// Selectcc 244 245class PatFPSelectcc<CondCode cc, LAInst CmpInst, LAInst SelInst, 246 RegisterClass RegTy> 247 : Pat<(select (GRLenVT (setcc RegTy:$a, RegTy:$b, cc)), RegTy:$t, RegTy:$f), 248 (SelInst RegTy:$f, RegTy:$t, (CmpInst RegTy:$a, RegTy:$b))>; 249def : PatFPSelectcc<SETOEQ, FCMP_CEQ_S, FSEL_xS, FPR32>; 250def : PatFPSelectcc<SETOLT, FCMP_CLT_S, FSEL_xS, FPR32>; 251def : PatFPSelectcc<SETOLE, FCMP_CLE_S, FSEL_xS, FPR32>; 252def : PatFPSelectcc<SETONE, FCMP_CNE_S, FSEL_xS, FPR32>; 253def : PatFPSelectcc<SETO, FCMP_COR_S, FSEL_xS, FPR32>; 254def : PatFPSelectcc<SETUEQ, FCMP_CUEQ_S, FSEL_xS, FPR32>; 255def : PatFPSelectcc<SETULT, FCMP_CULT_S, FSEL_xS, FPR32>; 256def : PatFPSelectcc<SETULE, FCMP_CULE_S, FSEL_xS, FPR32>; 257def : PatFPSelectcc<SETUNE, FCMP_CUNE_S, FSEL_xS, FPR32>; 258def : PatFPSelectcc<SETUO, FCMP_CUN_S, FSEL_xS, FPR32>; 259 260/// Loads 261 262defm : LdPat<load, FLD_S, f32>; 263def : RegRegLdPat<load, FLDX_S, f32>; 264 265/// Stores 266 267defm : StPat<store, FST_S, FPR32, f32>; 268def : RegRegStPat<store, FSTX_S, FPR32, f32>; 269 270/// Floating point constants 271 272def : Pat<(f32 fpimm0), (MOVGR2FR_W R0)>; 273def : Pat<(f32 fpimm0neg), (FNEG_S (MOVGR2FR_W R0))>; 274def : Pat<(f32 fpimm1), (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1)))>; 275 276// FP Conversion 277def : Pat<(loongarch_ftint FPR32:$src), (FTINTRZ_W_S FPR32:$src)>; 278 279// FP reciprocal operation 280def : Pat<(fdiv fpimm1, FPR32:$src), (FRECIP_S $src)>; 281 282// fmadd.s: fj * fk + fa 283def : Pat<(fma FPR32:$fj, FPR32:$fk, FPR32:$fa), (FMADD_S $fj, $fk, $fa)>; 284 285// fmsub.s: fj * fk - fa 286def : Pat<(fma FPR32:$fj, FPR32:$fk, (fneg FPR32:$fa)), 287 (FMSUB_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>; 288 289// fnmadd.s: -(fj * fk + fa) 290def : Pat<(fneg (fma FPR32:$fj, FPR32:$fk, FPR32:$fa)), 291 (FNMADD_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>; 292 293// fnmadd.s: -fj * fk - fa (the nsz flag on the FMA) 294def : Pat<(fma_nsz (fneg FPR32:$fj), FPR32:$fk, (fneg FPR32:$fa)), 295 (FNMADD_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>; 296 297// fnmsub.s: -fj * fk + fa 298def : Pat<(fma (fneg FPR32:$fj), FPR32:$fk, FPR32:$fa), 299 (FNMSUB_S FPR32:$fj, FPR32:$fk, FPR32:$fa)>; 300} // Predicates = [HasBasicF] 301 302let Predicates = [HasBasicF, IsLA64] in { 303// GPR -> FPR 304def : Pat<(loongarch_movgr2fr_w_la64 GPR:$src), (MOVGR2FR_W GPR:$src)>; 305// FPR -> GPR 306def : Pat<(loongarch_movfr2gr_s_la64 FPR32:$src), 307 (MOVFR2GR_S FPR32:$src)>; 308// int -> f32 309def : Pat<(f32 (sint_to_fp (i64 (sexti32 (i64 GPR:$src))))), 310 (FFINT_S_W (MOVGR2FR_W GPR:$src))>; 311// uint -> f32 312def : Pat<(f32 (uint_to_fp (i64 (sexti32 (i64 GPR:$src))))), 313 (FFINT_S_W (MOVGR2FR_W GPR:$src))>; 314} // Predicates = [HasBasicF, IsLA64] 315 316// FP Rounding 317let Predicates = [HasBasicF, IsLA64] in { 318def : PatFpr<frint, FRINT_S, FPR32>; 319} // Predicates = [HasBasicF, IsLA64] 320 321let Predicates = [HasBasicF, IsLA32] in { 322// GPR -> FPR 323def : Pat<(bitconvert (i32 GPR:$src)), (MOVGR2FR_W GPR:$src)>; 324// FPR -> GPR 325def : Pat<(i32 (bitconvert FPR32:$src)), (MOVFR2GR_S FPR32:$src)>; 326// int -> f32 327def : Pat<(f32 (sint_to_fp (i32 GPR:$src))), (FFINT_S_W (MOVGR2FR_W GPR:$src))>; 328} // Predicates = [HasBasicF, IsLA32] 329