xref: /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/LoongArch.td (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5) 
1//===-- LoongArch.td - Describe the LoongArch Target -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9include "llvm/Target/Target.td"
10
11//===----------------------------------------------------------------------===//
12// LoongArch subtarget features and instruction predicates.
13//===----------------------------------------------------------------------===//
14
15// LoongArch is divided into two versions, the 32-bit version (LA32) and the
16// 64-bit version (LA64).
17def Feature64Bit
18    : SubtargetFeature<"64bit", "HasLA64", "true",
19                       "LA64 Basic Integer and Privilege Instruction Set">;
20def IsLA64
21    : Predicate<"Subtarget->is64Bit()">,
22      AssemblerPredicate<(all_of Feature64Bit),
23                         "LA64 Basic Integer and Privilege Instruction Set">;
24def IsLA32
25    : Predicate<"!Subtarget->is64Bit()">,
26      AssemblerPredicate<(all_of(not Feature64Bit)),
27                         "LA32 Basic Integer and Privilege Instruction Set">;
28
29defvar LA32 = DefaultMode;
30def LA64 : HwMode<"+64bit">;
31
32// Single Precision floating point
33def FeatureBasicF
34    : SubtargetFeature<"f", "HasBasicF", "true",
35                       "'F' (Single-Precision Floating-Point)">;
36def HasBasicF
37    : Predicate<"Subtarget->hasBasicF()">,
38      AssemblerPredicate<(all_of FeatureBasicF),
39                         "'F' (Single-Precision Floating-Point)">;
40
41// Double Precision floating point
42def FeatureBasicD
43    : SubtargetFeature<"d", "HasBasicD", "true",
44                       "'D' (Double-Precision Floating-Point)",
45                       [FeatureBasicF]>;
46def HasBasicD
47    : Predicate<"Subtarget->hasBasicD()">,
48      AssemblerPredicate<(all_of FeatureBasicD),
49                         "'D' (Double-Precision Floating-Point)">;
50
51// Loongson SIMD eXtension (LSX)
52def FeatureExtLSX
53    : SubtargetFeature<"lsx", "HasExtLSX", "true",
54                       "'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>;
55def HasExtLSX
56    : Predicate<"Subtarget->hasExtLSX()">,
57      AssemblerPredicate<(all_of FeatureExtLSX),
58                         "'LSX' (Loongson SIMD Extension)">;
59
60// Loongson Advanced SIMD eXtension (LASX)
61def FeatureExtLASX
62    : SubtargetFeature<"lasx", "HasExtLASX", "true",
63                       "'LASX' (Loongson Advanced SIMD Extension)",
64                       [FeatureExtLSX]>;
65def HasExtLASX
66    : Predicate<"Subtarget->hasExtLASX()">,
67      AssemblerPredicate<(all_of FeatureExtLASX),
68                         "'LASX' (Loongson Advanced SIMD Extension)">;
69
70// Loongson VirtualiZation (LVZ)
71def FeatureExtLVZ
72    : SubtargetFeature<"lvz", "HasExtLVZ", "true",
73                       "'LVZ' (Loongson Virtualization Extension)">;
74def HasExtLVZ
75    : Predicate<"Subtarget->hasExtLVZ()">,
76      AssemblerPredicate<(all_of FeatureExtLVZ),
77                         "'LVZ' (Loongson Virtualization Extension)">;
78
79// Loongson Binary Translation (LBT)
80def FeatureExtLBT
81    : SubtargetFeature<"lbt", "HasExtLBT", "true",
82                       "'LBT' (Loongson Binary Translation Extension)">;
83def HasExtLBT
84    : Predicate<"Subtarget->hasExtLBT()">,
85      AssemblerPredicate<(all_of FeatureExtLBT),
86                         "'LBT' (Loongson Binary Translation Extension)">;
87
88//===----------------------------------------------------------------------===//
89// Registers, instruction descriptions ...
90//===----------------------------------------------------------------------===//
91
92include "LoongArchRegisterInfo.td"
93include "LoongArchCallingConv.td"
94include "LoongArchInstrInfo.td"
95
96//===----------------------------------------------------------------------===//
97// LoongArch processors supported.
98//===----------------------------------------------------------------------===//
99
100def : ProcessorModel<"generic-la32", NoSchedModel, []>;
101def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit]>;
102
103def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
104                                             FeatureExtLASX,
105                                             FeatureExtLVZ,
106                                             FeatureExtLBT]>;
107
108//===----------------------------------------------------------------------===//
109// Define the LoongArch target.
110//===----------------------------------------------------------------------===//
111
112def LoongArchInstrInfo : InstrInfo {
113  // guess mayLoad, mayStore, and hasSideEffects
114  // This option is a temporary migration help. It will go away.
115  let guessInstructionProperties = 1;
116}
117
118def LoongArchAsmParser : AsmParser {
119  let ShouldEmitMatchRegisterAltName = 1;
120  let AllowDuplicateRegisterNames = 1;
121}
122
123def LoongArchAsmParserVariant : AsmParserVariant {
124  int Variant = 0;
125  // Recognize hard coded registers.
126  string RegisterPrefix = "$";
127}
128
129def LoongArchAsmWriter : AsmWriter {
130  int PassSubtarget = 1;
131}
132
133def LoongArch : Target {
134  let InstructionSet = LoongArchInstrInfo;
135  let AssemblyParsers = [LoongArchAsmParser];
136  let AssemblyParserVariants = [LoongArchAsmParserVariant];
137  let AssemblyWriters = [LoongArchAsmWriter];
138  let AllowRegisterRenaming = 1;
139}
140