1//===-- LoongArch.td - Describe the LoongArch Target -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// LoongArch subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15// LoongArch is divided into two versions, the 32-bit version (LA32) and the 16// 64-bit version (LA64). 17def Feature64Bit 18 : SubtargetFeature<"64bit", "HasLA64", "true", 19 "LA64 Basic Integer and Privilege Instruction Set">; 20def Feature32Bit 21 : SubtargetFeature<"32bit", "HasLA32", "true", 22 "LA32 Basic Integer and Privilege Instruction Set">; 23def IsLA64 24 : Predicate<"Subtarget->is64Bit()">, 25 AssemblerPredicate<(all_of Feature64Bit), 26 "LA64 Basic Integer and Privilege Instruction Set">; 27def IsLA32 28 : Predicate<"!Subtarget->is64Bit()">, 29 AssemblerPredicate<(all_of(not Feature64Bit)), 30 "LA32 Basic Integer and Privilege Instruction Set">; 31 32defvar LA32 = DefaultMode; 33def LA64 : HwMode<"+64bit", [IsLA64]>; 34 35// Single Precision floating point 36def FeatureBasicF 37 : SubtargetFeature<"f", "HasBasicF", "true", 38 "'F' (Single-Precision Floating-Point)">; 39def HasBasicF : Predicate<"Subtarget->hasBasicF()">; 40 41// Double Precision floating point 42def FeatureBasicD 43 : SubtargetFeature<"d", "HasBasicD", "true", 44 "'D' (Double-Precision Floating-Point)", 45 [FeatureBasicF]>; 46def HasBasicD : Predicate<"Subtarget->hasBasicD()">; 47 48// Loongson SIMD eXtension (LSX) 49def FeatureExtLSX 50 : SubtargetFeature<"lsx", "HasExtLSX", "true", 51 "'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>; 52def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">; 53 54// Loongson Advanced SIMD eXtension (LASX) 55def FeatureExtLASX 56 : SubtargetFeature<"lasx", "HasExtLASX", "true", 57 "'LASX' (Loongson Advanced SIMD Extension)", 58 [FeatureExtLSX]>; 59def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">; 60 61// Loongson VirtualiZation (LVZ) 62def FeatureExtLVZ 63 : SubtargetFeature<"lvz", "HasExtLVZ", "true", 64 "'LVZ' (Loongson Virtualization Extension)">; 65def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">; 66 67// Loongson Binary Translation (LBT) 68def FeatureExtLBT 69 : SubtargetFeature<"lbt", "HasExtLBT", "true", 70 "'LBT' (Loongson Binary Translation Extension)">; 71def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">; 72 73// Expand la.global as la.pcrel 74def LaGlobalWithPcrel 75 : SubtargetFeature<"la-global-with-pcrel", "HasLaGlobalWithPcrel", "true", 76 "Expand la.global as la.pcrel">; 77def HasLaGlobalWithPcrel 78 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">, 79 AssemblerPredicate<(all_of LaGlobalWithPcrel), 80 "Expand la.global as la.pcrel">; 81 82// Expand la.global as la.abs 83def LaGlobalWithAbs 84 : SubtargetFeature<"la-global-with-abs", "HasLaGlobalWithAbs", "true", 85 "Expand la.global as la.abs">; 86def HasLaGlobalWithAbs 87 : Predicate<"Subtarget->hasLaGlobalWithAbs()">, 88 AssemblerPredicate<(all_of LaGlobalWithAbs), 89 "Expand la.global as la.abs">; 90 91// Expand la.local as la.abs 92def LaLocalWithAbs 93 : SubtargetFeature<"la-local-with-abs", "HasLaLocalWithAbs", "true", 94 "Expand la.local as la.abs">; 95def HasLaLocalWithAbs 96 : Predicate<"Subtarget->hasLaLocalWithAbs()">, 97 AssemblerPredicate<(all_of LaLocalWithAbs), 98 "Expand la.local as la.abs">; 99 100// Unaligned memory access 101def FeatureUAL 102 : SubtargetFeature<"ual", "HasUAL", "true", 103 "Allow memory accesses to be unaligned">; 104 105def FeatureRelax 106 : SubtargetFeature<"relax", "HasLinkerRelax", "true", 107 "Enable Linker relaxation">; 108 109// Experimental auto vectorization 110def FeatureAutoVec 111 : SubtargetFeature<"auto-vec", "HasExpAutoVec", "true", 112 "Experimental auto vectorization">; 113 114// Floating point approximation operation 115def FeatureFrecipe 116 : SubtargetFeature<"frecipe", "HasFrecipe", "true", 117 "Support frecipe.{s/d} and frsqrte.{s/d} instructions.">; 118def HasFrecipe : Predicate<"Subtarget->hasFrecipe()">; 119 120 121//===----------------------------------------------------------------------===// 122// Registers, instruction descriptions ... 123//===----------------------------------------------------------------------===// 124 125include "LoongArchRegisterInfo.td" 126include "LoongArchCallingConv.td" 127include "LoongArchInstrInfo.td" 128 129//===----------------------------------------------------------------------===// 130// LoongArch processors supported. 131//===----------------------------------------------------------------------===// 132 133def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>; 134def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, FeatureUAL]>; 135 136// Generic 64-bit processor with double-precision floating-point support. 137def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit, 138 FeatureUAL, 139 FeatureBasicD]>; 140 141// Support generic for compatibility with other targets. The triple will be used 142// to change to the appropriate la32/la64 version. 143def : ProcessorModel<"generic", NoSchedModel, []>; 144 145def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit, 146 FeatureUAL, 147 FeatureExtLASX, 148 FeatureExtLVZ, 149 FeatureExtLBT]>; 150 151//===----------------------------------------------------------------------===// 152// Define the LoongArch target. 153//===----------------------------------------------------------------------===// 154 155def LoongArchInstrInfo : InstrInfo { 156 let guessInstructionProperties = 0; 157} 158 159def LoongArchAsmParser : AsmParser { 160 let ShouldEmitMatchRegisterAltName = 1; 161 let AllowDuplicateRegisterNames = 1; 162} 163 164def LoongArchAsmParserVariant : AsmParserVariant { 165 int Variant = 0; 166 // Recognize hard coded registers. 167 string RegisterPrefix = "$"; 168} 169 170def LoongArchAsmWriter : AsmWriter { 171 int PassSubtarget = 1; 172} 173 174def LoongArch : Target { 175 let InstructionSet = LoongArchInstrInfo; 176 let AssemblyParsers = [LoongArchAsmParser]; 177 let AssemblyParserVariants = [LoongArchAsmParserVariant]; 178 let AssemblyWriters = [LoongArchAsmWriter]; 179 let AllowRegisterRenaming = 1; 180} 181