1//=-LanaiSchedule.td - Lanai Scheduling Definitions --*- tablegen -*-=========// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def ALU_FU : FuncUnit; 10def LDST_FU : FuncUnit; 11 12def IIC_ALU : InstrItinClass; 13def IIC_LD : InstrItinClass; 14def IIC_ST : InstrItinClass; 15def IIC_LDSW : InstrItinClass; 16def IIC_STSW : InstrItinClass; 17 18def LanaiItinerary : ProcessorItineraries<[ALU_FU, LDST_FU],[],[ 19 InstrItinData<IIC_LD, [InstrStage<1, [LDST_FU]>]>, 20 InstrItinData<IIC_ST, [InstrStage<1, [LDST_FU]>]>, 21 InstrItinData<IIC_LDSW, [InstrStage<2, [LDST_FU]>]>, 22 InstrItinData<IIC_STSW, [InstrStage<2, [LDST_FU]>]>, 23 InstrItinData<IIC_ALU, [InstrStage<1, [ALU_FU]>]> 24]>; 25 26def LanaiSchedModel : SchedMachineModel { 27 // Cycles for loads to access the cache [default = -1] 28 let LoadLatency = 2; 29 30 // Max micro-ops that can be buffered for optimized loop dispatch/execution. 31 // [default = -1] 32 let LoopMicroOpBufferSize = 0; 33 34 // Allow scheduler to assign default model to any unrecognized opcodes. 35 // [default = 1] 36 let CompleteModel = 0; 37 38 // Max micro-ops that may be scheduled per cycle. [default = 1] 39 let IssueWidth = 1; 40 41 // Extra cycles for a mispredicted branch. [default = -1] 42 let MispredictPenalty = 10; 43 44 // Enable Post RegAlloc Scheduler pass. [default = 0] 45 let PostRAScheduler = 0; 46 47 // Max micro-ops that can be buffered. [default = -1] 48 let MicroOpBufferSize = 0; 49 50 // Per-cycle resources tables. [default = NoItineraries] 51 let Itineraries = LanaiItinerary; 52} 53 54def ALU : ProcResource<1> { let BufferSize = 0; } 55def LdSt : ProcResource<1> { let BufferSize = 0; } 56 57def WriteLD : SchedWrite; 58def WriteST : SchedWrite; 59def WriteLDSW : SchedWrite; 60def WriteSTSW : SchedWrite; 61def WriteALU : SchedWrite; 62 63let SchedModel = LanaiSchedModel in { 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; } 68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; } 69} 70