xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/LanaiISelLowering.cpp (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873)
1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LanaiTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LanaiISelLowering.h"
14 #include "Lanai.h"
15 #include "LanaiCondCode.h"
16 #include "LanaiMachineFunctionInfo.h"
17 #include "LanaiSubtarget.h"
18 #include "LanaiTargetObjectFile.h"
19 #include "MCTargetDesc/LanaiBaseInfo.h"
20 #include "llvm/ADT/APInt.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RuntimeLibcalls.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/CodeGen/TargetCallingConv.h"
34 #include "llvm/CodeGen/ValueTypes.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalValue.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/KnownBits.h"
45 #include "llvm/Support/MachineValueType.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include <cassert>
50 #include <cmath>
51 #include <cstdint>
52 #include <cstdlib>
53 #include <utility>
54 
55 #define DEBUG_TYPE "lanai-lower"
56 
57 using namespace llvm;
58 
59 // Limit on number of instructions the lowered multiplication may have before a
60 // call to the library function should be generated instead. The threshold is
61 // currently set to 14 as this was the smallest threshold that resulted in all
62 // constant multiplications being lowered. A threshold of 5 covered all cases
63 // except for one multiplication which required 14. mulsi3 requires 16
64 // instructions (including the prologue and epilogue but excluding instructions
65 // at call site). Until we can inline mulsi3, generating at most 14 instructions
66 // will be faster than invoking mulsi3.
67 static cl::opt<int> LanaiLowerConstantMulThreshold(
68     "lanai-constant-mul-threshold", cl::Hidden,
69     cl::desc("Maximum number of instruction to generate when lowering constant "
70              "multiplication instead of calling library function [default=14]"),
71     cl::init(14));
72 
73 LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
74                                          const LanaiSubtarget &STI)
75     : TargetLowering(TM) {
76   // Set up the register classes.
77   addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
78 
79   // Compute derived properties from the register classes
80   TRI = STI.getRegisterInfo();
81   computeRegisterProperties(TRI);
82 
83   setStackPointerRegisterToSaveRestore(Lanai::SP);
84 
85   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
86   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88   setOperationAction(ISD::SETCC, MVT::i32, Custom);
89   setOperationAction(ISD::SELECT, MVT::i32, Expand);
90   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
91 
92   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
93   setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
94   setOperationAction(ISD::JumpTable, MVT::i32, Custom);
95   setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
96 
97   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
98   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
99   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
100 
101   setOperationAction(ISD::VASTART, MVT::Other, Custom);
102   setOperationAction(ISD::VAARG, MVT::Other, Expand);
103   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
104   setOperationAction(ISD::VAEND, MVT::Other, Expand);
105 
106   setOperationAction(ISD::SDIV, MVT::i32, Expand);
107   setOperationAction(ISD::UDIV, MVT::i32, Expand);
108   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
109   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
110   setOperationAction(ISD::SREM, MVT::i32, Expand);
111   setOperationAction(ISD::UREM, MVT::i32, Expand);
112 
113   setOperationAction(ISD::MUL, MVT::i32, Custom);
114   setOperationAction(ISD::MULHU, MVT::i32, Expand);
115   setOperationAction(ISD::MULHS, MVT::i32, Expand);
116   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 
119   setOperationAction(ISD::ROTR, MVT::i32, Expand);
120   setOperationAction(ISD::ROTL, MVT::i32, Expand);
121   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
122   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
123   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
124 
125   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
126   setOperationAction(ISD::CTPOP, MVT::i32, Legal);
127   setOperationAction(ISD::CTLZ, MVT::i32, Legal);
128   setOperationAction(ISD::CTTZ, MVT::i32, Legal);
129 
130   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
131   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
132   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
133 
134   // Extended load operations for i1 types must be promoted
135   for (MVT VT : MVT::integer_valuetypes()) {
136     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
137     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
138     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
139   }
140 
141   setTargetDAGCombine({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR});
142 
143   // Function alignments
144   setMinFunctionAlignment(Align(4));
145   setPrefFunctionAlignment(Align(4));
146 
147   setJumpIsExpensive(true);
148 
149   // TODO: Setting the minimum jump table entries needed before a
150   // switch is transformed to a jump table to 100 to avoid creating jump tables
151   // as this was causing bad performance compared to a large group of if
152   // statements. Re-evaluate this on new benchmarks.
153   setMinimumJumpTableEntries(100);
154 
155   // Use fast calling convention for library functions.
156   for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
157     setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
158   }
159 
160   MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
161   MaxStoresPerMemsetOptSize = 8;
162   MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
163   MaxStoresPerMemcpyOptSize = 8;
164   MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
165   MaxStoresPerMemmoveOptSize = 8;
166 
167   // Booleans always contain 0 or 1.
168   setBooleanContents(ZeroOrOneBooleanContent);
169 }
170 
171 SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
172                                             SelectionDAG &DAG) const {
173   switch (Op.getOpcode()) {
174   case ISD::MUL:
175     return LowerMUL(Op, DAG);
176   case ISD::BR_CC:
177     return LowerBR_CC(Op, DAG);
178   case ISD::ConstantPool:
179     return LowerConstantPool(Op, DAG);
180   case ISD::GlobalAddress:
181     return LowerGlobalAddress(Op, DAG);
182   case ISD::BlockAddress:
183     return LowerBlockAddress(Op, DAG);
184   case ISD::JumpTable:
185     return LowerJumpTable(Op, DAG);
186   case ISD::SELECT_CC:
187     return LowerSELECT_CC(Op, DAG);
188   case ISD::SETCC:
189     return LowerSETCC(Op, DAG);
190   case ISD::SHL_PARTS:
191     return LowerSHL_PARTS(Op, DAG);
192   case ISD::SRL_PARTS:
193     return LowerSRL_PARTS(Op, DAG);
194   case ISD::VASTART:
195     return LowerVASTART(Op, DAG);
196   case ISD::DYNAMIC_STACKALLOC:
197     return LowerDYNAMIC_STACKALLOC(Op, DAG);
198   case ISD::RETURNADDR:
199     return LowerRETURNADDR(Op, DAG);
200   case ISD::FRAMEADDR:
201     return LowerFRAMEADDR(Op, DAG);
202   default:
203     llvm_unreachable("unimplemented operand");
204   }
205 }
206 
207 //===----------------------------------------------------------------------===//
208 //                       Lanai Inline Assembly Support
209 //===----------------------------------------------------------------------===//
210 
211 Register LanaiTargetLowering::getRegisterByName(
212   const char *RegName, LLT /*VT*/,
213   const MachineFunction & /*MF*/) const {
214   // Only unallocatable registers should be matched here.
215   Register Reg = StringSwitch<unsigned>(RegName)
216                      .Case("pc", Lanai::PC)
217                      .Case("sp", Lanai::SP)
218                      .Case("fp", Lanai::FP)
219                      .Case("rr1", Lanai::RR1)
220                      .Case("r10", Lanai::R10)
221                      .Case("rr2", Lanai::RR2)
222                      .Case("r11", Lanai::R11)
223                      .Case("rca", Lanai::RCA)
224                      .Default(0);
225 
226   if (Reg)
227     return Reg;
228   report_fatal_error("Invalid register name global variable");
229 }
230 
231 std::pair<unsigned, const TargetRegisterClass *>
232 LanaiTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
233                                                   StringRef Constraint,
234                                                   MVT VT) const {
235   if (Constraint.size() == 1)
236     // GCC Constraint Letters
237     switch (Constraint[0]) {
238     case 'r': // GENERAL_REGS
239       return std::make_pair(0U, &Lanai::GPRRegClass);
240     default:
241       break;
242     }
243 
244   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
245 }
246 
247 // Examine constraint type and operand type and determine a weight value.
248 // This object must already have been set up with the operand type
249 // and the current alternative constraint selected.
250 TargetLowering::ConstraintWeight
251 LanaiTargetLowering::getSingleConstraintMatchWeight(
252     AsmOperandInfo &Info, const char *Constraint) const {
253   ConstraintWeight Weight = CW_Invalid;
254   Value *CallOperandVal = Info.CallOperandVal;
255   // If we don't have a value, we can't do a match,
256   // but allow it at the lowest weight.
257   if (CallOperandVal == nullptr)
258     return CW_Default;
259   // Look at the constraint type.
260   switch (*Constraint) {
261   case 'I': // signed 16 bit immediate
262   case 'J': // integer zero
263   case 'K': // unsigned 16 bit immediate
264   case 'L': // immediate in the range 0 to 31
265   case 'M': // signed 32 bit immediate where lower 16 bits are 0
266   case 'N': // signed 26 bit immediate
267   case 'O': // integer zero
268     if (isa<ConstantInt>(CallOperandVal))
269       Weight = CW_Constant;
270     break;
271   default:
272     Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
273     break;
274   }
275   return Weight;
276 }
277 
278 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
279 // vector.  If it is invalid, don't add anything to Ops.
280 void LanaiTargetLowering::LowerAsmOperandForConstraint(
281     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
282     SelectionDAG &DAG) const {
283   SDValue Result;
284 
285   // Only support length 1 constraints for now.
286   if (Constraint.length() > 1)
287     return;
288 
289   char ConstraintLetter = Constraint[0];
290   switch (ConstraintLetter) {
291   case 'I': // Signed 16 bit constant
292     // If this fails, the parent routine will give an error
293     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
294       if (isInt<16>(C->getSExtValue())) {
295         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
296                                        Op.getValueType());
297         break;
298       }
299     }
300     return;
301   case 'J': // integer zero
302   case 'O':
303     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
304       if (C->getZExtValue() == 0) {
305         Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
306         break;
307       }
308     }
309     return;
310   case 'K': // unsigned 16 bit immediate
311     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
312       if (isUInt<16>(C->getZExtValue())) {
313         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
314                                        Op.getValueType());
315         break;
316       }
317     }
318     return;
319   case 'L': // immediate in the range 0 to 31
320     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
321       if (C->getZExtValue() <= 31) {
322         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
323                                        Op.getValueType());
324         break;
325       }
326     }
327     return;
328   case 'M': // signed 32 bit immediate where lower 16 bits are 0
329     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
330       int64_t Val = C->getSExtValue();
331       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
332         Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
333         break;
334       }
335     }
336     return;
337   case 'N': // signed 26 bit immediate
338     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
339       int64_t Val = C->getSExtValue();
340       if ((Val >= -33554432) && (Val <= 33554431)) {
341         Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
342         break;
343       }
344     }
345     return;
346   default:
347     break; // This will fall through to the generic implementation
348   }
349 
350   if (Result.getNode()) {
351     Ops.push_back(Result);
352     return;
353   }
354 
355   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
356 }
357 
358 //===----------------------------------------------------------------------===//
359 //                      Calling Convention Implementation
360 //===----------------------------------------------------------------------===//
361 
362 #include "LanaiGenCallingConv.inc"
363 
364 static unsigned NumFixedArgs;
365 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
366                               CCValAssign::LocInfo LocInfo,
367                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
368   // Handle fixed arguments with default CC.
369   // Note: Both the default and fast CC handle VarArg the same and hence the
370   // calling convention of the function is not considered here.
371   if (ValNo < NumFixedArgs) {
372     return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
373   }
374 
375   // Promote i8/i16 args to i32
376   if (LocVT == MVT::i8 || LocVT == MVT::i16) {
377     LocVT = MVT::i32;
378     if (ArgFlags.isSExt())
379       LocInfo = CCValAssign::SExt;
380     else if (ArgFlags.isZExt())
381       LocInfo = CCValAssign::ZExt;
382     else
383       LocInfo = CCValAssign::AExt;
384   }
385 
386   // VarArgs get passed on stack
387   unsigned Offset = State.AllocateStack(4, Align(4));
388   State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
389   return false;
390 }
391 
392 SDValue LanaiTargetLowering::LowerFormalArguments(
393     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
394     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
395     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
396   switch (CallConv) {
397   case CallingConv::C:
398   case CallingConv::Fast:
399     return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
400   default:
401     report_fatal_error("Unsupported calling convention");
402   }
403 }
404 
405 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
406                                        SmallVectorImpl<SDValue> &InVals) const {
407   SelectionDAG &DAG = CLI.DAG;
408   SDLoc &DL = CLI.DL;
409   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
410   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
411   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
412   SDValue Chain = CLI.Chain;
413   SDValue Callee = CLI.Callee;
414   bool &IsTailCall = CLI.IsTailCall;
415   CallingConv::ID CallConv = CLI.CallConv;
416   bool IsVarArg = CLI.IsVarArg;
417 
418   // Lanai target does not yet support tail call optimization.
419   IsTailCall = false;
420 
421   switch (CallConv) {
422   case CallingConv::Fast:
423   case CallingConv::C:
424     return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
425                           OutVals, Ins, DL, DAG, InVals);
426   default:
427     report_fatal_error("Unsupported calling convention");
428   }
429 }
430 
431 // LowerCCCArguments - transform physical registers into virtual registers and
432 // generate load operations for arguments places on the stack.
433 SDValue LanaiTargetLowering::LowerCCCArguments(
434     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
435     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
436     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
437   MachineFunction &MF = DAG.getMachineFunction();
438   MachineFrameInfo &MFI = MF.getFrameInfo();
439   MachineRegisterInfo &RegInfo = MF.getRegInfo();
440   LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
441 
442   // Assign locations to all of the incoming arguments.
443   SmallVector<CCValAssign, 16> ArgLocs;
444   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
445                  *DAG.getContext());
446   if (CallConv == CallingConv::Fast) {
447     CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
448   } else {
449     CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
450   }
451 
452   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
453     CCValAssign &VA = ArgLocs[i];
454     if (VA.isRegLoc()) {
455       // Arguments passed in registers
456       EVT RegVT = VA.getLocVT();
457       switch (RegVT.getSimpleVT().SimpleTy) {
458       case MVT::i32: {
459         Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
460         RegInfo.addLiveIn(VA.getLocReg(), VReg);
461         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
462 
463         // If this is an 8/16-bit value, it is really passed promoted to 32
464         // bits. Insert an assert[sz]ext to capture this, then truncate to the
465         // right size.
466         if (VA.getLocInfo() == CCValAssign::SExt)
467           ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
468                                  DAG.getValueType(VA.getValVT()));
469         else if (VA.getLocInfo() == CCValAssign::ZExt)
470           ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
471                                  DAG.getValueType(VA.getValVT()));
472 
473         if (VA.getLocInfo() != CCValAssign::Full)
474           ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
475 
476         InVals.push_back(ArgValue);
477         break;
478       }
479       default:
480         LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
481                           << RegVT.getEVTString() << "\n");
482         llvm_unreachable("unhandled argument type");
483       }
484     } else {
485       // Only arguments passed on the stack should make it here.
486       assert(VA.isMemLoc());
487       // Load the argument to a virtual register
488       unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
489       // Check that the argument fits in stack slot
490       if (ObjSize > 4) {
491         errs() << "LowerFormalArguments Unhandled argument type: "
492                << EVT(VA.getLocVT()).getEVTString() << "\n";
493       }
494       // Create the frame index object for this incoming parameter...
495       int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
496 
497       // Create the SelectionDAG nodes corresponding to a load
498       // from this parameter
499       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
500       InVals.push_back(DAG.getLoad(
501           VA.getLocVT(), DL, Chain, FIN,
502           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
503     }
504   }
505 
506   // The Lanai ABI for returning structs by value requires that we copy
507   // the sret argument into rv for the return. Save the argument into
508   // a virtual register so that we can access it from the return points.
509   if (MF.getFunction().hasStructRetAttr()) {
510     Register Reg = LanaiMFI->getSRetReturnReg();
511     if (!Reg) {
512       Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
513       LanaiMFI->setSRetReturnReg(Reg);
514     }
515     SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
516     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
517   }
518 
519   if (IsVarArg) {
520     // Record the frame index of the first variable argument
521     // which is a value necessary to VASTART.
522     int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
523     LanaiMFI->setVarArgsFrameIndex(FI);
524   }
525 
526   return Chain;
527 }
528 
529 bool LanaiTargetLowering::CanLowerReturn(
530     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
531     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
532   SmallVector<CCValAssign, 16> RVLocs;
533   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
534 
535   return CCInfo.CheckReturn(Outs, RetCC_Lanai32);
536 }
537 
538 SDValue
539 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
540                                  bool IsVarArg,
541                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
542                                  const SmallVectorImpl<SDValue> &OutVals,
543                                  const SDLoc &DL, SelectionDAG &DAG) const {
544   // CCValAssign - represent the assignment of the return value to a location
545   SmallVector<CCValAssign, 16> RVLocs;
546 
547   // CCState - Info about the registers and stack slot.
548   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
549                  *DAG.getContext());
550 
551   // Analize return values.
552   CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
553 
554   SDValue Flag;
555   SmallVector<SDValue, 4> RetOps(1, Chain);
556 
557   // Copy the result values into the output registers.
558   for (unsigned i = 0; i != RVLocs.size(); ++i) {
559     CCValAssign &VA = RVLocs[i];
560     assert(VA.isRegLoc() && "Can only return in registers!");
561 
562     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
563 
564     // Guarantee that all emitted copies are stuck together with flags.
565     Flag = Chain.getValue(1);
566     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
567   }
568 
569   // The Lanai ABI for returning structs by value requires that we copy
570   // the sret argument into rv for the return. We saved the argument into
571   // a virtual register in the entry block, so now we copy the value out
572   // and into rv.
573   if (DAG.getMachineFunction().getFunction().hasStructRetAttr()) {
574     MachineFunction &MF = DAG.getMachineFunction();
575     LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
576     Register Reg = LanaiMFI->getSRetReturnReg();
577     assert(Reg &&
578            "SRetReturnReg should have been set in LowerFormalArguments().");
579     SDValue Val =
580         DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
581 
582     Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
583     Flag = Chain.getValue(1);
584     RetOps.push_back(
585         DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
586   }
587 
588   RetOps[0] = Chain; // Update chain
589 
590   unsigned Opc = LanaiISD::RET_FLAG;
591   if (Flag.getNode())
592     RetOps.push_back(Flag);
593 
594   // Return Void
595   return DAG.getNode(Opc, DL, MVT::Other,
596                      ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
597 }
598 
599 // LowerCCCCallTo - functions arguments are copied from virtual regs to
600 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
601 SDValue LanaiTargetLowering::LowerCCCCallTo(
602     SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
603     bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
604     const SmallVectorImpl<SDValue> &OutVals,
605     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
606     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
607   // Analyze operands of the call, assigning locations to each operand.
608   SmallVector<CCValAssign, 16> ArgLocs;
609   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
610                  *DAG.getContext());
611   GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
612   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
613 
614   NumFixedArgs = 0;
615   if (IsVarArg && G) {
616     const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
617     if (CalleeFn)
618       NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
619   }
620   if (NumFixedArgs)
621     CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
622   else {
623     if (CallConv == CallingConv::Fast)
624       CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
625     else
626       CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
627   }
628 
629   // Get a count of how many bytes are to be pushed on the stack.
630   unsigned NumBytes = CCInfo.getNextStackOffset();
631 
632   // Create local copies for byval args.
633   SmallVector<SDValue, 8> ByValArgs;
634   for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
635     ISD::ArgFlagsTy Flags = Outs[I].Flags;
636     if (!Flags.isByVal())
637       continue;
638 
639     SDValue Arg = OutVals[I];
640     unsigned Size = Flags.getByValSize();
641     Align Alignment = Flags.getNonZeroByValAlign();
642 
643     int FI = MFI.CreateStackObject(Size, Alignment, false);
644     SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
645     SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
646 
647     Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
648                           /*IsVolatile=*/false,
649                           /*AlwaysInline=*/false,
650                           /*isTailCall=*/false, MachinePointerInfo(),
651                           MachinePointerInfo());
652     ByValArgs.push_back(FIPtr);
653   }
654 
655   Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
656 
657   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
658   SmallVector<SDValue, 12> MemOpChains;
659   SDValue StackPtr;
660 
661   // Walk the register/memloc assignments, inserting copies/loads.
662   for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
663     CCValAssign &VA = ArgLocs[I];
664     SDValue Arg = OutVals[I];
665     ISD::ArgFlagsTy Flags = Outs[I].Flags;
666 
667     // Promote the value if needed.
668     switch (VA.getLocInfo()) {
669     case CCValAssign::Full:
670       break;
671     case CCValAssign::SExt:
672       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
673       break;
674     case CCValAssign::ZExt:
675       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
676       break;
677     case CCValAssign::AExt:
678       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
679       break;
680     default:
681       llvm_unreachable("Unknown loc info!");
682     }
683 
684     // Use local copy if it is a byval arg.
685     if (Flags.isByVal())
686       Arg = ByValArgs[J++];
687 
688     // Arguments that can be passed on register must be kept at RegsToPass
689     // vector
690     if (VA.isRegLoc()) {
691       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
692     } else {
693       assert(VA.isMemLoc());
694 
695       if (StackPtr.getNode() == nullptr)
696         StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
697                                       getPointerTy(DAG.getDataLayout()));
698 
699       SDValue PtrOff =
700           DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
701                       DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
702 
703       MemOpChains.push_back(
704           DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
705     }
706   }
707 
708   // Transform all store nodes into one single node because all store nodes are
709   // independent of each other.
710   if (!MemOpChains.empty())
711     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
712                         ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
713 
714   SDValue InFlag;
715 
716   // Build a sequence of copy-to-reg nodes chained together with token chain and
717   // flag operands which copy the outgoing args into registers.  The InFlag in
718   // necessary since all emitted instructions must be stuck together.
719   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
720     Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
721                              RegsToPass[I].second, InFlag);
722     InFlag = Chain.getValue(1);
723   }
724 
725   // If the callee is a GlobalAddress node (quite common, every direct call is)
726   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
727   // Likewise ExternalSymbol -> TargetExternalSymbol.
728   uint8_t OpFlag = LanaiII::MO_NO_FLAG;
729   if (G) {
730     Callee = DAG.getTargetGlobalAddress(
731         G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
732   } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
733     Callee = DAG.getTargetExternalSymbol(
734         E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
735   }
736 
737   // Returns a chain & a flag for retval copy to use.
738   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
739   SmallVector<SDValue, 8> Ops;
740   Ops.push_back(Chain);
741   Ops.push_back(Callee);
742 
743   // Add a register mask operand representing the call-preserved registers.
744   // TODO: Should return-twice functions be handled?
745   const uint32_t *Mask =
746       TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
747   assert(Mask && "Missing call preserved mask for calling convention");
748   Ops.push_back(DAG.getRegisterMask(Mask));
749 
750   // Add argument registers to the end of the list so that they are
751   // known live into the call.
752   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
753     Ops.push_back(DAG.getRegister(RegsToPass[I].first,
754                                   RegsToPass[I].second.getValueType()));
755 
756   if (InFlag.getNode())
757     Ops.push_back(InFlag);
758 
759   Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
760                       ArrayRef<SDValue>(&Ops[0], Ops.size()));
761   InFlag = Chain.getValue(1);
762 
763   // Create the CALLSEQ_END node.
764   Chain = DAG.getCALLSEQ_END(
765       Chain,
766       DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
767       DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
768       DL);
769   InFlag = Chain.getValue(1);
770 
771   // Handle result values, copying them out of physregs into vregs that we
772   // return.
773   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
774                          InVals);
775 }
776 
777 // LowerCallResult - Lower the result values of a call into the
778 // appropriate copies out of appropriate physical registers.
779 SDValue LanaiTargetLowering::LowerCallResult(
780     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
781     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
782     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
783   // Assign locations to each value returned by this call.
784   SmallVector<CCValAssign, 16> RVLocs;
785   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
786                  *DAG.getContext());
787 
788   CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
789 
790   // Copy all of the result registers out of their specified physreg.
791   for (unsigned I = 0; I != RVLocs.size(); ++I) {
792     Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
793                                RVLocs[I].getValVT(), InFlag)
794                 .getValue(1);
795     InFlag = Chain.getValue(2);
796     InVals.push_back(Chain.getValue(0));
797   }
798 
799   return Chain;
800 }
801 
802 //===----------------------------------------------------------------------===//
803 //                      Custom Lowerings
804 //===----------------------------------------------------------------------===//
805 
806 static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL,
807                                         SDValue &RHS, SelectionDAG &DAG) {
808   ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
809 
810   // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
811   // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
812   // and Lanai only supports integer comparisons, so only provide definitions
813   // for them.
814   switch (SetCCOpcode) {
815   case ISD::SETEQ:
816     return LPCC::ICC_EQ;
817   case ISD::SETGT:
818     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
819       if (RHSC->getZExtValue() == 0xFFFFFFFF) {
820         // X > -1 -> X >= 0 -> is_plus(X)
821         RHS = DAG.getConstant(0, DL, RHS.getValueType());
822         return LPCC::ICC_PL;
823       }
824     return LPCC::ICC_GT;
825   case ISD::SETUGT:
826     return LPCC::ICC_UGT;
827   case ISD::SETLT:
828     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
829       if (RHSC->getZExtValue() == 0)
830         // X < 0 -> is_minus(X)
831         return LPCC::ICC_MI;
832     return LPCC::ICC_LT;
833   case ISD::SETULT:
834     return LPCC::ICC_ULT;
835   case ISD::SETLE:
836     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
837       if (RHSC->getZExtValue() == 0xFFFFFFFF) {
838         // X <= -1 -> X < 0 -> is_minus(X)
839         RHS = DAG.getConstant(0, DL, RHS.getValueType());
840         return LPCC::ICC_MI;
841       }
842     return LPCC::ICC_LE;
843   case ISD::SETULE:
844     return LPCC::ICC_ULE;
845   case ISD::SETGE:
846     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
847       if (RHSC->getZExtValue() == 0)
848         // X >= 0 -> is_plus(X)
849         return LPCC::ICC_PL;
850     return LPCC::ICC_GE;
851   case ISD::SETUGE:
852     return LPCC::ICC_UGE;
853   case ISD::SETNE:
854     return LPCC::ICC_NE;
855   case ISD::SETONE:
856   case ISD::SETUNE:
857   case ISD::SETOGE:
858   case ISD::SETOLE:
859   case ISD::SETOLT:
860   case ISD::SETOGT:
861   case ISD::SETOEQ:
862   case ISD::SETUEQ:
863   case ISD::SETO:
864   case ISD::SETUO:
865     llvm_unreachable("Unsupported comparison.");
866   default:
867     llvm_unreachable("Unknown integer condition code!");
868   }
869 }
870 
871 SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
872   SDValue Chain = Op.getOperand(0);
873   SDValue Cond = Op.getOperand(1);
874   SDValue LHS = Op.getOperand(2);
875   SDValue RHS = Op.getOperand(3);
876   SDValue Dest = Op.getOperand(4);
877   SDLoc DL(Op);
878 
879   LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
880   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
881   SDValue Flag =
882       DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
883 
884   return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
885                      TargetCC, Flag);
886 }
887 
888 SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
889   EVT VT = Op->getValueType(0);
890   if (VT != MVT::i32)
891     return SDValue();
892 
893   ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
894   if (!C)
895     return SDValue();
896 
897   int64_t MulAmt = C->getSExtValue();
898   int32_t HighestOne = -1;
899   uint32_t NonzeroEntries = 0;
900   int SignedDigit[32] = {0};
901 
902   // Convert to non-adjacent form (NAF) signed-digit representation.
903   // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
904   // minimal Hamming weight representation of a number (on average 1/3 of the
905   // digits will be non-zero vs 1/2 for regular binary representation). And as
906   // the non-zero digits will be the only digits contributing to the instruction
907   // count, this is desirable. The next loop converts it to NAF (following the
908   // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
909   // choosing the non-zero coefficients such that the resulting quotient is
910   // divisible by 2 which will cause the next coefficient to be zero.
911   int64_t E = std::abs(MulAmt);
912   int S = (MulAmt < 0 ? -1 : 1);
913   int I = 0;
914   while (E > 0) {
915     int ZI = 0;
916     if (E % 2 == 1) {
917       ZI = 2 - (E % 4);
918       if (ZI != 0)
919         ++NonzeroEntries;
920     }
921     SignedDigit[I] = S * ZI;
922     if (SignedDigit[I] == 1)
923       HighestOne = I;
924     E = (E - ZI) / 2;
925     ++I;
926   }
927 
928   // Compute number of instructions required. Due to differences in lowering
929   // between the different processors this count is not exact.
930   // Start by assuming a shift and a add/sub for every non-zero entry (hence
931   // every non-zero entry requires 1 shift and 1 add/sub except for the first
932   // entry).
933   int32_t InstrRequired = 2 * NonzeroEntries - 1;
934   // Correct possible over-adding due to shift by 0 (which is not emitted).
935   if (std::abs(MulAmt) % 2 == 1)
936     --InstrRequired;
937   // Return if the form generated would exceed the instruction threshold.
938   if (InstrRequired > LanaiLowerConstantMulThreshold)
939     return SDValue();
940 
941   SDValue Res;
942   SDLoc DL(Op);
943   SDValue V = Op->getOperand(0);
944 
945   // Initialize the running sum. Set the running sum to the maximal shifted
946   // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
947   // term NAF).
948   if (HighestOne == -1)
949     Res = DAG.getConstant(0, DL, MVT::i32);
950   else {
951     Res = DAG.getNode(ISD::SHL, DL, VT, V,
952                       DAG.getConstant(HighestOne, DL, MVT::i32));
953     SignedDigit[HighestOne] = 0;
954   }
955 
956   // Assemble multiplication from shift, add, sub using NAF form and running
957   // sum.
958   for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
959        ++I) {
960     if (SignedDigit[I] == 0)
961       continue;
962 
963     // Shifted multiplicand (v<<i).
964     SDValue Op =
965         DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
966     if (SignedDigit[I] == 1)
967       Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
968     else if (SignedDigit[I] == -1)
969       Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
970   }
971   return Res;
972 }
973 
974 SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
975   SDValue LHS = Op.getOperand(0);
976   SDValue RHS = Op.getOperand(1);
977   SDValue Cond = Op.getOperand(2);
978   SDLoc DL(Op);
979 
980   LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
981   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
982   SDValue Flag =
983       DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
984 
985   return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
986 }
987 
988 SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
989                                             SelectionDAG &DAG) const {
990   SDValue LHS = Op.getOperand(0);
991   SDValue RHS = Op.getOperand(1);
992   SDValue TrueV = Op.getOperand(2);
993   SDValue FalseV = Op.getOperand(3);
994   SDValue Cond = Op.getOperand(4);
995   SDLoc DL(Op);
996 
997   LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
998   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
999   SDValue Flag =
1000       DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
1001 
1002   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1003   return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1004                      Flag);
1005 }
1006 
1007 SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1008   MachineFunction &MF = DAG.getMachineFunction();
1009   LanaiMachineFunctionInfo *FuncInfo = MF.getInfo<LanaiMachineFunctionInfo>();
1010 
1011   SDLoc DL(Op);
1012   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1013                                  getPointerTy(DAG.getDataLayout()));
1014 
1015   // vastart just stores the address of the VarArgsFrameIndex slot into the
1016   // memory location argument.
1017   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1018   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1019                       MachinePointerInfo(SV));
1020 }
1021 
1022 SDValue LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1023                                                      SelectionDAG &DAG) const {
1024   SDValue Chain = Op.getOperand(0);
1025   SDValue Size = Op.getOperand(1);
1026   SDLoc DL(Op);
1027 
1028   Register SPReg = getStackPointerRegisterToSaveRestore();
1029 
1030   // Get a reference to the stack pointer.
1031   SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1032 
1033   // Subtract the dynamic size from the actual stack size to
1034   // obtain the new stack size.
1035   SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1036 
1037   // For Lanai, the outgoing memory arguments area should be on top of the
1038   // alloca area on the stack i.e., the outgoing memory arguments should be
1039   // at a lower address than the alloca area. Move the alloca area down the
1040   // stack by adding back the space reserved for outgoing arguments to SP
1041   // here.
1042   //
1043   // We do not know what the size of the outgoing args is at this point.
1044   // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1045   // stack pointer. We replace this instruction with on that has the correct,
1046   // known offset in emitPrologue().
1047   SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1048 
1049   // The Sub result contains the new stack start address, so it
1050   // must be placed in the stack pointer register.
1051   SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1052 
1053   SDValue Ops[2] = {ArgAdjust, CopyChain};
1054   return DAG.getMergeValues(Ops, DL);
1055 }
1056 
1057 SDValue LanaiTargetLowering::LowerRETURNADDR(SDValue Op,
1058                                              SelectionDAG &DAG) const {
1059   MachineFunction &MF = DAG.getMachineFunction();
1060   MachineFrameInfo &MFI = MF.getFrameInfo();
1061   MFI.setReturnAddressIsTaken(true);
1062 
1063   EVT VT = Op.getValueType();
1064   SDLoc DL(Op);
1065   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1066   if (Depth) {
1067     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1068     const unsigned Offset = -4;
1069     SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1070                               DAG.getIntPtrConstant(Offset, DL));
1071     return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1072   }
1073 
1074   // Return the link register, which contains the return address.
1075   // Mark it an implicit live-in.
1076   Register Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1077   return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1078 }
1079 
1080 SDValue LanaiTargetLowering::LowerFRAMEADDR(SDValue Op,
1081                                             SelectionDAG &DAG) const {
1082   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1083   MFI.setFrameAddressIsTaken(true);
1084 
1085   EVT VT = Op.getValueType();
1086   SDLoc DL(Op);
1087   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1088   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1089   while (Depth--) {
1090     const unsigned Offset = -8;
1091     SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1092                               DAG.getIntPtrConstant(Offset, DL));
1093     FrameAddr =
1094         DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1095   }
1096   return FrameAddr;
1097 }
1098 
1099 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1100   switch (Opcode) {
1101   case LanaiISD::ADJDYNALLOC:
1102     return "LanaiISD::ADJDYNALLOC";
1103   case LanaiISD::RET_FLAG:
1104     return "LanaiISD::RET_FLAG";
1105   case LanaiISD::CALL:
1106     return "LanaiISD::CALL";
1107   case LanaiISD::SELECT_CC:
1108     return "LanaiISD::SELECT_CC";
1109   case LanaiISD::SETCC:
1110     return "LanaiISD::SETCC";
1111   case LanaiISD::SUBBF:
1112     return "LanaiISD::SUBBF";
1113   case LanaiISD::SET_FLAG:
1114     return "LanaiISD::SET_FLAG";
1115   case LanaiISD::BR_CC:
1116     return "LanaiISD::BR_CC";
1117   case LanaiISD::Wrapper:
1118     return "LanaiISD::Wrapper";
1119   case LanaiISD::HI:
1120     return "LanaiISD::HI";
1121   case LanaiISD::LO:
1122     return "LanaiISD::LO";
1123   case LanaiISD::SMALL:
1124     return "LanaiISD::SMALL";
1125   default:
1126     return nullptr;
1127   }
1128 }
1129 
1130 SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op,
1131                                                SelectionDAG &DAG) const {
1132   SDLoc DL(Op);
1133   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1134   const Constant *C = N->getConstVal();
1135   const LanaiTargetObjectFile *TLOF =
1136       static_cast<const LanaiTargetObjectFile *>(
1137           getTargetMachine().getObjFileLowering());
1138 
1139   // If the code model is small or constant will be placed in the small section,
1140   // then assume address will fit in 21-bits.
1141   if (getTargetMachine().getCodeModel() == CodeModel::Small ||
1142       TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1143     SDValue Small = DAG.getTargetConstantPool(
1144         C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG);
1145     return DAG.getNode(ISD::OR, DL, MVT::i32,
1146                        DAG.getRegister(Lanai::R0, MVT::i32),
1147                        DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1148   } else {
1149     uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1150     uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1151 
1152     SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1153                                            N->getOffset(), OpFlagHi);
1154     SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1155                                            N->getOffset(), OpFlagLo);
1156     Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1157     Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1158     SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1159     return Result;
1160   }
1161 }
1162 
1163 SDValue LanaiTargetLowering::LowerGlobalAddress(SDValue Op,
1164                                                 SelectionDAG &DAG) const {
1165   SDLoc DL(Op);
1166   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1167   int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1168 
1169   const LanaiTargetObjectFile *TLOF =
1170       static_cast<const LanaiTargetObjectFile *>(
1171           getTargetMachine().getObjFileLowering());
1172 
1173   // If the code model is small or global variable will be placed in the small
1174   // section, then assume address will fit in 21-bits.
1175   const GlobalObject *GO = GV->getAliaseeObject();
1176   if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1177     SDValue Small = DAG.getTargetGlobalAddress(
1178         GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1179     return DAG.getNode(ISD::OR, DL, MVT::i32,
1180                        DAG.getRegister(Lanai::R0, MVT::i32),
1181                        DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1182   } else {
1183     uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1184     uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1185 
1186     // Create the TargetGlobalAddress node, folding in the constant offset.
1187     SDValue Hi = DAG.getTargetGlobalAddress(
1188         GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1189     SDValue Lo = DAG.getTargetGlobalAddress(
1190         GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1191     Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1192     Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1193     return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1194   }
1195 }
1196 
1197 SDValue LanaiTargetLowering::LowerBlockAddress(SDValue Op,
1198                                                SelectionDAG &DAG) const {
1199   SDLoc DL(Op);
1200   const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1201 
1202   uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1203   uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1204 
1205   SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1206   SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1207   Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1208   Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1209   SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1210   return Result;
1211 }
1212 
1213 SDValue LanaiTargetLowering::LowerJumpTable(SDValue Op,
1214                                             SelectionDAG &DAG) const {
1215   SDLoc DL(Op);
1216   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1217 
1218   // If the code model is small assume address will fit in 21-bits.
1219   if (getTargetMachine().getCodeModel() == CodeModel::Small) {
1220     SDValue Small = DAG.getTargetJumpTable(
1221         JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1222     return DAG.getNode(ISD::OR, DL, MVT::i32,
1223                        DAG.getRegister(Lanai::R0, MVT::i32),
1224                        DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1225   } else {
1226     uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1227     uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1228 
1229     SDValue Hi = DAG.getTargetJumpTable(
1230         JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1231     SDValue Lo = DAG.getTargetJumpTable(
1232         JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1233     Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1234     Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1235     SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1236     return Result;
1237   }
1238 }
1239 
1240 SDValue LanaiTargetLowering::LowerSHL_PARTS(SDValue Op,
1241                                             SelectionDAG &DAG) const {
1242   EVT VT = Op.getValueType();
1243   unsigned VTBits = VT.getSizeInBits();
1244   SDLoc dl(Op);
1245   assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1246   SDValue ShOpLo = Op.getOperand(0);
1247   SDValue ShOpHi = Op.getOperand(1);
1248   SDValue ShAmt = Op.getOperand(2);
1249 
1250   // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1251   //   LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1252   //   HiBitsForHi = ShOpHi << ShAmt
1253   //   Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1254   //   Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1255   //   return (Hi << 32) | Lo;
1256 
1257   SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1258                                  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1259   SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1260 
1261   // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1262   // wanted 0, so CSEL it directly.
1263   SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1264   SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1265   LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1266 
1267   SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1268                                    DAG.getConstant(VTBits, dl, MVT::i32));
1269   SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1270   SDValue HiForNormalShift =
1271       DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1272 
1273   SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1274 
1275   SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1276   SDValue Hi =
1277       DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1278 
1279   // Lanai shifts of larger than register sizes are wrapped rather than
1280   // clamped, so we can't just emit "lo << b" if b is too big.
1281   SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1282   SDValue Lo = DAG.getSelect(
1283       dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1284 
1285   SDValue Ops[2] = {Lo, Hi};
1286   return DAG.getMergeValues(Ops, dl);
1287 }
1288 
1289 SDValue LanaiTargetLowering::LowerSRL_PARTS(SDValue Op,
1290                                             SelectionDAG &DAG) const {
1291   MVT VT = Op.getSimpleValueType();
1292   unsigned VTBits = VT.getSizeInBits();
1293   SDLoc dl(Op);
1294   SDValue ShOpLo = Op.getOperand(0);
1295   SDValue ShOpHi = Op.getOperand(1);
1296   SDValue ShAmt = Op.getOperand(2);
1297 
1298   // Performs the following for a >> b:
1299   //   unsigned r_high = a_high >> b;
1300   //   r_high = (32 - b <= 0) ? 0 : r_high;
1301   //
1302   //   unsigned r_low = a_low >> b;
1303   //   r_low = (32 - b <= 0) ? r_high : r_low;
1304   //   r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1305   //   return (unsigned long long)r_high << 32 | r_low;
1306   // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1307   // mask the shift amount.
1308 
1309   SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1310   SDValue NegatedPlus32 = DAG.getNode(
1311       ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1312   SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1313 
1314   SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1315   Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1316 
1317   SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1318   Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1319   SDValue CarryBits =
1320       DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1321   SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1322   Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1323                      DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1324 
1325   SDValue Ops[2] = {Lo, Hi};
1326   return DAG.getMergeValues(Ops, dl);
1327 }
1328 
1329 // Helper function that checks if N is a null or all ones constant.
1330 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1331   return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1332 }
1333 
1334 // Return true if N is conditionally 0 or all ones.
1335 // Detects these expressions where cc is an i1 value:
1336 //
1337 //   (select cc 0, y)   [AllOnes=0]
1338 //   (select cc y, 0)   [AllOnes=0]
1339 //   (zext cc)          [AllOnes=0]
1340 //   (sext cc)          [AllOnes=0/1]
1341 //   (select cc -1, y)  [AllOnes=1]
1342 //   (select cc y, -1)  [AllOnes=1]
1343 //
1344 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1345 //   all ones operand (AllOnes true).
1346 // * Invert is set when N is the all zero/ones constant when CC is false.
1347 // * OtherOp is set to the alternative value of N.
1348 //
1349 // For example, for (select cc X, Y) and AllOnes = 0 if:
1350 // * X = 0, Invert = False and OtherOp = Y
1351 // * Y = 0, Invert = True and OtherOp = X
1352 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1353                                        bool &Invert, SDValue &OtherOp,
1354                                        SelectionDAG &DAG) {
1355   switch (N->getOpcode()) {
1356   default:
1357     return false;
1358   case ISD::SELECT: {
1359     CC = N->getOperand(0);
1360     SDValue N1 = N->getOperand(1);
1361     SDValue N2 = N->getOperand(2);
1362     if (isZeroOrAllOnes(N1, AllOnes)) {
1363       Invert = false;
1364       OtherOp = N2;
1365       return true;
1366     }
1367     if (isZeroOrAllOnes(N2, AllOnes)) {
1368       Invert = true;
1369       OtherOp = N1;
1370       return true;
1371     }
1372     return false;
1373   }
1374   case ISD::ZERO_EXTEND: {
1375     // (zext cc) can never be the all ones value.
1376     if (AllOnes)
1377       return false;
1378     CC = N->getOperand(0);
1379     if (CC.getValueType() != MVT::i1)
1380       return false;
1381     SDLoc dl(N);
1382     EVT VT = N->getValueType(0);
1383     OtherOp = DAG.getConstant(1, dl, VT);
1384     Invert = true;
1385     return true;
1386   }
1387   case ISD::SIGN_EXTEND: {
1388     CC = N->getOperand(0);
1389     if (CC.getValueType() != MVT::i1)
1390       return false;
1391     SDLoc dl(N);
1392     EVT VT = N->getValueType(0);
1393     Invert = !AllOnes;
1394     if (AllOnes)
1395       // When looking for an AllOnes constant, N is an sext, and the 'other'
1396       // value is 0.
1397       OtherOp = DAG.getConstant(0, dl, VT);
1398     else
1399       OtherOp = DAG.getAllOnesConstant(dl, VT);
1400     return true;
1401   }
1402   }
1403 }
1404 
1405 // Combine a constant select operand into its use:
1406 //
1407 //   (add (select cc, 0, c), x)  -> (select cc, x, (add, x, c))
1408 //   (sub x, (select cc, 0, c))  -> (select cc, x, (sub, x, c))
1409 //   (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))  [AllOnes=1]
1410 //   (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
1411 //   (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))
1412 //
1413 // The transform is rejected if the select doesn't have a constant operand that
1414 // is null, or all ones when AllOnes is set.
1415 //
1416 // Also recognize sext/zext from i1:
1417 //
1418 //   (add (zext cc), x) -> (select cc (add x, 1), x)
1419 //   (add (sext cc), x) -> (select cc (add x, -1), x)
1420 //
1421 // These transformations eventually create predicated instructions.
1422 static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1423                                    TargetLowering::DAGCombinerInfo &DCI,
1424                                    bool AllOnes) {
1425   SelectionDAG &DAG = DCI.DAG;
1426   EVT VT = N->getValueType(0);
1427   SDValue NonConstantVal;
1428   SDValue CCOp;
1429   bool SwapSelectOps;
1430   if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1431                                   NonConstantVal, DAG))
1432     return SDValue();
1433 
1434   // Slct is now know to be the desired identity constant when CC is true.
1435   SDValue TrueVal = OtherOp;
1436   SDValue FalseVal =
1437       DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1438   // Unless SwapSelectOps says CC should be false.
1439   if (SwapSelectOps)
1440     std::swap(TrueVal, FalseVal);
1441 
1442   return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1443 }
1444 
1445 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1446 static SDValue
1447 combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1448                                bool AllOnes) {
1449   SDValue N0 = N->getOperand(0);
1450   SDValue N1 = N->getOperand(1);
1451   if (N0.getNode()->hasOneUse())
1452     if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1453       return Result;
1454   if (N1.getNode()->hasOneUse())
1455     if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1456       return Result;
1457   return SDValue();
1458 }
1459 
1460 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1461 static SDValue PerformSUBCombine(SDNode *N,
1462                                  TargetLowering::DAGCombinerInfo &DCI) {
1463   SDValue N0 = N->getOperand(0);
1464   SDValue N1 = N->getOperand(1);
1465 
1466   // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1467   if (N1.getNode()->hasOneUse())
1468     if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1469       return Result;
1470 
1471   return SDValue();
1472 }
1473 
1474 SDValue LanaiTargetLowering::PerformDAGCombine(SDNode *N,
1475                                                DAGCombinerInfo &DCI) const {
1476   switch (N->getOpcode()) {
1477   default:
1478     break;
1479   case ISD::ADD:
1480   case ISD::OR:
1481   case ISD::XOR:
1482     return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1483   case ISD::AND:
1484     return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1485   case ISD::SUB:
1486     return PerformSUBCombine(N, DCI);
1487   }
1488 
1489   return SDValue();
1490 }
1491 
1492 void LanaiTargetLowering::computeKnownBitsForTargetNode(
1493     const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1494     const SelectionDAG &DAG, unsigned Depth) const {
1495   unsigned BitWidth = Known.getBitWidth();
1496   switch (Op.getOpcode()) {
1497   default:
1498     break;
1499   case LanaiISD::SETCC:
1500     Known = KnownBits(BitWidth);
1501     Known.Zero.setBits(1, BitWidth);
1502     break;
1503   case LanaiISD::SELECT_CC:
1504     KnownBits Known2;
1505     Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1506     Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
1507     Known = KnownBits::commonBits(Known, Known2);
1508     break;
1509   }
1510 }
1511