1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides Hexagon specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H 14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H 15 16 #include "llvm/MC/MCRegisterInfo.h" 17 #include "llvm/Support/CommandLine.h" 18 #include <cstdint> 19 20 #define Hexagon_POINTER_SIZE 4 21 22 #define Hexagon_PointerSize (Hexagon_POINTER_SIZE) 23 #define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8) 24 #define Hexagon_WordSize Hexagon_PointerSize 25 #define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits 26 27 // allocframe saves LR and FP on stack before allocating 28 // a new stack frame. This takes 8 bytes. 29 #define HEXAGON_LRFP_SIZE 8 30 31 // Normal instruction size (in bytes). 32 #define HEXAGON_INSTR_SIZE 4 33 34 // Maximum number of words and instructions in a packet. 35 #define HEXAGON_PACKET_SIZE 4 36 #define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE) 37 // Minimum number of instructions in an end-loop packet. 38 #define HEXAGON_PACKET_INNER_SIZE 2 39 #define HEXAGON_PACKET_OUTER_SIZE 3 40 // Maximum number of instructions in a packet before shuffling, 41 // including a compound one or a duplex or an extender. 42 #define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3) 43 44 // Name of the global offset table as defined by the Hexagon ABI 45 #define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_" 46 47 namespace llvm { 48 49 struct InstrStage; 50 class FeatureBitset; 51 class MCAsmBackend; 52 class MCCodeEmitter; 53 class MCContext; 54 class MCInstrInfo; 55 class MCObjectTargetWriter; 56 class MCRegisterInfo; 57 class MCSubtargetInfo; 58 class MCTargetOptions; 59 class Target; 60 class Triple; 61 class StringRef; 62 63 extern cl::opt<bool> HexagonDisableCompound; 64 extern cl::opt<bool> HexagonDisableDuplex; 65 extern const InstrStage HexagonStages[]; 66 67 MCInstrInfo *createHexagonMCInstrInfo(); 68 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT); 69 70 namespace Hexagon_MC { 71 StringRef selectHexagonCPU(StringRef CPU); 72 73 FeatureBitset completeHVXFeatures(const FeatureBitset &FB); 74 /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser, 75 /// etc. do not need to go through TargetRegistry. 76 MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, 77 StringRef FS); 78 MCSubtargetInfo const *getArchSubtarget(MCSubtargetInfo const *STI); 79 void addArchSubtarget(MCSubtargetInfo const *STI, 80 StringRef FS); 81 unsigned GetELFFlags(const MCSubtargetInfo &STI); 82 83 llvm::ArrayRef<MCPhysReg> GetVectRegRev(); 84 } 85 86 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, 87 MCContext &MCT); 88 89 MCAsmBackend *createHexagonAsmBackend(const Target &T, 90 const MCSubtargetInfo &STI, 91 const MCRegisterInfo &MRI, 92 const MCTargetOptions &Options); 93 94 std::unique_ptr<MCObjectTargetWriter> 95 createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU); 96 97 unsigned HexagonGetLastSlot(); 98 unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes); 99 100 } // End llvm namespace 101 102 // Define symbolic names for Hexagon registers. This defines a mapping from 103 // register name to register number. 104 // 105 #define GET_REGINFO_ENUM 106 #include "HexagonGenRegisterInfo.inc" 107 108 // Defines symbolic names for the Hexagon instructions. 109 // 110 #define GET_INSTRINFO_ENUM 111 #define GET_INSTRINFO_SCHED_ENUM 112 #define GET_INSTRINFO_MC_HELPER_DECLS 113 #include "HexagonGenInstrInfo.inc" 114 115 #define GET_SUBTARGETINFO_ENUM 116 #include "HexagonGenSubtargetInfo.inc" 117 118 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H 119