1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides Hexagon specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H 14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H 15 16 #include "llvm/Support/CommandLine.h" 17 #include <cstdint> 18 #include <string> 19 20 #define Hexagon_POINTER_SIZE 4 21 22 #define Hexagon_PointerSize (Hexagon_POINTER_SIZE) 23 #define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8) 24 #define Hexagon_WordSize Hexagon_PointerSize 25 #define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits 26 27 // allocframe saves LR and FP on stack before allocating 28 // a new stack frame. This takes 8 bytes. 29 #define HEXAGON_LRFP_SIZE 8 30 31 // Normal instruction size (in bytes). 32 #define HEXAGON_INSTR_SIZE 4 33 34 // Maximum number of words and instructions in a packet. 35 #define HEXAGON_PACKET_SIZE 4 36 #define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE) 37 // Minimum number of instructions in an end-loop packet. 38 #define HEXAGON_PACKET_INNER_SIZE 2 39 #define HEXAGON_PACKET_OUTER_SIZE 3 40 // Maximum number of instructions in a packet before shuffling, 41 // including a compound one or a duplex or an extender. 42 #define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3) 43 44 // Name of the global offset table as defined by the Hexagon ABI 45 #define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_" 46 47 namespace llvm { 48 49 struct InstrItinerary; 50 struct InstrStage; 51 class FeatureBitset; 52 class MCAsmBackend; 53 class MCCodeEmitter; 54 class MCContext; 55 class MCInstrInfo; 56 class MCObjectTargetWriter; 57 class MCRegisterInfo; 58 class MCSubtargetInfo; 59 class MCTargetOptions; 60 class Target; 61 class Triple; 62 class StringRef; 63 class raw_ostream; 64 class raw_pwrite_stream; 65 66 extern cl::opt<bool> HexagonDisableCompound; 67 extern cl::opt<bool> HexagonDisableDuplex; 68 extern const InstrStage HexagonStages[]; 69 70 MCInstrInfo *createHexagonMCInstrInfo(); 71 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT); 72 73 namespace Hexagon_MC { 74 StringRef selectHexagonCPU(StringRef CPU); 75 76 FeatureBitset completeHVXFeatures(const FeatureBitset &FB); 77 /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser, 78 /// etc. do not need to go through TargetRegistry. 79 MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, 80 StringRef FS); 81 unsigned GetELFFlags(const MCSubtargetInfo &STI); 82 } 83 84 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, 85 const MCRegisterInfo &MRI, 86 MCContext &MCT); 87 88 MCAsmBackend *createHexagonAsmBackend(const Target &T, 89 const MCSubtargetInfo &STI, 90 const MCRegisterInfo &MRI, 91 const MCTargetOptions &Options); 92 93 std::unique_ptr<MCObjectTargetWriter> 94 createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU); 95 96 unsigned HexagonGetLastSlot(); 97 98 } // End llvm namespace 99 100 // Define symbolic names for Hexagon registers. This defines a mapping from 101 // register name to register number. 102 // 103 #define GET_REGINFO_ENUM 104 #include "HexagonGenRegisterInfo.inc" 105 106 // Defines symbolic names for the Hexagon instructions. 107 // 108 #define GET_INSTRINFO_ENUM 109 #define GET_INSTRINFO_SCHED_ENUM 110 #include "HexagonGenInstrInfo.inc" 111 112 #define GET_SUBTARGETINFO_ENUM 113 #include "HexagonGenSubtargetInfo.inc" 114 115 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H 116