xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (revision ccb59683b98360afaf5b5bb641a68fea22c68d0b) 
1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/HexagonMCInstrInfo.h"
14 #include "MCTargetDesc/HexagonBaseInfo.h"
15 #include "MCTargetDesc/HexagonMCChecker.h"
16 #include "MCTargetDesc/HexagonMCExpr.h"
17 #include "MCTargetDesc/HexagonMCShuffler.h"
18 #include "MCTargetDesc/HexagonMCTargetDesc.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCInstrItineraries.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/Casting.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <limits>
32 
33 using namespace llvm;
34 
35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const {
36   return Register != Hexagon::NoRegister;
37 }
38 
39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
40                                         MCInst const &Inst)
41     : MCII(MCII), BundleCurrent(Inst.begin() +
42                                 HexagonMCInstrInfo::bundleInstructionsOffset),
43       BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
44 
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
46                                         MCInst const &Inst, std::nullptr_t)
47     : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
48       DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
49 
50 Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
51   if (DuplexCurrent != DuplexEnd) {
52     ++DuplexCurrent;
53     if (DuplexCurrent == DuplexEnd) {
54       DuplexCurrent = BundleEnd;
55       DuplexEnd = BundleEnd;
56       ++BundleCurrent;
57     }
58     return *this;
59   }
60   ++BundleCurrent;
61   if (BundleCurrent != BundleEnd) {
62     MCInst const &Inst = *BundleCurrent->getInst();
63     if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
64       DuplexCurrent = Inst.begin();
65       DuplexEnd = Inst.end();
66     }
67   }
68   return *this;
69 }
70 
71 MCInst const &Hexagon::PacketIterator::operator*() const {
72   if (DuplexCurrent != DuplexEnd)
73     return *DuplexCurrent->getInst();
74   return *BundleCurrent->getInst();
75 }
76 
77 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
78   return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
79          DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
80 }
81 
82 void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
83                                      MCContext &Context) {
84   MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
85 }
86 
87 void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
88                                           MCInstrInfo const &MCII, MCInst &MCB,
89                                           MCInst const &MCI) {
90   assert(HexagonMCInstrInfo::isBundle(MCB));
91   MCOperand const &exOp =
92       MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
93 
94   // Create the extender.
95   MCInst *XMCI =
96       new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
97   XMCI->setLoc(MCI.getLoc());
98 
99   MCB.addOperand(MCOperand::createInst(XMCI));
100 }
101 
102 iterator_range<Hexagon::PacketIterator>
103 HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII,
104                                        MCInst const &MCI) {
105   assert(isBundle(MCI));
106   return make_range(Hexagon::PacketIterator(MCII, MCI),
107                     Hexagon::PacketIterator(MCII, MCI, nullptr));
108 }
109 
110 iterator_range<MCInst::const_iterator>
111 HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
112   assert(isBundle(MCI));
113   return drop_begin(MCI, bundleInstructionsOffset);
114 }
115 
116 size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
117   if (HexagonMCInstrInfo::isBundle(MCI))
118     return (MCI.size() - bundleInstructionsOffset);
119   else
120     return (1);
121 }
122 
123 namespace {
124 bool canonicalizePacketImpl(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
125                             MCContext &Context, MCInst &MCB,
126                             HexagonMCChecker *Check) {
127   // Check the bundle for errors.
128   bool CheckOk = Check ? Check->check(false) : true;
129   if (!CheckOk)
130     return false;
131 
132   MCInst OrigMCB = MCB;
133 
134   // Examine the packet and convert pairs of instructions to compound
135   // instructions when possible.
136   if (!HexagonDisableCompound)
137     HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
138   HexagonMCShuffle(Context, false, MCII, STI, MCB);
139 
140   const SmallVector<DuplexCandidate, 8> possibleDuplexes =
141       (STI.getFeatureBits()[Hexagon::FeatureDuplex])
142           ? HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB)
143           : SmallVector<DuplexCandidate, 8>();
144 
145   // Examine the packet and convert pairs of instructions to duplex
146   // instructions when possible.
147   HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
148 
149   // Examines packet and pad the packet, if needed, when an
150   // end-loop is in the bundle.
151   HexagonMCInstrInfo::padEndloop(MCB, Context);
152 
153   // If compounding and duplexing didn't reduce the size below
154   // 4 or less we have a packet that is too big.
155   if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
156     if (Check)
157       Check->reportError("invalid instruction packet: out of slots");
158     return false;
159   }
160   // Check the bundle for errors.
161   CheckOk = Check ? Check->check(true) : true;
162   if (!CheckOk)
163     return false;
164 
165   HexagonMCShuffle(Context, true, MCII, STI, MCB);
166 
167   return true;
168 }
169 } // namespace
170 
171 bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
172                                             MCSubtargetInfo const &STI,
173                                             MCContext &Context, MCInst &MCB,
174                                             HexagonMCChecker *Check,
175                                             bool AttemptCompatibility) {
176   auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
177   if (!AttemptCompatibility || ArchSTI == nullptr)
178     return canonicalizePacketImpl(MCII, STI, Context, MCB, Check);
179 
180   const MCRegisterInfo *RI = Context.getRegisterInfo();
181   HexagonMCChecker DefaultCheck(Context, MCII, STI, MCB, *RI, false);
182   HexagonMCChecker *BaseCheck = (Check == nullptr) ? &DefaultCheck : Check;
183   HexagonMCChecker PerfCheck(*BaseCheck, STI, false);
184   if (canonicalizePacketImpl(MCII, STI, Context, MCB, &PerfCheck))
185     return true;
186 
187   HexagonMCChecker ArchCheck(*BaseCheck, *ArchSTI, true);
188   return canonicalizePacketImpl(MCII, *ArchSTI, Context, MCB, &ArchCheck);
189 }
190 
191 MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
192                                           MCInst const &Inst,
193                                           MCOperand const &MO) {
194   assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
195          HexagonMCInstrInfo::isExtended(MCII, Inst));
196 
197   MCInst XMI;
198   XMI.setOpcode(Hexagon::A4_ext);
199   if (MO.isImm())
200     XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
201   else if (MO.isExpr())
202     XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
203   else
204     llvm_unreachable("invalid extendable operand");
205   return XMI;
206 }
207 
208 MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
209                                          MCInst const &inst0,
210                                          MCInst const &inst1) {
211   assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
212   MCInst *duplexInst = new (Context) MCInst;
213   duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
214 
215   MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
216   MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
217   duplexInst->addOperand(MCOperand::createInst(SubInst0));
218   duplexInst->addOperand(MCOperand::createInst(SubInst1));
219   return duplexInst;
220 }
221 
222 MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
223                                                    size_t Index) {
224   assert(Index <= bundleSize(MCB));
225   if (Index == 0)
226     return nullptr;
227   MCInst const *Inst =
228       MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
229   if (isImmext(*Inst))
230     return Inst;
231   return nullptr;
232 }
233 
234 void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
235                                         MCInstrInfo const &MCII, MCInst &MCB,
236                                         MCInst const &MCI) {
237   if (isConstExtended(MCII, MCI))
238     addConstExtender(Context, MCII, MCB, MCI);
239 }
240 
241 unsigned HexagonMCInstrInfo::getMemAccessSize(MCInstrInfo const &MCII,
242       MCInst const &MCI) {
243   uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
244   unsigned S = (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
245   return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S));
246 }
247 
248 unsigned HexagonMCInstrInfo::getAddrMode(MCInstrInfo const &MCII,
249                                          MCInst const &MCI) {
250   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
251   return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
252                                HexagonII::AddrModeMask);
253 }
254 
255 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
256                                                MCInst const &MCI) {
257   return MCII.get(MCI.getOpcode());
258 }
259 
260 unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
261   using namespace Hexagon;
262 
263   switch (Reg) {
264   default:
265     llvm_unreachable("unknown duplex register");
266   // Rs       Rss
267   case R0:
268   case D0:
269     return 0;
270   case R1:
271   case D1:
272     return 1;
273   case R2:
274   case D2:
275     return 2;
276   case R3:
277   case D3:
278     return 3;
279   case R4:
280   case D8:
281     return 4;
282   case R5:
283   case D9:
284     return 5;
285   case R6:
286   case D10:
287     return 6;
288   case R7:
289   case D11:
290     return 7;
291   case R16:
292     return 8;
293   case R17:
294     return 9;
295   case R18:
296     return 10;
297   case R19:
298     return 11;
299   case R20:
300     return 12;
301   case R21:
302     return 13;
303   case R22:
304     return 14;
305   case R23:
306     return 15;
307   }
308 }
309 
310 MCExpr const &HexagonMCInstrInfo::getExpr(MCExpr const &Expr) {
311   const auto &HExpr = cast<HexagonMCExpr>(Expr);
312   assert(HExpr.getExpr());
313   return *HExpr.getExpr();
314 }
315 
316 unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
317                                                    MCInst const &MCI) {
318   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
319   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
320 }
321 
322 MCOperand const &
323 HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
324                                          MCInst const &MCI) {
325   unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
326   MCOperand const &MO = MCI.getOperand(O);
327 
328   assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
329           HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
330          (MO.isImm() || MO.isExpr()));
331   return (MO);
332 }
333 
334 unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
335                                                 MCInst const &MCI) {
336   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
337   return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
338 }
339 
340 unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
341                                            MCInst const &MCI) {
342   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
343   return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
344 }
345 
346 bool HexagonMCInstrInfo::isExtentSigned(MCInstrInfo const &MCII,
347                                         MCInst const &MCI) {
348   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
349   return (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
350 }
351 
352 /// Return the maximum value of an extendable operand.
353 int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
354                                     MCInst const &MCI) {
355   assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
356          HexagonMCInstrInfo::isExtended(MCII, MCI));
357 
358   if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
359     return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
360   return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
361 }
362 
363 /// Return the minimum value of an extendable operand.
364 int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
365                                     MCInst const &MCI) {
366   assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
367          HexagonMCInstrInfo::isExtended(MCII, MCI));
368 
369   if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
370     return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
371   return 0;
372 }
373 
374 StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
375                                       MCInst const &MCI) {
376   return MCII.getName(MCI.getOpcode());
377 }
378 
379 unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
380                                                  MCInst const &MCI) {
381   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
382   return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
383 }
384 
385 MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
386                                                         MCInst const &MCI) {
387   if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
388     // VTMP doesn't actually exist in the encodings for these 184
389     // 3 instructions so go ahead and create it here.
390     static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
391     return (MCO);
392   } else {
393     unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
394     MCOperand const &MCO = MCI.getOperand(O);
395 
396     assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
397             HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
398            MCO.isReg());
399     return (MCO);
400   }
401 }
402 
403 /// Return the new value or the newly produced value.
404 unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
405                                                   MCInst const &MCI) {
406   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
407   return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
408 }
409 
410 MCOperand const &
411 HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
412                                         MCInst const &MCI) {
413   unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
414   MCOperand const &MCO = MCI.getOperand(O);
415 
416   assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
417           HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
418          MCO.isReg());
419   return (MCO);
420 }
421 
422 /// Return the Hexagon ISA class for the insn.
423 unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
424                                      MCInst const &MCI) {
425   const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
426   return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
427 }
428 
429 /// Return the resources used by this instruction
430 unsigned HexagonMCInstrInfo::getCVIResources(MCInstrInfo const &MCII,
431                                       MCSubtargetInfo const &STI,
432                                       MCInst const &MCI) {
433 
434   const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
435   int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
436   int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage;
437 
438   // HVX resources used are currenty located at the second to last stage.
439   // This could also be done with a linear search of the stages looking for:
440   // CVI_ALL, CVI_MPY01, CVI_XLSHF, CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE,
441   // CVI_ZW
442   unsigned Stage = II[SchedClass].LastStage - 1;
443 
444   if (Size < 2)
445     return 0;
446   return ((Stage + HexagonStages)->getUnits());
447 }
448 
449 /// Return the slots this instruction can execute out of
450 unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
451                                       MCSubtargetInfo const &STI,
452                                       MCInst const &MCI) {
453   const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
454   int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
455   return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
456 }
457 
458 /// Return the slots this instruction consumes in addition to
459 /// the slot(s) it can execute out of
460 
461 unsigned HexagonMCInstrInfo::getOtherReservedSlots(MCInstrInfo const &MCII,
462                                                    MCSubtargetInfo const &STI,
463                                                    MCInst const &MCI) {
464   const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
465   int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
466   unsigned Slots = 0;
467 
468   // FirstStage are slots that this instruction can execute in.
469   // FirstStage+1 are slots that are also consumed by this instruction.
470   // For example: vmemu can only execute in slot 0 but also consumes slot 1.
471   for (unsigned Stage = II[SchedClass].FirstStage + 1;
472        Stage < II[SchedClass].LastStage; ++Stage) {
473     unsigned Units = (Stage + HexagonStages)->getUnits();
474     if (Units > HexagonGetLastSlot())
475       break;
476     // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
477     Slots |= Units;
478   }
479 
480   // if 0 is returned, then no additional slots are consumed by this inst.
481   return Slots;
482 }
483 
484 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
485   if (!HexagonMCInstrInfo::isBundle(MCI))
486     return false;
487 
488   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
489     if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
490       return true;
491   }
492 
493   return false;
494 }
495 
496 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
497   return extenderForIndex(MCB, Index) != nullptr;
498 }
499 
500 bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
501   if (!HexagonMCInstrInfo::isBundle(MCI))
502     return false;
503 
504   for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
505     if (isImmext(*I.getInst()))
506       return true;
507   }
508 
509   return false;
510 }
511 
512 /// Return whether the insn produces a value.
513 bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
514                                      MCInst const &MCI) {
515   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
516   return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
517 }
518 
519 /// Return whether the insn produces a second value.
520 bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
521                                       MCInst const &MCI) {
522   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
523   return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
524 }
525 
526 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
527   assert(isBundle(MCB));
528   assert(Index < HEXAGON_PRESHUFFLE_PACKET_SIZE);
529   return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
530 }
531 
532 /// Return where the instruction is an accumulator.
533 bool HexagonMCInstrInfo::isAccumulator(MCInstrInfo const &MCII,
534                                        MCInst const &MCI) {
535   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
536   return ((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
537 }
538 
539 bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
540   auto Result = Hexagon::BUNDLE == MCI.getOpcode();
541   assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
542   return Result;
543 }
544 
545 bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
546                                          MCInst const &MCI) {
547   if (HexagonMCInstrInfo::isExtended(MCII, MCI))
548     return true;
549   if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
550     return false;
551   MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
552   if (isa<HexagonMCExpr>(MO.getExpr()) &&
553       HexagonMCInstrInfo::mustExtend(*MO.getExpr()))
554     return true;
555   // Branch insns are handled as necessary by relaxation.
556   if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
557       (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ &&
558        HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
559       (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ &&
560        HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
561     return false;
562   // Otherwise loop instructions and other CR insts are handled by relaxation
563   else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
564            (MCI.getOpcode() != Hexagon::C4_addipc))
565     return false;
566 
567   assert(!MO.isImm());
568   if (isa<HexagonMCExpr>(MO.getExpr()) &&
569       HexagonMCInstrInfo::mustNotExtend(*MO.getExpr()))
570     return false;
571   int64_t Value;
572   if (!MO.getExpr()->evaluateAsAbsolute(Value))
573     return true;
574   int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
575   int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
576   return (MinValue > Value || Value > MaxValue);
577 }
578 
579 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
580   return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
581          !HexagonMCInstrInfo::isPrefix(MCII, MCI);
582 }
583 
584 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
585   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
586   return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask);
587 }
588 
589 bool HexagonMCInstrInfo::isCofRelax1(MCInstrInfo const &MCII,
590                                      MCInst const &MCI) {
591   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
592   return ((F >> HexagonII::CofRelax1Pos) & HexagonII::CofRelax1Mask);
593 }
594 
595 bool HexagonMCInstrInfo::isCofRelax2(MCInstrInfo const &MCII,
596                                      MCInst const &MCI) {
597   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
598   return ((F >> HexagonII::CofRelax2Pos) & HexagonII::CofRelax2Mask);
599 }
600 
601 bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
602                                     MCInst const &MCI) {
603   return (getType(MCII, MCI) == HexagonII::TypeCJ);
604 }
605 
606 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
607   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
608   return ((F >> HexagonII::CVINewPos) & HexagonII::CVINewMask);
609 }
610 
611 bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
612   return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
613           (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
614 }
615 
616 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
617   return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
618 }
619 
620 bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
621                                       MCInst const &MCI) {
622   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
623   return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
624 }
625 
626 bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
627                                     MCInst const &MCI) {
628   uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
629   return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
630 }
631 
632 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
633   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
634   return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
635 }
636 
637 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
638   const uint64_t V = getType(MCII, MCI);
639   return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
640 }
641 
642 bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
643   return MCI.getOpcode() == Hexagon::A4_ext;
644 }
645 
646 bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
647   assert(isBundle(MCI));
648   int64_t Flags = MCI.getOperand(0).getImm();
649   return (Flags & innerLoopMask) != 0;
650 }
651 
652 bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
653   return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
654 }
655 
656 bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
657   return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
658           (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
659 }
660 
661 /// Return whether the insn expects newly produced value.
662 bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
663                                     MCInst const &MCI) {
664   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
665   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
666 }
667 
668 bool HexagonMCInstrInfo::isNewValueStore(MCInstrInfo const &MCII,
669                                          MCInst const &MCI) {
670   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
671   return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
672 }
673 
674 /// Return whether the operand is extendable.
675 bool HexagonMCInstrInfo::isOpExtendable(MCInstrInfo const &MCII,
676                                         MCInst const &MCI, unsigned short O) {
677   return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
678 }
679 
680 bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
681   assert(isBundle(MCI));
682   int64_t Flags = MCI.getOperand(0).getImm();
683   return (Flags & outerLoopMask) != 0;
684 }
685 
686 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) {
687   return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
688          (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
689 }
690 
691 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) {
692   return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
693 }
694 
695 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) {
696   return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
697 }
698 
699 std::pair<unsigned, unsigned>
700 HexagonMCInstrInfo::GetVecRegPairIndices(unsigned VecRegPair) {
701   assert(IsVecRegPair(VecRegPair) &&
702          "VecRegPair must be a vector register pair");
703 
704   const bool IsRev = IsReverseVecRegPair(VecRegPair);
705   const unsigned PairIndex =
706       2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
707 
708   return IsRev ? std::make_pair(PairIndex, PairIndex + 1)
709                : std::make_pair(PairIndex + 1, PairIndex);
710 }
711 
712 bool HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(unsigned Producer,
713                                                          unsigned Consumer) {
714   if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
715     const unsigned ProdPairIndex = IsReverseVecRegPair(Producer)
716                                        ? Producer - Hexagon::WR0
717                                        : Producer - Hexagon::W0;
718     const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;
719 
720     return ConsumerSingleIndex == ProdPairIndex;
721   }
722   return false;
723 }
724 
725 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
726                                       MCInst const &MCI) {
727   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
728   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
729 }
730 
731 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
732   return HexagonII::TypeEXTENDER == HexagonMCInstrInfo::getType(MCII, MCI);
733 }
734 
735 bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
736                                          MCInst const &MCI) {
737   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
738   return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
739 }
740 
741 /// Return whether the insn is newly predicated.
742 bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
743                                          MCInst const &MCI) {
744   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
745   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
746 }
747 
748 bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
749                                           MCInst const &MCI) {
750   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
751   return (
752       !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
753 }
754 
755 bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MRI, unsigned Reg) {
756   auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);
757   return PredRegClass.contains(Reg);
758 }
759 
760 bool HexagonMCInstrInfo::isPredRegister(MCInstrInfo const &MCII,
761                                         MCInst const &Inst, unsigned I) {
762   MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
763 
764   return Inst.getOperand(I).isReg() &&
765          Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID;
766 }
767 
768 /// Return whether the insn can be packaged only with A and X-type insns.
769 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
770   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
771   return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
772 }
773 
774 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
775 bool HexagonMCInstrInfo::isRestrictSlot1AOK(MCInstrInfo const &MCII,
776                                             MCInst const &MCI) {
777   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
778   return ((F >> HexagonII::RestrictSlot1AOKPos) &
779           HexagonII::RestrictSlot1AOKMask);
780 }
781 
782 bool HexagonMCInstrInfo::isRestrictNoSlot1Store(MCInstrInfo const &MCII,
783                                                 MCInst const &MCI) {
784   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
785   return ((F >> HexagonII::RestrictNoSlot1StorePos) &
786           HexagonII::RestrictNoSlot1StoreMask);
787 }
788 
789 /// Return whether the insn is solo, i.e., cannot be in a packet.
790 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
791   const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
792   return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
793 }
794 
795 bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
796   assert(isBundle(MCI));
797   auto Flags = MCI.getOperand(0).getImm();
798   return (Flags & memReorderDisabledMask) != 0;
799 }
800 
801 bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
802   switch (MCI.getOpcode()) {
803   default:
804     return false;
805   case Hexagon::SA1_addi:
806   case Hexagon::SA1_addrx:
807   case Hexagon::SA1_addsp:
808   case Hexagon::SA1_and1:
809   case Hexagon::SA1_clrf:
810   case Hexagon::SA1_clrfnew:
811   case Hexagon::SA1_clrt:
812   case Hexagon::SA1_clrtnew:
813   case Hexagon::SA1_cmpeqi:
814   case Hexagon::SA1_combine0i:
815   case Hexagon::SA1_combine1i:
816   case Hexagon::SA1_combine2i:
817   case Hexagon::SA1_combine3i:
818   case Hexagon::SA1_combinerz:
819   case Hexagon::SA1_combinezr:
820   case Hexagon::SA1_dec:
821   case Hexagon::SA1_inc:
822   case Hexagon::SA1_seti:
823   case Hexagon::SA1_setin1:
824   case Hexagon::SA1_sxtb:
825   case Hexagon::SA1_sxth:
826   case Hexagon::SA1_tfr:
827   case Hexagon::SA1_zxtb:
828   case Hexagon::SA1_zxth:
829   case Hexagon::SL1_loadri_io:
830   case Hexagon::SL1_loadrub_io:
831   case Hexagon::SL2_deallocframe:
832   case Hexagon::SL2_jumpr31:
833   case Hexagon::SL2_jumpr31_f:
834   case Hexagon::SL2_jumpr31_fnew:
835   case Hexagon::SL2_jumpr31_t:
836   case Hexagon::SL2_jumpr31_tnew:
837   case Hexagon::SL2_loadrb_io:
838   case Hexagon::SL2_loadrd_sp:
839   case Hexagon::SL2_loadrh_io:
840   case Hexagon::SL2_loadri_sp:
841   case Hexagon::SL2_loadruh_io:
842   case Hexagon::SL2_return:
843   case Hexagon::SL2_return_f:
844   case Hexagon::SL2_return_fnew:
845   case Hexagon::SL2_return_t:
846   case Hexagon::SL2_return_tnew:
847   case Hexagon::SS1_storeb_io:
848   case Hexagon::SS1_storew_io:
849   case Hexagon::SS2_allocframe:
850   case Hexagon::SS2_storebi0:
851   case Hexagon::SS2_storebi1:
852   case Hexagon::SS2_stored_sp:
853   case Hexagon::SS2_storeh_io:
854   case Hexagon::SS2_storew_sp:
855   case Hexagon::SS2_storewi0:
856   case Hexagon::SS2_storewi1:
857     return true;
858   }
859 }
860 
861 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
862   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
863   return (F >> HexagonII::isCVIPos) & HexagonII::isCVIMask;
864 }
865 
866 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
867   auto Sentinel = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
868                   << 8;
869   if (MCI.size() <= Index)
870     return Sentinel;
871   MCOperand const &MCO = MCI.getOperand(Index);
872   if (!MCO.isExpr())
873     return Sentinel;
874   int64_t Value;
875   if (!MCO.getExpr()->evaluateAsAbsolute(Value))
876     return Sentinel;
877   return Value;
878 }
879 
880 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
881   HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
882   HExpr.setMustExtend(Val);
883 }
884 
885 bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) {
886   HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
887   return HExpr.mustExtend();
888 }
889 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
890   HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
891   HExpr.setMustNotExtend(Val);
892 }
893 bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
894   HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
895   return HExpr.mustNotExtend();
896 }
897 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
898   HexagonMCExpr &HExpr =
899       const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
900   HExpr.setS27_2_reloc(Val);
901 }
902 bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) {
903   HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
904   if (!HExpr)
905     return false;
906   return HExpr->s27_2_reloc();
907 }
908 
909 unsigned HexagonMCInstrInfo::packetSizeSlots(MCSubtargetInfo const &STI) {
910   const bool IsTiny = STI.getFeatureBits()[Hexagon::ProcTinyCore];
911 
912   return IsTiny ? (HEXAGON_PACKET_SIZE - 1) : HEXAGON_PACKET_SIZE;
913 }
914 
915 unsigned HexagonMCInstrInfo::packetSize(StringRef CPU) {
916   return llvm::StringSwitch<unsigned>(CPU)
917       .Case("hexagonv67t", 3)
918       .Default(4);
919 }
920 
921 void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) {
922   MCInst Nop;
923   Nop.setOpcode(Hexagon::A2_nop);
924   assert(isBundle(MCB));
925   while (LoopNeedsPadding(MCB))
926     MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
927 }
928 
929 HexagonMCInstrInfo::PredicateInfo
930 HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) {
931   if (!isPredicated(MCII, MCI))
932     return {0, 0, false};
933   MCInstrDesc const &Desc = getDesc(MCII, MCI);
934   for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
935     if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
936       return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
937   return {0, 0, false};
938 }
939 
940 bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
941                                       MCInst const &MCI) {
942   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
943   return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;
944 }
945 
946 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
947   switch (MCI.getOpcode()) {
948   default:
949     return false;
950   case Hexagon::V6_vgathermh:
951   case Hexagon::V6_vgathermhq:
952   case Hexagon::V6_vgathermhw:
953   case Hexagon::V6_vgathermhwq:
954   case Hexagon::V6_vgathermw:
955   case Hexagon::V6_vgathermwq:
956     return true;
957   }
958   return false;
959 }
960 
961 bool HexagonMCInstrInfo::hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI) {
962   const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
963   return (F >> HexagonII::HasHvxTmpPos) & HexagonII::HasHvxTmpMask;
964 }
965 
966 bool HexagonMCInstrInfo::requiresSlot(MCSubtargetInfo const &STI,
967                                       MCInst const &MCI) {
968   const unsigned OpCode = MCI.getOpcode();
969   const bool IsTiny = STI.getFeatureBits() [Hexagon::ProcTinyCore];
970   const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
971                           (IsTiny && Hexagon::A2_nop == OpCode) ||
972                           (IsTiny && Hexagon::J4_hintjumpr == OpCode);
973 
974   return !NoSlotReqd;
975 }
976 
977 unsigned HexagonMCInstrInfo::slotsConsumed(MCInstrInfo const &MCII,
978                                            MCSubtargetInfo const &STI,
979                                            MCInst const &MCI) {
980   unsigned slotsUsed = 0;
981   for (auto HMI : bundleInstructions(MCI)) {
982     MCInst const &MCI = *HMI.getInst();
983     if (!requiresSlot(STI, MCI))
984       continue;
985     if (isDuplex(MCII, MCI))
986       slotsUsed += 2;
987     else
988       ++slotsUsed;
989   }
990   return slotsUsed;
991 }
992 
993 void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
994                                        DuplexCandidate Candidate) {
995   assert(Candidate.packetIndexI < MCB.size());
996   assert(Candidate.packetIndexJ < MCB.size());
997   assert(isBundle(MCB));
998   MCInst *Duplex =
999       deriveDuplex(Context, Candidate.iClass,
1000                    *MCB.getOperand(Candidate.packetIndexJ).getInst(),
1001                    *MCB.getOperand(Candidate.packetIndexI).getInst());
1002   assert(Duplex != nullptr);
1003   MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
1004   MCB.erase(MCB.begin() + Candidate.packetIndexJ);
1005 }
1006 
1007 void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
1008   assert(isBundle(MCI));
1009   MCOperand &Operand = MCI.getOperand(0);
1010   Operand.setImm(Operand.getImm() | innerLoopMask);
1011 }
1012 
1013 void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
1014   assert(isBundle(MCI));
1015   MCOperand &Operand = MCI.getOperand(0);
1016   Operand.setImm(Operand.getImm() | memReorderDisabledMask);
1017   assert(isMemReorderDisabled(MCI));
1018 }
1019 
1020 void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
1021   assert(isBundle(MCI));
1022   MCOperand &Operand = MCI.getOperand(0);
1023   Operand.setImm(Operand.getImm() | outerLoopMask);
1024 }
1025 
1026 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
1027                                             unsigned Producer,
1028                                             unsigned Producer2) {
1029   // If we're a single vector consumer of a double producer, set subreg bit
1030   // based on if we're accessing the lower or upper register component
1031   if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
1032     return (Consumer - Hexagon::V0) & 0x1;
1033   if (Producer2 != Hexagon::NoRegister)
1034     return Consumer == Producer;
1035   return 0;
1036 }
1037 
1038 bool HexagonMCInstrInfo::LoopNeedsPadding(MCInst const &MCB) {
1039   return (
1040       (HexagonMCInstrInfo::isInnerLoop(MCB) &&
1041        (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE)) ||
1042       ((HexagonMCInstrInfo::isOuterLoop(MCB) &&
1043         (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE))));
1044 }
1045 
1046 bool HexagonMCInstrInfo::IsABranchingInst(MCInstrInfo const &MCII,
1047                                           MCSubtargetInfo const &STI,
1048                                           MCInst const &I) {
1049   assert(!HexagonMCInstrInfo::isBundle(I));
1050   MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
1051   return (Desc.isBranch() || Desc.isCall() || Desc.isReturn());
1052 }
1053