10b57cec5SDimitry Andric //===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric /// 90b57cec5SDimitry Andric /// \file 100b57cec5SDimitry Andric /// Definition for classes that emit Hexagon machine code from MCInsts 110b57cec5SDimitry Andric /// 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "MCTargetDesc/HexagonFixupKinds.h" 180b57cec5SDimitry Andric #include "llvm/MC/MCCodeEmitter.h" 190b57cec5SDimitry Andric #include "llvm/MC/MCExpr.h" 20*06c3fb27SDimitry Andric #include "llvm/TargetParser/SubtargetFeature.h" 210b57cec5SDimitry Andric #include <cstddef> 220b57cec5SDimitry Andric #include <cstdint> 230b57cec5SDimitry Andric #include <memory> 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric namespace llvm { 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric class MCContext; 280b57cec5SDimitry Andric class MCInst; 290b57cec5SDimitry Andric class MCInstrInfo; 300b57cec5SDimitry Andric class MCOperand; 310b57cec5SDimitry Andric class MCSubtargetInfo; 320b57cec5SDimitry Andric class raw_ostream; 330b57cec5SDimitry Andric 340b57cec5SDimitry Andric class HexagonMCCodeEmitter : public MCCodeEmitter { 350b57cec5SDimitry Andric MCContext &MCT; 360b57cec5SDimitry Andric MCInstrInfo const &MCII; 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric // A mutable state of the emitter when encoding bundles and duplexes. 390b57cec5SDimitry Andric struct EmitterState { 400b57cec5SDimitry Andric unsigned Addend = 0; 410b57cec5SDimitry Andric bool Extended = false; 420b57cec5SDimitry Andric bool SubInst1 = false; 430b57cec5SDimitry Andric const MCInst *Bundle = nullptr; 440b57cec5SDimitry Andric size_t Index = 0; 450b57cec5SDimitry Andric }; 460b57cec5SDimitry Andric mutable EmitterState State; 470b57cec5SDimitry Andric 480b57cec5SDimitry Andric public: HexagonMCCodeEmitter(MCInstrInfo const & MII,MCContext & MCT)490b57cec5SDimitry Andric HexagonMCCodeEmitter(MCInstrInfo const &MII, MCContext &MCT) 500b57cec5SDimitry Andric : MCT(MCT), MCII(MII) {} 510b57cec5SDimitry Andric 52*06c3fb27SDimitry Andric void encodeInstruction(MCInst const &MI, SmallVectorImpl<char> &CB, 530b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 540b57cec5SDimitry Andric MCSubtargetInfo const &STI) const override; 550b57cec5SDimitry Andric 56*06c3fb27SDimitry Andric void encodeSingleInstruction(const MCInst &MI, SmallVectorImpl<char> &CB, 570b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 580b57cec5SDimitry Andric const MCSubtargetInfo &STI, 590b57cec5SDimitry Andric uint32_t Parse) const; 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric // TableGen'erated function for getting the 620b57cec5SDimitry Andric // binary encoding for an instruction. 630b57cec5SDimitry Andric uint64_t getBinaryCodeForInstr(MCInst const &MI, 640b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 650b57cec5SDimitry Andric MCSubtargetInfo const &STI) const; 660b57cec5SDimitry Andric 670b57cec5SDimitry Andric /// Return binary encoding of operand. 680b57cec5SDimitry Andric unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, 690b57cec5SDimitry Andric SmallVectorImpl<MCFixup> &Fixups, 700b57cec5SDimitry Andric MCSubtargetInfo const &STI) const; 710b57cec5SDimitry Andric 720b57cec5SDimitry Andric private: 730b57cec5SDimitry Andric // helper routine for getMachineOpValue() 740b57cec5SDimitry Andric unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO, 750b57cec5SDimitry Andric const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups, 760b57cec5SDimitry Andric const MCSubtargetInfo &STI) const; 770b57cec5SDimitry Andric 780b57cec5SDimitry Andric Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, 790b57cec5SDimitry Andric const MCOperand &MO, 800b57cec5SDimitry Andric const MCSymbolRefExpr::VariantKind Kind) const; 810b57cec5SDimitry Andric 820b57cec5SDimitry Andric // Return parse bits for instruction `MCI' inside bundle `MCB' 830b57cec5SDimitry Andric uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const; 840b57cec5SDimitry Andric }; 850b57cec5SDimitry Andric 860b57cec5SDimitry Andric } // end namespace llvm 870b57cec5SDimitry Andric 880b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H 89