1 //===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the Hexagon target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 17 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 18 19 #include "HexagonDepITypes.h" 20 #include "MCTargetDesc/HexagonMCTargetDesc.h" 21 22 namespace llvm { 23 24 /// HexagonII - This namespace holds all of the target specific flags that 25 /// instruction info tracks. 26 namespace HexagonII { 27 unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY; 28 unsigned const TypeCVI_LAST = TypeCVI_ZW; 29 30 enum SubTarget { 31 HasV55SubT = 0x3c, 32 HasV60SubT = 0x38, 33 }; 34 35 enum AddrMode { 36 NoAddrMode = 0, // No addressing mode 37 Absolute = 1, // Absolute addressing mode 38 AbsoluteSet = 2, // Absolute set addressing mode 39 BaseImmOffset = 3, // Indirect with offset 40 BaseLongOffset = 4, // Indirect with long offset 41 BaseRegOffset = 5, // Indirect with register offset 42 PostInc = 6 // Post increment addressing mode 43 }; 44 45 enum MemAccessSize { 46 NoMemAccess = 0, 47 ByteAccess, 48 HalfWordAccess, 49 WordAccess, 50 DoubleWordAccess, 51 HVXVectorAccess 52 }; 53 54 // MCInstrDesc TSFlags 55 // *** Must match HexagonInstrFormat*.td *** 56 enum { 57 // This 7-bit field describes the insn type. 58 TypePos = 0, 59 TypeMask = 0x7f, 60 61 // Solo instructions. 62 SoloPos = 7, 63 SoloMask = 0x1, 64 // Packed only with A or X-type instructions. 65 SoloAXPos = 8, 66 SoloAXMask = 0x1, 67 // Only A-type instruction in first slot or nothing. 68 RestrictSlot1AOKPos = 9, 69 RestrictSlot1AOKMask = 0x1, 70 71 // Predicated instructions. 72 PredicatedPos = 10, 73 PredicatedMask = 0x1, 74 PredicatedFalsePos = 11, 75 PredicatedFalseMask = 0x1, 76 PredicatedNewPos = 12, 77 PredicatedNewMask = 0x1, 78 PredicateLatePos = 13, 79 PredicateLateMask = 0x1, 80 81 // New-Value consumer instructions. 82 NewValuePos = 14, 83 NewValueMask = 0x1, 84 // New-Value producer instructions. 85 hasNewValuePos = 15, 86 hasNewValueMask = 0x1, 87 // Which operand consumes or produces a new value. 88 NewValueOpPos = 16, 89 NewValueOpMask = 0x7, 90 // Stores that can become new-value stores. 91 mayNVStorePos = 19, 92 mayNVStoreMask = 0x1, 93 // New-value store instructions. 94 NVStorePos = 20, 95 NVStoreMask = 0x1, 96 // Loads that can become current-value loads. 97 mayCVLoadPos = 21, 98 mayCVLoadMask = 0x1, 99 // Current-value load instructions. 100 CVLoadPos = 22, 101 CVLoadMask = 0x1, 102 103 // Extendable insns. 104 ExtendablePos = 23, 105 ExtendableMask = 0x1, 106 // Insns must be extended. 107 ExtendedPos = 24, 108 ExtendedMask = 0x1, 109 // Which operand may be extended. 110 ExtendableOpPos = 25, 111 ExtendableOpMask = 0x7, 112 // Signed or unsigned range. 113 ExtentSignedPos = 28, 114 ExtentSignedMask = 0x1, 115 // Number of bits of range before extending operand. 116 ExtentBitsPos = 29, 117 ExtentBitsMask = 0x1f, 118 // Alignment power-of-two before extending operand. 119 ExtentAlignPos = 34, 120 ExtentAlignMask = 0x3, 121 122 CofMax1Pos = 36, 123 CofMax1Mask = 0x1, 124 CofRelax1Pos = 37, 125 CofRelax1Mask = 0x1, 126 CofRelax2Pos = 38, 127 CofRelax2Mask = 0x1, 128 129 RestrictNoSlot1StorePos = 39, 130 RestrictNoSlot1StoreMask = 0x1, 131 132 // Addressing mode for load/store instructions. 133 AddrModePos = 42, 134 AddrModeMask = 0x7, 135 // Access size for load/store instructions. 136 MemAccessSizePos = 45, 137 MemAccesSizeMask = 0xf, 138 139 // Branch predicted taken. 140 TakenPos = 49, 141 TakenMask = 0x1, 142 143 // Floating-point instructions. 144 FPPos = 50, 145 FPMask = 0x1, 146 147 // New-Value producer-2 instructions. 148 hasNewValuePos2 = 52, 149 hasNewValueMask2 = 0x1, 150 // Which operand consumes or produces a new value. 151 NewValueOpPos2 = 53, 152 NewValueOpMask2 = 0x7, 153 154 // Accumulator instructions. 155 AccumulatorPos = 56, 156 AccumulatorMask = 0x1, 157 158 // Complex XU, prevent xu competition by preferring slot3 159 PrefersSlot3Pos = 57, 160 PrefersSlot3Mask = 0x1, 161 162 // v65 163 HasTmpDstPos = 60, 164 HasTmpDstMask = 0x1, 165 166 CVINewPos = 62, 167 CVINewMask = 0x1, 168 }; 169 170 // *** The code above must match HexagonInstrFormat*.td *** // 171 172 // Hexagon specific MO operand flag mask. 173 enum HexagonMOTargetFlagVal { 174 // Hexagon-specific MachineOperand target flags. 175 // 176 // When changing these, make sure to update 177 // getSerializableDirectMachineOperandTargetFlags and 178 // getSerializableBitmaskMachineOperandTargetFlags if needed. 179 MO_NO_FLAG, 180 181 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation 182 /// Used for computing a global address for PIC compilations 183 MO_PCREL, 184 185 /// MO_GOT - Indicates a GOT-relative relocation 186 MO_GOT, 187 188 // Low or high part of a symbol. 189 MO_LO16, 190 MO_HI16, 191 192 // Offset from the base of the SDA. 193 MO_GPREL, 194 195 // MO_GDGOT - indicates GOT relative relocation for TLS 196 // GeneralDynamic method 197 MO_GDGOT, 198 199 // MO_GDPLT - indicates PLT relative relocation for TLS 200 // GeneralDynamic method 201 MO_GDPLT, 202 203 // MO_IE - indicates non PIC relocation for TLS 204 // Initial Executable method 205 MO_IE, 206 207 // MO_IEGOT - indicates PIC relocation for TLS 208 // Initial Executable method 209 MO_IEGOT, 210 211 // MO_TPREL - indicates relocation for TLS 212 // local Executable method 213 MO_TPREL, 214 215 // HMOTF_ConstExtended 216 // Addendum to above, indicates a const extended op 217 // Can be used as a mask. 218 HMOTF_ConstExtended = 0x80, 219 220 // Union of all bitmasks (currently only HMOTF_ConstExtended). 221 MO_Bitmasks = HMOTF_ConstExtended 222 }; 223 224 // Hexagon Sub-instruction classes. 225 enum SubInstructionGroup { 226 HSIG_None = 0, 227 HSIG_L1, 228 HSIG_L2, 229 HSIG_S1, 230 HSIG_S2, 231 HSIG_A, 232 HSIG_Compound 233 }; 234 235 // Hexagon Compound classes. 236 enum CompoundGroup { 237 HCG_None = 0, 238 HCG_A, 239 HCG_B, 240 HCG_C 241 }; 242 243 enum InstParseBits { 244 INST_PARSE_MASK = 0x0000c000, 245 INST_PARSE_PACKET_END = 0x0000c000, 246 INST_PARSE_LOOP_END = 0x00008000, 247 INST_PARSE_NOT_END = 0x00004000, 248 INST_PARSE_DUPLEX = 0x00000000, 249 INST_PARSE_EXTENDER = 0x00000000 250 }; 251 252 enum InstIClassBits : unsigned { 253 INST_ICLASS_MASK = 0xf0000000, 254 INST_ICLASS_EXTENDER = 0x00000000, 255 INST_ICLASS_J_1 = 0x10000000, 256 INST_ICLASS_J_2 = 0x20000000, 257 INST_ICLASS_LD_ST_1 = 0x30000000, 258 INST_ICLASS_LD_ST_2 = 0x40000000, 259 INST_ICLASS_J_3 = 0x50000000, 260 INST_ICLASS_CR = 0x60000000, 261 INST_ICLASS_ALU32_1 = 0x70000000, 262 INST_ICLASS_XTYPE_1 = 0x80000000, 263 INST_ICLASS_LD = 0x90000000, 264 INST_ICLASS_ST = 0xa0000000, 265 INST_ICLASS_ALU32_2 = 0xb0000000, 266 INST_ICLASS_XTYPE_2 = 0xc0000000, 267 INST_ICLASS_XTYPE_3 = 0xd0000000, 268 INST_ICLASS_XTYPE_4 = 0xe0000000, 269 INST_ICLASS_ALU32_3 = 0xf0000000 270 }; 271 272 LLVM_ATTRIBUTE_UNUSED 273 static unsigned getMemAccessSizeInBytes(MemAccessSize S) { 274 switch (S) { 275 case ByteAccess: return 1; 276 case HalfWordAccess: return 2; 277 case WordAccess: return 4; 278 case DoubleWordAccess: return 8; 279 default: return 0; 280 } 281 } 282 } // end namespace HexagonII 283 284 } // end namespace llvm 285 286 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 287