xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (revision 7ef62cebc2f965b0f640263e179276928885e33d)
1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "HexagonFixupKinds.h"
10 #include "MCTargetDesc/HexagonBaseInfo.h"
11 #include "MCTargetDesc/HexagonMCChecker.h"
12 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
13 #include "MCTargetDesc/HexagonMCInstrInfo.h"
14 #include "MCTargetDesc/HexagonMCShuffler.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "llvm/MC/MCAsmBackend.h"
17 #include "llvm/MC/MCAsmLayout.h"
18 #include "llvm/MC/MCAssembler.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCELFObjectWriter.h"
21 #include "llvm/MC/MCFixupKindInfo.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/TargetRegistry.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/EndianStream.h"
28 
29 #include <sstream>
30 
31 using namespace llvm;
32 using namespace Hexagon;
33 
34 #define DEBUG_TYPE "hexagon-asm-backend"
35 
36 static cl::opt<bool> DisableFixup
37   ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
38 
39 namespace {
40 
41 class HexagonAsmBackend : public MCAsmBackend {
42   uint8_t OSABI;
43   StringRef CPU;
44   mutable uint64_t relaxedCnt;
45   std::unique_ptr <MCInstrInfo> MCII;
46   std::unique_ptr <MCInst *> RelaxTarget;
47   MCInst * Extender;
48   unsigned MaxPacketSize;
49 
50   void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
51                           MCInst &HMB) const {
52     SmallVector<MCFixup, 4> Fixups;
53     SmallString<256> Code;
54     raw_svector_ostream VecOS(Code);
55     E.encodeInstruction(HMB, VecOS, Fixups, *RF.getSubtargetInfo());
56 
57     // Update the fragment.
58     RF.setInst(HMB);
59     RF.getContents() = Code;
60     RF.getFixups() = Fixups;
61   }
62 
63 public:
64   HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
65                     StringRef CPU)
66       : MCAsmBackend(support::little), OSABI(OSABI), CPU(CPU), relaxedCnt(0),
67         MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
68         Extender(nullptr), MaxPacketSize(HexagonMCInstrInfo::packetSize(CPU))
69         {}
70 
71   std::unique_ptr<MCObjectTargetWriter>
72   createObjectTargetWriter() const override {
73     return createHexagonELFObjectWriter(OSABI, CPU);
74   }
75 
76   void setExtender(MCContext &Context) const {
77     if (Extender == nullptr)
78       const_cast<HexagonAsmBackend *>(this)->Extender = Context.createMCInst();
79   }
80 
81   MCInst *takeExtender() const {
82     assert(Extender != nullptr);
83     MCInst * Result = Extender;
84     const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
85     return Result;
86   }
87 
88   unsigned getNumFixupKinds() const override {
89     return Hexagon::NumTargetFixupKinds;
90   }
91 
92   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
93     const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
94       // This table *must* be in same the order of fixup_* kinds in
95       // HexagonFixupKinds.h.
96       //
97       // namei                          offset  bits    flags
98       { "fixup_Hexagon_B22_PCREL",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
99       { "fixup_Hexagon_B15_PCREL",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
100       { "fixup_Hexagon_B7_PCREL",       0,      32,     MCFixupKindInfo::FKF_IsPCRel },
101       { "fixup_Hexagon_LO16",           0,      32,     0 },
102       { "fixup_Hexagon_HI16",           0,      32,     0 },
103       { "fixup_Hexagon_32",             0,      32,     0 },
104       { "fixup_Hexagon_16",             0,      32,     0 },
105       { "fixup_Hexagon_8",              0,      32,     0 },
106       { "fixup_Hexagon_GPREL16_0",      0,      32,     0 },
107       { "fixup_Hexagon_GPREL16_1",      0,      32,     0 },
108       { "fixup_Hexagon_GPREL16_2",      0,      32,     0 },
109       { "fixup_Hexagon_GPREL16_3",      0,      32,     0 },
110       { "fixup_Hexagon_HL16",           0,      32,     0 },
111       { "fixup_Hexagon_B13_PCREL",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
112       { "fixup_Hexagon_B9_PCREL",       0,      32,     MCFixupKindInfo::FKF_IsPCRel },
113       { "fixup_Hexagon_B32_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
114       { "fixup_Hexagon_32_6_X",         0,      32,     0 },
115       { "fixup_Hexagon_B22_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
116       { "fixup_Hexagon_B15_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
117       { "fixup_Hexagon_B13_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
118       { "fixup_Hexagon_B9_PCREL_X",     0,      32,     MCFixupKindInfo::FKF_IsPCRel },
119       { "fixup_Hexagon_B7_PCREL_X",     0,      32,     MCFixupKindInfo::FKF_IsPCRel },
120       { "fixup_Hexagon_16_X",           0,      32,     0 },
121       { "fixup_Hexagon_12_X",           0,      32,     0 },
122       { "fixup_Hexagon_11_X",           0,      32,     0 },
123       { "fixup_Hexagon_10_X",           0,      32,     0 },
124       { "fixup_Hexagon_9_X",            0,      32,     0 },
125       { "fixup_Hexagon_8_X",            0,      32,     0 },
126       { "fixup_Hexagon_7_X",            0,      32,     0 },
127       { "fixup_Hexagon_6_X",            0,      32,     0 },
128       { "fixup_Hexagon_32_PCREL",       0,      32,     MCFixupKindInfo::FKF_IsPCRel },
129       { "fixup_Hexagon_COPY",           0,      32,     0 },
130       { "fixup_Hexagon_GLOB_DAT",       0,      32,     0 },
131       { "fixup_Hexagon_JMP_SLOT",       0,      32,     0 },
132       { "fixup_Hexagon_RELATIVE",       0,      32,     0 },
133       { "fixup_Hexagon_PLT_B22_PCREL",  0,      32,     MCFixupKindInfo::FKF_IsPCRel },
134       { "fixup_Hexagon_GOTREL_LO16",    0,      32,     0 },
135       { "fixup_Hexagon_GOTREL_HI16",    0,      32,     0 },
136       { "fixup_Hexagon_GOTREL_32",      0,      32,     0 },
137       { "fixup_Hexagon_GOT_LO16",       0,      32,     0 },
138       { "fixup_Hexagon_GOT_HI16",       0,      32,     0 },
139       { "fixup_Hexagon_GOT_32",         0,      32,     0 },
140       { "fixup_Hexagon_GOT_16",         0,      32,     0 },
141       { "fixup_Hexagon_DTPMOD_32",      0,      32,     0 },
142       { "fixup_Hexagon_DTPREL_LO16",    0,      32,     0 },
143       { "fixup_Hexagon_DTPREL_HI16",    0,      32,     0 },
144       { "fixup_Hexagon_DTPREL_32",      0,      32,     0 },
145       { "fixup_Hexagon_DTPREL_16",      0,      32,     0 },
146       { "fixup_Hexagon_GD_PLT_B22_PCREL",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
147       { "fixup_Hexagon_LD_PLT_B22_PCREL",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
148       { "fixup_Hexagon_GD_GOT_LO16",    0,      32,     0 },
149       { "fixup_Hexagon_GD_GOT_HI16",    0,      32,     0 },
150       { "fixup_Hexagon_GD_GOT_32",      0,      32,     0 },
151       { "fixup_Hexagon_GD_GOT_16",      0,      32,     0 },
152       { "fixup_Hexagon_LD_GOT_LO16",    0,      32,     0 },
153       { "fixup_Hexagon_LD_GOT_HI16",    0,      32,     0 },
154       { "fixup_Hexagon_LD_GOT_32",      0,      32,     0 },
155       { "fixup_Hexagon_LD_GOT_16",      0,      32,     0 },
156       { "fixup_Hexagon_IE_LO16",        0,      32,     0 },
157       { "fixup_Hexagon_IE_HI16",        0,      32,     0 },
158       { "fixup_Hexagon_IE_32",          0,      32,     0 },
159       { "fixup_Hexagon_IE_16",          0,      32,     0 },
160       { "fixup_Hexagon_IE_GOT_LO16",    0,      32,     0 },
161       { "fixup_Hexagon_IE_GOT_HI16",    0,      32,     0 },
162       { "fixup_Hexagon_IE_GOT_32",      0,      32,     0 },
163       { "fixup_Hexagon_IE_GOT_16",      0,      32,     0 },
164       { "fixup_Hexagon_TPREL_LO16",     0,      32,     0 },
165       { "fixup_Hexagon_TPREL_HI16",     0,      32,     0 },
166       { "fixup_Hexagon_TPREL_32",       0,      32,     0 },
167       { "fixup_Hexagon_TPREL_16",       0,      32,     0 },
168       { "fixup_Hexagon_6_PCREL_X",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
169       { "fixup_Hexagon_GOTREL_32_6_X",  0,      32,     0 },
170       { "fixup_Hexagon_GOTREL_16_X",    0,      32,     0 },
171       { "fixup_Hexagon_GOTREL_11_X",    0,      32,     0 },
172       { "fixup_Hexagon_GOT_32_6_X",     0,      32,     0 },
173       { "fixup_Hexagon_GOT_16_X",       0,      32,     0 },
174       { "fixup_Hexagon_GOT_11_X",       0,      32,     0 },
175       { "fixup_Hexagon_DTPREL_32_6_X",  0,      32,     0 },
176       { "fixup_Hexagon_DTPREL_16_X",    0,      32,     0 },
177       { "fixup_Hexagon_DTPREL_11_X",    0,      32,     0 },
178       { "fixup_Hexagon_GD_GOT_32_6_X",  0,      32,     0 },
179       { "fixup_Hexagon_GD_GOT_16_X",    0,      32,     0 },
180       { "fixup_Hexagon_GD_GOT_11_X",    0,      32,     0 },
181       { "fixup_Hexagon_LD_GOT_32_6_X",  0,      32,     0 },
182       { "fixup_Hexagon_LD_GOT_16_X",    0,      32,     0 },
183       { "fixup_Hexagon_LD_GOT_11_X",    0,      32,     0 },
184       { "fixup_Hexagon_IE_32_6_X",      0,      32,     0 },
185       { "fixup_Hexagon_IE_16_X",        0,      32,     0 },
186       { "fixup_Hexagon_IE_GOT_32_6_X",  0,      32,     0 },
187       { "fixup_Hexagon_IE_GOT_16_X",    0,      32,     0 },
188       { "fixup_Hexagon_IE_GOT_11_X",    0,      32,     0 },
189       { "fixup_Hexagon_TPREL_32_6_X",   0,      32,     0 },
190       { "fixup_Hexagon_TPREL_16_X",     0,      32,     0 },
191       { "fixup_Hexagon_TPREL_11_X",     0,      32,     0 },
192       { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
193       { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
194       { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
195       { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel }
196     };
197 
198     if (Kind < FirstTargetFixupKind)
199       return MCAsmBackend::getFixupKindInfo(Kind);
200 
201     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
202            "Invalid kind!");
203     return Infos[Kind - FirstTargetFixupKind];
204   }
205 
206   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
207                              const MCValue &Target) override {
208     switch(Fixup.getTargetKind()) {
209       default:
210         llvm_unreachable("Unknown Fixup Kind!");
211 
212       case fixup_Hexagon_LO16:
213       case fixup_Hexagon_HI16:
214       case fixup_Hexagon_16:
215       case fixup_Hexagon_8:
216       case fixup_Hexagon_GPREL16_0:
217       case fixup_Hexagon_GPREL16_1:
218       case fixup_Hexagon_GPREL16_2:
219       case fixup_Hexagon_GPREL16_3:
220       case fixup_Hexagon_HL16:
221       case fixup_Hexagon_32_6_X:
222       case fixup_Hexagon_16_X:
223       case fixup_Hexagon_12_X:
224       case fixup_Hexagon_11_X:
225       case fixup_Hexagon_10_X:
226       case fixup_Hexagon_9_X:
227       case fixup_Hexagon_8_X:
228       case fixup_Hexagon_7_X:
229       case fixup_Hexagon_6_X:
230       case fixup_Hexagon_COPY:
231       case fixup_Hexagon_GLOB_DAT:
232       case fixup_Hexagon_JMP_SLOT:
233       case fixup_Hexagon_RELATIVE:
234       case fixup_Hexagon_PLT_B22_PCREL:
235       case fixup_Hexagon_GOTREL_LO16:
236       case fixup_Hexagon_GOTREL_HI16:
237       case fixup_Hexagon_GOTREL_32:
238       case fixup_Hexagon_GOT_LO16:
239       case fixup_Hexagon_GOT_HI16:
240       case fixup_Hexagon_GOT_32:
241       case fixup_Hexagon_GOT_16:
242       case fixup_Hexagon_DTPMOD_32:
243       case fixup_Hexagon_DTPREL_LO16:
244       case fixup_Hexagon_DTPREL_HI16:
245       case fixup_Hexagon_DTPREL_32:
246       case fixup_Hexagon_DTPREL_16:
247       case fixup_Hexagon_GD_PLT_B22_PCREL:
248       case fixup_Hexagon_LD_PLT_B22_PCREL:
249       case fixup_Hexagon_GD_GOT_LO16:
250       case fixup_Hexagon_GD_GOT_HI16:
251       case fixup_Hexagon_GD_GOT_32:
252       case fixup_Hexagon_GD_GOT_16:
253       case fixup_Hexagon_LD_GOT_LO16:
254       case fixup_Hexagon_LD_GOT_HI16:
255       case fixup_Hexagon_LD_GOT_32:
256       case fixup_Hexagon_LD_GOT_16:
257       case fixup_Hexagon_IE_LO16:
258       case fixup_Hexagon_IE_HI16:
259       case fixup_Hexagon_IE_32:
260       case fixup_Hexagon_IE_16:
261       case fixup_Hexagon_IE_GOT_LO16:
262       case fixup_Hexagon_IE_GOT_HI16:
263       case fixup_Hexagon_IE_GOT_32:
264       case fixup_Hexagon_IE_GOT_16:
265       case fixup_Hexagon_TPREL_LO16:
266       case fixup_Hexagon_TPREL_HI16:
267       case fixup_Hexagon_TPREL_32:
268       case fixup_Hexagon_TPREL_16:
269       case fixup_Hexagon_GOTREL_32_6_X:
270       case fixup_Hexagon_GOTREL_16_X:
271       case fixup_Hexagon_GOTREL_11_X:
272       case fixup_Hexagon_GOT_32_6_X:
273       case fixup_Hexagon_GOT_16_X:
274       case fixup_Hexagon_GOT_11_X:
275       case fixup_Hexagon_DTPREL_32_6_X:
276       case fixup_Hexagon_DTPREL_16_X:
277       case fixup_Hexagon_DTPREL_11_X:
278       case fixup_Hexagon_GD_GOT_32_6_X:
279       case fixup_Hexagon_GD_GOT_16_X:
280       case fixup_Hexagon_GD_GOT_11_X:
281       case fixup_Hexagon_LD_GOT_32_6_X:
282       case fixup_Hexagon_LD_GOT_16_X:
283       case fixup_Hexagon_LD_GOT_11_X:
284       case fixup_Hexagon_IE_32_6_X:
285       case fixup_Hexagon_IE_16_X:
286       case fixup_Hexagon_IE_GOT_32_6_X:
287       case fixup_Hexagon_IE_GOT_16_X:
288       case fixup_Hexagon_IE_GOT_11_X:
289       case fixup_Hexagon_TPREL_32_6_X:
290       case fixup_Hexagon_TPREL_16_X:
291       case fixup_Hexagon_TPREL_11_X:
292       case fixup_Hexagon_32_PCREL:
293       case fixup_Hexagon_6_PCREL_X:
294       case fixup_Hexagon_23_REG:
295       case fixup_Hexagon_27_REG:
296       case fixup_Hexagon_GD_PLT_B22_PCREL_X:
297       case fixup_Hexagon_GD_PLT_B32_PCREL_X:
298       case fixup_Hexagon_LD_PLT_B22_PCREL_X:
299       case fixup_Hexagon_LD_PLT_B32_PCREL_X:
300         // These relocations should always have a relocation recorded
301         return true;
302 
303       case fixup_Hexagon_B22_PCREL:
304         //IsResolved = false;
305         break;
306 
307       case fixup_Hexagon_B13_PCREL:
308       case fixup_Hexagon_B13_PCREL_X:
309       case fixup_Hexagon_B32_PCREL_X:
310       case fixup_Hexagon_B22_PCREL_X:
311       case fixup_Hexagon_B15_PCREL:
312       case fixup_Hexagon_B15_PCREL_X:
313       case fixup_Hexagon_B9_PCREL:
314       case fixup_Hexagon_B9_PCREL_X:
315       case fixup_Hexagon_B7_PCREL:
316       case fixup_Hexagon_B7_PCREL_X:
317         if (DisableFixup)
318           return true;
319         break;
320 
321       case FK_Data_1:
322       case FK_Data_2:
323       case FK_Data_4:
324       case FK_PCRel_4:
325       case fixup_Hexagon_32:
326         // Leave these relocations alone as they are used for EH.
327         return false;
328     }
329     return false;
330   }
331 
332   /// getFixupKindNumBytes - The number of bytes the fixup may change.
333   static unsigned getFixupKindNumBytes(unsigned Kind) {
334     switch (Kind) {
335     default:
336         return 0;
337 
338       case FK_Data_1:
339         return 1;
340       case FK_Data_2:
341         return 2;
342       case FK_Data_4:         // this later gets mapped to R_HEX_32
343       case FK_PCRel_4:        // this later gets mapped to R_HEX_32_PCREL
344       case fixup_Hexagon_32:
345       case fixup_Hexagon_B32_PCREL_X:
346       case fixup_Hexagon_B22_PCREL:
347       case fixup_Hexagon_B22_PCREL_X:
348       case fixup_Hexagon_B15_PCREL:
349       case fixup_Hexagon_B15_PCREL_X:
350       case fixup_Hexagon_B13_PCREL:
351       case fixup_Hexagon_B13_PCREL_X:
352       case fixup_Hexagon_B9_PCREL:
353       case fixup_Hexagon_B9_PCREL_X:
354       case fixup_Hexagon_B7_PCREL:
355       case fixup_Hexagon_B7_PCREL_X:
356       case fixup_Hexagon_GD_PLT_B32_PCREL_X:
357       case fixup_Hexagon_LD_PLT_B32_PCREL_X:
358         return 4;
359     }
360   }
361 
362   // Make up for left shift when encoding the operand.
363   static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) {
364     switch((unsigned)Kind) {
365       default:
366         break;
367 
368       case fixup_Hexagon_B7_PCREL:
369       case fixup_Hexagon_B9_PCREL:
370       case fixup_Hexagon_B13_PCREL:
371       case fixup_Hexagon_B15_PCREL:
372       case fixup_Hexagon_B22_PCREL:
373         Value >>= 2;
374         break;
375 
376       case fixup_Hexagon_B7_PCREL_X:
377       case fixup_Hexagon_B9_PCREL_X:
378       case fixup_Hexagon_B13_PCREL_X:
379       case fixup_Hexagon_B15_PCREL_X:
380       case fixup_Hexagon_B22_PCREL_X:
381         Value &= 0x3f;
382         break;
383 
384       case fixup_Hexagon_B32_PCREL_X:
385       case fixup_Hexagon_GD_PLT_B32_PCREL_X:
386       case fixup_Hexagon_LD_PLT_B32_PCREL_X:
387         Value >>= 6;
388         break;
389     }
390     return (Value);
391   }
392 
393   void HandleFixupError(const int bits, const int align_bits,
394     const int64_t FixupValue, const char *fixupStr) const {
395     // Error: value 1124 out of range: -1024-1023 when resolving
396     // symbol in file xprtsock.S
397     const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
398     const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
399     std::stringstream errStr;
400     errStr << "\nError: value " <<
401       FixupValue <<
402       " out of range: " <<
403       IntMin.getSExtValue() <<
404       "-" <<
405       IntMax.getSExtValue() <<
406       " when resolving " <<
407       fixupStr <<
408       " fixup\n";
409     llvm_unreachable(errStr.str().c_str());
410   }
411 
412   /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
413   /// data fragment, at the offset specified by the fixup and following the
414   /// fixup kind as appropriate.
415   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
416                   const MCValue &Target, MutableArrayRef<char> Data,
417                   uint64_t FixupValue, bool IsResolved,
418                   const MCSubtargetInfo *STI) const override {
419 
420     // When FixupValue is 0 the relocation is external and there
421     // is nothing for us to do.
422     if (!FixupValue) return;
423 
424     MCFixupKind Kind = Fixup.getKind();
425     uint64_t Value;
426     uint32_t InstMask;
427     uint32_t Reloc;
428 
429     // LLVM gives us an encoded value, we have to convert it back
430     // to a real offset before we can use it.
431     uint32_t Offset = Fixup.getOffset();
432     unsigned NumBytes = getFixupKindNumBytes(Kind);
433     assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
434     char *InstAddr = Data.data() + Offset;
435 
436     Value = adjustFixupValue(Kind, FixupValue);
437     if(!Value)
438       return;
439     int sValue = (int)Value;
440 
441     switch((unsigned)Kind) {
442       default:
443         return;
444 
445       case fixup_Hexagon_B7_PCREL:
446         if (!(isIntN(7, sValue)))
447           HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
448         [[fallthrough]];
449       case fixup_Hexagon_B7_PCREL_X:
450         InstMask = 0x00001f18;  // Word32_B7
451         Reloc = (((Value >> 2) & 0x1f) << 8) |    // Value 6-2 = Target 12-8
452                 ((Value & 0x3) << 3);             // Value 1-0 = Target 4-3
453         break;
454 
455       case fixup_Hexagon_B9_PCREL:
456         if (!(isIntN(9, sValue)))
457           HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
458         [[fallthrough]];
459       case fixup_Hexagon_B9_PCREL_X:
460         InstMask = 0x003000fe;  // Word32_B9
461         Reloc = (((Value >> 7) & 0x3) << 20) |    // Value 8-7 = Target 21-20
462                 ((Value & 0x7f) << 1);            // Value 6-0 = Target 7-1
463         break;
464 
465         // Since the existing branches that use this relocation cannot be
466         // extended, they should only be fixed up if the target is within range.
467       case fixup_Hexagon_B13_PCREL:
468         if (!(isIntN(13, sValue)))
469           HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
470         [[fallthrough]];
471       case fixup_Hexagon_B13_PCREL_X:
472         InstMask = 0x00202ffe;  // Word32_B13
473         Reloc = (((Value >> 12) & 0x1) << 21) |    // Value 12   = Target 21
474                 (((Value >> 11) & 0x1) << 13) |    // Value 11   = Target 13
475                 ((Value & 0x7ff) << 1);            // Value 10-0 = Target 11-1
476         break;
477 
478       case fixup_Hexagon_B15_PCREL:
479         if (!(isIntN(15, sValue)))
480           HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
481         [[fallthrough]];
482       case fixup_Hexagon_B15_PCREL_X:
483         InstMask = 0x00df20fe;  // Word32_B15
484         Reloc = (((Value >> 13) & 0x3) << 22) |    // Value 14-13 = Target 23-22
485                 (((Value >> 8) & 0x1f) << 16) |    // Value 12-8  = Target 20-16
486                 (((Value >> 7) & 0x1)  << 13) |    // Value 7     = Target 13
487                 ((Value & 0x7f) << 1);             // Value 6-0   = Target 7-1
488         break;
489 
490       case fixup_Hexagon_B22_PCREL:
491         if (!(isIntN(22, sValue)))
492           HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
493         [[fallthrough]];
494       case fixup_Hexagon_B22_PCREL_X:
495         InstMask = 0x01ff3ffe;  // Word32_B22
496         Reloc = (((Value >> 13) & 0x1ff) << 16) |  // Value 21-13 = Target 24-16
497                 ((Value & 0x1fff) << 1);           // Value 12-0  = Target 13-1
498         break;
499 
500       case fixup_Hexagon_B32_PCREL_X:
501         InstMask = 0x0fff3fff;  // Word32_X26
502         Reloc = (((Value >> 14) & 0xfff) << 16) |  // Value 25-14 = Target 27-16
503                 (Value & 0x3fff);                  // Value 13-0  = Target 13-0
504         break;
505 
506       case FK_Data_1:
507       case FK_Data_2:
508       case FK_Data_4:
509       case fixup_Hexagon_32:
510         InstMask = 0xffffffff;  // Word32
511         Reloc = Value;
512         break;
513     }
514 
515     LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
516                       << (unsigned)Kind << ")\n");
517     LLVM_DEBUG(
518         uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
519                               (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
520         dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
521         dbgs().write_hex(FixupValue)
522         << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
523         dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
524 
525     // For each byte of the fragment that the fixup touches, mask in the
526     // bits from the fixup value. The Value has been "split up" into the
527     // appropriate bitfields above.
528     for (unsigned i = 0; i < NumBytes; i++){
529       InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
530       InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff;     // Apply new reloc
531     }
532 
533     LLVM_DEBUG(uint32_t NewData = 0;
534                for (unsigned i = 0; i < NumBytes; i++) NewData |=
535                (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
536                dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
537   }
538 
539   bool isInstRelaxable(MCInst const &HMI) const {
540     const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
541     bool Relaxable = false;
542     // Branches and loop-setup insns are handled as necessary by relaxation.
543     if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
544         (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ &&
545          MCID.isBranch()) ||
546         (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ &&
547          MCID.isBranch()) ||
548         (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
549          HMI.getOpcode() != Hexagon::C4_addipc))
550       if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
551         Relaxable = true;
552         MCOperand const &Operand =
553             HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI));
554         if (HexagonMCInstrInfo::mustNotExtend(*Operand.getExpr()))
555           Relaxable = false;
556       }
557 
558     return Relaxable;
559   }
560 
561   /// MayNeedRelaxation - Check whether the given instruction may need
562   /// relaxation.
563   ///
564   /// \param Inst - The instruction to test.
565   bool mayNeedRelaxation(MCInst const &Inst,
566                          const MCSubtargetInfo &STI) const override {
567     return true;
568   }
569 
570   /// fixupNeedsRelaxation - Target specific predicate for whether a given
571   /// fixup requires the associated instruction to be relaxed.
572   bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
573                                     uint64_t Value,
574                                     const MCRelaxableFragment *DF,
575                                     const MCAsmLayout &Layout,
576                                     const bool WasForced) const override {
577     MCInst const &MCB = DF->getInst();
578     assert(HexagonMCInstrInfo::isBundle(MCB));
579 
580     *RelaxTarget = nullptr;
581     MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
582         MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
583     bool Relaxable = isInstRelaxable(MCI);
584     if (Relaxable == false)
585       return false;
586     // If we cannot resolve the fixup value, it requires relaxation.
587     if (!Resolved) {
588       switch (Fixup.getTargetKind()) {
589       case fixup_Hexagon_B22_PCREL:
590         // GetFixupCount assumes B22 won't relax
591         [[fallthrough]];
592       default:
593         return false;
594         break;
595       case fixup_Hexagon_B13_PCREL:
596       case fixup_Hexagon_B15_PCREL:
597       case fixup_Hexagon_B9_PCREL:
598       case fixup_Hexagon_B7_PCREL: {
599         if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
600           ++relaxedCnt;
601           *RelaxTarget = &MCI;
602           setExtender(Layout.getAssembler().getContext());
603           return true;
604         } else {
605           return false;
606         }
607         break;
608       }
609       }
610     }
611 
612     MCFixupKind Kind = Fixup.getKind();
613     int64_t sValue = Value;
614     int64_t maxValue;
615 
616     switch ((unsigned)Kind) {
617     case fixup_Hexagon_B7_PCREL:
618       maxValue = 1 << 8;
619       break;
620     case fixup_Hexagon_B9_PCREL:
621       maxValue = 1 << 10;
622       break;
623     case fixup_Hexagon_B15_PCREL:
624       maxValue = 1 << 16;
625       break;
626     case fixup_Hexagon_B22_PCREL:
627       maxValue = 1 << 23;
628       break;
629     default:
630       maxValue = INT64_MAX;
631       break;
632     }
633 
634     bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
635 
636     if (isFarAway) {
637       if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
638         ++relaxedCnt;
639         *RelaxTarget = &MCI;
640         setExtender(Layout.getAssembler().getContext());
641         return true;
642       }
643     }
644 
645     return false;
646   }
647 
648   /// Simple predicate for targets where !Resolved implies requiring relaxation
649   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
650                             const MCRelaxableFragment *DF,
651                             const MCAsmLayout &Layout) const override {
652     llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
653   }
654 
655   void relaxInstruction(MCInst &Inst,
656                         const MCSubtargetInfo &STI) const override {
657     assert(HexagonMCInstrInfo::isBundle(Inst) &&
658            "Hexagon relaxInstruction only works on bundles");
659 
660     MCInst Res;
661     Res.setOpcode(Hexagon::BUNDLE);
662     Res.addOperand(MCOperand::createImm(Inst.getOperand(0).getImm()));
663     // Copy the results into the bundle.
664     bool Update = false;
665     for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
666       MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
667 
668       // if immediate extender needed, add it in
669       if (*RelaxTarget == &CrntHMI) {
670         Update = true;
671         assert((HexagonMCInstrInfo::bundleSize(Res) < HEXAGON_PACKET_SIZE) &&
672                "No room to insert extender for relaxation");
673 
674         MCInst *HMIx = takeExtender();
675         *HMIx = HexagonMCInstrInfo::deriveExtender(
676                 *MCII, CrntHMI,
677                 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI));
678         Res.addOperand(MCOperand::createInst(HMIx));
679         *RelaxTarget = nullptr;
680       }
681       // now copy over the original instruction(the one we may have extended)
682       Res.addOperand(MCOperand::createInst(I.getInst()));
683     }
684 
685     Inst = std::move(Res);
686     (void)Update;
687     assert(Update && "Didn't find relaxation target");
688   }
689 
690   bool writeNopData(raw_ostream &OS, uint64_t Count,
691                     const MCSubtargetInfo *STI) const override {
692     static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
693         ParseIn = 0x00004000,                   // In packet parse-bits.
694         ParseEnd = 0x0000c000;                  // End of packet parse-bits.
695 
696     while (Count % HEXAGON_INSTR_SIZE) {
697       LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
698                         << Count % HEXAGON_INSTR_SIZE << "/"
699                         << HEXAGON_INSTR_SIZE << "\n");
700       --Count;
701       OS << '\0';
702     }
703 
704     while (Count) {
705       Count -= HEXAGON_INSTR_SIZE;
706       // Close the packet whenever a multiple of the maximum packet size remains
707       uint32_t ParseBits = (Count % (MaxPacketSize * HEXAGON_INSTR_SIZE)) ?
708                            ParseIn : ParseEnd;
709       support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
710     }
711     return true;
712   }
713 
714   void finishLayout(MCAssembler const &Asm,
715                     MCAsmLayout &Layout) const override {
716     for (auto *I : Layout.getSectionOrder()) {
717       auto &Fragments = I->getFragmentList();
718       for (auto &J : Fragments) {
719         switch (J.getKind()) {
720         default:
721           break;
722         case MCFragment::FT_Align: {
723           auto Size = Asm.computeFragmentSize(Layout, J);
724           for (auto K = J.getIterator();
725                K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
726             --K;
727             switch (K->getKind()) {
728             default:
729               break;
730             case MCFragment::FT_Align: {
731               // Don't pad before other alignments
732               Size = 0;
733               break;
734             }
735             case MCFragment::FT_Relaxable: {
736               MCContext &Context = Asm.getContext();
737               auto &RF = cast<MCRelaxableFragment>(*K);
738               auto &Inst = const_cast<MCInst &>(RF.getInst());
739               while (Size > 0 &&
740                      HexagonMCInstrInfo::bundleSize(Inst) < MaxPacketSize) {
741                 MCInst *Nop = Context.createMCInst();
742                 Nop->setOpcode(Hexagon::A2_nop);
743                 Inst.addOperand(MCOperand::createInst(Nop));
744                 Size -= 4;
745                 if (!HexagonMCChecker(
746                          Context, *MCII, *RF.getSubtargetInfo(), Inst,
747                          *Context.getRegisterInfo(), false)
748                          .check()) {
749                   Inst.erase(Inst.end() - 1);
750                   Size = 0;
751                 }
752               }
753               bool Error = HexagonMCShuffle(Context, true, *MCII,
754                                             *RF.getSubtargetInfo(), Inst);
755               //assert(!Error);
756               (void)Error;
757               ReplaceInstruction(Asm.getEmitter(), RF, Inst);
758               Layout.invalidateFragmentsFrom(&RF);
759               Size = 0; // Only look back one instruction
760               break;
761             }
762             }
763           }
764         }
765         }
766       }
767     }
768   }
769 }; // class HexagonAsmBackend
770 
771 } // namespace
772 
773 // MCAsmBackend
774 MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
775                                             const MCSubtargetInfo &STI,
776                                             MCRegisterInfo const & /*MRI*/,
777                                             const MCTargetOptions &Options) {
778   const Triple &TT = STI.getTargetTriple();
779   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
780 
781   StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
782   return new HexagonAsmBackend(T, TT, OSABI, CPUString);
783 }
784