1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about Hexagon target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "HexagonTargetMachine.h" 14 #include "Hexagon.h" 15 #include "HexagonISelLowering.h" 16 #include "HexagonLoopIdiomRecognition.h" 17 #include "HexagonMachineScheduler.h" 18 #include "HexagonTargetObjectFile.h" 19 #include "HexagonTargetTransformInfo.h" 20 #include "HexagonVectorLoopCarriedReuse.h" 21 #include "TargetInfo/HexagonTargetInfo.h" 22 #include "llvm/CodeGen/Passes.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/CodeGen/VLIWMachineScheduler.h" 25 #include "llvm/IR/LegacyPassManager.h" 26 #include "llvm/IR/Module.h" 27 #include "llvm/MC/TargetRegistry.h" 28 #include "llvm/Passes/PassBuilder.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Transforms/IPO/PassManagerBuilder.h" 31 #include "llvm/Transforms/Scalar.h" 32 33 using namespace llvm; 34 35 static cl::opt<bool> 36 EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), 37 cl::desc("Enable Hexagon constant-extender optimization")); 38 39 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), 40 cl::desc("Enable RDF-based optimizations")); 41 42 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops", 43 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); 44 45 static cl::opt<bool> 46 DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, 47 cl::desc("Disable Hexagon Addressing Mode Optimization")); 48 49 static cl::opt<bool> 50 DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, 51 cl::desc("Disable Hexagon CFG Optimization")); 52 53 static cl::opt<bool> 54 DisableHCP("disable-hcp", cl::Hidden, 55 cl::desc("Disable Hexagon constant propagation")); 56 57 static cl::opt<bool> DisableStoreWidening("disable-store-widen", 58 cl::Hidden, cl::init(false), cl::desc("Disable store widening")); 59 60 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets", 61 cl::init(true), cl::Hidden, 62 cl::desc("Early expansion of MUX")); 63 64 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, 65 cl::desc("Enable early if-conversion")); 66 67 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true), 68 cl::Hidden, cl::desc("Generate \"insert\" instructions")); 69 70 static cl::opt<bool> 71 EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, 72 cl::desc("Enable commoning of GEP instructions")); 73 74 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true), 75 cl::Hidden, cl::desc("Generate \"extract\" instructions")); 76 77 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, 78 cl::desc("Enable converting conditional transfers into MUX instructions")); 79 80 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true), 81 cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " 82 "predicate instructions")); 83 84 static cl::opt<bool> 85 EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, 86 cl::desc("Enable loop data prefetch on Hexagon")); 87 88 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, 89 cl::desc("Disable splitting double registers")); 90 91 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true), 92 cl::Hidden, cl::desc("Bit simplification")); 93 94 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true), 95 cl::Hidden, cl::desc("Loop rescheduling")); 96 97 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false), 98 cl::Hidden, cl::desc("Disable backend optimizations")); 99 100 static cl::opt<bool> 101 EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, 102 cl::desc("Enable Hexagon Vector print instr pass")); 103 104 static cl::opt<bool> 105 EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), 106 cl::desc("Enable vextract optimization")); 107 108 static cl::opt<bool> 109 EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), 110 cl::desc("Enable HVX vector combining")); 111 112 static cl::opt<bool> EnableInitialCFGCleanup( 113 "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), 114 cl::desc("Simplify the CFG after atomic expansion pass")); 115 116 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden, 117 cl::init(true), 118 cl::desc("Enable instsimplify")); 119 120 /// HexagonTargetMachineModule - Note that this is used on hosts that 121 /// cannot link in a library unless there are references into the 122 /// library. In particular, it seems that it is not possible to get 123 /// things to work on Win32 without this. Though it is unused, do not 124 /// remove it. 125 extern "C" int HexagonTargetMachineModule; 126 int HexagonTargetMachineModule = 0; 127 128 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { 129 ScheduleDAGMILive *DAG = new VLIWMachineScheduler( 130 C, std::make_unique<HexagonConvergingVLIWScheduler>()); 131 DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>()); 132 DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>()); 133 DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>()); 134 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI)); 135 return DAG; 136 } 137 138 static MachineSchedRegistry 139 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", 140 createVLIWMachineSched); 141 142 namespace llvm { 143 extern char &HexagonExpandCondsetsID; 144 void initializeHexagonBitSimplifyPass(PassRegistry&); 145 void initializeHexagonConstExtendersPass(PassRegistry&); 146 void initializeHexagonConstPropagationPass(PassRegistry&); 147 void initializeHexagonCopyToCombinePass(PassRegistry&); 148 void initializeHexagonEarlyIfConversionPass(PassRegistry&); 149 void initializeHexagonExpandCondsetsPass(PassRegistry&); 150 void initializeHexagonGenMuxPass(PassRegistry&); 151 void initializeHexagonHardwareLoopsPass(PassRegistry&); 152 void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); 153 void initializeHexagonNewValueJumpPass(PassRegistry&); 154 void initializeHexagonOptAddrModePass(PassRegistry&); 155 void initializeHexagonPacketizerPass(PassRegistry&); 156 void initializeHexagonRDFOptPass(PassRegistry&); 157 void initializeHexagonSplitDoubleRegsPass(PassRegistry&); 158 void initializeHexagonVectorCombineLegacyPass(PassRegistry&); 159 void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); 160 void initializeHexagonVExtractPass(PassRegistry&); 161 Pass *createHexagonLoopIdiomPass(); 162 Pass *createHexagonVectorLoopCarriedReuseLegacyPass(); 163 164 FunctionPass *createHexagonBitSimplify(); 165 FunctionPass *createHexagonBranchRelaxation(); 166 FunctionPass *createHexagonCallFrameInformation(); 167 FunctionPass *createHexagonCFGOptimizer(); 168 FunctionPass *createHexagonCommonGEP(); 169 FunctionPass *createHexagonConstExtenders(); 170 FunctionPass *createHexagonConstPropagationPass(); 171 FunctionPass *createHexagonCopyToCombine(); 172 FunctionPass *createHexagonEarlyIfConversion(); 173 FunctionPass *createHexagonFixupHwLoops(); 174 FunctionPass *createHexagonGenExtract(); 175 FunctionPass *createHexagonGenInsert(); 176 FunctionPass *createHexagonGenMux(); 177 FunctionPass *createHexagonGenPredicate(); 178 FunctionPass *createHexagonHardwareLoops(); 179 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, 180 CodeGenOpt::Level OptLevel); 181 FunctionPass *createHexagonLoopRescheduling(); 182 FunctionPass *createHexagonNewValueJump(); 183 FunctionPass *createHexagonOptAddrMode(); 184 FunctionPass *createHexagonOptimizeSZextends(); 185 FunctionPass *createHexagonPacketizer(bool Minimal); 186 FunctionPass *createHexagonPeephole(); 187 FunctionPass *createHexagonRDFOpt(); 188 FunctionPass *createHexagonSplitConst32AndConst64(); 189 FunctionPass *createHexagonSplitDoubleRegs(); 190 FunctionPass *createHexagonStoreWidening(); 191 FunctionPass *createHexagonVectorCombineLegacyPass(); 192 FunctionPass *createHexagonVectorPrint(); 193 FunctionPass *createHexagonVExtract(); 194 } // end namespace llvm; 195 196 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 197 return RM.value_or(Reloc::Static); 198 } 199 200 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() { 201 // Register the target. 202 RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget()); 203 204 PassRegistry &PR = *PassRegistry::getPassRegistry(); 205 initializeHexagonBitSimplifyPass(PR); 206 initializeHexagonConstExtendersPass(PR); 207 initializeHexagonConstPropagationPass(PR); 208 initializeHexagonCopyToCombinePass(PR); 209 initializeHexagonEarlyIfConversionPass(PR); 210 initializeHexagonGenMuxPass(PR); 211 initializeHexagonHardwareLoopsPass(PR); 212 initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR); 213 initializeHexagonNewValueJumpPass(PR); 214 initializeHexagonOptAddrModePass(PR); 215 initializeHexagonPacketizerPass(PR); 216 initializeHexagonRDFOptPass(PR); 217 initializeHexagonSplitDoubleRegsPass(PR); 218 initializeHexagonVectorCombineLegacyPass(PR); 219 initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR); 220 initializeHexagonVExtractPass(PR); 221 } 222 223 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, 224 StringRef CPU, StringRef FS, 225 const TargetOptions &Options, 226 Optional<Reloc::Model> RM, 227 Optional<CodeModel::Model> CM, 228 CodeGenOpt::Level OL, bool JIT) 229 // Specify the vector alignment explicitly. For v512x1, the calculated 230 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 231 // the required minimum of 64 bytes. 232 : LLVMTargetMachine( 233 T, 234 "e-m:e-p:32:32:32-a:0-n16:32-" 235 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 236 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048", 237 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 238 getEffectiveCodeModel(CM, CodeModel::Small), 239 (HexagonNoOpt ? CodeGenOpt::None : OL)), 240 TLOF(std::make_unique<HexagonTargetObjectFile>()) { 241 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); 242 initAsmInfo(); 243 } 244 245 const HexagonSubtarget * 246 HexagonTargetMachine::getSubtargetImpl(const Function &F) const { 247 AttributeList FnAttrs = F.getAttributes(); 248 Attribute CPUAttr = 249 FnAttrs.getFnAttr("target-cpu"); 250 Attribute FSAttr = 251 FnAttrs.getFnAttr("target-features"); 252 253 std::string CPU = 254 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 255 std::string FS = 256 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 257 // Append the preexisting target features last, so that +mattr overrides 258 // the "unsafe-fp-math" function attribute. 259 // Creating a separate target feature is not strictly necessary, it only 260 // exists to make "unsafe-fp-math" force creating a new subtarget. 261 262 if (F.getFnAttribute("unsafe-fp-math").getValueAsBool()) 263 FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS; 264 265 auto &I = SubtargetMap[CPU + FS]; 266 if (!I) { 267 // This needs to be done before we create a new subtarget since any 268 // creation will depend on the TM and the code generation flags on the 269 // function that reside in TargetOptions. 270 resetTargetOptions(F); 271 I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this); 272 } 273 return I.get(); 274 } 275 276 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) { 277 PMB.addExtension( 278 PassManagerBuilder::EP_LateLoopOptimizations, 279 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { 280 PM.add(createHexagonLoopIdiomPass()); 281 }); 282 PMB.addExtension( 283 PassManagerBuilder::EP_LoopOptimizerEnd, 284 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { 285 PM.add(createHexagonVectorLoopCarriedReuseLegacyPass()); 286 }); 287 } 288 289 void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { 290 PB.registerLateLoopOptimizationsEPCallback( 291 [=](LoopPassManager &LPM, OptimizationLevel Level) { 292 LPM.addPass(HexagonLoopIdiomRecognitionPass()); 293 }); 294 PB.registerLoopOptimizerEndEPCallback( 295 [=](LoopPassManager &LPM, OptimizationLevel Level) { 296 LPM.addPass(HexagonVectorLoopCarriedReusePass()); 297 }); 298 } 299 300 TargetTransformInfo 301 HexagonTargetMachine::getTargetTransformInfo(const Function &F) const { 302 return TargetTransformInfo(HexagonTTIImpl(this, F)); 303 } 304 305 HexagonTargetMachine::~HexagonTargetMachine() = default; 306 307 namespace { 308 /// Hexagon Code Generator Pass Configuration Options. 309 class HexagonPassConfig : public TargetPassConfig { 310 public: 311 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM) 312 : TargetPassConfig(TM, PM) {} 313 314 HexagonTargetMachine &getHexagonTargetMachine() const { 315 return getTM<HexagonTargetMachine>(); 316 } 317 318 ScheduleDAGInstrs * 319 createMachineScheduler(MachineSchedContext *C) const override { 320 return createVLIWMachineSched(C); 321 } 322 323 void addIRPasses() override; 324 bool addInstSelector() override; 325 void addPreRegAlloc() override; 326 void addPostRegAlloc() override; 327 void addPreSched2() override; 328 void addPreEmitPass() override; 329 }; 330 } // namespace 331 332 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { 333 return new HexagonPassConfig(*this, PM); 334 } 335 336 void HexagonPassConfig::addIRPasses() { 337 TargetPassConfig::addIRPasses(); 338 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 339 340 if (!NoOpt) { 341 if (EnableInstSimplify) 342 addPass(createInstSimplifyLegacyPass()); 343 addPass(createDeadCodeEliminationPass()); 344 } 345 346 addPass(createAtomicExpandPass()); 347 348 if (!NoOpt) { 349 if (EnableInitialCFGCleanup) 350 addPass(createCFGSimplificationPass(SimplifyCFGOptions() 351 .forwardSwitchCondToPhi(true) 352 .convertSwitchRangeToICmp(true) 353 .convertSwitchToLookupTable(true) 354 .needCanonicalLoops(false) 355 .hoistCommonInsts(true) 356 .sinkCommonInsts(true))); 357 if (EnableLoopPrefetch) 358 addPass(createLoopDataPrefetchPass()); 359 if (EnableVectorCombine) 360 addPass(createHexagonVectorCombineLegacyPass()); 361 if (EnableCommGEP) 362 addPass(createHexagonCommonGEP()); 363 // Replace certain combinations of shifts and ands with extracts. 364 if (EnableGenExtract) 365 addPass(createHexagonGenExtract()); 366 } 367 } 368 369 bool HexagonPassConfig::addInstSelector() { 370 HexagonTargetMachine &TM = getHexagonTargetMachine(); 371 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 372 373 if (!NoOpt) 374 addPass(createHexagonOptimizeSZextends()); 375 376 addPass(createHexagonISelDag(TM, getOptLevel())); 377 378 if (!NoOpt) { 379 if (EnableVExtractOpt) 380 addPass(createHexagonVExtract()); 381 // Create logical operations on predicate registers. 382 if (EnableGenPred) 383 addPass(createHexagonGenPredicate()); 384 // Rotate loops to expose bit-simplification opportunities. 385 if (EnableLoopResched) 386 addPass(createHexagonLoopRescheduling()); 387 // Split double registers. 388 if (!DisableHSDR) 389 addPass(createHexagonSplitDoubleRegs()); 390 // Bit simplification. 391 if (EnableBitSimplify) 392 addPass(createHexagonBitSimplify()); 393 addPass(createHexagonPeephole()); 394 // Constant propagation. 395 if (!DisableHCP) { 396 addPass(createHexagonConstPropagationPass()); 397 addPass(&UnreachableMachineBlockElimID); 398 } 399 if (EnableGenInsert) 400 addPass(createHexagonGenInsert()); 401 if (EnableEarlyIf) 402 addPass(createHexagonEarlyIfConversion()); 403 } 404 405 return false; 406 } 407 408 void HexagonPassConfig::addPreRegAlloc() { 409 if (getOptLevel() != CodeGenOpt::None) { 410 if (EnableCExtOpt) 411 addPass(createHexagonConstExtenders()); 412 if (EnableExpandCondsets) 413 insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID); 414 if (!DisableStoreWidening) 415 addPass(createHexagonStoreWidening()); 416 if (!DisableHardwareLoops) 417 addPass(createHexagonHardwareLoops()); 418 } 419 if (TM->getOptLevel() >= CodeGenOpt::Default) 420 addPass(&MachinePipelinerID); 421 } 422 423 void HexagonPassConfig::addPostRegAlloc() { 424 if (getOptLevel() != CodeGenOpt::None) { 425 if (EnableRDFOpt) 426 addPass(createHexagonRDFOpt()); 427 if (!DisableHexagonCFGOpt) 428 addPass(createHexagonCFGOptimizer()); 429 if (!DisableAModeOpt) 430 addPass(createHexagonOptAddrMode()); 431 } 432 } 433 434 void HexagonPassConfig::addPreSched2() { 435 addPass(createHexagonCopyToCombine()); 436 if (getOptLevel() != CodeGenOpt::None) 437 addPass(&IfConverterID); 438 addPass(createHexagonSplitConst32AndConst64()); 439 } 440 441 void HexagonPassConfig::addPreEmitPass() { 442 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 443 444 if (!NoOpt) 445 addPass(createHexagonNewValueJump()); 446 447 addPass(createHexagonBranchRelaxation()); 448 449 if (!NoOpt) { 450 if (!DisableHardwareLoops) 451 addPass(createHexagonFixupHwLoops()); 452 // Generate MUX from pairs of conditional transfers. 453 if (EnableGenMux) 454 addPass(createHexagonGenMux()); 455 } 456 457 // Packetization is mandatory: it handles gather/scatter at all opt levels. 458 addPass(createHexagonPacketizer(NoOpt)); 459 460 if (EnableVectorPrint) 461 addPass(createHexagonVectorPrint()); 462 463 // Add CFI instructions if necessary. 464 addPass(createHexagonCallFrameInformation()); 465 } 466