xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (revision 5956d97f4b3204318ceb6aa9c77bd0bc6ea87a41) 
1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonLoopIdiomRecognition.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "HexagonVectorLoopCarriedReuse.h"
21 #include "TargetInfo/HexagonTargetInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/CodeGen/VLIWMachineScheduler.h"
25 #include "llvm/IR/LegacyPassManager.h"
26 #include "llvm/IR/Module.h"
27 #include "llvm/MC/TargetRegistry.h"
28 #include "llvm/Passes/PassBuilder.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
31 #include "llvm/Transforms/Scalar.h"
32 
33 using namespace llvm;
34 
35 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
36   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
37 
38 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
39   cl::init(true), cl::desc("Enable RDF-based optimizations"));
40 
41 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
42   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
43 
44 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon Addressing Mode Optimization"));
47 
48 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
49   cl::Hidden, cl::ZeroOrMore, cl::init(false),
50   cl::desc("Disable Hexagon CFG Optimization"));
51 
52 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
53   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
54 
55 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
56   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
57 
58 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
59   cl::init(true), cl::Hidden, cl::ZeroOrMore,
60   cl::desc("Early expansion of MUX"));
61 
62 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
63   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
64 
65 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
66   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
67 
68 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
69   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
70 
71 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
72   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
73 
74 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
75   cl::desc("Enable converting conditional transfers into MUX instructions"));
76 
77 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
78   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
79   "predicate instructions"));
80 
81 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
82   cl::init(false), cl::Hidden, cl::ZeroOrMore,
83   cl::desc("Enable loop data prefetch on Hexagon"));
84 
85 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
86   cl::desc("Disable splitting double registers"));
87 
88 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
89   cl::Hidden, cl::desc("Bit simplification"));
90 
91 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
92   cl::Hidden, cl::desc("Loop rescheduling"));
93 
94 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
95   cl::Hidden, cl::desc("Disable backend optimizations"));
96 
97 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
98   cl::Hidden, cl::ZeroOrMore, cl::init(false),
99   cl::desc("Enable Hexagon Vector print instr pass"));
100 
101 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
102   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
103 
104 static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden,
105   cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"));
106 
107 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
108   cl::Hidden, cl::ZeroOrMore, cl::init(true),
109   cl::desc("Simplify the CFG after atomic expansion pass"));
110 
111 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
112                                         cl::ZeroOrMore, cl::init(true),
113                                         cl::desc("Enable instsimplify"));
114 
115 /// HexagonTargetMachineModule - Note that this is used on hosts that
116 /// cannot link in a library unless there are references into the
117 /// library.  In particular, it seems that it is not possible to get
118 /// things to work on Win32 without this.  Though it is unused, do not
119 /// remove it.
120 extern "C" int HexagonTargetMachineModule;
121 int HexagonTargetMachineModule = 0;
122 
123 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
124   ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
125       C, std::make_unique<HexagonConvergingVLIWScheduler>());
126   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
127   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
128   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
129   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
130   return DAG;
131 }
132 
133 static MachineSchedRegistry
134 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
135                     createVLIWMachineSched);
136 
137 namespace llvm {
138   extern char &HexagonExpandCondsetsID;
139   void initializeHexagonBitSimplifyPass(PassRegistry&);
140   void initializeHexagonConstExtendersPass(PassRegistry&);
141   void initializeHexagonConstPropagationPass(PassRegistry&);
142   void initializeHexagonCopyToCombinePass(PassRegistry&);
143   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
144   void initializeHexagonExpandCondsetsPass(PassRegistry&);
145   void initializeHexagonGenMuxPass(PassRegistry&);
146   void initializeHexagonHardwareLoopsPass(PassRegistry&);
147   void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
148   void initializeHexagonNewValueJumpPass(PassRegistry&);
149   void initializeHexagonOptAddrModePass(PassRegistry&);
150   void initializeHexagonPacketizerPass(PassRegistry&);
151   void initializeHexagonRDFOptPass(PassRegistry&);
152   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
153   void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
154   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
155   void initializeHexagonVExtractPass(PassRegistry&);
156   Pass *createHexagonLoopIdiomPass();
157   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
158 
159   FunctionPass *createHexagonBitSimplify();
160   FunctionPass *createHexagonBranchRelaxation();
161   FunctionPass *createHexagonCallFrameInformation();
162   FunctionPass *createHexagonCFGOptimizer();
163   FunctionPass *createHexagonCommonGEP();
164   FunctionPass *createHexagonConstExtenders();
165   FunctionPass *createHexagonConstPropagationPass();
166   FunctionPass *createHexagonCopyToCombine();
167   FunctionPass *createHexagonEarlyIfConversion();
168   FunctionPass *createHexagonFixupHwLoops();
169   FunctionPass *createHexagonGenExtract();
170   FunctionPass *createHexagonGenInsert();
171   FunctionPass *createHexagonGenMux();
172   FunctionPass *createHexagonGenPredicate();
173   FunctionPass *createHexagonHardwareLoops();
174   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
175                                      CodeGenOpt::Level OptLevel);
176   FunctionPass *createHexagonLoopRescheduling();
177   FunctionPass *createHexagonNewValueJump();
178   FunctionPass *createHexagonOptAddrMode();
179   FunctionPass *createHexagonOptimizeSZextends();
180   FunctionPass *createHexagonPacketizer(bool Minimal);
181   FunctionPass *createHexagonPeephole();
182   FunctionPass *createHexagonRDFOpt();
183   FunctionPass *createHexagonSplitConst32AndConst64();
184   FunctionPass *createHexagonSplitDoubleRegs();
185   FunctionPass *createHexagonStoreWidening();
186   FunctionPass *createHexagonVectorCombineLegacyPass();
187   FunctionPass *createHexagonVectorPrint();
188   FunctionPass *createHexagonVExtract();
189 } // end namespace llvm;
190 
191 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
192   return RM.getValueOr(Reloc::Static);
193 }
194 
195 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
196   // Register the target.
197   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
198 
199   PassRegistry &PR = *PassRegistry::getPassRegistry();
200   initializeHexagonBitSimplifyPass(PR);
201   initializeHexagonConstExtendersPass(PR);
202   initializeHexagonConstPropagationPass(PR);
203   initializeHexagonCopyToCombinePass(PR);
204   initializeHexagonEarlyIfConversionPass(PR);
205   initializeHexagonGenMuxPass(PR);
206   initializeHexagonHardwareLoopsPass(PR);
207   initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
208   initializeHexagonNewValueJumpPass(PR);
209   initializeHexagonOptAddrModePass(PR);
210   initializeHexagonPacketizerPass(PR);
211   initializeHexagonRDFOptPass(PR);
212   initializeHexagonSplitDoubleRegsPass(PR);
213   initializeHexagonVectorCombineLegacyPass(PR);
214   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
215   initializeHexagonVExtractPass(PR);
216 }
217 
218 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
219                                            StringRef CPU, StringRef FS,
220                                            const TargetOptions &Options,
221                                            Optional<Reloc::Model> RM,
222                                            Optional<CodeModel::Model> CM,
223                                            CodeGenOpt::Level OL, bool JIT)
224     // Specify the vector alignment explicitly. For v512x1, the calculated
225     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
226     // the required minimum of 64 bytes.
227     : LLVMTargetMachine(
228           T,
229           "e-m:e-p:32:32:32-a:0-n16:32-"
230           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
231           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
232           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
233           getEffectiveCodeModel(CM, CodeModel::Small),
234           (HexagonNoOpt ? CodeGenOpt::None : OL)),
235       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
236   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
237   initAsmInfo();
238 }
239 
240 const HexagonSubtarget *
241 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
242   AttributeList FnAttrs = F.getAttributes();
243   Attribute CPUAttr =
244       FnAttrs.getFnAttr("target-cpu");
245   Attribute FSAttr =
246       FnAttrs.getFnAttr("target-features");
247 
248   std::string CPU =
249       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
250   std::string FS =
251       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
252   // Append the preexisting target features last, so that +mattr overrides
253   // the "unsafe-fp-math" function attribute.
254   // Creating a separate target feature is not strictly necessary, it only
255   // exists to make "unsafe-fp-math" force creating a new subtarget.
256 
257   if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
258     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
259 
260   auto &I = SubtargetMap[CPU + FS];
261   if (!I) {
262     // This needs to be done before we create a new subtarget since any
263     // creation will depend on the TM and the code generation flags on the
264     // function that reside in TargetOptions.
265     resetTargetOptions(F);
266     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
267   }
268   return I.get();
269 }
270 
271 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
272   PMB.addExtension(
273     PassManagerBuilder::EP_LateLoopOptimizations,
274     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
275       PM.add(createHexagonLoopIdiomPass());
276     });
277   PMB.addExtension(
278       PassManagerBuilder::EP_LoopOptimizerEnd,
279       [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
280         PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
281       });
282 }
283 
284 void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
285   PB.registerLateLoopOptimizationsEPCallback(
286       [=](LoopPassManager &LPM, OptimizationLevel Level) {
287         LPM.addPass(HexagonLoopIdiomRecognitionPass());
288       });
289   PB.registerLoopOptimizerEndEPCallback(
290       [=](LoopPassManager &LPM, OptimizationLevel Level) {
291         LPM.addPass(HexagonVectorLoopCarriedReusePass());
292       });
293 }
294 
295 TargetTransformInfo
296 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
297   return TargetTransformInfo(HexagonTTIImpl(this, F));
298 }
299 
300 
301 HexagonTargetMachine::~HexagonTargetMachine() {}
302 
303 namespace {
304 /// Hexagon Code Generator Pass Configuration Options.
305 class HexagonPassConfig : public TargetPassConfig {
306 public:
307   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
308     : TargetPassConfig(TM, PM) {}
309 
310   HexagonTargetMachine &getHexagonTargetMachine() const {
311     return getTM<HexagonTargetMachine>();
312   }
313 
314   ScheduleDAGInstrs *
315   createMachineScheduler(MachineSchedContext *C) const override {
316     return createVLIWMachineSched(C);
317   }
318 
319   void addIRPasses() override;
320   bool addInstSelector() override;
321   void addPreRegAlloc() override;
322   void addPostRegAlloc() override;
323   void addPreSched2() override;
324   void addPreEmitPass() override;
325 };
326 } // namespace
327 
328 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
329   return new HexagonPassConfig(*this, PM);
330 }
331 
332 void HexagonPassConfig::addIRPasses() {
333   TargetPassConfig::addIRPasses();
334   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
335 
336   if (!NoOpt) {
337     if (EnableInstSimplify)
338       addPass(createInstSimplifyLegacyPass());
339     addPass(createDeadCodeEliminationPass());
340   }
341 
342   addPass(createAtomicExpandPass());
343 
344   if (!NoOpt) {
345     if (EnableInitialCFGCleanup)
346       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
347                                               .forwardSwitchCondToPhi(true)
348                                               .convertSwitchRangeToICmp(true)
349                                               .convertSwitchToLookupTable(true)
350                                               .needCanonicalLoops(false)
351                                               .hoistCommonInsts(true)
352                                               .sinkCommonInsts(true)));
353     if (EnableLoopPrefetch)
354       addPass(createLoopDataPrefetchPass());
355     if (EnableVectorCombine)
356       addPass(createHexagonVectorCombineLegacyPass());
357     if (EnableCommGEP)
358       addPass(createHexagonCommonGEP());
359     // Replace certain combinations of shifts and ands with extracts.
360     if (EnableGenExtract)
361       addPass(createHexagonGenExtract());
362   }
363 }
364 
365 bool HexagonPassConfig::addInstSelector() {
366   HexagonTargetMachine &TM = getHexagonTargetMachine();
367   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
368 
369   if (!NoOpt)
370     addPass(createHexagonOptimizeSZextends());
371 
372   addPass(createHexagonISelDag(TM, getOptLevel()));
373 
374   if (!NoOpt) {
375     if (EnableVExtractOpt)
376       addPass(createHexagonVExtract());
377     // Create logical operations on predicate registers.
378     if (EnableGenPred)
379       addPass(createHexagonGenPredicate());
380     // Rotate loops to expose bit-simplification opportunities.
381     if (EnableLoopResched)
382       addPass(createHexagonLoopRescheduling());
383     // Split double registers.
384     if (!DisableHSDR)
385       addPass(createHexagonSplitDoubleRegs());
386     // Bit simplification.
387     if (EnableBitSimplify)
388       addPass(createHexagonBitSimplify());
389     addPass(createHexagonPeephole());
390     // Constant propagation.
391     if (!DisableHCP) {
392       addPass(createHexagonConstPropagationPass());
393       addPass(&UnreachableMachineBlockElimID);
394     }
395     if (EnableGenInsert)
396       addPass(createHexagonGenInsert());
397     if (EnableEarlyIf)
398       addPass(createHexagonEarlyIfConversion());
399   }
400 
401   return false;
402 }
403 
404 void HexagonPassConfig::addPreRegAlloc() {
405   if (getOptLevel() != CodeGenOpt::None) {
406     if (EnableCExtOpt)
407       addPass(createHexagonConstExtenders());
408     if (EnableExpandCondsets)
409       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
410     if (!DisableStoreWidening)
411       addPass(createHexagonStoreWidening());
412     if (!DisableHardwareLoops)
413       addPass(createHexagonHardwareLoops());
414   }
415   if (TM->getOptLevel() >= CodeGenOpt::Default)
416     addPass(&MachinePipelinerID);
417 }
418 
419 void HexagonPassConfig::addPostRegAlloc() {
420   if (getOptLevel() != CodeGenOpt::None) {
421     if (EnableRDFOpt)
422       addPass(createHexagonRDFOpt());
423     if (!DisableHexagonCFGOpt)
424       addPass(createHexagonCFGOptimizer());
425     if (!DisableAModeOpt)
426       addPass(createHexagonOptAddrMode());
427   }
428 }
429 
430 void HexagonPassConfig::addPreSched2() {
431   addPass(createHexagonCopyToCombine());
432   if (getOptLevel() != CodeGenOpt::None)
433     addPass(&IfConverterID);
434   addPass(createHexagonSplitConst32AndConst64());
435 }
436 
437 void HexagonPassConfig::addPreEmitPass() {
438   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
439 
440   if (!NoOpt)
441     addPass(createHexagonNewValueJump());
442 
443   addPass(createHexagonBranchRelaxation());
444 
445   if (!NoOpt) {
446     if (!DisableHardwareLoops)
447       addPass(createHexagonFixupHwLoops());
448     // Generate MUX from pairs of conditional transfers.
449     if (EnableGenMux)
450       addPass(createHexagonGenMux());
451   }
452 
453   // Packetization is mandatory: it handles gather/scatter at all opt levels.
454   addPass(createHexagonPacketizer(NoOpt));
455 
456   if (EnableVectorPrint)
457     addPass(createHexagonVectorPrint());
458 
459   // Add CFI instructions if necessary.
460   addPass(createHexagonCallFrameInformation());
461 }
462