xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonSubtarget.h (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 
16 #include "HexagonArch.h"
17 #include "HexagonFrameLowering.h"
18 #include "HexagonISelLowering.h"
19 #include "HexagonInstrInfo.h"
20 #include "HexagonRegisterInfo.h"
21 #include "HexagonSelectionDAGInfo.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/CodeGen/ScheduleDAGMutation.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include <memory>
28 #include <string>
29 #include <vector>
30 
31 #define GET_SUBTARGETINFO_HEADER
32 #include "HexagonGenSubtargetInfo.inc"
33 
34 namespace llvm {
35 
36 class MachineInstr;
37 class SDep;
38 class SUnit;
39 class TargetMachine;
40 class Triple;
41 
42 class HexagonSubtarget : public HexagonGenSubtargetInfo {
43   virtual void anchor();
44 
45   bool UseHVX64BOps = false;
46   bool UseHVX128BOps = false;
47 
48   bool UseAudioOps = false;
49   bool UseCompound = false;
50   bool UseLongCalls = false;
51   bool UseMemops = false;
52   bool UsePackets = false;
53   bool UseNewValueJumps = false;
54   bool UseNewValueStores = false;
55   bool UseSmallData = false;
56   bool UseUnsafeMath = false;
57   bool UseZRegOps = false;
58 
59   bool HasPreV65 = false;
60   bool HasMemNoShuf = false;
61   bool EnableDuplex = false;
62   bool ReservedR19 = false;
63   bool NoreturnStackElim = false;
64 
65 public:
66   Hexagon::ArchEnum HexagonArchVersion;
67   Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
68   CodeGenOpt::Level OptLevel;
69   /// True if the target should use Back-Skip-Back scheduling. This is the
70   /// default for V60.
71   bool UseBSBScheduling;
72 
73   struct UsrOverflowMutation : public ScheduleDAGMutation {
74     void apply(ScheduleDAGInstrs *DAG) override;
75   };
76   struct HVXMemLatencyMutation : public ScheduleDAGMutation {
77     void apply(ScheduleDAGInstrs *DAG) override;
78   };
79   struct CallMutation : public ScheduleDAGMutation {
80     void apply(ScheduleDAGInstrs *DAG) override;
81   private:
82     bool shouldTFRICallBind(const HexagonInstrInfo &HII,
83           const SUnit &Inst1, const SUnit &Inst2) const;
84   };
85   struct BankConflictMutation : public ScheduleDAGMutation {
86     void apply(ScheduleDAGInstrs *DAG) override;
87   };
88 
89 private:
90   enum HexagonProcFamilyEnum { Others, TinyCore };
91 
92   std::string CPUString;
93   Triple TargetTriple;
94 
95   // The following objects can use the TargetTriple, so they must be
96   // declared after it.
97   HexagonProcFamilyEnum HexagonProcFamily = Others;
98   HexagonInstrInfo InstrInfo;
99   HexagonRegisterInfo RegInfo;
100   HexagonTargetLowering TLInfo;
101   HexagonSelectionDAGInfo TSInfo;
102   HexagonFrameLowering FrameLowering;
103   InstrItineraryData InstrItins;
104 
105 public:
106   HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
107                    const TargetMachine &TM);
108 
109   const Triple &getTargetTriple() const { return TargetTriple; }
110   bool isEnvironmentMusl() const {
111     return TargetTriple.getEnvironment() == Triple::Musl;
112   }
113 
114   /// getInstrItins - Return the instruction itineraries based on subtarget
115   /// selection.
116   const InstrItineraryData *getInstrItineraryData() const override {
117     return &InstrItins;
118   }
119   const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
120   const HexagonRegisterInfo *getRegisterInfo() const override {
121     return &RegInfo;
122   }
123   const HexagonTargetLowering *getTargetLowering() const override {
124     return &TLInfo;
125   }
126   const HexagonFrameLowering *getFrameLowering() const override {
127     return &FrameLowering;
128   }
129   const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
130     return &TSInfo;
131   }
132 
133   HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
134                                                     StringRef FS);
135 
136   /// ParseSubtargetFeatures - Parses features string setting specified
137   /// subtarget options.  Definition of function is auto generated by tblgen.
138   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
139 
140   bool hasV5Ops() const {
141     return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
142   }
143   bool hasV5OpsOnly() const {
144     return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
145   }
146   bool hasV55Ops() const {
147     return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
148   }
149   bool hasV55OpsOnly() const {
150     return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
151   }
152   bool hasV60Ops() const {
153     return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
154   }
155   bool hasV60OpsOnly() const {
156     return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
157   }
158   bool hasV62Ops() const {
159     return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
160   }
161   bool hasV62OpsOnly() const {
162     return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
163   }
164   bool hasV65Ops() const {
165     return getHexagonArchVersion() >= Hexagon::ArchEnum::V65;
166   }
167   bool hasV65OpsOnly() const {
168     return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
169   }
170   bool hasV66Ops() const {
171     return getHexagonArchVersion() >= Hexagon::ArchEnum::V66;
172   }
173   bool hasV66OpsOnly() const {
174     return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
175   }
176   bool hasV67Ops() const {
177     return getHexagonArchVersion() >= Hexagon::ArchEnum::V67;
178   }
179   bool hasV67OpsOnly() const {
180     return getHexagonArchVersion() == Hexagon::ArchEnum::V67;
181   }
182 
183   bool useAudioOps() const { return UseAudioOps; }
184   bool useCompound() const { return UseCompound; }
185   bool useLongCalls() const { return UseLongCalls; }
186   bool useMemops() const { return UseMemops; }
187   bool usePackets() const { return UsePackets; }
188   bool useNewValueJumps() const { return UseNewValueJumps; }
189   bool useNewValueStores() const { return UseNewValueStores; }
190   bool useSmallData() const { return UseSmallData; }
191   bool useUnsafeMath() const { return UseUnsafeMath; }
192   bool useZRegOps() const { return UseZRegOps; }
193 
194   bool isTinyCore() const { return HexagonProcFamily == TinyCore; }
195   bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; }
196 
197   bool useHVXOps() const {
198     return HexagonHVXVersion > Hexagon::ArchEnum::NoArch;
199   }
200   bool useHVXV60Ops() const {
201     return HexagonHVXVersion >= Hexagon::ArchEnum::V60;
202   }
203   bool useHVXV62Ops() const {
204     return HexagonHVXVersion >= Hexagon::ArchEnum::V62;
205   }
206   bool useHVXV65Ops() const {
207     return HexagonHVXVersion >= Hexagon::ArchEnum::V65;
208   }
209   bool useHVXV66Ops() const {
210     return HexagonHVXVersion >= Hexagon::ArchEnum::V66;
211   }
212   bool useHVXV67Ops() const {
213     return HexagonHVXVersion >= Hexagon::ArchEnum::V67;
214   }
215   bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
216   bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
217 
218   bool hasMemNoShuf() const { return HasMemNoShuf; }
219   bool hasReservedR19() const { return ReservedR19; }
220   bool usePredicatedCalls() const;
221 
222   bool noreturnStackElim() const { return NoreturnStackElim; }
223 
224   bool useBSBScheduling() const { return UseBSBScheduling; }
225   bool enableMachineScheduler() const override;
226 
227   // Always use the TargetLowering default scheduler.
228   // FIXME: This will use the vliw scheduler which is probably just hurting
229   // compiler time and will be removed eventually anyway.
230   bool enableMachineSchedDefaultSched() const override { return false; }
231 
232   // For use with PostRAScheduling: get the anti-dependence breaking that should
233   // be performed before post-RA scheduling.
234   AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
235   /// True if the subtarget should run a scheduler after register
236   /// allocation.
237   bool enablePostRAScheduler() const override { return true; }
238 
239   bool enableSubRegLiveness() const override;
240 
241   const std::string &getCPUString () const { return CPUString; }
242 
243   const Hexagon::ArchEnum &getHexagonArchVersion() const {
244     return HexagonArchVersion;
245   }
246 
247   void getPostRAMutations(
248       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
249       const override;
250 
251   void getSMSMutations(
252       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
253       const override;
254 
255   /// Enable use of alias analysis during code generation (during MI
256   /// scheduling, DAGCombine, etc.).
257   bool useAA() const override;
258 
259   /// Perform target specific adjustments to the latency of a schedule
260   /// dependency.
261   void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
262                              SDep &Dep) const override;
263 
264   unsigned getVectorLength() const {
265     assert(useHVXOps());
266     if (useHVX64BOps())
267       return 64;
268     if (useHVX128BOps())
269       return 128;
270     llvm_unreachable("Invalid HVX vector length settings");
271   }
272 
273   ArrayRef<MVT> getHVXElementTypes() const {
274     static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
275     return makeArrayRef(Types);
276   }
277 
278   bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
279     if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
280       return false;
281     MVT ElemTy = VecTy.getVectorElementType();
282     if (!IncludeBool && ElemTy == MVT::i1)
283       return false;
284 
285     unsigned HwLen = getVectorLength();
286     unsigned NumElems = VecTy.getVectorNumElements();
287     ArrayRef<MVT> ElemTypes = getHVXElementTypes();
288 
289     if (IncludeBool && ElemTy == MVT::i1) {
290       // Boolean HVX vector types are formed from regular HVX vector types
291       // by replacing the element type with i1.
292       for (MVT T : ElemTypes)
293         if (NumElems * T.getSizeInBits() == 8*HwLen)
294           return true;
295       return false;
296     }
297 
298     unsigned VecWidth = VecTy.getSizeInBits();
299     if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
300       return false;
301     return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
302   }
303 
304   unsigned getTypeAlignment(MVT Ty) const {
305     if (isHVXVectorType(Ty, true))
306       return getVectorLength();
307     return Ty.getSizeInBits() / 8;
308   }
309 
310   unsigned getL1CacheLineSize() const;
311   unsigned getL1PrefetchDistance() const;
312 
313 private:
314   // Helper function responsible for increasing the latency only.
315   void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
316       const;
317   void restoreLatency(SUnit *Src, SUnit *Dst) const;
318   void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
319   bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
320       SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
321 };
322 
323 } // end namespace llvm
324 
325 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
326