1//=-HexagonScheduleV69.td - HexagonV69 Scheduling Definitions *- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// 11// ScalarItin and HVXItin contain some old itineraries 12// still used by a handful of instructions. Hopefully, we will be able 13// to get rid of them soon. 14def HexagonV69ItinList : DepScalarItinV69, ScalarItin, 15 DepHVXItinV69, HVXItin, PseudoItin { 16 list<InstrItinData> ItinList = 17 !listconcat(DepScalarItinV69_list, ScalarItin_list, 18 DepHVXItinV69_list, HVXItin_list, PseudoItin_list); 19} 20 21def HexagonItinerariesV69 : 22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 23 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 24 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 25 CVI_ALL_NOMEM, CVI_ZW], 26 [Hex_FWD, HVX_FWD], 27 HexagonV69ItinList.ItinList>; 28 29def HexagonModelV69 : SchedMachineModel { 30 // Max issue per cycle == bundle width. 31 let IssueWidth = 4; 32 let Itineraries = HexagonItinerariesV69; 33 let LoadLatency = 1; 34 let CompleteModel = 0; 35} 36 37//===----------------------------------------------------------------------===// 38// Hexagon V69 Resource Definitions - 39//===----------------------------------------------------------------------===// 40 41