1//=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// ScalarItin contains some old itineraries still used by a 10// handful of instructions. Hopefully, we will be able to get rid of them soon. 11 12def HexagonV62ItinList : DepScalarItinV62, ScalarItin, 13 DepHVXItinV62, HVXItin, PseudoItin { 14 list<InstrItinData> ItinList = 15 !listconcat(DepScalarItinV62_list, ScalarItin_list, 16 DepHVXItinV62_list, HVXItin_list, PseudoItin_list); 17} 18 19def HexagonItinerariesV62 : 20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 21 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 22 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 23 CVI_ALL_NOMEM, CVI_ZW], 24 [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>; 25 26def HexagonModelV62 : SchedMachineModel { 27 // Max issue per cycle == bundle width. 28 let IssueWidth = 4; 29 let Itineraries = HexagonItinerariesV62; 30 let LoadLatency = 1; 31 let CompleteModel = 0; 32} 33 34//===----------------------------------------------------------------------===// 35// Hexagon V62 Resource Definitions - 36//===----------------------------------------------------------------------===// 37