1//==- HexagonPatterns.td - Target Description for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def HQ8: PatLeaf<(VecQ8 HvxQR:$R)>; 91def HQ16: PatLeaf<(VecQ16 HvxQR:$R)>; 92def HQ32: PatLeaf<(VecQ32 HvxQR:$R)>; 93 94def HVI8: PatLeaf<(VecI8 HvxVR:$R)>; 95def HVI16: PatLeaf<(VecI16 HvxVR:$R)>; 96def HVI32: PatLeaf<(VecI32 HvxVR:$R)>; 97 98def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>; 99def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>; 100def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>; 101 102def SDTVecVecIntOp: 103 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 104 SDTCisVT<3,i32>]>; 105 106def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 107def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 108 109def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 110 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 111def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 112 113// Pattern fragments to extract the low and high subregisters from a 114// 64-bit value. 115def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>; 116def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>; 117 118def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 119 return isOrEquivalentToAdd(N); 120}]>; 121 122def IsPow2_32: PatLeaf<(i32 imm), [{ 123 uint32_t V = N->getZExtValue(); 124 return isPowerOf2_32(V); 125}]>; 126 127def IsPow2_64: PatLeaf<(i64 imm), [{ 128 uint64_t V = N->getZExtValue(); 129 return isPowerOf2_64(V); 130}]>; 131 132def IsNPow2_32: PatLeaf<(i32 imm), [{ 133 uint32_t NV = ~N->getZExtValue(); 134 return isPowerOf2_32(NV); 135}]>; 136 137def IsPow2_64L: PatLeaf<(i64 imm), [{ 138 uint64_t V = N->getZExtValue(); 139 return isPowerOf2_64(V) && Log2_64(V) < 32; 140}]>; 141 142def IsPow2_64H: PatLeaf<(i64 imm), [{ 143 uint64_t V = N->getZExtValue(); 144 return isPowerOf2_64(V) && Log2_64(V) >= 32; 145}]>; 146 147def IsNPow2_64L: PatLeaf<(i64 imm), [{ 148 uint64_t NV = ~N->getZExtValue(); 149 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 150}]>; 151 152def IsNPow2_64H: PatLeaf<(i64 imm), [{ 153 uint64_t NV = ~N->getZExtValue(); 154 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 155}]>; 156 157class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 158 "uint64_t V = N->getZExtValue();" # 159 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 160>; 161 162def SDEC1: SDNodeXForm<imm, [{ 163 int32_t V = N->getSExtValue(); 164 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 165}]>; 166 167def UDEC1: SDNodeXForm<imm, [{ 168 uint32_t V = N->getZExtValue(); 169 assert(V >= 1); 170 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 171}]>; 172 173def UDEC32: SDNodeXForm<imm, [{ 174 uint32_t V = N->getZExtValue(); 175 assert(V >= 32); 176 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 177}]>; 178 179class Subi<int From>: SDNodeXForm<imm, 180 "int32_t V = " # From # " - N->getSExtValue();" # 181 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 182>; 183 184def Log2_32: SDNodeXForm<imm, [{ 185 uint32_t V = N->getZExtValue(); 186 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 187}]>; 188 189def Log2_64: SDNodeXForm<imm, [{ 190 uint64_t V = N->getZExtValue(); 191 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 192}]>; 193 194def LogN2_32: SDNodeXForm<imm, [{ 195 uint32_t NV = ~N->getZExtValue(); 196 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 197}]>; 198 199def LogN2_64: SDNodeXForm<imm, [{ 200 uint64_t NV = ~N->getZExtValue(); 201 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 202}]>; 203 204def NegImm8: SDNodeXForm<imm, [{ 205 int8_t NV = -N->getSExtValue(); 206 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 207}]>; 208 209def NegImm16: SDNodeXForm<imm, [{ 210 int16_t NV = -N->getSExtValue(); 211 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 212}]>; 213 214def NegImm32: SDNodeXForm<imm, [{ 215 int32_t NV = -N->getSExtValue(); 216 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 217}]>; 218 219 220// Helpers for type promotions/contractions. 221def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 222def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 223def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 224def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 225def ToAext64: OutPatFrag<(ops node:$Rs), 226 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 227 228def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 229 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 230 231def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 232def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 233def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 234def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 235 236// Global address or an aligned constant. 237def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 238def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 239def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 240def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 241 242def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 243def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 244 245// This complex pattern is really only to detect various forms of 246// sign-extension i32->i64. The selected value will be of type i64 247// whose low word is the value being extended. The high word is 248// unspecified. 249def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 250 251def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 252def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 253def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 254 255def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 256def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 257 258def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 259 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 260 261 262// Converters from unary/binary SDNode to PatFrag. 263class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 264class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 265 266class Not2<PatFrag P> 267 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 268 269// If there is a constant operand that feeds the and/or instruction, 270// do not generate the compound instructions. 271// It is not always profitable, as some times we end up with a transfer. 272// Check the below example. 273// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 274// Instead this is preferable. 275// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 276class Su_ni1<PatFrag Op> 277 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 278 if (hasOneUse(N)){ 279 // Check if Op1 is an immediate operand. 280 SDValue Op1 = N->getOperand(1); 281 return !isa<ConstantSDNode>(Op1); 282 } 283 return false;}], 284 Op.OperandTransform>; 285 286class Su<PatFrag Op> 287 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 288 Op.OperandTransform>; 289 290// Main selection macros. 291 292class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 293 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 294 295class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 296 PatFrag RegPred, PatFrag ImmPred> 297 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 298 (MI RegPred:$Rs, imm:$I)>; 299 300class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 301 PatFrag RsPred, PatFrag RtPred = RsPred> 302 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 303 (MI RsPred:$Rs, RtPred:$Rt)>; 304 305class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 306 PatFrag RegPred, PatFrag ImmPred> 307 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 308 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 309 310class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 311 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 312 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 313 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 314 315multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 316 InstHexagon InstA, InstHexagon InstB> { 317 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 318 (InstA Val:$A, Val:$B)>; 319 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 320 (InstB Val:$A, Val:$B)>; 321} 322 323 324// Frags for commonly used SDNodes. 325def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 326def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 327def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 328 329def Rol: pf2<rotl>; 330 331// --(1) Immediate ------------------------------------------------------- 332// 333 334def SDTHexagonCONST32 335 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 336 337def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 338def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 339def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 340def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 341 342def TruncI64ToI32: SDNodeXForm<imm, [{ 343 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 344}]>; 345 346def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 347def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 348 349def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 350def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 351def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 352def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 353def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 354def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 355def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 356// The HVX load patterns also match CP directly. Make sure that if 357// the selection of this opcode changes, it's updated in all places. 358 359def: Pat<(i1 0), (PS_false)>; 360def: Pat<(i1 1), (PS_true)>; 361def: Pat<(i64 imm:$v), (CONST64 imm:$v)>; 362 363def ftoi : SDNodeXForm<fpimm, [{ 364 APInt I = N->getValueAPF().bitcastToAPInt(); 365 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 366 MVT::getIntegerVT(I.getBitWidth())); 367}]>; 368 369def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 370def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 371 372def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 373 374// --(2) Type cast ------------------------------------------------------- 375// 376 377def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 378def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 379 380def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 381def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 382def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 383def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 384 385def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 386def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 387def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 388def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 389 390def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 391def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 392def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 393def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 394 395def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 396def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 397def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 398def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 399 400// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 401def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 402def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 403def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 404def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 405 406multiclass Cast_pat<ValueType Ta, ValueType Tb, RegisterClass RC> { 407 def: Pat<(Tb (bitconvert (Ta RC:$Rs))), (Tb RC:$Rs)>; 408 def: Pat<(Ta (bitconvert (Tb RC:$Rs))), (Ta RC:$Rs)>; 409} 410 411// Bit convert vector types to integers. 412defm: Cast_pat<v4i8, i32, IntRegs>; 413defm: Cast_pat<v2i16, i32, IntRegs>; 414defm: Cast_pat<v8i8, i64, DoubleRegs>; 415defm: Cast_pat<v4i16, i64, DoubleRegs>; 416defm: Cast_pat<v2i32, i64, DoubleRegs>; 417 418 419// --(3) Extend/truncate ------------------------------------------------- 420// 421 422def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 423def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 424def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 425def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 426def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 427 428def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 429def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 430def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 431 432def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 433def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 434def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 435 436let AddedComplexity = 20 in { 437 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 438 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 439} 440 441// Extensions from i1 or vectors of i1. 442def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 443def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 444def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 445def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 446 (C2_muxii PredRegs:$Pu, -1, 0))>; 447 448def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 449def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 450def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 451def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 452def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 453 454def Vsplatpi: OutPatFrag<(ops node:$V), 455 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 456 457def: Pat<(v2i16 (azext V2I1:$Pu)), 458 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 459def: Pat<(v2i32 (azext V2I1:$Pu)), 460 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 461def: Pat<(v4i8 (azext V4I1:$Pu)), 462 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 463def: Pat<(v4i16 (azext V4I1:$Pu)), 464 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 465def: Pat<(v8i8 (azext V8I1:$Pu)), 466 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 467 468def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 469def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 470def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 471def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 472 473def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 474 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 475 476def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 477 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 478 479// Truncate: from vector B copy all 'E'ven 'B'yte elements: 480// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 481def: Pat<(v4i8 (trunc V4I16:$Rs)), 482 (S2_vtrunehb V4I16:$Rs)>; 483 484// Truncate: from vector B copy all 'O'dd 'B'yte elements: 485// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 486// S2_vtrunohb 487 488// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 489// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 490// S2_vtruneh 491 492def: Pat<(v2i16 (trunc V2I32:$Rs)), 493 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 494 495 496// --(4) Logical --------------------------------------------------------- 497// 498 499def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 500def: Pat<(not V8I1:$Ps), (C2_not V8I1:$Ps)>; 501def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 502 503multiclass BoolOpR_RR_pat<InstHexagon MI, PatFrag Op> { 504 def: OpR_RR_pat<MI, Op, i1, I1>; 505 def: OpR_RR_pat<MI, Op, v2i1, V2I1>; 506 def: OpR_RR_pat<MI, Op, v4i1, V4I1>; 507 def: OpR_RR_pat<MI, Op, v8i1, V8I1>; 508} 509 510multiclass BoolAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op> { 511 def: AccRRR_pat<MI, AccOp, Op, I1, I1, I1>; 512 def: AccRRR_pat<MI, AccOp, Op, V2I1, V2I1, V2I1>; 513 def: AccRRR_pat<MI, AccOp, Op, V4I1, V4I1, V4I1>; 514 def: AccRRR_pat<MI, AccOp, Op, V8I1, V8I1, V8I1>; 515} 516 517defm: BoolOpR_RR_pat<C2_and, And>; 518defm: BoolOpR_RR_pat<C2_or, Or>; 519defm: BoolOpR_RR_pat<C2_xor, Xor>; 520defm: BoolOpR_RR_pat<C2_andn, Not2<And>>; 521defm: BoolOpR_RR_pat<C2_orn, Not2<Or>>; 522 523// op(Ps, op(Pt, Pu)) 524defm: BoolAccRRR_pat<C4_and_and, And, Su<And>>; 525defm: BoolAccRRR_pat<C4_and_or, And, Su<Or>>; 526defm: BoolAccRRR_pat<C4_or_and, Or, Su<And>>; 527defm: BoolAccRRR_pat<C4_or_or, Or, Su<Or>>; 528 529// op(Ps, op(Pt, ~Pu)) 530defm: BoolAccRRR_pat<C4_and_andn, And, Su<Not2<And>>>; 531defm: BoolAccRRR_pat<C4_and_orn, And, Su<Not2<Or>>>; 532defm: BoolAccRRR_pat<C4_or_andn, Or, Su<Not2<And>>>; 533defm: BoolAccRRR_pat<C4_or_orn, Or, Su<Not2<Or>>>; 534 535 536// --(5) Compare --------------------------------------------------------- 537// 538 539// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 540// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 541 542def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 543def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 544def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 545 546def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 547 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 548def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 549 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 550 551def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 552 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 553def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 554 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 555 556// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 557// that reverse the order of the operands. 558class RevCmp<PatFrag F> 559 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 560 F.OperandTransform>; 561 562def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 563def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 564def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 565def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 566def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 567def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 568def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 569def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 570def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 571def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 572def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 573def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 574def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 575def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 576def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 577def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 578def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 579def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 580def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 581def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 582def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 583def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 584def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 585def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 586def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 587def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 588def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 589def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 590def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 591def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 592def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 593def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 594def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 595def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 596def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 597def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 598def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 599def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 600def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 601def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 602 603def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 604def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 605def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 606def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 607def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 608def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 609def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 610def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 611def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 612def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 613def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 614 615def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 616def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 617def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 618def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 619def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 620def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 621def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 622def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 623def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 624def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 625def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 626 627// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 628 629def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 630 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 631def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 632 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 633def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 634 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 635 636class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 637 PatFrag RsPred, PatFrag RtPred = RsPred> 638 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 639 (Output RsPred:$Rs, RtPred:$Rt)>; 640 641class Outn<InstHexagon MI> 642 : OutPatFrag<(ops node:$Rs, node:$Rt), 643 (C2_not (MI $Rs, $Rt))>; 644 645def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 646def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 647def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 648def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 649def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 650def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 651def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 652def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 653def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 654def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 655def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 656def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 657def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 658def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 659def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 660def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 661def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 662def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 663def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 664def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 665def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 666def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 667def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 668def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 669def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 670 671let AddedComplexity = 100 in { 672 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 673 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 674 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 675 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 676 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 677 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 678 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 679 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 680} 681 682// PatFrag for AsserZext which takes the original type as a parameter. 683def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 684def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 685class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 686 687multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 688 PatLeaf ImmPred, int Mask> { 689 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 690 (MI I32:$Rs, imm:$I)>; 691 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 692 (MI I32:$Rs, imm:$I)>; 693} 694 695multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 696 PatLeaf ImmPred, int Mask> { 697 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 698 (C2_not (MI I32:$Rs, imm:$I))>; 699 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 700 (C2_not (MI I32:$Rs, imm:$I))>; 701} 702 703multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 704 PatLeaf ImmPred, int Mask> { 705 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 706 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 707 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 708 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 709} 710 711let AddedComplexity = 200 in { 712 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 713 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 714 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 715 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 716 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 717 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 718 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 719 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 720} 721 722def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 723 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 724def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 725 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 726def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 727 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 728def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 729 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 730 731def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 732def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 733def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>; 734def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 735 736// Floating-point comparisons with checks for ordered/unordered status. 737 738class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 739 : OutPatFrag<(ops node:$Rs, node:$Rt), 740 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 741 742class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 743class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 744 745class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 746class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 747 748def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 749def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 750def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 751def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 752def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 753def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 754 755def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 756def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 757def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 758def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 759def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 760def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 761 762def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 763def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 764 765def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 766def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 767 768def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 769def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 770 771 772// --(6) Select ---------------------------------------------------------- 773// 774 775def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 776 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 777def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 778 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 779def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 780 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 781def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 782 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 783 784def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 785 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 786def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 787 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 788def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 789 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 790def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 791 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 792 793// Map from a 64-bit select to an emulated 64-bit mux. 794// Hexagon does not support 64-bit MUXes; so emulate with combines. 795def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 796 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 797 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 798 799def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 800 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 801def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 802 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 803def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 804 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 805def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 806 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 807 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 808 809def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 810 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 811def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 812 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 813 814def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 815 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 816def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 817 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 818 819def: Pat<(select I1:$Pu, V4I8:$Rs, V4I8:$Rt), 820 (LoReg (C2_vmux I1:$Pu, (ToAext64 $Rs), (ToAext64 $Rt)))>; 821def: Pat<(select I1:$Pu, V2I16:$Rs, V2I16:$Rt), 822 (LoReg (C2_vmux I1:$Pu, (ToAext64 $Rs), (ToAext64 $Rt)))>; 823def: Pat<(select I1:$Pu, V2I32:$Rs, V2I32:$Rt), 824 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 825 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 826 827def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 828 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 829def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 830 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 831def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 832 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 833 834// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 835def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw), 836 (C2_or (C2_and I1:$Pu, I1:$Pv), 837 (C2_andn I1:$Pw, I1:$Pu))>; 838 839 840def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 841 return isPositiveHalfWord(N); 842}]>; 843 844multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 845 InstHexagon InstB> { 846 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 847 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 848 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 849 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 850 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 851 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 852} 853 854let AddedComplexity = 200 in { 855 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 856 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 857 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 858 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 859 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 860 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 861 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 862 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 863} 864 865let AddedComplexity = 200 in { 866 defm: SelMinMax_pats<setge, I32, A2_max, A2_min>; 867 defm: SelMinMax_pats<setgt, I32, A2_max, A2_min>; 868 defm: SelMinMax_pats<setle, I32, A2_min, A2_max>; 869 defm: SelMinMax_pats<setlt, I32, A2_min, A2_max>; 870 defm: SelMinMax_pats<setuge, I32, A2_maxu, A2_minu>; 871 defm: SelMinMax_pats<setugt, I32, A2_maxu, A2_minu>; 872 defm: SelMinMax_pats<setule, I32, A2_minu, A2_maxu>; 873 defm: SelMinMax_pats<setult, I32, A2_minu, A2_maxu>; 874 875 defm: SelMinMax_pats<setge, I64, A2_maxp, A2_minp>; 876 defm: SelMinMax_pats<setgt, I64, A2_maxp, A2_minp>; 877 defm: SelMinMax_pats<setle, I64, A2_minp, A2_maxp>; 878 defm: SelMinMax_pats<setlt, I64, A2_minp, A2_maxp>; 879 defm: SelMinMax_pats<setuge, I64, A2_maxup, A2_minup>; 880 defm: SelMinMax_pats<setugt, I64, A2_maxup, A2_minup>; 881 defm: SelMinMax_pats<setule, I64, A2_minup, A2_maxup>; 882 defm: SelMinMax_pats<setult, I64, A2_minup, A2_maxup>; 883} 884 885let AddedComplexity = 100 in { 886 defm: SelMinMax_pats<setolt, F32, F2_sfmin, F2_sfmax>; 887 defm: SelMinMax_pats<setole, F32, F2_sfmin, F2_sfmax>; 888 defm: SelMinMax_pats<setogt, F32, F2_sfmax, F2_sfmin>; 889 defm: SelMinMax_pats<setoge, F32, F2_sfmax, F2_sfmin>; 890} 891 892 893// --(7) Insert/extract -------------------------------------------------- 894// 895 896def SDTHexagonINSERT: 897 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 898 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 899def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 900 901let AddedComplexity = 10 in { 902 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 903 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 904 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 905 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 906} 907def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 908 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 909def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 910 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 911 912def SDTHexagonEXTRACTU 913 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 914 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 915def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 916 917let AddedComplexity = 10 in { 918 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 919 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 920 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 921 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 922} 923def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 924 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 925def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 926 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 927 928def SDTHexagonVSPLAT: 929 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 930 931def HexagonVSPLAT: SDNode<"HexagonISD::VSPLAT", SDTHexagonVSPLAT>; 932 933def: Pat<(v4i8 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 934def: Pat<(v4i16 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 935def: Pat<(v2i32 (HexagonVSPLAT s8_0ImmPred:$s8)), 936 (A2_combineii imm:$s8, imm:$s8)>; 937def: Pat<(v2i32 (HexagonVSPLAT I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 938 939let AddedComplexity = 10 in 940def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 941 Requires<[HasV62]>; 942def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), 943 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 944 945 946// --(8) Shift/permute --------------------------------------------------- 947// 948 949def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 950 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 951 952def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 953 954def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 955 956// The complexity of the combines involving immediates should be greater 957// than the complexity of the combine with two registers. 958let AddedComplexity = 50 in { 959 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 960 (A4_combineri IntRegs:$Rs, imm:$s8)>; 961 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 962 (A4_combineir imm:$s8, IntRegs:$Rs)>; 963} 964 965// The complexity of the combine with two immediates should be greater than 966// the complexity of a combine involving a register. 967let AddedComplexity = 75 in { 968 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 969 (A4_combineii imm:$s8, imm:$u6)>; 970 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 971 (A2_combineii imm:$s8, imm:$S8)>; 972} 973 974def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 975def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 976 (A2_swiz (HiReg $Rss)))>; 977 978def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 979def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 980def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 981 982def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 983def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 984def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 985def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 986def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 987def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 988def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 989def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 990def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 991def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 992def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 993def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 994 995def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 996def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 997def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 998def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 999def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1000def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1001 1002// Funnel shifts. 1003def IsMul8_U3: PatLeaf<(i32 imm), [{ 1004 uint64_t V = N->getZExtValue(); 1005 return V % 8 == 0 && isUInt<3>(V / 8); 1006}]>; 1007 1008def Divu8: SDNodeXForm<imm, [{ 1009 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1010}]>; 1011 1012// Funnel shift-left. 1013def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1014 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1015def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1016 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1017 1018def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1019 (S2_lsr_i_p_or (S2_asl_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1020def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1021 (S2_lsr_r_p_or (S2_asl_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1022 1023// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1024def Divu64_8: SDNodeXForm<imm, [{ 1025 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1026 SDLoc(N), MVT::i32); 1027}]>; 1028 1029// Special cases: 1030let AddedComplexity = 100 in { 1031 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1032 (A2_combine_hl I32:$Rs, I32:$Rt)>; 1033 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1034 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1035} 1036 1037let Predicates = [HasV60], AddedComplexity = 50 in { 1038 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1039 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1040} 1041let AddedComplexity = 30 in { 1042 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1043 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1044 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1045 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1046} 1047def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1048def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1049def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1050def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1051 1052// Funnel shift-right. 1053def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1054 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1055def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1056 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1057 1058def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1059 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1060def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1061 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1062 1063// Special cases: 1064let AddedComplexity = 100 in { 1065 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1066 (A2_combine_hl I32:$Rs, I32:$Rt)>; 1067 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1068 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1069} 1070 1071let Predicates = [HasV60], AddedComplexity = 50 in { 1072 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1073 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1074} 1075let AddedComplexity = 30 in { 1076 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1077 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1078 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1079 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1080} 1081def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1082def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1083def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1084def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1085 1086 1087def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1088 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1089def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1090 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1091 1092// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1093let AddedComplexity = 120 in 1094def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1095 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1096 1097let AddedComplexity = 100 in { 1098 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1099 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1100 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1101 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1102 1103 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1104 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1105 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1106 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1107 1108 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1109 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1110 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1111 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1112 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1113 1114 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1115 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1116 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1117 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1118 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1119 1120 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1121 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1122 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1123 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1124 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1125 1126 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1127 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1128 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1129 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1130 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1131 1132 let Predicates = [HasV60] in { 1133 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1134 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1135 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1136 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1137 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1138 1139 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1140 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1141 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1142 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1143 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1144 } 1145} 1146 1147let AddedComplexity = 100 in { 1148 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1149 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1150 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1151 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1152 1153 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1154 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1155 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1156 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1157 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1158 1159 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1160 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1161 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1162 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1163 1164 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1165 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1166 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1167 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1168 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1169 1170 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1171 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1172 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1173 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1174 1175 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1176 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1177 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1178 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1179 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1180} 1181 1182 1183class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1184 PatFrag RegPred, PatFrag ImmPred> 1185 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1186 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1187 1188let AddedComplexity = 200 in { 1189 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1190 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1191 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1192 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1193 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1194 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1195 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1196 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1197} 1198 1199// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1200// two 32-bit words into a 64-bit word. 1201let AddedComplexity = 200 in 1202def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1203 (Combinew I32:$a, I32:$b)>; 1204 1205def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1206 (Zext64 (and I32:$a, (i32 65535)))), 1207 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1208 (shl (Aext64 I32:$d), (i32 48))), 1209 (Combinew (A2_combine_ll I32:$d, I32:$c), 1210 (A2_combine_ll I32:$b, I32:$a))>; 1211 1212let AddedComplexity = 200 in { 1213 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1214 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1215 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1216 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1217 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1218 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1219 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1220 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1221} 1222 1223def SDTHexagonVShift 1224 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1225 1226def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1227def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1228def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1229 1230def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1231def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1232def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1233def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1234def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1235def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1236 1237def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1238def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1239def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1240def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1241def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1242def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1243 1244def: Pat<(sra V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))), 1245 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1246def: Pat<(srl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))), 1247 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1248def: Pat<(shl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))), 1249 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1250def: Pat<(sra V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), 1251 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1252def: Pat<(srl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), 1253 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1254def: Pat<(shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), 1255 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1256 1257def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1258 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1259def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1260 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1261def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1262 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1263def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1264 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1265def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1266 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1267def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1268 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1269 1270 1271// --(9) Arithmetic/bitwise ---------------------------------------------- 1272// 1273 1274def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1275def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1276def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1277def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1278def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1279 1280def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1281def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1282 1283def: Pat<(fabs F64:$Rs), 1284 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1285 (i32 (LoReg $Rs)))>; 1286def: Pat<(fneg F64:$Rs), 1287 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1288 (i32 (LoReg $Rs)))>; 1289 1290def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1291def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1292def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1293def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1294 1295def: OpR_RR_pat<A2_add, Add, i32, I32>; 1296def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1297def: OpR_RR_pat<A2_and, And, i32, I32>; 1298def: OpR_RR_pat<A2_or, Or, i32, I32>; 1299def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1300def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1301def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1302def: OpR_RR_pat<A2_andp, And, i64, I64>; 1303def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1304def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1305def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1306def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1307 1308def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1309def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1310 1311def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1312def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1313def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1314def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1315def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1316def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1317 1318def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1319def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1320def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1321def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1322def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1323def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1324def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1325def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1326def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1327def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1328def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1329def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1330def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1331def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1332def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1333 1334def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1335def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1336def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1337def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1338def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1339 1340// Arithmetic on predicates. 1341def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1342def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1343def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1344def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1345def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1346def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1347def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1348def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1349def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1350def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1351def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1352def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1353 1354def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1355def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1356def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1357def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1358def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1359 1360let Predicates = [HasV66] in { 1361 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1362 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1363} 1364 1365// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1366// over add-add with individual multiplies as inputs. 1367let AddedComplexity = 10 in { 1368 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1369 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1370 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1371 let Predicates = [HasV66] in 1372 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1373} 1374 1375def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1376def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1377def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1378 1379// Mulh for vectors 1380// 1381def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1382 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1383 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1384 1385def: Pat<(v2i32 (mulhs V2I32:$Rs, V2I32:$Rt)), 1386 (Combinew (M2_mpy_up (HiReg $Rs), (HiReg $Rt)), 1387 (M2_mpy_up (LoReg $Rt), (LoReg $Rt)))>; 1388 1389def Mulhub: 1390 OutPatFrag<(ops node:$Rss, node:$Rtt), 1391 (Combinew (S2_vtrunohb (M5_vmpybuu (HiReg $Rss), (HiReg $Rtt))), 1392 (S2_vtrunohb (M5_vmpybuu (LoReg $Rss), (LoReg $Rtt))))>; 1393 1394// Equivalent of byte-wise arithmetic shift right by 7 in v8i8. 1395def Asr7: 1396 OutPatFrag<(ops node:$Rss), (C2_mask (C2_not (A4_vcmpbgti $Rss, 0)))>; 1397 1398def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), 1399 (Mulhub $Rss, $Rtt)>; 1400 1401def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), 1402 (A2_vsubub 1403 (Mulhub $Rss, $Rtt), 1404 (A2_vaddub (A2_andp V8I8:$Rss, (Asr7 $Rtt)), 1405 (A2_andp V8I8:$Rtt, (Asr7 $Rss))))>; 1406 1407def Mpysh: 1408 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1409def Mpyshh: 1410 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (HiReg $Rss), (HiReg $Rtt))>; 1411def Mpyshl: 1412 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (LoReg $Rss), (LoReg $Rtt))>; 1413 1414def Mulhsh: 1415 OutPatFrag<(ops node:$Rss, node:$Rtt), 1416 (Combinew (A2_combine_hh (HiReg (Mpyshh $Rss, $Rtt)), 1417 (LoReg (Mpyshh $Rss, $Rtt))), 1418 (A2_combine_hh (HiReg (Mpyshl $Rss, $Rtt)), 1419 (LoReg (Mpyshl $Rss, $Rtt))))>; 1420 1421def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh $Rss, $Rtt)>; 1422 1423def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1424 (A2_vaddh 1425 (Mulhsh $Rss, $Rtt), 1426 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1427 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1428 1429 1430def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1431 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1432 1433def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1434 int64_t V = N->getSExtValue(); 1435 return -255 <= V && V <= 0; 1436}]>; 1437 1438// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1439def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1440 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1441 1442def: Pat<(add Sext64:$Rs, I64:$Rt), 1443 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1444 1445def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1446def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1447def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1448def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1449def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1450def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1451def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1452def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1453def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1454def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1455 1456// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1457// one argument matches the patterns below, and with the other argument 1458// matches S2_asl_r_r_or, etc, prefer the patterns below. 1459let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1460 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1461 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1462 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1463} 1464 1465// S4_addaddi and S4_subaddi don't have tied operands, so give them 1466// a bit of preference. 1467let AddedComplexity = 30 in { 1468 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1469 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1470 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1471 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1472 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1473 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1474 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1475 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1476 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1477 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1478} 1479 1480def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1481 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1482def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1483 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1484def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1485 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1486 1487 1488def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1489 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1490def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1491 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1492 1493def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1494 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1495def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1496 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1497def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1498 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1499 1500def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1501 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1502def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1503 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1504def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1505 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1506def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1507 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1508def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1509 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1510def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1511 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1512 1513// Add halfword. 1514def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1515 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1516def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1517 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1518def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1519 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1520 1521// Subtract halfword. 1522def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1523 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1524def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1525 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1526def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1527 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1528 1529def: Pat<(mul I64:$Rss, I64:$Rtt), 1530 (Combinew 1531 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1532 (LoReg $Rss), 1533 (HiReg $Rtt)), 1534 (LoReg $Rtt), 1535 (HiReg $Rss)), 1536 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1537 1538def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1539 (A2_addp 1540 (M2_dpmpyuu_acc_s0 1541 (S2_lsr_i_p 1542 (A2_addp 1543 (M2_dpmpyuu_acc_s0 1544 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1545 (HiReg $Rss), 1546 (LoReg $Rtt)), 1547 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1548 32), 1549 (HiReg $Rss), 1550 (HiReg $Rtt)), 1551 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1552 1553// Multiply 64-bit unsigned and use upper result. 1554def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1555 1556// Multiply 64-bit signed and use upper result. 1557// 1558// For two signed 64-bit integers A and B, let A' and B' denote A and B 1559// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1560// sign bit of A (and identically for B). With this notation, the signed 1561// product A*B can be written as: 1562// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1563// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1564// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1565// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1566 1567// Clear the sign bit in a 64-bit register. 1568def ClearSign : OutPatFrag<(ops node:$Rss), 1569 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1570 1571def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1572 (A2_subp 1573 (MulHU $Rss, $Rtt), 1574 (A2_addp 1575 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1576 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1577 1578// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1579// will put the immediate addend into a register, while these instructions will 1580// use it directly. Such a construct does not appear in the middle of a gep, 1581// where M2_macsip would be preferable. 1582let AddedComplexity = 20 in { 1583 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1584 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1585 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1586 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1587} 1588 1589// Keep these instructions less preferable to M2_macsip/M2_macsin. 1590def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1591 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1592def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1593 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1594def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1595 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1596 1597 1598def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1599 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1600def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1601 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1602def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx), 1603 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1604 1605 1606def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1607 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1608def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1609 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1610 1611// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1612// we use the double add v8i8, and use only the low part of the result. 1613def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1614 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1615def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1616 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1617 1618// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1619// half-words, and saturates the result to a 32-bit value, except the 1620// saturation never happens (it can only occur with scaling). 1621def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1622 (LoReg (S2_vtrunewh (A2_combineii 0, 0), 1623 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1624def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1625 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1626 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1627 1628// Multiplies two v4i8 vectors. 1629def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1630 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1631 1632// Multiplies two v8i8 vectors. 1633def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1634 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1635 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1636 1637 1638// --(10) Bit ------------------------------------------------------------ 1639// 1640 1641// Count leading zeros. 1642def: Pat<(ctlz I32:$Rs), (S2_cl0 I32:$Rs)>; 1643def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1644 1645// Count trailing zeros. 1646def: Pat<(cttz I32:$Rs), (S2_ct0 I32:$Rs)>; 1647def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1648 1649// Count leading ones. 1650def: Pat<(ctlz (not I32:$Rs)), (S2_cl1 I32:$Rs)>; 1651def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1652 1653// Count trailing ones. 1654def: Pat<(cttz (not I32:$Rs)), (S2_ct1 I32:$Rs)>; 1655def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1656 1657// Define leading/trailing patterns that require zero-extensions to 64 bits. 1658def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1659def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1660def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1661def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1662 1663def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1664def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1665 1666def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1667def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1668 1669let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1670 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1671 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1672 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1673 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1674 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1675 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1676 1677 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1678 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1679 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1680 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1681 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1682 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1683} 1684 1685// Clr/set/toggle bit for 64-bit values with immediate bit index. 1686let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1687 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1688 (Combinew (i32 (HiReg $Rss)), 1689 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1690 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1691 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1692 (i32 (LoReg $Rss)))>; 1693 1694 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1695 (Combinew (i32 (HiReg $Rss)), 1696 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1697 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1698 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1699 (i32 (LoReg $Rss)))>; 1700 1701 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1702 (Combinew (i32 (HiReg $Rss)), 1703 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1704 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1705 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1706 (i32 (LoReg $Rss)))>; 1707} 1708 1709let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1710 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1711 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1712 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1713 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1714 def: Pat<(i1 (trunc I32:$Rs)), 1715 (S2_tstbit_i IntRegs:$Rs, 0)>; 1716 def: Pat<(i1 (trunc I64:$Rs)), 1717 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1718} 1719 1720let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1721 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1722 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1723 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1724 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 1725} 1726 1727let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 1728def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 1729 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 1730 1731def SDTTestBit: 1732 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1733def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 1734 1735def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 1736 (S2_tstbit_i I32:$Rs, imm:$u5)>; 1737def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 1738 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1739 1740let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1741 def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1742 (S4_ntstbit_i I32:$Rs, imm:$u5)>; 1743 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1744 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 1745} 1746 1747// Add extra complexity to prefer these instructions over bitsset/bitsclr. 1748// The reason is that tstbit/ntstbit can be folded into a compound instruction: 1749// if ([!]tstbit(...)) jump ... 1750let AddedComplexity = 100 in 1751def: Pat<(i1 (setne (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))), 1752 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1753 1754let AddedComplexity = 100 in 1755def: Pat<(i1 (seteq (and I32:$Rs, (i32 IsPow2_32:$u5)), (i32 0))), 1756 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1757 1758// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 1759// represented as a compare against "value & 0xFF", which is an exact match 1760// for cmpb (same for cmph). The patterns below do not contain any additional 1761// complexity that would make them preferable, and if they were actually used 1762// instead of cmpb/cmph, they would result in a compare against register that 1763// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 1764def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1765 (C4_nbitsclri I32:$Rs, imm:$u6)>; 1766def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 1767 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 1768def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 1769 (C4_nbitsset I32:$Rs, I32:$Rt)>; 1770 1771// Special patterns to address certain cases where the "top-down" matching 1772// algorithm would cause suboptimal selection. 1773 1774let AddedComplexity = 100 in { 1775 // Avoid A4_rcmp[n]eqi in these cases: 1776 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1777 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1778 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1779 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1780} 1781 1782// --(11) PIC ------------------------------------------------------------ 1783// 1784 1785def SDT_HexagonAtGot 1786 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1787def SDT_HexagonAtPcrel 1788 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 1789 1790// AT_GOT address-of-GOT, address-of-global, offset-in-global 1791def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 1792// AT_PCREL address-of-global 1793def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 1794 1795def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 1796 (L2_loadri_io I32:$got, imm:$addr)>; 1797def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 1798 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 1799def: Pat<(HexagonAtPcrel I32:$addr), 1800 (C4_addipc imm:$addr)>; 1801 1802// The HVX load patterns also match AT_PCREL directly. Make sure that 1803// if the selection of this opcode changes, it's updated in all places. 1804 1805 1806// --(12) Load ----------------------------------------------------------- 1807// 1808 1809def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1810 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1811}]>; 1812def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1813 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1814}]>; 1815 1816def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1817 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1818}]>; 1819def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1820 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1821}]>; 1822 1823def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1824 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1825}]>; 1826def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1827 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1828}]>; 1829 1830// Patterns to select load-indexed: Rs + Off. 1831// - frameindex [+ imm], 1832multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1833 InstHexagon MI> { 1834 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1835 (VT (MI AddrFI:$fi, imm:$Off))>; 1836 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1837 (VT (MI AddrFI:$fi, imm:$Off))>; 1838 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 1839} 1840 1841// Patterns to select load-indexed: Rs + Off. 1842// - base reg [+ imm] 1843multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1844 InstHexagon MI> { 1845 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 1846 (VT (MI IntRegs:$Rs, imm:$Off))>; 1847 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 1848 (VT (MI IntRegs:$Rs, imm:$Off))>; 1849 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 1850} 1851 1852// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 1853multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1854 InstHexagon MI> { 1855 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 1856 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 1857} 1858 1859// Patterns to select load reg indexed: Rs + Off with a value modifier. 1860// - frameindex [+ imm] 1861multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1862 PatLeaf ImmPred, InstHexagon MI> { 1863 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1864 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 1865 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1866 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 1867 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 1868} 1869 1870// Patterns to select load reg indexed: Rs + Off with a value modifier. 1871// - base reg [+ imm] 1872multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1873 PatLeaf ImmPred, InstHexagon MI> { 1874 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 1875 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 1876 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 1877 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 1878 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 1879} 1880 1881// Patterns to select load reg indexed: Rs + Off with a value modifier. 1882// Combines Loadxfim + Loadxgim. 1883multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1884 PatLeaf ImmPred, InstHexagon MI> { 1885 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 1886 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 1887} 1888 1889// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 1890class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 1891 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 1892 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 1893 1894// Pattern to select load reg reg-indexed: Rs + Rt<<0. 1895class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 1896 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 1897 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 1898 1899// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 1900class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1901 InstHexagon MI> 1902 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 1903 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 1904 1905// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 1906class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1907 InstHexagon MI> 1908 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 1909 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 1910 1911// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 1912// Don't match for u2==0, instead use reg+imm for those cases. 1913class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 1914 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 1915 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 1916 1917class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 1918 InstHexagon MI> 1919 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 1920 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 1921 1922// Pattern to select load absolute. 1923class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 1924 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 1925 1926// Pattern to select load absolute with value modifier. 1927class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 1928 InstHexagon MI> 1929 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 1930 1931 1932let AddedComplexity = 20 in { 1933 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 1934 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 1935 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 1936 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 1937 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 1938 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 1939 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 1940 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 1941 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 1942 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 1943 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 1944 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 1945 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 1946 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 1947 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 1948 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 1949 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 1950 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 1951 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 1952 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 1953 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 1954 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 1955 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 1956 // No sextloadi1. 1957 1958 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 1959 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 1960 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 1961 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 1962} 1963 1964let AddedComplexity = 30 in { 1965 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 1966 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 1967 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 1968 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 1969 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 1970 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 1971 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 1972 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 1973 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 1974 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 1975 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 1976} 1977 1978let AddedComplexity = 60 in { 1979 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 1980 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 1981 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 1982 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 1983 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 1984 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 1985 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 1986 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 1987 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 1988 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 1989 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 1990 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 1991 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 1992 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 1993 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 1994 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 1995 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 1996 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 1997 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 1998 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 1999 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2000 2001 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2002 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2003 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2004 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2005 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2006 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2007 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2008 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2009 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2010} 2011 2012let AddedComplexity = 40 in { 2013 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2014 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2015 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2016 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2017 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2018 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2019 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2020 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2021 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2022 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2023 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2024 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2025 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2026 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2027 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2028} 2029 2030let AddedComplexity = 20 in { 2031 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2032 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2033 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2034 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2035 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2036 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2037 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2038 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2039 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2040 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2041 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2042 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2043 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2044 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2045 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2046} 2047 2048let AddedComplexity = 40 in { 2049 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2050 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2051 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2052 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2053 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2054 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2055 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2056 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2057 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2058} 2059 2060let AddedComplexity = 20 in { 2061 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2062 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2063 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2064 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2065 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2066 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2067 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2068 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2069 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2070} 2071 2072// Absolute address 2073 2074let AddedComplexity = 60 in { 2075 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2076 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2077 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2078 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2079 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2080 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2081 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2082 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2083 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2084 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2085 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2086 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2087 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2088 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2089 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2090 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2091 2092 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2093 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2094 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2095 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2096} 2097 2098let AddedComplexity = 30 in { 2099 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2100 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2101 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2102 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2103 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2104 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2105 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2106 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2107 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2108 2109 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2110 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2111} 2112 2113// GP-relative address 2114 2115let AddedComplexity = 100 in { 2116 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2117 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2118 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2119 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2120 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2121 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2122 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2123 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2124 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2125 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2126 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2127 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2128 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2129 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2130 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2131 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2132 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2133 2134 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2135 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2136 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2137 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2138} 2139 2140let AddedComplexity = 70 in { 2141 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2142 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2143 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2144 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2145 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2146 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2147 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2148 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2149 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2150 2151 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2152 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2153} 2154 2155 2156// Sign-extending loads of i1 need to replicate the lowest bit throughout 2157// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should 2158// do the trick. 2159let AddedComplexity = 20 in 2160def: Pat<(i32 (sextloadi1 I32:$Rs)), 2161 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>; 2162 2163// Patterns for loads of i1: 2164def: Pat<(i1 (load AddrFI:$fi)), 2165 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2166def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2167 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2168def: Pat<(i1 (load I32:$Rs)), 2169 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2170 2171 2172// --(13) Store ---------------------------------------------------------- 2173// 2174 2175class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2176 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2177 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2178 2179def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2180def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2181def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2182def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2183 2184// Patterns for generating stores, where the address takes different forms: 2185// - frameindex, 2186// - frameindex + offset, 2187// - base + offset, 2188// - simple (base address without offset). 2189// These would usually be used together (via Storexi_pat defined below), but 2190// in some cases one may want to apply different properties (such as 2191// AddedComplexity) to the individual patterns. 2192class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2193 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2194 2195multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2196 InstHexagon MI> { 2197 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2198 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2199 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2200 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2201} 2202 2203multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2204 InstHexagon MI> { 2205 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2206 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2207 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2208 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2209} 2210 2211class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2212 : Pat<(Store Value:$Rt, I32:$Rs), 2213 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2214 2215// Patterns for generating stores, where the address takes different forms, 2216// and where the value being stored is transformed through the value modifier 2217// ValueMod. The address forms are same as above. 2218class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2219 InstHexagon MI> 2220 : Pat<(Store Value:$Rs, AddrFI:$fi), 2221 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2222 2223multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2224 PatFrag ValueMod, InstHexagon MI> { 2225 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2226 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2227 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2228 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2229} 2230 2231multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2232 PatFrag ValueMod, InstHexagon MI> { 2233 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2234 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2235 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2236 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2237} 2238 2239class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2240 InstHexagon MI> 2241 : Pat<(Store Value:$Rt, I32:$Rs), 2242 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2243 2244multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2245 InstHexagon MI> { 2246 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2247 def: Storexi_fi_pat <Store, Value, MI>; 2248 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2249} 2250 2251multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2252 PatFrag ValueMod, InstHexagon MI> { 2253 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2254 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2255 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2256} 2257 2258// Reg<<S + Imm 2259class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2260 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2261 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2262 2263// Reg<<S + Reg 2264class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2265 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2266 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2267 2268// Reg + Reg 2269class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2270 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2271 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2272 2273class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2274 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2275 2276class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2277 InstHexagon MI> 2278 : Pat<(Store Value:$val, Addr:$addr), 2279 (MI Addr:$addr, (ValueMod Value:$val))>; 2280 2281// Regular stores in the DAG have two operands: value and address. 2282// Atomic stores also have two, but they are reversed: address, value. 2283// To use atomic stores with the patterns, they need to have their operands 2284// swapped. This relies on the knowledge that the F.Fragment uses names 2285// "ptr" and "val". 2286class AtomSt<PatFrag F> 2287 : PatFrag<(ops node:$val, node:$ptr), !head(F.Fragments), F.PredicateCode, 2288 F.OperandTransform> { 2289 let IsAtomic = F.IsAtomic; 2290 let MemoryVT = F.MemoryVT; 2291} 2292 2293 2294def IMM_BYTE : SDNodeXForm<imm, [{ 2295 // -1 can be represented as 255, etc. 2296 // assigning to a byte restores our desired signed value. 2297 int8_t imm = N->getSExtValue(); 2298 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2299}]>; 2300 2301def IMM_HALF : SDNodeXForm<imm, [{ 2302 // -1 can be represented as 65535, etc. 2303 // assigning to a short restores our desired signed value. 2304 int16_t imm = N->getSExtValue(); 2305 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2306}]>; 2307 2308def IMM_WORD : SDNodeXForm<imm, [{ 2309 // -1 can be represented as 4294967295, etc. 2310 // Currently, it's not doing this. But some optimization 2311 // might convert -1 to a large +ve number. 2312 // assigning to a word restores our desired signed value. 2313 int32_t imm = N->getSExtValue(); 2314 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2315}]>; 2316 2317def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2318def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2319def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2320 2321// Even though the offset is not extendable in the store-immediate, we 2322// can still generate the fi# in the base address. If the final offset 2323// is not valid for the instruction, we will replace it with a scratch 2324// register. 2325class SmallStackStore<PatFrag Store> 2326 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2327 return isSmallStackStore(cast<StoreSDNode>(N)); 2328}]>; 2329 2330// This is the complement of SmallStackStore. 2331class LargeStackStore<PatFrag Store> 2332 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2333 return !isSmallStackStore(cast<StoreSDNode>(N)); 2334}]>; 2335 2336// Preferred addressing modes for various combinations of stored value 2337// and address computation. 2338// For stores where the address and value are both immediates, prefer 2339// store-immediate. The reason is that the constant-extender optimization 2340// can replace store-immediate with a store-register, but there is nothing 2341// to generate a store-immediate out of a store-register. 2342// 2343// C R F F+C R+C R+R R<<S+C R<<S+R 2344// --+-------+-----+-----+------+-----+-----+--------+-------- 2345// C | imm | imm | imm | imm | imm | rr | ur | rr 2346// R | abs* | io | io | io | io | rr | ur | rr 2347// 2348// (*) Absolute or GP-relative. 2349// 2350// Note that any expression can be matched by Reg. In particular, an immediate 2351// can always be placed in a register, so patterns checking for Imm should 2352// have a higher priority than the ones involving Reg that could also match. 2353// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2354// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2355// Reg alone. 2356// 2357// The order in which the different combinations are tried: 2358// 2359// C F R F+C R+C R+R R<<S+C R<<S+R 2360// --+-------+-----+-----+------+-----+-----+--------+-------- 2361// C | 1 | 6 | - | 5 | 9 | - | - | - 2362// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2363 2364 2365// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2366// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2367// implies that Reg is also a proper multiple of 4. To still generate a 2368// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2369 2370def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2371 int64_t v = (int64_t)N->getSExtValue(); 2372 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2373}]>; 2374def RoundTo8 : SDNodeXForm<imm, [{ 2375 int32_t Imm = N->getSExtValue(); 2376 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2377}]>; 2378 2379let AddedComplexity = 150 in 2380def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2381 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2382 2383class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2384 : Pat<(Store Value:$val, anyimm:$addr), 2385 (MI (ToI32 $addr), 0, Value:$val)>; 2386class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2387 InstHexagon MI> 2388 : Pat<(Store Value:$val, anyimm:$addr), 2389 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2390 2391let AddedComplexity = 140 in { 2392 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2393 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2394 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2395 2396 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2397 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2398 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2399} 2400 2401// GP-relative address 2402let AddedComplexity = 120 in { 2403 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2404 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2405 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2406 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2407 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2408 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2409 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2410 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2411 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2412 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2413 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2414 def: Storea_pat<AtomSt<atomic_store_8>, I32, addrgp, S2_storerbgp>; 2415 def: Storea_pat<AtomSt<atomic_store_16>, I32, addrgp, S2_storerhgp>; 2416 def: Storea_pat<AtomSt<atomic_store_32>, I32, addrgp, S2_storerigp>; 2417 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, addrgp, S2_storerigp>; 2418 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, addrgp, S2_storerigp>; 2419 def: Storea_pat<AtomSt<atomic_store_64>, I64, addrgp, S2_storerdgp>; 2420 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, addrgp, S2_storerdgp>; 2421 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, addrgp, S2_storerdgp>; 2422 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, addrgp, S2_storerdgp>; 2423 2424 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2425 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2426 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2427 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2428} 2429 2430// Absolute address 2431let AddedComplexity = 110 in { 2432 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2433 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2434 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2435 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2436 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2437 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2438 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2439 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2440 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2441 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2442 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2443 def: Storea_pat<AtomSt<atomic_store_8>, I32, anyimm0, PS_storerbabs>; 2444 def: Storea_pat<AtomSt<atomic_store_16>, I32, anyimm1, PS_storerhabs>; 2445 def: Storea_pat<AtomSt<atomic_store_32>, I32, anyimm2, PS_storeriabs>; 2446 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, PS_storeriabs>; 2447 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, PS_storeriabs>; 2448 def: Storea_pat<AtomSt<atomic_store_64>, I64, anyimm3, PS_storerdabs>; 2449 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, PS_storerdabs>; 2450 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, PS_storerdabs>; 2451 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, PS_storerdabs>; 2452 2453 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2454 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2455 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2456 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2457} 2458 2459// Reg<<S + Imm 2460let AddedComplexity = 100 in { 2461 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2462 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2463 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2464 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2465 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2466 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2467 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2468 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2469 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2470 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2471 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2472 2473 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2474 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2475} 2476 2477// Reg<<S + Reg 2478let AddedComplexity = 90 in { 2479 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2480 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2481 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2482 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2483 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2484 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2485 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2486 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2487 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2488 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2489 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2490 2491 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2492 (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2493} 2494 2495class SS_<PatFrag F> : SmallStackStore<F>; 2496class LS_<PatFrag F> : LargeStackStore<F>; 2497 2498multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2499 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2500} 2501multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2502 defm: Storexi_fi_add_pat<S, V, O, I>; 2503} 2504 2505// Fi+Imm, store-immediate 2506let AddedComplexity = 80 in { 2507 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2508 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2509 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2510 2511 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2512 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2513 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2514 2515 // For large-stack stores, generate store-register (prefer explicit Fi 2516 // in the address). 2517 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2518 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2519 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2520} 2521 2522// Fi, store-immediate 2523let AddedComplexity = 70 in { 2524 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2525 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2526 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2527 2528 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2529 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2530 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2531 2532 // For large-stack stores, generate store-register (prefer explicit Fi 2533 // in the address). 2534 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2535 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2536 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2537} 2538 2539// Fi+Imm, Fi, store-register 2540let AddedComplexity = 60 in { 2541 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2542 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2543 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2544 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2545 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2546 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2547 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2548 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2549 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2550 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2551 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2552 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2553 2554 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2555 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2556 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2557 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2558 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2559 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2560 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2561 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2562 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2563 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2564 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2565 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2566} 2567 2568 2569multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2570 defm: Storexim_add_pat<S, V, O, M, I>; 2571} 2572multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2573 defm: Storexi_add_pat<S, V, O, I>; 2574} 2575 2576// Reg+Imm, store-immediate 2577let AddedComplexity = 50 in { 2578 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2579 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2580 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2581 2582 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2583 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2584 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2585} 2586 2587// Reg+Imm, store-register 2588let AddedComplexity = 40 in { 2589 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2590 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2591 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2592 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2593 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2594 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2595 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2596 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2597 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2598 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2599 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2600 2601 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2602 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2603 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2604 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2605 2606 defm: Storexi_pat<AtomSt<atomic_store_8>, I32, anyimm0, S2_storerb_io>; 2607 defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>; 2608 defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>; 2609 defm: Storexi_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, S2_storeri_io>; 2610 defm: Storexi_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, S2_storeri_io>; 2611 defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>; 2612 defm: Storexi_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, S2_storerd_io>; 2613 defm: Storexi_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, S2_storerd_io>; 2614 defm: Storexi_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, S2_storerd_io>; 2615} 2616 2617// Reg+Reg 2618let AddedComplexity = 30 in { 2619 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2620 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2621 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2622 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2623 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2624 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2625 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2626 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2627 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2628 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2629 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2630 2631 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2632 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2633} 2634 2635// Reg, store-immediate 2636let AddedComplexity = 20 in { 2637 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2638 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2639 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2640 2641 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2642 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2643 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2644} 2645 2646// Reg, store-register 2647let AddedComplexity = 10 in { 2648 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2649 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2650 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2651 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2652 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2653 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2654 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2655 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2656 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2657 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2658 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2659 2660 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2661 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2662 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2663 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2664 2665 def: Storexi_base_pat<AtomSt<atomic_store_8>, I32, S2_storerb_io>; 2666 def: Storexi_base_pat<AtomSt<atomic_store_16>, I32, S2_storerh_io>; 2667 def: Storexi_base_pat<AtomSt<atomic_store_32>, I32, S2_storeri_io>; 2668 def: Storexi_base_pat<AtomSt<atomic_store_32>, V4I8, S2_storeri_io>; 2669 def: Storexi_base_pat<AtomSt<atomic_store_32>, V2I16, S2_storeri_io>; 2670 def: Storexi_base_pat<AtomSt<atomic_store_64>, I64, S2_storerd_io>; 2671 def: Storexi_base_pat<AtomSt<atomic_store_64>, V8I8, S2_storerd_io>; 2672 def: Storexi_base_pat<AtomSt<atomic_store_64>, V4I16, S2_storerd_io>; 2673 def: Storexi_base_pat<AtomSt<atomic_store_64>, V2I32, S2_storerd_io>; 2674} 2675 2676 2677// --(14) Memop ---------------------------------------------------------- 2678// 2679 2680def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2681 int8_t V = N->getSExtValue(); 2682 return -32 < V && V <= -1; 2683}]>; 2684 2685def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2686 int16_t V = N->getSExtValue(); 2687 return -32 < V && V <= -1; 2688}]>; 2689 2690def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2691 int64_t V = N->getSExtValue(); 2692 return -31 <= V && V <= -1; 2693}]>; 2694 2695def IsNPow2_8 : PatLeaf<(i32 imm), [{ 2696 uint8_t NV = ~N->getZExtValue(); 2697 return isPowerOf2_32(NV); 2698}]>; 2699 2700def IsNPow2_16 : PatLeaf<(i32 imm), [{ 2701 uint16_t NV = ~N->getZExtValue(); 2702 return isPowerOf2_32(NV); 2703}]>; 2704 2705def Log2_8 : SDNodeXForm<imm, [{ 2706 uint8_t V = N->getZExtValue(); 2707 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2708}]>; 2709 2710def Log2_16 : SDNodeXForm<imm, [{ 2711 uint16_t V = N->getZExtValue(); 2712 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2713}]>; 2714 2715def LogN2_8 : SDNodeXForm<imm, [{ 2716 uint8_t NV = ~N->getZExtValue(); 2717 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2718}]>; 2719 2720def LogN2_16 : SDNodeXForm<imm, [{ 2721 uint16_t NV = ~N->getZExtValue(); 2722 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2723}]>; 2724 2725def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 2726 2727multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2728 InstHexagon MI> { 2729 // Addr: i32 2730 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 2731 (MI I32:$Rs, 0, I32:$A)>; 2732 // Addr: fi 2733 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 2734 (MI AddrFI:$Rs, 0, I32:$A)>; 2735} 2736 2737multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2738 SDNode Oper, InstHexagon MI> { 2739 // Addr: i32 2740 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 2741 (add I32:$Rs, ImmPred:$Off)), 2742 (MI I32:$Rs, imm:$Off, I32:$A)>; 2743 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 2744 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2745 (MI I32:$Rs, imm:$Off, I32:$A)>; 2746 // Addr: fi 2747 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2748 (add AddrFI:$Rs, ImmPred:$Off)), 2749 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2750 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2751 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2752 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2753} 2754 2755multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2756 SDNode Oper, InstHexagon MI> { 2757 let Predicates = [UseMEMOPS] in { 2758 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 2759 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 2760 } 2761} 2762 2763let AddedComplexity = 200 in { 2764 // add reg 2765 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 2766 /*anyext*/ L4_add_memopb_io>; 2767 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 2768 /*sext*/ L4_add_memopb_io>; 2769 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 2770 /*zext*/ L4_add_memopb_io>; 2771 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 2772 /*anyext*/ L4_add_memoph_io>; 2773 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 2774 /*sext*/ L4_add_memoph_io>; 2775 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 2776 /*zext*/ L4_add_memoph_io>; 2777 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 2778 2779 // sub reg 2780 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 2781 /*anyext*/ L4_sub_memopb_io>; 2782 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 2783 /*sext*/ L4_sub_memopb_io>; 2784 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 2785 /*zext*/ L4_sub_memopb_io>; 2786 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 2787 /*anyext*/ L4_sub_memoph_io>; 2788 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 2789 /*sext*/ L4_sub_memoph_io>; 2790 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 2791 /*zext*/ L4_sub_memoph_io>; 2792 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 2793 2794 // and reg 2795 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 2796 /*anyext*/ L4_and_memopb_io>; 2797 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 2798 /*sext*/ L4_and_memopb_io>; 2799 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 2800 /*zext*/ L4_and_memopb_io>; 2801 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 2802 /*anyext*/ L4_and_memoph_io>; 2803 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 2804 /*sext*/ L4_and_memoph_io>; 2805 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 2806 /*zext*/ L4_and_memoph_io>; 2807 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 2808 2809 // or reg 2810 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 2811 /*anyext*/ L4_or_memopb_io>; 2812 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 2813 /*sext*/ L4_or_memopb_io>; 2814 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 2815 /*zext*/ L4_or_memopb_io>; 2816 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 2817 /*anyext*/ L4_or_memoph_io>; 2818 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 2819 /*sext*/ L4_or_memoph_io>; 2820 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 2821 /*zext*/ L4_or_memoph_io>; 2822 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 2823} 2824 2825 2826multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2827 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 2828 // Addr: i32 2829 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 2830 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 2831 // Addr: fi 2832 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 2833 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 2834} 2835 2836multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2837 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 2838 InstHexagon MI> { 2839 // Addr: i32 2840 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 2841 (add I32:$Rs, ImmPred:$Off)), 2842 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2843 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 2844 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2845 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2846 // Addr: fi 2847 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 2848 (add AddrFI:$Rs, ImmPred:$Off)), 2849 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2850 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 2851 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2852 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2853} 2854 2855multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2856 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 2857 InstHexagon MI> { 2858 let Predicates = [UseMEMOPS] in { 2859 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 2860 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 2861 } 2862} 2863 2864let AddedComplexity = 220 in { 2865 // add imm 2866 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2867 /*anyext*/ IdImm, L4_iadd_memopb_io>; 2868 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2869 /*sext*/ IdImm, L4_iadd_memopb_io>; 2870 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2871 /*zext*/ IdImm, L4_iadd_memopb_io>; 2872 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 2873 /*anyext*/ IdImm, L4_iadd_memoph_io>; 2874 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 2875 /*sext*/ IdImm, L4_iadd_memoph_io>; 2876 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 2877 /*zext*/ IdImm, L4_iadd_memoph_io>; 2878 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 2879 L4_iadd_memopw_io>; 2880 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 2881 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 2882 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 2883 /*sext*/ NegImm8, L4_iadd_memopb_io>; 2884 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 2885 /*zext*/ NegImm8, L4_iadd_memopb_io>; 2886 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 2887 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 2888 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 2889 /*sext*/ NegImm16, L4_iadd_memoph_io>; 2890 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 2891 /*zext*/ NegImm16, L4_iadd_memoph_io>; 2892 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 2893 L4_iadd_memopw_io>; 2894 2895 // sub imm 2896 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 2897 /*anyext*/ IdImm, L4_isub_memopb_io>; 2898 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 2899 /*sext*/ IdImm, L4_isub_memopb_io>; 2900 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 2901 /*zext*/ IdImm, L4_isub_memopb_io>; 2902 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 2903 /*anyext*/ IdImm, L4_isub_memoph_io>; 2904 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 2905 /*sext*/ IdImm, L4_isub_memoph_io>; 2906 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 2907 /*zext*/ IdImm, L4_isub_memoph_io>; 2908 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 2909 L4_isub_memopw_io>; 2910 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 2911 /*anyext*/ NegImm8, L4_isub_memopb_io>; 2912 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 2913 /*sext*/ NegImm8, L4_isub_memopb_io>; 2914 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 2915 /*zext*/ NegImm8, L4_isub_memopb_io>; 2916 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 2917 /*anyext*/ NegImm16, L4_isub_memoph_io>; 2918 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 2919 /*sext*/ NegImm16, L4_isub_memoph_io>; 2920 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 2921 /*zext*/ NegImm16, L4_isub_memoph_io>; 2922 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 2923 L4_isub_memopw_io>; 2924 2925 // clrbit imm 2926 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 2927 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 2928 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 2929 /*sext*/ LogN2_8, L4_iand_memopb_io>; 2930 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 2931 /*zext*/ LogN2_8, L4_iand_memopb_io>; 2932 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 2933 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 2934 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 2935 /*sext*/ LogN2_16, L4_iand_memoph_io>; 2936 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 2937 /*zext*/ LogN2_16, L4_iand_memoph_io>; 2938 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 2939 LogN2_32, L4_iand_memopw_io>; 2940 2941 // setbit imm 2942 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 2943 /*anyext*/ Log2_8, L4_ior_memopb_io>; 2944 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 2945 /*sext*/ Log2_8, L4_ior_memopb_io>; 2946 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 2947 /*zext*/ Log2_8, L4_ior_memopb_io>; 2948 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 2949 /*anyext*/ Log2_16, L4_ior_memoph_io>; 2950 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 2951 /*sext*/ Log2_16, L4_ior_memoph_io>; 2952 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 2953 /*zext*/ Log2_16, L4_ior_memoph_io>; 2954 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 2955 Log2_32, L4_ior_memopw_io>; 2956} 2957 2958 2959// --(15) Call ----------------------------------------------------------- 2960// 2961 2962// Pseudo instructions. 2963def SDT_SPCallSeqStart 2964 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2965def SDT_SPCallSeqEnd 2966 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2967 2968def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 2969 [SDNPHasChain, SDNPOutGlue]>; 2970def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 2971 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 2972 2973def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 2974 2975def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 2976 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 2977def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 2978 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 2979def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 2980 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 2981 2982def: Pat<(callseq_start timm:$amt, timm:$amt2), 2983 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 2984def: Pat<(callseq_end timm:$amt1, timm:$amt2), 2985 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 2986 2987def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 2988def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 2989def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 2990 2991def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 2992def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 2993def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 2994def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 2995 2996def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 2997def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 2998def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 2999 3000def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 3001 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3002def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3003 3004def: Pat<(retflag), (PS_jmpret (i32 R31))>; 3005def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3006 3007 3008// --(16) Branch --------------------------------------------------------- 3009// 3010 3011def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3012def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3013 3014def: Pat<(brcond I1:$Pu, bb:$dst), 3015 (J2_jumpt I1:$Pu, bb:$dst)>; 3016def: Pat<(brcond (not I1:$Pu), bb:$dst), 3017 (J2_jumpf I1:$Pu, bb:$dst)>; 3018def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3019 (J2_jumpf I1:$Pu, bb:$dst)>; 3020def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3021 (J2_jumpf I1:$Pu, bb:$dst)>; 3022def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3023 (J2_jumpt I1:$Pu, bb:$dst)>; 3024 3025 3026// --(17) Misc ----------------------------------------------------------- 3027 3028 3029// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3030// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3031// The isdigit transformation relies on two 'clever' aspects: 3032// 1) The data type is unsigned which allows us to eliminate a zero test after 3033// biasing the expression by 48. We are depending on the representation of 3034// the unsigned types, and semantics. 3035// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3036// 3037// For the C code: 3038// retval = (c >= '0' && c <= '9') ? 1 : 0; 3039// The code is transformed upstream of llvm into 3040// retval = (c-48) < 10 ? 1 : 0; 3041 3042def u7_0PosImmPred : ImmLeaf<i32, [{ 3043 // True if the immediate fits in an 7-bit unsigned field and is positive. 3044 return Imm > 0 && isUInt<7>(Imm); 3045}]>; 3046 3047let AddedComplexity = 139 in 3048def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3049 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3050 3051let AddedComplexity = 100 in 3052def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3053 (i32 (extloadi8 (add I32:$b, 3))), 3054 24, 8), 3055 (i32 16)), 3056 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3057 (zextloadi8 I32:$b)), 3058 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3059 3060 3061// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3062// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3063// We don't really want either one here. 3064def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3065def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3066 [SDNPHasChain]>; 3067 3068def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3069 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3070def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3071 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3072 3073def SDTHexagonALLOCA 3074 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3075def HexagonALLOCA 3076 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3077 3078def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3079 (PS_alloca IntRegs:$Rs, imm:$A)>; 3080 3081def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3082def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3083 3084def: Pat<(trap), (PS_crash)>; 3085 3086// Read cycle counter. 3087def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3088def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3089 [SDNPHasChain]>; 3090 3091def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3092 3093// The declared return value of the store-locked intrinsics is i32, but 3094// the instructions actually define i1. To avoid register copies from 3095// IntRegs to PredRegs and back, fold the entire pattern checking the 3096// result against true/false. 3097let AddedComplexity = 100 in { 3098 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3099 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3100 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3101 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3102 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3103 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3104 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3105 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3106} 3107