1//==- HexagonPatterns.td - Target Description for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def HQ8: PatLeaf<(VecQ8 HvxQR:$R)>; 91def HQ16: PatLeaf<(VecQ16 HvxQR:$R)>; 92def HQ32: PatLeaf<(VecQ32 HvxQR:$R)>; 93 94def HVI8: PatLeaf<(VecI8 HvxVR:$R)>; 95def HVI16: PatLeaf<(VecI16 HvxVR:$R)>; 96def HVI32: PatLeaf<(VecI32 HvxVR:$R)>; 97 98def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>; 99def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>; 100def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>; 101 102def SDTVecLeaf: 103 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 104def SDTVecVecIntOp: 105 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 106 SDTCisVT<3,i32>]>; 107 108def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>; 109def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>; 110def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 111def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 112 113def ptrue: PatFrag<(ops), (HexagonPTRUE)>; 114def pfalse: PatFrag<(ops), (HexagonPFALSE)>; 115def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>; 116 117def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 118 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 119def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 120 121// Pattern fragments to extract the low and high subregisters from a 122// 64-bit value. 123def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>; 124def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>; 125 126def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 127 return isOrEquivalentToAdd(N); 128}]>; 129 130def IsPow2_32: PatLeaf<(i32 imm), [{ 131 uint32_t V = N->getZExtValue(); 132 return isPowerOf2_32(V); 133}]>; 134 135def IsPow2_64: PatLeaf<(i64 imm), [{ 136 uint64_t V = N->getZExtValue(); 137 return isPowerOf2_64(V); 138}]>; 139 140def IsNPow2_32: PatLeaf<(i32 imm), [{ 141 uint32_t NV = ~N->getZExtValue(); 142 return isPowerOf2_32(NV); 143}]>; 144 145def IsPow2_64L: PatLeaf<(i64 imm), [{ 146 uint64_t V = N->getZExtValue(); 147 return isPowerOf2_64(V) && Log2_64(V) < 32; 148}]>; 149 150def IsPow2_64H: PatLeaf<(i64 imm), [{ 151 uint64_t V = N->getZExtValue(); 152 return isPowerOf2_64(V) && Log2_64(V) >= 32; 153}]>; 154 155def IsNPow2_64L: PatLeaf<(i64 imm), [{ 156 uint64_t NV = ~N->getZExtValue(); 157 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 158}]>; 159 160def IsNPow2_64H: PatLeaf<(i64 imm), [{ 161 uint64_t NV = ~N->getZExtValue(); 162 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 163}]>; 164 165class IsULE<int Width, int Arg>: PatLeaf<(i32 imm), 166 "uint64_t V = N->getZExtValue();" # 167 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";" 168>; 169 170class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 171 "uint64_t V = N->getZExtValue();" # 172 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 173>; 174 175def SDEC1: SDNodeXForm<imm, [{ 176 int32_t V = N->getSExtValue(); 177 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 178}]>; 179 180def UDEC1: SDNodeXForm<imm, [{ 181 uint32_t V = N->getZExtValue(); 182 assert(V >= 1); 183 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 184}]>; 185 186def UDEC32: SDNodeXForm<imm, [{ 187 uint32_t V = N->getZExtValue(); 188 assert(V >= 32); 189 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 190}]>; 191 192class Subi<int From>: SDNodeXForm<imm, 193 "int32_t V = " # From # " - N->getSExtValue();" # 194 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 195>; 196 197def Log2_32: SDNodeXForm<imm, [{ 198 uint32_t V = N->getZExtValue(); 199 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 200}]>; 201 202def Log2_64: SDNodeXForm<imm, [{ 203 uint64_t V = N->getZExtValue(); 204 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 205}]>; 206 207def LogN2_32: SDNodeXForm<imm, [{ 208 uint32_t NV = ~N->getZExtValue(); 209 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 210}]>; 211 212def LogN2_64: SDNodeXForm<imm, [{ 213 uint64_t NV = ~N->getZExtValue(); 214 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 215}]>; 216 217def NegImm8: SDNodeXForm<imm, [{ 218 int8_t NV = -N->getSExtValue(); 219 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 220}]>; 221 222def NegImm16: SDNodeXForm<imm, [{ 223 int16_t NV = -N->getSExtValue(); 224 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 225}]>; 226 227def NegImm32: SDNodeXForm<imm, [{ 228 int32_t NV = -N->getSExtValue(); 229 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 230}]>; 231 232 233// Helpers for type promotions/contractions. 234def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 235def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 236def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 237def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 238def ToAext64: OutPatFrag<(ops node:$Rs), 239 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 240 241def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 242 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 243 244def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 245def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 246def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 247def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 248 249// Global address or an aligned constant. 250def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 251def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 252def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 253def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 254 255def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 256def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 257 258// This complex pattern is really only to detect various forms of 259// sign-extension i32->i64. The selected value will be of type i64 260// whose low word is the value being extended. The high word is 261// unspecified. 262def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 263 264def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 265def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 266def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 267 268def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 269def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 270 271def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 272 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 273 274 275// Converters from unary/binary SDNode to PatFrag. 276class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 277class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 278 279class Not2<PatFrag P> 280 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 281 282// If there is a constant operand that feeds the and/or instruction, 283// do not generate the compound instructions. 284// It is not always profitable, as some times we end up with a transfer. 285// Check the below example. 286// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 287// Instead this is preferable. 288// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 289class Su_ni1<PatFrag Op> 290 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 291 if (hasOneUse(N)){ 292 // Check if Op1 is an immediate operand. 293 SDValue Op1 = N->getOperand(1); 294 return !isa<ConstantSDNode>(Op1); 295 } 296 return false;}], 297 Op.OperandTransform>; 298 299class Su<PatFrag Op> 300 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 301 Op.OperandTransform>; 302 303// Main selection macros. 304 305class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 306 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 307 308class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 309 PatFrag RegPred, PatFrag ImmPred> 310 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 311 (MI RegPred:$Rs, imm:$I)>; 312 313class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 314 PatFrag RsPred, PatFrag RtPred = RsPred> 315 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 316 (MI RsPred:$Rs, RtPred:$Rt)>; 317 318class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 319 PatFrag RegPred, PatFrag ImmPred> 320 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 321 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 322 323class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 324 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 325 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 326 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 327 328multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 329 InstHexagon InstA, InstHexagon InstB> { 330 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 331 (InstA Val:$A, Val:$B)>; 332 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 333 (InstB Val:$A, Val:$B)>; 334} 335 336multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, 337 PatFrag Sel, PatFrag CmpOp, 338 ValueType CmpType, PatFrag CmpPred> { 339 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 340 CmpPred:$Vt, CmpPred:$Vs), 341 (PickT CmpPred:$Vs, CmpPred:$Vt)>; 342 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 343 CmpPred:$Vs, CmpPred:$Vt), 344 (PickS CmpPred:$Vs, CmpPred:$Vt)>; 345} 346 347// Bitcasts between same-size vector types are no-ops, except for the 348// actual type change. 349multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> { 350 def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>; 351 def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; 352} 353 354 355// Frags for commonly used SDNodes. 356def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 357def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 358def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 359 360def Rol: pf2<rotl>; 361 362// --(1) Immediate ------------------------------------------------------- 363// 364 365def Imm64Lo: SDNodeXForm<imm, [{ 366 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()), 367 SDLoc(N), MVT::i32); 368}]>; 369def Imm64Hi: SDNodeXForm<imm, [{ 370 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32), 371 SDLoc(N), MVT::i32); 372}]>; 373 374 375def SDTHexagonCONST32 376 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 377 378def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 379def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 380def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 381def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 382 383def TruncI64ToI32: SDNodeXForm<imm, [{ 384 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 385}]>; 386 387def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 388def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 389 390def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 391def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 392def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 393def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 394def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 395def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 396def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 397// The HVX load patterns also match CP directly. Make sure that if 398// the selection of this opcode changes, it's updated in all places. 399 400def: Pat<(i1 0), (PS_false)>; 401def: Pat<(i1 1), (PS_true)>; 402def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, 403 Requires<[UseSmallData,NotOptTinyCore]>; 404def: Pat<(i64 imm:$v), 405 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; 406 407def ftoi : SDNodeXForm<fpimm, [{ 408 APInt I = N->getValueAPF().bitcastToAPInt(); 409 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 410 MVT::getIntegerVT(I.getBitWidth())); 411}]>; 412 413def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 414def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 415 416def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 417 418// --(2) Type cast ------------------------------------------------------- 419// 420 421def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 422def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 423 424def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 425def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 426def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 427def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 428 429def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 430def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 431def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 432def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 433 434def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 435def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 436def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 437def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 438 439def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 440def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 441def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 442def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 443 444// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 445def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 446def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 447def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 448def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 449 450// Bit convert 32- and 64-bit types. 451// All of these are bitcastable to one another: i32, v2i16, v4i8. 452defm: NopCast_pat<i32, v2i16, IntRegs>; 453defm: NopCast_pat<i32, v4i8, IntRegs>; 454defm: NopCast_pat<v2i16, v4i8, IntRegs>; 455// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 456defm: NopCast_pat<i64, v2i32, DoubleRegs>; 457defm: NopCast_pat<i64, v4i16, DoubleRegs>; 458defm: NopCast_pat<i64, v8i8, DoubleRegs>; 459defm: NopCast_pat<v2i32, v4i16, DoubleRegs>; 460defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 461defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 462 463 464// --(3) Extend/truncate ------------------------------------------------- 465// 466 467def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 468def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 469def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 470def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 471def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 472 473def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 474def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 475def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 476 477def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 478def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 479def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 480 481let AddedComplexity = 20 in { 482 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 483 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 484} 485 486// Extensions from i1 or vectors of i1. 487def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 488def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 489def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 490def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 491 (C2_muxii PredRegs:$Pu, -1, 0))>; 492 493def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 494def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 495def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 496def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 497def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 498 499def Vsplatpi: OutPatFrag<(ops node:$V), 500 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 501 502def: Pat<(v2i16 (azext V2I1:$Pu)), 503 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 504def: Pat<(v2i32 (azext V2I1:$Pu)), 505 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 506def: Pat<(v4i8 (azext V4I1:$Pu)), 507 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 508def: Pat<(v4i16 (azext V4I1:$Pu)), 509 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 510def: Pat<(v8i8 (azext V8I1:$Pu)), 511 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 512 513def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 514def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 515def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 516def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 517 518def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 519 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 520 521def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 522 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 523 524// Truncate: from vector B copy all 'E'ven 'B'yte elements: 525// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 526def: Pat<(v4i8 (trunc V4I16:$Rs)), 527 (S2_vtrunehb V4I16:$Rs)>; 528 529// Truncate: from vector B copy all 'O'dd 'B'yte elements: 530// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 531// S2_vtrunohb 532 533// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 534// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 535// S2_vtruneh 536 537def: Pat<(v2i16 (trunc V2I32:$Rs)), 538 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 539 540 541// --(4) Logical --------------------------------------------------------- 542// 543 544def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 545def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>; 546def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>; 547def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>; 548def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 549 550multiclass BoolOpR_RR_pat<InstHexagon MI, PatFrag Op> { 551 def: OpR_RR_pat<MI, Op, i1, I1>; 552 def: OpR_RR_pat<MI, Op, v2i1, V2I1>; 553 def: OpR_RR_pat<MI, Op, v4i1, V4I1>; 554 def: OpR_RR_pat<MI, Op, v8i1, V8I1>; 555} 556 557multiclass BoolAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op> { 558 def: AccRRR_pat<MI, AccOp, Op, I1, I1, I1>; 559 def: AccRRR_pat<MI, AccOp, Op, V2I1, V2I1, V2I1>; 560 def: AccRRR_pat<MI, AccOp, Op, V4I1, V4I1, V4I1>; 561 def: AccRRR_pat<MI, AccOp, Op, V8I1, V8I1, V8I1>; 562} 563 564defm: BoolOpR_RR_pat<C2_and, And>; 565defm: BoolOpR_RR_pat<C2_or, Or>; 566defm: BoolOpR_RR_pat<C2_xor, Xor>; 567defm: BoolOpR_RR_pat<C2_andn, Not2<And>>; 568defm: BoolOpR_RR_pat<C2_orn, Not2<Or>>; 569 570// op(Ps, op(Pt, Pu)) 571defm: BoolAccRRR_pat<C4_and_and, And, Su<And>>; 572defm: BoolAccRRR_pat<C4_and_or, And, Su<Or>>; 573defm: BoolAccRRR_pat<C4_or_and, Or, Su<And>>; 574defm: BoolAccRRR_pat<C4_or_or, Or, Su<Or>>; 575 576// op(Ps, op(Pt, ~Pu)) 577defm: BoolAccRRR_pat<C4_and_andn, And, Su<Not2<And>>>; 578defm: BoolAccRRR_pat<C4_and_orn, And, Su<Not2<Or>>>; 579defm: BoolAccRRR_pat<C4_or_andn, Or, Su<Not2<And>>>; 580defm: BoolAccRRR_pat<C4_or_orn, Or, Su<Not2<Or>>>; 581 582 583// --(5) Compare --------------------------------------------------------- 584// 585 586// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 587// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 588 589def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 590def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 591def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 592 593def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 594 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 595def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 596 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 597 598def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 599 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 600def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 601 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 602 603// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 604// that reverse the order of the operands. 605class RevCmp<PatFrag F> 606 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 607 F.OperandTransform>; 608 609def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 610def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 611def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 612def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 613def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 614def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 615def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 616def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 617def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 618def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 619def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 620def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 621def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 622def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 623def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 624def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 625def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 626def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 627def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 628def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 629def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 630def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 631def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 632def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 633def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 634def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 635def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 636def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 637def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 638def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 639def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 640def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 641def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 642def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 643def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 644def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 645def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 646def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 647def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 648def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 649 650def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 651def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 652def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 653def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 654def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 655def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 656def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 657def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 658def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 659def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 660def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 661 662def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 663def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 664def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 665def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 666def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 667def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 668def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 669def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 670def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 671def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 672def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 673 674// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 675 676def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 677 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 678def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 679 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 680def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 681 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 682 683class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 684 PatFrag RsPred, PatFrag RtPred = RsPred> 685 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 686 (Output RsPred:$Rs, RtPred:$Rt)>; 687 688class Outn<InstHexagon MI> 689 : OutPatFrag<(ops node:$Rs, node:$Rt), 690 (C2_not (MI $Rs, $Rt))>; 691 692def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 693def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 694def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 695def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 696def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 697def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 698def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 699def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 700def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 701def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 702def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 703def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 704def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 705def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 706def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 707def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 708def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 709def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 710def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 711def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 712def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 713def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 714def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 715def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 716def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 717 718let AddedComplexity = 100 in { 719 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 720 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 721 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 722 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 723 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 724 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 725 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 726 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 727} 728 729// PatFrag for AsserZext which takes the original type as a parameter. 730def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 731def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 732class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 733 734multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 735 PatLeaf ImmPred, int Mask> { 736 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 737 (MI I32:$Rs, imm:$I)>; 738 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 739 (MI I32:$Rs, imm:$I)>; 740} 741 742multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 743 PatLeaf ImmPred, int Mask> { 744 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 745 (C2_not (MI I32:$Rs, imm:$I))>; 746 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 747 (C2_not (MI I32:$Rs, imm:$I))>; 748} 749 750multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 751 PatLeaf ImmPred, int Mask> { 752 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 753 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 754 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 755 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 756} 757 758let AddedComplexity = 200 in { 759 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 760 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 761 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 762 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 763 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 764 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 765 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 766 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 767} 768 769def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 770 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 771def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 772 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 773def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 774 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 775def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 776 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 777 778def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 779def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 780def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>; 781def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 782 783// Floating-point comparisons with checks for ordered/unordered status. 784 785class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 786 : OutPatFrag<(ops node:$Rs, node:$Rt), 787 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 788 789class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 790class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 791 792class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 793class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 794 795def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 796def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 797def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 798def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 799def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 800def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 801 802def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 803def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 804def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 805def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 806def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 807def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 808 809def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 810def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 811 812def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 813def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 814 815def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 816def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 817 818 819// --(6) Select ---------------------------------------------------------- 820// 821 822def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 823 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 824def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 825 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 826def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 827 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 828def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 829 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 830 831def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 832 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 833def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 834 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 835def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 836 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 837def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 838 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 839 840// Map from a 64-bit select to an emulated 64-bit mux. 841// Hexagon does not support 64-bit MUXes; so emulate with combines. 842def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 843 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 844 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 845 846def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 847 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 848def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 849 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 850def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 851 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 852def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 853 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 854 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 855 856def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 857 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 858def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 859 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 860 861def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 862 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 863def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 864 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 865 866def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 867 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 868def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 869 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 870def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 871 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 872 873def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt), 874 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>; 875def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt), 876 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>; 877def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt), 878 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>; 879 880 881// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 882def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw), 883 (C2_or (C2_and I1:$Pu, I1:$Pv), 884 (C2_andn I1:$Pw, I1:$Pu))>; 885 886 887def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 888 return isPositiveHalfWord(N); 889}]>; 890 891multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 892 InstHexagon InstB> { 893 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 894 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 895 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 896 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 897 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 898 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 899} 900 901let AddedComplexity = 200 in { 902 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 903 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 904 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 905 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 906 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 907 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 908 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 909 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 910} 911 912let AddedComplexity = 200 in { 913 defm: MinMax_pats<A2_min, A2_max, select, setgt, i1, I32>; 914 defm: MinMax_pats<A2_min, A2_max, select, setge, i1, I32>; 915 defm: MinMax_pats<A2_max, A2_min, select, setlt, i1, I32>; 916 defm: MinMax_pats<A2_max, A2_min, select, setle, i1, I32>; 917 defm: MinMax_pats<A2_minu, A2_maxu, select, setugt, i1, I32>; 918 defm: MinMax_pats<A2_minu, A2_maxu, select, setuge, i1, I32>; 919 defm: MinMax_pats<A2_maxu, A2_minu, select, setult, i1, I32>; 920 defm: MinMax_pats<A2_maxu, A2_minu, select, setule, i1, I32>; 921 922 defm: MinMax_pats<A2_minp, A2_maxp, select, setgt, i1, I64>; 923 defm: MinMax_pats<A2_minp, A2_maxp, select, setge, i1, I64>; 924 defm: MinMax_pats<A2_maxp, A2_minp, select, setlt, i1, I64>; 925 defm: MinMax_pats<A2_maxp, A2_minp, select, setle, i1, I64>; 926 defm: MinMax_pats<A2_minup, A2_maxup, select, setugt, i1, I64>; 927 defm: MinMax_pats<A2_minup, A2_maxup, select, setuge, i1, I64>; 928 defm: MinMax_pats<A2_maxup, A2_minup, select, setult, i1, I64>; 929 defm: MinMax_pats<A2_maxup, A2_minup, select, setule, i1, I64>; 930} 931 932let AddedComplexity = 100 in { 933 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>; 934 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>; 935 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>; 936 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; 937} 938 939let AddedComplexity = 100, Predicates = [HasV67] in { 940 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; 941 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; 942 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; 943 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; 944} 945 946defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setgt, v8i1, V8I8>; 947defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setge, v8i1, V8I8>; 948defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setgt, v4i1, V4I16>; 949defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setge, v4i1, V4I16>; 950defm: MinMax_pats<A2_vminw, A2_vmaxw, vselect, setgt, v2i1, V2I32>; 951defm: MinMax_pats<A2_vminw, A2_vmaxw, vselect, setge, v2i1, V2I32>; 952defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setugt, v8i1, V8I8>; 953defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setuge, v8i1, V8I8>; 954defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setugt, v4i1, V4I16>; 955defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setuge, v4i1, V4I16>; 956defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setugt, v2i1, V2I32>; 957defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setuge, v2i1, V2I32>; 958 959// --(7) Insert/extract -------------------------------------------------- 960// 961 962def SDTHexagonINSERT: 963 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 964 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 965def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 966 967let AddedComplexity = 10 in { 968 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 969 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 970 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 971 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 972} 973def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 974 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 975def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 976 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 977 978def SDTHexagonEXTRACTU 979 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 980 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 981def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 982 983let AddedComplexity = 10 in { 984 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 985 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 986 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 987 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 988} 989def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 990 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 991def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 992 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 993 994def SDTHexagonVSPLAT: 995 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 996 997def HexagonVSPLAT: SDNode<"HexagonISD::VSPLAT", SDTHexagonVSPLAT>; 998 999def: Pat<(v4i8 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 1000def: Pat<(v4i16 (HexagonVSPLAT I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 1001def: Pat<(v2i32 (HexagonVSPLAT s8_0ImmPred:$s8)), 1002 (A2_combineii imm:$s8, imm:$s8)>; 1003def: Pat<(v2i32 (HexagonVSPLAT I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 1004 1005let AddedComplexity = 10 in 1006def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 1007 Requires<[HasV62]>; 1008def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), 1009 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 1010 1011 1012// --(8) Shift/permute --------------------------------------------------- 1013// 1014 1015def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 1016 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 1017 1018def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 1019 1020def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 1021 1022// The complexity of the combines involving immediates should be greater 1023// than the complexity of the combine with two registers. 1024let AddedComplexity = 50 in { 1025 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 1026 (A4_combineri IntRegs:$Rs, imm:$s8)>; 1027 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 1028 (A4_combineir imm:$s8, IntRegs:$Rs)>; 1029} 1030 1031// The complexity of the combine with two immediates should be greater than 1032// the complexity of a combine involving a register. 1033let AddedComplexity = 75 in { 1034 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 1035 (A4_combineii imm:$s8, imm:$u6)>; 1036 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 1037 (A2_combineii imm:$s8, imm:$S8)>; 1038} 1039 1040def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 1041def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 1042 (A2_swiz (HiReg $Rss)))>; 1043 1044def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 1045def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 1046def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1047 1048def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 1049def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1050def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 1051def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 1052def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1053def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 1054def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 1055def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1056def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 1057def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 1058def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1059def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 1060 1061def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 1062def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1063def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 1064def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 1065def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1066def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1067 1068// Funnel shifts. 1069def IsMul8_U3: PatLeaf<(i32 imm), [{ 1070 uint64_t V = N->getZExtValue(); 1071 return V % 8 == 0 && isUInt<3>(V / 8); 1072}]>; 1073 1074def Divu8: SDNodeXForm<imm, [{ 1075 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1076}]>; 1077 1078// Funnel shift-left. 1079def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1080 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1081def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1082 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1083 1084def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1085 (S2_lsr_i_p_or (S2_asl_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1086def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1087 (S2_lsr_r_p_or (S2_asl_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1088 1089// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1090def Divu64_8: SDNodeXForm<imm, [{ 1091 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1092 SDLoc(N), MVT::i32); 1093}]>; 1094 1095// Special cases: 1096let AddedComplexity = 100 in { 1097 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1098 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1099 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1100 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1101} 1102 1103let Predicates = [HasV60], AddedComplexity = 50 in { 1104 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1105 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1106} 1107let AddedComplexity = 30 in { 1108 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1109 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1110 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1111 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1112} 1113def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1114def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1115def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1116def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1117 1118// Funnel shift-right. 1119def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1120 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1121def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1122 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1123 1124def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1125 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1126def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1127 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1128 1129// Special cases: 1130let AddedComplexity = 100 in { 1131 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1132 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1133 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1134 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1135} 1136 1137let Predicates = [HasV60], AddedComplexity = 50 in { 1138 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1139 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1140} 1141let AddedComplexity = 30 in { 1142 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1143 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1144 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1145 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1146} 1147def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1148def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1149def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1150def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1151 1152 1153def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1154 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1155def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1156 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1157 1158// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1159let AddedComplexity = 120 in 1160def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1161 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1162 1163let AddedComplexity = 100 in { 1164 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1165 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1166 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1167 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1168 1169 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1170 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1171 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1172 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1173 1174 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1175 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1176 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1177 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1178 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1179 1180 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1181 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1182 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1183 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1184 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1185 1186 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1187 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1188 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1189 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1190 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1191 1192 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1193 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1194 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1195 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1196 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1197 1198 let Predicates = [HasV60] in { 1199 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1200 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1201 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1202 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1203 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1204 1205 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1206 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1207 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1208 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1209 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1210 } 1211} 1212 1213let AddedComplexity = 100 in { 1214 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1215 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1216 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1217 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1218 1219 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1220 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1221 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1222 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1223 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1224 1225 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1226 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1227 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1228 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1229 1230 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1231 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1232 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1233 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1234 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1235 1236 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1237 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1238 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1239 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1240 1241 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1242 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1243 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1244 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1245 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1246} 1247 1248 1249class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1250 PatFrag RegPred, PatFrag ImmPred> 1251 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1252 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1253 1254let AddedComplexity = 200, Predicates = [UseCompound] in { 1255 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1256 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1257 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1258 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1259 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1260 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1261 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1262 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1263} 1264 1265// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1266// two 32-bit words into a 64-bit word. 1267let AddedComplexity = 200 in 1268def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1269 (Combinew I32:$a, I32:$b)>; 1270 1271def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1272 (Zext64 (and I32:$a, (i32 65535)))), 1273 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1274 (shl (Aext64 I32:$d), (i32 48))), 1275 (Combinew (A2_combine_ll I32:$d, I32:$c), 1276 (A2_combine_ll I32:$b, I32:$a))>; 1277 1278let AddedComplexity = 200 in { 1279 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1280 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1281 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1282 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1283 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1284 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1285 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1286 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1287} 1288 1289def SDTHexagonVShift 1290 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1291 1292def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1293def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1294def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1295 1296def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1297def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1298def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1299def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1300def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1301def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1302 1303def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1304def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1305def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1306def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1307def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1308def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1309 1310def: Pat<(sra V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))), 1311 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1312def: Pat<(srl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))), 1313 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1314def: Pat<(shl V2I32:$b, (v2i32 (HexagonVSPLAT u5_0ImmPred:$c))), 1315 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1316def: Pat<(sra V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), 1317 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1318def: Pat<(srl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), 1319 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1320def: Pat<(shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), 1321 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1322 1323def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1324 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1325def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1326 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1327def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1328 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1329def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1330 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1331def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1332 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1333def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1334 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1335 1336 1337// --(9) Arithmetic/bitwise ---------------------------------------------- 1338// 1339 1340def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1341def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1342def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1343def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1344def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1345 1346def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1347def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1348 1349def: Pat<(fabs F64:$Rs), 1350 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1351 (i32 (LoReg $Rs)))>; 1352def: Pat<(fneg F64:$Rs), 1353 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1354 (i32 (LoReg $Rs)))>; 1355 1356def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1357def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1358def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1359def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1360 1361def: OpR_RR_pat<A2_add, Add, i32, I32>; 1362def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1363def: OpR_RR_pat<A2_and, And, i32, I32>; 1364def: OpR_RR_pat<A2_or, Or, i32, I32>; 1365def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1366def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1367def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1368def: OpR_RR_pat<A2_andp, And, i64, I64>; 1369def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1370def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1371def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1372def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1373 1374def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1375def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1376 1377def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1378def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1379def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1380def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1381def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1382def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1383 1384def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1385def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1386def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1387def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1388def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1389def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1390def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1391def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1392def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1393def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1394def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1395def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1396def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1397def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1398def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1399 1400def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1401def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1402def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1403def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1404def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1405 1406// Arithmetic on predicates. 1407def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1408def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1409def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1410def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1411def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1412def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1413def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1414def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1415def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1416def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1417def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1418def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1419 1420def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1421def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1422def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1423def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1424def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1425 1426let Predicates = [HasV66] in { 1427 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1428 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1429} 1430 1431def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), 1432 (F2_dfmpyhh 1433 (F2_dfmpylh 1434 (F2_dfmpylh 1435 (F2_dfmpyll $Rs, $Rt), 1436 $Rs, $Rt), 1437 $Rt, $Rs), 1438 $Rs, $Rt)>; 1439 1440let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { 1441 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; 1442} 1443let Predicates = [HasV67] in { 1444 def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; 1445 def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; 1446 1447 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), 1448 (F2_dfmpyfix $Rt, $Rs))>; 1449} 1450 1451// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1452// over add-add with individual multiplies as inputs. 1453let AddedComplexity = 10 in { 1454 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1455 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1456 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1457 let Predicates = [HasV66] in 1458 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1459} 1460 1461def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1462def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1463def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1464 1465// Mulh for vectors 1466// 1467def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1468 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1469 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1470 1471def: Pat<(v2i32 (mulhs V2I32:$Rs, V2I32:$Rt)), 1472 (Combinew (M2_mpy_up (HiReg $Rs), (HiReg $Rt)), 1473 (M2_mpy_up (LoReg $Rt), (LoReg $Rt)))>; 1474 1475def Mulhub: 1476 OutPatFrag<(ops node:$Rss, node:$Rtt), 1477 (Combinew (S2_vtrunohb (M5_vmpybuu (HiReg $Rss), (HiReg $Rtt))), 1478 (S2_vtrunohb (M5_vmpybuu (LoReg $Rss), (LoReg $Rtt))))>; 1479 1480// Equivalent of byte-wise arithmetic shift right by 7 in v8i8. 1481def Asr7: 1482 OutPatFrag<(ops node:$Rss), (C2_mask (C2_not (A4_vcmpbgti $Rss, 0)))>; 1483 1484def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), 1485 (Mulhub $Rss, $Rtt)>; 1486 1487def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), 1488 (A2_vsubub 1489 (Mulhub $Rss, $Rtt), 1490 (A2_vaddub (A2_andp V8I8:$Rss, (Asr7 $Rtt)), 1491 (A2_andp V8I8:$Rtt, (Asr7 $Rss))))>; 1492 1493def Mpysh: 1494 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1495def Mpyshh: 1496 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (HiReg $Rss), (HiReg $Rtt))>; 1497def Mpyshl: 1498 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (LoReg $Rss), (LoReg $Rtt))>; 1499 1500def Mulhsh: 1501 OutPatFrag<(ops node:$Rss, node:$Rtt), 1502 (Combinew (A2_combine_hh (HiReg (Mpyshh $Rss, $Rtt)), 1503 (LoReg (Mpyshh $Rss, $Rtt))), 1504 (A2_combine_hh (HiReg (Mpyshl $Rss, $Rtt)), 1505 (LoReg (Mpyshl $Rss, $Rtt))))>; 1506 1507def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh $Rss, $Rtt)>; 1508 1509def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1510 (A2_vaddh 1511 (Mulhsh $Rss, $Rtt), 1512 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1513 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1514 1515 1516def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1517 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1518 1519def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1520 int64_t V = N->getSExtValue(); 1521 return -255 <= V && V <= 0; 1522}]>; 1523 1524// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1525def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1526 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1527 1528def: Pat<(add Sext64:$Rs, I64:$Rt), 1529 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1530 1531def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1532def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1533def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1534def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1535def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1536def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1537def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1538def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1539def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1540def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1541 1542// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1543// one argument matches the patterns below, and with the other argument 1544// matches S2_asl_r_r_or, etc, prefer the patterns below. 1545let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1546 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1547 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1548 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1549} 1550 1551// S4_addaddi and S4_subaddi don't have tied operands, so give them 1552// a bit of preference. 1553let AddedComplexity = 30, Predicates = [UseCompound] in { 1554 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1555 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1556 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1557 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1558 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1559 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1560 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1561 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1562 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1563 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1564} 1565 1566let Predicates = [UseCompound] in 1567def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1568 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1569 1570def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1571 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1572def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1573 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1574 1575 1576def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1577 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1578def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1579 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1580 1581def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1582 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1583def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1584 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1585def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1586 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1587 1588def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1589 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1590def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1591 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1592def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1593 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1594def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1595 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1596def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1597 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1598def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1599 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1600 1601// Add halfword. 1602def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1603 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1604def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1605 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1606def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1607 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1608 1609// Subtract halfword. 1610def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1611 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1612def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1613 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1614def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1615 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1616 1617def: Pat<(mul I64:$Rss, I64:$Rtt), 1618 (Combinew 1619 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1620 (LoReg $Rss), 1621 (HiReg $Rtt)), 1622 (LoReg $Rtt), 1623 (HiReg $Rss)), 1624 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1625 1626def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1627 (A2_addp 1628 (M2_dpmpyuu_acc_s0 1629 (S2_lsr_i_p 1630 (A2_addp 1631 (M2_dpmpyuu_acc_s0 1632 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1633 (HiReg $Rss), 1634 (LoReg $Rtt)), 1635 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1636 32), 1637 (HiReg $Rss), 1638 (HiReg $Rtt)), 1639 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1640 1641// Multiply 64-bit unsigned and use upper result. 1642def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1643 1644// Multiply 64-bit signed and use upper result. 1645// 1646// For two signed 64-bit integers A and B, let A' and B' denote A and B 1647// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1648// sign bit of A (and identically for B). With this notation, the signed 1649// product A*B can be written as: 1650// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1651// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1652// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1653// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1654 1655// Clear the sign bit in a 64-bit register. 1656def ClearSign : OutPatFrag<(ops node:$Rss), 1657 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1658 1659def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1660 (A2_subp 1661 (MulHU $Rss, $Rtt), 1662 (A2_addp 1663 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1664 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1665 1666// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1667// will put the immediate addend into a register, while these instructions will 1668// use it directly. Such a construct does not appear in the middle of a gep, 1669// where M2_macsip would be preferable. 1670let AddedComplexity = 20, Predicates = [UseCompound] in { 1671 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1672 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1673 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1674 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1675} 1676 1677// Keep these instructions less preferable to M2_macsip/M2_macsin. 1678let Predicates = [UseCompound] in { 1679 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1680 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1681 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1682 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1683 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1684 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1685} 1686 1687def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1688 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1689def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1690 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1691def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx), 1692 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1693 1694def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1695 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1696def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1697 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1698 1699// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1700// we use the double add v8i8, and use only the low part of the result. 1701def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1702 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1703def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1704 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1705 1706// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1707// half-words, and saturates the result to a 32-bit value, except the 1708// saturation never happens (it can only occur with scaling). 1709def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1710 (LoReg (S2_vtrunewh (A2_combineii 0, 0), 1711 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1712def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1713 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1714 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1715 1716// Multiplies two v4i8 vectors. 1717def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1718 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1719 1720// Multiplies two v8i8 vectors. 1721def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1722 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1723 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1724 1725 1726// --(10) Bit ------------------------------------------------------------ 1727// 1728 1729// Count leading zeros. 1730def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 1731def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1732 1733// Count trailing zeros. 1734def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 1735def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1736 1737// Count leading ones. 1738def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 1739def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1740 1741// Count trailing ones. 1742def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 1743def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1744 1745// Define leading/trailing patterns that require zero-extensions to 64 bits. 1746def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1747def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1748def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1749def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1750 1751def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1752def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1753 1754def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1755def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1756 1757let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1758 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1759 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1760 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1761 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1762 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1763 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1764 1765 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1766 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1767 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1768 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1769 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1770 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1771} 1772 1773// Clr/set/toggle bit for 64-bit values with immediate bit index. 1774let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1775 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1776 (Combinew (i32 (HiReg $Rss)), 1777 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1778 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1779 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1780 (i32 (LoReg $Rss)))>; 1781 1782 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1783 (Combinew (i32 (HiReg $Rss)), 1784 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1785 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1786 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1787 (i32 (LoReg $Rss)))>; 1788 1789 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1790 (Combinew (i32 (HiReg $Rss)), 1791 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1792 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1793 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1794 (i32 (LoReg $Rss)))>; 1795} 1796 1797 1798let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1799 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1800 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1801 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1802 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1803 def: Pat<(i1 (trunc I32:$Rs)), 1804 (S2_tstbit_i IntRegs:$Rs, 0)>; 1805 def: Pat<(i1 (trunc I64:$Rs)), 1806 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1807} 1808 1809def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1), 1810 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>; 1811def: Pat<(and (srl I64:$Rss, IsULE<32,31>:$u6), 1), 1812 (ToZext64 (I1toI32 (S2_tstbit_i (LoReg $Rss), imm:$u6)))>; 1813def: Pat<(and (srl I64:$Rss, IsUGT<32,31>:$u6), 1), 1814 (ToZext64 (I1toI32 (S2_tstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1815 1816def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1), 1817 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>; 1818def: Pat<(and (not (srl I64:$Rss, IsULE<32,31>:$u6)), 1), 1819 (ToZext64 (I1toI32 (S4_ntstbit_i (LoReg $Rss), imm:$u6)))>; 1820def: Pat<(and (not (srl I64:$Rss, IsUGT<32,31>:$u6)), 1), 1821 (ToZext64 (I1toI32 (S4_ntstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1822 1823let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1824 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1825 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1826 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1827 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 1828} 1829 1830let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 1831def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 1832 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 1833 1834def SDTTestBit: 1835 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1836def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 1837 1838def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 1839 (S2_tstbit_i I32:$Rs, imm:$u5)>; 1840def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 1841 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1842 1843// Add extra complexity to prefer these instructions over bitsset/bitsclr. 1844// The reason is that tstbit/ntstbit can be folded into a compound instruction: 1845// if ([!]tstbit(...)) jump ... 1846let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1847 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)), 1848 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1849 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)), 1850 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1851 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1852 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 1853 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1854 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1855} 1856 1857def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)), 1858 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>; 1859def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)), 1860 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>; 1861def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)), 1862 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>; 1863def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)), 1864 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>; 1865 1866// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 1867// represented as a compare against "value & 0xFF", which is an exact match 1868// for cmpb (same for cmph). The patterns below do not contain any additional 1869// complexity that would make them preferable, and if they were actually used 1870// instead of cmpb/cmph, they would result in a compare against register that 1871// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 1872def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1873 (C4_nbitsclri I32:$Rs, imm:$u6)>; 1874def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 1875 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 1876def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 1877 (C4_nbitsset I32:$Rs, I32:$Rt)>; 1878 1879// Special patterns to address certain cases where the "top-down" matching 1880// algorithm would cause suboptimal selection. 1881 1882let AddedComplexity = 100 in { 1883 // Avoid A4_rcmp[n]eqi in these cases: 1884 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1885 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1886 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1887 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1888 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))), 1889 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1890 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))), 1891 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1892 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1893 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>; 1894 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1895 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>; 1896} 1897 1898// --(11) PIC ------------------------------------------------------------ 1899// 1900 1901def SDT_HexagonAtGot 1902 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1903def SDT_HexagonAtPcrel 1904 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 1905 1906// AT_GOT address-of-GOT, address-of-global, offset-in-global 1907def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 1908// AT_PCREL address-of-global 1909def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 1910 1911def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 1912 (L2_loadri_io I32:$got, imm:$addr)>; 1913def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 1914 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 1915def: Pat<(HexagonAtPcrel I32:$addr), 1916 (C4_addipc imm:$addr)>; 1917 1918// The HVX load patterns also match AT_PCREL directly. Make sure that 1919// if the selection of this opcode changes, it's updated in all places. 1920 1921 1922// --(12) Load ----------------------------------------------------------- 1923// 1924 1925def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1926 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1927}]>; 1928def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1929 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1930}]>; 1931 1932def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1933 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1934}]>; 1935def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1936 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1937}]>; 1938 1939def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1940 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1941}]>; 1942def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1943 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1944}]>; 1945 1946// Patterns to select load-indexed: Rs + Off. 1947// - frameindex [+ imm], 1948multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1949 InstHexagon MI> { 1950 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1951 (VT (MI AddrFI:$fi, imm:$Off))>; 1952 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1953 (VT (MI AddrFI:$fi, imm:$Off))>; 1954 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 1955} 1956 1957// Patterns to select load-indexed: Rs + Off. 1958// - base reg [+ imm] 1959multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1960 InstHexagon MI> { 1961 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 1962 (VT (MI IntRegs:$Rs, imm:$Off))>; 1963 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 1964 (VT (MI IntRegs:$Rs, imm:$Off))>; 1965 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 1966} 1967 1968// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 1969multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1970 InstHexagon MI> { 1971 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 1972 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 1973} 1974 1975// Patterns to select load reg indexed: Rs + Off with a value modifier. 1976// - frameindex [+ imm] 1977multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1978 PatLeaf ImmPred, InstHexagon MI> { 1979 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1980 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 1981 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1982 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 1983 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 1984} 1985 1986// Patterns to select load reg indexed: Rs + Off with a value modifier. 1987// - base reg [+ imm] 1988multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1989 PatLeaf ImmPred, InstHexagon MI> { 1990 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 1991 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 1992 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 1993 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 1994 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 1995} 1996 1997// Patterns to select load reg indexed: Rs + Off with a value modifier. 1998// Combines Loadxfim + Loadxgim. 1999multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2000 PatLeaf ImmPred, InstHexagon MI> { 2001 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 2002 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 2003} 2004 2005// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 2006class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2007 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2008 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 2009 2010// Pattern to select load reg reg-indexed: Rs + Rt<<0. 2011class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2012 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2013 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 2014 2015// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 2016class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2017 InstHexagon MI> 2018 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2019 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 2020 2021// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 2022class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2023 InstHexagon MI> 2024 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2025 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 2026 2027// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 2028// Don't match for u2==0, instead use reg+imm for those cases. 2029class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 2030 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2031 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 2032 2033class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 2034 InstHexagon MI> 2035 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2036 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 2037 2038// Pattern to select load absolute. 2039class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 2040 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 2041 2042// Pattern to select load absolute with value modifier. 2043class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 2044 InstHexagon MI> 2045 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 2046 2047 2048let AddedComplexity = 20 in { 2049 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 2050 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 2051 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 2052 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2053 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2054 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 2055 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 2056 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 2057 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2058 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 2059 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 2060 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 2061 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2062 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2063 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 2064 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 2065 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 2066 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 2067 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 2068 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 2069 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 2070 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 2071 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 2072 // No sextloadi1. 2073 2074 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 2075 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 2076 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 2077 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 2078} 2079 2080let AddedComplexity = 30 in { 2081 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 2082 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 2083 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 2084 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 2085 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 2086 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 2087 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 2088 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 2089 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 2090 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 2091 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 2092} 2093 2094let AddedComplexity = 60 in { 2095 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 2096 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 2097 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2098 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2099 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 2100 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 2101 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 2102 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2103 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 2104 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 2105 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2106 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2107 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 2108 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 2109 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 2110 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 2111 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 2112 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 2113 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 2114 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 2115 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2116 2117 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2118 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2119 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2120 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2121 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2122 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2123 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2124 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2125 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2126} 2127 2128let AddedComplexity = 40 in { 2129 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2130 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2131 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2132 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2133 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2134 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2135 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2136 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2137 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2138 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2139 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2140 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2141 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2142 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2143 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2144} 2145 2146let AddedComplexity = 20 in { 2147 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2148 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2149 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2150 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2151 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2152 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2153 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2154 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2155 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2156 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2157 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2158 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2159 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2160 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2161 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2162} 2163 2164let AddedComplexity = 40 in { 2165 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2166 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2167 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2168 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2169 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2170 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2171 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2172 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2173 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2174} 2175 2176let AddedComplexity = 20 in { 2177 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2178 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2179 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2180 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2181 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2182 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2183 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2184 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2185 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2186} 2187 2188// Absolute address 2189 2190let AddedComplexity = 60 in { 2191 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2192 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2193 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2194 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2195 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2196 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2197 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2198 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2199 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2200 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2201 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2202 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2203 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2204 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2205 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2206 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2207 2208 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2209 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2210 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2211 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2212} 2213 2214let AddedComplexity = 30 in { 2215 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2216 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2217 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2218 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2219 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2220 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2221 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2222 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2223 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2224 2225 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2226 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2227} 2228 2229// GP-relative address 2230 2231let AddedComplexity = 100 in { 2232 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2233 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2234 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2235 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2236 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2237 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2238 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2239 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2240 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2241 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2242 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2243 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2244 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2245 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2246 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2247 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2248 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2249 2250 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2251 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2252 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2253 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2254} 2255 2256let AddedComplexity = 70 in { 2257 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2258 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2259 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2260 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2261 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2262 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2263 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2264 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2265 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2266 2267 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2268 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2269} 2270 2271 2272// Sign-extending loads of i1 need to replicate the lowest bit throughout 2273// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should 2274// do the trick. 2275let AddedComplexity = 20 in 2276def: Pat<(i32 (sextloadi1 I32:$Rs)), 2277 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>; 2278 2279// Patterns for loads of i1: 2280def: Pat<(i1 (load AddrFI:$fi)), 2281 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2282def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2283 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2284def: Pat<(i1 (load I32:$Rs)), 2285 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2286 2287 2288// --(13) Store ---------------------------------------------------------- 2289// 2290 2291class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2292 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2293 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2294 2295def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2296def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2297def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2298def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2299 2300// Patterns for generating stores, where the address takes different forms: 2301// - frameindex, 2302// - frameindex + offset, 2303// - base + offset, 2304// - simple (base address without offset). 2305// These would usually be used together (via Storexi_pat defined below), but 2306// in some cases one may want to apply different properties (such as 2307// AddedComplexity) to the individual patterns. 2308class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2309 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2310 2311multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2312 InstHexagon MI> { 2313 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2314 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2315 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2316 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2317} 2318 2319multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2320 InstHexagon MI> { 2321 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2322 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2323 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2324 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2325} 2326 2327class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2328 : Pat<(Store Value:$Rt, I32:$Rs), 2329 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2330 2331// Patterns for generating stores, where the address takes different forms, 2332// and where the value being stored is transformed through the value modifier 2333// ValueMod. The address forms are same as above. 2334class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2335 InstHexagon MI> 2336 : Pat<(Store Value:$Rs, AddrFI:$fi), 2337 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2338 2339multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2340 PatFrag ValueMod, InstHexagon MI> { 2341 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2342 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2343 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2344 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2345} 2346 2347multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2348 PatFrag ValueMod, InstHexagon MI> { 2349 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2350 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2351 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2352 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2353} 2354 2355class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2356 InstHexagon MI> 2357 : Pat<(Store Value:$Rt, I32:$Rs), 2358 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2359 2360multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2361 InstHexagon MI> { 2362 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2363 def: Storexi_fi_pat <Store, Value, MI>; 2364 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2365} 2366 2367multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2368 PatFrag ValueMod, InstHexagon MI> { 2369 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2370 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2371 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2372} 2373 2374// Reg<<S + Imm 2375class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2376 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2377 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2378 2379// Reg<<S + Reg 2380class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2381 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2382 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2383 2384// Reg + Reg 2385class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2386 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2387 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2388 2389class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2390 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2391 2392class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2393 InstHexagon MI> 2394 : Pat<(Store Value:$val, Addr:$addr), 2395 (MI Addr:$addr, (ValueMod Value:$val))>; 2396 2397// Regular stores in the DAG have two operands: value and address. 2398// Atomic stores also have two, but they are reversed: address, value. 2399// To use atomic stores with the patterns, they need to have their operands 2400// swapped. This relies on the knowledge that the F.Fragment uses names 2401// "ptr" and "val". 2402class AtomSt<PatFrag F> 2403 : PatFrag<(ops node:$val, node:$ptr), !head(F.Fragments), F.PredicateCode, 2404 F.OperandTransform> { 2405 let IsAtomic = F.IsAtomic; 2406 let MemoryVT = F.MemoryVT; 2407} 2408 2409 2410def IMM_BYTE : SDNodeXForm<imm, [{ 2411 // -1 can be represented as 255, etc. 2412 // assigning to a byte restores our desired signed value. 2413 int8_t imm = N->getSExtValue(); 2414 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2415}]>; 2416 2417def IMM_HALF : SDNodeXForm<imm, [{ 2418 // -1 can be represented as 65535, etc. 2419 // assigning to a short restores our desired signed value. 2420 int16_t imm = N->getSExtValue(); 2421 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2422}]>; 2423 2424def IMM_WORD : SDNodeXForm<imm, [{ 2425 // -1 can be represented as 4294967295, etc. 2426 // Currently, it's not doing this. But some optimization 2427 // might convert -1 to a large +ve number. 2428 // assigning to a word restores our desired signed value. 2429 int32_t imm = N->getSExtValue(); 2430 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2431}]>; 2432 2433def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2434def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2435def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2436 2437// Even though the offset is not extendable in the store-immediate, we 2438// can still generate the fi# in the base address. If the final offset 2439// is not valid for the instruction, we will replace it with a scratch 2440// register. 2441class SmallStackStore<PatFrag Store> 2442 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2443 return isSmallStackStore(cast<StoreSDNode>(N)); 2444}]>; 2445 2446// This is the complement of SmallStackStore. 2447class LargeStackStore<PatFrag Store> 2448 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2449 return !isSmallStackStore(cast<StoreSDNode>(N)); 2450}]>; 2451 2452// Preferred addressing modes for various combinations of stored value 2453// and address computation. 2454// For stores where the address and value are both immediates, prefer 2455// store-immediate. The reason is that the constant-extender optimization 2456// can replace store-immediate with a store-register, but there is nothing 2457// to generate a store-immediate out of a store-register. 2458// 2459// C R F F+C R+C R+R R<<S+C R<<S+R 2460// --+-------+-----+-----+------+-----+-----+--------+-------- 2461// C | imm | imm | imm | imm | imm | rr | ur | rr 2462// R | abs* | io | io | io | io | rr | ur | rr 2463// 2464// (*) Absolute or GP-relative. 2465// 2466// Note that any expression can be matched by Reg. In particular, an immediate 2467// can always be placed in a register, so patterns checking for Imm should 2468// have a higher priority than the ones involving Reg that could also match. 2469// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2470// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2471// Reg alone. 2472// 2473// The order in which the different combinations are tried: 2474// 2475// C F R F+C R+C R+R R<<S+C R<<S+R 2476// --+-------+-----+-----+------+-----+-----+--------+-------- 2477// C | 1 | 6 | - | 5 | 9 | - | - | - 2478// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2479 2480 2481// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2482// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2483// implies that Reg is also a proper multiple of 4. To still generate a 2484// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2485 2486def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2487 int64_t v = (int64_t)N->getSExtValue(); 2488 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2489}]>; 2490def RoundTo8 : SDNodeXForm<imm, [{ 2491 int32_t Imm = N->getSExtValue(); 2492 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2493}]>; 2494 2495let AddedComplexity = 150 in 2496def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2497 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2498 2499class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2500 : Pat<(Store Value:$val, anyimm:$addr), 2501 (MI (ToI32 $addr), 0, Value:$val)>; 2502class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2503 InstHexagon MI> 2504 : Pat<(Store Value:$val, anyimm:$addr), 2505 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2506 2507let AddedComplexity = 140 in { 2508 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2509 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2510 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2511 2512 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2513 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2514 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2515} 2516 2517// GP-relative address 2518let AddedComplexity = 120 in { 2519 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2520 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2521 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2522 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2523 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2524 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2525 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2526 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2527 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2528 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2529 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2530 def: Storea_pat<AtomSt<atomic_store_8>, I32, addrgp, S2_storerbgp>; 2531 def: Storea_pat<AtomSt<atomic_store_16>, I32, addrgp, S2_storerhgp>; 2532 def: Storea_pat<AtomSt<atomic_store_32>, I32, addrgp, S2_storerigp>; 2533 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, addrgp, S2_storerigp>; 2534 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, addrgp, S2_storerigp>; 2535 def: Storea_pat<AtomSt<atomic_store_64>, I64, addrgp, S2_storerdgp>; 2536 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, addrgp, S2_storerdgp>; 2537 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, addrgp, S2_storerdgp>; 2538 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, addrgp, S2_storerdgp>; 2539 2540 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2541 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2542 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2543 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2544} 2545 2546// Absolute address 2547let AddedComplexity = 110 in { 2548 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2549 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2550 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2551 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2552 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2553 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2554 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2555 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2556 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2557 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2558 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2559 def: Storea_pat<AtomSt<atomic_store_8>, I32, anyimm0, PS_storerbabs>; 2560 def: Storea_pat<AtomSt<atomic_store_16>, I32, anyimm1, PS_storerhabs>; 2561 def: Storea_pat<AtomSt<atomic_store_32>, I32, anyimm2, PS_storeriabs>; 2562 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, PS_storeriabs>; 2563 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, PS_storeriabs>; 2564 def: Storea_pat<AtomSt<atomic_store_64>, I64, anyimm3, PS_storerdabs>; 2565 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, PS_storerdabs>; 2566 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, PS_storerdabs>; 2567 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, PS_storerdabs>; 2568 2569 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2570 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2571 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2572 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2573} 2574 2575// Reg<<S + Imm 2576let AddedComplexity = 100 in { 2577 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2578 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2579 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2580 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2581 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2582 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2583 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2584 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2585 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2586 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2587 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2588 2589 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2590 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2591} 2592 2593// Reg<<S + Reg 2594let AddedComplexity = 90 in { 2595 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2596 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2597 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2598 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2599 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2600 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2601 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2602 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2603 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2604 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2605 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2606 2607 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2608 (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2609} 2610 2611class SS_<PatFrag F> : SmallStackStore<F>; 2612class LS_<PatFrag F> : LargeStackStore<F>; 2613 2614multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2615 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2616} 2617multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2618 defm: Storexi_fi_add_pat<S, V, O, I>; 2619} 2620 2621// Fi+Imm, store-immediate 2622let AddedComplexity = 80 in { 2623 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2624 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2625 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2626 2627 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2628 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2629 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2630 2631 // For large-stack stores, generate store-register (prefer explicit Fi 2632 // in the address). 2633 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2634 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2635 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2636} 2637 2638// Fi, store-immediate 2639let AddedComplexity = 70 in { 2640 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2641 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2642 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2643 2644 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2645 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2646 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2647 2648 // For large-stack stores, generate store-register (prefer explicit Fi 2649 // in the address). 2650 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2651 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2652 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2653} 2654 2655// Fi+Imm, Fi, store-register 2656let AddedComplexity = 60 in { 2657 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2658 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2659 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2660 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2661 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2662 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2663 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2664 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2665 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2666 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2667 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2668 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2669 2670 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2671 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2672 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2673 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2674 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2675 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2676 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2677 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2678 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2679 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2680 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2681 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2682} 2683 2684 2685multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2686 defm: Storexim_add_pat<S, V, O, M, I>; 2687} 2688multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2689 defm: Storexi_add_pat<S, V, O, I>; 2690} 2691 2692// Reg+Imm, store-immediate 2693let AddedComplexity = 50 in { 2694 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2695 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2696 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2697 2698 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2699 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2700 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2701} 2702 2703// Reg+Imm, store-register 2704let AddedComplexity = 40 in { 2705 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2706 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2707 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2708 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2709 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2710 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2711 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2712 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2713 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2714 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2715 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2716 2717 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2718 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2719 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2720 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2721 2722 defm: Storexi_pat<AtomSt<atomic_store_8>, I32, anyimm0, S2_storerb_io>; 2723 defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>; 2724 defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>; 2725 defm: Storexi_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, S2_storeri_io>; 2726 defm: Storexi_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, S2_storeri_io>; 2727 defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>; 2728 defm: Storexi_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, S2_storerd_io>; 2729 defm: Storexi_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, S2_storerd_io>; 2730 defm: Storexi_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, S2_storerd_io>; 2731} 2732 2733// Reg+Reg 2734let AddedComplexity = 30 in { 2735 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2736 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2737 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2738 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2739 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2740 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2741 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2742 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2743 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2744 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2745 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2746 2747 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2748 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2749} 2750 2751// Reg, store-immediate 2752let AddedComplexity = 20 in { 2753 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2754 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2755 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2756 2757 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2758 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2759 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2760} 2761 2762// Reg, store-register 2763let AddedComplexity = 10 in { 2764 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2765 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2766 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2767 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2768 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2769 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2770 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2771 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2772 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2773 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2774 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2775 2776 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2777 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2778 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2779 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2780 2781 def: Storexi_base_pat<AtomSt<atomic_store_8>, I32, S2_storerb_io>; 2782 def: Storexi_base_pat<AtomSt<atomic_store_16>, I32, S2_storerh_io>; 2783 def: Storexi_base_pat<AtomSt<atomic_store_32>, I32, S2_storeri_io>; 2784 def: Storexi_base_pat<AtomSt<atomic_store_32>, V4I8, S2_storeri_io>; 2785 def: Storexi_base_pat<AtomSt<atomic_store_32>, V2I16, S2_storeri_io>; 2786 def: Storexi_base_pat<AtomSt<atomic_store_64>, I64, S2_storerd_io>; 2787 def: Storexi_base_pat<AtomSt<atomic_store_64>, V8I8, S2_storerd_io>; 2788 def: Storexi_base_pat<AtomSt<atomic_store_64>, V4I16, S2_storerd_io>; 2789 def: Storexi_base_pat<AtomSt<atomic_store_64>, V2I32, S2_storerd_io>; 2790} 2791 2792 2793// --(14) Memop ---------------------------------------------------------- 2794// 2795 2796def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2797 int8_t V = N->getSExtValue(); 2798 return -32 < V && V <= -1; 2799}]>; 2800 2801def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2802 int16_t V = N->getSExtValue(); 2803 return -32 < V && V <= -1; 2804}]>; 2805 2806def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2807 int64_t V = N->getSExtValue(); 2808 return -31 <= V && V <= -1; 2809}]>; 2810 2811def IsNPow2_8 : PatLeaf<(i32 imm), [{ 2812 uint8_t NV = ~N->getZExtValue(); 2813 return isPowerOf2_32(NV); 2814}]>; 2815 2816def IsNPow2_16 : PatLeaf<(i32 imm), [{ 2817 uint16_t NV = ~N->getZExtValue(); 2818 return isPowerOf2_32(NV); 2819}]>; 2820 2821def Log2_8 : SDNodeXForm<imm, [{ 2822 uint8_t V = N->getZExtValue(); 2823 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2824}]>; 2825 2826def Log2_16 : SDNodeXForm<imm, [{ 2827 uint16_t V = N->getZExtValue(); 2828 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2829}]>; 2830 2831def LogN2_8 : SDNodeXForm<imm, [{ 2832 uint8_t NV = ~N->getZExtValue(); 2833 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2834}]>; 2835 2836def LogN2_16 : SDNodeXForm<imm, [{ 2837 uint16_t NV = ~N->getZExtValue(); 2838 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2839}]>; 2840 2841def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 2842 2843multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2844 InstHexagon MI> { 2845 // Addr: i32 2846 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 2847 (MI I32:$Rs, 0, I32:$A)>; 2848 // Addr: fi 2849 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 2850 (MI AddrFI:$Rs, 0, I32:$A)>; 2851} 2852 2853multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2854 SDNode Oper, InstHexagon MI> { 2855 // Addr: i32 2856 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 2857 (add I32:$Rs, ImmPred:$Off)), 2858 (MI I32:$Rs, imm:$Off, I32:$A)>; 2859 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 2860 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2861 (MI I32:$Rs, imm:$Off, I32:$A)>; 2862 // Addr: fi 2863 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2864 (add AddrFI:$Rs, ImmPred:$Off)), 2865 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2866 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2867 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2868 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2869} 2870 2871multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2872 SDNode Oper, InstHexagon MI> { 2873 let Predicates = [UseMEMOPS] in { 2874 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 2875 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 2876 } 2877} 2878 2879let AddedComplexity = 200 in { 2880 // add reg 2881 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 2882 /*anyext*/ L4_add_memopb_io>; 2883 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 2884 /*sext*/ L4_add_memopb_io>; 2885 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 2886 /*zext*/ L4_add_memopb_io>; 2887 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 2888 /*anyext*/ L4_add_memoph_io>; 2889 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 2890 /*sext*/ L4_add_memoph_io>; 2891 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 2892 /*zext*/ L4_add_memoph_io>; 2893 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 2894 2895 // sub reg 2896 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 2897 /*anyext*/ L4_sub_memopb_io>; 2898 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 2899 /*sext*/ L4_sub_memopb_io>; 2900 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 2901 /*zext*/ L4_sub_memopb_io>; 2902 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 2903 /*anyext*/ L4_sub_memoph_io>; 2904 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 2905 /*sext*/ L4_sub_memoph_io>; 2906 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 2907 /*zext*/ L4_sub_memoph_io>; 2908 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 2909 2910 // and reg 2911 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 2912 /*anyext*/ L4_and_memopb_io>; 2913 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 2914 /*sext*/ L4_and_memopb_io>; 2915 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 2916 /*zext*/ L4_and_memopb_io>; 2917 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 2918 /*anyext*/ L4_and_memoph_io>; 2919 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 2920 /*sext*/ L4_and_memoph_io>; 2921 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 2922 /*zext*/ L4_and_memoph_io>; 2923 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 2924 2925 // or reg 2926 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 2927 /*anyext*/ L4_or_memopb_io>; 2928 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 2929 /*sext*/ L4_or_memopb_io>; 2930 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 2931 /*zext*/ L4_or_memopb_io>; 2932 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 2933 /*anyext*/ L4_or_memoph_io>; 2934 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 2935 /*sext*/ L4_or_memoph_io>; 2936 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 2937 /*zext*/ L4_or_memoph_io>; 2938 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 2939} 2940 2941 2942multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2943 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 2944 // Addr: i32 2945 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 2946 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 2947 // Addr: fi 2948 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 2949 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 2950} 2951 2952multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2953 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 2954 InstHexagon MI> { 2955 // Addr: i32 2956 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 2957 (add I32:$Rs, ImmPred:$Off)), 2958 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2959 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 2960 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2961 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2962 // Addr: fi 2963 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 2964 (add AddrFI:$Rs, ImmPred:$Off)), 2965 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2966 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 2967 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2968 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2969} 2970 2971multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2972 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 2973 InstHexagon MI> { 2974 let Predicates = [UseMEMOPS] in { 2975 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 2976 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 2977 } 2978} 2979 2980let AddedComplexity = 220 in { 2981 // add imm 2982 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2983 /*anyext*/ IdImm, L4_iadd_memopb_io>; 2984 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2985 /*sext*/ IdImm, L4_iadd_memopb_io>; 2986 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2987 /*zext*/ IdImm, L4_iadd_memopb_io>; 2988 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 2989 /*anyext*/ IdImm, L4_iadd_memoph_io>; 2990 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 2991 /*sext*/ IdImm, L4_iadd_memoph_io>; 2992 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 2993 /*zext*/ IdImm, L4_iadd_memoph_io>; 2994 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 2995 L4_iadd_memopw_io>; 2996 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 2997 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 2998 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 2999 /*sext*/ NegImm8, L4_iadd_memopb_io>; 3000 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3001 /*zext*/ NegImm8, L4_iadd_memopb_io>; 3002 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3003 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 3004 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3005 /*sext*/ NegImm16, L4_iadd_memoph_io>; 3006 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3007 /*zext*/ NegImm16, L4_iadd_memoph_io>; 3008 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 3009 L4_iadd_memopw_io>; 3010 3011 // sub imm 3012 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3013 /*anyext*/ IdImm, L4_isub_memopb_io>; 3014 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3015 /*sext*/ IdImm, L4_isub_memopb_io>; 3016 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3017 /*zext*/ IdImm, L4_isub_memopb_io>; 3018 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3019 /*anyext*/ IdImm, L4_isub_memoph_io>; 3020 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3021 /*sext*/ IdImm, L4_isub_memoph_io>; 3022 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3023 /*zext*/ IdImm, L4_isub_memoph_io>; 3024 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 3025 L4_isub_memopw_io>; 3026 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3027 /*anyext*/ NegImm8, L4_isub_memopb_io>; 3028 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3029 /*sext*/ NegImm8, L4_isub_memopb_io>; 3030 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3031 /*zext*/ NegImm8, L4_isub_memopb_io>; 3032 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3033 /*anyext*/ NegImm16, L4_isub_memoph_io>; 3034 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3035 /*sext*/ NegImm16, L4_isub_memoph_io>; 3036 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3037 /*zext*/ NegImm16, L4_isub_memoph_io>; 3038 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 3039 L4_isub_memopw_io>; 3040 3041 // clrbit imm 3042 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3043 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 3044 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3045 /*sext*/ LogN2_8, L4_iand_memopb_io>; 3046 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3047 /*zext*/ LogN2_8, L4_iand_memopb_io>; 3048 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3049 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 3050 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3051 /*sext*/ LogN2_16, L4_iand_memoph_io>; 3052 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3053 /*zext*/ LogN2_16, L4_iand_memoph_io>; 3054 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 3055 LogN2_32, L4_iand_memopw_io>; 3056 3057 // setbit imm 3058 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3059 /*anyext*/ Log2_8, L4_ior_memopb_io>; 3060 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3061 /*sext*/ Log2_8, L4_ior_memopb_io>; 3062 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3063 /*zext*/ Log2_8, L4_ior_memopb_io>; 3064 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3065 /*anyext*/ Log2_16, L4_ior_memoph_io>; 3066 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3067 /*sext*/ Log2_16, L4_ior_memoph_io>; 3068 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3069 /*zext*/ Log2_16, L4_ior_memoph_io>; 3070 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 3071 Log2_32, L4_ior_memopw_io>; 3072} 3073 3074 3075// --(15) Call ----------------------------------------------------------- 3076// 3077 3078// Pseudo instructions. 3079def SDT_SPCallSeqStart 3080 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3081def SDT_SPCallSeqEnd 3082 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3083 3084def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 3085 [SDNPHasChain, SDNPOutGlue]>; 3086def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 3087 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 3088 3089def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3090 3091def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 3092 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3093def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 3094 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3095def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 3096 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3097 3098def: Pat<(callseq_start timm:$amt, timm:$amt2), 3099 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 3100def: Pat<(callseq_end timm:$amt1, timm:$amt2), 3101 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 3102 3103def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 3104def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 3105def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 3106 3107def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 3108def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 3109def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 3110def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 3111 3112def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 3113def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 3114def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 3115 3116def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 3117 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3118def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3119 3120def: Pat<(retflag), (PS_jmpret (i32 R31))>; 3121def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3122 3123 3124// --(16) Branch --------------------------------------------------------- 3125// 3126 3127def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3128def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3129 3130def: Pat<(brcond I1:$Pu, bb:$dst), 3131 (J2_jumpt I1:$Pu, bb:$dst)>; 3132def: Pat<(brcond (not I1:$Pu), bb:$dst), 3133 (J2_jumpf I1:$Pu, bb:$dst)>; 3134def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3135 (J2_jumpf I1:$Pu, bb:$dst)>; 3136def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3137 (J2_jumpf I1:$Pu, bb:$dst)>; 3138def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3139 (J2_jumpt I1:$Pu, bb:$dst)>; 3140 3141 3142// --(17) Misc ----------------------------------------------------------- 3143 3144 3145// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3146// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3147// The isdigit transformation relies on two 'clever' aspects: 3148// 1) The data type is unsigned which allows us to eliminate a zero test after 3149// biasing the expression by 48. We are depending on the representation of 3150// the unsigned types, and semantics. 3151// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3152// 3153// For the C code: 3154// retval = (c >= '0' && c <= '9') ? 1 : 0; 3155// The code is transformed upstream of llvm into 3156// retval = (c-48) < 10 ? 1 : 0; 3157 3158def u7_0PosImmPred : ImmLeaf<i32, [{ 3159 // True if the immediate fits in an 7-bit unsigned field and is positive. 3160 return Imm > 0 && isUInt<7>(Imm); 3161}]>; 3162 3163let AddedComplexity = 139 in 3164def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3165 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3166 3167let AddedComplexity = 100 in 3168def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3169 (i32 (extloadi8 (add I32:$b, 3))), 3170 24, 8), 3171 (i32 16)), 3172 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3173 (zextloadi8 I32:$b)), 3174 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3175 3176 3177// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3178// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3179// We don't really want either one here. 3180def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3181def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3182 [SDNPHasChain]>; 3183 3184def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3185 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3186def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3187 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3188 3189def SDTHexagonALLOCA 3190 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3191def HexagonALLOCA 3192 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3193 3194def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3195 (PS_alloca IntRegs:$Rs, imm:$A)>; 3196 3197def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3198def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3199 3200def: Pat<(trap), (PS_crash)>; 3201 3202// Read cycle counter. 3203def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3204def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3205 [SDNPHasChain]>; 3206 3207def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3208 3209// The declared return value of the store-locked intrinsics is i32, but 3210// the instructions actually define i1. To avoid register copies from 3211// IntRegs to PredRegs and back, fold the entire pattern checking the 3212// result against true/false. 3213let AddedComplexity = 100 in { 3214 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3215 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3216 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3217 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3218 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3219 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3220 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3221 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3222} 3223