1//===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def HQ8: PatLeaf<(VecQ8 HvxQR:$R)>; 91def HQ16: PatLeaf<(VecQ16 HvxQR:$R)>; 92def HQ32: PatLeaf<(VecQ32 HvxQR:$R)>; 93 94def HVI8: PatLeaf<(VecI8 HvxVR:$R)>; 95def HVI16: PatLeaf<(VecI16 HvxVR:$R)>; 96def HVI32: PatLeaf<(VecI32 HvxVR:$R)>; 97 98def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>; 99def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>; 100def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>; 101 102def SDTVecLeaf: 103 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 104def SDTVecVecIntOp: 105 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 106 SDTCisVT<3,i32>]>; 107 108def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>; 109def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>; 110def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 111def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 112 113def ptrue: PatFrag<(ops), (HexagonPTRUE)>; 114def pfalse: PatFrag<(ops), (HexagonPFALSE)>; 115def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>; 116 117def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 118 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 119def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 120 121// Pattern fragments to extract the low and high subregisters from a 122// 64-bit value. 123def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>; 124def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>; 125 126def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 127 return isOrEquivalentToAdd(N); 128}]>; 129 130def IsPow2_32: PatLeaf<(i32 imm), [{ 131 uint32_t V = N->getZExtValue(); 132 return isPowerOf2_32(V); 133}]>; 134 135def IsPow2_64: PatLeaf<(i64 imm), [{ 136 uint64_t V = N->getZExtValue(); 137 return isPowerOf2_64(V); 138}]>; 139 140def IsNPow2_32: PatLeaf<(i32 imm), [{ 141 uint32_t NV = ~N->getZExtValue(); 142 return isPowerOf2_32(NV); 143}]>; 144 145def IsPow2_64L: PatLeaf<(i64 imm), [{ 146 uint64_t V = N->getZExtValue(); 147 return isPowerOf2_64(V) && Log2_64(V) < 32; 148}]>; 149 150def IsPow2_64H: PatLeaf<(i64 imm), [{ 151 uint64_t V = N->getZExtValue(); 152 return isPowerOf2_64(V) && Log2_64(V) >= 32; 153}]>; 154 155def IsNPow2_64L: PatLeaf<(i64 imm), [{ 156 uint64_t NV = ~N->getZExtValue(); 157 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 158}]>; 159 160def IsNPow2_64H: PatLeaf<(i64 imm), [{ 161 uint64_t NV = ~N->getZExtValue(); 162 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 163}]>; 164 165class IsULE<int Width, int Arg>: PatLeaf<(i32 imm), 166 "uint64_t V = N->getZExtValue();" # 167 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";" 168>; 169 170class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 171 "uint64_t V = N->getZExtValue();" # 172 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 173>; 174 175def SDEC1: SDNodeXForm<imm, [{ 176 int32_t V = N->getSExtValue(); 177 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 178}]>; 179 180def UDEC1: SDNodeXForm<imm, [{ 181 uint32_t V = N->getZExtValue(); 182 assert(V >= 1); 183 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 184}]>; 185 186def UDEC32: SDNodeXForm<imm, [{ 187 uint32_t V = N->getZExtValue(); 188 assert(V >= 32); 189 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 190}]>; 191 192class Subi<int From>: SDNodeXForm<imm, 193 "int32_t V = " # From # " - N->getSExtValue();" # 194 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 195>; 196 197def Log2_32: SDNodeXForm<imm, [{ 198 uint32_t V = N->getZExtValue(); 199 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 200}]>; 201 202def Log2_64: SDNodeXForm<imm, [{ 203 uint64_t V = N->getZExtValue(); 204 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 205}]>; 206 207def LogN2_32: SDNodeXForm<imm, [{ 208 uint32_t NV = ~N->getZExtValue(); 209 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 210}]>; 211 212def LogN2_64: SDNodeXForm<imm, [{ 213 uint64_t NV = ~N->getZExtValue(); 214 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 215}]>; 216 217def NegImm8: SDNodeXForm<imm, [{ 218 int8_t NV = -N->getSExtValue(); 219 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 220}]>; 221 222def NegImm16: SDNodeXForm<imm, [{ 223 int16_t NV = -N->getSExtValue(); 224 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 225}]>; 226 227def NegImm32: SDNodeXForm<imm, [{ 228 int32_t NV = -N->getSExtValue(); 229 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 230}]>; 231 232def SplatB: SDNodeXForm<imm, [{ 233 uint32_t V = N->getZExtValue(); 234 assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF); 235 V &= 0xFF; 236 uint32_t S = V << 24 | V << 16 | V << 8 | V; 237 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32); 238}]>; 239 240def SplatH: SDNodeXForm<imm, [{ 241 uint32_t V = N->getZExtValue(); 242 assert(isUInt<16>(V) || V >> 16 == 0xFFFF); 243 V &= 0xFFFF; 244 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32); 245}]>; 246 247 248// Helpers for type promotions/contractions. 249def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 250def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 251def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 252def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 253def ToAext64: OutPatFrag<(ops node:$Rs), 254 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 255 256def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 257 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 258 259def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 260def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 261def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 262def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 263 264// Global address or an aligned constant. 265def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 266def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 267def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 268def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 269 270def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 271def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 272 273// This complex pattern is really only to detect various forms of 274// sign-extension i32->i64. The selected value will be of type i64 275// whose low word is the value being extended. The high word is 276// unspecified. 277def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 278 279def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 280def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 281def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 282 283def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 284def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 285 286def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 287 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 288 289 290// Converters from unary/binary SDNode to PatFrag. 291class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 292class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 293 294class Not2<PatFrag P> 295 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 296 297// If there is a constant operand that feeds the and/or instruction, 298// do not generate the compound instructions. 299// It is not always profitable, as some times we end up with a transfer. 300// Check the below example. 301// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 302// Instead this is preferable. 303// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 304class Su_ni1<PatFrag Op> 305 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 306 if (hasOneUse(N)){ 307 // Check if Op1 is an immediate operand. 308 SDValue Op1 = N->getOperand(1); 309 return !isa<ConstantSDNode>(Op1); 310 } 311 return false;}], 312 Op.OperandTransform>; 313 314class Su<PatFrag Op> 315 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 316 Op.OperandTransform>; 317 318// Main selection macros. 319 320class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 321 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 322 323class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 324 PatFrag RegPred, PatFrag ImmPred> 325 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 326 (MI RegPred:$Rs, imm:$I)>; 327 328class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 329 PatFrag RsPred, PatFrag RtPred = RsPred> 330 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 331 (MI RsPred:$Rs, RtPred:$Rt)>; 332 333class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 334 PatFrag RegPred, PatFrag ImmPred> 335 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 336 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 337 338class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 339 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 340 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 341 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 342 343multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 344 InstHexagon InstA, InstHexagon InstB> { 345 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 346 (InstA Val:$A, Val:$B)>; 347 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 348 (InstB Val:$A, Val:$B)>; 349} 350 351multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, 352 PatFrag Sel, PatFrag CmpOp, 353 ValueType CmpType, PatFrag CmpPred> { 354 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 355 CmpPred:$Vt, CmpPred:$Vs), 356 (PickT CmpPred:$Vs, CmpPred:$Vt)>; 357 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 358 CmpPred:$Vs, CmpPred:$Vt), 359 (PickS CmpPred:$Vs, CmpPred:$Vt)>; 360} 361 362// Bitcasts between same-size vector types are no-ops, except for the 363// actual type change. 364multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> { 365 def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>; 366 def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; 367} 368 369// Frags for commonly used SDNodes. 370def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 371def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 372def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 373 374def Smin: pf2<smin>; def Smax: pf2<smax>; 375def Umin: pf2<umin>; def Umax: pf2<umax>; 376 377def Rol: pf2<rotl>; 378 379// --(1) Immediate ------------------------------------------------------- 380// 381 382def Imm64Lo: SDNodeXForm<imm, [{ 383 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()), 384 SDLoc(N), MVT::i32); 385}]>; 386def Imm64Hi: SDNodeXForm<imm, [{ 387 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32), 388 SDLoc(N), MVT::i32); 389}]>; 390 391 392def SDTHexagonCONST32 393 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 394 395def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 396def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 397def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 398def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 399 400def TruncI64ToI32: SDNodeXForm<imm, [{ 401 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 402}]>; 403 404def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 405def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 406 407def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 408def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 409def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 410def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 411def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 412def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 413def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 414// The HVX load patterns also match CP directly. Make sure that if 415// the selection of this opcode changes, it's updated in all places. 416 417def: Pat<(i1 0), (PS_false)>; 418def: Pat<(i1 1), (PS_true)>; 419def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, 420 Requires<[UseSmallData,NotOptTinyCore]>; 421def: Pat<(i64 imm:$v), 422 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; 423 424def ftoi : SDNodeXForm<fpimm, [{ 425 APInt I = N->getValueAPF().bitcastToAPInt(); 426 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 427 MVT::getIntegerVT(I.getBitWidth())); 428}]>; 429 430def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 431def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 432 433def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 434 435// --(2) Type cast ------------------------------------------------------- 436// 437 438def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 439def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 440 441def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 442def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 443def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 444def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 445 446def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 447def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 448def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 449def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 450 451def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 452def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 453def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 454def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 455 456def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 457def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 458def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 459def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 460 461// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 462def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 463def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 464def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 465def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 466 467// Bit convert 32- and 64-bit types. 468// All of these are bitcastable to one another: i32, v2i16, v4i8. 469defm: NopCast_pat<i32, v2i16, IntRegs>; 470defm: NopCast_pat<i32, v4i8, IntRegs>; 471defm: NopCast_pat<v2i16, v4i8, IntRegs>; 472// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 473defm: NopCast_pat<i64, v2i32, DoubleRegs>; 474defm: NopCast_pat<i64, v4i16, DoubleRegs>; 475defm: NopCast_pat<i64, v8i8, DoubleRegs>; 476defm: NopCast_pat<v2i32, v4i16, DoubleRegs>; 477defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 478defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 479 480 481// --(3) Extend/truncate ------------------------------------------------- 482// 483 484def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 485def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 486def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 487def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 488def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 489 490def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 491def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 492def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 493 494def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 495def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 496def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 497 498let AddedComplexity = 20 in { 499 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 500 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 501} 502 503// Extensions from i1 or vectors of i1. 504def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 505def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 506def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 507def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 508 (C2_muxii PredRegs:$Pu, -1, 0))>; 509 510def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 511def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 512def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 513def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 514def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 515 516def Vsplatpi: OutPatFrag<(ops node:$V), 517 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 518 519def: Pat<(v2i16 (azext V2I1:$Pu)), 520 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 521def: Pat<(v2i32 (azext V2I1:$Pu)), 522 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 523def: Pat<(v4i8 (azext V4I1:$Pu)), 524 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 525def: Pat<(v4i16 (azext V4I1:$Pu)), 526 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 527def: Pat<(v8i8 (azext V8I1:$Pu)), 528 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 529 530def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 531def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 532def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 533def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 534 535def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 536 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 537 538def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 539 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 540 541// Truncate: from vector B copy all 'E'ven 'B'yte elements: 542// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 543def: Pat<(v4i8 (trunc V4I16:$Rs)), 544 (S2_vtrunehb V4I16:$Rs)>; 545 546// Truncate: from vector B copy all 'O'dd 'B'yte elements: 547// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 548// S2_vtrunohb 549 550// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 551// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 552// S2_vtruneh 553 554def: Pat<(v2i16 (trunc V2I32:$Rs)), 555 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 556 557 558// --(4) Logical --------------------------------------------------------- 559// 560 561def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 562def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>; 563def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>; 564def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>; 565def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 566 567multiclass BoolOpR_RR_pat<InstHexagon MI, PatFrag Op> { 568 def: OpR_RR_pat<MI, Op, i1, I1>; 569 def: OpR_RR_pat<MI, Op, v2i1, V2I1>; 570 def: OpR_RR_pat<MI, Op, v4i1, V4I1>; 571 def: OpR_RR_pat<MI, Op, v8i1, V8I1>; 572} 573 574multiclass BoolAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op> { 575 def: AccRRR_pat<MI, AccOp, Op, I1, I1, I1>; 576 def: AccRRR_pat<MI, AccOp, Op, V2I1, V2I1, V2I1>; 577 def: AccRRR_pat<MI, AccOp, Op, V4I1, V4I1, V4I1>; 578 def: AccRRR_pat<MI, AccOp, Op, V8I1, V8I1, V8I1>; 579} 580 581defm: BoolOpR_RR_pat<C2_and, And>; 582defm: BoolOpR_RR_pat<C2_or, Or>; 583defm: BoolOpR_RR_pat<C2_xor, Xor>; 584defm: BoolOpR_RR_pat<C2_andn, Not2<And>>; 585defm: BoolOpR_RR_pat<C2_orn, Not2<Or>>; 586 587// op(Ps, op(Pt, Pu)) 588defm: BoolAccRRR_pat<C4_and_and, And, Su<And>>; 589defm: BoolAccRRR_pat<C4_and_or, And, Su<Or>>; 590defm: BoolAccRRR_pat<C4_or_and, Or, Su<And>>; 591defm: BoolAccRRR_pat<C4_or_or, Or, Su<Or>>; 592 593// op(Ps, op(Pt, ~Pu)) 594defm: BoolAccRRR_pat<C4_and_andn, And, Su<Not2<And>>>; 595defm: BoolAccRRR_pat<C4_and_orn, And, Su<Not2<Or>>>; 596defm: BoolAccRRR_pat<C4_or_andn, Or, Su<Not2<And>>>; 597defm: BoolAccRRR_pat<C4_or_orn, Or, Su<Not2<Or>>>; 598 599 600// --(5) Compare --------------------------------------------------------- 601// 602 603// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 604// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 605 606def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 607def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 608def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 609 610def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 611 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 612def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 613 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 614 615def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 616 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 617def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 618 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 619 620// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 621// that reverse the order of the operands. 622class RevCmp<PatFrag F> 623 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 624 F.OperandTransform>; 625 626def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 627def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 628def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 629def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 630def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 631def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 632def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 633def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 634def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 635def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 636def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 637def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 638def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 639def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 640def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 641def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 642def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 643def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 644def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 645def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 646def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 647def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 648def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 649def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 650def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 651def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 652def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 653def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 654def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 655def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 656def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 657def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 658def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 659def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 660def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 661def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 662def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 663def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 664def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 665def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 666 667def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 668def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 669def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 670def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 671def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 672def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 673def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 674def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 675def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 676def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 677def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 678 679def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 680def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 681def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 682def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 683def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 684def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 685def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 686def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 687def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 688def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 689def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 690 691// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 692 693def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 694 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 695def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 696 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 697def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 698 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 699 700class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 701 PatFrag RsPred, PatFrag RtPred = RsPred> 702 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 703 (Output RsPred:$Rs, RtPred:$Rt)>; 704 705class Outn<InstHexagon MI> 706 : OutPatFrag<(ops node:$Rs, node:$Rt), 707 (C2_not (MI $Rs, $Rt))>; 708 709def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 710def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 711def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 712def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 713def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 714def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 715def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 716def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 717def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 718def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 719def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 720def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 721def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 722def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 723def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 724def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 725def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 726def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 727def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 728def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 729def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 730def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 731def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 732def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 733def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 734 735let AddedComplexity = 100 in { 736 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 737 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 738 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 739 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 740 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 741 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 742 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 743 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 744} 745 746// PatFrag for AsserZext which takes the original type as a parameter. 747def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 748def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 749class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 750 751multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 752 PatLeaf ImmPred, int Mask> { 753 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 754 (MI I32:$Rs, imm:$I)>; 755 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 756 (MI I32:$Rs, imm:$I)>; 757} 758 759multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 760 PatLeaf ImmPred, int Mask> { 761 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 762 (C2_not (MI I32:$Rs, imm:$I))>; 763 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 764 (C2_not (MI I32:$Rs, imm:$I))>; 765} 766 767multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 768 PatLeaf ImmPred, int Mask> { 769 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 770 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 771 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 772 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 773} 774 775let AddedComplexity = 200 in { 776 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 777 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 778 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 779 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 780 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 781 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 782 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 783 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 784} 785 786def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 787 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 788def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 789 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 790def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 791 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 792def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 793 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 794 795def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 796def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 797def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>; 798def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 799 800// Floating-point comparisons with checks for ordered/unordered status. 801 802class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 803 : OutPatFrag<(ops node:$Rs, node:$Rt), 804 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 805 806class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 807class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 808 809class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 810class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 811 812def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 813def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 814def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 815def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 816def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 817def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 818 819def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 820def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 821def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 822def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 823def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 824def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 825 826def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 827def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 828 829def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 830def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 831 832def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 833def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 834 835 836// --(6) Select ---------------------------------------------------------- 837// 838 839def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 840 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 841def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 842 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 843def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 844 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 845def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 846 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 847 848def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 849 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 850def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 851 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 852def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 853 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 854def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 855 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 856 857// Map from a 64-bit select to an emulated 64-bit mux. 858// Hexagon does not support 64-bit MUXes; so emulate with combines. 859def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 860 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 861 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 862 863def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 864 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 865def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 866 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 867def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 868 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 869def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 870 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 871 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 872 873def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 874 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 875def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 876 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 877 878def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 879 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 880def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 881 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 882 883def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 884 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 885def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 886 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 887def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 888 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 889 890def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt), 891 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>; 892def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt), 893 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>; 894def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt), 895 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>; 896 897 898// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 899def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw), 900 (C2_or (C2_and I1:$Pu, I1:$Pv), 901 (C2_andn I1:$Pw, I1:$Pu))>; 902 903 904def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 905 return isPositiveHalfWord(N); 906}]>; 907 908multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 909 InstHexagon InstB> { 910 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 911 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 912 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 913 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 914 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 915 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 916} 917 918let AddedComplexity = 200 in { 919 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 920 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 921 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 922 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 923 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 924 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 925 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 926 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 927} 928 929def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>; 930def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>; 931def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>; 932def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>; 933def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>; 934def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>; 935def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>; 936def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>; 937 938let AddedComplexity = 100 in { 939 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>; 940 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>; 941 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>; 942 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; 943} 944 945let AddedComplexity = 100, Predicates = [HasV67] in { 946 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; 947 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; 948 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; 949 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; 950} 951 952def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>; 953def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>; 954def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>; 955def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>; 956 957def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>; 958def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>; 959def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>; 960def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>; 961 962def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>; 963def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>; 964def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>; 965def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>; 966 967// --(7) Insert/extract -------------------------------------------------- 968// 969 970def SDTHexagonINSERT: 971 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 972 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 973def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 974 975let AddedComplexity = 10 in { 976 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 977 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 978 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 979 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 980} 981def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 982 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 983def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 984 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 985 986def SDTHexagonEXTRACTU 987 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 988 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 989def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 990 991let AddedComplexity = 10 in { 992 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 993 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 994 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 995 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 996} 997def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 998 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 999def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 1000 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 1001 1002def: Pat<(v4i8 (splat_vector anyint:$V)), (ToI32 (SplatB $V))>; 1003def: Pat<(v2i16 (splat_vector anyint:$V)), (ToI32 (SplatH $V))>; 1004def: Pat<(v8i8 (splat_vector anyint:$V)), 1005 (Combinew (ToI32 (SplatB $V)), (ToI32 (SplatB $V)))>; 1006def: Pat<(v4i16 (splat_vector anyint:$V)), 1007 (Combinew (ToI32 (SplatH $V)), (ToI32 (SplatH $V)))>; 1008let AddedComplexity = 10 in 1009def: Pat<(v2i32 (splat_vector s8_0ImmPred:$s8)), 1010 (A2_combineii imm:$s8, imm:$s8)>; 1011def: Pat<(v2i32 (splat_vector anyimm:$V)), (Combinew (ToI32 $V), (ToI32 $V))>; 1012 1013def: Pat<(v4i8 (splat_vector I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 1014def: Pat<(v2i16 (splat_vector I32:$Rs)), (LoReg (S2_vsplatrh I32:$Rs))>; 1015def: Pat<(v4i16 (splat_vector I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 1016def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 1017 1018let AddedComplexity = 10 in 1019def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 1020 Requires<[HasV62]>; 1021def: Pat<(v8i8 (splat_vector I32:$Rs)), 1022 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 1023 1024 1025// --(8) Shift/permute --------------------------------------------------- 1026// 1027 1028def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 1029 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 1030 1031def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 1032 1033def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 1034 1035// The complexity of the combines involving immediates should be greater 1036// than the complexity of the combine with two registers. 1037let AddedComplexity = 50 in { 1038 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 1039 (A4_combineri IntRegs:$Rs, imm:$s8)>; 1040 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 1041 (A4_combineir imm:$s8, IntRegs:$Rs)>; 1042} 1043 1044// The complexity of the combine with two immediates should be greater than 1045// the complexity of a combine involving a register. 1046let AddedComplexity = 75 in { 1047 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 1048 (A4_combineii imm:$s8, imm:$u6)>; 1049 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 1050 (A2_combineii imm:$s8, imm:$S8)>; 1051} 1052 1053def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 1054def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 1055 (A2_swiz (HiReg $Rss)))>; 1056 1057def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 1058def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 1059def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1060 1061def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 1062def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1063def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 1064def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 1065def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1066def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 1067def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 1068def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1069def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 1070def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 1071def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1072def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 1073 1074def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 1075def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1076def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 1077def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 1078def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1079def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1080 1081// Funnel shifts. 1082def IsMul8_U3: PatLeaf<(i32 imm), [{ 1083 uint64_t V = N->getZExtValue(); 1084 return V % 8 == 0 && isUInt<3>(V / 8); 1085}]>; 1086 1087def Divu8: SDNodeXForm<imm, [{ 1088 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1089}]>; 1090 1091// Funnel shift-left. 1092def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1093 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1094def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1095 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1096 1097def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1098 (S2_lsr_i_p_or (S2_asl_i_p $Rs, $S), $Rt, (Subi<64> $S))>; 1099def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1100 (S2_lsr_r_p_or (S2_asl_r_p $Rs, $Ru), $Rt, (A2_subri 64, $Ru))>; 1101 1102// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1103def Divu64_8: SDNodeXForm<imm, [{ 1104 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1105 SDLoc(N), MVT::i32); 1106}]>; 1107 1108// Special cases: 1109let AddedComplexity = 100 in { 1110 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1111 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1112 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1113 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1114} 1115 1116let Predicates = [HasV60], AddedComplexity = 50 in { 1117 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1118 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1119} 1120let AddedComplexity = 30 in { 1121 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1122 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1123 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1124 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1125} 1126def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1127def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1128def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1129def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1130 1131// Funnel shift-right. 1132def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1133 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1134def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1135 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1136 1137def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1138 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1139def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1140 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1141 1142// Special cases: 1143let AddedComplexity = 100 in { 1144 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1145 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1146 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1147 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1148} 1149 1150let Predicates = [HasV60], AddedComplexity = 50 in { 1151 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1152 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1153} 1154let AddedComplexity = 30 in { 1155 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1156 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1157 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1158 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1159} 1160def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1161def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1162def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1163def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1164 1165 1166def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1167 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1168def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1169 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1170 1171// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1172let AddedComplexity = 120 in 1173def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1174 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1175 1176let AddedComplexity = 100 in { 1177 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1178 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1179 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1180 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1181 1182 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1183 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1184 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1185 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1186 1187 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1188 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1189 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1190 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1191 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1192 1193 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1194 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1195 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1196 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1197 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1198 1199 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1200 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1201 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1202 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1203 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1204 1205 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1206 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1207 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1208 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1209 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1210 1211 let Predicates = [HasV60] in { 1212 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1213 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1214 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1215 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1216 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1217 1218 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1219 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1220 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1221 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1222 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1223 } 1224} 1225 1226let AddedComplexity = 100 in { 1227 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1228 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1229 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1230 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1231 1232 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1233 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1234 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1235 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1236 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1237 1238 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1239 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1240 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1241 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1242 1243 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1244 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1245 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1246 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1247 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1248 1249 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1250 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1251 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1252 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1253 1254 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1255 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1256 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1257 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1258 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1259} 1260 1261 1262class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1263 PatFrag RegPred, PatFrag ImmPred> 1264 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1265 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1266 1267let AddedComplexity = 200, Predicates = [UseCompound] in { 1268 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1269 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1270 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1271 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1272 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1273 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1274 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1275 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1276} 1277 1278// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1279// two 32-bit words into a 64-bit word. 1280let AddedComplexity = 200 in 1281def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1282 (Combinew I32:$a, I32:$b)>; 1283 1284def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1285 (Zext64 (and I32:$a, (i32 65535)))), 1286 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1287 (shl (Aext64 I32:$d), (i32 48))), 1288 (Combinew (A2_combine_ll I32:$d, I32:$c), 1289 (A2_combine_ll I32:$b, I32:$a))>; 1290 1291let AddedComplexity = 200 in { 1292 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1293 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1294 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1295 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1296 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1297 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1298 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1299 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1300} 1301 1302def SDTHexagonVShift 1303 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1304 1305def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1306def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1307def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1308 1309def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1310def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1311def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1312def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1313def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1314def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1315 1316def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1317def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1318def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1319def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1320def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1321def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1322 1323def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1324 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1325def: Pat<(srl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1326 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1327def: Pat<(shl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1328 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1329def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1330 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1331def: Pat<(srl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1332 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1333def: Pat<(shl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1334 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1335 1336def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1337 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1338def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1339 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1340def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1341 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1342def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1343 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1344def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1345 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1346def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1347 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1348 1349 1350// --(9) Arithmetic/bitwise ---------------------------------------------- 1351// 1352 1353def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1354def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1355def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1356def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1357def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1358 1359def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1360def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1361 1362def: Pat<(fabs F64:$Rs), 1363 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1364 (i32 (LoReg $Rs)))>; 1365def: Pat<(fneg F64:$Rs), 1366 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1367 (i32 (LoReg $Rs)))>; 1368 1369def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1370def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1371def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1372def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1373 1374def: OpR_RR_pat<A2_add, Add, i32, I32>; 1375def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1376def: OpR_RR_pat<A2_and, And, i32, I32>; 1377def: OpR_RR_pat<A2_or, Or, i32, I32>; 1378def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1379def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1380def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1381def: OpR_RR_pat<A2_andp, And, i64, I64>; 1382def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1383def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1384def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1385def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1386 1387def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1388def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1389 1390def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1391def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1392def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1393def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1394def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1395def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1396 1397def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1398def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1399def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1400def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1401def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1402def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1403def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1404def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1405def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1406def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1407def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1408def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1409def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1410def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1411def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1412 1413def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1414def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1415def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1416def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1417def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1418 1419// Arithmetic on predicates. 1420def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1421def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1422def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1423def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1424def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1425def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1426def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1427def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1428def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1429def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1430def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1431def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1432 1433def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1434def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1435def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1436def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1437def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1438 1439let Predicates = [HasV66] in { 1440 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1441 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1442} 1443 1444def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), 1445 (F2_dfmpyhh 1446 (F2_dfmpylh 1447 (F2_dfmpylh 1448 (F2_dfmpyll $Rs, $Rt), 1449 $Rs, $Rt), 1450 $Rt, $Rs), 1451 $Rs, $Rt)>; 1452 1453let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { 1454 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; 1455} 1456let Predicates = [HasV67] in { 1457 def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; 1458 def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; 1459 1460 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), 1461 (F2_dfmpyfix $Rt, $Rs))>; 1462} 1463 1464// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1465// over add-add with individual multiplies as inputs. 1466let AddedComplexity = 10 in { 1467 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1468 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1469 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1470 let Predicates = [HasV66] in 1471 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1472} 1473 1474def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1475def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1476def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1477 1478// Mulh for vectors 1479// 1480def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1481 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1482 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1483 1484def: Pat<(v2i32 (mulhs V2I32:$Rs, V2I32:$Rt)), 1485 (Combinew (M2_mpy_up (HiReg $Rs), (HiReg $Rt)), 1486 (M2_mpy_up (LoReg $Rt), (LoReg $Rt)))>; 1487 1488def Mulhub: 1489 OutPatFrag<(ops node:$Rss, node:$Rtt), 1490 (Combinew (S2_vtrunohb (M5_vmpybuu (HiReg $Rss), (HiReg $Rtt))), 1491 (S2_vtrunohb (M5_vmpybuu (LoReg $Rss), (LoReg $Rtt))))>; 1492 1493// Equivalent of byte-wise arithmetic shift right by 7 in v8i8. 1494def Asr7: 1495 OutPatFrag<(ops node:$Rss), (C2_mask (C2_not (A4_vcmpbgti $Rss, 0)))>; 1496 1497def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), 1498 (Mulhub $Rss, $Rtt)>; 1499 1500def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), 1501 (A2_vsubub 1502 (Mulhub $Rss, $Rtt), 1503 (A2_vaddub (A2_andp V8I8:$Rss, (Asr7 $Rtt)), 1504 (A2_andp V8I8:$Rtt, (Asr7 $Rss))))>; 1505 1506def Mpysh: 1507 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1508def Mpyshh: 1509 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (HiReg $Rss), (HiReg $Rtt))>; 1510def Mpyshl: 1511 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (LoReg $Rss), (LoReg $Rtt))>; 1512 1513def Mulhsh: 1514 OutPatFrag<(ops node:$Rss, node:$Rtt), 1515 (Combinew (A2_combine_hh (HiReg (Mpyshh $Rss, $Rtt)), 1516 (LoReg (Mpyshh $Rss, $Rtt))), 1517 (A2_combine_hh (HiReg (Mpyshl $Rss, $Rtt)), 1518 (LoReg (Mpyshl $Rss, $Rtt))))>; 1519 1520def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh $Rss, $Rtt)>; 1521 1522def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1523 (A2_vaddh 1524 (Mulhsh $Rss, $Rtt), 1525 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1526 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1527 1528 1529def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1530 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1531 1532def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1533 int64_t V = N->getSExtValue(); 1534 return -255 <= V && V <= 0; 1535}]>; 1536 1537// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1538def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1539 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1540 1541def: Pat<(add Sext64:$Rs, I64:$Rt), 1542 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1543 1544def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1545def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1546def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1547def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1548def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1549def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1550def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1551def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1552def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1553def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1554 1555// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1556// one argument matches the patterns below, and with the other argument 1557// matches S2_asl_r_r_or, etc, prefer the patterns below. 1558let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1559 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1560 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1561 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1562} 1563 1564// S4_addaddi and S4_subaddi don't have tied operands, so give them 1565// a bit of preference. 1566let AddedComplexity = 30, Predicates = [UseCompound] in { 1567 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1568 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1569 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1570 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1571 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1572 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1573 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1574 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1575 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1576 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1577} 1578 1579let Predicates = [UseCompound] in 1580def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1581 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1582 1583def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1584 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1585def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1586 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1587 1588 1589def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1590 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1591def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1592 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1593 1594def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1595 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1596def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1597 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1598def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1599 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1600 1601def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1602 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1603def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1604 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1605def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1606 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1607def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1608 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1609def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1610 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1611def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1612 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1613 1614// Add halfword. 1615def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1616 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1617def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1618 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1619def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1620 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1621 1622// Subtract halfword. 1623def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1624 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1625def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1626 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1627def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1628 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1629 1630def: Pat<(mul I64:$Rss, I64:$Rtt), 1631 (Combinew 1632 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1633 (LoReg $Rss), 1634 (HiReg $Rtt)), 1635 (LoReg $Rtt), 1636 (HiReg $Rss)), 1637 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1638 1639def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1640 (A2_addp 1641 (M2_dpmpyuu_acc_s0 1642 (S2_lsr_i_p 1643 (A2_addp 1644 (M2_dpmpyuu_acc_s0 1645 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1646 (HiReg $Rss), 1647 (LoReg $Rtt)), 1648 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1649 32), 1650 (HiReg $Rss), 1651 (HiReg $Rtt)), 1652 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1653 1654// Multiply 64-bit unsigned and use upper result. 1655def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1656 1657// Multiply 64-bit signed and use upper result. 1658// 1659// For two signed 64-bit integers A and B, let A' and B' denote A and B 1660// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1661// sign bit of A (and identically for B). With this notation, the signed 1662// product A*B can be written as: 1663// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1664// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1665// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1666// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1667 1668// Clear the sign bit in a 64-bit register. 1669def ClearSign : OutPatFrag<(ops node:$Rss), 1670 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1671 1672def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1673 (A2_subp 1674 (MulHU $Rss, $Rtt), 1675 (A2_addp 1676 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1677 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1678 1679// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1680// will put the immediate addend into a register, while these instructions will 1681// use it directly. Such a construct does not appear in the middle of a gep, 1682// where M2_macsip would be preferable. 1683let AddedComplexity = 20, Predicates = [UseCompound] in { 1684 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1685 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1686 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1687 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1688} 1689 1690// Keep these instructions less preferable to M2_macsip/M2_macsin. 1691let Predicates = [UseCompound] in { 1692 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1693 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1694 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1695 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1696 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1697 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1698} 1699 1700def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1701 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1702def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1703 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1704 1705def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1706 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1707def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1708 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1709 1710// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1711// we use the double add v8i8, and use only the low part of the result. 1712def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1713 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1714def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1715 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1716 1717// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1718// half-words, and saturates the result to a 32-bit value, except the 1719// saturation never happens (it can only occur with scaling). 1720def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1721 (LoReg (S2_vtrunewh (A2_combineii 0, 0), 1722 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1723def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1724 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1725 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1726 1727// Multiplies two v4i8 vectors. 1728def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1729 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1730 1731// Multiplies two v8i8 vectors. 1732def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1733 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1734 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1735 1736 1737// --(10) Bit ------------------------------------------------------------ 1738// 1739 1740// Count leading zeros. 1741def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 1742def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1743 1744// Count trailing zeros. 1745def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 1746def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1747 1748// Count leading ones. 1749def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 1750def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1751 1752// Count trailing ones. 1753def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 1754def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1755 1756// Define leading/trailing patterns that require zero-extensions to 64 bits. 1757def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1758def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1759def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1760def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1761 1762def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1763def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1764 1765def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1766def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1767 1768let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1769 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1770 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1771 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1772 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1773 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1774 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1775 1776 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1777 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1778 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1779 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1780 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1781 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1782} 1783 1784// Clr/set/toggle bit for 64-bit values with immediate bit index. 1785let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1786 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1787 (Combinew (i32 (HiReg $Rss)), 1788 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1789 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1790 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1791 (i32 (LoReg $Rss)))>; 1792 1793 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1794 (Combinew (i32 (HiReg $Rss)), 1795 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1796 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1797 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1798 (i32 (LoReg $Rss)))>; 1799 1800 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1801 (Combinew (i32 (HiReg $Rss)), 1802 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1803 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1804 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1805 (i32 (LoReg $Rss)))>; 1806} 1807 1808 1809let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1810 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1811 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1812 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1813 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1814 def: Pat<(i1 (trunc I32:$Rs)), 1815 (S2_tstbit_i IntRegs:$Rs, 0)>; 1816 def: Pat<(i1 (trunc I64:$Rs)), 1817 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1818} 1819 1820def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1), 1821 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>; 1822def: Pat<(and (srl I64:$Rss, IsULE<32,31>:$u6), 1), 1823 (ToZext64 (I1toI32 (S2_tstbit_i (LoReg $Rss), imm:$u6)))>; 1824def: Pat<(and (srl I64:$Rss, IsUGT<32,31>:$u6), 1), 1825 (ToZext64 (I1toI32 (S2_tstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1826 1827def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1), 1828 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>; 1829def: Pat<(and (not (srl I64:$Rss, IsULE<32,31>:$u6)), 1), 1830 (ToZext64 (I1toI32 (S4_ntstbit_i (LoReg $Rss), imm:$u6)))>; 1831def: Pat<(and (not (srl I64:$Rss, IsUGT<32,31>:$u6)), 1), 1832 (ToZext64 (I1toI32 (S4_ntstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1833 1834let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1835 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1836 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1837 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1838 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 1839} 1840 1841let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 1842def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 1843 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 1844 1845def SDTTestBit: 1846 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1847def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 1848 1849def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 1850 (S2_tstbit_i I32:$Rs, imm:$u5)>; 1851def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 1852 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1853 1854// Add extra complexity to prefer these instructions over bitsset/bitsclr. 1855// The reason is that tstbit/ntstbit can be folded into a compound instruction: 1856// if ([!]tstbit(...)) jump ... 1857let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1858 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)), 1859 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1860 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)), 1861 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1862 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1863 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 1864 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1865 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1866} 1867 1868def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)), 1869 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>; 1870def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)), 1871 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>; 1872def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)), 1873 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>; 1874def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)), 1875 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>; 1876 1877// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 1878// represented as a compare against "value & 0xFF", which is an exact match 1879// for cmpb (same for cmph). The patterns below do not contain any additional 1880// complexity that would make them preferable, and if they were actually used 1881// instead of cmpb/cmph, they would result in a compare against register that 1882// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 1883def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1884 (C4_nbitsclri I32:$Rs, imm:$u6)>; 1885def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 1886 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 1887def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 1888 (C4_nbitsset I32:$Rs, I32:$Rt)>; 1889 1890// Special patterns to address certain cases where the "top-down" matching 1891// algorithm would cause suboptimal selection. 1892 1893let AddedComplexity = 100 in { 1894 // Avoid A4_rcmp[n]eqi in these cases: 1895 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1896 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1897 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1898 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1899 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))), 1900 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1901 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))), 1902 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1903 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1904 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>; 1905 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1906 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>; 1907} 1908 1909// --(11) PIC ------------------------------------------------------------ 1910// 1911 1912def SDT_HexagonAtGot 1913 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1914def SDT_HexagonAtPcrel 1915 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 1916 1917// AT_GOT address-of-GOT, address-of-global, offset-in-global 1918def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 1919// AT_PCREL address-of-global 1920def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 1921 1922def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 1923 (L2_loadri_io I32:$got, imm:$addr)>; 1924def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 1925 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 1926def: Pat<(HexagonAtPcrel I32:$addr), 1927 (C4_addipc imm:$addr)>; 1928 1929// The HVX load patterns also match AT_PCREL directly. Make sure that 1930// if the selection of this opcode changes, it's updated in all places. 1931 1932 1933// --(12) Load ----------------------------------------------------------- 1934// 1935 1936def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1937 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1938}]>; 1939def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1940 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1941}]>; 1942 1943def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1944 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1945}]>; 1946def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1947 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1948}]>; 1949 1950def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1951 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1952}]>; 1953def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1954 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1955}]>; 1956 1957// Patterns to select load-indexed: Rs + Off. 1958// - frameindex [+ imm], 1959multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1960 InstHexagon MI> { 1961 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1962 (VT (MI AddrFI:$fi, imm:$Off))>; 1963 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1964 (VT (MI AddrFI:$fi, imm:$Off))>; 1965 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 1966} 1967 1968// Patterns to select load-indexed: Rs + Off. 1969// - base reg [+ imm] 1970multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1971 InstHexagon MI> { 1972 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 1973 (VT (MI IntRegs:$Rs, imm:$Off))>; 1974 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 1975 (VT (MI IntRegs:$Rs, imm:$Off))>; 1976 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 1977} 1978 1979// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 1980multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1981 InstHexagon MI> { 1982 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 1983 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 1984} 1985 1986// Patterns to select load reg indexed: Rs + Off with a value modifier. 1987// - frameindex [+ imm] 1988multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 1989 PatLeaf ImmPred, InstHexagon MI> { 1990 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1991 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 1992 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1993 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 1994 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 1995} 1996 1997// Patterns to select load reg indexed: Rs + Off with a value modifier. 1998// - base reg [+ imm] 1999multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2000 PatLeaf ImmPred, InstHexagon MI> { 2001 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2002 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2003 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2004 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2005 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 2006} 2007 2008// Patterns to select load reg indexed: Rs + Off with a value modifier. 2009// Combines Loadxfim + Loadxgim. 2010multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2011 PatLeaf ImmPred, InstHexagon MI> { 2012 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 2013 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 2014} 2015 2016// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 2017class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2018 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2019 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 2020 2021// Pattern to select load reg reg-indexed: Rs + Rt<<0. 2022class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2023 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2024 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 2025 2026// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 2027class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2028 InstHexagon MI> 2029 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2030 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 2031 2032// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 2033class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2034 InstHexagon MI> 2035 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2036 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 2037 2038// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 2039// Don't match for u2==0, instead use reg+imm for those cases. 2040class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 2041 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2042 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 2043 2044class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 2045 InstHexagon MI> 2046 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2047 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 2048 2049// Pattern to select load absolute. 2050class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 2051 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 2052 2053// Pattern to select load absolute with value modifier. 2054class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 2055 InstHexagon MI> 2056 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 2057 2058 2059let AddedComplexity = 20 in { 2060 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 2061 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 2062 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 2063 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2064 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2065 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 2066 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 2067 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 2068 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2069 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 2070 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 2071 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 2072 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2073 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2074 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 2075 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 2076 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 2077 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 2078 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 2079 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 2080 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 2081 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 2082 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 2083 // No sextloadi1. 2084 2085 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 2086 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 2087 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 2088 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 2089} 2090 2091let AddedComplexity = 30 in { 2092 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 2093 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 2094 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 2095 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 2096 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 2097 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 2098 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 2099 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 2100 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 2101 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 2102 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 2103} 2104 2105let AddedComplexity = 60 in { 2106 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 2107 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 2108 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2109 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2110 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 2111 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 2112 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 2113 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2114 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 2115 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 2116 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2117 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2118 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 2119 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 2120 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 2121 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 2122 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 2123 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 2124 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 2125 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 2126 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2127 2128 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2129 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2130 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2131 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2132 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2133 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2134 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2135 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2136 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2137} 2138 2139let AddedComplexity = 40 in { 2140 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2141 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2142 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2143 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2144 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2145 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2146 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2147 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2148 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2149 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2150 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2151 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2152 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2153 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2154 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2155} 2156 2157let AddedComplexity = 20 in { 2158 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2159 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2160 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2161 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2162 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2163 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2164 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2165 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2166 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2167 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2168 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2169 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2170 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2171 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2172 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2173} 2174 2175let AddedComplexity = 40 in { 2176 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2177 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2178 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2179 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2180 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2181 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2182 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2183 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2184 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2185} 2186 2187let AddedComplexity = 20 in { 2188 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2189 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2190 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2191 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2192 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2193 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2194 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2195 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2196 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2197} 2198 2199// Absolute address 2200 2201let AddedComplexity = 60 in { 2202 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2203 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2204 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2205 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2206 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2207 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2208 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2209 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2210 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2211 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2212 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2213 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2214 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2215 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2216 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2217 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2218 2219 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2220 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2221 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2222 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2223} 2224 2225let AddedComplexity = 30 in { 2226 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2227 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2228 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2229 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2230 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2231 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2232 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2233 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2234 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2235 2236 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2237 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2238} 2239 2240// GP-relative address 2241 2242let AddedComplexity = 100 in { 2243 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2244 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2245 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2246 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2247 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2248 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2249 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2250 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2251 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2252 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2253 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2254 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2255 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2256 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2257 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2258 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2259 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2260 2261 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2262 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2263 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2264 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2265} 2266 2267let AddedComplexity = 70 in { 2268 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2269 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2270 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2271 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2272 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2273 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2274 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2275 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2276 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2277 2278 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2279 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2280} 2281 2282 2283// Sign-extending loads of i1 need to replicate the lowest bit throughout 2284// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should 2285// do the trick. 2286let AddedComplexity = 20 in 2287def: Pat<(i32 (sextloadi1 I32:$Rs)), 2288 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>; 2289 2290// Patterns for loads of i1: 2291def: Pat<(i1 (load AddrFI:$fi)), 2292 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2293def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2294 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2295def: Pat<(i1 (load I32:$Rs)), 2296 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2297 2298 2299// --(13) Store ---------------------------------------------------------- 2300// 2301 2302class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2303 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2304 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2305 2306def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2307def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2308def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2309def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2310 2311// Patterns for generating stores, where the address takes different forms: 2312// - frameindex, 2313// - frameindex + offset, 2314// - base + offset, 2315// - simple (base address without offset). 2316// These would usually be used together (via Storexi_pat defined below), but 2317// in some cases one may want to apply different properties (such as 2318// AddedComplexity) to the individual patterns. 2319class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2320 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2321 2322multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2323 InstHexagon MI> { 2324 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2325 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2326 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2327 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2328} 2329 2330multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2331 InstHexagon MI> { 2332 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2333 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2334 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2335 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2336} 2337 2338class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2339 : Pat<(Store Value:$Rt, I32:$Rs), 2340 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2341 2342// Patterns for generating stores, where the address takes different forms, 2343// and where the value being stored is transformed through the value modifier 2344// ValueMod. The address forms are same as above. 2345class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2346 InstHexagon MI> 2347 : Pat<(Store Value:$Rs, AddrFI:$fi), 2348 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2349 2350multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2351 PatFrag ValueMod, InstHexagon MI> { 2352 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2353 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2354 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2355 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2356} 2357 2358multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2359 PatFrag ValueMod, InstHexagon MI> { 2360 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2361 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2362 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2363 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2364} 2365 2366class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2367 InstHexagon MI> 2368 : Pat<(Store Value:$Rt, I32:$Rs), 2369 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2370 2371multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2372 InstHexagon MI> { 2373 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2374 def: Storexi_fi_pat <Store, Value, MI>; 2375 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2376} 2377 2378multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2379 PatFrag ValueMod, InstHexagon MI> { 2380 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2381 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2382 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2383} 2384 2385// Reg<<S + Imm 2386class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2387 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2388 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2389 2390// Reg<<S + Reg 2391class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2392 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2393 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2394 2395// Reg + Reg 2396class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2397 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2398 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2399 2400class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2401 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2402 2403class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2404 InstHexagon MI> 2405 : Pat<(Store Value:$val, Addr:$addr), 2406 (MI Addr:$addr, (ValueMod Value:$val))>; 2407 2408// Regular stores in the DAG have two operands: value and address. 2409// Atomic stores also have two, but they are reversed: address, value. 2410// To use atomic stores with the patterns, they need to have their operands 2411// swapped. This relies on the knowledge that the F.Fragment uses names 2412// "ptr" and "val". 2413class AtomSt<PatFrag F> 2414 : PatFrag<(ops node:$val, node:$ptr), !head(F.Fragments), F.PredicateCode, 2415 F.OperandTransform> { 2416 let IsAtomic = F.IsAtomic; 2417 let MemoryVT = F.MemoryVT; 2418} 2419 2420 2421def IMM_BYTE : SDNodeXForm<imm, [{ 2422 // -1 can be represented as 255, etc. 2423 // assigning to a byte restores our desired signed value. 2424 int8_t imm = N->getSExtValue(); 2425 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2426}]>; 2427 2428def IMM_HALF : SDNodeXForm<imm, [{ 2429 // -1 can be represented as 65535, etc. 2430 // assigning to a short restores our desired signed value. 2431 int16_t imm = N->getSExtValue(); 2432 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2433}]>; 2434 2435def IMM_WORD : SDNodeXForm<imm, [{ 2436 // -1 can be represented as 4294967295, etc. 2437 // Currently, it's not doing this. But some optimization 2438 // might convert -1 to a large +ve number. 2439 // assigning to a word restores our desired signed value. 2440 int32_t imm = N->getSExtValue(); 2441 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2442}]>; 2443 2444def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2445def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2446def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2447 2448// Even though the offset is not extendable in the store-immediate, we 2449// can still generate the fi# in the base address. If the final offset 2450// is not valid for the instruction, we will replace it with a scratch 2451// register. 2452class SmallStackStore<PatFrag Store> 2453 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2454 return isSmallStackStore(cast<StoreSDNode>(N)); 2455}]>; 2456 2457// This is the complement of SmallStackStore. 2458class LargeStackStore<PatFrag Store> 2459 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2460 return !isSmallStackStore(cast<StoreSDNode>(N)); 2461}]>; 2462 2463// Preferred addressing modes for various combinations of stored value 2464// and address computation. 2465// For stores where the address and value are both immediates, prefer 2466// store-immediate. The reason is that the constant-extender optimization 2467// can replace store-immediate with a store-register, but there is nothing 2468// to generate a store-immediate out of a store-register. 2469// 2470// C R F F+C R+C R+R R<<S+C R<<S+R 2471// --+-------+-----+-----+------+-----+-----+--------+-------- 2472// C | imm | imm | imm | imm | imm | rr | ur | rr 2473// R | abs* | io | io | io | io | rr | ur | rr 2474// 2475// (*) Absolute or GP-relative. 2476// 2477// Note that any expression can be matched by Reg. In particular, an immediate 2478// can always be placed in a register, so patterns checking for Imm should 2479// have a higher priority than the ones involving Reg that could also match. 2480// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2481// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2482// Reg alone. 2483// 2484// The order in which the different combinations are tried: 2485// 2486// C F R F+C R+C R+R R<<S+C R<<S+R 2487// --+-------+-----+-----+------+-----+-----+--------+-------- 2488// C | 1 | 6 | - | 5 | 9 | - | - | - 2489// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2490 2491 2492// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2493// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2494// implies that Reg is also a proper multiple of 4. To still generate a 2495// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2496 2497def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2498 int64_t v = (int64_t)N->getSExtValue(); 2499 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2500}]>; 2501def RoundTo8 : SDNodeXForm<imm, [{ 2502 int32_t Imm = N->getSExtValue(); 2503 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2504}]>; 2505 2506let AddedComplexity = 150 in 2507def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2508 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2509 2510class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2511 : Pat<(Store Value:$val, anyimm:$addr), 2512 (MI (ToI32 $addr), 0, Value:$val)>; 2513class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2514 InstHexagon MI> 2515 : Pat<(Store Value:$val, anyimm:$addr), 2516 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2517 2518let AddedComplexity = 140 in { 2519 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2520 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2521 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2522 2523 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2524 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2525 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2526} 2527 2528// GP-relative address 2529let AddedComplexity = 120 in { 2530 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2531 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2532 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2533 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2534 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2535 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2536 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2537 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2538 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2539 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2540 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2541 def: Storea_pat<AtomSt<atomic_store_8>, I32, addrgp, S2_storerbgp>; 2542 def: Storea_pat<AtomSt<atomic_store_16>, I32, addrgp, S2_storerhgp>; 2543 def: Storea_pat<AtomSt<atomic_store_32>, I32, addrgp, S2_storerigp>; 2544 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, addrgp, S2_storerigp>; 2545 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, addrgp, S2_storerigp>; 2546 def: Storea_pat<AtomSt<atomic_store_64>, I64, addrgp, S2_storerdgp>; 2547 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, addrgp, S2_storerdgp>; 2548 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, addrgp, S2_storerdgp>; 2549 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, addrgp, S2_storerdgp>; 2550 2551 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2552 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2553 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2554 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2555} 2556 2557// Absolute address 2558let AddedComplexity = 110 in { 2559 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2560 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2561 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2562 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2563 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2564 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2565 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2566 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2567 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2568 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2569 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2570 def: Storea_pat<AtomSt<atomic_store_8>, I32, anyimm0, PS_storerbabs>; 2571 def: Storea_pat<AtomSt<atomic_store_16>, I32, anyimm1, PS_storerhabs>; 2572 def: Storea_pat<AtomSt<atomic_store_32>, I32, anyimm2, PS_storeriabs>; 2573 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, PS_storeriabs>; 2574 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, PS_storeriabs>; 2575 def: Storea_pat<AtomSt<atomic_store_64>, I64, anyimm3, PS_storerdabs>; 2576 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, PS_storerdabs>; 2577 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, PS_storerdabs>; 2578 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, PS_storerdabs>; 2579 2580 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2581 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2582 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2583 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2584} 2585 2586// Reg<<S + Imm 2587let AddedComplexity = 100 in { 2588 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2589 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2590 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2591 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2592 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2593 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2594 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2595 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2596 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2597 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2598 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2599 2600 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2601 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2602} 2603 2604// Reg<<S + Reg 2605let AddedComplexity = 90 in { 2606 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2607 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2608 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2609 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2610 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2611 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2612 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2613 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2614 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2615 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2616 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2617 2618 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2619 (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2620} 2621 2622class SS_<PatFrag F> : SmallStackStore<F>; 2623class LS_<PatFrag F> : LargeStackStore<F>; 2624 2625multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2626 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2627} 2628multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2629 defm: Storexi_fi_add_pat<S, V, O, I>; 2630} 2631 2632// Fi+Imm, store-immediate 2633let AddedComplexity = 80 in { 2634 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2635 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2636 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2637 2638 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2639 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2640 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2641 2642 // For large-stack stores, generate store-register (prefer explicit Fi 2643 // in the address). 2644 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2645 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2646 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2647} 2648 2649// Fi, store-immediate 2650let AddedComplexity = 70 in { 2651 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2652 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2653 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2654 2655 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2656 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2657 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2658 2659 // For large-stack stores, generate store-register (prefer explicit Fi 2660 // in the address). 2661 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2662 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2663 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2664} 2665 2666// Fi+Imm, Fi, store-register 2667let AddedComplexity = 60 in { 2668 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2669 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2670 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2671 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2672 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2673 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2674 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2675 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2676 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2677 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2678 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2679 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2680 2681 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2682 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2683 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2684 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2685 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2686 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2687 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2688 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2689 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2690 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2691 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2692 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2693} 2694 2695 2696multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2697 defm: Storexim_add_pat<S, V, O, M, I>; 2698} 2699multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2700 defm: Storexi_add_pat<S, V, O, I>; 2701} 2702 2703// Reg+Imm, store-immediate 2704let AddedComplexity = 50 in { 2705 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2706 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2707 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2708 2709 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2710 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2711 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2712} 2713 2714// Reg+Imm, store-register 2715let AddedComplexity = 40 in { 2716 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2717 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2718 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2719 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2720 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2721 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2722 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2723 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2724 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2725 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2726 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2727 2728 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2729 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2730 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2731 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2732 2733 defm: Storexi_pat<AtomSt<atomic_store_8>, I32, anyimm0, S2_storerb_io>; 2734 defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>; 2735 defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>; 2736 defm: Storexi_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, S2_storeri_io>; 2737 defm: Storexi_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, S2_storeri_io>; 2738 defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>; 2739 defm: Storexi_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, S2_storerd_io>; 2740 defm: Storexi_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, S2_storerd_io>; 2741 defm: Storexi_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, S2_storerd_io>; 2742} 2743 2744// Reg+Reg 2745let AddedComplexity = 30 in { 2746 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2747 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2748 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2749 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2750 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2751 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2752 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2753 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2754 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2755 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2756 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2757 2758 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2759 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2760} 2761 2762// Reg, store-immediate 2763let AddedComplexity = 20 in { 2764 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2765 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2766 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2767 2768 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2769 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2770 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2771} 2772 2773// Reg, store-register 2774let AddedComplexity = 10 in { 2775 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2776 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2777 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2778 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2779 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2780 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2781 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2782 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2783 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2784 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2785 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2786 2787 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2788 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2789 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2790 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2791 2792 def: Storexi_base_pat<AtomSt<atomic_store_8>, I32, S2_storerb_io>; 2793 def: Storexi_base_pat<AtomSt<atomic_store_16>, I32, S2_storerh_io>; 2794 def: Storexi_base_pat<AtomSt<atomic_store_32>, I32, S2_storeri_io>; 2795 def: Storexi_base_pat<AtomSt<atomic_store_32>, V4I8, S2_storeri_io>; 2796 def: Storexi_base_pat<AtomSt<atomic_store_32>, V2I16, S2_storeri_io>; 2797 def: Storexi_base_pat<AtomSt<atomic_store_64>, I64, S2_storerd_io>; 2798 def: Storexi_base_pat<AtomSt<atomic_store_64>, V8I8, S2_storerd_io>; 2799 def: Storexi_base_pat<AtomSt<atomic_store_64>, V4I16, S2_storerd_io>; 2800 def: Storexi_base_pat<AtomSt<atomic_store_64>, V2I32, S2_storerd_io>; 2801} 2802 2803 2804// --(14) Memop ---------------------------------------------------------- 2805// 2806 2807def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2808 int8_t V = N->getSExtValue(); 2809 return -32 < V && V <= -1; 2810}]>; 2811 2812def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2813 int16_t V = N->getSExtValue(); 2814 return -32 < V && V <= -1; 2815}]>; 2816 2817def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2818 int64_t V = N->getSExtValue(); 2819 return -31 <= V && V <= -1; 2820}]>; 2821 2822def IsNPow2_8 : PatLeaf<(i32 imm), [{ 2823 uint8_t NV = ~N->getZExtValue(); 2824 return isPowerOf2_32(NV); 2825}]>; 2826 2827def IsNPow2_16 : PatLeaf<(i32 imm), [{ 2828 uint16_t NV = ~N->getZExtValue(); 2829 return isPowerOf2_32(NV); 2830}]>; 2831 2832def Log2_8 : SDNodeXForm<imm, [{ 2833 uint8_t V = N->getZExtValue(); 2834 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2835}]>; 2836 2837def Log2_16 : SDNodeXForm<imm, [{ 2838 uint16_t V = N->getZExtValue(); 2839 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2840}]>; 2841 2842def LogN2_8 : SDNodeXForm<imm, [{ 2843 uint8_t NV = ~N->getZExtValue(); 2844 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2845}]>; 2846 2847def LogN2_16 : SDNodeXForm<imm, [{ 2848 uint16_t NV = ~N->getZExtValue(); 2849 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2850}]>; 2851 2852def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 2853 2854multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2855 InstHexagon MI> { 2856 // Addr: i32 2857 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 2858 (MI I32:$Rs, 0, I32:$A)>; 2859 // Addr: fi 2860 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 2861 (MI AddrFI:$Rs, 0, I32:$A)>; 2862} 2863 2864multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2865 SDNode Oper, InstHexagon MI> { 2866 // Addr: i32 2867 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 2868 (add I32:$Rs, ImmPred:$Off)), 2869 (MI I32:$Rs, imm:$Off, I32:$A)>; 2870 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 2871 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2872 (MI I32:$Rs, imm:$Off, I32:$A)>; 2873 // Addr: fi 2874 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2875 (add AddrFI:$Rs, ImmPred:$Off)), 2876 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2877 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2878 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2879 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2880} 2881 2882multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2883 SDNode Oper, InstHexagon MI> { 2884 let Predicates = [UseMEMOPS] in { 2885 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 2886 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 2887 } 2888} 2889 2890let AddedComplexity = 200 in { 2891 // add reg 2892 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 2893 /*anyext*/ L4_add_memopb_io>; 2894 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 2895 /*sext*/ L4_add_memopb_io>; 2896 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 2897 /*zext*/ L4_add_memopb_io>; 2898 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 2899 /*anyext*/ L4_add_memoph_io>; 2900 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 2901 /*sext*/ L4_add_memoph_io>; 2902 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 2903 /*zext*/ L4_add_memoph_io>; 2904 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 2905 2906 // sub reg 2907 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 2908 /*anyext*/ L4_sub_memopb_io>; 2909 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 2910 /*sext*/ L4_sub_memopb_io>; 2911 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 2912 /*zext*/ L4_sub_memopb_io>; 2913 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 2914 /*anyext*/ L4_sub_memoph_io>; 2915 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 2916 /*sext*/ L4_sub_memoph_io>; 2917 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 2918 /*zext*/ L4_sub_memoph_io>; 2919 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 2920 2921 // and reg 2922 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 2923 /*anyext*/ L4_and_memopb_io>; 2924 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 2925 /*sext*/ L4_and_memopb_io>; 2926 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 2927 /*zext*/ L4_and_memopb_io>; 2928 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 2929 /*anyext*/ L4_and_memoph_io>; 2930 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 2931 /*sext*/ L4_and_memoph_io>; 2932 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 2933 /*zext*/ L4_and_memoph_io>; 2934 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 2935 2936 // or reg 2937 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 2938 /*anyext*/ L4_or_memopb_io>; 2939 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 2940 /*sext*/ L4_or_memopb_io>; 2941 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 2942 /*zext*/ L4_or_memopb_io>; 2943 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 2944 /*anyext*/ L4_or_memoph_io>; 2945 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 2946 /*sext*/ L4_or_memoph_io>; 2947 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 2948 /*zext*/ L4_or_memoph_io>; 2949 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 2950} 2951 2952 2953multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2954 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 2955 // Addr: i32 2956 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 2957 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 2958 // Addr: fi 2959 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 2960 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 2961} 2962 2963multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2964 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 2965 InstHexagon MI> { 2966 // Addr: i32 2967 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 2968 (add I32:$Rs, ImmPred:$Off)), 2969 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2970 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 2971 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2972 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2973 // Addr: fi 2974 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 2975 (add AddrFI:$Rs, ImmPred:$Off)), 2976 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2977 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 2978 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2979 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 2980} 2981 2982multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2983 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 2984 InstHexagon MI> { 2985 let Predicates = [UseMEMOPS] in { 2986 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 2987 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 2988 } 2989} 2990 2991let AddedComplexity = 220 in { 2992 // add imm 2993 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2994 /*anyext*/ IdImm, L4_iadd_memopb_io>; 2995 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2996 /*sext*/ IdImm, L4_iadd_memopb_io>; 2997 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 2998 /*zext*/ IdImm, L4_iadd_memopb_io>; 2999 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3000 /*anyext*/ IdImm, L4_iadd_memoph_io>; 3001 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3002 /*sext*/ IdImm, L4_iadd_memoph_io>; 3003 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3004 /*zext*/ IdImm, L4_iadd_memoph_io>; 3005 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 3006 L4_iadd_memopw_io>; 3007 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3008 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 3009 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3010 /*sext*/ NegImm8, L4_iadd_memopb_io>; 3011 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3012 /*zext*/ NegImm8, L4_iadd_memopb_io>; 3013 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3014 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 3015 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3016 /*sext*/ NegImm16, L4_iadd_memoph_io>; 3017 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3018 /*zext*/ NegImm16, L4_iadd_memoph_io>; 3019 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 3020 L4_iadd_memopw_io>; 3021 3022 // sub imm 3023 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3024 /*anyext*/ IdImm, L4_isub_memopb_io>; 3025 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3026 /*sext*/ IdImm, L4_isub_memopb_io>; 3027 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3028 /*zext*/ IdImm, L4_isub_memopb_io>; 3029 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3030 /*anyext*/ IdImm, L4_isub_memoph_io>; 3031 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3032 /*sext*/ IdImm, L4_isub_memoph_io>; 3033 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3034 /*zext*/ IdImm, L4_isub_memoph_io>; 3035 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 3036 L4_isub_memopw_io>; 3037 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3038 /*anyext*/ NegImm8, L4_isub_memopb_io>; 3039 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3040 /*sext*/ NegImm8, L4_isub_memopb_io>; 3041 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3042 /*zext*/ NegImm8, L4_isub_memopb_io>; 3043 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3044 /*anyext*/ NegImm16, L4_isub_memoph_io>; 3045 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3046 /*sext*/ NegImm16, L4_isub_memoph_io>; 3047 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3048 /*zext*/ NegImm16, L4_isub_memoph_io>; 3049 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 3050 L4_isub_memopw_io>; 3051 3052 // clrbit imm 3053 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3054 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 3055 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3056 /*sext*/ LogN2_8, L4_iand_memopb_io>; 3057 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3058 /*zext*/ LogN2_8, L4_iand_memopb_io>; 3059 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3060 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 3061 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3062 /*sext*/ LogN2_16, L4_iand_memoph_io>; 3063 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3064 /*zext*/ LogN2_16, L4_iand_memoph_io>; 3065 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 3066 LogN2_32, L4_iand_memopw_io>; 3067 3068 // setbit imm 3069 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3070 /*anyext*/ Log2_8, L4_ior_memopb_io>; 3071 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3072 /*sext*/ Log2_8, L4_ior_memopb_io>; 3073 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3074 /*zext*/ Log2_8, L4_ior_memopb_io>; 3075 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3076 /*anyext*/ Log2_16, L4_ior_memoph_io>; 3077 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3078 /*sext*/ Log2_16, L4_ior_memoph_io>; 3079 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3080 /*zext*/ Log2_16, L4_ior_memoph_io>; 3081 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 3082 Log2_32, L4_ior_memopw_io>; 3083} 3084 3085 3086// --(15) Call ----------------------------------------------------------- 3087// 3088 3089// Pseudo instructions. 3090def SDT_SPCallSeqStart 3091 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3092def SDT_SPCallSeqEnd 3093 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3094 3095def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 3096 [SDNPHasChain, SDNPOutGlue]>; 3097def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 3098 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 3099 3100def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3101 3102def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 3103 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3104def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 3105 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3106def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 3107 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3108 3109def: Pat<(callseq_start timm:$amt, timm:$amt2), 3110 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 3111def: Pat<(callseq_end timm:$amt1, timm:$amt2), 3112 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 3113 3114def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 3115def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 3116def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 3117 3118def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 3119def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 3120def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 3121def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 3122 3123def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 3124def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 3125def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 3126 3127def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 3128 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3129def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3130 3131def: Pat<(retflag), (PS_jmpret (i32 R31))>; 3132def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3133 3134 3135// --(16) Branch --------------------------------------------------------- 3136// 3137 3138def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3139def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3140 3141def: Pat<(brcond I1:$Pu, bb:$dst), 3142 (J2_jumpt I1:$Pu, bb:$dst)>; 3143def: Pat<(brcond (not I1:$Pu), bb:$dst), 3144 (J2_jumpf I1:$Pu, bb:$dst)>; 3145def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3146 (J2_jumpf I1:$Pu, bb:$dst)>; 3147def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3148 (J2_jumpf I1:$Pu, bb:$dst)>; 3149def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3150 (J2_jumpt I1:$Pu, bb:$dst)>; 3151 3152 3153// --(17) Misc ----------------------------------------------------------- 3154 3155 3156// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3157// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3158// The isdigit transformation relies on two 'clever' aspects: 3159// 1) The data type is unsigned which allows us to eliminate a zero test after 3160// biasing the expression by 48. We are depending on the representation of 3161// the unsigned types, and semantics. 3162// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3163// 3164// For the C code: 3165// retval = (c >= '0' && c <= '9') ? 1 : 0; 3166// The code is transformed upstream of llvm into 3167// retval = (c-48) < 10 ? 1 : 0; 3168 3169def u7_0PosImmPred : ImmLeaf<i32, [{ 3170 // True if the immediate fits in an 7-bit unsigned field and is positive. 3171 return Imm > 0 && isUInt<7>(Imm); 3172}]>; 3173 3174let AddedComplexity = 139 in 3175def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3176 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3177 3178let AddedComplexity = 100 in 3179def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3180 (i32 (extloadi8 (add I32:$b, 3))), 3181 24, 8), 3182 (i32 16)), 3183 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3184 (zextloadi8 I32:$b)), 3185 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3186 3187 3188// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3189// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3190// We don't really want either one here. 3191def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3192def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3193 [SDNPHasChain]>; 3194 3195def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3196 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3197def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3198 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3199 3200def SDTHexagonALLOCA 3201 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3202def HexagonALLOCA 3203 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3204 3205def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3206 (PS_alloca IntRegs:$Rs, imm:$A)>; 3207 3208def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3209def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3210 3211def: Pat<(trap), (PS_crash)>; 3212 3213// Read cycle counter. 3214def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3215def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3216 [SDNPHasChain]>; 3217 3218def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3219 3220// The declared return value of the store-locked intrinsics is i32, but 3221// the instructions actually define i1. To avoid register copies from 3222// IntRegs to PredRegs and back, fold the entire pattern checking the 3223// result against true/false. 3224let AddedComplexity = 100 in { 3225 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3226 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3227 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3228 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3229 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3230 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3231 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3232 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3233} 3234