1//===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate/saturate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def SDTVecLeaf: 91 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 92def SDTVecVecIntOp: 93 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 94 SDTCisVT<3,i32>]>; 95 96def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>; 97def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>; 98def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 99def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 100def HexagonMULHUS: SDNode<"HexagonISD::MULHUS", SDTIntBinOp>; 101 102def SDTSaturate: 103 SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, SDTCisVT<2, OtherVT>]>; 104def HexagonSSAT: SDNode<"HexagonISD::SSAT", SDTSaturate>; 105def HexagonUSAT: SDNode<"HexagonISD::USAT", SDTSaturate>; 106 107def ptrue: PatFrag<(ops), (HexagonPTRUE)>; 108def pfalse: PatFrag<(ops), (HexagonPFALSE)>; 109def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>; 110 111def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 112 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 113def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 114 115def ssat: PatFrag<(ops node:$V, node:$Ty), (HexagonSSAT node:$V, node:$Ty)>; 116def usat: PatFrag<(ops node:$V, node:$Ty), (HexagonUSAT node:$V, node:$Ty)>; 117 118// Pattern fragments to extract the low and high subregisters from a 119// 64-bit value. 120def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_lo)>; 121def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>; 122 123def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 124 return isOrEquivalentToAdd(N); 125}]>; 126 127def IsPow2_32: PatLeaf<(i32 imm), [{ 128 uint32_t V = N->getZExtValue(); 129 return isPowerOf2_32(V); 130}]>; 131 132def IsPow2_64: PatLeaf<(i64 imm), [{ 133 uint64_t V = N->getZExtValue(); 134 return isPowerOf2_64(V); 135}]>; 136 137def IsNPow2_32: PatLeaf<(i32 imm), [{ 138 uint32_t NV = ~N->getZExtValue(); 139 return isPowerOf2_32(NV); 140}]>; 141 142def IsPow2_64L: PatLeaf<(i64 imm), [{ 143 uint64_t V = N->getZExtValue(); 144 return isPowerOf2_64(V) && Log2_64(V) < 32; 145}]>; 146 147def IsPow2_64H: PatLeaf<(i64 imm), [{ 148 uint64_t V = N->getZExtValue(); 149 return isPowerOf2_64(V) && Log2_64(V) >= 32; 150}]>; 151 152def IsNPow2_64L: PatLeaf<(i64 imm), [{ 153 uint64_t NV = ~N->getZExtValue(); 154 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 155}]>; 156 157def IsNPow2_64H: PatLeaf<(i64 imm), [{ 158 uint64_t NV = ~N->getZExtValue(); 159 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 160}]>; 161 162class IsULE<int Width, int Arg>: PatLeaf<(i32 imm), 163 "uint64_t V = N->getZExtValue();" # 164 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";" 165>; 166 167class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 168 "uint64_t V = N->getZExtValue();" # 169 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 170>; 171 172def SDEC1: SDNodeXForm<imm, [{ 173 int32_t V = N->getSExtValue(); 174 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 175}]>; 176 177def UDEC1: SDNodeXForm<imm, [{ 178 uint32_t V = N->getZExtValue(); 179 assert(V >= 1); 180 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 181}]>; 182 183def UDEC32: SDNodeXForm<imm, [{ 184 uint32_t V = N->getZExtValue(); 185 assert(V >= 32); 186 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 187}]>; 188 189class Subi<int From>: SDNodeXForm<imm, 190 "int32_t V = " # From # " - N->getSExtValue();" # 191 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 192>; 193 194def Log2_32: SDNodeXForm<imm, [{ 195 uint32_t V = N->getZExtValue(); 196 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 197}]>; 198 199def Log2_64: SDNodeXForm<imm, [{ 200 uint64_t V = N->getZExtValue(); 201 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 202}]>; 203 204def LogN2_32: SDNodeXForm<imm, [{ 205 uint32_t NV = ~N->getZExtValue(); 206 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 207}]>; 208 209def LogN2_64: SDNodeXForm<imm, [{ 210 uint64_t NV = ~N->getZExtValue(); 211 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 212}]>; 213 214def NegImm8: SDNodeXForm<imm, [{ 215 int8_t NV = -N->getSExtValue(); 216 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 217}]>; 218 219def NegImm16: SDNodeXForm<imm, [{ 220 int16_t NV = -N->getSExtValue(); 221 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 222}]>; 223 224def NegImm32: SDNodeXForm<imm, [{ 225 int32_t NV = -N->getSExtValue(); 226 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 227}]>; 228 229def SplatB: SDNodeXForm<imm, [{ 230 uint32_t V = N->getZExtValue(); 231 assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF); 232 V &= 0xFF; 233 uint32_t S = V << 24 | V << 16 | V << 8 | V; 234 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32); 235}]>; 236 237def SplatH: SDNodeXForm<imm, [{ 238 uint32_t V = N->getZExtValue(); 239 assert(isUInt<16>(V) || V >> 16 == 0xFFFF); 240 V &= 0xFFFF; 241 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32); 242}]>; 243 244 245// Helpers for type promotions/contractions. 246def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 247def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 248def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 249def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 250def ToAext64: OutPatFrag<(ops node:$Rs), 251 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 252 253def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 254 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 255 256def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 257def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 258def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 259def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 260 261// Global address or an aligned constant. 262def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 263def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 264def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 265def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 266 267def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 268def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 269def f32zero: PatLeaf<(f32 fpimm:$F), [{ 270 return N->isExactlyValue(APFloat::getZero(APFloat::IEEEsingle(), false)); 271}]>; 272 273// This complex pattern is really only to detect various forms of 274// sign-extension i32->i64. The selected value will be of type i64 275// whose low word is the value being extended. The high word is 276// unspecified. 277def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 278 279def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 280def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 281def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 282 283def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 284def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 285 286def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 287 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 288 289 290// Converters from unary/binary SDNode to PatFrag. 291class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 292class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 293 294class Not2<PatFrag P> 295 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 296class VNot2<PatFrag P, PatFrag Not> 297 : PatFrag<(ops node:$A, node:$B), (P node:$A, (Not node:$B))>; 298 299// If there is a constant operand that feeds the and/or instruction, 300// do not generate the compound instructions. 301// It is not always profitable, as some times we end up with a transfer. 302// Check the below example. 303// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 304// Instead this is preferable. 305// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 306class Su_ni1<PatFrag Op> 307 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 308 if (hasOneUse(N)){ 309 // Check if Op1 is an immediate operand. 310 SDValue Op1 = N->getOperand(1); 311 return !isa<ConstantSDNode>(Op1); 312 } 313 return false;}], 314 Op.OperandTransform>; 315 316class Su<PatFrag Op> 317 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 318 Op.OperandTransform>; 319 320// Main selection macros. 321 322class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 323 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 324 325class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 326 PatFrag RegPred, PatFrag ImmPred> 327 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 328 (MI RegPred:$Rs, imm:$I)>; 329 330class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 331 PatFrag RsPred, PatFrag RtPred = RsPred> 332 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 333 (MI RsPred:$Rs, RtPred:$Rt)>; 334 335class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 336 PatFrag RegPred, PatFrag ImmPred> 337 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 338 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 339 340class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 341 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 344 345multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 346 InstHexagon InstA, InstHexagon InstB> { 347 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 348 (InstA Val:$A, Val:$B)>; 349 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 350 (InstB Val:$A, Val:$B)>; 351} 352 353multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, 354 SDPatternOperator Sel, SDPatternOperator CmpOp, 355 ValueType CmpType, PatFrag CmpPred> { 356 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 357 CmpPred:$Vt, CmpPred:$Vs), 358 (PickT CmpPred:$Vs, CmpPred:$Vt)>; 359 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 360 CmpPred:$Vs, CmpPred:$Vt), 361 (PickS CmpPred:$Vs, CmpPred:$Vt)>; 362} 363 364// Bitcasts between same-size vector types are no-ops, except for the 365// actual type change. 366multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> { 367 def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>; 368 def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; 369} 370 371// Frags for commonly used SDNodes. 372def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 373def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 374def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 375 376def Smin: pf2<smin>; def Smax: pf2<smax>; 377def Umin: pf2<umin>; def Umax: pf2<umax>; 378 379def Rol: pf2<rotl>; 380 381def Fptosi: pf1<fp_to_sint>; 382def Fptoui: pf1<fp_to_uint>; 383def Sitofp: pf1<sint_to_fp>; 384def Uitofp: pf1<uint_to_fp>; 385 386 387// --(1) Immediate ------------------------------------------------------- 388// 389 390def Imm64Lo: SDNodeXForm<imm, [{ 391 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()), 392 SDLoc(N), MVT::i32); 393}]>; 394def Imm64Hi: SDNodeXForm<imm, [{ 395 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32), 396 SDLoc(N), MVT::i32); 397}]>; 398 399 400def SDTHexagonCONST32 401 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 402 403def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 404def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 405def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 406def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 407 408def TruncI64ToI32: SDNodeXForm<imm, [{ 409 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 410}]>; 411 412def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 413def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 414 415def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 416def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 417def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 418def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 419def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 420def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 421def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 422// The HVX load patterns also match CP directly. Make sure that if 423// the selection of this opcode changes, it's updated in all places. 424 425def: Pat<(i1 0), (PS_false)>; 426def: Pat<(i1 1), (PS_true)>; 427def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, 428 Requires<[UseSmallData,NotOptTinyCore]>; 429def: Pat<(i64 imm:$v), 430 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; 431 432def ftoi : SDNodeXForm<fpimm, [{ 433 APInt I = N->getValueAPF().bitcastToAPInt(); 434 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 435 MVT::getIntegerVT(I.getBitWidth())); 436}]>; 437 438def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 439def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 440 441def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 442 443// --(2) Type cast ------------------------------------------------------- 444// 445 446def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 447def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 448 449def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 450def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 451def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 452def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 453 454def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 455def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 456def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 457def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 458 459def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 460def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 461def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 462def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 463 464def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 465def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 466def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 467def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 468 469// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 470def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 471def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 472def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 473def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 474 475// Bit convert 32- and 64-bit types. 476// All of these are bitcastable to one another: i32, v2i16, v4i8. 477defm: NopCast_pat<i32, v2i16, IntRegs>; 478defm: NopCast_pat<i32, v4i8, IntRegs>; 479defm: NopCast_pat<v2i16, v4i8, IntRegs>; 480// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 481defm: NopCast_pat<i64, v2i32, DoubleRegs>; 482defm: NopCast_pat<i64, v4i16, DoubleRegs>; 483defm: NopCast_pat<i64, v8i8, DoubleRegs>; 484defm: NopCast_pat<v2i32, v4i16, DoubleRegs>; 485defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 486defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 487 488 489// --(3) Extend/truncate/saturate ---------------------------------------- 490// 491 492def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 493def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 494def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 495def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 496def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 497 498def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 499def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 500def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 501 502def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 503def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 504def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 505 506let AddedComplexity = 20 in { 507 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 508 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 509} 510 511// Extensions from i1 or vectors of i1. 512def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 513def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 514def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 515def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 516 (C2_muxii PredRegs:$Pu, -1, 0))>; 517 518def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 519def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 520def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 521def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 522def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 523 524def Vsplatpi: OutPatFrag<(ops node:$V), 525 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 526 527def: Pat<(v2i16 (azext V2I1:$Pu)), 528 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 529def: Pat<(v2i32 (azext V2I1:$Pu)), 530 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 531def: Pat<(v4i8 (azext V4I1:$Pu)), 532 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 533def: Pat<(v4i16 (azext V4I1:$Pu)), 534 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 535def: Pat<(v8i8 (azext V8I1:$Pu)), 536 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 537 538def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 539def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 540def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 541def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 542 543def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 544 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 545 546def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 547 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 548 549// Truncate: from vector B copy all 'E'ven 'B'yte elements: 550// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 551def: Pat<(v4i8 (trunc V4I16:$Rs)), 552 (S2_vtrunehb V4I16:$Rs)>; 553 554// Truncate: from vector B copy all 'O'dd 'B'yte elements: 555// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 556// S2_vtrunohb 557 558// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 559// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 560// S2_vtruneh 561 562def: Pat<(v2i16 (trunc V2I32:$Rs)), 563 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 564 565// Truncate to vNi1 566def: Pat<(v2i1 (trunc V2I32:$Rs)), 567 (A4_vcmpweqi (A2_andp V2I32:$Rs, (A2_combineii (i32 1), (i32 1))), 568 (i32 1))>; 569def: Pat<(v4i1 (trunc V4I16:$Rs)), 570 (A4_vcmpheqi (Combinew (A2_andir (HiReg $Rs), (i32 0x00010001)), 571 (A2_andir (LoReg $Rs), (i32 0x00010001))), 572 (i32 1))>; 573def: Pat<(v8i1 (trunc V8I8:$Rs)), 574 (A4_vcmpbeqi (Combinew (A2_andir (HiReg $Rs), (i32 0x01010101)), 575 (A2_andir (LoReg $Rs), (i32 0x01010101))), 576 (i32 1))>; 577 578 579// Saturation: 580// Note: saturation assumes the same signed-ness for the input and the 581// output. 582def: Pat<(i32 (ssat I32:$Rs, i8)), (A2_satb I32:$Rs)>; 583def: Pat<(i32 (ssat I32:$Rs, i16)), (A2_sath I32:$Rs)>; 584def: Pat<(i32 (ssat I64:$Rs, i32)), (A2_sat I64:$Rs)>; 585def: Pat<(i32 (usat I32:$Rs, i8)), (A2_satub I32:$Rs)>; 586def: Pat<(i32 (usat I32:$Rs, i16)), (A2_satuh I32:$Rs)>; 587def: Pat<(i32 (usat I64:$Rs, i32)), 588 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>; 589 590def: Pat<(v4i8 (ssat V4I16:$Rs, v4i8)), (S2_vsathb V4I16:$Rs)>; 591def: Pat<(v2i16 (ssat V2I32:$Rs, v2i16)), (S2_vsatwh V2I32:$Rs)>; 592def: Pat<(v4i8 (usat V4I16:$Rs, v4i8)), (S2_vsathub V4I16:$Rs)>; 593def: Pat<(v2i16 (usat V2I32:$Rs, v2i16)), (S2_vsatwuh V2I32:$Rs)>; 594 595 596// --(4) Logical --------------------------------------------------------- 597// 598 599def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 600def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>; 601def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>; 602def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>; 603def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 604 605def: OpR_RR_pat<C2_and, And, i1, I1>; 606def: OpR_RR_pat<C2_or, Or, i1, I1>; 607def: OpR_RR_pat<C2_xor, Xor, i1, I1>; 608def: OpR_RR_pat<C2_andn, Not2<And>, i1, I1>; 609def: OpR_RR_pat<C2_orn, Not2<Or>, i1, I1>; 610 611def: AccRRR_pat<C4_and_and, And, Su<And>, I1, I1, I1>; 612def: AccRRR_pat<C4_and_or, And, Su< Or>, I1, I1, I1>; 613def: AccRRR_pat<C4_or_and, Or, Su<And>, I1, I1, I1>; 614def: AccRRR_pat<C4_or_or, Or, Su< Or>, I1, I1, I1>; 615def: AccRRR_pat<C4_and_andn, And, Su<Not2<And>>, I1, I1, I1>; 616def: AccRRR_pat<C4_and_orn, And, Su<Not2< Or>>, I1, I1, I1>; 617def: AccRRR_pat<C4_or_andn, Or, Su<Not2<And>>, I1, I1, I1>; 618def: AccRRR_pat<C4_or_orn, Or, Su<Not2< Or>>, I1, I1, I1>; 619 620multiclass BoolvOpR_RR_pat<InstHexagon MI, PatFrag VOp> { 621 def: OpR_RR_pat<MI, VOp, v2i1, V2I1>; 622 def: OpR_RR_pat<MI, VOp, v4i1, V4I1>; 623 def: OpR_RR_pat<MI, VOp, v8i1, V8I1>; 624} 625 626multiclass BoolvAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag VOp> { 627 def: AccRRR_pat<MI, AccOp, VOp, V2I1, V2I1, V2I1>; 628 def: AccRRR_pat<MI, AccOp, VOp, V4I1, V4I1, V4I1>; 629 def: AccRRR_pat<MI, AccOp, VOp, V8I1, V8I1, V8I1>; 630} 631 632defm: BoolvOpR_RR_pat<C2_and, And>; 633defm: BoolvOpR_RR_pat<C2_or, Or>; 634defm: BoolvOpR_RR_pat<C2_xor, Xor>; 635defm: BoolvOpR_RR_pat<C2_andn, VNot2<And, pnot>>; 636defm: BoolvOpR_RR_pat<C2_orn, VNot2< Or, pnot>>; 637 638// op(Ps, op(Pt, Pu)) 639defm: BoolvAccRRR_pat<C4_and_and, And, Su<And>>; 640defm: BoolvAccRRR_pat<C4_and_or, And, Su<Or>>; 641defm: BoolvAccRRR_pat<C4_or_and, Or, Su<And>>; 642defm: BoolvAccRRR_pat<C4_or_or, Or, Su<Or>>; 643 644// op(Ps, op(Pt, !Pu)) 645defm: BoolvAccRRR_pat<C4_and_andn, And, Su<VNot2<And, pnot>>>; 646defm: BoolvAccRRR_pat<C4_and_orn, And, Su<VNot2< Or, pnot>>>; 647defm: BoolvAccRRR_pat<C4_or_andn, Or, Su<VNot2<And, pnot>>>; 648defm: BoolvAccRRR_pat<C4_or_orn, Or, Su<VNot2< Or, pnot>>>; 649 650 651// --(5) Compare --------------------------------------------------------- 652// 653 654// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 655// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 656 657def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 658def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 659def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 660 661def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 662 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 663def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 664 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 665 666def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 667 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 668def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 669 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 670 671// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 672// that reverse the order of the operands. 673class RevCmp<PatFrag F> 674 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 675 F.OperandTransform>; 676 677def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 678def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 679def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 680def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 681def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 682def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 683def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 684def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 685def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 686def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 687def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 688def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 689def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 690def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 691def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 692def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 693def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 694def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 695def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 696def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 697def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 698def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 699def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 700def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 701def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 702def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 703def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 704def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 705def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 706def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 707def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 708def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 709def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 710def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 711def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 712def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 713def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 714def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 715def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 716def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 717 718def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 719def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 720def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 721def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 722def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 723def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 724def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 725def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 726def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 727def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 728def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 729 730def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 731def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 732def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 733def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 734def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 735def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 736def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 737def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 738def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 739def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 740def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 741 742// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 743 744def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 745 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 746def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 747 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 748def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 749 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 750 751class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 752 PatFrag RsPred, PatFrag RtPred = RsPred> 753 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 754 (Output RsPred:$Rs, RtPred:$Rt)>; 755 756class Outn<InstHexagon MI> 757 : OutPatFrag<(ops node:$Rs, node:$Rt), 758 (C2_not (MI $Rs, $Rt))>; 759 760def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 761def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 762def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 763def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 764def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 765def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 766def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 767def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 768def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 769def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 770def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 771def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 772def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 773def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 774def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 775def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 776def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 777def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 778def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 779def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 780def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 781def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 782def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 783def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 784def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 785 786let AddedComplexity = 100 in { 787 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 788 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 789 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 790 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 791 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 792 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 793 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 794 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 795} 796 797// PatFrag for AsserZext which takes the original type as a parameter. 798def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 799def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 800class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 801 802multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 803 PatLeaf ImmPred, int Mask> { 804 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 805 (MI I32:$Rs, imm:$I)>; 806 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 807 (MI I32:$Rs, imm:$I)>; 808} 809 810multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 811 PatLeaf ImmPred, int Mask> { 812 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 813 (C2_not (MI I32:$Rs, imm:$I))>; 814 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 815 (C2_not (MI I32:$Rs, imm:$I))>; 816} 817 818multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 819 PatLeaf ImmPred, int Mask> { 820 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 821 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 822 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 823 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 824} 825 826let AddedComplexity = 200 in { 827 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 828 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 829 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 830 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 831 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 832 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 833 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 834 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 835} 836 837def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 838 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 839def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 840 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 841def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 842 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 843def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 844 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 845 846def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 847def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 848def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_not (C2_xor I1:$Ps, I1:$Pt))>; 849def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 850 851multiclass BoolE_pat<PatFrag OpPred, ValueType ResTy> { 852 def: Pat<(ResTy (seteq OpPred:$Ps, OpPred:$Pt)), (C2_not (C2_xor $Ps, $Pt))>; 853 def: Pat<(ResTy (setne OpPred:$Ps, OpPred:$Pt)), (C2_xor $Ps, $Pt)>; 854} 855 856defm: BoolE_pat<I1, i1>; 857defm: BoolE_pat<V2I1, v2i1>; 858defm: BoolE_pat<V4I1, v4i1>; 859defm: BoolE_pat<V8I1, v8i1>; 860 861multiclass BoolL_pat<PatFrag OpPred, ValueType ResTy> { 862 // Signed "true" == -1 863 def: Pat<(ResTy (setlt OpPred:$Ps, OpPred:$Pt)), (C2_andn $Ps, $Pt)>; 864 def: Pat<(ResTy (setle OpPred:$Ps, OpPred:$Pt)), (C2_orn $Ps, $Pt)>; 865 def: Pat<(ResTy (setult OpPred:$Ps, OpPred:$Pt)), (C2_andn $Pt, $Ps)>; 866 def: Pat<(ResTy (setule OpPred:$Ps, OpPred:$Pt)), (C2_orn $Pt, $Ps)>; 867} 868 869defm: BoolL_pat<I1, i1>; 870defm: BoolL_pat<V2I1, v2i1>; 871defm: BoolL_pat<V4I1, v4i1>; 872defm: BoolL_pat<V8I1, v8i1>; 873 874// Floating-point comparisons with checks for ordered/unordered status. 875 876class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 877 : OutPatFrag<(ops node:$Rs, node:$Rt), 878 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 879 880class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 881class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 882 883class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 884class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 885 886def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 887def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 888def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 889def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 890def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 891def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 892 893def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 894def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 895def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 896def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 897def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 898def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 899 900def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 901def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 902 903def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 904def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 905 906def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 907def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 908 909 910// --(6) Select ---------------------------------------------------------- 911// 912 913def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 914 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 915def: Pat<(select I1:$Pu, v4i8:$Rs, v4i8:$Rt), 916 (C2_mux I1:$Pu, v4i8:$Rs, v4i8:$Rt)>; 917def: Pat<(select I1:$Pu, v2i16:$Rs, v2i16:$Rt), 918 (C2_mux I1:$Pu, v2i16:$Rs, v2i16:$Rt)>; 919def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 920 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 921def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 922 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 923def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 924 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 925 926def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 927 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 928def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 929 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 930def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 931 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 932def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 933 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 934 935// Map from a 64-bit select to an emulated 64-bit mux. 936// Hexagon does not support 64-bit MUXes; so emulate with combines. 937def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 938 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 939 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 940 941def: Pat<(select I1:$Pu, v2i32:$Rs, v2i32:$Rt), 942 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 943 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 944 945def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 946 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 947def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 948 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 949def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 950 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 951def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 952 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 953 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 954 955def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 956 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 957def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 958 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 959 960def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 961 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 962def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 963 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 964 965def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 966 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 967def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 968 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 969def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 970 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 971 972def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt), 973 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>; 974def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt), 975 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>; 976def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt), 977 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>; 978 979 980// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 981def: Pat<(select I1:$Pu, I1:$Ps, I1:$Pt), 982 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 983 984def: Pat<(vselect V2I1:$Pu, V2I1:$Ps, V2I1:$Pt), 985 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 986def: Pat<(vselect V4I1:$Pu, V4I1:$Ps, V4I1:$Pt), 987 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 988def: Pat<(vselect V8I1:$Pu, V8I1:$Ps, V8I1:$Pt), 989 (C4_or_andn (C2_and $Ps, $Pu), $Pt, $Pu)>; 990 991def: Pat<(select I1:$Pu, V2I1:$Ps, V2I1:$Pt), 992 (C2_tfrrp (C2_mux $Pu, (C2_tfrpr $Ps), (C2_tfrpr $Pt)))>; 993def: Pat<(select I1:$Pu, V4I1:$Ps, V4I1:$Pt), 994 (C2_tfrrp (C2_mux $Pu, (C2_tfrpr $Ps), (C2_tfrpr $Pt)))>; 995def: Pat<(select I1:$Pu, V8I1:$Ps, V8I1:$Pt), 996 (C2_tfrrp (C2_mux $Pu, (C2_tfrpr $Ps), (C2_tfrpr $Pt)))>; 997 998def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 999 return isPositiveHalfWord(N); 1000}]>; 1001 1002multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 1003 InstHexagon InstB> { 1004 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 1005 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 1006 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 1007 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 1008 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 1009 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 1010} 1011 1012let AddedComplexity = 200 in { 1013 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 1014 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 1015 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 1016 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 1017 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 1018 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 1019 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 1020 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 1021} 1022 1023def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>; 1024def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>; 1025def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>; 1026def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>; 1027def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>; 1028def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>; 1029def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>; 1030def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>; 1031 1032let AddedComplexity = 100 in { 1033 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>; 1034 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>; 1035 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>; 1036 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; 1037} 1038 1039let AddedComplexity = 100, Predicates = [HasV67] in { 1040 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; 1041 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; 1042 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; 1043 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; 1044} 1045 1046def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>; 1047def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>; 1048def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>; 1049def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>; 1050 1051def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>; 1052def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>; 1053def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>; 1054def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>; 1055 1056def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>; 1057def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>; 1058def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>; 1059def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>; 1060 1061// --(7) Insert/extract -------------------------------------------------- 1062// 1063 1064def SDTHexagonINSERT: 1065 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 1066 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 1067def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 1068 1069let AddedComplexity = 10 in { 1070 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 1071 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 1072 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 1073 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 1074} 1075def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 1076 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 1077def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 1078 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 1079 1080def SDTHexagonEXTRACTU 1081 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 1082 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 1083def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 1084 1085let AddedComplexity = 10 in { 1086 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 1087 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 1088 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 1089 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 1090} 1091def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 1092 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 1093def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 1094 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 1095 1096def: Pat<(v4i8 (splat_vector anyint:$V)), (ToI32 (SplatB $V))>; 1097def: Pat<(v2i16 (splat_vector anyint:$V)), (ToI32 (SplatH $V))>; 1098def: Pat<(v8i8 (splat_vector anyint:$V)), 1099 (Combinew (ToI32 (SplatB $V)), (ToI32 (SplatB $V)))>; 1100def: Pat<(v4i16 (splat_vector anyint:$V)), 1101 (Combinew (ToI32 (SplatH $V)), (ToI32 (SplatH $V)))>; 1102let AddedComplexity = 10 in 1103def: Pat<(v2i32 (splat_vector s8_0ImmPred:$s8)), 1104 (A2_combineii imm:$s8, imm:$s8)>; 1105def: Pat<(v2i32 (splat_vector anyimm:$V)), (Combinew (ToI32 $V), (ToI32 $V))>; 1106 1107def: Pat<(v4i8 (splat_vector I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 1108def: Pat<(v2i16 (splat_vector I32:$Rs)), (LoReg (S2_vsplatrh I32:$Rs))>; 1109def: Pat<(v4i16 (splat_vector I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 1110def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 1111 1112let AddedComplexity = 10 in 1113def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 1114 Requires<[HasV62]>; 1115def: Pat<(v8i8 (splat_vector I32:$Rs)), 1116 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 1117 1118let AddedComplexity = 10 in { 1119 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, u5_0ImmPred:$U5), i8), 1120 (S4_extract I32:$Rs, 8, imm:$U5)>; 1121 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, u5_0ImmPred:$U5), i16), 1122 (S4_extract I32:$Rs, 16, imm:$U5)>; 1123 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, u6_0ImmPred:$U6), i8), 1124 (S4_extractp I64:$Rs, 8, imm:$U6)>; 1125 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, u6_0ImmPred:$U6), i16), 1126 (S4_extractp I64:$Rs, 16, imm:$U6)>; 1127 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, u6_0ImmPred:$U6), i32), 1128 (S4_extractp I64:$Rs, 32, imm:$U6)>; 1129} 1130 1131def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, I32:$Off), i8), 1132 (S4_extract_rp I32:$Rs, (Combinew (ToI32 8), I32:$Off))>; 1133def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, I32:$Off), i16), 1134 (S4_extract_rp I32:$Rs, (Combinew (ToI32 16), I32:$Off))>; 1135def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, I32:$Off), i8), 1136 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 8), I32:$Off))>; 1137def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, I32:$Off), i16), 1138 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 16), I32:$Off))>; 1139def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, I32:$Off), i32), 1140 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 32), I32:$Off))>; 1141 1142 1143// --(8) Shift/permute --------------------------------------------------- 1144// 1145 1146def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 1147 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 1148 1149def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 1150 1151def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 1152 1153// The complexity of the combines involving immediates should be greater 1154// than the complexity of the combine with two registers. 1155let AddedComplexity = 50 in { 1156 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 1157 (A4_combineri IntRegs:$Rs, imm:$s8)>; 1158 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 1159 (A4_combineir imm:$s8, IntRegs:$Rs)>; 1160} 1161 1162// The complexity of the combine with two immediates should be greater than 1163// the complexity of a combine involving a register. 1164let AddedComplexity = 75 in { 1165 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 1166 (A4_combineii imm:$s8, imm:$u6)>; 1167 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 1168 (A2_combineii imm:$s8, imm:$S8)>; 1169} 1170 1171def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 1172def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 1173 (A2_swiz (HiReg $Rss)))>; 1174 1175def: Pat<(bswap V2I16:$Rs), (A2_combine_lh (A2_swiz $Rs), (A2_swiz $Rs))>; 1176def: Pat<(bswap V2I32:$Rs), (Combinew (A2_swiz (HiReg $Rs)), 1177 (A2_swiz (LoReg $Rs)))>; 1178def: Pat<(bswap V4I16:$Rs), (A2_orp (S2_lsr_i_vh $Rs, 8), 1179 (S2_asl_i_vh $Rs, 8))>; 1180 1181def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 1182def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 1183def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1184 1185def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 1186def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1187def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 1188def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 1189def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1190def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 1191def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 1192def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1193def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 1194def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 1195def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1196def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 1197 1198def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 1199def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1200def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 1201def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 1202def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1203def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1204 1205// Funnel shifts. 1206def IsMul8_U3: PatLeaf<(i32 imm), [{ 1207 uint64_t V = N->getZExtValue(); 1208 return V % 8 == 0 && isUInt<3>(V / 8); 1209}]>; 1210 1211def Divu8: SDNodeXForm<imm, [{ 1212 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1213}]>; 1214 1215// Funnel shift-left. 1216def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1217 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1218def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1219 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1220 1221def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1222 (S2_lsr_i_p_or (S2_asl_i_p $Rs, $S), $Rt, (Subi<64> $S))>; 1223def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1224 (S2_lsr_r_p_or (S2_asl_r_p $Rs, $Ru), $Rt, (A2_subri 64, $Ru))>; 1225 1226// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1227def Divu64_8: SDNodeXForm<imm, [{ 1228 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1229 SDLoc(N), MVT::i32); 1230}]>; 1231 1232// Special cases: 1233let AddedComplexity = 100 in { 1234 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1235 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1236 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1237 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1238} 1239 1240let Predicates = [HasV60], AddedComplexity = 50 in { 1241 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1242 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1243} 1244let AddedComplexity = 30 in { 1245 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1246 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1247 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1248 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1249} 1250def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1251def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1252def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1253def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1254 1255// Funnel shift-right. 1256def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1257 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1258def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1259 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1260 1261def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1262 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1263def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1264 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1265 1266// Special cases: 1267let AddedComplexity = 100 in { 1268 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1269 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1270 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1271 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1272} 1273 1274let Predicates = [HasV60], AddedComplexity = 50 in { 1275 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1276 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1277} 1278let AddedComplexity = 30 in { 1279 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1280 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1281 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1282 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1283} 1284def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1285def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1286def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1287def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1288 1289 1290def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1291 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1292def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1293 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1294 1295// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1296let AddedComplexity = 120 in 1297def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1298 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1299 1300let AddedComplexity = 100 in { 1301 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1302 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1303 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1304 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1305 1306 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1307 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1308 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1309 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1310 1311 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1312 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1313 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1314 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1315 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1316 1317 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1318 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1319 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1320 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1321 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1322 1323 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1324 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1325 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1326 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1327 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1328 1329 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1330 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1331 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1332 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1333 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1334 1335 let Predicates = [HasV60] in { 1336 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1337 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1338 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1339 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1340 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1341 1342 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1343 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1344 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1345 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1346 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1347 } 1348} 1349 1350let AddedComplexity = 100 in { 1351 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1352 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1353 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1354 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1355 1356 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1357 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1358 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1359 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1360 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1361 1362 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1363 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1364 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1365 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1366 1367 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1368 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1369 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1370 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1371 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1372 1373 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1374 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1375 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1376 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1377 1378 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1379 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1380 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1381 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1382 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1383} 1384 1385 1386class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1387 PatFrag RegPred, PatFrag ImmPred> 1388 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1389 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1390 1391let AddedComplexity = 200, Predicates = [UseCompound] in { 1392 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1393 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1394 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1395 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1396 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1397 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1398 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1399 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1400} 1401 1402// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1403// two 32-bit words into a 64-bit word. 1404let AddedComplexity = 200 in 1405def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1406 (Combinew I32:$a, I32:$b)>; 1407 1408def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1409 (Zext64 (and I32:$a, (i32 65535)))), 1410 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1411 (shl (Aext64 I32:$d), (i32 48))), 1412 (Combinew (A2_combine_ll I32:$d, I32:$c), 1413 (A2_combine_ll I32:$b, I32:$a))>; 1414 1415let AddedComplexity = 200 in { 1416 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1417 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1418 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1419 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1420 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1421 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1422 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1423 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1424} 1425 1426def SDTHexagonVShift 1427 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1428 1429def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1430def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1431def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1432 1433// Funnel shifts with the shift amount module element bit width. 1434def HexagonMFSHL: SDNode<"HexagonISD::MFSHL", SDTIntShiftDOp>; 1435def HexagonMFSHR: SDNode<"HexagonISD::MFSHR", SDTIntShiftDOp>; 1436 1437def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1438def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1439def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1440def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1441def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1442def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1443 1444def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1445def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1446def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1447def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1448def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1449def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1450 1451def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1452 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1453def: Pat<(srl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1454 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1455def: Pat<(shl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1456 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1457def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1458 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1459def: Pat<(srl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1460 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1461def: Pat<(shl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1462 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1463 1464def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1465 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1466def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1467 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1468def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1469 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1470def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1471 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1472def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1473 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1474def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1475 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1476 1477 1478// --(9) Arithmetic/bitwise ---------------------------------------------- 1479// 1480 1481def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1482def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1483def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1484def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1485def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1486 1487def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1488def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1489 1490def: Pat<(fabs F64:$Rs), 1491 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1492 (i32 (LoReg $Rs)))>; 1493def: Pat<(fneg F64:$Rs), 1494 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1495 (i32 (LoReg $Rs)))>; 1496 1497def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1498def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1499def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1500def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1501 1502def: OpR_RR_pat<A2_add, Add, i32, I32>; 1503def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1504def: OpR_RR_pat<A2_and, And, i32, I32>; 1505def: OpR_RR_pat<A2_or, Or, i32, I32>; 1506def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1507def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1508def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1509def: OpR_RR_pat<A2_andp, And, i64, I64>; 1510def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1511def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1512def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1513def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1514 1515def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1516def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1517 1518def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1519def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1520def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1521def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1522def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1523def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1524 1525def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1526def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1527def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1528def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1529def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1530def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1531def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1532def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1533def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1534def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1535def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1536def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1537def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1538def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1539def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1540 1541def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1542def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1543def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1544def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1545def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1546 1547// Arithmetic on predicates. 1548def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1549def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1550def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1551def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1552def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1553def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1554def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1555def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1556def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1557def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1558def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1559def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1560 1561def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1562def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1563def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1564def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1565def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1566 1567let Predicates = [HasV66] in { 1568 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1569 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1570} 1571 1572def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), 1573 (F2_dfmpyhh 1574 (F2_dfmpylh 1575 (F2_dfmpylh 1576 (F2_dfmpyll $Rs, $Rt), 1577 $Rs, $Rt), 1578 $Rt, $Rs), 1579 $Rs, $Rt)>; 1580 1581let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { 1582 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; 1583} 1584let Predicates = [HasV67] in { 1585 def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; 1586 def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; 1587 1588 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), 1589 (F2_dfmpyfix $Rt, $Rs))>; 1590} 1591 1592// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1593// over add-add with individual multiplies as inputs. 1594let AddedComplexity = 10 in { 1595 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1596 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1597 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1598 let Predicates = [HasV66] in 1599 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1600} 1601 1602def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1603def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1604def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1605 1606// Mulh for vectors 1607// 1608def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1609 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1610 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1611 1612def: Pat<(v2i32 (mulhs V2I32:$Rss, V2I32:$Rtt)), 1613 (Combinew (M2_mpy_up (HiReg $Rss), (HiReg $Rtt)), 1614 (M2_mpy_up (LoReg $Rss), (LoReg $Rtt)))>; 1615 1616def Mulhub4: 1617 OutPatFrag<(ops node:$Rs, node:$Rt), (S2_vtrunohb (M5_vmpybuu $Rs, $Rt))>; 1618def Mulhub8: 1619 OutPatFrag<(ops node:$Rss, node:$Rtt), 1620 (Combinew (Mulhub4 (HiReg $Rss), (HiReg $Rtt)), 1621 (Mulhub4 (LoReg $Rss), (LoReg $Rtt)))>; 1622 1623// (mux (x >= 0), 0, y) 1624def Negbytes8: 1625 OutPatFrag<(ops node:$Rss, node:$Rtt), 1626 (C2_vmux (A4_vcmpbgti $Rss, -1), (A2_tfrpi 0), $Rtt)>; 1627 1628def: Pat<(v4i8 (mulhu V4I8:$Rs, V4I8:$Rt)), (Mulhub4 $Rs, $Rt)>; 1629def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), (Mulhub8 $Rss, $Rtt)>; 1630 1631// (Mulhs x, y) = (Mulhu x, y) - (x < 0 ? y : 0) - (y < 0 ? x : 0) 1632def Mulhsb8: 1633 OutPatFrag<(ops node:$Rss, node:$Rtt), 1634 (A2_vsubub (Mulhub8 $Rss, $Rtt), 1635 (A2_vaddub (Negbytes8 $Rss, $Rtt), 1636 (Negbytes8 $Rtt, $Rss)))>; 1637 1638def: Pat<(v4i8 (mulhs V4I8:$Rs, V4I8:$Rt)), 1639 (LoReg (Mulhsb8 (v8i8 (ToAext64 $Rs)), (v8i8 (ToAext64 $Rt))))>; 1640def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), (Mulhsb8 $Rss, $Rtt)>; 1641 1642// v2i16 *s v2i16 -> v2i32 1643def Muli16: 1644 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1645 1646def Mulhsh2: 1647 OutPatFrag<(ops node:$Rs, node:$Rt), 1648 (A2_combine_hh (HiReg (Muli16 $Rs, $Rt)), 1649 (LoReg (Muli16 $Rs, $Rt)))>; 1650def Mulhsh4: 1651 OutPatFrag<(ops node:$Rss, node:$Rtt), 1652 (Combinew (Mulhsh2 (HiReg $Rss), (HiReg $Rtt)), 1653 (Mulhsh2 (LoReg $Rss), (LoReg $Rtt)))>; 1654 1655def: Pat<(v2i16 (mulhs V2I16:$Rs, V2I16:$Rt)), (Mulhsh2 $Rs, $Rt)>; 1656def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh4 $Rss, $Rtt)>; 1657 1658def: Pat<(v2i16 (mulhu V2I16:$Rs, V2I16:$Rt)), 1659 (A2_svaddh 1660 (Mulhsh2 $Rs, $Rt), 1661 (A2_svaddh (LoReg (A2_andp (Combinew $Rt, $Rs), 1662 (S2_asr_i_vh (Combinew $Rs, $Rt), 15))), 1663 (HiReg (A2_andp (Combinew $Rt, $Rs), 1664 (S2_asr_i_vh (Combinew $Rs, $Rt), 15)))))>; 1665 1666def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1667 (A2_vaddh 1668 (Mulhsh4 $Rss, $Rtt), 1669 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1670 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1671 1672 1673def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1674 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1675 1676def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1677 int64_t V = N->getSExtValue(); 1678 return -255 <= V && V <= 0; 1679}]>; 1680 1681// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1682def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1683 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1684 1685def: Pat<(add Sext64:$Rs, I64:$Rt), 1686 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1687 1688def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1689def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1690def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1691def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1692def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1693def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1694def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1695def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1696def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1697def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1698 1699// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1700// one argument matches the patterns below, and with the other argument 1701// matches S2_asl_r_r_or, etc, prefer the patterns below. 1702let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1703 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1704 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1705 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1706} 1707 1708// S4_addaddi and S4_subaddi don't have tied operands, so give them 1709// a bit of preference. 1710let AddedComplexity = 30, Predicates = [UseCompound] in { 1711 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1712 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1713 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1714 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1715 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1716 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1717 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1718 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1719 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1720 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1721} 1722 1723let Predicates = [UseCompound] in 1724def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1725 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1726 1727def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1728 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1729def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1730 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1731 1732 1733def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1734 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1735def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1736 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1737 1738def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1739 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1740def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1741 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1742def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1743 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1744 1745def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1746 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1747def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1748 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1749def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1750 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1751def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1752 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1753def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1754 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1755def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1756 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1757 1758// Add halfword. 1759def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1760 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1761def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1762 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1763def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1764 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1765 1766// Subtract halfword. 1767def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1768 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1769def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1770 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1771def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1772 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1773 1774def: Pat<(mul I64:$Rss, I64:$Rtt), 1775 (Combinew 1776 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1777 (LoReg $Rss), 1778 (HiReg $Rtt)), 1779 (LoReg $Rtt), 1780 (HiReg $Rss)), 1781 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1782 1783def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1784 (A2_addp 1785 (M2_dpmpyuu_acc_s0 1786 (S2_lsr_i_p 1787 (A2_addp 1788 (M2_dpmpyuu_acc_s0 1789 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1790 (HiReg $Rss), 1791 (LoReg $Rtt)), 1792 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1793 32), 1794 (HiReg $Rss), 1795 (HiReg $Rtt)), 1796 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1797 1798// Multiply 64-bit unsigned and use upper result. 1799def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1800 1801// Multiply 64-bit signed and use upper result. 1802// 1803// For two signed 64-bit integers A and B, let A' and B' denote A and B 1804// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1805// sign bit of A (and identically for B). With this notation, the signed 1806// product A*B can be written as: 1807// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1808// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1809// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1810// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1811 1812// Clear the sign bit in a 64-bit register. 1813def ClearSign : OutPatFrag<(ops node:$Rss), 1814 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1815 1816def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1817 (A2_subp 1818 (MulHU $Rss, $Rtt), 1819 (A2_addp 1820 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1821 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1822 1823// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1824// will put the immediate addend into a register, while these instructions will 1825// use it directly. Such a construct does not appear in the middle of a gep, 1826// where M2_macsip would be preferable. 1827let AddedComplexity = 20, Predicates = [UseCompound] in { 1828 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1829 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1830 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1831 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1832} 1833 1834// Keep these instructions less preferable to M2_macsip/M2_macsin. 1835let Predicates = [UseCompound] in { 1836 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1837 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1838 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1839 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1840 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1841 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1842} 1843 1844def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1845 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1846def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1847 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1848 1849def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1850 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1851def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1852 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1853 1854// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1855// we use the double add v8i8, and use only the low part of the result. 1856def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1857 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1858def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1859 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1860 1861// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1862// half-words, and saturates the result to a 32-bit value, except the 1863// saturation never happens (it can only occur with scaling). 1864def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1865 (LoReg (S2_vtrunewh (IMPLICIT_DEF), 1866 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1867def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1868 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1869 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1870 1871// Multiplies two v4i8 vectors. 1872def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1873 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1874 1875// Multiplies two v8i8 vectors. 1876def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1877 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1878 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1879 1880 1881// --(10) Bit ------------------------------------------------------------ 1882// 1883 1884// Count leading zeros. 1885def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 1886def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1887 1888// Count trailing zeros. 1889def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 1890def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1891 1892// Count leading ones. 1893def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 1894def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1895 1896// Count trailing ones. 1897def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 1898def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1899 1900// Define leading/trailing patterns that require zero-extensions to 64 bits. 1901def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1902def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1903def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1904def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1905 1906def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1907def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1908 1909def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1910def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1911 1912def: Pat<(bitreverse V4I8:$Rs), (A2_swiz (S2_brev $Rs))>; 1913def: Pat<(bitreverse V8I8:$Rs), (Combinew (A2_swiz (LoReg (S2_brevp $Rs))), 1914 (A2_swiz (HiReg (S2_brevp $Rs))))>; 1915def: Pat<(bitreverse V2I16:$Rs), (A2_combine_lh (S2_brev $Rs), 1916 (S2_brev $Rs))>; 1917def: Pat<(bitreverse V4I16:$Rs), 1918 (Combinew (A2_combine_lh (LoReg (S2_brevp $Rs)), 1919 (LoReg (S2_brevp $Rs))), 1920 (A2_combine_lh (HiReg (S2_brevp $Rs)), 1921 (HiReg (S2_brevp $Rs))))>; 1922def: Pat<(bitreverse V2I32:$Rs), 1923 (Combinew (i32 (LoReg (S2_brevp $Rs))), 1924 (i32 (HiReg (S2_brevp $Rs))))>; 1925 1926let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1927 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1928 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1929 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1930 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1931 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1932 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1933 1934 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1935 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1936 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1937 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1938 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1939 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1940} 1941 1942// Clr/set/toggle bit for 64-bit values with immediate bit index. 1943let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1944 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1945 (Combinew (i32 (HiReg $Rss)), 1946 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1947 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1948 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1949 (i32 (LoReg $Rss)))>; 1950 1951 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1952 (Combinew (i32 (HiReg $Rss)), 1953 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1954 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1955 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1956 (i32 (LoReg $Rss)))>; 1957 1958 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1959 (Combinew (i32 (HiReg $Rss)), 1960 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1961 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1962 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1963 (i32 (LoReg $Rss)))>; 1964} 1965 1966 1967let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1968 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1969 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1970 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1971 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1972 def: Pat<(i1 (trunc I32:$Rs)), 1973 (S2_tstbit_i IntRegs:$Rs, 0)>; 1974 def: Pat<(i1 (trunc I64:$Rs)), 1975 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1976} 1977 1978def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1), 1979 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>; 1980def: Pat<(and (srl I64:$Rss, IsULE<32,31>:$u6), 1), 1981 (ToZext64 (I1toI32 (S2_tstbit_i (LoReg $Rss), imm:$u6)))>; 1982def: Pat<(and (srl I64:$Rss, IsUGT<32,31>:$u6), 1), 1983 (ToZext64 (I1toI32 (S2_tstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1984 1985def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1), 1986 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>; 1987def: Pat<(and (not (srl I64:$Rss, IsULE<32,31>:$u6)), 1), 1988 (ToZext64 (I1toI32 (S4_ntstbit_i (LoReg $Rss), imm:$u6)))>; 1989def: Pat<(and (not (srl I64:$Rss, IsUGT<32,31>:$u6)), 1), 1990 (ToZext64 (I1toI32 (S4_ntstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1991 1992let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1993 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1994 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1995 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1996 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 1997} 1998 1999let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 2000def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 2001 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 2002 2003def SDTTestBit: 2004 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 2005def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 2006 2007def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 2008 (S2_tstbit_i I32:$Rs, imm:$u5)>; 2009def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 2010 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 2011 2012// Add extra complexity to prefer these instructions over bitsset/bitsclr. 2013// The reason is that tstbit/ntstbit can be folded into a compound instruction: 2014// if ([!]tstbit(...)) jump ... 2015let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 2016 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)), 2017 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 2018 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)), 2019 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 2020 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 2021 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 2022 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 2023 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 2024} 2025 2026def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)), 2027 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>; 2028def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)), 2029 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>; 2030def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)), 2031 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>; 2032def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)), 2033 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>; 2034 2035// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 2036// represented as a compare against "value & 0xFF", which is an exact match 2037// for cmpb (same for cmph). The patterns below do not contain any additional 2038// complexity that would make them preferable, and if they were actually used 2039// instead of cmpb/cmph, they would result in a compare against register that 2040// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 2041def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 2042 (C4_nbitsclri I32:$Rs, imm:$u6)>; 2043def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 2044 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 2045def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 2046 (C4_nbitsset I32:$Rs, I32:$Rt)>; 2047 2048// Special patterns to address certain cases where the "top-down" matching 2049// algorithm would cause suboptimal selection. 2050 2051let AddedComplexity = 100 in { 2052 // Avoid A4_rcmp[n]eqi in these cases: 2053 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2054 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 2055 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2056 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 2057 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))), 2058 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 2059 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))), 2060 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 2061 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2062 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>; 2063 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2064 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>; 2065} 2066 2067// --(11) PIC ------------------------------------------------------------ 2068// 2069 2070def SDT_HexagonAtGot 2071 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 2072def SDT_HexagonAtPcrel 2073 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2074 2075// AT_GOT address-of-GOT, address-of-global, offset-in-global 2076def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 2077// AT_PCREL address-of-global 2078def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 2079 2080def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 2081 (L2_loadri_io I32:$got, imm:$addr)>; 2082def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 2083 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 2084def: Pat<(HexagonAtPcrel I32:$addr), 2085 (C4_addipc imm:$addr)>; 2086 2087// The HVX load patterns also match AT_PCREL directly. Make sure that 2088// if the selection of this opcode changes, it's updated in all places. 2089 2090 2091// --(12) Load ----------------------------------------------------------- 2092// 2093 2094def L1toI32: OutPatFrag<(ops node:$Rs), (A2_subri 0, (i32 $Rs))>; 2095def L1toI64: OutPatFrag<(ops node:$Rs), (ToSext64 (L1toI32 $Rs))>; 2096 2097def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 2098 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2099}]>; 2100def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 2101 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2102}]>; 2103 2104def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 2105 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2106}]>; 2107def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 2108 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2109}]>; 2110 2111def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 2112 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2113}]>; 2114def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 2115 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2116}]>; 2117 2118// Patterns to select load-indexed: Rs + Off. 2119// - frameindex [+ imm], 2120multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2121 InstHexagon MI> { 2122 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2123 (VT (MI AddrFI:$fi, imm:$Off))>; 2124 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2125 (VT (MI AddrFI:$fi, imm:$Off))>; 2126 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 2127} 2128 2129// Patterns to select load-indexed: Rs + Off. 2130// - base reg [+ imm] 2131multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2132 InstHexagon MI> { 2133 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2134 (VT (MI IntRegs:$Rs, imm:$Off))>; 2135 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2136 (VT (MI IntRegs:$Rs, imm:$Off))>; 2137 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 2138} 2139 2140// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 2141multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2142 InstHexagon MI> { 2143 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 2144 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 2145} 2146 2147// Patterns to select load reg indexed: Rs + Off with a value modifier. 2148// - frameindex [+ imm] 2149multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2150 PatLeaf ImmPred, InstHexagon MI> { 2151 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2152 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2153 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2154 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2155 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 2156} 2157 2158// Patterns to select load reg indexed: Rs + Off with a value modifier. 2159// - base reg [+ imm] 2160multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2161 PatLeaf ImmPred, InstHexagon MI> { 2162 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2163 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2164 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2165 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2166 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 2167} 2168 2169// Patterns to select load reg indexed: Rs + Off with a value modifier. 2170// Combines Loadxfim + Loadxgim. 2171multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2172 PatLeaf ImmPred, InstHexagon MI> { 2173 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 2174 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 2175} 2176 2177// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 2178class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2179 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2180 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 2181 2182// Pattern to select load reg reg-indexed: Rs + Rt<<0. 2183class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2184 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2185 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 2186 2187// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 2188class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2189 InstHexagon MI> 2190 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2191 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 2192 2193// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 2194class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2195 InstHexagon MI> 2196 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2197 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 2198 2199// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 2200// Don't match for u2==0, instead use reg+imm for those cases. 2201class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 2202 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2203 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 2204 2205class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 2206 InstHexagon MI> 2207 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2208 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 2209 2210// Pattern to select load absolute. 2211class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 2212 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 2213 2214// Pattern to select load absolute with value modifier. 2215class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 2216 InstHexagon MI> 2217 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 2218 2219 2220let AddedComplexity = 20 in { 2221 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 2222 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 2223 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 2224 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2225 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2226 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 2227 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 2228 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 2229 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbsw4_io>; 2230 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 2231 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 2232 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 2233 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2234 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2235 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 2236 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 2237 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 2238 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 2239 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 2240 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 2241 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 2242 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 2243 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 2244 // No sextloadi1. 2245 2246 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 2247 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 2248 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 2249 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 2250} 2251 2252let AddedComplexity = 30 in { 2253 // Loads of i1 are loading a byte, and the byte should be either 0 or 1. 2254 // It doesn't matter if it's sign- or zero-extended, so use zero-extension 2255 // everywhere. 2256 defm: Loadxim_pat<sextloadi1, i32, L1toI32, anyimm0, L2_loadrub_io>; 2257 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 2258 defm: Loadxim_pat<sextloadi1, i64, L1toI64, anyimm0, L2_loadrub_io>; 2259 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 2260 2261 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 2262 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 2263 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 2264 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 2265 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 2266 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 2267 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 2268 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 2269 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 2270} 2271 2272let AddedComplexity = 60 in { 2273 def: Loadxu_pat<extloadi1, i32, anyimm0, L4_loadrub_ur>; 2274 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 2275 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 2276 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2277 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2278 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 2279 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 2280 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 2281 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbsw4_ur>; 2282 def: Loadxu_pat<zextloadi1, i32, anyimm0, L4_loadrub_ur>; 2283 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 2284 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 2285 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2286 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2287 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 2288 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 2289 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 2290 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 2291 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 2292 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 2293 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 2294 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 2295 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2296 2297 def: Loadxum_pat<sextloadi1, i32, anyimm0, L1toI32, L4_loadrub_ur>; 2298 def: Loadxum_pat<extloadi1, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2299 def: Loadxum_pat<sextloadi1, i64, anyimm0, L1toI64, L4_loadrub_ur>; 2300 def: Loadxum_pat<zextloadi1, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2301 2302 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2303 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2304 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2305 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2306 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2307 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2308 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2309 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2310 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2311} 2312 2313let AddedComplexity = 40 in { 2314 def: Loadxr_shl_pat<extloadi1, i32, L4_loadrub_rr>; 2315 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2316 def: Loadxr_shl_pat<zextloadi1, i32, L4_loadrub_rr>; 2317 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2318 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2319 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2320 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2321 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2322 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2323 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2324 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2325 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2326 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2327 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2328 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2329 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2330 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2331} 2332 2333let AddedComplexity = 20 in { 2334 def: Loadxr_add_pat<extloadi1, i32, L4_loadrub_rr>; 2335 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2336 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2337 def: Loadxr_add_pat<zextloadi1, i32, L4_loadrub_rr>; 2338 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2339 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2340 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2341 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2342 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2343 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2344 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2345 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2346 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2347 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2348 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2349 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2350 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2351} 2352 2353let AddedComplexity = 40 in { 2354 def: Loadxrm_shl_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2355 def: Loadxrm_shl_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2356 def: Loadxrm_shl_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2357 def: Loadxrm_shl_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2358 2359 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2360 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2361 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2362 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2363 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2364 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2365 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2366 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2367 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2368} 2369 2370let AddedComplexity = 30 in { 2371 def: Loadxrm_add_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2372 def: Loadxrm_add_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2373 def: Loadxrm_add_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2374 def: Loadxrm_add_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2375 2376 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2377 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2378 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2379 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2380 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2381 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2382 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2383 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2384 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2385} 2386 2387// Absolute address 2388 2389let AddedComplexity = 60 in { 2390 def: Loada_pat<extloadi1, i32, anyimm0, PS_loadrubabs>; 2391 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2392 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2393 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2394 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2395 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2396 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2397 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2398 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2399 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2400 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2401 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2402 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2403 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2404 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2405 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2406 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2407 2408 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2409 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2410 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2411 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2412} 2413 2414let AddedComplexity = 30 in { 2415 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2416 def: Loadam_pat<sextloadi1, i32, anyimm0, L1toI32, PS_loadrubabs>; 2417 def: Loadam_pat<extloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2418 def: Loadam_pat<sextloadi1, i64, anyimm0, L1toI64, PS_loadrubabs>; 2419 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2420 2421 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2422 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2423 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2424 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2425 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2426 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2427 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2428 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2429 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2430} 2431 2432// GP-relative address 2433 2434let AddedComplexity = 100 in { 2435 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2436 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2437 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2438 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2439 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2440 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2441 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2442 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2443 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2444 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2445 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2446 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2447 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2448 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2449 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2450 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2451 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2452 2453 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2454 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2455 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2456 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2457} 2458 2459let AddedComplexity = 70 in { 2460 def: Loadam_pat<sextloadi1, i32, addrgp, L1toI32, L2_loadrubgp>; 2461 def: Loadam_pat<extloadi1, i64, addrgp, ToAext64, L2_loadrubgp>; 2462 def: Loadam_pat<sextloadi1, i64, addrgp, L1toI64, L2_loadrubgp>; 2463 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2464 2465 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2466 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2467 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2468 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2469 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2470 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2471 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2472 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2473 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2474 2475 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2476} 2477 2478// Patterns for loads of i1: 2479def: Pat<(i1 (load AddrFI:$fi)), 2480 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2481def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2482 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2483def: Pat<(i1 (load I32:$Rs)), 2484 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2485 2486 2487// --(13) Store ---------------------------------------------------------- 2488// 2489 2490class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2491 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2492 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2493 2494def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2495def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2496def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2497def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2498 2499// Patterns for generating stores, where the address takes different forms: 2500// - frameindex, 2501// - frameindex + offset, 2502// - base + offset, 2503// - simple (base address without offset). 2504// These would usually be used together (via Storexi_pat defined below), but 2505// in some cases one may want to apply different properties (such as 2506// AddedComplexity) to the individual patterns. 2507class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2508 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2509 2510multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2511 InstHexagon MI> { 2512 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2513 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2514 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2515 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2516} 2517 2518multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2519 InstHexagon MI> { 2520 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2521 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2522 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2523 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2524} 2525 2526class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2527 : Pat<(Store Value:$Rt, I32:$Rs), 2528 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2529 2530// Patterns for generating stores, where the address takes different forms, 2531// and where the value being stored is transformed through the value modifier 2532// ValueMod. The address forms are same as above. 2533class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2534 InstHexagon MI> 2535 : Pat<(Store Value:$Rs, AddrFI:$fi), 2536 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2537 2538multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2539 PatFrag ValueMod, InstHexagon MI> { 2540 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2541 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2542 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2543 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2544} 2545 2546multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2547 PatFrag ValueMod, InstHexagon MI> { 2548 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2549 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2550 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2551 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2552} 2553 2554class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2555 InstHexagon MI> 2556 : Pat<(Store Value:$Rt, I32:$Rs), 2557 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2558 2559multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2560 InstHexagon MI> { 2561 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2562 def: Storexi_fi_pat <Store, Value, MI>; 2563 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2564} 2565 2566multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2567 PatFrag ValueMod, InstHexagon MI> { 2568 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2569 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2570 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2571} 2572 2573// Reg<<S + Imm 2574class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2575 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2576 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2577 2578// Reg<<S + Reg 2579class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2580 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2581 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2582 2583// Reg + Reg 2584class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2585 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2586 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2587 2588class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2589 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2590 2591class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2592 InstHexagon MI> 2593 : Pat<(Store Value:$val, Addr:$addr), 2594 (MI Addr:$addr, (ValueMod Value:$val))>; 2595 2596def IMM_BYTE : SDNodeXForm<imm, [{ 2597 // -1 can be represented as 255, etc. 2598 // assigning to a byte restores our desired signed value. 2599 int8_t imm = N->getSExtValue(); 2600 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2601}]>; 2602 2603def IMM_HALF : SDNodeXForm<imm, [{ 2604 // -1 can be represented as 65535, etc. 2605 // assigning to a short restores our desired signed value. 2606 int16_t imm = N->getSExtValue(); 2607 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2608}]>; 2609 2610def IMM_WORD : SDNodeXForm<imm, [{ 2611 // -1 can be represented as 4294967295, etc. 2612 // Currently, it's not doing this. But some optimization 2613 // might convert -1 to a large +ve number. 2614 // assigning to a word restores our desired signed value. 2615 int32_t imm = N->getSExtValue(); 2616 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2617}]>; 2618 2619def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2620def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2621def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2622 2623// Even though the offset is not extendable in the store-immediate, we 2624// can still generate the fi# in the base address. If the final offset 2625// is not valid for the instruction, we will replace it with a scratch 2626// register. 2627class SmallStackStore<PatFrag Store> 2628 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2629 return isSmallStackStore(cast<StoreSDNode>(N)); 2630}]>; 2631 2632// This is the complement of SmallStackStore. 2633class LargeStackStore<PatFrag Store> 2634 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2635 return !isSmallStackStore(cast<StoreSDNode>(N)); 2636}]>; 2637 2638// Preferred addressing modes for various combinations of stored value 2639// and address computation. 2640// For stores where the address and value are both immediates, prefer 2641// store-immediate. The reason is that the constant-extender optimization 2642// can replace store-immediate with a store-register, but there is nothing 2643// to generate a store-immediate out of a store-register. 2644// 2645// C R F F+C R+C R+R R<<S+C R<<S+R 2646// --+-------+-----+-----+------+-----+-----+--------+-------- 2647// C | imm | imm | imm | imm | imm | rr | ur | rr 2648// R | abs* | io | io | io | io | rr | ur | rr 2649// 2650// (*) Absolute or GP-relative. 2651// 2652// Note that any expression can be matched by Reg. In particular, an immediate 2653// can always be placed in a register, so patterns checking for Imm should 2654// have a higher priority than the ones involving Reg that could also match. 2655// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2656// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2657// Reg alone. 2658// 2659// The order in which the different combinations are tried: 2660// 2661// C F R F+C R+C R+R R<<S+C R<<S+R 2662// --+-------+-----+-----+------+-----+-----+--------+-------- 2663// C | 1 | 6 | - | 5 | 9 | - | - | - 2664// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2665 2666 2667// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2668// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2669// implies that Reg is also a proper multiple of 4. To still generate a 2670// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2671 2672def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2673 int64_t v = (int64_t)N->getSExtValue(); 2674 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2675}]>; 2676def RoundTo8 : SDNodeXForm<imm, [{ 2677 int32_t Imm = N->getSExtValue(); 2678 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2679}]>; 2680 2681let AddedComplexity = 150 in 2682def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2683 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2684 2685class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2686 : Pat<(Store Value:$val, anyimm:$addr), 2687 (MI (ToI32 $addr), 0, Value:$val)>; 2688class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2689 InstHexagon MI> 2690 : Pat<(Store Value:$val, anyimm:$addr), 2691 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2692 2693let AddedComplexity = 140 in { 2694 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2695 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2696 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2697 2698 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2699 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2700 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2701} 2702 2703// GP-relative address 2704let AddedComplexity = 120 in { 2705 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2706 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2707 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2708 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2709 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2710 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2711 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2712 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2713 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2714 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2715 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2716 def: Storea_pat<atomic_store_8, I32, addrgp, S2_storerbgp>; 2717 def: Storea_pat<atomic_store_16, I32, addrgp, S2_storerhgp>; 2718 def: Storea_pat<atomic_store_32, I32, addrgp, S2_storerigp>; 2719 def: Storea_pat<atomic_store_32, V4I8, addrgp, S2_storerigp>; 2720 def: Storea_pat<atomic_store_32, V2I16, addrgp, S2_storerigp>; 2721 def: Storea_pat<atomic_store_64, I64, addrgp, S2_storerdgp>; 2722 def: Storea_pat<atomic_store_64, V8I8, addrgp, S2_storerdgp>; 2723 def: Storea_pat<atomic_store_64, V4I16, addrgp, S2_storerdgp>; 2724 def: Storea_pat<atomic_store_64, V2I32, addrgp, S2_storerdgp>; 2725 2726 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2727 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2728 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2729 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2730} 2731 2732// Absolute address 2733let AddedComplexity = 110 in { 2734 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2735 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2736 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2737 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2738 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2739 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2740 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2741 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2742 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2743 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2744 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2745 def: Storea_pat<atomic_store_8, I32, anyimm0, PS_storerbabs>; 2746 def: Storea_pat<atomic_store_16, I32, anyimm1, PS_storerhabs>; 2747 def: Storea_pat<atomic_store_32, I32, anyimm2, PS_storeriabs>; 2748 def: Storea_pat<atomic_store_32, V4I8, anyimm2, PS_storeriabs>; 2749 def: Storea_pat<atomic_store_32, V2I16, anyimm2, PS_storeriabs>; 2750 def: Storea_pat<atomic_store_64, I64, anyimm3, PS_storerdabs>; 2751 def: Storea_pat<atomic_store_64, V8I8, anyimm3, PS_storerdabs>; 2752 def: Storea_pat<atomic_store_64, V4I16, anyimm3, PS_storerdabs>; 2753 def: Storea_pat<atomic_store_64, V2I32, anyimm3, PS_storerdabs>; 2754 2755 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2756 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2757 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2758 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2759} 2760 2761// Reg<<S + Imm 2762let AddedComplexity = 100 in { 2763 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2764 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2765 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2766 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2767 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2768 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2769 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2770 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2771 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2772 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2773 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2774 2775 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2776 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2777} 2778 2779// Reg<<S + Reg 2780let AddedComplexity = 90 in { 2781 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2782 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2783 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2784 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2785 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2786 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2787 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2788 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2789 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2790 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2791 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2792 2793 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2794 (S4_storerb_rr IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2795} 2796 2797class SS_<PatFrag F> : SmallStackStore<F>; 2798class LS_<PatFrag F> : LargeStackStore<F>; 2799 2800multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2801 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2802} 2803multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2804 defm: Storexi_fi_add_pat<S, V, O, I>; 2805} 2806 2807// Fi+Imm, store-immediate 2808let AddedComplexity = 80 in { 2809 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2810 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2811 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2812 2813 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2814 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2815 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2816 2817 // For large-stack stores, generate store-register (prefer explicit Fi 2818 // in the address). 2819 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2820 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2821 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2822} 2823 2824// Fi, store-immediate 2825let AddedComplexity = 70 in { 2826 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2827 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2828 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2829 2830 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2831 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2832 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2833 2834 // For large-stack stores, generate store-register (prefer explicit Fi 2835 // in the address). 2836 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2837 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2838 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2839} 2840 2841// Fi+Imm, Fi, store-register 2842let AddedComplexity = 60 in { 2843 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2844 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2845 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2846 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2847 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2848 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2849 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2850 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2851 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2852 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2853 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2854 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2855 2856 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2857 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2858 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2859 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2860 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2861 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2862 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2863 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2864 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2865 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2866 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2867 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2868} 2869 2870 2871multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2872 defm: Storexim_add_pat<S, V, O, M, I>; 2873} 2874multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2875 defm: Storexi_add_pat<S, V, O, I>; 2876} 2877 2878// Reg+Imm, store-immediate 2879let AddedComplexity = 50 in { 2880 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2881 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2882 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2883 2884 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2885 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2886 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2887} 2888 2889// Reg+Imm, store-register 2890let AddedComplexity = 40 in { 2891 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2892 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2893 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2894 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2895 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2896 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2897 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2898 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2899 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2900 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2901 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2902 2903 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2904 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2905 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2906 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2907 2908 defm: Storexi_pat<atomic_store_8, I32, anyimm0, S2_storerb_io>; 2909 defm: Storexi_pat<atomic_store_16, I32, anyimm1, S2_storerh_io>; 2910 defm: Storexi_pat<atomic_store_32, I32, anyimm2, S2_storeri_io>; 2911 defm: Storexi_pat<atomic_store_32, V4I8, anyimm2, S2_storeri_io>; 2912 defm: Storexi_pat<atomic_store_32, V2I16, anyimm2, S2_storeri_io>; 2913 defm: Storexi_pat<atomic_store_64, I64, anyimm3, S2_storerd_io>; 2914 defm: Storexi_pat<atomic_store_64, V8I8, anyimm3, S2_storerd_io>; 2915 defm: Storexi_pat<atomic_store_64, V4I16, anyimm3, S2_storerd_io>; 2916 defm: Storexi_pat<atomic_store_64, V2I32, anyimm3, S2_storerd_io>; 2917} 2918 2919// Reg+Reg 2920let AddedComplexity = 30 in { 2921 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2922 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2923 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2924 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2925 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2926 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2927 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2928 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2929 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2930 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2931 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2932 2933 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2934 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2935} 2936 2937// Reg, store-immediate 2938let AddedComplexity = 20 in { 2939 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2940 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2941 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2942 2943 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2944 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2945 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2946} 2947 2948// Reg, store-register 2949let AddedComplexity = 10 in { 2950 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2951 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2952 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2953 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2954 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2955 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2956 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2957 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2958 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2959 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2960 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2961 2962 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2963 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2964 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2965 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2966 2967 def: Storexi_base_pat<atomic_store_8, I32, S2_storerb_io>; 2968 def: Storexi_base_pat<atomic_store_16, I32, S2_storerh_io>; 2969 def: Storexi_base_pat<atomic_store_32, I32, S2_storeri_io>; 2970 def: Storexi_base_pat<atomic_store_32, V4I8, S2_storeri_io>; 2971 def: Storexi_base_pat<atomic_store_32, V2I16, S2_storeri_io>; 2972 def: Storexi_base_pat<atomic_store_64, I64, S2_storerd_io>; 2973 def: Storexi_base_pat<atomic_store_64, V8I8, S2_storerd_io>; 2974 def: Storexi_base_pat<atomic_store_64, V4I16, S2_storerd_io>; 2975 def: Storexi_base_pat<atomic_store_64, V2I32, S2_storerd_io>; 2976} 2977 2978 2979// --(14) Memop ---------------------------------------------------------- 2980// 2981 2982def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2983 int8_t V = N->getSExtValue(); 2984 return -32 < V && V <= -1; 2985}]>; 2986 2987def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2988 int16_t V = N->getSExtValue(); 2989 return -32 < V && V <= -1; 2990}]>; 2991 2992def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2993 int64_t V = N->getSExtValue(); 2994 return -31 <= V && V <= -1; 2995}]>; 2996 2997def IsNPow2_8 : PatLeaf<(i32 imm), [{ 2998 uint8_t NV = ~N->getZExtValue(); 2999 return isPowerOf2_32(NV); 3000}]>; 3001 3002def IsNPow2_16 : PatLeaf<(i32 imm), [{ 3003 uint16_t NV = ~N->getZExtValue(); 3004 return isPowerOf2_32(NV); 3005}]>; 3006 3007def Log2_8 : SDNodeXForm<imm, [{ 3008 uint8_t V = N->getZExtValue(); 3009 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 3010}]>; 3011 3012def Log2_16 : SDNodeXForm<imm, [{ 3013 uint16_t V = N->getZExtValue(); 3014 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 3015}]>; 3016 3017def LogN2_8 : SDNodeXForm<imm, [{ 3018 uint8_t NV = ~N->getZExtValue(); 3019 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 3020}]>; 3021 3022def LogN2_16 : SDNodeXForm<imm, [{ 3023 uint16_t NV = ~N->getZExtValue(); 3024 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 3025}]>; 3026 3027def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 3028 3029multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 3030 InstHexagon MI> { 3031 // Addr: i32 3032 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 3033 (MI I32:$Rs, 0, I32:$A)>; 3034 // Addr: fi 3035 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 3036 (MI AddrFI:$Rs, 0, I32:$A)>; 3037} 3038 3039multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3040 SDNode Oper, InstHexagon MI> { 3041 // Addr: i32 3042 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 3043 (add I32:$Rs, ImmPred:$Off)), 3044 (MI I32:$Rs, imm:$Off, I32:$A)>; 3045 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 3046 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3047 (MI I32:$Rs, imm:$Off, I32:$A)>; 3048 // Addr: fi 3049 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 3050 (add AddrFI:$Rs, ImmPred:$Off)), 3051 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 3052 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 3053 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3054 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 3055} 3056 3057multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3058 SDNode Oper, InstHexagon MI> { 3059 let Predicates = [UseMEMOPS] in { 3060 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 3061 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 3062 } 3063} 3064 3065let AddedComplexity = 200 in { 3066 // add reg 3067 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 3068 /*anyext*/ L4_add_memopb_io>; 3069 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 3070 /*sext*/ L4_add_memopb_io>; 3071 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 3072 /*zext*/ L4_add_memopb_io>; 3073 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 3074 /*anyext*/ L4_add_memoph_io>; 3075 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 3076 /*sext*/ L4_add_memoph_io>; 3077 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 3078 /*zext*/ L4_add_memoph_io>; 3079 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 3080 3081 // sub reg 3082 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 3083 /*anyext*/ L4_sub_memopb_io>; 3084 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 3085 /*sext*/ L4_sub_memopb_io>; 3086 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 3087 /*zext*/ L4_sub_memopb_io>; 3088 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 3089 /*anyext*/ L4_sub_memoph_io>; 3090 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 3091 /*sext*/ L4_sub_memoph_io>; 3092 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 3093 /*zext*/ L4_sub_memoph_io>; 3094 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 3095 3096 // and reg 3097 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 3098 /*anyext*/ L4_and_memopb_io>; 3099 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 3100 /*sext*/ L4_and_memopb_io>; 3101 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 3102 /*zext*/ L4_and_memopb_io>; 3103 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 3104 /*anyext*/ L4_and_memoph_io>; 3105 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 3106 /*sext*/ L4_and_memoph_io>; 3107 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 3108 /*zext*/ L4_and_memoph_io>; 3109 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 3110 3111 // or reg 3112 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 3113 /*anyext*/ L4_or_memopb_io>; 3114 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 3115 /*sext*/ L4_or_memopb_io>; 3116 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 3117 /*zext*/ L4_or_memopb_io>; 3118 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 3119 /*anyext*/ L4_or_memoph_io>; 3120 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 3121 /*sext*/ L4_or_memoph_io>; 3122 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 3123 /*zext*/ L4_or_memoph_io>; 3124 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 3125} 3126 3127 3128multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 3129 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 3130 // Addr: i32 3131 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 3132 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 3133 // Addr: fi 3134 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 3135 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 3136} 3137 3138multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3139 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3140 InstHexagon MI> { 3141 // Addr: i32 3142 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 3143 (add I32:$Rs, ImmPred:$Off)), 3144 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3145 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 3146 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3147 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3148 // Addr: fi 3149 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3150 (add AddrFI:$Rs, ImmPred:$Off)), 3151 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3152 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3153 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3154 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3155} 3156 3157multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3158 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3159 InstHexagon MI> { 3160 let Predicates = [UseMEMOPS] in { 3161 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 3162 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 3163 } 3164} 3165 3166let AddedComplexity = 220 in { 3167 // add imm 3168 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3169 /*anyext*/ IdImm, L4_iadd_memopb_io>; 3170 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3171 /*sext*/ IdImm, L4_iadd_memopb_io>; 3172 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3173 /*zext*/ IdImm, L4_iadd_memopb_io>; 3174 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3175 /*anyext*/ IdImm, L4_iadd_memoph_io>; 3176 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3177 /*sext*/ IdImm, L4_iadd_memoph_io>; 3178 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3179 /*zext*/ IdImm, L4_iadd_memoph_io>; 3180 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 3181 L4_iadd_memopw_io>; 3182 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3183 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 3184 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3185 /*sext*/ NegImm8, L4_iadd_memopb_io>; 3186 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3187 /*zext*/ NegImm8, L4_iadd_memopb_io>; 3188 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3189 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 3190 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3191 /*sext*/ NegImm16, L4_iadd_memoph_io>; 3192 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3193 /*zext*/ NegImm16, L4_iadd_memoph_io>; 3194 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 3195 L4_iadd_memopw_io>; 3196 3197 // sub imm 3198 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3199 /*anyext*/ IdImm, L4_isub_memopb_io>; 3200 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3201 /*sext*/ IdImm, L4_isub_memopb_io>; 3202 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3203 /*zext*/ IdImm, L4_isub_memopb_io>; 3204 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3205 /*anyext*/ IdImm, L4_isub_memoph_io>; 3206 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3207 /*sext*/ IdImm, L4_isub_memoph_io>; 3208 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3209 /*zext*/ IdImm, L4_isub_memoph_io>; 3210 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 3211 L4_isub_memopw_io>; 3212 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3213 /*anyext*/ NegImm8, L4_isub_memopb_io>; 3214 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3215 /*sext*/ NegImm8, L4_isub_memopb_io>; 3216 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3217 /*zext*/ NegImm8, L4_isub_memopb_io>; 3218 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3219 /*anyext*/ NegImm16, L4_isub_memoph_io>; 3220 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3221 /*sext*/ NegImm16, L4_isub_memoph_io>; 3222 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3223 /*zext*/ NegImm16, L4_isub_memoph_io>; 3224 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 3225 L4_isub_memopw_io>; 3226 3227 // clrbit imm 3228 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3229 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 3230 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3231 /*sext*/ LogN2_8, L4_iand_memopb_io>; 3232 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3233 /*zext*/ LogN2_8, L4_iand_memopb_io>; 3234 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3235 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 3236 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3237 /*sext*/ LogN2_16, L4_iand_memoph_io>; 3238 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3239 /*zext*/ LogN2_16, L4_iand_memoph_io>; 3240 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 3241 LogN2_32, L4_iand_memopw_io>; 3242 3243 // setbit imm 3244 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3245 /*anyext*/ Log2_8, L4_ior_memopb_io>; 3246 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3247 /*sext*/ Log2_8, L4_ior_memopb_io>; 3248 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3249 /*zext*/ Log2_8, L4_ior_memopb_io>; 3250 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3251 /*anyext*/ Log2_16, L4_ior_memoph_io>; 3252 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3253 /*sext*/ Log2_16, L4_ior_memoph_io>; 3254 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3255 /*zext*/ Log2_16, L4_ior_memoph_io>; 3256 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 3257 Log2_32, L4_ior_memopw_io>; 3258} 3259 3260 3261// --(15) Call ----------------------------------------------------------- 3262// 3263 3264// Pseudo instructions. 3265def SDT_SPCallSeqStart 3266 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3267def SDT_SPCallSeqEnd 3268 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3269 3270def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 3271 [SDNPHasChain, SDNPOutGlue]>; 3272def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 3273 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 3274 3275def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3276 3277def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 3278 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3279def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 3280 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3281def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 3282 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3283 3284def: Pat<(callseq_start timm:$amt, timm:$amt2), 3285 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 3286def: Pat<(callseq_end timm:$amt1, timm:$amt2), 3287 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 3288 3289def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 3290def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 3291def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 3292 3293def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 3294def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 3295def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 3296def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 3297 3298def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 3299def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 3300def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 3301 3302def retglue : SDNode<"HexagonISD::RET_GLUE", SDTNone, 3303 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3304def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3305 3306def: Pat<(retglue), (PS_jmpret (i32 R31))>; 3307def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3308 3309 3310// --(16) Branch --------------------------------------------------------- 3311// 3312 3313def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3314def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3315 3316def: Pat<(brcond I1:$Pu, bb:$dst), 3317 (J2_jumpt I1:$Pu, bb:$dst)>; 3318def: Pat<(brcond (not I1:$Pu), bb:$dst), 3319 (J2_jumpf I1:$Pu, bb:$dst)>; 3320def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3321 (J2_jumpf I1:$Pu, bb:$dst)>; 3322def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3323 (J2_jumpf I1:$Pu, bb:$dst)>; 3324def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3325 (J2_jumpt I1:$Pu, bb:$dst)>; 3326 3327 3328// --(17) Misc ----------------------------------------------------------- 3329 3330 3331// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3332// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3333// The isdigit transformation relies on two 'clever' aspects: 3334// 1) The data type is unsigned which allows us to eliminate a zero test after 3335// biasing the expression by 48. We are depending on the representation of 3336// the unsigned types, and semantics. 3337// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3338// 3339// For the C code: 3340// retval = (c >= '0' && c <= '9') ? 1 : 0; 3341// The code is transformed upstream of llvm into 3342// retval = (c-48) < 10 ? 1 : 0; 3343 3344def u7_0PosImmPred : ImmLeaf<i32, [{ 3345 // True if the immediate fits in an 7-bit unsigned field and is positive. 3346 return Imm > 0 && isUInt<7>(Imm); 3347}]>; 3348 3349let AddedComplexity = 139 in 3350def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3351 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3352 3353let AddedComplexity = 100 in 3354def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3355 (i32 (extloadi8 (add I32:$b, 3))), 3356 24, 8), 3357 (i32 16)), 3358 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3359 (zextloadi8 I32:$b)), 3360 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3361 3362 3363// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3364// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3365// We don't really want either one here. 3366def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3367def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3368 [SDNPHasChain]>; 3369 3370def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3371 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3372def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3373 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3374 3375def SDTHexagonALLOCA 3376 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3377def HexagonALLOCA 3378 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3379 3380def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3381 (PS_alloca IntRegs:$Rs, imm:$A)>; 3382 3383def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3384def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3385 3386def: Pat<(trap), (PS_crash)>; 3387 3388// Read cycle counter. 3389def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3390def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3391 [SDNPHasChain]>; 3392 3393def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3394 3395// The declared return value of the store-locked intrinsics is i32, but 3396// the instructions actually define i1. To avoid register copies from 3397// IntRegs to PredRegs and back, fold the entire pattern checking the 3398// result against true/false. 3399let AddedComplexity = 100 in { 3400 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3401 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3402 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3403 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3404 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3405 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3406 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3407 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3408} 3409 3410def: Pat<(int_hexagon_instrprof_custom (HexagonAtPcrel tglobaladdr:$addr), u32_0ImmPred:$I), 3411 (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; 3412 3413def: Pat<(int_hexagon_instrprof_custom (HexagonCONST32 tglobaladdr:$addr), u32_0ImmPred:$I), 3414 (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; 3415