1//===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def SDTVecLeaf: 91 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 92def SDTVecVecIntOp: 93 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 94 SDTCisVT<3,i32>]>; 95 96def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>; 97def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>; 98def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 99def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 100 101def ptrue: PatFrag<(ops), (HexagonPTRUE)>; 102def pfalse: PatFrag<(ops), (HexagonPFALSE)>; 103def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>; 104 105def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 106 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 107def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 108 109// Pattern fragments to extract the low and high subregisters from a 110// 64-bit value. 111def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>; 112def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>; 113 114def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 115 return isOrEquivalentToAdd(N); 116}]>; 117 118def IsPow2_32: PatLeaf<(i32 imm), [{ 119 uint32_t V = N->getZExtValue(); 120 return isPowerOf2_32(V); 121}]>; 122 123def IsPow2_64: PatLeaf<(i64 imm), [{ 124 uint64_t V = N->getZExtValue(); 125 return isPowerOf2_64(V); 126}]>; 127 128def IsNPow2_32: PatLeaf<(i32 imm), [{ 129 uint32_t NV = ~N->getZExtValue(); 130 return isPowerOf2_32(NV); 131}]>; 132 133def IsPow2_64L: PatLeaf<(i64 imm), [{ 134 uint64_t V = N->getZExtValue(); 135 return isPowerOf2_64(V) && Log2_64(V) < 32; 136}]>; 137 138def IsPow2_64H: PatLeaf<(i64 imm), [{ 139 uint64_t V = N->getZExtValue(); 140 return isPowerOf2_64(V) && Log2_64(V) >= 32; 141}]>; 142 143def IsNPow2_64L: PatLeaf<(i64 imm), [{ 144 uint64_t NV = ~N->getZExtValue(); 145 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 146}]>; 147 148def IsNPow2_64H: PatLeaf<(i64 imm), [{ 149 uint64_t NV = ~N->getZExtValue(); 150 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 151}]>; 152 153class IsULE<int Width, int Arg>: PatLeaf<(i32 imm), 154 "uint64_t V = N->getZExtValue();" # 155 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";" 156>; 157 158class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 159 "uint64_t V = N->getZExtValue();" # 160 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 161>; 162 163def SDEC1: SDNodeXForm<imm, [{ 164 int32_t V = N->getSExtValue(); 165 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 166}]>; 167 168def UDEC1: SDNodeXForm<imm, [{ 169 uint32_t V = N->getZExtValue(); 170 assert(V >= 1); 171 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 172}]>; 173 174def UDEC32: SDNodeXForm<imm, [{ 175 uint32_t V = N->getZExtValue(); 176 assert(V >= 32); 177 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 178}]>; 179 180class Subi<int From>: SDNodeXForm<imm, 181 "int32_t V = " # From # " - N->getSExtValue();" # 182 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 183>; 184 185def Log2_32: SDNodeXForm<imm, [{ 186 uint32_t V = N->getZExtValue(); 187 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 188}]>; 189 190def Log2_64: SDNodeXForm<imm, [{ 191 uint64_t V = N->getZExtValue(); 192 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 193}]>; 194 195def LogN2_32: SDNodeXForm<imm, [{ 196 uint32_t NV = ~N->getZExtValue(); 197 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 198}]>; 199 200def LogN2_64: SDNodeXForm<imm, [{ 201 uint64_t NV = ~N->getZExtValue(); 202 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 203}]>; 204 205def NegImm8: SDNodeXForm<imm, [{ 206 int8_t NV = -N->getSExtValue(); 207 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 208}]>; 209 210def NegImm16: SDNodeXForm<imm, [{ 211 int16_t NV = -N->getSExtValue(); 212 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 213}]>; 214 215def NegImm32: SDNodeXForm<imm, [{ 216 int32_t NV = -N->getSExtValue(); 217 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 218}]>; 219 220def SplatB: SDNodeXForm<imm, [{ 221 uint32_t V = N->getZExtValue(); 222 assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF); 223 V &= 0xFF; 224 uint32_t S = V << 24 | V << 16 | V << 8 | V; 225 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32); 226}]>; 227 228def SplatH: SDNodeXForm<imm, [{ 229 uint32_t V = N->getZExtValue(); 230 assert(isUInt<16>(V) || V >> 16 == 0xFFFF); 231 V &= 0xFFFF; 232 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32); 233}]>; 234 235 236// Helpers for type promotions/contractions. 237def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 238def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 239def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 240def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 241def ToAext64: OutPatFrag<(ops node:$Rs), 242 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 243 244def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 245 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 246 247def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 248def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 249def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 250def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 251 252// Global address or an aligned constant. 253def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 254def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 255def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 256def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 257 258def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 259def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 260def f32zero: PatLeaf<(f32 fpimm:$F), [{ 261 return N->isExactlyValue(APFloat::getZero(APFloat::IEEEsingle(), false)); 262}]>; 263 264// This complex pattern is really only to detect various forms of 265// sign-extension i32->i64. The selected value will be of type i64 266// whose low word is the value being extended. The high word is 267// unspecified. 268def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 269 270def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 271def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 272def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 273 274def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 275def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 276 277def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 278 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 279 280 281// Converters from unary/binary SDNode to PatFrag. 282class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 283class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 284 285class Not2<PatFrag P> 286 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 287class VNot2<PatFrag P, PatFrag Not> 288 : PatFrag<(ops node:$A, node:$B), (P node:$A, (Not node:$B))>; 289 290// If there is a constant operand that feeds the and/or instruction, 291// do not generate the compound instructions. 292// It is not always profitable, as some times we end up with a transfer. 293// Check the below example. 294// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 295// Instead this is preferable. 296// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 297class Su_ni1<PatFrag Op> 298 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 299 if (hasOneUse(N)){ 300 // Check if Op1 is an immediate operand. 301 SDValue Op1 = N->getOperand(1); 302 return !isa<ConstantSDNode>(Op1); 303 } 304 return false;}], 305 Op.OperandTransform>; 306 307class Su<PatFrag Op> 308 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 309 Op.OperandTransform>; 310 311// Main selection macros. 312 313class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 314 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 315 316class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 317 PatFrag RegPred, PatFrag ImmPred> 318 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 319 (MI RegPred:$Rs, imm:$I)>; 320 321class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 322 PatFrag RsPred, PatFrag RtPred = RsPred> 323 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 324 (MI RsPred:$Rs, RtPred:$Rt)>; 325 326class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 327 PatFrag RegPred, PatFrag ImmPred> 328 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 329 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 330 331class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 332 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 333 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 334 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 335 336multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 337 InstHexagon InstA, InstHexagon InstB> { 338 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 339 (InstA Val:$A, Val:$B)>; 340 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 341 (InstB Val:$A, Val:$B)>; 342} 343 344multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, 345 SDPatternOperator Sel, SDPatternOperator CmpOp, 346 ValueType CmpType, PatFrag CmpPred> { 347 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 348 CmpPred:$Vt, CmpPred:$Vs), 349 (PickT CmpPred:$Vs, CmpPred:$Vt)>; 350 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 351 CmpPred:$Vs, CmpPred:$Vt), 352 (PickS CmpPred:$Vs, CmpPred:$Vt)>; 353} 354 355// Bitcasts between same-size vector types are no-ops, except for the 356// actual type change. 357multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> { 358 def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>; 359 def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; 360} 361 362// Frags for commonly used SDNodes. 363def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 364def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 365def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 366 367def Smin: pf2<smin>; def Smax: pf2<smax>; 368def Umin: pf2<umin>; def Umax: pf2<umax>; 369 370def Rol: pf2<rotl>; 371 372def Fptosi: pf1<fp_to_sint>; 373def Fptoui: pf1<fp_to_uint>; 374def Sitofp: pf1<sint_to_fp>; 375def Uitofp: pf1<uint_to_fp>; 376 377 378// --(1) Immediate ------------------------------------------------------- 379// 380 381def Imm64Lo: SDNodeXForm<imm, [{ 382 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()), 383 SDLoc(N), MVT::i32); 384}]>; 385def Imm64Hi: SDNodeXForm<imm, [{ 386 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32), 387 SDLoc(N), MVT::i32); 388}]>; 389 390 391def SDTHexagonCONST32 392 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 393 394def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 395def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 396def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 397def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 398 399def TruncI64ToI32: SDNodeXForm<imm, [{ 400 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 401}]>; 402 403def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 404def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 405 406def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 407def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 408def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 409def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 410def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 411def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 412def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 413// The HVX load patterns also match CP directly. Make sure that if 414// the selection of this opcode changes, it's updated in all places. 415 416def: Pat<(i1 0), (PS_false)>; 417def: Pat<(i1 1), (PS_true)>; 418def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, 419 Requires<[UseSmallData,NotOptTinyCore]>; 420def: Pat<(i64 imm:$v), 421 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; 422 423def ftoi : SDNodeXForm<fpimm, [{ 424 APInt I = N->getValueAPF().bitcastToAPInt(); 425 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 426 MVT::getIntegerVT(I.getBitWidth())); 427}]>; 428 429def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 430def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 431 432def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 433 434// --(2) Type cast ------------------------------------------------------- 435// 436 437def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 438def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 439 440def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 441def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 442def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 443def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 444 445def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 446def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 447def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 448def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 449 450def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 451def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 452def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 453def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 454 455def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 456def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 457def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 458def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 459 460// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 461def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 462def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 463def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 464def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 465 466// Bit convert 32- and 64-bit types. 467// All of these are bitcastable to one another: i32, v2i16, v4i8. 468defm: NopCast_pat<i32, v2i16, IntRegs>; 469defm: NopCast_pat<i32, v4i8, IntRegs>; 470defm: NopCast_pat<v2i16, v4i8, IntRegs>; 471// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 472defm: NopCast_pat<i64, v2i32, DoubleRegs>; 473defm: NopCast_pat<i64, v4i16, DoubleRegs>; 474defm: NopCast_pat<i64, v8i8, DoubleRegs>; 475defm: NopCast_pat<v2i32, v4i16, DoubleRegs>; 476defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 477defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 478 479 480// --(3) Extend/truncate ------------------------------------------------- 481// 482 483def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 484def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 485def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 486def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 487def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 488 489def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 490def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 491def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 492 493def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 494def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 495def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 496 497let AddedComplexity = 20 in { 498 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 499 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 500} 501 502// Extensions from i1 or vectors of i1. 503def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 504def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 505def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 506def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 507 (C2_muxii PredRegs:$Pu, -1, 0))>; 508 509def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 510def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 511def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 512def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 513def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 514 515def Vsplatpi: OutPatFrag<(ops node:$V), 516 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 517 518def: Pat<(v2i16 (azext V2I1:$Pu)), 519 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 520def: Pat<(v2i32 (azext V2I1:$Pu)), 521 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 522def: Pat<(v4i8 (azext V4I1:$Pu)), 523 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 524def: Pat<(v4i16 (azext V4I1:$Pu)), 525 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 526def: Pat<(v8i8 (azext V8I1:$Pu)), 527 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 528 529def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 530def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 531def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 532def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 533 534def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 535 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 536 537def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 538 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 539 540// Truncate: from vector B copy all 'E'ven 'B'yte elements: 541// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 542def: Pat<(v4i8 (trunc V4I16:$Rs)), 543 (S2_vtrunehb V4I16:$Rs)>; 544 545// Truncate: from vector B copy all 'O'dd 'B'yte elements: 546// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 547// S2_vtrunohb 548 549// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 550// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 551// S2_vtruneh 552 553def: Pat<(v2i16 (trunc V2I32:$Rs)), 554 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 555 556 557// --(4) Logical --------------------------------------------------------- 558// 559 560def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 561def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>; 562def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>; 563def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>; 564def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 565 566def: OpR_RR_pat<C2_and, And, i1, I1>; 567def: OpR_RR_pat<C2_or, Or, i1, I1>; 568def: OpR_RR_pat<C2_xor, Xor, i1, I1>; 569def: OpR_RR_pat<C2_andn, Not2<And>, i1, I1>; 570def: OpR_RR_pat<C2_orn, Not2<Or>, i1, I1>; 571 572def: AccRRR_pat<C4_and_and, And, Su<And>, I1, I1, I1>; 573def: AccRRR_pat<C4_and_or, And, Su< Or>, I1, I1, I1>; 574def: AccRRR_pat<C4_or_and, Or, Su<And>, I1, I1, I1>; 575def: AccRRR_pat<C4_or_or, Or, Su< Or>, I1, I1, I1>; 576def: AccRRR_pat<C4_and_andn, And, Su<Not2<And>>, I1, I1, I1>; 577def: AccRRR_pat<C4_and_orn, And, Su<Not2< Or>>, I1, I1, I1>; 578def: AccRRR_pat<C4_or_andn, Or, Su<Not2<And>>, I1, I1, I1>; 579def: AccRRR_pat<C4_or_orn, Or, Su<Not2< Or>>, I1, I1, I1>; 580 581multiclass BoolvOpR_RR_pat<InstHexagon MI, PatFrag VOp> { 582 def: OpR_RR_pat<MI, VOp, v2i1, V2I1>; 583 def: OpR_RR_pat<MI, VOp, v4i1, V4I1>; 584 def: OpR_RR_pat<MI, VOp, v8i1, V8I1>; 585} 586 587multiclass BoolvAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag VOp> { 588 def: AccRRR_pat<MI, AccOp, VOp, V2I1, V2I1, V2I1>; 589 def: AccRRR_pat<MI, AccOp, VOp, V4I1, V4I1, V4I1>; 590 def: AccRRR_pat<MI, AccOp, VOp, V8I1, V8I1, V8I1>; 591} 592 593defm: BoolvOpR_RR_pat<C2_and, And>; 594defm: BoolvOpR_RR_pat<C2_or, Or>; 595defm: BoolvOpR_RR_pat<C2_xor, Xor>; 596defm: BoolvOpR_RR_pat<C2_andn, VNot2<And, pnot>>; 597defm: BoolvOpR_RR_pat<C2_orn, VNot2< Or, pnot>>; 598 599// op(Ps, op(Pt, Pu)) 600defm: BoolvAccRRR_pat<C4_and_and, And, Su<And>>; 601defm: BoolvAccRRR_pat<C4_and_or, And, Su<Or>>; 602defm: BoolvAccRRR_pat<C4_or_and, Or, Su<And>>; 603defm: BoolvAccRRR_pat<C4_or_or, Or, Su<Or>>; 604 605// op(Ps, op(Pt, !Pu)) 606defm: BoolvAccRRR_pat<C4_and_andn, And, Su<VNot2<And, pnot>>>; 607defm: BoolvAccRRR_pat<C4_and_orn, And, Su<VNot2< Or, pnot>>>; 608defm: BoolvAccRRR_pat<C4_or_andn, Or, Su<VNot2<And, pnot>>>; 609defm: BoolvAccRRR_pat<C4_or_orn, Or, Su<VNot2< Or, pnot>>>; 610 611 612// --(5) Compare --------------------------------------------------------- 613// 614 615// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 616// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 617 618def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 619def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 620def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 621 622def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 623 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 624def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 625 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 626 627def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 628 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 629def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 630 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 631 632// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 633// that reverse the order of the operands. 634class RevCmp<PatFrag F> 635 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 636 F.OperandTransform>; 637 638def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 639def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 640def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 641def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 642def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 643def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 644def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 645def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 646def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 647def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 648def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 649def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 650def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 651def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 652def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 653def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 654def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 655def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 656def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 657def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 658def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 659def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 660def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 661def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 662def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 663def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 664def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 665def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 666def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 667def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 668def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 669def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 670def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 671def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 672def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 673def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 674def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 675def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 676def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 677def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 678 679def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 680def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 681def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 682def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 683def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 684def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 685def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 686def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 687def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 688def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 689def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 690 691def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 692def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 693def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 694def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 695def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 696def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 697def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 698def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 699def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 700def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 701def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 702 703// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 704 705def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 706 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 707def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 708 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 709def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 710 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 711 712class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 713 PatFrag RsPred, PatFrag RtPred = RsPred> 714 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 715 (Output RsPred:$Rs, RtPred:$Rt)>; 716 717class Outn<InstHexagon MI> 718 : OutPatFrag<(ops node:$Rs, node:$Rt), 719 (C2_not (MI $Rs, $Rt))>; 720 721def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 722def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 723def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 724def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 725def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 726def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 727def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 728def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 729def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 730def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 731def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 732def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 733def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 734def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 735def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 736def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 737def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 738def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 739def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 740def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 741def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 742def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 743def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 744def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 745def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 746 747let AddedComplexity = 100 in { 748 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 749 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 750 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 751 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 752 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 753 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 754 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 755 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 756} 757 758// PatFrag for AsserZext which takes the original type as a parameter. 759def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 760def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 761class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 762 763multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 764 PatLeaf ImmPred, int Mask> { 765 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 766 (MI I32:$Rs, imm:$I)>; 767 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 768 (MI I32:$Rs, imm:$I)>; 769} 770 771multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 772 PatLeaf ImmPred, int Mask> { 773 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 774 (C2_not (MI I32:$Rs, imm:$I))>; 775 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 776 (C2_not (MI I32:$Rs, imm:$I))>; 777} 778 779multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 780 PatLeaf ImmPred, int Mask> { 781 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 782 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 783 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 784 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 785} 786 787let AddedComplexity = 200 in { 788 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 789 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 790 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 791 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 792 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 793 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 794 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 795 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 796} 797 798def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 799 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 800def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 801 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 802def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 803 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 804def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 805 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 806 807def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 808def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 809def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>; 810def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 811 812// Floating-point comparisons with checks for ordered/unordered status. 813 814class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 815 : OutPatFrag<(ops node:$Rs, node:$Rt), 816 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 817 818class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 819class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 820 821class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 822class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 823 824def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 825def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 826def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 827def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 828def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 829def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 830 831def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 832def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 833def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 834def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 835def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 836def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 837 838def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 839def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 840 841def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 842def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 843 844def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 845def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 846 847 848// --(6) Select ---------------------------------------------------------- 849// 850 851def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 852 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 853def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 854 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 855def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 856 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 857def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 858 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 859 860def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 861 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 862def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 863 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 864def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 865 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 866def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 867 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 868 869// Map from a 64-bit select to an emulated 64-bit mux. 870// Hexagon does not support 64-bit MUXes; so emulate with combines. 871def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 872 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 873 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 874 875def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 876 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 877def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 878 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 879def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 880 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 881def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 882 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 883 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 884 885def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 886 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 887def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 888 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 889 890def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 891 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 892def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 893 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 894 895def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 896 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 897def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 898 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 899def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 900 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 901 902def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt), 903 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>; 904def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt), 905 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>; 906def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt), 907 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>; 908 909 910// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 911def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw), 912 (C2_or (C2_and I1:$Pu, I1:$Pv), 913 (C2_andn I1:$Pw, I1:$Pu))>; 914 915 916def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 917 return isPositiveHalfWord(N); 918}]>; 919 920multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 921 InstHexagon InstB> { 922 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 923 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 924 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 925 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 926 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 927 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 928} 929 930let AddedComplexity = 200 in { 931 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 932 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 933 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 934 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 935 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 936 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 937 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 938 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 939} 940 941def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>; 942def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>; 943def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>; 944def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>; 945def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>; 946def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>; 947def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>; 948def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>; 949 950let AddedComplexity = 100 in { 951 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>; 952 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>; 953 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>; 954 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; 955} 956 957let AddedComplexity = 100, Predicates = [HasV67] in { 958 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; 959 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; 960 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; 961 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; 962} 963 964def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>; 965def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>; 966def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>; 967def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>; 968 969def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>; 970def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>; 971def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>; 972def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>; 973 974def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>; 975def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>; 976def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>; 977def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>; 978 979// --(7) Insert/extract -------------------------------------------------- 980// 981 982def SDTHexagonINSERT: 983 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 984 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 985def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 986 987let AddedComplexity = 10 in { 988 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 989 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 990 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 991 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 992} 993def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 994 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 995def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 996 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 997 998def SDTHexagonEXTRACTU 999 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 1000 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 1001def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 1002 1003let AddedComplexity = 10 in { 1004 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 1005 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 1006 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 1007 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 1008} 1009def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 1010 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 1011def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 1012 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 1013 1014def: Pat<(v4i8 (splat_vector anyint:$V)), (ToI32 (SplatB $V))>; 1015def: Pat<(v2i16 (splat_vector anyint:$V)), (ToI32 (SplatH $V))>; 1016def: Pat<(v8i8 (splat_vector anyint:$V)), 1017 (Combinew (ToI32 (SplatB $V)), (ToI32 (SplatB $V)))>; 1018def: Pat<(v4i16 (splat_vector anyint:$V)), 1019 (Combinew (ToI32 (SplatH $V)), (ToI32 (SplatH $V)))>; 1020let AddedComplexity = 10 in 1021def: Pat<(v2i32 (splat_vector s8_0ImmPred:$s8)), 1022 (A2_combineii imm:$s8, imm:$s8)>; 1023def: Pat<(v2i32 (splat_vector anyimm:$V)), (Combinew (ToI32 $V), (ToI32 $V))>; 1024 1025def: Pat<(v4i8 (splat_vector I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 1026def: Pat<(v2i16 (splat_vector I32:$Rs)), (LoReg (S2_vsplatrh I32:$Rs))>; 1027def: Pat<(v4i16 (splat_vector I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 1028def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 1029 1030let AddedComplexity = 10 in 1031def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 1032 Requires<[HasV62]>; 1033def: Pat<(v8i8 (splat_vector I32:$Rs)), 1034 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 1035 1036 1037// --(8) Shift/permute --------------------------------------------------- 1038// 1039 1040def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 1041 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 1042 1043def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 1044 1045def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 1046 1047// The complexity of the combines involving immediates should be greater 1048// than the complexity of the combine with two registers. 1049let AddedComplexity = 50 in { 1050 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 1051 (A4_combineri IntRegs:$Rs, imm:$s8)>; 1052 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 1053 (A4_combineir imm:$s8, IntRegs:$Rs)>; 1054} 1055 1056// The complexity of the combine with two immediates should be greater than 1057// the complexity of a combine involving a register. 1058let AddedComplexity = 75 in { 1059 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 1060 (A4_combineii imm:$s8, imm:$u6)>; 1061 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 1062 (A2_combineii imm:$s8, imm:$S8)>; 1063} 1064 1065def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 1066def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 1067 (A2_swiz (HiReg $Rss)))>; 1068 1069def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 1070def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 1071def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1072 1073def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 1074def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1075def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 1076def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 1077def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1078def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 1079def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 1080def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1081def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 1082def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 1083def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1084def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 1085 1086def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 1087def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1088def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 1089def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 1090def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1091def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1092 1093// Funnel shifts. 1094def IsMul8_U3: PatLeaf<(i32 imm), [{ 1095 uint64_t V = N->getZExtValue(); 1096 return V % 8 == 0 && isUInt<3>(V / 8); 1097}]>; 1098 1099def Divu8: SDNodeXForm<imm, [{ 1100 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1101}]>; 1102 1103// Funnel shift-left. 1104def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1105 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1106def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1107 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1108 1109def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1110 (S2_lsr_i_p_or (S2_asl_i_p $Rs, $S), $Rt, (Subi<64> $S))>; 1111def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1112 (S2_lsr_r_p_or (S2_asl_r_p $Rs, $Ru), $Rt, (A2_subri 64, $Ru))>; 1113 1114// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1115def Divu64_8: SDNodeXForm<imm, [{ 1116 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1117 SDLoc(N), MVT::i32); 1118}]>; 1119 1120// Special cases: 1121let AddedComplexity = 100 in { 1122 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1123 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1124 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1125 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1126} 1127 1128let Predicates = [HasV60], AddedComplexity = 50 in { 1129 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1130 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1131} 1132let AddedComplexity = 30 in { 1133 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1134 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1135 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1136 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1137} 1138def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1139def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1140def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1141def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1142 1143// Funnel shift-right. 1144def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1145 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1146def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1147 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1148 1149def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1150 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1151def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1152 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1153 1154// Special cases: 1155let AddedComplexity = 100 in { 1156 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1157 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1158 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1159 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1160} 1161 1162let Predicates = [HasV60], AddedComplexity = 50 in { 1163 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1164 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1165} 1166let AddedComplexity = 30 in { 1167 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1168 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1169 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1170 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1171} 1172def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1173def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1174def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1175def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1176 1177 1178def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1179 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1180def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1181 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1182 1183// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1184let AddedComplexity = 120 in 1185def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1186 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1187 1188let AddedComplexity = 100 in { 1189 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1190 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1191 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1192 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1193 1194 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1195 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1196 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1197 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1198 1199 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1200 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1201 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1202 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1203 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1204 1205 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1206 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1207 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1208 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1209 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1210 1211 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1212 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1213 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1214 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1215 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1216 1217 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1218 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1219 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1220 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1221 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1222 1223 let Predicates = [HasV60] in { 1224 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1225 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1226 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1227 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1228 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1229 1230 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1231 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1232 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1233 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1234 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1235 } 1236} 1237 1238let AddedComplexity = 100 in { 1239 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1240 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1241 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1242 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1243 1244 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1245 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1246 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1247 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1248 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1249 1250 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1251 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1252 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1253 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1254 1255 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1256 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1257 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1258 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1259 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1260 1261 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1262 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1263 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1264 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1265 1266 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1267 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1268 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1269 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1270 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1271} 1272 1273 1274class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1275 PatFrag RegPred, PatFrag ImmPred> 1276 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1277 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1278 1279let AddedComplexity = 200, Predicates = [UseCompound] in { 1280 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1281 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1282 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1283 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1284 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1285 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1286 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1287 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1288} 1289 1290// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1291// two 32-bit words into a 64-bit word. 1292let AddedComplexity = 200 in 1293def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1294 (Combinew I32:$a, I32:$b)>; 1295 1296def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1297 (Zext64 (and I32:$a, (i32 65535)))), 1298 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1299 (shl (Aext64 I32:$d), (i32 48))), 1300 (Combinew (A2_combine_ll I32:$d, I32:$c), 1301 (A2_combine_ll I32:$b, I32:$a))>; 1302 1303let AddedComplexity = 200 in { 1304 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1305 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1306 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1307 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1308 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1309 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1310 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1311 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1312} 1313 1314def SDTHexagonVShift 1315 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1316 1317def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1318def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1319def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1320 1321def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1322def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1323def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1324def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1325def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1326def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1327 1328def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1329def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1330def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1331def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1332def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1333def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1334 1335def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1336 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1337def: Pat<(srl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1338 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1339def: Pat<(shl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1340 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1341def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1342 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1343def: Pat<(srl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1344 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1345def: Pat<(shl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1346 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1347 1348def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1349 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1350def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1351 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1352def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1353 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1354def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1355 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1356def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1357 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1358def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1359 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1360 1361 1362// --(9) Arithmetic/bitwise ---------------------------------------------- 1363// 1364 1365def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1366def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1367def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1368def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1369def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1370 1371def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1372def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1373 1374def: Pat<(fabs F64:$Rs), 1375 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1376 (i32 (LoReg $Rs)))>; 1377def: Pat<(fneg F64:$Rs), 1378 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1379 (i32 (LoReg $Rs)))>; 1380 1381def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1382def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1383def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1384def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1385 1386def: OpR_RR_pat<A2_add, Add, i32, I32>; 1387def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1388def: OpR_RR_pat<A2_and, And, i32, I32>; 1389def: OpR_RR_pat<A2_or, Or, i32, I32>; 1390def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1391def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1392def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1393def: OpR_RR_pat<A2_andp, And, i64, I64>; 1394def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1395def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1396def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1397def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1398 1399def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1400def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1401 1402def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1403def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1404def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1405def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1406def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1407def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1408 1409def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1410def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1411def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1412def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1413def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1414def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1415def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1416def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1417def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1418def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1419def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1420def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1421def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1422def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1423def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1424 1425def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1426def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1427def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1428def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1429def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1430 1431// Arithmetic on predicates. 1432def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1433def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1434def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1435def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1436def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1437def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1438def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1439def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1440def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1441def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1442def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1443def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1444 1445def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1446def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1447def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1448def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1449def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1450 1451let Predicates = [HasV66] in { 1452 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1453 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1454} 1455 1456def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), 1457 (F2_dfmpyhh 1458 (F2_dfmpylh 1459 (F2_dfmpylh 1460 (F2_dfmpyll $Rs, $Rt), 1461 $Rs, $Rt), 1462 $Rt, $Rs), 1463 $Rs, $Rt)>; 1464 1465let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { 1466 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; 1467} 1468let Predicates = [HasV67] in { 1469 def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; 1470 def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; 1471 1472 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), 1473 (F2_dfmpyfix $Rt, $Rs))>; 1474} 1475 1476// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1477// over add-add with individual multiplies as inputs. 1478let AddedComplexity = 10 in { 1479 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1480 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1481 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1482 let Predicates = [HasV66] in 1483 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1484} 1485 1486def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1487def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1488def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1489 1490// Mulh for vectors 1491// 1492def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1493 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1494 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1495 1496def: Pat<(v2i32 (mulhs V2I32:$Rs, V2I32:$Rt)), 1497 (Combinew (M2_mpy_up (HiReg $Rs), (HiReg $Rt)), 1498 (M2_mpy_up (LoReg $Rt), (LoReg $Rt)))>; 1499 1500def Mulhub: 1501 OutPatFrag<(ops node:$Rss, node:$Rtt), 1502 (Combinew (S2_vtrunohb (M5_vmpybuu (HiReg $Rss), (HiReg $Rtt))), 1503 (S2_vtrunohb (M5_vmpybuu (LoReg $Rss), (LoReg $Rtt))))>; 1504 1505// Equivalent of byte-wise arithmetic shift right by 7 in v8i8. 1506def Asr7: 1507 OutPatFrag<(ops node:$Rss), (C2_mask (C2_not (A4_vcmpbgti $Rss, 0)))>; 1508 1509def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), 1510 (Mulhub $Rss, $Rtt)>; 1511 1512def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), 1513 (A2_vsubub 1514 (Mulhub $Rss, $Rtt), 1515 (A2_vaddub (A2_andp V8I8:$Rss, (Asr7 $Rtt)), 1516 (A2_andp V8I8:$Rtt, (Asr7 $Rss))))>; 1517 1518def Mpysh: 1519 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1520def Mpyshh: 1521 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (HiReg $Rss), (HiReg $Rtt))>; 1522def Mpyshl: 1523 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (LoReg $Rss), (LoReg $Rtt))>; 1524 1525def Mulhsh: 1526 OutPatFrag<(ops node:$Rss, node:$Rtt), 1527 (Combinew (A2_combine_hh (HiReg (Mpyshh $Rss, $Rtt)), 1528 (LoReg (Mpyshh $Rss, $Rtt))), 1529 (A2_combine_hh (HiReg (Mpyshl $Rss, $Rtt)), 1530 (LoReg (Mpyshl $Rss, $Rtt))))>; 1531 1532def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh $Rss, $Rtt)>; 1533 1534def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1535 (A2_vaddh 1536 (Mulhsh $Rss, $Rtt), 1537 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1538 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1539 1540 1541def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1542 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1543 1544def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1545 int64_t V = N->getSExtValue(); 1546 return -255 <= V && V <= 0; 1547}]>; 1548 1549// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1550def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1551 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1552 1553def: Pat<(add Sext64:$Rs, I64:$Rt), 1554 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1555 1556def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1557def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1558def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1559def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1560def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1561def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1562def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1563def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1564def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1565def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1566 1567// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1568// one argument matches the patterns below, and with the other argument 1569// matches S2_asl_r_r_or, etc, prefer the patterns below. 1570let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1571 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1572 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1573 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1574} 1575 1576// S4_addaddi and S4_subaddi don't have tied operands, so give them 1577// a bit of preference. 1578let AddedComplexity = 30, Predicates = [UseCompound] in { 1579 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1580 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1581 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1582 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1583 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1584 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1585 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1586 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1587 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1588 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1589} 1590 1591let Predicates = [UseCompound] in 1592def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1593 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1594 1595def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1596 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1597def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1598 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1599 1600 1601def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1602 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1603def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1604 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1605 1606def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1607 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1608def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1609 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1610def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1611 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1612 1613def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1614 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1615def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1616 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1617def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1618 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1619def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1620 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1621def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1622 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1623def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1624 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1625 1626// Add halfword. 1627def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1628 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1629def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1630 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1631def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1632 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1633 1634// Subtract halfword. 1635def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1636 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1637def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1638 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1639def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1640 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1641 1642def: Pat<(mul I64:$Rss, I64:$Rtt), 1643 (Combinew 1644 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1645 (LoReg $Rss), 1646 (HiReg $Rtt)), 1647 (LoReg $Rtt), 1648 (HiReg $Rss)), 1649 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1650 1651def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1652 (A2_addp 1653 (M2_dpmpyuu_acc_s0 1654 (S2_lsr_i_p 1655 (A2_addp 1656 (M2_dpmpyuu_acc_s0 1657 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1658 (HiReg $Rss), 1659 (LoReg $Rtt)), 1660 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1661 32), 1662 (HiReg $Rss), 1663 (HiReg $Rtt)), 1664 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1665 1666// Multiply 64-bit unsigned and use upper result. 1667def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1668 1669// Multiply 64-bit signed and use upper result. 1670// 1671// For two signed 64-bit integers A and B, let A' and B' denote A and B 1672// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1673// sign bit of A (and identically for B). With this notation, the signed 1674// product A*B can be written as: 1675// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1676// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1677// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1678// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1679 1680// Clear the sign bit in a 64-bit register. 1681def ClearSign : OutPatFrag<(ops node:$Rss), 1682 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1683 1684def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1685 (A2_subp 1686 (MulHU $Rss, $Rtt), 1687 (A2_addp 1688 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1689 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1690 1691// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1692// will put the immediate addend into a register, while these instructions will 1693// use it directly. Such a construct does not appear in the middle of a gep, 1694// where M2_macsip would be preferable. 1695let AddedComplexity = 20, Predicates = [UseCompound] in { 1696 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1697 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1698 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1699 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1700} 1701 1702// Keep these instructions less preferable to M2_macsip/M2_macsin. 1703let Predicates = [UseCompound] in { 1704 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1705 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1706 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1707 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1708 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1709 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1710} 1711 1712def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1713 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1714def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1715 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1716 1717def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1718 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1719def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1720 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1721 1722// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1723// we use the double add v8i8, and use only the low part of the result. 1724def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1725 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1726def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1727 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1728 1729// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1730// half-words, and saturates the result to a 32-bit value, except the 1731// saturation never happens (it can only occur with scaling). 1732def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1733 (LoReg (S2_vtrunewh (A2_combineii 0, 0), 1734 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1735def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1736 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1737 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1738 1739// Multiplies two v4i8 vectors. 1740def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1741 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1742 1743// Multiplies two v8i8 vectors. 1744def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1745 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1746 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1747 1748 1749// --(10) Bit ------------------------------------------------------------ 1750// 1751 1752// Count leading zeros. 1753def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 1754def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1755 1756// Count trailing zeros. 1757def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 1758def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1759 1760// Count leading ones. 1761def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 1762def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1763 1764// Count trailing ones. 1765def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 1766def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1767 1768// Define leading/trailing patterns that require zero-extensions to 64 bits. 1769def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1770def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1771def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1772def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1773 1774def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1775def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1776 1777def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1778def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1779 1780let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1781 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1782 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1783 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1784 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1785 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1786 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1787 1788 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1789 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1790 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1791 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1792 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1793 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1794} 1795 1796// Clr/set/toggle bit for 64-bit values with immediate bit index. 1797let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1798 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1799 (Combinew (i32 (HiReg $Rss)), 1800 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1801 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1802 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1803 (i32 (LoReg $Rss)))>; 1804 1805 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1806 (Combinew (i32 (HiReg $Rss)), 1807 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1808 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1809 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1810 (i32 (LoReg $Rss)))>; 1811 1812 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1813 (Combinew (i32 (HiReg $Rss)), 1814 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1815 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1816 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1817 (i32 (LoReg $Rss)))>; 1818} 1819 1820 1821let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1822 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1823 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1824 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1825 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1826 def: Pat<(i1 (trunc I32:$Rs)), 1827 (S2_tstbit_i IntRegs:$Rs, 0)>; 1828 def: Pat<(i1 (trunc I64:$Rs)), 1829 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1830} 1831 1832def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1), 1833 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>; 1834def: Pat<(and (srl I64:$Rss, IsULE<32,31>:$u6), 1), 1835 (ToZext64 (I1toI32 (S2_tstbit_i (LoReg $Rss), imm:$u6)))>; 1836def: Pat<(and (srl I64:$Rss, IsUGT<32,31>:$u6), 1), 1837 (ToZext64 (I1toI32 (S2_tstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1838 1839def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1), 1840 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>; 1841def: Pat<(and (not (srl I64:$Rss, IsULE<32,31>:$u6)), 1), 1842 (ToZext64 (I1toI32 (S4_ntstbit_i (LoReg $Rss), imm:$u6)))>; 1843def: Pat<(and (not (srl I64:$Rss, IsUGT<32,31>:$u6)), 1), 1844 (ToZext64 (I1toI32 (S4_ntstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1845 1846let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1847 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1848 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1849 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1850 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 1851} 1852 1853let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 1854def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 1855 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 1856 1857def SDTTestBit: 1858 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1859def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 1860 1861def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 1862 (S2_tstbit_i I32:$Rs, imm:$u5)>; 1863def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 1864 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1865 1866// Add extra complexity to prefer these instructions over bitsset/bitsclr. 1867// The reason is that tstbit/ntstbit can be folded into a compound instruction: 1868// if ([!]tstbit(...)) jump ... 1869let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1870 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)), 1871 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1872 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)), 1873 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1874 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1875 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 1876 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1877 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1878} 1879 1880def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)), 1881 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>; 1882def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)), 1883 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>; 1884def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)), 1885 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>; 1886def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)), 1887 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>; 1888 1889// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 1890// represented as a compare against "value & 0xFF", which is an exact match 1891// for cmpb (same for cmph). The patterns below do not contain any additional 1892// complexity that would make them preferable, and if they were actually used 1893// instead of cmpb/cmph, they would result in a compare against register that 1894// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 1895def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1896 (C4_nbitsclri I32:$Rs, imm:$u6)>; 1897def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 1898 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 1899def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 1900 (C4_nbitsset I32:$Rs, I32:$Rt)>; 1901 1902// Special patterns to address certain cases where the "top-down" matching 1903// algorithm would cause suboptimal selection. 1904 1905let AddedComplexity = 100 in { 1906 // Avoid A4_rcmp[n]eqi in these cases: 1907 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1908 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1909 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1910 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1911 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))), 1912 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1913 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))), 1914 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1915 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1916 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>; 1917 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1918 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>; 1919} 1920 1921// --(11) PIC ------------------------------------------------------------ 1922// 1923 1924def SDT_HexagonAtGot 1925 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1926def SDT_HexagonAtPcrel 1927 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 1928 1929// AT_GOT address-of-GOT, address-of-global, offset-in-global 1930def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 1931// AT_PCREL address-of-global 1932def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 1933 1934def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 1935 (L2_loadri_io I32:$got, imm:$addr)>; 1936def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 1937 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 1938def: Pat<(HexagonAtPcrel I32:$addr), 1939 (C4_addipc imm:$addr)>; 1940 1941// The HVX load patterns also match AT_PCREL directly. Make sure that 1942// if the selection of this opcode changes, it's updated in all places. 1943 1944 1945// --(12) Load ----------------------------------------------------------- 1946// 1947 1948def L1toI32: OutPatFrag<(ops node:$Rs), (A2_subri 0, (i32 $Rs))>; 1949def L1toI64: OutPatFrag<(ops node:$Rs), (ToSext64 (L1toI32 $Rs))>; 1950 1951def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1952 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1953}]>; 1954def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1955 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1956}]>; 1957 1958def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1959 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1960}]>; 1961def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1962 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1963}]>; 1964 1965def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1966 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1967}]>; 1968def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1969 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1970}]>; 1971 1972// Patterns to select load-indexed: Rs + Off. 1973// - frameindex [+ imm], 1974multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1975 InstHexagon MI> { 1976 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1977 (VT (MI AddrFI:$fi, imm:$Off))>; 1978 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1979 (VT (MI AddrFI:$fi, imm:$Off))>; 1980 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 1981} 1982 1983// Patterns to select load-indexed: Rs + Off. 1984// - base reg [+ imm] 1985multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1986 InstHexagon MI> { 1987 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 1988 (VT (MI IntRegs:$Rs, imm:$Off))>; 1989 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 1990 (VT (MI IntRegs:$Rs, imm:$Off))>; 1991 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 1992} 1993 1994// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 1995multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1996 InstHexagon MI> { 1997 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 1998 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 1999} 2000 2001// Patterns to select load reg indexed: Rs + Off with a value modifier. 2002// - frameindex [+ imm] 2003multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2004 PatLeaf ImmPred, InstHexagon MI> { 2005 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2006 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2007 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2008 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2009 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 2010} 2011 2012// Patterns to select load reg indexed: Rs + Off with a value modifier. 2013// - base reg [+ imm] 2014multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2015 PatLeaf ImmPred, InstHexagon MI> { 2016 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2017 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2018 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2019 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2020 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 2021} 2022 2023// Patterns to select load reg indexed: Rs + Off with a value modifier. 2024// Combines Loadxfim + Loadxgim. 2025multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2026 PatLeaf ImmPred, InstHexagon MI> { 2027 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 2028 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 2029} 2030 2031// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 2032class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2033 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2034 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 2035 2036// Pattern to select load reg reg-indexed: Rs + Rt<<0. 2037class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2038 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2039 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 2040 2041// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 2042class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2043 InstHexagon MI> 2044 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2045 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 2046 2047// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 2048class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2049 InstHexagon MI> 2050 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2051 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 2052 2053// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 2054// Don't match for u2==0, instead use reg+imm for those cases. 2055class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 2056 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2057 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 2058 2059class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 2060 InstHexagon MI> 2061 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2062 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 2063 2064// Pattern to select load absolute. 2065class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 2066 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 2067 2068// Pattern to select load absolute with value modifier. 2069class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 2070 InstHexagon MI> 2071 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 2072 2073 2074let AddedComplexity = 20 in { 2075 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 2076 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 2077 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 2078 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2079 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2080 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 2081 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 2082 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 2083 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbsw4_io>; 2084 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 2085 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 2086 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 2087 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2088 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2089 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 2090 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 2091 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 2092 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 2093 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 2094 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 2095 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 2096 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 2097 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 2098 // No sextloadi1. 2099 2100 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 2101 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 2102 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 2103 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 2104} 2105 2106let AddedComplexity = 30 in { 2107 // Loads of i1 are loading a byte, and the byte should be either 0 or 1. 2108 // It doesn't matter if it's sign- or zero-extended, so use zero-extension 2109 // everywhere. 2110 defm: Loadxim_pat<sextloadi1, i32, L1toI32, anyimm0, L2_loadrub_io>; 2111 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 2112 defm: Loadxim_pat<sextloadi1, i64, L1toI64, anyimm0, L2_loadrub_io>; 2113 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 2114 2115 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 2116 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 2117 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 2118 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 2119 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 2120 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 2121 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 2122 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 2123 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 2124} 2125 2126let AddedComplexity = 60 in { 2127 def: Loadxu_pat<extloadi1, i32, anyimm0, L4_loadrub_ur>; 2128 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 2129 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 2130 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2131 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2132 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 2133 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 2134 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 2135 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbsw4_ur>; 2136 def: Loadxu_pat<zextloadi1, i32, anyimm0, L4_loadrub_ur>; 2137 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 2138 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 2139 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2140 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2141 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 2142 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 2143 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 2144 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 2145 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 2146 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 2147 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 2148 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 2149 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2150 2151 def: Loadxum_pat<sextloadi1, i32, anyimm0, L1toI32, L4_loadrub_ur>; 2152 def: Loadxum_pat<extloadi1, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2153 def: Loadxum_pat<sextloadi1, i64, anyimm0, L1toI64, L4_loadrub_ur>; 2154 def: Loadxum_pat<zextloadi1, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2155 2156 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2157 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2158 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2159 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2160 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2161 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2162 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2163 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2164 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2165} 2166 2167let AddedComplexity = 40 in { 2168 def: Loadxr_shl_pat<extloadi1, i32, L4_loadrub_rr>; 2169 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2170 def: Loadxr_shl_pat<zextloadi1, i32, L4_loadrub_rr>; 2171 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2172 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2173 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2174 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2175 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2176 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2177 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2178 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2179 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2180 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2181 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2182 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2183 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2184 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2185} 2186 2187let AddedComplexity = 20 in { 2188 def: Loadxr_add_pat<extloadi1, i32, L4_loadrub_rr>; 2189 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2190 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2191 def: Loadxr_add_pat<zextloadi1, i32, L4_loadrub_rr>; 2192 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2193 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2194 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2195 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2196 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2197 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2198 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2199 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2200 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2201 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2202 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2203 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2204 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2205} 2206 2207let AddedComplexity = 40 in { 2208 def: Loadxrm_shl_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2209 def: Loadxrm_shl_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2210 def: Loadxrm_shl_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2211 def: Loadxrm_shl_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2212 2213 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2214 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2215 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2216 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2217 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2218 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2219 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2220 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2221 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2222} 2223 2224let AddedComplexity = 30 in { 2225 def: Loadxrm_add_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2226 def: Loadxrm_add_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2227 def: Loadxrm_add_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2228 def: Loadxrm_add_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2229 2230 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2231 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2232 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2233 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2234 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2235 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2236 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2237 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2238 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2239} 2240 2241// Absolute address 2242 2243let AddedComplexity = 60 in { 2244 def: Loada_pat<extloadi1, i32, anyimm0, PS_loadrubabs>; 2245 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2246 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2247 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2248 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2249 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2250 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2251 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2252 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2253 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2254 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2255 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2256 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2257 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2258 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2259 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2260 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2261 2262 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2263 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2264 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2265 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2266} 2267 2268let AddedComplexity = 30 in { 2269 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2270 def: Loadam_pat<sextloadi1, i32, anyimm0, L1toI32, PS_loadrubabs>; 2271 def: Loadam_pat<extloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2272 def: Loadam_pat<sextloadi1, i64, anyimm0, L1toI64, PS_loadrubabs>; 2273 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2274 2275 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2276 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2277 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2278 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2279 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2280 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2281 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2282 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2283 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2284} 2285 2286// GP-relative address 2287 2288let AddedComplexity = 100 in { 2289 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2290 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2291 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2292 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2293 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2294 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2295 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2296 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2297 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2298 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2299 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2300 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2301 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2302 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2303 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2304 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2305 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2306 2307 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2308 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2309 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2310 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2311} 2312 2313let AddedComplexity = 70 in { 2314 def: Loadam_pat<sextloadi1, i32, addrgp, L1toI32, L2_loadrubgp>; 2315 def: Loadam_pat<extloadi1, i64, addrgp, ToAext64, L2_loadrubgp>; 2316 def: Loadam_pat<sextloadi1, i64, addrgp, L1toI64, L2_loadrubgp>; 2317 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2318 2319 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2320 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2321 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2322 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2323 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2324 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2325 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2326 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2327 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2328 2329 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2330} 2331 2332// Patterns for loads of i1: 2333def: Pat<(i1 (load AddrFI:$fi)), 2334 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2335def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2336 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2337def: Pat<(i1 (load I32:$Rs)), 2338 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2339 2340 2341// --(13) Store ---------------------------------------------------------- 2342// 2343 2344class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2345 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2346 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2347 2348def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2349def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2350def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2351def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2352 2353// Patterns for generating stores, where the address takes different forms: 2354// - frameindex, 2355// - frameindex + offset, 2356// - base + offset, 2357// - simple (base address without offset). 2358// These would usually be used together (via Storexi_pat defined below), but 2359// in some cases one may want to apply different properties (such as 2360// AddedComplexity) to the individual patterns. 2361class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2362 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2363 2364multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2365 InstHexagon MI> { 2366 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2367 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2368 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2369 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2370} 2371 2372multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2373 InstHexagon MI> { 2374 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2375 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2376 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2377 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2378} 2379 2380class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2381 : Pat<(Store Value:$Rt, I32:$Rs), 2382 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2383 2384// Patterns for generating stores, where the address takes different forms, 2385// and where the value being stored is transformed through the value modifier 2386// ValueMod. The address forms are same as above. 2387class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2388 InstHexagon MI> 2389 : Pat<(Store Value:$Rs, AddrFI:$fi), 2390 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2391 2392multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2393 PatFrag ValueMod, InstHexagon MI> { 2394 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2395 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2396 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2397 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2398} 2399 2400multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2401 PatFrag ValueMod, InstHexagon MI> { 2402 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2403 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2404 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2405 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2406} 2407 2408class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2409 InstHexagon MI> 2410 : Pat<(Store Value:$Rt, I32:$Rs), 2411 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2412 2413multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2414 InstHexagon MI> { 2415 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2416 def: Storexi_fi_pat <Store, Value, MI>; 2417 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2418} 2419 2420multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2421 PatFrag ValueMod, InstHexagon MI> { 2422 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2423 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2424 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2425} 2426 2427// Reg<<S + Imm 2428class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2429 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2430 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2431 2432// Reg<<S + Reg 2433class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2434 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2435 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2436 2437// Reg + Reg 2438class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2439 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2440 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2441 2442class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2443 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2444 2445class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2446 InstHexagon MI> 2447 : Pat<(Store Value:$val, Addr:$addr), 2448 (MI Addr:$addr, (ValueMod Value:$val))>; 2449 2450// Regular stores in the DAG have two operands: value and address. 2451// Atomic stores also have two, but they are reversed: address, value. 2452// To use atomic stores with the patterns, they need to have their operands 2453// swapped. This relies on the knowledge that the F.Fragment uses names 2454// "ptr" and "val". 2455class AtomSt<PatFrag F> 2456 : PatFrag<(ops node:$val, node:$ptr), !head(F.Fragments), F.PredicateCode, 2457 F.OperandTransform> { 2458 let IsAtomic = F.IsAtomic; 2459 let MemoryVT = F.MemoryVT; 2460} 2461 2462 2463def IMM_BYTE : SDNodeXForm<imm, [{ 2464 // -1 can be represented as 255, etc. 2465 // assigning to a byte restores our desired signed value. 2466 int8_t imm = N->getSExtValue(); 2467 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2468}]>; 2469 2470def IMM_HALF : SDNodeXForm<imm, [{ 2471 // -1 can be represented as 65535, etc. 2472 // assigning to a short restores our desired signed value. 2473 int16_t imm = N->getSExtValue(); 2474 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2475}]>; 2476 2477def IMM_WORD : SDNodeXForm<imm, [{ 2478 // -1 can be represented as 4294967295, etc. 2479 // Currently, it's not doing this. But some optimization 2480 // might convert -1 to a large +ve number. 2481 // assigning to a word restores our desired signed value. 2482 int32_t imm = N->getSExtValue(); 2483 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2484}]>; 2485 2486def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2487def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2488def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2489 2490// Even though the offset is not extendable in the store-immediate, we 2491// can still generate the fi# in the base address. If the final offset 2492// is not valid for the instruction, we will replace it with a scratch 2493// register. 2494class SmallStackStore<PatFrag Store> 2495 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2496 return isSmallStackStore(cast<StoreSDNode>(N)); 2497}]>; 2498 2499// This is the complement of SmallStackStore. 2500class LargeStackStore<PatFrag Store> 2501 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2502 return !isSmallStackStore(cast<StoreSDNode>(N)); 2503}]>; 2504 2505// Preferred addressing modes for various combinations of stored value 2506// and address computation. 2507// For stores where the address and value are both immediates, prefer 2508// store-immediate. The reason is that the constant-extender optimization 2509// can replace store-immediate with a store-register, but there is nothing 2510// to generate a store-immediate out of a store-register. 2511// 2512// C R F F+C R+C R+R R<<S+C R<<S+R 2513// --+-------+-----+-----+------+-----+-----+--------+-------- 2514// C | imm | imm | imm | imm | imm | rr | ur | rr 2515// R | abs* | io | io | io | io | rr | ur | rr 2516// 2517// (*) Absolute or GP-relative. 2518// 2519// Note that any expression can be matched by Reg. In particular, an immediate 2520// can always be placed in a register, so patterns checking for Imm should 2521// have a higher priority than the ones involving Reg that could also match. 2522// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2523// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2524// Reg alone. 2525// 2526// The order in which the different combinations are tried: 2527// 2528// C F R F+C R+C R+R R<<S+C R<<S+R 2529// --+-------+-----+-----+------+-----+-----+--------+-------- 2530// C | 1 | 6 | - | 5 | 9 | - | - | - 2531// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2532 2533 2534// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2535// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2536// implies that Reg is also a proper multiple of 4. To still generate a 2537// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2538 2539def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2540 int64_t v = (int64_t)N->getSExtValue(); 2541 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2542}]>; 2543def RoundTo8 : SDNodeXForm<imm, [{ 2544 int32_t Imm = N->getSExtValue(); 2545 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2546}]>; 2547 2548let AddedComplexity = 150 in 2549def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2550 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2551 2552class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2553 : Pat<(Store Value:$val, anyimm:$addr), 2554 (MI (ToI32 $addr), 0, Value:$val)>; 2555class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2556 InstHexagon MI> 2557 : Pat<(Store Value:$val, anyimm:$addr), 2558 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2559 2560let AddedComplexity = 140 in { 2561 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2562 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2563 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2564 2565 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2566 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2567 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2568} 2569 2570// GP-relative address 2571let AddedComplexity = 120 in { 2572 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2573 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2574 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2575 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2576 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2577 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2578 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2579 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2580 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2581 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2582 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2583 def: Storea_pat<AtomSt<atomic_store_8>, I32, addrgp, S2_storerbgp>; 2584 def: Storea_pat<AtomSt<atomic_store_16>, I32, addrgp, S2_storerhgp>; 2585 def: Storea_pat<AtomSt<atomic_store_32>, I32, addrgp, S2_storerigp>; 2586 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, addrgp, S2_storerigp>; 2587 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, addrgp, S2_storerigp>; 2588 def: Storea_pat<AtomSt<atomic_store_64>, I64, addrgp, S2_storerdgp>; 2589 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, addrgp, S2_storerdgp>; 2590 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, addrgp, S2_storerdgp>; 2591 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, addrgp, S2_storerdgp>; 2592 2593 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2594 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2595 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2596 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2597} 2598 2599// Absolute address 2600let AddedComplexity = 110 in { 2601 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2602 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2603 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2604 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2605 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2606 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2607 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2608 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2609 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2610 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2611 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2612 def: Storea_pat<AtomSt<atomic_store_8>, I32, anyimm0, PS_storerbabs>; 2613 def: Storea_pat<AtomSt<atomic_store_16>, I32, anyimm1, PS_storerhabs>; 2614 def: Storea_pat<AtomSt<atomic_store_32>, I32, anyimm2, PS_storeriabs>; 2615 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, PS_storeriabs>; 2616 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, PS_storeriabs>; 2617 def: Storea_pat<AtomSt<atomic_store_64>, I64, anyimm3, PS_storerdabs>; 2618 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, PS_storerdabs>; 2619 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, PS_storerdabs>; 2620 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, PS_storerdabs>; 2621 2622 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2623 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2624 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2625 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2626} 2627 2628// Reg<<S + Imm 2629let AddedComplexity = 100 in { 2630 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2631 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2632 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2633 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2634 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2635 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2636 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2637 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2638 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2639 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2640 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2641 2642 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2643 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2644} 2645 2646// Reg<<S + Reg 2647let AddedComplexity = 90 in { 2648 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2649 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2650 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2651 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2652 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2653 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2654 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2655 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2656 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2657 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2658 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2659 2660 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2661 (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2662} 2663 2664class SS_<PatFrag F> : SmallStackStore<F>; 2665class LS_<PatFrag F> : LargeStackStore<F>; 2666 2667multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2668 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2669} 2670multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2671 defm: Storexi_fi_add_pat<S, V, O, I>; 2672} 2673 2674// Fi+Imm, store-immediate 2675let AddedComplexity = 80 in { 2676 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2677 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2678 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2679 2680 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2681 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2682 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2683 2684 // For large-stack stores, generate store-register (prefer explicit Fi 2685 // in the address). 2686 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2687 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2688 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2689} 2690 2691// Fi, store-immediate 2692let AddedComplexity = 70 in { 2693 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2694 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2695 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2696 2697 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2698 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2699 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2700 2701 // For large-stack stores, generate store-register (prefer explicit Fi 2702 // in the address). 2703 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2704 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2705 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2706} 2707 2708// Fi+Imm, Fi, store-register 2709let AddedComplexity = 60 in { 2710 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2711 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2712 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2713 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2714 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2715 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2716 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2717 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2718 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2719 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2720 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2721 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2722 2723 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2724 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2725 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2726 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2727 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2728 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2729 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2730 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2731 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2732 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2733 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2734 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2735} 2736 2737 2738multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2739 defm: Storexim_add_pat<S, V, O, M, I>; 2740} 2741multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2742 defm: Storexi_add_pat<S, V, O, I>; 2743} 2744 2745// Reg+Imm, store-immediate 2746let AddedComplexity = 50 in { 2747 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2748 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2749 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2750 2751 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2752 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2753 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2754} 2755 2756// Reg+Imm, store-register 2757let AddedComplexity = 40 in { 2758 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2759 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2760 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2761 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2762 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2763 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2764 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2765 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2766 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2767 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2768 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2769 2770 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2771 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2772 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2773 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2774 2775 defm: Storexi_pat<AtomSt<atomic_store_8>, I32, anyimm0, S2_storerb_io>; 2776 defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>; 2777 defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>; 2778 defm: Storexi_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, S2_storeri_io>; 2779 defm: Storexi_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, S2_storeri_io>; 2780 defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>; 2781 defm: Storexi_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, S2_storerd_io>; 2782 defm: Storexi_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, S2_storerd_io>; 2783 defm: Storexi_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, S2_storerd_io>; 2784} 2785 2786// Reg+Reg 2787let AddedComplexity = 30 in { 2788 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2789 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2790 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2791 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2792 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2793 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2794 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2795 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2796 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2797 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2798 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2799 2800 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2801 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2802} 2803 2804// Reg, store-immediate 2805let AddedComplexity = 20 in { 2806 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2807 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2808 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2809 2810 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2811 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2812 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2813} 2814 2815// Reg, store-register 2816let AddedComplexity = 10 in { 2817 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2818 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2819 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2820 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2821 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2822 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2823 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2824 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2825 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2826 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2827 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2828 2829 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2830 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2831 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2832 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2833 2834 def: Storexi_base_pat<AtomSt<atomic_store_8>, I32, S2_storerb_io>; 2835 def: Storexi_base_pat<AtomSt<atomic_store_16>, I32, S2_storerh_io>; 2836 def: Storexi_base_pat<AtomSt<atomic_store_32>, I32, S2_storeri_io>; 2837 def: Storexi_base_pat<AtomSt<atomic_store_32>, V4I8, S2_storeri_io>; 2838 def: Storexi_base_pat<AtomSt<atomic_store_32>, V2I16, S2_storeri_io>; 2839 def: Storexi_base_pat<AtomSt<atomic_store_64>, I64, S2_storerd_io>; 2840 def: Storexi_base_pat<AtomSt<atomic_store_64>, V8I8, S2_storerd_io>; 2841 def: Storexi_base_pat<AtomSt<atomic_store_64>, V4I16, S2_storerd_io>; 2842 def: Storexi_base_pat<AtomSt<atomic_store_64>, V2I32, S2_storerd_io>; 2843} 2844 2845 2846// --(14) Memop ---------------------------------------------------------- 2847// 2848 2849def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2850 int8_t V = N->getSExtValue(); 2851 return -32 < V && V <= -1; 2852}]>; 2853 2854def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2855 int16_t V = N->getSExtValue(); 2856 return -32 < V && V <= -1; 2857}]>; 2858 2859def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2860 int64_t V = N->getSExtValue(); 2861 return -31 <= V && V <= -1; 2862}]>; 2863 2864def IsNPow2_8 : PatLeaf<(i32 imm), [{ 2865 uint8_t NV = ~N->getZExtValue(); 2866 return isPowerOf2_32(NV); 2867}]>; 2868 2869def IsNPow2_16 : PatLeaf<(i32 imm), [{ 2870 uint16_t NV = ~N->getZExtValue(); 2871 return isPowerOf2_32(NV); 2872}]>; 2873 2874def Log2_8 : SDNodeXForm<imm, [{ 2875 uint8_t V = N->getZExtValue(); 2876 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2877}]>; 2878 2879def Log2_16 : SDNodeXForm<imm, [{ 2880 uint16_t V = N->getZExtValue(); 2881 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2882}]>; 2883 2884def LogN2_8 : SDNodeXForm<imm, [{ 2885 uint8_t NV = ~N->getZExtValue(); 2886 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2887}]>; 2888 2889def LogN2_16 : SDNodeXForm<imm, [{ 2890 uint16_t NV = ~N->getZExtValue(); 2891 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2892}]>; 2893 2894def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 2895 2896multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2897 InstHexagon MI> { 2898 // Addr: i32 2899 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 2900 (MI I32:$Rs, 0, I32:$A)>; 2901 // Addr: fi 2902 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 2903 (MI AddrFI:$Rs, 0, I32:$A)>; 2904} 2905 2906multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2907 SDNode Oper, InstHexagon MI> { 2908 // Addr: i32 2909 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 2910 (add I32:$Rs, ImmPred:$Off)), 2911 (MI I32:$Rs, imm:$Off, I32:$A)>; 2912 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 2913 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2914 (MI I32:$Rs, imm:$Off, I32:$A)>; 2915 // Addr: fi 2916 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2917 (add AddrFI:$Rs, ImmPred:$Off)), 2918 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2919 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2920 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2921 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2922} 2923 2924multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2925 SDNode Oper, InstHexagon MI> { 2926 let Predicates = [UseMEMOPS] in { 2927 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 2928 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 2929 } 2930} 2931 2932let AddedComplexity = 200 in { 2933 // add reg 2934 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 2935 /*anyext*/ L4_add_memopb_io>; 2936 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 2937 /*sext*/ L4_add_memopb_io>; 2938 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 2939 /*zext*/ L4_add_memopb_io>; 2940 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 2941 /*anyext*/ L4_add_memoph_io>; 2942 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 2943 /*sext*/ L4_add_memoph_io>; 2944 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 2945 /*zext*/ L4_add_memoph_io>; 2946 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 2947 2948 // sub reg 2949 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 2950 /*anyext*/ L4_sub_memopb_io>; 2951 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 2952 /*sext*/ L4_sub_memopb_io>; 2953 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 2954 /*zext*/ L4_sub_memopb_io>; 2955 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 2956 /*anyext*/ L4_sub_memoph_io>; 2957 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 2958 /*sext*/ L4_sub_memoph_io>; 2959 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 2960 /*zext*/ L4_sub_memoph_io>; 2961 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 2962 2963 // and reg 2964 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 2965 /*anyext*/ L4_and_memopb_io>; 2966 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 2967 /*sext*/ L4_and_memopb_io>; 2968 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 2969 /*zext*/ L4_and_memopb_io>; 2970 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 2971 /*anyext*/ L4_and_memoph_io>; 2972 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 2973 /*sext*/ L4_and_memoph_io>; 2974 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 2975 /*zext*/ L4_and_memoph_io>; 2976 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 2977 2978 // or reg 2979 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 2980 /*anyext*/ L4_or_memopb_io>; 2981 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 2982 /*sext*/ L4_or_memopb_io>; 2983 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 2984 /*zext*/ L4_or_memopb_io>; 2985 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 2986 /*anyext*/ L4_or_memoph_io>; 2987 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 2988 /*sext*/ L4_or_memoph_io>; 2989 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 2990 /*zext*/ L4_or_memoph_io>; 2991 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 2992} 2993 2994 2995multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2996 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 2997 // Addr: i32 2998 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 2999 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 3000 // Addr: fi 3001 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 3002 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 3003} 3004 3005multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3006 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3007 InstHexagon MI> { 3008 // Addr: i32 3009 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 3010 (add I32:$Rs, ImmPred:$Off)), 3011 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3012 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 3013 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3014 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3015 // Addr: fi 3016 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3017 (add AddrFI:$Rs, ImmPred:$Off)), 3018 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3019 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3020 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3021 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3022} 3023 3024multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3025 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3026 InstHexagon MI> { 3027 let Predicates = [UseMEMOPS] in { 3028 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 3029 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 3030 } 3031} 3032 3033let AddedComplexity = 220 in { 3034 // add imm 3035 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3036 /*anyext*/ IdImm, L4_iadd_memopb_io>; 3037 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3038 /*sext*/ IdImm, L4_iadd_memopb_io>; 3039 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3040 /*zext*/ IdImm, L4_iadd_memopb_io>; 3041 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3042 /*anyext*/ IdImm, L4_iadd_memoph_io>; 3043 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3044 /*sext*/ IdImm, L4_iadd_memoph_io>; 3045 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3046 /*zext*/ IdImm, L4_iadd_memoph_io>; 3047 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 3048 L4_iadd_memopw_io>; 3049 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3050 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 3051 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3052 /*sext*/ NegImm8, L4_iadd_memopb_io>; 3053 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3054 /*zext*/ NegImm8, L4_iadd_memopb_io>; 3055 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3056 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 3057 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3058 /*sext*/ NegImm16, L4_iadd_memoph_io>; 3059 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3060 /*zext*/ NegImm16, L4_iadd_memoph_io>; 3061 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 3062 L4_iadd_memopw_io>; 3063 3064 // sub imm 3065 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3066 /*anyext*/ IdImm, L4_isub_memopb_io>; 3067 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3068 /*sext*/ IdImm, L4_isub_memopb_io>; 3069 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3070 /*zext*/ IdImm, L4_isub_memopb_io>; 3071 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3072 /*anyext*/ IdImm, L4_isub_memoph_io>; 3073 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3074 /*sext*/ IdImm, L4_isub_memoph_io>; 3075 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3076 /*zext*/ IdImm, L4_isub_memoph_io>; 3077 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 3078 L4_isub_memopw_io>; 3079 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3080 /*anyext*/ NegImm8, L4_isub_memopb_io>; 3081 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3082 /*sext*/ NegImm8, L4_isub_memopb_io>; 3083 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3084 /*zext*/ NegImm8, L4_isub_memopb_io>; 3085 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3086 /*anyext*/ NegImm16, L4_isub_memoph_io>; 3087 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3088 /*sext*/ NegImm16, L4_isub_memoph_io>; 3089 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3090 /*zext*/ NegImm16, L4_isub_memoph_io>; 3091 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 3092 L4_isub_memopw_io>; 3093 3094 // clrbit imm 3095 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3096 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 3097 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3098 /*sext*/ LogN2_8, L4_iand_memopb_io>; 3099 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3100 /*zext*/ LogN2_8, L4_iand_memopb_io>; 3101 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3102 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 3103 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3104 /*sext*/ LogN2_16, L4_iand_memoph_io>; 3105 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3106 /*zext*/ LogN2_16, L4_iand_memoph_io>; 3107 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 3108 LogN2_32, L4_iand_memopw_io>; 3109 3110 // setbit imm 3111 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3112 /*anyext*/ Log2_8, L4_ior_memopb_io>; 3113 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3114 /*sext*/ Log2_8, L4_ior_memopb_io>; 3115 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3116 /*zext*/ Log2_8, L4_ior_memopb_io>; 3117 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3118 /*anyext*/ Log2_16, L4_ior_memoph_io>; 3119 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3120 /*sext*/ Log2_16, L4_ior_memoph_io>; 3121 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3122 /*zext*/ Log2_16, L4_ior_memoph_io>; 3123 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 3124 Log2_32, L4_ior_memopw_io>; 3125} 3126 3127 3128// --(15) Call ----------------------------------------------------------- 3129// 3130 3131// Pseudo instructions. 3132def SDT_SPCallSeqStart 3133 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3134def SDT_SPCallSeqEnd 3135 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3136 3137def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 3138 [SDNPHasChain, SDNPOutGlue]>; 3139def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 3140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 3141 3142def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3143 3144def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 3145 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3146def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 3147 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3148def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 3149 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3150 3151def: Pat<(callseq_start timm:$amt, timm:$amt2), 3152 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 3153def: Pat<(callseq_end timm:$amt1, timm:$amt2), 3154 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 3155 3156def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 3157def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 3158def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 3159 3160def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 3161def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 3162def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 3163def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 3164 3165def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 3166def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 3167def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 3168 3169def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 3170 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3171def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3172 3173def: Pat<(retflag), (PS_jmpret (i32 R31))>; 3174def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3175 3176 3177// --(16) Branch --------------------------------------------------------- 3178// 3179 3180def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3181def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3182 3183def: Pat<(brcond I1:$Pu, bb:$dst), 3184 (J2_jumpt I1:$Pu, bb:$dst)>; 3185def: Pat<(brcond (not I1:$Pu), bb:$dst), 3186 (J2_jumpf I1:$Pu, bb:$dst)>; 3187def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3188 (J2_jumpf I1:$Pu, bb:$dst)>; 3189def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3190 (J2_jumpf I1:$Pu, bb:$dst)>; 3191def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3192 (J2_jumpt I1:$Pu, bb:$dst)>; 3193 3194 3195// --(17) Misc ----------------------------------------------------------- 3196 3197 3198// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3199// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3200// The isdigit transformation relies on two 'clever' aspects: 3201// 1) The data type is unsigned which allows us to eliminate a zero test after 3202// biasing the expression by 48. We are depending on the representation of 3203// the unsigned types, and semantics. 3204// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3205// 3206// For the C code: 3207// retval = (c >= '0' && c <= '9') ? 1 : 0; 3208// The code is transformed upstream of llvm into 3209// retval = (c-48) < 10 ? 1 : 0; 3210 3211def u7_0PosImmPred : ImmLeaf<i32, [{ 3212 // True if the immediate fits in an 7-bit unsigned field and is positive. 3213 return Imm > 0 && isUInt<7>(Imm); 3214}]>; 3215 3216let AddedComplexity = 139 in 3217def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3218 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3219 3220let AddedComplexity = 100 in 3221def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3222 (i32 (extloadi8 (add I32:$b, 3))), 3223 24, 8), 3224 (i32 16)), 3225 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3226 (zextloadi8 I32:$b)), 3227 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3228 3229 3230// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3231// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3232// We don't really want either one here. 3233def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3234def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3235 [SDNPHasChain]>; 3236 3237def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3238 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3239def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3240 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3241 3242def SDTHexagonALLOCA 3243 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3244def HexagonALLOCA 3245 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3246 3247def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3248 (PS_alloca IntRegs:$Rs, imm:$A)>; 3249 3250def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3251def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3252 3253def: Pat<(trap), (PS_crash)>; 3254 3255// Read cycle counter. 3256def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3257def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3258 [SDNPHasChain]>; 3259 3260def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3261 3262// The declared return value of the store-locked intrinsics is i32, but 3263// the instructions actually define i1. To avoid register copies from 3264// IntRegs to PredRegs and back, fold the entire pattern checking the 3265// result against true/false. 3266let AddedComplexity = 100 in { 3267 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3268 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3269 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3270 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3271 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3272 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3273 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3274 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3275} 3276