1//===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def HQ8: PatLeaf<(VecQ8 HvxQR:$R)>; 91def HQ16: PatLeaf<(VecQ16 HvxQR:$R)>; 92def HQ32: PatLeaf<(VecQ32 HvxQR:$R)>; 93 94def HVI8: PatLeaf<(VecI8 HvxVR:$R)>; 95def HVI16: PatLeaf<(VecI16 HvxVR:$R)>; 96def HVI32: PatLeaf<(VecI32 HvxVR:$R)>; 97 98def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>; 99def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>; 100def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>; 101 102def SDTVecLeaf: 103 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 104def SDTVecVecIntOp: 105 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 106 SDTCisVT<3,i32>]>; 107 108def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>; 109def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>; 110def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 111def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 112 113def ptrue: PatFrag<(ops), (HexagonPTRUE)>; 114def pfalse: PatFrag<(ops), (HexagonPFALSE)>; 115def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>; 116 117def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 118 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 119def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 120 121// Pattern fragments to extract the low and high subregisters from a 122// 64-bit value. 123def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>; 124def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>; 125 126def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 127 return isOrEquivalentToAdd(N); 128}]>; 129 130def IsPow2_32: PatLeaf<(i32 imm), [{ 131 uint32_t V = N->getZExtValue(); 132 return isPowerOf2_32(V); 133}]>; 134 135def IsPow2_64: PatLeaf<(i64 imm), [{ 136 uint64_t V = N->getZExtValue(); 137 return isPowerOf2_64(V); 138}]>; 139 140def IsNPow2_32: PatLeaf<(i32 imm), [{ 141 uint32_t NV = ~N->getZExtValue(); 142 return isPowerOf2_32(NV); 143}]>; 144 145def IsPow2_64L: PatLeaf<(i64 imm), [{ 146 uint64_t V = N->getZExtValue(); 147 return isPowerOf2_64(V) && Log2_64(V) < 32; 148}]>; 149 150def IsPow2_64H: PatLeaf<(i64 imm), [{ 151 uint64_t V = N->getZExtValue(); 152 return isPowerOf2_64(V) && Log2_64(V) >= 32; 153}]>; 154 155def IsNPow2_64L: PatLeaf<(i64 imm), [{ 156 uint64_t NV = ~N->getZExtValue(); 157 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 158}]>; 159 160def IsNPow2_64H: PatLeaf<(i64 imm), [{ 161 uint64_t NV = ~N->getZExtValue(); 162 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 163}]>; 164 165class IsULE<int Width, int Arg>: PatLeaf<(i32 imm), 166 "uint64_t V = N->getZExtValue();" # 167 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";" 168>; 169 170class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 171 "uint64_t V = N->getZExtValue();" # 172 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 173>; 174 175def SDEC1: SDNodeXForm<imm, [{ 176 int32_t V = N->getSExtValue(); 177 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 178}]>; 179 180def UDEC1: SDNodeXForm<imm, [{ 181 uint32_t V = N->getZExtValue(); 182 assert(V >= 1); 183 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 184}]>; 185 186def UDEC32: SDNodeXForm<imm, [{ 187 uint32_t V = N->getZExtValue(); 188 assert(V >= 32); 189 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 190}]>; 191 192class Subi<int From>: SDNodeXForm<imm, 193 "int32_t V = " # From # " - N->getSExtValue();" # 194 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 195>; 196 197def Log2_32: SDNodeXForm<imm, [{ 198 uint32_t V = N->getZExtValue(); 199 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 200}]>; 201 202def Log2_64: SDNodeXForm<imm, [{ 203 uint64_t V = N->getZExtValue(); 204 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 205}]>; 206 207def LogN2_32: SDNodeXForm<imm, [{ 208 uint32_t NV = ~N->getZExtValue(); 209 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 210}]>; 211 212def LogN2_64: SDNodeXForm<imm, [{ 213 uint64_t NV = ~N->getZExtValue(); 214 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 215}]>; 216 217def NegImm8: SDNodeXForm<imm, [{ 218 int8_t NV = -N->getSExtValue(); 219 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 220}]>; 221 222def NegImm16: SDNodeXForm<imm, [{ 223 int16_t NV = -N->getSExtValue(); 224 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 225}]>; 226 227def NegImm32: SDNodeXForm<imm, [{ 228 int32_t NV = -N->getSExtValue(); 229 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 230}]>; 231 232def SplatB: SDNodeXForm<imm, [{ 233 uint32_t V = N->getZExtValue(); 234 assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF); 235 V &= 0xFF; 236 uint32_t S = V << 24 | V << 16 | V << 8 | V; 237 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32); 238}]>; 239 240def SplatH: SDNodeXForm<imm, [{ 241 uint32_t V = N->getZExtValue(); 242 assert(isUInt<16>(V) || V >> 16 == 0xFFFF); 243 V &= 0xFFFF; 244 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32); 245}]>; 246 247 248// Helpers for type promotions/contractions. 249def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 250def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 251def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 252def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 253def ToAext64: OutPatFrag<(ops node:$Rs), 254 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 255 256def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 257 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 258 259def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 260def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 261def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 262def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 263 264// Global address or an aligned constant. 265def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 266def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 267def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 268def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 269 270def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 271def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 272 273// This complex pattern is really only to detect various forms of 274// sign-extension i32->i64. The selected value will be of type i64 275// whose low word is the value being extended. The high word is 276// unspecified. 277def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 278 279def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 280def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 281def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 282 283def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 284def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 285 286def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 287 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 288 289 290// Converters from unary/binary SDNode to PatFrag. 291class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 292class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 293 294class Not2<PatFrag P> 295 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 296class VNot2<PatFrag P, PatFrag Not> 297 : PatFrag<(ops node:$A, node:$B), (P node:$A, (Not node:$B))>; 298 299// If there is a constant operand that feeds the and/or instruction, 300// do not generate the compound instructions. 301// It is not always profitable, as some times we end up with a transfer. 302// Check the below example. 303// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 304// Instead this is preferable. 305// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 306class Su_ni1<PatFrag Op> 307 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 308 if (hasOneUse(N)){ 309 // Check if Op1 is an immediate operand. 310 SDValue Op1 = N->getOperand(1); 311 return !isa<ConstantSDNode>(Op1); 312 } 313 return false;}], 314 Op.OperandTransform>; 315 316class Su<PatFrag Op> 317 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 318 Op.OperandTransform>; 319 320// Main selection macros. 321 322class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 323 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 324 325class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 326 PatFrag RegPred, PatFrag ImmPred> 327 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 328 (MI RegPred:$Rs, imm:$I)>; 329 330class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 331 PatFrag RsPred, PatFrag RtPred = RsPred> 332 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 333 (MI RsPred:$Rs, RtPred:$Rt)>; 334 335class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 336 PatFrag RegPred, PatFrag ImmPred> 337 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 338 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 339 340class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 341 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 344 345multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 346 InstHexagon InstA, InstHexagon InstB> { 347 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 348 (InstA Val:$A, Val:$B)>; 349 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 350 (InstB Val:$A, Val:$B)>; 351} 352 353multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, 354 SDPatternOperator Sel, SDPatternOperator CmpOp, 355 ValueType CmpType, PatFrag CmpPred> { 356 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 357 CmpPred:$Vt, CmpPred:$Vs), 358 (PickT CmpPred:$Vs, CmpPred:$Vt)>; 359 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 360 CmpPred:$Vs, CmpPred:$Vt), 361 (PickS CmpPred:$Vs, CmpPred:$Vt)>; 362} 363 364// Bitcasts between same-size vector types are no-ops, except for the 365// actual type change. 366multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> { 367 def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>; 368 def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; 369} 370 371// Frags for commonly used SDNodes. 372def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 373def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 374def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 375 376def Smin: pf2<smin>; def Smax: pf2<smax>; 377def Umin: pf2<umin>; def Umax: pf2<umax>; 378 379def Rol: pf2<rotl>; 380 381// --(1) Immediate ------------------------------------------------------- 382// 383 384def Imm64Lo: SDNodeXForm<imm, [{ 385 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()), 386 SDLoc(N), MVT::i32); 387}]>; 388def Imm64Hi: SDNodeXForm<imm, [{ 389 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32), 390 SDLoc(N), MVT::i32); 391}]>; 392 393 394def SDTHexagonCONST32 395 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 396 397def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 398def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 399def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 400def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 401 402def TruncI64ToI32: SDNodeXForm<imm, [{ 403 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 404}]>; 405 406def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 407def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 408 409def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 410def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 411def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 412def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 413def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 414def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 415def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 416// The HVX load patterns also match CP directly. Make sure that if 417// the selection of this opcode changes, it's updated in all places. 418 419def: Pat<(i1 0), (PS_false)>; 420def: Pat<(i1 1), (PS_true)>; 421def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, 422 Requires<[UseSmallData,NotOptTinyCore]>; 423def: Pat<(i64 imm:$v), 424 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; 425 426def ftoi : SDNodeXForm<fpimm, [{ 427 APInt I = N->getValueAPF().bitcastToAPInt(); 428 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 429 MVT::getIntegerVT(I.getBitWidth())); 430}]>; 431 432def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 433def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 434 435def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 436 437// --(2) Type cast ------------------------------------------------------- 438// 439 440def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 441def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 442 443def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 444def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 445def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 446def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 447 448def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 449def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 450def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 451def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 452 453def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 454def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 455def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 456def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 457 458def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 459def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 460def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 461def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 462 463// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 464def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 465def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 466def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 467def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 468 469// Bit convert 32- and 64-bit types. 470// All of these are bitcastable to one another: i32, v2i16, v4i8. 471defm: NopCast_pat<i32, v2i16, IntRegs>; 472defm: NopCast_pat<i32, v4i8, IntRegs>; 473defm: NopCast_pat<v2i16, v4i8, IntRegs>; 474// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 475defm: NopCast_pat<i64, v2i32, DoubleRegs>; 476defm: NopCast_pat<i64, v4i16, DoubleRegs>; 477defm: NopCast_pat<i64, v8i8, DoubleRegs>; 478defm: NopCast_pat<v2i32, v4i16, DoubleRegs>; 479defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 480defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 481 482 483// --(3) Extend/truncate ------------------------------------------------- 484// 485 486def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 487def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 488def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 489def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 490def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 491 492def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 493def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 494def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 495 496def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 497def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 498def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 499 500let AddedComplexity = 20 in { 501 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 502 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 503} 504 505// Extensions from i1 or vectors of i1. 506def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 507def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 508def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 509def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 510 (C2_muxii PredRegs:$Pu, -1, 0))>; 511 512def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 513def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 514def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 515def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 516def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 517 518def Vsplatpi: OutPatFrag<(ops node:$V), 519 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 520 521def: Pat<(v2i16 (azext V2I1:$Pu)), 522 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 523def: Pat<(v2i32 (azext V2I1:$Pu)), 524 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 525def: Pat<(v4i8 (azext V4I1:$Pu)), 526 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 527def: Pat<(v4i16 (azext V4I1:$Pu)), 528 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 529def: Pat<(v8i8 (azext V8I1:$Pu)), 530 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 531 532def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 533def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 534def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 535def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 536 537def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 538 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 539 540def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 541 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 542 543// Truncate: from vector B copy all 'E'ven 'B'yte elements: 544// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 545def: Pat<(v4i8 (trunc V4I16:$Rs)), 546 (S2_vtrunehb V4I16:$Rs)>; 547 548// Truncate: from vector B copy all 'O'dd 'B'yte elements: 549// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 550// S2_vtrunohb 551 552// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 553// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 554// S2_vtruneh 555 556def: Pat<(v2i16 (trunc V2I32:$Rs)), 557 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 558 559 560// --(4) Logical --------------------------------------------------------- 561// 562 563def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 564def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>; 565def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>; 566def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>; 567def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 568 569def: OpR_RR_pat<C2_and, And, i1, I1>; 570def: OpR_RR_pat<C2_or, Or, i1, I1>; 571def: OpR_RR_pat<C2_xor, Xor, i1, I1>; 572def: OpR_RR_pat<C2_andn, Not2<And>, i1, I1>; 573def: OpR_RR_pat<C2_orn, Not2<Or>, i1, I1>; 574 575def: AccRRR_pat<C4_and_and, And, Su<And>, I1, I1, I1>; 576def: AccRRR_pat<C4_and_or, And, Su< Or>, I1, I1, I1>; 577def: AccRRR_pat<C4_or_and, Or, Su<And>, I1, I1, I1>; 578def: AccRRR_pat<C4_or_or, Or, Su< Or>, I1, I1, I1>; 579def: AccRRR_pat<C4_and_andn, And, Su<Not2<And>>, I1, I1, I1>; 580def: AccRRR_pat<C4_and_orn, And, Su<Not2< Or>>, I1, I1, I1>; 581def: AccRRR_pat<C4_or_andn, Or, Su<Not2<And>>, I1, I1, I1>; 582def: AccRRR_pat<C4_or_orn, Or, Su<Not2< Or>>, I1, I1, I1>; 583 584multiclass BoolvOpR_RR_pat<InstHexagon MI, PatFrag VOp> { 585 def: OpR_RR_pat<MI, VOp, v2i1, V2I1>; 586 def: OpR_RR_pat<MI, VOp, v4i1, V4I1>; 587 def: OpR_RR_pat<MI, VOp, v8i1, V8I1>; 588} 589 590multiclass BoolvAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag VOp> { 591 def: AccRRR_pat<MI, AccOp, VOp, V2I1, V2I1, V2I1>; 592 def: AccRRR_pat<MI, AccOp, VOp, V4I1, V4I1, V4I1>; 593 def: AccRRR_pat<MI, AccOp, VOp, V8I1, V8I1, V8I1>; 594} 595 596defm: BoolvOpR_RR_pat<C2_and, And>; 597defm: BoolvOpR_RR_pat<C2_or, Or>; 598defm: BoolvOpR_RR_pat<C2_xor, Xor>; 599defm: BoolvOpR_RR_pat<C2_andn, VNot2<And, pnot>>; 600defm: BoolvOpR_RR_pat<C2_orn, VNot2< Or, pnot>>; 601 602// op(Ps, op(Pt, Pu)) 603defm: BoolvAccRRR_pat<C4_and_and, And, Su<And>>; 604defm: BoolvAccRRR_pat<C4_and_or, And, Su<Or>>; 605defm: BoolvAccRRR_pat<C4_or_and, Or, Su<And>>; 606defm: BoolvAccRRR_pat<C4_or_or, Or, Su<Or>>; 607 608// op(Ps, op(Pt, !Pu)) 609defm: BoolvAccRRR_pat<C4_and_andn, And, Su<VNot2<And, pnot>>>; 610defm: BoolvAccRRR_pat<C4_and_orn, And, Su<VNot2< Or, pnot>>>; 611defm: BoolvAccRRR_pat<C4_or_andn, Or, Su<VNot2<And, pnot>>>; 612defm: BoolvAccRRR_pat<C4_or_orn, Or, Su<VNot2< Or, pnot>>>; 613 614 615// --(5) Compare --------------------------------------------------------- 616// 617 618// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 619// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 620 621def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 622def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 623def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 624 625def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 626 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 627def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 628 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 629 630def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 631 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 632def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 633 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 634 635// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 636// that reverse the order of the operands. 637class RevCmp<PatFrag F> 638 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 639 F.OperandTransform>; 640 641def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 642def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 643def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 644def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 645def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 646def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 647def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 648def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 649def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 650def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 651def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 652def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 653def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 654def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 655def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 656def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 657def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 658def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 659def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 660def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 661def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 662def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 663def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 664def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 665def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 666def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 667def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 668def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 669def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 670def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 671def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 672def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 673def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 674def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 675def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 676def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 677def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 678def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 679def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 680def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 681 682def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 683def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 684def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 685def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 686def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 687def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 688def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 689def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 690def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 691def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 692def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 693 694def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 695def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 696def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 697def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 698def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 699def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 700def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 701def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 702def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 703def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 704def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 705 706// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 707 708def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 709 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 710def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 711 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 712def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 713 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 714 715class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 716 PatFrag RsPred, PatFrag RtPred = RsPred> 717 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 718 (Output RsPred:$Rs, RtPred:$Rt)>; 719 720class Outn<InstHexagon MI> 721 : OutPatFrag<(ops node:$Rs, node:$Rt), 722 (C2_not (MI $Rs, $Rt))>; 723 724def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 725def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 726def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 727def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 728def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 729def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 730def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 731def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 732def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 733def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 734def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 735def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 736def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 737def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 738def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 739def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 740def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 741def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 742def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 743def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 744def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 745def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 746def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 747def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 748def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 749 750let AddedComplexity = 100 in { 751 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 752 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 753 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 754 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 755 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 756 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 757 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 758 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 759} 760 761// PatFrag for AsserZext which takes the original type as a parameter. 762def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 763def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 764class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 765 766multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 767 PatLeaf ImmPred, int Mask> { 768 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 769 (MI I32:$Rs, imm:$I)>; 770 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 771 (MI I32:$Rs, imm:$I)>; 772} 773 774multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 775 PatLeaf ImmPred, int Mask> { 776 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 777 (C2_not (MI I32:$Rs, imm:$I))>; 778 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 779 (C2_not (MI I32:$Rs, imm:$I))>; 780} 781 782multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 783 PatLeaf ImmPred, int Mask> { 784 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 785 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 786 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 787 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 788} 789 790let AddedComplexity = 200 in { 791 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 792 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 793 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 794 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 795 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 796 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 797 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 798 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 799} 800 801def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 802 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 803def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 804 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 805def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 806 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 807def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 808 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 809 810def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 811def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 812def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>; 813def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 814 815// Floating-point comparisons with checks for ordered/unordered status. 816 817class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 818 : OutPatFrag<(ops node:$Rs, node:$Rt), 819 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 820 821class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 822class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 823 824class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 825class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 826 827def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 828def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 829def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 830def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 831def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 832def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 833 834def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 835def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 836def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 837def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 838def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 839def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 840 841def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 842def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 843 844def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 845def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 846 847def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 848def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 849 850 851// --(6) Select ---------------------------------------------------------- 852// 853 854def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 855 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 856def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 857 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 858def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 859 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 860def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 861 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 862 863def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 864 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 865def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 866 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 867def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 868 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 869def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 870 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 871 872// Map from a 64-bit select to an emulated 64-bit mux. 873// Hexagon does not support 64-bit MUXes; so emulate with combines. 874def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 875 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 876 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 877 878def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 879 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 880def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 881 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 882def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 883 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 884def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 885 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 886 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 887 888def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 889 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 890def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 891 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 892 893def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 894 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 895def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 896 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 897 898def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 899 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 900def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 901 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 902def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 903 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 904 905def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt), 906 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>; 907def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt), 908 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>; 909def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt), 910 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>; 911 912 913// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 914def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw), 915 (C2_or (C2_and I1:$Pu, I1:$Pv), 916 (C2_andn I1:$Pw, I1:$Pu))>; 917 918 919def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 920 return isPositiveHalfWord(N); 921}]>; 922 923multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 924 InstHexagon InstB> { 925 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 926 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 927 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 928 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 929 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 930 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 931} 932 933let AddedComplexity = 200 in { 934 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 935 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 936 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 937 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 938 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 939 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 940 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 941 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 942} 943 944def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>; 945def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>; 946def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>; 947def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>; 948def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>; 949def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>; 950def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>; 951def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>; 952 953let AddedComplexity = 100 in { 954 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>; 955 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>; 956 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>; 957 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; 958} 959 960let AddedComplexity = 100, Predicates = [HasV67] in { 961 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; 962 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; 963 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; 964 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; 965} 966 967def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>; 968def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>; 969def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>; 970def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>; 971 972def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>; 973def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>; 974def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>; 975def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>; 976 977def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>; 978def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>; 979def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>; 980def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>; 981 982// --(7) Insert/extract -------------------------------------------------- 983// 984 985def SDTHexagonINSERT: 986 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 987 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 988def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 989 990let AddedComplexity = 10 in { 991 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 992 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 993 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 994 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 995} 996def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 997 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 998def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 999 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 1000 1001def SDTHexagonEXTRACTU 1002 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 1003 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 1004def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 1005 1006let AddedComplexity = 10 in { 1007 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 1008 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 1009 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 1010 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 1011} 1012def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 1013 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 1014def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 1015 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 1016 1017def: Pat<(v4i8 (splat_vector anyint:$V)), (ToI32 (SplatB $V))>; 1018def: Pat<(v2i16 (splat_vector anyint:$V)), (ToI32 (SplatH $V))>; 1019def: Pat<(v8i8 (splat_vector anyint:$V)), 1020 (Combinew (ToI32 (SplatB $V)), (ToI32 (SplatB $V)))>; 1021def: Pat<(v4i16 (splat_vector anyint:$V)), 1022 (Combinew (ToI32 (SplatH $V)), (ToI32 (SplatH $V)))>; 1023let AddedComplexity = 10 in 1024def: Pat<(v2i32 (splat_vector s8_0ImmPred:$s8)), 1025 (A2_combineii imm:$s8, imm:$s8)>; 1026def: Pat<(v2i32 (splat_vector anyimm:$V)), (Combinew (ToI32 $V), (ToI32 $V))>; 1027 1028def: Pat<(v4i8 (splat_vector I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 1029def: Pat<(v2i16 (splat_vector I32:$Rs)), (LoReg (S2_vsplatrh I32:$Rs))>; 1030def: Pat<(v4i16 (splat_vector I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 1031def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 1032 1033let AddedComplexity = 10 in 1034def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 1035 Requires<[HasV62]>; 1036def: Pat<(v8i8 (splat_vector I32:$Rs)), 1037 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 1038 1039 1040// --(8) Shift/permute --------------------------------------------------- 1041// 1042 1043def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 1044 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 1045 1046def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 1047 1048def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 1049 1050// The complexity of the combines involving immediates should be greater 1051// than the complexity of the combine with two registers. 1052let AddedComplexity = 50 in { 1053 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 1054 (A4_combineri IntRegs:$Rs, imm:$s8)>; 1055 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 1056 (A4_combineir imm:$s8, IntRegs:$Rs)>; 1057} 1058 1059// The complexity of the combine with two immediates should be greater than 1060// the complexity of a combine involving a register. 1061let AddedComplexity = 75 in { 1062 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 1063 (A4_combineii imm:$s8, imm:$u6)>; 1064 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 1065 (A2_combineii imm:$s8, imm:$S8)>; 1066} 1067 1068def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 1069def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 1070 (A2_swiz (HiReg $Rss)))>; 1071 1072def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 1073def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 1074def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1075 1076def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 1077def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1078def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 1079def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 1080def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1081def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 1082def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 1083def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1084def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 1085def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 1086def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1087def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 1088 1089def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 1090def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1091def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 1092def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 1093def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1094def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1095 1096// Funnel shifts. 1097def IsMul8_U3: PatLeaf<(i32 imm), [{ 1098 uint64_t V = N->getZExtValue(); 1099 return V % 8 == 0 && isUInt<3>(V / 8); 1100}]>; 1101 1102def Divu8: SDNodeXForm<imm, [{ 1103 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1104}]>; 1105 1106// Funnel shift-left. 1107def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1108 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1109def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1110 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1111 1112def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1113 (S2_lsr_i_p_or (S2_asl_i_p $Rs, $S), $Rt, (Subi<64> $S))>; 1114def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1115 (S2_lsr_r_p_or (S2_asl_r_p $Rs, $Ru), $Rt, (A2_subri 64, $Ru))>; 1116 1117// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1118def Divu64_8: SDNodeXForm<imm, [{ 1119 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1120 SDLoc(N), MVT::i32); 1121}]>; 1122 1123// Special cases: 1124let AddedComplexity = 100 in { 1125 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1126 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1127 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1128 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1129} 1130 1131let Predicates = [HasV60], AddedComplexity = 50 in { 1132 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1133 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1134} 1135let AddedComplexity = 30 in { 1136 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1137 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1138 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1139 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1140} 1141def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1142def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1143def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1144def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1145 1146// Funnel shift-right. 1147def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1148 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1149def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1150 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1151 1152def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1153 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1154def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1155 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1156 1157// Special cases: 1158let AddedComplexity = 100 in { 1159 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1160 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1161 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1162 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1163} 1164 1165let Predicates = [HasV60], AddedComplexity = 50 in { 1166 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1167 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1168} 1169let AddedComplexity = 30 in { 1170 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1171 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1172 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1173 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1174} 1175def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1176def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1177def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1178def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1179 1180 1181def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1182 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1183def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1184 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1185 1186// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1187let AddedComplexity = 120 in 1188def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1189 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1190 1191let AddedComplexity = 100 in { 1192 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1193 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1194 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1195 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1196 1197 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1198 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1199 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1200 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1201 1202 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1203 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1204 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1205 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1206 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1207 1208 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1209 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1210 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1211 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1212 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1213 1214 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1215 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1216 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1217 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1218 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1219 1220 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1221 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1222 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1223 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1224 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1225 1226 let Predicates = [HasV60] in { 1227 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1228 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1229 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1230 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1231 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1232 1233 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1234 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1235 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1236 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1237 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1238 } 1239} 1240 1241let AddedComplexity = 100 in { 1242 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1243 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1244 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1245 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1246 1247 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1248 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1249 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1250 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1251 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1252 1253 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1254 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1255 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1256 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1257 1258 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1259 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1260 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1261 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1262 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1263 1264 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1265 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1266 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1267 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1268 1269 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1270 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1271 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1272 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1273 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1274} 1275 1276 1277class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1278 PatFrag RegPred, PatFrag ImmPred> 1279 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1280 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1281 1282let AddedComplexity = 200, Predicates = [UseCompound] in { 1283 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1284 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1285 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1286 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1287 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1288 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1289 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1290 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1291} 1292 1293// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1294// two 32-bit words into a 64-bit word. 1295let AddedComplexity = 200 in 1296def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1297 (Combinew I32:$a, I32:$b)>; 1298 1299def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1300 (Zext64 (and I32:$a, (i32 65535)))), 1301 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1302 (shl (Aext64 I32:$d), (i32 48))), 1303 (Combinew (A2_combine_ll I32:$d, I32:$c), 1304 (A2_combine_ll I32:$b, I32:$a))>; 1305 1306let AddedComplexity = 200 in { 1307 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1308 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1309 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1310 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1311 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1312 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1313 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1314 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1315} 1316 1317def SDTHexagonVShift 1318 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1319 1320def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1321def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1322def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1323 1324def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1325def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1326def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1327def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1328def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1329def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1330 1331def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1332def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1333def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1334def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1335def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1336def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1337 1338def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1339 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1340def: Pat<(srl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1341 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1342def: Pat<(shl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1343 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1344def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1345 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1346def: Pat<(srl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1347 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1348def: Pat<(shl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1349 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1350 1351def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1352 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1353def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1354 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1355def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1356 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1357def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1358 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1359def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1360 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1361def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1362 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1363 1364 1365// --(9) Arithmetic/bitwise ---------------------------------------------- 1366// 1367 1368def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1369def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1370def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1371def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1372def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1373 1374def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1375def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1376 1377def: Pat<(fabs F64:$Rs), 1378 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1379 (i32 (LoReg $Rs)))>; 1380def: Pat<(fneg F64:$Rs), 1381 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1382 (i32 (LoReg $Rs)))>; 1383 1384def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1385def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1386def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1387def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1388 1389def: OpR_RR_pat<A2_add, Add, i32, I32>; 1390def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1391def: OpR_RR_pat<A2_and, And, i32, I32>; 1392def: OpR_RR_pat<A2_or, Or, i32, I32>; 1393def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1394def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1395def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1396def: OpR_RR_pat<A2_andp, And, i64, I64>; 1397def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1398def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1399def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1400def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1401 1402def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1403def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1404 1405def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1406def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1407def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1408def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1409def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1410def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1411 1412def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1413def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1414def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1415def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1416def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1417def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1418def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1419def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1420def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1421def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1422def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1423def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1424def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1425def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1426def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1427 1428def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1429def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1430def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1431def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1432def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1433 1434// Arithmetic on predicates. 1435def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1436def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1437def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1438def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1439def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1440def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1441def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1442def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1443def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1444def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1445def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1446def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1447 1448def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1449def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1450def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1451def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1452def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1453 1454let Predicates = [HasV66] in { 1455 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1456 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1457} 1458 1459def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), 1460 (F2_dfmpyhh 1461 (F2_dfmpylh 1462 (F2_dfmpylh 1463 (F2_dfmpyll $Rs, $Rt), 1464 $Rs, $Rt), 1465 $Rt, $Rs), 1466 $Rs, $Rt)>; 1467 1468let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { 1469 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; 1470} 1471let Predicates = [HasV67] in { 1472 def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; 1473 def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; 1474 1475 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), 1476 (F2_dfmpyfix $Rt, $Rs))>; 1477} 1478 1479// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1480// over add-add with individual multiplies as inputs. 1481let AddedComplexity = 10 in { 1482 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1483 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1484 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1485 let Predicates = [HasV66] in 1486 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1487} 1488 1489def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1490def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1491def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1492 1493// Mulh for vectors 1494// 1495def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1496 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1497 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1498 1499def: Pat<(v2i32 (mulhs V2I32:$Rs, V2I32:$Rt)), 1500 (Combinew (M2_mpy_up (HiReg $Rs), (HiReg $Rt)), 1501 (M2_mpy_up (LoReg $Rt), (LoReg $Rt)))>; 1502 1503def Mulhub: 1504 OutPatFrag<(ops node:$Rss, node:$Rtt), 1505 (Combinew (S2_vtrunohb (M5_vmpybuu (HiReg $Rss), (HiReg $Rtt))), 1506 (S2_vtrunohb (M5_vmpybuu (LoReg $Rss), (LoReg $Rtt))))>; 1507 1508// Equivalent of byte-wise arithmetic shift right by 7 in v8i8. 1509def Asr7: 1510 OutPatFrag<(ops node:$Rss), (C2_mask (C2_not (A4_vcmpbgti $Rss, 0)))>; 1511 1512def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), 1513 (Mulhub $Rss, $Rtt)>; 1514 1515def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), 1516 (A2_vsubub 1517 (Mulhub $Rss, $Rtt), 1518 (A2_vaddub (A2_andp V8I8:$Rss, (Asr7 $Rtt)), 1519 (A2_andp V8I8:$Rtt, (Asr7 $Rss))))>; 1520 1521def Mpysh: 1522 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1523def Mpyshh: 1524 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (HiReg $Rss), (HiReg $Rtt))>; 1525def Mpyshl: 1526 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (LoReg $Rss), (LoReg $Rtt))>; 1527 1528def Mulhsh: 1529 OutPatFrag<(ops node:$Rss, node:$Rtt), 1530 (Combinew (A2_combine_hh (HiReg (Mpyshh $Rss, $Rtt)), 1531 (LoReg (Mpyshh $Rss, $Rtt))), 1532 (A2_combine_hh (HiReg (Mpyshl $Rss, $Rtt)), 1533 (LoReg (Mpyshl $Rss, $Rtt))))>; 1534 1535def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh $Rss, $Rtt)>; 1536 1537def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1538 (A2_vaddh 1539 (Mulhsh $Rss, $Rtt), 1540 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1541 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1542 1543 1544def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1545 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1546 1547def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1548 int64_t V = N->getSExtValue(); 1549 return -255 <= V && V <= 0; 1550}]>; 1551 1552// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1553def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1554 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1555 1556def: Pat<(add Sext64:$Rs, I64:$Rt), 1557 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1558 1559def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1560def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1561def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1562def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1563def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1564def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1565def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1566def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1567def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1568def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1569 1570// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1571// one argument matches the patterns below, and with the other argument 1572// matches S2_asl_r_r_or, etc, prefer the patterns below. 1573let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1574 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1575 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1576 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1577} 1578 1579// S4_addaddi and S4_subaddi don't have tied operands, so give them 1580// a bit of preference. 1581let AddedComplexity = 30, Predicates = [UseCompound] in { 1582 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1583 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1584 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1585 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1586 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1587 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1588 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1589 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1590 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1591 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1592} 1593 1594let Predicates = [UseCompound] in 1595def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1596 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1597 1598def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1599 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1600def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1601 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1602 1603 1604def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1605 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1606def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1607 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1608 1609def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1610 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1611def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1612 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1613def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1614 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1615 1616def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1617 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1618def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1619 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1620def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1621 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1622def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1623 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1624def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1625 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1626def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1627 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1628 1629// Add halfword. 1630def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1631 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1632def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1633 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1634def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1635 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1636 1637// Subtract halfword. 1638def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1639 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1640def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1641 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1642def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1643 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1644 1645def: Pat<(mul I64:$Rss, I64:$Rtt), 1646 (Combinew 1647 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1648 (LoReg $Rss), 1649 (HiReg $Rtt)), 1650 (LoReg $Rtt), 1651 (HiReg $Rss)), 1652 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1653 1654def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1655 (A2_addp 1656 (M2_dpmpyuu_acc_s0 1657 (S2_lsr_i_p 1658 (A2_addp 1659 (M2_dpmpyuu_acc_s0 1660 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1661 (HiReg $Rss), 1662 (LoReg $Rtt)), 1663 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1664 32), 1665 (HiReg $Rss), 1666 (HiReg $Rtt)), 1667 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1668 1669// Multiply 64-bit unsigned and use upper result. 1670def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1671 1672// Multiply 64-bit signed and use upper result. 1673// 1674// For two signed 64-bit integers A and B, let A' and B' denote A and B 1675// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1676// sign bit of A (and identically for B). With this notation, the signed 1677// product A*B can be written as: 1678// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1679// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1680// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1681// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1682 1683// Clear the sign bit in a 64-bit register. 1684def ClearSign : OutPatFrag<(ops node:$Rss), 1685 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1686 1687def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1688 (A2_subp 1689 (MulHU $Rss, $Rtt), 1690 (A2_addp 1691 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1692 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1693 1694// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1695// will put the immediate addend into a register, while these instructions will 1696// use it directly. Such a construct does not appear in the middle of a gep, 1697// where M2_macsip would be preferable. 1698let AddedComplexity = 20, Predicates = [UseCompound] in { 1699 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1700 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1701 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1702 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1703} 1704 1705// Keep these instructions less preferable to M2_macsip/M2_macsin. 1706let Predicates = [UseCompound] in { 1707 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1708 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1709 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1710 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1711 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1712 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1713} 1714 1715def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1716 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1717def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1718 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1719 1720def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1721 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1722def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1723 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1724 1725// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1726// we use the double add v8i8, and use only the low part of the result. 1727def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1728 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1729def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1730 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1731 1732// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1733// half-words, and saturates the result to a 32-bit value, except the 1734// saturation never happens (it can only occur with scaling). 1735def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1736 (LoReg (S2_vtrunewh (A2_combineii 0, 0), 1737 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1738def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1739 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1740 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1741 1742// Multiplies two v4i8 vectors. 1743def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1744 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1745 1746// Multiplies two v8i8 vectors. 1747def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1748 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1749 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1750 1751 1752// --(10) Bit ------------------------------------------------------------ 1753// 1754 1755// Count leading zeros. 1756def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 1757def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1758 1759// Count trailing zeros. 1760def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 1761def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1762 1763// Count leading ones. 1764def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 1765def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1766 1767// Count trailing ones. 1768def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 1769def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1770 1771// Define leading/trailing patterns that require zero-extensions to 64 bits. 1772def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1773def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1774def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1775def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1776 1777def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1778def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1779 1780def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1781def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1782 1783let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1784 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1785 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1786 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1787 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1788 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1789 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1790 1791 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1792 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1793 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1794 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1795 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1796 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1797} 1798 1799// Clr/set/toggle bit for 64-bit values with immediate bit index. 1800let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1801 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1802 (Combinew (i32 (HiReg $Rss)), 1803 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1804 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1805 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1806 (i32 (LoReg $Rss)))>; 1807 1808 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1809 (Combinew (i32 (HiReg $Rss)), 1810 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1811 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1812 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1813 (i32 (LoReg $Rss)))>; 1814 1815 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1816 (Combinew (i32 (HiReg $Rss)), 1817 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1818 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1819 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1820 (i32 (LoReg $Rss)))>; 1821} 1822 1823 1824let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1825 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1826 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1827 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1828 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1829 def: Pat<(i1 (trunc I32:$Rs)), 1830 (S2_tstbit_i IntRegs:$Rs, 0)>; 1831 def: Pat<(i1 (trunc I64:$Rs)), 1832 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1833} 1834 1835def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1), 1836 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>; 1837def: Pat<(and (srl I64:$Rss, IsULE<32,31>:$u6), 1), 1838 (ToZext64 (I1toI32 (S2_tstbit_i (LoReg $Rss), imm:$u6)))>; 1839def: Pat<(and (srl I64:$Rss, IsUGT<32,31>:$u6), 1), 1840 (ToZext64 (I1toI32 (S2_tstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1841 1842def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1), 1843 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>; 1844def: Pat<(and (not (srl I64:$Rss, IsULE<32,31>:$u6)), 1), 1845 (ToZext64 (I1toI32 (S4_ntstbit_i (LoReg $Rss), imm:$u6)))>; 1846def: Pat<(and (not (srl I64:$Rss, IsUGT<32,31>:$u6)), 1), 1847 (ToZext64 (I1toI32 (S4_ntstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1848 1849let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1850 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1851 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1852 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1853 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 1854} 1855 1856let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 1857def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 1858 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 1859 1860def SDTTestBit: 1861 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1862def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 1863 1864def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 1865 (S2_tstbit_i I32:$Rs, imm:$u5)>; 1866def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 1867 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1868 1869// Add extra complexity to prefer these instructions over bitsset/bitsclr. 1870// The reason is that tstbit/ntstbit can be folded into a compound instruction: 1871// if ([!]tstbit(...)) jump ... 1872let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1873 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)), 1874 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1875 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)), 1876 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1877 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1878 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 1879 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1880 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1881} 1882 1883def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)), 1884 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>; 1885def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)), 1886 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>; 1887def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)), 1888 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>; 1889def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)), 1890 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>; 1891 1892// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 1893// represented as a compare against "value & 0xFF", which is an exact match 1894// for cmpb (same for cmph). The patterns below do not contain any additional 1895// complexity that would make them preferable, and if they were actually used 1896// instead of cmpb/cmph, they would result in a compare against register that 1897// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 1898def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1899 (C4_nbitsclri I32:$Rs, imm:$u6)>; 1900def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 1901 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 1902def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 1903 (C4_nbitsset I32:$Rs, I32:$Rt)>; 1904 1905// Special patterns to address certain cases where the "top-down" matching 1906// algorithm would cause suboptimal selection. 1907 1908let AddedComplexity = 100 in { 1909 // Avoid A4_rcmp[n]eqi in these cases: 1910 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1911 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1912 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1913 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 1914 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))), 1915 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1916 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))), 1917 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 1918 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1919 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>; 1920 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 1921 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>; 1922} 1923 1924// --(11) PIC ------------------------------------------------------------ 1925// 1926 1927def SDT_HexagonAtGot 1928 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1929def SDT_HexagonAtPcrel 1930 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 1931 1932// AT_GOT address-of-GOT, address-of-global, offset-in-global 1933def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 1934// AT_PCREL address-of-global 1935def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 1936 1937def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 1938 (L2_loadri_io I32:$got, imm:$addr)>; 1939def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 1940 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 1941def: Pat<(HexagonAtPcrel I32:$addr), 1942 (C4_addipc imm:$addr)>; 1943 1944// The HVX load patterns also match AT_PCREL directly. Make sure that 1945// if the selection of this opcode changes, it's updated in all places. 1946 1947 1948// --(12) Load ----------------------------------------------------------- 1949// 1950 1951def L1toI32: OutPatFrag<(ops node:$Rs), (A2_subri 0, (i32 $Rs))>; 1952def L1toI64: OutPatFrag<(ops node:$Rs), (ToSext64 (L1toI32 $Rs))>; 1953 1954def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1955 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1956}]>; 1957def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 1958 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1959}]>; 1960 1961def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1962 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1963}]>; 1964def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 1965 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1966}]>; 1967 1968def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1969 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 1970}]>; 1971def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 1972 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 1973}]>; 1974 1975// Patterns to select load-indexed: Rs + Off. 1976// - frameindex [+ imm], 1977multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1978 InstHexagon MI> { 1979 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1980 (VT (MI AddrFI:$fi, imm:$Off))>; 1981 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 1982 (VT (MI AddrFI:$fi, imm:$Off))>; 1983 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 1984} 1985 1986// Patterns to select load-indexed: Rs + Off. 1987// - base reg [+ imm] 1988multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1989 InstHexagon MI> { 1990 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 1991 (VT (MI IntRegs:$Rs, imm:$Off))>; 1992 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 1993 (VT (MI IntRegs:$Rs, imm:$Off))>; 1994 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 1995} 1996 1997// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 1998multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1999 InstHexagon MI> { 2000 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 2001 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 2002} 2003 2004// Patterns to select load reg indexed: Rs + Off with a value modifier. 2005// - frameindex [+ imm] 2006multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2007 PatLeaf ImmPred, InstHexagon MI> { 2008 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2009 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2010 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2011 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2012 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 2013} 2014 2015// Patterns to select load reg indexed: Rs + Off with a value modifier. 2016// - base reg [+ imm] 2017multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2018 PatLeaf ImmPred, InstHexagon MI> { 2019 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2020 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2021 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2022 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2023 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 2024} 2025 2026// Patterns to select load reg indexed: Rs + Off with a value modifier. 2027// Combines Loadxfim + Loadxgim. 2028multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2029 PatLeaf ImmPred, InstHexagon MI> { 2030 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 2031 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 2032} 2033 2034// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 2035class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2036 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2037 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 2038 2039// Pattern to select load reg reg-indexed: Rs + Rt<<0. 2040class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2041 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2042 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 2043 2044// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 2045class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2046 InstHexagon MI> 2047 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2048 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 2049 2050// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 2051class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2052 InstHexagon MI> 2053 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2054 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 2055 2056// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 2057// Don't match for u2==0, instead use reg+imm for those cases. 2058class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 2059 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2060 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 2061 2062class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 2063 InstHexagon MI> 2064 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2065 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 2066 2067// Pattern to select load absolute. 2068class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 2069 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 2070 2071// Pattern to select load absolute with value modifier. 2072class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 2073 InstHexagon MI> 2074 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 2075 2076 2077let AddedComplexity = 20 in { 2078 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 2079 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 2080 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 2081 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2082 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2083 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 2084 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 2085 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 2086 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2087 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 2088 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 2089 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 2090 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2091 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2092 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 2093 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 2094 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 2095 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 2096 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 2097 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 2098 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 2099 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 2100 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 2101 // No sextloadi1. 2102 2103 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 2104 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 2105 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 2106 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 2107} 2108 2109let AddedComplexity = 30 in { 2110 // Loads of i1 are loading a byte, and the byte should be either 0 or 1. 2111 // It doesn't matter if it's sign- or zero-extended, so use zero-extension 2112 // everywhere. 2113 defm: Loadxim_pat<sextloadi1, i32, L1toI32, anyimm0, L2_loadrub_io>; 2114 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 2115 defm: Loadxim_pat<sextloadi1, i64, L1toI64, anyimm0, L2_loadrub_io>; 2116 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 2117 2118 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 2119 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 2120 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 2121 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 2122 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 2123 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 2124 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 2125 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 2126 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 2127} 2128 2129let AddedComplexity = 60 in { 2130 def: Loadxu_pat<extloadi1, i32, anyimm0, L4_loadrub_ur>; 2131 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 2132 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 2133 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2134 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2135 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 2136 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 2137 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 2138 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2139 def: Loadxu_pat<zextloadi1, i32, anyimm0, L4_loadrub_ur>; 2140 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 2141 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 2142 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2143 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2144 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 2145 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 2146 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 2147 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 2148 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 2149 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 2150 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 2151 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 2152 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2153 2154 def: Loadxum_pat<sextloadi1, i32, anyimm0, L1toI32, L4_loadrub_ur>; 2155 def: Loadxum_pat<extloadi1, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2156 def: Loadxum_pat<sextloadi1, i64, anyimm0, L1toI64, L4_loadrub_ur>; 2157 def: Loadxum_pat<zextloadi1, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2158 2159 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2160 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2161 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2162 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2163 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2164 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2165 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2166 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2167 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2168} 2169 2170let AddedComplexity = 40 in { 2171 def: Loadxr_shl_pat<extloadi1, i32, L4_loadrub_rr>; 2172 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2173 def: Loadxr_shl_pat<zextloadi1, i32, L4_loadrub_rr>; 2174 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2175 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2176 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2177 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2178 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2179 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2180 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2181 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2182 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2183 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2184 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2185 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2186 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2187 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2188} 2189 2190let AddedComplexity = 20 in { 2191 def: Loadxr_add_pat<extloadi1, i32, L4_loadrub_rr>; 2192 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2193 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2194 def: Loadxr_add_pat<zextloadi1, i32, L4_loadrub_rr>; 2195 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2196 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2197 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2198 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2199 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2200 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2201 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2202 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2203 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2204 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2205 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2206 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2207 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2208} 2209 2210let AddedComplexity = 40 in { 2211 def: Loadxrm_shl_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2212 def: Loadxrm_shl_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2213 def: Loadxrm_shl_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2214 def: Loadxrm_shl_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2215 2216 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2217 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2218 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2219 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2220 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2221 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2222 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2223 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2224 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2225} 2226 2227let AddedComplexity = 30 in { 2228 def: Loadxrm_add_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2229 def: Loadxrm_add_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2230 def: Loadxrm_add_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2231 def: Loadxrm_add_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2232 2233 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2234 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2235 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2236 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2237 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2238 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2239 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2240 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2241 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2242} 2243 2244// Absolute address 2245 2246let AddedComplexity = 60 in { 2247 def: Loada_pat<extloadi1, i32, anyimm0, PS_loadrubabs>; 2248 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2249 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2250 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2251 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2252 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2253 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2254 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2255 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2256 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2257 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2258 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2259 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2260 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2261 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2262 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2263 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2264 2265 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2266 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2267 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2268 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2269} 2270 2271let AddedComplexity = 30 in { 2272 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2273 def: Loadam_pat<sextloadi1, i32, anyimm0, L1toI32, PS_loadrubabs>; 2274 def: Loadam_pat<extloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2275 def: Loadam_pat<sextloadi1, i64, anyimm0, L1toI64, PS_loadrubabs>; 2276 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2277 2278 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2279 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2280 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2281 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2282 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2283 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2284 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2285 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2286 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2287} 2288 2289// GP-relative address 2290 2291let AddedComplexity = 100 in { 2292 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2293 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2294 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2295 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2296 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2297 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2298 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2299 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2300 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2301 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2302 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2303 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2304 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2305 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2306 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2307 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2308 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2309 2310 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2311 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2312 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2313 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2314} 2315 2316let AddedComplexity = 70 in { 2317 def: Loadam_pat<sextloadi1, i32, addrgp, L1toI32, L2_loadrubgp>; 2318 def: Loadam_pat<extloadi1, i64, addrgp, ToAext64, L2_loadrubgp>; 2319 def: Loadam_pat<sextloadi1, i64, addrgp, L1toI64, L2_loadrubgp>; 2320 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2321 2322 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2323 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2324 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2325 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2326 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2327 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2328 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2329 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2330 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2331 2332 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2333} 2334 2335// Patterns for loads of i1: 2336def: Pat<(i1 (load AddrFI:$fi)), 2337 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2338def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2339 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2340def: Pat<(i1 (load I32:$Rs)), 2341 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2342 2343 2344// --(13) Store ---------------------------------------------------------- 2345// 2346 2347class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2348 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2349 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2350 2351def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2352def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2353def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2354def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2355 2356// Patterns for generating stores, where the address takes different forms: 2357// - frameindex, 2358// - frameindex + offset, 2359// - base + offset, 2360// - simple (base address without offset). 2361// These would usually be used together (via Storexi_pat defined below), but 2362// in some cases one may want to apply different properties (such as 2363// AddedComplexity) to the individual patterns. 2364class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2365 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2366 2367multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2368 InstHexagon MI> { 2369 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2370 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2371 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2372 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2373} 2374 2375multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2376 InstHexagon MI> { 2377 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2378 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2379 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2380 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2381} 2382 2383class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2384 : Pat<(Store Value:$Rt, I32:$Rs), 2385 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2386 2387// Patterns for generating stores, where the address takes different forms, 2388// and where the value being stored is transformed through the value modifier 2389// ValueMod. The address forms are same as above. 2390class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2391 InstHexagon MI> 2392 : Pat<(Store Value:$Rs, AddrFI:$fi), 2393 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2394 2395multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2396 PatFrag ValueMod, InstHexagon MI> { 2397 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2398 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2399 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2400 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2401} 2402 2403multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2404 PatFrag ValueMod, InstHexagon MI> { 2405 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2406 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2407 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2408 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2409} 2410 2411class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2412 InstHexagon MI> 2413 : Pat<(Store Value:$Rt, I32:$Rs), 2414 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2415 2416multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2417 InstHexagon MI> { 2418 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2419 def: Storexi_fi_pat <Store, Value, MI>; 2420 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2421} 2422 2423multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2424 PatFrag ValueMod, InstHexagon MI> { 2425 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2426 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2427 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2428} 2429 2430// Reg<<S + Imm 2431class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2432 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2433 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2434 2435// Reg<<S + Reg 2436class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2437 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2438 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2439 2440// Reg + Reg 2441class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2442 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2443 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2444 2445class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2446 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2447 2448class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2449 InstHexagon MI> 2450 : Pat<(Store Value:$val, Addr:$addr), 2451 (MI Addr:$addr, (ValueMod Value:$val))>; 2452 2453// Regular stores in the DAG have two operands: value and address. 2454// Atomic stores also have two, but they are reversed: address, value. 2455// To use atomic stores with the patterns, they need to have their operands 2456// swapped. This relies on the knowledge that the F.Fragment uses names 2457// "ptr" and "val". 2458class AtomSt<PatFrag F> 2459 : PatFrag<(ops node:$val, node:$ptr), !head(F.Fragments), F.PredicateCode, 2460 F.OperandTransform> { 2461 let IsAtomic = F.IsAtomic; 2462 let MemoryVT = F.MemoryVT; 2463} 2464 2465 2466def IMM_BYTE : SDNodeXForm<imm, [{ 2467 // -1 can be represented as 255, etc. 2468 // assigning to a byte restores our desired signed value. 2469 int8_t imm = N->getSExtValue(); 2470 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2471}]>; 2472 2473def IMM_HALF : SDNodeXForm<imm, [{ 2474 // -1 can be represented as 65535, etc. 2475 // assigning to a short restores our desired signed value. 2476 int16_t imm = N->getSExtValue(); 2477 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2478}]>; 2479 2480def IMM_WORD : SDNodeXForm<imm, [{ 2481 // -1 can be represented as 4294967295, etc. 2482 // Currently, it's not doing this. But some optimization 2483 // might convert -1 to a large +ve number. 2484 // assigning to a word restores our desired signed value. 2485 int32_t imm = N->getSExtValue(); 2486 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2487}]>; 2488 2489def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2490def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2491def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2492 2493// Even though the offset is not extendable in the store-immediate, we 2494// can still generate the fi# in the base address. If the final offset 2495// is not valid for the instruction, we will replace it with a scratch 2496// register. 2497class SmallStackStore<PatFrag Store> 2498 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2499 return isSmallStackStore(cast<StoreSDNode>(N)); 2500}]>; 2501 2502// This is the complement of SmallStackStore. 2503class LargeStackStore<PatFrag Store> 2504 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2505 return !isSmallStackStore(cast<StoreSDNode>(N)); 2506}]>; 2507 2508// Preferred addressing modes for various combinations of stored value 2509// and address computation. 2510// For stores where the address and value are both immediates, prefer 2511// store-immediate. The reason is that the constant-extender optimization 2512// can replace store-immediate with a store-register, but there is nothing 2513// to generate a store-immediate out of a store-register. 2514// 2515// C R F F+C R+C R+R R<<S+C R<<S+R 2516// --+-------+-----+-----+------+-----+-----+--------+-------- 2517// C | imm | imm | imm | imm | imm | rr | ur | rr 2518// R | abs* | io | io | io | io | rr | ur | rr 2519// 2520// (*) Absolute or GP-relative. 2521// 2522// Note that any expression can be matched by Reg. In particular, an immediate 2523// can always be placed in a register, so patterns checking for Imm should 2524// have a higher priority than the ones involving Reg that could also match. 2525// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2526// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2527// Reg alone. 2528// 2529// The order in which the different combinations are tried: 2530// 2531// C F R F+C R+C R+R R<<S+C R<<S+R 2532// --+-------+-----+-----+------+-----+-----+--------+-------- 2533// C | 1 | 6 | - | 5 | 9 | - | - | - 2534// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2535 2536 2537// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2538// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2539// implies that Reg is also a proper multiple of 4. To still generate a 2540// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2541 2542def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2543 int64_t v = (int64_t)N->getSExtValue(); 2544 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2545}]>; 2546def RoundTo8 : SDNodeXForm<imm, [{ 2547 int32_t Imm = N->getSExtValue(); 2548 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2549}]>; 2550 2551let AddedComplexity = 150 in 2552def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2553 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2554 2555class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2556 : Pat<(Store Value:$val, anyimm:$addr), 2557 (MI (ToI32 $addr), 0, Value:$val)>; 2558class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2559 InstHexagon MI> 2560 : Pat<(Store Value:$val, anyimm:$addr), 2561 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2562 2563let AddedComplexity = 140 in { 2564 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2565 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2566 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2567 2568 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2569 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2570 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2571} 2572 2573// GP-relative address 2574let AddedComplexity = 120 in { 2575 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2576 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2577 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2578 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2579 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2580 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2581 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2582 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2583 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2584 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2585 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2586 def: Storea_pat<AtomSt<atomic_store_8>, I32, addrgp, S2_storerbgp>; 2587 def: Storea_pat<AtomSt<atomic_store_16>, I32, addrgp, S2_storerhgp>; 2588 def: Storea_pat<AtomSt<atomic_store_32>, I32, addrgp, S2_storerigp>; 2589 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, addrgp, S2_storerigp>; 2590 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, addrgp, S2_storerigp>; 2591 def: Storea_pat<AtomSt<atomic_store_64>, I64, addrgp, S2_storerdgp>; 2592 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, addrgp, S2_storerdgp>; 2593 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, addrgp, S2_storerdgp>; 2594 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, addrgp, S2_storerdgp>; 2595 2596 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2597 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2598 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2599 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2600} 2601 2602// Absolute address 2603let AddedComplexity = 110 in { 2604 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2605 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2606 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2607 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2608 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2609 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2610 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2611 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2612 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2613 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2614 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2615 def: Storea_pat<AtomSt<atomic_store_8>, I32, anyimm0, PS_storerbabs>; 2616 def: Storea_pat<AtomSt<atomic_store_16>, I32, anyimm1, PS_storerhabs>; 2617 def: Storea_pat<AtomSt<atomic_store_32>, I32, anyimm2, PS_storeriabs>; 2618 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, PS_storeriabs>; 2619 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, PS_storeriabs>; 2620 def: Storea_pat<AtomSt<atomic_store_64>, I64, anyimm3, PS_storerdabs>; 2621 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, PS_storerdabs>; 2622 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, PS_storerdabs>; 2623 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, PS_storerdabs>; 2624 2625 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2626 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2627 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2628 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2629} 2630 2631// Reg<<S + Imm 2632let AddedComplexity = 100 in { 2633 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2634 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2635 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2636 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2637 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2638 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2639 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2640 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2641 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2642 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2643 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2644 2645 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2646 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2647} 2648 2649// Reg<<S + Reg 2650let AddedComplexity = 90 in { 2651 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2652 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2653 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2654 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2655 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2656 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2657 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2658 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2659 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2660 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2661 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2662 2663 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2664 (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2665} 2666 2667class SS_<PatFrag F> : SmallStackStore<F>; 2668class LS_<PatFrag F> : LargeStackStore<F>; 2669 2670multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2671 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2672} 2673multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2674 defm: Storexi_fi_add_pat<S, V, O, I>; 2675} 2676 2677// Fi+Imm, store-immediate 2678let AddedComplexity = 80 in { 2679 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2680 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2681 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2682 2683 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2684 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2685 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2686 2687 // For large-stack stores, generate store-register (prefer explicit Fi 2688 // in the address). 2689 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2690 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2691 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2692} 2693 2694// Fi, store-immediate 2695let AddedComplexity = 70 in { 2696 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2697 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2698 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2699 2700 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2701 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2702 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2703 2704 // For large-stack stores, generate store-register (prefer explicit Fi 2705 // in the address). 2706 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2707 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2708 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2709} 2710 2711// Fi+Imm, Fi, store-register 2712let AddedComplexity = 60 in { 2713 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2714 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2715 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2716 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2717 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2718 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2719 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2720 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2721 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2722 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2723 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2724 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2725 2726 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2727 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2728 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2729 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2730 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2731 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2732 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2733 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2734 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2735 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2736 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2737 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2738} 2739 2740 2741multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2742 defm: Storexim_add_pat<S, V, O, M, I>; 2743} 2744multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2745 defm: Storexi_add_pat<S, V, O, I>; 2746} 2747 2748// Reg+Imm, store-immediate 2749let AddedComplexity = 50 in { 2750 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2751 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2752 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2753 2754 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2755 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2756 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2757} 2758 2759// Reg+Imm, store-register 2760let AddedComplexity = 40 in { 2761 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2762 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2763 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2764 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2765 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2766 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2767 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2768 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2769 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2770 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2771 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2772 2773 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2774 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2775 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2776 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2777 2778 defm: Storexi_pat<AtomSt<atomic_store_8>, I32, anyimm0, S2_storerb_io>; 2779 defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>; 2780 defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>; 2781 defm: Storexi_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, S2_storeri_io>; 2782 defm: Storexi_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, S2_storeri_io>; 2783 defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>; 2784 defm: Storexi_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, S2_storerd_io>; 2785 defm: Storexi_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, S2_storerd_io>; 2786 defm: Storexi_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, S2_storerd_io>; 2787} 2788 2789// Reg+Reg 2790let AddedComplexity = 30 in { 2791 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2792 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2793 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2794 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2795 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2796 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2797 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2798 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2799 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2800 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2801 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2802 2803 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2804 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2805} 2806 2807// Reg, store-immediate 2808let AddedComplexity = 20 in { 2809 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2810 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2811 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2812 2813 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2814 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2815 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2816} 2817 2818// Reg, store-register 2819let AddedComplexity = 10 in { 2820 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2821 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2822 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2823 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2824 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2825 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2826 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2827 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2828 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2829 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2830 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2831 2832 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2833 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2834 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2835 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2836 2837 def: Storexi_base_pat<AtomSt<atomic_store_8>, I32, S2_storerb_io>; 2838 def: Storexi_base_pat<AtomSt<atomic_store_16>, I32, S2_storerh_io>; 2839 def: Storexi_base_pat<AtomSt<atomic_store_32>, I32, S2_storeri_io>; 2840 def: Storexi_base_pat<AtomSt<atomic_store_32>, V4I8, S2_storeri_io>; 2841 def: Storexi_base_pat<AtomSt<atomic_store_32>, V2I16, S2_storeri_io>; 2842 def: Storexi_base_pat<AtomSt<atomic_store_64>, I64, S2_storerd_io>; 2843 def: Storexi_base_pat<AtomSt<atomic_store_64>, V8I8, S2_storerd_io>; 2844 def: Storexi_base_pat<AtomSt<atomic_store_64>, V4I16, S2_storerd_io>; 2845 def: Storexi_base_pat<AtomSt<atomic_store_64>, V2I32, S2_storerd_io>; 2846} 2847 2848 2849// --(14) Memop ---------------------------------------------------------- 2850// 2851 2852def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2853 int8_t V = N->getSExtValue(); 2854 return -32 < V && V <= -1; 2855}]>; 2856 2857def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2858 int16_t V = N->getSExtValue(); 2859 return -32 < V && V <= -1; 2860}]>; 2861 2862def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2863 int64_t V = N->getSExtValue(); 2864 return -31 <= V && V <= -1; 2865}]>; 2866 2867def IsNPow2_8 : PatLeaf<(i32 imm), [{ 2868 uint8_t NV = ~N->getZExtValue(); 2869 return isPowerOf2_32(NV); 2870}]>; 2871 2872def IsNPow2_16 : PatLeaf<(i32 imm), [{ 2873 uint16_t NV = ~N->getZExtValue(); 2874 return isPowerOf2_32(NV); 2875}]>; 2876 2877def Log2_8 : SDNodeXForm<imm, [{ 2878 uint8_t V = N->getZExtValue(); 2879 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2880}]>; 2881 2882def Log2_16 : SDNodeXForm<imm, [{ 2883 uint16_t V = N->getZExtValue(); 2884 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2885}]>; 2886 2887def LogN2_8 : SDNodeXForm<imm, [{ 2888 uint8_t NV = ~N->getZExtValue(); 2889 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2890}]>; 2891 2892def LogN2_16 : SDNodeXForm<imm, [{ 2893 uint16_t NV = ~N->getZExtValue(); 2894 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2895}]>; 2896 2897def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 2898 2899multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2900 InstHexagon MI> { 2901 // Addr: i32 2902 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 2903 (MI I32:$Rs, 0, I32:$A)>; 2904 // Addr: fi 2905 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 2906 (MI AddrFI:$Rs, 0, I32:$A)>; 2907} 2908 2909multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2910 SDNode Oper, InstHexagon MI> { 2911 // Addr: i32 2912 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 2913 (add I32:$Rs, ImmPred:$Off)), 2914 (MI I32:$Rs, imm:$Off, I32:$A)>; 2915 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 2916 (IsOrAdd I32:$Rs, ImmPred:$Off)), 2917 (MI I32:$Rs, imm:$Off, I32:$A)>; 2918 // Addr: fi 2919 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2920 (add AddrFI:$Rs, ImmPred:$Off)), 2921 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2922 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 2923 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 2924 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 2925} 2926 2927multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 2928 SDNode Oper, InstHexagon MI> { 2929 let Predicates = [UseMEMOPS] in { 2930 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 2931 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 2932 } 2933} 2934 2935let AddedComplexity = 200 in { 2936 // add reg 2937 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 2938 /*anyext*/ L4_add_memopb_io>; 2939 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 2940 /*sext*/ L4_add_memopb_io>; 2941 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 2942 /*zext*/ L4_add_memopb_io>; 2943 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 2944 /*anyext*/ L4_add_memoph_io>; 2945 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 2946 /*sext*/ L4_add_memoph_io>; 2947 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 2948 /*zext*/ L4_add_memoph_io>; 2949 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 2950 2951 // sub reg 2952 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 2953 /*anyext*/ L4_sub_memopb_io>; 2954 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 2955 /*sext*/ L4_sub_memopb_io>; 2956 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 2957 /*zext*/ L4_sub_memopb_io>; 2958 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 2959 /*anyext*/ L4_sub_memoph_io>; 2960 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 2961 /*sext*/ L4_sub_memoph_io>; 2962 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 2963 /*zext*/ L4_sub_memoph_io>; 2964 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 2965 2966 // and reg 2967 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 2968 /*anyext*/ L4_and_memopb_io>; 2969 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 2970 /*sext*/ L4_and_memopb_io>; 2971 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 2972 /*zext*/ L4_and_memopb_io>; 2973 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 2974 /*anyext*/ L4_and_memoph_io>; 2975 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 2976 /*sext*/ L4_and_memoph_io>; 2977 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 2978 /*zext*/ L4_and_memoph_io>; 2979 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 2980 2981 // or reg 2982 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 2983 /*anyext*/ L4_or_memopb_io>; 2984 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 2985 /*sext*/ L4_or_memopb_io>; 2986 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 2987 /*zext*/ L4_or_memopb_io>; 2988 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 2989 /*anyext*/ L4_or_memoph_io>; 2990 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 2991 /*sext*/ L4_or_memoph_io>; 2992 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 2993 /*zext*/ L4_or_memoph_io>; 2994 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 2995} 2996 2997 2998multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2999 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 3000 // Addr: i32 3001 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 3002 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 3003 // Addr: fi 3004 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 3005 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 3006} 3007 3008multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3009 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3010 InstHexagon MI> { 3011 // Addr: i32 3012 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 3013 (add I32:$Rs, ImmPred:$Off)), 3014 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3015 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 3016 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3017 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3018 // Addr: fi 3019 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3020 (add AddrFI:$Rs, ImmPred:$Off)), 3021 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3022 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3023 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3024 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3025} 3026 3027multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3028 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3029 InstHexagon MI> { 3030 let Predicates = [UseMEMOPS] in { 3031 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 3032 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 3033 } 3034} 3035 3036let AddedComplexity = 220 in { 3037 // add imm 3038 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3039 /*anyext*/ IdImm, L4_iadd_memopb_io>; 3040 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3041 /*sext*/ IdImm, L4_iadd_memopb_io>; 3042 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3043 /*zext*/ IdImm, L4_iadd_memopb_io>; 3044 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3045 /*anyext*/ IdImm, L4_iadd_memoph_io>; 3046 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3047 /*sext*/ IdImm, L4_iadd_memoph_io>; 3048 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3049 /*zext*/ IdImm, L4_iadd_memoph_io>; 3050 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 3051 L4_iadd_memopw_io>; 3052 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3053 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 3054 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3055 /*sext*/ NegImm8, L4_iadd_memopb_io>; 3056 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3057 /*zext*/ NegImm8, L4_iadd_memopb_io>; 3058 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3059 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 3060 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3061 /*sext*/ NegImm16, L4_iadd_memoph_io>; 3062 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3063 /*zext*/ NegImm16, L4_iadd_memoph_io>; 3064 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 3065 L4_iadd_memopw_io>; 3066 3067 // sub imm 3068 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3069 /*anyext*/ IdImm, L4_isub_memopb_io>; 3070 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3071 /*sext*/ IdImm, L4_isub_memopb_io>; 3072 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3073 /*zext*/ IdImm, L4_isub_memopb_io>; 3074 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3075 /*anyext*/ IdImm, L4_isub_memoph_io>; 3076 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3077 /*sext*/ IdImm, L4_isub_memoph_io>; 3078 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3079 /*zext*/ IdImm, L4_isub_memoph_io>; 3080 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 3081 L4_isub_memopw_io>; 3082 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3083 /*anyext*/ NegImm8, L4_isub_memopb_io>; 3084 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3085 /*sext*/ NegImm8, L4_isub_memopb_io>; 3086 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3087 /*zext*/ NegImm8, L4_isub_memopb_io>; 3088 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3089 /*anyext*/ NegImm16, L4_isub_memoph_io>; 3090 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3091 /*sext*/ NegImm16, L4_isub_memoph_io>; 3092 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3093 /*zext*/ NegImm16, L4_isub_memoph_io>; 3094 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 3095 L4_isub_memopw_io>; 3096 3097 // clrbit imm 3098 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3099 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 3100 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3101 /*sext*/ LogN2_8, L4_iand_memopb_io>; 3102 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3103 /*zext*/ LogN2_8, L4_iand_memopb_io>; 3104 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3105 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 3106 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3107 /*sext*/ LogN2_16, L4_iand_memoph_io>; 3108 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3109 /*zext*/ LogN2_16, L4_iand_memoph_io>; 3110 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 3111 LogN2_32, L4_iand_memopw_io>; 3112 3113 // setbit imm 3114 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3115 /*anyext*/ Log2_8, L4_ior_memopb_io>; 3116 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3117 /*sext*/ Log2_8, L4_ior_memopb_io>; 3118 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3119 /*zext*/ Log2_8, L4_ior_memopb_io>; 3120 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3121 /*anyext*/ Log2_16, L4_ior_memoph_io>; 3122 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3123 /*sext*/ Log2_16, L4_ior_memoph_io>; 3124 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3125 /*zext*/ Log2_16, L4_ior_memoph_io>; 3126 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 3127 Log2_32, L4_ior_memopw_io>; 3128} 3129 3130 3131// --(15) Call ----------------------------------------------------------- 3132// 3133 3134// Pseudo instructions. 3135def SDT_SPCallSeqStart 3136 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3137def SDT_SPCallSeqEnd 3138 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3139 3140def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 3141 [SDNPHasChain, SDNPOutGlue]>; 3142def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 3143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 3144 3145def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3146 3147def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 3148 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3149def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 3150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3151def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 3152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3153 3154def: Pat<(callseq_start timm:$amt, timm:$amt2), 3155 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 3156def: Pat<(callseq_end timm:$amt1, timm:$amt2), 3157 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 3158 3159def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 3160def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 3161def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 3162 3163def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 3164def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 3165def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 3166def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 3167 3168def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 3169def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 3170def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 3171 3172def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 3173 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3174def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3175 3176def: Pat<(retflag), (PS_jmpret (i32 R31))>; 3177def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3178 3179 3180// --(16) Branch --------------------------------------------------------- 3181// 3182 3183def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3184def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3185 3186def: Pat<(brcond I1:$Pu, bb:$dst), 3187 (J2_jumpt I1:$Pu, bb:$dst)>; 3188def: Pat<(brcond (not I1:$Pu), bb:$dst), 3189 (J2_jumpf I1:$Pu, bb:$dst)>; 3190def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3191 (J2_jumpf I1:$Pu, bb:$dst)>; 3192def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3193 (J2_jumpf I1:$Pu, bb:$dst)>; 3194def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3195 (J2_jumpt I1:$Pu, bb:$dst)>; 3196 3197 3198// --(17) Misc ----------------------------------------------------------- 3199 3200 3201// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3202// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3203// The isdigit transformation relies on two 'clever' aspects: 3204// 1) The data type is unsigned which allows us to eliminate a zero test after 3205// biasing the expression by 48. We are depending on the representation of 3206// the unsigned types, and semantics. 3207// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3208// 3209// For the C code: 3210// retval = (c >= '0' && c <= '9') ? 1 : 0; 3211// The code is transformed upstream of llvm into 3212// retval = (c-48) < 10 ? 1 : 0; 3213 3214def u7_0PosImmPred : ImmLeaf<i32, [{ 3215 // True if the immediate fits in an 7-bit unsigned field and is positive. 3216 return Imm > 0 && isUInt<7>(Imm); 3217}]>; 3218 3219let AddedComplexity = 139 in 3220def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3221 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3222 3223let AddedComplexity = 100 in 3224def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3225 (i32 (extloadi8 (add I32:$b, 3))), 3226 24, 8), 3227 (i32 16)), 3228 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3229 (zextloadi8 I32:$b)), 3230 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3231 3232 3233// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3234// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3235// We don't really want either one here. 3236def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3237def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3238 [SDNPHasChain]>; 3239 3240def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3241 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3242def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3243 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3244 3245def SDTHexagonALLOCA 3246 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3247def HexagonALLOCA 3248 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3249 3250def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3251 (PS_alloca IntRegs:$Rs, imm:$A)>; 3252 3253def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3254def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3255 3256def: Pat<(trap), (PS_crash)>; 3257 3258// Read cycle counter. 3259def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3260def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3261 [SDNPHasChain]>; 3262 3263def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3264 3265// The declared return value of the store-locked intrinsics is i32, but 3266// the instructions actually define i1. To avoid register copies from 3267// IntRegs to PredRegs and back, fold the entire pattern checking the 3268// result against true/false. 3269let AddedComplexity = 100 in { 3270 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3271 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3272 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3273 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3274 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3275 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3276 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3277 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3278} 3279