10b57cec5SDimitry Andric //===- HexagonMachineScheduler.h - Custom Hexagon MI scheduler --*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // Custom Hexagon MI scheduler. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/CodeGen/MachineScheduler.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/RegisterPressure.h" 180b57cec5SDimitry Andric #include "llvm/CodeGen/TargetSubtargetInfo.h" 19*0eae32dcSDimitry Andric #include "llvm/CodeGen/VLIWMachineScheduler.h" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric namespace llvm { 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric class SUnit; 240b57cec5SDimitry Andric 25*0eae32dcSDimitry Andric class HexagonVLIWResourceModel : public VLIWResourceModel { 260b57cec5SDimitry Andric public: 27*0eae32dcSDimitry Andric using VLIWResourceModel::VLIWResourceModel; 28*0eae32dcSDimitry Andric bool hasDependence(const SUnit *SUd, const SUnit *SUu) override; 290b57cec5SDimitry Andric }; 300b57cec5SDimitry Andric 31*0eae32dcSDimitry Andric class HexagonConvergingVLIWScheduler : public ConvergingVLIWScheduler { 320b57cec5SDimitry Andric protected: 33*0eae32dcSDimitry Andric VLIWResourceModel * 34*0eae32dcSDimitry Andric createVLIWResourceModel(const TargetSubtargetInfo &STI, 35*0eae32dcSDimitry Andric const TargetSchedModel *SchedModel) const override; 36*0eae32dcSDimitry Andric int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, 37*0eae32dcSDimitry Andric RegPressureDelta &Delta, bool verbose) override; 380b57cec5SDimitry Andric }; 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric } // end namespace llvm 410b57cec5SDimitry Andric 420b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H 43