1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 11 12 #include "llvm/CodeGen/MachineFunction.h" 13 #include <map> 14 15 namespace llvm { 16 17 namespace Hexagon { 18 19 const unsigned int StartPacket = 0x1; 20 const unsigned int EndPacket = 0x2; 21 22 } // end namespace Hexagon 23 24 /// Hexagon target-specific information for each MachineFunction. 25 class HexagonMachineFunctionInfo : public MachineFunctionInfo { 26 // SRetReturnReg - Some subtargets require that sret lowering includes 27 // returning the value of the returned struct in a register. This field 28 // holds the virtual register into which the sret argument is passed. 29 unsigned SRetReturnReg = 0; 30 unsigned StackAlignBaseVReg = 0; // Aligned-stack base register (virtual) 31 unsigned StackAlignBasePhysReg = 0; // (physical) 32 int VarArgsFrameIndex; 33 int RegSavedAreaStartFrameIndex; 34 int FirstNamedArgFrameIndex; 35 int LastNamedArgFrameIndex; 36 bool HasClobberLR = false; 37 bool HasEHReturn = false; 38 std::map<const MachineInstr*, unsigned> PacketInfo; 39 virtual void anchor(); 40 41 public: 42 HexagonMachineFunctionInfo() = default; 43 44 HexagonMachineFunctionInfo(MachineFunction &MF) {} 45 MachineFunctionInfo * 46 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, 47 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB) 48 const override; 49 50 unsigned getSRetReturnReg() const { return SRetReturnReg; } 51 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } 52 53 void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; } 54 int getVarArgsFrameIndex() { return VarArgsFrameIndex; } 55 56 void setRegSavedAreaStartFrameIndex(int v) { RegSavedAreaStartFrameIndex = v;} 57 int getRegSavedAreaStartFrameIndex() { return RegSavedAreaStartFrameIndex; } 58 59 void setFirstNamedArgFrameIndex(int v) { FirstNamedArgFrameIndex = v; } 60 int getFirstNamedArgFrameIndex() { return FirstNamedArgFrameIndex; } 61 62 void setLastNamedArgFrameIndex(int v) { LastNamedArgFrameIndex = v; } 63 int getLastNamedArgFrameIndex() { return LastNamedArgFrameIndex; } 64 65 void setStartPacket(MachineInstr* MI) { 66 PacketInfo[MI] |= Hexagon::StartPacket; 67 } 68 void setEndPacket(MachineInstr* MI) { 69 PacketInfo[MI] |= Hexagon::EndPacket; 70 } 71 bool isStartPacket(const MachineInstr* MI) const { 72 return (PacketInfo.count(MI) && 73 (PacketInfo.find(MI)->second & Hexagon::StartPacket)); 74 } 75 bool isEndPacket(const MachineInstr* MI) const { 76 return (PacketInfo.count(MI) && 77 (PacketInfo.find(MI)->second & Hexagon::EndPacket)); 78 } 79 void setHasClobberLR(bool v) { HasClobberLR = v; } 80 bool hasClobberLR() const { return HasClobberLR; } 81 82 bool hasEHReturn() const { return HasEHReturn; }; 83 void setHasEHReturn(bool H = true) { HasEHReturn = H; }; 84 85 void setStackAlignBaseVReg(unsigned R) { StackAlignBaseVReg = R; } 86 unsigned getStackAlignBaseVReg() const { return StackAlignBaseVReg; } 87 88 void setStackAlignBasePhysReg(unsigned R) { StackAlignBasePhysReg = R; } 89 unsigned getStackAlignBasePhysReg() const { return StackAlignBasePhysReg; } 90 }; 91 92 } // end namespace llvm 93 94 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 95