1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 11 12 #include "llvm/CodeGen/MachineFunction.h" 13 #include <map> 14 15 namespace llvm { 16 17 namespace Hexagon { 18 19 const unsigned int StartPacket = 0x1; 20 const unsigned int EndPacket = 0x2; 21 22 } // end namespace Hexagon 23 24 /// Hexagon target-specific information for each MachineFunction. 25 class HexagonMachineFunctionInfo : public MachineFunctionInfo { 26 // SRetReturnReg - Some subtargets require that sret lowering includes 27 // returning the value of the returned struct in a register. This field 28 // holds the virtual register into which the sret argument is passed. 29 unsigned SRetReturnReg = 0; 30 unsigned StackAlignBaseVReg = 0; // Aligned-stack base register (virtual) 31 unsigned StackAlignBasePhysReg = 0; // (physical) 32 int VarArgsFrameIndex; 33 bool HasClobberLR = false; 34 bool HasEHReturn = false; 35 std::map<const MachineInstr*, unsigned> PacketInfo; 36 virtual void anchor(); 37 38 public: 39 HexagonMachineFunctionInfo() = default; 40 41 HexagonMachineFunctionInfo(MachineFunction &MF) {} 42 43 unsigned getSRetReturnReg() const { return SRetReturnReg; } 44 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } 45 46 void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; } 47 int getVarArgsFrameIndex() { return VarArgsFrameIndex; } 48 49 void setStartPacket(MachineInstr* MI) { 50 PacketInfo[MI] |= Hexagon::StartPacket; 51 } 52 void setEndPacket(MachineInstr* MI) { 53 PacketInfo[MI] |= Hexagon::EndPacket; 54 } 55 bool isStartPacket(const MachineInstr* MI) const { 56 return (PacketInfo.count(MI) && 57 (PacketInfo.find(MI)->second & Hexagon::StartPacket)); 58 } 59 bool isEndPacket(const MachineInstr* MI) const { 60 return (PacketInfo.count(MI) && 61 (PacketInfo.find(MI)->second & Hexagon::EndPacket)); 62 } 63 void setHasClobberLR(bool v) { HasClobberLR = v; } 64 bool hasClobberLR() const { return HasClobberLR; } 65 66 bool hasEHReturn() const { return HasEHReturn; }; 67 void setHasEHReturn(bool H = true) { HasEHReturn = H; }; 68 69 void setStackAlignBaseVReg(unsigned R) { StackAlignBaseVReg = R; } 70 unsigned getStackAlignBaseVReg() const { return StackAlignBaseVReg; } 71 72 void setStackAlignBasePhysReg(unsigned R) { StackAlignBasePhysReg = R; } 73 unsigned getStackAlignBasePhysReg() const { return StackAlignBasePhysReg; } 74 }; 75 76 } // end namespace llvm 77 78 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 79