1*0b57cec5SDimitry Andric //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 10*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 11*0b57cec5SDimitry Andric 12*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 13*0b57cec5SDimitry Andric #include <map> 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric namespace llvm { 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andric namespace Hexagon { 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric const unsigned int StartPacket = 0x1; 20*0b57cec5SDimitry Andric const unsigned int EndPacket = 0x2; 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric } // end namespace Hexagon 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric /// Hexagon target-specific information for each MachineFunction. 25*0b57cec5SDimitry Andric class HexagonMachineFunctionInfo : public MachineFunctionInfo { 26*0b57cec5SDimitry Andric // SRetReturnReg - Some subtargets require that sret lowering includes 27*0b57cec5SDimitry Andric // returning the value of the returned struct in a register. This field 28*0b57cec5SDimitry Andric // holds the virtual register into which the sret argument is passed. 29*0b57cec5SDimitry Andric unsigned SRetReturnReg = 0; 30*0b57cec5SDimitry Andric unsigned StackAlignBaseVReg = 0; // Aligned-stack base register (virtual) 31*0b57cec5SDimitry Andric unsigned StackAlignBasePhysReg = 0; // (physical) 32*0b57cec5SDimitry Andric int VarArgsFrameIndex; 33*0b57cec5SDimitry Andric bool HasClobberLR = false; 34*0b57cec5SDimitry Andric bool HasEHReturn = false; 35*0b57cec5SDimitry Andric std::map<const MachineInstr*, unsigned> PacketInfo; 36*0b57cec5SDimitry Andric virtual void anchor(); 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric public: 39*0b57cec5SDimitry Andric HexagonMachineFunctionInfo() = default; 40*0b57cec5SDimitry Andric 41*0b57cec5SDimitry Andric HexagonMachineFunctionInfo(MachineFunction &MF) {} 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric unsigned getSRetReturnReg() const { return SRetReturnReg; } 44*0b57cec5SDimitry Andric void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; } 47*0b57cec5SDimitry Andric int getVarArgsFrameIndex() { return VarArgsFrameIndex; } 48*0b57cec5SDimitry Andric 49*0b57cec5SDimitry Andric void setStartPacket(MachineInstr* MI) { 50*0b57cec5SDimitry Andric PacketInfo[MI] |= Hexagon::StartPacket; 51*0b57cec5SDimitry Andric } 52*0b57cec5SDimitry Andric void setEndPacket(MachineInstr* MI) { 53*0b57cec5SDimitry Andric PacketInfo[MI] |= Hexagon::EndPacket; 54*0b57cec5SDimitry Andric } 55*0b57cec5SDimitry Andric bool isStartPacket(const MachineInstr* MI) const { 56*0b57cec5SDimitry Andric return (PacketInfo.count(MI) && 57*0b57cec5SDimitry Andric (PacketInfo.find(MI)->second & Hexagon::StartPacket)); 58*0b57cec5SDimitry Andric } 59*0b57cec5SDimitry Andric bool isEndPacket(const MachineInstr* MI) const { 60*0b57cec5SDimitry Andric return (PacketInfo.count(MI) && 61*0b57cec5SDimitry Andric (PacketInfo.find(MI)->second & Hexagon::EndPacket)); 62*0b57cec5SDimitry Andric } 63*0b57cec5SDimitry Andric void setHasClobberLR(bool v) { HasClobberLR = v; } 64*0b57cec5SDimitry Andric bool hasClobberLR() const { return HasClobberLR; } 65*0b57cec5SDimitry Andric 66*0b57cec5SDimitry Andric bool hasEHReturn() const { return HasEHReturn; }; 67*0b57cec5SDimitry Andric void setHasEHReturn(bool H = true) { HasEHReturn = H; }; 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric void setStackAlignBaseVReg(unsigned R) { StackAlignBaseVReg = R; } 70*0b57cec5SDimitry Andric unsigned getStackAlignBaseVReg() const { return StackAlignBaseVReg; } 71*0b57cec5SDimitry Andric 72*0b57cec5SDimitry Andric void setStackAlignBasePhysReg(unsigned R) { StackAlignBasePhysReg = R; } 73*0b57cec5SDimitry Andric unsigned getStackAlignBasePhysReg() const { return StackAlignBasePhysReg; } 74*0b57cec5SDimitry Andric }; 75*0b57cec5SDimitry Andric 76*0b57cec5SDimitry Andric } // end namespace llvm 77*0b57cec5SDimitry Andric 78*0b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H 79