xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td (revision d4eeb02986980bf33dd56c41ceb9fc5f180c0d47) 
1//===- HexagonIntrinsicsV60.td - V60 instruction intrinsics -*- tablegen *-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the Hexagon V60 Compiler Intrinsics in TableGen format.
10//
11//===----------------------------------------------------------------------===//
12
13
14let AddedComplexity = 100 in {
15def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16            (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
17
18def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19            (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
20
21def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22            (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
23
24def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25            (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
26}
27
28def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
29           (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
30
31def : Pat <(v64i1 (bitconvert (v32i16 HvxVR:$src1))),
32           (v64i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
33
34def : Pat <(v64i1 (bitconvert (v64i8  HvxVR:$src1))),
35           (v64i1 (V6_vandvrt(v64i8  HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
36
37def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))),
38           (v16i32 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
39
40def : Pat <(v32i16 (bitconvert (v64i1 HvxQR:$src1))),
41           (v32i16 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
42
43def : Pat <(v64i8  (bitconvert (v64i1 HvxQR:$src1))),
44           (v64i8  (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
45
46def : Pat <(v128i1 (bitconvert (v32i32 HvxVR:$src1))),
47           (v128i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
48
49def : Pat <(v128i1 (bitconvert (v64i16 HvxVR:$src1))),
50           (v128i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
51
52def : Pat <(v128i1 (bitconvert (v128i8  HvxVR:$src1))),
53           (v128i1 (V6_vandvrt (v128i8  HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
54
55def : Pat <(v32i32 (bitconvert (v128i1 HvxQR:$src1))),
56           (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
57
58def : Pat <(v64i16 (bitconvert (v128i1 HvxQR:$src1))),
59           (v64i16 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
60
61def : Pat <(v128i8  (bitconvert (v128i1 HvxQR:$src1))),
62           (v128i8  (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
63
64let AddedComplexity = 140 in {
65def : Pat <(store (v64i1 HvxQR:$src1), (i32 IntRegs:$addr)),
66           (V6_vS32b_ai IntRegs:$addr, 0,
67           (v16i32 (V6_vandqrt (v64i1 HvxQR:$src1),
68                                       (A2_tfrsi 0x01010101))))>;
69
70def : Pat <(v64i1 (load (i32 IntRegs:$addr))),
71           (v64i1 (V6_vandvrt
72           (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
73
74def : Pat <(store (v128i1 HvxQR:$src1), (i32 IntRegs:$addr)),
75           (V6_vS32b_ai IntRegs:$addr, 0,
76           (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1),
77                                       (A2_tfrsi 0x01010101))))>;
78
79def : Pat <(v128i1 (load (i32 IntRegs:$addr))),
80           (v128i1 (V6_vandvrt
81           (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
82}
83
84multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
85  def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86  def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
87           (MI IntRegs:$src1)>;
88}
89
90multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
91  def: Pat<(IntID HvxVR:$src1),
92           (MI    HvxVR:$src1)>;
93
94  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
95           (MI HvxVR:$src1)>;
96}
97
98multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
99  def: Pat<(IntID HvxWR:$src1),
100           (MI    HvxWR:$src1)>;
101
102  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
103           (MI HvxWR:$src1)>;
104}
105
106multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
107  def: Pat<(IntID HvxQR:$src1),
108           (MI    HvxQR:$src1)>;
109
110  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1),
111           (MI HvxQR:$src1)>;
112}
113
114multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> {
115  def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
116           (MI    HvxWR:$src1, IntRegs:$src2)>;
117
118  def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
119           (MI HvxWR:$src1, IntRegs:$src2)>;
120}
121
122multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> {
123  def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
124           (MI    HvxVR:$src1, IntRegs:$src2)>;
125
126  def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
127           (MI HvxVR:$src1, IntRegs:$src2)>;
128}
129
130multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> {
131  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132           (MI    HvxWR:$src1, HvxVR:$src2)>;
133
134  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2),
135           (MI  HvxWR:$src1, HvxVR:$src2)>;
136}
137
138multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> {
139  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
140           (MI    HvxWR:$src1, HvxWR:$src2)>;
141
142  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
143           (MI  HvxWR:$src1, HvxWR:$src2)>;
144}
145
146multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> {
147  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
148           (MI    HvxVR:$src1, HvxVR:$src2)>;
149
150  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
151           (MI  HvxVR:$src1, HvxVR:$src2)>;
152}
153
154multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> {
155  def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
156           (MI    HvxQR:$src1, IntRegs:$src2)>;
157
158  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
159           (MI  HvxQR:$src1, IntRegs:$src2)>;
160}
161
162multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> {
163  def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
164           (MI    HvxQR:$src1, HvxQR:$src2)>;
165
166  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
167           (MI  HvxQR:$src1, HvxQR:$src2)>;
168}
169
170multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> {
171  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172           (MI    HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
173
174  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
175                                            IntRegs:$src3),
176           (MI  HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
177}
178
179multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
180  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181           (MI    HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
182
183  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
184                                            IntRegs:$src3),
185           (MI  HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
186}
187
188multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> {
189  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190           (MI    HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
191
192  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
193                                            IntRegs:$src3),
194           (MI  HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
195}
196
197multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> {
198  def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
199           (MI    HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
200
201  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2,
202                                            IntRegs:$src3),
203           (MI  HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
204}
205
206multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> {
207  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
208           (MI    HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
209
210  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
211                                            HvxVR:$src3),
212           (MI  HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
213}
214
215multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> {
216  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
217           (MI    HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
218
219  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
220                                            HvxVR:$src3),
221           (MI  HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
222}
223
224multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> {
225  def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
226           (MI    HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
227
228  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
229                                            HvxVR:$src3),
230           (MI  HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
231}
232
233multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> {
234  def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
235           (MI    HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
236
237  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
238                                            IntRegs:$src3),
239           (MI  HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
240}
241
242
243multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> {
244  def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
245           (MI    HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
246
247  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
248                                            IntRegs:$src3),
249           (MI  HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
250}
251
252multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
253  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
254           (MI    HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
255
256  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1,
257                                            HvxVR:$src2, imm:$src3),
258           (MI  HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
259}
260
261multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> {
262  def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
263           (MI    HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
264
265  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1,
266                                            IntRegs:$src2, imm:$src3),
267           (MI  HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
268}
269
270multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> {
271  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272           (MI   HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
273
274  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
275                                            IntRegs:$src3, imm:$src4),
276           (MI  HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
277}
278
279multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> {
280  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281           (MI    HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
282
283  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
284                                            HvxVR:$src3, IntRegs:$src4),
285           (MI  HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
286}
287
288multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> {
289  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
290           (MI    HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
291
292  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
293                                            HvxVR:$src3, IntRegs:$src4),
294           (MI  HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
295}
296
297defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>;
298defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>;
299defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>;
300defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>;
301defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>;
302defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>;
303defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>;
304defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>;
305defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>;
306defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>;
307defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>;
308defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>;
309defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>;
310defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>;
311defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>;
312defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>;
313defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>;
314defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>;
315defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>;
316defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>;
317defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>;
318defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>;
319defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>;
320defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>;
321defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>;
322defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>;
323defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>;
324defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>;
325defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>;
326defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>;
327defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>;
328defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>;
329
330defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>;
331defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>;
332defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>;
333defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>;
334defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>;
335defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>;
336defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>;
337defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>;
338defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>;
339defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>;
340defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>;
341defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>;
342defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>;
343defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>;
344defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>;
345defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>;
346defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>;
347defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>;
348defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>;
349defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>;
350defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>;
351defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>;
352defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>;
353defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>;
354defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>;
355defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>;
356defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>;
357defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>;
358defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>;
359defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>;
360defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>;
361defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>;
362defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>;
363defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>;
364defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>;
365defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>;
366defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>;
367defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>;
368defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>;
369defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>;
370defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>;
371defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>;
372defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>;
373defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>;
374defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>;
375defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>;
376defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>;
377defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>;
378defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>;
379defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>;
380defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>;
381defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>;
382defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>;
383defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>;
384defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>;
385defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>;
386defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>;
387defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>;
388defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>;
389defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>;
390defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>;
391defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>;
392defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>;
393defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>;
394
395defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>;
396defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>;
397defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>;
398defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>;
399defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>;
400defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>;
401defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>;
402defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>;
403defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>;
404defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>;
405defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>;
406
407defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>;
408defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>;
409
410defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>;
411defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>;
412defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>;
413defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>;
414
415defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>;
416defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>;
417defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>;
418defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>;
419defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>;
420defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>;
421defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>;
422defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>;
423
424defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>;
425defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>;
426defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>;
427defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>;
428defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>;
429defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>;
430defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>;
431defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>;
432defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>;
433defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>;
434defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>;
435defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>;
436defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>;
437defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>;
438defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>;
439
440// Compare instructions
441defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>;
442defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>;
443defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>;
444defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>;
445defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>;
446defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>;
447defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>;
448defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>;
449defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>;
450defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>;
451defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>;
452defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>;
453defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>;
454defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>;
455defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>;
456defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>;
457defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>;
458defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>;
459defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>;
460defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>;
461defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>;
462defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>;
463defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>;
464defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>;
465defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>;
466defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>;
467defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>;
468
469defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>;
470defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>;
471defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>;
472defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>;
473defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>;
474defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>;
475defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>;
476defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>;
477defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>;
478defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>;
479defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>;
480defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>;
481defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>;
482defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>;
483defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>;
484defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>;
485defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>;
486defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>;
487defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>;
488defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>;
489defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>;
490defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>;
491defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>;
492defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>;
493defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>;
494defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>;
495defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>;
496defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>;
497defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>;
498defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>;
499defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>;
500defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>;
501defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>;
502defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>;
503defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>;
504defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>;
505defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>;
506defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>;
507defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>;
508defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>;
509defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>;
510defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>;
511defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>;
512defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>;
513defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>;
514defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>;
515
516defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>;
517defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>;
518defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>;
519defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>;
520defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>;
521defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>;
522defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>;
523defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>;
524defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>;
525defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>;
526defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>;
527defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>;
528
529defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>;
530defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>;
531defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>;
532defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>;
533defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>;
534defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>;
535defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>;
536defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>;
537defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>;
538defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>;
539defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>;
540defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>;
541defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>;
542defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>;
543defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>;
544defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>;
545defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>;
546defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>;
547defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>;
548defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>;
549defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>;
550defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>;
551defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>;
552
553defm : T_W_pat <V6_lo, int_hexagon_V6_lo>;
554defm : T_W_pat <V6_hi, int_hexagon_V6_hi>;
555defm : T_W_pat <V6_vassignp, int_hexagon_V6_vassignp>;
556
557defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>;
558defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>;
559defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>;
560
561defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>;
562defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>;
563defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>;
564
565// assembler mapped.
566//defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>;
567// not present earlier.. need to add intrinsic
568defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>;
569defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>;
570defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>;
571defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>;
572defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>;
573defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>;
574defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>;
575defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>;
576defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>;
577
578defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>;
579defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>;
580
581defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>;
582defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>;
583defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>;
584defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>;
585
586defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>;
587defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>;
588defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>;
589defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>;
590defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>;
591defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>;
592defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>;
593defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>;
594defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>;
595defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>;
596defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>;
597defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>;
598defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>;
599defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>;
600defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>;
601defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>;
602defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>;
603
604defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>;
605defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
606defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>;
607defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>;
608defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>;
609defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>;
610
611defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>;
612defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>;
613defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>;
614defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>;
615
616defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
617def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>;
618def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>;
619def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>;
620def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>;
621def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>;
622def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>;
623def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>;
624def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>;
625def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>;
626def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>;
627def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>;
628def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>;
629
630defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>;
631defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>;
632
633//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
634
635def: Pat<(v64i16 (trunc v64i32:$Vdd)),
636         (v64i16 (V6_vpackwh_sat
637                 (v32i32 (V6_hi HvxWR:$Vdd)),
638                 (v32i32 (V6_lo HvxWR:$Vdd))))>;
639
640def: Pat<(int_hexagon_V6_vd0),      (V6_vd0)>;
641def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0)>;
642
643