1//===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>; 10def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>; 11def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>; 12 13// Vector reduce add unsigned halfwords 14def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>; 15 16def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>; 17def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>; 18def: T_PP_pat<A2_minp, int_hexagon_A2_minp>; 19def: T_PP_pat<A2_minup, int_hexagon_A2_minup>; 20def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>; 21def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>; 22 23// Vector reduce multiply word by signed half (32x16) 24//Rdd=vrmpyweh(Rss,Rtt)[:<<1] 25def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>; 26def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>; 27 28//Rdd=vrmpywoh(Rss,Rtt)[:<<1] 29def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>; 30def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>; 31 32//Rdd+=vrmpyweh(Rss,Rtt)[:<<1] 33def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>; 34def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>; 35 36//Rdd=vrmpywoh(Rss,Rtt)[:<<1] 37def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>; 38def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>; 39 40// Vector multiply halfwords, signed by unsigned 41// Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat 42def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>; 43def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>; 44 45// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat 46def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>; 47def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>; 48 49// Vector polynomial multiply halfwords 50// Rdd=vpmpyh(Rs,Rt) 51def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>; 52// Rxx[^]=vpmpyh(Rs,Rt) 53def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>; 54 55// Polynomial multiply words 56// Rdd=pmpyw(Rs,Rt) 57def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>; 58// Rxx^=pmpyw(Rs,Rt) 59def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>; 60 61//Rxx^=asr(Rss,Rt) 62def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>; 63//Rxx^=asl(Rss,Rt) 64def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>; 65//Rxx^=lsr(Rss,Rt) 66def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>; 67//Rxx^=lsl(Rss,Rt) 68def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>; 69 70// Multiply and use upper result 71def : T_RR_pat <M2_mpysu_up, int_hexagon_M2_mpysu_up>; 72def : T_RR_pat <M2_mpy_up_s1, int_hexagon_M2_mpy_up_s1>; 73def : T_RR_pat <M2_hmmpyh_s1, int_hexagon_M2_hmmpyh_s1>; 74def : T_RR_pat <M2_hmmpyl_s1, int_hexagon_M2_hmmpyl_s1>; 75def : T_RR_pat <M2_mpy_up_s1_sat, int_hexagon_M2_mpy_up_s1_sat>; 76 77def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddb_map>; 78def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubb_map>; 79 80// Vector reduce add unsigned halfwords 81def : T_PP_pat <M2_vraddh, int_hexagon_M2_vraddh>; 82 83def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>; 84def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>; 85def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>; 86 87def: T_Q_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>; 88def: T_Q_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>; 89def: T_Q_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>; 90 91def : T_Q_PI_pat<A4_vcmpbeqi, int_hexagon_A4_vcmpbeqi>; 92def : T_Q_PI_pat<A4_vcmpbgti, int_hexagon_A4_vcmpbgti>; 93def : T_Q_PI_pat<A4_vcmpbgtui, int_hexagon_A4_vcmpbgtui>; 94def : T_Q_PI_pat<A4_vcmpheqi, int_hexagon_A4_vcmpheqi>; 95def : T_Q_PI_pat<A4_vcmphgti, int_hexagon_A4_vcmphgti>; 96def : T_Q_PI_pat<A4_vcmphgtui, int_hexagon_A4_vcmphgtui>; 97def : T_Q_PI_pat<A4_vcmpweqi, int_hexagon_A4_vcmpweqi>; 98def : T_Q_PI_pat<A4_vcmpwgti, int_hexagon_A4_vcmpwgti>; 99def : T_Q_PI_pat<A4_vcmpwgtui, int_hexagon_A4_vcmpwgtui>; 100def : T_Q_PP_pat<A4_vcmpbeq_any, int_hexagon_A4_vcmpbeq_any>; 101 102def : T_Q_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>; 103def : T_Q_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>; 104def : T_Q_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>; 105def : T_Q_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>; 106def : T_Q_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>; 107def : T_Q_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>; 108 109def : T_Q_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>; 110def : T_Q_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>; 111def : T_Q_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>; 112 113def : T_Q_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>; 114def : T_Q_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>; 115def : T_Q_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>; 116 117def : T_Q_RP_pat<A4_boundscheck, int_hexagon_A4_boundscheck>; 118def : T_Q_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>; 119 120def : T_RRR_pat <M4_mpyrr_addr, int_hexagon_M4_mpyrr_addr>; 121def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>; 122def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>; 123def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>; 124def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>; 125def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>; 126def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>; 127 128// Complex multiply 32x16 129def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>; 130def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>; 131 132def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>; 133def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>; 134 135def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>; 136def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>; 137 138// Complex add/sub halfwords/words 139def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>; 140def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>; 141def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>; 142def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>; 143 144def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>; 145def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>; 146 147// Extract bitfield 148def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>; 149def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>; 150def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>; 151def : T_RII_pat <S4_extract, int_hexagon_S4_extract>; 152 153// Vector conditional negate 154// Rdd=vcnegh(Rss,Rt) 155def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>; 156 157// Shift an immediate left by register amount 158def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>; 159 160// Vector reduce maximum halfwords 161def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>; 162def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>; 163 164// Vector reduce maximum words 165def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>; 166def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>; 167 168// Vector reduce minimum halfwords 169def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>; 170def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>; 171 172// Vector reduce minimum words 173def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>; 174def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>; 175 176// Rotate and reduce bytes 177def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, 178 u2_0ImmPred:$src3), 179 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>; 180 181// Rotate and reduce bytes with accumulation 182// Rxx+=vrcrotate(Rss,Rt,#u2) 183def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, 184 IntRegs:$src3, u2_0ImmPred:$src4), 185 (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, 186 IntRegs:$src3, u2_0ImmPred:$src4)>; 187 188// Vector conditional negate 189def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>; 190 191// Logical xor with xor accumulation 192def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>; 193 194// ALU64 - Vector min/max byte 195def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>; 196def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>; 197 198// Shift and add/sub/and/or 199def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>; 200def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>; 201def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>; 202def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>; 203def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>; 204def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>; 205def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>; 206def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>; 207 208// Split bitfield 209def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>; 210def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>; 211 212def: T_RR_pat<S4_parity, int_hexagon_S4_parity>; 213 214def: T_Q_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>; 215def: T_Q_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>; 216 217def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>; 218def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>; 219def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>; 220 221//******************************************************************* 222// ALU32/ALU 223//******************************************************************* 224 225// ALU32 / ALU / Logical Operations. 226def: T_RR_pat<A4_andn, int_hexagon_A4_andn>; 227def: T_RR_pat<A4_orn, int_hexagon_A4_orn>; 228 229//******************************************************************* 230// ALU32/PERM 231//******************************************************************* 232 233// Combine Words Into Doublewords. 234def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32_0ImmPred>; 235def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32_0ImmPred>; 236 237//******************************************************************* 238// ALU32/PRED 239//******************************************************************* 240 241// Compare 242def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32_0ImmPred>; 243def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32_0ImmPred>; 244def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32_0ImmPred>; 245 246// Compare To General Register. 247def: T_Q_RR_pat<C4_cmpneq, int_hexagon_C4_cmpneq>; 248def: T_Q_RR_pat<C4_cmplte, int_hexagon_C4_cmplte>; 249def: T_Q_RR_pat<C4_cmplteu, int_hexagon_C4_cmplteu>; 250 251def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>; 252def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>; 253 254def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>; 255def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>; 256 257//******************************************************************* 258// CR 259//******************************************************************* 260 261// CR / Logical Operations On Predicates. 262def: T_Q_QQQ_pat<C4_and_and, int_hexagon_C4_and_and>; 263def: T_Q_QQQ_pat<C4_and_andn, int_hexagon_C4_and_andn>; 264def: T_Q_QQQ_pat<C4_and_or, int_hexagon_C4_and_or>; 265def: T_Q_QQQ_pat<C4_and_orn, int_hexagon_C4_and_orn>; 266def: T_Q_QQQ_pat<C4_or_and, int_hexagon_C4_or_and>; 267def: T_Q_QQQ_pat<C4_or_andn, int_hexagon_C4_or_andn>; 268def: T_Q_QQQ_pat<C4_or_or, int_hexagon_C4_or_or>; 269def: T_Q_QQQ_pat<C4_or_orn, int_hexagon_C4_or_orn>; 270 271//******************************************************************* 272// XTYPE/ALU 273//******************************************************************* 274 275// Add And Accumulate. 276 277def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>; 278def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>; 279 280 281// XTYPE / ALU / Logical-logical Words. 282def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>; 283def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>; 284def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>; 285def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>; 286def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>; 287def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>; 288def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>; 289def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>; 290def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>; 291def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>; 292def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>; 293 294def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>; 295def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>; 296def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>; 297 298// Modulo wrap. 299def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>; 300 301// Arithmetic/Convergent round 302// Rd=[cround|round](Rs,Rt)[:sat] 303// Rd=[cround|round](Rs,#u5)[:sat] 304def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>; 305def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>; 306 307def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>; 308def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>; 309 310def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>; 311def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>; 312 313def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>; 314 315//Rdd[+]=vrmpybsu(Rss,Rtt) 316//Rdd[+]=vrmpybuu(Rss,Rtt) 317def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>; 318def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>; 319 320def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>; 321 322def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>; 323def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>; 324//Rxx+=vdmpybsu(Rss,Rtt):sat 325def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>; 326 327// Vector multiply bytes 328// Rdd=vmpyb[s]u(Rs,Rt) 329def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>; 330def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>; 331 332// Rxx+=vmpyb[s]u(Rs,Rt) 333def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>; 334def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>; 335 336// Rd=vaddhub(Rss,Rtt):sat 337def : T_PP_pat <A5_vaddhubs, int_hexagon_A5_vaddhubs>; 338 339def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>; 340def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>; 341def : T_FF_pat<F2_sfmpy, int_hexagon_F2_sfmpy>; 342def : T_FF_pat<F2_sfmax, int_hexagon_F2_sfmax>; 343def : T_FF_pat<F2_sfmin, int_hexagon_F2_sfmin>; 344 345def : T_FF_pat<F2_sffixupn, int_hexagon_F2_sffixupn>; 346def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>; 347def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>; 348 349def : T_Q_QQ_pat<C4_fastcorner9, int_hexagon_C4_fastcorner9>; 350def : T_Q_QQ_pat<C4_fastcorner9_not, int_hexagon_C4_fastcorner9_not>; 351 352def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>; 353def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>; 354 355def : T_PI_pat <S2_asr_i_p_rnd, int_hexagon_S2_asr_i_p_rnd>; 356def : T_PI_pat <S2_asr_i_p_rnd_goodsyntax, 357 int_hexagon_S2_asr_i_p_rnd_goodsyntax>; 358 359def : T_PI_pat <S5_asrhub_rnd_sat_goodsyntax, 360 int_hexagon_S5_asrhub_rnd_sat_goodsyntax>; 361 362def : T_PI_pat <S5_vasrhrnd_goodsyntax, int_hexagon_S5_vasrhrnd_goodsyntax>; 363 364def : T_FFF_pat <F2_sffma, int_hexagon_F2_sffma>; 365def : T_FFF_pat <F2_sffms, int_hexagon_F2_sffms>; 366def : T_FFF_pat <F2_sffma_lib, int_hexagon_F2_sffma_lib>; 367def : T_FFF_pat <F2_sffms_lib, int_hexagon_F2_sffms_lib>; 368def : T_FFFQ_pat <F2_sffma_sc, int_hexagon_F2_sffma_sc>; 369 370// Compare floating-point value 371def : T_Q_FF_pat <F2_sfcmpge, int_hexagon_F2_sfcmpge>; 372def : T_Q_FF_pat <F2_sfcmpuo, int_hexagon_F2_sfcmpuo>; 373def : T_Q_FF_pat <F2_sfcmpeq, int_hexagon_F2_sfcmpeq>; 374def : T_Q_FF_pat <F2_sfcmpgt, int_hexagon_F2_sfcmpgt>; 375 376def : T_Q_DD_pat <F2_dfcmpeq, int_hexagon_F2_dfcmpeq>; 377def : T_Q_DD_pat <F2_dfcmpgt, int_hexagon_F2_dfcmpgt>; 378def : T_Q_DD_pat <F2_dfcmpge, int_hexagon_F2_dfcmpge>; 379def : T_Q_DD_pat <F2_dfcmpuo, int_hexagon_F2_dfcmpuo>; 380 381// Create floating-point value 382def : T_I_pat <F2_sfimm_p, int_hexagon_F2_sfimm_p>; 383def : T_I_pat <F2_sfimm_n, int_hexagon_F2_sfimm_n>; 384def : T_I_pat <F2_dfimm_p, int_hexagon_F2_dfimm_p>; 385def : T_I_pat <F2_dfimm_n, int_hexagon_F2_dfimm_n>; 386 387def : T_Q_DI_pat <F2_dfclass, int_hexagon_F2_dfclass>; 388def : T_Q_FI_pat <F2_sfclass, int_hexagon_F2_sfclass>; 389def : T_F_pat <F2_conv_sf2df, int_hexagon_F2_conv_sf2df>; 390def : T_D_pat <F2_conv_df2sf, int_hexagon_F2_conv_df2sf>; 391def : T_R_pat <F2_conv_uw2sf, int_hexagon_F2_conv_uw2sf>; 392def : T_R_pat <F2_conv_uw2df, int_hexagon_F2_conv_uw2df>; 393def : T_R_pat <F2_conv_w2sf, int_hexagon_F2_conv_w2sf>; 394def : T_R_pat <F2_conv_w2df, int_hexagon_F2_conv_w2df>; 395def : T_P_pat <F2_conv_ud2sf, int_hexagon_F2_conv_ud2sf>; 396def : T_P_pat <F2_conv_ud2df, int_hexagon_F2_conv_ud2df>; 397def : T_P_pat <F2_conv_d2sf, int_hexagon_F2_conv_d2sf>; 398def : T_P_pat <F2_conv_d2df, int_hexagon_F2_conv_d2df>; 399def : T_F_pat <F2_conv_sf2uw, int_hexagon_F2_conv_sf2uw>; 400def : T_F_pat <F2_conv_sf2w, int_hexagon_F2_conv_sf2w>; 401def : T_F_pat <F2_conv_sf2ud, int_hexagon_F2_conv_sf2ud>; 402def : T_F_pat <F2_conv_sf2d, int_hexagon_F2_conv_sf2d>; 403def : T_D_pat <F2_conv_df2uw, int_hexagon_F2_conv_df2uw>; 404def : T_D_pat <F2_conv_df2w, int_hexagon_F2_conv_df2w>; 405def : T_D_pat <F2_conv_df2ud, int_hexagon_F2_conv_df2ud>; 406def : T_D_pat <F2_conv_df2d, int_hexagon_F2_conv_df2d>; 407def : T_F_pat <F2_conv_sf2uw_chop, int_hexagon_F2_conv_sf2uw_chop>; 408def : T_F_pat <F2_conv_sf2w_chop, int_hexagon_F2_conv_sf2w_chop>; 409def : T_F_pat <F2_conv_sf2ud_chop, int_hexagon_F2_conv_sf2ud_chop>; 410def : T_F_pat <F2_conv_sf2d_chop, int_hexagon_F2_conv_sf2d_chop>; 411def : T_D_pat <F2_conv_df2uw_chop, int_hexagon_F2_conv_df2uw_chop>; 412def : T_D_pat <F2_conv_df2w_chop, int_hexagon_F2_conv_df2w_chop>; 413def : T_D_pat <F2_conv_df2ud_chop, int_hexagon_F2_conv_df2ud_chop>; 414def : T_D_pat <F2_conv_df2d_chop, int_hexagon_F2_conv_df2d_chop>; 415