1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Hexagon implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 15 16 #include "MCTargetDesc/HexagonBaseInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include "llvm/CodeGen/ValueTypes.h" 22 #include "llvm/Support/MachineValueType.h" 23 #include <cstdint> 24 #include <vector> 25 26 #define GET_INSTRINFO_HEADER 27 #include "HexagonGenInstrInfo.inc" 28 29 namespace llvm { 30 31 class HexagonSubtarget; 32 class MachineBranchProbabilityInfo; 33 class MachineFunction; 34 class MachineInstr; 35 class MachineOperand; 36 class TargetRegisterInfo; 37 38 class HexagonInstrInfo : public HexagonGenInstrInfo { 39 const HexagonSubtarget &Subtarget; 40 41 enum BundleAttribute { 42 memShufDisabledMask = 0x4 43 }; 44 45 virtual void anchor(); 46 47 public: 48 explicit HexagonInstrInfo(HexagonSubtarget &ST); 49 50 /// TargetInstrInfo overrides. 51 52 /// If the specified machine instruction is a direct 53 /// load from a stack slot, return the virtual or physical register number of 54 /// the destination along with the FrameIndex of the loaded stack slot. If 55 /// not, return 0. This predicate must return 0 if the instruction has 56 /// any side effects other than loading from the stack slot. 57 unsigned isLoadFromStackSlot(const MachineInstr &MI, 58 int &FrameIndex) const override; 59 60 /// If the specified machine instruction is a direct 61 /// store to a stack slot, return the virtual or physical register number of 62 /// the source reg along with the FrameIndex of the loaded stack slot. If 63 /// not, return 0. This predicate must return 0 if the instruction has 64 /// any side effects other than storing to the stack slot. 65 unsigned isStoreToStackSlot(const MachineInstr &MI, 66 int &FrameIndex) const override; 67 68 /// Check if the instruction or the bundle of instructions has 69 /// load from stack slots. Return the frameindex and machine memory operand 70 /// if true. 71 bool hasLoadFromStackSlot( 72 const MachineInstr &MI, 73 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override; 74 75 /// Check if the instruction or the bundle of instructions has 76 /// store to stack slots. Return the frameindex and machine memory operand 77 /// if true. 78 bool hasStoreToStackSlot( 79 const MachineInstr &MI, 80 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override; 81 82 /// Analyze the branching code at the end of MBB, returning 83 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 84 /// implemented for a target). Upon success, this returns false and returns 85 /// with the following information in various cases: 86 /// 87 /// 1. If this block ends with no branches (it just falls through to its succ) 88 /// just return false, leaving TBB/FBB null. 89 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 90 /// the destination block. 91 /// 3. If this block ends with a conditional branch and it falls through to a 92 /// successor block, it sets TBB to be the branch destination block and a 93 /// list of operands that evaluate the condition. These operands can be 94 /// passed to other TargetInstrInfo methods to create new branches. 95 /// 4. If this block ends with a conditional branch followed by an 96 /// unconditional branch, it returns the 'true' destination in TBB, the 97 /// 'false' destination in FBB, and a list of operands that evaluate the 98 /// condition. These operands can be passed to other TargetInstrInfo 99 /// methods to create new branches. 100 /// 101 /// Note that removeBranch and insertBranch must be implemented to support 102 /// cases where this method returns success. 103 /// 104 /// If AllowModify is true, then this routine is allowed to modify the basic 105 /// block (e.g. delete instructions after the unconditional branch). 106 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 107 MachineBasicBlock *&FBB, 108 SmallVectorImpl<MachineOperand> &Cond, 109 bool AllowModify) const override; 110 111 /// Remove the branching code at the end of the specific MBB. 112 /// This is only invoked in cases where analyzeBranch returns success. It 113 /// returns the number of instructions that were removed. 114 unsigned removeBranch(MachineBasicBlock &MBB, 115 int *BytesRemoved = nullptr) const override; 116 117 /// Insert branch code into the end of the specified MachineBasicBlock. 118 /// The operands to this method are the same as those 119 /// returned by analyzeBranch. This is only invoked in cases where 120 /// analyzeBranch returns success. It returns the number of instructions 121 /// inserted. 122 /// 123 /// It is also invoked by tail merging to add unconditional branches in 124 /// cases where analyzeBranch doesn't apply because there was no original 125 /// branch to analyze. At least this much must be implemented, else tail 126 /// merging needs to be disabled. 127 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 128 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 129 const DebugLoc &DL, 130 int *BytesAdded = nullptr) const override; 131 132 /// Analyze loop L, which must be a single-basic-block loop, and if the 133 /// conditions can be understood enough produce a PipelinerLoopInfo object. 134 std::unique_ptr<PipelinerLoopInfo> 135 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 136 137 /// Return true if it's profitable to predicate 138 /// instructions with accumulated instruction latency of "NumCycles" 139 /// of the specified basic block, where the probability of the instructions 140 /// being executed is given by Probability, and Confidence is a measure 141 /// of our confidence that it will be properly predicted. 142 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 143 unsigned ExtraPredCycles, 144 BranchProbability Probability) const override; 145 146 /// Second variant of isProfitableToIfCvt. This one 147 /// checks for the case where two basic blocks from true and false path 148 /// of a if-then-else (diamond) are predicated on mutally exclusive 149 /// predicates, where the probability of the true path being taken is given 150 /// by Probability, and Confidence is a measure of our confidence that it 151 /// will be properly predicted. 152 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 153 unsigned NumTCycles, unsigned ExtraTCycles, 154 MachineBasicBlock &FMBB, 155 unsigned NumFCycles, unsigned ExtraFCycles, 156 BranchProbability Probability) const override; 157 158 /// Return true if it's profitable for if-converter to duplicate instructions 159 /// of specified accumulated instruction latencies in the specified MBB to 160 /// enable if-conversion. 161 /// The probability of the instructions being executed is given by 162 /// Probability, and Confidence is a measure of our confidence that it 163 /// will be properly predicted. 164 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 165 BranchProbability Probability) const override; 166 167 /// Emit instructions to copy a pair of physical registers. 168 /// 169 /// This function should support copies within any legal register class as 170 /// well as any cross-class copies created during instruction selection. 171 /// 172 /// The source and destination registers may overlap, which may require a 173 /// careful implementation when multiple copy instructions are required for 174 /// large registers. See for example the ARM target. 175 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 176 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 177 bool KillSrc) const override; 178 179 /// Store the specified register of the given register class to the specified 180 /// stack frame index. The store instruction is to be added to the given 181 /// machine basic block before the specified machine instruction. If isKill 182 /// is true, the register operand is the last use and must be marked kill. 183 void storeRegToStackSlot(MachineBasicBlock &MBB, 184 MachineBasicBlock::iterator MBBI, 185 Register SrcReg, bool isKill, int FrameIndex, 186 const TargetRegisterClass *RC, 187 const TargetRegisterInfo *TRI) const override; 188 189 /// Load the specified register of the given register class from the specified 190 /// stack frame index. The load instruction is to be added to the given 191 /// machine basic block before the specified machine instruction. 192 void loadRegFromStackSlot(MachineBasicBlock &MBB, 193 MachineBasicBlock::iterator MBBI, 194 Register DestReg, int FrameIndex, 195 const TargetRegisterClass *RC, 196 const TargetRegisterInfo *TRI) const override; 197 198 /// This function is called for all pseudo instructions 199 /// that remain after register allocation. Many pseudo instructions are 200 /// created to help register allocation. This is the place to convert them 201 /// into real instructions. The target can edit MI in place, or it can insert 202 /// new instructions and erase MI. The function should return true if 203 /// anything was changed. 204 bool expandPostRAPseudo(MachineInstr &MI) const override; 205 206 /// Get the base register and byte offset of a load/store instr. 207 bool getMemOperandsWithOffsetWidth( 208 const MachineInstr &LdSt, 209 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 210 bool &OffsetIsScalable, unsigned &Width, 211 const TargetRegisterInfo *TRI) const override; 212 213 /// Reverses the branch condition of the specified condition list, 214 /// returning false on success and true if it cannot be reversed. 215 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 216 const override; 217 218 /// Insert a noop into the instruction stream at the specified point. 219 void insertNoop(MachineBasicBlock &MBB, 220 MachineBasicBlock::iterator MI) const override; 221 222 /// Returns true if the instruction is already predicated. 223 bool isPredicated(const MachineInstr &MI) const override; 224 225 /// Return true for post-incremented instructions. 226 bool isPostIncrement(const MachineInstr &MI) const override; 227 228 /// Convert the instruction into a predicated instruction. 229 /// It returns true if the operation was successful. 230 bool PredicateInstruction(MachineInstr &MI, 231 ArrayRef<MachineOperand> Cond) const override; 232 233 /// Returns true if the first specified predicate 234 /// subsumes the second, e.g. GE subsumes GT. 235 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 236 ArrayRef<MachineOperand> Pred2) const override; 237 238 /// If the specified instruction defines any predicate 239 /// or condition code register(s) used for predication, returns true as well 240 /// as the definition predicate(s) by reference. 241 bool DefinesPredicate(MachineInstr &MI, 242 std::vector<MachineOperand> &Pred) const override; 243 244 /// Return true if the specified instruction can be predicated. 245 /// By default, this returns true for every instruction with a 246 /// PredicateOperand. 247 bool isPredicable(const MachineInstr &MI) const override; 248 249 /// Test if the given instruction should be considered a scheduling boundary. 250 /// This primarily includes labels and terminators. 251 bool isSchedulingBoundary(const MachineInstr &MI, 252 const MachineBasicBlock *MBB, 253 const MachineFunction &MF) const override; 254 255 /// Measure the specified inline asm to determine an approximation of its 256 /// length. 257 unsigned getInlineAsmLength( 258 const char *Str, 259 const MCAsmInfo &MAI, 260 const TargetSubtargetInfo *STI = nullptr) const override; 261 262 /// Allocate and return a hazard recognizer to use for this target when 263 /// scheduling the machine instructions after register allocation. 264 ScheduleHazardRecognizer* 265 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 266 const ScheduleDAG *DAG) const override; 267 268 /// For a comparison instruction, return the source registers 269 /// in SrcReg and SrcReg2 if having two register operands, and the value it 270 /// compares against in CmpValue. Return true if the comparison instruction 271 /// can be analyzed. 272 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 273 Register &SrcReg2, int &Mask, int &Value) const override; 274 275 /// Compute the instruction latency of a given instruction. 276 /// If the instruction has higher cost when predicated, it's returned via 277 /// PredCost. 278 unsigned getInstrLatency(const InstrItineraryData *ItinData, 279 const MachineInstr &MI, 280 unsigned *PredCost = nullptr) const override; 281 282 /// Create machine specific model for scheduling. 283 DFAPacketizer * 284 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override; 285 286 // Sometimes, it is possible for the target 287 // to tell, even without aliasing information, that two MIs access different 288 // memory addresses. This function returns true if two MIs access different 289 // memory addresses and false otherwise. 290 bool 291 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 292 const MachineInstr &MIb) const override; 293 294 /// For instructions with a base and offset, return the position of the 295 /// base register and offset operands. 296 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, 297 unsigned &OffsetPos) const override; 298 299 /// If the instruction is an increment of a constant value, return the amount. 300 bool getIncrementValue(const MachineInstr &MI, int &Value) const override; 301 302 /// getOperandLatency - Compute and return the use operand latency of a given 303 /// pair of def and use. 304 /// In most cases, the static scheduling itinerary was enough to determine the 305 /// operand latency. But it may not be possible for instructions with variable 306 /// number of defs / uses. 307 /// 308 /// This is a raw interface to the itinerary that may be directly overriden by 309 /// a target. Use computeOperandLatency to get the best estimate of latency. 310 int getOperandLatency(const InstrItineraryData *ItinData, 311 const MachineInstr &DefMI, unsigned DefIdx, 312 const MachineInstr &UseMI, 313 unsigned UseIdx) const override; 314 315 /// Decompose the machine operand's target flags into two values - the direct 316 /// target flag value and any of bit flags that are applied. 317 std::pair<unsigned, unsigned> 318 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 319 320 /// Return an array that contains the direct target flag values and their 321 /// names. 322 /// 323 /// MIR Serialization is able to serialize only the target flags that are 324 /// defined by this method. 325 ArrayRef<std::pair<unsigned, const char *>> 326 getSerializableDirectMachineOperandTargetFlags() const override; 327 328 /// Return an array that contains the bitmask target flag values and their 329 /// names. 330 /// 331 /// MIR Serialization is able to serialize only the target flags that are 332 /// defined by this method. 333 ArrayRef<std::pair<unsigned, const char *>> 334 getSerializableBitmaskMachineOperandTargetFlags() const override; 335 336 bool isTailCall(const MachineInstr &MI) const override; 337 338 /// HexagonInstrInfo specifics. 339 340 unsigned createVR(MachineFunction *MF, MVT VT) const; 341 MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, 342 MachineBasicBlock *TargetBB, 343 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 344 345 bool isAbsoluteSet(const MachineInstr &MI) const; 346 bool isAccumulator(const MachineInstr &MI) const; 347 bool isAddrModeWithOffset(const MachineInstr &MI) const; 348 bool isBaseImmOffset(const MachineInstr &MI) const; 349 bool isComplex(const MachineInstr &MI) const; 350 bool isCompoundBranchInstr(const MachineInstr &MI) const; 351 bool isConstExtended(const MachineInstr &MI) const; 352 bool isDeallocRet(const MachineInstr &MI) const; 353 bool isDependent(const MachineInstr &ProdMI, 354 const MachineInstr &ConsMI) const; 355 bool isDotCurInst(const MachineInstr &MI) const; 356 bool isDotNewInst(const MachineInstr &MI) const; 357 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const; 358 bool isEarlySourceInstr(const MachineInstr &MI) const; 359 bool isEndLoopN(unsigned Opcode) const; 360 bool isExpr(unsigned OpType) const; 361 bool isExtendable(const MachineInstr &MI) const; 362 bool isExtended(const MachineInstr &MI) const; 363 bool isFloat(const MachineInstr &MI) const; 364 bool isHVXMemWithAIndirect(const MachineInstr &I, 365 const MachineInstr &J) const; 366 bool isIndirectCall(const MachineInstr &MI) const; 367 bool isIndirectL4Return(const MachineInstr &MI) const; 368 bool isJumpR(const MachineInstr &MI) const; 369 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const; 370 bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, 371 const MachineInstr &ESMI) const; 372 bool isLateResultInstr(const MachineInstr &MI) const; 373 bool isLateSourceInstr(const MachineInstr &MI) const; 374 bool isLoopN(const MachineInstr &MI) const; 375 bool isMemOp(const MachineInstr &MI) const; 376 bool isNewValue(const MachineInstr &MI) const; 377 bool isNewValue(unsigned Opcode) const; 378 bool isNewValueInst(const MachineInstr &MI) const; 379 bool isNewValueJump(const MachineInstr &MI) const; 380 bool isNewValueJump(unsigned Opcode) const; 381 bool isNewValueStore(const MachineInstr &MI) const; 382 bool isNewValueStore(unsigned Opcode) const; 383 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const; 384 bool isPredicatedNew(const MachineInstr &MI) const; 385 bool isPredicatedNew(unsigned Opcode) const; 386 bool isPredicatedTrue(const MachineInstr &MI) const; 387 bool isPredicatedTrue(unsigned Opcode) const; 388 bool isPredicated(unsigned Opcode) const; 389 bool isPredicateLate(unsigned Opcode) const; 390 bool isPredictedTaken(unsigned Opcode) const; 391 bool isPureSlot0(const MachineInstr &MI) const; 392 bool isRestrictNoSlot1Store(const MachineInstr &MI) const; 393 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const; 394 bool isSignExtendingLoad(const MachineInstr &MI) const; 395 bool isSolo(const MachineInstr &MI) const; 396 bool isSpillPredRegOp(const MachineInstr &MI) const; 397 bool isTC1(const MachineInstr &MI) const; 398 bool isTC2(const MachineInstr &MI) const; 399 bool isTC2Early(const MachineInstr &MI) const; 400 bool isTC4x(const MachineInstr &MI) const; 401 bool isToBeScheduledASAP(const MachineInstr &MI1, 402 const MachineInstr &MI2) const; 403 bool isHVXVec(const MachineInstr &MI) const; 404 bool isValidAutoIncImm(const EVT VT, const int Offset) const; 405 bool isValidOffset(unsigned Opcode, int Offset, 406 const TargetRegisterInfo *TRI, bool Extend = true) const; 407 bool isVecAcc(const MachineInstr &MI) const; 408 bool isVecALU(const MachineInstr &MI) const; 409 bool isVecUsableNextPacket(const MachineInstr &ProdMI, 410 const MachineInstr &ConsMI) const; 411 bool isZeroExtendingLoad(const MachineInstr &MI) const; 412 413 bool addLatencyToSchedule(const MachineInstr &MI1, 414 const MachineInstr &MI2) const; 415 bool canExecuteInBundle(const MachineInstr &First, 416 const MachineInstr &Second) const; 417 bool doesNotReturn(const MachineInstr &CallMI) const; 418 bool hasEHLabel(const MachineBasicBlock *B) const; 419 bool hasNonExtEquivalent(const MachineInstr &MI) const; 420 bool hasPseudoInstrPair(const MachineInstr &MI) const; 421 bool hasUncondBranch(const MachineBasicBlock *B) const; 422 bool mayBeCurLoad(const MachineInstr &MI) const; 423 bool mayBeNewStore(const MachineInstr &MI) const; 424 bool producesStall(const MachineInstr &ProdMI, 425 const MachineInstr &ConsMI) const; 426 bool producesStall(const MachineInstr &MI, 427 MachineBasicBlock::const_instr_iterator MII) const; 428 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const; 429 bool PredOpcodeHasJMP_c(unsigned Opcode) const; 430 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const; 431 432 unsigned getAddrMode(const MachineInstr &MI) const; 433 MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, 434 unsigned &AccessSize) const; 435 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const; 436 unsigned getCExtOpNum(const MachineInstr &MI) const; 437 HexagonII::CompoundGroup 438 getCompoundCandidateGroup(const MachineInstr &MI) const; 439 unsigned getCompoundOpcode(const MachineInstr &GA, 440 const MachineInstr &GB) const; 441 int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const; 442 int getCondOpcode(int Opc, bool sense) const; 443 int getDotCurOp(const MachineInstr &MI) const; 444 int getNonDotCurOp(const MachineInstr &MI) const; 445 int getDotNewOp(const MachineInstr &MI) const; 446 int getDotNewPredJumpOp(const MachineInstr &MI, 447 const MachineBranchProbabilityInfo *MBPI) const; 448 int getDotNewPredOp(const MachineInstr &MI, 449 const MachineBranchProbabilityInfo *MBPI) const; 450 int getDotOldOp(const MachineInstr &MI) const; 451 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) 452 const; 453 short getEquivalentHWInstr(const MachineInstr &MI) const; 454 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, 455 const MachineInstr &MI) const; 456 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const; 457 unsigned getInvertedPredicatedOpcode(const int Opc) const; 458 int getMaxValue(const MachineInstr &MI) const; 459 unsigned getMemAccessSize(const MachineInstr &MI) const; 460 int getMinValue(const MachineInstr &MI) const; 461 short getNonExtOpcode(const MachineInstr &MI) const; 462 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg, 463 unsigned &PredRegPos, unsigned &PredRegFlags) const; 464 short getPseudoInstrPair(const MachineInstr &MI) const; 465 short getRegForm(const MachineInstr &MI) const; 466 unsigned getSize(const MachineInstr &MI) const; 467 uint64_t getType(const MachineInstr &MI) const; 468 InstrStage::FuncUnits getUnits(const MachineInstr &MI) const; 469 470 MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const; 471 472 /// getInstrTimingClassLatency - Compute the instruction latency of a given 473 /// instruction using Timing Class information, if available. 474 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const; 475 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const; 476 477 void immediateExtend(MachineInstr &MI) const; 478 bool invertAndChangeJumpTarget(MachineInstr &MI, 479 MachineBasicBlock *NewTarget) const; 480 void genAllInsnTimingClasses(MachineFunction &MF) const; 481 bool reversePredSense(MachineInstr &MI) const; 482 unsigned reversePrediction(unsigned Opcode) const; 483 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const; 484 485 void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const; 486 bool getBundleNoShuf(const MachineInstr &MIB) const; 487 488 // When TinyCore with Duplexes is enabled, this function is used to translate 489 // tiny-instructions to big-instructions and vice versa to get the slot 490 // consumption. 491 void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, 492 bool ToBigInstrs) const; 493 void translateInstrsForDup(MachineFunction &MF, 494 bool ToBigInstrs = true) const; 495 void translateInstrsForDup(MachineBasicBlock::instr_iterator MII, 496 bool ToBigInstrs) const; 497 498 // Addressing mode relations. 499 short changeAddrMode_abs_io(short Opc) const; 500 short changeAddrMode_io_abs(short Opc) const; 501 short changeAddrMode_io_pi(short Opc) const; 502 short changeAddrMode_io_rr(short Opc) const; 503 short changeAddrMode_pi_io(short Opc) const; 504 short changeAddrMode_rr_io(short Opc) const; 505 short changeAddrMode_rr_ur(short Opc) const; 506 short changeAddrMode_ur_rr(short Opc) const; 507 508 short changeAddrMode_abs_io(const MachineInstr &MI) const { 509 return changeAddrMode_abs_io(MI.getOpcode()); 510 } 511 short changeAddrMode_io_abs(const MachineInstr &MI) const { 512 return changeAddrMode_io_abs(MI.getOpcode()); 513 } 514 short changeAddrMode_io_rr(const MachineInstr &MI) const { 515 return changeAddrMode_io_rr(MI.getOpcode()); 516 } 517 short changeAddrMode_rr_io(const MachineInstr &MI) const { 518 return changeAddrMode_rr_io(MI.getOpcode()); 519 } 520 short changeAddrMode_rr_ur(const MachineInstr &MI) const { 521 return changeAddrMode_rr_ur(MI.getOpcode()); 522 } 523 short changeAddrMode_ur_rr(const MachineInstr &MI) const { 524 return changeAddrMode_ur_rr(MI.getOpcode()); 525 } 526 }; 527 528 } // end namespace llvm 529 530 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 531