xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrFormats.td (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5)
1//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// Addressing modes for load/store instructions
10class AddrModeType<bits<3> value> {
11  bits<3> Value = value;
12}
13
14def NoAddrMode     : AddrModeType<0>;  // No addressing mode
15def Absolute       : AddrModeType<1>;  // Absolute addressing mode
16def AbsoluteSet    : AddrModeType<2>;  // Absolute set addressing mode
17def BaseImmOffset  : AddrModeType<3>;  // Indirect with offset
18def BaseLongOffset : AddrModeType<4>;  // Indirect with long offset
19def BaseRegOffset  : AddrModeType<5>;  // Indirect with register offset
20def PostInc        : AddrModeType<6>;  // Post increment addressing mode
21
22class MemAccessSize<bits<4> value> {
23  bits<4> Value = value;
24}
25
26// These numbers must match the MemAccessSize enumeration values in
27// HexagonBaseInfo.h.
28def NoMemAccess      : MemAccessSize<0>;
29def ByteAccess       : MemAccessSize<1>;
30def HalfWordAccess   : MemAccessSize<2>;
31def WordAccess       : MemAccessSize<3>;
32def DoubleWordAccess : MemAccessSize<4>;
33def HVXVectorAccess  : MemAccessSize<5>;
34
35
36//===----------------------------------------------------------------------===//
37//                         Instruction Class Declaration +
38//===----------------------------------------------------------------------===//
39
40// "Parse" bits are explicitly NOT defined in the opcode space to prevent
41//  TableGen from using them for generation of the decoder tables.
42class OpcodeHexagon {
43  field bits<32> Inst = ?; // Default to an invalid insn.
44  bits<4> IClass = 0; // ICLASS
45  bits<1> zero = 0;
46
47  let Inst{31-28} = IClass;
48}
49
50class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
51                  string cstr, InstrItinClass itin, IType type>
52  : Instruction {
53  let Namespace = "Hexagon";
54
55  dag OutOperandList = outs;
56  dag InOperandList = ins;
57  let AsmString = asmstr;
58  let Pattern = pattern;
59  let Constraints = cstr;
60  let Itinerary = itin;
61  let Size = 4;
62
63  // SoftFail is a field the disassembler can use to provide a way for
64  // instructions to not match without killing the whole decode process. It is
65  // mainly used for ARM, but Tablegen expects this field to exist or it fails
66  // to build the decode table.
67  field bits<32> SoftFail = 0;
68
69  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
70
71  // Instruction type according to the ISA.
72  IType Type = type;
73  let TSFlags{6-0} = Type.Value;
74
75  // Solo instructions, i.e., those that cannot be in a packet with others.
76  bits<1> isSolo = 0;
77  let TSFlags{7} = isSolo;
78  // Packed only with A or X-type instructions.
79  bits<1> isSoloAX = 0;
80  let TSFlags{8} = isSoloAX;
81  // Restricts slot 1 to ALU-only instructions.
82  bits<1> isRestrictSlot1AOK = 0;
83  let TSFlags{9} = isRestrictSlot1AOK;
84
85  // Predicated instructions.
86  bits<1> isPredicated = 0;
87  let TSFlags{10} = isPredicated;
88  bits<1> isPredicatedFalse = 0;
89  let TSFlags{11} = isPredicatedFalse;
90  bits<1> isPredicatedNew = 0;
91  let TSFlags{12} = isPredicatedNew;
92  bits<1> isPredicateLate = 0;
93  let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
94
95  // New-value insn helper fields.
96  bits<1> isNewValue = 0;
97  let TSFlags{14} = isNewValue; // New-value consumer insn.
98  bits<1> hasNewValue = 0;
99  let TSFlags{15} = hasNewValue; // New-value producer insn.
100  bits<3> opNewValue = 0;
101  let TSFlags{18-16} = opNewValue; // New-value produced operand.
102  bits<1> isNVStorable = 0;
103  let TSFlags{19} = isNVStorable; // Store that can become new-value store.
104  bits<1> isNVStore = 0;
105  let TSFlags{20} = isNVStore; // New-value store insn.
106  bits<1> isCVLoadable = 0;
107  let TSFlags{21} = isCVLoadable; // Load that can become cur-value load.
108  bits<1> isCVLoad = 0;
109  let TSFlags{22} = isCVLoad; // Cur-value load insn.
110
111  // Immediate extender helper fields.
112  bits<1> isExtendable = 0;
113  let TSFlags{23} = isExtendable; // Insn may be extended.
114  bits<1> isExtended = 0;
115  let TSFlags{24} = isExtended; // Insn must be extended.
116  bits<3> opExtendable = 0;
117  let TSFlags{27-25} = opExtendable; // Which operand may be extended.
118  bits<1> isExtentSigned = 0;
119  let TSFlags{28} = isExtentSigned; // Signed or unsigned range.
120  bits<5> opExtentBits = 0;
121  let TSFlags{33-29} = opExtentBits; //Number of bits of range before extending.
122  bits<2> opExtentAlign = 0;
123  let TSFlags{35-34} = opExtentAlign; // Alignment exponent before extending.
124
125  bit cofMax1 = 0;
126  let TSFlags{36} = cofMax1;
127  bit cofRelax1 = 0;
128  let TSFlags{37} = cofRelax1;
129  bit cofRelax2 = 0;
130  let TSFlags{38} = cofRelax2;
131
132  bit isRestrictNoSlot1Store = 0;
133  let TSFlags{39} = isRestrictNoSlot1Store;
134
135  // Addressing mode for load/store instructions.
136  AddrModeType addrMode = NoAddrMode;
137  let TSFlags{44-42} = addrMode.Value;
138
139  // Memory access size for mem access instructions (load/store)
140  MemAccessSize accessSize = NoMemAccess;
141  let TSFlags{48-45} = accessSize.Value;
142
143  bits<1> isTaken = 0;
144  let TSFlags {49} = isTaken; // Branch prediction.
145
146  bits<1> isFP = 0;
147  let TSFlags {50} = isFP; // Floating-point.
148
149  bits<1> hasNewValue2 = 0;
150  let TSFlags{52} = hasNewValue2; // Second New-value producer insn.
151  bits<3> opNewValue2 = 0;
152  let TSFlags{55-53} = opNewValue2; // Second New-value produced operand.
153
154  bits<1> isAccumulator = 0;
155  let TSFlags{56} = isAccumulator;
156
157  bits<1> prefersSlot3 = 0;
158  let TSFlags{57} = prefersSlot3; // Complex XU
159
160  bits<1> hasHvxTmp = 0;
161  let TSFlags{60} = hasHvxTmp;  // vector register vX.tmp false-write
162
163  bit CVINew = 0;
164  let TSFlags{62} = CVINew;
165
166  bit isCVI = 0;
167  let TSFlags{63} = isCVI;
168
169  // Fields used for relation models.
170  bit isNonTemporal = 0;
171  string isNT = ""; // set to "true" for non-temporal vector stores.
172  string BaseOpcode = "";
173  string CextOpcode = "";
174  string PredSense = "";
175  string PNewValue = "";
176  string NValueST  = "";    // Set to "true" for new-value stores.
177  string InputType = "";    // Input is "imm" or "reg" type.
178  string isFloat = "false"; // Set to "true" for the floating-point load/store.
179  string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
180
181  let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
182                                    "");
183  let PNewValue = !if(isPredicatedNew, "new", "");
184  let NValueST = !if(isNVStore, "true", "false");
185  let isNT = !if(isNonTemporal, "true", "false");
186
187  let hasSideEffects = 0;
188  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
189}
190
191class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
192      InstHexagon<outs, ins, asmstr, [], "", itin, type>;
193
194//===----------------------------------------------------------------------===//
195//                         Instruction Classes Definitions +
196//===----------------------------------------------------------------------===//
197
198let mayLoad = 1 in
199class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
200             string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
201  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
202
203class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
204             string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
205  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
206
207let mayStore = 1 in
208class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
209             string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
210  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
211
212let isCodeGenOnly = 1, isPseudo = 1 in
213class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
214              string cstr = "", InstrItinClass itin = tc_ENDLOOP>
215  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
216    OpcodeHexagon;
217
218let isCodeGenOnly = 1, isPseudo = 1 in
219class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
220             string cstr = "">
221  : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
222    OpcodeHexagon;
223
224let isCodeGenOnly = 1, isPseudo = 1 in
225class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
226              string cstr="">
227  : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
228    OpcodeHexagon;
229
230//===----------------------------------------------------------------------===//
231//                         Special Instructions -
232//===----------------------------------------------------------------------===//
233
234// The 'invalid_decode' instruction is used by the disassembler to
235// show an instruction that didn't decode correctly.  This feature
236// is only leveraged in a special disassembler mode that's activated
237// by a command line flag.
238def tc_invalid : InstrItinClass;
239class Enc_invalid : OpcodeHexagon {
240}
241def invalid_decode : HInst<
242(outs ),
243(ins ),
244"<invalid>",
245tc_invalid, TypeALU32_2op>, Enc_invalid {
246let Inst{13-0} = 0b00000000000000;
247let Inst{31-16} = 0b0000000000000000;
248let isCodeGenOnly = 1;
249}
250
251//===----------------------------------------------------------------------===//
252//                      Duplex Instruction Class Declaration
253//===----------------------------------------------------------------------===//
254
255class OpcodeDuplex {
256  field bits<32> Inst = ?; // Default to an invalid insn.
257  bits<4> IClass = 0; // ICLASS
258  bits<13> ISubHi = 0; // Low sub-insn
259  bits<13> ISubLo = 0; // High sub-insn
260
261  let Inst{31-29} = IClass{3-1};
262  let Inst{13}    = IClass{0};
263  let Inst{15-14} = 0;
264  let Inst{28-16} = ISubHi;
265  let Inst{12-0}  = ISubLo;
266}
267
268class InstDuplex<bits<4> iClass, string cstr = "">
269  : Instruction, OpcodeDuplex {
270  let Namespace = "Hexagon";
271  IType Type = TypeDUPLEX;  // uses slot 0,1
272  let isCodeGenOnly = 1;
273  let hasSideEffects = 0;
274  dag OutOperandList = (outs);
275  dag InOperandList = (ins);
276  let IClass = iClass;
277  let Constraints = cstr;
278  let Itinerary = DUPLEX;
279  let Size = 4;
280
281  // SoftFail is a field the disassembler can use to provide a way for
282  // instructions to not match without killing the whole decode process. It is
283  // mainly used for ARM, but Tablegen expects this field to exist or it fails
284  // to build the decode table.
285  field bits<32> SoftFail = 0;
286
287  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
288
289  let TSFlags{6-0} = Type.Value;
290
291  // Predicated instructions.
292  bits<1> isPredicated = 0;
293  let TSFlags{7} = isPredicated;
294  bits<1> isPredicatedFalse = 0;
295  let TSFlags{8} = isPredicatedFalse;
296  bits<1> isPredicatedNew = 0;
297  let TSFlags{9} = isPredicatedNew;
298
299  // New-value insn helper fields.
300  bits<1> isNewValue = 0;
301  let TSFlags{10} = isNewValue; // New-value consumer insn.
302  bits<1> hasNewValue = 0;
303  let TSFlags{11} = hasNewValue; // New-value producer insn.
304  bits<3> opNewValue = 0;
305  let TSFlags{14-12} = opNewValue; // New-value produced operand.
306  bits<1> isNVStorable = 0;
307  let TSFlags{15} = isNVStorable; // Store that can become new-value store.
308  bits<1> isNVStore = 0;
309  let TSFlags{16} = isNVStore; // New-value store insn.
310
311  // Immediate extender helper fields.
312  bits<1> isExtendable = 0;
313  let TSFlags{17} = isExtendable; // Insn may be extended.
314  bits<1> isExtended = 0;
315  let TSFlags{18} = isExtended; // Insn must be extended.
316  bits<3> opExtendable = 0;
317  let TSFlags{21-19} = opExtendable; // Which operand may be extended.
318  bits<1> isExtentSigned = 0;
319  let TSFlags{22} = isExtentSigned; // Signed or unsigned range.
320  bits<5> opExtentBits = 0;
321  let TSFlags{27-23} = opExtentBits; //Number of bits of range before extending.
322  bits<2> opExtentAlign = 0;
323  let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending.
324}
325
326//===----------------------------------------------------------------------===//
327//                         Instruction Classes Definitions -
328//===----------------------------------------------------------------------===//
329
330include "HexagonInstrFormatsV60.td"
331include "HexagonInstrFormatsV65.td"
332