1//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Addressing modes for load/store instructions 10class AddrModeType<bits<3> value> { 11 bits<3> Value = value; 12} 13 14def NoAddrMode : AddrModeType<0>; // No addressing mode 15def Absolute : AddrModeType<1>; // Absolute addressing mode 16def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode 17def BaseImmOffset : AddrModeType<3>; // Indirect with offset 18def BaseLongOffset : AddrModeType<4>; // Indirect with long offset 19def BaseRegOffset : AddrModeType<5>; // Indirect with register offset 20def PostInc : AddrModeType<6>; // Post increment addressing mode 21 22class MemAccessSize<bits<4> value> { 23 bits<4> Value = value; 24} 25 26// These numbers must match the MemAccessSize enumeration values in 27// HexagonBaseInfo.h. 28def NoMemAccess : MemAccessSize<0>; 29def ByteAccess : MemAccessSize<1>; 30def HalfWordAccess : MemAccessSize<2>; 31def WordAccess : MemAccessSize<3>; 32def DoubleWordAccess : MemAccessSize<4>; 33def HVXVectorAccess : MemAccessSize<5>; 34 35 36//===----------------------------------------------------------------------===// 37// Instruction Class Declaration + 38//===----------------------------------------------------------------------===// 39 40class OpcodeHexagon { 41 field bits<32> Inst = ?; // Default to an invalid insn. 42 bits<4> IClass = 0; // ICLASS 43 bits<1> zero = 0; 44 45 let Inst{31-28} = IClass; 46} 47 48class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, 49 string cstr, InstrItinClass itin, IType type> 50 : Instruction { 51 let Namespace = "Hexagon"; 52 53 dag OutOperandList = outs; 54 dag InOperandList = ins; 55 let AsmString = asmstr; 56 let Pattern = pattern; 57 let Constraints = cstr; 58 let Itinerary = itin; 59 let Size = 4; 60 61 // SoftFail is a field the disassembler can use to provide a way for 62 // instructions to not match without killing the whole decode process. It is 63 // mainly used for ARM, but Tablegen expects this field to exist or it fails 64 // to build the decode table. 65 field bits<32> SoftFail = 0; 66 67 // *** Must match MCTargetDesc/HexagonBaseInfo.h *** 68 69 // Instruction type according to the ISA. 70 IType Type = type; 71 let TSFlags{6-0} = Type.Value; 72 73 // Solo instructions, i.e., those that cannot be in a packet with others. 74 bits<1> isSolo = 0; 75 let TSFlags{7} = isSolo; 76 // Packed only with A or X-type instructions. 77 bits<1> isSoloAX = 0; 78 let TSFlags{8} = isSoloAX; 79 // Restricts slot 1 to ALU-only instructions. 80 bits<1> isRestrictSlot1AOK = 0; 81 let TSFlags{9} = isRestrictSlot1AOK; 82 83 // Predicated instructions. 84 bits<1> isPredicated = 0; 85 let TSFlags{10} = isPredicated; 86 bits<1> isPredicatedFalse = 0; 87 let TSFlags{11} = isPredicatedFalse; 88 bits<1> isPredicatedNew = 0; 89 let TSFlags{12} = isPredicatedNew; 90 bits<1> isPredicateLate = 0; 91 let TSFlags{13} = isPredicateLate; // Late predicate producer insn. 92 93 // New-value insn helper fields. 94 bits<1> isNewValue = 0; 95 let TSFlags{14} = isNewValue; // New-value consumer insn. 96 bits<1> hasNewValue = 0; 97 let TSFlags{15} = hasNewValue; // New-value producer insn. 98 bits<3> opNewValue = 0; 99 let TSFlags{18-16} = opNewValue; // New-value produced operand. 100 bits<1> isNVStorable = 0; 101 let TSFlags{19} = isNVStorable; // Store that can become new-value store. 102 bits<1> isNVStore = 0; 103 let TSFlags{20} = isNVStore; // New-value store insn. 104 bits<1> isCVLoadable = 0; 105 let TSFlags{21} = isCVLoadable; // Load that can become cur-value load. 106 bits<1> isCVLoad = 0; 107 let TSFlags{22} = isCVLoad; // Cur-value load insn. 108 109 // Immediate extender helper fields. 110 bits<1> isExtendable = 0; 111 let TSFlags{23} = isExtendable; // Insn may be extended. 112 bits<1> isExtended = 0; 113 let TSFlags{24} = isExtended; // Insn must be extended. 114 bits<3> opExtendable = 0; 115 let TSFlags{27-25} = opExtendable; // Which operand may be extended. 116 bits<1> isExtentSigned = 0; 117 let TSFlags{28} = isExtentSigned; // Signed or unsigned range. 118 bits<5> opExtentBits = 0; 119 let TSFlags{33-29} = opExtentBits; //Number of bits of range before extending. 120 bits<2> opExtentAlign = 0; 121 let TSFlags{35-34} = opExtentAlign; // Alignment exponent before extending. 122 123 bit cofMax1 = 0; 124 let TSFlags{36} = cofMax1; 125 bit cofRelax1 = 0; 126 let TSFlags{37} = cofRelax1; 127 bit cofRelax2 = 0; 128 let TSFlags{38} = cofRelax2; 129 130 bit isRestrictNoSlot1Store = 0; 131 let TSFlags{39} = isRestrictNoSlot1Store; 132 133 // Addressing mode for load/store instructions. 134 AddrModeType addrMode = NoAddrMode; 135 let TSFlags{44-42} = addrMode.Value; 136 137 // Memory access size for mem access instructions (load/store) 138 MemAccessSize accessSize = NoMemAccess; 139 let TSFlags{48-45} = accessSize.Value; 140 141 bits<1> isTaken = 0; 142 let TSFlags {49} = isTaken; // Branch prediction. 143 144 bits<1> isFP = 0; 145 let TSFlags {50} = isFP; // Floating-point. 146 147 bits<1> isSomeOK = 0; 148 let TSFlags {51} = isSomeOK; // Relax some grouping constraints. 149 150 bits<1> hasNewValue2 = 0; 151 let TSFlags{52} = hasNewValue2; // Second New-value producer insn. 152 bits<3> opNewValue2 = 0; 153 let TSFlags{55-53} = opNewValue2; // Second New-value produced operand. 154 155 bits<1> isAccumulator = 0; 156 let TSFlags{56} = isAccumulator; 157 158 bits<1> prefersSlot3 = 0; 159 let TSFlags{57} = prefersSlot3; // Complex XU 160 161 bits<1> hasTmpDst = 0; 162 let TSFlags{60} = hasTmpDst; // v65 : 'fake" register VTMP is set 163 164 bit CVINew = 0; 165 let TSFlags{62} = CVINew; 166 167 // Fields used for relation models. 168 bit isNonTemporal = 0; 169 string isNT = ""; // set to "true" for non-temporal vector stores. 170 string BaseOpcode = ""; 171 string CextOpcode = ""; 172 string PredSense = ""; 173 string PNewValue = ""; 174 string NValueST = ""; // Set to "true" for new-value stores. 175 string InputType = ""; // Input is "imm" or "reg" type. 176 string isFloat = "false"; // Set to "true" for the floating-point load/store. 177 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions 178 179 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"), 180 ""); 181 let PNewValue = !if(isPredicatedNew, "new", ""); 182 let NValueST = !if(isNVStore, "true", "false"); 183 let isNT = !if(isNonTemporal, "true", "false"); 184 185 let hasSideEffects = 0; 186 // *** Must match MCTargetDesc/HexagonBaseInfo.h *** 187} 188 189class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> : 190 InstHexagon<outs, ins, asmstr, [], "", itin, type>; 191 192//===----------------------------------------------------------------------===// 193// Instruction Classes Definitions + 194//===----------------------------------------------------------------------===// 195 196let mayLoad = 1 in 197class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 198 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> 199 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; 200 201class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 202 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> 203 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; 204 205let mayStore = 1 in 206class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 207 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> 208 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon; 209 210let isCodeGenOnly = 1, isPseudo = 1 in 211class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [], 212 string cstr = "", InstrItinClass itin = tc_ENDLOOP> 213 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>, 214 OpcodeHexagon; 215 216let isCodeGenOnly = 1, isPseudo = 1 in 217class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [], 218 string cstr = ""> 219 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>, 220 OpcodeHexagon; 221 222let isCodeGenOnly = 1, isPseudo = 1 in 223class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], 224 string cstr=""> 225 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>, 226 OpcodeHexagon; 227 228//===----------------------------------------------------------------------===// 229// Instruction Classes Definitions - 230//===----------------------------------------------------------------------===// 231 232include "HexagonInstrFormatsV5.td" 233include "HexagonInstrFormatsV60.td" 234include "HexagonInstrFormatsV65.td" 235