xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonIICScalar.td (revision 02e9120893770924227138ba49df1edb3896112a)
1//===--- HexagonIICScalar.td ----------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// These itinerary class descriptions are based on the instruction timing
10// classes as per V62. Currently, they are just extracted from
11// HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
12
13class PseudoItin {
14  list<InstrItinData> PseudoItin_list = [
15    InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
16                          [1, 1, 1]>,
17    InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
18                            InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
19    InstrItinData<DUPLEX,  [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
20    InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
21  ];
22}
23
24class ScalarItin {
25  list<InstrItinData> ScalarItin_list = [
26    InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
27                                   [3, 1], [Hex_FWD, Hex_FWD]>,
28    InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
29                                   [1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
30  ];
31}
32