1 //===- HexagonExpandCondsets.cpp ------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 // Replace mux instructions with the corresponding legal instructions. 10 // It is meant to work post-SSA, but still on virtual registers. It was 11 // originally placed between register coalescing and machine instruction 12 // scheduler. 13 // In this place in the optimization sequence, live interval analysis had 14 // been performed, and the live intervals should be preserved. A large part 15 // of the code deals with preserving the liveness information. 16 // 17 // Liveness tracking aside, the main functionality of this pass is divided 18 // into two steps. The first step is to replace an instruction 19 // %0 = C2_mux %1, %2, %3 20 // with a pair of conditional transfers 21 // %0 = A2_tfrt %1, %2 22 // %0 = A2_tfrf %1, %3 23 // It is the intention that the execution of this pass could be terminated 24 // after this step, and the code generated would be functionally correct. 25 // 26 // If the uses of the source values %1 and %2 are kills, and their 27 // definitions are predicable, then in the second step, the conditional 28 // transfers will then be rewritten as predicated instructions. E.g. 29 // %0 = A2_or %1, %2 30 // %3 = A2_tfrt %99, killed %0 31 // will be rewritten as 32 // %3 = A2_port %99, %1, %2 33 // 34 // This replacement has two variants: "up" and "down". Consider this case: 35 // %0 = A2_or %1, %2 36 // ... [intervening instructions] ... 37 // %3 = A2_tfrt %99, killed %0 38 // variant "up": 39 // %3 = A2_port %99, %1, %2 40 // ... [intervening instructions, %0->vreg3] ... 41 // [deleted] 42 // variant "down": 43 // [deleted] 44 // ... [intervening instructions] ... 45 // %3 = A2_port %99, %1, %2 46 // 47 // Both, one or none of these variants may be valid, and checks are made 48 // to rule out inapplicable variants. 49 // 50 // As an additional optimization, before either of the two steps above is 51 // executed, the pass attempts to coalesce the target register with one of 52 // the source registers, e.g. given an instruction 53 // %3 = C2_mux %0, %1, %2 54 // %3 will be coalesced with either %1 or %2. If this succeeds, 55 // the instruction would then be (for example) 56 // %3 = C2_mux %0, %3, %2 57 // and, under certain circumstances, this could result in only one predicated 58 // instruction: 59 // %3 = A2_tfrf %0, %2 60 // 61 62 // Splitting a definition of a register into two predicated transfers 63 // creates a complication in liveness tracking. Live interval computation 64 // will see both instructions as actual definitions, and will mark the 65 // first one as dead. The definition is not actually dead, and this 66 // situation will need to be fixed. For example: 67 // dead %1 = A2_tfrt ... ; marked as dead 68 // %1 = A2_tfrf ... 69 // 70 // Since any of the individual predicated transfers may end up getting 71 // removed (in case it is an identity copy), some pre-existing def may 72 // be marked as dead after live interval recomputation: 73 // dead %1 = ... ; marked as dead 74 // ... 75 // %1 = A2_tfrf ... ; if A2_tfrt is removed 76 // This case happens if %1 was used as a source in A2_tfrt, which means 77 // that is it actually live at the A2_tfrf, and so the now dead definition 78 // of %1 will need to be updated to non-dead at some point. 79 // 80 // This issue could be remedied by adding implicit uses to the predicated 81 // transfers, but this will create a problem with subsequent predication, 82 // since the transfers will no longer be possible to reorder. To avoid 83 // that, the initial splitting will not add any implicit uses. These 84 // implicit uses will be added later, after predication. The extra price, 85 // however, is that finding the locations where the implicit uses need 86 // to be added, and updating the live ranges will be more involved. 87 88 #include "HexagonInstrInfo.h" 89 #include "HexagonRegisterInfo.h" 90 #include "llvm/ADT/DenseMap.h" 91 #include "llvm/ADT/SetVector.h" 92 #include "llvm/ADT/SmallVector.h" 93 #include "llvm/ADT/StringRef.h" 94 #include "llvm/CodeGen/LiveInterval.h" 95 #include "llvm/CodeGen/LiveIntervals.h" 96 #include "llvm/CodeGen/MachineBasicBlock.h" 97 #include "llvm/CodeGen/MachineDominators.h" 98 #include "llvm/CodeGen/MachineFunction.h" 99 #include "llvm/CodeGen/MachineFunctionPass.h" 100 #include "llvm/CodeGen/MachineInstr.h" 101 #include "llvm/CodeGen/MachineInstrBuilder.h" 102 #include "llvm/CodeGen/MachineOperand.h" 103 #include "llvm/CodeGen/MachineRegisterInfo.h" 104 #include "llvm/CodeGen/SlotIndexes.h" 105 #include "llvm/CodeGen/TargetRegisterInfo.h" 106 #include "llvm/CodeGen/TargetSubtargetInfo.h" 107 #include "llvm/IR/DebugLoc.h" 108 #include "llvm/IR/Function.h" 109 #include "llvm/InitializePasses.h" 110 #include "llvm/MC/LaneBitmask.h" 111 #include "llvm/Pass.h" 112 #include "llvm/Support/CommandLine.h" 113 #include "llvm/Support/Debug.h" 114 #include "llvm/Support/ErrorHandling.h" 115 #include "llvm/Support/raw_ostream.h" 116 #include <cassert> 117 #include <iterator> 118 #include <set> 119 #include <utility> 120 121 #define DEBUG_TYPE "expand-condsets" 122 123 using namespace llvm; 124 125 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit", 126 cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions")); 127 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit", 128 cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings")); 129 130 namespace llvm { 131 132 void initializeHexagonExpandCondsetsPass(PassRegistry&); 133 FunctionPass *createHexagonExpandCondsets(); 134 135 } // end namespace llvm 136 137 namespace { 138 139 class HexagonExpandCondsets : public MachineFunctionPass { 140 public: 141 static char ID; 142 143 HexagonExpandCondsets() : MachineFunctionPass(ID) { 144 if (OptCoaLimit.getPosition()) 145 CoaLimitActive = true, CoaLimit = OptCoaLimit; 146 if (OptTfrLimit.getPosition()) 147 TfrLimitActive = true, TfrLimit = OptTfrLimit; 148 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); 149 } 150 151 StringRef getPassName() const override { return "Hexagon Expand Condsets"; } 152 153 void getAnalysisUsage(AnalysisUsage &AU) const override { 154 AU.addRequired<LiveIntervals>(); 155 AU.addPreserved<LiveIntervals>(); 156 AU.addPreserved<SlotIndexes>(); 157 AU.addRequired<MachineDominatorTree>(); 158 AU.addPreserved<MachineDominatorTree>(); 159 MachineFunctionPass::getAnalysisUsage(AU); 160 } 161 162 bool runOnMachineFunction(MachineFunction &MF) override; 163 164 private: 165 const HexagonInstrInfo *HII = nullptr; 166 const TargetRegisterInfo *TRI = nullptr; 167 MachineDominatorTree *MDT; 168 MachineRegisterInfo *MRI = nullptr; 169 LiveIntervals *LIS = nullptr; 170 bool CoaLimitActive = false; 171 bool TfrLimitActive = false; 172 unsigned CoaLimit; 173 unsigned TfrLimit; 174 unsigned CoaCounter = 0; 175 unsigned TfrCounter = 0; 176 177 // FIXME: Consolidate duplicate definitions of RegisterRef 178 struct RegisterRef { 179 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()), 180 Sub(Op.getSubReg()) {} 181 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} 182 183 bool operator== (RegisterRef RR) const { 184 return Reg == RR.Reg && Sub == RR.Sub; 185 } 186 bool operator!= (RegisterRef RR) const { return !operator==(RR); } 187 bool operator< (RegisterRef RR) const { 188 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); 189 } 190 191 Register Reg; 192 unsigned Sub; 193 }; 194 195 using ReferenceMap = DenseMap<unsigned, unsigned>; 196 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) }; 197 enum { Exec_Then = 0x10, Exec_Else = 0x20 }; 198 199 unsigned getMaskForSub(unsigned Sub); 200 bool isCondset(const MachineInstr &MI); 201 LaneBitmask getLaneMask(Register Reg, unsigned Sub); 202 203 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec); 204 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec); 205 206 void updateDeadsInRange(Register Reg, LaneBitmask LM, LiveRange &Range); 207 void updateKillFlags(Register Reg); 208 void updateDeadFlags(Register Reg); 209 void recalculateLiveInterval(Register Reg); 210 void removeInstr(MachineInstr &MI); 211 void updateLiveness(std::set<Register> &RegSet, bool Recalc, 212 bool UpdateKills, bool UpdateDeads); 213 214 unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond); 215 MachineInstr *genCondTfrFor(MachineOperand &SrcOp, 216 MachineBasicBlock::iterator At, unsigned DstR, 217 unsigned DstSR, const MachineOperand &PredOp, bool PredSense, 218 bool ReadUndef, bool ImpUse); 219 bool split(MachineInstr &MI, std::set<Register> &UpdRegs); 220 221 bool isPredicable(MachineInstr *MI); 222 MachineInstr *getReachingDefForPred(RegisterRef RD, 223 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond); 224 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses); 225 bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown); 226 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI, 227 MachineBasicBlock::iterator Where, 228 const MachineOperand &PredOp, bool Cond, 229 std::set<Register> &UpdRegs); 230 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR, 231 bool Cond, MachineBasicBlock::iterator First, 232 MachineBasicBlock::iterator Last); 233 bool predicate(MachineInstr &TfrI, bool Cond, std::set<Register> &UpdRegs); 234 bool predicateInBlock(MachineBasicBlock &B, std::set<Register> &UpdRegs); 235 236 bool isIntReg(RegisterRef RR, unsigned &BW); 237 bool isIntraBlocks(LiveInterval &LI); 238 bool coalesceRegisters(RegisterRef R1, RegisterRef R2); 239 bool coalesceSegments(const SmallVectorImpl<MachineInstr *> &Condsets, 240 std::set<Register> &UpdRegs); 241 }; 242 243 } // end anonymous namespace 244 245 char HexagonExpandCondsets::ID = 0; 246 247 namespace llvm { 248 249 char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID; 250 251 } // end namespace llvm 252 253 INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets", 254 "Hexagon Expand Condsets", false, false) 255 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 256 INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 257 INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 258 INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets", 259 "Hexagon Expand Condsets", false, false) 260 261 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) { 262 switch (Sub) { 263 case Hexagon::isub_lo: 264 case Hexagon::vsub_lo: 265 return Sub_Low; 266 case Hexagon::isub_hi: 267 case Hexagon::vsub_hi: 268 return Sub_High; 269 case Hexagon::NoSubRegister: 270 return Sub_None; 271 } 272 llvm_unreachable("Invalid subregister"); 273 } 274 275 bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) { 276 unsigned Opc = MI.getOpcode(); 277 switch (Opc) { 278 case Hexagon::C2_mux: 279 case Hexagon::C2_muxii: 280 case Hexagon::C2_muxir: 281 case Hexagon::C2_muxri: 282 case Hexagon::PS_pselect: 283 return true; 284 break; 285 } 286 return false; 287 } 288 289 LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) { 290 assert(Reg.isVirtual()); 291 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) 292 : MRI->getMaxLaneMaskForVReg(Reg); 293 } 294 295 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, 296 unsigned Exec) { 297 unsigned Mask = getMaskForSub(RR.Sub) | Exec; 298 ReferenceMap::iterator F = Map.find(RR.Reg); 299 if (F == Map.end()) 300 Map.insert(std::make_pair(RR.Reg, Mask)); 301 else 302 F->second |= Mask; 303 } 304 305 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map, 306 unsigned Exec) { 307 ReferenceMap::iterator F = Map.find(RR.Reg); 308 if (F == Map.end()) 309 return false; 310 unsigned Mask = getMaskForSub(RR.Sub) | Exec; 311 if (Mask & F->second) 312 return true; 313 return false; 314 } 315 316 void HexagonExpandCondsets::updateKillFlags(Register Reg) { 317 auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void { 318 // Set the <kill> flag on a use of Reg whose lane mask is contained in LM. 319 MachineInstr *MI = LIS->getInstructionFromIndex(K); 320 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 321 MachineOperand &Op = MI->getOperand(i); 322 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg || 323 MI->isRegTiedToDefOperand(i)) 324 continue; 325 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); 326 if ((SLM & LM) == SLM) { 327 // Only set the kill flag on the first encountered use of Reg in this 328 // instruction. 329 Op.setIsKill(true); 330 break; 331 } 332 } 333 }; 334 335 LiveInterval &LI = LIS->getInterval(Reg); 336 for (auto I = LI.begin(), E = LI.end(); I != E; ++I) { 337 if (!I->end.isRegister()) 338 continue; 339 // Do not mark the end of the segment as <kill>, if the next segment 340 // starts with a predicated instruction. 341 auto NextI = std::next(I); 342 if (NextI != E && NextI->start.isRegister()) { 343 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start); 344 if (HII->isPredicated(*DefI)) 345 continue; 346 } 347 bool WholeReg = true; 348 if (LI.hasSubRanges()) { 349 auto EndsAtI = [I] (LiveInterval::SubRange &S) -> bool { 350 LiveRange::iterator F = S.find(I->end); 351 return F != S.end() && I->end == F->end; 352 }; 353 // Check if all subranges end at I->end. If so, make sure to kill 354 // the whole register. 355 for (LiveInterval::SubRange &S : LI.subranges()) { 356 if (EndsAtI(S)) 357 KillAt(I->end, S.LaneMask); 358 else 359 WholeReg = false; 360 } 361 } 362 if (WholeReg) 363 KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg)); 364 } 365 } 366 367 void HexagonExpandCondsets::updateDeadsInRange(Register Reg, LaneBitmask LM, 368 LiveRange &Range) { 369 assert(Reg.isVirtual()); 370 if (Range.empty()) 371 return; 372 373 // Return two booleans: { def-modifes-reg, def-covers-reg }. 374 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> { 375 if (!Op.isReg() || !Op.isDef()) 376 return { false, false }; 377 Register DR = Op.getReg(), DSR = Op.getSubReg(); 378 if (!DR.isVirtual() || DR != Reg) 379 return { false, false }; 380 LaneBitmask SLM = getLaneMask(DR, DSR); 381 LaneBitmask A = SLM & LM; 382 return { A.any(), A == SLM }; 383 }; 384 385 // The splitting step will create pairs of predicated definitions without 386 // any implicit uses (since implicit uses would interfere with predication). 387 // This can cause the reaching defs to become dead after live range 388 // recomputation, even though they are not really dead. 389 // We need to identify predicated defs that need implicit uses, and 390 // dead defs that are not really dead, and correct both problems. 391 392 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs, 393 MachineBasicBlock *Dest) -> bool { 394 for (MachineBasicBlock *D : Defs) 395 if (D != Dest && MDT->dominates(D, Dest)) 396 return true; 397 398 MachineBasicBlock *Entry = &Dest->getParent()->front(); 399 SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end()); 400 for (unsigned i = 0; i < Work.size(); ++i) { 401 MachineBasicBlock *B = Work[i]; 402 if (Defs.count(B)) 403 continue; 404 if (B == Entry) 405 return false; 406 for (auto *P : B->predecessors()) 407 Work.insert(P); 408 } 409 return true; 410 }; 411 412 // First, try to extend live range within individual basic blocks. This 413 // will leave us only with dead defs that do not reach any predicated 414 // defs in the same block. 415 SetVector<MachineBasicBlock*> Defs; 416 SmallVector<SlotIndex,4> PredDefs; 417 for (auto &Seg : Range) { 418 if (!Seg.start.isRegister()) 419 continue; 420 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); 421 Defs.insert(DefI->getParent()); 422 if (HII->isPredicated(*DefI)) 423 PredDefs.push_back(Seg.start); 424 } 425 426 SmallVector<SlotIndex,8> Undefs; 427 LiveInterval &LI = LIS->getInterval(Reg); 428 LI.computeSubRangeUndefs(Undefs, LM, *MRI, *LIS->getSlotIndexes()); 429 430 for (auto &SI : PredDefs) { 431 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); 432 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI); 433 if (P.first != nullptr || P.second) 434 SI = SlotIndex(); 435 } 436 437 // Calculate reachability for those predicated defs that were not handled 438 // by the in-block extension. 439 SmallVector<SlotIndex,4> ExtTo; 440 for (auto &SI : PredDefs) { 441 if (!SI.isValid()) 442 continue; 443 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); 444 if (BB->pred_empty()) 445 continue; 446 // If the defs from this range reach SI via all predecessors, it is live. 447 // It can happen that SI is reached by the defs through some paths, but 448 // not all. In the IR coming into this optimization, SI would not be 449 // considered live, since the defs would then not jointly dominate SI. 450 // That means that SI is an overwriting def, and no implicit use is 451 // needed at this point. Do not add SI to the extension points, since 452 // extendToIndices will abort if there is no joint dominance. 453 // If the abort was avoided by adding extra undefs added to Undefs, 454 // extendToIndices could actually indicate that SI is live, contrary 455 // to the original IR. 456 if (Dominate(Defs, BB)) 457 ExtTo.push_back(SI); 458 } 459 460 if (!ExtTo.empty()) 461 LIS->extendToIndices(Range, ExtTo, Undefs); 462 463 // Remove <dead> flags from all defs that are not dead after live range 464 // extension, and collect all def operands. They will be used to generate 465 // the necessary implicit uses. 466 // At the same time, add <dead> flag to all defs that are actually dead. 467 // This can happen, for example, when a mux with identical inputs is 468 // replaced with a COPY: the use of the predicate register disappears and 469 // the dead can become dead. 470 std::set<RegisterRef> DefRegs; 471 for (auto &Seg : Range) { 472 if (!Seg.start.isRegister()) 473 continue; 474 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); 475 for (auto &Op : DefI->operands()) { 476 auto P = IsRegDef(Op); 477 if (P.second && Seg.end.isDead()) { 478 Op.setIsDead(true); 479 } else if (P.first) { 480 DefRegs.insert(Op); 481 Op.setIsDead(false); 482 } 483 } 484 } 485 486 // Now, add implicit uses to each predicated def that is reached 487 // by other defs. 488 for (auto &Seg : Range) { 489 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot())) 490 continue; 491 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); 492 if (!HII->isPredicated(*DefI)) 493 continue; 494 // Construct the set of all necessary implicit uses, based on the def 495 // operands in the instruction. We need to tie the implicit uses to 496 // the corresponding defs. 497 std::map<RegisterRef,unsigned> ImpUses; 498 for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) { 499 MachineOperand &Op = DefI->getOperand(i); 500 if (!Op.isReg() || !DefRegs.count(Op)) 501 continue; 502 if (Op.isDef()) { 503 // Tied defs will always have corresponding uses, so no extra 504 // implicit uses are needed. 505 if (!Op.isTied()) 506 ImpUses.insert({Op, i}); 507 } else { 508 // This function can be called for the same register with different 509 // lane masks. If the def in this instruction was for the whole 510 // register, we can get here more than once. Avoid adding multiple 511 // implicit uses (or adding an implicit use when an explicit one is 512 // present). 513 if (Op.isTied()) 514 ImpUses.erase(Op); 515 } 516 } 517 if (ImpUses.empty()) 518 continue; 519 MachineFunction &MF = *DefI->getParent()->getParent(); 520 for (std::pair<RegisterRef, unsigned> P : ImpUses) { 521 RegisterRef R = P.first; 522 MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub); 523 DefI->tieOperands(P.second, DefI->getNumOperands()-1); 524 } 525 } 526 } 527 528 void HexagonExpandCondsets::updateDeadFlags(Register Reg) { 529 LiveInterval &LI = LIS->getInterval(Reg); 530 if (LI.hasSubRanges()) { 531 for (LiveInterval::SubRange &S : LI.subranges()) { 532 updateDeadsInRange(Reg, S.LaneMask, S); 533 LIS->shrinkToUses(S, Reg); 534 } 535 LI.clear(); 536 LIS->constructMainRangeFromSubranges(LI); 537 } else { 538 updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI); 539 } 540 } 541 542 void HexagonExpandCondsets::recalculateLiveInterval(Register Reg) { 543 LIS->removeInterval(Reg); 544 LIS->createAndComputeVirtRegInterval(Reg); 545 } 546 547 void HexagonExpandCondsets::removeInstr(MachineInstr &MI) { 548 LIS->RemoveMachineInstrFromMaps(MI); 549 MI.eraseFromParent(); 550 } 551 552 void HexagonExpandCondsets::updateLiveness(std::set<Register> &RegSet, 553 bool Recalc, bool UpdateKills, 554 bool UpdateDeads) { 555 UpdateKills |= UpdateDeads; 556 for (Register R : RegSet) { 557 if (!R.isVirtual()) { 558 assert(R.isPhysical()); 559 // There shouldn't be any physical registers as operands, except 560 // possibly reserved registers. 561 assert(MRI->isReserved(R)); 562 continue; 563 } 564 if (Recalc) 565 recalculateLiveInterval(R); 566 if (UpdateKills) 567 MRI->clearKillFlags(R); 568 if (UpdateDeads) 569 updateDeadFlags(R); 570 // Fixing <dead> flags may extend live ranges, so reset <kill> flags 571 // after that. 572 if (UpdateKills) 573 updateKillFlags(R); 574 LIS->getInterval(R).verify(); 575 } 576 } 577 578 /// Get the opcode for a conditional transfer of the value in SO (source 579 /// operand). The condition (true/false) is given in Cond. 580 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO, 581 bool IfTrue) { 582 using namespace Hexagon; 583 584 if (SO.isReg()) { 585 MCRegister PhysR; 586 RegisterRef RS = SO; 587 if (RS.Reg.isVirtual()) { 588 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg); 589 assert(VC->begin() != VC->end() && "Empty register class"); 590 PhysR = *VC->begin(); 591 } else { 592 PhysR = RS.Reg; 593 } 594 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); 595 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); 596 switch (TRI->getRegSizeInBits(*RC)) { 597 case 32: 598 return IfTrue ? A2_tfrt : A2_tfrf; 599 case 64: 600 return IfTrue ? A2_tfrpt : A2_tfrpf; 601 } 602 llvm_unreachable("Invalid register operand"); 603 } 604 switch (SO.getType()) { 605 case MachineOperand::MO_Immediate: 606 case MachineOperand::MO_FPImmediate: 607 case MachineOperand::MO_ConstantPoolIndex: 608 case MachineOperand::MO_TargetIndex: 609 case MachineOperand::MO_JumpTableIndex: 610 case MachineOperand::MO_ExternalSymbol: 611 case MachineOperand::MO_GlobalAddress: 612 case MachineOperand::MO_BlockAddress: 613 return IfTrue ? C2_cmoveit : C2_cmoveif; 614 default: 615 break; 616 } 617 llvm_unreachable("Unexpected source operand"); 618 } 619 620 /// Generate a conditional transfer, copying the value SrcOp to the 621 /// destination register DstR:DstSR, and using the predicate register from 622 /// PredOp. The Cond argument specifies whether the predicate is to be 623 /// if(PredOp), or if(!PredOp). 624 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, 625 MachineBasicBlock::iterator At, 626 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, 627 bool PredSense, bool ReadUndef, bool ImpUse) { 628 MachineInstr *MI = SrcOp.getParent(); 629 MachineBasicBlock &B = *At->getParent(); 630 const DebugLoc &DL = MI->getDebugLoc(); 631 632 // Don't avoid identity copies here (i.e. if the source and the destination 633 // are the same registers). It is actually better to generate them here, 634 // since this would cause the copy to potentially be predicated in the next 635 // step. The predication will remove such a copy if it is unable to 636 /// predicate. 637 638 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); 639 unsigned DstState = RegState::Define | (ReadUndef ? RegState::Undef : 0); 640 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; 641 MachineInstrBuilder MIB; 642 643 if (SrcOp.isReg()) { 644 unsigned SrcState = getRegState(SrcOp); 645 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) 646 SrcState &= ~RegState::Kill; 647 MIB = BuildMI(B, At, DL, HII->get(Opc)) 648 .addReg(DstR, DstState, DstSR) 649 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) 650 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); 651 } else { 652 MIB = BuildMI(B, At, DL, HII->get(Opc)) 653 .addReg(DstR, DstState, DstSR) 654 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) 655 .add(SrcOp); 656 } 657 658 LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB); 659 return &*MIB; 660 } 661 662 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function 663 /// performs all necessary changes to complete the replacement. 664 bool HexagonExpandCondsets::split(MachineInstr &MI, 665 std::set<Register> &UpdRegs) { 666 if (TfrLimitActive) { 667 if (TfrCounter >= TfrLimit) 668 return false; 669 TfrCounter++; 670 } 671 LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) 672 << ": " << MI); 673 MachineOperand &MD = MI.getOperand(0); // Definition 674 MachineOperand &MP = MI.getOperand(1); // Predicate register 675 assert(MD.isDef()); 676 Register DR = MD.getReg(), DSR = MD.getSubReg(); 677 bool ReadUndef = MD.isUndef(); 678 MachineBasicBlock::iterator At = MI; 679 680 auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void { 681 for (auto &Op : MI.operands()) 682 if (Op.isReg()) 683 UpdRegs.insert(Op.getReg()); 684 }; 685 686 // If this is a mux of the same register, just replace it with COPY. 687 // Ideally, this would happen earlier, so that register coalescing would 688 // see it. 689 MachineOperand &ST = MI.getOperand(2); 690 MachineOperand &SF = MI.getOperand(3); 691 if (ST.isReg() && SF.isReg()) { 692 RegisterRef RT(ST); 693 if (RT == RegisterRef(SF)) { 694 // Copy regs to update first. 695 updateRegs(MI); 696 MI.setDesc(HII->get(TargetOpcode::COPY)); 697 unsigned S = getRegState(ST); 698 while (MI.getNumOperands() > 1) 699 MI.RemoveOperand(MI.getNumOperands()-1); 700 MachineFunction &MF = *MI.getParent()->getParent(); 701 MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub); 702 return true; 703 } 704 } 705 706 // First, create the two invididual conditional transfers, and add each 707 // of them to the live intervals information. Do that first and then remove 708 // the old instruction from live intervals. 709 MachineInstr *TfrT = 710 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false); 711 MachineInstr *TfrF = 712 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true); 713 LIS->InsertMachineInstrInMaps(*TfrT); 714 LIS->InsertMachineInstrInMaps(*TfrF); 715 716 // Will need to recalculate live intervals for all registers in MI. 717 updateRegs(MI); 718 719 removeInstr(MI); 720 return true; 721 } 722 723 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { 724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) 725 return false; 726 if (MI->hasUnmodeledSideEffects() || MI->mayStore()) 727 return false; 728 // Reject instructions with multiple defs (e.g. post-increment loads). 729 bool HasDef = false; 730 for (auto &Op : MI->operands()) { 731 if (!Op.isReg() || !Op.isDef()) 732 continue; 733 if (HasDef) 734 return false; 735 HasDef = true; 736 } 737 for (auto &Mo : MI->memoperands()) 738 if (Mo->isVolatile() || Mo->isAtomic()) 739 return false; 740 return true; 741 } 742 743 /// Find the reaching definition for a predicated use of RD. The RD is used 744 /// under the conditions given by PredR and Cond, and this function will ignore 745 /// definitions that set RD under the opposite conditions. 746 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD, 747 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { 748 MachineBasicBlock &B = *UseIt->getParent(); 749 MachineBasicBlock::iterator I = UseIt, S = B.begin(); 750 if (I == S) 751 return nullptr; 752 753 bool PredValid = true; 754 do { 755 --I; 756 MachineInstr *MI = &*I; 757 // Check if this instruction can be ignored, i.e. if it is predicated 758 // on the complementary condition. 759 if (PredValid && HII->isPredicated(*MI)) { 760 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI))) 761 continue; 762 } 763 764 // Check the defs. If the PredR is defined, invalidate it. If RD is 765 // defined, return the instruction or 0, depending on the circumstances. 766 for (auto &Op : MI->operands()) { 767 if (!Op.isReg() || !Op.isDef()) 768 continue; 769 RegisterRef RR = Op; 770 if (RR.Reg == PredR) { 771 PredValid = false; 772 continue; 773 } 774 if (RR.Reg != RD.Reg) 775 continue; 776 // If the "Reg" part agrees, there is still the subregister to check. 777 // If we are looking for %1:loreg, we can skip %1:hireg, but 778 // not %1 (w/o subregisters). 779 if (RR.Sub == RD.Sub) 780 return MI; 781 if (RR.Sub == 0 || RD.Sub == 0) 782 return nullptr; 783 // We have different subregisters, so we can continue looking. 784 } 785 } while (I != S); 786 787 return nullptr; 788 } 789 790 /// Check if the instruction MI can be safely moved over a set of instructions 791 /// whose side-effects (in terms of register defs and uses) are expressed in 792 /// the maps Defs and Uses. These maps reflect the conditional defs and uses 793 /// that depend on the same predicate register to allow moving instructions 794 /// over instructions predicated on the opposite condition. 795 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, 796 ReferenceMap &Uses) { 797 // In order to be able to safely move MI over instructions that define 798 // "Defs" and use "Uses", no def operand from MI can be defined or used 799 // and no use operand can be defined. 800 for (auto &Op : MI.operands()) { 801 if (!Op.isReg()) 802 continue; 803 RegisterRef RR = Op; 804 // For physical register we would need to check register aliases, etc. 805 // and we don't want to bother with that. It would be of little value 806 // before the actual register rewriting (from virtual to physical). 807 if (!RR.Reg.isVirtual()) 808 return false; 809 // No redefs for any operand. 810 if (isRefInMap(RR, Defs, Exec_Then)) 811 return false; 812 // For defs, there cannot be uses. 813 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) 814 return false; 815 } 816 return true; 817 } 818 819 /// Check if the instruction accessing memory (TheI) can be moved to the 820 /// location ToI. 821 bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI, 822 bool IsDown) { 823 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); 824 if (!IsLoad && !IsStore) 825 return true; 826 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI)) 827 return true; 828 if (TheI.hasUnmodeledSideEffects()) 829 return false; 830 831 MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI; 832 MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI; 833 bool Ordered = TheI.hasOrderedMemoryRef(); 834 835 // Search for aliased memory reference in (StartI, EndI). 836 for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) { 837 MachineInstr *MI = &*I; 838 if (MI->hasUnmodeledSideEffects()) 839 return false; 840 bool L = MI->mayLoad(), S = MI->mayStore(); 841 if (!L && !S) 842 continue; 843 if (Ordered && MI->hasOrderedMemoryRef()) 844 return false; 845 846 bool Conflict = (L && IsStore) || S; 847 if (Conflict) 848 return false; 849 } 850 return true; 851 } 852 853 /// Generate a predicated version of MI (where the condition is given via 854 /// PredR and Cond) at the point indicated by Where. 855 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp, 856 MachineInstr &MI, 857 MachineBasicBlock::iterator Where, 858 const MachineOperand &PredOp, bool Cond, 859 std::set<Register> &UpdRegs) { 860 // The problem with updating live intervals is that we can move one def 861 // past another def. In particular, this can happen when moving an A2_tfrt 862 // over an A2_tfrf defining the same register. From the point of view of 863 // live intervals, these two instructions are two separate definitions, 864 // and each one starts another live segment. LiveIntervals's "handleMove" 865 // does not allow such moves, so we need to handle it ourselves. To avoid 866 // invalidating liveness data while we are using it, the move will be 867 // implemented in 4 steps: (1) add a clone of the instruction MI at the 868 // target location, (2) update liveness, (3) delete the old instruction, 869 // and (4) update liveness again. 870 871 MachineBasicBlock &B = *MI.getParent(); 872 DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction. 873 unsigned Opc = MI.getOpcode(); 874 unsigned PredOpc = HII->getCondOpcode(Opc, !Cond); 875 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc)); 876 unsigned Ox = 0, NP = MI.getNumOperands(); 877 // Skip all defs from MI first. 878 while (Ox < NP) { 879 MachineOperand &MO = MI.getOperand(Ox); 880 if (!MO.isReg() || !MO.isDef()) 881 break; 882 Ox++; 883 } 884 // Add the new def, then the predicate register, then the rest of the 885 // operands. 886 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); 887 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, 888 PredOp.getSubReg()); 889 while (Ox < NP) { 890 MachineOperand &MO = MI.getOperand(Ox); 891 if (!MO.isReg() || !MO.isImplicit()) 892 MB.add(MO); 893 Ox++; 894 } 895 MB.cloneMemRefs(MI); 896 897 MachineInstr *NewI = MB; 898 NewI->clearKillInfo(); 899 LIS->InsertMachineInstrInMaps(*NewI); 900 901 for (auto &Op : NewI->operands()) 902 if (Op.isReg()) 903 UpdRegs.insert(Op.getReg()); 904 } 905 906 /// In the range [First, Last], rename all references to the "old" register RO 907 /// to the "new" register RN, but only in instructions predicated on the given 908 /// condition. 909 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, 910 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, 911 MachineBasicBlock::iterator Last) { 912 MachineBasicBlock::iterator End = std::next(Last); 913 for (MachineBasicBlock::iterator I = First; I != End; ++I) { 914 MachineInstr *MI = &*I; 915 // Do not touch instructions that are not predicated, or are predicated 916 // on the opposite condition. 917 if (!HII->isPredicated(*MI)) 918 continue; 919 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) 920 continue; 921 922 for (auto &Op : MI->operands()) { 923 if (!Op.isReg() || RO != RegisterRef(Op)) 924 continue; 925 Op.setReg(RN.Reg); 926 Op.setSubReg(RN.Sub); 927 // In practice, this isn't supposed to see any defs. 928 assert(!Op.isDef() && "Not expecting a def"); 929 } 930 } 931 } 932 933 /// For a given conditional copy, predicate the definition of the source of 934 /// the copy under the given condition (using the same predicate register as 935 /// the copy). 936 bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, 937 std::set<Register> &UpdRegs) { 938 // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi). 939 unsigned Opc = TfrI.getOpcode(); 940 (void)Opc; 941 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf); 942 LLVM_DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") 943 << ": " << TfrI); 944 945 MachineOperand &MD = TfrI.getOperand(0); 946 MachineOperand &MP = TfrI.getOperand(1); 947 MachineOperand &MS = TfrI.getOperand(2); 948 // The source operand should be a <kill>. This is not strictly necessary, 949 // but it makes things a lot simpler. Otherwise, we would need to rename 950 // some registers, which would complicate the transformation considerably. 951 if (!MS.isKill()) 952 return false; 953 // Avoid predicating instructions that define a subregister if subregister 954 // liveness tracking is not enabled. 955 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg())) 956 return false; 957 958 RegisterRef RT(MS); 959 Register PredR = MP.getReg(); 960 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); 961 if (!DefI || !isPredicable(DefI)) 962 return false; 963 964 LLVM_DEBUG(dbgs() << "Source def: " << *DefI); 965 966 // Collect the information about registers defined and used between the 967 // DefI and the TfrI. 968 // Map: reg -> bitmask of subregs 969 ReferenceMap Uses, Defs; 970 MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI; 971 972 // Check if the predicate register is valid between DefI and TfrI. 973 // If it is, we can then ignore instructions predicated on the negated 974 // conditions when collecting def and use information. 975 bool PredValid = true; 976 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) { 977 if (!I->modifiesRegister(PredR, nullptr)) 978 continue; 979 PredValid = false; 980 break; 981 } 982 983 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) { 984 MachineInstr *MI = &*I; 985 // If this instruction is predicated on the same register, it could 986 // potentially be ignored. 987 // By default assume that the instruction executes on the same condition 988 // as TfrI (Exec_Then), and also on the opposite one (Exec_Else). 989 unsigned Exec = Exec_Then | Exec_Else; 990 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR)) 991 Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else; 992 993 for (auto &Op : MI->operands()) { 994 if (!Op.isReg()) 995 continue; 996 // We don't want to deal with physical registers. The reason is that 997 // they can be aliased with other physical registers. Aliased virtual 998 // registers must share the same register number, and can only differ 999 // in the subregisters, which we are keeping track of. Physical 1000 // registers ters no longer have subregisters---their super- and 1001 // subregisters are other physical registers, and we are not checking 1002 // that. 1003 RegisterRef RR = Op; 1004 if (!RR.Reg.isVirtual()) 1005 return false; 1006 1007 ReferenceMap &Map = Op.isDef() ? Defs : Uses; 1008 if (Op.isDef() && Op.isUndef()) { 1009 assert(RR.Sub && "Expecting a subregister on <def,read-undef>"); 1010 // If this is a <def,read-undef>, then it invalidates the non-written 1011 // part of the register. For the purpose of checking the validity of 1012 // the move, assume that it modifies the whole register. 1013 RR.Sub = 0; 1014 } 1015 addRefToMap(RR, Map, Exec); 1016 } 1017 } 1018 1019 // The situation: 1020 // RT = DefI 1021 // ... 1022 // RD = TfrI ..., RT 1023 1024 // If the register-in-the-middle (RT) is used or redefined between 1025 // DefI and TfrI, we may not be able proceed with this transformation. 1026 // We can ignore a def that will not execute together with TfrI, and a 1027 // use that will. If there is such a use (that does execute together with 1028 // TfrI), we will not be able to move DefI down. If there is a use that 1029 // executed if TfrI's condition is false, then RT must be available 1030 // unconditionally (cannot be predicated). 1031 // Essentially, we need to be able to rename RT to RD in this segment. 1032 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else)) 1033 return false; 1034 RegisterRef RD = MD; 1035 // If the predicate register is defined between DefI and TfrI, the only 1036 // potential thing to do would be to move the DefI down to TfrI, and then 1037 // predicate. The reaching def (DefI) must be movable down to the location 1038 // of the TfrI. 1039 // If the target register of the TfrI (RD) is not used or defined between 1040 // DefI and TfrI, consider moving TfrI up to DefI. 1041 bool CanUp = canMoveOver(TfrI, Defs, Uses); 1042 bool CanDown = canMoveOver(*DefI, Defs, Uses); 1043 // The TfrI does not access memory, but DefI could. Check if it's safe 1044 // to move DefI down to TfrI. 1045 if (DefI->mayLoadOrStore()) 1046 if (!canMoveMemTo(*DefI, TfrI, true)) 1047 CanDown = false; 1048 1049 LLVM_DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no") 1050 << ", can move down: " << (CanDown ? "yes\n" : "no\n")); 1051 MachineBasicBlock::iterator PastDefIt = std::next(DefIt); 1052 if (CanUp) 1053 predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs); 1054 else if (CanDown) 1055 predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs); 1056 else 1057 return false; 1058 1059 if (RT != RD) { 1060 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt); 1061 UpdRegs.insert(RT.Reg); 1062 } 1063 1064 removeInstr(TfrI); 1065 removeInstr(*DefI); 1066 return true; 1067 } 1068 1069 /// Predicate all cases of conditional copies in the specified block. 1070 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B, 1071 std::set<Register> &UpdRegs) { 1072 bool Changed = false; 1073 MachineBasicBlock::iterator I, E, NextI; 1074 for (I = B.begin(), E = B.end(); I != E; I = NextI) { 1075 NextI = std::next(I); 1076 unsigned Opc = I->getOpcode(); 1077 if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) { 1078 bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs); 1079 if (!Done) { 1080 // If we didn't predicate I, we may need to remove it in case it is 1081 // an "identity" copy, e.g. %1 = A2_tfrt %2, %1. 1082 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) { 1083 for (auto &Op : I->operands()) 1084 if (Op.isReg()) 1085 UpdRegs.insert(Op.getReg()); 1086 removeInstr(*I); 1087 } 1088 } 1089 Changed |= Done; 1090 } 1091 } 1092 return Changed; 1093 } 1094 1095 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { 1096 if (!RR.Reg.isVirtual()) 1097 return false; 1098 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); 1099 if (RC == &Hexagon::IntRegsRegClass) { 1100 BW = 32; 1101 return true; 1102 } 1103 if (RC == &Hexagon::DoubleRegsRegClass) { 1104 BW = (RR.Sub != 0) ? 32 : 64; 1105 return true; 1106 } 1107 return false; 1108 } 1109 1110 bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) { 1111 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 1112 LiveRange::Segment &LR = *I; 1113 // Range must start at a register... 1114 if (!LR.start.isRegister()) 1115 return false; 1116 // ...and end in a register or in a dead slot. 1117 if (!LR.end.isRegister() && !LR.end.isDead()) 1118 return false; 1119 } 1120 return true; 1121 } 1122 1123 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { 1124 if (CoaLimitActive) { 1125 if (CoaCounter >= CoaLimit) 1126 return false; 1127 CoaCounter++; 1128 } 1129 unsigned BW1, BW2; 1130 if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2) 1131 return false; 1132 if (MRI->isLiveIn(R1.Reg)) 1133 return false; 1134 if (MRI->isLiveIn(R2.Reg)) 1135 return false; 1136 1137 LiveInterval &L1 = LIS->getInterval(R1.Reg); 1138 LiveInterval &L2 = LIS->getInterval(R2.Reg); 1139 if (L2.empty()) 1140 return false; 1141 if (L1.hasSubRanges() || L2.hasSubRanges()) 1142 return false; 1143 bool Overlap = L1.overlaps(L2); 1144 1145 LLVM_DEBUG(dbgs() << "compatible registers: (" 1146 << (Overlap ? "overlap" : "disjoint") << ")\n " 1147 << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " 1148 << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); 1149 if (R1.Sub || R2.Sub) 1150 return false; 1151 if (Overlap) 1152 return false; 1153 1154 // Coalescing could have a negative impact on scheduling, so try to limit 1155 // to some reasonable extent. Only consider coalescing segments, when one 1156 // of them does not cross basic block boundaries. 1157 if (!isIntraBlocks(L1) && !isIntraBlocks(L2)) 1158 return false; 1159 1160 MRI->replaceRegWith(R2.Reg, R1.Reg); 1161 1162 // Move all live segments from L2 to L1. 1163 using ValueInfoMap = DenseMap<VNInfo *, VNInfo *>; 1164 ValueInfoMap VM; 1165 for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) { 1166 VNInfo *NewVN, *OldVN = I->valno; 1167 ValueInfoMap::iterator F = VM.find(OldVN); 1168 if (F == VM.end()) { 1169 NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator()); 1170 VM.insert(std::make_pair(OldVN, NewVN)); 1171 } else { 1172 NewVN = F->second; 1173 } 1174 L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN)); 1175 } 1176 while (!L2.empty()) 1177 L2.removeSegment(*L2.begin()); 1178 LIS->removeInterval(R2.Reg); 1179 1180 updateKillFlags(R1.Reg); 1181 LLVM_DEBUG(dbgs() << "coalesced: " << L1 << "\n"); 1182 L1.verify(); 1183 1184 return true; 1185 } 1186 1187 /// Attempt to coalesce one of the source registers to a MUX instruction with 1188 /// the destination register. This could lead to having only one predicated 1189 /// instruction in the end instead of two. 1190 bool HexagonExpandCondsets::coalesceSegments( 1191 const SmallVectorImpl<MachineInstr *> &Condsets, 1192 std::set<Register> &UpdRegs) { 1193 SmallVector<MachineInstr*,16> TwoRegs; 1194 for (MachineInstr *MI : Condsets) { 1195 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3); 1196 if (!S1.isReg() && !S2.isReg()) 1197 continue; 1198 TwoRegs.push_back(MI); 1199 } 1200 1201 bool Changed = false; 1202 for (MachineInstr *CI : TwoRegs) { 1203 RegisterRef RD = CI->getOperand(0); 1204 RegisterRef RP = CI->getOperand(1); 1205 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3); 1206 bool Done = false; 1207 // Consider this case: 1208 // %1 = instr1 ... 1209 // %2 = instr2 ... 1210 // %0 = C2_mux ..., %1, %2 1211 // If %0 was coalesced with %1, we could end up with the following 1212 // code: 1213 // %0 = instr1 ... 1214 // %2 = instr2 ... 1215 // %0 = A2_tfrf ..., %2 1216 // which will later become: 1217 // %0 = instr1 ... 1218 // %0 = instr2_cNotPt ... 1219 // i.e. there will be an unconditional definition (instr1) of %0 1220 // followed by a conditional one. The output dependency was there before 1221 // and it unavoidable, but if instr1 is predicable, we will no longer be 1222 // able to predicate it here. 1223 // To avoid this scenario, don't coalesce the destination register with 1224 // a source register that is defined by a predicable instruction. 1225 if (S1.isReg()) { 1226 RegisterRef RS = S1; 1227 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true); 1228 if (!RDef || !HII->isPredicable(*RDef)) { 1229 Done = coalesceRegisters(RD, RegisterRef(S1)); 1230 if (Done) { 1231 UpdRegs.insert(RD.Reg); 1232 UpdRegs.insert(S1.getReg()); 1233 } 1234 } 1235 } 1236 if (!Done && S2.isReg()) { 1237 RegisterRef RS = S2; 1238 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false); 1239 if (!RDef || !HII->isPredicable(*RDef)) { 1240 Done = coalesceRegisters(RD, RegisterRef(S2)); 1241 if (Done) { 1242 UpdRegs.insert(RD.Reg); 1243 UpdRegs.insert(S2.getReg()); 1244 } 1245 } 1246 } 1247 Changed |= Done; 1248 } 1249 return Changed; 1250 } 1251 1252 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { 1253 if (skipFunction(MF.getFunction())) 1254 return false; 1255 1256 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo()); 1257 TRI = MF.getSubtarget().getRegisterInfo(); 1258 MDT = &getAnalysis<MachineDominatorTree>(); 1259 LIS = &getAnalysis<LiveIntervals>(); 1260 MRI = &MF.getRegInfo(); 1261 1262 LLVM_DEBUG(LIS->print(dbgs() << "Before expand-condsets\n", 1263 MF.getFunction().getParent())); 1264 1265 bool Changed = false; 1266 std::set<Register> CoalUpd, PredUpd; 1267 1268 SmallVector<MachineInstr*,16> Condsets; 1269 for (auto &B : MF) 1270 for (auto &I : B) 1271 if (isCondset(I)) 1272 Condsets.push_back(&I); 1273 1274 // Try to coalesce the target of a mux with one of its sources. 1275 // This could eliminate a register copy in some circumstances. 1276 Changed |= coalesceSegments(Condsets, CoalUpd); 1277 1278 // Update kill flags on all source operands. This is done here because 1279 // at this moment (when expand-condsets runs), there are no kill flags 1280 // in the IR (they have been removed by live range analysis). 1281 // Updating them right before we split is the easiest, because splitting 1282 // adds definitions which would interfere with updating kills afterwards. 1283 std::set<Register> KillUpd; 1284 for (MachineInstr *MI : Condsets) 1285 for (MachineOperand &Op : MI->operands()) 1286 if (Op.isReg() && Op.isUse()) 1287 if (!CoalUpd.count(Op.getReg())) 1288 KillUpd.insert(Op.getReg()); 1289 updateLiveness(KillUpd, false, true, false); 1290 LLVM_DEBUG( 1291 LIS->print(dbgs() << "After coalescing\n", MF.getFunction().getParent())); 1292 1293 // First, simply split all muxes into a pair of conditional transfers 1294 // and update the live intervals to reflect the new arrangement. The 1295 // goal is to update the kill flags, since predication will rely on 1296 // them. 1297 for (MachineInstr *MI : Condsets) 1298 Changed |= split(*MI, PredUpd); 1299 Condsets.clear(); // The contents of Condsets are invalid here anyway. 1300 1301 // Do not update live ranges after splitting. Recalculation of live 1302 // intervals removes kill flags, which were preserved by splitting on 1303 // the source operands of condsets. These kill flags are needed by 1304 // predication, and after splitting they are difficult to recalculate 1305 // (because of predicated defs), so make sure they are left untouched. 1306 // Predication does not use live intervals. 1307 LLVM_DEBUG( 1308 LIS->print(dbgs() << "After splitting\n", MF.getFunction().getParent())); 1309 1310 // Traverse all blocks and collapse predicable instructions feeding 1311 // conditional transfers into predicated instructions. 1312 // Walk over all the instructions again, so we may catch pre-existing 1313 // cases that were not created in the previous step. 1314 for (auto &B : MF) 1315 Changed |= predicateInBlock(B, PredUpd); 1316 LLVM_DEBUG(LIS->print(dbgs() << "After predicating\n", 1317 MF.getFunction().getParent())); 1318 1319 PredUpd.insert(CoalUpd.begin(), CoalUpd.end()); 1320 updateLiveness(PredUpd, true, true, true); 1321 1322 LLVM_DEBUG({ 1323 if (Changed) 1324 LIS->print(dbgs() << "After expand-condsets\n", 1325 MF.getFunction().getParent()); 1326 }); 1327 1328 return Changed; 1329 } 1330 1331 //===----------------------------------------------------------------------===// 1332 // Public Constructor Functions 1333 //===----------------------------------------------------------------------===// 1334 FunctionPass *llvm::createHexagonExpandCondsets() { 1335 return new HexagonExpandCondsets(); 1336 } 1337