xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (revision da5432eda807c4b7232d030d5157d5b417ea4f52) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11def A2_abs : HInst<
12(outs IntRegs:$Rd32),
13(ins IntRegs:$Rs32),
14"$Rd32 = abs($Rs32)",
15tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
16let Inst{13-5} = 0b000000100;
17let Inst{31-21} = 0b10001100100;
18let hasNewValue = 1;
19let opNewValue = 0;
20let prefersSlot3 = 1;
21}
22def A2_absp : HInst<
23(outs DoubleRegs:$Rdd32),
24(ins DoubleRegs:$Rss32),
25"$Rdd32 = abs($Rss32)",
26tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
27let Inst{13-5} = 0b000000110;
28let Inst{31-21} = 0b10000000100;
29let prefersSlot3 = 1;
30}
31def A2_abssat : HInst<
32(outs IntRegs:$Rd32),
33(ins IntRegs:$Rs32),
34"$Rd32 = abs($Rs32):sat",
35tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
36let Inst{13-5} = 0b000000101;
37let Inst{31-21} = 0b10001100100;
38let hasNewValue = 1;
39let opNewValue = 0;
40let prefersSlot3 = 1;
41let Defs = [USR_OVF];
42}
43def A2_add : HInst<
44(outs IntRegs:$Rd32),
45(ins IntRegs:$Rs32, IntRegs:$Rt32),
46"$Rd32 = add($Rs32,$Rt32)",
47tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
48let Inst{7-5} = 0b000;
49let Inst{13-13} = 0b0;
50let Inst{31-21} = 0b11110011000;
51let hasNewValue = 1;
52let opNewValue = 0;
53let BaseOpcode = "A2_add";
54let CextOpcode = "A2_add";
55let InputType = "reg";
56let isCommutable = 1;
57let isPredicable = 1;
58}
59def A2_addh_h16_hh : HInst<
60(outs IntRegs:$Rd32),
61(ins IntRegs:$Rt32, IntRegs:$Rs32),
62"$Rd32 = add($Rt32.h,$Rs32.h):<<16",
63tc_01d44cb2, TypeALU64>, Enc_bd6011 {
64let Inst{7-5} = 0b011;
65let Inst{13-13} = 0b0;
66let Inst{31-21} = 0b11010101010;
67let hasNewValue = 1;
68let opNewValue = 0;
69let prefersSlot3 = 1;
70}
71def A2_addh_h16_hl : HInst<
72(outs IntRegs:$Rd32),
73(ins IntRegs:$Rt32, IntRegs:$Rs32),
74"$Rd32 = add($Rt32.h,$Rs32.l):<<16",
75tc_01d44cb2, TypeALU64>, Enc_bd6011 {
76let Inst{7-5} = 0b010;
77let Inst{13-13} = 0b0;
78let Inst{31-21} = 0b11010101010;
79let hasNewValue = 1;
80let opNewValue = 0;
81let prefersSlot3 = 1;
82}
83def A2_addh_h16_lh : HInst<
84(outs IntRegs:$Rd32),
85(ins IntRegs:$Rt32, IntRegs:$Rs32),
86"$Rd32 = add($Rt32.l,$Rs32.h):<<16",
87tc_01d44cb2, TypeALU64>, Enc_bd6011 {
88let Inst{7-5} = 0b001;
89let Inst{13-13} = 0b0;
90let Inst{31-21} = 0b11010101010;
91let hasNewValue = 1;
92let opNewValue = 0;
93let prefersSlot3 = 1;
94}
95def A2_addh_h16_ll : HInst<
96(outs IntRegs:$Rd32),
97(ins IntRegs:$Rt32, IntRegs:$Rs32),
98"$Rd32 = add($Rt32.l,$Rs32.l):<<16",
99tc_01d44cb2, TypeALU64>, Enc_bd6011 {
100let Inst{7-5} = 0b000;
101let Inst{13-13} = 0b0;
102let Inst{31-21} = 0b11010101010;
103let hasNewValue = 1;
104let opNewValue = 0;
105let prefersSlot3 = 1;
106}
107def A2_addh_h16_sat_hh : HInst<
108(outs IntRegs:$Rd32),
109(ins IntRegs:$Rt32, IntRegs:$Rs32),
110"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
111tc_8a825db2, TypeALU64>, Enc_bd6011 {
112let Inst{7-5} = 0b111;
113let Inst{13-13} = 0b0;
114let Inst{31-21} = 0b11010101010;
115let hasNewValue = 1;
116let opNewValue = 0;
117let prefersSlot3 = 1;
118let Defs = [USR_OVF];
119}
120def A2_addh_h16_sat_hl : HInst<
121(outs IntRegs:$Rd32),
122(ins IntRegs:$Rt32, IntRegs:$Rs32),
123"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
124tc_8a825db2, TypeALU64>, Enc_bd6011 {
125let Inst{7-5} = 0b110;
126let Inst{13-13} = 0b0;
127let Inst{31-21} = 0b11010101010;
128let hasNewValue = 1;
129let opNewValue = 0;
130let prefersSlot3 = 1;
131let Defs = [USR_OVF];
132}
133def A2_addh_h16_sat_lh : HInst<
134(outs IntRegs:$Rd32),
135(ins IntRegs:$Rt32, IntRegs:$Rs32),
136"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
137tc_8a825db2, TypeALU64>, Enc_bd6011 {
138let Inst{7-5} = 0b101;
139let Inst{13-13} = 0b0;
140let Inst{31-21} = 0b11010101010;
141let hasNewValue = 1;
142let opNewValue = 0;
143let prefersSlot3 = 1;
144let Defs = [USR_OVF];
145}
146def A2_addh_h16_sat_ll : HInst<
147(outs IntRegs:$Rd32),
148(ins IntRegs:$Rt32, IntRegs:$Rs32),
149"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
150tc_8a825db2, TypeALU64>, Enc_bd6011 {
151let Inst{7-5} = 0b100;
152let Inst{13-13} = 0b0;
153let Inst{31-21} = 0b11010101010;
154let hasNewValue = 1;
155let opNewValue = 0;
156let prefersSlot3 = 1;
157let Defs = [USR_OVF];
158}
159def A2_addh_l16_hl : HInst<
160(outs IntRegs:$Rd32),
161(ins IntRegs:$Rt32, IntRegs:$Rs32),
162"$Rd32 = add($Rt32.l,$Rs32.h)",
163tc_f34c1c21, TypeALU64>, Enc_bd6011 {
164let Inst{7-5} = 0b010;
165let Inst{13-13} = 0b0;
166let Inst{31-21} = 0b11010101000;
167let hasNewValue = 1;
168let opNewValue = 0;
169let prefersSlot3 = 1;
170}
171def A2_addh_l16_ll : HInst<
172(outs IntRegs:$Rd32),
173(ins IntRegs:$Rt32, IntRegs:$Rs32),
174"$Rd32 = add($Rt32.l,$Rs32.l)",
175tc_f34c1c21, TypeALU64>, Enc_bd6011 {
176let Inst{7-5} = 0b000;
177let Inst{13-13} = 0b0;
178let Inst{31-21} = 0b11010101000;
179let hasNewValue = 1;
180let opNewValue = 0;
181let prefersSlot3 = 1;
182}
183def A2_addh_l16_sat_hl : HInst<
184(outs IntRegs:$Rd32),
185(ins IntRegs:$Rt32, IntRegs:$Rs32),
186"$Rd32 = add($Rt32.l,$Rs32.h):sat",
187tc_8a825db2, TypeALU64>, Enc_bd6011 {
188let Inst{7-5} = 0b110;
189let Inst{13-13} = 0b0;
190let Inst{31-21} = 0b11010101000;
191let hasNewValue = 1;
192let opNewValue = 0;
193let prefersSlot3 = 1;
194let Defs = [USR_OVF];
195}
196def A2_addh_l16_sat_ll : HInst<
197(outs IntRegs:$Rd32),
198(ins IntRegs:$Rt32, IntRegs:$Rs32),
199"$Rd32 = add($Rt32.l,$Rs32.l):sat",
200tc_8a825db2, TypeALU64>, Enc_bd6011 {
201let Inst{7-5} = 0b100;
202let Inst{13-13} = 0b0;
203let Inst{31-21} = 0b11010101000;
204let hasNewValue = 1;
205let opNewValue = 0;
206let prefersSlot3 = 1;
207let Defs = [USR_OVF];
208}
209def A2_addi : HInst<
210(outs IntRegs:$Rd32),
211(ins IntRegs:$Rs32, s32_0Imm:$Ii),
212"$Rd32 = add($Rs32,#$Ii)",
213tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
214let Inst{31-28} = 0b1011;
215let hasNewValue = 1;
216let opNewValue = 0;
217let BaseOpcode = "A2_addi";
218let CextOpcode = "A2_add";
219let InputType = "imm";
220let isAdd = 1;
221let isPredicable = 1;
222let isExtendable = 1;
223let opExtendable = 2;
224let isExtentSigned = 1;
225let opExtentBits = 16;
226let opExtentAlign = 0;
227}
228def A2_addp : HInst<
229(outs DoubleRegs:$Rdd32),
230(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
231"$Rdd32 = add($Rss32,$Rtt32)",
232tc_5da50c4b, TypeALU64>, Enc_a56825 {
233let Inst{7-5} = 0b111;
234let Inst{13-13} = 0b0;
235let Inst{31-21} = 0b11010011000;
236let isAdd = 1;
237let isCommutable = 1;
238}
239def A2_addpsat : HInst<
240(outs DoubleRegs:$Rdd32),
241(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
242"$Rdd32 = add($Rss32,$Rtt32):sat",
243tc_8a825db2, TypeALU64>, Enc_a56825 {
244let Inst{7-5} = 0b101;
245let Inst{13-13} = 0b0;
246let Inst{31-21} = 0b11010011011;
247let prefersSlot3 = 1;
248let Defs = [USR_OVF];
249let isCommutable = 1;
250}
251def A2_addsat : HInst<
252(outs IntRegs:$Rd32),
253(ins IntRegs:$Rs32, IntRegs:$Rt32),
254"$Rd32 = add($Rs32,$Rt32):sat",
255tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
256let Inst{7-5} = 0b000;
257let Inst{13-13} = 0b0;
258let Inst{31-21} = 0b11110110010;
259let hasNewValue = 1;
260let opNewValue = 0;
261let prefersSlot3 = 1;
262let Defs = [USR_OVF];
263let InputType = "reg";
264let isCommutable = 1;
265}
266def A2_addsp : HInst<
267(outs DoubleRegs:$Rdd32),
268(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
269"$Rdd32 = add($Rs32,$Rtt32)",
270tc_01d44cb2, TypeALU64> {
271let isPseudo = 1;
272}
273def A2_addsph : HInst<
274(outs DoubleRegs:$Rdd32),
275(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
276"$Rdd32 = add($Rss32,$Rtt32):raw:hi",
277tc_01d44cb2, TypeALU64>, Enc_a56825 {
278let Inst{7-5} = 0b111;
279let Inst{13-13} = 0b0;
280let Inst{31-21} = 0b11010011011;
281let prefersSlot3 = 1;
282}
283def A2_addspl : HInst<
284(outs DoubleRegs:$Rdd32),
285(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
286"$Rdd32 = add($Rss32,$Rtt32):raw:lo",
287tc_01d44cb2, TypeALU64>, Enc_a56825 {
288let Inst{7-5} = 0b110;
289let Inst{13-13} = 0b0;
290let Inst{31-21} = 0b11010011011;
291let prefersSlot3 = 1;
292}
293def A2_and : HInst<
294(outs IntRegs:$Rd32),
295(ins IntRegs:$Rs32, IntRegs:$Rt32),
296"$Rd32 = and($Rs32,$Rt32)",
297tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
298let Inst{7-5} = 0b000;
299let Inst{13-13} = 0b0;
300let Inst{31-21} = 0b11110001000;
301let hasNewValue = 1;
302let opNewValue = 0;
303let BaseOpcode = "A2_and";
304let CextOpcode = "A2_and";
305let InputType = "reg";
306let isCommutable = 1;
307let isPredicable = 1;
308}
309def A2_andir : HInst<
310(outs IntRegs:$Rd32),
311(ins IntRegs:$Rs32, s32_0Imm:$Ii),
312"$Rd32 = and($Rs32,#$Ii)",
313tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
314let Inst{31-22} = 0b0111011000;
315let hasNewValue = 1;
316let opNewValue = 0;
317let CextOpcode = "A2_and";
318let InputType = "imm";
319let isExtendable = 1;
320let opExtendable = 2;
321let isExtentSigned = 1;
322let opExtentBits = 10;
323let opExtentAlign = 0;
324}
325def A2_andp : HInst<
326(outs DoubleRegs:$Rdd32),
327(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
328"$Rdd32 = and($Rss32,$Rtt32)",
329tc_5da50c4b, TypeALU64>, Enc_a56825 {
330let Inst{7-5} = 0b000;
331let Inst{13-13} = 0b0;
332let Inst{31-21} = 0b11010011111;
333let isCommutable = 1;
334}
335def A2_aslh : HInst<
336(outs IntRegs:$Rd32),
337(ins IntRegs:$Rs32),
338"$Rd32 = aslh($Rs32)",
339tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
340let Inst{13-5} = 0b000000000;
341let Inst{31-21} = 0b01110000000;
342let hasNewValue = 1;
343let opNewValue = 0;
344let BaseOpcode = "A2_aslh";
345let isPredicable = 1;
346}
347def A2_asrh : HInst<
348(outs IntRegs:$Rd32),
349(ins IntRegs:$Rs32),
350"$Rd32 = asrh($Rs32)",
351tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
352let Inst{13-5} = 0b000000000;
353let Inst{31-21} = 0b01110000001;
354let hasNewValue = 1;
355let opNewValue = 0;
356let BaseOpcode = "A2_asrh";
357let isPredicable = 1;
358}
359def A2_combine_hh : HInst<
360(outs IntRegs:$Rd32),
361(ins IntRegs:$Rt32, IntRegs:$Rs32),
362"$Rd32 = combine($Rt32.h,$Rs32.h)",
363tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
364let Inst{7-5} = 0b000;
365let Inst{13-13} = 0b0;
366let Inst{31-21} = 0b11110011100;
367let hasNewValue = 1;
368let opNewValue = 0;
369let InputType = "reg";
370}
371def A2_combine_hl : HInst<
372(outs IntRegs:$Rd32),
373(ins IntRegs:$Rt32, IntRegs:$Rs32),
374"$Rd32 = combine($Rt32.h,$Rs32.l)",
375tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
376let Inst{7-5} = 0b000;
377let Inst{13-13} = 0b0;
378let Inst{31-21} = 0b11110011101;
379let hasNewValue = 1;
380let opNewValue = 0;
381let InputType = "reg";
382}
383def A2_combine_lh : HInst<
384(outs IntRegs:$Rd32),
385(ins IntRegs:$Rt32, IntRegs:$Rs32),
386"$Rd32 = combine($Rt32.l,$Rs32.h)",
387tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
388let Inst{7-5} = 0b000;
389let Inst{13-13} = 0b0;
390let Inst{31-21} = 0b11110011110;
391let hasNewValue = 1;
392let opNewValue = 0;
393let InputType = "reg";
394}
395def A2_combine_ll : HInst<
396(outs IntRegs:$Rd32),
397(ins IntRegs:$Rt32, IntRegs:$Rs32),
398"$Rd32 = combine($Rt32.l,$Rs32.l)",
399tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
400let Inst{7-5} = 0b000;
401let Inst{13-13} = 0b0;
402let Inst{31-21} = 0b11110011111;
403let hasNewValue = 1;
404let opNewValue = 0;
405let InputType = "reg";
406}
407def A2_combineii : HInst<
408(outs DoubleRegs:$Rdd32),
409(ins s32_0Imm:$Ii, s8_0Imm:$II),
410"$Rdd32 = combine(#$Ii,#$II)",
411tc_713b66bf, TypeALU32_2op>, Enc_18c338 {
412let Inst{31-23} = 0b011111000;
413let isAsCheapAsAMove = 1;
414let isMoveImm = 1;
415let isReMaterializable = 1;
416let isExtendable = 1;
417let opExtendable = 1;
418let isExtentSigned = 1;
419let opExtentBits = 8;
420let opExtentAlign = 0;
421}
422def A2_combinew : HInst<
423(outs DoubleRegs:$Rdd32),
424(ins IntRegs:$Rs32, IntRegs:$Rt32),
425"$Rdd32 = combine($Rs32,$Rt32)",
426tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel {
427let Inst{7-5} = 0b000;
428let Inst{13-13} = 0b0;
429let Inst{31-21} = 0b11110101000;
430let BaseOpcode = "A2_combinew";
431let InputType = "reg";
432let isPredicable = 1;
433}
434def A2_max : HInst<
435(outs IntRegs:$Rd32),
436(ins IntRegs:$Rs32, IntRegs:$Rt32),
437"$Rd32 = max($Rs32,$Rt32)",
438tc_8a825db2, TypeALU64>, Enc_5ab2be {
439let Inst{7-5} = 0b000;
440let Inst{13-13} = 0b0;
441let Inst{31-21} = 0b11010101110;
442let hasNewValue = 1;
443let opNewValue = 0;
444let prefersSlot3 = 1;
445}
446def A2_maxp : HInst<
447(outs DoubleRegs:$Rdd32),
448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
449"$Rdd32 = max($Rss32,$Rtt32)",
450tc_8a825db2, TypeALU64>, Enc_a56825 {
451let Inst{7-5} = 0b100;
452let Inst{13-13} = 0b0;
453let Inst{31-21} = 0b11010011110;
454let prefersSlot3 = 1;
455}
456def A2_maxu : HInst<
457(outs IntRegs:$Rd32),
458(ins IntRegs:$Rs32, IntRegs:$Rt32),
459"$Rd32 = maxu($Rs32,$Rt32)",
460tc_8a825db2, TypeALU64>, Enc_5ab2be {
461let Inst{7-5} = 0b100;
462let Inst{13-13} = 0b0;
463let Inst{31-21} = 0b11010101110;
464let hasNewValue = 1;
465let opNewValue = 0;
466let prefersSlot3 = 1;
467}
468def A2_maxup : HInst<
469(outs DoubleRegs:$Rdd32),
470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
471"$Rdd32 = maxu($Rss32,$Rtt32)",
472tc_8a825db2, TypeALU64>, Enc_a56825 {
473let Inst{7-5} = 0b101;
474let Inst{13-13} = 0b0;
475let Inst{31-21} = 0b11010011110;
476let prefersSlot3 = 1;
477}
478def A2_min : HInst<
479(outs IntRegs:$Rd32),
480(ins IntRegs:$Rt32, IntRegs:$Rs32),
481"$Rd32 = min($Rt32,$Rs32)",
482tc_8a825db2, TypeALU64>, Enc_bd6011 {
483let Inst{7-5} = 0b000;
484let Inst{13-13} = 0b0;
485let Inst{31-21} = 0b11010101101;
486let hasNewValue = 1;
487let opNewValue = 0;
488let prefersSlot3 = 1;
489}
490def A2_minp : HInst<
491(outs DoubleRegs:$Rdd32),
492(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
493"$Rdd32 = min($Rtt32,$Rss32)",
494tc_8a825db2, TypeALU64>, Enc_ea23e4 {
495let Inst{7-5} = 0b110;
496let Inst{13-13} = 0b0;
497let Inst{31-21} = 0b11010011101;
498let prefersSlot3 = 1;
499}
500def A2_minu : HInst<
501(outs IntRegs:$Rd32),
502(ins IntRegs:$Rt32, IntRegs:$Rs32),
503"$Rd32 = minu($Rt32,$Rs32)",
504tc_8a825db2, TypeALU64>, Enc_bd6011 {
505let Inst{7-5} = 0b100;
506let Inst{13-13} = 0b0;
507let Inst{31-21} = 0b11010101101;
508let hasNewValue = 1;
509let opNewValue = 0;
510let prefersSlot3 = 1;
511}
512def A2_minup : HInst<
513(outs DoubleRegs:$Rdd32),
514(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
515"$Rdd32 = minu($Rtt32,$Rss32)",
516tc_8a825db2, TypeALU64>, Enc_ea23e4 {
517let Inst{7-5} = 0b111;
518let Inst{13-13} = 0b0;
519let Inst{31-21} = 0b11010011101;
520let prefersSlot3 = 1;
521}
522def A2_neg : HInst<
523(outs IntRegs:$Rd32),
524(ins IntRegs:$Rs32),
525"$Rd32 = neg($Rs32)",
526tc_c57d9f39, TypeALU32_2op> {
527let hasNewValue = 1;
528let opNewValue = 0;
529let isPseudo = 1;
530let isCodeGenOnly = 1;
531}
532def A2_negp : HInst<
533(outs DoubleRegs:$Rdd32),
534(ins DoubleRegs:$Rss32),
535"$Rdd32 = neg($Rss32)",
536tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
537let Inst{13-5} = 0b000000101;
538let Inst{31-21} = 0b10000000100;
539}
540def A2_negsat : HInst<
541(outs IntRegs:$Rd32),
542(ins IntRegs:$Rs32),
543"$Rd32 = neg($Rs32):sat",
544tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
545let Inst{13-5} = 0b000000110;
546let Inst{31-21} = 0b10001100100;
547let hasNewValue = 1;
548let opNewValue = 0;
549let prefersSlot3 = 1;
550let Defs = [USR_OVF];
551}
552def A2_nop : HInst<
553(outs),
554(ins),
555"nop",
556tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 {
557let Inst{13-0} = 0b00000000000000;
558let Inst{31-16} = 0b0111111100000000;
559}
560def A2_not : HInst<
561(outs IntRegs:$Rd32),
562(ins IntRegs:$Rs32),
563"$Rd32 = not($Rs32)",
564tc_c57d9f39, TypeALU32_2op> {
565let hasNewValue = 1;
566let opNewValue = 0;
567let isPseudo = 1;
568let isCodeGenOnly = 1;
569}
570def A2_notp : HInst<
571(outs DoubleRegs:$Rdd32),
572(ins DoubleRegs:$Rss32),
573"$Rdd32 = not($Rss32)",
574tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
575let Inst{13-5} = 0b000000100;
576let Inst{31-21} = 0b10000000100;
577}
578def A2_or : HInst<
579(outs IntRegs:$Rd32),
580(ins IntRegs:$Rs32, IntRegs:$Rt32),
581"$Rd32 = or($Rs32,$Rt32)",
582tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
583let Inst{7-5} = 0b000;
584let Inst{13-13} = 0b0;
585let Inst{31-21} = 0b11110001001;
586let hasNewValue = 1;
587let opNewValue = 0;
588let BaseOpcode = "A2_or";
589let CextOpcode = "A2_or";
590let InputType = "reg";
591let isCommutable = 1;
592let isPredicable = 1;
593}
594def A2_orir : HInst<
595(outs IntRegs:$Rd32),
596(ins IntRegs:$Rs32, s32_0Imm:$Ii),
597"$Rd32 = or($Rs32,#$Ii)",
598tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
599let Inst{31-22} = 0b0111011010;
600let hasNewValue = 1;
601let opNewValue = 0;
602let CextOpcode = "A2_or";
603let InputType = "imm";
604let isExtendable = 1;
605let opExtendable = 2;
606let isExtentSigned = 1;
607let opExtentBits = 10;
608let opExtentAlign = 0;
609}
610def A2_orp : HInst<
611(outs DoubleRegs:$Rdd32),
612(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
613"$Rdd32 = or($Rss32,$Rtt32)",
614tc_5da50c4b, TypeALU64>, Enc_a56825 {
615let Inst{7-5} = 0b010;
616let Inst{13-13} = 0b0;
617let Inst{31-21} = 0b11010011111;
618let isCommutable = 1;
619}
620def A2_paddf : HInst<
621(outs IntRegs:$Rd32),
622(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
623"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
624tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
625let Inst{7-7} = 0b1;
626let Inst{13-13} = 0b0;
627let Inst{31-21} = 0b11111011000;
628let isPredicated = 1;
629let isPredicatedFalse = 1;
630let hasNewValue = 1;
631let opNewValue = 0;
632let BaseOpcode = "A2_add";
633let CextOpcode = "A2_add";
634let InputType = "reg";
635}
636def A2_paddfnew : HInst<
637(outs IntRegs:$Rd32),
638(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
639"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
640tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
641let Inst{7-7} = 0b1;
642let Inst{13-13} = 0b1;
643let Inst{31-21} = 0b11111011000;
644let isPredicated = 1;
645let isPredicatedFalse = 1;
646let hasNewValue = 1;
647let opNewValue = 0;
648let isPredicatedNew = 1;
649let BaseOpcode = "A2_add";
650let CextOpcode = "A2_add";
651let InputType = "reg";
652}
653def A2_paddif : HInst<
654(outs IntRegs:$Rd32),
655(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
656"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
657tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
658let Inst{13-13} = 0b0;
659let Inst{31-23} = 0b011101001;
660let isPredicated = 1;
661let isPredicatedFalse = 1;
662let hasNewValue = 1;
663let opNewValue = 0;
664let BaseOpcode = "A2_addi";
665let CextOpcode = "A2_add";
666let InputType = "imm";
667let isExtendable = 1;
668let opExtendable = 3;
669let isExtentSigned = 1;
670let opExtentBits = 8;
671let opExtentAlign = 0;
672}
673def A2_paddifnew : HInst<
674(outs IntRegs:$Rd32),
675(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
676"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
677tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
678let Inst{13-13} = 0b1;
679let Inst{31-23} = 0b011101001;
680let isPredicated = 1;
681let isPredicatedFalse = 1;
682let hasNewValue = 1;
683let opNewValue = 0;
684let isPredicatedNew = 1;
685let BaseOpcode = "A2_addi";
686let CextOpcode = "A2_add";
687let InputType = "imm";
688let isExtendable = 1;
689let opExtendable = 3;
690let isExtentSigned = 1;
691let opExtentBits = 8;
692let opExtentAlign = 0;
693}
694def A2_paddit : HInst<
695(outs IntRegs:$Rd32),
696(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
697"if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
698tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
699let Inst{13-13} = 0b0;
700let Inst{31-23} = 0b011101000;
701let isPredicated = 1;
702let hasNewValue = 1;
703let opNewValue = 0;
704let BaseOpcode = "A2_addi";
705let CextOpcode = "A2_add";
706let InputType = "imm";
707let isExtendable = 1;
708let opExtendable = 3;
709let isExtentSigned = 1;
710let opExtentBits = 8;
711let opExtentAlign = 0;
712}
713def A2_padditnew : HInst<
714(outs IntRegs:$Rd32),
715(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
716"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
717tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
718let Inst{13-13} = 0b1;
719let Inst{31-23} = 0b011101000;
720let isPredicated = 1;
721let hasNewValue = 1;
722let opNewValue = 0;
723let isPredicatedNew = 1;
724let BaseOpcode = "A2_addi";
725let CextOpcode = "A2_add";
726let InputType = "imm";
727let isExtendable = 1;
728let opExtendable = 3;
729let isExtentSigned = 1;
730let opExtentBits = 8;
731let opExtentAlign = 0;
732}
733def A2_paddt : HInst<
734(outs IntRegs:$Rd32),
735(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
736"if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
737tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
738let Inst{7-7} = 0b0;
739let Inst{13-13} = 0b0;
740let Inst{31-21} = 0b11111011000;
741let isPredicated = 1;
742let hasNewValue = 1;
743let opNewValue = 0;
744let BaseOpcode = "A2_add";
745let CextOpcode = "A2_add";
746let InputType = "reg";
747}
748def A2_paddtnew : HInst<
749(outs IntRegs:$Rd32),
750(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
751"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
752tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
753let Inst{7-7} = 0b0;
754let Inst{13-13} = 0b1;
755let Inst{31-21} = 0b11111011000;
756let isPredicated = 1;
757let hasNewValue = 1;
758let opNewValue = 0;
759let isPredicatedNew = 1;
760let BaseOpcode = "A2_add";
761let CextOpcode = "A2_add";
762let InputType = "reg";
763}
764def A2_pandf : HInst<
765(outs IntRegs:$Rd32),
766(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
767"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
768tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
769let Inst{7-7} = 0b1;
770let Inst{13-13} = 0b0;
771let Inst{31-21} = 0b11111001000;
772let isPredicated = 1;
773let isPredicatedFalse = 1;
774let hasNewValue = 1;
775let opNewValue = 0;
776let BaseOpcode = "A2_and";
777}
778def A2_pandfnew : HInst<
779(outs IntRegs:$Rd32),
780(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
781"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
782tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
783let Inst{7-7} = 0b1;
784let Inst{13-13} = 0b1;
785let Inst{31-21} = 0b11111001000;
786let isPredicated = 1;
787let isPredicatedFalse = 1;
788let hasNewValue = 1;
789let opNewValue = 0;
790let isPredicatedNew = 1;
791let BaseOpcode = "A2_and";
792}
793def A2_pandt : HInst<
794(outs IntRegs:$Rd32),
795(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
796"if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
797tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
798let Inst{7-7} = 0b0;
799let Inst{13-13} = 0b0;
800let Inst{31-21} = 0b11111001000;
801let isPredicated = 1;
802let hasNewValue = 1;
803let opNewValue = 0;
804let BaseOpcode = "A2_and";
805}
806def A2_pandtnew : HInst<
807(outs IntRegs:$Rd32),
808(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
809"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
810tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
811let Inst{7-7} = 0b0;
812let Inst{13-13} = 0b1;
813let Inst{31-21} = 0b11111001000;
814let isPredicated = 1;
815let hasNewValue = 1;
816let opNewValue = 0;
817let isPredicatedNew = 1;
818let BaseOpcode = "A2_and";
819}
820def A2_porf : HInst<
821(outs IntRegs:$Rd32),
822(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
823"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
824tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
825let Inst{7-7} = 0b1;
826let Inst{13-13} = 0b0;
827let Inst{31-21} = 0b11111001001;
828let isPredicated = 1;
829let isPredicatedFalse = 1;
830let hasNewValue = 1;
831let opNewValue = 0;
832let BaseOpcode = "A2_or";
833}
834def A2_porfnew : HInst<
835(outs IntRegs:$Rd32),
836(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
837"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
838tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
839let Inst{7-7} = 0b1;
840let Inst{13-13} = 0b1;
841let Inst{31-21} = 0b11111001001;
842let isPredicated = 1;
843let isPredicatedFalse = 1;
844let hasNewValue = 1;
845let opNewValue = 0;
846let isPredicatedNew = 1;
847let BaseOpcode = "A2_or";
848}
849def A2_port : HInst<
850(outs IntRegs:$Rd32),
851(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
852"if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
853tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
854let Inst{7-7} = 0b0;
855let Inst{13-13} = 0b0;
856let Inst{31-21} = 0b11111001001;
857let isPredicated = 1;
858let hasNewValue = 1;
859let opNewValue = 0;
860let BaseOpcode = "A2_or";
861}
862def A2_portnew : HInst<
863(outs IntRegs:$Rd32),
864(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
865"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
866tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
867let Inst{7-7} = 0b0;
868let Inst{13-13} = 0b1;
869let Inst{31-21} = 0b11111001001;
870let isPredicated = 1;
871let hasNewValue = 1;
872let opNewValue = 0;
873let isPredicatedNew = 1;
874let BaseOpcode = "A2_or";
875}
876def A2_psubf : HInst<
877(outs IntRegs:$Rd32),
878(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
879"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
880tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
881let Inst{7-7} = 0b1;
882let Inst{13-13} = 0b0;
883let Inst{31-21} = 0b11111011001;
884let isPredicated = 1;
885let isPredicatedFalse = 1;
886let hasNewValue = 1;
887let opNewValue = 0;
888let BaseOpcode = "A2_sub";
889}
890def A2_psubfnew : HInst<
891(outs IntRegs:$Rd32),
892(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
893"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
894tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
895let Inst{7-7} = 0b1;
896let Inst{13-13} = 0b1;
897let Inst{31-21} = 0b11111011001;
898let isPredicated = 1;
899let isPredicatedFalse = 1;
900let hasNewValue = 1;
901let opNewValue = 0;
902let isPredicatedNew = 1;
903let BaseOpcode = "A2_sub";
904}
905def A2_psubt : HInst<
906(outs IntRegs:$Rd32),
907(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
908"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
909tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
910let Inst{7-7} = 0b0;
911let Inst{13-13} = 0b0;
912let Inst{31-21} = 0b11111011001;
913let isPredicated = 1;
914let hasNewValue = 1;
915let opNewValue = 0;
916let BaseOpcode = "A2_sub";
917}
918def A2_psubtnew : HInst<
919(outs IntRegs:$Rd32),
920(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
921"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
922tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
923let Inst{7-7} = 0b0;
924let Inst{13-13} = 0b1;
925let Inst{31-21} = 0b11111011001;
926let isPredicated = 1;
927let hasNewValue = 1;
928let opNewValue = 0;
929let isPredicatedNew = 1;
930let BaseOpcode = "A2_sub";
931}
932def A2_pxorf : HInst<
933(outs IntRegs:$Rd32),
934(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
935"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
936tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
937let Inst{7-7} = 0b1;
938let Inst{13-13} = 0b0;
939let Inst{31-21} = 0b11111001011;
940let isPredicated = 1;
941let isPredicatedFalse = 1;
942let hasNewValue = 1;
943let opNewValue = 0;
944let BaseOpcode = "A2_xor";
945}
946def A2_pxorfnew : HInst<
947(outs IntRegs:$Rd32),
948(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
949"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
950tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
951let Inst{7-7} = 0b1;
952let Inst{13-13} = 0b1;
953let Inst{31-21} = 0b11111001011;
954let isPredicated = 1;
955let isPredicatedFalse = 1;
956let hasNewValue = 1;
957let opNewValue = 0;
958let isPredicatedNew = 1;
959let BaseOpcode = "A2_xor";
960}
961def A2_pxort : HInst<
962(outs IntRegs:$Rd32),
963(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
964"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
965tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
966let Inst{7-7} = 0b0;
967let Inst{13-13} = 0b0;
968let Inst{31-21} = 0b11111001011;
969let isPredicated = 1;
970let hasNewValue = 1;
971let opNewValue = 0;
972let BaseOpcode = "A2_xor";
973}
974def A2_pxortnew : HInst<
975(outs IntRegs:$Rd32),
976(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
977"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
978tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
979let Inst{7-7} = 0b0;
980let Inst{13-13} = 0b1;
981let Inst{31-21} = 0b11111001011;
982let isPredicated = 1;
983let hasNewValue = 1;
984let opNewValue = 0;
985let isPredicatedNew = 1;
986let BaseOpcode = "A2_xor";
987}
988def A2_roundsat : HInst<
989(outs IntRegs:$Rd32),
990(ins DoubleRegs:$Rss32),
991"$Rd32 = round($Rss32):sat",
992tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
993let Inst{13-5} = 0b000000001;
994let Inst{31-21} = 0b10001000110;
995let hasNewValue = 1;
996let opNewValue = 0;
997let prefersSlot3 = 1;
998let Defs = [USR_OVF];
999}
1000def A2_sat : HInst<
1001(outs IntRegs:$Rd32),
1002(ins DoubleRegs:$Rss32),
1003"$Rd32 = sat($Rss32)",
1004tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
1005let Inst{13-5} = 0b000000000;
1006let Inst{31-21} = 0b10001000110;
1007let hasNewValue = 1;
1008let opNewValue = 0;
1009let Defs = [USR_OVF];
1010}
1011def A2_satb : HInst<
1012(outs IntRegs:$Rd32),
1013(ins IntRegs:$Rs32),
1014"$Rd32 = satb($Rs32)",
1015tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1016let Inst{13-5} = 0b000000111;
1017let Inst{31-21} = 0b10001100110;
1018let hasNewValue = 1;
1019let opNewValue = 0;
1020let Defs = [USR_OVF];
1021}
1022def A2_sath : HInst<
1023(outs IntRegs:$Rd32),
1024(ins IntRegs:$Rs32),
1025"$Rd32 = sath($Rs32)",
1026tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1027let Inst{13-5} = 0b000000100;
1028let Inst{31-21} = 0b10001100110;
1029let hasNewValue = 1;
1030let opNewValue = 0;
1031let Defs = [USR_OVF];
1032}
1033def A2_satub : HInst<
1034(outs IntRegs:$Rd32),
1035(ins IntRegs:$Rs32),
1036"$Rd32 = satub($Rs32)",
1037tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1038let Inst{13-5} = 0b000000110;
1039let Inst{31-21} = 0b10001100110;
1040let hasNewValue = 1;
1041let opNewValue = 0;
1042let Defs = [USR_OVF];
1043}
1044def A2_satuh : HInst<
1045(outs IntRegs:$Rd32),
1046(ins IntRegs:$Rs32),
1047"$Rd32 = satuh($Rs32)",
1048tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1049let Inst{13-5} = 0b000000101;
1050let Inst{31-21} = 0b10001100110;
1051let hasNewValue = 1;
1052let opNewValue = 0;
1053let Defs = [USR_OVF];
1054}
1055def A2_sub : HInst<
1056(outs IntRegs:$Rd32),
1057(ins IntRegs:$Rt32, IntRegs:$Rs32),
1058"$Rd32 = sub($Rt32,$Rs32)",
1059tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
1060let Inst{7-5} = 0b000;
1061let Inst{13-13} = 0b0;
1062let Inst{31-21} = 0b11110011001;
1063let hasNewValue = 1;
1064let opNewValue = 0;
1065let BaseOpcode = "A2_sub";
1066let CextOpcode = "A2_sub";
1067let InputType = "reg";
1068let isPredicable = 1;
1069}
1070def A2_subh_h16_hh : HInst<
1071(outs IntRegs:$Rd32),
1072(ins IntRegs:$Rt32, IntRegs:$Rs32),
1073"$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
1074tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1075let Inst{7-5} = 0b011;
1076let Inst{13-13} = 0b0;
1077let Inst{31-21} = 0b11010101011;
1078let hasNewValue = 1;
1079let opNewValue = 0;
1080let prefersSlot3 = 1;
1081}
1082def A2_subh_h16_hl : HInst<
1083(outs IntRegs:$Rd32),
1084(ins IntRegs:$Rt32, IntRegs:$Rs32),
1085"$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
1086tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1087let Inst{7-5} = 0b010;
1088let Inst{13-13} = 0b0;
1089let Inst{31-21} = 0b11010101011;
1090let hasNewValue = 1;
1091let opNewValue = 0;
1092let prefersSlot3 = 1;
1093}
1094def A2_subh_h16_lh : HInst<
1095(outs IntRegs:$Rd32),
1096(ins IntRegs:$Rt32, IntRegs:$Rs32),
1097"$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
1098tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1099let Inst{7-5} = 0b001;
1100let Inst{13-13} = 0b0;
1101let Inst{31-21} = 0b11010101011;
1102let hasNewValue = 1;
1103let opNewValue = 0;
1104let prefersSlot3 = 1;
1105}
1106def A2_subh_h16_ll : HInst<
1107(outs IntRegs:$Rd32),
1108(ins IntRegs:$Rt32, IntRegs:$Rs32),
1109"$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
1110tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1111let Inst{7-5} = 0b000;
1112let Inst{13-13} = 0b0;
1113let Inst{31-21} = 0b11010101011;
1114let hasNewValue = 1;
1115let opNewValue = 0;
1116let prefersSlot3 = 1;
1117}
1118def A2_subh_h16_sat_hh : HInst<
1119(outs IntRegs:$Rd32),
1120(ins IntRegs:$Rt32, IntRegs:$Rs32),
1121"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
1122tc_8a825db2, TypeALU64>, Enc_bd6011 {
1123let Inst{7-5} = 0b111;
1124let Inst{13-13} = 0b0;
1125let Inst{31-21} = 0b11010101011;
1126let hasNewValue = 1;
1127let opNewValue = 0;
1128let prefersSlot3 = 1;
1129let Defs = [USR_OVF];
1130}
1131def A2_subh_h16_sat_hl : HInst<
1132(outs IntRegs:$Rd32),
1133(ins IntRegs:$Rt32, IntRegs:$Rs32),
1134"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
1135tc_8a825db2, TypeALU64>, Enc_bd6011 {
1136let Inst{7-5} = 0b110;
1137let Inst{13-13} = 0b0;
1138let Inst{31-21} = 0b11010101011;
1139let hasNewValue = 1;
1140let opNewValue = 0;
1141let prefersSlot3 = 1;
1142let Defs = [USR_OVF];
1143}
1144def A2_subh_h16_sat_lh : HInst<
1145(outs IntRegs:$Rd32),
1146(ins IntRegs:$Rt32, IntRegs:$Rs32),
1147"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
1148tc_8a825db2, TypeALU64>, Enc_bd6011 {
1149let Inst{7-5} = 0b101;
1150let Inst{13-13} = 0b0;
1151let Inst{31-21} = 0b11010101011;
1152let hasNewValue = 1;
1153let opNewValue = 0;
1154let prefersSlot3 = 1;
1155let Defs = [USR_OVF];
1156}
1157def A2_subh_h16_sat_ll : HInst<
1158(outs IntRegs:$Rd32),
1159(ins IntRegs:$Rt32, IntRegs:$Rs32),
1160"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
1161tc_8a825db2, TypeALU64>, Enc_bd6011 {
1162let Inst{7-5} = 0b100;
1163let Inst{13-13} = 0b0;
1164let Inst{31-21} = 0b11010101011;
1165let hasNewValue = 1;
1166let opNewValue = 0;
1167let prefersSlot3 = 1;
1168let Defs = [USR_OVF];
1169}
1170def A2_subh_l16_hl : HInst<
1171(outs IntRegs:$Rd32),
1172(ins IntRegs:$Rt32, IntRegs:$Rs32),
1173"$Rd32 = sub($Rt32.l,$Rs32.h)",
1174tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1175let Inst{7-5} = 0b010;
1176let Inst{13-13} = 0b0;
1177let Inst{31-21} = 0b11010101001;
1178let hasNewValue = 1;
1179let opNewValue = 0;
1180let prefersSlot3 = 1;
1181}
1182def A2_subh_l16_ll : HInst<
1183(outs IntRegs:$Rd32),
1184(ins IntRegs:$Rt32, IntRegs:$Rs32),
1185"$Rd32 = sub($Rt32.l,$Rs32.l)",
1186tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1187let Inst{7-5} = 0b000;
1188let Inst{13-13} = 0b0;
1189let Inst{31-21} = 0b11010101001;
1190let hasNewValue = 1;
1191let opNewValue = 0;
1192let prefersSlot3 = 1;
1193}
1194def A2_subh_l16_sat_hl : HInst<
1195(outs IntRegs:$Rd32),
1196(ins IntRegs:$Rt32, IntRegs:$Rs32),
1197"$Rd32 = sub($Rt32.l,$Rs32.h):sat",
1198tc_8a825db2, TypeALU64>, Enc_bd6011 {
1199let Inst{7-5} = 0b110;
1200let Inst{13-13} = 0b0;
1201let Inst{31-21} = 0b11010101001;
1202let hasNewValue = 1;
1203let opNewValue = 0;
1204let prefersSlot3 = 1;
1205let Defs = [USR_OVF];
1206}
1207def A2_subh_l16_sat_ll : HInst<
1208(outs IntRegs:$Rd32),
1209(ins IntRegs:$Rt32, IntRegs:$Rs32),
1210"$Rd32 = sub($Rt32.l,$Rs32.l):sat",
1211tc_8a825db2, TypeALU64>, Enc_bd6011 {
1212let Inst{7-5} = 0b100;
1213let Inst{13-13} = 0b0;
1214let Inst{31-21} = 0b11010101001;
1215let hasNewValue = 1;
1216let opNewValue = 0;
1217let prefersSlot3 = 1;
1218let Defs = [USR_OVF];
1219}
1220def A2_subp : HInst<
1221(outs DoubleRegs:$Rdd32),
1222(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1223"$Rdd32 = sub($Rtt32,$Rss32)",
1224tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
1225let Inst{7-5} = 0b111;
1226let Inst{13-13} = 0b0;
1227let Inst{31-21} = 0b11010011001;
1228}
1229def A2_subri : HInst<
1230(outs IntRegs:$Rd32),
1231(ins s32_0Imm:$Ii, IntRegs:$Rs32),
1232"$Rd32 = sub(#$Ii,$Rs32)",
1233tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
1234let Inst{31-22} = 0b0111011001;
1235let hasNewValue = 1;
1236let opNewValue = 0;
1237let CextOpcode = "A2_sub";
1238let InputType = "imm";
1239let isExtendable = 1;
1240let opExtendable = 1;
1241let isExtentSigned = 1;
1242let opExtentBits = 10;
1243let opExtentAlign = 0;
1244}
1245def A2_subsat : HInst<
1246(outs IntRegs:$Rd32),
1247(ins IntRegs:$Rt32, IntRegs:$Rs32),
1248"$Rd32 = sub($Rt32,$Rs32):sat",
1249tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1250let Inst{7-5} = 0b000;
1251let Inst{13-13} = 0b0;
1252let Inst{31-21} = 0b11110110110;
1253let hasNewValue = 1;
1254let opNewValue = 0;
1255let prefersSlot3 = 1;
1256let Defs = [USR_OVF];
1257let InputType = "reg";
1258}
1259def A2_svaddh : HInst<
1260(outs IntRegs:$Rd32),
1261(ins IntRegs:$Rs32, IntRegs:$Rt32),
1262"$Rd32 = vaddh($Rs32,$Rt32)",
1263tc_713b66bf, TypeALU32_3op>, Enc_5ab2be {
1264let Inst{7-5} = 0b000;
1265let Inst{13-13} = 0b0;
1266let Inst{31-21} = 0b11110110000;
1267let hasNewValue = 1;
1268let opNewValue = 0;
1269let InputType = "reg";
1270let isCommutable = 1;
1271}
1272def A2_svaddhs : HInst<
1273(outs IntRegs:$Rd32),
1274(ins IntRegs:$Rs32, IntRegs:$Rt32),
1275"$Rd32 = vaddh($Rs32,$Rt32):sat",
1276tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1277let Inst{7-5} = 0b000;
1278let Inst{13-13} = 0b0;
1279let Inst{31-21} = 0b11110110001;
1280let hasNewValue = 1;
1281let opNewValue = 0;
1282let prefersSlot3 = 1;
1283let Defs = [USR_OVF];
1284let InputType = "reg";
1285let isCommutable = 1;
1286}
1287def A2_svadduhs : HInst<
1288(outs IntRegs:$Rd32),
1289(ins IntRegs:$Rs32, IntRegs:$Rt32),
1290"$Rd32 = vadduh($Rs32,$Rt32):sat",
1291tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1292let Inst{7-5} = 0b000;
1293let Inst{13-13} = 0b0;
1294let Inst{31-21} = 0b11110110011;
1295let hasNewValue = 1;
1296let opNewValue = 0;
1297let prefersSlot3 = 1;
1298let Defs = [USR_OVF];
1299let InputType = "reg";
1300let isCommutable = 1;
1301}
1302def A2_svavgh : HInst<
1303(outs IntRegs:$Rd32),
1304(ins IntRegs:$Rs32, IntRegs:$Rt32),
1305"$Rd32 = vavgh($Rs32,$Rt32)",
1306tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be {
1307let Inst{7-5} = 0b000;
1308let Inst{13-13} = 0b0;
1309let Inst{31-21} = 0b11110111000;
1310let hasNewValue = 1;
1311let opNewValue = 0;
1312let prefersSlot3 = 1;
1313let InputType = "reg";
1314let isCommutable = 1;
1315}
1316def A2_svavghs : HInst<
1317(outs IntRegs:$Rd32),
1318(ins IntRegs:$Rs32, IntRegs:$Rt32),
1319"$Rd32 = vavgh($Rs32,$Rt32):rnd",
1320tc_84a7500d, TypeALU32_3op>, Enc_5ab2be {
1321let Inst{7-5} = 0b000;
1322let Inst{13-13} = 0b0;
1323let Inst{31-21} = 0b11110111001;
1324let hasNewValue = 1;
1325let opNewValue = 0;
1326let prefersSlot3 = 1;
1327let InputType = "reg";
1328let isCommutable = 1;
1329}
1330def A2_svnavgh : HInst<
1331(outs IntRegs:$Rd32),
1332(ins IntRegs:$Rt32, IntRegs:$Rs32),
1333"$Rd32 = vnavgh($Rt32,$Rs32)",
1334tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 {
1335let Inst{7-5} = 0b000;
1336let Inst{13-13} = 0b0;
1337let Inst{31-21} = 0b11110111011;
1338let hasNewValue = 1;
1339let opNewValue = 0;
1340let prefersSlot3 = 1;
1341let InputType = "reg";
1342}
1343def A2_svsubh : HInst<
1344(outs IntRegs:$Rd32),
1345(ins IntRegs:$Rt32, IntRegs:$Rs32),
1346"$Rd32 = vsubh($Rt32,$Rs32)",
1347tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
1348let Inst{7-5} = 0b000;
1349let Inst{13-13} = 0b0;
1350let Inst{31-21} = 0b11110110100;
1351let hasNewValue = 1;
1352let opNewValue = 0;
1353let InputType = "reg";
1354}
1355def A2_svsubhs : HInst<
1356(outs IntRegs:$Rd32),
1357(ins IntRegs:$Rt32, IntRegs:$Rs32),
1358"$Rd32 = vsubh($Rt32,$Rs32):sat",
1359tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1360let Inst{7-5} = 0b000;
1361let Inst{13-13} = 0b0;
1362let Inst{31-21} = 0b11110110101;
1363let hasNewValue = 1;
1364let opNewValue = 0;
1365let prefersSlot3 = 1;
1366let Defs = [USR_OVF];
1367let InputType = "reg";
1368}
1369def A2_svsubuhs : HInst<
1370(outs IntRegs:$Rd32),
1371(ins IntRegs:$Rt32, IntRegs:$Rs32),
1372"$Rd32 = vsubuh($Rt32,$Rs32):sat",
1373tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1374let Inst{7-5} = 0b000;
1375let Inst{13-13} = 0b0;
1376let Inst{31-21} = 0b11110110111;
1377let hasNewValue = 1;
1378let opNewValue = 0;
1379let prefersSlot3 = 1;
1380let Defs = [USR_OVF];
1381let InputType = "reg";
1382}
1383def A2_swiz : HInst<
1384(outs IntRegs:$Rd32),
1385(ins IntRegs:$Rs32),
1386"$Rd32 = swiz($Rs32)",
1387tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1388let Inst{13-5} = 0b000000111;
1389let Inst{31-21} = 0b10001100100;
1390let hasNewValue = 1;
1391let opNewValue = 0;
1392}
1393def A2_sxtb : HInst<
1394(outs IntRegs:$Rd32),
1395(ins IntRegs:$Rs32),
1396"$Rd32 = sxtb($Rs32)",
1397tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1398let Inst{13-5} = 0b000000000;
1399let Inst{31-21} = 0b01110000101;
1400let hasNewValue = 1;
1401let opNewValue = 0;
1402let BaseOpcode = "A2_sxtb";
1403let isPredicable = 1;
1404}
1405def A2_sxth : HInst<
1406(outs IntRegs:$Rd32),
1407(ins IntRegs:$Rs32),
1408"$Rd32 = sxth($Rs32)",
1409tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1410let Inst{13-5} = 0b000000000;
1411let Inst{31-21} = 0b01110000111;
1412let hasNewValue = 1;
1413let opNewValue = 0;
1414let BaseOpcode = "A2_sxth";
1415let isPredicable = 1;
1416}
1417def A2_sxtw : HInst<
1418(outs DoubleRegs:$Rdd32),
1419(ins IntRegs:$Rs32),
1420"$Rdd32 = sxtw($Rs32)",
1421tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
1422let Inst{13-5} = 0b000000000;
1423let Inst{31-21} = 0b10000100010;
1424}
1425def A2_tfr : HInst<
1426(outs IntRegs:$Rd32),
1427(ins IntRegs:$Rs32),
1428"$Rd32 = $Rs32",
1429tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1430let Inst{13-5} = 0b000000000;
1431let Inst{31-21} = 0b01110000011;
1432let hasNewValue = 1;
1433let opNewValue = 0;
1434let BaseOpcode = "A2_tfr";
1435let InputType = "reg";
1436let isPredicable = 1;
1437}
1438def A2_tfrcrr : HInst<
1439(outs IntRegs:$Rd32),
1440(ins CtrRegs:$Cs32),
1441"$Rd32 = $Cs32",
1442tc_7476d766, TypeCR>, Enc_0cb018 {
1443let Inst{13-5} = 0b000000000;
1444let Inst{31-21} = 0b01101010000;
1445let hasNewValue = 1;
1446let opNewValue = 0;
1447}
1448def A2_tfrf : HInst<
1449(outs IntRegs:$Rd32),
1450(ins PredRegs:$Pu4, IntRegs:$Rs32),
1451"if (!$Pu4) $Rd32 = $Rs32",
1452tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1453let isPredicated = 1;
1454let isPredicatedFalse = 1;
1455let hasNewValue = 1;
1456let opNewValue = 0;
1457let BaseOpcode = "A2_tfr";
1458let CextOpcode = "A2_tfr";
1459let InputType = "reg";
1460let isPseudo = 1;
1461let isCodeGenOnly = 1;
1462}
1463def A2_tfrfnew : HInst<
1464(outs IntRegs:$Rd32),
1465(ins PredRegs:$Pu4, IntRegs:$Rs32),
1466"if (!$Pu4.new) $Rd32 = $Rs32",
1467tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1468let isPredicated = 1;
1469let isPredicatedFalse = 1;
1470let hasNewValue = 1;
1471let opNewValue = 0;
1472let isPredicatedNew = 1;
1473let BaseOpcode = "A2_tfr";
1474let CextOpcode = "A2_tfr";
1475let InputType = "reg";
1476let isPseudo = 1;
1477let isCodeGenOnly = 1;
1478}
1479def A2_tfrih : HInst<
1480(outs IntRegs:$Rx32),
1481(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1482"$Rx32.h = #$Ii",
1483tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1484let Inst{21-21} = 0b1;
1485let Inst{31-24} = 0b01110010;
1486let hasNewValue = 1;
1487let opNewValue = 0;
1488let Constraints = "$Rx32 = $Rx32in";
1489}
1490def A2_tfril : HInst<
1491(outs IntRegs:$Rx32),
1492(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1493"$Rx32.l = #$Ii",
1494tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1495let Inst{21-21} = 0b1;
1496let Inst{31-24} = 0b01110001;
1497let hasNewValue = 1;
1498let opNewValue = 0;
1499let Constraints = "$Rx32 = $Rx32in";
1500}
1501def A2_tfrp : HInst<
1502(outs DoubleRegs:$Rdd32),
1503(ins DoubleRegs:$Rss32),
1504"$Rdd32 = $Rss32",
1505tc_713b66bf, TypeALU32_2op>, PredNewRel {
1506let BaseOpcode = "A2_tfrp";
1507let isPredicable = 1;
1508let isPseudo = 1;
1509}
1510def A2_tfrpf : HInst<
1511(outs DoubleRegs:$Rdd32),
1512(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1513"if (!$Pu4) $Rdd32 = $Rss32",
1514tc_713b66bf, TypeALU32_2op>, PredNewRel {
1515let isPredicated = 1;
1516let isPredicatedFalse = 1;
1517let BaseOpcode = "A2_tfrp";
1518let isPseudo = 1;
1519}
1520def A2_tfrpfnew : HInst<
1521(outs DoubleRegs:$Rdd32),
1522(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1523"if (!$Pu4.new) $Rdd32 = $Rss32",
1524tc_86173609, TypeALU32_2op>, PredNewRel {
1525let isPredicated = 1;
1526let isPredicatedFalse = 1;
1527let isPredicatedNew = 1;
1528let BaseOpcode = "A2_tfrp";
1529let isPseudo = 1;
1530}
1531def A2_tfrpi : HInst<
1532(outs DoubleRegs:$Rdd32),
1533(ins s8_0Imm:$Ii),
1534"$Rdd32 = #$Ii",
1535tc_713b66bf, TypeALU64> {
1536let isAsCheapAsAMove = 1;
1537let isMoveImm = 1;
1538let isReMaterializable = 1;
1539let isPseudo = 1;
1540}
1541def A2_tfrpt : HInst<
1542(outs DoubleRegs:$Rdd32),
1543(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1544"if ($Pu4) $Rdd32 = $Rss32",
1545tc_713b66bf, TypeALU32_2op>, PredNewRel {
1546let isPredicated = 1;
1547let BaseOpcode = "A2_tfrp";
1548let isPseudo = 1;
1549}
1550def A2_tfrptnew : HInst<
1551(outs DoubleRegs:$Rdd32),
1552(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1553"if ($Pu4.new) $Rdd32 = $Rss32",
1554tc_86173609, TypeALU32_2op>, PredNewRel {
1555let isPredicated = 1;
1556let isPredicatedNew = 1;
1557let BaseOpcode = "A2_tfrp";
1558let isPseudo = 1;
1559}
1560def A2_tfrrcr : HInst<
1561(outs CtrRegs:$Cd32),
1562(ins IntRegs:$Rs32),
1563"$Cd32 = $Rs32",
1564tc_49fdfd4b, TypeCR>, Enc_bd811a {
1565let Inst{13-5} = 0b000000000;
1566let Inst{31-21} = 0b01100010001;
1567let hasNewValue = 1;
1568let opNewValue = 0;
1569}
1570def A2_tfrsi : HInst<
1571(outs IntRegs:$Rd32),
1572(ins s32_0Imm:$Ii),
1573"$Rd32 = #$Ii",
1574tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
1575let Inst{21-21} = 0b0;
1576let Inst{31-24} = 0b01111000;
1577let hasNewValue = 1;
1578let opNewValue = 0;
1579let BaseOpcode = "A2_tfrsi";
1580let CextOpcode = "A2_tfr";
1581let InputType = "imm";
1582let isAsCheapAsAMove = 1;
1583let isMoveImm = 1;
1584let isPredicable = 1;
1585let isReMaterializable = 1;
1586let isExtendable = 1;
1587let opExtendable = 1;
1588let isExtentSigned = 1;
1589let opExtentBits = 16;
1590let opExtentAlign = 0;
1591}
1592def A2_tfrt : HInst<
1593(outs IntRegs:$Rd32),
1594(ins PredRegs:$Pu4, IntRegs:$Rs32),
1595"if ($Pu4) $Rd32 = $Rs32",
1596tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1597let isPredicated = 1;
1598let hasNewValue = 1;
1599let opNewValue = 0;
1600let BaseOpcode = "A2_tfr";
1601let CextOpcode = "A2_tfr";
1602let InputType = "reg";
1603let isPseudo = 1;
1604let isCodeGenOnly = 1;
1605}
1606def A2_tfrtnew : HInst<
1607(outs IntRegs:$Rd32),
1608(ins PredRegs:$Pu4, IntRegs:$Rs32),
1609"if ($Pu4.new) $Rd32 = $Rs32",
1610tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1611let isPredicated = 1;
1612let hasNewValue = 1;
1613let opNewValue = 0;
1614let isPredicatedNew = 1;
1615let BaseOpcode = "A2_tfr";
1616let CextOpcode = "A2_tfr";
1617let InputType = "reg";
1618let isPseudo = 1;
1619let isCodeGenOnly = 1;
1620}
1621def A2_vabsh : HInst<
1622(outs DoubleRegs:$Rdd32),
1623(ins DoubleRegs:$Rss32),
1624"$Rdd32 = vabsh($Rss32)",
1625tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1626let Inst{13-5} = 0b000000100;
1627let Inst{31-21} = 0b10000000010;
1628let prefersSlot3 = 1;
1629}
1630def A2_vabshsat : HInst<
1631(outs DoubleRegs:$Rdd32),
1632(ins DoubleRegs:$Rss32),
1633"$Rdd32 = vabsh($Rss32):sat",
1634tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1635let Inst{13-5} = 0b000000101;
1636let Inst{31-21} = 0b10000000010;
1637let prefersSlot3 = 1;
1638let Defs = [USR_OVF];
1639}
1640def A2_vabsw : HInst<
1641(outs DoubleRegs:$Rdd32),
1642(ins DoubleRegs:$Rss32),
1643"$Rdd32 = vabsw($Rss32)",
1644tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1645let Inst{13-5} = 0b000000110;
1646let Inst{31-21} = 0b10000000010;
1647let prefersSlot3 = 1;
1648}
1649def A2_vabswsat : HInst<
1650(outs DoubleRegs:$Rdd32),
1651(ins DoubleRegs:$Rss32),
1652"$Rdd32 = vabsw($Rss32):sat",
1653tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1654let Inst{13-5} = 0b000000111;
1655let Inst{31-21} = 0b10000000010;
1656let prefersSlot3 = 1;
1657let Defs = [USR_OVF];
1658}
1659def A2_vaddb_map : HInst<
1660(outs DoubleRegs:$Rdd32),
1661(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1662"$Rdd32 = vaddb($Rss32,$Rtt32)",
1663tc_5da50c4b, TypeMAPPING> {
1664let isPseudo = 1;
1665let isCodeGenOnly = 1;
1666}
1667def A2_vaddh : HInst<
1668(outs DoubleRegs:$Rdd32),
1669(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1670"$Rdd32 = vaddh($Rss32,$Rtt32)",
1671tc_5da50c4b, TypeALU64>, Enc_a56825 {
1672let Inst{7-5} = 0b010;
1673let Inst{13-13} = 0b0;
1674let Inst{31-21} = 0b11010011000;
1675}
1676def A2_vaddhs : HInst<
1677(outs DoubleRegs:$Rdd32),
1678(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1679"$Rdd32 = vaddh($Rss32,$Rtt32):sat",
1680tc_8a825db2, TypeALU64>, Enc_a56825 {
1681let Inst{7-5} = 0b011;
1682let Inst{13-13} = 0b0;
1683let Inst{31-21} = 0b11010011000;
1684let prefersSlot3 = 1;
1685let Defs = [USR_OVF];
1686}
1687def A2_vaddub : HInst<
1688(outs DoubleRegs:$Rdd32),
1689(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1690"$Rdd32 = vaddub($Rss32,$Rtt32)",
1691tc_5da50c4b, TypeALU64>, Enc_a56825 {
1692let Inst{7-5} = 0b000;
1693let Inst{13-13} = 0b0;
1694let Inst{31-21} = 0b11010011000;
1695}
1696def A2_vaddubs : HInst<
1697(outs DoubleRegs:$Rdd32),
1698(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1699"$Rdd32 = vaddub($Rss32,$Rtt32):sat",
1700tc_8a825db2, TypeALU64>, Enc_a56825 {
1701let Inst{7-5} = 0b001;
1702let Inst{13-13} = 0b0;
1703let Inst{31-21} = 0b11010011000;
1704let prefersSlot3 = 1;
1705let Defs = [USR_OVF];
1706}
1707def A2_vadduhs : HInst<
1708(outs DoubleRegs:$Rdd32),
1709(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1710"$Rdd32 = vadduh($Rss32,$Rtt32):sat",
1711tc_8a825db2, TypeALU64>, Enc_a56825 {
1712let Inst{7-5} = 0b100;
1713let Inst{13-13} = 0b0;
1714let Inst{31-21} = 0b11010011000;
1715let prefersSlot3 = 1;
1716let Defs = [USR_OVF];
1717}
1718def A2_vaddw : HInst<
1719(outs DoubleRegs:$Rdd32),
1720(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1721"$Rdd32 = vaddw($Rss32,$Rtt32)",
1722tc_5da50c4b, TypeALU64>, Enc_a56825 {
1723let Inst{7-5} = 0b101;
1724let Inst{13-13} = 0b0;
1725let Inst{31-21} = 0b11010011000;
1726}
1727def A2_vaddws : HInst<
1728(outs DoubleRegs:$Rdd32),
1729(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1730"$Rdd32 = vaddw($Rss32,$Rtt32):sat",
1731tc_8a825db2, TypeALU64>, Enc_a56825 {
1732let Inst{7-5} = 0b110;
1733let Inst{13-13} = 0b0;
1734let Inst{31-21} = 0b11010011000;
1735let prefersSlot3 = 1;
1736let Defs = [USR_OVF];
1737}
1738def A2_vavgh : HInst<
1739(outs DoubleRegs:$Rdd32),
1740(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1741"$Rdd32 = vavgh($Rss32,$Rtt32)",
1742tc_f098b237, TypeALU64>, Enc_a56825 {
1743let Inst{7-5} = 0b010;
1744let Inst{13-13} = 0b0;
1745let Inst{31-21} = 0b11010011010;
1746let prefersSlot3 = 1;
1747}
1748def A2_vavghcr : HInst<
1749(outs DoubleRegs:$Rdd32),
1750(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1751"$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
1752tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1753let Inst{7-5} = 0b100;
1754let Inst{13-13} = 0b0;
1755let Inst{31-21} = 0b11010011010;
1756let prefersSlot3 = 1;
1757}
1758def A2_vavghr : HInst<
1759(outs DoubleRegs:$Rdd32),
1760(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1761"$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
1762tc_20131976, TypeALU64>, Enc_a56825 {
1763let Inst{7-5} = 0b011;
1764let Inst{13-13} = 0b0;
1765let Inst{31-21} = 0b11010011010;
1766let prefersSlot3 = 1;
1767}
1768def A2_vavgub : HInst<
1769(outs DoubleRegs:$Rdd32),
1770(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1771"$Rdd32 = vavgub($Rss32,$Rtt32)",
1772tc_f098b237, TypeALU64>, Enc_a56825 {
1773let Inst{7-5} = 0b000;
1774let Inst{13-13} = 0b0;
1775let Inst{31-21} = 0b11010011010;
1776let prefersSlot3 = 1;
1777}
1778def A2_vavgubr : HInst<
1779(outs DoubleRegs:$Rdd32),
1780(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1781"$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
1782tc_20131976, TypeALU64>, Enc_a56825 {
1783let Inst{7-5} = 0b001;
1784let Inst{13-13} = 0b0;
1785let Inst{31-21} = 0b11010011010;
1786let prefersSlot3 = 1;
1787}
1788def A2_vavguh : HInst<
1789(outs DoubleRegs:$Rdd32),
1790(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1791"$Rdd32 = vavguh($Rss32,$Rtt32)",
1792tc_f098b237, TypeALU64>, Enc_a56825 {
1793let Inst{7-5} = 0b101;
1794let Inst{13-13} = 0b0;
1795let Inst{31-21} = 0b11010011010;
1796let prefersSlot3 = 1;
1797}
1798def A2_vavguhr : HInst<
1799(outs DoubleRegs:$Rdd32),
1800(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1801"$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
1802tc_20131976, TypeALU64>, Enc_a56825 {
1803let Inst{7-5} = 0b110;
1804let Inst{13-13} = 0b0;
1805let Inst{31-21} = 0b11010011010;
1806let prefersSlot3 = 1;
1807}
1808def A2_vavguw : HInst<
1809(outs DoubleRegs:$Rdd32),
1810(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1811"$Rdd32 = vavguw($Rss32,$Rtt32)",
1812tc_f098b237, TypeALU64>, Enc_a56825 {
1813let Inst{7-5} = 0b011;
1814let Inst{13-13} = 0b0;
1815let Inst{31-21} = 0b11010011011;
1816let prefersSlot3 = 1;
1817}
1818def A2_vavguwr : HInst<
1819(outs DoubleRegs:$Rdd32),
1820(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1821"$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
1822tc_20131976, TypeALU64>, Enc_a56825 {
1823let Inst{7-5} = 0b100;
1824let Inst{13-13} = 0b0;
1825let Inst{31-21} = 0b11010011011;
1826let prefersSlot3 = 1;
1827}
1828def A2_vavgw : HInst<
1829(outs DoubleRegs:$Rdd32),
1830(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1831"$Rdd32 = vavgw($Rss32,$Rtt32)",
1832tc_f098b237, TypeALU64>, Enc_a56825 {
1833let Inst{7-5} = 0b000;
1834let Inst{13-13} = 0b0;
1835let Inst{31-21} = 0b11010011011;
1836let prefersSlot3 = 1;
1837}
1838def A2_vavgwcr : HInst<
1839(outs DoubleRegs:$Rdd32),
1840(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1841"$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
1842tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1843let Inst{7-5} = 0b010;
1844let Inst{13-13} = 0b0;
1845let Inst{31-21} = 0b11010011011;
1846let prefersSlot3 = 1;
1847}
1848def A2_vavgwr : HInst<
1849(outs DoubleRegs:$Rdd32),
1850(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1851"$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
1852tc_20131976, TypeALU64>, Enc_a56825 {
1853let Inst{7-5} = 0b001;
1854let Inst{13-13} = 0b0;
1855let Inst{31-21} = 0b11010011011;
1856let prefersSlot3 = 1;
1857}
1858def A2_vcmpbeq : HInst<
1859(outs PredRegs:$Pd4),
1860(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1861"$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
1862tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1863let Inst{7-2} = 0b110000;
1864let Inst{13-13} = 0b0;
1865let Inst{31-21} = 0b11010010000;
1866}
1867def A2_vcmpbgtu : HInst<
1868(outs PredRegs:$Pd4),
1869(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1870"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
1871tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1872let Inst{7-2} = 0b111000;
1873let Inst{13-13} = 0b0;
1874let Inst{31-21} = 0b11010010000;
1875}
1876def A2_vcmpheq : HInst<
1877(outs PredRegs:$Pd4),
1878(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1879"$Pd4 = vcmph.eq($Rss32,$Rtt32)",
1880tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1881let Inst{7-2} = 0b011000;
1882let Inst{13-13} = 0b0;
1883let Inst{31-21} = 0b11010010000;
1884}
1885def A2_vcmphgt : HInst<
1886(outs PredRegs:$Pd4),
1887(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1888"$Pd4 = vcmph.gt($Rss32,$Rtt32)",
1889tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1890let Inst{7-2} = 0b100000;
1891let Inst{13-13} = 0b0;
1892let Inst{31-21} = 0b11010010000;
1893}
1894def A2_vcmphgtu : HInst<
1895(outs PredRegs:$Pd4),
1896(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1897"$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
1898tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1899let Inst{7-2} = 0b101000;
1900let Inst{13-13} = 0b0;
1901let Inst{31-21} = 0b11010010000;
1902}
1903def A2_vcmpweq : HInst<
1904(outs PredRegs:$Pd4),
1905(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1906"$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
1907tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1908let Inst{7-2} = 0b000000;
1909let Inst{13-13} = 0b0;
1910let Inst{31-21} = 0b11010010000;
1911}
1912def A2_vcmpwgt : HInst<
1913(outs PredRegs:$Pd4),
1914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1915"$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
1916tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1917let Inst{7-2} = 0b001000;
1918let Inst{13-13} = 0b0;
1919let Inst{31-21} = 0b11010010000;
1920}
1921def A2_vcmpwgtu : HInst<
1922(outs PredRegs:$Pd4),
1923(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1924"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
1925tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1926let Inst{7-2} = 0b010000;
1927let Inst{13-13} = 0b0;
1928let Inst{31-21} = 0b11010010000;
1929}
1930def A2_vconj : HInst<
1931(outs DoubleRegs:$Rdd32),
1932(ins DoubleRegs:$Rss32),
1933"$Rdd32 = vconj($Rss32):sat",
1934tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1935let Inst{13-5} = 0b000000111;
1936let Inst{31-21} = 0b10000000100;
1937let prefersSlot3 = 1;
1938let Defs = [USR_OVF];
1939}
1940def A2_vmaxb : HInst<
1941(outs DoubleRegs:$Rdd32),
1942(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1943"$Rdd32 = vmaxb($Rtt32,$Rss32)",
1944tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1945let Inst{7-5} = 0b110;
1946let Inst{13-13} = 0b0;
1947let Inst{31-21} = 0b11010011110;
1948let prefersSlot3 = 1;
1949}
1950def A2_vmaxh : HInst<
1951(outs DoubleRegs:$Rdd32),
1952(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1953"$Rdd32 = vmaxh($Rtt32,$Rss32)",
1954tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1955let Inst{7-5} = 0b001;
1956let Inst{13-13} = 0b0;
1957let Inst{31-21} = 0b11010011110;
1958let prefersSlot3 = 1;
1959}
1960def A2_vmaxub : HInst<
1961(outs DoubleRegs:$Rdd32),
1962(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1963"$Rdd32 = vmaxub($Rtt32,$Rss32)",
1964tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1965let Inst{7-5} = 0b000;
1966let Inst{13-13} = 0b0;
1967let Inst{31-21} = 0b11010011110;
1968let prefersSlot3 = 1;
1969}
1970def A2_vmaxuh : HInst<
1971(outs DoubleRegs:$Rdd32),
1972(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1973"$Rdd32 = vmaxuh($Rtt32,$Rss32)",
1974tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1975let Inst{7-5} = 0b010;
1976let Inst{13-13} = 0b0;
1977let Inst{31-21} = 0b11010011110;
1978let prefersSlot3 = 1;
1979}
1980def A2_vmaxuw : HInst<
1981(outs DoubleRegs:$Rdd32),
1982(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1983"$Rdd32 = vmaxuw($Rtt32,$Rss32)",
1984tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1985let Inst{7-5} = 0b101;
1986let Inst{13-13} = 0b0;
1987let Inst{31-21} = 0b11010011101;
1988let prefersSlot3 = 1;
1989}
1990def A2_vmaxw : HInst<
1991(outs DoubleRegs:$Rdd32),
1992(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1993"$Rdd32 = vmaxw($Rtt32,$Rss32)",
1994tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1995let Inst{7-5} = 0b011;
1996let Inst{13-13} = 0b0;
1997let Inst{31-21} = 0b11010011110;
1998let prefersSlot3 = 1;
1999}
2000def A2_vminb : HInst<
2001(outs DoubleRegs:$Rdd32),
2002(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2003"$Rdd32 = vminb($Rtt32,$Rss32)",
2004tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2005let Inst{7-5} = 0b111;
2006let Inst{13-13} = 0b0;
2007let Inst{31-21} = 0b11010011110;
2008let prefersSlot3 = 1;
2009}
2010def A2_vminh : HInst<
2011(outs DoubleRegs:$Rdd32),
2012(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2013"$Rdd32 = vminh($Rtt32,$Rss32)",
2014tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2015let Inst{7-5} = 0b001;
2016let Inst{13-13} = 0b0;
2017let Inst{31-21} = 0b11010011101;
2018let prefersSlot3 = 1;
2019}
2020def A2_vminub : HInst<
2021(outs DoubleRegs:$Rdd32),
2022(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2023"$Rdd32 = vminub($Rtt32,$Rss32)",
2024tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2025let Inst{7-5} = 0b000;
2026let Inst{13-13} = 0b0;
2027let Inst{31-21} = 0b11010011101;
2028let prefersSlot3 = 1;
2029}
2030def A2_vminuh : HInst<
2031(outs DoubleRegs:$Rdd32),
2032(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2033"$Rdd32 = vminuh($Rtt32,$Rss32)",
2034tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2035let Inst{7-5} = 0b010;
2036let Inst{13-13} = 0b0;
2037let Inst{31-21} = 0b11010011101;
2038let prefersSlot3 = 1;
2039}
2040def A2_vminuw : HInst<
2041(outs DoubleRegs:$Rdd32),
2042(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2043"$Rdd32 = vminuw($Rtt32,$Rss32)",
2044tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2045let Inst{7-5} = 0b100;
2046let Inst{13-13} = 0b0;
2047let Inst{31-21} = 0b11010011101;
2048let prefersSlot3 = 1;
2049}
2050def A2_vminw : HInst<
2051(outs DoubleRegs:$Rdd32),
2052(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2053"$Rdd32 = vminw($Rtt32,$Rss32)",
2054tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2055let Inst{7-5} = 0b011;
2056let Inst{13-13} = 0b0;
2057let Inst{31-21} = 0b11010011101;
2058let prefersSlot3 = 1;
2059}
2060def A2_vnavgh : HInst<
2061(outs DoubleRegs:$Rdd32),
2062(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2063"$Rdd32 = vnavgh($Rtt32,$Rss32)",
2064tc_f098b237, TypeALU64>, Enc_ea23e4 {
2065let Inst{7-5} = 0b000;
2066let Inst{13-13} = 0b0;
2067let Inst{31-21} = 0b11010011100;
2068let prefersSlot3 = 1;
2069}
2070def A2_vnavghcr : HInst<
2071(outs DoubleRegs:$Rdd32),
2072(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2073"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
2074tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2075let Inst{7-5} = 0b010;
2076let Inst{13-13} = 0b0;
2077let Inst{31-21} = 0b11010011100;
2078let prefersSlot3 = 1;
2079let Defs = [USR_OVF];
2080}
2081def A2_vnavghr : HInst<
2082(outs DoubleRegs:$Rdd32),
2083(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2084"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
2085tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2086let Inst{7-5} = 0b001;
2087let Inst{13-13} = 0b0;
2088let Inst{31-21} = 0b11010011100;
2089let prefersSlot3 = 1;
2090let Defs = [USR_OVF];
2091}
2092def A2_vnavgw : HInst<
2093(outs DoubleRegs:$Rdd32),
2094(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2095"$Rdd32 = vnavgw($Rtt32,$Rss32)",
2096tc_f098b237, TypeALU64>, Enc_ea23e4 {
2097let Inst{7-5} = 0b011;
2098let Inst{13-13} = 0b0;
2099let Inst{31-21} = 0b11010011100;
2100let prefersSlot3 = 1;
2101}
2102def A2_vnavgwcr : HInst<
2103(outs DoubleRegs:$Rdd32),
2104(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2105"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
2106tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2107let Inst{7-5} = 0b110;
2108let Inst{13-13} = 0b0;
2109let Inst{31-21} = 0b11010011100;
2110let prefersSlot3 = 1;
2111let Defs = [USR_OVF];
2112}
2113def A2_vnavgwr : HInst<
2114(outs DoubleRegs:$Rdd32),
2115(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2116"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
2117tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2118let Inst{7-5} = 0b100;
2119let Inst{13-13} = 0b0;
2120let Inst{31-21} = 0b11010011100;
2121let prefersSlot3 = 1;
2122let Defs = [USR_OVF];
2123}
2124def A2_vraddub : HInst<
2125(outs DoubleRegs:$Rdd32),
2126(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2127"$Rdd32 = vraddub($Rss32,$Rtt32)",
2128tc_c21d7447, TypeM>, Enc_a56825 {
2129let Inst{7-5} = 0b001;
2130let Inst{13-13} = 0b0;
2131let Inst{31-21} = 0b11101000010;
2132let prefersSlot3 = 1;
2133}
2134def A2_vraddub_acc : HInst<
2135(outs DoubleRegs:$Rxx32),
2136(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2137"$Rxx32 += vraddub($Rss32,$Rtt32)",
2138tc_7f8ae742, TypeM>, Enc_88c16c {
2139let Inst{7-5} = 0b001;
2140let Inst{13-13} = 0b0;
2141let Inst{31-21} = 0b11101010010;
2142let prefersSlot3 = 1;
2143let Constraints = "$Rxx32 = $Rxx32in";
2144}
2145def A2_vrsadub : HInst<
2146(outs DoubleRegs:$Rdd32),
2147(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2148"$Rdd32 = vrsadub($Rss32,$Rtt32)",
2149tc_c21d7447, TypeM>, Enc_a56825 {
2150let Inst{7-5} = 0b010;
2151let Inst{13-13} = 0b0;
2152let Inst{31-21} = 0b11101000010;
2153let prefersSlot3 = 1;
2154}
2155def A2_vrsadub_acc : HInst<
2156(outs DoubleRegs:$Rxx32),
2157(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2158"$Rxx32 += vrsadub($Rss32,$Rtt32)",
2159tc_7f8ae742, TypeM>, Enc_88c16c {
2160let Inst{7-5} = 0b010;
2161let Inst{13-13} = 0b0;
2162let Inst{31-21} = 0b11101010010;
2163let prefersSlot3 = 1;
2164let Constraints = "$Rxx32 = $Rxx32in";
2165}
2166def A2_vsubb_map : HInst<
2167(outs DoubleRegs:$Rdd32),
2168(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2169"$Rdd32 = vsubb($Rss32,$Rtt32)",
2170tc_5da50c4b, TypeMAPPING> {
2171let isPseudo = 1;
2172let isCodeGenOnly = 1;
2173}
2174def A2_vsubh : HInst<
2175(outs DoubleRegs:$Rdd32),
2176(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2177"$Rdd32 = vsubh($Rtt32,$Rss32)",
2178tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2179let Inst{7-5} = 0b010;
2180let Inst{13-13} = 0b0;
2181let Inst{31-21} = 0b11010011001;
2182}
2183def A2_vsubhs : HInst<
2184(outs DoubleRegs:$Rdd32),
2185(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2186"$Rdd32 = vsubh($Rtt32,$Rss32):sat",
2187tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2188let Inst{7-5} = 0b011;
2189let Inst{13-13} = 0b0;
2190let Inst{31-21} = 0b11010011001;
2191let prefersSlot3 = 1;
2192let Defs = [USR_OVF];
2193}
2194def A2_vsubub : HInst<
2195(outs DoubleRegs:$Rdd32),
2196(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2197"$Rdd32 = vsubub($Rtt32,$Rss32)",
2198tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2199let Inst{7-5} = 0b000;
2200let Inst{13-13} = 0b0;
2201let Inst{31-21} = 0b11010011001;
2202}
2203def A2_vsububs : HInst<
2204(outs DoubleRegs:$Rdd32),
2205(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2206"$Rdd32 = vsubub($Rtt32,$Rss32):sat",
2207tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2208let Inst{7-5} = 0b001;
2209let Inst{13-13} = 0b0;
2210let Inst{31-21} = 0b11010011001;
2211let prefersSlot3 = 1;
2212let Defs = [USR_OVF];
2213}
2214def A2_vsubuhs : HInst<
2215(outs DoubleRegs:$Rdd32),
2216(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2217"$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
2218tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2219let Inst{7-5} = 0b100;
2220let Inst{13-13} = 0b0;
2221let Inst{31-21} = 0b11010011001;
2222let prefersSlot3 = 1;
2223let Defs = [USR_OVF];
2224}
2225def A2_vsubw : HInst<
2226(outs DoubleRegs:$Rdd32),
2227(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2228"$Rdd32 = vsubw($Rtt32,$Rss32)",
2229tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2230let Inst{7-5} = 0b101;
2231let Inst{13-13} = 0b0;
2232let Inst{31-21} = 0b11010011001;
2233}
2234def A2_vsubws : HInst<
2235(outs DoubleRegs:$Rdd32),
2236(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2237"$Rdd32 = vsubw($Rtt32,$Rss32):sat",
2238tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2239let Inst{7-5} = 0b110;
2240let Inst{13-13} = 0b0;
2241let Inst{31-21} = 0b11010011001;
2242let prefersSlot3 = 1;
2243let Defs = [USR_OVF];
2244}
2245def A2_xor : HInst<
2246(outs IntRegs:$Rd32),
2247(ins IntRegs:$Rs32, IntRegs:$Rt32),
2248"$Rd32 = xor($Rs32,$Rt32)",
2249tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
2250let Inst{7-5} = 0b000;
2251let Inst{13-13} = 0b0;
2252let Inst{31-21} = 0b11110001011;
2253let hasNewValue = 1;
2254let opNewValue = 0;
2255let BaseOpcode = "A2_xor";
2256let InputType = "reg";
2257let isCommutable = 1;
2258let isPredicable = 1;
2259}
2260def A2_xorp : HInst<
2261(outs DoubleRegs:$Rdd32),
2262(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2263"$Rdd32 = xor($Rss32,$Rtt32)",
2264tc_5da50c4b, TypeALU64>, Enc_a56825 {
2265let Inst{7-5} = 0b100;
2266let Inst{13-13} = 0b0;
2267let Inst{31-21} = 0b11010011111;
2268let isCommutable = 1;
2269}
2270def A2_zxtb : HInst<
2271(outs IntRegs:$Rd32),
2272(ins IntRegs:$Rs32),
2273"$Rd32 = zxtb($Rs32)",
2274tc_713b66bf, TypeALU32_2op>, PredNewRel {
2275let hasNewValue = 1;
2276let opNewValue = 0;
2277let BaseOpcode = "A2_zxtb";
2278let isPredicable = 1;
2279let isPseudo = 1;
2280let isCodeGenOnly = 1;
2281}
2282def A2_zxth : HInst<
2283(outs IntRegs:$Rd32),
2284(ins IntRegs:$Rs32),
2285"$Rd32 = zxth($Rs32)",
2286tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
2287let Inst{13-5} = 0b000000000;
2288let Inst{31-21} = 0b01110000110;
2289let hasNewValue = 1;
2290let opNewValue = 0;
2291let BaseOpcode = "A2_zxth";
2292let isPredicable = 1;
2293}
2294def A4_addp_c : HInst<
2295(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
2296(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
2297"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
2298tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
2299let Inst{7-7} = 0b0;
2300let Inst{13-13} = 0b0;
2301let Inst{31-21} = 0b11000010110;
2302let isPredicateLate = 1;
2303let Constraints = "$Px4 = $Px4in";
2304}
2305def A4_andn : HInst<
2306(outs IntRegs:$Rd32),
2307(ins IntRegs:$Rt32, IntRegs:$Rs32),
2308"$Rd32 = and($Rt32,~$Rs32)",
2309tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2310let Inst{7-5} = 0b000;
2311let Inst{13-13} = 0b0;
2312let Inst{31-21} = 0b11110001100;
2313let hasNewValue = 1;
2314let opNewValue = 0;
2315let InputType = "reg";
2316}
2317def A4_andnp : HInst<
2318(outs DoubleRegs:$Rdd32),
2319(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2320"$Rdd32 = and($Rtt32,~$Rss32)",
2321tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2322let Inst{7-5} = 0b001;
2323let Inst{13-13} = 0b0;
2324let Inst{31-21} = 0b11010011111;
2325}
2326def A4_bitsplit : HInst<
2327(outs DoubleRegs:$Rdd32),
2328(ins IntRegs:$Rs32, IntRegs:$Rt32),
2329"$Rdd32 = bitsplit($Rs32,$Rt32)",
2330tc_f34c1c21, TypeALU64>, Enc_be32a5 {
2331let Inst{7-5} = 0b000;
2332let Inst{13-13} = 0b0;
2333let Inst{31-21} = 0b11010100001;
2334let prefersSlot3 = 1;
2335}
2336def A4_bitspliti : HInst<
2337(outs DoubleRegs:$Rdd32),
2338(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2339"$Rdd32 = bitsplit($Rs32,#$Ii)",
2340tc_f34c1c21, TypeS_2op>, Enc_311abd {
2341let Inst{7-5} = 0b100;
2342let Inst{13-13} = 0b0;
2343let Inst{31-21} = 0b10001000110;
2344let prefersSlot3 = 1;
2345}
2346def A4_boundscheck : HInst<
2347(outs PredRegs:$Pd4),
2348(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
2349"$Pd4 = boundscheck($Rs32,$Rtt32)",
2350tc_4a55d03c, TypeALU64> {
2351let isPseudo = 1;
2352}
2353def A4_boundscheck_hi : HInst<
2354(outs PredRegs:$Pd4),
2355(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2356"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
2357tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2358let Inst{7-2} = 0b101000;
2359let Inst{13-13} = 0b1;
2360let Inst{31-21} = 0b11010010000;
2361}
2362def A4_boundscheck_lo : HInst<
2363(outs PredRegs:$Pd4),
2364(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2365"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
2366tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2367let Inst{7-2} = 0b100000;
2368let Inst{13-13} = 0b1;
2369let Inst{31-21} = 0b11010010000;
2370}
2371def A4_cmpbeq : HInst<
2372(outs PredRegs:$Pd4),
2373(ins IntRegs:$Rs32, IntRegs:$Rt32),
2374"$Pd4 = cmpb.eq($Rs32,$Rt32)",
2375tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2376let Inst{7-2} = 0b110000;
2377let Inst{13-13} = 0b0;
2378let Inst{31-21} = 0b11000111110;
2379let CextOpcode = "A4_cmpbeq";
2380let InputType = "reg";
2381let isCommutable = 1;
2382let isCompare = 1;
2383}
2384def A4_cmpbeqi : HInst<
2385(outs PredRegs:$Pd4),
2386(ins IntRegs:$Rs32, u8_0Imm:$Ii),
2387"$Pd4 = cmpb.eq($Rs32,#$Ii)",
2388tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2389let Inst{4-2} = 0b000;
2390let Inst{13-13} = 0b0;
2391let Inst{31-21} = 0b11011101000;
2392let CextOpcode = "A4_cmpbeq";
2393let InputType = "imm";
2394let isCommutable = 1;
2395let isCompare = 1;
2396}
2397def A4_cmpbgt : HInst<
2398(outs PredRegs:$Pd4),
2399(ins IntRegs:$Rs32, IntRegs:$Rt32),
2400"$Pd4 = cmpb.gt($Rs32,$Rt32)",
2401tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2402let Inst{7-2} = 0b010000;
2403let Inst{13-13} = 0b0;
2404let Inst{31-21} = 0b11000111110;
2405let CextOpcode = "A4_cmpbgt";
2406let InputType = "reg";
2407let isCompare = 1;
2408}
2409def A4_cmpbgti : HInst<
2410(outs PredRegs:$Pd4),
2411(ins IntRegs:$Rs32, s8_0Imm:$Ii),
2412"$Pd4 = cmpb.gt($Rs32,#$Ii)",
2413tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2414let Inst{4-2} = 0b000;
2415let Inst{13-13} = 0b0;
2416let Inst{31-21} = 0b11011101001;
2417let CextOpcode = "A4_cmpbgt";
2418let InputType = "imm";
2419let isCompare = 1;
2420}
2421def A4_cmpbgtu : HInst<
2422(outs PredRegs:$Pd4),
2423(ins IntRegs:$Rs32, IntRegs:$Rt32),
2424"$Pd4 = cmpb.gtu($Rs32,$Rt32)",
2425tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2426let Inst{7-2} = 0b111000;
2427let Inst{13-13} = 0b0;
2428let Inst{31-21} = 0b11000111110;
2429let CextOpcode = "A4_cmpbgtu";
2430let InputType = "reg";
2431let isCompare = 1;
2432}
2433def A4_cmpbgtui : HInst<
2434(outs PredRegs:$Pd4),
2435(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2436"$Pd4 = cmpb.gtu($Rs32,#$Ii)",
2437tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2438let Inst{4-2} = 0b000;
2439let Inst{13-12} = 0b00;
2440let Inst{31-21} = 0b11011101010;
2441let CextOpcode = "A4_cmpbgtu";
2442let InputType = "imm";
2443let isCompare = 1;
2444let isExtendable = 1;
2445let opExtendable = 2;
2446let isExtentSigned = 0;
2447let opExtentBits = 7;
2448let opExtentAlign = 0;
2449}
2450def A4_cmpheq : HInst<
2451(outs PredRegs:$Pd4),
2452(ins IntRegs:$Rs32, IntRegs:$Rt32),
2453"$Pd4 = cmph.eq($Rs32,$Rt32)",
2454tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2455let Inst{7-2} = 0b011000;
2456let Inst{13-13} = 0b0;
2457let Inst{31-21} = 0b11000111110;
2458let CextOpcode = "A4_cmpheq";
2459let InputType = "reg";
2460let isCommutable = 1;
2461let isCompare = 1;
2462}
2463def A4_cmpheqi : HInst<
2464(outs PredRegs:$Pd4),
2465(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2466"$Pd4 = cmph.eq($Rs32,#$Ii)",
2467tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2468let Inst{4-2} = 0b010;
2469let Inst{13-13} = 0b0;
2470let Inst{31-21} = 0b11011101000;
2471let CextOpcode = "A4_cmpheq";
2472let InputType = "imm";
2473let isCommutable = 1;
2474let isCompare = 1;
2475let isExtendable = 1;
2476let opExtendable = 2;
2477let isExtentSigned = 1;
2478let opExtentBits = 8;
2479let opExtentAlign = 0;
2480}
2481def A4_cmphgt : HInst<
2482(outs PredRegs:$Pd4),
2483(ins IntRegs:$Rs32, IntRegs:$Rt32),
2484"$Pd4 = cmph.gt($Rs32,$Rt32)",
2485tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2486let Inst{7-2} = 0b100000;
2487let Inst{13-13} = 0b0;
2488let Inst{31-21} = 0b11000111110;
2489let CextOpcode = "A4_cmphgt";
2490let InputType = "reg";
2491let isCompare = 1;
2492}
2493def A4_cmphgti : HInst<
2494(outs PredRegs:$Pd4),
2495(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2496"$Pd4 = cmph.gt($Rs32,#$Ii)",
2497tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2498let Inst{4-2} = 0b010;
2499let Inst{13-13} = 0b0;
2500let Inst{31-21} = 0b11011101001;
2501let CextOpcode = "A4_cmphgt";
2502let InputType = "imm";
2503let isCompare = 1;
2504let isExtendable = 1;
2505let opExtendable = 2;
2506let isExtentSigned = 1;
2507let opExtentBits = 8;
2508let opExtentAlign = 0;
2509}
2510def A4_cmphgtu : HInst<
2511(outs PredRegs:$Pd4),
2512(ins IntRegs:$Rs32, IntRegs:$Rt32),
2513"$Pd4 = cmph.gtu($Rs32,$Rt32)",
2514tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2515let Inst{7-2} = 0b101000;
2516let Inst{13-13} = 0b0;
2517let Inst{31-21} = 0b11000111110;
2518let CextOpcode = "A4_cmphgtu";
2519let InputType = "reg";
2520let isCompare = 1;
2521}
2522def A4_cmphgtui : HInst<
2523(outs PredRegs:$Pd4),
2524(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2525"$Pd4 = cmph.gtu($Rs32,#$Ii)",
2526tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2527let Inst{4-2} = 0b010;
2528let Inst{13-12} = 0b00;
2529let Inst{31-21} = 0b11011101010;
2530let CextOpcode = "A4_cmphgtu";
2531let InputType = "imm";
2532let isCompare = 1;
2533let isExtendable = 1;
2534let opExtendable = 2;
2535let isExtentSigned = 0;
2536let opExtentBits = 7;
2537let opExtentAlign = 0;
2538}
2539def A4_combineii : HInst<
2540(outs DoubleRegs:$Rdd32),
2541(ins s8_0Imm:$Ii, u32_0Imm:$II),
2542"$Rdd32 = combine(#$Ii,#$II)",
2543tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 {
2544let Inst{31-21} = 0b01111100100;
2545let isExtendable = 1;
2546let opExtendable = 2;
2547let isExtentSigned = 0;
2548let opExtentBits = 6;
2549let opExtentAlign = 0;
2550}
2551def A4_combineir : HInst<
2552(outs DoubleRegs:$Rdd32),
2553(ins s32_0Imm:$Ii, IntRegs:$Rs32),
2554"$Rdd32 = combine(#$Ii,$Rs32)",
2555tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2556let Inst{13-13} = 0b1;
2557let Inst{31-21} = 0b01110011001;
2558let isExtendable = 1;
2559let opExtendable = 1;
2560let isExtentSigned = 1;
2561let opExtentBits = 8;
2562let opExtentAlign = 0;
2563}
2564def A4_combineri : HInst<
2565(outs DoubleRegs:$Rdd32),
2566(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2567"$Rdd32 = combine($Rs32,#$Ii)",
2568tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2569let Inst{13-13} = 0b1;
2570let Inst{31-21} = 0b01110011000;
2571let isExtendable = 1;
2572let opExtendable = 2;
2573let isExtentSigned = 1;
2574let opExtentBits = 8;
2575let opExtentAlign = 0;
2576}
2577def A4_cround_ri : HInst<
2578(outs IntRegs:$Rd32),
2579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2580"$Rd32 = cround($Rs32,#$Ii)",
2581tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
2582let Inst{7-5} = 0b000;
2583let Inst{13-13} = 0b0;
2584let Inst{31-21} = 0b10001100111;
2585let hasNewValue = 1;
2586let opNewValue = 0;
2587let prefersSlot3 = 1;
2588}
2589def A4_cround_rr : HInst<
2590(outs IntRegs:$Rd32),
2591(ins IntRegs:$Rs32, IntRegs:$Rt32),
2592"$Rd32 = cround($Rs32,$Rt32)",
2593tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
2594let Inst{7-5} = 0b000;
2595let Inst{13-13} = 0b0;
2596let Inst{31-21} = 0b11000110110;
2597let hasNewValue = 1;
2598let opNewValue = 0;
2599let prefersSlot3 = 1;
2600}
2601def A4_ext : HInst<
2602(outs),
2603(ins u26_6Imm:$Ii),
2604"immext(#$Ii)",
2605tc_112d30d6, TypeEXTENDER>, Enc_2b518f {
2606let Inst{31-28} = 0b0000;
2607}
2608def A4_modwrapu : HInst<
2609(outs IntRegs:$Rd32),
2610(ins IntRegs:$Rs32, IntRegs:$Rt32),
2611"$Rd32 = modwrap($Rs32,$Rt32)",
2612tc_8a825db2, TypeALU64>, Enc_5ab2be {
2613let Inst{7-5} = 0b111;
2614let Inst{13-13} = 0b0;
2615let Inst{31-21} = 0b11010011111;
2616let hasNewValue = 1;
2617let opNewValue = 0;
2618let prefersSlot3 = 1;
2619}
2620def A4_orn : HInst<
2621(outs IntRegs:$Rd32),
2622(ins IntRegs:$Rt32, IntRegs:$Rs32),
2623"$Rd32 = or($Rt32,~$Rs32)",
2624tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2625let Inst{7-5} = 0b000;
2626let Inst{13-13} = 0b0;
2627let Inst{31-21} = 0b11110001101;
2628let hasNewValue = 1;
2629let opNewValue = 0;
2630let InputType = "reg";
2631}
2632def A4_ornp : HInst<
2633(outs DoubleRegs:$Rdd32),
2634(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2635"$Rdd32 = or($Rtt32,~$Rss32)",
2636tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2637let Inst{7-5} = 0b011;
2638let Inst{13-13} = 0b0;
2639let Inst{31-21} = 0b11010011111;
2640}
2641def A4_paslhf : HInst<
2642(outs IntRegs:$Rd32),
2643(ins PredRegs:$Pu4, IntRegs:$Rs32),
2644"if (!$Pu4) $Rd32 = aslh($Rs32)",
2645tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2646let Inst{7-5} = 0b000;
2647let Inst{13-10} = 0b1010;
2648let Inst{31-21} = 0b01110000000;
2649let isPredicated = 1;
2650let isPredicatedFalse = 1;
2651let hasNewValue = 1;
2652let opNewValue = 0;
2653let BaseOpcode = "A2_aslh";
2654}
2655def A4_paslhfnew : HInst<
2656(outs IntRegs:$Rd32),
2657(ins PredRegs:$Pu4, IntRegs:$Rs32),
2658"if (!$Pu4.new) $Rd32 = aslh($Rs32)",
2659tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2660let Inst{7-5} = 0b000;
2661let Inst{13-10} = 0b1011;
2662let Inst{31-21} = 0b01110000000;
2663let isPredicated = 1;
2664let isPredicatedFalse = 1;
2665let hasNewValue = 1;
2666let opNewValue = 0;
2667let isPredicatedNew = 1;
2668let BaseOpcode = "A2_aslh";
2669}
2670def A4_paslht : HInst<
2671(outs IntRegs:$Rd32),
2672(ins PredRegs:$Pu4, IntRegs:$Rs32),
2673"if ($Pu4) $Rd32 = aslh($Rs32)",
2674tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2675let Inst{7-5} = 0b000;
2676let Inst{13-10} = 0b1000;
2677let Inst{31-21} = 0b01110000000;
2678let isPredicated = 1;
2679let hasNewValue = 1;
2680let opNewValue = 0;
2681let BaseOpcode = "A2_aslh";
2682}
2683def A4_paslhtnew : HInst<
2684(outs IntRegs:$Rd32),
2685(ins PredRegs:$Pu4, IntRegs:$Rs32),
2686"if ($Pu4.new) $Rd32 = aslh($Rs32)",
2687tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2688let Inst{7-5} = 0b000;
2689let Inst{13-10} = 0b1001;
2690let Inst{31-21} = 0b01110000000;
2691let isPredicated = 1;
2692let hasNewValue = 1;
2693let opNewValue = 0;
2694let isPredicatedNew = 1;
2695let BaseOpcode = "A2_aslh";
2696}
2697def A4_pasrhf : HInst<
2698(outs IntRegs:$Rd32),
2699(ins PredRegs:$Pu4, IntRegs:$Rs32),
2700"if (!$Pu4) $Rd32 = asrh($Rs32)",
2701tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2702let Inst{7-5} = 0b000;
2703let Inst{13-10} = 0b1010;
2704let Inst{31-21} = 0b01110000001;
2705let isPredicated = 1;
2706let isPredicatedFalse = 1;
2707let hasNewValue = 1;
2708let opNewValue = 0;
2709let BaseOpcode = "A2_asrh";
2710}
2711def A4_pasrhfnew : HInst<
2712(outs IntRegs:$Rd32),
2713(ins PredRegs:$Pu4, IntRegs:$Rs32),
2714"if (!$Pu4.new) $Rd32 = asrh($Rs32)",
2715tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2716let Inst{7-5} = 0b000;
2717let Inst{13-10} = 0b1011;
2718let Inst{31-21} = 0b01110000001;
2719let isPredicated = 1;
2720let isPredicatedFalse = 1;
2721let hasNewValue = 1;
2722let opNewValue = 0;
2723let isPredicatedNew = 1;
2724let BaseOpcode = "A2_asrh";
2725}
2726def A4_pasrht : HInst<
2727(outs IntRegs:$Rd32),
2728(ins PredRegs:$Pu4, IntRegs:$Rs32),
2729"if ($Pu4) $Rd32 = asrh($Rs32)",
2730tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2731let Inst{7-5} = 0b000;
2732let Inst{13-10} = 0b1000;
2733let Inst{31-21} = 0b01110000001;
2734let isPredicated = 1;
2735let hasNewValue = 1;
2736let opNewValue = 0;
2737let BaseOpcode = "A2_asrh";
2738}
2739def A4_pasrhtnew : HInst<
2740(outs IntRegs:$Rd32),
2741(ins PredRegs:$Pu4, IntRegs:$Rs32),
2742"if ($Pu4.new) $Rd32 = asrh($Rs32)",
2743tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2744let Inst{7-5} = 0b000;
2745let Inst{13-10} = 0b1001;
2746let Inst{31-21} = 0b01110000001;
2747let isPredicated = 1;
2748let hasNewValue = 1;
2749let opNewValue = 0;
2750let isPredicatedNew = 1;
2751let BaseOpcode = "A2_asrh";
2752}
2753def A4_psxtbf : HInst<
2754(outs IntRegs:$Rd32),
2755(ins PredRegs:$Pu4, IntRegs:$Rs32),
2756"if (!$Pu4) $Rd32 = sxtb($Rs32)",
2757tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2758let Inst{7-5} = 0b000;
2759let Inst{13-10} = 0b1010;
2760let Inst{31-21} = 0b01110000101;
2761let isPredicated = 1;
2762let isPredicatedFalse = 1;
2763let hasNewValue = 1;
2764let opNewValue = 0;
2765let BaseOpcode = "A2_sxtb";
2766}
2767def A4_psxtbfnew : HInst<
2768(outs IntRegs:$Rd32),
2769(ins PredRegs:$Pu4, IntRegs:$Rs32),
2770"if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
2771tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2772let Inst{7-5} = 0b000;
2773let Inst{13-10} = 0b1011;
2774let Inst{31-21} = 0b01110000101;
2775let isPredicated = 1;
2776let isPredicatedFalse = 1;
2777let hasNewValue = 1;
2778let opNewValue = 0;
2779let isPredicatedNew = 1;
2780let BaseOpcode = "A2_sxtb";
2781}
2782def A4_psxtbt : HInst<
2783(outs IntRegs:$Rd32),
2784(ins PredRegs:$Pu4, IntRegs:$Rs32),
2785"if ($Pu4) $Rd32 = sxtb($Rs32)",
2786tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2787let Inst{7-5} = 0b000;
2788let Inst{13-10} = 0b1000;
2789let Inst{31-21} = 0b01110000101;
2790let isPredicated = 1;
2791let hasNewValue = 1;
2792let opNewValue = 0;
2793let BaseOpcode = "A2_sxtb";
2794}
2795def A4_psxtbtnew : HInst<
2796(outs IntRegs:$Rd32),
2797(ins PredRegs:$Pu4, IntRegs:$Rs32),
2798"if ($Pu4.new) $Rd32 = sxtb($Rs32)",
2799tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2800let Inst{7-5} = 0b000;
2801let Inst{13-10} = 0b1001;
2802let Inst{31-21} = 0b01110000101;
2803let isPredicated = 1;
2804let hasNewValue = 1;
2805let opNewValue = 0;
2806let isPredicatedNew = 1;
2807let BaseOpcode = "A2_sxtb";
2808}
2809def A4_psxthf : HInst<
2810(outs IntRegs:$Rd32),
2811(ins PredRegs:$Pu4, IntRegs:$Rs32),
2812"if (!$Pu4) $Rd32 = sxth($Rs32)",
2813tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2814let Inst{7-5} = 0b000;
2815let Inst{13-10} = 0b1010;
2816let Inst{31-21} = 0b01110000111;
2817let isPredicated = 1;
2818let isPredicatedFalse = 1;
2819let hasNewValue = 1;
2820let opNewValue = 0;
2821let BaseOpcode = "A2_sxth";
2822}
2823def A4_psxthfnew : HInst<
2824(outs IntRegs:$Rd32),
2825(ins PredRegs:$Pu4, IntRegs:$Rs32),
2826"if (!$Pu4.new) $Rd32 = sxth($Rs32)",
2827tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2828let Inst{7-5} = 0b000;
2829let Inst{13-10} = 0b1011;
2830let Inst{31-21} = 0b01110000111;
2831let isPredicated = 1;
2832let isPredicatedFalse = 1;
2833let hasNewValue = 1;
2834let opNewValue = 0;
2835let isPredicatedNew = 1;
2836let BaseOpcode = "A2_sxth";
2837}
2838def A4_psxtht : HInst<
2839(outs IntRegs:$Rd32),
2840(ins PredRegs:$Pu4, IntRegs:$Rs32),
2841"if ($Pu4) $Rd32 = sxth($Rs32)",
2842tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2843let Inst{7-5} = 0b000;
2844let Inst{13-10} = 0b1000;
2845let Inst{31-21} = 0b01110000111;
2846let isPredicated = 1;
2847let hasNewValue = 1;
2848let opNewValue = 0;
2849let BaseOpcode = "A2_sxth";
2850}
2851def A4_psxthtnew : HInst<
2852(outs IntRegs:$Rd32),
2853(ins PredRegs:$Pu4, IntRegs:$Rs32),
2854"if ($Pu4.new) $Rd32 = sxth($Rs32)",
2855tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2856let Inst{7-5} = 0b000;
2857let Inst{13-10} = 0b1001;
2858let Inst{31-21} = 0b01110000111;
2859let isPredicated = 1;
2860let hasNewValue = 1;
2861let opNewValue = 0;
2862let isPredicatedNew = 1;
2863let BaseOpcode = "A2_sxth";
2864}
2865def A4_pzxtbf : HInst<
2866(outs IntRegs:$Rd32),
2867(ins PredRegs:$Pu4, IntRegs:$Rs32),
2868"if (!$Pu4) $Rd32 = zxtb($Rs32)",
2869tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2870let Inst{7-5} = 0b000;
2871let Inst{13-10} = 0b1010;
2872let Inst{31-21} = 0b01110000100;
2873let isPredicated = 1;
2874let isPredicatedFalse = 1;
2875let hasNewValue = 1;
2876let opNewValue = 0;
2877let BaseOpcode = "A2_zxtb";
2878}
2879def A4_pzxtbfnew : HInst<
2880(outs IntRegs:$Rd32),
2881(ins PredRegs:$Pu4, IntRegs:$Rs32),
2882"if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
2883tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2884let Inst{7-5} = 0b000;
2885let Inst{13-10} = 0b1011;
2886let Inst{31-21} = 0b01110000100;
2887let isPredicated = 1;
2888let isPredicatedFalse = 1;
2889let hasNewValue = 1;
2890let opNewValue = 0;
2891let isPredicatedNew = 1;
2892let BaseOpcode = "A2_zxtb";
2893}
2894def A4_pzxtbt : HInst<
2895(outs IntRegs:$Rd32),
2896(ins PredRegs:$Pu4, IntRegs:$Rs32),
2897"if ($Pu4) $Rd32 = zxtb($Rs32)",
2898tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2899let Inst{7-5} = 0b000;
2900let Inst{13-10} = 0b1000;
2901let Inst{31-21} = 0b01110000100;
2902let isPredicated = 1;
2903let hasNewValue = 1;
2904let opNewValue = 0;
2905let BaseOpcode = "A2_zxtb";
2906}
2907def A4_pzxtbtnew : HInst<
2908(outs IntRegs:$Rd32),
2909(ins PredRegs:$Pu4, IntRegs:$Rs32),
2910"if ($Pu4.new) $Rd32 = zxtb($Rs32)",
2911tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2912let Inst{7-5} = 0b000;
2913let Inst{13-10} = 0b1001;
2914let Inst{31-21} = 0b01110000100;
2915let isPredicated = 1;
2916let hasNewValue = 1;
2917let opNewValue = 0;
2918let isPredicatedNew = 1;
2919let BaseOpcode = "A2_zxtb";
2920}
2921def A4_pzxthf : HInst<
2922(outs IntRegs:$Rd32),
2923(ins PredRegs:$Pu4, IntRegs:$Rs32),
2924"if (!$Pu4) $Rd32 = zxth($Rs32)",
2925tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2926let Inst{7-5} = 0b000;
2927let Inst{13-10} = 0b1010;
2928let Inst{31-21} = 0b01110000110;
2929let isPredicated = 1;
2930let isPredicatedFalse = 1;
2931let hasNewValue = 1;
2932let opNewValue = 0;
2933let BaseOpcode = "A2_zxth";
2934}
2935def A4_pzxthfnew : HInst<
2936(outs IntRegs:$Rd32),
2937(ins PredRegs:$Pu4, IntRegs:$Rs32),
2938"if (!$Pu4.new) $Rd32 = zxth($Rs32)",
2939tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2940let Inst{7-5} = 0b000;
2941let Inst{13-10} = 0b1011;
2942let Inst{31-21} = 0b01110000110;
2943let isPredicated = 1;
2944let isPredicatedFalse = 1;
2945let hasNewValue = 1;
2946let opNewValue = 0;
2947let isPredicatedNew = 1;
2948let BaseOpcode = "A2_zxth";
2949}
2950def A4_pzxtht : HInst<
2951(outs IntRegs:$Rd32),
2952(ins PredRegs:$Pu4, IntRegs:$Rs32),
2953"if ($Pu4) $Rd32 = zxth($Rs32)",
2954tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2955let Inst{7-5} = 0b000;
2956let Inst{13-10} = 0b1000;
2957let Inst{31-21} = 0b01110000110;
2958let isPredicated = 1;
2959let hasNewValue = 1;
2960let opNewValue = 0;
2961let BaseOpcode = "A2_zxth";
2962}
2963def A4_pzxthtnew : HInst<
2964(outs IntRegs:$Rd32),
2965(ins PredRegs:$Pu4, IntRegs:$Rs32),
2966"if ($Pu4.new) $Rd32 = zxth($Rs32)",
2967tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2968let Inst{7-5} = 0b000;
2969let Inst{13-10} = 0b1001;
2970let Inst{31-21} = 0b01110000110;
2971let isPredicated = 1;
2972let hasNewValue = 1;
2973let opNewValue = 0;
2974let isPredicatedNew = 1;
2975let BaseOpcode = "A2_zxth";
2976}
2977def A4_rcmpeq : HInst<
2978(outs IntRegs:$Rd32),
2979(ins IntRegs:$Rs32, IntRegs:$Rt32),
2980"$Rd32 = cmp.eq($Rs32,$Rt32)",
2981tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
2982let Inst{7-5} = 0b000;
2983let Inst{13-13} = 0b0;
2984let Inst{31-21} = 0b11110011010;
2985let hasNewValue = 1;
2986let opNewValue = 0;
2987let CextOpcode = "A4_rcmpeq";
2988let InputType = "reg";
2989let isCommutable = 1;
2990}
2991def A4_rcmpeqi : HInst<
2992(outs IntRegs:$Rd32),
2993(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2994"$Rd32 = cmp.eq($Rs32,#$Ii)",
2995tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
2996let Inst{13-13} = 0b1;
2997let Inst{31-21} = 0b01110011010;
2998let hasNewValue = 1;
2999let opNewValue = 0;
3000let CextOpcode = "A4_rcmpeqi";
3001let InputType = "imm";
3002let isExtendable = 1;
3003let opExtendable = 2;
3004let isExtentSigned = 1;
3005let opExtentBits = 8;
3006let opExtentAlign = 0;
3007}
3008def A4_rcmpneq : HInst<
3009(outs IntRegs:$Rd32),
3010(ins IntRegs:$Rs32, IntRegs:$Rt32),
3011"$Rd32 = !cmp.eq($Rs32,$Rt32)",
3012tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
3013let Inst{7-5} = 0b000;
3014let Inst{13-13} = 0b0;
3015let Inst{31-21} = 0b11110011011;
3016let hasNewValue = 1;
3017let opNewValue = 0;
3018let CextOpcode = "A4_rcmpneq";
3019let InputType = "reg";
3020let isCommutable = 1;
3021}
3022def A4_rcmpneqi : HInst<
3023(outs IntRegs:$Rd32),
3024(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3025"$Rd32 = !cmp.eq($Rs32,#$Ii)",
3026tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
3027let Inst{13-13} = 0b1;
3028let Inst{31-21} = 0b01110011011;
3029let hasNewValue = 1;
3030let opNewValue = 0;
3031let CextOpcode = "A4_rcmpeqi";
3032let InputType = "imm";
3033let isExtendable = 1;
3034let opExtendable = 2;
3035let isExtentSigned = 1;
3036let opExtentBits = 8;
3037let opExtentAlign = 0;
3038}
3039def A4_round_ri : HInst<
3040(outs IntRegs:$Rd32),
3041(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3042"$Rd32 = round($Rs32,#$Ii)",
3043tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3044let Inst{7-5} = 0b100;
3045let Inst{13-13} = 0b0;
3046let Inst{31-21} = 0b10001100111;
3047let hasNewValue = 1;
3048let opNewValue = 0;
3049let prefersSlot3 = 1;
3050}
3051def A4_round_ri_sat : HInst<
3052(outs IntRegs:$Rd32),
3053(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3054"$Rd32 = round($Rs32,#$Ii):sat",
3055tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3056let Inst{7-5} = 0b110;
3057let Inst{13-13} = 0b0;
3058let Inst{31-21} = 0b10001100111;
3059let hasNewValue = 1;
3060let opNewValue = 0;
3061let prefersSlot3 = 1;
3062let Defs = [USR_OVF];
3063}
3064def A4_round_rr : HInst<
3065(outs IntRegs:$Rd32),
3066(ins IntRegs:$Rs32, IntRegs:$Rt32),
3067"$Rd32 = round($Rs32,$Rt32)",
3068tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3069let Inst{7-5} = 0b100;
3070let Inst{13-13} = 0b0;
3071let Inst{31-21} = 0b11000110110;
3072let hasNewValue = 1;
3073let opNewValue = 0;
3074let prefersSlot3 = 1;
3075}
3076def A4_round_rr_sat : HInst<
3077(outs IntRegs:$Rd32),
3078(ins IntRegs:$Rs32, IntRegs:$Rt32),
3079"$Rd32 = round($Rs32,$Rt32):sat",
3080tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3081let Inst{7-5} = 0b110;
3082let Inst{13-13} = 0b0;
3083let Inst{31-21} = 0b11000110110;
3084let hasNewValue = 1;
3085let opNewValue = 0;
3086let prefersSlot3 = 1;
3087let Defs = [USR_OVF];
3088}
3089def A4_subp_c : HInst<
3090(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
3091(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
3092"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
3093tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
3094let Inst{7-7} = 0b0;
3095let Inst{13-13} = 0b0;
3096let Inst{31-21} = 0b11000010111;
3097let isPredicateLate = 1;
3098let Constraints = "$Px4 = $Px4in";
3099}
3100def A4_tfrcpp : HInst<
3101(outs DoubleRegs:$Rdd32),
3102(ins CtrRegs64:$Css32),
3103"$Rdd32 = $Css32",
3104tc_7476d766, TypeCR>, Enc_667b39 {
3105let Inst{13-5} = 0b000000000;
3106let Inst{31-21} = 0b01101000000;
3107}
3108def A4_tfrpcp : HInst<
3109(outs CtrRegs64:$Cdd32),
3110(ins DoubleRegs:$Rss32),
3111"$Cdd32 = $Rss32",
3112tc_49fdfd4b, TypeCR>, Enc_0ed752 {
3113let Inst{13-5} = 0b000000000;
3114let Inst{31-21} = 0b01100011001;
3115}
3116def A4_tlbmatch : HInst<
3117(outs PredRegs:$Pd4),
3118(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3119"$Pd4 = tlbmatch($Rss32,$Rt32)",
3120tc_d68dca5c, TypeALU64>, Enc_03833b {
3121let Inst{7-2} = 0b011000;
3122let Inst{13-13} = 0b1;
3123let Inst{31-21} = 0b11010010000;
3124let isPredicateLate = 1;
3125}
3126def A4_vcmpbeq_any : HInst<
3127(outs PredRegs:$Pd4),
3128(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3129"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
3130tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3131let Inst{7-2} = 0b000000;
3132let Inst{13-13} = 0b1;
3133let Inst{31-21} = 0b11010010000;
3134}
3135def A4_vcmpbeqi : HInst<
3136(outs PredRegs:$Pd4),
3137(ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
3138"$Pd4 = vcmpb.eq($Rss32,#$Ii)",
3139tc_a1297125, TypeALU64>, Enc_0d8adb {
3140let Inst{4-2} = 0b000;
3141let Inst{13-13} = 0b0;
3142let Inst{31-21} = 0b11011100000;
3143}
3144def A4_vcmpbgt : HInst<
3145(outs PredRegs:$Pd4),
3146(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3147"$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
3148tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3149let Inst{7-2} = 0b010000;
3150let Inst{13-13} = 0b1;
3151let Inst{31-21} = 0b11010010000;
3152}
3153def A4_vcmpbgti : HInst<
3154(outs PredRegs:$Pd4),
3155(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3156"$Pd4 = vcmpb.gt($Rss32,#$Ii)",
3157tc_a1297125, TypeALU64>, Enc_0d8adb {
3158let Inst{4-2} = 0b000;
3159let Inst{13-13} = 0b0;
3160let Inst{31-21} = 0b11011100001;
3161}
3162def A4_vcmpbgtui : HInst<
3163(outs PredRegs:$Pd4),
3164(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3165"$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
3166tc_a1297125, TypeALU64>, Enc_3680c2 {
3167let Inst{4-2} = 0b000;
3168let Inst{13-12} = 0b00;
3169let Inst{31-21} = 0b11011100010;
3170}
3171def A4_vcmpheqi : HInst<
3172(outs PredRegs:$Pd4),
3173(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3174"$Pd4 = vcmph.eq($Rss32,#$Ii)",
3175tc_a1297125, TypeALU64>, Enc_0d8adb {
3176let Inst{4-2} = 0b010;
3177let Inst{13-13} = 0b0;
3178let Inst{31-21} = 0b11011100000;
3179}
3180def A4_vcmphgti : HInst<
3181(outs PredRegs:$Pd4),
3182(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3183"$Pd4 = vcmph.gt($Rss32,#$Ii)",
3184tc_a1297125, TypeALU64>, Enc_0d8adb {
3185let Inst{4-2} = 0b010;
3186let Inst{13-13} = 0b0;
3187let Inst{31-21} = 0b11011100001;
3188}
3189def A4_vcmphgtui : HInst<
3190(outs PredRegs:$Pd4),
3191(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3192"$Pd4 = vcmph.gtu($Rss32,#$Ii)",
3193tc_a1297125, TypeALU64>, Enc_3680c2 {
3194let Inst{4-2} = 0b010;
3195let Inst{13-12} = 0b00;
3196let Inst{31-21} = 0b11011100010;
3197}
3198def A4_vcmpweqi : HInst<
3199(outs PredRegs:$Pd4),
3200(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3201"$Pd4 = vcmpw.eq($Rss32,#$Ii)",
3202tc_a1297125, TypeALU64>, Enc_0d8adb {
3203let Inst{4-2} = 0b100;
3204let Inst{13-13} = 0b0;
3205let Inst{31-21} = 0b11011100000;
3206}
3207def A4_vcmpwgti : HInst<
3208(outs PredRegs:$Pd4),
3209(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3210"$Pd4 = vcmpw.gt($Rss32,#$Ii)",
3211tc_a1297125, TypeALU64>, Enc_0d8adb {
3212let Inst{4-2} = 0b100;
3213let Inst{13-13} = 0b0;
3214let Inst{31-21} = 0b11011100001;
3215}
3216def A4_vcmpwgtui : HInst<
3217(outs PredRegs:$Pd4),
3218(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3219"$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
3220tc_a1297125, TypeALU64>, Enc_3680c2 {
3221let Inst{4-2} = 0b100;
3222let Inst{13-12} = 0b00;
3223let Inst{31-21} = 0b11011100010;
3224}
3225def A4_vrmaxh : HInst<
3226(outs DoubleRegs:$Rxx32),
3227(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3228"$Rxx32 = vrmaxh($Rss32,$Ru32)",
3229tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3230let Inst{7-5} = 0b001;
3231let Inst{13-13} = 0b0;
3232let Inst{31-21} = 0b11001011001;
3233let prefersSlot3 = 1;
3234let Constraints = "$Rxx32 = $Rxx32in";
3235}
3236def A4_vrmaxuh : HInst<
3237(outs DoubleRegs:$Rxx32),
3238(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3239"$Rxx32 = vrmaxuh($Rss32,$Ru32)",
3240tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3241let Inst{7-5} = 0b001;
3242let Inst{13-13} = 0b1;
3243let Inst{31-21} = 0b11001011001;
3244let prefersSlot3 = 1;
3245let Constraints = "$Rxx32 = $Rxx32in";
3246}
3247def A4_vrmaxuw : HInst<
3248(outs DoubleRegs:$Rxx32),
3249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3250"$Rxx32 = vrmaxuw($Rss32,$Ru32)",
3251tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3252let Inst{7-5} = 0b010;
3253let Inst{13-13} = 0b1;
3254let Inst{31-21} = 0b11001011001;
3255let prefersSlot3 = 1;
3256let Constraints = "$Rxx32 = $Rxx32in";
3257}
3258def A4_vrmaxw : HInst<
3259(outs DoubleRegs:$Rxx32),
3260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3261"$Rxx32 = vrmaxw($Rss32,$Ru32)",
3262tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3263let Inst{7-5} = 0b010;
3264let Inst{13-13} = 0b0;
3265let Inst{31-21} = 0b11001011001;
3266let prefersSlot3 = 1;
3267let Constraints = "$Rxx32 = $Rxx32in";
3268}
3269def A4_vrminh : HInst<
3270(outs DoubleRegs:$Rxx32),
3271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3272"$Rxx32 = vrminh($Rss32,$Ru32)",
3273tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3274let Inst{7-5} = 0b101;
3275let Inst{13-13} = 0b0;
3276let Inst{31-21} = 0b11001011001;
3277let prefersSlot3 = 1;
3278let Constraints = "$Rxx32 = $Rxx32in";
3279}
3280def A4_vrminuh : HInst<
3281(outs DoubleRegs:$Rxx32),
3282(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3283"$Rxx32 = vrminuh($Rss32,$Ru32)",
3284tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3285let Inst{7-5} = 0b101;
3286let Inst{13-13} = 0b1;
3287let Inst{31-21} = 0b11001011001;
3288let prefersSlot3 = 1;
3289let Constraints = "$Rxx32 = $Rxx32in";
3290}
3291def A4_vrminuw : HInst<
3292(outs DoubleRegs:$Rxx32),
3293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3294"$Rxx32 = vrminuw($Rss32,$Ru32)",
3295tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3296let Inst{7-5} = 0b110;
3297let Inst{13-13} = 0b1;
3298let Inst{31-21} = 0b11001011001;
3299let prefersSlot3 = 1;
3300let Constraints = "$Rxx32 = $Rxx32in";
3301}
3302def A4_vrminw : HInst<
3303(outs DoubleRegs:$Rxx32),
3304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3305"$Rxx32 = vrminw($Rss32,$Ru32)",
3306tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3307let Inst{7-5} = 0b110;
3308let Inst{13-13} = 0b0;
3309let Inst{31-21} = 0b11001011001;
3310let prefersSlot3 = 1;
3311let Constraints = "$Rxx32 = $Rxx32in";
3312}
3313def A5_ACS : HInst<
3314(outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
3315(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3316"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
3317tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> {
3318let Inst{7-7} = 0b0;
3319let Inst{13-13} = 0b0;
3320let Inst{31-21} = 0b11101010101;
3321let isPredicateLate = 1;
3322let prefersSlot3 = 1;
3323let Defs = [USR_OVF];
3324let Constraints = "$Rxx32 = $Rxx32in";
3325}
3326def A5_vaddhubs : HInst<
3327(outs IntRegs:$Rd32),
3328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3329"$Rd32 = vaddhub($Rss32,$Rtt32):sat",
3330tc_0dfac0a7, TypeS_3op>, Enc_d2216a {
3331let Inst{7-5} = 0b001;
3332let Inst{13-13} = 0b0;
3333let Inst{31-21} = 0b11000001010;
3334let hasNewValue = 1;
3335let opNewValue = 0;
3336let prefersSlot3 = 1;
3337let Defs = [USR_OVF];
3338}
3339def A6_vcmpbeq_notany : HInst<
3340(outs PredRegs:$Pd4),
3341(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3342"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
3343tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> {
3344let Inst{7-2} = 0b001000;
3345let Inst{13-13} = 0b1;
3346let Inst{31-21} = 0b11010010000;
3347}
3348def A6_vminub_RdP : HInst<
3349(outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
3350(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
3351"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
3352tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> {
3353let Inst{7-7} = 0b0;
3354let Inst{13-13} = 0b0;
3355let Inst{31-21} = 0b11101010111;
3356let isPredicateLate = 1;
3357let prefersSlot3 = 1;
3358}
3359def A7_clip : HInst<
3360(outs IntRegs:$Rd32),
3361(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3362"$Rd32 = clip($Rs32,#$Ii)",
3363tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> {
3364let Inst{7-5} = 0b101;
3365let Inst{13-13} = 0b0;
3366let Inst{31-21} = 0b10001000110;
3367let hasNewValue = 1;
3368let opNewValue = 0;
3369}
3370def A7_croundd_ri : HInst<
3371(outs DoubleRegs:$Rdd32),
3372(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
3373"$Rdd32 = cround($Rss32,#$Ii)",
3374tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> {
3375let Inst{7-5} = 0b010;
3376let Inst{31-21} = 0b10001100111;
3377let prefersSlot3 = 1;
3378}
3379def A7_croundd_rr : HInst<
3380(outs DoubleRegs:$Rdd32),
3381(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3382"$Rdd32 = cround($Rss32,$Rt32)",
3383tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> {
3384let Inst{7-5} = 0b010;
3385let Inst{13-13} = 0b0;
3386let Inst{31-21} = 0b11000110110;
3387let prefersSlot3 = 1;
3388}
3389def A7_vclip : HInst<
3390(outs DoubleRegs:$Rdd32),
3391(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
3392"$Rdd32 = vclip($Rss32,#$Ii)",
3393tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> {
3394let Inst{7-5} = 0b110;
3395let Inst{13-13} = 0b0;
3396let Inst{31-21} = 0b10001000110;
3397}
3398def C2_all8 : HInst<
3399(outs PredRegs:$Pd4),
3400(ins PredRegs:$Ps4),
3401"$Pd4 = all8($Ps4)",
3402tc_151bf368, TypeCR>, Enc_65d691 {
3403let Inst{13-2} = 0b000000000000;
3404let Inst{31-18} = 0b01101011101000;
3405}
3406def C2_and : HInst<
3407(outs PredRegs:$Pd4),
3408(ins PredRegs:$Pt4, PredRegs:$Ps4),
3409"$Pd4 = and($Pt4,$Ps4)",
3410tc_651cbe02, TypeCR>, Enc_454a26 {
3411let Inst{7-2} = 0b000000;
3412let Inst{13-10} = 0b0000;
3413let Inst{31-18} = 0b01101011000000;
3414}
3415def C2_andn : HInst<
3416(outs PredRegs:$Pd4),
3417(ins PredRegs:$Pt4, PredRegs:$Ps4),
3418"$Pd4 = and($Pt4,!$Ps4)",
3419tc_651cbe02, TypeCR>, Enc_454a26 {
3420let Inst{7-2} = 0b000000;
3421let Inst{13-10} = 0b0000;
3422let Inst{31-18} = 0b01101011011000;
3423}
3424def C2_any8 : HInst<
3425(outs PredRegs:$Pd4),
3426(ins PredRegs:$Ps4),
3427"$Pd4 = any8($Ps4)",
3428tc_151bf368, TypeCR>, Enc_65d691 {
3429let Inst{13-2} = 0b000000000000;
3430let Inst{31-18} = 0b01101011100000;
3431}
3432def C2_bitsclr : HInst<
3433(outs PredRegs:$Pd4),
3434(ins IntRegs:$Rs32, IntRegs:$Rt32),
3435"$Pd4 = bitsclr($Rs32,$Rt32)",
3436tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3437let Inst{7-2} = 0b000000;
3438let Inst{13-13} = 0b0;
3439let Inst{31-21} = 0b11000111100;
3440}
3441def C2_bitsclri : HInst<
3442(outs PredRegs:$Pd4),
3443(ins IntRegs:$Rs32, u6_0Imm:$Ii),
3444"$Pd4 = bitsclr($Rs32,#$Ii)",
3445tc_a1297125, TypeS_2op>, Enc_5d6c34 {
3446let Inst{7-2} = 0b000000;
3447let Inst{31-21} = 0b10000101100;
3448}
3449def C2_bitsset : HInst<
3450(outs PredRegs:$Pd4),
3451(ins IntRegs:$Rs32, IntRegs:$Rt32),
3452"$Pd4 = bitsset($Rs32,$Rt32)",
3453tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3454let Inst{7-2} = 0b000000;
3455let Inst{13-13} = 0b0;
3456let Inst{31-21} = 0b11000111010;
3457}
3458def C2_ccombinewf : HInst<
3459(outs DoubleRegs:$Rdd32),
3460(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3461"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3462tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3463let Inst{7-7} = 0b1;
3464let Inst{13-13} = 0b0;
3465let Inst{31-21} = 0b11111101000;
3466let isPredicated = 1;
3467let isPredicatedFalse = 1;
3468let BaseOpcode = "A2_combinew";
3469}
3470def C2_ccombinewnewf : HInst<
3471(outs DoubleRegs:$Rdd32),
3472(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3473"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3474tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3475let Inst{7-7} = 0b1;
3476let Inst{13-13} = 0b1;
3477let Inst{31-21} = 0b11111101000;
3478let isPredicated = 1;
3479let isPredicatedFalse = 1;
3480let isPredicatedNew = 1;
3481let BaseOpcode = "A2_combinew";
3482}
3483def C2_ccombinewnewt : HInst<
3484(outs DoubleRegs:$Rdd32),
3485(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3486"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3487tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3488let Inst{7-7} = 0b0;
3489let Inst{13-13} = 0b1;
3490let Inst{31-21} = 0b11111101000;
3491let isPredicated = 1;
3492let isPredicatedNew = 1;
3493let BaseOpcode = "A2_combinew";
3494}
3495def C2_ccombinewt : HInst<
3496(outs DoubleRegs:$Rdd32),
3497(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3498"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3499tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3500let Inst{7-7} = 0b0;
3501let Inst{13-13} = 0b0;
3502let Inst{31-21} = 0b11111101000;
3503let isPredicated = 1;
3504let BaseOpcode = "A2_combinew";
3505}
3506def C2_cmoveif : HInst<
3507(outs IntRegs:$Rd32),
3508(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3509"if (!$Pu4) $Rd32 = #$Ii",
3510tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3511let Inst{13-13} = 0b0;
3512let Inst{20-20} = 0b0;
3513let Inst{31-23} = 0b011111101;
3514let isPredicated = 1;
3515let isPredicatedFalse = 1;
3516let hasNewValue = 1;
3517let opNewValue = 0;
3518let BaseOpcode = "A2_tfrsi";
3519let CextOpcode = "A2_tfr";
3520let InputType = "imm";
3521let isMoveImm = 1;
3522let isExtendable = 1;
3523let opExtendable = 2;
3524let isExtentSigned = 1;
3525let opExtentBits = 12;
3526let opExtentAlign = 0;
3527}
3528def C2_cmoveit : HInst<
3529(outs IntRegs:$Rd32),
3530(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3531"if ($Pu4) $Rd32 = #$Ii",
3532tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3533let Inst{13-13} = 0b0;
3534let Inst{20-20} = 0b0;
3535let Inst{31-23} = 0b011111100;
3536let isPredicated = 1;
3537let hasNewValue = 1;
3538let opNewValue = 0;
3539let BaseOpcode = "A2_tfrsi";
3540let CextOpcode = "A2_tfr";
3541let InputType = "imm";
3542let isMoveImm = 1;
3543let isExtendable = 1;
3544let opExtendable = 2;
3545let isExtentSigned = 1;
3546let opExtentBits = 12;
3547let opExtentAlign = 0;
3548}
3549def C2_cmovenewif : HInst<
3550(outs IntRegs:$Rd32),
3551(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3552"if (!$Pu4.new) $Rd32 = #$Ii",
3553tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3554let Inst{13-13} = 0b1;
3555let Inst{20-20} = 0b0;
3556let Inst{31-23} = 0b011111101;
3557let isPredicated = 1;
3558let isPredicatedFalse = 1;
3559let hasNewValue = 1;
3560let opNewValue = 0;
3561let isPredicatedNew = 1;
3562let BaseOpcode = "A2_tfrsi";
3563let CextOpcode = "A2_tfr";
3564let InputType = "imm";
3565let isMoveImm = 1;
3566let isExtendable = 1;
3567let opExtendable = 2;
3568let isExtentSigned = 1;
3569let opExtentBits = 12;
3570let opExtentAlign = 0;
3571}
3572def C2_cmovenewit : HInst<
3573(outs IntRegs:$Rd32),
3574(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3575"if ($Pu4.new) $Rd32 = #$Ii",
3576tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3577let Inst{13-13} = 0b1;
3578let Inst{20-20} = 0b0;
3579let Inst{31-23} = 0b011111100;
3580let isPredicated = 1;
3581let hasNewValue = 1;
3582let opNewValue = 0;
3583let isPredicatedNew = 1;
3584let BaseOpcode = "A2_tfrsi";
3585let CextOpcode = "A2_tfr";
3586let InputType = "imm";
3587let isMoveImm = 1;
3588let isExtendable = 1;
3589let opExtendable = 2;
3590let isExtentSigned = 1;
3591let opExtentBits = 12;
3592let opExtentAlign = 0;
3593}
3594def C2_cmpeq : HInst<
3595(outs PredRegs:$Pd4),
3596(ins IntRegs:$Rs32, IntRegs:$Rt32),
3597"$Pd4 = cmp.eq($Rs32,$Rt32)",
3598tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3599let Inst{7-2} = 0b000000;
3600let Inst{13-13} = 0b0;
3601let Inst{31-21} = 0b11110010000;
3602let CextOpcode = "C2_cmpeq";
3603let InputType = "reg";
3604let isCommutable = 1;
3605let isCompare = 1;
3606}
3607def C2_cmpeqi : HInst<
3608(outs PredRegs:$Pd4),
3609(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3610"$Pd4 = cmp.eq($Rs32,#$Ii)",
3611tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3612let Inst{4-2} = 0b000;
3613let Inst{31-22} = 0b0111010100;
3614let CextOpcode = "C2_cmpeq";
3615let InputType = "imm";
3616let isCompare = 1;
3617let isExtendable = 1;
3618let opExtendable = 2;
3619let isExtentSigned = 1;
3620let opExtentBits = 10;
3621let opExtentAlign = 0;
3622}
3623def C2_cmpeqp : HInst<
3624(outs PredRegs:$Pd4),
3625(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3626"$Pd4 = cmp.eq($Rss32,$Rtt32)",
3627tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3628let Inst{7-2} = 0b000000;
3629let Inst{13-13} = 0b0;
3630let Inst{31-21} = 0b11010010100;
3631let isCommutable = 1;
3632let isCompare = 1;
3633}
3634def C2_cmpgei : HInst<
3635(outs PredRegs:$Pd4),
3636(ins IntRegs:$Rs32, s8_0Imm:$Ii),
3637"$Pd4 = cmp.ge($Rs32,#$Ii)",
3638tc_d33e5eee, TypeALU32_2op> {
3639let isCompare = 1;
3640let isPseudo = 1;
3641}
3642def C2_cmpgeui : HInst<
3643(outs PredRegs:$Pd4),
3644(ins IntRegs:$Rs32, u8_0Imm:$Ii),
3645"$Pd4 = cmp.geu($Rs32,#$Ii)",
3646tc_d33e5eee, TypeALU32_2op> {
3647let isCompare = 1;
3648let isPseudo = 1;
3649}
3650def C2_cmpgt : HInst<
3651(outs PredRegs:$Pd4),
3652(ins IntRegs:$Rs32, IntRegs:$Rt32),
3653"$Pd4 = cmp.gt($Rs32,$Rt32)",
3654tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3655let Inst{7-2} = 0b000000;
3656let Inst{13-13} = 0b0;
3657let Inst{31-21} = 0b11110010010;
3658let CextOpcode = "C2_cmpgt";
3659let InputType = "reg";
3660let isCompare = 1;
3661}
3662def C2_cmpgti : HInst<
3663(outs PredRegs:$Pd4),
3664(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3665"$Pd4 = cmp.gt($Rs32,#$Ii)",
3666tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3667let Inst{4-2} = 0b000;
3668let Inst{31-22} = 0b0111010101;
3669let CextOpcode = "C2_cmpgt";
3670let InputType = "imm";
3671let isCompare = 1;
3672let isExtendable = 1;
3673let opExtendable = 2;
3674let isExtentSigned = 1;
3675let opExtentBits = 10;
3676let opExtentAlign = 0;
3677}
3678def C2_cmpgtp : HInst<
3679(outs PredRegs:$Pd4),
3680(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3681"$Pd4 = cmp.gt($Rss32,$Rtt32)",
3682tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3683let Inst{7-2} = 0b010000;
3684let Inst{13-13} = 0b0;
3685let Inst{31-21} = 0b11010010100;
3686let isCompare = 1;
3687}
3688def C2_cmpgtu : HInst<
3689(outs PredRegs:$Pd4),
3690(ins IntRegs:$Rs32, IntRegs:$Rt32),
3691"$Pd4 = cmp.gtu($Rs32,$Rt32)",
3692tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3693let Inst{7-2} = 0b000000;
3694let Inst{13-13} = 0b0;
3695let Inst{31-21} = 0b11110010011;
3696let CextOpcode = "C2_cmpgtu";
3697let InputType = "reg";
3698let isCompare = 1;
3699}
3700def C2_cmpgtui : HInst<
3701(outs PredRegs:$Pd4),
3702(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3703"$Pd4 = cmp.gtu($Rs32,#$Ii)",
3704tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3705let Inst{4-2} = 0b000;
3706let Inst{31-21} = 0b01110101100;
3707let CextOpcode = "C2_cmpgtu";
3708let InputType = "imm";
3709let isCompare = 1;
3710let isExtendable = 1;
3711let opExtendable = 2;
3712let isExtentSigned = 0;
3713let opExtentBits = 9;
3714let opExtentAlign = 0;
3715}
3716def C2_cmpgtup : HInst<
3717(outs PredRegs:$Pd4),
3718(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3719"$Pd4 = cmp.gtu($Rss32,$Rtt32)",
3720tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3721let Inst{7-2} = 0b100000;
3722let Inst{13-13} = 0b0;
3723let Inst{31-21} = 0b11010010100;
3724let isCompare = 1;
3725}
3726def C2_cmplt : HInst<
3727(outs PredRegs:$Pd4),
3728(ins IntRegs:$Rs32, IntRegs:$Rt32),
3729"$Pd4 = cmp.lt($Rs32,$Rt32)",
3730tc_d33e5eee, TypeALU32_3op> {
3731let isCompare = 1;
3732let isPseudo = 1;
3733let isCodeGenOnly = 1;
3734}
3735def C2_cmpltu : HInst<
3736(outs PredRegs:$Pd4),
3737(ins IntRegs:$Rs32, IntRegs:$Rt32),
3738"$Pd4 = cmp.ltu($Rs32,$Rt32)",
3739tc_d33e5eee, TypeALU32_3op> {
3740let isCompare = 1;
3741let isPseudo = 1;
3742let isCodeGenOnly = 1;
3743}
3744def C2_mask : HInst<
3745(outs DoubleRegs:$Rdd32),
3746(ins PredRegs:$Pt4),
3747"$Rdd32 = mask($Pt4)",
3748tc_9f6cd987, TypeS_2op>, Enc_78e566 {
3749let Inst{7-5} = 0b000;
3750let Inst{13-10} = 0b0000;
3751let Inst{31-16} = 0b1000011000000000;
3752}
3753def C2_mux : HInst<
3754(outs IntRegs:$Rd32),
3755(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3756"$Rd32 = mux($Pu4,$Rs32,$Rt32)",
3757tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 {
3758let Inst{7-7} = 0b0;
3759let Inst{13-13} = 0b0;
3760let Inst{31-21} = 0b11110100000;
3761let hasNewValue = 1;
3762let opNewValue = 0;
3763let InputType = "reg";
3764}
3765def C2_muxii : HInst<
3766(outs IntRegs:$Rd32),
3767(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
3768"$Rd32 = mux($Pu4,#$Ii,#$II)",
3769tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d {
3770let Inst{31-25} = 0b0111101;
3771let hasNewValue = 1;
3772let opNewValue = 0;
3773let isExtendable = 1;
3774let opExtendable = 2;
3775let isExtentSigned = 1;
3776let opExtentBits = 8;
3777let opExtentAlign = 0;
3778}
3779def C2_muxir : HInst<
3780(outs IntRegs:$Rd32),
3781(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
3782"$Rd32 = mux($Pu4,$Rs32,#$Ii)",
3783tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3784let Inst{13-13} = 0b0;
3785let Inst{31-23} = 0b011100110;
3786let hasNewValue = 1;
3787let opNewValue = 0;
3788let InputType = "imm";
3789let isExtendable = 1;
3790let opExtendable = 3;
3791let isExtentSigned = 1;
3792let opExtentBits = 8;
3793let opExtentAlign = 0;
3794}
3795def C2_muxri : HInst<
3796(outs IntRegs:$Rd32),
3797(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
3798"$Rd32 = mux($Pu4,#$Ii,$Rs32)",
3799tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3800let Inst{13-13} = 0b0;
3801let Inst{31-23} = 0b011100111;
3802let hasNewValue = 1;
3803let opNewValue = 0;
3804let InputType = "imm";
3805let isExtendable = 1;
3806let opExtendable = 2;
3807let isExtentSigned = 1;
3808let opExtentBits = 8;
3809let opExtentAlign = 0;
3810}
3811def C2_not : HInst<
3812(outs PredRegs:$Pd4),
3813(ins PredRegs:$Ps4),
3814"$Pd4 = not($Ps4)",
3815tc_151bf368, TypeCR>, Enc_65d691 {
3816let Inst{13-2} = 0b000000000000;
3817let Inst{31-18} = 0b01101011110000;
3818}
3819def C2_or : HInst<
3820(outs PredRegs:$Pd4),
3821(ins PredRegs:$Pt4, PredRegs:$Ps4),
3822"$Pd4 = or($Pt4,$Ps4)",
3823tc_651cbe02, TypeCR>, Enc_454a26 {
3824let Inst{7-2} = 0b000000;
3825let Inst{13-10} = 0b0000;
3826let Inst{31-18} = 0b01101011001000;
3827}
3828def C2_orn : HInst<
3829(outs PredRegs:$Pd4),
3830(ins PredRegs:$Pt4, PredRegs:$Ps4),
3831"$Pd4 = or($Pt4,!$Ps4)",
3832tc_651cbe02, TypeCR>, Enc_454a26 {
3833let Inst{7-2} = 0b000000;
3834let Inst{13-10} = 0b0000;
3835let Inst{31-18} = 0b01101011111000;
3836}
3837def C2_pxfer_map : HInst<
3838(outs PredRegs:$Pd4),
3839(ins PredRegs:$Ps4),
3840"$Pd4 = $Ps4",
3841tc_651cbe02, TypeMAPPING> {
3842let isPseudo = 1;
3843let isCodeGenOnly = 1;
3844}
3845def C2_tfrpr : HInst<
3846(outs IntRegs:$Rd32),
3847(ins PredRegs:$Ps4),
3848"$Rd32 = $Ps4",
3849tc_9f6cd987, TypeS_2op>, Enc_f5e933 {
3850let Inst{13-5} = 0b000000000;
3851let Inst{31-18} = 0b10001001010000;
3852let hasNewValue = 1;
3853let opNewValue = 0;
3854}
3855def C2_tfrrp : HInst<
3856(outs PredRegs:$Pd4),
3857(ins IntRegs:$Rs32),
3858"$Pd4 = $Rs32",
3859tc_55b33fda, TypeS_2op>, Enc_48b75f {
3860let Inst{13-2} = 0b000000000000;
3861let Inst{31-21} = 0b10000101010;
3862}
3863def C2_vitpack : HInst<
3864(outs IntRegs:$Rd32),
3865(ins PredRegs:$Ps4, PredRegs:$Pt4),
3866"$Rd32 = vitpack($Ps4,$Pt4)",
3867tc_f34c1c21, TypeS_2op>, Enc_527412 {
3868let Inst{7-5} = 0b000;
3869let Inst{13-10} = 0b0000;
3870let Inst{31-18} = 0b10001001000000;
3871let hasNewValue = 1;
3872let opNewValue = 0;
3873let prefersSlot3 = 1;
3874}
3875def C2_vmux : HInst<
3876(outs DoubleRegs:$Rdd32),
3877(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3878"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
3879tc_6fc5dbea, TypeALU64>, Enc_329361 {
3880let Inst{7-7} = 0b0;
3881let Inst{13-13} = 0b0;
3882let Inst{31-21} = 0b11010001000;
3883}
3884def C2_xor : HInst<
3885(outs PredRegs:$Pd4),
3886(ins PredRegs:$Ps4, PredRegs:$Pt4),
3887"$Pd4 = xor($Ps4,$Pt4)",
3888tc_651cbe02, TypeCR>, Enc_284ebb {
3889let Inst{7-2} = 0b000000;
3890let Inst{13-10} = 0b0000;
3891let Inst{31-18} = 0b01101011010000;
3892}
3893def C4_addipc : HInst<
3894(outs IntRegs:$Rd32),
3895(ins u32_0Imm:$Ii),
3896"$Rd32 = add(pc,#$Ii)",
3897tc_3edca78f, TypeCR>, Enc_607661 {
3898let Inst{6-5} = 0b00;
3899let Inst{13-13} = 0b0;
3900let Inst{31-16} = 0b0110101001001001;
3901let hasNewValue = 1;
3902let opNewValue = 0;
3903let isExtendable = 1;
3904let opExtendable = 1;
3905let isExtentSigned = 0;
3906let opExtentBits = 6;
3907let opExtentAlign = 0;
3908}
3909def C4_and_and : HInst<
3910(outs PredRegs:$Pd4),
3911(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3912"$Pd4 = and($Ps4,and($Pt4,$Pu4))",
3913tc_a7a13fac, TypeCR>, Enc_9ac432 {
3914let Inst{5-2} = 0b0000;
3915let Inst{13-10} = 0b0000;
3916let Inst{31-18} = 0b01101011000100;
3917}
3918def C4_and_andn : HInst<
3919(outs PredRegs:$Pd4),
3920(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3921"$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
3922tc_a7a13fac, TypeCR>, Enc_9ac432 {
3923let Inst{5-2} = 0b0000;
3924let Inst{13-10} = 0b0000;
3925let Inst{31-18} = 0b01101011100100;
3926}
3927def C4_and_or : HInst<
3928(outs PredRegs:$Pd4),
3929(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3930"$Pd4 = and($Ps4,or($Pt4,$Pu4))",
3931tc_a7a13fac, TypeCR>, Enc_9ac432 {
3932let Inst{5-2} = 0b0000;
3933let Inst{13-10} = 0b0000;
3934let Inst{31-18} = 0b01101011001100;
3935}
3936def C4_and_orn : HInst<
3937(outs PredRegs:$Pd4),
3938(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3939"$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
3940tc_a7a13fac, TypeCR>, Enc_9ac432 {
3941let Inst{5-2} = 0b0000;
3942let Inst{13-10} = 0b0000;
3943let Inst{31-18} = 0b01101011101100;
3944}
3945def C4_cmplte : HInst<
3946(outs PredRegs:$Pd4),
3947(ins IntRegs:$Rs32, IntRegs:$Rt32),
3948"$Pd4 = !cmp.gt($Rs32,$Rt32)",
3949tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3950let Inst{7-2} = 0b000100;
3951let Inst{13-13} = 0b0;
3952let Inst{31-21} = 0b11110010010;
3953let CextOpcode = "C4_cmplte";
3954let InputType = "reg";
3955let isCompare = 1;
3956}
3957def C4_cmpltei : HInst<
3958(outs PredRegs:$Pd4),
3959(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3960"$Pd4 = !cmp.gt($Rs32,#$Ii)",
3961tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3962let Inst{4-2} = 0b100;
3963let Inst{31-22} = 0b0111010101;
3964let CextOpcode = "C4_cmplte";
3965let InputType = "imm";
3966let isCompare = 1;
3967let isExtendable = 1;
3968let opExtendable = 2;
3969let isExtentSigned = 1;
3970let opExtentBits = 10;
3971let opExtentAlign = 0;
3972}
3973def C4_cmplteu : HInst<
3974(outs PredRegs:$Pd4),
3975(ins IntRegs:$Rs32, IntRegs:$Rt32),
3976"$Pd4 = !cmp.gtu($Rs32,$Rt32)",
3977tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3978let Inst{7-2} = 0b000100;
3979let Inst{13-13} = 0b0;
3980let Inst{31-21} = 0b11110010011;
3981let CextOpcode = "C4_cmplteu";
3982let InputType = "reg";
3983let isCompare = 1;
3984}
3985def C4_cmplteui : HInst<
3986(outs PredRegs:$Pd4),
3987(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3988"$Pd4 = !cmp.gtu($Rs32,#$Ii)",
3989tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3990let Inst{4-2} = 0b100;
3991let Inst{31-21} = 0b01110101100;
3992let CextOpcode = "C4_cmplteu";
3993let InputType = "imm";
3994let isCompare = 1;
3995let isExtendable = 1;
3996let opExtendable = 2;
3997let isExtentSigned = 0;
3998let opExtentBits = 9;
3999let opExtentAlign = 0;
4000}
4001def C4_cmpneq : HInst<
4002(outs PredRegs:$Pd4),
4003(ins IntRegs:$Rs32, IntRegs:$Rt32),
4004"$Pd4 = !cmp.eq($Rs32,$Rt32)",
4005tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
4006let Inst{7-2} = 0b000100;
4007let Inst{13-13} = 0b0;
4008let Inst{31-21} = 0b11110010000;
4009let CextOpcode = "C4_cmpneq";
4010let InputType = "reg";
4011let isCommutable = 1;
4012let isCompare = 1;
4013}
4014def C4_cmpneqi : HInst<
4015(outs PredRegs:$Pd4),
4016(ins IntRegs:$Rs32, s32_0Imm:$Ii),
4017"$Pd4 = !cmp.eq($Rs32,#$Ii)",
4018tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
4019let Inst{4-2} = 0b100;
4020let Inst{31-22} = 0b0111010100;
4021let CextOpcode = "C4_cmpneq";
4022let InputType = "imm";
4023let isCompare = 1;
4024let isExtendable = 1;
4025let opExtendable = 2;
4026let isExtentSigned = 1;
4027let opExtentBits = 10;
4028let opExtentAlign = 0;
4029}
4030def C4_fastcorner9 : HInst<
4031(outs PredRegs:$Pd4),
4032(ins PredRegs:$Ps4, PredRegs:$Pt4),
4033"$Pd4 = fastcorner9($Ps4,$Pt4)",
4034tc_651cbe02, TypeCR>, Enc_284ebb {
4035let Inst{7-2} = 0b100100;
4036let Inst{13-10} = 0b1000;
4037let Inst{31-18} = 0b01101011000000;
4038}
4039def C4_fastcorner9_not : HInst<
4040(outs PredRegs:$Pd4),
4041(ins PredRegs:$Ps4, PredRegs:$Pt4),
4042"$Pd4 = !fastcorner9($Ps4,$Pt4)",
4043tc_651cbe02, TypeCR>, Enc_284ebb {
4044let Inst{7-2} = 0b100100;
4045let Inst{13-10} = 0b1000;
4046let Inst{31-18} = 0b01101011000100;
4047}
4048def C4_nbitsclr : HInst<
4049(outs PredRegs:$Pd4),
4050(ins IntRegs:$Rs32, IntRegs:$Rt32),
4051"$Pd4 = !bitsclr($Rs32,$Rt32)",
4052tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4053let Inst{7-2} = 0b000000;
4054let Inst{13-13} = 0b0;
4055let Inst{31-21} = 0b11000111101;
4056}
4057def C4_nbitsclri : HInst<
4058(outs PredRegs:$Pd4),
4059(ins IntRegs:$Rs32, u6_0Imm:$Ii),
4060"$Pd4 = !bitsclr($Rs32,#$Ii)",
4061tc_a1297125, TypeS_2op>, Enc_5d6c34 {
4062let Inst{7-2} = 0b000000;
4063let Inst{31-21} = 0b10000101101;
4064}
4065def C4_nbitsset : HInst<
4066(outs PredRegs:$Pd4),
4067(ins IntRegs:$Rs32, IntRegs:$Rt32),
4068"$Pd4 = !bitsset($Rs32,$Rt32)",
4069tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4070let Inst{7-2} = 0b000000;
4071let Inst{13-13} = 0b0;
4072let Inst{31-21} = 0b11000111011;
4073}
4074def C4_or_and : HInst<
4075(outs PredRegs:$Pd4),
4076(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4077"$Pd4 = or($Ps4,and($Pt4,$Pu4))",
4078tc_a7a13fac, TypeCR>, Enc_9ac432 {
4079let Inst{5-2} = 0b0000;
4080let Inst{13-10} = 0b0000;
4081let Inst{31-18} = 0b01101011010100;
4082}
4083def C4_or_andn : HInst<
4084(outs PredRegs:$Pd4),
4085(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4086"$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
4087tc_a7a13fac, TypeCR>, Enc_9ac432 {
4088let Inst{5-2} = 0b0000;
4089let Inst{13-10} = 0b0000;
4090let Inst{31-18} = 0b01101011110100;
4091}
4092def C4_or_or : HInst<
4093(outs PredRegs:$Pd4),
4094(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4095"$Pd4 = or($Ps4,or($Pt4,$Pu4))",
4096tc_a7a13fac, TypeCR>, Enc_9ac432 {
4097let Inst{5-2} = 0b0000;
4098let Inst{13-10} = 0b0000;
4099let Inst{31-18} = 0b01101011011100;
4100}
4101def C4_or_orn : HInst<
4102(outs PredRegs:$Pd4),
4103(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4104"$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
4105tc_a7a13fac, TypeCR>, Enc_9ac432 {
4106let Inst{5-2} = 0b0000;
4107let Inst{13-10} = 0b0000;
4108let Inst{31-18} = 0b01101011111100;
4109}
4110def F2_conv_d2df : HInst<
4111(outs DoubleRegs:$Rdd32),
4112(ins DoubleRegs:$Rss32),
4113"$Rdd32 = convert_d2df($Rss32)",
4114tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4115let Inst{13-5} = 0b000000011;
4116let Inst{31-21} = 0b10000000111;
4117let isFP = 1;
4118let Uses = [USR];
4119}
4120def F2_conv_d2sf : HInst<
4121(outs IntRegs:$Rd32),
4122(ins DoubleRegs:$Rss32),
4123"$Rd32 = convert_d2sf($Rss32)",
4124tc_9783714b, TypeS_2op>, Enc_90cd8b {
4125let Inst{13-5} = 0b000000001;
4126let Inst{31-21} = 0b10001000010;
4127let hasNewValue = 1;
4128let opNewValue = 0;
4129let isFP = 1;
4130let Uses = [USR];
4131}
4132def F2_conv_df2d : HInst<
4133(outs DoubleRegs:$Rdd32),
4134(ins DoubleRegs:$Rss32),
4135"$Rdd32 = convert_df2d($Rss32)",
4136tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4137let Inst{13-5} = 0b000000000;
4138let Inst{31-21} = 0b10000000111;
4139let isFP = 1;
4140let Uses = [USR];
4141}
4142def F2_conv_df2d_chop : HInst<
4143(outs DoubleRegs:$Rdd32),
4144(ins DoubleRegs:$Rss32),
4145"$Rdd32 = convert_df2d($Rss32):chop",
4146tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4147let Inst{13-5} = 0b000000110;
4148let Inst{31-21} = 0b10000000111;
4149let isFP = 1;
4150let Uses = [USR];
4151}
4152def F2_conv_df2sf : HInst<
4153(outs IntRegs:$Rd32),
4154(ins DoubleRegs:$Rss32),
4155"$Rd32 = convert_df2sf($Rss32)",
4156tc_9783714b, TypeS_2op>, Enc_90cd8b {
4157let Inst{13-5} = 0b000000001;
4158let Inst{31-21} = 0b10001000000;
4159let hasNewValue = 1;
4160let opNewValue = 0;
4161let isFP = 1;
4162let Uses = [USR];
4163}
4164def F2_conv_df2ud : HInst<
4165(outs DoubleRegs:$Rdd32),
4166(ins DoubleRegs:$Rss32),
4167"$Rdd32 = convert_df2ud($Rss32)",
4168tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4169let Inst{13-5} = 0b000000001;
4170let Inst{31-21} = 0b10000000111;
4171let isFP = 1;
4172let Uses = [USR];
4173}
4174def F2_conv_df2ud_chop : HInst<
4175(outs DoubleRegs:$Rdd32),
4176(ins DoubleRegs:$Rss32),
4177"$Rdd32 = convert_df2ud($Rss32):chop",
4178tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4179let Inst{13-5} = 0b000000111;
4180let Inst{31-21} = 0b10000000111;
4181let isFP = 1;
4182let Uses = [USR];
4183}
4184def F2_conv_df2uw : HInst<
4185(outs IntRegs:$Rd32),
4186(ins DoubleRegs:$Rss32),
4187"$Rd32 = convert_df2uw($Rss32)",
4188tc_9783714b, TypeS_2op>, Enc_90cd8b {
4189let Inst{13-5} = 0b000000001;
4190let Inst{31-21} = 0b10001000011;
4191let hasNewValue = 1;
4192let opNewValue = 0;
4193let isFP = 1;
4194let Uses = [USR];
4195}
4196def F2_conv_df2uw_chop : HInst<
4197(outs IntRegs:$Rd32),
4198(ins DoubleRegs:$Rss32),
4199"$Rd32 = convert_df2uw($Rss32):chop",
4200tc_9783714b, TypeS_2op>, Enc_90cd8b {
4201let Inst{13-5} = 0b000000001;
4202let Inst{31-21} = 0b10001000101;
4203let hasNewValue = 1;
4204let opNewValue = 0;
4205let isFP = 1;
4206let Uses = [USR];
4207}
4208def F2_conv_df2w : HInst<
4209(outs IntRegs:$Rd32),
4210(ins DoubleRegs:$Rss32),
4211"$Rd32 = convert_df2w($Rss32)",
4212tc_9783714b, TypeS_2op>, Enc_90cd8b {
4213let Inst{13-5} = 0b000000001;
4214let Inst{31-21} = 0b10001000100;
4215let hasNewValue = 1;
4216let opNewValue = 0;
4217let isFP = 1;
4218let Uses = [USR];
4219}
4220def F2_conv_df2w_chop : HInst<
4221(outs IntRegs:$Rd32),
4222(ins DoubleRegs:$Rss32),
4223"$Rd32 = convert_df2w($Rss32):chop",
4224tc_9783714b, TypeS_2op>, Enc_90cd8b {
4225let Inst{13-5} = 0b000000001;
4226let Inst{31-21} = 0b10001000111;
4227let hasNewValue = 1;
4228let opNewValue = 0;
4229let isFP = 1;
4230let Uses = [USR];
4231}
4232def F2_conv_sf2d : HInst<
4233(outs DoubleRegs:$Rdd32),
4234(ins IntRegs:$Rs32),
4235"$Rdd32 = convert_sf2d($Rs32)",
4236tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4237let Inst{13-5} = 0b000000100;
4238let Inst{31-21} = 0b10000100100;
4239let isFP = 1;
4240let Uses = [USR];
4241}
4242def F2_conv_sf2d_chop : HInst<
4243(outs DoubleRegs:$Rdd32),
4244(ins IntRegs:$Rs32),
4245"$Rdd32 = convert_sf2d($Rs32):chop",
4246tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4247let Inst{13-5} = 0b000000110;
4248let Inst{31-21} = 0b10000100100;
4249let isFP = 1;
4250let Uses = [USR];
4251}
4252def F2_conv_sf2df : HInst<
4253(outs DoubleRegs:$Rdd32),
4254(ins IntRegs:$Rs32),
4255"$Rdd32 = convert_sf2df($Rs32)",
4256tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4257let Inst{13-5} = 0b000000000;
4258let Inst{31-21} = 0b10000100100;
4259let isFP = 1;
4260let Uses = [USR];
4261}
4262def F2_conv_sf2ud : HInst<
4263(outs DoubleRegs:$Rdd32),
4264(ins IntRegs:$Rs32),
4265"$Rdd32 = convert_sf2ud($Rs32)",
4266tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4267let Inst{13-5} = 0b000000011;
4268let Inst{31-21} = 0b10000100100;
4269let isFP = 1;
4270let Uses = [USR];
4271}
4272def F2_conv_sf2ud_chop : HInst<
4273(outs DoubleRegs:$Rdd32),
4274(ins IntRegs:$Rs32),
4275"$Rdd32 = convert_sf2ud($Rs32):chop",
4276tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4277let Inst{13-5} = 0b000000101;
4278let Inst{31-21} = 0b10000100100;
4279let isFP = 1;
4280let Uses = [USR];
4281}
4282def F2_conv_sf2uw : HInst<
4283(outs IntRegs:$Rd32),
4284(ins IntRegs:$Rs32),
4285"$Rd32 = convert_sf2uw($Rs32)",
4286tc_9783714b, TypeS_2op>, Enc_5e2823 {
4287let Inst{13-5} = 0b000000000;
4288let Inst{31-21} = 0b10001011011;
4289let hasNewValue = 1;
4290let opNewValue = 0;
4291let isFP = 1;
4292let Uses = [USR];
4293}
4294def F2_conv_sf2uw_chop : HInst<
4295(outs IntRegs:$Rd32),
4296(ins IntRegs:$Rs32),
4297"$Rd32 = convert_sf2uw($Rs32):chop",
4298tc_9783714b, TypeS_2op>, Enc_5e2823 {
4299let Inst{13-5} = 0b000000001;
4300let Inst{31-21} = 0b10001011011;
4301let hasNewValue = 1;
4302let opNewValue = 0;
4303let isFP = 1;
4304let Uses = [USR];
4305}
4306def F2_conv_sf2w : HInst<
4307(outs IntRegs:$Rd32),
4308(ins IntRegs:$Rs32),
4309"$Rd32 = convert_sf2w($Rs32)",
4310tc_9783714b, TypeS_2op>, Enc_5e2823 {
4311let Inst{13-5} = 0b000000000;
4312let Inst{31-21} = 0b10001011100;
4313let hasNewValue = 1;
4314let opNewValue = 0;
4315let isFP = 1;
4316let Uses = [USR];
4317}
4318def F2_conv_sf2w_chop : HInst<
4319(outs IntRegs:$Rd32),
4320(ins IntRegs:$Rs32),
4321"$Rd32 = convert_sf2w($Rs32):chop",
4322tc_9783714b, TypeS_2op>, Enc_5e2823 {
4323let Inst{13-5} = 0b000000001;
4324let Inst{31-21} = 0b10001011100;
4325let hasNewValue = 1;
4326let opNewValue = 0;
4327let isFP = 1;
4328let Uses = [USR];
4329}
4330def F2_conv_ud2df : HInst<
4331(outs DoubleRegs:$Rdd32),
4332(ins DoubleRegs:$Rss32),
4333"$Rdd32 = convert_ud2df($Rss32)",
4334tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4335let Inst{13-5} = 0b000000010;
4336let Inst{31-21} = 0b10000000111;
4337let isFP = 1;
4338let Uses = [USR];
4339}
4340def F2_conv_ud2sf : HInst<
4341(outs IntRegs:$Rd32),
4342(ins DoubleRegs:$Rss32),
4343"$Rd32 = convert_ud2sf($Rss32)",
4344tc_9783714b, TypeS_2op>, Enc_90cd8b {
4345let Inst{13-5} = 0b000000001;
4346let Inst{31-21} = 0b10001000001;
4347let hasNewValue = 1;
4348let opNewValue = 0;
4349let isFP = 1;
4350let Uses = [USR];
4351}
4352def F2_conv_uw2df : HInst<
4353(outs DoubleRegs:$Rdd32),
4354(ins IntRegs:$Rs32),
4355"$Rdd32 = convert_uw2df($Rs32)",
4356tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4357let Inst{13-5} = 0b000000001;
4358let Inst{31-21} = 0b10000100100;
4359let isFP = 1;
4360let Uses = [USR];
4361}
4362def F2_conv_uw2sf : HInst<
4363(outs IntRegs:$Rd32),
4364(ins IntRegs:$Rs32),
4365"$Rd32 = convert_uw2sf($Rs32)",
4366tc_9783714b, TypeS_2op>, Enc_5e2823 {
4367let Inst{13-5} = 0b000000000;
4368let Inst{31-21} = 0b10001011001;
4369let hasNewValue = 1;
4370let opNewValue = 0;
4371let isFP = 1;
4372let Uses = [USR];
4373}
4374def F2_conv_w2df : HInst<
4375(outs DoubleRegs:$Rdd32),
4376(ins IntRegs:$Rs32),
4377"$Rdd32 = convert_w2df($Rs32)",
4378tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4379let Inst{13-5} = 0b000000010;
4380let Inst{31-21} = 0b10000100100;
4381let isFP = 1;
4382let Uses = [USR];
4383}
4384def F2_conv_w2sf : HInst<
4385(outs IntRegs:$Rd32),
4386(ins IntRegs:$Rs32),
4387"$Rd32 = convert_w2sf($Rs32)",
4388tc_9783714b, TypeS_2op>, Enc_5e2823 {
4389let Inst{13-5} = 0b000000000;
4390let Inst{31-21} = 0b10001011010;
4391let hasNewValue = 1;
4392let opNewValue = 0;
4393let isFP = 1;
4394let Uses = [USR];
4395}
4396def F2_dfadd : HInst<
4397(outs DoubleRegs:$Rdd32),
4398(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4399"$Rdd32 = dfadd($Rss32,$Rtt32)",
4400tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4401let Inst{7-5} = 0b011;
4402let Inst{13-13} = 0b0;
4403let Inst{31-21} = 0b11101000000;
4404let isFP = 1;
4405let Uses = [USR];
4406}
4407def F2_dfclass : HInst<
4408(outs PredRegs:$Pd4),
4409(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
4410"$Pd4 = dfclass($Rss32,#$Ii)",
4411tc_a1297125, TypeALU64>, Enc_1f19b5 {
4412let Inst{4-2} = 0b100;
4413let Inst{13-10} = 0b0000;
4414let Inst{31-21} = 0b11011100100;
4415let isFP = 1;
4416let Uses = [USR];
4417}
4418def F2_dfcmpeq : HInst<
4419(outs PredRegs:$Pd4),
4420(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4421"$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
4422tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4423let Inst{7-2} = 0b000000;
4424let Inst{13-13} = 0b0;
4425let Inst{31-21} = 0b11010010111;
4426let isFP = 1;
4427let Uses = [USR];
4428let isCompare = 1;
4429}
4430def F2_dfcmpge : HInst<
4431(outs PredRegs:$Pd4),
4432(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4433"$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
4434tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4435let Inst{7-2} = 0b010000;
4436let Inst{13-13} = 0b0;
4437let Inst{31-21} = 0b11010010111;
4438let isFP = 1;
4439let Uses = [USR];
4440let isCompare = 1;
4441}
4442def F2_dfcmpgt : HInst<
4443(outs PredRegs:$Pd4),
4444(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4445"$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
4446tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4447let Inst{7-2} = 0b001000;
4448let Inst{13-13} = 0b0;
4449let Inst{31-21} = 0b11010010111;
4450let isFP = 1;
4451let Uses = [USR];
4452let isCompare = 1;
4453}
4454def F2_dfcmpuo : HInst<
4455(outs PredRegs:$Pd4),
4456(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4457"$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
4458tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4459let Inst{7-2} = 0b011000;
4460let Inst{13-13} = 0b0;
4461let Inst{31-21} = 0b11010010111;
4462let isFP = 1;
4463let Uses = [USR];
4464let isCompare = 1;
4465}
4466def F2_dfimm_n : HInst<
4467(outs DoubleRegs:$Rdd32),
4468(ins u10_0Imm:$Ii),
4469"$Rdd32 = dfmake(#$Ii):neg",
4470tc_65279839, TypeALU64>, Enc_e6c957 {
4471let Inst{20-16} = 0b00000;
4472let Inst{31-22} = 0b1101100101;
4473let prefersSlot3 = 1;
4474}
4475def F2_dfimm_p : HInst<
4476(outs DoubleRegs:$Rdd32),
4477(ins u10_0Imm:$Ii),
4478"$Rdd32 = dfmake(#$Ii):pos",
4479tc_65279839, TypeALU64>, Enc_e6c957 {
4480let Inst{20-16} = 0b00000;
4481let Inst{31-22} = 0b1101100100;
4482let prefersSlot3 = 1;
4483}
4484def F2_dfmax : HInst<
4485(outs DoubleRegs:$Rdd32),
4486(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4487"$Rdd32 = dfmax($Rss32,$Rtt32)",
4488tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4489let Inst{7-5} = 0b011;
4490let Inst{13-13} = 0b0;
4491let Inst{31-21} = 0b11101000001;
4492let isFP = 1;
4493let prefersSlot3 = 1;
4494let Uses = [USR];
4495}
4496def F2_dfmin : HInst<
4497(outs DoubleRegs:$Rdd32),
4498(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4499"$Rdd32 = dfmin($Rss32,$Rtt32)",
4500tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4501let Inst{7-5} = 0b011;
4502let Inst{13-13} = 0b0;
4503let Inst{31-21} = 0b11101000110;
4504let isFP = 1;
4505let prefersSlot3 = 1;
4506let Uses = [USR];
4507}
4508def F2_dfmpyfix : HInst<
4509(outs DoubleRegs:$Rdd32),
4510(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4511"$Rdd32 = dfmpyfix($Rss32,$Rtt32)",
4512tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> {
4513let Inst{7-5} = 0b011;
4514let Inst{13-13} = 0b0;
4515let Inst{31-21} = 0b11101000010;
4516let isFP = 1;
4517let Uses = [USR];
4518}
4519def F2_dfmpyhh : HInst<
4520(outs DoubleRegs:$Rxx32),
4521(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4522"$Rxx32 += dfmpyhh($Rss32,$Rtt32)",
4523tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4524let Inst{7-5} = 0b011;
4525let Inst{13-13} = 0b0;
4526let Inst{31-21} = 0b11101010100;
4527let isFP = 1;
4528let Uses = [USR];
4529let Constraints = "$Rxx32 = $Rxx32in";
4530}
4531def F2_dfmpylh : HInst<
4532(outs DoubleRegs:$Rxx32),
4533(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4534"$Rxx32 += dfmpylh($Rss32,$Rtt32)",
4535tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4536let Inst{7-5} = 0b011;
4537let Inst{13-13} = 0b0;
4538let Inst{31-21} = 0b11101010000;
4539let prefersSlot3 = 1;
4540let Constraints = "$Rxx32 = $Rxx32in";
4541}
4542def F2_dfmpyll : HInst<
4543(outs DoubleRegs:$Rdd32),
4544(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4545"$Rdd32 = dfmpyll($Rss32,$Rtt32)",
4546tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> {
4547let Inst{7-5} = 0b011;
4548let Inst{13-13} = 0b0;
4549let Inst{31-21} = 0b11101000101;
4550let prefersSlot3 = 1;
4551}
4552def F2_dfsub : HInst<
4553(outs DoubleRegs:$Rdd32),
4554(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4555"$Rdd32 = dfsub($Rss32,$Rtt32)",
4556tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4557let Inst{7-5} = 0b011;
4558let Inst{13-13} = 0b0;
4559let Inst{31-21} = 0b11101000100;
4560let isFP = 1;
4561let Uses = [USR];
4562}
4563def F2_sfadd : HInst<
4564(outs IntRegs:$Rd32),
4565(ins IntRegs:$Rs32, IntRegs:$Rt32),
4566"$Rd32 = sfadd($Rs32,$Rt32)",
4567tc_02fe1c65, TypeM>, Enc_5ab2be {
4568let Inst{7-5} = 0b000;
4569let Inst{13-13} = 0b0;
4570let Inst{31-21} = 0b11101011000;
4571let hasNewValue = 1;
4572let opNewValue = 0;
4573let isFP = 1;
4574let Uses = [USR];
4575let isCommutable = 1;
4576}
4577def F2_sfclass : HInst<
4578(outs PredRegs:$Pd4),
4579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
4580"$Pd4 = sfclass($Rs32,#$Ii)",
4581tc_a1297125, TypeS_2op>, Enc_83ee64 {
4582let Inst{7-2} = 0b000000;
4583let Inst{13-13} = 0b0;
4584let Inst{31-21} = 0b10000101111;
4585let isFP = 1;
4586let Uses = [USR];
4587}
4588def F2_sfcmpeq : HInst<
4589(outs PredRegs:$Pd4),
4590(ins IntRegs:$Rs32, IntRegs:$Rt32),
4591"$Pd4 = sfcmp.eq($Rs32,$Rt32)",
4592tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4593let Inst{7-2} = 0b011000;
4594let Inst{13-13} = 0b0;
4595let Inst{31-21} = 0b11000111111;
4596let isFP = 1;
4597let Uses = [USR];
4598let isCompare = 1;
4599}
4600def F2_sfcmpge : HInst<
4601(outs PredRegs:$Pd4),
4602(ins IntRegs:$Rs32, IntRegs:$Rt32),
4603"$Pd4 = sfcmp.ge($Rs32,$Rt32)",
4604tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4605let Inst{7-2} = 0b000000;
4606let Inst{13-13} = 0b0;
4607let Inst{31-21} = 0b11000111111;
4608let isFP = 1;
4609let Uses = [USR];
4610let isCompare = 1;
4611}
4612def F2_sfcmpgt : HInst<
4613(outs PredRegs:$Pd4),
4614(ins IntRegs:$Rs32, IntRegs:$Rt32),
4615"$Pd4 = sfcmp.gt($Rs32,$Rt32)",
4616tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4617let Inst{7-2} = 0b100000;
4618let Inst{13-13} = 0b0;
4619let Inst{31-21} = 0b11000111111;
4620let isFP = 1;
4621let Uses = [USR];
4622let isCompare = 1;
4623}
4624def F2_sfcmpuo : HInst<
4625(outs PredRegs:$Pd4),
4626(ins IntRegs:$Rs32, IntRegs:$Rt32),
4627"$Pd4 = sfcmp.uo($Rs32,$Rt32)",
4628tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4629let Inst{7-2} = 0b001000;
4630let Inst{13-13} = 0b0;
4631let Inst{31-21} = 0b11000111111;
4632let isFP = 1;
4633let Uses = [USR];
4634let isCompare = 1;
4635}
4636def F2_sffixupd : HInst<
4637(outs IntRegs:$Rd32),
4638(ins IntRegs:$Rs32, IntRegs:$Rt32),
4639"$Rd32 = sffixupd($Rs32,$Rt32)",
4640tc_02fe1c65, TypeM>, Enc_5ab2be {
4641let Inst{7-5} = 0b001;
4642let Inst{13-13} = 0b0;
4643let Inst{31-21} = 0b11101011110;
4644let hasNewValue = 1;
4645let opNewValue = 0;
4646let isFP = 1;
4647}
4648def F2_sffixupn : HInst<
4649(outs IntRegs:$Rd32),
4650(ins IntRegs:$Rs32, IntRegs:$Rt32),
4651"$Rd32 = sffixupn($Rs32,$Rt32)",
4652tc_02fe1c65, TypeM>, Enc_5ab2be {
4653let Inst{7-5} = 0b000;
4654let Inst{13-13} = 0b0;
4655let Inst{31-21} = 0b11101011110;
4656let hasNewValue = 1;
4657let opNewValue = 0;
4658let isFP = 1;
4659}
4660def F2_sffixupr : HInst<
4661(outs IntRegs:$Rd32),
4662(ins IntRegs:$Rs32),
4663"$Rd32 = sffixupr($Rs32)",
4664tc_9783714b, TypeS_2op>, Enc_5e2823 {
4665let Inst{13-5} = 0b000000000;
4666let Inst{31-21} = 0b10001011101;
4667let hasNewValue = 1;
4668let opNewValue = 0;
4669let isFP = 1;
4670}
4671def F2_sffma : HInst<
4672(outs IntRegs:$Rx32),
4673(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4674"$Rx32 += sfmpy($Rs32,$Rt32)",
4675tc_9e72dc89, TypeM>, Enc_2ae154 {
4676let Inst{7-5} = 0b100;
4677let Inst{13-13} = 0b0;
4678let Inst{31-21} = 0b11101111000;
4679let hasNewValue = 1;
4680let opNewValue = 0;
4681let isFP = 1;
4682let Uses = [USR];
4683let Constraints = "$Rx32 = $Rx32in";
4684}
4685def F2_sffma_lib : HInst<
4686(outs IntRegs:$Rx32),
4687(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4688"$Rx32 += sfmpy($Rs32,$Rt32):lib",
4689tc_9e72dc89, TypeM>, Enc_2ae154 {
4690let Inst{7-5} = 0b110;
4691let Inst{13-13} = 0b0;
4692let Inst{31-21} = 0b11101111000;
4693let hasNewValue = 1;
4694let opNewValue = 0;
4695let isFP = 1;
4696let Uses = [USR];
4697let Constraints = "$Rx32 = $Rx32in";
4698}
4699def F2_sffma_sc : HInst<
4700(outs IntRegs:$Rx32),
4701(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
4702"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
4703tc_9edb7c77, TypeM>, Enc_437f33 {
4704let Inst{7-7} = 0b1;
4705let Inst{13-13} = 0b0;
4706let Inst{31-21} = 0b11101111011;
4707let hasNewValue = 1;
4708let opNewValue = 0;
4709let isFP = 1;
4710let Uses = [USR];
4711let Constraints = "$Rx32 = $Rx32in";
4712}
4713def F2_sffms : HInst<
4714(outs IntRegs:$Rx32),
4715(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4716"$Rx32 -= sfmpy($Rs32,$Rt32)",
4717tc_9e72dc89, TypeM>, Enc_2ae154 {
4718let Inst{7-5} = 0b101;
4719let Inst{13-13} = 0b0;
4720let Inst{31-21} = 0b11101111000;
4721let hasNewValue = 1;
4722let opNewValue = 0;
4723let isFP = 1;
4724let Uses = [USR];
4725let Constraints = "$Rx32 = $Rx32in";
4726}
4727def F2_sffms_lib : HInst<
4728(outs IntRegs:$Rx32),
4729(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4730"$Rx32 -= sfmpy($Rs32,$Rt32):lib",
4731tc_9e72dc89, TypeM>, Enc_2ae154 {
4732let Inst{7-5} = 0b111;
4733let Inst{13-13} = 0b0;
4734let Inst{31-21} = 0b11101111000;
4735let hasNewValue = 1;
4736let opNewValue = 0;
4737let isFP = 1;
4738let Uses = [USR];
4739let Constraints = "$Rx32 = $Rx32in";
4740}
4741def F2_sfimm_n : HInst<
4742(outs IntRegs:$Rd32),
4743(ins u10_0Imm:$Ii),
4744"$Rd32 = sfmake(#$Ii):neg",
4745tc_65279839, TypeALU64>, Enc_6c9440 {
4746let Inst{20-16} = 0b00000;
4747let Inst{31-22} = 0b1101011001;
4748let hasNewValue = 1;
4749let opNewValue = 0;
4750let prefersSlot3 = 1;
4751}
4752def F2_sfimm_p : HInst<
4753(outs IntRegs:$Rd32),
4754(ins u10_0Imm:$Ii),
4755"$Rd32 = sfmake(#$Ii):pos",
4756tc_65279839, TypeALU64>, Enc_6c9440 {
4757let Inst{20-16} = 0b00000;
4758let Inst{31-22} = 0b1101011000;
4759let hasNewValue = 1;
4760let opNewValue = 0;
4761let prefersSlot3 = 1;
4762}
4763def F2_sfinvsqrta : HInst<
4764(outs IntRegs:$Rd32, PredRegs:$Pe4),
4765(ins IntRegs:$Rs32),
4766"$Rd32,$Pe4 = sfinvsqrta($Rs32)",
4767tc_7f7f45f5, TypeS_2op>, Enc_890909 {
4768let Inst{13-7} = 0b0000000;
4769let Inst{31-21} = 0b10001011111;
4770let hasNewValue = 1;
4771let opNewValue = 0;
4772let isFP = 1;
4773let isPredicateLate = 1;
4774}
4775def F2_sfmax : HInst<
4776(outs IntRegs:$Rd32),
4777(ins IntRegs:$Rs32, IntRegs:$Rt32),
4778"$Rd32 = sfmax($Rs32,$Rt32)",
4779tc_c20701f0, TypeM>, Enc_5ab2be {
4780let Inst{7-5} = 0b000;
4781let Inst{13-13} = 0b0;
4782let Inst{31-21} = 0b11101011100;
4783let hasNewValue = 1;
4784let opNewValue = 0;
4785let isFP = 1;
4786let prefersSlot3 = 1;
4787let Uses = [USR];
4788}
4789def F2_sfmin : HInst<
4790(outs IntRegs:$Rd32),
4791(ins IntRegs:$Rs32, IntRegs:$Rt32),
4792"$Rd32 = sfmin($Rs32,$Rt32)",
4793tc_c20701f0, TypeM>, Enc_5ab2be {
4794let Inst{7-5} = 0b001;
4795let Inst{13-13} = 0b0;
4796let Inst{31-21} = 0b11101011100;
4797let hasNewValue = 1;
4798let opNewValue = 0;
4799let isFP = 1;
4800let prefersSlot3 = 1;
4801let Uses = [USR];
4802}
4803def F2_sfmpy : HInst<
4804(outs IntRegs:$Rd32),
4805(ins IntRegs:$Rs32, IntRegs:$Rt32),
4806"$Rd32 = sfmpy($Rs32,$Rt32)",
4807tc_02fe1c65, TypeM>, Enc_5ab2be {
4808let Inst{7-5} = 0b000;
4809let Inst{13-13} = 0b0;
4810let Inst{31-21} = 0b11101011010;
4811let hasNewValue = 1;
4812let opNewValue = 0;
4813let isFP = 1;
4814let Uses = [USR];
4815let isCommutable = 1;
4816}
4817def F2_sfrecipa : HInst<
4818(outs IntRegs:$Rd32, PredRegs:$Pe4),
4819(ins IntRegs:$Rs32, IntRegs:$Rt32),
4820"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
4821tc_f7569068, TypeM>, Enc_a94f3b {
4822let Inst{7-7} = 0b1;
4823let Inst{13-13} = 0b0;
4824let Inst{31-21} = 0b11101011111;
4825let hasNewValue = 1;
4826let opNewValue = 0;
4827let isFP = 1;
4828let isPredicateLate = 1;
4829}
4830def F2_sfsub : HInst<
4831(outs IntRegs:$Rd32),
4832(ins IntRegs:$Rs32, IntRegs:$Rt32),
4833"$Rd32 = sfsub($Rs32,$Rt32)",
4834tc_02fe1c65, TypeM>, Enc_5ab2be {
4835let Inst{7-5} = 0b001;
4836let Inst{13-13} = 0b0;
4837let Inst{31-21} = 0b11101011000;
4838let hasNewValue = 1;
4839let opNewValue = 0;
4840let isFP = 1;
4841let Uses = [USR];
4842}
4843def G4_tfrgcpp : HInst<
4844(outs DoubleRegs:$Rdd32),
4845(ins GuestRegs64:$Gss32),
4846"$Rdd32 = $Gss32",
4847tc_fae9dfa5, TypeCR>, Enc_0aa344 {
4848let Inst{13-5} = 0b000000000;
4849let Inst{31-21} = 0b01101000001;
4850}
4851def G4_tfrgcrr : HInst<
4852(outs IntRegs:$Rd32),
4853(ins GuestRegs:$Gs32),
4854"$Rd32 = $Gs32",
4855tc_fae9dfa5, TypeCR>, Enc_44271f {
4856let Inst{13-5} = 0b000000000;
4857let Inst{31-21} = 0b01101010001;
4858let hasNewValue = 1;
4859let opNewValue = 0;
4860}
4861def G4_tfrgpcp : HInst<
4862(outs GuestRegs64:$Gdd32),
4863(ins DoubleRegs:$Rss32),
4864"$Gdd32 = $Rss32",
4865tc_6ae3426b, TypeCR>, Enc_ed5027 {
4866let Inst{13-5} = 0b000000000;
4867let Inst{31-21} = 0b01100011000;
4868let hasNewValue = 1;
4869let opNewValue = 0;
4870}
4871def G4_tfrgrcr : HInst<
4872(outs GuestRegs:$Gd32),
4873(ins IntRegs:$Rs32),
4874"$Gd32 = $Rs32",
4875tc_6ae3426b, TypeCR>, Enc_621fba {
4876let Inst{13-5} = 0b000000000;
4877let Inst{31-21} = 0b01100010000;
4878let hasNewValue = 1;
4879let opNewValue = 0;
4880}
4881def J2_call : HInst<
4882(outs),
4883(ins a30_2Imm:$Ii),
4884"call $Ii",
4885tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel {
4886let Inst{0-0} = 0b0;
4887let Inst{31-25} = 0b0101101;
4888let isCall = 1;
4889let prefersSlot3 = 1;
4890let cofRelax2 = 1;
4891let cofMax1 = 1;
4892let Uses = [R29];
4893let Defs = [PC, R31];
4894let BaseOpcode = "J2_call";
4895let hasSideEffects = 1;
4896let isPredicable = 1;
4897let isExtendable = 1;
4898let opExtendable = 0;
4899let isExtentSigned = 1;
4900let opExtentBits = 24;
4901let opExtentAlign = 2;
4902}
4903def J2_callf : HInst<
4904(outs),
4905(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4906"if (!$Pu4) call $Ii",
4907tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4908let Inst{0-0} = 0b0;
4909let Inst{12-10} = 0b000;
4910let Inst{21-21} = 0b1;
4911let Inst{31-24} = 0b01011101;
4912let isPredicated = 1;
4913let isPredicatedFalse = 1;
4914let isCall = 1;
4915let prefersSlot3 = 1;
4916let cofRelax1 = 1;
4917let cofRelax2 = 1;
4918let cofMax1 = 1;
4919let Uses = [R29];
4920let Defs = [PC, R31];
4921let BaseOpcode = "J2_call";
4922let hasSideEffects = 1;
4923let isTaken = Inst{12};
4924let isExtendable = 1;
4925let opExtendable = 1;
4926let isExtentSigned = 1;
4927let opExtentBits = 17;
4928let opExtentAlign = 2;
4929}
4930def J2_callr : HInst<
4931(outs),
4932(ins IntRegs:$Rs32),
4933"callr $Rs32",
4934tc_362b0be2, TypeJ>, Enc_ecbcc8 {
4935let Inst{13-0} = 0b00000000000000;
4936let Inst{31-21} = 0b01010000101;
4937let isCall = 1;
4938let prefersSlot3 = 1;
4939let cofMax1 = 1;
4940let Uses = [R29];
4941let Defs = [PC, R31];
4942let hasSideEffects = 1;
4943}
4944def J2_callrf : HInst<
4945(outs),
4946(ins PredRegs:$Pu4, IntRegs:$Rs32),
4947"if (!$Pu4) callr $Rs32",
4948tc_dc51281d, TypeJ>, Enc_88d4d9 {
4949let Inst{7-0} = 0b00000000;
4950let Inst{13-10} = 0b0000;
4951let Inst{31-21} = 0b01010001001;
4952let isPredicated = 1;
4953let isPredicatedFalse = 1;
4954let isCall = 1;
4955let prefersSlot3 = 1;
4956let cofMax1 = 1;
4957let Uses = [R29];
4958let Defs = [PC, R31];
4959let hasSideEffects = 1;
4960let isTaken = Inst{12};
4961}
4962def J2_callrh : HInst<
4963(outs),
4964(ins IntRegs:$Rs32),
4965"callrh $Rs32",
4966tc_95f43c5e, TypeJ>, Enc_ecbcc8, Requires<[HasV73]> {
4967let Inst{13-0} = 0b00000000000000;
4968let Inst{31-21} = 0b01010000110;
4969let isCall = 1;
4970let prefersSlot3 = 1;
4971let cofMax1 = 1;
4972let Defs = [PC, R31];
4973}
4974def J2_callrt : HInst<
4975(outs),
4976(ins PredRegs:$Pu4, IntRegs:$Rs32),
4977"if ($Pu4) callr $Rs32",
4978tc_dc51281d, TypeJ>, Enc_88d4d9 {
4979let Inst{7-0} = 0b00000000;
4980let Inst{13-10} = 0b0000;
4981let Inst{31-21} = 0b01010001000;
4982let isPredicated = 1;
4983let isCall = 1;
4984let prefersSlot3 = 1;
4985let cofMax1 = 1;
4986let Uses = [R29];
4987let Defs = [PC, R31];
4988let hasSideEffects = 1;
4989let isTaken = Inst{12};
4990}
4991def J2_callt : HInst<
4992(outs),
4993(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4994"if ($Pu4) call $Ii",
4995tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4996let Inst{0-0} = 0b0;
4997let Inst{12-10} = 0b000;
4998let Inst{21-21} = 0b0;
4999let Inst{31-24} = 0b01011101;
5000let isPredicated = 1;
5001let isCall = 1;
5002let prefersSlot3 = 1;
5003let cofRelax1 = 1;
5004let cofRelax2 = 1;
5005let cofMax1 = 1;
5006let Uses = [R29];
5007let Defs = [PC, R31];
5008let BaseOpcode = "J2_call";
5009let hasSideEffects = 1;
5010let isTaken = Inst{12};
5011let isExtendable = 1;
5012let opExtendable = 1;
5013let isExtentSigned = 1;
5014let opExtentBits = 17;
5015let opExtentAlign = 2;
5016}
5017def J2_endloop0 : HInst<
5018(outs),
5019(ins),
5020"endloop0",
5021tc_23708a21, TypeJ> {
5022let Uses = [LC0, SA0];
5023let Defs = [LC0, P3, PC, USR];
5024let isBranch = 1;
5025let isTerminator = 1;
5026let isPseudo = 1;
5027}
5028def J2_endloop01 : HInst<
5029(outs),
5030(ins),
5031"endloop01",
5032tc_23708a21, TypeJ> {
5033let Uses = [LC0, LC1, SA0, SA1];
5034let Defs = [LC0, LC1, P3, PC, USR];
5035let isPseudo = 1;
5036}
5037def J2_endloop1 : HInst<
5038(outs),
5039(ins),
5040"endloop1",
5041tc_23708a21, TypeJ> {
5042let Uses = [LC1, SA1];
5043let Defs = [LC1, PC];
5044let isBranch = 1;
5045let isTerminator = 1;
5046let isPseudo = 1;
5047}
5048def J2_jump : HInst<
5049(outs),
5050(ins b30_2Imm:$Ii),
5051"jump $Ii",
5052tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel {
5053let Inst{0-0} = 0b0;
5054let Inst{31-25} = 0b0101100;
5055let isTerminator = 1;
5056let isBranch = 1;
5057let cofRelax2 = 1;
5058let cofMax1 = 1;
5059let Defs = [PC];
5060let BaseOpcode = "J2_jump";
5061let InputType = "imm";
5062let isBarrier = 1;
5063let isPredicable = 1;
5064let isExtendable = 1;
5065let opExtendable = 0;
5066let isExtentSigned = 1;
5067let opExtentBits = 24;
5068let opExtentAlign = 2;
5069}
5070def J2_jumpf : HInst<
5071(outs),
5072(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5073"if (!$Pu4) jump:nt $Ii",
5074tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5075let Inst{0-0} = 0b0;
5076let Inst{12-10} = 0b000;
5077let Inst{21-21} = 0b1;
5078let Inst{31-24} = 0b01011100;
5079let isPredicated = 1;
5080let isPredicatedFalse = 1;
5081let isTerminator = 1;
5082let isBranch = 1;
5083let cofRelax1 = 1;
5084let cofRelax2 = 1;
5085let cofMax1 = 1;
5086let Defs = [PC];
5087let BaseOpcode = "J2_jump";
5088let InputType = "imm";
5089let isTaken = Inst{12};
5090let isExtendable = 1;
5091let opExtendable = 1;
5092let isExtentSigned = 1;
5093let opExtentBits = 17;
5094let opExtentAlign = 2;
5095}
5096def J2_jumpf_nopred_map : HInst<
5097(outs),
5098(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5099"if (!$Pu4) jump $Ii",
5100tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5101let isPseudo = 1;
5102let isCodeGenOnly = 1;
5103}
5104def J2_jumpfnew : HInst<
5105(outs),
5106(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5107"if (!$Pu4.new) jump:nt $Ii",
5108tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5109let Inst{0-0} = 0b0;
5110let Inst{12-10} = 0b010;
5111let Inst{21-21} = 0b1;
5112let Inst{31-24} = 0b01011100;
5113let isPredicated = 1;
5114let isPredicatedFalse = 1;
5115let isTerminator = 1;
5116let isBranch = 1;
5117let isPredicatedNew = 1;
5118let cofRelax1 = 1;
5119let cofRelax2 = 1;
5120let cofMax1 = 1;
5121let Defs = [PC];
5122let BaseOpcode = "J2_jump";
5123let InputType = "imm";
5124let isTaken = Inst{12};
5125let isExtendable = 1;
5126let opExtendable = 1;
5127let isExtentSigned = 1;
5128let opExtentBits = 17;
5129let opExtentAlign = 2;
5130}
5131def J2_jumpfnewpt : HInst<
5132(outs),
5133(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5134"if (!$Pu4.new) jump:t $Ii",
5135tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5136let Inst{0-0} = 0b0;
5137let Inst{12-10} = 0b110;
5138let Inst{21-21} = 0b1;
5139let Inst{31-24} = 0b01011100;
5140let isPredicated = 1;
5141let isPredicatedFalse = 1;
5142let isTerminator = 1;
5143let isBranch = 1;
5144let isPredicatedNew = 1;
5145let cofRelax1 = 1;
5146let cofRelax2 = 1;
5147let cofMax1 = 1;
5148let Defs = [PC];
5149let BaseOpcode = "J2_jump";
5150let InputType = "imm";
5151let isTaken = Inst{12};
5152let isExtendable = 1;
5153let opExtendable = 1;
5154let isExtentSigned = 1;
5155let opExtentBits = 17;
5156let opExtentAlign = 2;
5157}
5158def J2_jumpfpt : HInst<
5159(outs),
5160(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5161"if (!$Pu4) jump:t $Ii",
5162tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5163let Inst{0-0} = 0b0;
5164let Inst{12-10} = 0b100;
5165let Inst{21-21} = 0b1;
5166let Inst{31-24} = 0b01011100;
5167let isPredicated = 1;
5168let isPredicatedFalse = 1;
5169let isTerminator = 1;
5170let isBranch = 1;
5171let cofRelax1 = 1;
5172let cofRelax2 = 1;
5173let cofMax1 = 1;
5174let Defs = [PC];
5175let BaseOpcode = "J2_jump";
5176let InputType = "imm";
5177let isTaken = Inst{12};
5178let isExtendable = 1;
5179let opExtendable = 1;
5180let isExtentSigned = 1;
5181let opExtentBits = 17;
5182let opExtentAlign = 2;
5183}
5184def J2_jumpr : HInst<
5185(outs),
5186(ins IntRegs:$Rs32),
5187"jumpr $Rs32",
5188tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel {
5189let Inst{13-0} = 0b00000000000000;
5190let Inst{31-21} = 0b01010010100;
5191let isTerminator = 1;
5192let isIndirectBranch = 1;
5193let isBranch = 1;
5194let cofMax1 = 1;
5195let Defs = [PC];
5196let BaseOpcode = "J2_jumpr";
5197let InputType = "reg";
5198let isBarrier = 1;
5199let isPredicable = 1;
5200}
5201def J2_jumprf : HInst<
5202(outs),
5203(ins PredRegs:$Pu4, IntRegs:$Rs32),
5204"if (!$Pu4) jumpr:nt $Rs32",
5205tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5206let Inst{7-0} = 0b00000000;
5207let Inst{13-10} = 0b0000;
5208let Inst{31-21} = 0b01010011011;
5209let isPredicated = 1;
5210let isPredicatedFalse = 1;
5211let isTerminator = 1;
5212let isIndirectBranch = 1;
5213let isBranch = 1;
5214let cofMax1 = 1;
5215let Defs = [PC];
5216let BaseOpcode = "J2_jumpr";
5217let InputType = "reg";
5218let isTaken = Inst{12};
5219}
5220def J2_jumprf_nopred_map : HInst<
5221(outs),
5222(ins PredRegs:$Pu4, IntRegs:$Rs32),
5223"if (!$Pu4) jumpr $Rs32",
5224tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5225let isPseudo = 1;
5226let isCodeGenOnly = 1;
5227}
5228def J2_jumprfnew : HInst<
5229(outs),
5230(ins PredRegs:$Pu4, IntRegs:$Rs32),
5231"if (!$Pu4.new) jumpr:nt $Rs32",
5232tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5233let Inst{7-0} = 0b00000000;
5234let Inst{13-10} = 0b0010;
5235let Inst{31-21} = 0b01010011011;
5236let isPredicated = 1;
5237let isPredicatedFalse = 1;
5238let isTerminator = 1;
5239let isIndirectBranch = 1;
5240let isBranch = 1;
5241let isPredicatedNew = 1;
5242let cofMax1 = 1;
5243let Defs = [PC];
5244let BaseOpcode = "J2_jumpr";
5245let InputType = "reg";
5246let isTaken = Inst{12};
5247}
5248def J2_jumprfnewpt : HInst<
5249(outs),
5250(ins PredRegs:$Pu4, IntRegs:$Rs32),
5251"if (!$Pu4.new) jumpr:t $Rs32",
5252tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5253let Inst{7-0} = 0b00000000;
5254let Inst{13-10} = 0b0110;
5255let Inst{31-21} = 0b01010011011;
5256let isPredicated = 1;
5257let isPredicatedFalse = 1;
5258let isTerminator = 1;
5259let isIndirectBranch = 1;
5260let isBranch = 1;
5261let isPredicatedNew = 1;
5262let cofMax1 = 1;
5263let Defs = [PC];
5264let BaseOpcode = "J2_jumpr";
5265let InputType = "reg";
5266let isTaken = Inst{12};
5267}
5268def J2_jumprfpt : HInst<
5269(outs),
5270(ins PredRegs:$Pu4, IntRegs:$Rs32),
5271"if (!$Pu4) jumpr:t $Rs32",
5272tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5273let Inst{7-0} = 0b00000000;
5274let Inst{13-10} = 0b0100;
5275let Inst{31-21} = 0b01010011011;
5276let isPredicated = 1;
5277let isPredicatedFalse = 1;
5278let isTerminator = 1;
5279let isIndirectBranch = 1;
5280let isBranch = 1;
5281let cofMax1 = 1;
5282let Defs = [PC];
5283let BaseOpcode = "J2_jumpr";
5284let InputType = "reg";
5285let isTaken = Inst{12};
5286}
5287def J2_jumprgtez : HInst<
5288(outs),
5289(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5290"if ($Rs32>=#0) jump:nt $Ii",
5291tc_57a55b54, TypeCR>, Enc_0fa531 {
5292let Inst{0-0} = 0b0;
5293let Inst{12-12} = 0b0;
5294let Inst{31-22} = 0b0110000101;
5295let isPredicated = 1;
5296let isTerminator = 1;
5297let isBranch = 1;
5298let isPredicatedNew = 1;
5299let cofRelax1 = 1;
5300let cofRelax2 = 1;
5301let cofMax1 = 1;
5302let Defs = [PC];
5303let isTaken = Inst{12};
5304}
5305def J2_jumprgtezpt : HInst<
5306(outs),
5307(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5308"if ($Rs32>=#0) jump:t $Ii",
5309tc_57a55b54, TypeCR>, Enc_0fa531 {
5310let Inst{0-0} = 0b0;
5311let Inst{12-12} = 0b1;
5312let Inst{31-22} = 0b0110000101;
5313let isPredicated = 1;
5314let isTerminator = 1;
5315let isBranch = 1;
5316let isPredicatedNew = 1;
5317let cofRelax1 = 1;
5318let cofRelax2 = 1;
5319let cofMax1 = 1;
5320let Defs = [PC];
5321let isTaken = Inst{12};
5322}
5323def J2_jumprh : HInst<
5324(outs),
5325(ins IntRegs:$Rs32),
5326"jumprh $Rs32",
5327tc_f97707c1, TypeJ>, Enc_ecbcc8, Requires<[HasV73]> {
5328let Inst{13-0} = 0b00000000000000;
5329let Inst{31-21} = 0b01010010110;
5330let isTerminator = 1;
5331let isIndirectBranch = 1;
5332let isBranch = 1;
5333let cofMax1 = 1;
5334let Defs = [PC];
5335}
5336def J2_jumprltez : HInst<
5337(outs),
5338(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5339"if ($Rs32<=#0) jump:nt $Ii",
5340tc_57a55b54, TypeCR>, Enc_0fa531 {
5341let Inst{0-0} = 0b0;
5342let Inst{12-12} = 0b0;
5343let Inst{31-22} = 0b0110000111;
5344let isPredicated = 1;
5345let isTerminator = 1;
5346let isBranch = 1;
5347let isPredicatedNew = 1;
5348let cofRelax1 = 1;
5349let cofRelax2 = 1;
5350let cofMax1 = 1;
5351let Defs = [PC];
5352let isTaken = Inst{12};
5353}
5354def J2_jumprltezpt : HInst<
5355(outs),
5356(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5357"if ($Rs32<=#0) jump:t $Ii",
5358tc_57a55b54, TypeCR>, Enc_0fa531 {
5359let Inst{0-0} = 0b0;
5360let Inst{12-12} = 0b1;
5361let Inst{31-22} = 0b0110000111;
5362let isPredicated = 1;
5363let isTerminator = 1;
5364let isBranch = 1;
5365let isPredicatedNew = 1;
5366let cofRelax1 = 1;
5367let cofRelax2 = 1;
5368let cofMax1 = 1;
5369let Defs = [PC];
5370let isTaken = Inst{12};
5371}
5372def J2_jumprnz : HInst<
5373(outs),
5374(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5375"if ($Rs32==#0) jump:nt $Ii",
5376tc_57a55b54, TypeCR>, Enc_0fa531 {
5377let Inst{0-0} = 0b0;
5378let Inst{12-12} = 0b0;
5379let Inst{31-22} = 0b0110000110;
5380let isPredicated = 1;
5381let isTerminator = 1;
5382let isBranch = 1;
5383let isPredicatedNew = 1;
5384let cofRelax1 = 1;
5385let cofRelax2 = 1;
5386let cofMax1 = 1;
5387let Defs = [PC];
5388let isTaken = Inst{12};
5389}
5390def J2_jumprnzpt : HInst<
5391(outs),
5392(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5393"if ($Rs32==#0) jump:t $Ii",
5394tc_57a55b54, TypeCR>, Enc_0fa531 {
5395let Inst{0-0} = 0b0;
5396let Inst{12-12} = 0b1;
5397let Inst{31-22} = 0b0110000110;
5398let isPredicated = 1;
5399let isTerminator = 1;
5400let isBranch = 1;
5401let isPredicatedNew = 1;
5402let cofRelax1 = 1;
5403let cofRelax2 = 1;
5404let cofMax1 = 1;
5405let Defs = [PC];
5406let isTaken = Inst{12};
5407}
5408def J2_jumprt : HInst<
5409(outs),
5410(ins PredRegs:$Pu4, IntRegs:$Rs32),
5411"if ($Pu4) jumpr:nt $Rs32",
5412tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5413let Inst{7-0} = 0b00000000;
5414let Inst{13-10} = 0b0000;
5415let Inst{31-21} = 0b01010011010;
5416let isPredicated = 1;
5417let isTerminator = 1;
5418let isIndirectBranch = 1;
5419let isBranch = 1;
5420let cofMax1 = 1;
5421let Defs = [PC];
5422let BaseOpcode = "J2_jumpr";
5423let InputType = "reg";
5424let isTaken = Inst{12};
5425}
5426def J2_jumprt_nopred_map : HInst<
5427(outs),
5428(ins PredRegs:$Pu4, IntRegs:$Rs32),
5429"if ($Pu4) jumpr $Rs32",
5430tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5431let isPseudo = 1;
5432let isCodeGenOnly = 1;
5433}
5434def J2_jumprtnew : HInst<
5435(outs),
5436(ins PredRegs:$Pu4, IntRegs:$Rs32),
5437"if ($Pu4.new) jumpr:nt $Rs32",
5438tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5439let Inst{7-0} = 0b00000000;
5440let Inst{13-10} = 0b0010;
5441let Inst{31-21} = 0b01010011010;
5442let isPredicated = 1;
5443let isTerminator = 1;
5444let isIndirectBranch = 1;
5445let isBranch = 1;
5446let isPredicatedNew = 1;
5447let cofMax1 = 1;
5448let Defs = [PC];
5449let BaseOpcode = "J2_jumpr";
5450let InputType = "reg";
5451let isTaken = Inst{12};
5452}
5453def J2_jumprtnewpt : HInst<
5454(outs),
5455(ins PredRegs:$Pu4, IntRegs:$Rs32),
5456"if ($Pu4.new) jumpr:t $Rs32",
5457tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5458let Inst{7-0} = 0b00000000;
5459let Inst{13-10} = 0b0110;
5460let Inst{31-21} = 0b01010011010;
5461let isPredicated = 1;
5462let isTerminator = 1;
5463let isIndirectBranch = 1;
5464let isBranch = 1;
5465let isPredicatedNew = 1;
5466let cofMax1 = 1;
5467let Defs = [PC];
5468let BaseOpcode = "J2_jumpr";
5469let InputType = "reg";
5470let isTaken = Inst{12};
5471}
5472def J2_jumprtpt : HInst<
5473(outs),
5474(ins PredRegs:$Pu4, IntRegs:$Rs32),
5475"if ($Pu4) jumpr:t $Rs32",
5476tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5477let Inst{7-0} = 0b00000000;
5478let Inst{13-10} = 0b0100;
5479let Inst{31-21} = 0b01010011010;
5480let isPredicated = 1;
5481let isTerminator = 1;
5482let isIndirectBranch = 1;
5483let isBranch = 1;
5484let cofMax1 = 1;
5485let Defs = [PC];
5486let BaseOpcode = "J2_jumpr";
5487let InputType = "reg";
5488let isTaken = Inst{12};
5489}
5490def J2_jumprz : HInst<
5491(outs),
5492(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5493"if ($Rs32!=#0) jump:nt $Ii",
5494tc_57a55b54, TypeCR>, Enc_0fa531 {
5495let Inst{0-0} = 0b0;
5496let Inst{12-12} = 0b0;
5497let Inst{31-22} = 0b0110000100;
5498let isPredicated = 1;
5499let isTerminator = 1;
5500let isBranch = 1;
5501let isPredicatedNew = 1;
5502let cofRelax1 = 1;
5503let cofRelax2 = 1;
5504let cofMax1 = 1;
5505let Defs = [PC];
5506let isTaken = Inst{12};
5507}
5508def J2_jumprzpt : HInst<
5509(outs),
5510(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5511"if ($Rs32!=#0) jump:t $Ii",
5512tc_57a55b54, TypeCR>, Enc_0fa531 {
5513let Inst{0-0} = 0b0;
5514let Inst{12-12} = 0b1;
5515let Inst{31-22} = 0b0110000100;
5516let isPredicated = 1;
5517let isTerminator = 1;
5518let isBranch = 1;
5519let isPredicatedNew = 1;
5520let cofRelax1 = 1;
5521let cofRelax2 = 1;
5522let cofMax1 = 1;
5523let Defs = [PC];
5524let isTaken = Inst{12};
5525}
5526def J2_jumpt : HInst<
5527(outs),
5528(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5529"if ($Pu4) jump:nt $Ii",
5530tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5531let Inst{0-0} = 0b0;
5532let Inst{12-10} = 0b000;
5533let Inst{21-21} = 0b0;
5534let Inst{31-24} = 0b01011100;
5535let isPredicated = 1;
5536let isTerminator = 1;
5537let isBranch = 1;
5538let cofRelax1 = 1;
5539let cofRelax2 = 1;
5540let cofMax1 = 1;
5541let Defs = [PC];
5542let BaseOpcode = "J2_jump";
5543let InputType = "imm";
5544let isTaken = Inst{12};
5545let isExtendable = 1;
5546let opExtendable = 1;
5547let isExtentSigned = 1;
5548let opExtentBits = 17;
5549let opExtentAlign = 2;
5550}
5551def J2_jumpt_nopred_map : HInst<
5552(outs),
5553(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5554"if ($Pu4) jump $Ii",
5555tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5556let isPseudo = 1;
5557let isCodeGenOnly = 1;
5558}
5559def J2_jumptnew : HInst<
5560(outs),
5561(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5562"if ($Pu4.new) jump:nt $Ii",
5563tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5564let Inst{0-0} = 0b0;
5565let Inst{12-10} = 0b010;
5566let Inst{21-21} = 0b0;
5567let Inst{31-24} = 0b01011100;
5568let isPredicated = 1;
5569let isTerminator = 1;
5570let isBranch = 1;
5571let isPredicatedNew = 1;
5572let cofRelax1 = 1;
5573let cofRelax2 = 1;
5574let cofMax1 = 1;
5575let Defs = [PC];
5576let BaseOpcode = "J2_jump";
5577let InputType = "imm";
5578let isTaken = Inst{12};
5579let isExtendable = 1;
5580let opExtendable = 1;
5581let isExtentSigned = 1;
5582let opExtentBits = 17;
5583let opExtentAlign = 2;
5584}
5585def J2_jumptnewpt : HInst<
5586(outs),
5587(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5588"if ($Pu4.new) jump:t $Ii",
5589tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5590let Inst{0-0} = 0b0;
5591let Inst{12-10} = 0b110;
5592let Inst{21-21} = 0b0;
5593let Inst{31-24} = 0b01011100;
5594let isPredicated = 1;
5595let isTerminator = 1;
5596let isBranch = 1;
5597let isPredicatedNew = 1;
5598let cofRelax1 = 1;
5599let cofRelax2 = 1;
5600let cofMax1 = 1;
5601let Defs = [PC];
5602let BaseOpcode = "J2_jump";
5603let InputType = "imm";
5604let isTaken = Inst{12};
5605let isExtendable = 1;
5606let opExtendable = 1;
5607let isExtentSigned = 1;
5608let opExtentBits = 17;
5609let opExtentAlign = 2;
5610}
5611def J2_jumptpt : HInst<
5612(outs),
5613(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5614"if ($Pu4) jump:t $Ii",
5615tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5616let Inst{0-0} = 0b0;
5617let Inst{12-10} = 0b100;
5618let Inst{21-21} = 0b0;
5619let Inst{31-24} = 0b01011100;
5620let isPredicated = 1;
5621let isTerminator = 1;
5622let isBranch = 1;
5623let cofRelax1 = 1;
5624let cofRelax2 = 1;
5625let cofMax1 = 1;
5626let Defs = [PC];
5627let BaseOpcode = "J2_jump";
5628let InputType = "imm";
5629let isTaken = Inst{12};
5630let isExtendable = 1;
5631let opExtendable = 1;
5632let isExtentSigned = 1;
5633let opExtentBits = 17;
5634let opExtentAlign = 2;
5635}
5636def J2_loop0i : HInst<
5637(outs),
5638(ins b30_2Imm:$Ii, u10_0Imm:$II),
5639"loop0($Ii,#$II)",
5640tc_1248597c, TypeCR>, Enc_4dc228 {
5641let Inst{2-2} = 0b0;
5642let Inst{13-13} = 0b0;
5643let Inst{31-21} = 0b01101001000;
5644let cofRelax1 = 1;
5645let cofRelax2 = 1;
5646let Defs = [LC0, SA0, USR];
5647let isExtendable = 1;
5648let opExtendable = 0;
5649let isExtentSigned = 1;
5650let opExtentBits = 9;
5651let opExtentAlign = 2;
5652}
5653def J2_loop0r : HInst<
5654(outs),
5655(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5656"loop0($Ii,$Rs32)",
5657tc_9406230a, TypeCR>, Enc_864a5a {
5658let Inst{2-0} = 0b000;
5659let Inst{7-5} = 0b000;
5660let Inst{13-13} = 0b0;
5661let Inst{31-21} = 0b01100000000;
5662let cofRelax1 = 1;
5663let cofRelax2 = 1;
5664let Defs = [LC0, SA0, USR];
5665let isExtendable = 1;
5666let opExtendable = 0;
5667let isExtentSigned = 1;
5668let opExtentBits = 9;
5669let opExtentAlign = 2;
5670}
5671def J2_loop1i : HInst<
5672(outs),
5673(ins b30_2Imm:$Ii, u10_0Imm:$II),
5674"loop1($Ii,#$II)",
5675tc_1248597c, TypeCR>, Enc_4dc228 {
5676let Inst{2-2} = 0b0;
5677let Inst{13-13} = 0b0;
5678let Inst{31-21} = 0b01101001001;
5679let cofRelax1 = 1;
5680let cofRelax2 = 1;
5681let Defs = [LC1, SA1];
5682let isExtendable = 1;
5683let opExtendable = 0;
5684let isExtentSigned = 1;
5685let opExtentBits = 9;
5686let opExtentAlign = 2;
5687}
5688def J2_loop1r : HInst<
5689(outs),
5690(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5691"loop1($Ii,$Rs32)",
5692tc_9406230a, TypeCR>, Enc_864a5a {
5693let Inst{2-0} = 0b000;
5694let Inst{7-5} = 0b000;
5695let Inst{13-13} = 0b0;
5696let Inst{31-21} = 0b01100000001;
5697let cofRelax1 = 1;
5698let cofRelax2 = 1;
5699let Defs = [LC1, SA1];
5700let isExtendable = 1;
5701let opExtendable = 0;
5702let isExtentSigned = 1;
5703let opExtentBits = 9;
5704let opExtentAlign = 2;
5705}
5706def J2_pause : HInst<
5707(outs),
5708(ins u10_0Imm:$Ii),
5709"pause(#$Ii)",
5710tc_d57d649c, TypeJ>, Enc_bea5da {
5711let Inst{1-0} = 0b00;
5712let Inst{7-5} = 0b000;
5713let Inst{13-13} = 0b0;
5714let Inst{31-18} = 0b01010100010000;
5715let isSolo = 1;
5716}
5717def J2_ploop1si : HInst<
5718(outs),
5719(ins b30_2Imm:$Ii, u10_0Imm:$II),
5720"p3 = sp1loop0($Ii,#$II)",
5721tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5722let Inst{2-2} = 0b0;
5723let Inst{13-13} = 0b0;
5724let Inst{31-21} = 0b01101001101;
5725let isPredicateLate = 1;
5726let cofRelax1 = 1;
5727let cofRelax2 = 1;
5728let Defs = [LC0, P3, SA0, USR];
5729let isExtendable = 1;
5730let opExtendable = 0;
5731let isExtentSigned = 1;
5732let opExtentBits = 9;
5733let opExtentAlign = 2;
5734}
5735def J2_ploop1sr : HInst<
5736(outs),
5737(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5738"p3 = sp1loop0($Ii,$Rs32)",
5739tc_6d861a95, TypeCR>, Enc_864a5a {
5740let Inst{2-0} = 0b000;
5741let Inst{7-5} = 0b000;
5742let Inst{13-13} = 0b0;
5743let Inst{31-21} = 0b01100000101;
5744let isPredicateLate = 1;
5745let cofRelax1 = 1;
5746let cofRelax2 = 1;
5747let Defs = [LC0, P3, SA0, USR];
5748let isExtendable = 1;
5749let opExtendable = 0;
5750let isExtentSigned = 1;
5751let opExtentBits = 9;
5752let opExtentAlign = 2;
5753}
5754def J2_ploop2si : HInst<
5755(outs),
5756(ins b30_2Imm:$Ii, u10_0Imm:$II),
5757"p3 = sp2loop0($Ii,#$II)",
5758tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5759let Inst{2-2} = 0b0;
5760let Inst{13-13} = 0b0;
5761let Inst{31-21} = 0b01101001110;
5762let isPredicateLate = 1;
5763let cofRelax1 = 1;
5764let cofRelax2 = 1;
5765let Defs = [LC0, P3, SA0, USR];
5766let isExtendable = 1;
5767let opExtendable = 0;
5768let isExtentSigned = 1;
5769let opExtentBits = 9;
5770let opExtentAlign = 2;
5771}
5772def J2_ploop2sr : HInst<
5773(outs),
5774(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5775"p3 = sp2loop0($Ii,$Rs32)",
5776tc_6d861a95, TypeCR>, Enc_864a5a {
5777let Inst{2-0} = 0b000;
5778let Inst{7-5} = 0b000;
5779let Inst{13-13} = 0b0;
5780let Inst{31-21} = 0b01100000110;
5781let isPredicateLate = 1;
5782let cofRelax1 = 1;
5783let cofRelax2 = 1;
5784let Defs = [LC0, P3, SA0, USR];
5785let isExtendable = 1;
5786let opExtendable = 0;
5787let isExtentSigned = 1;
5788let opExtentBits = 9;
5789let opExtentAlign = 2;
5790}
5791def J2_ploop3si : HInst<
5792(outs),
5793(ins b30_2Imm:$Ii, u10_0Imm:$II),
5794"p3 = sp3loop0($Ii,#$II)",
5795tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5796let Inst{2-2} = 0b0;
5797let Inst{13-13} = 0b0;
5798let Inst{31-21} = 0b01101001111;
5799let isPredicateLate = 1;
5800let cofRelax1 = 1;
5801let cofRelax2 = 1;
5802let Defs = [LC0, P3, SA0, USR];
5803let isExtendable = 1;
5804let opExtendable = 0;
5805let isExtentSigned = 1;
5806let opExtentBits = 9;
5807let opExtentAlign = 2;
5808}
5809def J2_ploop3sr : HInst<
5810(outs),
5811(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5812"p3 = sp3loop0($Ii,$Rs32)",
5813tc_6d861a95, TypeCR>, Enc_864a5a {
5814let Inst{2-0} = 0b000;
5815let Inst{7-5} = 0b000;
5816let Inst{13-13} = 0b0;
5817let Inst{31-21} = 0b01100000111;
5818let isPredicateLate = 1;
5819let cofRelax1 = 1;
5820let cofRelax2 = 1;
5821let Defs = [LC0, P3, SA0, USR];
5822let isExtendable = 1;
5823let opExtendable = 0;
5824let isExtentSigned = 1;
5825let opExtentBits = 9;
5826let opExtentAlign = 2;
5827}
5828def J2_trap0 : HInst<
5829(outs),
5830(ins u8_0Imm:$Ii),
5831"trap0(#$Ii)",
5832tc_45f9d1be, TypeJ>, Enc_a51a9a {
5833let Inst{1-0} = 0b00;
5834let Inst{7-5} = 0b000;
5835let Inst{13-13} = 0b0;
5836let Inst{31-16} = 0b0101010000000000;
5837let isSolo = 1;
5838let hasSideEffects = 1;
5839}
5840def J2_trap1 : HInst<
5841(outs IntRegs:$Rx32),
5842(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
5843"trap1($Rx32,#$Ii)",
5844tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> {
5845let Inst{1-0} = 0b00;
5846let Inst{7-5} = 0b000;
5847let Inst{13-13} = 0b0;
5848let Inst{31-21} = 0b01010100100;
5849let hasNewValue = 1;
5850let opNewValue = 0;
5851let isSolo = 1;
5852let Uses = [CCR, GOSP];
5853let Defs = [CCR, GOSP, PC];
5854let hasSideEffects = 1;
5855let Constraints = "$Rx32 = $Rx32in";
5856}
5857def J2_trap1_noregmap : HInst<
5858(outs),
5859(ins u8_0Imm:$Ii),
5860"trap1(#$Ii)",
5861tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> {
5862let hasSideEffects = 1;
5863let isPseudo = 1;
5864let isCodeGenOnly = 1;
5865}
5866def J2_unpause : HInst<
5867(outs),
5868(ins),
5869"unpause",
5870tc_33e7e673, TypeJ>, Enc_e3b0c4, Requires<[HasV73]> {
5871let Inst{13-0} = 0b01000000000000;
5872let Inst{31-16} = 0b0101011111100000;
5873let isSolo = 1;
5874}
5875def J4_cmpeq_f_jumpnv_nt : HInst<
5876(outs),
5877(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5878"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5879tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5880let Inst{0-0} = 0b0;
5881let Inst{13-13} = 0b0;
5882let Inst{19-19} = 0b0;
5883let Inst{31-22} = 0b0010000001;
5884let isPredicated = 1;
5885let isPredicatedFalse = 1;
5886let isTerminator = 1;
5887let isBranch = 1;
5888let isNewValue = 1;
5889let cofMax1 = 1;
5890let isRestrictNoSlot1Store = 1;
5891let Defs = [PC];
5892let BaseOpcode = "J4_cmpeqr";
5893let isTaken = Inst{13};
5894let isExtendable = 1;
5895let opExtendable = 2;
5896let isExtentSigned = 1;
5897let opExtentBits = 11;
5898let opExtentAlign = 2;
5899let opNewValue = 0;
5900}
5901def J4_cmpeq_f_jumpnv_t : HInst<
5902(outs),
5903(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5904"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5905tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5906let Inst{0-0} = 0b0;
5907let Inst{13-13} = 0b1;
5908let Inst{19-19} = 0b0;
5909let Inst{31-22} = 0b0010000001;
5910let isPredicated = 1;
5911let isPredicatedFalse = 1;
5912let isTerminator = 1;
5913let isBranch = 1;
5914let isNewValue = 1;
5915let cofMax1 = 1;
5916let isRestrictNoSlot1Store = 1;
5917let Defs = [PC];
5918let BaseOpcode = "J4_cmpeqr";
5919let isTaken = Inst{13};
5920let isExtendable = 1;
5921let opExtendable = 2;
5922let isExtentSigned = 1;
5923let opExtentBits = 11;
5924let opExtentAlign = 2;
5925let opNewValue = 0;
5926}
5927def J4_cmpeq_fp0_jump_nt : HInst<
5928(outs),
5929(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5930"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
5931tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5932let Inst{0-0} = 0b0;
5933let Inst{13-12} = 0b00;
5934let Inst{31-22} = 0b0001010001;
5935let isPredicated = 1;
5936let isPredicatedFalse = 1;
5937let isTerminator = 1;
5938let isBranch = 1;
5939let isPredicatedNew = 1;
5940let cofRelax1 = 1;
5941let cofRelax2 = 1;
5942let cofMax1 = 1;
5943let Uses = [P0];
5944let Defs = [P0, PC];
5945let BaseOpcode = "J4_cmpeqp0";
5946let isTaken = Inst{13};
5947let isExtendable = 1;
5948let opExtendable = 2;
5949let isExtentSigned = 1;
5950let opExtentBits = 11;
5951let opExtentAlign = 2;
5952}
5953def J4_cmpeq_fp0_jump_t : HInst<
5954(outs),
5955(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5956"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
5957tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5958let Inst{0-0} = 0b0;
5959let Inst{13-12} = 0b10;
5960let Inst{31-22} = 0b0001010001;
5961let isPredicated = 1;
5962let isPredicatedFalse = 1;
5963let isTerminator = 1;
5964let isBranch = 1;
5965let isPredicatedNew = 1;
5966let cofRelax1 = 1;
5967let cofRelax2 = 1;
5968let cofMax1 = 1;
5969let Uses = [P0];
5970let Defs = [P0, PC];
5971let BaseOpcode = "J4_cmpeqp0";
5972let isTaken = Inst{13};
5973let isExtendable = 1;
5974let opExtendable = 2;
5975let isExtentSigned = 1;
5976let opExtentBits = 11;
5977let opExtentAlign = 2;
5978}
5979def J4_cmpeq_fp1_jump_nt : HInst<
5980(outs),
5981(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5982"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
5983tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5984let Inst{0-0} = 0b0;
5985let Inst{13-12} = 0b01;
5986let Inst{31-22} = 0b0001010001;
5987let isPredicated = 1;
5988let isPredicatedFalse = 1;
5989let isTerminator = 1;
5990let isBranch = 1;
5991let isPredicatedNew = 1;
5992let cofRelax1 = 1;
5993let cofRelax2 = 1;
5994let cofMax1 = 1;
5995let Uses = [P1];
5996let Defs = [P1, PC];
5997let BaseOpcode = "J4_cmpeqp1";
5998let isTaken = Inst{13};
5999let isExtendable = 1;
6000let opExtendable = 2;
6001let isExtentSigned = 1;
6002let opExtentBits = 11;
6003let opExtentAlign = 2;
6004}
6005def J4_cmpeq_fp1_jump_t : HInst<
6006(outs),
6007(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6008"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6009tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6010let Inst{0-0} = 0b0;
6011let Inst{13-12} = 0b11;
6012let Inst{31-22} = 0b0001010001;
6013let isPredicated = 1;
6014let isPredicatedFalse = 1;
6015let isTerminator = 1;
6016let isBranch = 1;
6017let isPredicatedNew = 1;
6018let cofRelax1 = 1;
6019let cofRelax2 = 1;
6020let cofMax1 = 1;
6021let Uses = [P1];
6022let Defs = [P1, PC];
6023let BaseOpcode = "J4_cmpeqp1";
6024let isTaken = Inst{13};
6025let isExtendable = 1;
6026let opExtendable = 2;
6027let isExtentSigned = 1;
6028let opExtentBits = 11;
6029let opExtentAlign = 2;
6030}
6031def J4_cmpeq_t_jumpnv_nt : HInst<
6032(outs),
6033(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6034"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
6035tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6036let Inst{0-0} = 0b0;
6037let Inst{13-13} = 0b0;
6038let Inst{19-19} = 0b0;
6039let Inst{31-22} = 0b0010000000;
6040let isPredicated = 1;
6041let isTerminator = 1;
6042let isBranch = 1;
6043let isNewValue = 1;
6044let cofMax1 = 1;
6045let isRestrictNoSlot1Store = 1;
6046let Defs = [PC];
6047let BaseOpcode = "J4_cmpeqr";
6048let isTaken = Inst{13};
6049let isExtendable = 1;
6050let opExtendable = 2;
6051let isExtentSigned = 1;
6052let opExtentBits = 11;
6053let opExtentAlign = 2;
6054let opNewValue = 0;
6055}
6056def J4_cmpeq_t_jumpnv_t : HInst<
6057(outs),
6058(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6059"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
6060tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6061let Inst{0-0} = 0b0;
6062let Inst{13-13} = 0b1;
6063let Inst{19-19} = 0b0;
6064let Inst{31-22} = 0b0010000000;
6065let isPredicated = 1;
6066let isTerminator = 1;
6067let isBranch = 1;
6068let isNewValue = 1;
6069let cofMax1 = 1;
6070let isRestrictNoSlot1Store = 1;
6071let Defs = [PC];
6072let BaseOpcode = "J4_cmpeqr";
6073let isTaken = Inst{13};
6074let isExtendable = 1;
6075let opExtendable = 2;
6076let isExtentSigned = 1;
6077let opExtentBits = 11;
6078let opExtentAlign = 2;
6079let opNewValue = 0;
6080}
6081def J4_cmpeq_tp0_jump_nt : HInst<
6082(outs),
6083(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6084"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6085tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6086let Inst{0-0} = 0b0;
6087let Inst{13-12} = 0b00;
6088let Inst{31-22} = 0b0001010000;
6089let isPredicated = 1;
6090let isTerminator = 1;
6091let isBranch = 1;
6092let isPredicatedNew = 1;
6093let cofRelax1 = 1;
6094let cofRelax2 = 1;
6095let cofMax1 = 1;
6096let Uses = [P0];
6097let Defs = [P0, PC];
6098let BaseOpcode = "J4_cmpeqp0";
6099let isTaken = Inst{13};
6100let isExtendable = 1;
6101let opExtendable = 2;
6102let isExtentSigned = 1;
6103let opExtentBits = 11;
6104let opExtentAlign = 2;
6105}
6106def J4_cmpeq_tp0_jump_t : HInst<
6107(outs),
6108(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6109"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6110tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6111let Inst{0-0} = 0b0;
6112let Inst{13-12} = 0b10;
6113let Inst{31-22} = 0b0001010000;
6114let isPredicated = 1;
6115let isTerminator = 1;
6116let isBranch = 1;
6117let isPredicatedNew = 1;
6118let cofRelax1 = 1;
6119let cofRelax2 = 1;
6120let cofMax1 = 1;
6121let Uses = [P0];
6122let Defs = [P0, PC];
6123let BaseOpcode = "J4_cmpeqp0";
6124let isTaken = Inst{13};
6125let isExtendable = 1;
6126let opExtendable = 2;
6127let isExtentSigned = 1;
6128let opExtentBits = 11;
6129let opExtentAlign = 2;
6130}
6131def J4_cmpeq_tp1_jump_nt : HInst<
6132(outs),
6133(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6134"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
6135tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6136let Inst{0-0} = 0b0;
6137let Inst{13-12} = 0b01;
6138let Inst{31-22} = 0b0001010000;
6139let isPredicated = 1;
6140let isTerminator = 1;
6141let isBranch = 1;
6142let isPredicatedNew = 1;
6143let cofRelax1 = 1;
6144let cofRelax2 = 1;
6145let cofMax1 = 1;
6146let Uses = [P1];
6147let Defs = [P1, PC];
6148let BaseOpcode = "J4_cmpeqp1";
6149let isTaken = Inst{13};
6150let isExtendable = 1;
6151let opExtendable = 2;
6152let isExtentSigned = 1;
6153let opExtentBits = 11;
6154let opExtentAlign = 2;
6155}
6156def J4_cmpeq_tp1_jump_t : HInst<
6157(outs),
6158(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6159"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6160tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6161let Inst{0-0} = 0b0;
6162let Inst{13-12} = 0b11;
6163let Inst{31-22} = 0b0001010000;
6164let isPredicated = 1;
6165let isTerminator = 1;
6166let isBranch = 1;
6167let isPredicatedNew = 1;
6168let cofRelax1 = 1;
6169let cofRelax2 = 1;
6170let cofMax1 = 1;
6171let Uses = [P1];
6172let Defs = [P1, PC];
6173let BaseOpcode = "J4_cmpeqp1";
6174let isTaken = Inst{13};
6175let isExtendable = 1;
6176let opExtendable = 2;
6177let isExtentSigned = 1;
6178let opExtentBits = 11;
6179let opExtentAlign = 2;
6180}
6181def J4_cmpeqi_f_jumpnv_nt : HInst<
6182(outs),
6183(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6184"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6185tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6186let Inst{0-0} = 0b0;
6187let Inst{13-13} = 0b0;
6188let Inst{19-19} = 0b0;
6189let Inst{31-22} = 0b0010010001;
6190let isPredicated = 1;
6191let isPredicatedFalse = 1;
6192let isTerminator = 1;
6193let isBranch = 1;
6194let isNewValue = 1;
6195let cofMax1 = 1;
6196let isRestrictNoSlot1Store = 1;
6197let Defs = [PC];
6198let BaseOpcode = "J4_cmpeqi";
6199let isTaken = Inst{13};
6200let isExtendable = 1;
6201let opExtendable = 2;
6202let isExtentSigned = 1;
6203let opExtentBits = 11;
6204let opExtentAlign = 2;
6205let opNewValue = 0;
6206}
6207def J4_cmpeqi_f_jumpnv_t : HInst<
6208(outs),
6209(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6210"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6211tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6212let Inst{0-0} = 0b0;
6213let Inst{13-13} = 0b1;
6214let Inst{19-19} = 0b0;
6215let Inst{31-22} = 0b0010010001;
6216let isPredicated = 1;
6217let isPredicatedFalse = 1;
6218let isTerminator = 1;
6219let isBranch = 1;
6220let isNewValue = 1;
6221let cofMax1 = 1;
6222let isRestrictNoSlot1Store = 1;
6223let Defs = [PC];
6224let BaseOpcode = "J4_cmpeqi";
6225let isTaken = Inst{13};
6226let isExtendable = 1;
6227let opExtendable = 2;
6228let isExtentSigned = 1;
6229let opExtentBits = 11;
6230let opExtentAlign = 2;
6231let opNewValue = 0;
6232}
6233def J4_cmpeqi_fp0_jump_nt : HInst<
6234(outs),
6235(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6236"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
6237tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6238let Inst{0-0} = 0b0;
6239let Inst{13-13} = 0b0;
6240let Inst{31-22} = 0b0001000001;
6241let isPredicated = 1;
6242let isPredicatedFalse = 1;
6243let isTerminator = 1;
6244let isBranch = 1;
6245let isPredicatedNew = 1;
6246let cofRelax1 = 1;
6247let cofRelax2 = 1;
6248let cofMax1 = 1;
6249let Uses = [P0];
6250let Defs = [P0, PC];
6251let BaseOpcode = "J4_cmpeqip0";
6252let isTaken = Inst{13};
6253let isExtendable = 1;
6254let opExtendable = 2;
6255let isExtentSigned = 1;
6256let opExtentBits = 11;
6257let opExtentAlign = 2;
6258}
6259def J4_cmpeqi_fp0_jump_t : HInst<
6260(outs),
6261(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6262"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
6263tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6264let Inst{0-0} = 0b0;
6265let Inst{13-13} = 0b1;
6266let Inst{31-22} = 0b0001000001;
6267let isPredicated = 1;
6268let isPredicatedFalse = 1;
6269let isTerminator = 1;
6270let isBranch = 1;
6271let isPredicatedNew = 1;
6272let cofRelax1 = 1;
6273let cofRelax2 = 1;
6274let cofMax1 = 1;
6275let Uses = [P0];
6276let Defs = [P0, PC];
6277let BaseOpcode = "J4_cmpeqip0";
6278let isTaken = Inst{13};
6279let isExtendable = 1;
6280let opExtendable = 2;
6281let isExtentSigned = 1;
6282let opExtentBits = 11;
6283let opExtentAlign = 2;
6284}
6285def J4_cmpeqi_fp1_jump_nt : HInst<
6286(outs),
6287(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6288"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6289tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6290let Inst{0-0} = 0b0;
6291let Inst{13-13} = 0b0;
6292let Inst{31-22} = 0b0001001001;
6293let isPredicated = 1;
6294let isPredicatedFalse = 1;
6295let isTerminator = 1;
6296let isBranch = 1;
6297let isPredicatedNew = 1;
6298let cofRelax1 = 1;
6299let cofRelax2 = 1;
6300let cofMax1 = 1;
6301let Uses = [P1];
6302let Defs = [P1, PC];
6303let BaseOpcode = "J4_cmpeqip1";
6304let isTaken = Inst{13};
6305let isExtendable = 1;
6306let opExtendable = 2;
6307let isExtentSigned = 1;
6308let opExtentBits = 11;
6309let opExtentAlign = 2;
6310}
6311def J4_cmpeqi_fp1_jump_t : HInst<
6312(outs),
6313(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6314"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
6315tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6316let Inst{0-0} = 0b0;
6317let Inst{13-13} = 0b1;
6318let Inst{31-22} = 0b0001001001;
6319let isPredicated = 1;
6320let isPredicatedFalse = 1;
6321let isTerminator = 1;
6322let isBranch = 1;
6323let isPredicatedNew = 1;
6324let cofRelax1 = 1;
6325let cofRelax2 = 1;
6326let cofMax1 = 1;
6327let Uses = [P1];
6328let Defs = [P1, PC];
6329let BaseOpcode = "J4_cmpeqip1";
6330let isTaken = Inst{13};
6331let isExtendable = 1;
6332let opExtendable = 2;
6333let isExtentSigned = 1;
6334let opExtentBits = 11;
6335let opExtentAlign = 2;
6336}
6337def J4_cmpeqi_t_jumpnv_nt : HInst<
6338(outs),
6339(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6340"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6341tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6342let Inst{0-0} = 0b0;
6343let Inst{13-13} = 0b0;
6344let Inst{19-19} = 0b0;
6345let Inst{31-22} = 0b0010010000;
6346let isPredicated = 1;
6347let isTerminator = 1;
6348let isBranch = 1;
6349let isNewValue = 1;
6350let cofMax1 = 1;
6351let isRestrictNoSlot1Store = 1;
6352let Defs = [PC];
6353let BaseOpcode = "J4_cmpeqi";
6354let isTaken = Inst{13};
6355let isExtendable = 1;
6356let opExtendable = 2;
6357let isExtentSigned = 1;
6358let opExtentBits = 11;
6359let opExtentAlign = 2;
6360let opNewValue = 0;
6361}
6362def J4_cmpeqi_t_jumpnv_t : HInst<
6363(outs),
6364(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6365"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6366tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6367let Inst{0-0} = 0b0;
6368let Inst{13-13} = 0b1;
6369let Inst{19-19} = 0b0;
6370let Inst{31-22} = 0b0010010000;
6371let isPredicated = 1;
6372let isTerminator = 1;
6373let isBranch = 1;
6374let isNewValue = 1;
6375let cofMax1 = 1;
6376let isRestrictNoSlot1Store = 1;
6377let Defs = [PC];
6378let BaseOpcode = "J4_cmpeqi";
6379let isTaken = Inst{13};
6380let isExtendable = 1;
6381let opExtendable = 2;
6382let isExtentSigned = 1;
6383let opExtentBits = 11;
6384let opExtentAlign = 2;
6385let opNewValue = 0;
6386}
6387def J4_cmpeqi_tp0_jump_nt : HInst<
6388(outs),
6389(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6390"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
6391tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6392let Inst{0-0} = 0b0;
6393let Inst{13-13} = 0b0;
6394let Inst{31-22} = 0b0001000000;
6395let isPredicated = 1;
6396let isTerminator = 1;
6397let isBranch = 1;
6398let isPredicatedNew = 1;
6399let cofRelax1 = 1;
6400let cofRelax2 = 1;
6401let cofMax1 = 1;
6402let Uses = [P0];
6403let Defs = [P0, PC];
6404let BaseOpcode = "J4_cmpeqip0";
6405let isTaken = Inst{13};
6406let isExtendable = 1;
6407let opExtendable = 2;
6408let isExtentSigned = 1;
6409let opExtentBits = 11;
6410let opExtentAlign = 2;
6411}
6412def J4_cmpeqi_tp0_jump_t : HInst<
6413(outs),
6414(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6415"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
6416tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6417let Inst{0-0} = 0b0;
6418let Inst{13-13} = 0b1;
6419let Inst{31-22} = 0b0001000000;
6420let isPredicated = 1;
6421let isTerminator = 1;
6422let isBranch = 1;
6423let isPredicatedNew = 1;
6424let cofRelax1 = 1;
6425let cofRelax2 = 1;
6426let cofMax1 = 1;
6427let Uses = [P0];
6428let Defs = [P0, PC];
6429let BaseOpcode = "J4_cmpeqip0";
6430let isTaken = Inst{13};
6431let isExtendable = 1;
6432let opExtendable = 2;
6433let isExtentSigned = 1;
6434let opExtentBits = 11;
6435let opExtentAlign = 2;
6436}
6437def J4_cmpeqi_tp1_jump_nt : HInst<
6438(outs),
6439(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6440"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
6441tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6442let Inst{0-0} = 0b0;
6443let Inst{13-13} = 0b0;
6444let Inst{31-22} = 0b0001001000;
6445let isPredicated = 1;
6446let isTerminator = 1;
6447let isBranch = 1;
6448let isPredicatedNew = 1;
6449let cofRelax1 = 1;
6450let cofRelax2 = 1;
6451let cofMax1 = 1;
6452let Uses = [P1];
6453let Defs = [P1, PC];
6454let BaseOpcode = "J4_cmpeqip1";
6455let isTaken = Inst{13};
6456let isExtendable = 1;
6457let opExtendable = 2;
6458let isExtentSigned = 1;
6459let opExtentBits = 11;
6460let opExtentAlign = 2;
6461}
6462def J4_cmpeqi_tp1_jump_t : HInst<
6463(outs),
6464(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6465"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
6466tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6467let Inst{0-0} = 0b0;
6468let Inst{13-13} = 0b1;
6469let Inst{31-22} = 0b0001001000;
6470let isPredicated = 1;
6471let isTerminator = 1;
6472let isBranch = 1;
6473let isPredicatedNew = 1;
6474let cofRelax1 = 1;
6475let cofRelax2 = 1;
6476let cofMax1 = 1;
6477let Uses = [P1];
6478let Defs = [P1, PC];
6479let BaseOpcode = "J4_cmpeqip1";
6480let isTaken = Inst{13};
6481let isExtendable = 1;
6482let opExtendable = 2;
6483let isExtentSigned = 1;
6484let opExtentBits = 11;
6485let opExtentAlign = 2;
6486}
6487def J4_cmpeqn1_f_jumpnv_nt : HInst<
6488(outs),
6489(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6490"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6491tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel {
6492let Inst{0-0} = 0b0;
6493let Inst{13-8} = 0b000000;
6494let Inst{19-19} = 0b0;
6495let Inst{31-22} = 0b0010011001;
6496let isPredicated = 1;
6497let isPredicatedFalse = 1;
6498let isTerminator = 1;
6499let isBranch = 1;
6500let isNewValue = 1;
6501let cofMax1 = 1;
6502let isRestrictNoSlot1Store = 1;
6503let Defs = [PC];
6504let BaseOpcode = "J4_cmpeqn1r";
6505let isTaken = Inst{13};
6506let isExtendable = 1;
6507let opExtendable = 2;
6508let isExtentSigned = 1;
6509let opExtentBits = 11;
6510let opExtentAlign = 2;
6511let opNewValue = 0;
6512}
6513def J4_cmpeqn1_f_jumpnv_t : HInst<
6514(outs),
6515(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6516"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6517tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel {
6518let Inst{0-0} = 0b0;
6519let Inst{13-8} = 0b100000;
6520let Inst{19-19} = 0b0;
6521let Inst{31-22} = 0b0010011001;
6522let isPredicated = 1;
6523let isPredicatedFalse = 1;
6524let isTerminator = 1;
6525let isBranch = 1;
6526let isNewValue = 1;
6527let cofMax1 = 1;
6528let isRestrictNoSlot1Store = 1;
6529let Defs = [PC];
6530let BaseOpcode = "J4_cmpeqn1r";
6531let isTaken = Inst{13};
6532let isExtendable = 1;
6533let opExtendable = 2;
6534let isExtentSigned = 1;
6535let opExtentBits = 11;
6536let opExtentAlign = 2;
6537let opNewValue = 0;
6538}
6539def J4_cmpeqn1_fp0_jump_nt : HInst<
6540(outs),
6541(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6542"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
6543tc_24f426ab, TypeCJ>, Enc_1de724, PredRel {
6544let Inst{0-0} = 0b0;
6545let Inst{13-8} = 0b000000;
6546let Inst{31-22} = 0b0001000111;
6547let isPredicated = 1;
6548let isPredicatedFalse = 1;
6549let isTerminator = 1;
6550let isBranch = 1;
6551let isPredicatedNew = 1;
6552let cofRelax1 = 1;
6553let cofRelax2 = 1;
6554let cofMax1 = 1;
6555let Uses = [P0];
6556let Defs = [P0, PC];
6557let BaseOpcode = "J4_cmpeqn1p0";
6558let isTaken = Inst{13};
6559let isExtendable = 1;
6560let opExtendable = 2;
6561let isExtentSigned = 1;
6562let opExtentBits = 11;
6563let opExtentAlign = 2;
6564}
6565def J4_cmpeqn1_fp0_jump_t : HInst<
6566(outs),
6567(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6568"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
6569tc_24f426ab, TypeCJ>, Enc_14640c, PredRel {
6570let Inst{0-0} = 0b0;
6571let Inst{13-8} = 0b100000;
6572let Inst{31-22} = 0b0001000111;
6573let isPredicated = 1;
6574let isPredicatedFalse = 1;
6575let isTerminator = 1;
6576let isBranch = 1;
6577let isPredicatedNew = 1;
6578let cofRelax1 = 1;
6579let cofRelax2 = 1;
6580let cofMax1 = 1;
6581let Uses = [P0];
6582let Defs = [P0, PC];
6583let BaseOpcode = "J4_cmpeqn1p0";
6584let isTaken = Inst{13};
6585let isExtendable = 1;
6586let opExtendable = 2;
6587let isExtentSigned = 1;
6588let opExtentBits = 11;
6589let opExtentAlign = 2;
6590}
6591def J4_cmpeqn1_fp1_jump_nt : HInst<
6592(outs),
6593(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6594"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
6595tc_24f426ab, TypeCJ>, Enc_668704, PredRel {
6596let Inst{0-0} = 0b0;
6597let Inst{13-8} = 0b000000;
6598let Inst{31-22} = 0b0001001111;
6599let isPredicated = 1;
6600let isPredicatedFalse = 1;
6601let isTerminator = 1;
6602let isBranch = 1;
6603let isPredicatedNew = 1;
6604let cofRelax1 = 1;
6605let cofRelax2 = 1;
6606let cofMax1 = 1;
6607let Uses = [P1];
6608let Defs = [P1, PC];
6609let BaseOpcode = "J4_cmpeqn1p1";
6610let isTaken = Inst{13};
6611let isExtendable = 1;
6612let opExtendable = 2;
6613let isExtentSigned = 1;
6614let opExtentBits = 11;
6615let opExtentAlign = 2;
6616}
6617def J4_cmpeqn1_fp1_jump_t : HInst<
6618(outs),
6619(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6620"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
6621tc_24f426ab, TypeCJ>, Enc_800e04, PredRel {
6622let Inst{0-0} = 0b0;
6623let Inst{13-8} = 0b100000;
6624let Inst{31-22} = 0b0001001111;
6625let isPredicated = 1;
6626let isPredicatedFalse = 1;
6627let isTerminator = 1;
6628let isBranch = 1;
6629let isPredicatedNew = 1;
6630let cofRelax1 = 1;
6631let cofRelax2 = 1;
6632let cofMax1 = 1;
6633let Uses = [P1];
6634let Defs = [P1, PC];
6635let BaseOpcode = "J4_cmpeqn1p1";
6636let isTaken = Inst{13};
6637let isExtendable = 1;
6638let opExtendable = 2;
6639let isExtentSigned = 1;
6640let opExtentBits = 11;
6641let opExtentAlign = 2;
6642}
6643def J4_cmpeqn1_t_jumpnv_nt : HInst<
6644(outs),
6645(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6646"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6647tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel {
6648let Inst{0-0} = 0b0;
6649let Inst{13-8} = 0b000000;
6650let Inst{19-19} = 0b0;
6651let Inst{31-22} = 0b0010011000;
6652let isPredicated = 1;
6653let isTerminator = 1;
6654let isBranch = 1;
6655let isNewValue = 1;
6656let cofMax1 = 1;
6657let isRestrictNoSlot1Store = 1;
6658let Defs = [PC];
6659let BaseOpcode = "J4_cmpeqn1r";
6660let isTaken = Inst{13};
6661let isExtendable = 1;
6662let opExtendable = 2;
6663let isExtentSigned = 1;
6664let opExtentBits = 11;
6665let opExtentAlign = 2;
6666let opNewValue = 0;
6667}
6668def J4_cmpeqn1_t_jumpnv_t : HInst<
6669(outs),
6670(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6671"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6672tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel {
6673let Inst{0-0} = 0b0;
6674let Inst{13-8} = 0b100000;
6675let Inst{19-19} = 0b0;
6676let Inst{31-22} = 0b0010011000;
6677let isPredicated = 1;
6678let isTerminator = 1;
6679let isBranch = 1;
6680let isNewValue = 1;
6681let cofMax1 = 1;
6682let isRestrictNoSlot1Store = 1;
6683let Defs = [PC];
6684let BaseOpcode = "J4_cmpeqn1r";
6685let isTaken = Inst{13};
6686let isExtendable = 1;
6687let opExtendable = 2;
6688let isExtentSigned = 1;
6689let opExtentBits = 11;
6690let opExtentAlign = 2;
6691let opNewValue = 0;
6692}
6693def J4_cmpeqn1_tp0_jump_nt : HInst<
6694(outs),
6695(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6696"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
6697tc_24f426ab, TypeCJ>, Enc_405228, PredRel {
6698let Inst{0-0} = 0b0;
6699let Inst{13-8} = 0b000000;
6700let Inst{31-22} = 0b0001000110;
6701let isPredicated = 1;
6702let isTerminator = 1;
6703let isBranch = 1;
6704let isPredicatedNew = 1;
6705let cofRelax1 = 1;
6706let cofRelax2 = 1;
6707let cofMax1 = 1;
6708let Uses = [P0];
6709let Defs = [P0, PC];
6710let BaseOpcode = "J4_cmpeqn1p0";
6711let isTaken = Inst{13};
6712let isExtendable = 1;
6713let opExtendable = 2;
6714let isExtentSigned = 1;
6715let opExtentBits = 11;
6716let opExtentAlign = 2;
6717}
6718def J4_cmpeqn1_tp0_jump_t : HInst<
6719(outs),
6720(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6721"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
6722tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel {
6723let Inst{0-0} = 0b0;
6724let Inst{13-8} = 0b100000;
6725let Inst{31-22} = 0b0001000110;
6726let isPredicated = 1;
6727let isTerminator = 1;
6728let isBranch = 1;
6729let isPredicatedNew = 1;
6730let cofRelax1 = 1;
6731let cofRelax2 = 1;
6732let cofMax1 = 1;
6733let Uses = [P0];
6734let Defs = [P0, PC];
6735let BaseOpcode = "J4_cmpeqn1p0";
6736let isTaken = Inst{13};
6737let isExtendable = 1;
6738let opExtendable = 2;
6739let isExtentSigned = 1;
6740let opExtentBits = 11;
6741let opExtentAlign = 2;
6742}
6743def J4_cmpeqn1_tp1_jump_nt : HInst<
6744(outs),
6745(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6746"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
6747tc_24f426ab, TypeCJ>, Enc_736575, PredRel {
6748let Inst{0-0} = 0b0;
6749let Inst{13-8} = 0b000000;
6750let Inst{31-22} = 0b0001001110;
6751let isPredicated = 1;
6752let isTerminator = 1;
6753let isBranch = 1;
6754let isPredicatedNew = 1;
6755let cofRelax1 = 1;
6756let cofRelax2 = 1;
6757let cofMax1 = 1;
6758let Uses = [P1];
6759let Defs = [P1, PC];
6760let BaseOpcode = "J4_cmpeqn1p1";
6761let isTaken = Inst{13};
6762let isExtendable = 1;
6763let opExtendable = 2;
6764let isExtentSigned = 1;
6765let opExtentBits = 11;
6766let opExtentAlign = 2;
6767}
6768def J4_cmpeqn1_tp1_jump_t : HInst<
6769(outs),
6770(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6771"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
6772tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel {
6773let Inst{0-0} = 0b0;
6774let Inst{13-8} = 0b100000;
6775let Inst{31-22} = 0b0001001110;
6776let isPredicated = 1;
6777let isTerminator = 1;
6778let isBranch = 1;
6779let isPredicatedNew = 1;
6780let cofRelax1 = 1;
6781let cofRelax2 = 1;
6782let cofMax1 = 1;
6783let Uses = [P1];
6784let Defs = [P1, PC];
6785let BaseOpcode = "J4_cmpeqn1p1";
6786let isTaken = Inst{13};
6787let isExtendable = 1;
6788let opExtendable = 2;
6789let isExtentSigned = 1;
6790let opExtentBits = 11;
6791let opExtentAlign = 2;
6792}
6793def J4_cmpgt_f_jumpnv_nt : HInst<
6794(outs),
6795(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6796"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6797tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6798let Inst{0-0} = 0b0;
6799let Inst{13-13} = 0b0;
6800let Inst{19-19} = 0b0;
6801let Inst{31-22} = 0b0010000011;
6802let isPredicated = 1;
6803let isPredicatedFalse = 1;
6804let isTerminator = 1;
6805let isBranch = 1;
6806let isNewValue = 1;
6807let cofMax1 = 1;
6808let isRestrictNoSlot1Store = 1;
6809let Defs = [PC];
6810let BaseOpcode = "J4_cmpgtr";
6811let isTaken = Inst{13};
6812let isExtendable = 1;
6813let opExtendable = 2;
6814let isExtentSigned = 1;
6815let opExtentBits = 11;
6816let opExtentAlign = 2;
6817let opNewValue = 0;
6818}
6819def J4_cmpgt_f_jumpnv_t : HInst<
6820(outs),
6821(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6822"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6823tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6824let Inst{0-0} = 0b0;
6825let Inst{13-13} = 0b1;
6826let Inst{19-19} = 0b0;
6827let Inst{31-22} = 0b0010000011;
6828let isPredicated = 1;
6829let isPredicatedFalse = 1;
6830let isTerminator = 1;
6831let isBranch = 1;
6832let isNewValue = 1;
6833let cofMax1 = 1;
6834let isRestrictNoSlot1Store = 1;
6835let Defs = [PC];
6836let BaseOpcode = "J4_cmpgtr";
6837let isTaken = Inst{13};
6838let isExtendable = 1;
6839let opExtendable = 2;
6840let isExtentSigned = 1;
6841let opExtentBits = 11;
6842let opExtentAlign = 2;
6843let opNewValue = 0;
6844}
6845def J4_cmpgt_fp0_jump_nt : HInst<
6846(outs),
6847(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6848"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
6849tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6850let Inst{0-0} = 0b0;
6851let Inst{13-12} = 0b00;
6852let Inst{31-22} = 0b0001010011;
6853let isPredicated = 1;
6854let isPredicatedFalse = 1;
6855let isTerminator = 1;
6856let isBranch = 1;
6857let isPredicatedNew = 1;
6858let cofRelax1 = 1;
6859let cofRelax2 = 1;
6860let cofMax1 = 1;
6861let Uses = [P0];
6862let Defs = [P0, PC];
6863let BaseOpcode = "J4_cmpgtp0";
6864let isTaken = Inst{13};
6865let isExtendable = 1;
6866let opExtendable = 2;
6867let isExtentSigned = 1;
6868let opExtentBits = 11;
6869let opExtentAlign = 2;
6870}
6871def J4_cmpgt_fp0_jump_t : HInst<
6872(outs),
6873(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6874"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
6875tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6876let Inst{0-0} = 0b0;
6877let Inst{13-12} = 0b10;
6878let Inst{31-22} = 0b0001010011;
6879let isPredicated = 1;
6880let isPredicatedFalse = 1;
6881let isTerminator = 1;
6882let isBranch = 1;
6883let isPredicatedNew = 1;
6884let cofRelax1 = 1;
6885let cofRelax2 = 1;
6886let cofMax1 = 1;
6887let Uses = [P0];
6888let Defs = [P0, PC];
6889let BaseOpcode = "J4_cmpgtp0";
6890let isTaken = Inst{13};
6891let isExtendable = 1;
6892let opExtendable = 2;
6893let isExtentSigned = 1;
6894let opExtentBits = 11;
6895let opExtentAlign = 2;
6896}
6897def J4_cmpgt_fp1_jump_nt : HInst<
6898(outs),
6899(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6900"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
6901tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6902let Inst{0-0} = 0b0;
6903let Inst{13-12} = 0b01;
6904let Inst{31-22} = 0b0001010011;
6905let isPredicated = 1;
6906let isPredicatedFalse = 1;
6907let isTerminator = 1;
6908let isBranch = 1;
6909let isPredicatedNew = 1;
6910let cofRelax1 = 1;
6911let cofRelax2 = 1;
6912let cofMax1 = 1;
6913let Uses = [P1];
6914let Defs = [P1, PC];
6915let BaseOpcode = "J4_cmpgtp1";
6916let isTaken = Inst{13};
6917let isExtendable = 1;
6918let opExtendable = 2;
6919let isExtentSigned = 1;
6920let opExtentBits = 11;
6921let opExtentAlign = 2;
6922}
6923def J4_cmpgt_fp1_jump_t : HInst<
6924(outs),
6925(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6926"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6927tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6928let Inst{0-0} = 0b0;
6929let Inst{13-12} = 0b11;
6930let Inst{31-22} = 0b0001010011;
6931let isPredicated = 1;
6932let isPredicatedFalse = 1;
6933let isTerminator = 1;
6934let isBranch = 1;
6935let isPredicatedNew = 1;
6936let cofRelax1 = 1;
6937let cofRelax2 = 1;
6938let cofMax1 = 1;
6939let Uses = [P1];
6940let Defs = [P1, PC];
6941let BaseOpcode = "J4_cmpgtp1";
6942let isTaken = Inst{13};
6943let isExtendable = 1;
6944let opExtendable = 2;
6945let isExtentSigned = 1;
6946let opExtentBits = 11;
6947let opExtentAlign = 2;
6948}
6949def J4_cmpgt_t_jumpnv_nt : HInst<
6950(outs),
6951(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6952"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6953tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6954let Inst{0-0} = 0b0;
6955let Inst{13-13} = 0b0;
6956let Inst{19-19} = 0b0;
6957let Inst{31-22} = 0b0010000010;
6958let isPredicated = 1;
6959let isTerminator = 1;
6960let isBranch = 1;
6961let isNewValue = 1;
6962let cofMax1 = 1;
6963let isRestrictNoSlot1Store = 1;
6964let Defs = [PC];
6965let BaseOpcode = "J4_cmpgtr";
6966let isTaken = Inst{13};
6967let isExtendable = 1;
6968let opExtendable = 2;
6969let isExtentSigned = 1;
6970let opExtentBits = 11;
6971let opExtentAlign = 2;
6972let opNewValue = 0;
6973}
6974def J4_cmpgt_t_jumpnv_t : HInst<
6975(outs),
6976(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6977"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6978tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6979let Inst{0-0} = 0b0;
6980let Inst{13-13} = 0b1;
6981let Inst{19-19} = 0b0;
6982let Inst{31-22} = 0b0010000010;
6983let isPredicated = 1;
6984let isTerminator = 1;
6985let isBranch = 1;
6986let isNewValue = 1;
6987let cofMax1 = 1;
6988let isRestrictNoSlot1Store = 1;
6989let Defs = [PC];
6990let BaseOpcode = "J4_cmpgtr";
6991let isTaken = Inst{13};
6992let isExtendable = 1;
6993let opExtendable = 2;
6994let isExtentSigned = 1;
6995let opExtentBits = 11;
6996let opExtentAlign = 2;
6997let opNewValue = 0;
6998}
6999def J4_cmpgt_tp0_jump_nt : HInst<
7000(outs),
7001(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7002"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7003tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7004let Inst{0-0} = 0b0;
7005let Inst{13-12} = 0b00;
7006let Inst{31-22} = 0b0001010010;
7007let isPredicated = 1;
7008let isTerminator = 1;
7009let isBranch = 1;
7010let isPredicatedNew = 1;
7011let cofRelax1 = 1;
7012let cofRelax2 = 1;
7013let cofMax1 = 1;
7014let Uses = [P0];
7015let Defs = [P0, PC];
7016let BaseOpcode = "J4_cmpgtp0";
7017let isTaken = Inst{13};
7018let isExtendable = 1;
7019let opExtendable = 2;
7020let isExtentSigned = 1;
7021let opExtentBits = 11;
7022let opExtentAlign = 2;
7023}
7024def J4_cmpgt_tp0_jump_t : HInst<
7025(outs),
7026(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7027"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7028tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7029let Inst{0-0} = 0b0;
7030let Inst{13-12} = 0b10;
7031let Inst{31-22} = 0b0001010010;
7032let isPredicated = 1;
7033let isTerminator = 1;
7034let isBranch = 1;
7035let isPredicatedNew = 1;
7036let cofRelax1 = 1;
7037let cofRelax2 = 1;
7038let cofMax1 = 1;
7039let Uses = [P0];
7040let Defs = [P0, PC];
7041let BaseOpcode = "J4_cmpgtp0";
7042let isTaken = Inst{13};
7043let isExtendable = 1;
7044let opExtendable = 2;
7045let isExtentSigned = 1;
7046let opExtentBits = 11;
7047let opExtentAlign = 2;
7048}
7049def J4_cmpgt_tp1_jump_nt : HInst<
7050(outs),
7051(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7052"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7053tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7054let Inst{0-0} = 0b0;
7055let Inst{13-12} = 0b01;
7056let Inst{31-22} = 0b0001010010;
7057let isPredicated = 1;
7058let isTerminator = 1;
7059let isBranch = 1;
7060let isPredicatedNew = 1;
7061let cofRelax1 = 1;
7062let cofRelax2 = 1;
7063let cofMax1 = 1;
7064let Uses = [P1];
7065let Defs = [P1, PC];
7066let BaseOpcode = "J4_cmpgtp1";
7067let isTaken = Inst{13};
7068let isExtendable = 1;
7069let opExtendable = 2;
7070let isExtentSigned = 1;
7071let opExtentBits = 11;
7072let opExtentAlign = 2;
7073}
7074def J4_cmpgt_tp1_jump_t : HInst<
7075(outs),
7076(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7077"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7078tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7079let Inst{0-0} = 0b0;
7080let Inst{13-12} = 0b11;
7081let Inst{31-22} = 0b0001010010;
7082let isPredicated = 1;
7083let isTerminator = 1;
7084let isBranch = 1;
7085let isPredicatedNew = 1;
7086let cofRelax1 = 1;
7087let cofRelax2 = 1;
7088let cofMax1 = 1;
7089let Uses = [P1];
7090let Defs = [P1, PC];
7091let BaseOpcode = "J4_cmpgtp1";
7092let isTaken = Inst{13};
7093let isExtendable = 1;
7094let opExtendable = 2;
7095let isExtentSigned = 1;
7096let opExtentBits = 11;
7097let opExtentAlign = 2;
7098}
7099def J4_cmpgti_f_jumpnv_nt : HInst<
7100(outs),
7101(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7102"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7103tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7104let Inst{0-0} = 0b0;
7105let Inst{13-13} = 0b0;
7106let Inst{19-19} = 0b0;
7107let Inst{31-22} = 0b0010010011;
7108let isPredicated = 1;
7109let isPredicatedFalse = 1;
7110let isTerminator = 1;
7111let isBranch = 1;
7112let isNewValue = 1;
7113let cofMax1 = 1;
7114let isRestrictNoSlot1Store = 1;
7115let Defs = [PC];
7116let BaseOpcode = "J4_cmpgtir";
7117let isTaken = Inst{13};
7118let isExtendable = 1;
7119let opExtendable = 2;
7120let isExtentSigned = 1;
7121let opExtentBits = 11;
7122let opExtentAlign = 2;
7123let opNewValue = 0;
7124}
7125def J4_cmpgti_f_jumpnv_t : HInst<
7126(outs),
7127(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7128"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7129tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7130let Inst{0-0} = 0b0;
7131let Inst{13-13} = 0b1;
7132let Inst{19-19} = 0b0;
7133let Inst{31-22} = 0b0010010011;
7134let isPredicated = 1;
7135let isPredicatedFalse = 1;
7136let isTerminator = 1;
7137let isBranch = 1;
7138let isNewValue = 1;
7139let cofMax1 = 1;
7140let isRestrictNoSlot1Store = 1;
7141let Defs = [PC];
7142let BaseOpcode = "J4_cmpgtir";
7143let isTaken = Inst{13};
7144let isExtendable = 1;
7145let opExtendable = 2;
7146let isExtentSigned = 1;
7147let opExtentBits = 11;
7148let opExtentAlign = 2;
7149let opNewValue = 0;
7150}
7151def J4_cmpgti_fp0_jump_nt : HInst<
7152(outs),
7153(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7154"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7155tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7156let Inst{0-0} = 0b0;
7157let Inst{13-13} = 0b0;
7158let Inst{31-22} = 0b0001000011;
7159let isPredicated = 1;
7160let isPredicatedFalse = 1;
7161let isTerminator = 1;
7162let isBranch = 1;
7163let isPredicatedNew = 1;
7164let cofRelax1 = 1;
7165let cofRelax2 = 1;
7166let cofMax1 = 1;
7167let Uses = [P0];
7168let Defs = [P0, PC];
7169let BaseOpcode = "J4_cmpgtip0";
7170let isTaken = Inst{13};
7171let isExtendable = 1;
7172let opExtendable = 2;
7173let isExtentSigned = 1;
7174let opExtentBits = 11;
7175let opExtentAlign = 2;
7176}
7177def J4_cmpgti_fp0_jump_t : HInst<
7178(outs),
7179(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7180"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
7181tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7182let Inst{0-0} = 0b0;
7183let Inst{13-13} = 0b1;
7184let Inst{31-22} = 0b0001000011;
7185let isPredicated = 1;
7186let isPredicatedFalse = 1;
7187let isTerminator = 1;
7188let isBranch = 1;
7189let isPredicatedNew = 1;
7190let cofRelax1 = 1;
7191let cofRelax2 = 1;
7192let cofMax1 = 1;
7193let Uses = [P0];
7194let Defs = [P0, PC];
7195let BaseOpcode = "J4_cmpgtip0";
7196let isTaken = Inst{13};
7197let isExtendable = 1;
7198let opExtendable = 2;
7199let isExtentSigned = 1;
7200let opExtentBits = 11;
7201let opExtentAlign = 2;
7202}
7203def J4_cmpgti_fp1_jump_nt : HInst<
7204(outs),
7205(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7206"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7207tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7208let Inst{0-0} = 0b0;
7209let Inst{13-13} = 0b0;
7210let Inst{31-22} = 0b0001001011;
7211let isPredicated = 1;
7212let isPredicatedFalse = 1;
7213let isTerminator = 1;
7214let isBranch = 1;
7215let isPredicatedNew = 1;
7216let cofRelax1 = 1;
7217let cofRelax2 = 1;
7218let cofMax1 = 1;
7219let Uses = [P1];
7220let Defs = [P1, PC];
7221let BaseOpcode = "J4_cmpgtip1";
7222let isTaken = Inst{13};
7223let isExtendable = 1;
7224let opExtendable = 2;
7225let isExtentSigned = 1;
7226let opExtentBits = 11;
7227let opExtentAlign = 2;
7228}
7229def J4_cmpgti_fp1_jump_t : HInst<
7230(outs),
7231(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7232"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
7233tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7234let Inst{0-0} = 0b0;
7235let Inst{13-13} = 0b1;
7236let Inst{31-22} = 0b0001001011;
7237let isPredicated = 1;
7238let isPredicatedFalse = 1;
7239let isTerminator = 1;
7240let isBranch = 1;
7241let isPredicatedNew = 1;
7242let cofRelax1 = 1;
7243let cofRelax2 = 1;
7244let cofMax1 = 1;
7245let Uses = [P1];
7246let Defs = [P1, PC];
7247let BaseOpcode = "J4_cmpgtip1";
7248let isTaken = Inst{13};
7249let isExtendable = 1;
7250let opExtendable = 2;
7251let isExtentSigned = 1;
7252let opExtentBits = 11;
7253let opExtentAlign = 2;
7254}
7255def J4_cmpgti_t_jumpnv_nt : HInst<
7256(outs),
7257(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7258"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7259tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7260let Inst{0-0} = 0b0;
7261let Inst{13-13} = 0b0;
7262let Inst{19-19} = 0b0;
7263let Inst{31-22} = 0b0010010010;
7264let isPredicated = 1;
7265let isTerminator = 1;
7266let isBranch = 1;
7267let isNewValue = 1;
7268let cofMax1 = 1;
7269let isRestrictNoSlot1Store = 1;
7270let Defs = [PC];
7271let BaseOpcode = "J4_cmpgtir";
7272let isTaken = Inst{13};
7273let isExtendable = 1;
7274let opExtendable = 2;
7275let isExtentSigned = 1;
7276let opExtentBits = 11;
7277let opExtentAlign = 2;
7278let opNewValue = 0;
7279}
7280def J4_cmpgti_t_jumpnv_t : HInst<
7281(outs),
7282(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7283"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7284tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7285let Inst{0-0} = 0b0;
7286let Inst{13-13} = 0b1;
7287let Inst{19-19} = 0b0;
7288let Inst{31-22} = 0b0010010010;
7289let isPredicated = 1;
7290let isTerminator = 1;
7291let isBranch = 1;
7292let isNewValue = 1;
7293let cofMax1 = 1;
7294let isRestrictNoSlot1Store = 1;
7295let Defs = [PC];
7296let BaseOpcode = "J4_cmpgtir";
7297let isTaken = Inst{13};
7298let isExtendable = 1;
7299let opExtendable = 2;
7300let isExtentSigned = 1;
7301let opExtentBits = 11;
7302let opExtentAlign = 2;
7303let opNewValue = 0;
7304}
7305def J4_cmpgti_tp0_jump_nt : HInst<
7306(outs),
7307(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7308"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
7309tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7310let Inst{0-0} = 0b0;
7311let Inst{13-13} = 0b0;
7312let Inst{31-22} = 0b0001000010;
7313let isPredicated = 1;
7314let isTerminator = 1;
7315let isBranch = 1;
7316let isPredicatedNew = 1;
7317let cofRelax1 = 1;
7318let cofRelax2 = 1;
7319let cofMax1 = 1;
7320let Uses = [P0];
7321let Defs = [P0, PC];
7322let BaseOpcode = "J4_cmpgtip0";
7323let isTaken = Inst{13};
7324let isExtendable = 1;
7325let opExtendable = 2;
7326let isExtentSigned = 1;
7327let opExtentBits = 11;
7328let opExtentAlign = 2;
7329}
7330def J4_cmpgti_tp0_jump_t : HInst<
7331(outs),
7332(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7333"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
7334tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7335let Inst{0-0} = 0b0;
7336let Inst{13-13} = 0b1;
7337let Inst{31-22} = 0b0001000010;
7338let isPredicated = 1;
7339let isTerminator = 1;
7340let isBranch = 1;
7341let isPredicatedNew = 1;
7342let cofRelax1 = 1;
7343let cofRelax2 = 1;
7344let cofMax1 = 1;
7345let Uses = [P0];
7346let Defs = [P0, PC];
7347let BaseOpcode = "J4_cmpgtip0";
7348let isTaken = Inst{13};
7349let isExtendable = 1;
7350let opExtendable = 2;
7351let isExtentSigned = 1;
7352let opExtentBits = 11;
7353let opExtentAlign = 2;
7354}
7355def J4_cmpgti_tp1_jump_nt : HInst<
7356(outs),
7357(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7358"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
7359tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7360let Inst{0-0} = 0b0;
7361let Inst{13-13} = 0b0;
7362let Inst{31-22} = 0b0001001010;
7363let isPredicated = 1;
7364let isTerminator = 1;
7365let isBranch = 1;
7366let isPredicatedNew = 1;
7367let cofRelax1 = 1;
7368let cofRelax2 = 1;
7369let cofMax1 = 1;
7370let Uses = [P1];
7371let Defs = [P1, PC];
7372let BaseOpcode = "J4_cmpgtip1";
7373let isTaken = Inst{13};
7374let isExtendable = 1;
7375let opExtendable = 2;
7376let isExtentSigned = 1;
7377let opExtentBits = 11;
7378let opExtentAlign = 2;
7379}
7380def J4_cmpgti_tp1_jump_t : HInst<
7381(outs),
7382(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7383"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
7384tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7385let Inst{0-0} = 0b0;
7386let Inst{13-13} = 0b1;
7387let Inst{31-22} = 0b0001001010;
7388let isPredicated = 1;
7389let isTerminator = 1;
7390let isBranch = 1;
7391let isPredicatedNew = 1;
7392let cofRelax1 = 1;
7393let cofRelax2 = 1;
7394let cofMax1 = 1;
7395let Uses = [P1];
7396let Defs = [P1, PC];
7397let BaseOpcode = "J4_cmpgtip1";
7398let isTaken = Inst{13};
7399let isExtendable = 1;
7400let opExtendable = 2;
7401let isExtentSigned = 1;
7402let opExtentBits = 11;
7403let opExtentAlign = 2;
7404}
7405def J4_cmpgtn1_f_jumpnv_nt : HInst<
7406(outs),
7407(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7408"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7409tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel {
7410let Inst{0-0} = 0b0;
7411let Inst{13-8} = 0b000000;
7412let Inst{19-19} = 0b0;
7413let Inst{31-22} = 0b0010011011;
7414let isPredicated = 1;
7415let isPredicatedFalse = 1;
7416let isTerminator = 1;
7417let isBranch = 1;
7418let isNewValue = 1;
7419let cofMax1 = 1;
7420let isRestrictNoSlot1Store = 1;
7421let Defs = [PC];
7422let BaseOpcode = "J4_cmpgtn1r";
7423let isTaken = Inst{13};
7424let isExtendable = 1;
7425let opExtendable = 2;
7426let isExtentSigned = 1;
7427let opExtentBits = 11;
7428let opExtentAlign = 2;
7429let opNewValue = 0;
7430}
7431def J4_cmpgtn1_f_jumpnv_t : HInst<
7432(outs),
7433(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7434"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7435tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel {
7436let Inst{0-0} = 0b0;
7437let Inst{13-8} = 0b100000;
7438let Inst{19-19} = 0b0;
7439let Inst{31-22} = 0b0010011011;
7440let isPredicated = 1;
7441let isPredicatedFalse = 1;
7442let isTerminator = 1;
7443let isBranch = 1;
7444let isNewValue = 1;
7445let cofMax1 = 1;
7446let isRestrictNoSlot1Store = 1;
7447let Defs = [PC];
7448let BaseOpcode = "J4_cmpgtn1r";
7449let isTaken = Inst{13};
7450let isExtendable = 1;
7451let opExtendable = 2;
7452let isExtentSigned = 1;
7453let opExtentBits = 11;
7454let opExtentAlign = 2;
7455let opNewValue = 0;
7456}
7457def J4_cmpgtn1_fp0_jump_nt : HInst<
7458(outs),
7459(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7460"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
7461tc_24f426ab, TypeCJ>, Enc_a42857, PredRel {
7462let Inst{0-0} = 0b0;
7463let Inst{13-8} = 0b000001;
7464let Inst{31-22} = 0b0001000111;
7465let isPredicated = 1;
7466let isPredicatedFalse = 1;
7467let isTerminator = 1;
7468let isBranch = 1;
7469let isPredicatedNew = 1;
7470let cofRelax1 = 1;
7471let cofRelax2 = 1;
7472let cofMax1 = 1;
7473let Uses = [P0];
7474let Defs = [P0, PC];
7475let BaseOpcode = "J4_cmpgtn1p0";
7476let isTaken = Inst{13};
7477let isExtendable = 1;
7478let opExtendable = 2;
7479let isExtentSigned = 1;
7480let opExtentBits = 11;
7481let opExtentAlign = 2;
7482}
7483def J4_cmpgtn1_fp0_jump_t : HInst<
7484(outs),
7485(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7486"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
7487tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel {
7488let Inst{0-0} = 0b0;
7489let Inst{13-8} = 0b100001;
7490let Inst{31-22} = 0b0001000111;
7491let isPredicated = 1;
7492let isPredicatedFalse = 1;
7493let isTerminator = 1;
7494let isBranch = 1;
7495let isPredicatedNew = 1;
7496let cofRelax1 = 1;
7497let cofRelax2 = 1;
7498let cofMax1 = 1;
7499let Uses = [P0];
7500let Defs = [P0, PC];
7501let BaseOpcode = "J4_cmpgtn1p0";
7502let isTaken = Inst{13};
7503let isExtendable = 1;
7504let opExtendable = 2;
7505let isExtentSigned = 1;
7506let opExtentBits = 11;
7507let opExtentAlign = 2;
7508}
7509def J4_cmpgtn1_fp1_jump_nt : HInst<
7510(outs),
7511(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7512"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
7513tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel {
7514let Inst{0-0} = 0b0;
7515let Inst{13-8} = 0b000001;
7516let Inst{31-22} = 0b0001001111;
7517let isPredicated = 1;
7518let isPredicatedFalse = 1;
7519let isTerminator = 1;
7520let isBranch = 1;
7521let isPredicatedNew = 1;
7522let cofRelax1 = 1;
7523let cofRelax2 = 1;
7524let cofMax1 = 1;
7525let Uses = [P1];
7526let Defs = [P1, PC];
7527let BaseOpcode = "J4_cmpgtn1p1";
7528let isTaken = Inst{13};
7529let isExtendable = 1;
7530let opExtendable = 2;
7531let isExtentSigned = 1;
7532let opExtentBits = 11;
7533let opExtentAlign = 2;
7534}
7535def J4_cmpgtn1_fp1_jump_t : HInst<
7536(outs),
7537(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7538"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
7539tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel {
7540let Inst{0-0} = 0b0;
7541let Inst{13-8} = 0b100001;
7542let Inst{31-22} = 0b0001001111;
7543let isPredicated = 1;
7544let isPredicatedFalse = 1;
7545let isTerminator = 1;
7546let isBranch = 1;
7547let isPredicatedNew = 1;
7548let cofRelax1 = 1;
7549let cofRelax2 = 1;
7550let cofMax1 = 1;
7551let Uses = [P1];
7552let Defs = [P1, PC];
7553let BaseOpcode = "J4_cmpgtn1p1";
7554let isTaken = Inst{13};
7555let isExtendable = 1;
7556let opExtendable = 2;
7557let isExtentSigned = 1;
7558let opExtentBits = 11;
7559let opExtentAlign = 2;
7560}
7561def J4_cmpgtn1_t_jumpnv_nt : HInst<
7562(outs),
7563(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7564"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7565tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel {
7566let Inst{0-0} = 0b0;
7567let Inst{13-8} = 0b000000;
7568let Inst{19-19} = 0b0;
7569let Inst{31-22} = 0b0010011010;
7570let isPredicated = 1;
7571let isTerminator = 1;
7572let isBranch = 1;
7573let isNewValue = 1;
7574let cofMax1 = 1;
7575let isRestrictNoSlot1Store = 1;
7576let Defs = [PC];
7577let BaseOpcode = "J4_cmpgtn1r";
7578let isTaken = Inst{13};
7579let isExtendable = 1;
7580let opExtendable = 2;
7581let isExtentSigned = 1;
7582let opExtentBits = 11;
7583let opExtentAlign = 2;
7584let opNewValue = 0;
7585}
7586def J4_cmpgtn1_t_jumpnv_t : HInst<
7587(outs),
7588(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7589"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7590tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel {
7591let Inst{0-0} = 0b0;
7592let Inst{13-8} = 0b100000;
7593let Inst{19-19} = 0b0;
7594let Inst{31-22} = 0b0010011010;
7595let isPredicated = 1;
7596let isTerminator = 1;
7597let isBranch = 1;
7598let isNewValue = 1;
7599let cofMax1 = 1;
7600let isRestrictNoSlot1Store = 1;
7601let Defs = [PC];
7602let BaseOpcode = "J4_cmpgtn1r";
7603let isTaken = Inst{13};
7604let isExtendable = 1;
7605let opExtendable = 2;
7606let isExtentSigned = 1;
7607let opExtentBits = 11;
7608let opExtentAlign = 2;
7609let opNewValue = 0;
7610}
7611def J4_cmpgtn1_tp0_jump_nt : HInst<
7612(outs),
7613(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7614"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
7615tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel {
7616let Inst{0-0} = 0b0;
7617let Inst{13-8} = 0b000001;
7618let Inst{31-22} = 0b0001000110;
7619let isPredicated = 1;
7620let isTerminator = 1;
7621let isBranch = 1;
7622let isPredicatedNew = 1;
7623let cofRelax1 = 1;
7624let cofRelax2 = 1;
7625let cofMax1 = 1;
7626let Uses = [P0];
7627let Defs = [P0, PC];
7628let BaseOpcode = "J4_cmpgtn1p0";
7629let isTaken = Inst{13};
7630let isExtendable = 1;
7631let opExtendable = 2;
7632let isExtentSigned = 1;
7633let opExtentBits = 11;
7634let opExtentAlign = 2;
7635}
7636def J4_cmpgtn1_tp0_jump_t : HInst<
7637(outs),
7638(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7639"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
7640tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel {
7641let Inst{0-0} = 0b0;
7642let Inst{13-8} = 0b100001;
7643let Inst{31-22} = 0b0001000110;
7644let isPredicated = 1;
7645let isTerminator = 1;
7646let isBranch = 1;
7647let isPredicatedNew = 1;
7648let cofRelax1 = 1;
7649let cofRelax2 = 1;
7650let cofMax1 = 1;
7651let Uses = [P0];
7652let Defs = [P0, PC];
7653let BaseOpcode = "J4_cmpgtn1p0";
7654let isTaken = Inst{13};
7655let isExtendable = 1;
7656let opExtendable = 2;
7657let isExtentSigned = 1;
7658let opExtentBits = 11;
7659let opExtentAlign = 2;
7660}
7661def J4_cmpgtn1_tp1_jump_nt : HInst<
7662(outs),
7663(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7664"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
7665tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel {
7666let Inst{0-0} = 0b0;
7667let Inst{13-8} = 0b000001;
7668let Inst{31-22} = 0b0001001110;
7669let isPredicated = 1;
7670let isTerminator = 1;
7671let isBranch = 1;
7672let isPredicatedNew = 1;
7673let cofRelax1 = 1;
7674let cofRelax2 = 1;
7675let cofMax1 = 1;
7676let Uses = [P1];
7677let Defs = [P1, PC];
7678let BaseOpcode = "J4_cmpgtn1p1";
7679let isTaken = Inst{13};
7680let isExtendable = 1;
7681let opExtendable = 2;
7682let isExtentSigned = 1;
7683let opExtentBits = 11;
7684let opExtentAlign = 2;
7685}
7686def J4_cmpgtn1_tp1_jump_t : HInst<
7687(outs),
7688(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7689"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
7690tc_24f426ab, TypeCJ>, Enc_178717, PredRel {
7691let Inst{0-0} = 0b0;
7692let Inst{13-8} = 0b100001;
7693let Inst{31-22} = 0b0001001110;
7694let isPredicated = 1;
7695let isTerminator = 1;
7696let isBranch = 1;
7697let isPredicatedNew = 1;
7698let cofRelax1 = 1;
7699let cofRelax2 = 1;
7700let cofMax1 = 1;
7701let Uses = [P1];
7702let Defs = [P1, PC];
7703let BaseOpcode = "J4_cmpgtn1p1";
7704let isTaken = Inst{13};
7705let isExtendable = 1;
7706let opExtendable = 2;
7707let isExtentSigned = 1;
7708let opExtentBits = 11;
7709let opExtentAlign = 2;
7710}
7711def J4_cmpgtu_f_jumpnv_nt : HInst<
7712(outs),
7713(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7714"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7715tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7716let Inst{0-0} = 0b0;
7717let Inst{13-13} = 0b0;
7718let Inst{19-19} = 0b0;
7719let Inst{31-22} = 0b0010000101;
7720let isPredicated = 1;
7721let isPredicatedFalse = 1;
7722let isTerminator = 1;
7723let isBranch = 1;
7724let isNewValue = 1;
7725let cofMax1 = 1;
7726let isRestrictNoSlot1Store = 1;
7727let Defs = [PC];
7728let BaseOpcode = "J4_cmpgtur";
7729let isTaken = Inst{13};
7730let isExtendable = 1;
7731let opExtendable = 2;
7732let isExtentSigned = 1;
7733let opExtentBits = 11;
7734let opExtentAlign = 2;
7735let opNewValue = 0;
7736}
7737def J4_cmpgtu_f_jumpnv_t : HInst<
7738(outs),
7739(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7740"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7741tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7742let Inst{0-0} = 0b0;
7743let Inst{13-13} = 0b1;
7744let Inst{19-19} = 0b0;
7745let Inst{31-22} = 0b0010000101;
7746let isPredicated = 1;
7747let isPredicatedFalse = 1;
7748let isTerminator = 1;
7749let isBranch = 1;
7750let isNewValue = 1;
7751let cofMax1 = 1;
7752let isRestrictNoSlot1Store = 1;
7753let Defs = [PC];
7754let BaseOpcode = "J4_cmpgtur";
7755let isTaken = Inst{13};
7756let isExtendable = 1;
7757let opExtendable = 2;
7758let isExtentSigned = 1;
7759let opExtentBits = 11;
7760let opExtentAlign = 2;
7761let opNewValue = 0;
7762}
7763def J4_cmpgtu_fp0_jump_nt : HInst<
7764(outs),
7765(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7766"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
7767tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7768let Inst{0-0} = 0b0;
7769let Inst{13-12} = 0b00;
7770let Inst{31-22} = 0b0001010101;
7771let isPredicated = 1;
7772let isPredicatedFalse = 1;
7773let isTerminator = 1;
7774let isBranch = 1;
7775let isPredicatedNew = 1;
7776let cofRelax1 = 1;
7777let cofRelax2 = 1;
7778let cofMax1 = 1;
7779let Uses = [P0];
7780let Defs = [P0, PC];
7781let BaseOpcode = "J4_cmpgtup0";
7782let isTaken = Inst{13};
7783let isExtendable = 1;
7784let opExtendable = 2;
7785let isExtentSigned = 1;
7786let opExtentBits = 11;
7787let opExtentAlign = 2;
7788}
7789def J4_cmpgtu_fp0_jump_t : HInst<
7790(outs),
7791(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7792"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
7793tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7794let Inst{0-0} = 0b0;
7795let Inst{13-12} = 0b10;
7796let Inst{31-22} = 0b0001010101;
7797let isPredicated = 1;
7798let isPredicatedFalse = 1;
7799let isTerminator = 1;
7800let isBranch = 1;
7801let isPredicatedNew = 1;
7802let cofRelax1 = 1;
7803let cofRelax2 = 1;
7804let cofMax1 = 1;
7805let Uses = [P0];
7806let Defs = [P0, PC];
7807let BaseOpcode = "J4_cmpgtup0";
7808let isTaken = Inst{13};
7809let isExtendable = 1;
7810let opExtendable = 2;
7811let isExtentSigned = 1;
7812let opExtentBits = 11;
7813let opExtentAlign = 2;
7814}
7815def J4_cmpgtu_fp1_jump_nt : HInst<
7816(outs),
7817(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7818"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
7819tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7820let Inst{0-0} = 0b0;
7821let Inst{13-12} = 0b01;
7822let Inst{31-22} = 0b0001010101;
7823let isPredicated = 1;
7824let isPredicatedFalse = 1;
7825let isTerminator = 1;
7826let isBranch = 1;
7827let isPredicatedNew = 1;
7828let cofRelax1 = 1;
7829let cofRelax2 = 1;
7830let cofMax1 = 1;
7831let Uses = [P1];
7832let Defs = [P1, PC];
7833let BaseOpcode = "J4_cmpgtup1";
7834let isTaken = Inst{13};
7835let isExtendable = 1;
7836let opExtendable = 2;
7837let isExtentSigned = 1;
7838let opExtentBits = 11;
7839let opExtentAlign = 2;
7840}
7841def J4_cmpgtu_fp1_jump_t : HInst<
7842(outs),
7843(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7844"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
7845tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7846let Inst{0-0} = 0b0;
7847let Inst{13-12} = 0b11;
7848let Inst{31-22} = 0b0001010101;
7849let isPredicated = 1;
7850let isPredicatedFalse = 1;
7851let isTerminator = 1;
7852let isBranch = 1;
7853let isPredicatedNew = 1;
7854let cofRelax1 = 1;
7855let cofRelax2 = 1;
7856let cofMax1 = 1;
7857let Uses = [P1];
7858let Defs = [P1, PC];
7859let BaseOpcode = "J4_cmpgtup1";
7860let isTaken = Inst{13};
7861let isExtendable = 1;
7862let opExtendable = 2;
7863let isExtentSigned = 1;
7864let opExtentBits = 11;
7865let opExtentAlign = 2;
7866}
7867def J4_cmpgtu_t_jumpnv_nt : HInst<
7868(outs),
7869(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7870"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7871tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7872let Inst{0-0} = 0b0;
7873let Inst{13-13} = 0b0;
7874let Inst{19-19} = 0b0;
7875let Inst{31-22} = 0b0010000100;
7876let isPredicated = 1;
7877let isTerminator = 1;
7878let isBranch = 1;
7879let isNewValue = 1;
7880let cofMax1 = 1;
7881let isRestrictNoSlot1Store = 1;
7882let Defs = [PC];
7883let BaseOpcode = "J4_cmpgtur";
7884let isTaken = Inst{13};
7885let isExtendable = 1;
7886let opExtendable = 2;
7887let isExtentSigned = 1;
7888let opExtentBits = 11;
7889let opExtentAlign = 2;
7890let opNewValue = 0;
7891}
7892def J4_cmpgtu_t_jumpnv_t : HInst<
7893(outs),
7894(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7895"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7896tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7897let Inst{0-0} = 0b0;
7898let Inst{13-13} = 0b1;
7899let Inst{19-19} = 0b0;
7900let Inst{31-22} = 0b0010000100;
7901let isPredicated = 1;
7902let isTerminator = 1;
7903let isBranch = 1;
7904let isNewValue = 1;
7905let cofMax1 = 1;
7906let isRestrictNoSlot1Store = 1;
7907let Defs = [PC];
7908let BaseOpcode = "J4_cmpgtur";
7909let isTaken = Inst{13};
7910let isExtendable = 1;
7911let opExtendable = 2;
7912let isExtentSigned = 1;
7913let opExtentBits = 11;
7914let opExtentAlign = 2;
7915let opNewValue = 0;
7916}
7917def J4_cmpgtu_tp0_jump_nt : HInst<
7918(outs),
7919(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7920"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7921tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7922let Inst{0-0} = 0b0;
7923let Inst{13-12} = 0b00;
7924let Inst{31-22} = 0b0001010100;
7925let isPredicated = 1;
7926let isTerminator = 1;
7927let isBranch = 1;
7928let isPredicatedNew = 1;
7929let cofRelax1 = 1;
7930let cofRelax2 = 1;
7931let cofMax1 = 1;
7932let Uses = [P0];
7933let Defs = [P0, PC];
7934let BaseOpcode = "J4_cmpgtup0";
7935let isTaken = Inst{13};
7936let isExtendable = 1;
7937let opExtendable = 2;
7938let isExtentSigned = 1;
7939let opExtentBits = 11;
7940let opExtentAlign = 2;
7941}
7942def J4_cmpgtu_tp0_jump_t : HInst<
7943(outs),
7944(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7945"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7946tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7947let Inst{0-0} = 0b0;
7948let Inst{13-12} = 0b10;
7949let Inst{31-22} = 0b0001010100;
7950let isPredicated = 1;
7951let isTerminator = 1;
7952let isBranch = 1;
7953let isPredicatedNew = 1;
7954let cofRelax1 = 1;
7955let cofRelax2 = 1;
7956let cofMax1 = 1;
7957let Uses = [P0];
7958let Defs = [P0, PC];
7959let BaseOpcode = "J4_cmpgtup0";
7960let isTaken = Inst{13};
7961let isExtendable = 1;
7962let opExtendable = 2;
7963let isExtentSigned = 1;
7964let opExtentBits = 11;
7965let opExtentAlign = 2;
7966}
7967def J4_cmpgtu_tp1_jump_nt : HInst<
7968(outs),
7969(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7970"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7971tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7972let Inst{0-0} = 0b0;
7973let Inst{13-12} = 0b01;
7974let Inst{31-22} = 0b0001010100;
7975let isPredicated = 1;
7976let isTerminator = 1;
7977let isBranch = 1;
7978let isPredicatedNew = 1;
7979let cofRelax1 = 1;
7980let cofRelax2 = 1;
7981let cofMax1 = 1;
7982let Uses = [P1];
7983let Defs = [P1, PC];
7984let BaseOpcode = "J4_cmpgtup1";
7985let isTaken = Inst{13};
7986let isExtendable = 1;
7987let opExtendable = 2;
7988let isExtentSigned = 1;
7989let opExtentBits = 11;
7990let opExtentAlign = 2;
7991}
7992def J4_cmpgtu_tp1_jump_t : HInst<
7993(outs),
7994(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7995"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7996tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7997let Inst{0-0} = 0b0;
7998let Inst{13-12} = 0b11;
7999let Inst{31-22} = 0b0001010100;
8000let isPredicated = 1;
8001let isTerminator = 1;
8002let isBranch = 1;
8003let isPredicatedNew = 1;
8004let cofRelax1 = 1;
8005let cofRelax2 = 1;
8006let cofMax1 = 1;
8007let Uses = [P1];
8008let Defs = [P1, PC];
8009let BaseOpcode = "J4_cmpgtup1";
8010let isTaken = Inst{13};
8011let isExtendable = 1;
8012let opExtendable = 2;
8013let isExtentSigned = 1;
8014let opExtentBits = 11;
8015let opExtentAlign = 2;
8016}
8017def J4_cmpgtui_f_jumpnv_nt : HInst<
8018(outs),
8019(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8020"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8021tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8022let Inst{0-0} = 0b0;
8023let Inst{13-13} = 0b0;
8024let Inst{19-19} = 0b0;
8025let Inst{31-22} = 0b0010010101;
8026let isPredicated = 1;
8027let isPredicatedFalse = 1;
8028let isTerminator = 1;
8029let isBranch = 1;
8030let isNewValue = 1;
8031let cofMax1 = 1;
8032let isRestrictNoSlot1Store = 1;
8033let Defs = [PC];
8034let BaseOpcode = "J4_cmpgtuir";
8035let isTaken = Inst{13};
8036let isExtendable = 1;
8037let opExtendable = 2;
8038let isExtentSigned = 1;
8039let opExtentBits = 11;
8040let opExtentAlign = 2;
8041let opNewValue = 0;
8042}
8043def J4_cmpgtui_f_jumpnv_t : HInst<
8044(outs),
8045(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8046"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8047tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8048let Inst{0-0} = 0b0;
8049let Inst{13-13} = 0b1;
8050let Inst{19-19} = 0b0;
8051let Inst{31-22} = 0b0010010101;
8052let isPredicated = 1;
8053let isPredicatedFalse = 1;
8054let isTerminator = 1;
8055let isBranch = 1;
8056let isNewValue = 1;
8057let cofMax1 = 1;
8058let isRestrictNoSlot1Store = 1;
8059let Defs = [PC];
8060let BaseOpcode = "J4_cmpgtuir";
8061let isTaken = Inst{13};
8062let isExtendable = 1;
8063let opExtendable = 2;
8064let isExtentSigned = 1;
8065let opExtentBits = 11;
8066let opExtentAlign = 2;
8067let opNewValue = 0;
8068}
8069def J4_cmpgtui_fp0_jump_nt : HInst<
8070(outs),
8071(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8072"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
8073tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8074let Inst{0-0} = 0b0;
8075let Inst{13-13} = 0b0;
8076let Inst{31-22} = 0b0001000101;
8077let isPredicated = 1;
8078let isPredicatedFalse = 1;
8079let isTerminator = 1;
8080let isBranch = 1;
8081let isPredicatedNew = 1;
8082let cofRelax1 = 1;
8083let cofRelax2 = 1;
8084let cofMax1 = 1;
8085let Uses = [P0];
8086let Defs = [P0, PC];
8087let BaseOpcode = "J4_cmpgtuip0";
8088let isTaken = Inst{13};
8089let isExtendable = 1;
8090let opExtendable = 2;
8091let isExtentSigned = 1;
8092let opExtentBits = 11;
8093let opExtentAlign = 2;
8094}
8095def J4_cmpgtui_fp0_jump_t : HInst<
8096(outs),
8097(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8098"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
8099tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8100let Inst{0-0} = 0b0;
8101let Inst{13-13} = 0b1;
8102let Inst{31-22} = 0b0001000101;
8103let isPredicated = 1;
8104let isPredicatedFalse = 1;
8105let isTerminator = 1;
8106let isBranch = 1;
8107let isPredicatedNew = 1;
8108let cofRelax1 = 1;
8109let cofRelax2 = 1;
8110let cofMax1 = 1;
8111let Uses = [P0];
8112let Defs = [P0, PC];
8113let BaseOpcode = "J4_cmpgtuip0";
8114let isTaken = Inst{13};
8115let isExtendable = 1;
8116let opExtendable = 2;
8117let isExtentSigned = 1;
8118let opExtentBits = 11;
8119let opExtentAlign = 2;
8120}
8121def J4_cmpgtui_fp1_jump_nt : HInst<
8122(outs),
8123(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8124"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
8125tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8126let Inst{0-0} = 0b0;
8127let Inst{13-13} = 0b0;
8128let Inst{31-22} = 0b0001001101;
8129let isPredicated = 1;
8130let isPredicatedFalse = 1;
8131let isTerminator = 1;
8132let isBranch = 1;
8133let isPredicatedNew = 1;
8134let cofRelax1 = 1;
8135let cofRelax2 = 1;
8136let cofMax1 = 1;
8137let Uses = [P1];
8138let Defs = [P1, PC];
8139let BaseOpcode = "J4_cmpgtuip1";
8140let isTaken = Inst{13};
8141let isExtendable = 1;
8142let opExtendable = 2;
8143let isExtentSigned = 1;
8144let opExtentBits = 11;
8145let opExtentAlign = 2;
8146}
8147def J4_cmpgtui_fp1_jump_t : HInst<
8148(outs),
8149(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8150"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
8151tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8152let Inst{0-0} = 0b0;
8153let Inst{13-13} = 0b1;
8154let Inst{31-22} = 0b0001001101;
8155let isPredicated = 1;
8156let isPredicatedFalse = 1;
8157let isTerminator = 1;
8158let isBranch = 1;
8159let isPredicatedNew = 1;
8160let cofRelax1 = 1;
8161let cofRelax2 = 1;
8162let cofMax1 = 1;
8163let Uses = [P1];
8164let Defs = [P1, PC];
8165let BaseOpcode = "J4_cmpgtuip1";
8166let isTaken = Inst{13};
8167let isExtendable = 1;
8168let opExtendable = 2;
8169let isExtentSigned = 1;
8170let opExtentBits = 11;
8171let opExtentAlign = 2;
8172}
8173def J4_cmpgtui_t_jumpnv_nt : HInst<
8174(outs),
8175(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8176"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8177tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8178let Inst{0-0} = 0b0;
8179let Inst{13-13} = 0b0;
8180let Inst{19-19} = 0b0;
8181let Inst{31-22} = 0b0010010100;
8182let isPredicated = 1;
8183let isTerminator = 1;
8184let isBranch = 1;
8185let isNewValue = 1;
8186let cofMax1 = 1;
8187let isRestrictNoSlot1Store = 1;
8188let Defs = [PC];
8189let BaseOpcode = "J4_cmpgtuir";
8190let isTaken = Inst{13};
8191let isExtendable = 1;
8192let opExtendable = 2;
8193let isExtentSigned = 1;
8194let opExtentBits = 11;
8195let opExtentAlign = 2;
8196let opNewValue = 0;
8197}
8198def J4_cmpgtui_t_jumpnv_t : HInst<
8199(outs),
8200(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8201"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8202tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8203let Inst{0-0} = 0b0;
8204let Inst{13-13} = 0b1;
8205let Inst{19-19} = 0b0;
8206let Inst{31-22} = 0b0010010100;
8207let isPredicated = 1;
8208let isTerminator = 1;
8209let isBranch = 1;
8210let isNewValue = 1;
8211let cofMax1 = 1;
8212let isRestrictNoSlot1Store = 1;
8213let Defs = [PC];
8214let BaseOpcode = "J4_cmpgtuir";
8215let isTaken = Inst{13};
8216let isExtendable = 1;
8217let opExtendable = 2;
8218let isExtentSigned = 1;
8219let opExtentBits = 11;
8220let opExtentAlign = 2;
8221let opNewValue = 0;
8222}
8223def J4_cmpgtui_tp0_jump_nt : HInst<
8224(outs),
8225(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8226"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
8227tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8228let Inst{0-0} = 0b0;
8229let Inst{13-13} = 0b0;
8230let Inst{31-22} = 0b0001000100;
8231let isPredicated = 1;
8232let isTerminator = 1;
8233let isBranch = 1;
8234let isPredicatedNew = 1;
8235let cofRelax1 = 1;
8236let cofRelax2 = 1;
8237let cofMax1 = 1;
8238let Uses = [P0];
8239let Defs = [P0, PC];
8240let BaseOpcode = "J4_cmpgtuip0";
8241let isTaken = Inst{13};
8242let isExtendable = 1;
8243let opExtendable = 2;
8244let isExtentSigned = 1;
8245let opExtentBits = 11;
8246let opExtentAlign = 2;
8247}
8248def J4_cmpgtui_tp0_jump_t : HInst<
8249(outs),
8250(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8251"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
8252tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8253let Inst{0-0} = 0b0;
8254let Inst{13-13} = 0b1;
8255let Inst{31-22} = 0b0001000100;
8256let isPredicated = 1;
8257let isTerminator = 1;
8258let isBranch = 1;
8259let isPredicatedNew = 1;
8260let cofRelax1 = 1;
8261let cofRelax2 = 1;
8262let cofMax1 = 1;
8263let Uses = [P0];
8264let Defs = [P0, PC];
8265let BaseOpcode = "J4_cmpgtuip0";
8266let isTaken = Inst{13};
8267let isExtendable = 1;
8268let opExtendable = 2;
8269let isExtentSigned = 1;
8270let opExtentBits = 11;
8271let opExtentAlign = 2;
8272}
8273def J4_cmpgtui_tp1_jump_nt : HInst<
8274(outs),
8275(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8276"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
8277tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8278let Inst{0-0} = 0b0;
8279let Inst{13-13} = 0b0;
8280let Inst{31-22} = 0b0001001100;
8281let isPredicated = 1;
8282let isTerminator = 1;
8283let isBranch = 1;
8284let isPredicatedNew = 1;
8285let cofRelax1 = 1;
8286let cofRelax2 = 1;
8287let cofMax1 = 1;
8288let Uses = [P1];
8289let Defs = [P1, PC];
8290let BaseOpcode = "J4_cmpgtuip1";
8291let isTaken = Inst{13};
8292let isExtendable = 1;
8293let opExtendable = 2;
8294let isExtentSigned = 1;
8295let opExtentBits = 11;
8296let opExtentAlign = 2;
8297}
8298def J4_cmpgtui_tp1_jump_t : HInst<
8299(outs),
8300(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8301"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
8302tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8303let Inst{0-0} = 0b0;
8304let Inst{13-13} = 0b1;
8305let Inst{31-22} = 0b0001001100;
8306let isPredicated = 1;
8307let isTerminator = 1;
8308let isBranch = 1;
8309let isPredicatedNew = 1;
8310let cofRelax1 = 1;
8311let cofRelax2 = 1;
8312let cofMax1 = 1;
8313let Uses = [P1];
8314let Defs = [P1, PC];
8315let BaseOpcode = "J4_cmpgtuip1";
8316let isTaken = Inst{13};
8317let isExtendable = 1;
8318let opExtendable = 2;
8319let isExtentSigned = 1;
8320let opExtentBits = 11;
8321let opExtentAlign = 2;
8322}
8323def J4_cmplt_f_jumpnv_nt : HInst<
8324(outs),
8325(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8326"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8327tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8328let Inst{0-0} = 0b0;
8329let Inst{13-13} = 0b0;
8330let Inst{19-19} = 0b0;
8331let Inst{31-22} = 0b0010000111;
8332let isPredicated = 1;
8333let isPredicatedFalse = 1;
8334let isTerminator = 1;
8335let isBranch = 1;
8336let isNewValue = 1;
8337let cofMax1 = 1;
8338let isRestrictNoSlot1Store = 1;
8339let Defs = [PC];
8340let BaseOpcode = "J4_cmpltr";
8341let isTaken = Inst{13};
8342let isExtendable = 1;
8343let opExtendable = 2;
8344let isExtentSigned = 1;
8345let opExtentBits = 11;
8346let opExtentAlign = 2;
8347let opNewValue = 1;
8348}
8349def J4_cmplt_f_jumpnv_t : HInst<
8350(outs),
8351(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8352"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8353tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8354let Inst{0-0} = 0b0;
8355let Inst{13-13} = 0b1;
8356let Inst{19-19} = 0b0;
8357let Inst{31-22} = 0b0010000111;
8358let isPredicated = 1;
8359let isPredicatedFalse = 1;
8360let isTerminator = 1;
8361let isBranch = 1;
8362let isNewValue = 1;
8363let cofMax1 = 1;
8364let isRestrictNoSlot1Store = 1;
8365let Defs = [PC];
8366let BaseOpcode = "J4_cmpltr";
8367let isTaken = Inst{13};
8368let isExtendable = 1;
8369let opExtendable = 2;
8370let isExtentSigned = 1;
8371let opExtentBits = 11;
8372let opExtentAlign = 2;
8373let opNewValue = 1;
8374}
8375def J4_cmplt_t_jumpnv_nt : HInst<
8376(outs),
8377(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8378"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8379tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8380let Inst{0-0} = 0b0;
8381let Inst{13-13} = 0b0;
8382let Inst{19-19} = 0b0;
8383let Inst{31-22} = 0b0010000110;
8384let isPredicated = 1;
8385let isTerminator = 1;
8386let isBranch = 1;
8387let isNewValue = 1;
8388let cofMax1 = 1;
8389let isRestrictNoSlot1Store = 1;
8390let Defs = [PC];
8391let BaseOpcode = "J4_cmpltr";
8392let isTaken = Inst{13};
8393let isExtendable = 1;
8394let opExtendable = 2;
8395let isExtentSigned = 1;
8396let opExtentBits = 11;
8397let opExtentAlign = 2;
8398let opNewValue = 1;
8399}
8400def J4_cmplt_t_jumpnv_t : HInst<
8401(outs),
8402(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8403"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8404tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8405let Inst{0-0} = 0b0;
8406let Inst{13-13} = 0b1;
8407let Inst{19-19} = 0b0;
8408let Inst{31-22} = 0b0010000110;
8409let isPredicated = 1;
8410let isTerminator = 1;
8411let isBranch = 1;
8412let isNewValue = 1;
8413let cofMax1 = 1;
8414let isRestrictNoSlot1Store = 1;
8415let Defs = [PC];
8416let BaseOpcode = "J4_cmpltr";
8417let isTaken = Inst{13};
8418let isExtendable = 1;
8419let opExtendable = 2;
8420let isExtentSigned = 1;
8421let opExtentBits = 11;
8422let opExtentAlign = 2;
8423let opNewValue = 1;
8424}
8425def J4_cmpltu_f_jumpnv_nt : HInst<
8426(outs),
8427(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8428"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8429tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8430let Inst{0-0} = 0b0;
8431let Inst{13-13} = 0b0;
8432let Inst{19-19} = 0b0;
8433let Inst{31-22} = 0b0010001001;
8434let isPredicated = 1;
8435let isPredicatedFalse = 1;
8436let isTerminator = 1;
8437let isBranch = 1;
8438let isNewValue = 1;
8439let cofMax1 = 1;
8440let isRestrictNoSlot1Store = 1;
8441let Defs = [PC];
8442let BaseOpcode = "J4_cmpltur";
8443let isTaken = Inst{13};
8444let isExtendable = 1;
8445let opExtendable = 2;
8446let isExtentSigned = 1;
8447let opExtentBits = 11;
8448let opExtentAlign = 2;
8449let opNewValue = 1;
8450}
8451def J4_cmpltu_f_jumpnv_t : HInst<
8452(outs),
8453(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8454"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8455tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8456let Inst{0-0} = 0b0;
8457let Inst{13-13} = 0b1;
8458let Inst{19-19} = 0b0;
8459let Inst{31-22} = 0b0010001001;
8460let isPredicated = 1;
8461let isPredicatedFalse = 1;
8462let isTerminator = 1;
8463let isBranch = 1;
8464let isNewValue = 1;
8465let cofMax1 = 1;
8466let isRestrictNoSlot1Store = 1;
8467let Defs = [PC];
8468let BaseOpcode = "J4_cmpltur";
8469let isTaken = Inst{13};
8470let isExtendable = 1;
8471let opExtendable = 2;
8472let isExtentSigned = 1;
8473let opExtentBits = 11;
8474let opExtentAlign = 2;
8475let opNewValue = 1;
8476}
8477def J4_cmpltu_t_jumpnv_nt : HInst<
8478(outs),
8479(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8480"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8481tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8482let Inst{0-0} = 0b0;
8483let Inst{13-13} = 0b0;
8484let Inst{19-19} = 0b0;
8485let Inst{31-22} = 0b0010001000;
8486let isPredicated = 1;
8487let isTerminator = 1;
8488let isBranch = 1;
8489let isNewValue = 1;
8490let cofMax1 = 1;
8491let isRestrictNoSlot1Store = 1;
8492let Defs = [PC];
8493let BaseOpcode = "J4_cmpltur";
8494let isTaken = Inst{13};
8495let isExtendable = 1;
8496let opExtendable = 2;
8497let isExtentSigned = 1;
8498let opExtentBits = 11;
8499let opExtentAlign = 2;
8500let opNewValue = 1;
8501}
8502def J4_cmpltu_t_jumpnv_t : HInst<
8503(outs),
8504(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8505"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8506tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8507let Inst{0-0} = 0b0;
8508let Inst{13-13} = 0b1;
8509let Inst{19-19} = 0b0;
8510let Inst{31-22} = 0b0010001000;
8511let isPredicated = 1;
8512let isTerminator = 1;
8513let isBranch = 1;
8514let isNewValue = 1;
8515let cofMax1 = 1;
8516let isRestrictNoSlot1Store = 1;
8517let Defs = [PC];
8518let BaseOpcode = "J4_cmpltur";
8519let isTaken = Inst{13};
8520let isExtendable = 1;
8521let opExtendable = 2;
8522let isExtentSigned = 1;
8523let opExtentBits = 11;
8524let opExtentAlign = 2;
8525let opNewValue = 1;
8526}
8527def J4_hintjumpr : HInst<
8528(outs),
8529(ins IntRegs:$Rs32),
8530"hintjr($Rs32)",
8531tc_e60def48, TypeJ>, Enc_ecbcc8 {
8532let Inst{13-0} = 0b00000000000000;
8533let Inst{31-21} = 0b01010010101;
8534let isTerminator = 1;
8535let isIndirectBranch = 1;
8536let isBranch = 1;
8537let cofRelax1 = 1;
8538let cofRelax2 = 1;
8539let cofMax1 = 1;
8540}
8541def J4_jumpseti : HInst<
8542(outs GeneralSubRegs:$Rd16),
8543(ins u6_0Imm:$II, b30_2Imm:$Ii),
8544"$Rd16 = #$II ; jump $Ii",
8545tc_5502c366, TypeCJ>, Enc_9e4c3f {
8546let Inst{0-0} = 0b0;
8547let Inst{31-22} = 0b0001011000;
8548let hasNewValue = 1;
8549let opNewValue = 0;
8550let isTerminator = 1;
8551let isBranch = 1;
8552let cofRelax2 = 1;
8553let cofMax1 = 1;
8554let Defs = [PC];
8555let isExtendable = 1;
8556let opExtendable = 2;
8557let isExtentSigned = 1;
8558let opExtentBits = 11;
8559let opExtentAlign = 2;
8560}
8561def J4_jumpsetr : HInst<
8562(outs GeneralSubRegs:$Rd16),
8563(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8564"$Rd16 = $Rs16 ; jump $Ii",
8565tc_5502c366, TypeCJ>, Enc_66bce1 {
8566let Inst{0-0} = 0b0;
8567let Inst{13-12} = 0b00;
8568let Inst{31-22} = 0b0001011100;
8569let hasNewValue = 1;
8570let opNewValue = 0;
8571let isTerminator = 1;
8572let isBranch = 1;
8573let cofRelax2 = 1;
8574let cofMax1 = 1;
8575let Defs = [PC];
8576let isExtendable = 1;
8577let opExtendable = 2;
8578let isExtentSigned = 1;
8579let opExtentBits = 11;
8580let opExtentAlign = 2;
8581}
8582def J4_tstbit0_f_jumpnv_nt : HInst<
8583(outs),
8584(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8585"if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
8586tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8587let Inst{0-0} = 0b0;
8588let Inst{13-8} = 0b000000;
8589let Inst{19-19} = 0b0;
8590let Inst{31-22} = 0b0010010111;
8591let isPredicated = 1;
8592let isPredicatedFalse = 1;
8593let isTerminator = 1;
8594let isBranch = 1;
8595let isNewValue = 1;
8596let cofMax1 = 1;
8597let isRestrictNoSlot1Store = 1;
8598let Defs = [PC];
8599let isTaken = Inst{13};
8600let isExtendable = 1;
8601let opExtendable = 1;
8602let isExtentSigned = 1;
8603let opExtentBits = 11;
8604let opExtentAlign = 2;
8605let opNewValue = 0;
8606}
8607def J4_tstbit0_f_jumpnv_t : HInst<
8608(outs),
8609(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8610"if (!tstbit($Ns8.new,#0)) jump:t $Ii",
8611tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8612let Inst{0-0} = 0b0;
8613let Inst{13-8} = 0b100000;
8614let Inst{19-19} = 0b0;
8615let Inst{31-22} = 0b0010010111;
8616let isPredicated = 1;
8617let isPredicatedFalse = 1;
8618let isTerminator = 1;
8619let isBranch = 1;
8620let isNewValue = 1;
8621let cofMax1 = 1;
8622let isRestrictNoSlot1Store = 1;
8623let Defs = [PC];
8624let isTaken = Inst{13};
8625let isExtendable = 1;
8626let opExtendable = 1;
8627let isExtentSigned = 1;
8628let opExtentBits = 11;
8629let opExtentAlign = 2;
8630let opNewValue = 0;
8631}
8632def J4_tstbit0_fp0_jump_nt : HInst<
8633(outs),
8634(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8635"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
8636tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8637let Inst{0-0} = 0b0;
8638let Inst{13-8} = 0b000011;
8639let Inst{31-22} = 0b0001000111;
8640let isPredicated = 1;
8641let isPredicatedFalse = 1;
8642let isTerminator = 1;
8643let isBranch = 1;
8644let isPredicatedNew = 1;
8645let cofRelax1 = 1;
8646let cofRelax2 = 1;
8647let cofMax1 = 1;
8648let Uses = [P0];
8649let Defs = [P0, PC];
8650let isTaken = Inst{13};
8651let isExtendable = 1;
8652let opExtendable = 1;
8653let isExtentSigned = 1;
8654let opExtentBits = 11;
8655let opExtentAlign = 2;
8656}
8657def J4_tstbit0_fp0_jump_t : HInst<
8658(outs),
8659(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8660"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
8661tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8662let Inst{0-0} = 0b0;
8663let Inst{13-8} = 0b100011;
8664let Inst{31-22} = 0b0001000111;
8665let isPredicated = 1;
8666let isPredicatedFalse = 1;
8667let isTerminator = 1;
8668let isBranch = 1;
8669let isPredicatedNew = 1;
8670let cofRelax1 = 1;
8671let cofRelax2 = 1;
8672let cofMax1 = 1;
8673let Uses = [P0];
8674let Defs = [P0, PC];
8675let isTaken = Inst{13};
8676let isExtendable = 1;
8677let opExtendable = 1;
8678let isExtentSigned = 1;
8679let opExtentBits = 11;
8680let opExtentAlign = 2;
8681}
8682def J4_tstbit0_fp1_jump_nt : HInst<
8683(outs),
8684(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8685"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
8686tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8687let Inst{0-0} = 0b0;
8688let Inst{13-8} = 0b000011;
8689let Inst{31-22} = 0b0001001111;
8690let isPredicated = 1;
8691let isPredicatedFalse = 1;
8692let isTerminator = 1;
8693let isBranch = 1;
8694let isPredicatedNew = 1;
8695let cofRelax1 = 1;
8696let cofRelax2 = 1;
8697let cofMax1 = 1;
8698let Uses = [P1];
8699let Defs = [P1, PC];
8700let isTaken = Inst{13};
8701let isExtendable = 1;
8702let opExtendable = 1;
8703let isExtentSigned = 1;
8704let opExtentBits = 11;
8705let opExtentAlign = 2;
8706}
8707def J4_tstbit0_fp1_jump_t : HInst<
8708(outs),
8709(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8710"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
8711tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8712let Inst{0-0} = 0b0;
8713let Inst{13-8} = 0b100011;
8714let Inst{31-22} = 0b0001001111;
8715let isPredicated = 1;
8716let isPredicatedFalse = 1;
8717let isTerminator = 1;
8718let isBranch = 1;
8719let isPredicatedNew = 1;
8720let cofRelax1 = 1;
8721let cofRelax2 = 1;
8722let cofMax1 = 1;
8723let Uses = [P1];
8724let Defs = [P1, PC];
8725let isTaken = Inst{13};
8726let isExtendable = 1;
8727let opExtendable = 1;
8728let isExtentSigned = 1;
8729let opExtentBits = 11;
8730let opExtentAlign = 2;
8731}
8732def J4_tstbit0_t_jumpnv_nt : HInst<
8733(outs),
8734(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8735"if (tstbit($Ns8.new,#0)) jump:nt $Ii",
8736tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8737let Inst{0-0} = 0b0;
8738let Inst{13-8} = 0b000000;
8739let Inst{19-19} = 0b0;
8740let Inst{31-22} = 0b0010010110;
8741let isPredicated = 1;
8742let isTerminator = 1;
8743let isBranch = 1;
8744let isNewValue = 1;
8745let cofMax1 = 1;
8746let isRestrictNoSlot1Store = 1;
8747let Defs = [PC];
8748let isTaken = Inst{13};
8749let isExtendable = 1;
8750let opExtendable = 1;
8751let isExtentSigned = 1;
8752let opExtentBits = 11;
8753let opExtentAlign = 2;
8754let opNewValue = 0;
8755}
8756def J4_tstbit0_t_jumpnv_t : HInst<
8757(outs),
8758(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8759"if (tstbit($Ns8.new,#0)) jump:t $Ii",
8760tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8761let Inst{0-0} = 0b0;
8762let Inst{13-8} = 0b100000;
8763let Inst{19-19} = 0b0;
8764let Inst{31-22} = 0b0010010110;
8765let isPredicated = 1;
8766let isTerminator = 1;
8767let isBranch = 1;
8768let isNewValue = 1;
8769let cofMax1 = 1;
8770let isRestrictNoSlot1Store = 1;
8771let Defs = [PC];
8772let isTaken = Inst{13};
8773let isExtendable = 1;
8774let opExtendable = 1;
8775let isExtentSigned = 1;
8776let opExtentBits = 11;
8777let opExtentAlign = 2;
8778let opNewValue = 0;
8779}
8780def J4_tstbit0_tp0_jump_nt : HInst<
8781(outs),
8782(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8783"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
8784tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8785let Inst{0-0} = 0b0;
8786let Inst{13-8} = 0b000011;
8787let Inst{31-22} = 0b0001000110;
8788let isPredicated = 1;
8789let isTerminator = 1;
8790let isBranch = 1;
8791let isPredicatedNew = 1;
8792let cofRelax1 = 1;
8793let cofRelax2 = 1;
8794let cofMax1 = 1;
8795let Uses = [P0];
8796let Defs = [P0, PC];
8797let isTaken = Inst{13};
8798let isExtendable = 1;
8799let opExtendable = 1;
8800let isExtentSigned = 1;
8801let opExtentBits = 11;
8802let opExtentAlign = 2;
8803}
8804def J4_tstbit0_tp0_jump_t : HInst<
8805(outs),
8806(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8807"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
8808tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8809let Inst{0-0} = 0b0;
8810let Inst{13-8} = 0b100011;
8811let Inst{31-22} = 0b0001000110;
8812let isPredicated = 1;
8813let isTerminator = 1;
8814let isBranch = 1;
8815let isPredicatedNew = 1;
8816let cofRelax1 = 1;
8817let cofRelax2 = 1;
8818let cofMax1 = 1;
8819let Uses = [P0];
8820let Defs = [P0, PC];
8821let isTaken = Inst{13};
8822let isExtendable = 1;
8823let opExtendable = 1;
8824let isExtentSigned = 1;
8825let opExtentBits = 11;
8826let opExtentAlign = 2;
8827}
8828def J4_tstbit0_tp1_jump_nt : HInst<
8829(outs),
8830(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8831"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
8832tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8833let Inst{0-0} = 0b0;
8834let Inst{13-8} = 0b000011;
8835let Inst{31-22} = 0b0001001110;
8836let isPredicated = 1;
8837let isTerminator = 1;
8838let isBranch = 1;
8839let isPredicatedNew = 1;
8840let cofRelax1 = 1;
8841let cofRelax2 = 1;
8842let cofMax1 = 1;
8843let Uses = [P1];
8844let Defs = [P1, PC];
8845let isTaken = Inst{13};
8846let isExtendable = 1;
8847let opExtendable = 1;
8848let isExtentSigned = 1;
8849let opExtentBits = 11;
8850let opExtentAlign = 2;
8851}
8852def J4_tstbit0_tp1_jump_t : HInst<
8853(outs),
8854(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8855"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
8856tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8857let Inst{0-0} = 0b0;
8858let Inst{13-8} = 0b100011;
8859let Inst{31-22} = 0b0001001110;
8860let isPredicated = 1;
8861let isTerminator = 1;
8862let isBranch = 1;
8863let isPredicatedNew = 1;
8864let cofRelax1 = 1;
8865let cofRelax2 = 1;
8866let cofMax1 = 1;
8867let Uses = [P1];
8868let Defs = [P1, PC];
8869let isTaken = Inst{13};
8870let isExtendable = 1;
8871let opExtendable = 1;
8872let isExtentSigned = 1;
8873let opExtentBits = 11;
8874let opExtentAlign = 2;
8875}
8876def L2_deallocframe : HInst<
8877(outs DoubleRegs:$Rdd32),
8878(ins IntRegs:$Rs32),
8879"$Rdd32 = deallocframe($Rs32):raw",
8880tc_e9170fb7, TypeLD>, Enc_3a3d62 {
8881let Inst{13-5} = 0b000000000;
8882let Inst{31-21} = 0b10010000000;
8883let accessSize = DoubleWordAccess;
8884let mayLoad = 1;
8885let Uses = [FRAMEKEY];
8886let Defs = [R29];
8887}
8888def L2_loadalignb_io : HInst<
8889(outs DoubleRegs:$Ryy32),
8890(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
8891"$Ryy32 = memb_fifo($Rs32+#$Ii)",
8892tc_fedb7e19, TypeLD>, Enc_a27588 {
8893let Inst{24-21} = 0b0100;
8894let Inst{31-27} = 0b10010;
8895let addrMode = BaseImmOffset;
8896let accessSize = ByteAccess;
8897let mayLoad = 1;
8898let isExtendable = 1;
8899let opExtendable = 3;
8900let isExtentSigned = 1;
8901let opExtentBits = 11;
8902let opExtentAlign = 0;
8903let Constraints = "$Ryy32 = $Ryy32in";
8904}
8905def L2_loadalignb_pbr : HInst<
8906(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8907(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8908"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
8909tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8910let Inst{12-5} = 0b00000000;
8911let Inst{31-21} = 0b10011110100;
8912let addrMode = PostInc;
8913let accessSize = ByteAccess;
8914let mayLoad = 1;
8915let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8916}
8917def L2_loadalignb_pci : HInst<
8918(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8919(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
8920"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
8921tc_76bb5435, TypeLD>, Enc_74aef2 {
8922let Inst{12-9} = 0b0000;
8923let Inst{31-21} = 0b10011000100;
8924let addrMode = PostInc;
8925let accessSize = ByteAccess;
8926let mayLoad = 1;
8927let Uses = [CS];
8928let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8929}
8930def L2_loadalignb_pcr : HInst<
8931(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8932(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8933"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
8934tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8935let Inst{12-5} = 0b00010000;
8936let Inst{31-21} = 0b10011000100;
8937let addrMode = PostInc;
8938let accessSize = ByteAccess;
8939let mayLoad = 1;
8940let Uses = [CS];
8941let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8942}
8943def L2_loadalignb_pi : HInst<
8944(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8945(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
8946"$Ryy32 = memb_fifo($Rx32++#$Ii)",
8947tc_1c7522a8, TypeLD>, Enc_6b197f {
8948let Inst{13-9} = 0b00000;
8949let Inst{31-21} = 0b10011010100;
8950let addrMode = PostInc;
8951let accessSize = ByteAccess;
8952let mayLoad = 1;
8953let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8954}
8955def L2_loadalignb_pr : HInst<
8956(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8957(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8958"$Ryy32 = memb_fifo($Rx32++$Mu2)",
8959tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8960let Inst{12-5} = 0b00000000;
8961let Inst{31-21} = 0b10011100100;
8962let addrMode = PostInc;
8963let accessSize = ByteAccess;
8964let mayLoad = 1;
8965let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8966}
8967def L2_loadalignb_zomap : HInst<
8968(outs DoubleRegs:$Ryy32),
8969(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8970"$Ryy32 = memb_fifo($Rs32)",
8971tc_fedb7e19, TypeMAPPING> {
8972let isPseudo = 1;
8973let isCodeGenOnly = 1;
8974let Constraints = "$Ryy32 = $Ryy32in";
8975}
8976def L2_loadalignh_io : HInst<
8977(outs DoubleRegs:$Ryy32),
8978(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
8979"$Ryy32 = memh_fifo($Rs32+#$Ii)",
8980tc_fedb7e19, TypeLD>, Enc_5cd7e9 {
8981let Inst{24-21} = 0b0010;
8982let Inst{31-27} = 0b10010;
8983let addrMode = BaseImmOffset;
8984let accessSize = HalfWordAccess;
8985let mayLoad = 1;
8986let isExtendable = 1;
8987let opExtendable = 3;
8988let isExtentSigned = 1;
8989let opExtentBits = 12;
8990let opExtentAlign = 1;
8991let Constraints = "$Ryy32 = $Ryy32in";
8992}
8993def L2_loadalignh_pbr : HInst<
8994(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8995(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8996"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
8997tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8998let Inst{12-5} = 0b00000000;
8999let Inst{31-21} = 0b10011110010;
9000let addrMode = PostInc;
9001let accessSize = HalfWordAccess;
9002let mayLoad = 1;
9003let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9004}
9005def L2_loadalignh_pci : HInst<
9006(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9007(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9008"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
9009tc_76bb5435, TypeLD>, Enc_9e2e1c {
9010let Inst{12-9} = 0b0000;
9011let Inst{31-21} = 0b10011000010;
9012let addrMode = PostInc;
9013let accessSize = HalfWordAccess;
9014let mayLoad = 1;
9015let Uses = [CS];
9016let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9017}
9018def L2_loadalignh_pcr : HInst<
9019(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9020(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9021"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
9022tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9023let Inst{12-5} = 0b00010000;
9024let Inst{31-21} = 0b10011000010;
9025let addrMode = PostInc;
9026let accessSize = HalfWordAccess;
9027let mayLoad = 1;
9028let Uses = [CS];
9029let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9030}
9031def L2_loadalignh_pi : HInst<
9032(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9033(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
9034"$Ryy32 = memh_fifo($Rx32++#$Ii)",
9035tc_1c7522a8, TypeLD>, Enc_bd1cbc {
9036let Inst{13-9} = 0b00000;
9037let Inst{31-21} = 0b10011010010;
9038let addrMode = PostInc;
9039let accessSize = HalfWordAccess;
9040let mayLoad = 1;
9041let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9042}
9043def L2_loadalignh_pr : HInst<
9044(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9045(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9046"$Ryy32 = memh_fifo($Rx32++$Mu2)",
9047tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9048let Inst{12-5} = 0b00000000;
9049let Inst{31-21} = 0b10011100010;
9050let addrMode = PostInc;
9051let accessSize = HalfWordAccess;
9052let mayLoad = 1;
9053let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9054}
9055def L2_loadalignh_zomap : HInst<
9056(outs DoubleRegs:$Ryy32),
9057(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
9058"$Ryy32 = memh_fifo($Rs32)",
9059tc_fedb7e19, TypeMAPPING> {
9060let isPseudo = 1;
9061let isCodeGenOnly = 1;
9062let Constraints = "$Ryy32 = $Ryy32in";
9063}
9064def L2_loadbsw2_io : HInst<
9065(outs IntRegs:$Rd32),
9066(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9067"$Rd32 = membh($Rs32+#$Ii)",
9068tc_4222e6bf, TypeLD>, Enc_de0214 {
9069let Inst{24-21} = 0b0001;
9070let Inst{31-27} = 0b10010;
9071let hasNewValue = 1;
9072let opNewValue = 0;
9073let addrMode = BaseImmOffset;
9074let accessSize = HalfWordAccess;
9075let mayLoad = 1;
9076let isExtendable = 1;
9077let opExtendable = 2;
9078let isExtentSigned = 1;
9079let opExtentBits = 12;
9080let opExtentAlign = 1;
9081}
9082def L2_loadbsw2_pbr : HInst<
9083(outs IntRegs:$Rd32, IntRegs:$Rx32),
9084(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9085"$Rd32 = membh($Rx32++$Mu2:brev)",
9086tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9087let Inst{12-5} = 0b00000000;
9088let Inst{31-21} = 0b10011110001;
9089let hasNewValue = 1;
9090let opNewValue = 0;
9091let addrMode = PostInc;
9092let accessSize = HalfWordAccess;
9093let mayLoad = 1;
9094let Constraints = "$Rx32 = $Rx32in";
9095}
9096def L2_loadbsw2_pci : HInst<
9097(outs IntRegs:$Rd32, IntRegs:$Rx32),
9098(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9099"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
9100tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9101let Inst{12-9} = 0b0000;
9102let Inst{31-21} = 0b10011000001;
9103let hasNewValue = 1;
9104let opNewValue = 0;
9105let addrMode = PostInc;
9106let accessSize = HalfWordAccess;
9107let mayLoad = 1;
9108let Uses = [CS];
9109let Constraints = "$Rx32 = $Rx32in";
9110}
9111def L2_loadbsw2_pcr : HInst<
9112(outs IntRegs:$Rd32, IntRegs:$Rx32),
9113(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9114"$Rd32 = membh($Rx32++I:circ($Mu2))",
9115tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9116let Inst{12-5} = 0b00010000;
9117let Inst{31-21} = 0b10011000001;
9118let hasNewValue = 1;
9119let opNewValue = 0;
9120let addrMode = PostInc;
9121let accessSize = HalfWordAccess;
9122let mayLoad = 1;
9123let Uses = [CS];
9124let Constraints = "$Rx32 = $Rx32in";
9125}
9126def L2_loadbsw2_pi : HInst<
9127(outs IntRegs:$Rd32, IntRegs:$Rx32),
9128(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9129"$Rd32 = membh($Rx32++#$Ii)",
9130tc_075c8dd8, TypeLD>, Enc_152467 {
9131let Inst{13-9} = 0b00000;
9132let Inst{31-21} = 0b10011010001;
9133let hasNewValue = 1;
9134let opNewValue = 0;
9135let addrMode = PostInc;
9136let accessSize = HalfWordAccess;
9137let mayLoad = 1;
9138let Constraints = "$Rx32 = $Rx32in";
9139}
9140def L2_loadbsw2_pr : HInst<
9141(outs IntRegs:$Rd32, IntRegs:$Rx32),
9142(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9143"$Rd32 = membh($Rx32++$Mu2)",
9144tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9145let Inst{12-5} = 0b00000000;
9146let Inst{31-21} = 0b10011100001;
9147let hasNewValue = 1;
9148let opNewValue = 0;
9149let addrMode = PostInc;
9150let accessSize = HalfWordAccess;
9151let mayLoad = 1;
9152let Constraints = "$Rx32 = $Rx32in";
9153}
9154def L2_loadbsw2_zomap : HInst<
9155(outs IntRegs:$Rd32),
9156(ins IntRegs:$Rs32),
9157"$Rd32 = membh($Rs32)",
9158tc_4222e6bf, TypeMAPPING> {
9159let hasNewValue = 1;
9160let opNewValue = 0;
9161let isPseudo = 1;
9162let isCodeGenOnly = 1;
9163}
9164def L2_loadbsw4_io : HInst<
9165(outs DoubleRegs:$Rdd32),
9166(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9167"$Rdd32 = membh($Rs32+#$Ii)",
9168tc_4222e6bf, TypeLD>, Enc_2d7491 {
9169let Inst{24-21} = 0b0111;
9170let Inst{31-27} = 0b10010;
9171let addrMode = BaseImmOffset;
9172let accessSize = WordAccess;
9173let mayLoad = 1;
9174let isExtendable = 1;
9175let opExtendable = 2;
9176let isExtentSigned = 1;
9177let opExtentBits = 13;
9178let opExtentAlign = 2;
9179}
9180def L2_loadbsw4_pbr : HInst<
9181(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9182(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9183"$Rdd32 = membh($Rx32++$Mu2:brev)",
9184tc_075c8dd8, TypeLD>, Enc_7eee72 {
9185let Inst{12-5} = 0b00000000;
9186let Inst{31-21} = 0b10011110111;
9187let addrMode = PostInc;
9188let accessSize = WordAccess;
9189let mayLoad = 1;
9190let Constraints = "$Rx32 = $Rx32in";
9191}
9192def L2_loadbsw4_pci : HInst<
9193(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9194(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9195"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
9196tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9197let Inst{12-9} = 0b0000;
9198let Inst{31-21} = 0b10011000111;
9199let addrMode = PostInc;
9200let accessSize = WordAccess;
9201let mayLoad = 1;
9202let Uses = [CS];
9203let Constraints = "$Rx32 = $Rx32in";
9204}
9205def L2_loadbsw4_pcr : HInst<
9206(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9207(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9208"$Rdd32 = membh($Rx32++I:circ($Mu2))",
9209tc_075c8dd8, TypeLD>, Enc_7eee72 {
9210let Inst{12-5} = 0b00010000;
9211let Inst{31-21} = 0b10011000111;
9212let addrMode = PostInc;
9213let accessSize = WordAccess;
9214let mayLoad = 1;
9215let Uses = [CS];
9216let Constraints = "$Rx32 = $Rx32in";
9217}
9218def L2_loadbsw4_pi : HInst<
9219(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9220(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9221"$Rdd32 = membh($Rx32++#$Ii)",
9222tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9223let Inst{13-9} = 0b00000;
9224let Inst{31-21} = 0b10011010111;
9225let addrMode = PostInc;
9226let accessSize = WordAccess;
9227let mayLoad = 1;
9228let Constraints = "$Rx32 = $Rx32in";
9229}
9230def L2_loadbsw4_pr : HInst<
9231(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9232(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9233"$Rdd32 = membh($Rx32++$Mu2)",
9234tc_075c8dd8, TypeLD>, Enc_7eee72 {
9235let Inst{12-5} = 0b00000000;
9236let Inst{31-21} = 0b10011100111;
9237let addrMode = PostInc;
9238let accessSize = WordAccess;
9239let mayLoad = 1;
9240let Constraints = "$Rx32 = $Rx32in";
9241}
9242def L2_loadbsw4_zomap : HInst<
9243(outs DoubleRegs:$Rdd32),
9244(ins IntRegs:$Rs32),
9245"$Rdd32 = membh($Rs32)",
9246tc_4222e6bf, TypeMAPPING> {
9247let isPseudo = 1;
9248let isCodeGenOnly = 1;
9249}
9250def L2_loadbzw2_io : HInst<
9251(outs IntRegs:$Rd32),
9252(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9253"$Rd32 = memubh($Rs32+#$Ii)",
9254tc_4222e6bf, TypeLD>, Enc_de0214 {
9255let Inst{24-21} = 0b0011;
9256let Inst{31-27} = 0b10010;
9257let hasNewValue = 1;
9258let opNewValue = 0;
9259let addrMode = BaseImmOffset;
9260let accessSize = HalfWordAccess;
9261let mayLoad = 1;
9262let isExtendable = 1;
9263let opExtendable = 2;
9264let isExtentSigned = 1;
9265let opExtentBits = 12;
9266let opExtentAlign = 1;
9267}
9268def L2_loadbzw2_pbr : HInst<
9269(outs IntRegs:$Rd32, IntRegs:$Rx32),
9270(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9271"$Rd32 = memubh($Rx32++$Mu2:brev)",
9272tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9273let Inst{12-5} = 0b00000000;
9274let Inst{31-21} = 0b10011110011;
9275let hasNewValue = 1;
9276let opNewValue = 0;
9277let addrMode = PostInc;
9278let accessSize = HalfWordAccess;
9279let mayLoad = 1;
9280let Constraints = "$Rx32 = $Rx32in";
9281}
9282def L2_loadbzw2_pci : HInst<
9283(outs IntRegs:$Rd32, IntRegs:$Rx32),
9284(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9285"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9286tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9287let Inst{12-9} = 0b0000;
9288let Inst{31-21} = 0b10011000011;
9289let hasNewValue = 1;
9290let opNewValue = 0;
9291let addrMode = PostInc;
9292let accessSize = HalfWordAccess;
9293let mayLoad = 1;
9294let Uses = [CS];
9295let Constraints = "$Rx32 = $Rx32in";
9296}
9297def L2_loadbzw2_pcr : HInst<
9298(outs IntRegs:$Rd32, IntRegs:$Rx32),
9299(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9300"$Rd32 = memubh($Rx32++I:circ($Mu2))",
9301tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9302let Inst{12-5} = 0b00010000;
9303let Inst{31-21} = 0b10011000011;
9304let hasNewValue = 1;
9305let opNewValue = 0;
9306let addrMode = PostInc;
9307let accessSize = HalfWordAccess;
9308let mayLoad = 1;
9309let Uses = [CS];
9310let Constraints = "$Rx32 = $Rx32in";
9311}
9312def L2_loadbzw2_pi : HInst<
9313(outs IntRegs:$Rd32, IntRegs:$Rx32),
9314(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9315"$Rd32 = memubh($Rx32++#$Ii)",
9316tc_075c8dd8, TypeLD>, Enc_152467 {
9317let Inst{13-9} = 0b00000;
9318let Inst{31-21} = 0b10011010011;
9319let hasNewValue = 1;
9320let opNewValue = 0;
9321let addrMode = PostInc;
9322let accessSize = HalfWordAccess;
9323let mayLoad = 1;
9324let Constraints = "$Rx32 = $Rx32in";
9325}
9326def L2_loadbzw2_pr : HInst<
9327(outs IntRegs:$Rd32, IntRegs:$Rx32),
9328(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9329"$Rd32 = memubh($Rx32++$Mu2)",
9330tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9331let Inst{12-5} = 0b00000000;
9332let Inst{31-21} = 0b10011100011;
9333let hasNewValue = 1;
9334let opNewValue = 0;
9335let addrMode = PostInc;
9336let accessSize = HalfWordAccess;
9337let mayLoad = 1;
9338let Constraints = "$Rx32 = $Rx32in";
9339}
9340def L2_loadbzw2_zomap : HInst<
9341(outs IntRegs:$Rd32),
9342(ins IntRegs:$Rs32),
9343"$Rd32 = memubh($Rs32)",
9344tc_4222e6bf, TypeMAPPING> {
9345let hasNewValue = 1;
9346let opNewValue = 0;
9347let isPseudo = 1;
9348let isCodeGenOnly = 1;
9349}
9350def L2_loadbzw4_io : HInst<
9351(outs DoubleRegs:$Rdd32),
9352(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9353"$Rdd32 = memubh($Rs32+#$Ii)",
9354tc_4222e6bf, TypeLD>, Enc_2d7491 {
9355let Inst{24-21} = 0b0101;
9356let Inst{31-27} = 0b10010;
9357let addrMode = BaseImmOffset;
9358let accessSize = WordAccess;
9359let mayLoad = 1;
9360let isExtendable = 1;
9361let opExtendable = 2;
9362let isExtentSigned = 1;
9363let opExtentBits = 13;
9364let opExtentAlign = 2;
9365}
9366def L2_loadbzw4_pbr : HInst<
9367(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9368(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9369"$Rdd32 = memubh($Rx32++$Mu2:brev)",
9370tc_075c8dd8, TypeLD>, Enc_7eee72 {
9371let Inst{12-5} = 0b00000000;
9372let Inst{31-21} = 0b10011110101;
9373let addrMode = PostInc;
9374let accessSize = WordAccess;
9375let mayLoad = 1;
9376let Constraints = "$Rx32 = $Rx32in";
9377}
9378def L2_loadbzw4_pci : HInst<
9379(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9380(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9381"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9382tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9383let Inst{12-9} = 0b0000;
9384let Inst{31-21} = 0b10011000101;
9385let addrMode = PostInc;
9386let accessSize = WordAccess;
9387let mayLoad = 1;
9388let Uses = [CS];
9389let Constraints = "$Rx32 = $Rx32in";
9390}
9391def L2_loadbzw4_pcr : HInst<
9392(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9393(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9394"$Rdd32 = memubh($Rx32++I:circ($Mu2))",
9395tc_075c8dd8, TypeLD>, Enc_7eee72 {
9396let Inst{12-5} = 0b00010000;
9397let Inst{31-21} = 0b10011000101;
9398let addrMode = PostInc;
9399let accessSize = WordAccess;
9400let mayLoad = 1;
9401let Uses = [CS];
9402let Constraints = "$Rx32 = $Rx32in";
9403}
9404def L2_loadbzw4_pi : HInst<
9405(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9406(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9407"$Rdd32 = memubh($Rx32++#$Ii)",
9408tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9409let Inst{13-9} = 0b00000;
9410let Inst{31-21} = 0b10011010101;
9411let addrMode = PostInc;
9412let accessSize = WordAccess;
9413let mayLoad = 1;
9414let Constraints = "$Rx32 = $Rx32in";
9415}
9416def L2_loadbzw4_pr : HInst<
9417(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9418(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9419"$Rdd32 = memubh($Rx32++$Mu2)",
9420tc_075c8dd8, TypeLD>, Enc_7eee72 {
9421let Inst{12-5} = 0b00000000;
9422let Inst{31-21} = 0b10011100101;
9423let addrMode = PostInc;
9424let accessSize = WordAccess;
9425let mayLoad = 1;
9426let Constraints = "$Rx32 = $Rx32in";
9427}
9428def L2_loadbzw4_zomap : HInst<
9429(outs DoubleRegs:$Rdd32),
9430(ins IntRegs:$Rs32),
9431"$Rdd32 = memubh($Rs32)",
9432tc_4222e6bf, TypeMAPPING> {
9433let isPseudo = 1;
9434let isCodeGenOnly = 1;
9435}
9436def L2_loadrb_io : HInst<
9437(outs IntRegs:$Rd32),
9438(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9439"$Rd32 = memb($Rs32+#$Ii)",
9440tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9441let Inst{24-21} = 0b1000;
9442let Inst{31-27} = 0b10010;
9443let hasNewValue = 1;
9444let opNewValue = 0;
9445let addrMode = BaseImmOffset;
9446let accessSize = ByteAccess;
9447let mayLoad = 1;
9448let BaseOpcode = "L2_loadrb_io";
9449let CextOpcode = "L2_loadrb";
9450let isPredicable = 1;
9451let isExtendable = 1;
9452let opExtendable = 2;
9453let isExtentSigned = 1;
9454let opExtentBits = 11;
9455let opExtentAlign = 0;
9456}
9457def L2_loadrb_pbr : HInst<
9458(outs IntRegs:$Rd32, IntRegs:$Rx32),
9459(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9460"$Rd32 = memb($Rx32++$Mu2:brev)",
9461tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9462let Inst{12-5} = 0b00000000;
9463let Inst{31-21} = 0b10011111000;
9464let hasNewValue = 1;
9465let opNewValue = 0;
9466let addrMode = PostInc;
9467let accessSize = ByteAccess;
9468let mayLoad = 1;
9469let Constraints = "$Rx32 = $Rx32in";
9470}
9471def L2_loadrb_pci : HInst<
9472(outs IntRegs:$Rd32, IntRegs:$Rx32),
9473(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9474"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
9475tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9476let Inst{12-9} = 0b0000;
9477let Inst{31-21} = 0b10011001000;
9478let hasNewValue = 1;
9479let opNewValue = 0;
9480let addrMode = PostInc;
9481let accessSize = ByteAccess;
9482let mayLoad = 1;
9483let Uses = [CS];
9484let Constraints = "$Rx32 = $Rx32in";
9485}
9486def L2_loadrb_pcr : HInst<
9487(outs IntRegs:$Rd32, IntRegs:$Rx32),
9488(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9489"$Rd32 = memb($Rx32++I:circ($Mu2))",
9490tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9491let Inst{12-5} = 0b00010000;
9492let Inst{31-21} = 0b10011001000;
9493let hasNewValue = 1;
9494let opNewValue = 0;
9495let addrMode = PostInc;
9496let accessSize = ByteAccess;
9497let mayLoad = 1;
9498let Uses = [CS];
9499let Constraints = "$Rx32 = $Rx32in";
9500}
9501def L2_loadrb_pi : HInst<
9502(outs IntRegs:$Rd32, IntRegs:$Rx32),
9503(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9504"$Rd32 = memb($Rx32++#$Ii)",
9505tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9506let Inst{13-9} = 0b00000;
9507let Inst{31-21} = 0b10011011000;
9508let hasNewValue = 1;
9509let opNewValue = 0;
9510let addrMode = PostInc;
9511let accessSize = ByteAccess;
9512let mayLoad = 1;
9513let BaseOpcode = "L2_loadrb_pi";
9514let CextOpcode = "L2_loadrb";
9515let isPredicable = 1;
9516let Constraints = "$Rx32 = $Rx32in";
9517}
9518def L2_loadrb_pr : HInst<
9519(outs IntRegs:$Rd32, IntRegs:$Rx32),
9520(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9521"$Rd32 = memb($Rx32++$Mu2)",
9522tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9523let Inst{12-5} = 0b00000000;
9524let Inst{31-21} = 0b10011101000;
9525let hasNewValue = 1;
9526let opNewValue = 0;
9527let addrMode = PostInc;
9528let accessSize = ByteAccess;
9529let mayLoad = 1;
9530let Constraints = "$Rx32 = $Rx32in";
9531}
9532def L2_loadrb_zomap : HInst<
9533(outs IntRegs:$Rd32),
9534(ins IntRegs:$Rs32),
9535"$Rd32 = memb($Rs32)",
9536tc_4222e6bf, TypeMAPPING> {
9537let hasNewValue = 1;
9538let opNewValue = 0;
9539let isPseudo = 1;
9540let isCodeGenOnly = 1;
9541}
9542def L2_loadrbgp : HInst<
9543(outs IntRegs:$Rd32),
9544(ins u32_0Imm:$Ii),
9545"$Rd32 = memb(gp+#$Ii)",
9546tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9547let Inst{24-21} = 0b1000;
9548let Inst{31-27} = 0b01001;
9549let hasNewValue = 1;
9550let opNewValue = 0;
9551let accessSize = ByteAccess;
9552let mayLoad = 1;
9553let Uses = [GP];
9554let BaseOpcode = "L4_loadrb_abs";
9555let isPredicable = 1;
9556let opExtendable = 1;
9557let isExtentSigned = 0;
9558let opExtentBits = 16;
9559let opExtentAlign = 0;
9560}
9561def L2_loadrd_io : HInst<
9562(outs DoubleRegs:$Rdd32),
9563(ins IntRegs:$Rs32, s29_3Imm:$Ii),
9564"$Rdd32 = memd($Rs32+#$Ii)",
9565tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
9566let Inst{24-21} = 0b1110;
9567let Inst{31-27} = 0b10010;
9568let addrMode = BaseImmOffset;
9569let accessSize = DoubleWordAccess;
9570let mayLoad = 1;
9571let BaseOpcode = "L2_loadrd_io";
9572let CextOpcode = "L2_loadrd";
9573let isPredicable = 1;
9574let isExtendable = 1;
9575let opExtendable = 2;
9576let isExtentSigned = 1;
9577let opExtentBits = 14;
9578let opExtentAlign = 3;
9579}
9580def L2_loadrd_pbr : HInst<
9581(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9582(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9583"$Rdd32 = memd($Rx32++$Mu2:brev)",
9584tc_075c8dd8, TypeLD>, Enc_7eee72 {
9585let Inst{12-5} = 0b00000000;
9586let Inst{31-21} = 0b10011111110;
9587let addrMode = PostInc;
9588let accessSize = DoubleWordAccess;
9589let mayLoad = 1;
9590let Constraints = "$Rx32 = $Rx32in";
9591}
9592def L2_loadrd_pci : HInst<
9593(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9594(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
9595"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
9596tc_5ceb2f9e, TypeLD>, Enc_b05839 {
9597let Inst{12-9} = 0b0000;
9598let Inst{31-21} = 0b10011001110;
9599let addrMode = PostInc;
9600let accessSize = DoubleWordAccess;
9601let mayLoad = 1;
9602let Uses = [CS];
9603let Constraints = "$Rx32 = $Rx32in";
9604}
9605def L2_loadrd_pcr : HInst<
9606(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9607(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9608"$Rdd32 = memd($Rx32++I:circ($Mu2))",
9609tc_075c8dd8, TypeLD>, Enc_7eee72 {
9610let Inst{12-5} = 0b00010000;
9611let Inst{31-21} = 0b10011001110;
9612let addrMode = PostInc;
9613let accessSize = DoubleWordAccess;
9614let mayLoad = 1;
9615let Uses = [CS];
9616let Constraints = "$Rx32 = $Rx32in";
9617}
9618def L2_loadrd_pi : HInst<
9619(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9620(ins IntRegs:$Rx32in, s4_3Imm:$Ii),
9621"$Rdd32 = memd($Rx32++#$Ii)",
9622tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
9623let Inst{13-9} = 0b00000;
9624let Inst{31-21} = 0b10011011110;
9625let addrMode = PostInc;
9626let accessSize = DoubleWordAccess;
9627let mayLoad = 1;
9628let BaseOpcode = "L2_loadrd_pi";
9629let CextOpcode = "L2_loadrd";
9630let isPredicable = 1;
9631let Constraints = "$Rx32 = $Rx32in";
9632}
9633def L2_loadrd_pr : HInst<
9634(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9635(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9636"$Rdd32 = memd($Rx32++$Mu2)",
9637tc_075c8dd8, TypeLD>, Enc_7eee72 {
9638let Inst{12-5} = 0b00000000;
9639let Inst{31-21} = 0b10011101110;
9640let addrMode = PostInc;
9641let accessSize = DoubleWordAccess;
9642let mayLoad = 1;
9643let Constraints = "$Rx32 = $Rx32in";
9644}
9645def L2_loadrd_zomap : HInst<
9646(outs DoubleRegs:$Rdd32),
9647(ins IntRegs:$Rs32),
9648"$Rdd32 = memd($Rs32)",
9649tc_4222e6bf, TypeMAPPING> {
9650let isPseudo = 1;
9651let isCodeGenOnly = 1;
9652}
9653def L2_loadrdgp : HInst<
9654(outs DoubleRegs:$Rdd32),
9655(ins u29_3Imm:$Ii),
9656"$Rdd32 = memd(gp+#$Ii)",
9657tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
9658let Inst{24-21} = 0b1110;
9659let Inst{31-27} = 0b01001;
9660let accessSize = DoubleWordAccess;
9661let mayLoad = 1;
9662let Uses = [GP];
9663let BaseOpcode = "L4_loadrd_abs";
9664let isPredicable = 1;
9665let opExtendable = 1;
9666let isExtentSigned = 0;
9667let opExtentBits = 19;
9668let opExtentAlign = 3;
9669}
9670def L2_loadrh_io : HInst<
9671(outs IntRegs:$Rd32),
9672(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9673"$Rd32 = memh($Rs32+#$Ii)",
9674tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9675let Inst{24-21} = 0b1010;
9676let Inst{31-27} = 0b10010;
9677let hasNewValue = 1;
9678let opNewValue = 0;
9679let addrMode = BaseImmOffset;
9680let accessSize = HalfWordAccess;
9681let mayLoad = 1;
9682let BaseOpcode = "L2_loadrh_io";
9683let CextOpcode = "L2_loadrh";
9684let isPredicable = 1;
9685let isExtendable = 1;
9686let opExtendable = 2;
9687let isExtentSigned = 1;
9688let opExtentBits = 12;
9689let opExtentAlign = 1;
9690}
9691def L2_loadrh_pbr : HInst<
9692(outs IntRegs:$Rd32, IntRegs:$Rx32),
9693(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9694"$Rd32 = memh($Rx32++$Mu2:brev)",
9695tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9696let Inst{12-5} = 0b00000000;
9697let Inst{31-21} = 0b10011111010;
9698let hasNewValue = 1;
9699let opNewValue = 0;
9700let addrMode = PostInc;
9701let accessSize = HalfWordAccess;
9702let mayLoad = 1;
9703let Constraints = "$Rx32 = $Rx32in";
9704}
9705def L2_loadrh_pci : HInst<
9706(outs IntRegs:$Rd32, IntRegs:$Rx32),
9707(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9708"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
9709tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9710let Inst{12-9} = 0b0000;
9711let Inst{31-21} = 0b10011001010;
9712let hasNewValue = 1;
9713let opNewValue = 0;
9714let addrMode = PostInc;
9715let accessSize = HalfWordAccess;
9716let mayLoad = 1;
9717let Uses = [CS];
9718let Constraints = "$Rx32 = $Rx32in";
9719}
9720def L2_loadrh_pcr : HInst<
9721(outs IntRegs:$Rd32, IntRegs:$Rx32),
9722(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9723"$Rd32 = memh($Rx32++I:circ($Mu2))",
9724tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9725let Inst{12-5} = 0b00010000;
9726let Inst{31-21} = 0b10011001010;
9727let hasNewValue = 1;
9728let opNewValue = 0;
9729let addrMode = PostInc;
9730let accessSize = HalfWordAccess;
9731let mayLoad = 1;
9732let Uses = [CS];
9733let Constraints = "$Rx32 = $Rx32in";
9734}
9735def L2_loadrh_pi : HInst<
9736(outs IntRegs:$Rd32, IntRegs:$Rx32),
9737(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9738"$Rd32 = memh($Rx32++#$Ii)",
9739tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9740let Inst{13-9} = 0b00000;
9741let Inst{31-21} = 0b10011011010;
9742let hasNewValue = 1;
9743let opNewValue = 0;
9744let addrMode = PostInc;
9745let accessSize = HalfWordAccess;
9746let mayLoad = 1;
9747let BaseOpcode = "L2_loadrh_pi";
9748let CextOpcode = "L2_loadrh";
9749let isPredicable = 1;
9750let Constraints = "$Rx32 = $Rx32in";
9751}
9752def L2_loadrh_pr : HInst<
9753(outs IntRegs:$Rd32, IntRegs:$Rx32),
9754(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9755"$Rd32 = memh($Rx32++$Mu2)",
9756tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9757let Inst{12-5} = 0b00000000;
9758let Inst{31-21} = 0b10011101010;
9759let hasNewValue = 1;
9760let opNewValue = 0;
9761let addrMode = PostInc;
9762let accessSize = HalfWordAccess;
9763let mayLoad = 1;
9764let Constraints = "$Rx32 = $Rx32in";
9765}
9766def L2_loadrh_zomap : HInst<
9767(outs IntRegs:$Rd32),
9768(ins IntRegs:$Rs32),
9769"$Rd32 = memh($Rs32)",
9770tc_4222e6bf, TypeMAPPING> {
9771let hasNewValue = 1;
9772let opNewValue = 0;
9773let isPseudo = 1;
9774let isCodeGenOnly = 1;
9775}
9776def L2_loadrhgp : HInst<
9777(outs IntRegs:$Rd32),
9778(ins u31_1Imm:$Ii),
9779"$Rd32 = memh(gp+#$Ii)",
9780tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9781let Inst{24-21} = 0b1010;
9782let Inst{31-27} = 0b01001;
9783let hasNewValue = 1;
9784let opNewValue = 0;
9785let accessSize = HalfWordAccess;
9786let mayLoad = 1;
9787let Uses = [GP];
9788let BaseOpcode = "L4_loadrh_abs";
9789let isPredicable = 1;
9790let opExtendable = 1;
9791let isExtentSigned = 0;
9792let opExtentBits = 17;
9793let opExtentAlign = 1;
9794}
9795def L2_loadri_io : HInst<
9796(outs IntRegs:$Rd32),
9797(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9798"$Rd32 = memw($Rs32+#$Ii)",
9799tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
9800let Inst{24-21} = 0b1100;
9801let Inst{31-27} = 0b10010;
9802let hasNewValue = 1;
9803let opNewValue = 0;
9804let addrMode = BaseImmOffset;
9805let accessSize = WordAccess;
9806let mayLoad = 1;
9807let BaseOpcode = "L2_loadri_io";
9808let CextOpcode = "L2_loadri";
9809let isPredicable = 1;
9810let isExtendable = 1;
9811let opExtendable = 2;
9812let isExtentSigned = 1;
9813let opExtentBits = 13;
9814let opExtentAlign = 2;
9815}
9816def L2_loadri_pbr : HInst<
9817(outs IntRegs:$Rd32, IntRegs:$Rx32),
9818(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9819"$Rd32 = memw($Rx32++$Mu2:brev)",
9820tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9821let Inst{12-5} = 0b00000000;
9822let Inst{31-21} = 0b10011111100;
9823let hasNewValue = 1;
9824let opNewValue = 0;
9825let addrMode = PostInc;
9826let accessSize = WordAccess;
9827let mayLoad = 1;
9828let Constraints = "$Rx32 = $Rx32in";
9829}
9830def L2_loadri_pci : HInst<
9831(outs IntRegs:$Rd32, IntRegs:$Rx32),
9832(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9833"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
9834tc_5ceb2f9e, TypeLD>, Enc_27fd0e {
9835let Inst{12-9} = 0b0000;
9836let Inst{31-21} = 0b10011001100;
9837let hasNewValue = 1;
9838let opNewValue = 0;
9839let addrMode = PostInc;
9840let accessSize = WordAccess;
9841let mayLoad = 1;
9842let Uses = [CS];
9843let Constraints = "$Rx32 = $Rx32in";
9844}
9845def L2_loadri_pcr : HInst<
9846(outs IntRegs:$Rd32, IntRegs:$Rx32),
9847(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9848"$Rd32 = memw($Rx32++I:circ($Mu2))",
9849tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9850let Inst{12-5} = 0b00010000;
9851let Inst{31-21} = 0b10011001100;
9852let hasNewValue = 1;
9853let opNewValue = 0;
9854let addrMode = PostInc;
9855let accessSize = WordAccess;
9856let mayLoad = 1;
9857let Uses = [CS];
9858let Constraints = "$Rx32 = $Rx32in";
9859}
9860def L2_loadri_pi : HInst<
9861(outs IntRegs:$Rd32, IntRegs:$Rx32),
9862(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9863"$Rd32 = memw($Rx32++#$Ii)",
9864tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
9865let Inst{13-9} = 0b00000;
9866let Inst{31-21} = 0b10011011100;
9867let hasNewValue = 1;
9868let opNewValue = 0;
9869let addrMode = PostInc;
9870let accessSize = WordAccess;
9871let mayLoad = 1;
9872let BaseOpcode = "L2_loadri_pi";
9873let CextOpcode = "L2_loadri";
9874let isPredicable = 1;
9875let Constraints = "$Rx32 = $Rx32in";
9876}
9877def L2_loadri_pr : HInst<
9878(outs IntRegs:$Rd32, IntRegs:$Rx32),
9879(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9880"$Rd32 = memw($Rx32++$Mu2)",
9881tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9882let Inst{12-5} = 0b00000000;
9883let Inst{31-21} = 0b10011101100;
9884let hasNewValue = 1;
9885let opNewValue = 0;
9886let addrMode = PostInc;
9887let accessSize = WordAccess;
9888let mayLoad = 1;
9889let Constraints = "$Rx32 = $Rx32in";
9890}
9891def L2_loadri_zomap : HInst<
9892(outs IntRegs:$Rd32),
9893(ins IntRegs:$Rs32),
9894"$Rd32 = memw($Rs32)",
9895tc_4222e6bf, TypeMAPPING> {
9896let hasNewValue = 1;
9897let opNewValue = 0;
9898let isPseudo = 1;
9899let isCodeGenOnly = 1;
9900}
9901def L2_loadrigp : HInst<
9902(outs IntRegs:$Rd32),
9903(ins u30_2Imm:$Ii),
9904"$Rd32 = memw(gp+#$Ii)",
9905tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
9906let Inst{24-21} = 0b1100;
9907let Inst{31-27} = 0b01001;
9908let hasNewValue = 1;
9909let opNewValue = 0;
9910let accessSize = WordAccess;
9911let mayLoad = 1;
9912let Uses = [GP];
9913let BaseOpcode = "L4_loadri_abs";
9914let isPredicable = 1;
9915let opExtendable = 1;
9916let isExtentSigned = 0;
9917let opExtentBits = 18;
9918let opExtentAlign = 2;
9919}
9920def L2_loadrub_io : HInst<
9921(outs IntRegs:$Rd32),
9922(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9923"$Rd32 = memub($Rs32+#$Ii)",
9924tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9925let Inst{24-21} = 0b1001;
9926let Inst{31-27} = 0b10010;
9927let hasNewValue = 1;
9928let opNewValue = 0;
9929let addrMode = BaseImmOffset;
9930let accessSize = ByteAccess;
9931let mayLoad = 1;
9932let BaseOpcode = "L2_loadrub_io";
9933let CextOpcode = "L2_loadrub";
9934let isPredicable = 1;
9935let isExtendable = 1;
9936let opExtendable = 2;
9937let isExtentSigned = 1;
9938let opExtentBits = 11;
9939let opExtentAlign = 0;
9940}
9941def L2_loadrub_pbr : HInst<
9942(outs IntRegs:$Rd32, IntRegs:$Rx32),
9943(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9944"$Rd32 = memub($Rx32++$Mu2:brev)",
9945tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9946let Inst{12-5} = 0b00000000;
9947let Inst{31-21} = 0b10011111001;
9948let hasNewValue = 1;
9949let opNewValue = 0;
9950let addrMode = PostInc;
9951let accessSize = ByteAccess;
9952let mayLoad = 1;
9953let Constraints = "$Rx32 = $Rx32in";
9954}
9955def L2_loadrub_pci : HInst<
9956(outs IntRegs:$Rd32, IntRegs:$Rx32),
9957(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9958"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
9959tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9960let Inst{12-9} = 0b0000;
9961let Inst{31-21} = 0b10011001001;
9962let hasNewValue = 1;
9963let opNewValue = 0;
9964let addrMode = PostInc;
9965let accessSize = ByteAccess;
9966let mayLoad = 1;
9967let Uses = [CS];
9968let Constraints = "$Rx32 = $Rx32in";
9969}
9970def L2_loadrub_pcr : HInst<
9971(outs IntRegs:$Rd32, IntRegs:$Rx32),
9972(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9973"$Rd32 = memub($Rx32++I:circ($Mu2))",
9974tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9975let Inst{12-5} = 0b00010000;
9976let Inst{31-21} = 0b10011001001;
9977let hasNewValue = 1;
9978let opNewValue = 0;
9979let addrMode = PostInc;
9980let accessSize = ByteAccess;
9981let mayLoad = 1;
9982let Uses = [CS];
9983let Constraints = "$Rx32 = $Rx32in";
9984}
9985def L2_loadrub_pi : HInst<
9986(outs IntRegs:$Rd32, IntRegs:$Rx32),
9987(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9988"$Rd32 = memub($Rx32++#$Ii)",
9989tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9990let Inst{13-9} = 0b00000;
9991let Inst{31-21} = 0b10011011001;
9992let hasNewValue = 1;
9993let opNewValue = 0;
9994let addrMode = PostInc;
9995let accessSize = ByteAccess;
9996let mayLoad = 1;
9997let BaseOpcode = "L2_loadrub_pi";
9998let CextOpcode = "L2_loadrub";
9999let isPredicable = 1;
10000let Constraints = "$Rx32 = $Rx32in";
10001}
10002def L2_loadrub_pr : HInst<
10003(outs IntRegs:$Rd32, IntRegs:$Rx32),
10004(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10005"$Rd32 = memub($Rx32++$Mu2)",
10006tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10007let Inst{12-5} = 0b00000000;
10008let Inst{31-21} = 0b10011101001;
10009let hasNewValue = 1;
10010let opNewValue = 0;
10011let addrMode = PostInc;
10012let accessSize = ByteAccess;
10013let mayLoad = 1;
10014let Constraints = "$Rx32 = $Rx32in";
10015}
10016def L2_loadrub_zomap : HInst<
10017(outs IntRegs:$Rd32),
10018(ins IntRegs:$Rs32),
10019"$Rd32 = memub($Rs32)",
10020tc_4222e6bf, TypeMAPPING> {
10021let hasNewValue = 1;
10022let opNewValue = 0;
10023let isPseudo = 1;
10024let isCodeGenOnly = 1;
10025}
10026def L2_loadrubgp : HInst<
10027(outs IntRegs:$Rd32),
10028(ins u32_0Imm:$Ii),
10029"$Rd32 = memub(gp+#$Ii)",
10030tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
10031let Inst{24-21} = 0b1001;
10032let Inst{31-27} = 0b01001;
10033let hasNewValue = 1;
10034let opNewValue = 0;
10035let accessSize = ByteAccess;
10036let mayLoad = 1;
10037let Uses = [GP];
10038let BaseOpcode = "L4_loadrub_abs";
10039let isPredicable = 1;
10040let opExtendable = 1;
10041let isExtentSigned = 0;
10042let opExtentBits = 16;
10043let opExtentAlign = 0;
10044}
10045def L2_loadruh_io : HInst<
10046(outs IntRegs:$Rd32),
10047(ins IntRegs:$Rs32, s31_1Imm:$Ii),
10048"$Rd32 = memuh($Rs32+#$Ii)",
10049tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
10050let Inst{24-21} = 0b1011;
10051let Inst{31-27} = 0b10010;
10052let hasNewValue = 1;
10053let opNewValue = 0;
10054let addrMode = BaseImmOffset;
10055let accessSize = HalfWordAccess;
10056let mayLoad = 1;
10057let BaseOpcode = "L2_loadruh_io";
10058let CextOpcode = "L2_loadruh";
10059let isPredicable = 1;
10060let isExtendable = 1;
10061let opExtendable = 2;
10062let isExtentSigned = 1;
10063let opExtentBits = 12;
10064let opExtentAlign = 1;
10065}
10066def L2_loadruh_pbr : HInst<
10067(outs IntRegs:$Rd32, IntRegs:$Rx32),
10068(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10069"$Rd32 = memuh($Rx32++$Mu2:brev)",
10070tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10071let Inst{12-5} = 0b00000000;
10072let Inst{31-21} = 0b10011111011;
10073let hasNewValue = 1;
10074let opNewValue = 0;
10075let addrMode = PostInc;
10076let accessSize = HalfWordAccess;
10077let mayLoad = 1;
10078let Constraints = "$Rx32 = $Rx32in";
10079}
10080def L2_loadruh_pci : HInst<
10081(outs IntRegs:$Rd32, IntRegs:$Rx32),
10082(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
10083"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
10084tc_5ceb2f9e, TypeLD>, Enc_e83554 {
10085let Inst{12-9} = 0b0000;
10086let Inst{31-21} = 0b10011001011;
10087let hasNewValue = 1;
10088let opNewValue = 0;
10089let addrMode = PostInc;
10090let accessSize = HalfWordAccess;
10091let mayLoad = 1;
10092let Uses = [CS];
10093let Constraints = "$Rx32 = $Rx32in";
10094}
10095def L2_loadruh_pcr : HInst<
10096(outs IntRegs:$Rd32, IntRegs:$Rx32),
10097(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10098"$Rd32 = memuh($Rx32++I:circ($Mu2))",
10099tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10100let Inst{12-5} = 0b00010000;
10101let Inst{31-21} = 0b10011001011;
10102let hasNewValue = 1;
10103let opNewValue = 0;
10104let addrMode = PostInc;
10105let accessSize = HalfWordAccess;
10106let mayLoad = 1;
10107let Uses = [CS];
10108let Constraints = "$Rx32 = $Rx32in";
10109}
10110def L2_loadruh_pi : HInst<
10111(outs IntRegs:$Rd32, IntRegs:$Rx32),
10112(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
10113"$Rd32 = memuh($Rx32++#$Ii)",
10114tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
10115let Inst{13-9} = 0b00000;
10116let Inst{31-21} = 0b10011011011;
10117let hasNewValue = 1;
10118let opNewValue = 0;
10119let addrMode = PostInc;
10120let accessSize = HalfWordAccess;
10121let mayLoad = 1;
10122let BaseOpcode = "L2_loadruh_pi";
10123let CextOpcode = "L2_loadruh";
10124let isPredicable = 1;
10125let Constraints = "$Rx32 = $Rx32in";
10126}
10127def L2_loadruh_pr : HInst<
10128(outs IntRegs:$Rd32, IntRegs:$Rx32),
10129(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10130"$Rd32 = memuh($Rx32++$Mu2)",
10131tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10132let Inst{12-5} = 0b00000000;
10133let Inst{31-21} = 0b10011101011;
10134let hasNewValue = 1;
10135let opNewValue = 0;
10136let addrMode = PostInc;
10137let accessSize = HalfWordAccess;
10138let mayLoad = 1;
10139let Constraints = "$Rx32 = $Rx32in";
10140}
10141def L2_loadruh_zomap : HInst<
10142(outs IntRegs:$Rd32),
10143(ins IntRegs:$Rs32),
10144"$Rd32 = memuh($Rs32)",
10145tc_4222e6bf, TypeMAPPING> {
10146let hasNewValue = 1;
10147let opNewValue = 0;
10148let isPseudo = 1;
10149let isCodeGenOnly = 1;
10150}
10151def L2_loadruhgp : HInst<
10152(outs IntRegs:$Rd32),
10153(ins u31_1Imm:$Ii),
10154"$Rd32 = memuh(gp+#$Ii)",
10155tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
10156let Inst{24-21} = 0b1011;
10157let Inst{31-27} = 0b01001;
10158let hasNewValue = 1;
10159let opNewValue = 0;
10160let accessSize = HalfWordAccess;
10161let mayLoad = 1;
10162let Uses = [GP];
10163let BaseOpcode = "L4_loadruh_abs";
10164let isPredicable = 1;
10165let opExtendable = 1;
10166let isExtentSigned = 0;
10167let opExtentBits = 17;
10168let opExtentAlign = 1;
10169}
10170def L2_loadw_aq : HInst<
10171(outs IntRegs:$Rd32),
10172(ins IntRegs:$Rs32),
10173"$Rd32 = memw_aq($Rs32)",
10174tc_2471c1c8, TypeLD>, Enc_5e2823, Requires<[HasV68]> {
10175let Inst{13-5} = 0b001000000;
10176let Inst{31-21} = 0b10010010000;
10177let hasNewValue = 1;
10178let opNewValue = 0;
10179let accessSize = WordAccess;
10180let mayLoad = 1;
10181}
10182def L2_loadw_locked : HInst<
10183(outs IntRegs:$Rd32),
10184(ins IntRegs:$Rs32),
10185"$Rd32 = memw_locked($Rs32)",
10186tc_64b00d8a, TypeLD>, Enc_5e2823 {
10187let Inst{13-5} = 0b000000000;
10188let Inst{31-21} = 0b10010010000;
10189let hasNewValue = 1;
10190let opNewValue = 0;
10191let accessSize = WordAccess;
10192let mayLoad = 1;
10193let isSoloAX = 1;
10194}
10195def L2_ploadrbf_io : HInst<
10196(outs IntRegs:$Rd32),
10197(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10198"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
10199tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10200let Inst{13-13} = 0b0;
10201let Inst{31-21} = 0b01000101000;
10202let isPredicated = 1;
10203let isPredicatedFalse = 1;
10204let hasNewValue = 1;
10205let opNewValue = 0;
10206let addrMode = BaseImmOffset;
10207let accessSize = ByteAccess;
10208let mayLoad = 1;
10209let BaseOpcode = "L2_loadrb_io";
10210let CextOpcode = "L2_loadrb";
10211let isExtendable = 1;
10212let opExtendable = 3;
10213let isExtentSigned = 0;
10214let opExtentBits = 6;
10215let opExtentAlign = 0;
10216}
10217def L2_ploadrbf_pi : HInst<
10218(outs IntRegs:$Rd32, IntRegs:$Rx32),
10219(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10220"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
10221tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10222let Inst{13-11} = 0b101;
10223let Inst{31-21} = 0b10011011000;
10224let isPredicated = 1;
10225let isPredicatedFalse = 1;
10226let hasNewValue = 1;
10227let opNewValue = 0;
10228let addrMode = PostInc;
10229let accessSize = ByteAccess;
10230let mayLoad = 1;
10231let BaseOpcode = "L2_loadrb_pi";
10232let Constraints = "$Rx32 = $Rx32in";
10233}
10234def L2_ploadrbf_zomap : HInst<
10235(outs IntRegs:$Rd32),
10236(ins PredRegs:$Pt4, IntRegs:$Rs32),
10237"if (!$Pt4) $Rd32 = memb($Rs32)",
10238tc_fedb7e19, TypeMAPPING> {
10239let hasNewValue = 1;
10240let opNewValue = 0;
10241let isPseudo = 1;
10242let isCodeGenOnly = 1;
10243}
10244def L2_ploadrbfnew_io : HInst<
10245(outs IntRegs:$Rd32),
10246(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10247"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10248tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10249let Inst{13-13} = 0b0;
10250let Inst{31-21} = 0b01000111000;
10251let isPredicated = 1;
10252let isPredicatedFalse = 1;
10253let hasNewValue = 1;
10254let opNewValue = 0;
10255let addrMode = BaseImmOffset;
10256let accessSize = ByteAccess;
10257let isPredicatedNew = 1;
10258let mayLoad = 1;
10259let BaseOpcode = "L2_loadrb_io";
10260let CextOpcode = "L2_loadrb";
10261let isExtendable = 1;
10262let opExtendable = 3;
10263let isExtentSigned = 0;
10264let opExtentBits = 6;
10265let opExtentAlign = 0;
10266}
10267def L2_ploadrbfnew_pi : HInst<
10268(outs IntRegs:$Rd32, IntRegs:$Rx32),
10269(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10270"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10271tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10272let Inst{13-11} = 0b111;
10273let Inst{31-21} = 0b10011011000;
10274let isPredicated = 1;
10275let isPredicatedFalse = 1;
10276let hasNewValue = 1;
10277let opNewValue = 0;
10278let addrMode = PostInc;
10279let accessSize = ByteAccess;
10280let isPredicatedNew = 1;
10281let mayLoad = 1;
10282let BaseOpcode = "L2_loadrb_pi";
10283let Constraints = "$Rx32 = $Rx32in";
10284}
10285def L2_ploadrbfnew_zomap : HInst<
10286(outs IntRegs:$Rd32),
10287(ins PredRegs:$Pt4, IntRegs:$Rs32),
10288"if (!$Pt4.new) $Rd32 = memb($Rs32)",
10289tc_075c8dd8, TypeMAPPING> {
10290let hasNewValue = 1;
10291let opNewValue = 0;
10292let isPseudo = 1;
10293let isCodeGenOnly = 1;
10294}
10295def L2_ploadrbt_io : HInst<
10296(outs IntRegs:$Rd32),
10297(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10298"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
10299tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10300let Inst{13-13} = 0b0;
10301let Inst{31-21} = 0b01000001000;
10302let isPredicated = 1;
10303let hasNewValue = 1;
10304let opNewValue = 0;
10305let addrMode = BaseImmOffset;
10306let accessSize = ByteAccess;
10307let mayLoad = 1;
10308let BaseOpcode = "L2_loadrb_io";
10309let CextOpcode = "L2_loadrb";
10310let isExtendable = 1;
10311let opExtendable = 3;
10312let isExtentSigned = 0;
10313let opExtentBits = 6;
10314let opExtentAlign = 0;
10315}
10316def L2_ploadrbt_pi : HInst<
10317(outs IntRegs:$Rd32, IntRegs:$Rx32),
10318(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10319"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
10320tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10321let Inst{13-11} = 0b100;
10322let Inst{31-21} = 0b10011011000;
10323let isPredicated = 1;
10324let hasNewValue = 1;
10325let opNewValue = 0;
10326let addrMode = PostInc;
10327let accessSize = ByteAccess;
10328let mayLoad = 1;
10329let BaseOpcode = "L2_loadrb_pi";
10330let Constraints = "$Rx32 = $Rx32in";
10331}
10332def L2_ploadrbt_zomap : HInst<
10333(outs IntRegs:$Rd32),
10334(ins PredRegs:$Pt4, IntRegs:$Rs32),
10335"if ($Pt4) $Rd32 = memb($Rs32)",
10336tc_fedb7e19, TypeMAPPING> {
10337let hasNewValue = 1;
10338let opNewValue = 0;
10339let isPseudo = 1;
10340let isCodeGenOnly = 1;
10341}
10342def L2_ploadrbtnew_io : HInst<
10343(outs IntRegs:$Rd32),
10344(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10345"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10346tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10347let Inst{13-13} = 0b0;
10348let Inst{31-21} = 0b01000011000;
10349let isPredicated = 1;
10350let hasNewValue = 1;
10351let opNewValue = 0;
10352let addrMode = BaseImmOffset;
10353let accessSize = ByteAccess;
10354let isPredicatedNew = 1;
10355let mayLoad = 1;
10356let BaseOpcode = "L2_loadrb_io";
10357let CextOpcode = "L2_loadrb";
10358let isExtendable = 1;
10359let opExtendable = 3;
10360let isExtentSigned = 0;
10361let opExtentBits = 6;
10362let opExtentAlign = 0;
10363}
10364def L2_ploadrbtnew_pi : HInst<
10365(outs IntRegs:$Rd32, IntRegs:$Rx32),
10366(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10367"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10368tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10369let Inst{13-11} = 0b110;
10370let Inst{31-21} = 0b10011011000;
10371let isPredicated = 1;
10372let hasNewValue = 1;
10373let opNewValue = 0;
10374let addrMode = PostInc;
10375let accessSize = ByteAccess;
10376let isPredicatedNew = 1;
10377let mayLoad = 1;
10378let BaseOpcode = "L2_loadrb_pi";
10379let Constraints = "$Rx32 = $Rx32in";
10380}
10381def L2_ploadrbtnew_zomap : HInst<
10382(outs IntRegs:$Rd32),
10383(ins PredRegs:$Pt4, IntRegs:$Rs32),
10384"if ($Pt4.new) $Rd32 = memb($Rs32)",
10385tc_075c8dd8, TypeMAPPING> {
10386let hasNewValue = 1;
10387let opNewValue = 0;
10388let isPseudo = 1;
10389let isCodeGenOnly = 1;
10390}
10391def L2_ploadrdf_io : HInst<
10392(outs DoubleRegs:$Rdd32),
10393(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10394"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10395tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10396let Inst{13-13} = 0b0;
10397let Inst{31-21} = 0b01000101110;
10398let isPredicated = 1;
10399let isPredicatedFalse = 1;
10400let addrMode = BaseImmOffset;
10401let accessSize = DoubleWordAccess;
10402let mayLoad = 1;
10403let BaseOpcode = "L2_loadrd_io";
10404let CextOpcode = "L2_loadrd";
10405let isExtendable = 1;
10406let opExtendable = 3;
10407let isExtentSigned = 0;
10408let opExtentBits = 9;
10409let opExtentAlign = 3;
10410}
10411def L2_ploadrdf_pi : HInst<
10412(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10413(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10414"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10415tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10416let Inst{13-11} = 0b101;
10417let Inst{31-21} = 0b10011011110;
10418let isPredicated = 1;
10419let isPredicatedFalse = 1;
10420let addrMode = PostInc;
10421let accessSize = DoubleWordAccess;
10422let mayLoad = 1;
10423let BaseOpcode = "L2_loadrd_pi";
10424let Constraints = "$Rx32 = $Rx32in";
10425}
10426def L2_ploadrdf_zomap : HInst<
10427(outs DoubleRegs:$Rdd32),
10428(ins PredRegs:$Pt4, IntRegs:$Rs32),
10429"if (!$Pt4) $Rdd32 = memd($Rs32)",
10430tc_fedb7e19, TypeMAPPING> {
10431let isPseudo = 1;
10432let isCodeGenOnly = 1;
10433}
10434def L2_ploadrdfnew_io : HInst<
10435(outs DoubleRegs:$Rdd32),
10436(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10437"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10438tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10439let Inst{13-13} = 0b0;
10440let Inst{31-21} = 0b01000111110;
10441let isPredicated = 1;
10442let isPredicatedFalse = 1;
10443let addrMode = BaseImmOffset;
10444let accessSize = DoubleWordAccess;
10445let isPredicatedNew = 1;
10446let mayLoad = 1;
10447let BaseOpcode = "L2_loadrd_io";
10448let CextOpcode = "L2_loadrd";
10449let isExtendable = 1;
10450let opExtendable = 3;
10451let isExtentSigned = 0;
10452let opExtentBits = 9;
10453let opExtentAlign = 3;
10454}
10455def L2_ploadrdfnew_pi : HInst<
10456(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10457(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10458"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10459tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10460let Inst{13-11} = 0b111;
10461let Inst{31-21} = 0b10011011110;
10462let isPredicated = 1;
10463let isPredicatedFalse = 1;
10464let addrMode = PostInc;
10465let accessSize = DoubleWordAccess;
10466let isPredicatedNew = 1;
10467let mayLoad = 1;
10468let BaseOpcode = "L2_loadrd_pi";
10469let Constraints = "$Rx32 = $Rx32in";
10470}
10471def L2_ploadrdfnew_zomap : HInst<
10472(outs DoubleRegs:$Rdd32),
10473(ins PredRegs:$Pt4, IntRegs:$Rs32),
10474"if (!$Pt4.new) $Rdd32 = memd($Rs32)",
10475tc_075c8dd8, TypeMAPPING> {
10476let isPseudo = 1;
10477let isCodeGenOnly = 1;
10478}
10479def L2_ploadrdt_io : HInst<
10480(outs DoubleRegs:$Rdd32),
10481(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10482"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10483tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10484let Inst{13-13} = 0b0;
10485let Inst{31-21} = 0b01000001110;
10486let isPredicated = 1;
10487let addrMode = BaseImmOffset;
10488let accessSize = DoubleWordAccess;
10489let mayLoad = 1;
10490let BaseOpcode = "L2_loadrd_io";
10491let CextOpcode = "L2_loadrd";
10492let isExtendable = 1;
10493let opExtendable = 3;
10494let isExtentSigned = 0;
10495let opExtentBits = 9;
10496let opExtentAlign = 3;
10497}
10498def L2_ploadrdt_pi : HInst<
10499(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10500(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10501"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10502tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10503let Inst{13-11} = 0b100;
10504let Inst{31-21} = 0b10011011110;
10505let isPredicated = 1;
10506let addrMode = PostInc;
10507let accessSize = DoubleWordAccess;
10508let mayLoad = 1;
10509let BaseOpcode = "L2_loadrd_pi";
10510let Constraints = "$Rx32 = $Rx32in";
10511}
10512def L2_ploadrdt_zomap : HInst<
10513(outs DoubleRegs:$Rdd32),
10514(ins PredRegs:$Pt4, IntRegs:$Rs32),
10515"if ($Pt4) $Rdd32 = memd($Rs32)",
10516tc_fedb7e19, TypeMAPPING> {
10517let isPseudo = 1;
10518let isCodeGenOnly = 1;
10519}
10520def L2_ploadrdtnew_io : HInst<
10521(outs DoubleRegs:$Rdd32),
10522(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10523"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10524tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10525let Inst{13-13} = 0b0;
10526let Inst{31-21} = 0b01000011110;
10527let isPredicated = 1;
10528let addrMode = BaseImmOffset;
10529let accessSize = DoubleWordAccess;
10530let isPredicatedNew = 1;
10531let mayLoad = 1;
10532let BaseOpcode = "L2_loadrd_io";
10533let CextOpcode = "L2_loadrd";
10534let isExtendable = 1;
10535let opExtendable = 3;
10536let isExtentSigned = 0;
10537let opExtentBits = 9;
10538let opExtentAlign = 3;
10539}
10540def L2_ploadrdtnew_pi : HInst<
10541(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10542(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10543"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10544tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10545let Inst{13-11} = 0b110;
10546let Inst{31-21} = 0b10011011110;
10547let isPredicated = 1;
10548let addrMode = PostInc;
10549let accessSize = DoubleWordAccess;
10550let isPredicatedNew = 1;
10551let mayLoad = 1;
10552let BaseOpcode = "L2_loadrd_pi";
10553let Constraints = "$Rx32 = $Rx32in";
10554}
10555def L2_ploadrdtnew_zomap : HInst<
10556(outs DoubleRegs:$Rdd32),
10557(ins PredRegs:$Pt4, IntRegs:$Rs32),
10558"if ($Pt4.new) $Rdd32 = memd($Rs32)",
10559tc_075c8dd8, TypeMAPPING> {
10560let isPseudo = 1;
10561let isCodeGenOnly = 1;
10562}
10563def L2_ploadrhf_io : HInst<
10564(outs IntRegs:$Rd32),
10565(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10566"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
10567tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10568let Inst{13-13} = 0b0;
10569let Inst{31-21} = 0b01000101010;
10570let isPredicated = 1;
10571let isPredicatedFalse = 1;
10572let hasNewValue = 1;
10573let opNewValue = 0;
10574let addrMode = BaseImmOffset;
10575let accessSize = HalfWordAccess;
10576let mayLoad = 1;
10577let BaseOpcode = "L2_loadrh_io";
10578let CextOpcode = "L2_loadrh";
10579let isExtendable = 1;
10580let opExtendable = 3;
10581let isExtentSigned = 0;
10582let opExtentBits = 7;
10583let opExtentAlign = 1;
10584}
10585def L2_ploadrhf_pi : HInst<
10586(outs IntRegs:$Rd32, IntRegs:$Rx32),
10587(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10588"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
10589tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10590let Inst{13-11} = 0b101;
10591let Inst{31-21} = 0b10011011010;
10592let isPredicated = 1;
10593let isPredicatedFalse = 1;
10594let hasNewValue = 1;
10595let opNewValue = 0;
10596let addrMode = PostInc;
10597let accessSize = HalfWordAccess;
10598let mayLoad = 1;
10599let BaseOpcode = "L2_loadrh_pi";
10600let Constraints = "$Rx32 = $Rx32in";
10601}
10602def L2_ploadrhf_zomap : HInst<
10603(outs IntRegs:$Rd32),
10604(ins PredRegs:$Pt4, IntRegs:$Rs32),
10605"if (!$Pt4) $Rd32 = memh($Rs32)",
10606tc_fedb7e19, TypeMAPPING> {
10607let hasNewValue = 1;
10608let opNewValue = 0;
10609let isPseudo = 1;
10610let isCodeGenOnly = 1;
10611}
10612def L2_ploadrhfnew_io : HInst<
10613(outs IntRegs:$Rd32),
10614(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10615"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10616tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10617let Inst{13-13} = 0b0;
10618let Inst{31-21} = 0b01000111010;
10619let isPredicated = 1;
10620let isPredicatedFalse = 1;
10621let hasNewValue = 1;
10622let opNewValue = 0;
10623let addrMode = BaseImmOffset;
10624let accessSize = HalfWordAccess;
10625let isPredicatedNew = 1;
10626let mayLoad = 1;
10627let BaseOpcode = "L2_loadrh_io";
10628let CextOpcode = "L2_loadrh";
10629let isExtendable = 1;
10630let opExtendable = 3;
10631let isExtentSigned = 0;
10632let opExtentBits = 7;
10633let opExtentAlign = 1;
10634}
10635def L2_ploadrhfnew_pi : HInst<
10636(outs IntRegs:$Rd32, IntRegs:$Rx32),
10637(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10638"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10639tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10640let Inst{13-11} = 0b111;
10641let Inst{31-21} = 0b10011011010;
10642let isPredicated = 1;
10643let isPredicatedFalse = 1;
10644let hasNewValue = 1;
10645let opNewValue = 0;
10646let addrMode = PostInc;
10647let accessSize = HalfWordAccess;
10648let isPredicatedNew = 1;
10649let mayLoad = 1;
10650let BaseOpcode = "L2_loadrh_pi";
10651let Constraints = "$Rx32 = $Rx32in";
10652}
10653def L2_ploadrhfnew_zomap : HInst<
10654(outs IntRegs:$Rd32),
10655(ins PredRegs:$Pt4, IntRegs:$Rs32),
10656"if (!$Pt4.new) $Rd32 = memh($Rs32)",
10657tc_075c8dd8, TypeMAPPING> {
10658let hasNewValue = 1;
10659let opNewValue = 0;
10660let isPseudo = 1;
10661let isCodeGenOnly = 1;
10662}
10663def L2_ploadrht_io : HInst<
10664(outs IntRegs:$Rd32),
10665(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10666"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
10667tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10668let Inst{13-13} = 0b0;
10669let Inst{31-21} = 0b01000001010;
10670let isPredicated = 1;
10671let hasNewValue = 1;
10672let opNewValue = 0;
10673let addrMode = BaseImmOffset;
10674let accessSize = HalfWordAccess;
10675let mayLoad = 1;
10676let BaseOpcode = "L2_loadrh_io";
10677let CextOpcode = "L2_loadrh";
10678let isExtendable = 1;
10679let opExtendable = 3;
10680let isExtentSigned = 0;
10681let opExtentBits = 7;
10682let opExtentAlign = 1;
10683}
10684def L2_ploadrht_pi : HInst<
10685(outs IntRegs:$Rd32, IntRegs:$Rx32),
10686(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10687"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
10688tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10689let Inst{13-11} = 0b100;
10690let Inst{31-21} = 0b10011011010;
10691let isPredicated = 1;
10692let hasNewValue = 1;
10693let opNewValue = 0;
10694let addrMode = PostInc;
10695let accessSize = HalfWordAccess;
10696let mayLoad = 1;
10697let BaseOpcode = "L2_loadrh_pi";
10698let Constraints = "$Rx32 = $Rx32in";
10699}
10700def L2_ploadrht_zomap : HInst<
10701(outs IntRegs:$Rd32),
10702(ins PredRegs:$Pt4, IntRegs:$Rs32),
10703"if ($Pt4) $Rd32 = memh($Rs32)",
10704tc_fedb7e19, TypeMAPPING> {
10705let hasNewValue = 1;
10706let opNewValue = 0;
10707let isPseudo = 1;
10708let isCodeGenOnly = 1;
10709}
10710def L2_ploadrhtnew_io : HInst<
10711(outs IntRegs:$Rd32),
10712(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10713"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10714tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10715let Inst{13-13} = 0b0;
10716let Inst{31-21} = 0b01000011010;
10717let isPredicated = 1;
10718let hasNewValue = 1;
10719let opNewValue = 0;
10720let addrMode = BaseImmOffset;
10721let accessSize = HalfWordAccess;
10722let isPredicatedNew = 1;
10723let mayLoad = 1;
10724let BaseOpcode = "L2_loadrh_io";
10725let CextOpcode = "L2_loadrh";
10726let isExtendable = 1;
10727let opExtendable = 3;
10728let isExtentSigned = 0;
10729let opExtentBits = 7;
10730let opExtentAlign = 1;
10731}
10732def L2_ploadrhtnew_pi : HInst<
10733(outs IntRegs:$Rd32, IntRegs:$Rx32),
10734(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10735"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10736tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10737let Inst{13-11} = 0b110;
10738let Inst{31-21} = 0b10011011010;
10739let isPredicated = 1;
10740let hasNewValue = 1;
10741let opNewValue = 0;
10742let addrMode = PostInc;
10743let accessSize = HalfWordAccess;
10744let isPredicatedNew = 1;
10745let mayLoad = 1;
10746let BaseOpcode = "L2_loadrh_pi";
10747let Constraints = "$Rx32 = $Rx32in";
10748}
10749def L2_ploadrhtnew_zomap : HInst<
10750(outs IntRegs:$Rd32),
10751(ins PredRegs:$Pt4, IntRegs:$Rs32),
10752"if ($Pt4.new) $Rd32 = memh($Rs32)",
10753tc_075c8dd8, TypeMAPPING> {
10754let hasNewValue = 1;
10755let opNewValue = 0;
10756let isPseudo = 1;
10757let isCodeGenOnly = 1;
10758}
10759def L2_ploadrif_io : HInst<
10760(outs IntRegs:$Rd32),
10761(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10762"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
10763tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10764let Inst{13-13} = 0b0;
10765let Inst{31-21} = 0b01000101100;
10766let isPredicated = 1;
10767let isPredicatedFalse = 1;
10768let hasNewValue = 1;
10769let opNewValue = 0;
10770let addrMode = BaseImmOffset;
10771let accessSize = WordAccess;
10772let mayLoad = 1;
10773let BaseOpcode = "L2_loadri_io";
10774let CextOpcode = "L2_loadri";
10775let isExtendable = 1;
10776let opExtendable = 3;
10777let isExtentSigned = 0;
10778let opExtentBits = 8;
10779let opExtentAlign = 2;
10780}
10781def L2_ploadrif_pi : HInst<
10782(outs IntRegs:$Rd32, IntRegs:$Rx32),
10783(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10784"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
10785tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10786let Inst{13-11} = 0b101;
10787let Inst{31-21} = 0b10011011100;
10788let isPredicated = 1;
10789let isPredicatedFalse = 1;
10790let hasNewValue = 1;
10791let opNewValue = 0;
10792let addrMode = PostInc;
10793let accessSize = WordAccess;
10794let mayLoad = 1;
10795let BaseOpcode = "L2_loadri_pi";
10796let Constraints = "$Rx32 = $Rx32in";
10797}
10798def L2_ploadrif_zomap : HInst<
10799(outs IntRegs:$Rd32),
10800(ins PredRegs:$Pt4, IntRegs:$Rs32),
10801"if (!$Pt4) $Rd32 = memw($Rs32)",
10802tc_fedb7e19, TypeMAPPING> {
10803let hasNewValue = 1;
10804let opNewValue = 0;
10805let isPseudo = 1;
10806let isCodeGenOnly = 1;
10807}
10808def L2_ploadrifnew_io : HInst<
10809(outs IntRegs:$Rd32),
10810(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10811"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10812tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10813let Inst{13-13} = 0b0;
10814let Inst{31-21} = 0b01000111100;
10815let isPredicated = 1;
10816let isPredicatedFalse = 1;
10817let hasNewValue = 1;
10818let opNewValue = 0;
10819let addrMode = BaseImmOffset;
10820let accessSize = WordAccess;
10821let isPredicatedNew = 1;
10822let mayLoad = 1;
10823let BaseOpcode = "L2_loadri_io";
10824let CextOpcode = "L2_loadri";
10825let isExtendable = 1;
10826let opExtendable = 3;
10827let isExtentSigned = 0;
10828let opExtentBits = 8;
10829let opExtentAlign = 2;
10830}
10831def L2_ploadrifnew_pi : HInst<
10832(outs IntRegs:$Rd32, IntRegs:$Rx32),
10833(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10834"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10835tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10836let Inst{13-11} = 0b111;
10837let Inst{31-21} = 0b10011011100;
10838let isPredicated = 1;
10839let isPredicatedFalse = 1;
10840let hasNewValue = 1;
10841let opNewValue = 0;
10842let addrMode = PostInc;
10843let accessSize = WordAccess;
10844let isPredicatedNew = 1;
10845let mayLoad = 1;
10846let BaseOpcode = "L2_loadri_pi";
10847let Constraints = "$Rx32 = $Rx32in";
10848}
10849def L2_ploadrifnew_zomap : HInst<
10850(outs IntRegs:$Rd32),
10851(ins PredRegs:$Pt4, IntRegs:$Rs32),
10852"if (!$Pt4.new) $Rd32 = memw($Rs32)",
10853tc_075c8dd8, TypeMAPPING> {
10854let hasNewValue = 1;
10855let opNewValue = 0;
10856let isPseudo = 1;
10857let isCodeGenOnly = 1;
10858}
10859def L2_ploadrit_io : HInst<
10860(outs IntRegs:$Rd32),
10861(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10862"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
10863tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10864let Inst{13-13} = 0b0;
10865let Inst{31-21} = 0b01000001100;
10866let isPredicated = 1;
10867let hasNewValue = 1;
10868let opNewValue = 0;
10869let addrMode = BaseImmOffset;
10870let accessSize = WordAccess;
10871let mayLoad = 1;
10872let BaseOpcode = "L2_loadri_io";
10873let CextOpcode = "L2_loadri";
10874let isExtendable = 1;
10875let opExtendable = 3;
10876let isExtentSigned = 0;
10877let opExtentBits = 8;
10878let opExtentAlign = 2;
10879}
10880def L2_ploadrit_pi : HInst<
10881(outs IntRegs:$Rd32, IntRegs:$Rx32),
10882(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10883"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
10884tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10885let Inst{13-11} = 0b100;
10886let Inst{31-21} = 0b10011011100;
10887let isPredicated = 1;
10888let hasNewValue = 1;
10889let opNewValue = 0;
10890let addrMode = PostInc;
10891let accessSize = WordAccess;
10892let mayLoad = 1;
10893let BaseOpcode = "L2_loadri_pi";
10894let Constraints = "$Rx32 = $Rx32in";
10895}
10896def L2_ploadrit_zomap : HInst<
10897(outs IntRegs:$Rd32),
10898(ins PredRegs:$Pt4, IntRegs:$Rs32),
10899"if ($Pt4) $Rd32 = memw($Rs32)",
10900tc_fedb7e19, TypeMAPPING> {
10901let hasNewValue = 1;
10902let opNewValue = 0;
10903let isPseudo = 1;
10904let isCodeGenOnly = 1;
10905}
10906def L2_ploadritnew_io : HInst<
10907(outs IntRegs:$Rd32),
10908(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10909"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10910tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10911let Inst{13-13} = 0b0;
10912let Inst{31-21} = 0b01000011100;
10913let isPredicated = 1;
10914let hasNewValue = 1;
10915let opNewValue = 0;
10916let addrMode = BaseImmOffset;
10917let accessSize = WordAccess;
10918let isPredicatedNew = 1;
10919let mayLoad = 1;
10920let BaseOpcode = "L2_loadri_io";
10921let CextOpcode = "L2_loadri";
10922let isExtendable = 1;
10923let opExtendable = 3;
10924let isExtentSigned = 0;
10925let opExtentBits = 8;
10926let opExtentAlign = 2;
10927}
10928def L2_ploadritnew_pi : HInst<
10929(outs IntRegs:$Rd32, IntRegs:$Rx32),
10930(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10931"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10932tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10933let Inst{13-11} = 0b110;
10934let Inst{31-21} = 0b10011011100;
10935let isPredicated = 1;
10936let hasNewValue = 1;
10937let opNewValue = 0;
10938let addrMode = PostInc;
10939let accessSize = WordAccess;
10940let isPredicatedNew = 1;
10941let mayLoad = 1;
10942let BaseOpcode = "L2_loadri_pi";
10943let Constraints = "$Rx32 = $Rx32in";
10944}
10945def L2_ploadritnew_zomap : HInst<
10946(outs IntRegs:$Rd32),
10947(ins PredRegs:$Pt4, IntRegs:$Rs32),
10948"if ($Pt4.new) $Rd32 = memw($Rs32)",
10949tc_075c8dd8, TypeMAPPING> {
10950let hasNewValue = 1;
10951let opNewValue = 0;
10952let isPseudo = 1;
10953let isCodeGenOnly = 1;
10954}
10955def L2_ploadrubf_io : HInst<
10956(outs IntRegs:$Rd32),
10957(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10958"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
10959tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10960let Inst{13-13} = 0b0;
10961let Inst{31-21} = 0b01000101001;
10962let isPredicated = 1;
10963let isPredicatedFalse = 1;
10964let hasNewValue = 1;
10965let opNewValue = 0;
10966let addrMode = BaseImmOffset;
10967let accessSize = ByteAccess;
10968let mayLoad = 1;
10969let BaseOpcode = "L2_loadrub_io";
10970let CextOpcode = "L2_loadrub";
10971let isExtendable = 1;
10972let opExtendable = 3;
10973let isExtentSigned = 0;
10974let opExtentBits = 6;
10975let opExtentAlign = 0;
10976}
10977def L2_ploadrubf_pi : HInst<
10978(outs IntRegs:$Rd32, IntRegs:$Rx32),
10979(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10980"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
10981tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10982let Inst{13-11} = 0b101;
10983let Inst{31-21} = 0b10011011001;
10984let isPredicated = 1;
10985let isPredicatedFalse = 1;
10986let hasNewValue = 1;
10987let opNewValue = 0;
10988let addrMode = PostInc;
10989let accessSize = ByteAccess;
10990let mayLoad = 1;
10991let BaseOpcode = "L2_loadrub_pi";
10992let Constraints = "$Rx32 = $Rx32in";
10993}
10994def L2_ploadrubf_zomap : HInst<
10995(outs IntRegs:$Rd32),
10996(ins PredRegs:$Pt4, IntRegs:$Rs32),
10997"if (!$Pt4) $Rd32 = memub($Rs32)",
10998tc_fedb7e19, TypeMAPPING> {
10999let hasNewValue = 1;
11000let opNewValue = 0;
11001let isPseudo = 1;
11002let isCodeGenOnly = 1;
11003}
11004def L2_ploadrubfnew_io : HInst<
11005(outs IntRegs:$Rd32),
11006(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11007"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
11008tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11009let Inst{13-13} = 0b0;
11010let Inst{31-21} = 0b01000111001;
11011let isPredicated = 1;
11012let isPredicatedFalse = 1;
11013let hasNewValue = 1;
11014let opNewValue = 0;
11015let addrMode = BaseImmOffset;
11016let accessSize = ByteAccess;
11017let isPredicatedNew = 1;
11018let mayLoad = 1;
11019let BaseOpcode = "L2_loadrub_io";
11020let CextOpcode = "L2_loadrub";
11021let isExtendable = 1;
11022let opExtendable = 3;
11023let isExtentSigned = 0;
11024let opExtentBits = 6;
11025let opExtentAlign = 0;
11026}
11027def L2_ploadrubfnew_pi : HInst<
11028(outs IntRegs:$Rd32, IntRegs:$Rx32),
11029(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11030"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
11031tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
11032let Inst{13-11} = 0b111;
11033let Inst{31-21} = 0b10011011001;
11034let isPredicated = 1;
11035let isPredicatedFalse = 1;
11036let hasNewValue = 1;
11037let opNewValue = 0;
11038let addrMode = PostInc;
11039let accessSize = ByteAccess;
11040let isPredicatedNew = 1;
11041let mayLoad = 1;
11042let BaseOpcode = "L2_loadrub_pi";
11043let Constraints = "$Rx32 = $Rx32in";
11044}
11045def L2_ploadrubfnew_zomap : HInst<
11046(outs IntRegs:$Rd32),
11047(ins PredRegs:$Pt4, IntRegs:$Rs32),
11048"if (!$Pt4.new) $Rd32 = memub($Rs32)",
11049tc_075c8dd8, TypeMAPPING> {
11050let hasNewValue = 1;
11051let opNewValue = 0;
11052let isPseudo = 1;
11053let isCodeGenOnly = 1;
11054}
11055def L2_ploadrubt_io : HInst<
11056(outs IntRegs:$Rd32),
11057(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11058"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
11059tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11060let Inst{13-13} = 0b0;
11061let Inst{31-21} = 0b01000001001;
11062let isPredicated = 1;
11063let hasNewValue = 1;
11064let opNewValue = 0;
11065let addrMode = BaseImmOffset;
11066let accessSize = ByteAccess;
11067let mayLoad = 1;
11068let BaseOpcode = "L2_loadrub_io";
11069let CextOpcode = "L2_loadrub";
11070let isExtendable = 1;
11071let opExtendable = 3;
11072let isExtentSigned = 0;
11073let opExtentBits = 6;
11074let opExtentAlign = 0;
11075}
11076def L2_ploadrubt_pi : HInst<
11077(outs IntRegs:$Rd32, IntRegs:$Rx32),
11078(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11079"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
11080tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
11081let Inst{13-11} = 0b100;
11082let Inst{31-21} = 0b10011011001;
11083let isPredicated = 1;
11084let hasNewValue = 1;
11085let opNewValue = 0;
11086let addrMode = PostInc;
11087let accessSize = ByteAccess;
11088let mayLoad = 1;
11089let BaseOpcode = "L2_loadrub_pi";
11090let Constraints = "$Rx32 = $Rx32in";
11091}
11092def L2_ploadrubt_zomap : HInst<
11093(outs IntRegs:$Rd32),
11094(ins PredRegs:$Pt4, IntRegs:$Rs32),
11095"if ($Pt4) $Rd32 = memub($Rs32)",
11096tc_fedb7e19, TypeMAPPING> {
11097let hasNewValue = 1;
11098let opNewValue = 0;
11099let isPseudo = 1;
11100let isCodeGenOnly = 1;
11101}
11102def L2_ploadrubtnew_io : HInst<
11103(outs IntRegs:$Rd32),
11104(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11105"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
11106tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11107let Inst{13-13} = 0b0;
11108let Inst{31-21} = 0b01000011001;
11109let isPredicated = 1;
11110let hasNewValue = 1;
11111let opNewValue = 0;
11112let addrMode = BaseImmOffset;
11113let accessSize = ByteAccess;
11114let isPredicatedNew = 1;
11115let mayLoad = 1;
11116let BaseOpcode = "L2_loadrub_io";
11117let CextOpcode = "L2_loadrub";
11118let isExtendable = 1;
11119let opExtendable = 3;
11120let isExtentSigned = 0;
11121let opExtentBits = 6;
11122let opExtentAlign = 0;
11123}
11124def L2_ploadrubtnew_pi : HInst<
11125(outs IntRegs:$Rd32, IntRegs:$Rx32),
11126(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11127"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
11128tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
11129let Inst{13-11} = 0b110;
11130let Inst{31-21} = 0b10011011001;
11131let isPredicated = 1;
11132let hasNewValue = 1;
11133let opNewValue = 0;
11134let addrMode = PostInc;
11135let accessSize = ByteAccess;
11136let isPredicatedNew = 1;
11137let mayLoad = 1;
11138let BaseOpcode = "L2_loadrub_pi";
11139let Constraints = "$Rx32 = $Rx32in";
11140}
11141def L2_ploadrubtnew_zomap : HInst<
11142(outs IntRegs:$Rd32),
11143(ins PredRegs:$Pt4, IntRegs:$Rs32),
11144"if ($Pt4.new) $Rd32 = memub($Rs32)",
11145tc_075c8dd8, TypeMAPPING> {
11146let hasNewValue = 1;
11147let opNewValue = 0;
11148let isPseudo = 1;
11149let isCodeGenOnly = 1;
11150}
11151def L2_ploadruhf_io : HInst<
11152(outs IntRegs:$Rd32),
11153(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11154"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11155tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11156let Inst{13-13} = 0b0;
11157let Inst{31-21} = 0b01000101011;
11158let isPredicated = 1;
11159let isPredicatedFalse = 1;
11160let hasNewValue = 1;
11161let opNewValue = 0;
11162let addrMode = BaseImmOffset;
11163let accessSize = HalfWordAccess;
11164let mayLoad = 1;
11165let BaseOpcode = "L2_loadruh_io";
11166let CextOpcode = "L2_loadruh";
11167let isExtendable = 1;
11168let opExtendable = 3;
11169let isExtentSigned = 0;
11170let opExtentBits = 7;
11171let opExtentAlign = 1;
11172}
11173def L2_ploadruhf_pi : HInst<
11174(outs IntRegs:$Rd32, IntRegs:$Rx32),
11175(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11176"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11177tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11178let Inst{13-11} = 0b101;
11179let Inst{31-21} = 0b10011011011;
11180let isPredicated = 1;
11181let isPredicatedFalse = 1;
11182let hasNewValue = 1;
11183let opNewValue = 0;
11184let addrMode = PostInc;
11185let accessSize = HalfWordAccess;
11186let mayLoad = 1;
11187let BaseOpcode = "L2_loadruh_pi";
11188let Constraints = "$Rx32 = $Rx32in";
11189}
11190def L2_ploadruhf_zomap : HInst<
11191(outs IntRegs:$Rd32),
11192(ins PredRegs:$Pt4, IntRegs:$Rs32),
11193"if (!$Pt4) $Rd32 = memuh($Rs32)",
11194tc_fedb7e19, TypeMAPPING> {
11195let hasNewValue = 1;
11196let opNewValue = 0;
11197let isPseudo = 1;
11198let isCodeGenOnly = 1;
11199}
11200def L2_ploadruhfnew_io : HInst<
11201(outs IntRegs:$Rd32),
11202(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11203"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11204tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11205let Inst{13-13} = 0b0;
11206let Inst{31-21} = 0b01000111011;
11207let isPredicated = 1;
11208let isPredicatedFalse = 1;
11209let hasNewValue = 1;
11210let opNewValue = 0;
11211let addrMode = BaseImmOffset;
11212let accessSize = HalfWordAccess;
11213let isPredicatedNew = 1;
11214let mayLoad = 1;
11215let BaseOpcode = "L2_loadruh_io";
11216let CextOpcode = "L2_loadruh";
11217let isExtendable = 1;
11218let opExtendable = 3;
11219let isExtentSigned = 0;
11220let opExtentBits = 7;
11221let opExtentAlign = 1;
11222}
11223def L2_ploadruhfnew_pi : HInst<
11224(outs IntRegs:$Rd32, IntRegs:$Rx32),
11225(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11226"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11227tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11228let Inst{13-11} = 0b111;
11229let Inst{31-21} = 0b10011011011;
11230let isPredicated = 1;
11231let isPredicatedFalse = 1;
11232let hasNewValue = 1;
11233let opNewValue = 0;
11234let addrMode = PostInc;
11235let accessSize = HalfWordAccess;
11236let isPredicatedNew = 1;
11237let mayLoad = 1;
11238let BaseOpcode = "L2_loadruh_pi";
11239let Constraints = "$Rx32 = $Rx32in";
11240}
11241def L2_ploadruhfnew_zomap : HInst<
11242(outs IntRegs:$Rd32),
11243(ins PredRegs:$Pt4, IntRegs:$Rs32),
11244"if (!$Pt4.new) $Rd32 = memuh($Rs32)",
11245tc_075c8dd8, TypeMAPPING> {
11246let hasNewValue = 1;
11247let opNewValue = 0;
11248let isPseudo = 1;
11249let isCodeGenOnly = 1;
11250}
11251def L2_ploadruht_io : HInst<
11252(outs IntRegs:$Rd32),
11253(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11254"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11255tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11256let Inst{13-13} = 0b0;
11257let Inst{31-21} = 0b01000001011;
11258let isPredicated = 1;
11259let hasNewValue = 1;
11260let opNewValue = 0;
11261let addrMode = BaseImmOffset;
11262let accessSize = HalfWordAccess;
11263let mayLoad = 1;
11264let BaseOpcode = "L2_loadruh_io";
11265let CextOpcode = "L2_loadruh";
11266let isExtendable = 1;
11267let opExtendable = 3;
11268let isExtentSigned = 0;
11269let opExtentBits = 7;
11270let opExtentAlign = 1;
11271}
11272def L2_ploadruht_pi : HInst<
11273(outs IntRegs:$Rd32, IntRegs:$Rx32),
11274(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11275"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11276tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11277let Inst{13-11} = 0b100;
11278let Inst{31-21} = 0b10011011011;
11279let isPredicated = 1;
11280let hasNewValue = 1;
11281let opNewValue = 0;
11282let addrMode = PostInc;
11283let accessSize = HalfWordAccess;
11284let mayLoad = 1;
11285let BaseOpcode = "L2_loadruh_pi";
11286let Constraints = "$Rx32 = $Rx32in";
11287}
11288def L2_ploadruht_zomap : HInst<
11289(outs IntRegs:$Rd32),
11290(ins PredRegs:$Pt4, IntRegs:$Rs32),
11291"if ($Pt4) $Rd32 = memuh($Rs32)",
11292tc_fedb7e19, TypeMAPPING> {
11293let hasNewValue = 1;
11294let opNewValue = 0;
11295let isPseudo = 1;
11296let isCodeGenOnly = 1;
11297}
11298def L2_ploadruhtnew_io : HInst<
11299(outs IntRegs:$Rd32),
11300(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11301"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11302tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11303let Inst{13-13} = 0b0;
11304let Inst{31-21} = 0b01000011011;
11305let isPredicated = 1;
11306let hasNewValue = 1;
11307let opNewValue = 0;
11308let addrMode = BaseImmOffset;
11309let accessSize = HalfWordAccess;
11310let isPredicatedNew = 1;
11311let mayLoad = 1;
11312let BaseOpcode = "L2_loadruh_io";
11313let CextOpcode = "L2_loadruh";
11314let isExtendable = 1;
11315let opExtendable = 3;
11316let isExtentSigned = 0;
11317let opExtentBits = 7;
11318let opExtentAlign = 1;
11319}
11320def L2_ploadruhtnew_pi : HInst<
11321(outs IntRegs:$Rd32, IntRegs:$Rx32),
11322(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11323"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11324tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11325let Inst{13-11} = 0b110;
11326let Inst{31-21} = 0b10011011011;
11327let isPredicated = 1;
11328let hasNewValue = 1;
11329let opNewValue = 0;
11330let addrMode = PostInc;
11331let accessSize = HalfWordAccess;
11332let isPredicatedNew = 1;
11333let mayLoad = 1;
11334let BaseOpcode = "L2_loadruh_pi";
11335let Constraints = "$Rx32 = $Rx32in";
11336}
11337def L2_ploadruhtnew_zomap : HInst<
11338(outs IntRegs:$Rd32),
11339(ins PredRegs:$Pt4, IntRegs:$Rs32),
11340"if ($Pt4.new) $Rd32 = memuh($Rs32)",
11341tc_075c8dd8, TypeMAPPING> {
11342let hasNewValue = 1;
11343let opNewValue = 0;
11344let isPseudo = 1;
11345let isCodeGenOnly = 1;
11346}
11347def L4_add_memopb_io : HInst<
11348(outs),
11349(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11350"memb($Rs32+#$Ii) += $Rt32",
11351tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11352let Inst{6-5} = 0b00;
11353let Inst{13-13} = 0b0;
11354let Inst{31-21} = 0b00111110000;
11355let addrMode = BaseImmOffset;
11356let accessSize = ByteAccess;
11357let mayLoad = 1;
11358let isRestrictNoSlot1Store = 1;
11359let mayStore = 1;
11360let isExtendable = 1;
11361let opExtendable = 1;
11362let isExtentSigned = 0;
11363let opExtentBits = 6;
11364let opExtentAlign = 0;
11365}
11366def L4_add_memopb_zomap : HInst<
11367(outs),
11368(ins IntRegs:$Rs32, IntRegs:$Rt32),
11369"memb($Rs32) += $Rt32",
11370tc_9bcfb2ee, TypeMAPPING> {
11371let isPseudo = 1;
11372let isCodeGenOnly = 1;
11373}
11374def L4_add_memoph_io : HInst<
11375(outs),
11376(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11377"memh($Rs32+#$Ii) += $Rt32",
11378tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11379let Inst{6-5} = 0b00;
11380let Inst{13-13} = 0b0;
11381let Inst{31-21} = 0b00111110001;
11382let addrMode = BaseImmOffset;
11383let accessSize = HalfWordAccess;
11384let mayLoad = 1;
11385let isRestrictNoSlot1Store = 1;
11386let mayStore = 1;
11387let isExtendable = 1;
11388let opExtendable = 1;
11389let isExtentSigned = 0;
11390let opExtentBits = 7;
11391let opExtentAlign = 1;
11392}
11393def L4_add_memoph_zomap : HInst<
11394(outs),
11395(ins IntRegs:$Rs32, IntRegs:$Rt32),
11396"memh($Rs32) += $Rt32",
11397tc_9bcfb2ee, TypeMAPPING> {
11398let isPseudo = 1;
11399let isCodeGenOnly = 1;
11400}
11401def L4_add_memopw_io : HInst<
11402(outs),
11403(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11404"memw($Rs32+#$Ii) += $Rt32",
11405tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11406let Inst{6-5} = 0b00;
11407let Inst{13-13} = 0b0;
11408let Inst{31-21} = 0b00111110010;
11409let addrMode = BaseImmOffset;
11410let accessSize = WordAccess;
11411let mayLoad = 1;
11412let isRestrictNoSlot1Store = 1;
11413let mayStore = 1;
11414let isExtendable = 1;
11415let opExtendable = 1;
11416let isExtentSigned = 0;
11417let opExtentBits = 8;
11418let opExtentAlign = 2;
11419}
11420def L4_add_memopw_zomap : HInst<
11421(outs),
11422(ins IntRegs:$Rs32, IntRegs:$Rt32),
11423"memw($Rs32) += $Rt32",
11424tc_9bcfb2ee, TypeMAPPING> {
11425let isPseudo = 1;
11426let isCodeGenOnly = 1;
11427}
11428def L4_and_memopb_io : HInst<
11429(outs),
11430(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11431"memb($Rs32+#$Ii) &= $Rt32",
11432tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11433let Inst{6-5} = 0b10;
11434let Inst{13-13} = 0b0;
11435let Inst{31-21} = 0b00111110000;
11436let addrMode = BaseImmOffset;
11437let accessSize = ByteAccess;
11438let mayLoad = 1;
11439let isRestrictNoSlot1Store = 1;
11440let mayStore = 1;
11441let isExtendable = 1;
11442let opExtendable = 1;
11443let isExtentSigned = 0;
11444let opExtentBits = 6;
11445let opExtentAlign = 0;
11446}
11447def L4_and_memopb_zomap : HInst<
11448(outs),
11449(ins IntRegs:$Rs32, IntRegs:$Rt32),
11450"memb($Rs32) &= $Rt32",
11451tc_9bcfb2ee, TypeMAPPING> {
11452let isPseudo = 1;
11453let isCodeGenOnly = 1;
11454}
11455def L4_and_memoph_io : HInst<
11456(outs),
11457(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11458"memh($Rs32+#$Ii) &= $Rt32",
11459tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11460let Inst{6-5} = 0b10;
11461let Inst{13-13} = 0b0;
11462let Inst{31-21} = 0b00111110001;
11463let addrMode = BaseImmOffset;
11464let accessSize = HalfWordAccess;
11465let mayLoad = 1;
11466let isRestrictNoSlot1Store = 1;
11467let mayStore = 1;
11468let isExtendable = 1;
11469let opExtendable = 1;
11470let isExtentSigned = 0;
11471let opExtentBits = 7;
11472let opExtentAlign = 1;
11473}
11474def L4_and_memoph_zomap : HInst<
11475(outs),
11476(ins IntRegs:$Rs32, IntRegs:$Rt32),
11477"memh($Rs32) &= $Rt32",
11478tc_9bcfb2ee, TypeMAPPING> {
11479let isPseudo = 1;
11480let isCodeGenOnly = 1;
11481}
11482def L4_and_memopw_io : HInst<
11483(outs),
11484(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11485"memw($Rs32+#$Ii) &= $Rt32",
11486tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11487let Inst{6-5} = 0b10;
11488let Inst{13-13} = 0b0;
11489let Inst{31-21} = 0b00111110010;
11490let addrMode = BaseImmOffset;
11491let accessSize = WordAccess;
11492let mayLoad = 1;
11493let isRestrictNoSlot1Store = 1;
11494let mayStore = 1;
11495let isExtendable = 1;
11496let opExtendable = 1;
11497let isExtentSigned = 0;
11498let opExtentBits = 8;
11499let opExtentAlign = 2;
11500}
11501def L4_and_memopw_zomap : HInst<
11502(outs),
11503(ins IntRegs:$Rs32, IntRegs:$Rt32),
11504"memw($Rs32) &= $Rt32",
11505tc_9bcfb2ee, TypeMAPPING> {
11506let isPseudo = 1;
11507let isCodeGenOnly = 1;
11508}
11509def L4_iadd_memopb_io : HInst<
11510(outs),
11511(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11512"memb($Rs32+#$Ii) += #$II",
11513tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11514let Inst{6-5} = 0b00;
11515let Inst{13-13} = 0b0;
11516let Inst{31-21} = 0b00111111000;
11517let addrMode = BaseImmOffset;
11518let accessSize = ByteAccess;
11519let mayLoad = 1;
11520let isRestrictNoSlot1Store = 1;
11521let mayStore = 1;
11522let isExtendable = 1;
11523let opExtendable = 1;
11524let isExtentSigned = 0;
11525let opExtentBits = 6;
11526let opExtentAlign = 0;
11527}
11528def L4_iadd_memopb_zomap : HInst<
11529(outs),
11530(ins IntRegs:$Rs32, u5_0Imm:$II),
11531"memb($Rs32) += #$II",
11532tc_158aa3f7, TypeMAPPING> {
11533let isPseudo = 1;
11534let isCodeGenOnly = 1;
11535}
11536def L4_iadd_memoph_io : HInst<
11537(outs),
11538(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11539"memh($Rs32+#$Ii) += #$II",
11540tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11541let Inst{6-5} = 0b00;
11542let Inst{13-13} = 0b0;
11543let Inst{31-21} = 0b00111111001;
11544let addrMode = BaseImmOffset;
11545let accessSize = HalfWordAccess;
11546let mayLoad = 1;
11547let isRestrictNoSlot1Store = 1;
11548let mayStore = 1;
11549let isExtendable = 1;
11550let opExtendable = 1;
11551let isExtentSigned = 0;
11552let opExtentBits = 7;
11553let opExtentAlign = 1;
11554}
11555def L4_iadd_memoph_zomap : HInst<
11556(outs),
11557(ins IntRegs:$Rs32, u5_0Imm:$II),
11558"memh($Rs32) += #$II",
11559tc_158aa3f7, TypeMAPPING> {
11560let isPseudo = 1;
11561let isCodeGenOnly = 1;
11562}
11563def L4_iadd_memopw_io : HInst<
11564(outs),
11565(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11566"memw($Rs32+#$Ii) += #$II",
11567tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11568let Inst{6-5} = 0b00;
11569let Inst{13-13} = 0b0;
11570let Inst{31-21} = 0b00111111010;
11571let addrMode = BaseImmOffset;
11572let accessSize = WordAccess;
11573let mayLoad = 1;
11574let isRestrictNoSlot1Store = 1;
11575let mayStore = 1;
11576let isExtendable = 1;
11577let opExtendable = 1;
11578let isExtentSigned = 0;
11579let opExtentBits = 8;
11580let opExtentAlign = 2;
11581}
11582def L4_iadd_memopw_zomap : HInst<
11583(outs),
11584(ins IntRegs:$Rs32, u5_0Imm:$II),
11585"memw($Rs32) += #$II",
11586tc_158aa3f7, TypeMAPPING> {
11587let isPseudo = 1;
11588let isCodeGenOnly = 1;
11589}
11590def L4_iand_memopb_io : HInst<
11591(outs),
11592(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11593"memb($Rs32+#$Ii) = clrbit(#$II)",
11594tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11595let Inst{6-5} = 0b10;
11596let Inst{13-13} = 0b0;
11597let Inst{31-21} = 0b00111111000;
11598let addrMode = BaseImmOffset;
11599let accessSize = ByteAccess;
11600let mayLoad = 1;
11601let isRestrictNoSlot1Store = 1;
11602let mayStore = 1;
11603let isExtendable = 1;
11604let opExtendable = 1;
11605let isExtentSigned = 0;
11606let opExtentBits = 6;
11607let opExtentAlign = 0;
11608}
11609def L4_iand_memopb_zomap : HInst<
11610(outs),
11611(ins IntRegs:$Rs32, u5_0Imm:$II),
11612"memb($Rs32) = clrbit(#$II)",
11613tc_158aa3f7, TypeMAPPING> {
11614let isPseudo = 1;
11615let isCodeGenOnly = 1;
11616}
11617def L4_iand_memoph_io : HInst<
11618(outs),
11619(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11620"memh($Rs32+#$Ii) = clrbit(#$II)",
11621tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11622let Inst{6-5} = 0b10;
11623let Inst{13-13} = 0b0;
11624let Inst{31-21} = 0b00111111001;
11625let addrMode = BaseImmOffset;
11626let accessSize = HalfWordAccess;
11627let mayLoad = 1;
11628let isRestrictNoSlot1Store = 1;
11629let mayStore = 1;
11630let isExtendable = 1;
11631let opExtendable = 1;
11632let isExtentSigned = 0;
11633let opExtentBits = 7;
11634let opExtentAlign = 1;
11635}
11636def L4_iand_memoph_zomap : HInst<
11637(outs),
11638(ins IntRegs:$Rs32, u5_0Imm:$II),
11639"memh($Rs32) = clrbit(#$II)",
11640tc_158aa3f7, TypeMAPPING> {
11641let isPseudo = 1;
11642let isCodeGenOnly = 1;
11643}
11644def L4_iand_memopw_io : HInst<
11645(outs),
11646(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11647"memw($Rs32+#$Ii) = clrbit(#$II)",
11648tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11649let Inst{6-5} = 0b10;
11650let Inst{13-13} = 0b0;
11651let Inst{31-21} = 0b00111111010;
11652let addrMode = BaseImmOffset;
11653let accessSize = WordAccess;
11654let mayLoad = 1;
11655let isRestrictNoSlot1Store = 1;
11656let mayStore = 1;
11657let isExtendable = 1;
11658let opExtendable = 1;
11659let isExtentSigned = 0;
11660let opExtentBits = 8;
11661let opExtentAlign = 2;
11662}
11663def L4_iand_memopw_zomap : HInst<
11664(outs),
11665(ins IntRegs:$Rs32, u5_0Imm:$II),
11666"memw($Rs32) = clrbit(#$II)",
11667tc_158aa3f7, TypeMAPPING> {
11668let isPseudo = 1;
11669let isCodeGenOnly = 1;
11670}
11671def L4_ior_memopb_io : HInst<
11672(outs),
11673(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11674"memb($Rs32+#$Ii) = setbit(#$II)",
11675tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11676let Inst{6-5} = 0b11;
11677let Inst{13-13} = 0b0;
11678let Inst{31-21} = 0b00111111000;
11679let addrMode = BaseImmOffset;
11680let accessSize = ByteAccess;
11681let mayLoad = 1;
11682let isRestrictNoSlot1Store = 1;
11683let mayStore = 1;
11684let isExtendable = 1;
11685let opExtendable = 1;
11686let isExtentSigned = 0;
11687let opExtentBits = 6;
11688let opExtentAlign = 0;
11689}
11690def L4_ior_memopb_zomap : HInst<
11691(outs),
11692(ins IntRegs:$Rs32, u5_0Imm:$II),
11693"memb($Rs32) = setbit(#$II)",
11694tc_158aa3f7, TypeMAPPING> {
11695let isPseudo = 1;
11696let isCodeGenOnly = 1;
11697}
11698def L4_ior_memoph_io : HInst<
11699(outs),
11700(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11701"memh($Rs32+#$Ii) = setbit(#$II)",
11702tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11703let Inst{6-5} = 0b11;
11704let Inst{13-13} = 0b0;
11705let Inst{31-21} = 0b00111111001;
11706let addrMode = BaseImmOffset;
11707let accessSize = HalfWordAccess;
11708let mayLoad = 1;
11709let isRestrictNoSlot1Store = 1;
11710let mayStore = 1;
11711let isExtendable = 1;
11712let opExtendable = 1;
11713let isExtentSigned = 0;
11714let opExtentBits = 7;
11715let opExtentAlign = 1;
11716}
11717def L4_ior_memoph_zomap : HInst<
11718(outs),
11719(ins IntRegs:$Rs32, u5_0Imm:$II),
11720"memh($Rs32) = setbit(#$II)",
11721tc_158aa3f7, TypeMAPPING> {
11722let isPseudo = 1;
11723let isCodeGenOnly = 1;
11724}
11725def L4_ior_memopw_io : HInst<
11726(outs),
11727(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11728"memw($Rs32+#$Ii) = setbit(#$II)",
11729tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11730let Inst{6-5} = 0b11;
11731let Inst{13-13} = 0b0;
11732let Inst{31-21} = 0b00111111010;
11733let addrMode = BaseImmOffset;
11734let accessSize = WordAccess;
11735let mayLoad = 1;
11736let isRestrictNoSlot1Store = 1;
11737let mayStore = 1;
11738let isExtendable = 1;
11739let opExtendable = 1;
11740let isExtentSigned = 0;
11741let opExtentBits = 8;
11742let opExtentAlign = 2;
11743}
11744def L4_ior_memopw_zomap : HInst<
11745(outs),
11746(ins IntRegs:$Rs32, u5_0Imm:$II),
11747"memw($Rs32) = setbit(#$II)",
11748tc_158aa3f7, TypeMAPPING> {
11749let isPseudo = 1;
11750let isCodeGenOnly = 1;
11751}
11752def L4_isub_memopb_io : HInst<
11753(outs),
11754(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11755"memb($Rs32+#$Ii) -= #$II",
11756tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11757let Inst{6-5} = 0b01;
11758let Inst{13-13} = 0b0;
11759let Inst{31-21} = 0b00111111000;
11760let addrMode = BaseImmOffset;
11761let accessSize = ByteAccess;
11762let mayLoad = 1;
11763let isRestrictNoSlot1Store = 1;
11764let mayStore = 1;
11765let isExtendable = 1;
11766let opExtendable = 1;
11767let isExtentSigned = 0;
11768let opExtentBits = 6;
11769let opExtentAlign = 0;
11770}
11771def L4_isub_memopb_zomap : HInst<
11772(outs),
11773(ins IntRegs:$Rs32, u5_0Imm:$II),
11774"memb($Rs32) -= #$II",
11775tc_158aa3f7, TypeMAPPING> {
11776let isPseudo = 1;
11777let isCodeGenOnly = 1;
11778}
11779def L4_isub_memoph_io : HInst<
11780(outs),
11781(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11782"memh($Rs32+#$Ii) -= #$II",
11783tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11784let Inst{6-5} = 0b01;
11785let Inst{13-13} = 0b0;
11786let Inst{31-21} = 0b00111111001;
11787let addrMode = BaseImmOffset;
11788let accessSize = HalfWordAccess;
11789let mayLoad = 1;
11790let isRestrictNoSlot1Store = 1;
11791let mayStore = 1;
11792let isExtendable = 1;
11793let opExtendable = 1;
11794let isExtentSigned = 0;
11795let opExtentBits = 7;
11796let opExtentAlign = 1;
11797}
11798def L4_isub_memoph_zomap : HInst<
11799(outs),
11800(ins IntRegs:$Rs32, u5_0Imm:$II),
11801"memh($Rs32) -= #$II",
11802tc_158aa3f7, TypeMAPPING> {
11803let isPseudo = 1;
11804let isCodeGenOnly = 1;
11805}
11806def L4_isub_memopw_io : HInst<
11807(outs),
11808(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11809"memw($Rs32+#$Ii) -= #$II",
11810tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11811let Inst{6-5} = 0b01;
11812let Inst{13-13} = 0b0;
11813let Inst{31-21} = 0b00111111010;
11814let addrMode = BaseImmOffset;
11815let accessSize = WordAccess;
11816let mayLoad = 1;
11817let isRestrictNoSlot1Store = 1;
11818let mayStore = 1;
11819let isExtendable = 1;
11820let opExtendable = 1;
11821let isExtentSigned = 0;
11822let opExtentBits = 8;
11823let opExtentAlign = 2;
11824}
11825def L4_isub_memopw_zomap : HInst<
11826(outs),
11827(ins IntRegs:$Rs32, u5_0Imm:$II),
11828"memw($Rs32) -= #$II",
11829tc_158aa3f7, TypeMAPPING> {
11830let isPseudo = 1;
11831let isCodeGenOnly = 1;
11832}
11833def L4_loadalignb_ap : HInst<
11834(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11835(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11836"$Ryy32 = memb_fifo($Re32=#$II)",
11837tc_ac65613f, TypeLD>, Enc_f394d3 {
11838let Inst{7-7} = 0b0;
11839let Inst{13-12} = 0b01;
11840let Inst{31-21} = 0b10011010100;
11841let addrMode = AbsoluteSet;
11842let accessSize = ByteAccess;
11843let mayLoad = 1;
11844let isExtended = 1;
11845let DecoderNamespace = "MustExtend";
11846let isExtendable = 1;
11847let opExtendable = 3;
11848let isExtentSigned = 0;
11849let opExtentBits = 6;
11850let opExtentAlign = 0;
11851let Constraints = "$Ryy32 = $Ryy32in";
11852}
11853def L4_loadalignb_ur : HInst<
11854(outs DoubleRegs:$Ryy32),
11855(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11856"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
11857tc_a32e03e7, TypeLD>, Enc_04c959 {
11858let Inst{12-12} = 0b1;
11859let Inst{31-21} = 0b10011100100;
11860let addrMode = BaseLongOffset;
11861let accessSize = ByteAccess;
11862let mayLoad = 1;
11863let isExtended = 1;
11864let InputType = "imm";
11865let DecoderNamespace = "MustExtend";
11866let isExtendable = 1;
11867let opExtendable = 4;
11868let isExtentSigned = 0;
11869let opExtentBits = 6;
11870let opExtentAlign = 0;
11871let Constraints = "$Ryy32 = $Ryy32in";
11872}
11873def L4_loadalignh_ap : HInst<
11874(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11875(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11876"$Ryy32 = memh_fifo($Re32=#$II)",
11877tc_ac65613f, TypeLD>, Enc_f394d3 {
11878let Inst{7-7} = 0b0;
11879let Inst{13-12} = 0b01;
11880let Inst{31-21} = 0b10011010010;
11881let addrMode = AbsoluteSet;
11882let accessSize = HalfWordAccess;
11883let mayLoad = 1;
11884let isExtended = 1;
11885let DecoderNamespace = "MustExtend";
11886let isExtendable = 1;
11887let opExtendable = 3;
11888let isExtentSigned = 0;
11889let opExtentBits = 6;
11890let opExtentAlign = 0;
11891let Constraints = "$Ryy32 = $Ryy32in";
11892}
11893def L4_loadalignh_ur : HInst<
11894(outs DoubleRegs:$Ryy32),
11895(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11896"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
11897tc_a32e03e7, TypeLD>, Enc_04c959 {
11898let Inst{12-12} = 0b1;
11899let Inst{31-21} = 0b10011100010;
11900let addrMode = BaseLongOffset;
11901let accessSize = HalfWordAccess;
11902let mayLoad = 1;
11903let isExtended = 1;
11904let InputType = "imm";
11905let DecoderNamespace = "MustExtend";
11906let isExtendable = 1;
11907let opExtendable = 4;
11908let isExtentSigned = 0;
11909let opExtentBits = 6;
11910let opExtentAlign = 0;
11911let Constraints = "$Ryy32 = $Ryy32in";
11912}
11913def L4_loadbsw2_ap : HInst<
11914(outs IntRegs:$Rd32, IntRegs:$Re32),
11915(ins u32_0Imm:$II),
11916"$Rd32 = membh($Re32=#$II)",
11917tc_822c3c68, TypeLD>, Enc_323f2d {
11918let Inst{7-7} = 0b0;
11919let Inst{13-12} = 0b01;
11920let Inst{31-21} = 0b10011010001;
11921let hasNewValue = 1;
11922let opNewValue = 0;
11923let addrMode = AbsoluteSet;
11924let accessSize = HalfWordAccess;
11925let mayLoad = 1;
11926let isExtended = 1;
11927let DecoderNamespace = "MustExtend";
11928let isExtendable = 1;
11929let opExtendable = 2;
11930let isExtentSigned = 0;
11931let opExtentBits = 6;
11932let opExtentAlign = 0;
11933}
11934def L4_loadbsw2_ur : HInst<
11935(outs IntRegs:$Rd32),
11936(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11937"$Rd32 = membh($Rt32<<#$Ii+#$II)",
11938tc_abfd9a6d, TypeLD>, Enc_4f677b {
11939let Inst{12-12} = 0b1;
11940let Inst{31-21} = 0b10011100001;
11941let hasNewValue = 1;
11942let opNewValue = 0;
11943let addrMode = BaseLongOffset;
11944let accessSize = HalfWordAccess;
11945let mayLoad = 1;
11946let isExtended = 1;
11947let InputType = "imm";
11948let DecoderNamespace = "MustExtend";
11949let isExtendable = 1;
11950let opExtendable = 3;
11951let isExtentSigned = 0;
11952let opExtentBits = 6;
11953let opExtentAlign = 0;
11954}
11955def L4_loadbsw4_ap : HInst<
11956(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11957(ins u32_0Imm:$II),
11958"$Rdd32 = membh($Re32=#$II)",
11959tc_822c3c68, TypeLD>, Enc_7fa7f6 {
11960let Inst{7-7} = 0b0;
11961let Inst{13-12} = 0b01;
11962let Inst{31-21} = 0b10011010111;
11963let addrMode = AbsoluteSet;
11964let accessSize = WordAccess;
11965let mayLoad = 1;
11966let isExtended = 1;
11967let DecoderNamespace = "MustExtend";
11968let isExtendable = 1;
11969let opExtendable = 2;
11970let isExtentSigned = 0;
11971let opExtentBits = 6;
11972let opExtentAlign = 0;
11973}
11974def L4_loadbsw4_ur : HInst<
11975(outs DoubleRegs:$Rdd32),
11976(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11977"$Rdd32 = membh($Rt32<<#$Ii+#$II)",
11978tc_abfd9a6d, TypeLD>, Enc_6185fe {
11979let Inst{12-12} = 0b1;
11980let Inst{31-21} = 0b10011100111;
11981let addrMode = BaseLongOffset;
11982let accessSize = WordAccess;
11983let mayLoad = 1;
11984let isExtended = 1;
11985let InputType = "imm";
11986let DecoderNamespace = "MustExtend";
11987let isExtendable = 1;
11988let opExtendable = 3;
11989let isExtentSigned = 0;
11990let opExtentBits = 6;
11991let opExtentAlign = 0;
11992}
11993def L4_loadbzw2_ap : HInst<
11994(outs IntRegs:$Rd32, IntRegs:$Re32),
11995(ins u32_0Imm:$II),
11996"$Rd32 = memubh($Re32=#$II)",
11997tc_822c3c68, TypeLD>, Enc_323f2d {
11998let Inst{7-7} = 0b0;
11999let Inst{13-12} = 0b01;
12000let Inst{31-21} = 0b10011010011;
12001let hasNewValue = 1;
12002let opNewValue = 0;
12003let addrMode = AbsoluteSet;
12004let accessSize = HalfWordAccess;
12005let mayLoad = 1;
12006let isExtended = 1;
12007let DecoderNamespace = "MustExtend";
12008let isExtendable = 1;
12009let opExtendable = 2;
12010let isExtentSigned = 0;
12011let opExtentBits = 6;
12012let opExtentAlign = 0;
12013}
12014def L4_loadbzw2_ur : HInst<
12015(outs IntRegs:$Rd32),
12016(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12017"$Rd32 = memubh($Rt32<<#$Ii+#$II)",
12018tc_abfd9a6d, TypeLD>, Enc_4f677b {
12019let Inst{12-12} = 0b1;
12020let Inst{31-21} = 0b10011100011;
12021let hasNewValue = 1;
12022let opNewValue = 0;
12023let addrMode = BaseLongOffset;
12024let accessSize = HalfWordAccess;
12025let mayLoad = 1;
12026let isExtended = 1;
12027let InputType = "imm";
12028let DecoderNamespace = "MustExtend";
12029let isExtendable = 1;
12030let opExtendable = 3;
12031let isExtentSigned = 0;
12032let opExtentBits = 6;
12033let opExtentAlign = 0;
12034}
12035def L4_loadbzw4_ap : HInst<
12036(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12037(ins u32_0Imm:$II),
12038"$Rdd32 = memubh($Re32=#$II)",
12039tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12040let Inst{7-7} = 0b0;
12041let Inst{13-12} = 0b01;
12042let Inst{31-21} = 0b10011010101;
12043let addrMode = AbsoluteSet;
12044let accessSize = WordAccess;
12045let mayLoad = 1;
12046let isExtended = 1;
12047let DecoderNamespace = "MustExtend";
12048let isExtendable = 1;
12049let opExtendable = 2;
12050let isExtentSigned = 0;
12051let opExtentBits = 6;
12052let opExtentAlign = 0;
12053}
12054def L4_loadbzw4_ur : HInst<
12055(outs DoubleRegs:$Rdd32),
12056(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12057"$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
12058tc_abfd9a6d, TypeLD>, Enc_6185fe {
12059let Inst{12-12} = 0b1;
12060let Inst{31-21} = 0b10011100101;
12061let addrMode = BaseLongOffset;
12062let accessSize = WordAccess;
12063let mayLoad = 1;
12064let isExtended = 1;
12065let InputType = "imm";
12066let DecoderNamespace = "MustExtend";
12067let isExtendable = 1;
12068let opExtendable = 3;
12069let isExtentSigned = 0;
12070let opExtentBits = 6;
12071let opExtentAlign = 0;
12072}
12073def L4_loadd_aq : HInst<
12074(outs DoubleRegs:$Rdd32),
12075(ins IntRegs:$Rs32),
12076"$Rdd32 = memd_aq($Rs32)",
12077tc_2471c1c8, TypeLD>, Enc_3a3d62, Requires<[HasV68]> {
12078let Inst{13-5} = 0b011000000;
12079let Inst{31-21} = 0b10010010000;
12080let accessSize = DoubleWordAccess;
12081let mayLoad = 1;
12082}
12083def L4_loadd_locked : HInst<
12084(outs DoubleRegs:$Rdd32),
12085(ins IntRegs:$Rs32),
12086"$Rdd32 = memd_locked($Rs32)",
12087tc_64b00d8a, TypeLD>, Enc_3a3d62 {
12088let Inst{13-5} = 0b010000000;
12089let Inst{31-21} = 0b10010010000;
12090let accessSize = DoubleWordAccess;
12091let mayLoad = 1;
12092let isSoloAX = 1;
12093}
12094def L4_loadrb_ap : HInst<
12095(outs IntRegs:$Rd32, IntRegs:$Re32),
12096(ins u32_0Imm:$II),
12097"$Rd32 = memb($Re32=#$II)",
12098tc_822c3c68, TypeLD>, Enc_323f2d {
12099let Inst{7-7} = 0b0;
12100let Inst{13-12} = 0b01;
12101let Inst{31-21} = 0b10011011000;
12102let hasNewValue = 1;
12103let opNewValue = 0;
12104let addrMode = AbsoluteSet;
12105let accessSize = ByteAccess;
12106let mayLoad = 1;
12107let isExtended = 1;
12108let DecoderNamespace = "MustExtend";
12109let isExtendable = 1;
12110let opExtendable = 2;
12111let isExtentSigned = 0;
12112let opExtentBits = 6;
12113let opExtentAlign = 0;
12114}
12115def L4_loadrb_rr : HInst<
12116(outs IntRegs:$Rd32),
12117(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12118"$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12119tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12120let Inst{6-5} = 0b00;
12121let Inst{31-21} = 0b00111010000;
12122let hasNewValue = 1;
12123let opNewValue = 0;
12124let addrMode = BaseRegOffset;
12125let accessSize = ByteAccess;
12126let mayLoad = 1;
12127let BaseOpcode = "L4_loadrb_rr";
12128let CextOpcode = "L2_loadrb";
12129let InputType = "reg";
12130let isPredicable = 1;
12131}
12132def L4_loadrb_ur : HInst<
12133(outs IntRegs:$Rd32),
12134(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12135"$Rd32 = memb($Rt32<<#$Ii+#$II)",
12136tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12137let Inst{12-12} = 0b1;
12138let Inst{31-21} = 0b10011101000;
12139let hasNewValue = 1;
12140let opNewValue = 0;
12141let addrMode = BaseLongOffset;
12142let accessSize = ByteAccess;
12143let mayLoad = 1;
12144let isExtended = 1;
12145let CextOpcode = "L2_loadrb";
12146let InputType = "imm";
12147let DecoderNamespace = "MustExtend";
12148let isExtendable = 1;
12149let opExtendable = 3;
12150let isExtentSigned = 0;
12151let opExtentBits = 6;
12152let opExtentAlign = 0;
12153}
12154def L4_loadrd_ap : HInst<
12155(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12156(ins u32_0Imm:$II),
12157"$Rdd32 = memd($Re32=#$II)",
12158tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12159let Inst{7-7} = 0b0;
12160let Inst{13-12} = 0b01;
12161let Inst{31-21} = 0b10011011110;
12162let addrMode = AbsoluteSet;
12163let accessSize = DoubleWordAccess;
12164let mayLoad = 1;
12165let isExtended = 1;
12166let DecoderNamespace = "MustExtend";
12167let isExtendable = 1;
12168let opExtendable = 2;
12169let isExtentSigned = 0;
12170let opExtentBits = 6;
12171let opExtentAlign = 0;
12172}
12173def L4_loadrd_rr : HInst<
12174(outs DoubleRegs:$Rdd32),
12175(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12176"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12177tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
12178let Inst{6-5} = 0b00;
12179let Inst{31-21} = 0b00111010110;
12180let addrMode = BaseRegOffset;
12181let accessSize = DoubleWordAccess;
12182let mayLoad = 1;
12183let BaseOpcode = "L4_loadrd_rr";
12184let CextOpcode = "L2_loadrd";
12185let InputType = "reg";
12186let isPredicable = 1;
12187}
12188def L4_loadrd_ur : HInst<
12189(outs DoubleRegs:$Rdd32),
12190(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12191"$Rdd32 = memd($Rt32<<#$Ii+#$II)",
12192tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
12193let Inst{12-12} = 0b1;
12194let Inst{31-21} = 0b10011101110;
12195let addrMode = BaseLongOffset;
12196let accessSize = DoubleWordAccess;
12197let mayLoad = 1;
12198let isExtended = 1;
12199let CextOpcode = "L2_loadrd";
12200let InputType = "imm";
12201let DecoderNamespace = "MustExtend";
12202let isExtendable = 1;
12203let opExtendable = 3;
12204let isExtentSigned = 0;
12205let opExtentBits = 6;
12206let opExtentAlign = 0;
12207}
12208def L4_loadrh_ap : HInst<
12209(outs IntRegs:$Rd32, IntRegs:$Re32),
12210(ins u32_0Imm:$II),
12211"$Rd32 = memh($Re32=#$II)",
12212tc_822c3c68, TypeLD>, Enc_323f2d {
12213let Inst{7-7} = 0b0;
12214let Inst{13-12} = 0b01;
12215let Inst{31-21} = 0b10011011010;
12216let hasNewValue = 1;
12217let opNewValue = 0;
12218let addrMode = AbsoluteSet;
12219let accessSize = HalfWordAccess;
12220let mayLoad = 1;
12221let isExtended = 1;
12222let DecoderNamespace = "MustExtend";
12223let isExtendable = 1;
12224let opExtendable = 2;
12225let isExtentSigned = 0;
12226let opExtentBits = 6;
12227let opExtentAlign = 0;
12228}
12229def L4_loadrh_rr : HInst<
12230(outs IntRegs:$Rd32),
12231(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12232"$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12233tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12234let Inst{6-5} = 0b00;
12235let Inst{31-21} = 0b00111010010;
12236let hasNewValue = 1;
12237let opNewValue = 0;
12238let addrMode = BaseRegOffset;
12239let accessSize = HalfWordAccess;
12240let mayLoad = 1;
12241let BaseOpcode = "L4_loadrh_rr";
12242let CextOpcode = "L2_loadrh";
12243let InputType = "reg";
12244let isPredicable = 1;
12245}
12246def L4_loadrh_ur : HInst<
12247(outs IntRegs:$Rd32),
12248(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12249"$Rd32 = memh($Rt32<<#$Ii+#$II)",
12250tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12251let Inst{12-12} = 0b1;
12252let Inst{31-21} = 0b10011101010;
12253let hasNewValue = 1;
12254let opNewValue = 0;
12255let addrMode = BaseLongOffset;
12256let accessSize = HalfWordAccess;
12257let mayLoad = 1;
12258let isExtended = 1;
12259let CextOpcode = "L2_loadrh";
12260let InputType = "imm";
12261let DecoderNamespace = "MustExtend";
12262let isExtendable = 1;
12263let opExtendable = 3;
12264let isExtentSigned = 0;
12265let opExtentBits = 6;
12266let opExtentAlign = 0;
12267}
12268def L4_loadri_ap : HInst<
12269(outs IntRegs:$Rd32, IntRegs:$Re32),
12270(ins u32_0Imm:$II),
12271"$Rd32 = memw($Re32=#$II)",
12272tc_822c3c68, TypeLD>, Enc_323f2d {
12273let Inst{7-7} = 0b0;
12274let Inst{13-12} = 0b01;
12275let Inst{31-21} = 0b10011011100;
12276let hasNewValue = 1;
12277let opNewValue = 0;
12278let addrMode = AbsoluteSet;
12279let accessSize = WordAccess;
12280let mayLoad = 1;
12281let isExtended = 1;
12282let DecoderNamespace = "MustExtend";
12283let isExtendable = 1;
12284let opExtendable = 2;
12285let isExtentSigned = 0;
12286let opExtentBits = 6;
12287let opExtentAlign = 0;
12288}
12289def L4_loadri_rr : HInst<
12290(outs IntRegs:$Rd32),
12291(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12292"$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12293tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12294let Inst{6-5} = 0b00;
12295let Inst{31-21} = 0b00111010100;
12296let hasNewValue = 1;
12297let opNewValue = 0;
12298let addrMode = BaseRegOffset;
12299let accessSize = WordAccess;
12300let mayLoad = 1;
12301let BaseOpcode = "L4_loadri_rr";
12302let CextOpcode = "L2_loadri";
12303let InputType = "reg";
12304let isPredicable = 1;
12305}
12306def L4_loadri_ur : HInst<
12307(outs IntRegs:$Rd32),
12308(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12309"$Rd32 = memw($Rt32<<#$Ii+#$II)",
12310tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12311let Inst{12-12} = 0b1;
12312let Inst{31-21} = 0b10011101100;
12313let hasNewValue = 1;
12314let opNewValue = 0;
12315let addrMode = BaseLongOffset;
12316let accessSize = WordAccess;
12317let mayLoad = 1;
12318let isExtended = 1;
12319let CextOpcode = "L2_loadri";
12320let InputType = "imm";
12321let DecoderNamespace = "MustExtend";
12322let isExtendable = 1;
12323let opExtendable = 3;
12324let isExtentSigned = 0;
12325let opExtentBits = 6;
12326let opExtentAlign = 0;
12327}
12328def L4_loadrub_ap : HInst<
12329(outs IntRegs:$Rd32, IntRegs:$Re32),
12330(ins u32_0Imm:$II),
12331"$Rd32 = memub($Re32=#$II)",
12332tc_822c3c68, TypeLD>, Enc_323f2d {
12333let Inst{7-7} = 0b0;
12334let Inst{13-12} = 0b01;
12335let Inst{31-21} = 0b10011011001;
12336let hasNewValue = 1;
12337let opNewValue = 0;
12338let addrMode = AbsoluteSet;
12339let accessSize = ByteAccess;
12340let mayLoad = 1;
12341let isExtended = 1;
12342let DecoderNamespace = "MustExtend";
12343let isExtendable = 1;
12344let opExtendable = 2;
12345let isExtentSigned = 0;
12346let opExtentBits = 6;
12347let opExtentAlign = 0;
12348}
12349def L4_loadrub_rr : HInst<
12350(outs IntRegs:$Rd32),
12351(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12352"$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12353tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12354let Inst{6-5} = 0b00;
12355let Inst{31-21} = 0b00111010001;
12356let hasNewValue = 1;
12357let opNewValue = 0;
12358let addrMode = BaseRegOffset;
12359let accessSize = ByteAccess;
12360let mayLoad = 1;
12361let BaseOpcode = "L4_loadrub_rr";
12362let CextOpcode = "L2_loadrub";
12363let InputType = "reg";
12364let isPredicable = 1;
12365}
12366def L4_loadrub_ur : HInst<
12367(outs IntRegs:$Rd32),
12368(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12369"$Rd32 = memub($Rt32<<#$Ii+#$II)",
12370tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12371let Inst{12-12} = 0b1;
12372let Inst{31-21} = 0b10011101001;
12373let hasNewValue = 1;
12374let opNewValue = 0;
12375let addrMode = BaseLongOffset;
12376let accessSize = ByteAccess;
12377let mayLoad = 1;
12378let isExtended = 1;
12379let CextOpcode = "L2_loadrub";
12380let InputType = "imm";
12381let DecoderNamespace = "MustExtend";
12382let isExtendable = 1;
12383let opExtendable = 3;
12384let isExtentSigned = 0;
12385let opExtentBits = 6;
12386let opExtentAlign = 0;
12387}
12388def L4_loadruh_ap : HInst<
12389(outs IntRegs:$Rd32, IntRegs:$Re32),
12390(ins u32_0Imm:$II),
12391"$Rd32 = memuh($Re32=#$II)",
12392tc_822c3c68, TypeLD>, Enc_323f2d {
12393let Inst{7-7} = 0b0;
12394let Inst{13-12} = 0b01;
12395let Inst{31-21} = 0b10011011011;
12396let hasNewValue = 1;
12397let opNewValue = 0;
12398let addrMode = AbsoluteSet;
12399let accessSize = HalfWordAccess;
12400let mayLoad = 1;
12401let isExtended = 1;
12402let DecoderNamespace = "MustExtend";
12403let isExtendable = 1;
12404let opExtendable = 2;
12405let isExtentSigned = 0;
12406let opExtentBits = 6;
12407let opExtentAlign = 0;
12408}
12409def L4_loadruh_rr : HInst<
12410(outs IntRegs:$Rd32),
12411(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12412"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
12413tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12414let Inst{6-5} = 0b00;
12415let Inst{31-21} = 0b00111010011;
12416let hasNewValue = 1;
12417let opNewValue = 0;
12418let addrMode = BaseRegOffset;
12419let accessSize = HalfWordAccess;
12420let mayLoad = 1;
12421let BaseOpcode = "L4_loadruh_rr";
12422let CextOpcode = "L2_loadruh";
12423let InputType = "reg";
12424let isPredicable = 1;
12425}
12426def L4_loadruh_ur : HInst<
12427(outs IntRegs:$Rd32),
12428(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12429"$Rd32 = memuh($Rt32<<#$Ii+#$II)",
12430tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12431let Inst{12-12} = 0b1;
12432let Inst{31-21} = 0b10011101011;
12433let hasNewValue = 1;
12434let opNewValue = 0;
12435let addrMode = BaseLongOffset;
12436let accessSize = HalfWordAccess;
12437let mayLoad = 1;
12438let isExtended = 1;
12439let CextOpcode = "L2_loadruh";
12440let InputType = "imm";
12441let DecoderNamespace = "MustExtend";
12442let isExtendable = 1;
12443let opExtendable = 3;
12444let isExtentSigned = 0;
12445let opExtentBits = 6;
12446let opExtentAlign = 0;
12447}
12448def L4_or_memopb_io : HInst<
12449(outs),
12450(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
12451"memb($Rs32+#$Ii) |= $Rt32",
12452tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
12453let Inst{6-5} = 0b11;
12454let Inst{13-13} = 0b0;
12455let Inst{31-21} = 0b00111110000;
12456let addrMode = BaseImmOffset;
12457let accessSize = ByteAccess;
12458let mayLoad = 1;
12459let isRestrictNoSlot1Store = 1;
12460let mayStore = 1;
12461let isExtendable = 1;
12462let opExtendable = 1;
12463let isExtentSigned = 0;
12464let opExtentBits = 6;
12465let opExtentAlign = 0;
12466}
12467def L4_or_memopb_zomap : HInst<
12468(outs),
12469(ins IntRegs:$Rs32, IntRegs:$Rt32),
12470"memb($Rs32) |= $Rt32",
12471tc_9bcfb2ee, TypeMAPPING> {
12472let isPseudo = 1;
12473let isCodeGenOnly = 1;
12474}
12475def L4_or_memoph_io : HInst<
12476(outs),
12477(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
12478"memh($Rs32+#$Ii) |= $Rt32",
12479tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
12480let Inst{6-5} = 0b11;
12481let Inst{13-13} = 0b0;
12482let Inst{31-21} = 0b00111110001;
12483let addrMode = BaseImmOffset;
12484let accessSize = HalfWordAccess;
12485let mayLoad = 1;
12486let isRestrictNoSlot1Store = 1;
12487let mayStore = 1;
12488let isExtendable = 1;
12489let opExtendable = 1;
12490let isExtentSigned = 0;
12491let opExtentBits = 7;
12492let opExtentAlign = 1;
12493}
12494def L4_or_memoph_zomap : HInst<
12495(outs),
12496(ins IntRegs:$Rs32, IntRegs:$Rt32),
12497"memh($Rs32) |= $Rt32",
12498tc_9bcfb2ee, TypeMAPPING> {
12499let isPseudo = 1;
12500let isCodeGenOnly = 1;
12501}
12502def L4_or_memopw_io : HInst<
12503(outs),
12504(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
12505"memw($Rs32+#$Ii) |= $Rt32",
12506tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
12507let Inst{6-5} = 0b11;
12508let Inst{13-13} = 0b0;
12509let Inst{31-21} = 0b00111110010;
12510let addrMode = BaseImmOffset;
12511let accessSize = WordAccess;
12512let mayLoad = 1;
12513let isRestrictNoSlot1Store = 1;
12514let mayStore = 1;
12515let isExtendable = 1;
12516let opExtendable = 1;
12517let isExtentSigned = 0;
12518let opExtentBits = 8;
12519let opExtentAlign = 2;
12520}
12521def L4_or_memopw_zomap : HInst<
12522(outs),
12523(ins IntRegs:$Rs32, IntRegs:$Rt32),
12524"memw($Rs32) |= $Rt32",
12525tc_9bcfb2ee, TypeMAPPING> {
12526let isPseudo = 1;
12527let isCodeGenOnly = 1;
12528}
12529def L4_ploadrbf_abs : HInst<
12530(outs IntRegs:$Rd32),
12531(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12532"if (!$Pt4) $Rd32 = memb(#$Ii)",
12533tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12534let Inst{7-5} = 0b100;
12535let Inst{13-11} = 0b101;
12536let Inst{31-21} = 0b10011111000;
12537let isPredicated = 1;
12538let isPredicatedFalse = 1;
12539let hasNewValue = 1;
12540let opNewValue = 0;
12541let addrMode = Absolute;
12542let accessSize = ByteAccess;
12543let mayLoad = 1;
12544let isExtended = 1;
12545let BaseOpcode = "L4_loadrb_abs";
12546let CextOpcode = "L2_loadrb";
12547let DecoderNamespace = "MustExtend";
12548let isExtendable = 1;
12549let opExtendable = 2;
12550let isExtentSigned = 0;
12551let opExtentBits = 6;
12552let opExtentAlign = 0;
12553}
12554def L4_ploadrbf_rr : HInst<
12555(outs IntRegs:$Rd32),
12556(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12557"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12558tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12559let Inst{31-21} = 0b00110001000;
12560let isPredicated = 1;
12561let isPredicatedFalse = 1;
12562let hasNewValue = 1;
12563let opNewValue = 0;
12564let addrMode = BaseRegOffset;
12565let accessSize = ByteAccess;
12566let mayLoad = 1;
12567let BaseOpcode = "L4_loadrb_rr";
12568let CextOpcode = "L2_loadrb";
12569let InputType = "reg";
12570}
12571def L4_ploadrbfnew_abs : HInst<
12572(outs IntRegs:$Rd32),
12573(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12574"if (!$Pt4.new) $Rd32 = memb(#$Ii)",
12575tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12576let Inst{7-5} = 0b100;
12577let Inst{13-11} = 0b111;
12578let Inst{31-21} = 0b10011111000;
12579let isPredicated = 1;
12580let isPredicatedFalse = 1;
12581let hasNewValue = 1;
12582let opNewValue = 0;
12583let addrMode = Absolute;
12584let accessSize = ByteAccess;
12585let isPredicatedNew = 1;
12586let mayLoad = 1;
12587let isExtended = 1;
12588let BaseOpcode = "L4_loadrb_abs";
12589let CextOpcode = "L2_loadrb";
12590let DecoderNamespace = "MustExtend";
12591let isExtendable = 1;
12592let opExtendable = 2;
12593let isExtentSigned = 0;
12594let opExtentBits = 6;
12595let opExtentAlign = 0;
12596}
12597def L4_ploadrbfnew_rr : HInst<
12598(outs IntRegs:$Rd32),
12599(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12600"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12601tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12602let Inst{31-21} = 0b00110011000;
12603let isPredicated = 1;
12604let isPredicatedFalse = 1;
12605let hasNewValue = 1;
12606let opNewValue = 0;
12607let addrMode = BaseRegOffset;
12608let accessSize = ByteAccess;
12609let isPredicatedNew = 1;
12610let mayLoad = 1;
12611let BaseOpcode = "L4_loadrb_rr";
12612let CextOpcode = "L2_loadrb";
12613let InputType = "reg";
12614}
12615def L4_ploadrbt_abs : HInst<
12616(outs IntRegs:$Rd32),
12617(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12618"if ($Pt4) $Rd32 = memb(#$Ii)",
12619tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12620let Inst{7-5} = 0b100;
12621let Inst{13-11} = 0b100;
12622let Inst{31-21} = 0b10011111000;
12623let isPredicated = 1;
12624let hasNewValue = 1;
12625let opNewValue = 0;
12626let addrMode = Absolute;
12627let accessSize = ByteAccess;
12628let mayLoad = 1;
12629let isExtended = 1;
12630let BaseOpcode = "L4_loadrb_abs";
12631let CextOpcode = "L2_loadrb";
12632let DecoderNamespace = "MustExtend";
12633let isExtendable = 1;
12634let opExtendable = 2;
12635let isExtentSigned = 0;
12636let opExtentBits = 6;
12637let opExtentAlign = 0;
12638}
12639def L4_ploadrbt_rr : HInst<
12640(outs IntRegs:$Rd32),
12641(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12642"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12643tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12644let Inst{31-21} = 0b00110000000;
12645let isPredicated = 1;
12646let hasNewValue = 1;
12647let opNewValue = 0;
12648let addrMode = BaseRegOffset;
12649let accessSize = ByteAccess;
12650let mayLoad = 1;
12651let BaseOpcode = "L4_loadrb_rr";
12652let CextOpcode = "L2_loadrb";
12653let InputType = "reg";
12654}
12655def L4_ploadrbtnew_abs : HInst<
12656(outs IntRegs:$Rd32),
12657(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12658"if ($Pt4.new) $Rd32 = memb(#$Ii)",
12659tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12660let Inst{7-5} = 0b100;
12661let Inst{13-11} = 0b110;
12662let Inst{31-21} = 0b10011111000;
12663let isPredicated = 1;
12664let hasNewValue = 1;
12665let opNewValue = 0;
12666let addrMode = Absolute;
12667let accessSize = ByteAccess;
12668let isPredicatedNew = 1;
12669let mayLoad = 1;
12670let isExtended = 1;
12671let BaseOpcode = "L4_loadrb_abs";
12672let CextOpcode = "L2_loadrb";
12673let DecoderNamespace = "MustExtend";
12674let isExtendable = 1;
12675let opExtendable = 2;
12676let isExtentSigned = 0;
12677let opExtentBits = 6;
12678let opExtentAlign = 0;
12679}
12680def L4_ploadrbtnew_rr : HInst<
12681(outs IntRegs:$Rd32),
12682(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12683"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12684tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12685let Inst{31-21} = 0b00110010000;
12686let isPredicated = 1;
12687let hasNewValue = 1;
12688let opNewValue = 0;
12689let addrMode = BaseRegOffset;
12690let accessSize = ByteAccess;
12691let isPredicatedNew = 1;
12692let mayLoad = 1;
12693let BaseOpcode = "L4_loadrb_rr";
12694let CextOpcode = "L2_loadrb";
12695let InputType = "reg";
12696}
12697def L4_ploadrdf_abs : HInst<
12698(outs DoubleRegs:$Rdd32),
12699(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12700"if (!$Pt4) $Rdd32 = memd(#$Ii)",
12701tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12702let Inst{7-5} = 0b100;
12703let Inst{13-11} = 0b101;
12704let Inst{31-21} = 0b10011111110;
12705let isPredicated = 1;
12706let isPredicatedFalse = 1;
12707let addrMode = Absolute;
12708let accessSize = DoubleWordAccess;
12709let mayLoad = 1;
12710let isExtended = 1;
12711let BaseOpcode = "L4_loadrd_abs";
12712let CextOpcode = "L2_loadrd";
12713let DecoderNamespace = "MustExtend";
12714let isExtendable = 1;
12715let opExtendable = 2;
12716let isExtentSigned = 0;
12717let opExtentBits = 6;
12718let opExtentAlign = 0;
12719}
12720def L4_ploadrdf_rr : HInst<
12721(outs DoubleRegs:$Rdd32),
12722(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12723"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12724tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12725let Inst{31-21} = 0b00110001110;
12726let isPredicated = 1;
12727let isPredicatedFalse = 1;
12728let addrMode = BaseRegOffset;
12729let accessSize = DoubleWordAccess;
12730let mayLoad = 1;
12731let BaseOpcode = "L4_loadrd_rr";
12732let CextOpcode = "L2_loadrd";
12733let InputType = "reg";
12734}
12735def L4_ploadrdfnew_abs : HInst<
12736(outs DoubleRegs:$Rdd32),
12737(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12738"if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
12739tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12740let Inst{7-5} = 0b100;
12741let Inst{13-11} = 0b111;
12742let Inst{31-21} = 0b10011111110;
12743let isPredicated = 1;
12744let isPredicatedFalse = 1;
12745let addrMode = Absolute;
12746let accessSize = DoubleWordAccess;
12747let isPredicatedNew = 1;
12748let mayLoad = 1;
12749let isExtended = 1;
12750let BaseOpcode = "L4_loadrd_abs";
12751let CextOpcode = "L2_loadrd";
12752let DecoderNamespace = "MustExtend";
12753let isExtendable = 1;
12754let opExtendable = 2;
12755let isExtentSigned = 0;
12756let opExtentBits = 6;
12757let opExtentAlign = 0;
12758}
12759def L4_ploadrdfnew_rr : HInst<
12760(outs DoubleRegs:$Rdd32),
12761(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12762"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12763tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12764let Inst{31-21} = 0b00110011110;
12765let isPredicated = 1;
12766let isPredicatedFalse = 1;
12767let addrMode = BaseRegOffset;
12768let accessSize = DoubleWordAccess;
12769let isPredicatedNew = 1;
12770let mayLoad = 1;
12771let BaseOpcode = "L4_loadrd_rr";
12772let CextOpcode = "L2_loadrd";
12773let InputType = "reg";
12774}
12775def L4_ploadrdt_abs : HInst<
12776(outs DoubleRegs:$Rdd32),
12777(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12778"if ($Pt4) $Rdd32 = memd(#$Ii)",
12779tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12780let Inst{7-5} = 0b100;
12781let Inst{13-11} = 0b100;
12782let Inst{31-21} = 0b10011111110;
12783let isPredicated = 1;
12784let addrMode = Absolute;
12785let accessSize = DoubleWordAccess;
12786let mayLoad = 1;
12787let isExtended = 1;
12788let BaseOpcode = "L4_loadrd_abs";
12789let CextOpcode = "L2_loadrd";
12790let DecoderNamespace = "MustExtend";
12791let isExtendable = 1;
12792let opExtendable = 2;
12793let isExtentSigned = 0;
12794let opExtentBits = 6;
12795let opExtentAlign = 0;
12796}
12797def L4_ploadrdt_rr : HInst<
12798(outs DoubleRegs:$Rdd32),
12799(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12800"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12801tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12802let Inst{31-21} = 0b00110000110;
12803let isPredicated = 1;
12804let addrMode = BaseRegOffset;
12805let accessSize = DoubleWordAccess;
12806let mayLoad = 1;
12807let BaseOpcode = "L4_loadrd_rr";
12808let CextOpcode = "L2_loadrd";
12809let InputType = "reg";
12810}
12811def L4_ploadrdtnew_abs : HInst<
12812(outs DoubleRegs:$Rdd32),
12813(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12814"if ($Pt4.new) $Rdd32 = memd(#$Ii)",
12815tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12816let Inst{7-5} = 0b100;
12817let Inst{13-11} = 0b110;
12818let Inst{31-21} = 0b10011111110;
12819let isPredicated = 1;
12820let addrMode = Absolute;
12821let accessSize = DoubleWordAccess;
12822let isPredicatedNew = 1;
12823let mayLoad = 1;
12824let isExtended = 1;
12825let BaseOpcode = "L4_loadrd_abs";
12826let CextOpcode = "L2_loadrd";
12827let DecoderNamespace = "MustExtend";
12828let isExtendable = 1;
12829let opExtendable = 2;
12830let isExtentSigned = 0;
12831let opExtentBits = 6;
12832let opExtentAlign = 0;
12833}
12834def L4_ploadrdtnew_rr : HInst<
12835(outs DoubleRegs:$Rdd32),
12836(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12837"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12838tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12839let Inst{31-21} = 0b00110010110;
12840let isPredicated = 1;
12841let addrMode = BaseRegOffset;
12842let accessSize = DoubleWordAccess;
12843let isPredicatedNew = 1;
12844let mayLoad = 1;
12845let BaseOpcode = "L4_loadrd_rr";
12846let CextOpcode = "L2_loadrd";
12847let InputType = "reg";
12848}
12849def L4_ploadrhf_abs : HInst<
12850(outs IntRegs:$Rd32),
12851(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12852"if (!$Pt4) $Rd32 = memh(#$Ii)",
12853tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12854let Inst{7-5} = 0b100;
12855let Inst{13-11} = 0b101;
12856let Inst{31-21} = 0b10011111010;
12857let isPredicated = 1;
12858let isPredicatedFalse = 1;
12859let hasNewValue = 1;
12860let opNewValue = 0;
12861let addrMode = Absolute;
12862let accessSize = HalfWordAccess;
12863let mayLoad = 1;
12864let isExtended = 1;
12865let BaseOpcode = "L4_loadrh_abs";
12866let CextOpcode = "L2_loadrh";
12867let DecoderNamespace = "MustExtend";
12868let isExtendable = 1;
12869let opExtendable = 2;
12870let isExtentSigned = 0;
12871let opExtentBits = 6;
12872let opExtentAlign = 0;
12873}
12874def L4_ploadrhf_rr : HInst<
12875(outs IntRegs:$Rd32),
12876(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12877"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12878tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12879let Inst{31-21} = 0b00110001010;
12880let isPredicated = 1;
12881let isPredicatedFalse = 1;
12882let hasNewValue = 1;
12883let opNewValue = 0;
12884let addrMode = BaseRegOffset;
12885let accessSize = HalfWordAccess;
12886let mayLoad = 1;
12887let BaseOpcode = "L4_loadrh_rr";
12888let CextOpcode = "L2_loadrh";
12889let InputType = "reg";
12890}
12891def L4_ploadrhfnew_abs : HInst<
12892(outs IntRegs:$Rd32),
12893(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12894"if (!$Pt4.new) $Rd32 = memh(#$Ii)",
12895tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12896let Inst{7-5} = 0b100;
12897let Inst{13-11} = 0b111;
12898let Inst{31-21} = 0b10011111010;
12899let isPredicated = 1;
12900let isPredicatedFalse = 1;
12901let hasNewValue = 1;
12902let opNewValue = 0;
12903let addrMode = Absolute;
12904let accessSize = HalfWordAccess;
12905let isPredicatedNew = 1;
12906let mayLoad = 1;
12907let isExtended = 1;
12908let BaseOpcode = "L4_loadrh_abs";
12909let CextOpcode = "L2_loadrh";
12910let DecoderNamespace = "MustExtend";
12911let isExtendable = 1;
12912let opExtendable = 2;
12913let isExtentSigned = 0;
12914let opExtentBits = 6;
12915let opExtentAlign = 0;
12916}
12917def L4_ploadrhfnew_rr : HInst<
12918(outs IntRegs:$Rd32),
12919(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12920"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12921tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12922let Inst{31-21} = 0b00110011010;
12923let isPredicated = 1;
12924let isPredicatedFalse = 1;
12925let hasNewValue = 1;
12926let opNewValue = 0;
12927let addrMode = BaseRegOffset;
12928let accessSize = HalfWordAccess;
12929let isPredicatedNew = 1;
12930let mayLoad = 1;
12931let BaseOpcode = "L4_loadrh_rr";
12932let CextOpcode = "L2_loadrh";
12933let InputType = "reg";
12934}
12935def L4_ploadrht_abs : HInst<
12936(outs IntRegs:$Rd32),
12937(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12938"if ($Pt4) $Rd32 = memh(#$Ii)",
12939tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12940let Inst{7-5} = 0b100;
12941let Inst{13-11} = 0b100;
12942let Inst{31-21} = 0b10011111010;
12943let isPredicated = 1;
12944let hasNewValue = 1;
12945let opNewValue = 0;
12946let addrMode = Absolute;
12947let accessSize = HalfWordAccess;
12948let mayLoad = 1;
12949let isExtended = 1;
12950let BaseOpcode = "L4_loadrh_abs";
12951let CextOpcode = "L2_loadrh";
12952let DecoderNamespace = "MustExtend";
12953let isExtendable = 1;
12954let opExtendable = 2;
12955let isExtentSigned = 0;
12956let opExtentBits = 6;
12957let opExtentAlign = 0;
12958}
12959def L4_ploadrht_rr : HInst<
12960(outs IntRegs:$Rd32),
12961(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12962"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12963tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12964let Inst{31-21} = 0b00110000010;
12965let isPredicated = 1;
12966let hasNewValue = 1;
12967let opNewValue = 0;
12968let addrMode = BaseRegOffset;
12969let accessSize = HalfWordAccess;
12970let mayLoad = 1;
12971let BaseOpcode = "L4_loadrh_rr";
12972let CextOpcode = "L2_loadrh";
12973let InputType = "reg";
12974}
12975def L4_ploadrhtnew_abs : HInst<
12976(outs IntRegs:$Rd32),
12977(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12978"if ($Pt4.new) $Rd32 = memh(#$Ii)",
12979tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12980let Inst{7-5} = 0b100;
12981let Inst{13-11} = 0b110;
12982let Inst{31-21} = 0b10011111010;
12983let isPredicated = 1;
12984let hasNewValue = 1;
12985let opNewValue = 0;
12986let addrMode = Absolute;
12987let accessSize = HalfWordAccess;
12988let isPredicatedNew = 1;
12989let mayLoad = 1;
12990let isExtended = 1;
12991let BaseOpcode = "L4_loadrh_abs";
12992let CextOpcode = "L2_loadrh";
12993let DecoderNamespace = "MustExtend";
12994let isExtendable = 1;
12995let opExtendable = 2;
12996let isExtentSigned = 0;
12997let opExtentBits = 6;
12998let opExtentAlign = 0;
12999}
13000def L4_ploadrhtnew_rr : HInst<
13001(outs IntRegs:$Rd32),
13002(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13003"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
13004tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13005let Inst{31-21} = 0b00110010010;
13006let isPredicated = 1;
13007let hasNewValue = 1;
13008let opNewValue = 0;
13009let addrMode = BaseRegOffset;
13010let accessSize = HalfWordAccess;
13011let isPredicatedNew = 1;
13012let mayLoad = 1;
13013let BaseOpcode = "L4_loadrh_rr";
13014let CextOpcode = "L2_loadrh";
13015let InputType = "reg";
13016}
13017def L4_ploadrif_abs : HInst<
13018(outs IntRegs:$Rd32),
13019(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13020"if (!$Pt4) $Rd32 = memw(#$Ii)",
13021tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13022let Inst{7-5} = 0b100;
13023let Inst{13-11} = 0b101;
13024let Inst{31-21} = 0b10011111100;
13025let isPredicated = 1;
13026let isPredicatedFalse = 1;
13027let hasNewValue = 1;
13028let opNewValue = 0;
13029let addrMode = Absolute;
13030let accessSize = WordAccess;
13031let mayLoad = 1;
13032let isExtended = 1;
13033let BaseOpcode = "L4_loadri_abs";
13034let CextOpcode = "L2_loadri";
13035let DecoderNamespace = "MustExtend";
13036let isExtendable = 1;
13037let opExtendable = 2;
13038let isExtentSigned = 0;
13039let opExtentBits = 6;
13040let opExtentAlign = 0;
13041}
13042def L4_ploadrif_rr : HInst<
13043(outs IntRegs:$Rd32),
13044(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13045"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13046tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13047let Inst{31-21} = 0b00110001100;
13048let isPredicated = 1;
13049let isPredicatedFalse = 1;
13050let hasNewValue = 1;
13051let opNewValue = 0;
13052let addrMode = BaseRegOffset;
13053let accessSize = WordAccess;
13054let mayLoad = 1;
13055let BaseOpcode = "L4_loadri_rr";
13056let CextOpcode = "L2_loadri";
13057let InputType = "reg";
13058}
13059def L4_ploadrifnew_abs : HInst<
13060(outs IntRegs:$Rd32),
13061(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13062"if (!$Pt4.new) $Rd32 = memw(#$Ii)",
13063tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13064let Inst{7-5} = 0b100;
13065let Inst{13-11} = 0b111;
13066let Inst{31-21} = 0b10011111100;
13067let isPredicated = 1;
13068let isPredicatedFalse = 1;
13069let hasNewValue = 1;
13070let opNewValue = 0;
13071let addrMode = Absolute;
13072let accessSize = WordAccess;
13073let isPredicatedNew = 1;
13074let mayLoad = 1;
13075let isExtended = 1;
13076let BaseOpcode = "L4_loadri_abs";
13077let CextOpcode = "L2_loadri";
13078let DecoderNamespace = "MustExtend";
13079let isExtendable = 1;
13080let opExtendable = 2;
13081let isExtentSigned = 0;
13082let opExtentBits = 6;
13083let opExtentAlign = 0;
13084}
13085def L4_ploadrifnew_rr : HInst<
13086(outs IntRegs:$Rd32),
13087(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13088"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13089tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13090let Inst{31-21} = 0b00110011100;
13091let isPredicated = 1;
13092let isPredicatedFalse = 1;
13093let hasNewValue = 1;
13094let opNewValue = 0;
13095let addrMode = BaseRegOffset;
13096let accessSize = WordAccess;
13097let isPredicatedNew = 1;
13098let mayLoad = 1;
13099let BaseOpcode = "L4_loadri_rr";
13100let CextOpcode = "L2_loadri";
13101let InputType = "reg";
13102}
13103def L4_ploadrit_abs : HInst<
13104(outs IntRegs:$Rd32),
13105(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13106"if ($Pt4) $Rd32 = memw(#$Ii)",
13107tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13108let Inst{7-5} = 0b100;
13109let Inst{13-11} = 0b100;
13110let Inst{31-21} = 0b10011111100;
13111let isPredicated = 1;
13112let hasNewValue = 1;
13113let opNewValue = 0;
13114let addrMode = Absolute;
13115let accessSize = WordAccess;
13116let mayLoad = 1;
13117let isExtended = 1;
13118let BaseOpcode = "L4_loadri_abs";
13119let CextOpcode = "L2_loadri";
13120let DecoderNamespace = "MustExtend";
13121let isExtendable = 1;
13122let opExtendable = 2;
13123let isExtentSigned = 0;
13124let opExtentBits = 6;
13125let opExtentAlign = 0;
13126}
13127def L4_ploadrit_rr : HInst<
13128(outs IntRegs:$Rd32),
13129(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13130"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13131tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13132let Inst{31-21} = 0b00110000100;
13133let isPredicated = 1;
13134let hasNewValue = 1;
13135let opNewValue = 0;
13136let addrMode = BaseRegOffset;
13137let accessSize = WordAccess;
13138let mayLoad = 1;
13139let BaseOpcode = "L4_loadri_rr";
13140let CextOpcode = "L2_loadri";
13141let InputType = "reg";
13142}
13143def L4_ploadritnew_abs : HInst<
13144(outs IntRegs:$Rd32),
13145(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13146"if ($Pt4.new) $Rd32 = memw(#$Ii)",
13147tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13148let Inst{7-5} = 0b100;
13149let Inst{13-11} = 0b110;
13150let Inst{31-21} = 0b10011111100;
13151let isPredicated = 1;
13152let hasNewValue = 1;
13153let opNewValue = 0;
13154let addrMode = Absolute;
13155let accessSize = WordAccess;
13156let isPredicatedNew = 1;
13157let mayLoad = 1;
13158let isExtended = 1;
13159let BaseOpcode = "L4_loadri_abs";
13160let CextOpcode = "L2_loadri";
13161let DecoderNamespace = "MustExtend";
13162let isExtendable = 1;
13163let opExtendable = 2;
13164let isExtentSigned = 0;
13165let opExtentBits = 6;
13166let opExtentAlign = 0;
13167}
13168def L4_ploadritnew_rr : HInst<
13169(outs IntRegs:$Rd32),
13170(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13171"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13172tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13173let Inst{31-21} = 0b00110010100;
13174let isPredicated = 1;
13175let hasNewValue = 1;
13176let opNewValue = 0;
13177let addrMode = BaseRegOffset;
13178let accessSize = WordAccess;
13179let isPredicatedNew = 1;
13180let mayLoad = 1;
13181let BaseOpcode = "L4_loadri_rr";
13182let CextOpcode = "L2_loadri";
13183let InputType = "reg";
13184}
13185def L4_ploadrubf_abs : HInst<
13186(outs IntRegs:$Rd32),
13187(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13188"if (!$Pt4) $Rd32 = memub(#$Ii)",
13189tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13190let Inst{7-5} = 0b100;
13191let Inst{13-11} = 0b101;
13192let Inst{31-21} = 0b10011111001;
13193let isPredicated = 1;
13194let isPredicatedFalse = 1;
13195let hasNewValue = 1;
13196let opNewValue = 0;
13197let addrMode = Absolute;
13198let accessSize = ByteAccess;
13199let mayLoad = 1;
13200let isExtended = 1;
13201let BaseOpcode = "L4_loadrub_abs";
13202let CextOpcode = "L2_loadrub";
13203let DecoderNamespace = "MustExtend";
13204let isExtendable = 1;
13205let opExtendable = 2;
13206let isExtentSigned = 0;
13207let opExtentBits = 6;
13208let opExtentAlign = 0;
13209}
13210def L4_ploadrubf_rr : HInst<
13211(outs IntRegs:$Rd32),
13212(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13213"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13214tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13215let Inst{31-21} = 0b00110001001;
13216let isPredicated = 1;
13217let isPredicatedFalse = 1;
13218let hasNewValue = 1;
13219let opNewValue = 0;
13220let addrMode = BaseRegOffset;
13221let accessSize = ByteAccess;
13222let mayLoad = 1;
13223let BaseOpcode = "L4_loadrub_rr";
13224let CextOpcode = "L2_loadrub";
13225let InputType = "reg";
13226}
13227def L4_ploadrubfnew_abs : HInst<
13228(outs IntRegs:$Rd32),
13229(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13230"if (!$Pt4.new) $Rd32 = memub(#$Ii)",
13231tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13232let Inst{7-5} = 0b100;
13233let Inst{13-11} = 0b111;
13234let Inst{31-21} = 0b10011111001;
13235let isPredicated = 1;
13236let isPredicatedFalse = 1;
13237let hasNewValue = 1;
13238let opNewValue = 0;
13239let addrMode = Absolute;
13240let accessSize = ByteAccess;
13241let isPredicatedNew = 1;
13242let mayLoad = 1;
13243let isExtended = 1;
13244let BaseOpcode = "L4_loadrub_abs";
13245let CextOpcode = "L2_loadrub";
13246let DecoderNamespace = "MustExtend";
13247let isExtendable = 1;
13248let opExtendable = 2;
13249let isExtentSigned = 0;
13250let opExtentBits = 6;
13251let opExtentAlign = 0;
13252}
13253def L4_ploadrubfnew_rr : HInst<
13254(outs IntRegs:$Rd32),
13255(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13256"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13257tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13258let Inst{31-21} = 0b00110011001;
13259let isPredicated = 1;
13260let isPredicatedFalse = 1;
13261let hasNewValue = 1;
13262let opNewValue = 0;
13263let addrMode = BaseRegOffset;
13264let accessSize = ByteAccess;
13265let isPredicatedNew = 1;
13266let mayLoad = 1;
13267let BaseOpcode = "L4_loadrub_rr";
13268let CextOpcode = "L2_loadrub";
13269let InputType = "reg";
13270}
13271def L4_ploadrubt_abs : HInst<
13272(outs IntRegs:$Rd32),
13273(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13274"if ($Pt4) $Rd32 = memub(#$Ii)",
13275tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13276let Inst{7-5} = 0b100;
13277let Inst{13-11} = 0b100;
13278let Inst{31-21} = 0b10011111001;
13279let isPredicated = 1;
13280let hasNewValue = 1;
13281let opNewValue = 0;
13282let addrMode = Absolute;
13283let accessSize = ByteAccess;
13284let mayLoad = 1;
13285let isExtended = 1;
13286let BaseOpcode = "L4_loadrub_abs";
13287let CextOpcode = "L2_loadrub";
13288let DecoderNamespace = "MustExtend";
13289let isExtendable = 1;
13290let opExtendable = 2;
13291let isExtentSigned = 0;
13292let opExtentBits = 6;
13293let opExtentAlign = 0;
13294}
13295def L4_ploadrubt_rr : HInst<
13296(outs IntRegs:$Rd32),
13297(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13298"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13299tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13300let Inst{31-21} = 0b00110000001;
13301let isPredicated = 1;
13302let hasNewValue = 1;
13303let opNewValue = 0;
13304let addrMode = BaseRegOffset;
13305let accessSize = ByteAccess;
13306let mayLoad = 1;
13307let BaseOpcode = "L4_loadrub_rr";
13308let CextOpcode = "L2_loadrub";
13309let InputType = "reg";
13310}
13311def L4_ploadrubtnew_abs : HInst<
13312(outs IntRegs:$Rd32),
13313(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13314"if ($Pt4.new) $Rd32 = memub(#$Ii)",
13315tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13316let Inst{7-5} = 0b100;
13317let Inst{13-11} = 0b110;
13318let Inst{31-21} = 0b10011111001;
13319let isPredicated = 1;
13320let hasNewValue = 1;
13321let opNewValue = 0;
13322let addrMode = Absolute;
13323let accessSize = ByteAccess;
13324let isPredicatedNew = 1;
13325let mayLoad = 1;
13326let isExtended = 1;
13327let BaseOpcode = "L4_loadrub_abs";
13328let CextOpcode = "L2_loadrub";
13329let DecoderNamespace = "MustExtend";
13330let isExtendable = 1;
13331let opExtendable = 2;
13332let isExtentSigned = 0;
13333let opExtentBits = 6;
13334let opExtentAlign = 0;
13335}
13336def L4_ploadrubtnew_rr : HInst<
13337(outs IntRegs:$Rd32),
13338(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13339"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13340tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13341let Inst{31-21} = 0b00110010001;
13342let isPredicated = 1;
13343let hasNewValue = 1;
13344let opNewValue = 0;
13345let addrMode = BaseRegOffset;
13346let accessSize = ByteAccess;
13347let isPredicatedNew = 1;
13348let mayLoad = 1;
13349let BaseOpcode = "L4_loadrub_rr";
13350let CextOpcode = "L2_loadrub";
13351let InputType = "reg";
13352}
13353def L4_ploadruhf_abs : HInst<
13354(outs IntRegs:$Rd32),
13355(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13356"if (!$Pt4) $Rd32 = memuh(#$Ii)",
13357tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13358let Inst{7-5} = 0b100;
13359let Inst{13-11} = 0b101;
13360let Inst{31-21} = 0b10011111011;
13361let isPredicated = 1;
13362let isPredicatedFalse = 1;
13363let hasNewValue = 1;
13364let opNewValue = 0;
13365let addrMode = Absolute;
13366let accessSize = HalfWordAccess;
13367let mayLoad = 1;
13368let isExtended = 1;
13369let BaseOpcode = "L4_loadruh_abs";
13370let CextOpcode = "L2_loadruh";
13371let DecoderNamespace = "MustExtend";
13372let isExtendable = 1;
13373let opExtendable = 2;
13374let isExtentSigned = 0;
13375let opExtentBits = 6;
13376let opExtentAlign = 0;
13377}
13378def L4_ploadruhf_rr : HInst<
13379(outs IntRegs:$Rd32),
13380(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13381"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13382tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13383let Inst{31-21} = 0b00110001011;
13384let isPredicated = 1;
13385let isPredicatedFalse = 1;
13386let hasNewValue = 1;
13387let opNewValue = 0;
13388let addrMode = BaseRegOffset;
13389let accessSize = HalfWordAccess;
13390let mayLoad = 1;
13391let BaseOpcode = "L4_loadruh_rr";
13392let CextOpcode = "L2_loadruh";
13393let InputType = "reg";
13394}
13395def L4_ploadruhfnew_abs : HInst<
13396(outs IntRegs:$Rd32),
13397(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13398"if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
13399tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13400let Inst{7-5} = 0b100;
13401let Inst{13-11} = 0b111;
13402let Inst{31-21} = 0b10011111011;
13403let isPredicated = 1;
13404let isPredicatedFalse = 1;
13405let hasNewValue = 1;
13406let opNewValue = 0;
13407let addrMode = Absolute;
13408let accessSize = HalfWordAccess;
13409let isPredicatedNew = 1;
13410let mayLoad = 1;
13411let isExtended = 1;
13412let BaseOpcode = "L4_loadruh_abs";
13413let CextOpcode = "L2_loadruh";
13414let DecoderNamespace = "MustExtend";
13415let isExtendable = 1;
13416let opExtendable = 2;
13417let isExtentSigned = 0;
13418let opExtentBits = 6;
13419let opExtentAlign = 0;
13420}
13421def L4_ploadruhfnew_rr : HInst<
13422(outs IntRegs:$Rd32),
13423(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13424"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13425tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13426let Inst{31-21} = 0b00110011011;
13427let isPredicated = 1;
13428let isPredicatedFalse = 1;
13429let hasNewValue = 1;
13430let opNewValue = 0;
13431let addrMode = BaseRegOffset;
13432let accessSize = HalfWordAccess;
13433let isPredicatedNew = 1;
13434let mayLoad = 1;
13435let BaseOpcode = "L4_loadruh_rr";
13436let CextOpcode = "L2_loadruh";
13437let InputType = "reg";
13438}
13439def L4_ploadruht_abs : HInst<
13440(outs IntRegs:$Rd32),
13441(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13442"if ($Pt4) $Rd32 = memuh(#$Ii)",
13443tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13444let Inst{7-5} = 0b100;
13445let Inst{13-11} = 0b100;
13446let Inst{31-21} = 0b10011111011;
13447let isPredicated = 1;
13448let hasNewValue = 1;
13449let opNewValue = 0;
13450let addrMode = Absolute;
13451let accessSize = HalfWordAccess;
13452let mayLoad = 1;
13453let isExtended = 1;
13454let BaseOpcode = "L4_loadruh_abs";
13455let CextOpcode = "L2_loadruh";
13456let DecoderNamespace = "MustExtend";
13457let isExtendable = 1;
13458let opExtendable = 2;
13459let isExtentSigned = 0;
13460let opExtentBits = 6;
13461let opExtentAlign = 0;
13462}
13463def L4_ploadruht_rr : HInst<
13464(outs IntRegs:$Rd32),
13465(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13466"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13467tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13468let Inst{31-21} = 0b00110000011;
13469let isPredicated = 1;
13470let hasNewValue = 1;
13471let opNewValue = 0;
13472let addrMode = BaseRegOffset;
13473let accessSize = HalfWordAccess;
13474let mayLoad = 1;
13475let BaseOpcode = "L4_loadruh_rr";
13476let CextOpcode = "L2_loadruh";
13477let InputType = "reg";
13478}
13479def L4_ploadruhtnew_abs : HInst<
13480(outs IntRegs:$Rd32),
13481(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13482"if ($Pt4.new) $Rd32 = memuh(#$Ii)",
13483tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13484let Inst{7-5} = 0b100;
13485let Inst{13-11} = 0b110;
13486let Inst{31-21} = 0b10011111011;
13487let isPredicated = 1;
13488let hasNewValue = 1;
13489let opNewValue = 0;
13490let addrMode = Absolute;
13491let accessSize = HalfWordAccess;
13492let isPredicatedNew = 1;
13493let mayLoad = 1;
13494let isExtended = 1;
13495let BaseOpcode = "L4_loadruh_abs";
13496let CextOpcode = "L2_loadruh";
13497let DecoderNamespace = "MustExtend";
13498let isExtendable = 1;
13499let opExtendable = 2;
13500let isExtentSigned = 0;
13501let opExtentBits = 6;
13502let opExtentAlign = 0;
13503}
13504def L4_ploadruhtnew_rr : HInst<
13505(outs IntRegs:$Rd32),
13506(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13507"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13508tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13509let Inst{31-21} = 0b00110010011;
13510let isPredicated = 1;
13511let hasNewValue = 1;
13512let opNewValue = 0;
13513let addrMode = BaseRegOffset;
13514let accessSize = HalfWordAccess;
13515let isPredicatedNew = 1;
13516let mayLoad = 1;
13517let BaseOpcode = "L4_loadruh_rr";
13518let CextOpcode = "L2_loadruh";
13519let InputType = "reg";
13520}
13521def L4_return : HInst<
13522(outs DoubleRegs:$Rdd32),
13523(ins IntRegs:$Rs32),
13524"$Rdd32 = dealloc_return($Rs32):raw",
13525tc_40d64c94, TypeLD>, Enc_3a3d62, PredNewRel {
13526let Inst{13-5} = 0b000000000;
13527let Inst{31-21} = 0b10010110000;
13528let isTerminator = 1;
13529let isIndirectBranch = 1;
13530let accessSize = DoubleWordAccess;
13531let mayLoad = 1;
13532let cofMax1 = 1;
13533let isRestrictNoSlot1Store = 1;
13534let isReturn = 1;
13535let Uses = [FRAMEKEY];
13536let Defs = [PC, R29];
13537let BaseOpcode = "L4_return";
13538let isBarrier = 1;
13539let isPredicable = 1;
13540let isTaken = 1;
13541}
13542def L4_return_f : HInst<
13543(outs DoubleRegs:$Rdd32),
13544(ins PredRegs:$Pv4, IntRegs:$Rs32),
13545"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13546tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13547let Inst{7-5} = 0b000;
13548let Inst{13-10} = 0b1100;
13549let Inst{31-21} = 0b10010110000;
13550let isPredicated = 1;
13551let isPredicatedFalse = 1;
13552let isTerminator = 1;
13553let isIndirectBranch = 1;
13554let accessSize = DoubleWordAccess;
13555let mayLoad = 1;
13556let cofMax1 = 1;
13557let isRestrictNoSlot1Store = 1;
13558let isReturn = 1;
13559let Uses = [FRAMEKEY];
13560let Defs = [PC, R29];
13561let BaseOpcode = "L4_return";
13562let isTaken = Inst{12};
13563}
13564def L4_return_fnew_pnt : HInst<
13565(outs DoubleRegs:$Rdd32),
13566(ins PredRegs:$Pv4, IntRegs:$Rs32),
13567"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13568tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13569let Inst{7-5} = 0b000;
13570let Inst{13-10} = 0b1010;
13571let Inst{31-21} = 0b10010110000;
13572let isPredicated = 1;
13573let isPredicatedFalse = 1;
13574let isTerminator = 1;
13575let isIndirectBranch = 1;
13576let accessSize = DoubleWordAccess;
13577let isPredicatedNew = 1;
13578let mayLoad = 1;
13579let cofMax1 = 1;
13580let isRestrictNoSlot1Store = 1;
13581let isReturn = 1;
13582let Uses = [FRAMEKEY];
13583let Defs = [PC, R29];
13584let BaseOpcode = "L4_return";
13585let isTaken = Inst{12};
13586}
13587def L4_return_fnew_pt : HInst<
13588(outs DoubleRegs:$Rdd32),
13589(ins PredRegs:$Pv4, IntRegs:$Rs32),
13590"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13591tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13592let Inst{7-5} = 0b000;
13593let Inst{13-10} = 0b1110;
13594let Inst{31-21} = 0b10010110000;
13595let isPredicated = 1;
13596let isPredicatedFalse = 1;
13597let isTerminator = 1;
13598let isIndirectBranch = 1;
13599let accessSize = DoubleWordAccess;
13600let isPredicatedNew = 1;
13601let mayLoad = 1;
13602let cofMax1 = 1;
13603let isRestrictNoSlot1Store = 1;
13604let isReturn = 1;
13605let Uses = [FRAMEKEY];
13606let Defs = [PC, R29];
13607let BaseOpcode = "L4_return";
13608let isTaken = Inst{12};
13609}
13610def L4_return_map_to_raw_f : HInst<
13611(outs),
13612(ins PredRegs:$Pv4),
13613"if (!$Pv4) dealloc_return",
13614tc_df5d53f9, TypeMAPPING>, Requires<[HasV65]> {
13615let isPseudo = 1;
13616let isCodeGenOnly = 1;
13617}
13618def L4_return_map_to_raw_fnew_pnt : HInst<
13619(outs),
13620(ins PredRegs:$Pv4),
13621"if (!$Pv4.new) dealloc_return:nt",
13622tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13623let isPseudo = 1;
13624let isCodeGenOnly = 1;
13625}
13626def L4_return_map_to_raw_fnew_pt : HInst<
13627(outs),
13628(ins PredRegs:$Pv4),
13629"if (!$Pv4.new) dealloc_return:t",
13630tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13631let isPseudo = 1;
13632let isCodeGenOnly = 1;
13633}
13634def L4_return_map_to_raw_t : HInst<
13635(outs),
13636(ins PredRegs:$Pv4),
13637"if ($Pv4) dealloc_return",
13638tc_f38f92e1, TypeMAPPING>, Requires<[HasV65]> {
13639let isPseudo = 1;
13640let isCodeGenOnly = 1;
13641}
13642def L4_return_map_to_raw_tnew_pnt : HInst<
13643(outs),
13644(ins PredRegs:$Pv4),
13645"if ($Pv4.new) dealloc_return:nt",
13646tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13647let isPseudo = 1;
13648let isCodeGenOnly = 1;
13649}
13650def L4_return_map_to_raw_tnew_pt : HInst<
13651(outs),
13652(ins PredRegs:$Pv4),
13653"if ($Pv4.new) dealloc_return:t",
13654tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13655let isPseudo = 1;
13656let isCodeGenOnly = 1;
13657}
13658def L4_return_t : HInst<
13659(outs DoubleRegs:$Rdd32),
13660(ins PredRegs:$Pv4, IntRegs:$Rs32),
13661"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13662tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13663let Inst{7-5} = 0b000;
13664let Inst{13-10} = 0b0100;
13665let Inst{31-21} = 0b10010110000;
13666let isPredicated = 1;
13667let isTerminator = 1;
13668let isIndirectBranch = 1;
13669let accessSize = DoubleWordAccess;
13670let mayLoad = 1;
13671let cofMax1 = 1;
13672let isRestrictNoSlot1Store = 1;
13673let isReturn = 1;
13674let Uses = [FRAMEKEY];
13675let Defs = [PC, R29];
13676let BaseOpcode = "L4_return";
13677let isTaken = Inst{12};
13678}
13679def L4_return_tnew_pnt : HInst<
13680(outs DoubleRegs:$Rdd32),
13681(ins PredRegs:$Pv4, IntRegs:$Rs32),
13682"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13683tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13684let Inst{7-5} = 0b000;
13685let Inst{13-10} = 0b0010;
13686let Inst{31-21} = 0b10010110000;
13687let isPredicated = 1;
13688let isTerminator = 1;
13689let isIndirectBranch = 1;
13690let accessSize = DoubleWordAccess;
13691let isPredicatedNew = 1;
13692let mayLoad = 1;
13693let cofMax1 = 1;
13694let isRestrictNoSlot1Store = 1;
13695let isReturn = 1;
13696let Uses = [FRAMEKEY];
13697let Defs = [PC, R29];
13698let BaseOpcode = "L4_return";
13699let isTaken = Inst{12};
13700}
13701def L4_return_tnew_pt : HInst<
13702(outs DoubleRegs:$Rdd32),
13703(ins PredRegs:$Pv4, IntRegs:$Rs32),
13704"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13705tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13706let Inst{7-5} = 0b000;
13707let Inst{13-10} = 0b0110;
13708let Inst{31-21} = 0b10010110000;
13709let isPredicated = 1;
13710let isTerminator = 1;
13711let isIndirectBranch = 1;
13712let accessSize = DoubleWordAccess;
13713let isPredicatedNew = 1;
13714let mayLoad = 1;
13715let cofMax1 = 1;
13716let isRestrictNoSlot1Store = 1;
13717let isReturn = 1;
13718let Uses = [FRAMEKEY];
13719let Defs = [PC, R29];
13720let BaseOpcode = "L4_return";
13721let isTaken = Inst{12};
13722}
13723def L4_sub_memopb_io : HInst<
13724(outs),
13725(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
13726"memb($Rs32+#$Ii) -= $Rt32",
13727tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
13728let Inst{6-5} = 0b01;
13729let Inst{13-13} = 0b0;
13730let Inst{31-21} = 0b00111110000;
13731let addrMode = BaseImmOffset;
13732let accessSize = ByteAccess;
13733let mayLoad = 1;
13734let isRestrictNoSlot1Store = 1;
13735let mayStore = 1;
13736let isExtendable = 1;
13737let opExtendable = 1;
13738let isExtentSigned = 0;
13739let opExtentBits = 6;
13740let opExtentAlign = 0;
13741}
13742def L4_sub_memopb_zomap : HInst<
13743(outs),
13744(ins IntRegs:$Rs32, IntRegs:$Rt32),
13745"memb($Rs32) -= $Rt32",
13746tc_9bcfb2ee, TypeMAPPING> {
13747let isPseudo = 1;
13748let isCodeGenOnly = 1;
13749}
13750def L4_sub_memoph_io : HInst<
13751(outs),
13752(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
13753"memh($Rs32+#$Ii) -= $Rt32",
13754tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
13755let Inst{6-5} = 0b01;
13756let Inst{13-13} = 0b0;
13757let Inst{31-21} = 0b00111110001;
13758let addrMode = BaseImmOffset;
13759let accessSize = HalfWordAccess;
13760let mayLoad = 1;
13761let isRestrictNoSlot1Store = 1;
13762let mayStore = 1;
13763let isExtendable = 1;
13764let opExtendable = 1;
13765let isExtentSigned = 0;
13766let opExtentBits = 7;
13767let opExtentAlign = 1;
13768}
13769def L4_sub_memoph_zomap : HInst<
13770(outs),
13771(ins IntRegs:$Rs32, IntRegs:$Rt32),
13772"memh($Rs32) -= $Rt32",
13773tc_9bcfb2ee, TypeMAPPING> {
13774let isPseudo = 1;
13775let isCodeGenOnly = 1;
13776}
13777def L4_sub_memopw_io : HInst<
13778(outs),
13779(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
13780"memw($Rs32+#$Ii) -= $Rt32",
13781tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
13782let Inst{6-5} = 0b01;
13783let Inst{13-13} = 0b0;
13784let Inst{31-21} = 0b00111110010;
13785let addrMode = BaseImmOffset;
13786let accessSize = WordAccess;
13787let mayLoad = 1;
13788let isRestrictNoSlot1Store = 1;
13789let mayStore = 1;
13790let isExtendable = 1;
13791let opExtendable = 1;
13792let isExtentSigned = 0;
13793let opExtentBits = 8;
13794let opExtentAlign = 2;
13795}
13796def L4_sub_memopw_zomap : HInst<
13797(outs),
13798(ins IntRegs:$Rs32, IntRegs:$Rt32),
13799"memw($Rs32) -= $Rt32",
13800tc_9bcfb2ee, TypeMAPPING> {
13801let isPseudo = 1;
13802let isCodeGenOnly = 1;
13803}
13804def L6_deallocframe_map_to_raw : HInst<
13805(outs),
13806(ins),
13807"deallocframe",
13808tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> {
13809let isPseudo = 1;
13810let isCodeGenOnly = 1;
13811}
13812def L6_memcpy : HInst<
13813(outs),
13814(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
13815"memcpy($Rs32,$Rt32,$Mu2)",
13816tc_5944960d, TypeLD>, Enc_a75aa6, Requires<[HasV66]> {
13817let Inst{7-0} = 0b01000000;
13818let Inst{31-21} = 0b10010010000;
13819let mayLoad = 1;
13820let isSolo = 1;
13821let mayStore = 1;
13822}
13823def L6_return_map_to_raw : HInst<
13824(outs),
13825(ins),
13826"dealloc_return",
13827tc_40d64c94, TypeMAPPING>, Requires<[HasV65]> {
13828let isPseudo = 1;
13829let isCodeGenOnly = 1;
13830}
13831def M2_acci : HInst<
13832(outs IntRegs:$Rx32),
13833(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13834"$Rx32 += add($Rs32,$Rt32)",
13835tc_2c13e7f5, TypeM>, Enc_2ae154, ImmRegRel {
13836let Inst{7-5} = 0b001;
13837let Inst{13-13} = 0b0;
13838let Inst{31-21} = 0b11101111000;
13839let hasNewValue = 1;
13840let opNewValue = 0;
13841let prefersSlot3 = 1;
13842let CextOpcode = "M2_acci";
13843let InputType = "reg";
13844let Constraints = "$Rx32 = $Rx32in";
13845}
13846def M2_accii : HInst<
13847(outs IntRegs:$Rx32),
13848(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
13849"$Rx32 += add($Rs32,#$Ii)",
13850tc_2c13e7f5, TypeM>, Enc_c90aca, ImmRegRel {
13851let Inst{13-13} = 0b0;
13852let Inst{31-21} = 0b11100010000;
13853let hasNewValue = 1;
13854let opNewValue = 0;
13855let prefersSlot3 = 1;
13856let CextOpcode = "M2_acci";
13857let InputType = "imm";
13858let isExtendable = 1;
13859let opExtendable = 3;
13860let isExtentSigned = 1;
13861let opExtentBits = 8;
13862let opExtentAlign = 0;
13863let Constraints = "$Rx32 = $Rx32in";
13864}
13865def M2_cmaci_s0 : HInst<
13866(outs DoubleRegs:$Rxx32),
13867(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13868"$Rxx32 += cmpyi($Rs32,$Rt32)",
13869tc_7f8ae742, TypeM>, Enc_61f0b0 {
13870let Inst{7-5} = 0b001;
13871let Inst{13-13} = 0b0;
13872let Inst{31-21} = 0b11100111000;
13873let prefersSlot3 = 1;
13874let Constraints = "$Rxx32 = $Rxx32in";
13875}
13876def M2_cmacr_s0 : HInst<
13877(outs DoubleRegs:$Rxx32),
13878(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13879"$Rxx32 += cmpyr($Rs32,$Rt32)",
13880tc_7f8ae742, TypeM>, Enc_61f0b0 {
13881let Inst{7-5} = 0b010;
13882let Inst{13-13} = 0b0;
13883let Inst{31-21} = 0b11100111000;
13884let prefersSlot3 = 1;
13885let Constraints = "$Rxx32 = $Rxx32in";
13886}
13887def M2_cmacs_s0 : HInst<
13888(outs DoubleRegs:$Rxx32),
13889(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13890"$Rxx32 += cmpy($Rs32,$Rt32):sat",
13891tc_7f8ae742, TypeM>, Enc_61f0b0 {
13892let Inst{7-5} = 0b110;
13893let Inst{13-13} = 0b0;
13894let Inst{31-21} = 0b11100111000;
13895let prefersSlot3 = 1;
13896let Defs = [USR_OVF];
13897let Constraints = "$Rxx32 = $Rxx32in";
13898}
13899def M2_cmacs_s1 : HInst<
13900(outs DoubleRegs:$Rxx32),
13901(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13902"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
13903tc_7f8ae742, TypeM>, Enc_61f0b0 {
13904let Inst{7-5} = 0b110;
13905let Inst{13-13} = 0b0;
13906let Inst{31-21} = 0b11100111100;
13907let prefersSlot3 = 1;
13908let Defs = [USR_OVF];
13909let Constraints = "$Rxx32 = $Rxx32in";
13910}
13911def M2_cmacsc_s0 : HInst<
13912(outs DoubleRegs:$Rxx32),
13913(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13914"$Rxx32 += cmpy($Rs32,$Rt32*):sat",
13915tc_7f8ae742, TypeM>, Enc_61f0b0 {
13916let Inst{7-5} = 0b110;
13917let Inst{13-13} = 0b0;
13918let Inst{31-21} = 0b11100111010;
13919let prefersSlot3 = 1;
13920let Defs = [USR_OVF];
13921let Constraints = "$Rxx32 = $Rxx32in";
13922}
13923def M2_cmacsc_s1 : HInst<
13924(outs DoubleRegs:$Rxx32),
13925(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13926"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
13927tc_7f8ae742, TypeM>, Enc_61f0b0 {
13928let Inst{7-5} = 0b110;
13929let Inst{13-13} = 0b0;
13930let Inst{31-21} = 0b11100111110;
13931let prefersSlot3 = 1;
13932let Defs = [USR_OVF];
13933let Constraints = "$Rxx32 = $Rxx32in";
13934}
13935def M2_cmpyi_s0 : HInst<
13936(outs DoubleRegs:$Rdd32),
13937(ins IntRegs:$Rs32, IntRegs:$Rt32),
13938"$Rdd32 = cmpyi($Rs32,$Rt32)",
13939tc_c21d7447, TypeM>, Enc_be32a5 {
13940let Inst{7-5} = 0b001;
13941let Inst{13-13} = 0b0;
13942let Inst{31-21} = 0b11100101000;
13943let prefersSlot3 = 1;
13944}
13945def M2_cmpyr_s0 : HInst<
13946(outs DoubleRegs:$Rdd32),
13947(ins IntRegs:$Rs32, IntRegs:$Rt32),
13948"$Rdd32 = cmpyr($Rs32,$Rt32)",
13949tc_c21d7447, TypeM>, Enc_be32a5 {
13950let Inst{7-5} = 0b010;
13951let Inst{13-13} = 0b0;
13952let Inst{31-21} = 0b11100101000;
13953let prefersSlot3 = 1;
13954}
13955def M2_cmpyrs_s0 : HInst<
13956(outs IntRegs:$Rd32),
13957(ins IntRegs:$Rs32, IntRegs:$Rt32),
13958"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
13959tc_c21d7447, TypeM>, Enc_5ab2be {
13960let Inst{7-5} = 0b110;
13961let Inst{13-13} = 0b0;
13962let Inst{31-21} = 0b11101101001;
13963let hasNewValue = 1;
13964let opNewValue = 0;
13965let prefersSlot3 = 1;
13966let Defs = [USR_OVF];
13967}
13968def M2_cmpyrs_s1 : HInst<
13969(outs IntRegs:$Rd32),
13970(ins IntRegs:$Rs32, IntRegs:$Rt32),
13971"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
13972tc_c21d7447, TypeM>, Enc_5ab2be {
13973let Inst{7-5} = 0b110;
13974let Inst{13-13} = 0b0;
13975let Inst{31-21} = 0b11101101101;
13976let hasNewValue = 1;
13977let opNewValue = 0;
13978let prefersSlot3 = 1;
13979let Defs = [USR_OVF];
13980}
13981def M2_cmpyrsc_s0 : HInst<
13982(outs IntRegs:$Rd32),
13983(ins IntRegs:$Rs32, IntRegs:$Rt32),
13984"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
13985tc_c21d7447, TypeM>, Enc_5ab2be {
13986let Inst{7-5} = 0b110;
13987let Inst{13-13} = 0b0;
13988let Inst{31-21} = 0b11101101011;
13989let hasNewValue = 1;
13990let opNewValue = 0;
13991let prefersSlot3 = 1;
13992let Defs = [USR_OVF];
13993}
13994def M2_cmpyrsc_s1 : HInst<
13995(outs IntRegs:$Rd32),
13996(ins IntRegs:$Rs32, IntRegs:$Rt32),
13997"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
13998tc_c21d7447, TypeM>, Enc_5ab2be {
13999let Inst{7-5} = 0b110;
14000let Inst{13-13} = 0b0;
14001let Inst{31-21} = 0b11101101111;
14002let hasNewValue = 1;
14003let opNewValue = 0;
14004let prefersSlot3 = 1;
14005let Defs = [USR_OVF];
14006}
14007def M2_cmpys_s0 : HInst<
14008(outs DoubleRegs:$Rdd32),
14009(ins IntRegs:$Rs32, IntRegs:$Rt32),
14010"$Rdd32 = cmpy($Rs32,$Rt32):sat",
14011tc_c21d7447, TypeM>, Enc_be32a5 {
14012let Inst{7-5} = 0b110;
14013let Inst{13-13} = 0b0;
14014let Inst{31-21} = 0b11100101000;
14015let prefersSlot3 = 1;
14016let Defs = [USR_OVF];
14017}
14018def M2_cmpys_s1 : HInst<
14019(outs DoubleRegs:$Rdd32),
14020(ins IntRegs:$Rs32, IntRegs:$Rt32),
14021"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
14022tc_c21d7447, TypeM>, Enc_be32a5 {
14023let Inst{7-5} = 0b110;
14024let Inst{13-13} = 0b0;
14025let Inst{31-21} = 0b11100101100;
14026let prefersSlot3 = 1;
14027let Defs = [USR_OVF];
14028}
14029def M2_cmpysc_s0 : HInst<
14030(outs DoubleRegs:$Rdd32),
14031(ins IntRegs:$Rs32, IntRegs:$Rt32),
14032"$Rdd32 = cmpy($Rs32,$Rt32*):sat",
14033tc_c21d7447, TypeM>, Enc_be32a5 {
14034let Inst{7-5} = 0b110;
14035let Inst{13-13} = 0b0;
14036let Inst{31-21} = 0b11100101010;
14037let prefersSlot3 = 1;
14038let Defs = [USR_OVF];
14039}
14040def M2_cmpysc_s1 : HInst<
14041(outs DoubleRegs:$Rdd32),
14042(ins IntRegs:$Rs32, IntRegs:$Rt32),
14043"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
14044tc_c21d7447, TypeM>, Enc_be32a5 {
14045let Inst{7-5} = 0b110;
14046let Inst{13-13} = 0b0;
14047let Inst{31-21} = 0b11100101110;
14048let prefersSlot3 = 1;
14049let Defs = [USR_OVF];
14050}
14051def M2_cnacs_s0 : HInst<
14052(outs DoubleRegs:$Rxx32),
14053(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14054"$Rxx32 -= cmpy($Rs32,$Rt32):sat",
14055tc_7f8ae742, TypeM>, Enc_61f0b0 {
14056let Inst{7-5} = 0b111;
14057let Inst{13-13} = 0b0;
14058let Inst{31-21} = 0b11100111000;
14059let prefersSlot3 = 1;
14060let Defs = [USR_OVF];
14061let Constraints = "$Rxx32 = $Rxx32in";
14062}
14063def M2_cnacs_s1 : HInst<
14064(outs DoubleRegs:$Rxx32),
14065(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14066"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
14067tc_7f8ae742, TypeM>, Enc_61f0b0 {
14068let Inst{7-5} = 0b111;
14069let Inst{13-13} = 0b0;
14070let Inst{31-21} = 0b11100111100;
14071let prefersSlot3 = 1;
14072let Defs = [USR_OVF];
14073let Constraints = "$Rxx32 = $Rxx32in";
14074}
14075def M2_cnacsc_s0 : HInst<
14076(outs DoubleRegs:$Rxx32),
14077(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14078"$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
14079tc_7f8ae742, TypeM>, Enc_61f0b0 {
14080let Inst{7-5} = 0b111;
14081let Inst{13-13} = 0b0;
14082let Inst{31-21} = 0b11100111010;
14083let prefersSlot3 = 1;
14084let Defs = [USR_OVF];
14085let Constraints = "$Rxx32 = $Rxx32in";
14086}
14087def M2_cnacsc_s1 : HInst<
14088(outs DoubleRegs:$Rxx32),
14089(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14090"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
14091tc_7f8ae742, TypeM>, Enc_61f0b0 {
14092let Inst{7-5} = 0b111;
14093let Inst{13-13} = 0b0;
14094let Inst{31-21} = 0b11100111110;
14095let prefersSlot3 = 1;
14096let Defs = [USR_OVF];
14097let Constraints = "$Rxx32 = $Rxx32in";
14098}
14099def M2_dpmpyss_acc_s0 : HInst<
14100(outs DoubleRegs:$Rxx32),
14101(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14102"$Rxx32 += mpy($Rs32,$Rt32)",
14103tc_7f8ae742, TypeM>, Enc_61f0b0 {
14104let Inst{7-5} = 0b000;
14105let Inst{13-13} = 0b0;
14106let Inst{31-21} = 0b11100111000;
14107let prefersSlot3 = 1;
14108let Constraints = "$Rxx32 = $Rxx32in";
14109}
14110def M2_dpmpyss_nac_s0 : HInst<
14111(outs DoubleRegs:$Rxx32),
14112(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14113"$Rxx32 -= mpy($Rs32,$Rt32)",
14114tc_7f8ae742, TypeM>, Enc_61f0b0 {
14115let Inst{7-5} = 0b000;
14116let Inst{13-13} = 0b0;
14117let Inst{31-21} = 0b11100111001;
14118let prefersSlot3 = 1;
14119let Constraints = "$Rxx32 = $Rxx32in";
14120}
14121def M2_dpmpyss_rnd_s0 : HInst<
14122(outs IntRegs:$Rd32),
14123(ins IntRegs:$Rs32, IntRegs:$Rt32),
14124"$Rd32 = mpy($Rs32,$Rt32):rnd",
14125tc_c21d7447, TypeM>, Enc_5ab2be {
14126let Inst{7-5} = 0b001;
14127let Inst{13-13} = 0b0;
14128let Inst{31-21} = 0b11101101001;
14129let hasNewValue = 1;
14130let opNewValue = 0;
14131let prefersSlot3 = 1;
14132}
14133def M2_dpmpyss_s0 : HInst<
14134(outs DoubleRegs:$Rdd32),
14135(ins IntRegs:$Rs32, IntRegs:$Rt32),
14136"$Rdd32 = mpy($Rs32,$Rt32)",
14137tc_c21d7447, TypeM>, Enc_be32a5 {
14138let Inst{7-5} = 0b000;
14139let Inst{13-13} = 0b0;
14140let Inst{31-21} = 0b11100101000;
14141let prefersSlot3 = 1;
14142}
14143def M2_dpmpyuu_acc_s0 : HInst<
14144(outs DoubleRegs:$Rxx32),
14145(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14146"$Rxx32 += mpyu($Rs32,$Rt32)",
14147tc_7f8ae742, TypeM>, Enc_61f0b0 {
14148let Inst{7-5} = 0b000;
14149let Inst{13-13} = 0b0;
14150let Inst{31-21} = 0b11100111010;
14151let prefersSlot3 = 1;
14152let Constraints = "$Rxx32 = $Rxx32in";
14153}
14154def M2_dpmpyuu_nac_s0 : HInst<
14155(outs DoubleRegs:$Rxx32),
14156(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14157"$Rxx32 -= mpyu($Rs32,$Rt32)",
14158tc_7f8ae742, TypeM>, Enc_61f0b0 {
14159let Inst{7-5} = 0b000;
14160let Inst{13-13} = 0b0;
14161let Inst{31-21} = 0b11100111011;
14162let prefersSlot3 = 1;
14163let Constraints = "$Rxx32 = $Rxx32in";
14164}
14165def M2_dpmpyuu_s0 : HInst<
14166(outs DoubleRegs:$Rdd32),
14167(ins IntRegs:$Rs32, IntRegs:$Rt32),
14168"$Rdd32 = mpyu($Rs32,$Rt32)",
14169tc_c21d7447, TypeM>, Enc_be32a5 {
14170let Inst{7-5} = 0b000;
14171let Inst{13-13} = 0b0;
14172let Inst{31-21} = 0b11100101010;
14173let prefersSlot3 = 1;
14174}
14175def M2_hmmpyh_rs1 : HInst<
14176(outs IntRegs:$Rd32),
14177(ins IntRegs:$Rs32, IntRegs:$Rt32),
14178"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
14179tc_c21d7447, TypeM>, Enc_5ab2be {
14180let Inst{7-5} = 0b100;
14181let Inst{13-13} = 0b0;
14182let Inst{31-21} = 0b11101101101;
14183let hasNewValue = 1;
14184let opNewValue = 0;
14185let prefersSlot3 = 1;
14186let Defs = [USR_OVF];
14187}
14188def M2_hmmpyh_s1 : HInst<
14189(outs IntRegs:$Rd32),
14190(ins IntRegs:$Rs32, IntRegs:$Rt32),
14191"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
14192tc_c21d7447, TypeM>, Enc_5ab2be {
14193let Inst{7-5} = 0b000;
14194let Inst{13-13} = 0b0;
14195let Inst{31-21} = 0b11101101101;
14196let hasNewValue = 1;
14197let opNewValue = 0;
14198let prefersSlot3 = 1;
14199let Defs = [USR_OVF];
14200}
14201def M2_hmmpyl_rs1 : HInst<
14202(outs IntRegs:$Rd32),
14203(ins IntRegs:$Rs32, IntRegs:$Rt32),
14204"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
14205tc_c21d7447, TypeM>, Enc_5ab2be {
14206let Inst{7-5} = 0b100;
14207let Inst{13-13} = 0b0;
14208let Inst{31-21} = 0b11101101111;
14209let hasNewValue = 1;
14210let opNewValue = 0;
14211let prefersSlot3 = 1;
14212let Defs = [USR_OVF];
14213}
14214def M2_hmmpyl_s1 : HInst<
14215(outs IntRegs:$Rd32),
14216(ins IntRegs:$Rs32, IntRegs:$Rt32),
14217"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
14218tc_c21d7447, TypeM>, Enc_5ab2be {
14219let Inst{7-5} = 0b001;
14220let Inst{13-13} = 0b0;
14221let Inst{31-21} = 0b11101101101;
14222let hasNewValue = 1;
14223let opNewValue = 0;
14224let prefersSlot3 = 1;
14225let Defs = [USR_OVF];
14226}
14227def M2_maci : HInst<
14228(outs IntRegs:$Rx32),
14229(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14230"$Rx32 += mpyi($Rs32,$Rt32)",
14231tc_7f8ae742, TypeM>, Enc_2ae154, ImmRegRel {
14232let Inst{7-5} = 0b000;
14233let Inst{13-13} = 0b0;
14234let Inst{31-21} = 0b11101111000;
14235let hasNewValue = 1;
14236let opNewValue = 0;
14237let prefersSlot3 = 1;
14238let CextOpcode = "M2_maci";
14239let InputType = "reg";
14240let Constraints = "$Rx32 = $Rx32in";
14241}
14242def M2_macsin : HInst<
14243(outs IntRegs:$Rx32),
14244(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14245"$Rx32 -= mpyi($Rs32,#$Ii)",
14246tc_a154b476, TypeM>, Enc_c90aca {
14247let Inst{13-13} = 0b0;
14248let Inst{31-21} = 0b11100001100;
14249let hasNewValue = 1;
14250let opNewValue = 0;
14251let prefersSlot3 = 1;
14252let InputType = "imm";
14253let isExtendable = 1;
14254let opExtendable = 3;
14255let isExtentSigned = 0;
14256let opExtentBits = 8;
14257let opExtentAlign = 0;
14258let Constraints = "$Rx32 = $Rx32in";
14259}
14260def M2_macsip : HInst<
14261(outs IntRegs:$Rx32),
14262(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14263"$Rx32 += mpyi($Rs32,#$Ii)",
14264tc_a154b476, TypeM>, Enc_c90aca, ImmRegRel {
14265let Inst{13-13} = 0b0;
14266let Inst{31-21} = 0b11100001000;
14267let hasNewValue = 1;
14268let opNewValue = 0;
14269let prefersSlot3 = 1;
14270let CextOpcode = "M2_maci";
14271let InputType = "imm";
14272let isExtendable = 1;
14273let opExtendable = 3;
14274let isExtentSigned = 0;
14275let opExtentBits = 8;
14276let opExtentAlign = 0;
14277let Constraints = "$Rx32 = $Rx32in";
14278}
14279def M2_mmachs_rs0 : HInst<
14280(outs DoubleRegs:$Rxx32),
14281(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14282"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
14283tc_7f8ae742, TypeM>, Enc_88c16c {
14284let Inst{7-5} = 0b111;
14285let Inst{13-13} = 0b0;
14286let Inst{31-21} = 0b11101010001;
14287let prefersSlot3 = 1;
14288let Defs = [USR_OVF];
14289let Constraints = "$Rxx32 = $Rxx32in";
14290}
14291def M2_mmachs_rs1 : HInst<
14292(outs DoubleRegs:$Rxx32),
14293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14294"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14295tc_7f8ae742, TypeM>, Enc_88c16c {
14296let Inst{7-5} = 0b111;
14297let Inst{13-13} = 0b0;
14298let Inst{31-21} = 0b11101010101;
14299let prefersSlot3 = 1;
14300let Defs = [USR_OVF];
14301let Constraints = "$Rxx32 = $Rxx32in";
14302}
14303def M2_mmachs_s0 : HInst<
14304(outs DoubleRegs:$Rxx32),
14305(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14306"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
14307tc_7f8ae742, TypeM>, Enc_88c16c {
14308let Inst{7-5} = 0b111;
14309let Inst{13-13} = 0b0;
14310let Inst{31-21} = 0b11101010000;
14311let prefersSlot3 = 1;
14312let Defs = [USR_OVF];
14313let Constraints = "$Rxx32 = $Rxx32in";
14314}
14315def M2_mmachs_s1 : HInst<
14316(outs DoubleRegs:$Rxx32),
14317(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14318"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
14319tc_7f8ae742, TypeM>, Enc_88c16c {
14320let Inst{7-5} = 0b111;
14321let Inst{13-13} = 0b0;
14322let Inst{31-21} = 0b11101010100;
14323let prefersSlot3 = 1;
14324let Defs = [USR_OVF];
14325let Constraints = "$Rxx32 = $Rxx32in";
14326}
14327def M2_mmacls_rs0 : HInst<
14328(outs DoubleRegs:$Rxx32),
14329(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14330"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
14331tc_7f8ae742, TypeM>, Enc_88c16c {
14332let Inst{7-5} = 0b101;
14333let Inst{13-13} = 0b0;
14334let Inst{31-21} = 0b11101010001;
14335let prefersSlot3 = 1;
14336let Defs = [USR_OVF];
14337let Constraints = "$Rxx32 = $Rxx32in";
14338}
14339def M2_mmacls_rs1 : HInst<
14340(outs DoubleRegs:$Rxx32),
14341(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14342"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14343tc_7f8ae742, TypeM>, Enc_88c16c {
14344let Inst{7-5} = 0b101;
14345let Inst{13-13} = 0b0;
14346let Inst{31-21} = 0b11101010101;
14347let prefersSlot3 = 1;
14348let Defs = [USR_OVF];
14349let Constraints = "$Rxx32 = $Rxx32in";
14350}
14351def M2_mmacls_s0 : HInst<
14352(outs DoubleRegs:$Rxx32),
14353(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14354"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
14355tc_7f8ae742, TypeM>, Enc_88c16c {
14356let Inst{7-5} = 0b101;
14357let Inst{13-13} = 0b0;
14358let Inst{31-21} = 0b11101010000;
14359let prefersSlot3 = 1;
14360let Defs = [USR_OVF];
14361let Constraints = "$Rxx32 = $Rxx32in";
14362}
14363def M2_mmacls_s1 : HInst<
14364(outs DoubleRegs:$Rxx32),
14365(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14366"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
14367tc_7f8ae742, TypeM>, Enc_88c16c {
14368let Inst{7-5} = 0b101;
14369let Inst{13-13} = 0b0;
14370let Inst{31-21} = 0b11101010100;
14371let prefersSlot3 = 1;
14372let Defs = [USR_OVF];
14373let Constraints = "$Rxx32 = $Rxx32in";
14374}
14375def M2_mmacuhs_rs0 : HInst<
14376(outs DoubleRegs:$Rxx32),
14377(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14378"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
14379tc_7f8ae742, TypeM>, Enc_88c16c {
14380let Inst{7-5} = 0b111;
14381let Inst{13-13} = 0b0;
14382let Inst{31-21} = 0b11101010011;
14383let prefersSlot3 = 1;
14384let Defs = [USR_OVF];
14385let Constraints = "$Rxx32 = $Rxx32in";
14386}
14387def M2_mmacuhs_rs1 : HInst<
14388(outs DoubleRegs:$Rxx32),
14389(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14390"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14391tc_7f8ae742, TypeM>, Enc_88c16c {
14392let Inst{7-5} = 0b111;
14393let Inst{13-13} = 0b0;
14394let Inst{31-21} = 0b11101010111;
14395let prefersSlot3 = 1;
14396let Defs = [USR_OVF];
14397let Constraints = "$Rxx32 = $Rxx32in";
14398}
14399def M2_mmacuhs_s0 : HInst<
14400(outs DoubleRegs:$Rxx32),
14401(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14402"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
14403tc_7f8ae742, TypeM>, Enc_88c16c {
14404let Inst{7-5} = 0b111;
14405let Inst{13-13} = 0b0;
14406let Inst{31-21} = 0b11101010010;
14407let prefersSlot3 = 1;
14408let Defs = [USR_OVF];
14409let Constraints = "$Rxx32 = $Rxx32in";
14410}
14411def M2_mmacuhs_s1 : HInst<
14412(outs DoubleRegs:$Rxx32),
14413(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14414"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
14415tc_7f8ae742, TypeM>, Enc_88c16c {
14416let Inst{7-5} = 0b111;
14417let Inst{13-13} = 0b0;
14418let Inst{31-21} = 0b11101010110;
14419let prefersSlot3 = 1;
14420let Defs = [USR_OVF];
14421let Constraints = "$Rxx32 = $Rxx32in";
14422}
14423def M2_mmaculs_rs0 : HInst<
14424(outs DoubleRegs:$Rxx32),
14425(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14426"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
14427tc_7f8ae742, TypeM>, Enc_88c16c {
14428let Inst{7-5} = 0b101;
14429let Inst{13-13} = 0b0;
14430let Inst{31-21} = 0b11101010011;
14431let prefersSlot3 = 1;
14432let Defs = [USR_OVF];
14433let Constraints = "$Rxx32 = $Rxx32in";
14434}
14435def M2_mmaculs_rs1 : HInst<
14436(outs DoubleRegs:$Rxx32),
14437(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14438"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14439tc_7f8ae742, TypeM>, Enc_88c16c {
14440let Inst{7-5} = 0b101;
14441let Inst{13-13} = 0b0;
14442let Inst{31-21} = 0b11101010111;
14443let prefersSlot3 = 1;
14444let Defs = [USR_OVF];
14445let Constraints = "$Rxx32 = $Rxx32in";
14446}
14447def M2_mmaculs_s0 : HInst<
14448(outs DoubleRegs:$Rxx32),
14449(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14450"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
14451tc_7f8ae742, TypeM>, Enc_88c16c {
14452let Inst{7-5} = 0b101;
14453let Inst{13-13} = 0b0;
14454let Inst{31-21} = 0b11101010010;
14455let prefersSlot3 = 1;
14456let Defs = [USR_OVF];
14457let Constraints = "$Rxx32 = $Rxx32in";
14458}
14459def M2_mmaculs_s1 : HInst<
14460(outs DoubleRegs:$Rxx32),
14461(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14462"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
14463tc_7f8ae742, TypeM>, Enc_88c16c {
14464let Inst{7-5} = 0b101;
14465let Inst{13-13} = 0b0;
14466let Inst{31-21} = 0b11101010110;
14467let prefersSlot3 = 1;
14468let Defs = [USR_OVF];
14469let Constraints = "$Rxx32 = $Rxx32in";
14470}
14471def M2_mmpyh_rs0 : HInst<
14472(outs DoubleRegs:$Rdd32),
14473(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14474"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
14475tc_c21d7447, TypeM>, Enc_a56825 {
14476let Inst{7-5} = 0b111;
14477let Inst{13-13} = 0b0;
14478let Inst{31-21} = 0b11101000001;
14479let prefersSlot3 = 1;
14480let Defs = [USR_OVF];
14481}
14482def M2_mmpyh_rs1 : HInst<
14483(outs DoubleRegs:$Rdd32),
14484(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14485"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14486tc_c21d7447, TypeM>, Enc_a56825 {
14487let Inst{7-5} = 0b111;
14488let Inst{13-13} = 0b0;
14489let Inst{31-21} = 0b11101000101;
14490let prefersSlot3 = 1;
14491let Defs = [USR_OVF];
14492}
14493def M2_mmpyh_s0 : HInst<
14494(outs DoubleRegs:$Rdd32),
14495(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14496"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
14497tc_c21d7447, TypeM>, Enc_a56825 {
14498let Inst{7-5} = 0b111;
14499let Inst{13-13} = 0b0;
14500let Inst{31-21} = 0b11101000000;
14501let prefersSlot3 = 1;
14502let Defs = [USR_OVF];
14503}
14504def M2_mmpyh_s1 : HInst<
14505(outs DoubleRegs:$Rdd32),
14506(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14507"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
14508tc_c21d7447, TypeM>, Enc_a56825 {
14509let Inst{7-5} = 0b111;
14510let Inst{13-13} = 0b0;
14511let Inst{31-21} = 0b11101000100;
14512let prefersSlot3 = 1;
14513let Defs = [USR_OVF];
14514}
14515def M2_mmpyl_rs0 : HInst<
14516(outs DoubleRegs:$Rdd32),
14517(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14518"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
14519tc_c21d7447, TypeM>, Enc_a56825 {
14520let Inst{7-5} = 0b101;
14521let Inst{13-13} = 0b0;
14522let Inst{31-21} = 0b11101000001;
14523let prefersSlot3 = 1;
14524let Defs = [USR_OVF];
14525}
14526def M2_mmpyl_rs1 : HInst<
14527(outs DoubleRegs:$Rdd32),
14528(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14529"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14530tc_c21d7447, TypeM>, Enc_a56825 {
14531let Inst{7-5} = 0b101;
14532let Inst{13-13} = 0b0;
14533let Inst{31-21} = 0b11101000101;
14534let prefersSlot3 = 1;
14535let Defs = [USR_OVF];
14536}
14537def M2_mmpyl_s0 : HInst<
14538(outs DoubleRegs:$Rdd32),
14539(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14540"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
14541tc_c21d7447, TypeM>, Enc_a56825 {
14542let Inst{7-5} = 0b101;
14543let Inst{13-13} = 0b0;
14544let Inst{31-21} = 0b11101000000;
14545let prefersSlot3 = 1;
14546let Defs = [USR_OVF];
14547}
14548def M2_mmpyl_s1 : HInst<
14549(outs DoubleRegs:$Rdd32),
14550(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14551"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
14552tc_c21d7447, TypeM>, Enc_a56825 {
14553let Inst{7-5} = 0b101;
14554let Inst{13-13} = 0b0;
14555let Inst{31-21} = 0b11101000100;
14556let prefersSlot3 = 1;
14557let Defs = [USR_OVF];
14558}
14559def M2_mmpyuh_rs0 : HInst<
14560(outs DoubleRegs:$Rdd32),
14561(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14562"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
14563tc_c21d7447, TypeM>, Enc_a56825 {
14564let Inst{7-5} = 0b111;
14565let Inst{13-13} = 0b0;
14566let Inst{31-21} = 0b11101000011;
14567let prefersSlot3 = 1;
14568let Defs = [USR_OVF];
14569}
14570def M2_mmpyuh_rs1 : HInst<
14571(outs DoubleRegs:$Rdd32),
14572(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14573"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14574tc_c21d7447, TypeM>, Enc_a56825 {
14575let Inst{7-5} = 0b111;
14576let Inst{13-13} = 0b0;
14577let Inst{31-21} = 0b11101000111;
14578let prefersSlot3 = 1;
14579let Defs = [USR_OVF];
14580}
14581def M2_mmpyuh_s0 : HInst<
14582(outs DoubleRegs:$Rdd32),
14583(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14584"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
14585tc_c21d7447, TypeM>, Enc_a56825 {
14586let Inst{7-5} = 0b111;
14587let Inst{13-13} = 0b0;
14588let Inst{31-21} = 0b11101000010;
14589let prefersSlot3 = 1;
14590let Defs = [USR_OVF];
14591}
14592def M2_mmpyuh_s1 : HInst<
14593(outs DoubleRegs:$Rdd32),
14594(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14595"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
14596tc_c21d7447, TypeM>, Enc_a56825 {
14597let Inst{7-5} = 0b111;
14598let Inst{13-13} = 0b0;
14599let Inst{31-21} = 0b11101000110;
14600let prefersSlot3 = 1;
14601let Defs = [USR_OVF];
14602}
14603def M2_mmpyul_rs0 : HInst<
14604(outs DoubleRegs:$Rdd32),
14605(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14606"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
14607tc_c21d7447, TypeM>, Enc_a56825 {
14608let Inst{7-5} = 0b101;
14609let Inst{13-13} = 0b0;
14610let Inst{31-21} = 0b11101000011;
14611let prefersSlot3 = 1;
14612let Defs = [USR_OVF];
14613}
14614def M2_mmpyul_rs1 : HInst<
14615(outs DoubleRegs:$Rdd32),
14616(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14617"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14618tc_c21d7447, TypeM>, Enc_a56825 {
14619let Inst{7-5} = 0b101;
14620let Inst{13-13} = 0b0;
14621let Inst{31-21} = 0b11101000111;
14622let prefersSlot3 = 1;
14623let Defs = [USR_OVF];
14624}
14625def M2_mmpyul_s0 : HInst<
14626(outs DoubleRegs:$Rdd32),
14627(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14628"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
14629tc_c21d7447, TypeM>, Enc_a56825 {
14630let Inst{7-5} = 0b101;
14631let Inst{13-13} = 0b0;
14632let Inst{31-21} = 0b11101000010;
14633let prefersSlot3 = 1;
14634let Defs = [USR_OVF];
14635}
14636def M2_mmpyul_s1 : HInst<
14637(outs DoubleRegs:$Rdd32),
14638(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14639"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
14640tc_c21d7447, TypeM>, Enc_a56825 {
14641let Inst{7-5} = 0b101;
14642let Inst{13-13} = 0b0;
14643let Inst{31-21} = 0b11101000110;
14644let prefersSlot3 = 1;
14645let Defs = [USR_OVF];
14646}
14647def M2_mnaci : HInst<
14648(outs IntRegs:$Rx32),
14649(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14650"$Rx32 -= mpyi($Rs32,$Rt32)",
14651tc_01e1be3b, TypeM>, Enc_2ae154, Requires<[HasV66]> {
14652let Inst{7-5} = 0b000;
14653let Inst{13-13} = 0b0;
14654let Inst{31-21} = 0b11101111100;
14655let hasNewValue = 1;
14656let opNewValue = 0;
14657let prefersSlot3 = 1;
14658let Constraints = "$Rx32 = $Rx32in";
14659}
14660def M2_mpy_acc_hh_s0 : HInst<
14661(outs IntRegs:$Rx32),
14662(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14663"$Rx32 += mpy($Rs32.h,$Rt32.h)",
14664tc_7f8ae742, TypeM>, Enc_2ae154 {
14665let Inst{7-5} = 0b011;
14666let Inst{13-13} = 0b0;
14667let Inst{31-21} = 0b11101110000;
14668let hasNewValue = 1;
14669let opNewValue = 0;
14670let prefersSlot3 = 1;
14671let Constraints = "$Rx32 = $Rx32in";
14672}
14673def M2_mpy_acc_hh_s1 : HInst<
14674(outs IntRegs:$Rx32),
14675(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14676"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
14677tc_7f8ae742, TypeM>, Enc_2ae154 {
14678let Inst{7-5} = 0b011;
14679let Inst{13-13} = 0b0;
14680let Inst{31-21} = 0b11101110100;
14681let hasNewValue = 1;
14682let opNewValue = 0;
14683let prefersSlot3 = 1;
14684let Constraints = "$Rx32 = $Rx32in";
14685}
14686def M2_mpy_acc_hl_s0 : HInst<
14687(outs IntRegs:$Rx32),
14688(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14689"$Rx32 += mpy($Rs32.h,$Rt32.l)",
14690tc_7f8ae742, TypeM>, Enc_2ae154 {
14691let Inst{7-5} = 0b010;
14692let Inst{13-13} = 0b0;
14693let Inst{31-21} = 0b11101110000;
14694let hasNewValue = 1;
14695let opNewValue = 0;
14696let prefersSlot3 = 1;
14697let Constraints = "$Rx32 = $Rx32in";
14698}
14699def M2_mpy_acc_hl_s1 : HInst<
14700(outs IntRegs:$Rx32),
14701(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14702"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
14703tc_7f8ae742, TypeM>, Enc_2ae154 {
14704let Inst{7-5} = 0b010;
14705let Inst{13-13} = 0b0;
14706let Inst{31-21} = 0b11101110100;
14707let hasNewValue = 1;
14708let opNewValue = 0;
14709let prefersSlot3 = 1;
14710let Constraints = "$Rx32 = $Rx32in";
14711}
14712def M2_mpy_acc_lh_s0 : HInst<
14713(outs IntRegs:$Rx32),
14714(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14715"$Rx32 += mpy($Rs32.l,$Rt32.h)",
14716tc_7f8ae742, TypeM>, Enc_2ae154 {
14717let Inst{7-5} = 0b001;
14718let Inst{13-13} = 0b0;
14719let Inst{31-21} = 0b11101110000;
14720let hasNewValue = 1;
14721let opNewValue = 0;
14722let prefersSlot3 = 1;
14723let Constraints = "$Rx32 = $Rx32in";
14724}
14725def M2_mpy_acc_lh_s1 : HInst<
14726(outs IntRegs:$Rx32),
14727(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14728"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
14729tc_7f8ae742, TypeM>, Enc_2ae154 {
14730let Inst{7-5} = 0b001;
14731let Inst{13-13} = 0b0;
14732let Inst{31-21} = 0b11101110100;
14733let hasNewValue = 1;
14734let opNewValue = 0;
14735let prefersSlot3 = 1;
14736let Constraints = "$Rx32 = $Rx32in";
14737}
14738def M2_mpy_acc_ll_s0 : HInst<
14739(outs IntRegs:$Rx32),
14740(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14741"$Rx32 += mpy($Rs32.l,$Rt32.l)",
14742tc_7f8ae742, TypeM>, Enc_2ae154 {
14743let Inst{7-5} = 0b000;
14744let Inst{13-13} = 0b0;
14745let Inst{31-21} = 0b11101110000;
14746let hasNewValue = 1;
14747let opNewValue = 0;
14748let prefersSlot3 = 1;
14749let Constraints = "$Rx32 = $Rx32in";
14750}
14751def M2_mpy_acc_ll_s1 : HInst<
14752(outs IntRegs:$Rx32),
14753(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14754"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
14755tc_7f8ae742, TypeM>, Enc_2ae154 {
14756let Inst{7-5} = 0b000;
14757let Inst{13-13} = 0b0;
14758let Inst{31-21} = 0b11101110100;
14759let hasNewValue = 1;
14760let opNewValue = 0;
14761let prefersSlot3 = 1;
14762let Constraints = "$Rx32 = $Rx32in";
14763}
14764def M2_mpy_acc_sat_hh_s0 : HInst<
14765(outs IntRegs:$Rx32),
14766(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14767"$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
14768tc_7f8ae742, TypeM>, Enc_2ae154 {
14769let Inst{7-5} = 0b111;
14770let Inst{13-13} = 0b0;
14771let Inst{31-21} = 0b11101110000;
14772let hasNewValue = 1;
14773let opNewValue = 0;
14774let prefersSlot3 = 1;
14775let Defs = [USR_OVF];
14776let Constraints = "$Rx32 = $Rx32in";
14777}
14778def M2_mpy_acc_sat_hh_s1 : HInst<
14779(outs IntRegs:$Rx32),
14780(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14781"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
14782tc_7f8ae742, TypeM>, Enc_2ae154 {
14783let Inst{7-5} = 0b111;
14784let Inst{13-13} = 0b0;
14785let Inst{31-21} = 0b11101110100;
14786let hasNewValue = 1;
14787let opNewValue = 0;
14788let prefersSlot3 = 1;
14789let Defs = [USR_OVF];
14790let Constraints = "$Rx32 = $Rx32in";
14791}
14792def M2_mpy_acc_sat_hl_s0 : HInst<
14793(outs IntRegs:$Rx32),
14794(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14795"$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
14796tc_7f8ae742, TypeM>, Enc_2ae154 {
14797let Inst{7-5} = 0b110;
14798let Inst{13-13} = 0b0;
14799let Inst{31-21} = 0b11101110000;
14800let hasNewValue = 1;
14801let opNewValue = 0;
14802let prefersSlot3 = 1;
14803let Defs = [USR_OVF];
14804let Constraints = "$Rx32 = $Rx32in";
14805}
14806def M2_mpy_acc_sat_hl_s1 : HInst<
14807(outs IntRegs:$Rx32),
14808(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14809"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
14810tc_7f8ae742, TypeM>, Enc_2ae154 {
14811let Inst{7-5} = 0b110;
14812let Inst{13-13} = 0b0;
14813let Inst{31-21} = 0b11101110100;
14814let hasNewValue = 1;
14815let opNewValue = 0;
14816let prefersSlot3 = 1;
14817let Defs = [USR_OVF];
14818let Constraints = "$Rx32 = $Rx32in";
14819}
14820def M2_mpy_acc_sat_lh_s0 : HInst<
14821(outs IntRegs:$Rx32),
14822(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14823"$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
14824tc_7f8ae742, TypeM>, Enc_2ae154 {
14825let Inst{7-5} = 0b101;
14826let Inst{13-13} = 0b0;
14827let Inst{31-21} = 0b11101110000;
14828let hasNewValue = 1;
14829let opNewValue = 0;
14830let prefersSlot3 = 1;
14831let Defs = [USR_OVF];
14832let Constraints = "$Rx32 = $Rx32in";
14833}
14834def M2_mpy_acc_sat_lh_s1 : HInst<
14835(outs IntRegs:$Rx32),
14836(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14837"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
14838tc_7f8ae742, TypeM>, Enc_2ae154 {
14839let Inst{7-5} = 0b101;
14840let Inst{13-13} = 0b0;
14841let Inst{31-21} = 0b11101110100;
14842let hasNewValue = 1;
14843let opNewValue = 0;
14844let prefersSlot3 = 1;
14845let Defs = [USR_OVF];
14846let Constraints = "$Rx32 = $Rx32in";
14847}
14848def M2_mpy_acc_sat_ll_s0 : HInst<
14849(outs IntRegs:$Rx32),
14850(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14851"$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
14852tc_7f8ae742, TypeM>, Enc_2ae154 {
14853let Inst{7-5} = 0b100;
14854let Inst{13-13} = 0b0;
14855let Inst{31-21} = 0b11101110000;
14856let hasNewValue = 1;
14857let opNewValue = 0;
14858let prefersSlot3 = 1;
14859let Defs = [USR_OVF];
14860let Constraints = "$Rx32 = $Rx32in";
14861}
14862def M2_mpy_acc_sat_ll_s1 : HInst<
14863(outs IntRegs:$Rx32),
14864(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14865"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
14866tc_7f8ae742, TypeM>, Enc_2ae154 {
14867let Inst{7-5} = 0b100;
14868let Inst{13-13} = 0b0;
14869let Inst{31-21} = 0b11101110100;
14870let hasNewValue = 1;
14871let opNewValue = 0;
14872let prefersSlot3 = 1;
14873let Defs = [USR_OVF];
14874let Constraints = "$Rx32 = $Rx32in";
14875}
14876def M2_mpy_hh_s0 : HInst<
14877(outs IntRegs:$Rd32),
14878(ins IntRegs:$Rs32, IntRegs:$Rt32),
14879"$Rd32 = mpy($Rs32.h,$Rt32.h)",
14880tc_c21d7447, TypeM>, Enc_5ab2be {
14881let Inst{7-5} = 0b011;
14882let Inst{13-13} = 0b0;
14883let Inst{31-21} = 0b11101100000;
14884let hasNewValue = 1;
14885let opNewValue = 0;
14886let prefersSlot3 = 1;
14887}
14888def M2_mpy_hh_s1 : HInst<
14889(outs IntRegs:$Rd32),
14890(ins IntRegs:$Rs32, IntRegs:$Rt32),
14891"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
14892tc_c21d7447, TypeM>, Enc_5ab2be {
14893let Inst{7-5} = 0b011;
14894let Inst{13-13} = 0b0;
14895let Inst{31-21} = 0b11101100100;
14896let hasNewValue = 1;
14897let opNewValue = 0;
14898let prefersSlot3 = 1;
14899}
14900def M2_mpy_hl_s0 : HInst<
14901(outs IntRegs:$Rd32),
14902(ins IntRegs:$Rs32, IntRegs:$Rt32),
14903"$Rd32 = mpy($Rs32.h,$Rt32.l)",
14904tc_c21d7447, TypeM>, Enc_5ab2be {
14905let Inst{7-5} = 0b010;
14906let Inst{13-13} = 0b0;
14907let Inst{31-21} = 0b11101100000;
14908let hasNewValue = 1;
14909let opNewValue = 0;
14910let prefersSlot3 = 1;
14911}
14912def M2_mpy_hl_s1 : HInst<
14913(outs IntRegs:$Rd32),
14914(ins IntRegs:$Rs32, IntRegs:$Rt32),
14915"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
14916tc_c21d7447, TypeM>, Enc_5ab2be {
14917let Inst{7-5} = 0b010;
14918let Inst{13-13} = 0b0;
14919let Inst{31-21} = 0b11101100100;
14920let hasNewValue = 1;
14921let opNewValue = 0;
14922let prefersSlot3 = 1;
14923}
14924def M2_mpy_lh_s0 : HInst<
14925(outs IntRegs:$Rd32),
14926(ins IntRegs:$Rs32, IntRegs:$Rt32),
14927"$Rd32 = mpy($Rs32.l,$Rt32.h)",
14928tc_c21d7447, TypeM>, Enc_5ab2be {
14929let Inst{7-5} = 0b001;
14930let Inst{13-13} = 0b0;
14931let Inst{31-21} = 0b11101100000;
14932let hasNewValue = 1;
14933let opNewValue = 0;
14934let prefersSlot3 = 1;
14935}
14936def M2_mpy_lh_s1 : HInst<
14937(outs IntRegs:$Rd32),
14938(ins IntRegs:$Rs32, IntRegs:$Rt32),
14939"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
14940tc_c21d7447, TypeM>, Enc_5ab2be {
14941let Inst{7-5} = 0b001;
14942let Inst{13-13} = 0b0;
14943let Inst{31-21} = 0b11101100100;
14944let hasNewValue = 1;
14945let opNewValue = 0;
14946let prefersSlot3 = 1;
14947}
14948def M2_mpy_ll_s0 : HInst<
14949(outs IntRegs:$Rd32),
14950(ins IntRegs:$Rs32, IntRegs:$Rt32),
14951"$Rd32 = mpy($Rs32.l,$Rt32.l)",
14952tc_c21d7447, TypeM>, Enc_5ab2be {
14953let Inst{7-5} = 0b000;
14954let Inst{13-13} = 0b0;
14955let Inst{31-21} = 0b11101100000;
14956let hasNewValue = 1;
14957let opNewValue = 0;
14958let prefersSlot3 = 1;
14959}
14960def M2_mpy_ll_s1 : HInst<
14961(outs IntRegs:$Rd32),
14962(ins IntRegs:$Rs32, IntRegs:$Rt32),
14963"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
14964tc_c21d7447, TypeM>, Enc_5ab2be {
14965let Inst{7-5} = 0b000;
14966let Inst{13-13} = 0b0;
14967let Inst{31-21} = 0b11101100100;
14968let hasNewValue = 1;
14969let opNewValue = 0;
14970let prefersSlot3 = 1;
14971}
14972def M2_mpy_nac_hh_s0 : HInst<
14973(outs IntRegs:$Rx32),
14974(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14975"$Rx32 -= mpy($Rs32.h,$Rt32.h)",
14976tc_7f8ae742, TypeM>, Enc_2ae154 {
14977let Inst{7-5} = 0b011;
14978let Inst{13-13} = 0b0;
14979let Inst{31-21} = 0b11101110001;
14980let hasNewValue = 1;
14981let opNewValue = 0;
14982let prefersSlot3 = 1;
14983let Constraints = "$Rx32 = $Rx32in";
14984}
14985def M2_mpy_nac_hh_s1 : HInst<
14986(outs IntRegs:$Rx32),
14987(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14988"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
14989tc_7f8ae742, TypeM>, Enc_2ae154 {
14990let Inst{7-5} = 0b011;
14991let Inst{13-13} = 0b0;
14992let Inst{31-21} = 0b11101110101;
14993let hasNewValue = 1;
14994let opNewValue = 0;
14995let prefersSlot3 = 1;
14996let Constraints = "$Rx32 = $Rx32in";
14997}
14998def M2_mpy_nac_hl_s0 : HInst<
14999(outs IntRegs:$Rx32),
15000(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15001"$Rx32 -= mpy($Rs32.h,$Rt32.l)",
15002tc_7f8ae742, TypeM>, Enc_2ae154 {
15003let Inst{7-5} = 0b010;
15004let Inst{13-13} = 0b0;
15005let Inst{31-21} = 0b11101110001;
15006let hasNewValue = 1;
15007let opNewValue = 0;
15008let prefersSlot3 = 1;
15009let Constraints = "$Rx32 = $Rx32in";
15010}
15011def M2_mpy_nac_hl_s1 : HInst<
15012(outs IntRegs:$Rx32),
15013(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15014"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15015tc_7f8ae742, TypeM>, Enc_2ae154 {
15016let Inst{7-5} = 0b010;
15017let Inst{13-13} = 0b0;
15018let Inst{31-21} = 0b11101110101;
15019let hasNewValue = 1;
15020let opNewValue = 0;
15021let prefersSlot3 = 1;
15022let Constraints = "$Rx32 = $Rx32in";
15023}
15024def M2_mpy_nac_lh_s0 : HInst<
15025(outs IntRegs:$Rx32),
15026(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15027"$Rx32 -= mpy($Rs32.l,$Rt32.h)",
15028tc_7f8ae742, TypeM>, Enc_2ae154 {
15029let Inst{7-5} = 0b001;
15030let Inst{13-13} = 0b0;
15031let Inst{31-21} = 0b11101110001;
15032let hasNewValue = 1;
15033let opNewValue = 0;
15034let prefersSlot3 = 1;
15035let Constraints = "$Rx32 = $Rx32in";
15036}
15037def M2_mpy_nac_lh_s1 : HInst<
15038(outs IntRegs:$Rx32),
15039(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15040"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15041tc_7f8ae742, TypeM>, Enc_2ae154 {
15042let Inst{7-5} = 0b001;
15043let Inst{13-13} = 0b0;
15044let Inst{31-21} = 0b11101110101;
15045let hasNewValue = 1;
15046let opNewValue = 0;
15047let prefersSlot3 = 1;
15048let Constraints = "$Rx32 = $Rx32in";
15049}
15050def M2_mpy_nac_ll_s0 : HInst<
15051(outs IntRegs:$Rx32),
15052(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15053"$Rx32 -= mpy($Rs32.l,$Rt32.l)",
15054tc_7f8ae742, TypeM>, Enc_2ae154 {
15055let Inst{7-5} = 0b000;
15056let Inst{13-13} = 0b0;
15057let Inst{31-21} = 0b11101110001;
15058let hasNewValue = 1;
15059let opNewValue = 0;
15060let prefersSlot3 = 1;
15061let Constraints = "$Rx32 = $Rx32in";
15062}
15063def M2_mpy_nac_ll_s1 : HInst<
15064(outs IntRegs:$Rx32),
15065(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15066"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15067tc_7f8ae742, TypeM>, Enc_2ae154 {
15068let Inst{7-5} = 0b000;
15069let Inst{13-13} = 0b0;
15070let Inst{31-21} = 0b11101110101;
15071let hasNewValue = 1;
15072let opNewValue = 0;
15073let prefersSlot3 = 1;
15074let Constraints = "$Rx32 = $Rx32in";
15075}
15076def M2_mpy_nac_sat_hh_s0 : HInst<
15077(outs IntRegs:$Rx32),
15078(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15079"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
15080tc_7f8ae742, TypeM>, Enc_2ae154 {
15081let Inst{7-5} = 0b111;
15082let Inst{13-13} = 0b0;
15083let Inst{31-21} = 0b11101110001;
15084let hasNewValue = 1;
15085let opNewValue = 0;
15086let prefersSlot3 = 1;
15087let Defs = [USR_OVF];
15088let Constraints = "$Rx32 = $Rx32in";
15089}
15090def M2_mpy_nac_sat_hh_s1 : HInst<
15091(outs IntRegs:$Rx32),
15092(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15093"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
15094tc_7f8ae742, TypeM>, Enc_2ae154 {
15095let Inst{7-5} = 0b111;
15096let Inst{13-13} = 0b0;
15097let Inst{31-21} = 0b11101110101;
15098let hasNewValue = 1;
15099let opNewValue = 0;
15100let prefersSlot3 = 1;
15101let Defs = [USR_OVF];
15102let Constraints = "$Rx32 = $Rx32in";
15103}
15104def M2_mpy_nac_sat_hl_s0 : HInst<
15105(outs IntRegs:$Rx32),
15106(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15107"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
15108tc_7f8ae742, TypeM>, Enc_2ae154 {
15109let Inst{7-5} = 0b110;
15110let Inst{13-13} = 0b0;
15111let Inst{31-21} = 0b11101110001;
15112let hasNewValue = 1;
15113let opNewValue = 0;
15114let prefersSlot3 = 1;
15115let Defs = [USR_OVF];
15116let Constraints = "$Rx32 = $Rx32in";
15117}
15118def M2_mpy_nac_sat_hl_s1 : HInst<
15119(outs IntRegs:$Rx32),
15120(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15121"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
15122tc_7f8ae742, TypeM>, Enc_2ae154 {
15123let Inst{7-5} = 0b110;
15124let Inst{13-13} = 0b0;
15125let Inst{31-21} = 0b11101110101;
15126let hasNewValue = 1;
15127let opNewValue = 0;
15128let prefersSlot3 = 1;
15129let Defs = [USR_OVF];
15130let Constraints = "$Rx32 = $Rx32in";
15131}
15132def M2_mpy_nac_sat_lh_s0 : HInst<
15133(outs IntRegs:$Rx32),
15134(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15135"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
15136tc_7f8ae742, TypeM>, Enc_2ae154 {
15137let Inst{7-5} = 0b101;
15138let Inst{13-13} = 0b0;
15139let Inst{31-21} = 0b11101110001;
15140let hasNewValue = 1;
15141let opNewValue = 0;
15142let prefersSlot3 = 1;
15143let Defs = [USR_OVF];
15144let Constraints = "$Rx32 = $Rx32in";
15145}
15146def M2_mpy_nac_sat_lh_s1 : HInst<
15147(outs IntRegs:$Rx32),
15148(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15149"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
15150tc_7f8ae742, TypeM>, Enc_2ae154 {
15151let Inst{7-5} = 0b101;
15152let Inst{13-13} = 0b0;
15153let Inst{31-21} = 0b11101110101;
15154let hasNewValue = 1;
15155let opNewValue = 0;
15156let prefersSlot3 = 1;
15157let Defs = [USR_OVF];
15158let Constraints = "$Rx32 = $Rx32in";
15159}
15160def M2_mpy_nac_sat_ll_s0 : HInst<
15161(outs IntRegs:$Rx32),
15162(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15163"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
15164tc_7f8ae742, TypeM>, Enc_2ae154 {
15165let Inst{7-5} = 0b100;
15166let Inst{13-13} = 0b0;
15167let Inst{31-21} = 0b11101110001;
15168let hasNewValue = 1;
15169let opNewValue = 0;
15170let prefersSlot3 = 1;
15171let Defs = [USR_OVF];
15172let Constraints = "$Rx32 = $Rx32in";
15173}
15174def M2_mpy_nac_sat_ll_s1 : HInst<
15175(outs IntRegs:$Rx32),
15176(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15177"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
15178tc_7f8ae742, TypeM>, Enc_2ae154 {
15179let Inst{7-5} = 0b100;
15180let Inst{13-13} = 0b0;
15181let Inst{31-21} = 0b11101110101;
15182let hasNewValue = 1;
15183let opNewValue = 0;
15184let prefersSlot3 = 1;
15185let Defs = [USR_OVF];
15186let Constraints = "$Rx32 = $Rx32in";
15187}
15188def M2_mpy_rnd_hh_s0 : HInst<
15189(outs IntRegs:$Rd32),
15190(ins IntRegs:$Rs32, IntRegs:$Rt32),
15191"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
15192tc_c21d7447, TypeM>, Enc_5ab2be {
15193let Inst{7-5} = 0b011;
15194let Inst{13-13} = 0b0;
15195let Inst{31-21} = 0b11101100001;
15196let hasNewValue = 1;
15197let opNewValue = 0;
15198let prefersSlot3 = 1;
15199}
15200def M2_mpy_rnd_hh_s1 : HInst<
15201(outs IntRegs:$Rd32),
15202(ins IntRegs:$Rs32, IntRegs:$Rt32),
15203"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15204tc_c21d7447, TypeM>, Enc_5ab2be {
15205let Inst{7-5} = 0b011;
15206let Inst{13-13} = 0b0;
15207let Inst{31-21} = 0b11101100101;
15208let hasNewValue = 1;
15209let opNewValue = 0;
15210let prefersSlot3 = 1;
15211}
15212def M2_mpy_rnd_hl_s0 : HInst<
15213(outs IntRegs:$Rd32),
15214(ins IntRegs:$Rs32, IntRegs:$Rt32),
15215"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
15216tc_c21d7447, TypeM>, Enc_5ab2be {
15217let Inst{7-5} = 0b010;
15218let Inst{13-13} = 0b0;
15219let Inst{31-21} = 0b11101100001;
15220let hasNewValue = 1;
15221let opNewValue = 0;
15222let prefersSlot3 = 1;
15223}
15224def M2_mpy_rnd_hl_s1 : HInst<
15225(outs IntRegs:$Rd32),
15226(ins IntRegs:$Rs32, IntRegs:$Rt32),
15227"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15228tc_c21d7447, TypeM>, Enc_5ab2be {
15229let Inst{7-5} = 0b010;
15230let Inst{13-13} = 0b0;
15231let Inst{31-21} = 0b11101100101;
15232let hasNewValue = 1;
15233let opNewValue = 0;
15234let prefersSlot3 = 1;
15235}
15236def M2_mpy_rnd_lh_s0 : HInst<
15237(outs IntRegs:$Rd32),
15238(ins IntRegs:$Rs32, IntRegs:$Rt32),
15239"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
15240tc_c21d7447, TypeM>, Enc_5ab2be {
15241let Inst{7-5} = 0b001;
15242let Inst{13-13} = 0b0;
15243let Inst{31-21} = 0b11101100001;
15244let hasNewValue = 1;
15245let opNewValue = 0;
15246let prefersSlot3 = 1;
15247}
15248def M2_mpy_rnd_lh_s1 : HInst<
15249(outs IntRegs:$Rd32),
15250(ins IntRegs:$Rs32, IntRegs:$Rt32),
15251"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15252tc_c21d7447, TypeM>, Enc_5ab2be {
15253let Inst{7-5} = 0b001;
15254let Inst{13-13} = 0b0;
15255let Inst{31-21} = 0b11101100101;
15256let hasNewValue = 1;
15257let opNewValue = 0;
15258let prefersSlot3 = 1;
15259}
15260def M2_mpy_rnd_ll_s0 : HInst<
15261(outs IntRegs:$Rd32),
15262(ins IntRegs:$Rs32, IntRegs:$Rt32),
15263"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
15264tc_c21d7447, TypeM>, Enc_5ab2be {
15265let Inst{7-5} = 0b000;
15266let Inst{13-13} = 0b0;
15267let Inst{31-21} = 0b11101100001;
15268let hasNewValue = 1;
15269let opNewValue = 0;
15270let prefersSlot3 = 1;
15271}
15272def M2_mpy_rnd_ll_s1 : HInst<
15273(outs IntRegs:$Rd32),
15274(ins IntRegs:$Rs32, IntRegs:$Rt32),
15275"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15276tc_c21d7447, TypeM>, Enc_5ab2be {
15277let Inst{7-5} = 0b000;
15278let Inst{13-13} = 0b0;
15279let Inst{31-21} = 0b11101100101;
15280let hasNewValue = 1;
15281let opNewValue = 0;
15282let prefersSlot3 = 1;
15283}
15284def M2_mpy_sat_hh_s0 : HInst<
15285(outs IntRegs:$Rd32),
15286(ins IntRegs:$Rs32, IntRegs:$Rt32),
15287"$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
15288tc_c21d7447, TypeM>, Enc_5ab2be {
15289let Inst{7-5} = 0b111;
15290let Inst{13-13} = 0b0;
15291let Inst{31-21} = 0b11101100000;
15292let hasNewValue = 1;
15293let opNewValue = 0;
15294let prefersSlot3 = 1;
15295let Defs = [USR_OVF];
15296}
15297def M2_mpy_sat_hh_s1 : HInst<
15298(outs IntRegs:$Rd32),
15299(ins IntRegs:$Rs32, IntRegs:$Rt32),
15300"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
15301tc_c21d7447, TypeM>, Enc_5ab2be {
15302let Inst{7-5} = 0b111;
15303let Inst{13-13} = 0b0;
15304let Inst{31-21} = 0b11101100100;
15305let hasNewValue = 1;
15306let opNewValue = 0;
15307let prefersSlot3 = 1;
15308let Defs = [USR_OVF];
15309}
15310def M2_mpy_sat_hl_s0 : HInst<
15311(outs IntRegs:$Rd32),
15312(ins IntRegs:$Rs32, IntRegs:$Rt32),
15313"$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
15314tc_c21d7447, TypeM>, Enc_5ab2be {
15315let Inst{7-5} = 0b110;
15316let Inst{13-13} = 0b0;
15317let Inst{31-21} = 0b11101100000;
15318let hasNewValue = 1;
15319let opNewValue = 0;
15320let prefersSlot3 = 1;
15321let Defs = [USR_OVF];
15322}
15323def M2_mpy_sat_hl_s1 : HInst<
15324(outs IntRegs:$Rd32),
15325(ins IntRegs:$Rs32, IntRegs:$Rt32),
15326"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
15327tc_c21d7447, TypeM>, Enc_5ab2be {
15328let Inst{7-5} = 0b110;
15329let Inst{13-13} = 0b0;
15330let Inst{31-21} = 0b11101100100;
15331let hasNewValue = 1;
15332let opNewValue = 0;
15333let prefersSlot3 = 1;
15334let Defs = [USR_OVF];
15335}
15336def M2_mpy_sat_lh_s0 : HInst<
15337(outs IntRegs:$Rd32),
15338(ins IntRegs:$Rs32, IntRegs:$Rt32),
15339"$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
15340tc_c21d7447, TypeM>, Enc_5ab2be {
15341let Inst{7-5} = 0b101;
15342let Inst{13-13} = 0b0;
15343let Inst{31-21} = 0b11101100000;
15344let hasNewValue = 1;
15345let opNewValue = 0;
15346let prefersSlot3 = 1;
15347let Defs = [USR_OVF];
15348}
15349def M2_mpy_sat_lh_s1 : HInst<
15350(outs IntRegs:$Rd32),
15351(ins IntRegs:$Rs32, IntRegs:$Rt32),
15352"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
15353tc_c21d7447, TypeM>, Enc_5ab2be {
15354let Inst{7-5} = 0b101;
15355let Inst{13-13} = 0b0;
15356let Inst{31-21} = 0b11101100100;
15357let hasNewValue = 1;
15358let opNewValue = 0;
15359let prefersSlot3 = 1;
15360let Defs = [USR_OVF];
15361}
15362def M2_mpy_sat_ll_s0 : HInst<
15363(outs IntRegs:$Rd32),
15364(ins IntRegs:$Rs32, IntRegs:$Rt32),
15365"$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
15366tc_c21d7447, TypeM>, Enc_5ab2be {
15367let Inst{7-5} = 0b100;
15368let Inst{13-13} = 0b0;
15369let Inst{31-21} = 0b11101100000;
15370let hasNewValue = 1;
15371let opNewValue = 0;
15372let prefersSlot3 = 1;
15373let Defs = [USR_OVF];
15374}
15375def M2_mpy_sat_ll_s1 : HInst<
15376(outs IntRegs:$Rd32),
15377(ins IntRegs:$Rs32, IntRegs:$Rt32),
15378"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
15379tc_c21d7447, TypeM>, Enc_5ab2be {
15380let Inst{7-5} = 0b100;
15381let Inst{13-13} = 0b0;
15382let Inst{31-21} = 0b11101100100;
15383let hasNewValue = 1;
15384let opNewValue = 0;
15385let prefersSlot3 = 1;
15386let Defs = [USR_OVF];
15387}
15388def M2_mpy_sat_rnd_hh_s0 : HInst<
15389(outs IntRegs:$Rd32),
15390(ins IntRegs:$Rs32, IntRegs:$Rt32),
15391"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
15392tc_c21d7447, TypeM>, Enc_5ab2be {
15393let Inst{7-5} = 0b111;
15394let Inst{13-13} = 0b0;
15395let Inst{31-21} = 0b11101100001;
15396let hasNewValue = 1;
15397let opNewValue = 0;
15398let prefersSlot3 = 1;
15399let Defs = [USR_OVF];
15400}
15401def M2_mpy_sat_rnd_hh_s1 : HInst<
15402(outs IntRegs:$Rd32),
15403(ins IntRegs:$Rs32, IntRegs:$Rt32),
15404"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
15405tc_c21d7447, TypeM>, Enc_5ab2be {
15406let Inst{7-5} = 0b111;
15407let Inst{13-13} = 0b0;
15408let Inst{31-21} = 0b11101100101;
15409let hasNewValue = 1;
15410let opNewValue = 0;
15411let prefersSlot3 = 1;
15412let Defs = [USR_OVF];
15413}
15414def M2_mpy_sat_rnd_hl_s0 : HInst<
15415(outs IntRegs:$Rd32),
15416(ins IntRegs:$Rs32, IntRegs:$Rt32),
15417"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
15418tc_c21d7447, TypeM>, Enc_5ab2be {
15419let Inst{7-5} = 0b110;
15420let Inst{13-13} = 0b0;
15421let Inst{31-21} = 0b11101100001;
15422let hasNewValue = 1;
15423let opNewValue = 0;
15424let prefersSlot3 = 1;
15425let Defs = [USR_OVF];
15426}
15427def M2_mpy_sat_rnd_hl_s1 : HInst<
15428(outs IntRegs:$Rd32),
15429(ins IntRegs:$Rs32, IntRegs:$Rt32),
15430"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
15431tc_c21d7447, TypeM>, Enc_5ab2be {
15432let Inst{7-5} = 0b110;
15433let Inst{13-13} = 0b0;
15434let Inst{31-21} = 0b11101100101;
15435let hasNewValue = 1;
15436let opNewValue = 0;
15437let prefersSlot3 = 1;
15438let Defs = [USR_OVF];
15439}
15440def M2_mpy_sat_rnd_lh_s0 : HInst<
15441(outs IntRegs:$Rd32),
15442(ins IntRegs:$Rs32, IntRegs:$Rt32),
15443"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
15444tc_c21d7447, TypeM>, Enc_5ab2be {
15445let Inst{7-5} = 0b101;
15446let Inst{13-13} = 0b0;
15447let Inst{31-21} = 0b11101100001;
15448let hasNewValue = 1;
15449let opNewValue = 0;
15450let prefersSlot3 = 1;
15451let Defs = [USR_OVF];
15452}
15453def M2_mpy_sat_rnd_lh_s1 : HInst<
15454(outs IntRegs:$Rd32),
15455(ins IntRegs:$Rs32, IntRegs:$Rt32),
15456"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
15457tc_c21d7447, TypeM>, Enc_5ab2be {
15458let Inst{7-5} = 0b101;
15459let Inst{13-13} = 0b0;
15460let Inst{31-21} = 0b11101100101;
15461let hasNewValue = 1;
15462let opNewValue = 0;
15463let prefersSlot3 = 1;
15464let Defs = [USR_OVF];
15465}
15466def M2_mpy_sat_rnd_ll_s0 : HInst<
15467(outs IntRegs:$Rd32),
15468(ins IntRegs:$Rs32, IntRegs:$Rt32),
15469"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
15470tc_c21d7447, TypeM>, Enc_5ab2be {
15471let Inst{7-5} = 0b100;
15472let Inst{13-13} = 0b0;
15473let Inst{31-21} = 0b11101100001;
15474let hasNewValue = 1;
15475let opNewValue = 0;
15476let prefersSlot3 = 1;
15477let Defs = [USR_OVF];
15478}
15479def M2_mpy_sat_rnd_ll_s1 : HInst<
15480(outs IntRegs:$Rd32),
15481(ins IntRegs:$Rs32, IntRegs:$Rt32),
15482"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
15483tc_c21d7447, TypeM>, Enc_5ab2be {
15484let Inst{7-5} = 0b100;
15485let Inst{13-13} = 0b0;
15486let Inst{31-21} = 0b11101100101;
15487let hasNewValue = 1;
15488let opNewValue = 0;
15489let prefersSlot3 = 1;
15490let Defs = [USR_OVF];
15491}
15492def M2_mpy_up : HInst<
15493(outs IntRegs:$Rd32),
15494(ins IntRegs:$Rs32, IntRegs:$Rt32),
15495"$Rd32 = mpy($Rs32,$Rt32)",
15496tc_c21d7447, TypeM>, Enc_5ab2be {
15497let Inst{7-5} = 0b001;
15498let Inst{13-13} = 0b0;
15499let Inst{31-21} = 0b11101101000;
15500let hasNewValue = 1;
15501let opNewValue = 0;
15502let prefersSlot3 = 1;
15503}
15504def M2_mpy_up_s1 : HInst<
15505(outs IntRegs:$Rd32),
15506(ins IntRegs:$Rs32, IntRegs:$Rt32),
15507"$Rd32 = mpy($Rs32,$Rt32):<<1",
15508tc_c21d7447, TypeM>, Enc_5ab2be {
15509let Inst{7-5} = 0b010;
15510let Inst{13-13} = 0b0;
15511let Inst{31-21} = 0b11101101101;
15512let hasNewValue = 1;
15513let opNewValue = 0;
15514let prefersSlot3 = 1;
15515}
15516def M2_mpy_up_s1_sat : HInst<
15517(outs IntRegs:$Rd32),
15518(ins IntRegs:$Rs32, IntRegs:$Rt32),
15519"$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
15520tc_c21d7447, TypeM>, Enc_5ab2be {
15521let Inst{7-5} = 0b000;
15522let Inst{13-13} = 0b0;
15523let Inst{31-21} = 0b11101101111;
15524let hasNewValue = 1;
15525let opNewValue = 0;
15526let prefersSlot3 = 1;
15527let Defs = [USR_OVF];
15528}
15529def M2_mpyd_acc_hh_s0 : HInst<
15530(outs DoubleRegs:$Rxx32),
15531(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15532"$Rxx32 += mpy($Rs32.h,$Rt32.h)",
15533tc_7f8ae742, TypeM>, Enc_61f0b0 {
15534let Inst{7-5} = 0b011;
15535let Inst{13-13} = 0b0;
15536let Inst{31-21} = 0b11100110000;
15537let prefersSlot3 = 1;
15538let Constraints = "$Rxx32 = $Rxx32in";
15539}
15540def M2_mpyd_acc_hh_s1 : HInst<
15541(outs DoubleRegs:$Rxx32),
15542(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15543"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
15544tc_7f8ae742, TypeM>, Enc_61f0b0 {
15545let Inst{7-5} = 0b011;
15546let Inst{13-13} = 0b0;
15547let Inst{31-21} = 0b11100110100;
15548let prefersSlot3 = 1;
15549let Constraints = "$Rxx32 = $Rxx32in";
15550}
15551def M2_mpyd_acc_hl_s0 : HInst<
15552(outs DoubleRegs:$Rxx32),
15553(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15554"$Rxx32 += mpy($Rs32.h,$Rt32.l)",
15555tc_7f8ae742, TypeM>, Enc_61f0b0 {
15556let Inst{7-5} = 0b010;
15557let Inst{13-13} = 0b0;
15558let Inst{31-21} = 0b11100110000;
15559let prefersSlot3 = 1;
15560let Constraints = "$Rxx32 = $Rxx32in";
15561}
15562def M2_mpyd_acc_hl_s1 : HInst<
15563(outs DoubleRegs:$Rxx32),
15564(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15565"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
15566tc_7f8ae742, TypeM>, Enc_61f0b0 {
15567let Inst{7-5} = 0b010;
15568let Inst{13-13} = 0b0;
15569let Inst{31-21} = 0b11100110100;
15570let prefersSlot3 = 1;
15571let Constraints = "$Rxx32 = $Rxx32in";
15572}
15573def M2_mpyd_acc_lh_s0 : HInst<
15574(outs DoubleRegs:$Rxx32),
15575(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15576"$Rxx32 += mpy($Rs32.l,$Rt32.h)",
15577tc_7f8ae742, TypeM>, Enc_61f0b0 {
15578let Inst{7-5} = 0b001;
15579let Inst{13-13} = 0b0;
15580let Inst{31-21} = 0b11100110000;
15581let prefersSlot3 = 1;
15582let Constraints = "$Rxx32 = $Rxx32in";
15583}
15584def M2_mpyd_acc_lh_s1 : HInst<
15585(outs DoubleRegs:$Rxx32),
15586(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15587"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
15588tc_7f8ae742, TypeM>, Enc_61f0b0 {
15589let Inst{7-5} = 0b001;
15590let Inst{13-13} = 0b0;
15591let Inst{31-21} = 0b11100110100;
15592let prefersSlot3 = 1;
15593let Constraints = "$Rxx32 = $Rxx32in";
15594}
15595def M2_mpyd_acc_ll_s0 : HInst<
15596(outs DoubleRegs:$Rxx32),
15597(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15598"$Rxx32 += mpy($Rs32.l,$Rt32.l)",
15599tc_7f8ae742, TypeM>, Enc_61f0b0 {
15600let Inst{7-5} = 0b000;
15601let Inst{13-13} = 0b0;
15602let Inst{31-21} = 0b11100110000;
15603let prefersSlot3 = 1;
15604let Constraints = "$Rxx32 = $Rxx32in";
15605}
15606def M2_mpyd_acc_ll_s1 : HInst<
15607(outs DoubleRegs:$Rxx32),
15608(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15609"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
15610tc_7f8ae742, TypeM>, Enc_61f0b0 {
15611let Inst{7-5} = 0b000;
15612let Inst{13-13} = 0b0;
15613let Inst{31-21} = 0b11100110100;
15614let prefersSlot3 = 1;
15615let Constraints = "$Rxx32 = $Rxx32in";
15616}
15617def M2_mpyd_hh_s0 : HInst<
15618(outs DoubleRegs:$Rdd32),
15619(ins IntRegs:$Rs32, IntRegs:$Rt32),
15620"$Rdd32 = mpy($Rs32.h,$Rt32.h)",
15621tc_c21d7447, TypeM>, Enc_be32a5 {
15622let Inst{7-5} = 0b011;
15623let Inst{13-13} = 0b0;
15624let Inst{31-21} = 0b11100100000;
15625let prefersSlot3 = 1;
15626}
15627def M2_mpyd_hh_s1 : HInst<
15628(outs DoubleRegs:$Rdd32),
15629(ins IntRegs:$Rs32, IntRegs:$Rt32),
15630"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
15631tc_c21d7447, TypeM>, Enc_be32a5 {
15632let Inst{7-5} = 0b011;
15633let Inst{13-13} = 0b0;
15634let Inst{31-21} = 0b11100100100;
15635let prefersSlot3 = 1;
15636}
15637def M2_mpyd_hl_s0 : HInst<
15638(outs DoubleRegs:$Rdd32),
15639(ins IntRegs:$Rs32, IntRegs:$Rt32),
15640"$Rdd32 = mpy($Rs32.h,$Rt32.l)",
15641tc_c21d7447, TypeM>, Enc_be32a5 {
15642let Inst{7-5} = 0b010;
15643let Inst{13-13} = 0b0;
15644let Inst{31-21} = 0b11100100000;
15645let prefersSlot3 = 1;
15646}
15647def M2_mpyd_hl_s1 : HInst<
15648(outs DoubleRegs:$Rdd32),
15649(ins IntRegs:$Rs32, IntRegs:$Rt32),
15650"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
15651tc_c21d7447, TypeM>, Enc_be32a5 {
15652let Inst{7-5} = 0b010;
15653let Inst{13-13} = 0b0;
15654let Inst{31-21} = 0b11100100100;
15655let prefersSlot3 = 1;
15656}
15657def M2_mpyd_lh_s0 : HInst<
15658(outs DoubleRegs:$Rdd32),
15659(ins IntRegs:$Rs32, IntRegs:$Rt32),
15660"$Rdd32 = mpy($Rs32.l,$Rt32.h)",
15661tc_c21d7447, TypeM>, Enc_be32a5 {
15662let Inst{7-5} = 0b001;
15663let Inst{13-13} = 0b0;
15664let Inst{31-21} = 0b11100100000;
15665let prefersSlot3 = 1;
15666}
15667def M2_mpyd_lh_s1 : HInst<
15668(outs DoubleRegs:$Rdd32),
15669(ins IntRegs:$Rs32, IntRegs:$Rt32),
15670"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
15671tc_c21d7447, TypeM>, Enc_be32a5 {
15672let Inst{7-5} = 0b001;
15673let Inst{13-13} = 0b0;
15674let Inst{31-21} = 0b11100100100;
15675let prefersSlot3 = 1;
15676}
15677def M2_mpyd_ll_s0 : HInst<
15678(outs DoubleRegs:$Rdd32),
15679(ins IntRegs:$Rs32, IntRegs:$Rt32),
15680"$Rdd32 = mpy($Rs32.l,$Rt32.l)",
15681tc_c21d7447, TypeM>, Enc_be32a5 {
15682let Inst{7-5} = 0b000;
15683let Inst{13-13} = 0b0;
15684let Inst{31-21} = 0b11100100000;
15685let prefersSlot3 = 1;
15686}
15687def M2_mpyd_ll_s1 : HInst<
15688(outs DoubleRegs:$Rdd32),
15689(ins IntRegs:$Rs32, IntRegs:$Rt32),
15690"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
15691tc_c21d7447, TypeM>, Enc_be32a5 {
15692let Inst{7-5} = 0b000;
15693let Inst{13-13} = 0b0;
15694let Inst{31-21} = 0b11100100100;
15695let prefersSlot3 = 1;
15696}
15697def M2_mpyd_nac_hh_s0 : HInst<
15698(outs DoubleRegs:$Rxx32),
15699(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15700"$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
15701tc_7f8ae742, TypeM>, Enc_61f0b0 {
15702let Inst{7-5} = 0b011;
15703let Inst{13-13} = 0b0;
15704let Inst{31-21} = 0b11100110001;
15705let prefersSlot3 = 1;
15706let Constraints = "$Rxx32 = $Rxx32in";
15707}
15708def M2_mpyd_nac_hh_s1 : HInst<
15709(outs DoubleRegs:$Rxx32),
15710(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15711"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15712tc_7f8ae742, TypeM>, Enc_61f0b0 {
15713let Inst{7-5} = 0b011;
15714let Inst{13-13} = 0b0;
15715let Inst{31-21} = 0b11100110101;
15716let prefersSlot3 = 1;
15717let Constraints = "$Rxx32 = $Rxx32in";
15718}
15719def M2_mpyd_nac_hl_s0 : HInst<
15720(outs DoubleRegs:$Rxx32),
15721(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15722"$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
15723tc_7f8ae742, TypeM>, Enc_61f0b0 {
15724let Inst{7-5} = 0b010;
15725let Inst{13-13} = 0b0;
15726let Inst{31-21} = 0b11100110001;
15727let prefersSlot3 = 1;
15728let Constraints = "$Rxx32 = $Rxx32in";
15729}
15730def M2_mpyd_nac_hl_s1 : HInst<
15731(outs DoubleRegs:$Rxx32),
15732(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15733"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15734tc_7f8ae742, TypeM>, Enc_61f0b0 {
15735let Inst{7-5} = 0b010;
15736let Inst{13-13} = 0b0;
15737let Inst{31-21} = 0b11100110101;
15738let prefersSlot3 = 1;
15739let Constraints = "$Rxx32 = $Rxx32in";
15740}
15741def M2_mpyd_nac_lh_s0 : HInst<
15742(outs DoubleRegs:$Rxx32),
15743(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15744"$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
15745tc_7f8ae742, TypeM>, Enc_61f0b0 {
15746let Inst{7-5} = 0b001;
15747let Inst{13-13} = 0b0;
15748let Inst{31-21} = 0b11100110001;
15749let prefersSlot3 = 1;
15750let Constraints = "$Rxx32 = $Rxx32in";
15751}
15752def M2_mpyd_nac_lh_s1 : HInst<
15753(outs DoubleRegs:$Rxx32),
15754(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15755"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15756tc_7f8ae742, TypeM>, Enc_61f0b0 {
15757let Inst{7-5} = 0b001;
15758let Inst{13-13} = 0b0;
15759let Inst{31-21} = 0b11100110101;
15760let prefersSlot3 = 1;
15761let Constraints = "$Rxx32 = $Rxx32in";
15762}
15763def M2_mpyd_nac_ll_s0 : HInst<
15764(outs DoubleRegs:$Rxx32),
15765(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15766"$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
15767tc_7f8ae742, TypeM>, Enc_61f0b0 {
15768let Inst{7-5} = 0b000;
15769let Inst{13-13} = 0b0;
15770let Inst{31-21} = 0b11100110001;
15771let prefersSlot3 = 1;
15772let Constraints = "$Rxx32 = $Rxx32in";
15773}
15774def M2_mpyd_nac_ll_s1 : HInst<
15775(outs DoubleRegs:$Rxx32),
15776(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15777"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15778tc_7f8ae742, TypeM>, Enc_61f0b0 {
15779let Inst{7-5} = 0b000;
15780let Inst{13-13} = 0b0;
15781let Inst{31-21} = 0b11100110101;
15782let prefersSlot3 = 1;
15783let Constraints = "$Rxx32 = $Rxx32in";
15784}
15785def M2_mpyd_rnd_hh_s0 : HInst<
15786(outs DoubleRegs:$Rdd32),
15787(ins IntRegs:$Rs32, IntRegs:$Rt32),
15788"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
15789tc_c21d7447, TypeM>, Enc_be32a5 {
15790let Inst{7-5} = 0b011;
15791let Inst{13-13} = 0b0;
15792let Inst{31-21} = 0b11100100001;
15793let prefersSlot3 = 1;
15794}
15795def M2_mpyd_rnd_hh_s1 : HInst<
15796(outs DoubleRegs:$Rdd32),
15797(ins IntRegs:$Rs32, IntRegs:$Rt32),
15798"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15799tc_c21d7447, TypeM>, Enc_be32a5 {
15800let Inst{7-5} = 0b011;
15801let Inst{13-13} = 0b0;
15802let Inst{31-21} = 0b11100100101;
15803let prefersSlot3 = 1;
15804}
15805def M2_mpyd_rnd_hl_s0 : HInst<
15806(outs DoubleRegs:$Rdd32),
15807(ins IntRegs:$Rs32, IntRegs:$Rt32),
15808"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
15809tc_c21d7447, TypeM>, Enc_be32a5 {
15810let Inst{7-5} = 0b010;
15811let Inst{13-13} = 0b0;
15812let Inst{31-21} = 0b11100100001;
15813let prefersSlot3 = 1;
15814}
15815def M2_mpyd_rnd_hl_s1 : HInst<
15816(outs DoubleRegs:$Rdd32),
15817(ins IntRegs:$Rs32, IntRegs:$Rt32),
15818"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15819tc_c21d7447, TypeM>, Enc_be32a5 {
15820let Inst{7-5} = 0b010;
15821let Inst{13-13} = 0b0;
15822let Inst{31-21} = 0b11100100101;
15823let prefersSlot3 = 1;
15824}
15825def M2_mpyd_rnd_lh_s0 : HInst<
15826(outs DoubleRegs:$Rdd32),
15827(ins IntRegs:$Rs32, IntRegs:$Rt32),
15828"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
15829tc_c21d7447, TypeM>, Enc_be32a5 {
15830let Inst{7-5} = 0b001;
15831let Inst{13-13} = 0b0;
15832let Inst{31-21} = 0b11100100001;
15833let prefersSlot3 = 1;
15834}
15835def M2_mpyd_rnd_lh_s1 : HInst<
15836(outs DoubleRegs:$Rdd32),
15837(ins IntRegs:$Rs32, IntRegs:$Rt32),
15838"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15839tc_c21d7447, TypeM>, Enc_be32a5 {
15840let Inst{7-5} = 0b001;
15841let Inst{13-13} = 0b0;
15842let Inst{31-21} = 0b11100100101;
15843let prefersSlot3 = 1;
15844}
15845def M2_mpyd_rnd_ll_s0 : HInst<
15846(outs DoubleRegs:$Rdd32),
15847(ins IntRegs:$Rs32, IntRegs:$Rt32),
15848"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
15849tc_c21d7447, TypeM>, Enc_be32a5 {
15850let Inst{7-5} = 0b000;
15851let Inst{13-13} = 0b0;
15852let Inst{31-21} = 0b11100100001;
15853let prefersSlot3 = 1;
15854}
15855def M2_mpyd_rnd_ll_s1 : HInst<
15856(outs DoubleRegs:$Rdd32),
15857(ins IntRegs:$Rs32, IntRegs:$Rt32),
15858"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15859tc_c21d7447, TypeM>, Enc_be32a5 {
15860let Inst{7-5} = 0b000;
15861let Inst{13-13} = 0b0;
15862let Inst{31-21} = 0b11100100101;
15863let prefersSlot3 = 1;
15864}
15865def M2_mpyi : HInst<
15866(outs IntRegs:$Rd32),
15867(ins IntRegs:$Rs32, IntRegs:$Rt32),
15868"$Rd32 = mpyi($Rs32,$Rt32)",
15869tc_c21d7447, TypeM>, Enc_5ab2be, ImmRegRel {
15870let Inst{7-5} = 0b000;
15871let Inst{13-13} = 0b0;
15872let Inst{31-21} = 0b11101101000;
15873let hasNewValue = 1;
15874let opNewValue = 0;
15875let prefersSlot3 = 1;
15876let CextOpcode = "M2_mpyi";
15877let InputType = "reg";
15878}
15879def M2_mpysin : HInst<
15880(outs IntRegs:$Rd32),
15881(ins IntRegs:$Rs32, u8_0Imm:$Ii),
15882"$Rd32 = -mpyi($Rs32,#$Ii)",
15883tc_38382228, TypeM>, Enc_b8c967 {
15884let Inst{13-13} = 0b0;
15885let Inst{31-21} = 0b11100000100;
15886let hasNewValue = 1;
15887let opNewValue = 0;
15888let prefersSlot3 = 1;
15889}
15890def M2_mpysip : HInst<
15891(outs IntRegs:$Rd32),
15892(ins IntRegs:$Rs32, u32_0Imm:$Ii),
15893"$Rd32 = +mpyi($Rs32,#$Ii)",
15894tc_38382228, TypeM>, Enc_b8c967 {
15895let Inst{13-13} = 0b0;
15896let Inst{31-21} = 0b11100000000;
15897let hasNewValue = 1;
15898let opNewValue = 0;
15899let prefersSlot3 = 1;
15900let isExtendable = 1;
15901let opExtendable = 2;
15902let isExtentSigned = 0;
15903let opExtentBits = 8;
15904let opExtentAlign = 0;
15905}
15906def M2_mpysmi : HInst<
15907(outs IntRegs:$Rd32),
15908(ins IntRegs:$Rs32, m32_0Imm:$Ii),
15909"$Rd32 = mpyi($Rs32,#$Ii)",
15910tc_38382228, TypeM>, ImmRegRel {
15911let hasNewValue = 1;
15912let opNewValue = 0;
15913let CextOpcode = "M2_mpyi";
15914let InputType = "imm";
15915let isPseudo = 1;
15916let isExtendable = 1;
15917let opExtendable = 2;
15918let isExtentSigned = 1;
15919let opExtentBits = 9;
15920let opExtentAlign = 0;
15921}
15922def M2_mpysu_up : HInst<
15923(outs IntRegs:$Rd32),
15924(ins IntRegs:$Rs32, IntRegs:$Rt32),
15925"$Rd32 = mpysu($Rs32,$Rt32)",
15926tc_c21d7447, TypeM>, Enc_5ab2be {
15927let Inst{7-5} = 0b001;
15928let Inst{13-13} = 0b0;
15929let Inst{31-21} = 0b11101101011;
15930let hasNewValue = 1;
15931let opNewValue = 0;
15932let prefersSlot3 = 1;
15933}
15934def M2_mpyu_acc_hh_s0 : HInst<
15935(outs IntRegs:$Rx32),
15936(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15937"$Rx32 += mpyu($Rs32.h,$Rt32.h)",
15938tc_7f8ae742, TypeM>, Enc_2ae154 {
15939let Inst{7-5} = 0b011;
15940let Inst{13-13} = 0b0;
15941let Inst{31-21} = 0b11101110010;
15942let hasNewValue = 1;
15943let opNewValue = 0;
15944let prefersSlot3 = 1;
15945let Constraints = "$Rx32 = $Rx32in";
15946}
15947def M2_mpyu_acc_hh_s1 : HInst<
15948(outs IntRegs:$Rx32),
15949(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15950"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15951tc_7f8ae742, TypeM>, Enc_2ae154 {
15952let Inst{7-5} = 0b011;
15953let Inst{13-13} = 0b0;
15954let Inst{31-21} = 0b11101110110;
15955let hasNewValue = 1;
15956let opNewValue = 0;
15957let prefersSlot3 = 1;
15958let Constraints = "$Rx32 = $Rx32in";
15959}
15960def M2_mpyu_acc_hl_s0 : HInst<
15961(outs IntRegs:$Rx32),
15962(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15963"$Rx32 += mpyu($Rs32.h,$Rt32.l)",
15964tc_7f8ae742, TypeM>, Enc_2ae154 {
15965let Inst{7-5} = 0b010;
15966let Inst{13-13} = 0b0;
15967let Inst{31-21} = 0b11101110010;
15968let hasNewValue = 1;
15969let opNewValue = 0;
15970let prefersSlot3 = 1;
15971let Constraints = "$Rx32 = $Rx32in";
15972}
15973def M2_mpyu_acc_hl_s1 : HInst<
15974(outs IntRegs:$Rx32),
15975(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15976"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
15977tc_7f8ae742, TypeM>, Enc_2ae154 {
15978let Inst{7-5} = 0b010;
15979let Inst{13-13} = 0b0;
15980let Inst{31-21} = 0b11101110110;
15981let hasNewValue = 1;
15982let opNewValue = 0;
15983let prefersSlot3 = 1;
15984let Constraints = "$Rx32 = $Rx32in";
15985}
15986def M2_mpyu_acc_lh_s0 : HInst<
15987(outs IntRegs:$Rx32),
15988(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15989"$Rx32 += mpyu($Rs32.l,$Rt32.h)",
15990tc_7f8ae742, TypeM>, Enc_2ae154 {
15991let Inst{7-5} = 0b001;
15992let Inst{13-13} = 0b0;
15993let Inst{31-21} = 0b11101110010;
15994let hasNewValue = 1;
15995let opNewValue = 0;
15996let prefersSlot3 = 1;
15997let Constraints = "$Rx32 = $Rx32in";
15998}
15999def M2_mpyu_acc_lh_s1 : HInst<
16000(outs IntRegs:$Rx32),
16001(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16002"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16003tc_7f8ae742, TypeM>, Enc_2ae154 {
16004let Inst{7-5} = 0b001;
16005let Inst{13-13} = 0b0;
16006let Inst{31-21} = 0b11101110110;
16007let hasNewValue = 1;
16008let opNewValue = 0;
16009let prefersSlot3 = 1;
16010let Constraints = "$Rx32 = $Rx32in";
16011}
16012def M2_mpyu_acc_ll_s0 : HInst<
16013(outs IntRegs:$Rx32),
16014(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16015"$Rx32 += mpyu($Rs32.l,$Rt32.l)",
16016tc_7f8ae742, TypeM>, Enc_2ae154 {
16017let Inst{7-5} = 0b000;
16018let Inst{13-13} = 0b0;
16019let Inst{31-21} = 0b11101110010;
16020let hasNewValue = 1;
16021let opNewValue = 0;
16022let prefersSlot3 = 1;
16023let Constraints = "$Rx32 = $Rx32in";
16024}
16025def M2_mpyu_acc_ll_s1 : HInst<
16026(outs IntRegs:$Rx32),
16027(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16028"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16029tc_7f8ae742, TypeM>, Enc_2ae154 {
16030let Inst{7-5} = 0b000;
16031let Inst{13-13} = 0b0;
16032let Inst{31-21} = 0b11101110110;
16033let hasNewValue = 1;
16034let opNewValue = 0;
16035let prefersSlot3 = 1;
16036let Constraints = "$Rx32 = $Rx32in";
16037}
16038def M2_mpyu_hh_s0 : HInst<
16039(outs IntRegs:$Rd32),
16040(ins IntRegs:$Rs32, IntRegs:$Rt32),
16041"$Rd32 = mpyu($Rs32.h,$Rt32.h)",
16042tc_c21d7447, TypeM>, Enc_5ab2be {
16043let Inst{7-5} = 0b011;
16044let Inst{13-13} = 0b0;
16045let Inst{31-21} = 0b11101100010;
16046let hasNewValue = 1;
16047let opNewValue = 0;
16048let prefersSlot3 = 1;
16049}
16050def M2_mpyu_hh_s1 : HInst<
16051(outs IntRegs:$Rd32),
16052(ins IntRegs:$Rs32, IntRegs:$Rt32),
16053"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16054tc_c21d7447, TypeM>, Enc_5ab2be {
16055let Inst{7-5} = 0b011;
16056let Inst{13-13} = 0b0;
16057let Inst{31-21} = 0b11101100110;
16058let hasNewValue = 1;
16059let opNewValue = 0;
16060let prefersSlot3 = 1;
16061}
16062def M2_mpyu_hl_s0 : HInst<
16063(outs IntRegs:$Rd32),
16064(ins IntRegs:$Rs32, IntRegs:$Rt32),
16065"$Rd32 = mpyu($Rs32.h,$Rt32.l)",
16066tc_c21d7447, TypeM>, Enc_5ab2be {
16067let Inst{7-5} = 0b010;
16068let Inst{13-13} = 0b0;
16069let Inst{31-21} = 0b11101100010;
16070let hasNewValue = 1;
16071let opNewValue = 0;
16072let prefersSlot3 = 1;
16073}
16074def M2_mpyu_hl_s1 : HInst<
16075(outs IntRegs:$Rd32),
16076(ins IntRegs:$Rs32, IntRegs:$Rt32),
16077"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16078tc_c21d7447, TypeM>, Enc_5ab2be {
16079let Inst{7-5} = 0b010;
16080let Inst{13-13} = 0b0;
16081let Inst{31-21} = 0b11101100110;
16082let hasNewValue = 1;
16083let opNewValue = 0;
16084let prefersSlot3 = 1;
16085}
16086def M2_mpyu_lh_s0 : HInst<
16087(outs IntRegs:$Rd32),
16088(ins IntRegs:$Rs32, IntRegs:$Rt32),
16089"$Rd32 = mpyu($Rs32.l,$Rt32.h)",
16090tc_c21d7447, TypeM>, Enc_5ab2be {
16091let Inst{7-5} = 0b001;
16092let Inst{13-13} = 0b0;
16093let Inst{31-21} = 0b11101100010;
16094let hasNewValue = 1;
16095let opNewValue = 0;
16096let prefersSlot3 = 1;
16097}
16098def M2_mpyu_lh_s1 : HInst<
16099(outs IntRegs:$Rd32),
16100(ins IntRegs:$Rs32, IntRegs:$Rt32),
16101"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16102tc_c21d7447, TypeM>, Enc_5ab2be {
16103let Inst{7-5} = 0b001;
16104let Inst{13-13} = 0b0;
16105let Inst{31-21} = 0b11101100110;
16106let hasNewValue = 1;
16107let opNewValue = 0;
16108let prefersSlot3 = 1;
16109}
16110def M2_mpyu_ll_s0 : HInst<
16111(outs IntRegs:$Rd32),
16112(ins IntRegs:$Rs32, IntRegs:$Rt32),
16113"$Rd32 = mpyu($Rs32.l,$Rt32.l)",
16114tc_c21d7447, TypeM>, Enc_5ab2be {
16115let Inst{7-5} = 0b000;
16116let Inst{13-13} = 0b0;
16117let Inst{31-21} = 0b11101100010;
16118let hasNewValue = 1;
16119let opNewValue = 0;
16120let prefersSlot3 = 1;
16121}
16122def M2_mpyu_ll_s1 : HInst<
16123(outs IntRegs:$Rd32),
16124(ins IntRegs:$Rs32, IntRegs:$Rt32),
16125"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16126tc_c21d7447, TypeM>, Enc_5ab2be {
16127let Inst{7-5} = 0b000;
16128let Inst{13-13} = 0b0;
16129let Inst{31-21} = 0b11101100110;
16130let hasNewValue = 1;
16131let opNewValue = 0;
16132let prefersSlot3 = 1;
16133}
16134def M2_mpyu_nac_hh_s0 : HInst<
16135(outs IntRegs:$Rx32),
16136(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16137"$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
16138tc_7f8ae742, TypeM>, Enc_2ae154 {
16139let Inst{7-5} = 0b011;
16140let Inst{13-13} = 0b0;
16141let Inst{31-21} = 0b11101110011;
16142let hasNewValue = 1;
16143let opNewValue = 0;
16144let prefersSlot3 = 1;
16145let Constraints = "$Rx32 = $Rx32in";
16146}
16147def M2_mpyu_nac_hh_s1 : HInst<
16148(outs IntRegs:$Rx32),
16149(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16150"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16151tc_7f8ae742, TypeM>, Enc_2ae154 {
16152let Inst{7-5} = 0b011;
16153let Inst{13-13} = 0b0;
16154let Inst{31-21} = 0b11101110111;
16155let hasNewValue = 1;
16156let opNewValue = 0;
16157let prefersSlot3 = 1;
16158let Constraints = "$Rx32 = $Rx32in";
16159}
16160def M2_mpyu_nac_hl_s0 : HInst<
16161(outs IntRegs:$Rx32),
16162(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16163"$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
16164tc_7f8ae742, TypeM>, Enc_2ae154 {
16165let Inst{7-5} = 0b010;
16166let Inst{13-13} = 0b0;
16167let Inst{31-21} = 0b11101110011;
16168let hasNewValue = 1;
16169let opNewValue = 0;
16170let prefersSlot3 = 1;
16171let Constraints = "$Rx32 = $Rx32in";
16172}
16173def M2_mpyu_nac_hl_s1 : HInst<
16174(outs IntRegs:$Rx32),
16175(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16176"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16177tc_7f8ae742, TypeM>, Enc_2ae154 {
16178let Inst{7-5} = 0b010;
16179let Inst{13-13} = 0b0;
16180let Inst{31-21} = 0b11101110111;
16181let hasNewValue = 1;
16182let opNewValue = 0;
16183let prefersSlot3 = 1;
16184let Constraints = "$Rx32 = $Rx32in";
16185}
16186def M2_mpyu_nac_lh_s0 : HInst<
16187(outs IntRegs:$Rx32),
16188(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16189"$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
16190tc_7f8ae742, TypeM>, Enc_2ae154 {
16191let Inst{7-5} = 0b001;
16192let Inst{13-13} = 0b0;
16193let Inst{31-21} = 0b11101110011;
16194let hasNewValue = 1;
16195let opNewValue = 0;
16196let prefersSlot3 = 1;
16197let Constraints = "$Rx32 = $Rx32in";
16198}
16199def M2_mpyu_nac_lh_s1 : HInst<
16200(outs IntRegs:$Rx32),
16201(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16202"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16203tc_7f8ae742, TypeM>, Enc_2ae154 {
16204let Inst{7-5} = 0b001;
16205let Inst{13-13} = 0b0;
16206let Inst{31-21} = 0b11101110111;
16207let hasNewValue = 1;
16208let opNewValue = 0;
16209let prefersSlot3 = 1;
16210let Constraints = "$Rx32 = $Rx32in";
16211}
16212def M2_mpyu_nac_ll_s0 : HInst<
16213(outs IntRegs:$Rx32),
16214(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16215"$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
16216tc_7f8ae742, TypeM>, Enc_2ae154 {
16217let Inst{7-5} = 0b000;
16218let Inst{13-13} = 0b0;
16219let Inst{31-21} = 0b11101110011;
16220let hasNewValue = 1;
16221let opNewValue = 0;
16222let prefersSlot3 = 1;
16223let Constraints = "$Rx32 = $Rx32in";
16224}
16225def M2_mpyu_nac_ll_s1 : HInst<
16226(outs IntRegs:$Rx32),
16227(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16228"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16229tc_7f8ae742, TypeM>, Enc_2ae154 {
16230let Inst{7-5} = 0b000;
16231let Inst{13-13} = 0b0;
16232let Inst{31-21} = 0b11101110111;
16233let hasNewValue = 1;
16234let opNewValue = 0;
16235let prefersSlot3 = 1;
16236let Constraints = "$Rx32 = $Rx32in";
16237}
16238def M2_mpyu_up : HInst<
16239(outs IntRegs:$Rd32),
16240(ins IntRegs:$Rs32, IntRegs:$Rt32),
16241"$Rd32 = mpyu($Rs32,$Rt32)",
16242tc_c21d7447, TypeM>, Enc_5ab2be {
16243let Inst{7-5} = 0b001;
16244let Inst{13-13} = 0b0;
16245let Inst{31-21} = 0b11101101010;
16246let hasNewValue = 1;
16247let opNewValue = 0;
16248let prefersSlot3 = 1;
16249}
16250def M2_mpyud_acc_hh_s0 : HInst<
16251(outs DoubleRegs:$Rxx32),
16252(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16253"$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
16254tc_7f8ae742, TypeM>, Enc_61f0b0 {
16255let Inst{7-5} = 0b011;
16256let Inst{13-13} = 0b0;
16257let Inst{31-21} = 0b11100110010;
16258let prefersSlot3 = 1;
16259let Constraints = "$Rxx32 = $Rxx32in";
16260}
16261def M2_mpyud_acc_hh_s1 : HInst<
16262(outs DoubleRegs:$Rxx32),
16263(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16264"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
16265tc_7f8ae742, TypeM>, Enc_61f0b0 {
16266let Inst{7-5} = 0b011;
16267let Inst{13-13} = 0b0;
16268let Inst{31-21} = 0b11100110110;
16269let prefersSlot3 = 1;
16270let Constraints = "$Rxx32 = $Rxx32in";
16271}
16272def M2_mpyud_acc_hl_s0 : HInst<
16273(outs DoubleRegs:$Rxx32),
16274(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16275"$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
16276tc_7f8ae742, TypeM>, Enc_61f0b0 {
16277let Inst{7-5} = 0b010;
16278let Inst{13-13} = 0b0;
16279let Inst{31-21} = 0b11100110010;
16280let prefersSlot3 = 1;
16281let Constraints = "$Rxx32 = $Rxx32in";
16282}
16283def M2_mpyud_acc_hl_s1 : HInst<
16284(outs DoubleRegs:$Rxx32),
16285(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16286"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
16287tc_7f8ae742, TypeM>, Enc_61f0b0 {
16288let Inst{7-5} = 0b010;
16289let Inst{13-13} = 0b0;
16290let Inst{31-21} = 0b11100110110;
16291let prefersSlot3 = 1;
16292let Constraints = "$Rxx32 = $Rxx32in";
16293}
16294def M2_mpyud_acc_lh_s0 : HInst<
16295(outs DoubleRegs:$Rxx32),
16296(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16297"$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
16298tc_7f8ae742, TypeM>, Enc_61f0b0 {
16299let Inst{7-5} = 0b001;
16300let Inst{13-13} = 0b0;
16301let Inst{31-21} = 0b11100110010;
16302let prefersSlot3 = 1;
16303let Constraints = "$Rxx32 = $Rxx32in";
16304}
16305def M2_mpyud_acc_lh_s1 : HInst<
16306(outs DoubleRegs:$Rxx32),
16307(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16308"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16309tc_7f8ae742, TypeM>, Enc_61f0b0 {
16310let Inst{7-5} = 0b001;
16311let Inst{13-13} = 0b0;
16312let Inst{31-21} = 0b11100110110;
16313let prefersSlot3 = 1;
16314let Constraints = "$Rxx32 = $Rxx32in";
16315}
16316def M2_mpyud_acc_ll_s0 : HInst<
16317(outs DoubleRegs:$Rxx32),
16318(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16319"$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
16320tc_7f8ae742, TypeM>, Enc_61f0b0 {
16321let Inst{7-5} = 0b000;
16322let Inst{13-13} = 0b0;
16323let Inst{31-21} = 0b11100110010;
16324let prefersSlot3 = 1;
16325let Constraints = "$Rxx32 = $Rxx32in";
16326}
16327def M2_mpyud_acc_ll_s1 : HInst<
16328(outs DoubleRegs:$Rxx32),
16329(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16330"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16331tc_7f8ae742, TypeM>, Enc_61f0b0 {
16332let Inst{7-5} = 0b000;
16333let Inst{13-13} = 0b0;
16334let Inst{31-21} = 0b11100110110;
16335let prefersSlot3 = 1;
16336let Constraints = "$Rxx32 = $Rxx32in";
16337}
16338def M2_mpyud_hh_s0 : HInst<
16339(outs DoubleRegs:$Rdd32),
16340(ins IntRegs:$Rs32, IntRegs:$Rt32),
16341"$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
16342tc_c21d7447, TypeM>, Enc_be32a5 {
16343let Inst{7-5} = 0b011;
16344let Inst{13-13} = 0b0;
16345let Inst{31-21} = 0b11100100010;
16346let prefersSlot3 = 1;
16347}
16348def M2_mpyud_hh_s1 : HInst<
16349(outs DoubleRegs:$Rdd32),
16350(ins IntRegs:$Rs32, IntRegs:$Rt32),
16351"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16352tc_c21d7447, TypeM>, Enc_be32a5 {
16353let Inst{7-5} = 0b011;
16354let Inst{13-13} = 0b0;
16355let Inst{31-21} = 0b11100100110;
16356let prefersSlot3 = 1;
16357}
16358def M2_mpyud_hl_s0 : HInst<
16359(outs DoubleRegs:$Rdd32),
16360(ins IntRegs:$Rs32, IntRegs:$Rt32),
16361"$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
16362tc_c21d7447, TypeM>, Enc_be32a5 {
16363let Inst{7-5} = 0b010;
16364let Inst{13-13} = 0b0;
16365let Inst{31-21} = 0b11100100010;
16366let prefersSlot3 = 1;
16367}
16368def M2_mpyud_hl_s1 : HInst<
16369(outs DoubleRegs:$Rdd32),
16370(ins IntRegs:$Rs32, IntRegs:$Rt32),
16371"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16372tc_c21d7447, TypeM>, Enc_be32a5 {
16373let Inst{7-5} = 0b010;
16374let Inst{13-13} = 0b0;
16375let Inst{31-21} = 0b11100100110;
16376let prefersSlot3 = 1;
16377}
16378def M2_mpyud_lh_s0 : HInst<
16379(outs DoubleRegs:$Rdd32),
16380(ins IntRegs:$Rs32, IntRegs:$Rt32),
16381"$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
16382tc_c21d7447, TypeM>, Enc_be32a5 {
16383let Inst{7-5} = 0b001;
16384let Inst{13-13} = 0b0;
16385let Inst{31-21} = 0b11100100010;
16386let prefersSlot3 = 1;
16387}
16388def M2_mpyud_lh_s1 : HInst<
16389(outs DoubleRegs:$Rdd32),
16390(ins IntRegs:$Rs32, IntRegs:$Rt32),
16391"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16392tc_c21d7447, TypeM>, Enc_be32a5 {
16393let Inst{7-5} = 0b001;
16394let Inst{13-13} = 0b0;
16395let Inst{31-21} = 0b11100100110;
16396let prefersSlot3 = 1;
16397}
16398def M2_mpyud_ll_s0 : HInst<
16399(outs DoubleRegs:$Rdd32),
16400(ins IntRegs:$Rs32, IntRegs:$Rt32),
16401"$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
16402tc_c21d7447, TypeM>, Enc_be32a5 {
16403let Inst{7-5} = 0b000;
16404let Inst{13-13} = 0b0;
16405let Inst{31-21} = 0b11100100010;
16406let prefersSlot3 = 1;
16407}
16408def M2_mpyud_ll_s1 : HInst<
16409(outs DoubleRegs:$Rdd32),
16410(ins IntRegs:$Rs32, IntRegs:$Rt32),
16411"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16412tc_c21d7447, TypeM>, Enc_be32a5 {
16413let Inst{7-5} = 0b000;
16414let Inst{13-13} = 0b0;
16415let Inst{31-21} = 0b11100100110;
16416let prefersSlot3 = 1;
16417}
16418def M2_mpyud_nac_hh_s0 : HInst<
16419(outs DoubleRegs:$Rxx32),
16420(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16421"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
16422tc_7f8ae742, TypeM>, Enc_61f0b0 {
16423let Inst{7-5} = 0b011;
16424let Inst{13-13} = 0b0;
16425let Inst{31-21} = 0b11100110011;
16426let prefersSlot3 = 1;
16427let Constraints = "$Rxx32 = $Rxx32in";
16428}
16429def M2_mpyud_nac_hh_s1 : HInst<
16430(outs DoubleRegs:$Rxx32),
16431(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16432"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16433tc_7f8ae742, TypeM>, Enc_61f0b0 {
16434let Inst{7-5} = 0b011;
16435let Inst{13-13} = 0b0;
16436let Inst{31-21} = 0b11100110111;
16437let prefersSlot3 = 1;
16438let Constraints = "$Rxx32 = $Rxx32in";
16439}
16440def M2_mpyud_nac_hl_s0 : HInst<
16441(outs DoubleRegs:$Rxx32),
16442(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16443"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
16444tc_7f8ae742, TypeM>, Enc_61f0b0 {
16445let Inst{7-5} = 0b010;
16446let Inst{13-13} = 0b0;
16447let Inst{31-21} = 0b11100110011;
16448let prefersSlot3 = 1;
16449let Constraints = "$Rxx32 = $Rxx32in";
16450}
16451def M2_mpyud_nac_hl_s1 : HInst<
16452(outs DoubleRegs:$Rxx32),
16453(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16454"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16455tc_7f8ae742, TypeM>, Enc_61f0b0 {
16456let Inst{7-5} = 0b010;
16457let Inst{13-13} = 0b0;
16458let Inst{31-21} = 0b11100110111;
16459let prefersSlot3 = 1;
16460let Constraints = "$Rxx32 = $Rxx32in";
16461}
16462def M2_mpyud_nac_lh_s0 : HInst<
16463(outs DoubleRegs:$Rxx32),
16464(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16465"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
16466tc_7f8ae742, TypeM>, Enc_61f0b0 {
16467let Inst{7-5} = 0b001;
16468let Inst{13-13} = 0b0;
16469let Inst{31-21} = 0b11100110011;
16470let prefersSlot3 = 1;
16471let Constraints = "$Rxx32 = $Rxx32in";
16472}
16473def M2_mpyud_nac_lh_s1 : HInst<
16474(outs DoubleRegs:$Rxx32),
16475(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16476"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16477tc_7f8ae742, TypeM>, Enc_61f0b0 {
16478let Inst{7-5} = 0b001;
16479let Inst{13-13} = 0b0;
16480let Inst{31-21} = 0b11100110111;
16481let prefersSlot3 = 1;
16482let Constraints = "$Rxx32 = $Rxx32in";
16483}
16484def M2_mpyud_nac_ll_s0 : HInst<
16485(outs DoubleRegs:$Rxx32),
16486(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16487"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
16488tc_7f8ae742, TypeM>, Enc_61f0b0 {
16489let Inst{7-5} = 0b000;
16490let Inst{13-13} = 0b0;
16491let Inst{31-21} = 0b11100110011;
16492let prefersSlot3 = 1;
16493let Constraints = "$Rxx32 = $Rxx32in";
16494}
16495def M2_mpyud_nac_ll_s1 : HInst<
16496(outs DoubleRegs:$Rxx32),
16497(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16498"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16499tc_7f8ae742, TypeM>, Enc_61f0b0 {
16500let Inst{7-5} = 0b000;
16501let Inst{13-13} = 0b0;
16502let Inst{31-21} = 0b11100110111;
16503let prefersSlot3 = 1;
16504let Constraints = "$Rxx32 = $Rxx32in";
16505}
16506def M2_mpyui : HInst<
16507(outs IntRegs:$Rd32),
16508(ins IntRegs:$Rs32, IntRegs:$Rt32),
16509"$Rd32 = mpyui($Rs32,$Rt32)",
16510tc_c21d7447, TypeM> {
16511let hasNewValue = 1;
16512let opNewValue = 0;
16513let isPseudo = 1;
16514let isCodeGenOnly = 1;
16515}
16516def M2_nacci : HInst<
16517(outs IntRegs:$Rx32),
16518(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16519"$Rx32 -= add($Rs32,$Rt32)",
16520tc_2c13e7f5, TypeM>, Enc_2ae154 {
16521let Inst{7-5} = 0b001;
16522let Inst{13-13} = 0b0;
16523let Inst{31-21} = 0b11101111100;
16524let hasNewValue = 1;
16525let opNewValue = 0;
16526let prefersSlot3 = 1;
16527let InputType = "reg";
16528let Constraints = "$Rx32 = $Rx32in";
16529}
16530def M2_naccii : HInst<
16531(outs IntRegs:$Rx32),
16532(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
16533"$Rx32 -= add($Rs32,#$Ii)",
16534tc_2c13e7f5, TypeM>, Enc_c90aca {
16535let Inst{13-13} = 0b0;
16536let Inst{31-21} = 0b11100010100;
16537let hasNewValue = 1;
16538let opNewValue = 0;
16539let prefersSlot3 = 1;
16540let InputType = "imm";
16541let isExtendable = 1;
16542let opExtendable = 3;
16543let isExtentSigned = 1;
16544let opExtentBits = 8;
16545let opExtentAlign = 0;
16546let Constraints = "$Rx32 = $Rx32in";
16547}
16548def M2_subacc : HInst<
16549(outs IntRegs:$Rx32),
16550(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
16551"$Rx32 += sub($Rt32,$Rs32)",
16552tc_2c13e7f5, TypeM>, Enc_a568d4 {
16553let Inst{7-5} = 0b011;
16554let Inst{13-13} = 0b0;
16555let Inst{31-21} = 0b11101111000;
16556let hasNewValue = 1;
16557let opNewValue = 0;
16558let prefersSlot3 = 1;
16559let InputType = "reg";
16560let Constraints = "$Rx32 = $Rx32in";
16561}
16562def M2_vabsdiffh : HInst<
16563(outs DoubleRegs:$Rdd32),
16564(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16565"$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
16566tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16567let Inst{7-5} = 0b000;
16568let Inst{13-13} = 0b0;
16569let Inst{31-21} = 0b11101000011;
16570let prefersSlot3 = 1;
16571}
16572def M2_vabsdiffw : HInst<
16573(outs DoubleRegs:$Rdd32),
16574(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16575"$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
16576tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16577let Inst{7-5} = 0b000;
16578let Inst{13-13} = 0b0;
16579let Inst{31-21} = 0b11101000001;
16580let prefersSlot3 = 1;
16581}
16582def M2_vcmac_s0_sat_i : HInst<
16583(outs DoubleRegs:$Rxx32),
16584(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16585"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
16586tc_7f8ae742, TypeM>, Enc_88c16c {
16587let Inst{7-5} = 0b100;
16588let Inst{13-13} = 0b0;
16589let Inst{31-21} = 0b11101010010;
16590let prefersSlot3 = 1;
16591let Defs = [USR_OVF];
16592let Constraints = "$Rxx32 = $Rxx32in";
16593}
16594def M2_vcmac_s0_sat_r : HInst<
16595(outs DoubleRegs:$Rxx32),
16596(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16597"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
16598tc_7f8ae742, TypeM>, Enc_88c16c {
16599let Inst{7-5} = 0b100;
16600let Inst{13-13} = 0b0;
16601let Inst{31-21} = 0b11101010001;
16602let prefersSlot3 = 1;
16603let Defs = [USR_OVF];
16604let Constraints = "$Rxx32 = $Rxx32in";
16605}
16606def M2_vcmpy_s0_sat_i : HInst<
16607(outs DoubleRegs:$Rdd32),
16608(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16609"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
16610tc_c21d7447, TypeM>, Enc_a56825 {
16611let Inst{7-5} = 0b110;
16612let Inst{13-13} = 0b0;
16613let Inst{31-21} = 0b11101000010;
16614let prefersSlot3 = 1;
16615let Defs = [USR_OVF];
16616}
16617def M2_vcmpy_s0_sat_r : HInst<
16618(outs DoubleRegs:$Rdd32),
16619(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16620"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
16621tc_c21d7447, TypeM>, Enc_a56825 {
16622let Inst{7-5} = 0b110;
16623let Inst{13-13} = 0b0;
16624let Inst{31-21} = 0b11101000001;
16625let prefersSlot3 = 1;
16626let Defs = [USR_OVF];
16627}
16628def M2_vcmpy_s1_sat_i : HInst<
16629(outs DoubleRegs:$Rdd32),
16630(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16631"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
16632tc_c21d7447, TypeM>, Enc_a56825 {
16633let Inst{7-5} = 0b110;
16634let Inst{13-13} = 0b0;
16635let Inst{31-21} = 0b11101000110;
16636let prefersSlot3 = 1;
16637let Defs = [USR_OVF];
16638}
16639def M2_vcmpy_s1_sat_r : HInst<
16640(outs DoubleRegs:$Rdd32),
16641(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16642"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
16643tc_c21d7447, TypeM>, Enc_a56825 {
16644let Inst{7-5} = 0b110;
16645let Inst{13-13} = 0b0;
16646let Inst{31-21} = 0b11101000101;
16647let prefersSlot3 = 1;
16648let Defs = [USR_OVF];
16649}
16650def M2_vdmacs_s0 : HInst<
16651(outs DoubleRegs:$Rxx32),
16652(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16653"$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
16654tc_7f8ae742, TypeM>, Enc_88c16c {
16655let Inst{7-5} = 0b100;
16656let Inst{13-13} = 0b0;
16657let Inst{31-21} = 0b11101010000;
16658let prefersSlot3 = 1;
16659let Defs = [USR_OVF];
16660let Constraints = "$Rxx32 = $Rxx32in";
16661}
16662def M2_vdmacs_s1 : HInst<
16663(outs DoubleRegs:$Rxx32),
16664(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16665"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
16666tc_7f8ae742, TypeM>, Enc_88c16c {
16667let Inst{7-5} = 0b100;
16668let Inst{13-13} = 0b0;
16669let Inst{31-21} = 0b11101010100;
16670let prefersSlot3 = 1;
16671let Defs = [USR_OVF];
16672let Constraints = "$Rxx32 = $Rxx32in";
16673}
16674def M2_vdmpyrs_s0 : HInst<
16675(outs IntRegs:$Rd32),
16676(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16677"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
16678tc_c21d7447, TypeM>, Enc_d2216a {
16679let Inst{7-5} = 0b000;
16680let Inst{13-13} = 0b0;
16681let Inst{31-21} = 0b11101001000;
16682let hasNewValue = 1;
16683let opNewValue = 0;
16684let prefersSlot3 = 1;
16685let Defs = [USR_OVF];
16686}
16687def M2_vdmpyrs_s1 : HInst<
16688(outs IntRegs:$Rd32),
16689(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16690"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
16691tc_c21d7447, TypeM>, Enc_d2216a {
16692let Inst{7-5} = 0b000;
16693let Inst{13-13} = 0b0;
16694let Inst{31-21} = 0b11101001100;
16695let hasNewValue = 1;
16696let opNewValue = 0;
16697let prefersSlot3 = 1;
16698let Defs = [USR_OVF];
16699}
16700def M2_vdmpys_s0 : HInst<
16701(outs DoubleRegs:$Rdd32),
16702(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16703"$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
16704tc_c21d7447, TypeM>, Enc_a56825 {
16705let Inst{7-5} = 0b100;
16706let Inst{13-13} = 0b0;
16707let Inst{31-21} = 0b11101000000;
16708let prefersSlot3 = 1;
16709let Defs = [USR_OVF];
16710}
16711def M2_vdmpys_s1 : HInst<
16712(outs DoubleRegs:$Rdd32),
16713(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16714"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
16715tc_c21d7447, TypeM>, Enc_a56825 {
16716let Inst{7-5} = 0b100;
16717let Inst{13-13} = 0b0;
16718let Inst{31-21} = 0b11101000100;
16719let prefersSlot3 = 1;
16720let Defs = [USR_OVF];
16721}
16722def M2_vmac2 : HInst<
16723(outs DoubleRegs:$Rxx32),
16724(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16725"$Rxx32 += vmpyh($Rs32,$Rt32)",
16726tc_7f8ae742, TypeM>, Enc_61f0b0 {
16727let Inst{7-5} = 0b001;
16728let Inst{13-13} = 0b0;
16729let Inst{31-21} = 0b11100111001;
16730let prefersSlot3 = 1;
16731let Constraints = "$Rxx32 = $Rxx32in";
16732}
16733def M2_vmac2es : HInst<
16734(outs DoubleRegs:$Rxx32),
16735(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16736"$Rxx32 += vmpyeh($Rss32,$Rtt32)",
16737tc_7f8ae742, TypeM>, Enc_88c16c {
16738let Inst{7-5} = 0b010;
16739let Inst{13-13} = 0b0;
16740let Inst{31-21} = 0b11101010001;
16741let prefersSlot3 = 1;
16742let Constraints = "$Rxx32 = $Rxx32in";
16743}
16744def M2_vmac2es_s0 : HInst<
16745(outs DoubleRegs:$Rxx32),
16746(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16747"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
16748tc_7f8ae742, TypeM>, Enc_88c16c {
16749let Inst{7-5} = 0b110;
16750let Inst{13-13} = 0b0;
16751let Inst{31-21} = 0b11101010000;
16752let prefersSlot3 = 1;
16753let Defs = [USR_OVF];
16754let Constraints = "$Rxx32 = $Rxx32in";
16755}
16756def M2_vmac2es_s1 : HInst<
16757(outs DoubleRegs:$Rxx32),
16758(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16759"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
16760tc_7f8ae742, TypeM>, Enc_88c16c {
16761let Inst{7-5} = 0b110;
16762let Inst{13-13} = 0b0;
16763let Inst{31-21} = 0b11101010100;
16764let prefersSlot3 = 1;
16765let Defs = [USR_OVF];
16766let Constraints = "$Rxx32 = $Rxx32in";
16767}
16768def M2_vmac2s_s0 : HInst<
16769(outs DoubleRegs:$Rxx32),
16770(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16771"$Rxx32 += vmpyh($Rs32,$Rt32):sat",
16772tc_7f8ae742, TypeM>, Enc_61f0b0 {
16773let Inst{7-5} = 0b101;
16774let Inst{13-13} = 0b0;
16775let Inst{31-21} = 0b11100111000;
16776let prefersSlot3 = 1;
16777let Defs = [USR_OVF];
16778let Constraints = "$Rxx32 = $Rxx32in";
16779}
16780def M2_vmac2s_s1 : HInst<
16781(outs DoubleRegs:$Rxx32),
16782(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16783"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
16784tc_7f8ae742, TypeM>, Enc_61f0b0 {
16785let Inst{7-5} = 0b101;
16786let Inst{13-13} = 0b0;
16787let Inst{31-21} = 0b11100111100;
16788let prefersSlot3 = 1;
16789let Defs = [USR_OVF];
16790let Constraints = "$Rxx32 = $Rxx32in";
16791}
16792def M2_vmac2su_s0 : HInst<
16793(outs DoubleRegs:$Rxx32),
16794(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16795"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
16796tc_7f8ae742, TypeM>, Enc_61f0b0 {
16797let Inst{7-5} = 0b101;
16798let Inst{13-13} = 0b0;
16799let Inst{31-21} = 0b11100111011;
16800let prefersSlot3 = 1;
16801let Defs = [USR_OVF];
16802let Constraints = "$Rxx32 = $Rxx32in";
16803}
16804def M2_vmac2su_s1 : HInst<
16805(outs DoubleRegs:$Rxx32),
16806(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16807"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
16808tc_7f8ae742, TypeM>, Enc_61f0b0 {
16809let Inst{7-5} = 0b101;
16810let Inst{13-13} = 0b0;
16811let Inst{31-21} = 0b11100111111;
16812let prefersSlot3 = 1;
16813let Defs = [USR_OVF];
16814let Constraints = "$Rxx32 = $Rxx32in";
16815}
16816def M2_vmpy2es_s0 : HInst<
16817(outs DoubleRegs:$Rdd32),
16818(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16819"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
16820tc_c21d7447, TypeM>, Enc_a56825 {
16821let Inst{7-5} = 0b110;
16822let Inst{13-13} = 0b0;
16823let Inst{31-21} = 0b11101000000;
16824let prefersSlot3 = 1;
16825let Defs = [USR_OVF];
16826}
16827def M2_vmpy2es_s1 : HInst<
16828(outs DoubleRegs:$Rdd32),
16829(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16830"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
16831tc_c21d7447, TypeM>, Enc_a56825 {
16832let Inst{7-5} = 0b110;
16833let Inst{13-13} = 0b0;
16834let Inst{31-21} = 0b11101000100;
16835let prefersSlot3 = 1;
16836let Defs = [USR_OVF];
16837}
16838def M2_vmpy2s_s0 : HInst<
16839(outs DoubleRegs:$Rdd32),
16840(ins IntRegs:$Rs32, IntRegs:$Rt32),
16841"$Rdd32 = vmpyh($Rs32,$Rt32):sat",
16842tc_c21d7447, TypeM>, Enc_be32a5 {
16843let Inst{7-5} = 0b101;
16844let Inst{13-13} = 0b0;
16845let Inst{31-21} = 0b11100101000;
16846let prefersSlot3 = 1;
16847let Defs = [USR_OVF];
16848}
16849def M2_vmpy2s_s0pack : HInst<
16850(outs IntRegs:$Rd32),
16851(ins IntRegs:$Rs32, IntRegs:$Rt32),
16852"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
16853tc_c21d7447, TypeM>, Enc_5ab2be {
16854let Inst{7-5} = 0b111;
16855let Inst{13-13} = 0b0;
16856let Inst{31-21} = 0b11101101001;
16857let hasNewValue = 1;
16858let opNewValue = 0;
16859let prefersSlot3 = 1;
16860let Defs = [USR_OVF];
16861}
16862def M2_vmpy2s_s1 : HInst<
16863(outs DoubleRegs:$Rdd32),
16864(ins IntRegs:$Rs32, IntRegs:$Rt32),
16865"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
16866tc_c21d7447, TypeM>, Enc_be32a5 {
16867let Inst{7-5} = 0b101;
16868let Inst{13-13} = 0b0;
16869let Inst{31-21} = 0b11100101100;
16870let prefersSlot3 = 1;
16871let Defs = [USR_OVF];
16872}
16873def M2_vmpy2s_s1pack : HInst<
16874(outs IntRegs:$Rd32),
16875(ins IntRegs:$Rs32, IntRegs:$Rt32),
16876"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
16877tc_c21d7447, TypeM>, Enc_5ab2be {
16878let Inst{7-5} = 0b111;
16879let Inst{13-13} = 0b0;
16880let Inst{31-21} = 0b11101101101;
16881let hasNewValue = 1;
16882let opNewValue = 0;
16883let prefersSlot3 = 1;
16884let Defs = [USR_OVF];
16885}
16886def M2_vmpy2su_s0 : HInst<
16887(outs DoubleRegs:$Rdd32),
16888(ins IntRegs:$Rs32, IntRegs:$Rt32),
16889"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
16890tc_c21d7447, TypeM>, Enc_be32a5 {
16891let Inst{7-5} = 0b111;
16892let Inst{13-13} = 0b0;
16893let Inst{31-21} = 0b11100101000;
16894let prefersSlot3 = 1;
16895let Defs = [USR_OVF];
16896}
16897def M2_vmpy2su_s1 : HInst<
16898(outs DoubleRegs:$Rdd32),
16899(ins IntRegs:$Rs32, IntRegs:$Rt32),
16900"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
16901tc_c21d7447, TypeM>, Enc_be32a5 {
16902let Inst{7-5} = 0b111;
16903let Inst{13-13} = 0b0;
16904let Inst{31-21} = 0b11100101100;
16905let prefersSlot3 = 1;
16906let Defs = [USR_OVF];
16907}
16908def M2_vraddh : HInst<
16909(outs IntRegs:$Rd32),
16910(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16911"$Rd32 = vraddh($Rss32,$Rtt32)",
16912tc_c21d7447, TypeM>, Enc_d2216a {
16913let Inst{7-5} = 0b111;
16914let Inst{13-13} = 0b0;
16915let Inst{31-21} = 0b11101001001;
16916let hasNewValue = 1;
16917let opNewValue = 0;
16918let prefersSlot3 = 1;
16919}
16920def M2_vradduh : HInst<
16921(outs IntRegs:$Rd32),
16922(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16923"$Rd32 = vradduh($Rss32,$Rtt32)",
16924tc_c21d7447, TypeM>, Enc_d2216a {
16925let Inst{7-5} = 0b001;
16926let Inst{13-13} = 0b0;
16927let Inst{31-21} = 0b11101001000;
16928let hasNewValue = 1;
16929let opNewValue = 0;
16930let prefersSlot3 = 1;
16931}
16932def M2_vrcmaci_s0 : HInst<
16933(outs DoubleRegs:$Rxx32),
16934(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16935"$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
16936tc_7f8ae742, TypeM>, Enc_88c16c {
16937let Inst{7-5} = 0b000;
16938let Inst{13-13} = 0b0;
16939let Inst{31-21} = 0b11101010000;
16940let prefersSlot3 = 1;
16941let Constraints = "$Rxx32 = $Rxx32in";
16942}
16943def M2_vrcmaci_s0c : HInst<
16944(outs DoubleRegs:$Rxx32),
16945(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16946"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
16947tc_7f8ae742, TypeM>, Enc_88c16c {
16948let Inst{7-5} = 0b000;
16949let Inst{13-13} = 0b0;
16950let Inst{31-21} = 0b11101010010;
16951let prefersSlot3 = 1;
16952let Constraints = "$Rxx32 = $Rxx32in";
16953}
16954def M2_vrcmacr_s0 : HInst<
16955(outs DoubleRegs:$Rxx32),
16956(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16957"$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
16958tc_7f8ae742, TypeM>, Enc_88c16c {
16959let Inst{7-5} = 0b001;
16960let Inst{13-13} = 0b0;
16961let Inst{31-21} = 0b11101010000;
16962let prefersSlot3 = 1;
16963let Constraints = "$Rxx32 = $Rxx32in";
16964}
16965def M2_vrcmacr_s0c : HInst<
16966(outs DoubleRegs:$Rxx32),
16967(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16968"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
16969tc_7f8ae742, TypeM>, Enc_88c16c {
16970let Inst{7-5} = 0b001;
16971let Inst{13-13} = 0b0;
16972let Inst{31-21} = 0b11101010011;
16973let prefersSlot3 = 1;
16974let Constraints = "$Rxx32 = $Rxx32in";
16975}
16976def M2_vrcmpyi_s0 : HInst<
16977(outs DoubleRegs:$Rdd32),
16978(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16979"$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
16980tc_c21d7447, TypeM>, Enc_a56825 {
16981let Inst{7-5} = 0b000;
16982let Inst{13-13} = 0b0;
16983let Inst{31-21} = 0b11101000000;
16984let prefersSlot3 = 1;
16985}
16986def M2_vrcmpyi_s0c : HInst<
16987(outs DoubleRegs:$Rdd32),
16988(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16989"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
16990tc_c21d7447, TypeM>, Enc_a56825 {
16991let Inst{7-5} = 0b000;
16992let Inst{13-13} = 0b0;
16993let Inst{31-21} = 0b11101000010;
16994let prefersSlot3 = 1;
16995}
16996def M2_vrcmpyr_s0 : HInst<
16997(outs DoubleRegs:$Rdd32),
16998(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16999"$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
17000tc_c21d7447, TypeM>, Enc_a56825 {
17001let Inst{7-5} = 0b001;
17002let Inst{13-13} = 0b0;
17003let Inst{31-21} = 0b11101000000;
17004let prefersSlot3 = 1;
17005}
17006def M2_vrcmpyr_s0c : HInst<
17007(outs DoubleRegs:$Rdd32),
17008(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17009"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
17010tc_c21d7447, TypeM>, Enc_a56825 {
17011let Inst{7-5} = 0b001;
17012let Inst{13-13} = 0b0;
17013let Inst{31-21} = 0b11101000011;
17014let prefersSlot3 = 1;
17015}
17016def M2_vrcmpys_acc_s1 : HInst<
17017(outs DoubleRegs:$Rxx32),
17018(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
17019"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
17020tc_7f8ae742, TypeM> {
17021let isPseudo = 1;
17022let Constraints = "$Rxx32 = $Rxx32in";
17023}
17024def M2_vrcmpys_acc_s1_h : HInst<
17025(outs DoubleRegs:$Rxx32),
17026(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17027"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
17028tc_7f8ae742, TypeM>, Enc_88c16c {
17029let Inst{7-5} = 0b100;
17030let Inst{13-13} = 0b0;
17031let Inst{31-21} = 0b11101010101;
17032let prefersSlot3 = 1;
17033let Defs = [USR_OVF];
17034let Constraints = "$Rxx32 = $Rxx32in";
17035}
17036def M2_vrcmpys_acc_s1_l : HInst<
17037(outs DoubleRegs:$Rxx32),
17038(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17039"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17040tc_7f8ae742, TypeM>, Enc_88c16c {
17041let Inst{7-5} = 0b100;
17042let Inst{13-13} = 0b0;
17043let Inst{31-21} = 0b11101010111;
17044let prefersSlot3 = 1;
17045let Defs = [USR_OVF];
17046let Constraints = "$Rxx32 = $Rxx32in";
17047}
17048def M2_vrcmpys_s1 : HInst<
17049(outs DoubleRegs:$Rdd32),
17050(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17051"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
17052tc_c21d7447, TypeM> {
17053let isPseudo = 1;
17054}
17055def M2_vrcmpys_s1_h : HInst<
17056(outs DoubleRegs:$Rdd32),
17057(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17058"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
17059tc_c21d7447, TypeM>, Enc_a56825 {
17060let Inst{7-5} = 0b100;
17061let Inst{13-13} = 0b0;
17062let Inst{31-21} = 0b11101000101;
17063let prefersSlot3 = 1;
17064let Defs = [USR_OVF];
17065}
17066def M2_vrcmpys_s1_l : HInst<
17067(outs DoubleRegs:$Rdd32),
17068(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17069"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17070tc_c21d7447, TypeM>, Enc_a56825 {
17071let Inst{7-5} = 0b100;
17072let Inst{13-13} = 0b0;
17073let Inst{31-21} = 0b11101000111;
17074let prefersSlot3 = 1;
17075let Defs = [USR_OVF];
17076}
17077def M2_vrcmpys_s1rp : HInst<
17078(outs IntRegs:$Rd32),
17079(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17080"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
17081tc_c21d7447, TypeM> {
17082let hasNewValue = 1;
17083let opNewValue = 0;
17084let isPseudo = 1;
17085}
17086def M2_vrcmpys_s1rp_h : HInst<
17087(outs IntRegs:$Rd32),
17088(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17089"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
17090tc_c21d7447, TypeM>, Enc_d2216a {
17091let Inst{7-5} = 0b110;
17092let Inst{13-13} = 0b0;
17093let Inst{31-21} = 0b11101001101;
17094let hasNewValue = 1;
17095let opNewValue = 0;
17096let prefersSlot3 = 1;
17097let Defs = [USR_OVF];
17098}
17099def M2_vrcmpys_s1rp_l : HInst<
17100(outs IntRegs:$Rd32),
17101(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17102"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
17103tc_c21d7447, TypeM>, Enc_d2216a {
17104let Inst{7-5} = 0b111;
17105let Inst{13-13} = 0b0;
17106let Inst{31-21} = 0b11101001101;
17107let hasNewValue = 1;
17108let opNewValue = 0;
17109let prefersSlot3 = 1;
17110let Defs = [USR_OVF];
17111}
17112def M2_vrmac_s0 : HInst<
17113(outs DoubleRegs:$Rxx32),
17114(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17115"$Rxx32 += vrmpyh($Rss32,$Rtt32)",
17116tc_7f8ae742, TypeM>, Enc_88c16c {
17117let Inst{7-5} = 0b010;
17118let Inst{13-13} = 0b0;
17119let Inst{31-21} = 0b11101010000;
17120let prefersSlot3 = 1;
17121let Constraints = "$Rxx32 = $Rxx32in";
17122}
17123def M2_vrmpy_s0 : HInst<
17124(outs DoubleRegs:$Rdd32),
17125(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17126"$Rdd32 = vrmpyh($Rss32,$Rtt32)",
17127tc_c21d7447, TypeM>, Enc_a56825 {
17128let Inst{7-5} = 0b010;
17129let Inst{13-13} = 0b0;
17130let Inst{31-21} = 0b11101000000;
17131let prefersSlot3 = 1;
17132}
17133def M2_xor_xacc : HInst<
17134(outs IntRegs:$Rx32),
17135(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17136"$Rx32 ^= xor($Rs32,$Rt32)",
17137tc_a4e22bbd, TypeM>, Enc_2ae154 {
17138let Inst{7-5} = 0b011;
17139let Inst{13-13} = 0b0;
17140let Inst{31-21} = 0b11101111100;
17141let hasNewValue = 1;
17142let opNewValue = 0;
17143let prefersSlot3 = 1;
17144let InputType = "reg";
17145let Constraints = "$Rx32 = $Rx32in";
17146}
17147def M4_and_and : HInst<
17148(outs IntRegs:$Rx32),
17149(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17150"$Rx32 &= and($Rs32,$Rt32)",
17151tc_a4e22bbd, TypeM>, Enc_2ae154 {
17152let Inst{7-5} = 0b000;
17153let Inst{13-13} = 0b0;
17154let Inst{31-21} = 0b11101111010;
17155let hasNewValue = 1;
17156let opNewValue = 0;
17157let prefersSlot3 = 1;
17158let InputType = "reg";
17159let Constraints = "$Rx32 = $Rx32in";
17160}
17161def M4_and_andn : HInst<
17162(outs IntRegs:$Rx32),
17163(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17164"$Rx32 &= and($Rs32,~$Rt32)",
17165tc_a4e22bbd, TypeM>, Enc_2ae154 {
17166let Inst{7-5} = 0b001;
17167let Inst{13-13} = 0b0;
17168let Inst{31-21} = 0b11101111001;
17169let hasNewValue = 1;
17170let opNewValue = 0;
17171let prefersSlot3 = 1;
17172let InputType = "reg";
17173let Constraints = "$Rx32 = $Rx32in";
17174}
17175def M4_and_or : HInst<
17176(outs IntRegs:$Rx32),
17177(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17178"$Rx32 &= or($Rs32,$Rt32)",
17179tc_a4e22bbd, TypeM>, Enc_2ae154 {
17180let Inst{7-5} = 0b001;
17181let Inst{13-13} = 0b0;
17182let Inst{31-21} = 0b11101111010;
17183let hasNewValue = 1;
17184let opNewValue = 0;
17185let prefersSlot3 = 1;
17186let InputType = "reg";
17187let Constraints = "$Rx32 = $Rx32in";
17188}
17189def M4_and_xor : HInst<
17190(outs IntRegs:$Rx32),
17191(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17192"$Rx32 &= xor($Rs32,$Rt32)",
17193tc_a4e22bbd, TypeM>, Enc_2ae154 {
17194let Inst{7-5} = 0b010;
17195let Inst{13-13} = 0b0;
17196let Inst{31-21} = 0b11101111010;
17197let hasNewValue = 1;
17198let opNewValue = 0;
17199let prefersSlot3 = 1;
17200let InputType = "reg";
17201let Constraints = "$Rx32 = $Rx32in";
17202}
17203def M4_cmpyi_wh : HInst<
17204(outs IntRegs:$Rd32),
17205(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17206"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
17207tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17208let Inst{7-5} = 0b100;
17209let Inst{13-13} = 0b0;
17210let Inst{31-21} = 0b11000101000;
17211let hasNewValue = 1;
17212let opNewValue = 0;
17213let prefersSlot3 = 1;
17214let Defs = [USR_OVF];
17215}
17216def M4_cmpyi_whc : HInst<
17217(outs IntRegs:$Rd32),
17218(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17219"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
17220tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17221let Inst{7-5} = 0b101;
17222let Inst{13-13} = 0b0;
17223let Inst{31-21} = 0b11000101000;
17224let hasNewValue = 1;
17225let opNewValue = 0;
17226let prefersSlot3 = 1;
17227let Defs = [USR_OVF];
17228}
17229def M4_cmpyr_wh : HInst<
17230(outs IntRegs:$Rd32),
17231(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17232"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
17233tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17234let Inst{7-5} = 0b110;
17235let Inst{13-13} = 0b0;
17236let Inst{31-21} = 0b11000101000;
17237let hasNewValue = 1;
17238let opNewValue = 0;
17239let prefersSlot3 = 1;
17240let Defs = [USR_OVF];
17241}
17242def M4_cmpyr_whc : HInst<
17243(outs IntRegs:$Rd32),
17244(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17245"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
17246tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17247let Inst{7-5} = 0b111;
17248let Inst{13-13} = 0b0;
17249let Inst{31-21} = 0b11000101000;
17250let hasNewValue = 1;
17251let opNewValue = 0;
17252let prefersSlot3 = 1;
17253let Defs = [USR_OVF];
17254}
17255def M4_mac_up_s1_sat : HInst<
17256(outs IntRegs:$Rx32),
17257(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17258"$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
17259tc_7f8ae742, TypeM>, Enc_2ae154 {
17260let Inst{7-5} = 0b000;
17261let Inst{13-13} = 0b0;
17262let Inst{31-21} = 0b11101111011;
17263let hasNewValue = 1;
17264let opNewValue = 0;
17265let prefersSlot3 = 1;
17266let Defs = [USR_OVF];
17267let InputType = "reg";
17268let Constraints = "$Rx32 = $Rx32in";
17269}
17270def M4_mpyri_addi : HInst<
17271(outs IntRegs:$Rd32),
17272(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
17273"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
17274tc_a154b476, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel {
17275let Inst{31-24} = 0b11011000;
17276let hasNewValue = 1;
17277let opNewValue = 0;
17278let prefersSlot3 = 1;
17279let CextOpcode = "M4_mpyri_addr";
17280let isExtendable = 1;
17281let opExtendable = 1;
17282let isExtentSigned = 0;
17283let opExtentBits = 6;
17284let opExtentAlign = 0;
17285}
17286def M4_mpyri_addr : HInst<
17287(outs IntRegs:$Rd32),
17288(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
17289"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
17290tc_a154b476, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel {
17291let Inst{31-23} = 0b110111111;
17292let hasNewValue = 1;
17293let opNewValue = 0;
17294let prefersSlot3 = 1;
17295let CextOpcode = "M4_mpyri_addr";
17296let InputType = "imm";
17297let isExtendable = 1;
17298let opExtendable = 3;
17299let isExtentSigned = 0;
17300let opExtentBits = 6;
17301let opExtentAlign = 0;
17302}
17303def M4_mpyri_addr_u2 : HInst<
17304(outs IntRegs:$Rd32),
17305(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
17306"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17307tc_503ce0f3, TypeALU64>, Enc_277737, Requires<[UseCompound]> {
17308let Inst{31-23} = 0b110111110;
17309let hasNewValue = 1;
17310let opNewValue = 0;
17311let prefersSlot3 = 1;
17312}
17313def M4_mpyrr_addi : HInst<
17314(outs IntRegs:$Rd32),
17315(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
17316"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17317tc_7f8ae742, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel {
17318let Inst{31-23} = 0b110101110;
17319let hasNewValue = 1;
17320let opNewValue = 0;
17321let prefersSlot3 = 1;
17322let CextOpcode = "M4_mpyrr_addr";
17323let InputType = "imm";
17324let isExtendable = 1;
17325let opExtendable = 1;
17326let isExtentSigned = 0;
17327let opExtentBits = 6;
17328let opExtentAlign = 0;
17329}
17330def M4_mpyrr_addr : HInst<
17331(outs IntRegs:$Ry32),
17332(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
17333"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17334tc_7f8ae742, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel {
17335let Inst{7-5} = 0b000;
17336let Inst{13-13} = 0b0;
17337let Inst{31-21} = 0b11100011000;
17338let hasNewValue = 1;
17339let opNewValue = 0;
17340let prefersSlot3 = 1;
17341let CextOpcode = "M4_mpyrr_addr";
17342let InputType = "reg";
17343let Constraints = "$Ry32 = $Ry32in";
17344}
17345def M4_nac_up_s1_sat : HInst<
17346(outs IntRegs:$Rx32),
17347(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17348"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
17349tc_7f8ae742, TypeM>, Enc_2ae154 {
17350let Inst{7-5} = 0b001;
17351let Inst{13-13} = 0b0;
17352let Inst{31-21} = 0b11101111011;
17353let hasNewValue = 1;
17354let opNewValue = 0;
17355let prefersSlot3 = 1;
17356let Defs = [USR_OVF];
17357let InputType = "reg";
17358let Constraints = "$Rx32 = $Rx32in";
17359}
17360def M4_or_and : HInst<
17361(outs IntRegs:$Rx32),
17362(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17363"$Rx32 |= and($Rs32,$Rt32)",
17364tc_a4e22bbd, TypeM>, Enc_2ae154 {
17365let Inst{7-5} = 0b011;
17366let Inst{13-13} = 0b0;
17367let Inst{31-21} = 0b11101111010;
17368let hasNewValue = 1;
17369let opNewValue = 0;
17370let prefersSlot3 = 1;
17371let InputType = "reg";
17372let Constraints = "$Rx32 = $Rx32in";
17373}
17374def M4_or_andn : HInst<
17375(outs IntRegs:$Rx32),
17376(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17377"$Rx32 |= and($Rs32,~$Rt32)",
17378tc_a4e22bbd, TypeM>, Enc_2ae154 {
17379let Inst{7-5} = 0b000;
17380let Inst{13-13} = 0b0;
17381let Inst{31-21} = 0b11101111001;
17382let hasNewValue = 1;
17383let opNewValue = 0;
17384let prefersSlot3 = 1;
17385let InputType = "reg";
17386let Constraints = "$Rx32 = $Rx32in";
17387}
17388def M4_or_or : HInst<
17389(outs IntRegs:$Rx32),
17390(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17391"$Rx32 |= or($Rs32,$Rt32)",
17392tc_a4e22bbd, TypeM>, Enc_2ae154 {
17393let Inst{7-5} = 0b000;
17394let Inst{13-13} = 0b0;
17395let Inst{31-21} = 0b11101111110;
17396let hasNewValue = 1;
17397let opNewValue = 0;
17398let prefersSlot3 = 1;
17399let InputType = "reg";
17400let Constraints = "$Rx32 = $Rx32in";
17401}
17402def M4_or_xor : HInst<
17403(outs IntRegs:$Rx32),
17404(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17405"$Rx32 |= xor($Rs32,$Rt32)",
17406tc_a4e22bbd, TypeM>, Enc_2ae154 {
17407let Inst{7-5} = 0b001;
17408let Inst{13-13} = 0b0;
17409let Inst{31-21} = 0b11101111110;
17410let hasNewValue = 1;
17411let opNewValue = 0;
17412let prefersSlot3 = 1;
17413let InputType = "reg";
17414let Constraints = "$Rx32 = $Rx32in";
17415}
17416def M4_pmpyw : HInst<
17417(outs DoubleRegs:$Rdd32),
17418(ins IntRegs:$Rs32, IntRegs:$Rt32),
17419"$Rdd32 = pmpyw($Rs32,$Rt32)",
17420tc_c21d7447, TypeM>, Enc_be32a5 {
17421let Inst{7-5} = 0b111;
17422let Inst{13-13} = 0b0;
17423let Inst{31-21} = 0b11100101010;
17424let prefersSlot3 = 1;
17425}
17426def M4_pmpyw_acc : HInst<
17427(outs DoubleRegs:$Rxx32),
17428(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17429"$Rxx32 ^= pmpyw($Rs32,$Rt32)",
17430tc_7f8ae742, TypeM>, Enc_61f0b0 {
17431let Inst{7-5} = 0b111;
17432let Inst{13-13} = 0b0;
17433let Inst{31-21} = 0b11100111001;
17434let prefersSlot3 = 1;
17435let Constraints = "$Rxx32 = $Rxx32in";
17436}
17437def M4_vpmpyh : HInst<
17438(outs DoubleRegs:$Rdd32),
17439(ins IntRegs:$Rs32, IntRegs:$Rt32),
17440"$Rdd32 = vpmpyh($Rs32,$Rt32)",
17441tc_c21d7447, TypeM>, Enc_be32a5 {
17442let Inst{7-5} = 0b111;
17443let Inst{13-13} = 0b0;
17444let Inst{31-21} = 0b11100101110;
17445let prefersSlot3 = 1;
17446}
17447def M4_vpmpyh_acc : HInst<
17448(outs DoubleRegs:$Rxx32),
17449(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17450"$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
17451tc_7f8ae742, TypeM>, Enc_61f0b0 {
17452let Inst{7-5} = 0b111;
17453let Inst{13-13} = 0b0;
17454let Inst{31-21} = 0b11100111101;
17455let prefersSlot3 = 1;
17456let Constraints = "$Rxx32 = $Rxx32in";
17457}
17458def M4_vrmpyeh_acc_s0 : HInst<
17459(outs DoubleRegs:$Rxx32),
17460(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17461"$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
17462tc_7f8ae742, TypeM>, Enc_88c16c {
17463let Inst{7-5} = 0b110;
17464let Inst{13-13} = 0b0;
17465let Inst{31-21} = 0b11101010001;
17466let prefersSlot3 = 1;
17467let Constraints = "$Rxx32 = $Rxx32in";
17468}
17469def M4_vrmpyeh_acc_s1 : HInst<
17470(outs DoubleRegs:$Rxx32),
17471(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17472"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
17473tc_7f8ae742, TypeM>, Enc_88c16c {
17474let Inst{7-5} = 0b110;
17475let Inst{13-13} = 0b0;
17476let Inst{31-21} = 0b11101010101;
17477let prefersSlot3 = 1;
17478let Constraints = "$Rxx32 = $Rxx32in";
17479}
17480def M4_vrmpyeh_s0 : HInst<
17481(outs DoubleRegs:$Rdd32),
17482(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17483"$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
17484tc_c21d7447, TypeM>, Enc_a56825 {
17485let Inst{7-5} = 0b100;
17486let Inst{13-13} = 0b0;
17487let Inst{31-21} = 0b11101000010;
17488let prefersSlot3 = 1;
17489}
17490def M4_vrmpyeh_s1 : HInst<
17491(outs DoubleRegs:$Rdd32),
17492(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17493"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
17494tc_c21d7447, TypeM>, Enc_a56825 {
17495let Inst{7-5} = 0b100;
17496let Inst{13-13} = 0b0;
17497let Inst{31-21} = 0b11101000110;
17498let prefersSlot3 = 1;
17499}
17500def M4_vrmpyoh_acc_s0 : HInst<
17501(outs DoubleRegs:$Rxx32),
17502(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17503"$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
17504tc_7f8ae742, TypeM>, Enc_88c16c {
17505let Inst{7-5} = 0b110;
17506let Inst{13-13} = 0b0;
17507let Inst{31-21} = 0b11101010011;
17508let prefersSlot3 = 1;
17509let Constraints = "$Rxx32 = $Rxx32in";
17510}
17511def M4_vrmpyoh_acc_s1 : HInst<
17512(outs DoubleRegs:$Rxx32),
17513(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17514"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
17515tc_7f8ae742, TypeM>, Enc_88c16c {
17516let Inst{7-5} = 0b110;
17517let Inst{13-13} = 0b0;
17518let Inst{31-21} = 0b11101010111;
17519let prefersSlot3 = 1;
17520let Constraints = "$Rxx32 = $Rxx32in";
17521}
17522def M4_vrmpyoh_s0 : HInst<
17523(outs DoubleRegs:$Rdd32),
17524(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17525"$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
17526tc_c21d7447, TypeM>, Enc_a56825 {
17527let Inst{7-5} = 0b010;
17528let Inst{13-13} = 0b0;
17529let Inst{31-21} = 0b11101000001;
17530let prefersSlot3 = 1;
17531}
17532def M4_vrmpyoh_s1 : HInst<
17533(outs DoubleRegs:$Rdd32),
17534(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17535"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
17536tc_c21d7447, TypeM>, Enc_a56825 {
17537let Inst{7-5} = 0b010;
17538let Inst{13-13} = 0b0;
17539let Inst{31-21} = 0b11101000101;
17540let prefersSlot3 = 1;
17541}
17542def M4_xor_and : HInst<
17543(outs IntRegs:$Rx32),
17544(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17545"$Rx32 ^= and($Rs32,$Rt32)",
17546tc_a4e22bbd, TypeM>, Enc_2ae154 {
17547let Inst{7-5} = 0b010;
17548let Inst{13-13} = 0b0;
17549let Inst{31-21} = 0b11101111110;
17550let hasNewValue = 1;
17551let opNewValue = 0;
17552let prefersSlot3 = 1;
17553let InputType = "reg";
17554let Constraints = "$Rx32 = $Rx32in";
17555}
17556def M4_xor_andn : HInst<
17557(outs IntRegs:$Rx32),
17558(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17559"$Rx32 ^= and($Rs32,~$Rt32)",
17560tc_a4e22bbd, TypeM>, Enc_2ae154 {
17561let Inst{7-5} = 0b010;
17562let Inst{13-13} = 0b0;
17563let Inst{31-21} = 0b11101111001;
17564let hasNewValue = 1;
17565let opNewValue = 0;
17566let prefersSlot3 = 1;
17567let InputType = "reg";
17568let Constraints = "$Rx32 = $Rx32in";
17569}
17570def M4_xor_or : HInst<
17571(outs IntRegs:$Rx32),
17572(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17573"$Rx32 ^= or($Rs32,$Rt32)",
17574tc_a4e22bbd, TypeM>, Enc_2ae154 {
17575let Inst{7-5} = 0b011;
17576let Inst{13-13} = 0b0;
17577let Inst{31-21} = 0b11101111110;
17578let hasNewValue = 1;
17579let opNewValue = 0;
17580let prefersSlot3 = 1;
17581let InputType = "reg";
17582let Constraints = "$Rx32 = $Rx32in";
17583}
17584def M4_xor_xacc : HInst<
17585(outs DoubleRegs:$Rxx32),
17586(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17587"$Rxx32 ^= xor($Rss32,$Rtt32)",
17588tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
17589let Inst{7-5} = 0b000;
17590let Inst{13-13} = 0b0;
17591let Inst{31-21} = 0b11001010100;
17592let prefersSlot3 = 1;
17593let Constraints = "$Rxx32 = $Rxx32in";
17594}
17595def M5_vdmacbsu : HInst<
17596(outs DoubleRegs:$Rxx32),
17597(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17598"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
17599tc_7f8ae742, TypeM>, Enc_88c16c {
17600let Inst{7-5} = 0b001;
17601let Inst{13-13} = 0b0;
17602let Inst{31-21} = 0b11101010001;
17603let prefersSlot3 = 1;
17604let Defs = [USR_OVF];
17605let Constraints = "$Rxx32 = $Rxx32in";
17606}
17607def M5_vdmpybsu : HInst<
17608(outs DoubleRegs:$Rdd32),
17609(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17610"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
17611tc_c21d7447, TypeM>, Enc_a56825 {
17612let Inst{7-5} = 0b001;
17613let Inst{13-13} = 0b0;
17614let Inst{31-21} = 0b11101000101;
17615let prefersSlot3 = 1;
17616let Defs = [USR_OVF];
17617}
17618def M5_vmacbsu : HInst<
17619(outs DoubleRegs:$Rxx32),
17620(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17621"$Rxx32 += vmpybsu($Rs32,$Rt32)",
17622tc_7f8ae742, TypeM>, Enc_61f0b0 {
17623let Inst{7-5} = 0b001;
17624let Inst{13-13} = 0b0;
17625let Inst{31-21} = 0b11100111110;
17626let prefersSlot3 = 1;
17627let Constraints = "$Rxx32 = $Rxx32in";
17628}
17629def M5_vmacbuu : HInst<
17630(outs DoubleRegs:$Rxx32),
17631(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17632"$Rxx32 += vmpybu($Rs32,$Rt32)",
17633tc_7f8ae742, TypeM>, Enc_61f0b0 {
17634let Inst{7-5} = 0b001;
17635let Inst{13-13} = 0b0;
17636let Inst{31-21} = 0b11100111100;
17637let prefersSlot3 = 1;
17638let Constraints = "$Rxx32 = $Rxx32in";
17639}
17640def M5_vmpybsu : HInst<
17641(outs DoubleRegs:$Rdd32),
17642(ins IntRegs:$Rs32, IntRegs:$Rt32),
17643"$Rdd32 = vmpybsu($Rs32,$Rt32)",
17644tc_c21d7447, TypeM>, Enc_be32a5 {
17645let Inst{7-5} = 0b001;
17646let Inst{13-13} = 0b0;
17647let Inst{31-21} = 0b11100101010;
17648let prefersSlot3 = 1;
17649}
17650def M5_vmpybuu : HInst<
17651(outs DoubleRegs:$Rdd32),
17652(ins IntRegs:$Rs32, IntRegs:$Rt32),
17653"$Rdd32 = vmpybu($Rs32,$Rt32)",
17654tc_c21d7447, TypeM>, Enc_be32a5 {
17655let Inst{7-5} = 0b001;
17656let Inst{13-13} = 0b0;
17657let Inst{31-21} = 0b11100101100;
17658let prefersSlot3 = 1;
17659}
17660def M5_vrmacbsu : HInst<
17661(outs DoubleRegs:$Rxx32),
17662(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17663"$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
17664tc_7f8ae742, TypeM>, Enc_88c16c {
17665let Inst{7-5} = 0b001;
17666let Inst{13-13} = 0b0;
17667let Inst{31-21} = 0b11101010110;
17668let prefersSlot3 = 1;
17669let Constraints = "$Rxx32 = $Rxx32in";
17670}
17671def M5_vrmacbuu : HInst<
17672(outs DoubleRegs:$Rxx32),
17673(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17674"$Rxx32 += vrmpybu($Rss32,$Rtt32)",
17675tc_7f8ae742, TypeM>, Enc_88c16c {
17676let Inst{7-5} = 0b001;
17677let Inst{13-13} = 0b0;
17678let Inst{31-21} = 0b11101010100;
17679let prefersSlot3 = 1;
17680let Constraints = "$Rxx32 = $Rxx32in";
17681}
17682def M5_vrmpybsu : HInst<
17683(outs DoubleRegs:$Rdd32),
17684(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17685"$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
17686tc_c21d7447, TypeM>, Enc_a56825 {
17687let Inst{7-5} = 0b001;
17688let Inst{13-13} = 0b0;
17689let Inst{31-21} = 0b11101000110;
17690let prefersSlot3 = 1;
17691}
17692def M5_vrmpybuu : HInst<
17693(outs DoubleRegs:$Rdd32),
17694(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17695"$Rdd32 = vrmpybu($Rss32,$Rtt32)",
17696tc_c21d7447, TypeM>, Enc_a56825 {
17697let Inst{7-5} = 0b001;
17698let Inst{13-13} = 0b0;
17699let Inst{31-21} = 0b11101000100;
17700let prefersSlot3 = 1;
17701}
17702def M6_vabsdiffb : HInst<
17703(outs DoubleRegs:$Rdd32),
17704(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17705"$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
17706tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17707let Inst{7-5} = 0b000;
17708let Inst{13-13} = 0b0;
17709let Inst{31-21} = 0b11101000111;
17710let prefersSlot3 = 1;
17711}
17712def M6_vabsdiffub : HInst<
17713(outs DoubleRegs:$Rdd32),
17714(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17715"$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
17716tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17717let Inst{7-5} = 0b000;
17718let Inst{13-13} = 0b0;
17719let Inst{31-21} = 0b11101000101;
17720let prefersSlot3 = 1;
17721}
17722def M7_dcmpyiw : HInst<
17723(outs DoubleRegs:$Rdd32),
17724(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17725"$Rdd32 = cmpyiw($Rss32,$Rtt32)",
17726tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17727let Inst{7-5} = 0b010;
17728let Inst{13-13} = 0b0;
17729let Inst{31-21} = 0b11101000011;
17730let prefersSlot3 = 1;
17731}
17732def M7_dcmpyiw_acc : HInst<
17733(outs DoubleRegs:$Rxx32),
17734(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17735"$Rxx32 += cmpyiw($Rss32,$Rtt32)",
17736tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17737let Inst{7-5} = 0b010;
17738let Inst{13-13} = 0b0;
17739let Inst{31-21} = 0b11101010011;
17740let prefersSlot3 = 1;
17741let Constraints = "$Rxx32 = $Rxx32in";
17742}
17743def M7_dcmpyiwc : HInst<
17744(outs DoubleRegs:$Rdd32),
17745(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17746"$Rdd32 = cmpyiw($Rss32,$Rtt32*)",
17747tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17748let Inst{7-5} = 0b010;
17749let Inst{13-13} = 0b0;
17750let Inst{31-21} = 0b11101000111;
17751let prefersSlot3 = 1;
17752}
17753def M7_dcmpyiwc_acc : HInst<
17754(outs DoubleRegs:$Rxx32),
17755(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17756"$Rxx32 += cmpyiw($Rss32,$Rtt32*)",
17757tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17758let Inst{7-5} = 0b110;
17759let Inst{13-13} = 0b0;
17760let Inst{31-21} = 0b11101010010;
17761let prefersSlot3 = 1;
17762let Constraints = "$Rxx32 = $Rxx32in";
17763}
17764def M7_dcmpyrw : HInst<
17765(outs DoubleRegs:$Rdd32),
17766(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17767"$Rdd32 = cmpyrw($Rss32,$Rtt32)",
17768tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17769let Inst{7-5} = 0b010;
17770let Inst{13-13} = 0b0;
17771let Inst{31-21} = 0b11101000100;
17772let prefersSlot3 = 1;
17773}
17774def M7_dcmpyrw_acc : HInst<
17775(outs DoubleRegs:$Rxx32),
17776(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17777"$Rxx32 += cmpyrw($Rss32,$Rtt32)",
17778tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17779let Inst{7-5} = 0b010;
17780let Inst{13-13} = 0b0;
17781let Inst{31-21} = 0b11101010100;
17782let prefersSlot3 = 1;
17783let Constraints = "$Rxx32 = $Rxx32in";
17784}
17785def M7_dcmpyrwc : HInst<
17786(outs DoubleRegs:$Rdd32),
17787(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17788"$Rdd32 = cmpyrw($Rss32,$Rtt32*)",
17789tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17790let Inst{7-5} = 0b010;
17791let Inst{13-13} = 0b0;
17792let Inst{31-21} = 0b11101000110;
17793let prefersSlot3 = 1;
17794}
17795def M7_dcmpyrwc_acc : HInst<
17796(outs DoubleRegs:$Rxx32),
17797(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17798"$Rxx32 += cmpyrw($Rss32,$Rtt32*)",
17799tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17800let Inst{7-5} = 0b010;
17801let Inst{13-13} = 0b0;
17802let Inst{31-21} = 0b11101010110;
17803let prefersSlot3 = 1;
17804let Constraints = "$Rxx32 = $Rxx32in";
17805}
17806def M7_vdmpy : HInst<
17807(outs DoubleRegs:$Rdd32),
17808(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17809"$Rdd32 = vdmpyw($Rss32,$Rtt32)",
17810tc_5a4b5e58, TypeM>, Requires<[HasV67]> {
17811let isPseudo = 1;
17812let isCodeGenOnly = 1;
17813}
17814def M7_vdmpy_acc : HInst<
17815(outs DoubleRegs:$Rxx32),
17816(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17817"$Rxx32 += vdmpyw($Rss32,$Rtt32)",
17818tc_197dce51, TypeM>, Requires<[HasV67]> {
17819let isPseudo = 1;
17820let isCodeGenOnly = 1;
17821let Constraints = "$Rxx32 = $Rxx32in";
17822}
17823def M7_wcmpyiw : HInst<
17824(outs IntRegs:$Rd32),
17825(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17826"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:sat",
17827tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17828let Inst{7-5} = 0b000;
17829let Inst{13-13} = 0b0;
17830let Inst{31-21} = 0b11101001001;
17831let hasNewValue = 1;
17832let opNewValue = 0;
17833let prefersSlot3 = 1;
17834let Defs = [USR_OVF];
17835}
17836def M7_wcmpyiw_rnd : HInst<
17837(outs IntRegs:$Rd32),
17838(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17839"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:rnd:sat",
17840tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17841let Inst{7-5} = 0b000;
17842let Inst{13-13} = 0b0;
17843let Inst{31-21} = 0b11101001101;
17844let hasNewValue = 1;
17845let opNewValue = 0;
17846let prefersSlot3 = 1;
17847let Defs = [USR_OVF];
17848}
17849def M7_wcmpyiwc : HInst<
17850(outs IntRegs:$Rd32),
17851(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17852"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:sat",
17853tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17854let Inst{7-5} = 0b100;
17855let Inst{13-13} = 0b0;
17856let Inst{31-21} = 0b11101001000;
17857let hasNewValue = 1;
17858let opNewValue = 0;
17859let prefersSlot3 = 1;
17860let Defs = [USR_OVF];
17861}
17862def M7_wcmpyiwc_rnd : HInst<
17863(outs IntRegs:$Rd32),
17864(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17865"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:rnd:sat",
17866tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17867let Inst{7-5} = 0b100;
17868let Inst{13-13} = 0b0;
17869let Inst{31-21} = 0b11101001100;
17870let hasNewValue = 1;
17871let opNewValue = 0;
17872let prefersSlot3 = 1;
17873let Defs = [USR_OVF];
17874}
17875def M7_wcmpyrw : HInst<
17876(outs IntRegs:$Rd32),
17877(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17878"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:sat",
17879tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17880let Inst{7-5} = 0b000;
17881let Inst{13-13} = 0b0;
17882let Inst{31-21} = 0b11101001010;
17883let hasNewValue = 1;
17884let opNewValue = 0;
17885let prefersSlot3 = 1;
17886let Defs = [USR_OVF];
17887}
17888def M7_wcmpyrw_rnd : HInst<
17889(outs IntRegs:$Rd32),
17890(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17891"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:rnd:sat",
17892tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17893let Inst{7-5} = 0b000;
17894let Inst{13-13} = 0b0;
17895let Inst{31-21} = 0b11101001110;
17896let hasNewValue = 1;
17897let opNewValue = 0;
17898let prefersSlot3 = 1;
17899let Defs = [USR_OVF];
17900}
17901def M7_wcmpyrwc : HInst<
17902(outs IntRegs:$Rd32),
17903(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17904"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:sat",
17905tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17906let Inst{7-5} = 0b000;
17907let Inst{13-13} = 0b0;
17908let Inst{31-21} = 0b11101001011;
17909let hasNewValue = 1;
17910let opNewValue = 0;
17911let prefersSlot3 = 1;
17912let Defs = [USR_OVF];
17913}
17914def M7_wcmpyrwc_rnd : HInst<
17915(outs IntRegs:$Rd32),
17916(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17917"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:rnd:sat",
17918tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17919let Inst{7-5} = 0b000;
17920let Inst{13-13} = 0b0;
17921let Inst{31-21} = 0b11101001111;
17922let hasNewValue = 1;
17923let opNewValue = 0;
17924let prefersSlot3 = 1;
17925let Defs = [USR_OVF];
17926}
17927def PS_loadrbabs : HInst<
17928(outs IntRegs:$Rd32),
17929(ins u32_0Imm:$Ii),
17930"$Rd32 = memb(#$Ii)",
17931tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17932let Inst{24-21} = 0b1000;
17933let Inst{31-27} = 0b01001;
17934let hasNewValue = 1;
17935let opNewValue = 0;
17936let addrMode = Absolute;
17937let accessSize = ByteAccess;
17938let mayLoad = 1;
17939let isExtended = 1;
17940let BaseOpcode = "L4_loadrb_abs";
17941let CextOpcode = "L2_loadrb";
17942let isPredicable = 1;
17943let DecoderNamespace = "MustExtend";
17944let isExtended = 1;
17945let opExtendable = 1;
17946let isExtentSigned = 0;
17947let opExtentBits = 16;
17948let opExtentAlign = 0;
17949}
17950def PS_loadrdabs : HInst<
17951(outs DoubleRegs:$Rdd32),
17952(ins u29_3Imm:$Ii),
17953"$Rdd32 = memd(#$Ii)",
17954tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
17955let Inst{24-21} = 0b1110;
17956let Inst{31-27} = 0b01001;
17957let addrMode = Absolute;
17958let accessSize = DoubleWordAccess;
17959let mayLoad = 1;
17960let isExtended = 1;
17961let BaseOpcode = "L4_loadrd_abs";
17962let CextOpcode = "L2_loadrd";
17963let isPredicable = 1;
17964let DecoderNamespace = "MustExtend";
17965let isExtended = 1;
17966let opExtendable = 1;
17967let isExtentSigned = 0;
17968let opExtentBits = 19;
17969let opExtentAlign = 3;
17970}
17971def PS_loadrhabs : HInst<
17972(outs IntRegs:$Rd32),
17973(ins u31_1Imm:$Ii),
17974"$Rd32 = memh(#$Ii)",
17975tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17976let Inst{24-21} = 0b1010;
17977let Inst{31-27} = 0b01001;
17978let hasNewValue = 1;
17979let opNewValue = 0;
17980let addrMode = Absolute;
17981let accessSize = HalfWordAccess;
17982let mayLoad = 1;
17983let isExtended = 1;
17984let BaseOpcode = "L4_loadrh_abs";
17985let CextOpcode = "L2_loadrh";
17986let isPredicable = 1;
17987let DecoderNamespace = "MustExtend";
17988let isExtended = 1;
17989let opExtendable = 1;
17990let isExtentSigned = 0;
17991let opExtentBits = 17;
17992let opExtentAlign = 1;
17993}
17994def PS_loadriabs : HInst<
17995(outs IntRegs:$Rd32),
17996(ins u30_2Imm:$Ii),
17997"$Rd32 = memw(#$Ii)",
17998tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
17999let Inst{24-21} = 0b1100;
18000let Inst{31-27} = 0b01001;
18001let hasNewValue = 1;
18002let opNewValue = 0;
18003let addrMode = Absolute;
18004let accessSize = WordAccess;
18005let mayLoad = 1;
18006let isExtended = 1;
18007let BaseOpcode = "L4_loadri_abs";
18008let CextOpcode = "L2_loadri";
18009let isPredicable = 1;
18010let DecoderNamespace = "MustExtend";
18011let isExtended = 1;
18012let opExtendable = 1;
18013let isExtentSigned = 0;
18014let opExtentBits = 18;
18015let opExtentAlign = 2;
18016}
18017def PS_loadrubabs : HInst<
18018(outs IntRegs:$Rd32),
18019(ins u32_0Imm:$Ii),
18020"$Rd32 = memub(#$Ii)",
18021tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
18022let Inst{24-21} = 0b1001;
18023let Inst{31-27} = 0b01001;
18024let hasNewValue = 1;
18025let opNewValue = 0;
18026let addrMode = Absolute;
18027let accessSize = ByteAccess;
18028let mayLoad = 1;
18029let isExtended = 1;
18030let BaseOpcode = "L4_loadrub_abs";
18031let CextOpcode = "L2_loadrub";
18032let isPredicable = 1;
18033let DecoderNamespace = "MustExtend";
18034let isExtended = 1;
18035let opExtendable = 1;
18036let isExtentSigned = 0;
18037let opExtentBits = 16;
18038let opExtentAlign = 0;
18039}
18040def PS_loadruhabs : HInst<
18041(outs IntRegs:$Rd32),
18042(ins u31_1Imm:$Ii),
18043"$Rd32 = memuh(#$Ii)",
18044tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
18045let Inst{24-21} = 0b1011;
18046let Inst{31-27} = 0b01001;
18047let hasNewValue = 1;
18048let opNewValue = 0;
18049let addrMode = Absolute;
18050let accessSize = HalfWordAccess;
18051let mayLoad = 1;
18052let isExtended = 1;
18053let BaseOpcode = "L4_loadruh_abs";
18054let CextOpcode = "L2_loadruh";
18055let isPredicable = 1;
18056let DecoderNamespace = "MustExtend";
18057let isExtended = 1;
18058let opExtendable = 1;
18059let isExtentSigned = 0;
18060let opExtentBits = 17;
18061let opExtentAlign = 1;
18062}
18063def PS_storerbabs : HInst<
18064(outs),
18065(ins u32_0Imm:$Ii, IntRegs:$Rt32),
18066"memb(#$Ii) = $Rt32",
18067tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
18068let Inst{24-21} = 0b0000;
18069let Inst{31-27} = 0b01001;
18070let addrMode = Absolute;
18071let accessSize = ByteAccess;
18072let isExtended = 1;
18073let mayStore = 1;
18074let BaseOpcode = "S2_storerbabs";
18075let CextOpcode = "S2_storerb";
18076let isNVStorable = 1;
18077let isPredicable = 1;
18078let DecoderNamespace = "MustExtend";
18079let isExtended = 1;
18080let opExtendable = 0;
18081let isExtentSigned = 0;
18082let opExtentBits = 16;
18083let opExtentAlign = 0;
18084}
18085def PS_storerbnewabs : HInst<
18086(outs),
18087(ins u32_0Imm:$Ii, IntRegs:$Nt8),
18088"memb(#$Ii) = $Nt8.new",
18089tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
18090let Inst{12-11} = 0b00;
18091let Inst{24-21} = 0b0101;
18092let Inst{31-27} = 0b01001;
18093let addrMode = Absolute;
18094let accessSize = ByteAccess;
18095let isNVStore = 1;
18096let isNewValue = 1;
18097let isExtended = 1;
18098let isRestrictNoSlot1Store = 1;
18099let mayStore = 1;
18100let BaseOpcode = "S2_storerbabs";
18101let CextOpcode = "S2_storerb";
18102let isPredicable = 1;
18103let DecoderNamespace = "MustExtend";
18104let isExtended = 1;
18105let opExtendable = 0;
18106let isExtentSigned = 0;
18107let opExtentBits = 16;
18108let opExtentAlign = 0;
18109let opNewValue = 1;
18110}
18111def PS_storerdabs : HInst<
18112(outs),
18113(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
18114"memd(#$Ii) = $Rtt32",
18115tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
18116let Inst{24-21} = 0b0110;
18117let Inst{31-27} = 0b01001;
18118let addrMode = Absolute;
18119let accessSize = DoubleWordAccess;
18120let isExtended = 1;
18121let mayStore = 1;
18122let BaseOpcode = "S2_storerdabs";
18123let CextOpcode = "S2_storerd";
18124let isPredicable = 1;
18125let DecoderNamespace = "MustExtend";
18126let isExtended = 1;
18127let opExtendable = 0;
18128let isExtentSigned = 0;
18129let opExtentBits = 19;
18130let opExtentAlign = 3;
18131}
18132def PS_storerfabs : HInst<
18133(outs),
18134(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18135"memh(#$Ii) = $Rt32.h",
18136tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18137let Inst{24-21} = 0b0011;
18138let Inst{31-27} = 0b01001;
18139let addrMode = Absolute;
18140let accessSize = HalfWordAccess;
18141let isExtended = 1;
18142let mayStore = 1;
18143let BaseOpcode = "S2_storerfabs";
18144let CextOpcode = "S2_storerf";
18145let isPredicable = 1;
18146let DecoderNamespace = "MustExtend";
18147let isExtended = 1;
18148let opExtendable = 0;
18149let isExtentSigned = 0;
18150let opExtentBits = 17;
18151let opExtentAlign = 1;
18152}
18153def PS_storerhabs : HInst<
18154(outs),
18155(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18156"memh(#$Ii) = $Rt32",
18157tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18158let Inst{24-21} = 0b0010;
18159let Inst{31-27} = 0b01001;
18160let addrMode = Absolute;
18161let accessSize = HalfWordAccess;
18162let isExtended = 1;
18163let mayStore = 1;
18164let BaseOpcode = "S2_storerhabs";
18165let CextOpcode = "S2_storerh";
18166let isNVStorable = 1;
18167let isPredicable = 1;
18168let DecoderNamespace = "MustExtend";
18169let isExtended = 1;
18170let opExtendable = 0;
18171let isExtentSigned = 0;
18172let opExtentBits = 17;
18173let opExtentAlign = 1;
18174}
18175def PS_storerhnewabs : HInst<
18176(outs),
18177(ins u31_1Imm:$Ii, IntRegs:$Nt8),
18178"memh(#$Ii) = $Nt8.new",
18179tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
18180let Inst{12-11} = 0b01;
18181let Inst{24-21} = 0b0101;
18182let Inst{31-27} = 0b01001;
18183let addrMode = Absolute;
18184let accessSize = HalfWordAccess;
18185let isNVStore = 1;
18186let isNewValue = 1;
18187let isExtended = 1;
18188let isRestrictNoSlot1Store = 1;
18189let mayStore = 1;
18190let BaseOpcode = "S2_storerhabs";
18191let CextOpcode = "S2_storerh";
18192let isPredicable = 1;
18193let DecoderNamespace = "MustExtend";
18194let isExtended = 1;
18195let opExtendable = 0;
18196let isExtentSigned = 0;
18197let opExtentBits = 17;
18198let opExtentAlign = 1;
18199let opNewValue = 1;
18200}
18201def PS_storeriabs : HInst<
18202(outs),
18203(ins u30_2Imm:$Ii, IntRegs:$Rt32),
18204"memw(#$Ii) = $Rt32",
18205tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
18206let Inst{24-21} = 0b0100;
18207let Inst{31-27} = 0b01001;
18208let addrMode = Absolute;
18209let accessSize = WordAccess;
18210let isExtended = 1;
18211let mayStore = 1;
18212let BaseOpcode = "S2_storeriabs";
18213let CextOpcode = "S2_storeri";
18214let isNVStorable = 1;
18215let isPredicable = 1;
18216let DecoderNamespace = "MustExtend";
18217let isExtended = 1;
18218let opExtendable = 0;
18219let isExtentSigned = 0;
18220let opExtentBits = 18;
18221let opExtentAlign = 2;
18222}
18223def PS_storerinewabs : HInst<
18224(outs),
18225(ins u30_2Imm:$Ii, IntRegs:$Nt8),
18226"memw(#$Ii) = $Nt8.new",
18227tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
18228let Inst{12-11} = 0b10;
18229let Inst{24-21} = 0b0101;
18230let Inst{31-27} = 0b01001;
18231let addrMode = Absolute;
18232let accessSize = WordAccess;
18233let isNVStore = 1;
18234let isNewValue = 1;
18235let isExtended = 1;
18236let isRestrictNoSlot1Store = 1;
18237let mayStore = 1;
18238let BaseOpcode = "S2_storeriabs";
18239let CextOpcode = "S2_storeri";
18240let isPredicable = 1;
18241let DecoderNamespace = "MustExtend";
18242let isExtended = 1;
18243let opExtendable = 0;
18244let isExtentSigned = 0;
18245let opExtentBits = 18;
18246let opExtentAlign = 2;
18247let opNewValue = 1;
18248}
18249def R6_release_at_vi : HInst<
18250(outs),
18251(ins IntRegs:$Rs32),
18252"release($Rs32):at",
18253tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18254let Inst{7-2} = 0b000011;
18255let Inst{13-13} = 0b0;
18256let Inst{31-21} = 0b10100000111;
18257let isSolo = 1;
18258let mayStore = 1;
18259}
18260def R6_release_st_vi : HInst<
18261(outs),
18262(ins IntRegs:$Rs32),
18263"release($Rs32):st",
18264tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18265let Inst{7-2} = 0b001011;
18266let Inst{13-13} = 0b0;
18267let Inst{31-21} = 0b10100000111;
18268let isSolo = 1;
18269let mayStore = 1;
18270}
18271def S2_addasl_rrri : HInst<
18272(outs IntRegs:$Rd32),
18273(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
18274"$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
18275tc_2c13e7f5, TypeS_3op>, Enc_47ef61 {
18276let Inst{13-13} = 0b0;
18277let Inst{31-21} = 0b11000100000;
18278let hasNewValue = 1;
18279let opNewValue = 0;
18280let prefersSlot3 = 1;
18281}
18282def S2_allocframe : HInst<
18283(outs IntRegs:$Rx32),
18284(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
18285"allocframe($Rx32,#$Ii):raw",
18286tc_934753bb, TypeST>, Enc_22c845 {
18287let Inst{13-11} = 0b000;
18288let Inst{31-21} = 0b10100000100;
18289let hasNewValue = 1;
18290let opNewValue = 0;
18291let addrMode = BaseImmOffset;
18292let accessSize = DoubleWordAccess;
18293let mayStore = 1;
18294let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
18295let Defs = [R30];
18296let Constraints = "$Rx32 = $Rx32in";
18297}
18298def S2_asl_i_p : HInst<
18299(outs DoubleRegs:$Rdd32),
18300(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18301"$Rdd32 = asl($Rss32,#$Ii)",
18302tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18303let Inst{7-5} = 0b010;
18304let Inst{31-21} = 0b10000000000;
18305}
18306def S2_asl_i_p_acc : HInst<
18307(outs DoubleRegs:$Rxx32),
18308(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18309"$Rxx32 += asl($Rss32,#$Ii)",
18310tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18311let Inst{7-5} = 0b110;
18312let Inst{31-21} = 0b10000010000;
18313let prefersSlot3 = 1;
18314let Constraints = "$Rxx32 = $Rxx32in";
18315}
18316def S2_asl_i_p_and : HInst<
18317(outs DoubleRegs:$Rxx32),
18318(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18319"$Rxx32 &= asl($Rss32,#$Ii)",
18320tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18321let Inst{7-5} = 0b010;
18322let Inst{31-21} = 0b10000010010;
18323let prefersSlot3 = 1;
18324let Constraints = "$Rxx32 = $Rxx32in";
18325}
18326def S2_asl_i_p_nac : HInst<
18327(outs DoubleRegs:$Rxx32),
18328(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18329"$Rxx32 -= asl($Rss32,#$Ii)",
18330tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18331let Inst{7-5} = 0b010;
18332let Inst{31-21} = 0b10000010000;
18333let prefersSlot3 = 1;
18334let Constraints = "$Rxx32 = $Rxx32in";
18335}
18336def S2_asl_i_p_or : HInst<
18337(outs DoubleRegs:$Rxx32),
18338(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18339"$Rxx32 |= asl($Rss32,#$Ii)",
18340tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18341let Inst{7-5} = 0b110;
18342let Inst{31-21} = 0b10000010010;
18343let prefersSlot3 = 1;
18344let Constraints = "$Rxx32 = $Rxx32in";
18345}
18346def S2_asl_i_p_xacc : HInst<
18347(outs DoubleRegs:$Rxx32),
18348(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18349"$Rxx32 ^= asl($Rss32,#$Ii)",
18350tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18351let Inst{7-5} = 0b010;
18352let Inst{31-21} = 0b10000010100;
18353let prefersSlot3 = 1;
18354let Constraints = "$Rxx32 = $Rxx32in";
18355}
18356def S2_asl_i_r : HInst<
18357(outs IntRegs:$Rd32),
18358(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18359"$Rd32 = asl($Rs32,#$Ii)",
18360tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18361let Inst{7-5} = 0b010;
18362let Inst{13-13} = 0b0;
18363let Inst{31-21} = 0b10001100000;
18364let hasNewValue = 1;
18365let opNewValue = 0;
18366}
18367def S2_asl_i_r_acc : HInst<
18368(outs IntRegs:$Rx32),
18369(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18370"$Rx32 += asl($Rs32,#$Ii)",
18371tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18372let Inst{7-5} = 0b110;
18373let Inst{13-13} = 0b0;
18374let Inst{31-21} = 0b10001110000;
18375let hasNewValue = 1;
18376let opNewValue = 0;
18377let prefersSlot3 = 1;
18378let Constraints = "$Rx32 = $Rx32in";
18379}
18380def S2_asl_i_r_and : HInst<
18381(outs IntRegs:$Rx32),
18382(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18383"$Rx32 &= asl($Rs32,#$Ii)",
18384tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18385let Inst{7-5} = 0b010;
18386let Inst{13-13} = 0b0;
18387let Inst{31-21} = 0b10001110010;
18388let hasNewValue = 1;
18389let opNewValue = 0;
18390let prefersSlot3 = 1;
18391let Constraints = "$Rx32 = $Rx32in";
18392}
18393def S2_asl_i_r_nac : HInst<
18394(outs IntRegs:$Rx32),
18395(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18396"$Rx32 -= asl($Rs32,#$Ii)",
18397tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18398let Inst{7-5} = 0b010;
18399let Inst{13-13} = 0b0;
18400let Inst{31-21} = 0b10001110000;
18401let hasNewValue = 1;
18402let opNewValue = 0;
18403let prefersSlot3 = 1;
18404let Constraints = "$Rx32 = $Rx32in";
18405}
18406def S2_asl_i_r_or : HInst<
18407(outs IntRegs:$Rx32),
18408(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18409"$Rx32 |= asl($Rs32,#$Ii)",
18410tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18411let Inst{7-5} = 0b110;
18412let Inst{13-13} = 0b0;
18413let Inst{31-21} = 0b10001110010;
18414let hasNewValue = 1;
18415let opNewValue = 0;
18416let prefersSlot3 = 1;
18417let Constraints = "$Rx32 = $Rx32in";
18418}
18419def S2_asl_i_r_sat : HInst<
18420(outs IntRegs:$Rd32),
18421(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18422"$Rd32 = asl($Rs32,#$Ii):sat",
18423tc_8a825db2, TypeS_2op>, Enc_a05677 {
18424let Inst{7-5} = 0b010;
18425let Inst{13-13} = 0b0;
18426let Inst{31-21} = 0b10001100010;
18427let hasNewValue = 1;
18428let opNewValue = 0;
18429let prefersSlot3 = 1;
18430let Defs = [USR_OVF];
18431}
18432def S2_asl_i_r_xacc : HInst<
18433(outs IntRegs:$Rx32),
18434(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18435"$Rx32 ^= asl($Rs32,#$Ii)",
18436tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18437let Inst{7-5} = 0b010;
18438let Inst{13-13} = 0b0;
18439let Inst{31-21} = 0b10001110100;
18440let hasNewValue = 1;
18441let opNewValue = 0;
18442let prefersSlot3 = 1;
18443let Constraints = "$Rx32 = $Rx32in";
18444}
18445def S2_asl_i_vh : HInst<
18446(outs DoubleRegs:$Rdd32),
18447(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18448"$Rdd32 = vaslh($Rss32,#$Ii)",
18449tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18450let Inst{7-5} = 0b010;
18451let Inst{13-12} = 0b00;
18452let Inst{31-21} = 0b10000000100;
18453}
18454def S2_asl_i_vw : HInst<
18455(outs DoubleRegs:$Rdd32),
18456(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18457"$Rdd32 = vaslw($Rss32,#$Ii)",
18458tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18459let Inst{7-5} = 0b010;
18460let Inst{13-13} = 0b0;
18461let Inst{31-21} = 0b10000000010;
18462}
18463def S2_asl_r_p : HInst<
18464(outs DoubleRegs:$Rdd32),
18465(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18466"$Rdd32 = asl($Rss32,$Rt32)",
18467tc_5da50c4b, TypeS_3op>, Enc_927852 {
18468let Inst{7-5} = 0b100;
18469let Inst{13-13} = 0b0;
18470let Inst{31-21} = 0b11000011100;
18471}
18472def S2_asl_r_p_acc : HInst<
18473(outs DoubleRegs:$Rxx32),
18474(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18475"$Rxx32 += asl($Rss32,$Rt32)",
18476tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18477let Inst{7-5} = 0b100;
18478let Inst{13-13} = 0b0;
18479let Inst{31-21} = 0b11001011110;
18480let prefersSlot3 = 1;
18481let Constraints = "$Rxx32 = $Rxx32in";
18482}
18483def S2_asl_r_p_and : HInst<
18484(outs DoubleRegs:$Rxx32),
18485(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18486"$Rxx32 &= asl($Rss32,$Rt32)",
18487tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18488let Inst{7-5} = 0b100;
18489let Inst{13-13} = 0b0;
18490let Inst{31-21} = 0b11001011010;
18491let prefersSlot3 = 1;
18492let Constraints = "$Rxx32 = $Rxx32in";
18493}
18494def S2_asl_r_p_nac : HInst<
18495(outs DoubleRegs:$Rxx32),
18496(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18497"$Rxx32 -= asl($Rss32,$Rt32)",
18498tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18499let Inst{7-5} = 0b100;
18500let Inst{13-13} = 0b0;
18501let Inst{31-21} = 0b11001011100;
18502let prefersSlot3 = 1;
18503let Constraints = "$Rxx32 = $Rxx32in";
18504}
18505def S2_asl_r_p_or : HInst<
18506(outs DoubleRegs:$Rxx32),
18507(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18508"$Rxx32 |= asl($Rss32,$Rt32)",
18509tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18510let Inst{7-5} = 0b100;
18511let Inst{13-13} = 0b0;
18512let Inst{31-21} = 0b11001011000;
18513let prefersSlot3 = 1;
18514let Constraints = "$Rxx32 = $Rxx32in";
18515}
18516def S2_asl_r_p_xor : HInst<
18517(outs DoubleRegs:$Rxx32),
18518(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18519"$Rxx32 ^= asl($Rss32,$Rt32)",
18520tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18521let Inst{7-5} = 0b100;
18522let Inst{13-13} = 0b0;
18523let Inst{31-21} = 0b11001011011;
18524let prefersSlot3 = 1;
18525let Constraints = "$Rxx32 = $Rxx32in";
18526}
18527def S2_asl_r_r : HInst<
18528(outs IntRegs:$Rd32),
18529(ins IntRegs:$Rs32, IntRegs:$Rt32),
18530"$Rd32 = asl($Rs32,$Rt32)",
18531tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18532let Inst{7-5} = 0b100;
18533let Inst{13-13} = 0b0;
18534let Inst{31-21} = 0b11000110010;
18535let hasNewValue = 1;
18536let opNewValue = 0;
18537}
18538def S2_asl_r_r_acc : HInst<
18539(outs IntRegs:$Rx32),
18540(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18541"$Rx32 += asl($Rs32,$Rt32)",
18542tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18543let Inst{7-5} = 0b100;
18544let Inst{13-13} = 0b0;
18545let Inst{31-21} = 0b11001100110;
18546let hasNewValue = 1;
18547let opNewValue = 0;
18548let prefersSlot3 = 1;
18549let Constraints = "$Rx32 = $Rx32in";
18550}
18551def S2_asl_r_r_and : HInst<
18552(outs IntRegs:$Rx32),
18553(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18554"$Rx32 &= asl($Rs32,$Rt32)",
18555tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18556let Inst{7-5} = 0b100;
18557let Inst{13-13} = 0b0;
18558let Inst{31-21} = 0b11001100010;
18559let hasNewValue = 1;
18560let opNewValue = 0;
18561let prefersSlot3 = 1;
18562let Constraints = "$Rx32 = $Rx32in";
18563}
18564def S2_asl_r_r_nac : HInst<
18565(outs IntRegs:$Rx32),
18566(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18567"$Rx32 -= asl($Rs32,$Rt32)",
18568tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18569let Inst{7-5} = 0b100;
18570let Inst{13-13} = 0b0;
18571let Inst{31-21} = 0b11001100100;
18572let hasNewValue = 1;
18573let opNewValue = 0;
18574let prefersSlot3 = 1;
18575let Constraints = "$Rx32 = $Rx32in";
18576}
18577def S2_asl_r_r_or : HInst<
18578(outs IntRegs:$Rx32),
18579(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18580"$Rx32 |= asl($Rs32,$Rt32)",
18581tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18582let Inst{7-5} = 0b100;
18583let Inst{13-13} = 0b0;
18584let Inst{31-21} = 0b11001100000;
18585let hasNewValue = 1;
18586let opNewValue = 0;
18587let prefersSlot3 = 1;
18588let Constraints = "$Rx32 = $Rx32in";
18589}
18590def S2_asl_r_r_sat : HInst<
18591(outs IntRegs:$Rd32),
18592(ins IntRegs:$Rs32, IntRegs:$Rt32),
18593"$Rd32 = asl($Rs32,$Rt32):sat",
18594tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18595let Inst{7-5} = 0b100;
18596let Inst{13-13} = 0b0;
18597let Inst{31-21} = 0b11000110000;
18598let hasNewValue = 1;
18599let opNewValue = 0;
18600let prefersSlot3 = 1;
18601let Defs = [USR_OVF];
18602}
18603def S2_asl_r_vh : HInst<
18604(outs DoubleRegs:$Rdd32),
18605(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18606"$Rdd32 = vaslh($Rss32,$Rt32)",
18607tc_5da50c4b, TypeS_3op>, Enc_927852 {
18608let Inst{7-5} = 0b100;
18609let Inst{13-13} = 0b0;
18610let Inst{31-21} = 0b11000011010;
18611}
18612def S2_asl_r_vw : HInst<
18613(outs DoubleRegs:$Rdd32),
18614(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18615"$Rdd32 = vaslw($Rss32,$Rt32)",
18616tc_5da50c4b, TypeS_3op>, Enc_927852 {
18617let Inst{7-5} = 0b100;
18618let Inst{13-13} = 0b0;
18619let Inst{31-21} = 0b11000011000;
18620}
18621def S2_asr_i_p : HInst<
18622(outs DoubleRegs:$Rdd32),
18623(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18624"$Rdd32 = asr($Rss32,#$Ii)",
18625tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18626let Inst{7-5} = 0b000;
18627let Inst{31-21} = 0b10000000000;
18628}
18629def S2_asr_i_p_acc : HInst<
18630(outs DoubleRegs:$Rxx32),
18631(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18632"$Rxx32 += asr($Rss32,#$Ii)",
18633tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18634let Inst{7-5} = 0b100;
18635let Inst{31-21} = 0b10000010000;
18636let prefersSlot3 = 1;
18637let Constraints = "$Rxx32 = $Rxx32in";
18638}
18639def S2_asr_i_p_and : HInst<
18640(outs DoubleRegs:$Rxx32),
18641(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18642"$Rxx32 &= asr($Rss32,#$Ii)",
18643tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18644let Inst{7-5} = 0b000;
18645let Inst{31-21} = 0b10000010010;
18646let prefersSlot3 = 1;
18647let Constraints = "$Rxx32 = $Rxx32in";
18648}
18649def S2_asr_i_p_nac : HInst<
18650(outs DoubleRegs:$Rxx32),
18651(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18652"$Rxx32 -= asr($Rss32,#$Ii)",
18653tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18654let Inst{7-5} = 0b000;
18655let Inst{31-21} = 0b10000010000;
18656let prefersSlot3 = 1;
18657let Constraints = "$Rxx32 = $Rxx32in";
18658}
18659def S2_asr_i_p_or : HInst<
18660(outs DoubleRegs:$Rxx32),
18661(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18662"$Rxx32 |= asr($Rss32,#$Ii)",
18663tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18664let Inst{7-5} = 0b100;
18665let Inst{31-21} = 0b10000010010;
18666let prefersSlot3 = 1;
18667let Constraints = "$Rxx32 = $Rxx32in";
18668}
18669def S2_asr_i_p_rnd : HInst<
18670(outs DoubleRegs:$Rdd32),
18671(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18672"$Rdd32 = asr($Rss32,#$Ii):rnd",
18673tc_0dfac0a7, TypeS_2op>, Enc_5eac98 {
18674let Inst{7-5} = 0b111;
18675let Inst{31-21} = 0b10000000110;
18676let prefersSlot3 = 1;
18677}
18678def S2_asr_i_p_rnd_goodsyntax : HInst<
18679(outs DoubleRegs:$Rdd32),
18680(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18681"$Rdd32 = asrrnd($Rss32,#$Ii)",
18682tc_0dfac0a7, TypeS_2op> {
18683let isPseudo = 1;
18684}
18685def S2_asr_i_r : HInst<
18686(outs IntRegs:$Rd32),
18687(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18688"$Rd32 = asr($Rs32,#$Ii)",
18689tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18690let Inst{7-5} = 0b000;
18691let Inst{13-13} = 0b0;
18692let Inst{31-21} = 0b10001100000;
18693let hasNewValue = 1;
18694let opNewValue = 0;
18695}
18696def S2_asr_i_r_acc : HInst<
18697(outs IntRegs:$Rx32),
18698(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18699"$Rx32 += asr($Rs32,#$Ii)",
18700tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18701let Inst{7-5} = 0b100;
18702let Inst{13-13} = 0b0;
18703let Inst{31-21} = 0b10001110000;
18704let hasNewValue = 1;
18705let opNewValue = 0;
18706let prefersSlot3 = 1;
18707let Constraints = "$Rx32 = $Rx32in";
18708}
18709def S2_asr_i_r_and : HInst<
18710(outs IntRegs:$Rx32),
18711(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18712"$Rx32 &= asr($Rs32,#$Ii)",
18713tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18714let Inst{7-5} = 0b000;
18715let Inst{13-13} = 0b0;
18716let Inst{31-21} = 0b10001110010;
18717let hasNewValue = 1;
18718let opNewValue = 0;
18719let prefersSlot3 = 1;
18720let Constraints = "$Rx32 = $Rx32in";
18721}
18722def S2_asr_i_r_nac : HInst<
18723(outs IntRegs:$Rx32),
18724(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18725"$Rx32 -= asr($Rs32,#$Ii)",
18726tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18727let Inst{7-5} = 0b000;
18728let Inst{13-13} = 0b0;
18729let Inst{31-21} = 0b10001110000;
18730let hasNewValue = 1;
18731let opNewValue = 0;
18732let prefersSlot3 = 1;
18733let Constraints = "$Rx32 = $Rx32in";
18734}
18735def S2_asr_i_r_or : HInst<
18736(outs IntRegs:$Rx32),
18737(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18738"$Rx32 |= asr($Rs32,#$Ii)",
18739tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18740let Inst{7-5} = 0b100;
18741let Inst{13-13} = 0b0;
18742let Inst{31-21} = 0b10001110010;
18743let hasNewValue = 1;
18744let opNewValue = 0;
18745let prefersSlot3 = 1;
18746let Constraints = "$Rx32 = $Rx32in";
18747}
18748def S2_asr_i_r_rnd : HInst<
18749(outs IntRegs:$Rd32),
18750(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18751"$Rd32 = asr($Rs32,#$Ii):rnd",
18752tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
18753let Inst{7-5} = 0b000;
18754let Inst{13-13} = 0b0;
18755let Inst{31-21} = 0b10001100010;
18756let hasNewValue = 1;
18757let opNewValue = 0;
18758let prefersSlot3 = 1;
18759}
18760def S2_asr_i_r_rnd_goodsyntax : HInst<
18761(outs IntRegs:$Rd32),
18762(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18763"$Rd32 = asrrnd($Rs32,#$Ii)",
18764tc_0dfac0a7, TypeS_2op> {
18765let hasNewValue = 1;
18766let opNewValue = 0;
18767let isPseudo = 1;
18768}
18769def S2_asr_i_svw_trun : HInst<
18770(outs IntRegs:$Rd32),
18771(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18772"$Rd32 = vasrw($Rss32,#$Ii)",
18773tc_f34c1c21, TypeS_2op>, Enc_8dec2e {
18774let Inst{7-5} = 0b010;
18775let Inst{13-13} = 0b0;
18776let Inst{31-21} = 0b10001000110;
18777let hasNewValue = 1;
18778let opNewValue = 0;
18779let prefersSlot3 = 1;
18780}
18781def S2_asr_i_vh : HInst<
18782(outs DoubleRegs:$Rdd32),
18783(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18784"$Rdd32 = vasrh($Rss32,#$Ii)",
18785tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18786let Inst{7-5} = 0b000;
18787let Inst{13-12} = 0b00;
18788let Inst{31-21} = 0b10000000100;
18789}
18790def S2_asr_i_vw : HInst<
18791(outs DoubleRegs:$Rdd32),
18792(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18793"$Rdd32 = vasrw($Rss32,#$Ii)",
18794tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18795let Inst{7-5} = 0b000;
18796let Inst{13-13} = 0b0;
18797let Inst{31-21} = 0b10000000010;
18798}
18799def S2_asr_r_p : HInst<
18800(outs DoubleRegs:$Rdd32),
18801(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18802"$Rdd32 = asr($Rss32,$Rt32)",
18803tc_5da50c4b, TypeS_3op>, Enc_927852 {
18804let Inst{7-5} = 0b000;
18805let Inst{13-13} = 0b0;
18806let Inst{31-21} = 0b11000011100;
18807}
18808def S2_asr_r_p_acc : HInst<
18809(outs DoubleRegs:$Rxx32),
18810(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18811"$Rxx32 += asr($Rss32,$Rt32)",
18812tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18813let Inst{7-5} = 0b000;
18814let Inst{13-13} = 0b0;
18815let Inst{31-21} = 0b11001011110;
18816let prefersSlot3 = 1;
18817let Constraints = "$Rxx32 = $Rxx32in";
18818}
18819def S2_asr_r_p_and : HInst<
18820(outs DoubleRegs:$Rxx32),
18821(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18822"$Rxx32 &= asr($Rss32,$Rt32)",
18823tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18824let Inst{7-5} = 0b000;
18825let Inst{13-13} = 0b0;
18826let Inst{31-21} = 0b11001011010;
18827let prefersSlot3 = 1;
18828let Constraints = "$Rxx32 = $Rxx32in";
18829}
18830def S2_asr_r_p_nac : HInst<
18831(outs DoubleRegs:$Rxx32),
18832(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18833"$Rxx32 -= asr($Rss32,$Rt32)",
18834tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18835let Inst{7-5} = 0b000;
18836let Inst{13-13} = 0b0;
18837let Inst{31-21} = 0b11001011100;
18838let prefersSlot3 = 1;
18839let Constraints = "$Rxx32 = $Rxx32in";
18840}
18841def S2_asr_r_p_or : HInst<
18842(outs DoubleRegs:$Rxx32),
18843(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18844"$Rxx32 |= asr($Rss32,$Rt32)",
18845tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18846let Inst{7-5} = 0b000;
18847let Inst{13-13} = 0b0;
18848let Inst{31-21} = 0b11001011000;
18849let prefersSlot3 = 1;
18850let Constraints = "$Rxx32 = $Rxx32in";
18851}
18852def S2_asr_r_p_xor : HInst<
18853(outs DoubleRegs:$Rxx32),
18854(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18855"$Rxx32 ^= asr($Rss32,$Rt32)",
18856tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18857let Inst{7-5} = 0b000;
18858let Inst{13-13} = 0b0;
18859let Inst{31-21} = 0b11001011011;
18860let prefersSlot3 = 1;
18861let Constraints = "$Rxx32 = $Rxx32in";
18862}
18863def S2_asr_r_r : HInst<
18864(outs IntRegs:$Rd32),
18865(ins IntRegs:$Rs32, IntRegs:$Rt32),
18866"$Rd32 = asr($Rs32,$Rt32)",
18867tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18868let Inst{7-5} = 0b000;
18869let Inst{13-13} = 0b0;
18870let Inst{31-21} = 0b11000110010;
18871let hasNewValue = 1;
18872let opNewValue = 0;
18873}
18874def S2_asr_r_r_acc : HInst<
18875(outs IntRegs:$Rx32),
18876(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18877"$Rx32 += asr($Rs32,$Rt32)",
18878tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18879let Inst{7-5} = 0b000;
18880let Inst{13-13} = 0b0;
18881let Inst{31-21} = 0b11001100110;
18882let hasNewValue = 1;
18883let opNewValue = 0;
18884let prefersSlot3 = 1;
18885let Constraints = "$Rx32 = $Rx32in";
18886}
18887def S2_asr_r_r_and : HInst<
18888(outs IntRegs:$Rx32),
18889(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18890"$Rx32 &= asr($Rs32,$Rt32)",
18891tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18892let Inst{7-5} = 0b000;
18893let Inst{13-13} = 0b0;
18894let Inst{31-21} = 0b11001100010;
18895let hasNewValue = 1;
18896let opNewValue = 0;
18897let prefersSlot3 = 1;
18898let Constraints = "$Rx32 = $Rx32in";
18899}
18900def S2_asr_r_r_nac : HInst<
18901(outs IntRegs:$Rx32),
18902(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18903"$Rx32 -= asr($Rs32,$Rt32)",
18904tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18905let Inst{7-5} = 0b000;
18906let Inst{13-13} = 0b0;
18907let Inst{31-21} = 0b11001100100;
18908let hasNewValue = 1;
18909let opNewValue = 0;
18910let prefersSlot3 = 1;
18911let Constraints = "$Rx32 = $Rx32in";
18912}
18913def S2_asr_r_r_or : HInst<
18914(outs IntRegs:$Rx32),
18915(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18916"$Rx32 |= asr($Rs32,$Rt32)",
18917tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18918let Inst{7-5} = 0b000;
18919let Inst{13-13} = 0b0;
18920let Inst{31-21} = 0b11001100000;
18921let hasNewValue = 1;
18922let opNewValue = 0;
18923let prefersSlot3 = 1;
18924let Constraints = "$Rx32 = $Rx32in";
18925}
18926def S2_asr_r_r_sat : HInst<
18927(outs IntRegs:$Rd32),
18928(ins IntRegs:$Rs32, IntRegs:$Rt32),
18929"$Rd32 = asr($Rs32,$Rt32):sat",
18930tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18931let Inst{7-5} = 0b000;
18932let Inst{13-13} = 0b0;
18933let Inst{31-21} = 0b11000110000;
18934let hasNewValue = 1;
18935let opNewValue = 0;
18936let prefersSlot3 = 1;
18937let Defs = [USR_OVF];
18938}
18939def S2_asr_r_svw_trun : HInst<
18940(outs IntRegs:$Rd32),
18941(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18942"$Rd32 = vasrw($Rss32,$Rt32)",
18943tc_f34c1c21, TypeS_3op>, Enc_3d5b28 {
18944let Inst{7-5} = 0b010;
18945let Inst{13-13} = 0b0;
18946let Inst{31-21} = 0b11000101000;
18947let hasNewValue = 1;
18948let opNewValue = 0;
18949let prefersSlot3 = 1;
18950}
18951def S2_asr_r_vh : HInst<
18952(outs DoubleRegs:$Rdd32),
18953(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18954"$Rdd32 = vasrh($Rss32,$Rt32)",
18955tc_5da50c4b, TypeS_3op>, Enc_927852 {
18956let Inst{7-5} = 0b000;
18957let Inst{13-13} = 0b0;
18958let Inst{31-21} = 0b11000011010;
18959}
18960def S2_asr_r_vw : HInst<
18961(outs DoubleRegs:$Rdd32),
18962(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18963"$Rdd32 = vasrw($Rss32,$Rt32)",
18964tc_5da50c4b, TypeS_3op>, Enc_927852 {
18965let Inst{7-5} = 0b000;
18966let Inst{13-13} = 0b0;
18967let Inst{31-21} = 0b11000011000;
18968}
18969def S2_brev : HInst<
18970(outs IntRegs:$Rd32),
18971(ins IntRegs:$Rs32),
18972"$Rd32 = brev($Rs32)",
18973tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18974let Inst{13-5} = 0b000000110;
18975let Inst{31-21} = 0b10001100010;
18976let hasNewValue = 1;
18977let opNewValue = 0;
18978let prefersSlot3 = 1;
18979}
18980def S2_brevp : HInst<
18981(outs DoubleRegs:$Rdd32),
18982(ins DoubleRegs:$Rss32),
18983"$Rdd32 = brev($Rss32)",
18984tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
18985let Inst{13-5} = 0b000000110;
18986let Inst{31-21} = 0b10000000110;
18987let prefersSlot3 = 1;
18988}
18989def S2_cabacdecbin : HInst<
18990(outs DoubleRegs:$Rdd32),
18991(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18992"$Rdd32 = decbin($Rss32,$Rtt32)",
18993tc_db596beb, TypeS_3op>, Enc_a56825, Requires<[UseCabac]> {
18994let Inst{7-5} = 0b110;
18995let Inst{13-13} = 0b0;
18996let Inst{31-21} = 0b11000001110;
18997let isPredicateLate = 1;
18998let prefersSlot3 = 1;
18999let Defs = [P0];
19000}
19001def S2_cl0 : HInst<
19002(outs IntRegs:$Rd32),
19003(ins IntRegs:$Rs32),
19004"$Rd32 = cl0($Rs32)",
19005tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19006let Inst{13-5} = 0b000000101;
19007let Inst{31-21} = 0b10001100000;
19008let hasNewValue = 1;
19009let opNewValue = 0;
19010let prefersSlot3 = 1;
19011}
19012def S2_cl0p : HInst<
19013(outs IntRegs:$Rd32),
19014(ins DoubleRegs:$Rss32),
19015"$Rd32 = cl0($Rss32)",
19016tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19017let Inst{13-5} = 0b000000010;
19018let Inst{31-21} = 0b10001000010;
19019let hasNewValue = 1;
19020let opNewValue = 0;
19021let prefersSlot3 = 1;
19022}
19023def S2_cl1 : HInst<
19024(outs IntRegs:$Rd32),
19025(ins IntRegs:$Rs32),
19026"$Rd32 = cl1($Rs32)",
19027tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19028let Inst{13-5} = 0b000000110;
19029let Inst{31-21} = 0b10001100000;
19030let hasNewValue = 1;
19031let opNewValue = 0;
19032let prefersSlot3 = 1;
19033}
19034def S2_cl1p : HInst<
19035(outs IntRegs:$Rd32),
19036(ins DoubleRegs:$Rss32),
19037"$Rd32 = cl1($Rss32)",
19038tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19039let Inst{13-5} = 0b000000100;
19040let Inst{31-21} = 0b10001000010;
19041let hasNewValue = 1;
19042let opNewValue = 0;
19043let prefersSlot3 = 1;
19044}
19045def S2_clb : HInst<
19046(outs IntRegs:$Rd32),
19047(ins IntRegs:$Rs32),
19048"$Rd32 = clb($Rs32)",
19049tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19050let Inst{13-5} = 0b000000100;
19051let Inst{31-21} = 0b10001100000;
19052let hasNewValue = 1;
19053let opNewValue = 0;
19054let prefersSlot3 = 1;
19055}
19056def S2_clbnorm : HInst<
19057(outs IntRegs:$Rd32),
19058(ins IntRegs:$Rs32),
19059"$Rd32 = normamt($Rs32)",
19060tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19061let Inst{13-5} = 0b000000111;
19062let Inst{31-21} = 0b10001100000;
19063let hasNewValue = 1;
19064let opNewValue = 0;
19065let prefersSlot3 = 1;
19066}
19067def S2_clbp : HInst<
19068(outs IntRegs:$Rd32),
19069(ins DoubleRegs:$Rss32),
19070"$Rd32 = clb($Rss32)",
19071tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19072let Inst{13-5} = 0b000000000;
19073let Inst{31-21} = 0b10001000010;
19074let hasNewValue = 1;
19075let opNewValue = 0;
19076let prefersSlot3 = 1;
19077}
19078def S2_clrbit_i : HInst<
19079(outs IntRegs:$Rd32),
19080(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19081"$Rd32 = clrbit($Rs32,#$Ii)",
19082tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19083let Inst{7-5} = 0b001;
19084let Inst{13-13} = 0b0;
19085let Inst{31-21} = 0b10001100110;
19086let hasNewValue = 1;
19087let opNewValue = 0;
19088}
19089def S2_clrbit_r : HInst<
19090(outs IntRegs:$Rd32),
19091(ins IntRegs:$Rs32, IntRegs:$Rt32),
19092"$Rd32 = clrbit($Rs32,$Rt32)",
19093tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19094let Inst{7-5} = 0b010;
19095let Inst{13-13} = 0b0;
19096let Inst{31-21} = 0b11000110100;
19097let hasNewValue = 1;
19098let opNewValue = 0;
19099}
19100def S2_ct0 : HInst<
19101(outs IntRegs:$Rd32),
19102(ins IntRegs:$Rs32),
19103"$Rd32 = ct0($Rs32)",
19104tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19105let Inst{13-5} = 0b000000100;
19106let Inst{31-21} = 0b10001100010;
19107let hasNewValue = 1;
19108let opNewValue = 0;
19109let prefersSlot3 = 1;
19110}
19111def S2_ct0p : HInst<
19112(outs IntRegs:$Rd32),
19113(ins DoubleRegs:$Rss32),
19114"$Rd32 = ct0($Rss32)",
19115tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19116let Inst{13-5} = 0b000000010;
19117let Inst{31-21} = 0b10001000111;
19118let hasNewValue = 1;
19119let opNewValue = 0;
19120let prefersSlot3 = 1;
19121}
19122def S2_ct1 : HInst<
19123(outs IntRegs:$Rd32),
19124(ins IntRegs:$Rs32),
19125"$Rd32 = ct1($Rs32)",
19126tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19127let Inst{13-5} = 0b000000101;
19128let Inst{31-21} = 0b10001100010;
19129let hasNewValue = 1;
19130let opNewValue = 0;
19131let prefersSlot3 = 1;
19132}
19133def S2_ct1p : HInst<
19134(outs IntRegs:$Rd32),
19135(ins DoubleRegs:$Rss32),
19136"$Rd32 = ct1($Rss32)",
19137tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19138let Inst{13-5} = 0b000000100;
19139let Inst{31-21} = 0b10001000111;
19140let hasNewValue = 1;
19141let opNewValue = 0;
19142let prefersSlot3 = 1;
19143}
19144def S2_deinterleave : HInst<
19145(outs DoubleRegs:$Rdd32),
19146(ins DoubleRegs:$Rss32),
19147"$Rdd32 = deinterleave($Rss32)",
19148tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19149let Inst{13-5} = 0b000000100;
19150let Inst{31-21} = 0b10000000110;
19151let prefersSlot3 = 1;
19152}
19153def S2_extractu : HInst<
19154(outs IntRegs:$Rd32),
19155(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19156"$Rd32 = extractu($Rs32,#$Ii,#$II)",
19157tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
19158let Inst{13-13} = 0b0;
19159let Inst{31-23} = 0b100011010;
19160let hasNewValue = 1;
19161let opNewValue = 0;
19162let prefersSlot3 = 1;
19163}
19164def S2_extractu_rp : HInst<
19165(outs IntRegs:$Rd32),
19166(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
19167"$Rd32 = extractu($Rs32,$Rtt32)",
19168tc_a08b630b, TypeS_3op>, Enc_e07374 {
19169let Inst{7-5} = 0b000;
19170let Inst{13-13} = 0b0;
19171let Inst{31-21} = 0b11001001000;
19172let hasNewValue = 1;
19173let opNewValue = 0;
19174let prefersSlot3 = 1;
19175}
19176def S2_extractup : HInst<
19177(outs DoubleRegs:$Rdd32),
19178(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19179"$Rdd32 = extractu($Rss32,#$Ii,#$II)",
19180tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
19181let Inst{31-24} = 0b10000001;
19182let prefersSlot3 = 1;
19183}
19184def S2_extractup_rp : HInst<
19185(outs DoubleRegs:$Rdd32),
19186(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19187"$Rdd32 = extractu($Rss32,$Rtt32)",
19188tc_a08b630b, TypeS_3op>, Enc_a56825 {
19189let Inst{7-5} = 0b000;
19190let Inst{13-13} = 0b0;
19191let Inst{31-21} = 0b11000001000;
19192let prefersSlot3 = 1;
19193}
19194def S2_insert : HInst<
19195(outs IntRegs:$Rx32),
19196(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19197"$Rx32 = insert($Rs32,#$Ii,#$II)",
19198tc_bb831a7c, TypeS_2op>, Enc_a1e29d {
19199let Inst{13-13} = 0b0;
19200let Inst{31-23} = 0b100011110;
19201let hasNewValue = 1;
19202let opNewValue = 0;
19203let prefersSlot3 = 1;
19204let Constraints = "$Rx32 = $Rx32in";
19205}
19206def S2_insert_rp : HInst<
19207(outs IntRegs:$Rx32),
19208(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19209"$Rx32 = insert($Rs32,$Rtt32)",
19210tc_a4e22bbd, TypeS_3op>, Enc_179b35 {
19211let Inst{7-5} = 0b000;
19212let Inst{13-13} = 0b0;
19213let Inst{31-21} = 0b11001000000;
19214let hasNewValue = 1;
19215let opNewValue = 0;
19216let prefersSlot3 = 1;
19217let Constraints = "$Rx32 = $Rx32in";
19218}
19219def S2_insertp : HInst<
19220(outs DoubleRegs:$Rxx32),
19221(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19222"$Rxx32 = insert($Rss32,#$Ii,#$II)",
19223tc_bb831a7c, TypeS_2op>, Enc_143a3c {
19224let Inst{31-24} = 0b10000011;
19225let prefersSlot3 = 1;
19226let Constraints = "$Rxx32 = $Rxx32in";
19227}
19228def S2_insertp_rp : HInst<
19229(outs DoubleRegs:$Rxx32),
19230(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19231"$Rxx32 = insert($Rss32,$Rtt32)",
19232tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
19233let Inst{7-5} = 0b000;
19234let Inst{13-13} = 0b0;
19235let Inst{31-21} = 0b11001010000;
19236let prefersSlot3 = 1;
19237let Constraints = "$Rxx32 = $Rxx32in";
19238}
19239def S2_interleave : HInst<
19240(outs DoubleRegs:$Rdd32),
19241(ins DoubleRegs:$Rss32),
19242"$Rdd32 = interleave($Rss32)",
19243tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19244let Inst{13-5} = 0b000000101;
19245let Inst{31-21} = 0b10000000110;
19246let prefersSlot3 = 1;
19247}
19248def S2_lfsp : HInst<
19249(outs DoubleRegs:$Rdd32),
19250(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19251"$Rdd32 = lfs($Rss32,$Rtt32)",
19252tc_a08b630b, TypeS_3op>, Enc_a56825 {
19253let Inst{7-5} = 0b110;
19254let Inst{13-13} = 0b0;
19255let Inst{31-21} = 0b11000001100;
19256let prefersSlot3 = 1;
19257}
19258def S2_lsl_r_p : HInst<
19259(outs DoubleRegs:$Rdd32),
19260(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19261"$Rdd32 = lsl($Rss32,$Rt32)",
19262tc_5da50c4b, TypeS_3op>, Enc_927852 {
19263let Inst{7-5} = 0b110;
19264let Inst{13-13} = 0b0;
19265let Inst{31-21} = 0b11000011100;
19266}
19267def S2_lsl_r_p_acc : HInst<
19268(outs DoubleRegs:$Rxx32),
19269(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19270"$Rxx32 += lsl($Rss32,$Rt32)",
19271tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19272let Inst{7-5} = 0b110;
19273let Inst{13-13} = 0b0;
19274let Inst{31-21} = 0b11001011110;
19275let prefersSlot3 = 1;
19276let Constraints = "$Rxx32 = $Rxx32in";
19277}
19278def S2_lsl_r_p_and : HInst<
19279(outs DoubleRegs:$Rxx32),
19280(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19281"$Rxx32 &= lsl($Rss32,$Rt32)",
19282tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19283let Inst{7-5} = 0b110;
19284let Inst{13-13} = 0b0;
19285let Inst{31-21} = 0b11001011010;
19286let prefersSlot3 = 1;
19287let Constraints = "$Rxx32 = $Rxx32in";
19288}
19289def S2_lsl_r_p_nac : HInst<
19290(outs DoubleRegs:$Rxx32),
19291(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19292"$Rxx32 -= lsl($Rss32,$Rt32)",
19293tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19294let Inst{7-5} = 0b110;
19295let Inst{13-13} = 0b0;
19296let Inst{31-21} = 0b11001011100;
19297let prefersSlot3 = 1;
19298let Constraints = "$Rxx32 = $Rxx32in";
19299}
19300def S2_lsl_r_p_or : HInst<
19301(outs DoubleRegs:$Rxx32),
19302(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19303"$Rxx32 |= lsl($Rss32,$Rt32)",
19304tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19305let Inst{7-5} = 0b110;
19306let Inst{13-13} = 0b0;
19307let Inst{31-21} = 0b11001011000;
19308let prefersSlot3 = 1;
19309let Constraints = "$Rxx32 = $Rxx32in";
19310}
19311def S2_lsl_r_p_xor : HInst<
19312(outs DoubleRegs:$Rxx32),
19313(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19314"$Rxx32 ^= lsl($Rss32,$Rt32)",
19315tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19316let Inst{7-5} = 0b110;
19317let Inst{13-13} = 0b0;
19318let Inst{31-21} = 0b11001011011;
19319let prefersSlot3 = 1;
19320let Constraints = "$Rxx32 = $Rxx32in";
19321}
19322def S2_lsl_r_r : HInst<
19323(outs IntRegs:$Rd32),
19324(ins IntRegs:$Rs32, IntRegs:$Rt32),
19325"$Rd32 = lsl($Rs32,$Rt32)",
19326tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19327let Inst{7-5} = 0b110;
19328let Inst{13-13} = 0b0;
19329let Inst{31-21} = 0b11000110010;
19330let hasNewValue = 1;
19331let opNewValue = 0;
19332}
19333def S2_lsl_r_r_acc : HInst<
19334(outs IntRegs:$Rx32),
19335(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19336"$Rx32 += lsl($Rs32,$Rt32)",
19337tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19338let Inst{7-5} = 0b110;
19339let Inst{13-13} = 0b0;
19340let Inst{31-21} = 0b11001100110;
19341let hasNewValue = 1;
19342let opNewValue = 0;
19343let prefersSlot3 = 1;
19344let Constraints = "$Rx32 = $Rx32in";
19345}
19346def S2_lsl_r_r_and : HInst<
19347(outs IntRegs:$Rx32),
19348(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19349"$Rx32 &= lsl($Rs32,$Rt32)",
19350tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19351let Inst{7-5} = 0b110;
19352let Inst{13-13} = 0b0;
19353let Inst{31-21} = 0b11001100010;
19354let hasNewValue = 1;
19355let opNewValue = 0;
19356let prefersSlot3 = 1;
19357let Constraints = "$Rx32 = $Rx32in";
19358}
19359def S2_lsl_r_r_nac : HInst<
19360(outs IntRegs:$Rx32),
19361(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19362"$Rx32 -= lsl($Rs32,$Rt32)",
19363tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19364let Inst{7-5} = 0b110;
19365let Inst{13-13} = 0b0;
19366let Inst{31-21} = 0b11001100100;
19367let hasNewValue = 1;
19368let opNewValue = 0;
19369let prefersSlot3 = 1;
19370let Constraints = "$Rx32 = $Rx32in";
19371}
19372def S2_lsl_r_r_or : HInst<
19373(outs IntRegs:$Rx32),
19374(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19375"$Rx32 |= lsl($Rs32,$Rt32)",
19376tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19377let Inst{7-5} = 0b110;
19378let Inst{13-13} = 0b0;
19379let Inst{31-21} = 0b11001100000;
19380let hasNewValue = 1;
19381let opNewValue = 0;
19382let prefersSlot3 = 1;
19383let Constraints = "$Rx32 = $Rx32in";
19384}
19385def S2_lsl_r_vh : HInst<
19386(outs DoubleRegs:$Rdd32),
19387(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19388"$Rdd32 = vlslh($Rss32,$Rt32)",
19389tc_5da50c4b, TypeS_3op>, Enc_927852 {
19390let Inst{7-5} = 0b110;
19391let Inst{13-13} = 0b0;
19392let Inst{31-21} = 0b11000011010;
19393}
19394def S2_lsl_r_vw : HInst<
19395(outs DoubleRegs:$Rdd32),
19396(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19397"$Rdd32 = vlslw($Rss32,$Rt32)",
19398tc_5da50c4b, TypeS_3op>, Enc_927852 {
19399let Inst{7-5} = 0b110;
19400let Inst{13-13} = 0b0;
19401let Inst{31-21} = 0b11000011000;
19402}
19403def S2_lsr_i_p : HInst<
19404(outs DoubleRegs:$Rdd32),
19405(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
19406"$Rdd32 = lsr($Rss32,#$Ii)",
19407tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
19408let Inst{7-5} = 0b001;
19409let Inst{31-21} = 0b10000000000;
19410}
19411def S2_lsr_i_p_acc : HInst<
19412(outs DoubleRegs:$Rxx32),
19413(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19414"$Rxx32 += lsr($Rss32,#$Ii)",
19415tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19416let Inst{7-5} = 0b101;
19417let Inst{31-21} = 0b10000010000;
19418let prefersSlot3 = 1;
19419let Constraints = "$Rxx32 = $Rxx32in";
19420}
19421def S2_lsr_i_p_and : HInst<
19422(outs DoubleRegs:$Rxx32),
19423(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19424"$Rxx32 &= lsr($Rss32,#$Ii)",
19425tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19426let Inst{7-5} = 0b001;
19427let Inst{31-21} = 0b10000010010;
19428let prefersSlot3 = 1;
19429let Constraints = "$Rxx32 = $Rxx32in";
19430}
19431def S2_lsr_i_p_nac : HInst<
19432(outs DoubleRegs:$Rxx32),
19433(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19434"$Rxx32 -= lsr($Rss32,#$Ii)",
19435tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19436let Inst{7-5} = 0b001;
19437let Inst{31-21} = 0b10000010000;
19438let prefersSlot3 = 1;
19439let Constraints = "$Rxx32 = $Rxx32in";
19440}
19441def S2_lsr_i_p_or : HInst<
19442(outs DoubleRegs:$Rxx32),
19443(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19444"$Rxx32 |= lsr($Rss32,#$Ii)",
19445tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19446let Inst{7-5} = 0b101;
19447let Inst{31-21} = 0b10000010010;
19448let prefersSlot3 = 1;
19449let Constraints = "$Rxx32 = $Rxx32in";
19450}
19451def S2_lsr_i_p_xacc : HInst<
19452(outs DoubleRegs:$Rxx32),
19453(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19454"$Rxx32 ^= lsr($Rss32,#$Ii)",
19455tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19456let Inst{7-5} = 0b001;
19457let Inst{31-21} = 0b10000010100;
19458let prefersSlot3 = 1;
19459let Constraints = "$Rxx32 = $Rxx32in";
19460}
19461def S2_lsr_i_r : HInst<
19462(outs IntRegs:$Rd32),
19463(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19464"$Rd32 = lsr($Rs32,#$Ii)",
19465tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19466let Inst{7-5} = 0b001;
19467let Inst{13-13} = 0b0;
19468let Inst{31-21} = 0b10001100000;
19469let hasNewValue = 1;
19470let opNewValue = 0;
19471}
19472def S2_lsr_i_r_acc : HInst<
19473(outs IntRegs:$Rx32),
19474(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19475"$Rx32 += lsr($Rs32,#$Ii)",
19476tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19477let Inst{7-5} = 0b101;
19478let Inst{13-13} = 0b0;
19479let Inst{31-21} = 0b10001110000;
19480let hasNewValue = 1;
19481let opNewValue = 0;
19482let prefersSlot3 = 1;
19483let Constraints = "$Rx32 = $Rx32in";
19484}
19485def S2_lsr_i_r_and : HInst<
19486(outs IntRegs:$Rx32),
19487(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19488"$Rx32 &= lsr($Rs32,#$Ii)",
19489tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19490let Inst{7-5} = 0b001;
19491let Inst{13-13} = 0b0;
19492let Inst{31-21} = 0b10001110010;
19493let hasNewValue = 1;
19494let opNewValue = 0;
19495let prefersSlot3 = 1;
19496let Constraints = "$Rx32 = $Rx32in";
19497}
19498def S2_lsr_i_r_nac : HInst<
19499(outs IntRegs:$Rx32),
19500(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19501"$Rx32 -= lsr($Rs32,#$Ii)",
19502tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19503let Inst{7-5} = 0b001;
19504let Inst{13-13} = 0b0;
19505let Inst{31-21} = 0b10001110000;
19506let hasNewValue = 1;
19507let opNewValue = 0;
19508let prefersSlot3 = 1;
19509let Constraints = "$Rx32 = $Rx32in";
19510}
19511def S2_lsr_i_r_or : HInst<
19512(outs IntRegs:$Rx32),
19513(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19514"$Rx32 |= lsr($Rs32,#$Ii)",
19515tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19516let Inst{7-5} = 0b101;
19517let Inst{13-13} = 0b0;
19518let Inst{31-21} = 0b10001110010;
19519let hasNewValue = 1;
19520let opNewValue = 0;
19521let prefersSlot3 = 1;
19522let Constraints = "$Rx32 = $Rx32in";
19523}
19524def S2_lsr_i_r_xacc : HInst<
19525(outs IntRegs:$Rx32),
19526(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19527"$Rx32 ^= lsr($Rs32,#$Ii)",
19528tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19529let Inst{7-5} = 0b001;
19530let Inst{13-13} = 0b0;
19531let Inst{31-21} = 0b10001110100;
19532let hasNewValue = 1;
19533let opNewValue = 0;
19534let prefersSlot3 = 1;
19535let Constraints = "$Rx32 = $Rx32in";
19536}
19537def S2_lsr_i_vh : HInst<
19538(outs DoubleRegs:$Rdd32),
19539(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
19540"$Rdd32 = vlsrh($Rss32,#$Ii)",
19541tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
19542let Inst{7-5} = 0b001;
19543let Inst{13-12} = 0b00;
19544let Inst{31-21} = 0b10000000100;
19545}
19546def S2_lsr_i_vw : HInst<
19547(outs DoubleRegs:$Rdd32),
19548(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
19549"$Rdd32 = vlsrw($Rss32,#$Ii)",
19550tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
19551let Inst{7-5} = 0b001;
19552let Inst{13-13} = 0b0;
19553let Inst{31-21} = 0b10000000010;
19554}
19555def S2_lsr_r_p : HInst<
19556(outs DoubleRegs:$Rdd32),
19557(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19558"$Rdd32 = lsr($Rss32,$Rt32)",
19559tc_5da50c4b, TypeS_3op>, Enc_927852 {
19560let Inst{7-5} = 0b010;
19561let Inst{13-13} = 0b0;
19562let Inst{31-21} = 0b11000011100;
19563}
19564def S2_lsr_r_p_acc : HInst<
19565(outs DoubleRegs:$Rxx32),
19566(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19567"$Rxx32 += lsr($Rss32,$Rt32)",
19568tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19569let Inst{7-5} = 0b010;
19570let Inst{13-13} = 0b0;
19571let Inst{31-21} = 0b11001011110;
19572let prefersSlot3 = 1;
19573let Constraints = "$Rxx32 = $Rxx32in";
19574}
19575def S2_lsr_r_p_and : HInst<
19576(outs DoubleRegs:$Rxx32),
19577(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19578"$Rxx32 &= lsr($Rss32,$Rt32)",
19579tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19580let Inst{7-5} = 0b010;
19581let Inst{13-13} = 0b0;
19582let Inst{31-21} = 0b11001011010;
19583let prefersSlot3 = 1;
19584let Constraints = "$Rxx32 = $Rxx32in";
19585}
19586def S2_lsr_r_p_nac : HInst<
19587(outs DoubleRegs:$Rxx32),
19588(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19589"$Rxx32 -= lsr($Rss32,$Rt32)",
19590tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19591let Inst{7-5} = 0b010;
19592let Inst{13-13} = 0b0;
19593let Inst{31-21} = 0b11001011100;
19594let prefersSlot3 = 1;
19595let Constraints = "$Rxx32 = $Rxx32in";
19596}
19597def S2_lsr_r_p_or : HInst<
19598(outs DoubleRegs:$Rxx32),
19599(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19600"$Rxx32 |= lsr($Rss32,$Rt32)",
19601tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19602let Inst{7-5} = 0b010;
19603let Inst{13-13} = 0b0;
19604let Inst{31-21} = 0b11001011000;
19605let prefersSlot3 = 1;
19606let Constraints = "$Rxx32 = $Rxx32in";
19607}
19608def S2_lsr_r_p_xor : HInst<
19609(outs DoubleRegs:$Rxx32),
19610(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19611"$Rxx32 ^= lsr($Rss32,$Rt32)",
19612tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19613let Inst{7-5} = 0b010;
19614let Inst{13-13} = 0b0;
19615let Inst{31-21} = 0b11001011011;
19616let prefersSlot3 = 1;
19617let Constraints = "$Rxx32 = $Rxx32in";
19618}
19619def S2_lsr_r_r : HInst<
19620(outs IntRegs:$Rd32),
19621(ins IntRegs:$Rs32, IntRegs:$Rt32),
19622"$Rd32 = lsr($Rs32,$Rt32)",
19623tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19624let Inst{7-5} = 0b010;
19625let Inst{13-13} = 0b0;
19626let Inst{31-21} = 0b11000110010;
19627let hasNewValue = 1;
19628let opNewValue = 0;
19629}
19630def S2_lsr_r_r_acc : HInst<
19631(outs IntRegs:$Rx32),
19632(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19633"$Rx32 += lsr($Rs32,$Rt32)",
19634tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19635let Inst{7-5} = 0b010;
19636let Inst{13-13} = 0b0;
19637let Inst{31-21} = 0b11001100110;
19638let hasNewValue = 1;
19639let opNewValue = 0;
19640let prefersSlot3 = 1;
19641let Constraints = "$Rx32 = $Rx32in";
19642}
19643def S2_lsr_r_r_and : HInst<
19644(outs IntRegs:$Rx32),
19645(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19646"$Rx32 &= lsr($Rs32,$Rt32)",
19647tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19648let Inst{7-5} = 0b010;
19649let Inst{13-13} = 0b0;
19650let Inst{31-21} = 0b11001100010;
19651let hasNewValue = 1;
19652let opNewValue = 0;
19653let prefersSlot3 = 1;
19654let Constraints = "$Rx32 = $Rx32in";
19655}
19656def S2_lsr_r_r_nac : HInst<
19657(outs IntRegs:$Rx32),
19658(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19659"$Rx32 -= lsr($Rs32,$Rt32)",
19660tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19661let Inst{7-5} = 0b010;
19662let Inst{13-13} = 0b0;
19663let Inst{31-21} = 0b11001100100;
19664let hasNewValue = 1;
19665let opNewValue = 0;
19666let prefersSlot3 = 1;
19667let Constraints = "$Rx32 = $Rx32in";
19668}
19669def S2_lsr_r_r_or : HInst<
19670(outs IntRegs:$Rx32),
19671(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19672"$Rx32 |= lsr($Rs32,$Rt32)",
19673tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19674let Inst{7-5} = 0b010;
19675let Inst{13-13} = 0b0;
19676let Inst{31-21} = 0b11001100000;
19677let hasNewValue = 1;
19678let opNewValue = 0;
19679let prefersSlot3 = 1;
19680let Constraints = "$Rx32 = $Rx32in";
19681}
19682def S2_lsr_r_vh : HInst<
19683(outs DoubleRegs:$Rdd32),
19684(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19685"$Rdd32 = vlsrh($Rss32,$Rt32)",
19686tc_5da50c4b, TypeS_3op>, Enc_927852 {
19687let Inst{7-5} = 0b010;
19688let Inst{13-13} = 0b0;
19689let Inst{31-21} = 0b11000011010;
19690}
19691def S2_lsr_r_vw : HInst<
19692(outs DoubleRegs:$Rdd32),
19693(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19694"$Rdd32 = vlsrw($Rss32,$Rt32)",
19695tc_5da50c4b, TypeS_3op>, Enc_927852 {
19696let Inst{7-5} = 0b010;
19697let Inst{13-13} = 0b0;
19698let Inst{31-21} = 0b11000011000;
19699}
19700def S2_mask : HInst<
19701(outs IntRegs:$Rd32),
19702(ins u5_0Imm:$Ii, u5_0Imm:$II),
19703"$Rd32 = mask(#$Ii,#$II)",
19704tc_1fcb8495, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> {
19705let Inst{13-13} = 0b1;
19706let Inst{20-16} = 0b00000;
19707let Inst{31-23} = 0b100011010;
19708let hasNewValue = 1;
19709let opNewValue = 0;
19710let prefersSlot3 = 1;
19711}
19712def S2_packhl : HInst<
19713(outs DoubleRegs:$Rdd32),
19714(ins IntRegs:$Rs32, IntRegs:$Rt32),
19715"$Rdd32 = packhl($Rs32,$Rt32)",
19716tc_713b66bf, TypeALU32_3op>, Enc_be32a5 {
19717let Inst{7-5} = 0b000;
19718let Inst{13-13} = 0b0;
19719let Inst{31-21} = 0b11110101100;
19720let InputType = "reg";
19721}
19722def S2_parityp : HInst<
19723(outs IntRegs:$Rd32),
19724(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19725"$Rd32 = parity($Rss32,$Rtt32)",
19726tc_a08b630b, TypeALU64>, Enc_d2216a {
19727let Inst{7-5} = 0b000;
19728let Inst{13-13} = 0b0;
19729let Inst{31-21} = 0b11010000000;
19730let hasNewValue = 1;
19731let opNewValue = 0;
19732let prefersSlot3 = 1;
19733}
19734def S2_pstorerbf_io : HInst<
19735(outs),
19736(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19737"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
19738tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19739let Inst{2-2} = 0b0;
19740let Inst{31-21} = 0b01000100000;
19741let isPredicated = 1;
19742let isPredicatedFalse = 1;
19743let addrMode = BaseImmOffset;
19744let accessSize = ByteAccess;
19745let mayStore = 1;
19746let BaseOpcode = "S2_storerb_io";
19747let CextOpcode = "S2_storerb";
19748let InputType = "imm";
19749let isNVStorable = 1;
19750let isExtendable = 1;
19751let opExtendable = 2;
19752let isExtentSigned = 0;
19753let opExtentBits = 6;
19754let opExtentAlign = 0;
19755}
19756def S2_pstorerbf_pi : HInst<
19757(outs IntRegs:$Rx32),
19758(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19759"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
19760tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19761let Inst{2-2} = 0b1;
19762let Inst{7-7} = 0b0;
19763let Inst{13-13} = 0b1;
19764let Inst{31-21} = 0b10101011000;
19765let isPredicated = 1;
19766let isPredicatedFalse = 1;
19767let addrMode = PostInc;
19768let accessSize = ByteAccess;
19769let mayStore = 1;
19770let BaseOpcode = "S2_storerb_pi";
19771let isNVStorable = 1;
19772let Constraints = "$Rx32 = $Rx32in";
19773}
19774def S2_pstorerbf_zomap : HInst<
19775(outs),
19776(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19777"if (!$Pv4) memb($Rs32) = $Rt32",
19778tc_8035e91f, TypeMAPPING> {
19779let isPseudo = 1;
19780let isCodeGenOnly = 1;
19781}
19782def S2_pstorerbfnew_pi : HInst<
19783(outs IntRegs:$Rx32),
19784(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19785"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19786tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19787let Inst{2-2} = 0b1;
19788let Inst{7-7} = 0b1;
19789let Inst{13-13} = 0b1;
19790let Inst{31-21} = 0b10101011000;
19791let isPredicated = 1;
19792let isPredicatedFalse = 1;
19793let addrMode = PostInc;
19794let accessSize = ByteAccess;
19795let isPredicatedNew = 1;
19796let mayStore = 1;
19797let BaseOpcode = "S2_storerb_pi";
19798let isNVStorable = 1;
19799let Constraints = "$Rx32 = $Rx32in";
19800}
19801def S2_pstorerbnewf_io : HInst<
19802(outs),
19803(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19804"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19805tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19806let Inst{2-2} = 0b0;
19807let Inst{12-11} = 0b00;
19808let Inst{31-21} = 0b01000100101;
19809let isPredicated = 1;
19810let isPredicatedFalse = 1;
19811let addrMode = BaseImmOffset;
19812let accessSize = ByteAccess;
19813let isNVStore = 1;
19814let isNewValue = 1;
19815let isRestrictNoSlot1Store = 1;
19816let mayStore = 1;
19817let BaseOpcode = "S2_storerb_io";
19818let CextOpcode = "S2_storerb";
19819let InputType = "imm";
19820let isExtendable = 1;
19821let opExtendable = 2;
19822let isExtentSigned = 0;
19823let opExtentBits = 6;
19824let opExtentAlign = 0;
19825let opNewValue = 3;
19826}
19827def S2_pstorerbnewf_pi : HInst<
19828(outs IntRegs:$Rx32),
19829(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19830"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19831tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19832let Inst{2-2} = 0b1;
19833let Inst{7-7} = 0b0;
19834let Inst{13-11} = 0b100;
19835let Inst{31-21} = 0b10101011101;
19836let isPredicated = 1;
19837let isPredicatedFalse = 1;
19838let addrMode = PostInc;
19839let accessSize = ByteAccess;
19840let isNVStore = 1;
19841let isNewValue = 1;
19842let isRestrictNoSlot1Store = 1;
19843let mayStore = 1;
19844let BaseOpcode = "S2_storerb_pi";
19845let CextOpcode = "S2_storerb";
19846let opNewValue = 4;
19847let Constraints = "$Rx32 = $Rx32in";
19848}
19849def S2_pstorerbnewf_zomap : HInst<
19850(outs),
19851(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19852"if (!$Pv4) memb($Rs32) = $Nt8.new",
19853tc_011e0e9d, TypeMAPPING> {
19854let isPseudo = 1;
19855let isCodeGenOnly = 1;
19856let opNewValue = 2;
19857}
19858def S2_pstorerbnewfnew_pi : HInst<
19859(outs IntRegs:$Rx32),
19860(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19861"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19862tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19863let Inst{2-2} = 0b1;
19864let Inst{7-7} = 0b1;
19865let Inst{13-11} = 0b100;
19866let Inst{31-21} = 0b10101011101;
19867let isPredicated = 1;
19868let isPredicatedFalse = 1;
19869let addrMode = PostInc;
19870let accessSize = ByteAccess;
19871let isNVStore = 1;
19872let isPredicatedNew = 1;
19873let isNewValue = 1;
19874let isRestrictNoSlot1Store = 1;
19875let mayStore = 1;
19876let BaseOpcode = "S2_storerb_pi";
19877let CextOpcode = "S2_storerb";
19878let opNewValue = 4;
19879let Constraints = "$Rx32 = $Rx32in";
19880}
19881def S2_pstorerbnewt_io : HInst<
19882(outs),
19883(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19884"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19885tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19886let Inst{2-2} = 0b0;
19887let Inst{12-11} = 0b00;
19888let Inst{31-21} = 0b01000000101;
19889let isPredicated = 1;
19890let addrMode = BaseImmOffset;
19891let accessSize = ByteAccess;
19892let isNVStore = 1;
19893let isNewValue = 1;
19894let isRestrictNoSlot1Store = 1;
19895let mayStore = 1;
19896let BaseOpcode = "S2_storerb_io";
19897let CextOpcode = "S2_storerb";
19898let InputType = "imm";
19899let isExtendable = 1;
19900let opExtendable = 2;
19901let isExtentSigned = 0;
19902let opExtentBits = 6;
19903let opExtentAlign = 0;
19904let opNewValue = 3;
19905}
19906def S2_pstorerbnewt_pi : HInst<
19907(outs IntRegs:$Rx32),
19908(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19909"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19910tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19911let Inst{2-2} = 0b0;
19912let Inst{7-7} = 0b0;
19913let Inst{13-11} = 0b100;
19914let Inst{31-21} = 0b10101011101;
19915let isPredicated = 1;
19916let addrMode = PostInc;
19917let accessSize = ByteAccess;
19918let isNVStore = 1;
19919let isNewValue = 1;
19920let isRestrictNoSlot1Store = 1;
19921let mayStore = 1;
19922let BaseOpcode = "S2_storerb_pi";
19923let CextOpcode = "S2_storerb";
19924let opNewValue = 4;
19925let Constraints = "$Rx32 = $Rx32in";
19926}
19927def S2_pstorerbnewt_zomap : HInst<
19928(outs),
19929(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19930"if ($Pv4) memb($Rs32) = $Nt8.new",
19931tc_011e0e9d, TypeMAPPING> {
19932let isPseudo = 1;
19933let isCodeGenOnly = 1;
19934let opNewValue = 2;
19935}
19936def S2_pstorerbnewtnew_pi : HInst<
19937(outs IntRegs:$Rx32),
19938(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19939"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19940tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19941let Inst{2-2} = 0b0;
19942let Inst{7-7} = 0b1;
19943let Inst{13-11} = 0b100;
19944let Inst{31-21} = 0b10101011101;
19945let isPredicated = 1;
19946let addrMode = PostInc;
19947let accessSize = ByteAccess;
19948let isNVStore = 1;
19949let isPredicatedNew = 1;
19950let isNewValue = 1;
19951let isRestrictNoSlot1Store = 1;
19952let mayStore = 1;
19953let BaseOpcode = "S2_storerb_pi";
19954let CextOpcode = "S2_storerb";
19955let opNewValue = 4;
19956let Constraints = "$Rx32 = $Rx32in";
19957}
19958def S2_pstorerbt_io : HInst<
19959(outs),
19960(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19961"if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
19962tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19963let Inst{2-2} = 0b0;
19964let Inst{31-21} = 0b01000000000;
19965let isPredicated = 1;
19966let addrMode = BaseImmOffset;
19967let accessSize = ByteAccess;
19968let mayStore = 1;
19969let BaseOpcode = "S2_storerb_io";
19970let CextOpcode = "S2_storerb";
19971let InputType = "imm";
19972let isNVStorable = 1;
19973let isExtendable = 1;
19974let opExtendable = 2;
19975let isExtentSigned = 0;
19976let opExtentBits = 6;
19977let opExtentAlign = 0;
19978}
19979def S2_pstorerbt_pi : HInst<
19980(outs IntRegs:$Rx32),
19981(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19982"if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
19983tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19984let Inst{2-2} = 0b0;
19985let Inst{7-7} = 0b0;
19986let Inst{13-13} = 0b1;
19987let Inst{31-21} = 0b10101011000;
19988let isPredicated = 1;
19989let addrMode = PostInc;
19990let accessSize = ByteAccess;
19991let mayStore = 1;
19992let BaseOpcode = "S2_storerb_pi";
19993let isNVStorable = 1;
19994let Constraints = "$Rx32 = $Rx32in";
19995}
19996def S2_pstorerbt_zomap : HInst<
19997(outs),
19998(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19999"if ($Pv4) memb($Rs32) = $Rt32",
20000tc_8035e91f, TypeMAPPING> {
20001let isPseudo = 1;
20002let isCodeGenOnly = 1;
20003}
20004def S2_pstorerbtnew_pi : HInst<
20005(outs IntRegs:$Rx32),
20006(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20007"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
20008tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
20009let Inst{2-2} = 0b0;
20010let Inst{7-7} = 0b1;
20011let Inst{13-13} = 0b1;
20012let Inst{31-21} = 0b10101011000;
20013let isPredicated = 1;
20014let addrMode = PostInc;
20015let accessSize = ByteAccess;
20016let isPredicatedNew = 1;
20017let mayStore = 1;
20018let BaseOpcode = "S2_storerb_pi";
20019let isNVStorable = 1;
20020let Constraints = "$Rx32 = $Rx32in";
20021}
20022def S2_pstorerdf_io : HInst<
20023(outs),
20024(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20025"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
20026tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20027let Inst{2-2} = 0b0;
20028let Inst{31-21} = 0b01000100110;
20029let isPredicated = 1;
20030let isPredicatedFalse = 1;
20031let addrMode = BaseImmOffset;
20032let accessSize = DoubleWordAccess;
20033let mayStore = 1;
20034let BaseOpcode = "S2_storerd_io";
20035let CextOpcode = "S2_storerd";
20036let InputType = "imm";
20037let isExtendable = 1;
20038let opExtendable = 2;
20039let isExtentSigned = 0;
20040let opExtentBits = 9;
20041let opExtentAlign = 3;
20042}
20043def S2_pstorerdf_pi : HInst<
20044(outs IntRegs:$Rx32),
20045(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20046"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
20047tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20048let Inst{2-2} = 0b1;
20049let Inst{7-7} = 0b0;
20050let Inst{13-13} = 0b1;
20051let Inst{31-21} = 0b10101011110;
20052let isPredicated = 1;
20053let isPredicatedFalse = 1;
20054let addrMode = PostInc;
20055let accessSize = DoubleWordAccess;
20056let mayStore = 1;
20057let BaseOpcode = "S2_storerd_pi";
20058let CextOpcode = "S2_storerd";
20059let Constraints = "$Rx32 = $Rx32in";
20060}
20061def S2_pstorerdf_zomap : HInst<
20062(outs),
20063(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20064"if (!$Pv4) memd($Rs32) = $Rtt32",
20065tc_8035e91f, TypeMAPPING> {
20066let isPseudo = 1;
20067let isCodeGenOnly = 1;
20068}
20069def S2_pstorerdfnew_pi : HInst<
20070(outs IntRegs:$Rx32),
20071(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20072"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20073tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20074let Inst{2-2} = 0b1;
20075let Inst{7-7} = 0b1;
20076let Inst{13-13} = 0b1;
20077let Inst{31-21} = 0b10101011110;
20078let isPredicated = 1;
20079let isPredicatedFalse = 1;
20080let addrMode = PostInc;
20081let accessSize = DoubleWordAccess;
20082let isPredicatedNew = 1;
20083let mayStore = 1;
20084let BaseOpcode = "S2_storerd_pi";
20085let CextOpcode = "S2_storerd";
20086let Constraints = "$Rx32 = $Rx32in";
20087}
20088def S2_pstorerdt_io : HInst<
20089(outs),
20090(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20091"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
20092tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20093let Inst{2-2} = 0b0;
20094let Inst{31-21} = 0b01000000110;
20095let isPredicated = 1;
20096let addrMode = BaseImmOffset;
20097let accessSize = DoubleWordAccess;
20098let mayStore = 1;
20099let BaseOpcode = "S2_storerd_io";
20100let CextOpcode = "S2_storerd";
20101let InputType = "imm";
20102let isExtendable = 1;
20103let opExtendable = 2;
20104let isExtentSigned = 0;
20105let opExtentBits = 9;
20106let opExtentAlign = 3;
20107}
20108def S2_pstorerdt_pi : HInst<
20109(outs IntRegs:$Rx32),
20110(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20111"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
20112tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20113let Inst{2-2} = 0b0;
20114let Inst{7-7} = 0b0;
20115let Inst{13-13} = 0b1;
20116let Inst{31-21} = 0b10101011110;
20117let isPredicated = 1;
20118let addrMode = PostInc;
20119let accessSize = DoubleWordAccess;
20120let mayStore = 1;
20121let BaseOpcode = "S2_storerd_pi";
20122let CextOpcode = "S2_storerd";
20123let Constraints = "$Rx32 = $Rx32in";
20124}
20125def S2_pstorerdt_zomap : HInst<
20126(outs),
20127(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20128"if ($Pv4) memd($Rs32) = $Rtt32",
20129tc_8035e91f, TypeMAPPING> {
20130let isPseudo = 1;
20131let isCodeGenOnly = 1;
20132}
20133def S2_pstorerdtnew_pi : HInst<
20134(outs IntRegs:$Rx32),
20135(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20136"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20137tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20138let Inst{2-2} = 0b0;
20139let Inst{7-7} = 0b1;
20140let Inst{13-13} = 0b1;
20141let Inst{31-21} = 0b10101011110;
20142let isPredicated = 1;
20143let addrMode = PostInc;
20144let accessSize = DoubleWordAccess;
20145let isPredicatedNew = 1;
20146let mayStore = 1;
20147let BaseOpcode = "S2_storerd_pi";
20148let CextOpcode = "S2_storerd";
20149let Constraints = "$Rx32 = $Rx32in";
20150}
20151def S2_pstorerff_io : HInst<
20152(outs),
20153(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20154"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20155tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20156let Inst{2-2} = 0b0;
20157let Inst{31-21} = 0b01000100011;
20158let isPredicated = 1;
20159let isPredicatedFalse = 1;
20160let addrMode = BaseImmOffset;
20161let accessSize = HalfWordAccess;
20162let mayStore = 1;
20163let BaseOpcode = "S2_storerf_io";
20164let CextOpcode = "S2_storerf";
20165let InputType = "imm";
20166let isExtendable = 1;
20167let opExtendable = 2;
20168let isExtentSigned = 0;
20169let opExtentBits = 7;
20170let opExtentAlign = 1;
20171}
20172def S2_pstorerff_pi : HInst<
20173(outs IntRegs:$Rx32),
20174(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20175"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20176tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20177let Inst{2-2} = 0b1;
20178let Inst{7-7} = 0b0;
20179let Inst{13-13} = 0b1;
20180let Inst{31-21} = 0b10101011011;
20181let isPredicated = 1;
20182let isPredicatedFalse = 1;
20183let addrMode = PostInc;
20184let accessSize = HalfWordAccess;
20185let mayStore = 1;
20186let BaseOpcode = "S2_storerf_pi";
20187let CextOpcode = "S2_storerf";
20188let Constraints = "$Rx32 = $Rx32in";
20189}
20190def S2_pstorerff_zomap : HInst<
20191(outs),
20192(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20193"if (!$Pv4) memh($Rs32) = $Rt32.h",
20194tc_8035e91f, TypeMAPPING> {
20195let isPseudo = 1;
20196let isCodeGenOnly = 1;
20197}
20198def S2_pstorerffnew_pi : HInst<
20199(outs IntRegs:$Rx32),
20200(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20201"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20202tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20203let Inst{2-2} = 0b1;
20204let Inst{7-7} = 0b1;
20205let Inst{13-13} = 0b1;
20206let Inst{31-21} = 0b10101011011;
20207let isPredicated = 1;
20208let isPredicatedFalse = 1;
20209let addrMode = PostInc;
20210let accessSize = HalfWordAccess;
20211let isPredicatedNew = 1;
20212let mayStore = 1;
20213let BaseOpcode = "S2_storerf_pi";
20214let CextOpcode = "S2_storerf";
20215let Constraints = "$Rx32 = $Rx32in";
20216}
20217def S2_pstorerft_io : HInst<
20218(outs),
20219(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20220"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20221tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20222let Inst{2-2} = 0b0;
20223let Inst{31-21} = 0b01000000011;
20224let isPredicated = 1;
20225let addrMode = BaseImmOffset;
20226let accessSize = HalfWordAccess;
20227let mayStore = 1;
20228let BaseOpcode = "S2_storerf_io";
20229let CextOpcode = "S2_storerf";
20230let InputType = "imm";
20231let isExtendable = 1;
20232let opExtendable = 2;
20233let isExtentSigned = 0;
20234let opExtentBits = 7;
20235let opExtentAlign = 1;
20236}
20237def S2_pstorerft_pi : HInst<
20238(outs IntRegs:$Rx32),
20239(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20240"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20241tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20242let Inst{2-2} = 0b0;
20243let Inst{7-7} = 0b0;
20244let Inst{13-13} = 0b1;
20245let Inst{31-21} = 0b10101011011;
20246let isPredicated = 1;
20247let addrMode = PostInc;
20248let accessSize = HalfWordAccess;
20249let mayStore = 1;
20250let BaseOpcode = "S2_storerf_pi";
20251let CextOpcode = "S2_storerf";
20252let Constraints = "$Rx32 = $Rx32in";
20253}
20254def S2_pstorerft_zomap : HInst<
20255(outs),
20256(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20257"if ($Pv4) memh($Rs32) = $Rt32.h",
20258tc_8035e91f, TypeMAPPING> {
20259let isPseudo = 1;
20260let isCodeGenOnly = 1;
20261}
20262def S2_pstorerftnew_pi : HInst<
20263(outs IntRegs:$Rx32),
20264(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20265"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20266tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20267let Inst{2-2} = 0b0;
20268let Inst{7-7} = 0b1;
20269let Inst{13-13} = 0b1;
20270let Inst{31-21} = 0b10101011011;
20271let isPredicated = 1;
20272let addrMode = PostInc;
20273let accessSize = HalfWordAccess;
20274let isPredicatedNew = 1;
20275let mayStore = 1;
20276let BaseOpcode = "S2_storerf_pi";
20277let CextOpcode = "S2_storerf";
20278let Constraints = "$Rx32 = $Rx32in";
20279}
20280def S2_pstorerhf_io : HInst<
20281(outs),
20282(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20283"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
20284tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20285let Inst{2-2} = 0b0;
20286let Inst{31-21} = 0b01000100010;
20287let isPredicated = 1;
20288let isPredicatedFalse = 1;
20289let addrMode = BaseImmOffset;
20290let accessSize = HalfWordAccess;
20291let mayStore = 1;
20292let BaseOpcode = "S2_storerh_io";
20293let CextOpcode = "S2_storerh";
20294let InputType = "imm";
20295let isNVStorable = 1;
20296let isExtendable = 1;
20297let opExtendable = 2;
20298let isExtentSigned = 0;
20299let opExtentBits = 7;
20300let opExtentAlign = 1;
20301}
20302def S2_pstorerhf_pi : HInst<
20303(outs IntRegs:$Rx32),
20304(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20305"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
20306tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20307let Inst{2-2} = 0b1;
20308let Inst{7-7} = 0b0;
20309let Inst{13-13} = 0b1;
20310let Inst{31-21} = 0b10101011010;
20311let isPredicated = 1;
20312let isPredicatedFalse = 1;
20313let addrMode = PostInc;
20314let accessSize = HalfWordAccess;
20315let mayStore = 1;
20316let BaseOpcode = "S2_storerh_pi";
20317let isNVStorable = 1;
20318let Constraints = "$Rx32 = $Rx32in";
20319}
20320def S2_pstorerhf_zomap : HInst<
20321(outs),
20322(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20323"if (!$Pv4) memh($Rs32) = $Rt32",
20324tc_8035e91f, TypeMAPPING> {
20325let isPseudo = 1;
20326let isCodeGenOnly = 1;
20327}
20328def S2_pstorerhfnew_pi : HInst<
20329(outs IntRegs:$Rx32),
20330(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20331"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20332tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20333let Inst{2-2} = 0b1;
20334let Inst{7-7} = 0b1;
20335let Inst{13-13} = 0b1;
20336let Inst{31-21} = 0b10101011010;
20337let isPredicated = 1;
20338let isPredicatedFalse = 1;
20339let addrMode = PostInc;
20340let accessSize = HalfWordAccess;
20341let isPredicatedNew = 1;
20342let mayStore = 1;
20343let BaseOpcode = "S2_storerh_pi";
20344let isNVStorable = 1;
20345let Constraints = "$Rx32 = $Rx32in";
20346}
20347def S2_pstorerhnewf_io : HInst<
20348(outs),
20349(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20350"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20351tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20352let Inst{2-2} = 0b0;
20353let Inst{12-11} = 0b01;
20354let Inst{31-21} = 0b01000100101;
20355let isPredicated = 1;
20356let isPredicatedFalse = 1;
20357let addrMode = BaseImmOffset;
20358let accessSize = HalfWordAccess;
20359let isNVStore = 1;
20360let isNewValue = 1;
20361let isRestrictNoSlot1Store = 1;
20362let mayStore = 1;
20363let BaseOpcode = "S2_storerh_io";
20364let CextOpcode = "S2_storerh";
20365let InputType = "imm";
20366let isExtendable = 1;
20367let opExtendable = 2;
20368let isExtentSigned = 0;
20369let opExtentBits = 7;
20370let opExtentAlign = 1;
20371let opNewValue = 3;
20372}
20373def S2_pstorerhnewf_pi : HInst<
20374(outs IntRegs:$Rx32),
20375(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20376"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20377tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20378let Inst{2-2} = 0b1;
20379let Inst{7-7} = 0b0;
20380let Inst{13-11} = 0b101;
20381let Inst{31-21} = 0b10101011101;
20382let isPredicated = 1;
20383let isPredicatedFalse = 1;
20384let addrMode = PostInc;
20385let accessSize = HalfWordAccess;
20386let isNVStore = 1;
20387let isNewValue = 1;
20388let isRestrictNoSlot1Store = 1;
20389let mayStore = 1;
20390let BaseOpcode = "S2_storerh_pi";
20391let CextOpcode = "S2_storerh";
20392let opNewValue = 4;
20393let Constraints = "$Rx32 = $Rx32in";
20394}
20395def S2_pstorerhnewf_zomap : HInst<
20396(outs),
20397(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20398"if (!$Pv4) memh($Rs32) = $Nt8.new",
20399tc_011e0e9d, TypeMAPPING> {
20400let isPseudo = 1;
20401let isCodeGenOnly = 1;
20402let opNewValue = 2;
20403}
20404def S2_pstorerhnewfnew_pi : HInst<
20405(outs IntRegs:$Rx32),
20406(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20407"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20408tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20409let Inst{2-2} = 0b1;
20410let Inst{7-7} = 0b1;
20411let Inst{13-11} = 0b101;
20412let Inst{31-21} = 0b10101011101;
20413let isPredicated = 1;
20414let isPredicatedFalse = 1;
20415let addrMode = PostInc;
20416let accessSize = HalfWordAccess;
20417let isNVStore = 1;
20418let isPredicatedNew = 1;
20419let isNewValue = 1;
20420let isRestrictNoSlot1Store = 1;
20421let mayStore = 1;
20422let BaseOpcode = "S2_storerh_pi";
20423let CextOpcode = "S2_storerh";
20424let opNewValue = 4;
20425let Constraints = "$Rx32 = $Rx32in";
20426}
20427def S2_pstorerhnewt_io : HInst<
20428(outs),
20429(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20430"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20431tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20432let Inst{2-2} = 0b0;
20433let Inst{12-11} = 0b01;
20434let Inst{31-21} = 0b01000000101;
20435let isPredicated = 1;
20436let addrMode = BaseImmOffset;
20437let accessSize = HalfWordAccess;
20438let isNVStore = 1;
20439let isNewValue = 1;
20440let isRestrictNoSlot1Store = 1;
20441let mayStore = 1;
20442let BaseOpcode = "S2_storerh_io";
20443let CextOpcode = "S2_storerh";
20444let InputType = "imm";
20445let isExtendable = 1;
20446let opExtendable = 2;
20447let isExtentSigned = 0;
20448let opExtentBits = 7;
20449let opExtentAlign = 1;
20450let opNewValue = 3;
20451}
20452def S2_pstorerhnewt_pi : HInst<
20453(outs IntRegs:$Rx32),
20454(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20455"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20456tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20457let Inst{2-2} = 0b0;
20458let Inst{7-7} = 0b0;
20459let Inst{13-11} = 0b101;
20460let Inst{31-21} = 0b10101011101;
20461let isPredicated = 1;
20462let addrMode = PostInc;
20463let accessSize = HalfWordAccess;
20464let isNVStore = 1;
20465let isNewValue = 1;
20466let isRestrictNoSlot1Store = 1;
20467let mayStore = 1;
20468let BaseOpcode = "S2_storerh_pi";
20469let CextOpcode = "S2_storerh";
20470let opNewValue = 4;
20471let Constraints = "$Rx32 = $Rx32in";
20472}
20473def S2_pstorerhnewt_zomap : HInst<
20474(outs),
20475(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20476"if ($Pv4) memh($Rs32) = $Nt8.new",
20477tc_011e0e9d, TypeMAPPING> {
20478let isPseudo = 1;
20479let isCodeGenOnly = 1;
20480let opNewValue = 2;
20481}
20482def S2_pstorerhnewtnew_pi : HInst<
20483(outs IntRegs:$Rx32),
20484(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20485"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20486tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20487let Inst{2-2} = 0b0;
20488let Inst{7-7} = 0b1;
20489let Inst{13-11} = 0b101;
20490let Inst{31-21} = 0b10101011101;
20491let isPredicated = 1;
20492let addrMode = PostInc;
20493let accessSize = HalfWordAccess;
20494let isNVStore = 1;
20495let isPredicatedNew = 1;
20496let isNewValue = 1;
20497let isRestrictNoSlot1Store = 1;
20498let mayStore = 1;
20499let BaseOpcode = "S2_storerh_pi";
20500let CextOpcode = "S2_storerh";
20501let opNewValue = 4;
20502let Constraints = "$Rx32 = $Rx32in";
20503}
20504def S2_pstorerht_io : HInst<
20505(outs),
20506(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20507"if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
20508tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20509let Inst{2-2} = 0b0;
20510let Inst{31-21} = 0b01000000010;
20511let isPredicated = 1;
20512let addrMode = BaseImmOffset;
20513let accessSize = HalfWordAccess;
20514let mayStore = 1;
20515let BaseOpcode = "S2_storerh_io";
20516let CextOpcode = "S2_storerh";
20517let InputType = "imm";
20518let isNVStorable = 1;
20519let isExtendable = 1;
20520let opExtendable = 2;
20521let isExtentSigned = 0;
20522let opExtentBits = 7;
20523let opExtentAlign = 1;
20524}
20525def S2_pstorerht_pi : HInst<
20526(outs IntRegs:$Rx32),
20527(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20528"if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
20529tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20530let Inst{2-2} = 0b0;
20531let Inst{7-7} = 0b0;
20532let Inst{13-13} = 0b1;
20533let Inst{31-21} = 0b10101011010;
20534let isPredicated = 1;
20535let addrMode = PostInc;
20536let accessSize = HalfWordAccess;
20537let mayStore = 1;
20538let BaseOpcode = "S2_storerh_pi";
20539let isNVStorable = 1;
20540let Constraints = "$Rx32 = $Rx32in";
20541}
20542def S2_pstorerht_zomap : HInst<
20543(outs),
20544(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20545"if ($Pv4) memh($Rs32) = $Rt32",
20546tc_8035e91f, TypeMAPPING> {
20547let isPseudo = 1;
20548let isCodeGenOnly = 1;
20549}
20550def S2_pstorerhtnew_pi : HInst<
20551(outs IntRegs:$Rx32),
20552(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20553"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20554tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20555let Inst{2-2} = 0b0;
20556let Inst{7-7} = 0b1;
20557let Inst{13-13} = 0b1;
20558let Inst{31-21} = 0b10101011010;
20559let isPredicated = 1;
20560let addrMode = PostInc;
20561let accessSize = HalfWordAccess;
20562let isPredicatedNew = 1;
20563let mayStore = 1;
20564let BaseOpcode = "S2_storerh_pi";
20565let isNVStorable = 1;
20566let Constraints = "$Rx32 = $Rx32in";
20567}
20568def S2_pstorerif_io : HInst<
20569(outs),
20570(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20571"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
20572tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20573let Inst{2-2} = 0b0;
20574let Inst{31-21} = 0b01000100100;
20575let isPredicated = 1;
20576let isPredicatedFalse = 1;
20577let addrMode = BaseImmOffset;
20578let accessSize = WordAccess;
20579let mayStore = 1;
20580let BaseOpcode = "S2_storeri_io";
20581let CextOpcode = "S2_storeri";
20582let InputType = "imm";
20583let isNVStorable = 1;
20584let isExtendable = 1;
20585let opExtendable = 2;
20586let isExtentSigned = 0;
20587let opExtentBits = 8;
20588let opExtentAlign = 2;
20589}
20590def S2_pstorerif_pi : HInst<
20591(outs IntRegs:$Rx32),
20592(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20593"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
20594tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20595let Inst{2-2} = 0b1;
20596let Inst{7-7} = 0b0;
20597let Inst{13-13} = 0b1;
20598let Inst{31-21} = 0b10101011100;
20599let isPredicated = 1;
20600let isPredicatedFalse = 1;
20601let addrMode = PostInc;
20602let accessSize = WordAccess;
20603let mayStore = 1;
20604let BaseOpcode = "S2_storeri_pi";
20605let isNVStorable = 1;
20606let Constraints = "$Rx32 = $Rx32in";
20607}
20608def S2_pstorerif_zomap : HInst<
20609(outs),
20610(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20611"if (!$Pv4) memw($Rs32) = $Rt32",
20612tc_8035e91f, TypeMAPPING> {
20613let isPseudo = 1;
20614let isCodeGenOnly = 1;
20615}
20616def S2_pstorerifnew_pi : HInst<
20617(outs IntRegs:$Rx32),
20618(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20619"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20620tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20621let Inst{2-2} = 0b1;
20622let Inst{7-7} = 0b1;
20623let Inst{13-13} = 0b1;
20624let Inst{31-21} = 0b10101011100;
20625let isPredicated = 1;
20626let isPredicatedFalse = 1;
20627let addrMode = PostInc;
20628let accessSize = WordAccess;
20629let isPredicatedNew = 1;
20630let mayStore = 1;
20631let BaseOpcode = "S2_storeri_pi";
20632let CextOpcode = "S2_storeri";
20633let isNVStorable = 1;
20634let Constraints = "$Rx32 = $Rx32in";
20635}
20636def S2_pstorerinewf_io : HInst<
20637(outs),
20638(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20639"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20640tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20641let Inst{2-2} = 0b0;
20642let Inst{12-11} = 0b10;
20643let Inst{31-21} = 0b01000100101;
20644let isPredicated = 1;
20645let isPredicatedFalse = 1;
20646let addrMode = BaseImmOffset;
20647let accessSize = WordAccess;
20648let isNVStore = 1;
20649let isNewValue = 1;
20650let isRestrictNoSlot1Store = 1;
20651let mayStore = 1;
20652let BaseOpcode = "S2_storeri_io";
20653let CextOpcode = "S2_storeri";
20654let InputType = "imm";
20655let isExtendable = 1;
20656let opExtendable = 2;
20657let isExtentSigned = 0;
20658let opExtentBits = 8;
20659let opExtentAlign = 2;
20660let opNewValue = 3;
20661}
20662def S2_pstorerinewf_pi : HInst<
20663(outs IntRegs:$Rx32),
20664(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20665"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20666tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20667let Inst{2-2} = 0b1;
20668let Inst{7-7} = 0b0;
20669let Inst{13-11} = 0b110;
20670let Inst{31-21} = 0b10101011101;
20671let isPredicated = 1;
20672let isPredicatedFalse = 1;
20673let addrMode = PostInc;
20674let accessSize = WordAccess;
20675let isNVStore = 1;
20676let isNewValue = 1;
20677let isRestrictNoSlot1Store = 1;
20678let mayStore = 1;
20679let BaseOpcode = "S2_storeri_pi";
20680let CextOpcode = "S2_storeri";
20681let opNewValue = 4;
20682let Constraints = "$Rx32 = $Rx32in";
20683}
20684def S2_pstorerinewf_zomap : HInst<
20685(outs),
20686(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20687"if (!$Pv4) memw($Rs32) = $Nt8.new",
20688tc_011e0e9d, TypeMAPPING> {
20689let isPseudo = 1;
20690let isCodeGenOnly = 1;
20691let opNewValue = 2;
20692}
20693def S2_pstorerinewfnew_pi : HInst<
20694(outs IntRegs:$Rx32),
20695(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20696"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20697tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20698let Inst{2-2} = 0b1;
20699let Inst{7-7} = 0b1;
20700let Inst{13-11} = 0b110;
20701let Inst{31-21} = 0b10101011101;
20702let isPredicated = 1;
20703let isPredicatedFalse = 1;
20704let addrMode = PostInc;
20705let accessSize = WordAccess;
20706let isNVStore = 1;
20707let isPredicatedNew = 1;
20708let isNewValue = 1;
20709let isRestrictNoSlot1Store = 1;
20710let mayStore = 1;
20711let BaseOpcode = "S2_storeri_pi";
20712let CextOpcode = "S2_storeri";
20713let opNewValue = 4;
20714let Constraints = "$Rx32 = $Rx32in";
20715}
20716def S2_pstorerinewt_io : HInst<
20717(outs),
20718(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20719"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20720tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20721let Inst{2-2} = 0b0;
20722let Inst{12-11} = 0b10;
20723let Inst{31-21} = 0b01000000101;
20724let isPredicated = 1;
20725let addrMode = BaseImmOffset;
20726let accessSize = WordAccess;
20727let isNVStore = 1;
20728let isNewValue = 1;
20729let isRestrictNoSlot1Store = 1;
20730let mayStore = 1;
20731let BaseOpcode = "S2_storeri_io";
20732let CextOpcode = "S2_storeri";
20733let InputType = "imm";
20734let isExtendable = 1;
20735let opExtendable = 2;
20736let isExtentSigned = 0;
20737let opExtentBits = 8;
20738let opExtentAlign = 2;
20739let opNewValue = 3;
20740}
20741def S2_pstorerinewt_pi : HInst<
20742(outs IntRegs:$Rx32),
20743(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20744"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20745tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20746let Inst{2-2} = 0b0;
20747let Inst{7-7} = 0b0;
20748let Inst{13-11} = 0b110;
20749let Inst{31-21} = 0b10101011101;
20750let isPredicated = 1;
20751let addrMode = PostInc;
20752let accessSize = WordAccess;
20753let isNVStore = 1;
20754let isNewValue = 1;
20755let isRestrictNoSlot1Store = 1;
20756let mayStore = 1;
20757let BaseOpcode = "S2_storeri_pi";
20758let CextOpcode = "S2_storeri";
20759let opNewValue = 4;
20760let Constraints = "$Rx32 = $Rx32in";
20761}
20762def S2_pstorerinewt_zomap : HInst<
20763(outs),
20764(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20765"if ($Pv4) memw($Rs32) = $Nt8.new",
20766tc_011e0e9d, TypeMAPPING> {
20767let isPseudo = 1;
20768let isCodeGenOnly = 1;
20769let opNewValue = 2;
20770}
20771def S2_pstorerinewtnew_pi : HInst<
20772(outs IntRegs:$Rx32),
20773(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20774"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20775tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20776let Inst{2-2} = 0b0;
20777let Inst{7-7} = 0b1;
20778let Inst{13-11} = 0b110;
20779let Inst{31-21} = 0b10101011101;
20780let isPredicated = 1;
20781let addrMode = PostInc;
20782let accessSize = WordAccess;
20783let isNVStore = 1;
20784let isPredicatedNew = 1;
20785let isNewValue = 1;
20786let isRestrictNoSlot1Store = 1;
20787let mayStore = 1;
20788let BaseOpcode = "S2_storeri_pi";
20789let CextOpcode = "S2_storeri";
20790let opNewValue = 4;
20791let Constraints = "$Rx32 = $Rx32in";
20792}
20793def S2_pstorerit_io : HInst<
20794(outs),
20795(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20796"if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
20797tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20798let Inst{2-2} = 0b0;
20799let Inst{31-21} = 0b01000000100;
20800let isPredicated = 1;
20801let addrMode = BaseImmOffset;
20802let accessSize = WordAccess;
20803let mayStore = 1;
20804let BaseOpcode = "S2_storeri_io";
20805let CextOpcode = "S2_storeri";
20806let InputType = "imm";
20807let isNVStorable = 1;
20808let isExtendable = 1;
20809let opExtendable = 2;
20810let isExtentSigned = 0;
20811let opExtentBits = 8;
20812let opExtentAlign = 2;
20813}
20814def S2_pstorerit_pi : HInst<
20815(outs IntRegs:$Rx32),
20816(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20817"if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
20818tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20819let Inst{2-2} = 0b0;
20820let Inst{7-7} = 0b0;
20821let Inst{13-13} = 0b1;
20822let Inst{31-21} = 0b10101011100;
20823let isPredicated = 1;
20824let addrMode = PostInc;
20825let accessSize = WordAccess;
20826let mayStore = 1;
20827let BaseOpcode = "S2_storeri_pi";
20828let isNVStorable = 1;
20829let Constraints = "$Rx32 = $Rx32in";
20830}
20831def S2_pstorerit_zomap : HInst<
20832(outs),
20833(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20834"if ($Pv4) memw($Rs32) = $Rt32",
20835tc_8035e91f, TypeMAPPING> {
20836let isPseudo = 1;
20837let isCodeGenOnly = 1;
20838}
20839def S2_pstoreritnew_pi : HInst<
20840(outs IntRegs:$Rx32),
20841(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20842"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20843tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20844let Inst{2-2} = 0b0;
20845let Inst{7-7} = 0b1;
20846let Inst{13-13} = 0b1;
20847let Inst{31-21} = 0b10101011100;
20848let isPredicated = 1;
20849let addrMode = PostInc;
20850let accessSize = WordAccess;
20851let isPredicatedNew = 1;
20852let mayStore = 1;
20853let BaseOpcode = "S2_storeri_pi";
20854let isNVStorable = 1;
20855let Constraints = "$Rx32 = $Rx32in";
20856}
20857def S2_setbit_i : HInst<
20858(outs IntRegs:$Rd32),
20859(ins IntRegs:$Rs32, u5_0Imm:$Ii),
20860"$Rd32 = setbit($Rs32,#$Ii)",
20861tc_5da50c4b, TypeS_2op>, Enc_a05677 {
20862let Inst{7-5} = 0b000;
20863let Inst{13-13} = 0b0;
20864let Inst{31-21} = 0b10001100110;
20865let hasNewValue = 1;
20866let opNewValue = 0;
20867}
20868def S2_setbit_r : HInst<
20869(outs IntRegs:$Rd32),
20870(ins IntRegs:$Rs32, IntRegs:$Rt32),
20871"$Rd32 = setbit($Rs32,$Rt32)",
20872tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
20873let Inst{7-5} = 0b000;
20874let Inst{13-13} = 0b0;
20875let Inst{31-21} = 0b11000110100;
20876let hasNewValue = 1;
20877let opNewValue = 0;
20878}
20879def S2_shuffeb : HInst<
20880(outs DoubleRegs:$Rdd32),
20881(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20882"$Rdd32 = shuffeb($Rss32,$Rtt32)",
20883tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20884let Inst{7-5} = 0b010;
20885let Inst{13-13} = 0b0;
20886let Inst{31-21} = 0b11000001000;
20887}
20888def S2_shuffeh : HInst<
20889(outs DoubleRegs:$Rdd32),
20890(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20891"$Rdd32 = shuffeh($Rss32,$Rtt32)",
20892tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20893let Inst{7-5} = 0b110;
20894let Inst{13-13} = 0b0;
20895let Inst{31-21} = 0b11000001000;
20896}
20897def S2_shuffob : HInst<
20898(outs DoubleRegs:$Rdd32),
20899(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20900"$Rdd32 = shuffob($Rtt32,$Rss32)",
20901tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20902let Inst{7-5} = 0b100;
20903let Inst{13-13} = 0b0;
20904let Inst{31-21} = 0b11000001000;
20905}
20906def S2_shuffoh : HInst<
20907(outs DoubleRegs:$Rdd32),
20908(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20909"$Rdd32 = shuffoh($Rtt32,$Rss32)",
20910tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20911let Inst{7-5} = 0b000;
20912let Inst{13-13} = 0b0;
20913let Inst{31-21} = 0b11000001100;
20914}
20915def S2_storerb_io : HInst<
20916(outs),
20917(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
20918"memb($Rs32+#$Ii) = $Rt32",
20919tc_ae5babd7, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
20920let Inst{24-21} = 0b1000;
20921let Inst{31-27} = 0b10100;
20922let addrMode = BaseImmOffset;
20923let accessSize = ByteAccess;
20924let mayStore = 1;
20925let BaseOpcode = "S2_storerb_io";
20926let CextOpcode = "S2_storerb";
20927let InputType = "imm";
20928let isNVStorable = 1;
20929let isPredicable = 1;
20930let isExtendable = 1;
20931let opExtendable = 1;
20932let isExtentSigned = 1;
20933let opExtentBits = 11;
20934let opExtentAlign = 0;
20935}
20936def S2_storerb_pbr : HInst<
20937(outs IntRegs:$Rx32),
20938(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20939"memb($Rx32++$Mu2:brev) = $Rt32",
20940tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20941let Inst{7-0} = 0b00000000;
20942let Inst{31-21} = 0b10101111000;
20943let addrMode = PostInc;
20944let accessSize = ByteAccess;
20945let mayStore = 1;
20946let BaseOpcode = "S2_storerb_pbr";
20947let isNVStorable = 1;
20948let Constraints = "$Rx32 = $Rx32in";
20949}
20950def S2_storerb_pci : HInst<
20951(outs IntRegs:$Rx32),
20952(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20953"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20954tc_b4dc7630, TypeST>, Enc_b15941, AddrModeRel {
20955let Inst{2-0} = 0b000;
20956let Inst{7-7} = 0b0;
20957let Inst{31-21} = 0b10101001000;
20958let addrMode = PostInc;
20959let accessSize = ByteAccess;
20960let mayStore = 1;
20961let Uses = [CS];
20962let BaseOpcode = "S2_storerb_pci";
20963let isNVStorable = 1;
20964let Constraints = "$Rx32 = $Rx32in";
20965}
20966def S2_storerb_pcr : HInst<
20967(outs IntRegs:$Rx32),
20968(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20969"memb($Rx32++I:circ($Mu2)) = $Rt32",
20970tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20971let Inst{7-0} = 0b00000010;
20972let Inst{31-21} = 0b10101001000;
20973let addrMode = PostInc;
20974let accessSize = ByteAccess;
20975let mayStore = 1;
20976let Uses = [CS];
20977let BaseOpcode = "S2_storerb_pcr";
20978let isNVStorable = 1;
20979let Constraints = "$Rx32 = $Rx32in";
20980}
20981def S2_storerb_pi : HInst<
20982(outs IntRegs:$Rx32),
20983(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20984"memb($Rx32++#$Ii) = $Rt32",
20985tc_a2b365d2, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
20986let Inst{2-0} = 0b000;
20987let Inst{7-7} = 0b0;
20988let Inst{13-13} = 0b0;
20989let Inst{31-21} = 0b10101011000;
20990let addrMode = PostInc;
20991let accessSize = ByteAccess;
20992let mayStore = 1;
20993let BaseOpcode = "S2_storerb_pi";
20994let CextOpcode = "S2_storerb";
20995let isNVStorable = 1;
20996let isPredicable = 1;
20997let Constraints = "$Rx32 = $Rx32in";
20998}
20999def S2_storerb_pr : HInst<
21000(outs IntRegs:$Rx32),
21001(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21002"memb($Rx32++$Mu2) = $Rt32",
21003tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21004let Inst{7-0} = 0b00000000;
21005let Inst{31-21} = 0b10101101000;
21006let addrMode = PostInc;
21007let accessSize = ByteAccess;
21008let mayStore = 1;
21009let BaseOpcode = "S2_storerb_pr";
21010let isNVStorable = 1;
21011let Constraints = "$Rx32 = $Rx32in";
21012}
21013def S2_storerb_zomap : HInst<
21014(outs),
21015(ins IntRegs:$Rs32, IntRegs:$Rt32),
21016"memb($Rs32) = $Rt32",
21017tc_ae5babd7, TypeMAPPING> {
21018let isPseudo = 1;
21019let isCodeGenOnly = 1;
21020}
21021def S2_storerbgp : HInst<
21022(outs),
21023(ins u32_0Imm:$Ii, IntRegs:$Rt32),
21024"memb(gp+#$Ii) = $Rt32",
21025tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
21026let Inst{24-21} = 0b0000;
21027let Inst{31-27} = 0b01001;
21028let accessSize = ByteAccess;
21029let mayStore = 1;
21030let Uses = [GP];
21031let BaseOpcode = "S2_storerbabs";
21032let isNVStorable = 1;
21033let isPredicable = 1;
21034let opExtendable = 0;
21035let isExtentSigned = 0;
21036let opExtentBits = 16;
21037let opExtentAlign = 0;
21038}
21039def S2_storerbnew_io : HInst<
21040(outs),
21041(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
21042"memb($Rs32+#$Ii) = $Nt8.new",
21043tc_5deb5e47, TypeST>, Enc_4df4e9, AddrModeRel {
21044let Inst{12-11} = 0b00;
21045let Inst{24-21} = 0b1101;
21046let Inst{31-27} = 0b10100;
21047let addrMode = BaseImmOffset;
21048let accessSize = ByteAccess;
21049let isNVStore = 1;
21050let isNewValue = 1;
21051let isRestrictNoSlot1Store = 1;
21052let mayStore = 1;
21053let BaseOpcode = "S2_storerb_io";
21054let CextOpcode = "S2_storerb";
21055let InputType = "imm";
21056let isPredicable = 1;
21057let isExtendable = 1;
21058let opExtendable = 1;
21059let isExtentSigned = 1;
21060let opExtentBits = 11;
21061let opExtentAlign = 0;
21062let opNewValue = 2;
21063}
21064def S2_storerbnew_pbr : HInst<
21065(outs IntRegs:$Rx32),
21066(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21067"memb($Rx32++$Mu2:brev) = $Nt8.new",
21068tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21069let Inst{7-0} = 0b00000000;
21070let Inst{12-11} = 0b00;
21071let Inst{31-21} = 0b10101111101;
21072let addrMode = PostInc;
21073let accessSize = ByteAccess;
21074let isNVStore = 1;
21075let isNewValue = 1;
21076let isRestrictNoSlot1Store = 1;
21077let mayStore = 1;
21078let BaseOpcode = "S2_storerb_pbr";
21079let opNewValue = 3;
21080let Constraints = "$Rx32 = $Rx32in";
21081}
21082def S2_storerbnew_pci : HInst<
21083(outs IntRegs:$Rx32),
21084(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21085"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21086tc_addc37a8, TypeST>, Enc_96ce4f, AddrModeRel {
21087let Inst{2-0} = 0b000;
21088let Inst{7-7} = 0b0;
21089let Inst{12-11} = 0b00;
21090let Inst{31-21} = 0b10101001101;
21091let addrMode = PostInc;
21092let accessSize = ByteAccess;
21093let isNVStore = 1;
21094let isNewValue = 1;
21095let isRestrictNoSlot1Store = 1;
21096let mayStore = 1;
21097let Uses = [CS];
21098let BaseOpcode = "S2_storerb_pci";
21099let opNewValue = 4;
21100let Constraints = "$Rx32 = $Rx32in";
21101}
21102def S2_storerbnew_pcr : HInst<
21103(outs IntRegs:$Rx32),
21104(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21105"memb($Rx32++I:circ($Mu2)) = $Nt8.new",
21106tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21107let Inst{7-0} = 0b00000010;
21108let Inst{12-11} = 0b00;
21109let Inst{31-21} = 0b10101001101;
21110let addrMode = PostInc;
21111let accessSize = ByteAccess;
21112let isNVStore = 1;
21113let isNewValue = 1;
21114let isRestrictNoSlot1Store = 1;
21115let mayStore = 1;
21116let Uses = [CS];
21117let BaseOpcode = "S2_storerb_pcr";
21118let opNewValue = 3;
21119let Constraints = "$Rx32 = $Rx32in";
21120}
21121def S2_storerbnew_pi : HInst<
21122(outs IntRegs:$Rx32),
21123(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
21124"memb($Rx32++#$Ii) = $Nt8.new",
21125tc_92240447, TypeST>, Enc_c7cd90, AddrModeRel {
21126let Inst{2-0} = 0b000;
21127let Inst{7-7} = 0b0;
21128let Inst{13-11} = 0b000;
21129let Inst{31-21} = 0b10101011101;
21130let addrMode = PostInc;
21131let accessSize = ByteAccess;
21132let isNVStore = 1;
21133let isNewValue = 1;
21134let isRestrictNoSlot1Store = 1;
21135let mayStore = 1;
21136let BaseOpcode = "S2_storerb_pi";
21137let isNVStorable = 1;
21138let isPredicable = 1;
21139let opNewValue = 3;
21140let Constraints = "$Rx32 = $Rx32in";
21141}
21142def S2_storerbnew_pr : HInst<
21143(outs IntRegs:$Rx32),
21144(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21145"memb($Rx32++$Mu2) = $Nt8.new",
21146tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21147let Inst{7-0} = 0b00000000;
21148let Inst{12-11} = 0b00;
21149let Inst{31-21} = 0b10101101101;
21150let addrMode = PostInc;
21151let accessSize = ByteAccess;
21152let isNVStore = 1;
21153let isNewValue = 1;
21154let isRestrictNoSlot1Store = 1;
21155let mayStore = 1;
21156let BaseOpcode = "S2_storerb_pr";
21157let opNewValue = 3;
21158let Constraints = "$Rx32 = $Rx32in";
21159}
21160def S2_storerbnew_zomap : HInst<
21161(outs),
21162(ins IntRegs:$Rs32, IntRegs:$Nt8),
21163"memb($Rs32) = $Nt8.new",
21164tc_5deb5e47, TypeMAPPING> {
21165let isPseudo = 1;
21166let isCodeGenOnly = 1;
21167let opNewValue = 1;
21168}
21169def S2_storerbnewgp : HInst<
21170(outs),
21171(ins u32_0Imm:$Ii, IntRegs:$Nt8),
21172"memb(gp+#$Ii) = $Nt8.new",
21173tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
21174let Inst{12-11} = 0b00;
21175let Inst{24-21} = 0b0101;
21176let Inst{31-27} = 0b01001;
21177let accessSize = ByteAccess;
21178let isNVStore = 1;
21179let isNewValue = 1;
21180let isRestrictNoSlot1Store = 1;
21181let mayStore = 1;
21182let Uses = [GP];
21183let BaseOpcode = "S2_storerbabs";
21184let isPredicable = 1;
21185let opExtendable = 0;
21186let isExtentSigned = 0;
21187let opExtentBits = 16;
21188let opExtentAlign = 0;
21189let opNewValue = 1;
21190}
21191def S2_storerd_io : HInst<
21192(outs),
21193(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
21194"memd($Rs32+#$Ii) = $Rtt32",
21195tc_ae5babd7, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
21196let Inst{24-21} = 0b1110;
21197let Inst{31-27} = 0b10100;
21198let addrMode = BaseImmOffset;
21199let accessSize = DoubleWordAccess;
21200let mayStore = 1;
21201let BaseOpcode = "S2_storerd_io";
21202let CextOpcode = "S2_storerd";
21203let InputType = "imm";
21204let isPredicable = 1;
21205let isExtendable = 1;
21206let opExtendable = 1;
21207let isExtentSigned = 1;
21208let opExtentBits = 14;
21209let opExtentAlign = 3;
21210}
21211def S2_storerd_pbr : HInst<
21212(outs IntRegs:$Rx32),
21213(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21214"memd($Rx32++$Mu2:brev) = $Rtt32",
21215tc_a2b365d2, TypeST>, Enc_928ca1 {
21216let Inst{7-0} = 0b00000000;
21217let Inst{31-21} = 0b10101111110;
21218let addrMode = PostInc;
21219let accessSize = DoubleWordAccess;
21220let mayStore = 1;
21221let Constraints = "$Rx32 = $Rx32in";
21222}
21223def S2_storerd_pci : HInst<
21224(outs IntRegs:$Rx32),
21225(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21226"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
21227tc_b4dc7630, TypeST>, Enc_395cc4 {
21228let Inst{2-0} = 0b000;
21229let Inst{7-7} = 0b0;
21230let Inst{31-21} = 0b10101001110;
21231let addrMode = PostInc;
21232let accessSize = DoubleWordAccess;
21233let mayStore = 1;
21234let Uses = [CS];
21235let Constraints = "$Rx32 = $Rx32in";
21236}
21237def S2_storerd_pcr : HInst<
21238(outs IntRegs:$Rx32),
21239(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21240"memd($Rx32++I:circ($Mu2)) = $Rtt32",
21241tc_a2b365d2, TypeST>, Enc_928ca1 {
21242let Inst{7-0} = 0b00000010;
21243let Inst{31-21} = 0b10101001110;
21244let addrMode = PostInc;
21245let accessSize = DoubleWordAccess;
21246let mayStore = 1;
21247let Uses = [CS];
21248let Constraints = "$Rx32 = $Rx32in";
21249}
21250def S2_storerd_pi : HInst<
21251(outs IntRegs:$Rx32),
21252(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
21253"memd($Rx32++#$Ii) = $Rtt32",
21254tc_a2b365d2, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
21255let Inst{2-0} = 0b000;
21256let Inst{7-7} = 0b0;
21257let Inst{13-13} = 0b0;
21258let Inst{31-21} = 0b10101011110;
21259let addrMode = PostInc;
21260let accessSize = DoubleWordAccess;
21261let mayStore = 1;
21262let BaseOpcode = "S2_storerd_pi";
21263let CextOpcode = "S2_storerd";
21264let isPredicable = 1;
21265let Constraints = "$Rx32 = $Rx32in";
21266}
21267def S2_storerd_pr : HInst<
21268(outs IntRegs:$Rx32),
21269(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21270"memd($Rx32++$Mu2) = $Rtt32",
21271tc_a2b365d2, TypeST>, Enc_928ca1 {
21272let Inst{7-0} = 0b00000000;
21273let Inst{31-21} = 0b10101101110;
21274let addrMode = PostInc;
21275let accessSize = DoubleWordAccess;
21276let mayStore = 1;
21277let Constraints = "$Rx32 = $Rx32in";
21278}
21279def S2_storerd_zomap : HInst<
21280(outs),
21281(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
21282"memd($Rs32) = $Rtt32",
21283tc_ae5babd7, TypeMAPPING> {
21284let isPseudo = 1;
21285let isCodeGenOnly = 1;
21286}
21287def S2_storerdgp : HInst<
21288(outs),
21289(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
21290"memd(gp+#$Ii) = $Rtt32",
21291tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
21292let Inst{24-21} = 0b0110;
21293let Inst{31-27} = 0b01001;
21294let accessSize = DoubleWordAccess;
21295let mayStore = 1;
21296let Uses = [GP];
21297let BaseOpcode = "S2_storerdabs";
21298let isPredicable = 1;
21299let opExtendable = 0;
21300let isExtentSigned = 0;
21301let opExtentBits = 19;
21302let opExtentAlign = 3;
21303}
21304def S2_storerf_io : HInst<
21305(outs),
21306(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21307"memh($Rs32+#$Ii) = $Rt32.h",
21308tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21309let Inst{24-21} = 0b1011;
21310let Inst{31-27} = 0b10100;
21311let addrMode = BaseImmOffset;
21312let accessSize = HalfWordAccess;
21313let mayStore = 1;
21314let BaseOpcode = "S2_storerf_io";
21315let CextOpcode = "S2_storerf";
21316let InputType = "imm";
21317let isPredicable = 1;
21318let isExtendable = 1;
21319let opExtendable = 1;
21320let isExtentSigned = 1;
21321let opExtentBits = 12;
21322let opExtentAlign = 1;
21323}
21324def S2_storerf_pbr : HInst<
21325(outs IntRegs:$Rx32),
21326(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21327"memh($Rx32++$Mu2:brev) = $Rt32.h",
21328tc_a2b365d2, TypeST>, Enc_d5c73f {
21329let Inst{7-0} = 0b00000000;
21330let Inst{31-21} = 0b10101111011;
21331let addrMode = PostInc;
21332let accessSize = HalfWordAccess;
21333let mayStore = 1;
21334let Constraints = "$Rx32 = $Rx32in";
21335}
21336def S2_storerf_pci : HInst<
21337(outs IntRegs:$Rx32),
21338(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21339"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
21340tc_b4dc7630, TypeST>, Enc_935d9b {
21341let Inst{2-0} = 0b000;
21342let Inst{7-7} = 0b0;
21343let Inst{31-21} = 0b10101001011;
21344let addrMode = PostInc;
21345let accessSize = HalfWordAccess;
21346let mayStore = 1;
21347let Uses = [CS];
21348let Constraints = "$Rx32 = $Rx32in";
21349}
21350def S2_storerf_pcr : HInst<
21351(outs IntRegs:$Rx32),
21352(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21353"memh($Rx32++I:circ($Mu2)) = $Rt32.h",
21354tc_a2b365d2, TypeST>, Enc_d5c73f {
21355let Inst{7-0} = 0b00000010;
21356let Inst{31-21} = 0b10101001011;
21357let addrMode = PostInc;
21358let accessSize = HalfWordAccess;
21359let mayStore = 1;
21360let Uses = [CS];
21361let Constraints = "$Rx32 = $Rx32in";
21362}
21363def S2_storerf_pi : HInst<
21364(outs IntRegs:$Rx32),
21365(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21366"memh($Rx32++#$Ii) = $Rt32.h",
21367tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21368let Inst{2-0} = 0b000;
21369let Inst{7-7} = 0b0;
21370let Inst{13-13} = 0b0;
21371let Inst{31-21} = 0b10101011011;
21372let addrMode = PostInc;
21373let accessSize = HalfWordAccess;
21374let mayStore = 1;
21375let BaseOpcode = "S2_storerf_pi";
21376let CextOpcode = "S2_storerf";
21377let isPredicable = 1;
21378let Constraints = "$Rx32 = $Rx32in";
21379}
21380def S2_storerf_pr : HInst<
21381(outs IntRegs:$Rx32),
21382(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21383"memh($Rx32++$Mu2) = $Rt32.h",
21384tc_a2b365d2, TypeST>, Enc_d5c73f {
21385let Inst{7-0} = 0b00000000;
21386let Inst{31-21} = 0b10101101011;
21387let addrMode = PostInc;
21388let accessSize = HalfWordAccess;
21389let mayStore = 1;
21390let Constraints = "$Rx32 = $Rx32in";
21391}
21392def S2_storerf_zomap : HInst<
21393(outs),
21394(ins IntRegs:$Rs32, IntRegs:$Rt32),
21395"memh($Rs32) = $Rt32.h",
21396tc_ae5babd7, TypeMAPPING> {
21397let isPseudo = 1;
21398let isCodeGenOnly = 1;
21399}
21400def S2_storerfgp : HInst<
21401(outs),
21402(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21403"memh(gp+#$Ii) = $Rt32.h",
21404tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21405let Inst{24-21} = 0b0011;
21406let Inst{31-27} = 0b01001;
21407let accessSize = HalfWordAccess;
21408let mayStore = 1;
21409let Uses = [GP];
21410let BaseOpcode = "S2_storerfabs";
21411let isPredicable = 1;
21412let opExtendable = 0;
21413let isExtentSigned = 0;
21414let opExtentBits = 17;
21415let opExtentAlign = 1;
21416}
21417def S2_storerh_io : HInst<
21418(outs),
21419(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21420"memh($Rs32+#$Ii) = $Rt32",
21421tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21422let Inst{24-21} = 0b1010;
21423let Inst{31-27} = 0b10100;
21424let addrMode = BaseImmOffset;
21425let accessSize = HalfWordAccess;
21426let mayStore = 1;
21427let BaseOpcode = "S2_storerh_io";
21428let CextOpcode = "S2_storerh";
21429let InputType = "imm";
21430let isNVStorable = 1;
21431let isPredicable = 1;
21432let isExtendable = 1;
21433let opExtendable = 1;
21434let isExtentSigned = 1;
21435let opExtentBits = 12;
21436let opExtentAlign = 1;
21437}
21438def S2_storerh_pbr : HInst<
21439(outs IntRegs:$Rx32),
21440(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21441"memh($Rx32++$Mu2:brev) = $Rt32",
21442tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21443let Inst{7-0} = 0b00000000;
21444let Inst{31-21} = 0b10101111010;
21445let addrMode = PostInc;
21446let accessSize = HalfWordAccess;
21447let mayStore = 1;
21448let BaseOpcode = "S2_storerh_pbr";
21449let isNVStorable = 1;
21450let Constraints = "$Rx32 = $Rx32in";
21451}
21452def S2_storerh_pci : HInst<
21453(outs IntRegs:$Rx32),
21454(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21455"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21456tc_b4dc7630, TypeST>, Enc_935d9b, AddrModeRel {
21457let Inst{2-0} = 0b000;
21458let Inst{7-7} = 0b0;
21459let Inst{31-21} = 0b10101001010;
21460let addrMode = PostInc;
21461let accessSize = HalfWordAccess;
21462let mayStore = 1;
21463let Uses = [CS];
21464let BaseOpcode = "S2_storerh_pci";
21465let isNVStorable = 1;
21466let Constraints = "$Rx32 = $Rx32in";
21467}
21468def S2_storerh_pcr : HInst<
21469(outs IntRegs:$Rx32),
21470(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21471"memh($Rx32++I:circ($Mu2)) = $Rt32",
21472tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21473let Inst{7-0} = 0b00000010;
21474let Inst{31-21} = 0b10101001010;
21475let addrMode = PostInc;
21476let accessSize = HalfWordAccess;
21477let mayStore = 1;
21478let Uses = [CS];
21479let BaseOpcode = "S2_storerh_pcr";
21480let isNVStorable = 1;
21481let Constraints = "$Rx32 = $Rx32in";
21482}
21483def S2_storerh_pi : HInst<
21484(outs IntRegs:$Rx32),
21485(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21486"memh($Rx32++#$Ii) = $Rt32",
21487tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21488let Inst{2-0} = 0b000;
21489let Inst{7-7} = 0b0;
21490let Inst{13-13} = 0b0;
21491let Inst{31-21} = 0b10101011010;
21492let addrMode = PostInc;
21493let accessSize = HalfWordAccess;
21494let mayStore = 1;
21495let BaseOpcode = "S2_storerh_pi";
21496let CextOpcode = "S2_storerh";
21497let isNVStorable = 1;
21498let isPredicable = 1;
21499let Constraints = "$Rx32 = $Rx32in";
21500}
21501def S2_storerh_pr : HInst<
21502(outs IntRegs:$Rx32),
21503(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21504"memh($Rx32++$Mu2) = $Rt32",
21505tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21506let Inst{7-0} = 0b00000000;
21507let Inst{31-21} = 0b10101101010;
21508let addrMode = PostInc;
21509let accessSize = HalfWordAccess;
21510let mayStore = 1;
21511let BaseOpcode = "S2_storerh_pr";
21512let isNVStorable = 1;
21513let Constraints = "$Rx32 = $Rx32in";
21514}
21515def S2_storerh_zomap : HInst<
21516(outs),
21517(ins IntRegs:$Rs32, IntRegs:$Rt32),
21518"memh($Rs32) = $Rt32",
21519tc_ae5babd7, TypeMAPPING> {
21520let isPseudo = 1;
21521let isCodeGenOnly = 1;
21522}
21523def S2_storerhgp : HInst<
21524(outs),
21525(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21526"memh(gp+#$Ii) = $Rt32",
21527tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21528let Inst{24-21} = 0b0010;
21529let Inst{31-27} = 0b01001;
21530let accessSize = HalfWordAccess;
21531let mayStore = 1;
21532let Uses = [GP];
21533let BaseOpcode = "S2_storerhabs";
21534let isNVStorable = 1;
21535let isPredicable = 1;
21536let opExtendable = 0;
21537let isExtentSigned = 0;
21538let opExtentBits = 17;
21539let opExtentAlign = 1;
21540}
21541def S2_storerhnew_io : HInst<
21542(outs),
21543(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
21544"memh($Rs32+#$Ii) = $Nt8.new",
21545tc_5deb5e47, TypeST>, Enc_0d8870, AddrModeRel {
21546let Inst{12-11} = 0b01;
21547let Inst{24-21} = 0b1101;
21548let Inst{31-27} = 0b10100;
21549let addrMode = BaseImmOffset;
21550let accessSize = HalfWordAccess;
21551let isNVStore = 1;
21552let isNewValue = 1;
21553let isRestrictNoSlot1Store = 1;
21554let mayStore = 1;
21555let BaseOpcode = "S2_storerh_io";
21556let CextOpcode = "S2_storerh";
21557let InputType = "imm";
21558let isPredicable = 1;
21559let isExtendable = 1;
21560let opExtendable = 1;
21561let isExtentSigned = 1;
21562let opExtentBits = 12;
21563let opExtentAlign = 1;
21564let opNewValue = 2;
21565}
21566def S2_storerhnew_pbr : HInst<
21567(outs IntRegs:$Rx32),
21568(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21569"memh($Rx32++$Mu2:brev) = $Nt8.new",
21570tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21571let Inst{7-0} = 0b00000000;
21572let Inst{12-11} = 0b01;
21573let Inst{31-21} = 0b10101111101;
21574let addrMode = PostInc;
21575let accessSize = HalfWordAccess;
21576let isNVStore = 1;
21577let isNewValue = 1;
21578let isRestrictNoSlot1Store = 1;
21579let mayStore = 1;
21580let BaseOpcode = "S2_storerh_pbr";
21581let opNewValue = 3;
21582let Constraints = "$Rx32 = $Rx32in";
21583}
21584def S2_storerhnew_pci : HInst<
21585(outs IntRegs:$Rx32),
21586(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21587"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21588tc_addc37a8, TypeST>, Enc_91b9fe, AddrModeRel {
21589let Inst{2-0} = 0b000;
21590let Inst{7-7} = 0b0;
21591let Inst{12-11} = 0b01;
21592let Inst{31-21} = 0b10101001101;
21593let addrMode = PostInc;
21594let accessSize = HalfWordAccess;
21595let isNVStore = 1;
21596let isNewValue = 1;
21597let isRestrictNoSlot1Store = 1;
21598let mayStore = 1;
21599let Uses = [CS];
21600let BaseOpcode = "S2_storerh_pci";
21601let opNewValue = 4;
21602let Constraints = "$Rx32 = $Rx32in";
21603}
21604def S2_storerhnew_pcr : HInst<
21605(outs IntRegs:$Rx32),
21606(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21607"memh($Rx32++I:circ($Mu2)) = $Nt8.new",
21608tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21609let Inst{7-0} = 0b00000010;
21610let Inst{12-11} = 0b01;
21611let Inst{31-21} = 0b10101001101;
21612let addrMode = PostInc;
21613let accessSize = HalfWordAccess;
21614let isNVStore = 1;
21615let isNewValue = 1;
21616let isRestrictNoSlot1Store = 1;
21617let mayStore = 1;
21618let Uses = [CS];
21619let BaseOpcode = "S2_storerh_pcr";
21620let opNewValue = 3;
21621let Constraints = "$Rx32 = $Rx32in";
21622}
21623def S2_storerhnew_pi : HInst<
21624(outs IntRegs:$Rx32),
21625(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
21626"memh($Rx32++#$Ii) = $Nt8.new",
21627tc_92240447, TypeST>, Enc_e26546, AddrModeRel {
21628let Inst{2-0} = 0b000;
21629let Inst{7-7} = 0b0;
21630let Inst{13-11} = 0b001;
21631let Inst{31-21} = 0b10101011101;
21632let addrMode = PostInc;
21633let accessSize = HalfWordAccess;
21634let isNVStore = 1;
21635let isNewValue = 1;
21636let isRestrictNoSlot1Store = 1;
21637let mayStore = 1;
21638let BaseOpcode = "S2_storerh_pi";
21639let isNVStorable = 1;
21640let isPredicable = 1;
21641let opNewValue = 3;
21642let Constraints = "$Rx32 = $Rx32in";
21643}
21644def S2_storerhnew_pr : HInst<
21645(outs IntRegs:$Rx32),
21646(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21647"memh($Rx32++$Mu2) = $Nt8.new",
21648tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21649let Inst{7-0} = 0b00000000;
21650let Inst{12-11} = 0b01;
21651let Inst{31-21} = 0b10101101101;
21652let addrMode = PostInc;
21653let accessSize = HalfWordAccess;
21654let isNVStore = 1;
21655let isNewValue = 1;
21656let isRestrictNoSlot1Store = 1;
21657let mayStore = 1;
21658let BaseOpcode = "S2_storerh_pr";
21659let opNewValue = 3;
21660let Constraints = "$Rx32 = $Rx32in";
21661}
21662def S2_storerhnew_zomap : HInst<
21663(outs),
21664(ins IntRegs:$Rs32, IntRegs:$Nt8),
21665"memh($Rs32) = $Nt8.new",
21666tc_5deb5e47, TypeMAPPING> {
21667let isPseudo = 1;
21668let isCodeGenOnly = 1;
21669let opNewValue = 1;
21670}
21671def S2_storerhnewgp : HInst<
21672(outs),
21673(ins u31_1Imm:$Ii, IntRegs:$Nt8),
21674"memh(gp+#$Ii) = $Nt8.new",
21675tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
21676let Inst{12-11} = 0b01;
21677let Inst{24-21} = 0b0101;
21678let Inst{31-27} = 0b01001;
21679let accessSize = HalfWordAccess;
21680let isNVStore = 1;
21681let isNewValue = 1;
21682let isRestrictNoSlot1Store = 1;
21683let mayStore = 1;
21684let Uses = [GP];
21685let BaseOpcode = "S2_storerhabs";
21686let isPredicable = 1;
21687let opExtendable = 0;
21688let isExtentSigned = 0;
21689let opExtentBits = 17;
21690let opExtentAlign = 1;
21691let opNewValue = 1;
21692}
21693def S2_storeri_io : HInst<
21694(outs),
21695(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
21696"memw($Rs32+#$Ii) = $Rt32",
21697tc_ae5babd7, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
21698let Inst{24-21} = 0b1100;
21699let Inst{31-27} = 0b10100;
21700let addrMode = BaseImmOffset;
21701let accessSize = WordAccess;
21702let mayStore = 1;
21703let BaseOpcode = "S2_storeri_io";
21704let CextOpcode = "S2_storeri";
21705let InputType = "imm";
21706let isNVStorable = 1;
21707let isPredicable = 1;
21708let isExtendable = 1;
21709let opExtendable = 1;
21710let isExtentSigned = 1;
21711let opExtentBits = 13;
21712let opExtentAlign = 2;
21713}
21714def S2_storeri_pbr : HInst<
21715(outs IntRegs:$Rx32),
21716(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21717"memw($Rx32++$Mu2:brev) = $Rt32",
21718tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21719let Inst{7-0} = 0b00000000;
21720let Inst{31-21} = 0b10101111100;
21721let addrMode = PostInc;
21722let accessSize = WordAccess;
21723let mayStore = 1;
21724let BaseOpcode = "S2_storeri_pbr";
21725let isNVStorable = 1;
21726let Constraints = "$Rx32 = $Rx32in";
21727}
21728def S2_storeri_pci : HInst<
21729(outs IntRegs:$Rx32),
21730(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21731"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21732tc_b4dc7630, TypeST>, Enc_79b8c8, AddrModeRel {
21733let Inst{2-0} = 0b000;
21734let Inst{7-7} = 0b0;
21735let Inst{31-21} = 0b10101001100;
21736let addrMode = PostInc;
21737let accessSize = WordAccess;
21738let mayStore = 1;
21739let Uses = [CS];
21740let BaseOpcode = "S2_storeri_pci";
21741let isNVStorable = 1;
21742let Constraints = "$Rx32 = $Rx32in";
21743}
21744def S2_storeri_pcr : HInst<
21745(outs IntRegs:$Rx32),
21746(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21747"memw($Rx32++I:circ($Mu2)) = $Rt32",
21748tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21749let Inst{7-0} = 0b00000010;
21750let Inst{31-21} = 0b10101001100;
21751let addrMode = PostInc;
21752let accessSize = WordAccess;
21753let mayStore = 1;
21754let Uses = [CS];
21755let BaseOpcode = "S2_storeri_pcr";
21756let isNVStorable = 1;
21757let Constraints = "$Rx32 = $Rx32in";
21758}
21759def S2_storeri_pi : HInst<
21760(outs IntRegs:$Rx32),
21761(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
21762"memw($Rx32++#$Ii) = $Rt32",
21763tc_a2b365d2, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
21764let Inst{2-0} = 0b000;
21765let Inst{7-7} = 0b0;
21766let Inst{13-13} = 0b0;
21767let Inst{31-21} = 0b10101011100;
21768let addrMode = PostInc;
21769let accessSize = WordAccess;
21770let mayStore = 1;
21771let BaseOpcode = "S2_storeri_pi";
21772let CextOpcode = "S2_storeri";
21773let isNVStorable = 1;
21774let isPredicable = 1;
21775let Constraints = "$Rx32 = $Rx32in";
21776}
21777def S2_storeri_pr : HInst<
21778(outs IntRegs:$Rx32),
21779(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21780"memw($Rx32++$Mu2) = $Rt32",
21781tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21782let Inst{7-0} = 0b00000000;
21783let Inst{31-21} = 0b10101101100;
21784let addrMode = PostInc;
21785let accessSize = WordAccess;
21786let mayStore = 1;
21787let BaseOpcode = "S2_storeri_pr";
21788let isNVStorable = 1;
21789let Constraints = "$Rx32 = $Rx32in";
21790}
21791def S2_storeri_zomap : HInst<
21792(outs),
21793(ins IntRegs:$Rs32, IntRegs:$Rt32),
21794"memw($Rs32) = $Rt32",
21795tc_ae5babd7, TypeMAPPING> {
21796let isPseudo = 1;
21797let isCodeGenOnly = 1;
21798}
21799def S2_storerigp : HInst<
21800(outs),
21801(ins u30_2Imm:$Ii, IntRegs:$Rt32),
21802"memw(gp+#$Ii) = $Rt32",
21803tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
21804let Inst{24-21} = 0b0100;
21805let Inst{31-27} = 0b01001;
21806let accessSize = WordAccess;
21807let mayStore = 1;
21808let Uses = [GP];
21809let BaseOpcode = "S2_storeriabs";
21810let isNVStorable = 1;
21811let isPredicable = 1;
21812let opExtendable = 0;
21813let isExtentSigned = 0;
21814let opExtentBits = 18;
21815let opExtentAlign = 2;
21816}
21817def S2_storerinew_io : HInst<
21818(outs),
21819(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
21820"memw($Rs32+#$Ii) = $Nt8.new",
21821tc_5deb5e47, TypeST>, Enc_690862, AddrModeRel {
21822let Inst{12-11} = 0b10;
21823let Inst{24-21} = 0b1101;
21824let Inst{31-27} = 0b10100;
21825let addrMode = BaseImmOffset;
21826let accessSize = WordAccess;
21827let isNVStore = 1;
21828let isNewValue = 1;
21829let isRestrictNoSlot1Store = 1;
21830let mayStore = 1;
21831let BaseOpcode = "S2_storeri_io";
21832let CextOpcode = "S2_storeri";
21833let InputType = "imm";
21834let isPredicable = 1;
21835let isExtendable = 1;
21836let opExtendable = 1;
21837let isExtentSigned = 1;
21838let opExtentBits = 13;
21839let opExtentAlign = 2;
21840let opNewValue = 2;
21841}
21842def S2_storerinew_pbr : HInst<
21843(outs IntRegs:$Rx32),
21844(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21845"memw($Rx32++$Mu2:brev) = $Nt8.new",
21846tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21847let Inst{7-0} = 0b00000000;
21848let Inst{12-11} = 0b10;
21849let Inst{31-21} = 0b10101111101;
21850let addrMode = PostInc;
21851let accessSize = WordAccess;
21852let isNVStore = 1;
21853let isNewValue = 1;
21854let isRestrictNoSlot1Store = 1;
21855let mayStore = 1;
21856let BaseOpcode = "S2_storeri_pbr";
21857let opNewValue = 3;
21858let Constraints = "$Rx32 = $Rx32in";
21859}
21860def S2_storerinew_pci : HInst<
21861(outs IntRegs:$Rx32),
21862(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21863"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21864tc_addc37a8, TypeST>, Enc_3f97c8, AddrModeRel {
21865let Inst{2-0} = 0b000;
21866let Inst{7-7} = 0b0;
21867let Inst{12-11} = 0b10;
21868let Inst{31-21} = 0b10101001101;
21869let addrMode = PostInc;
21870let accessSize = WordAccess;
21871let isNVStore = 1;
21872let isNewValue = 1;
21873let isRestrictNoSlot1Store = 1;
21874let mayStore = 1;
21875let Uses = [CS];
21876let BaseOpcode = "S2_storeri_pci";
21877let opNewValue = 4;
21878let Constraints = "$Rx32 = $Rx32in";
21879}
21880def S2_storerinew_pcr : HInst<
21881(outs IntRegs:$Rx32),
21882(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21883"memw($Rx32++I:circ($Mu2)) = $Nt8.new",
21884tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21885let Inst{7-0} = 0b00000010;
21886let Inst{12-11} = 0b10;
21887let Inst{31-21} = 0b10101001101;
21888let addrMode = PostInc;
21889let accessSize = WordAccess;
21890let isNVStore = 1;
21891let isNewValue = 1;
21892let isRestrictNoSlot1Store = 1;
21893let mayStore = 1;
21894let Uses = [CS];
21895let BaseOpcode = "S2_storeri_pcr";
21896let opNewValue = 3;
21897let Constraints = "$Rx32 = $Rx32in";
21898}
21899def S2_storerinew_pi : HInst<
21900(outs IntRegs:$Rx32),
21901(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
21902"memw($Rx32++#$Ii) = $Nt8.new",
21903tc_92240447, TypeST>, Enc_223005, AddrModeRel {
21904let Inst{2-0} = 0b000;
21905let Inst{7-7} = 0b0;
21906let Inst{13-11} = 0b010;
21907let Inst{31-21} = 0b10101011101;
21908let addrMode = PostInc;
21909let accessSize = WordAccess;
21910let isNVStore = 1;
21911let isNewValue = 1;
21912let isRestrictNoSlot1Store = 1;
21913let mayStore = 1;
21914let BaseOpcode = "S2_storeri_pi";
21915let isPredicable = 1;
21916let opNewValue = 3;
21917let Constraints = "$Rx32 = $Rx32in";
21918}
21919def S2_storerinew_pr : HInst<
21920(outs IntRegs:$Rx32),
21921(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21922"memw($Rx32++$Mu2) = $Nt8.new",
21923tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21924let Inst{7-0} = 0b00000000;
21925let Inst{12-11} = 0b10;
21926let Inst{31-21} = 0b10101101101;
21927let addrMode = PostInc;
21928let accessSize = WordAccess;
21929let isNVStore = 1;
21930let isNewValue = 1;
21931let isRestrictNoSlot1Store = 1;
21932let mayStore = 1;
21933let BaseOpcode = "S2_storeri_pr";
21934let opNewValue = 3;
21935let Constraints = "$Rx32 = $Rx32in";
21936}
21937def S2_storerinew_zomap : HInst<
21938(outs),
21939(ins IntRegs:$Rs32, IntRegs:$Nt8),
21940"memw($Rs32) = $Nt8.new",
21941tc_5deb5e47, TypeMAPPING> {
21942let isPseudo = 1;
21943let isCodeGenOnly = 1;
21944let opNewValue = 1;
21945}
21946def S2_storerinewgp : HInst<
21947(outs),
21948(ins u30_2Imm:$Ii, IntRegs:$Nt8),
21949"memw(gp+#$Ii) = $Nt8.new",
21950tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
21951let Inst{12-11} = 0b10;
21952let Inst{24-21} = 0b0101;
21953let Inst{31-27} = 0b01001;
21954let accessSize = WordAccess;
21955let isNVStore = 1;
21956let isNewValue = 1;
21957let isRestrictNoSlot1Store = 1;
21958let mayStore = 1;
21959let Uses = [GP];
21960let BaseOpcode = "S2_storeriabs";
21961let isPredicable = 1;
21962let opExtendable = 0;
21963let isExtentSigned = 0;
21964let opExtentBits = 18;
21965let opExtentAlign = 2;
21966let opNewValue = 1;
21967}
21968def S2_storew_locked : HInst<
21969(outs PredRegs:$Pd4),
21970(ins IntRegs:$Rs32, IntRegs:$Rt32),
21971"memw_locked($Rs32,$Pd4) = $Rt32",
21972tc_6f42bc60, TypeST>, Enc_c2b48e {
21973let Inst{7-2} = 0b000000;
21974let Inst{13-13} = 0b0;
21975let Inst{31-21} = 0b10100000101;
21976let accessSize = WordAccess;
21977let isPredicateLate = 1;
21978let isSoloAX = 1;
21979let mayStore = 1;
21980}
21981def S2_storew_rl_at_vi : HInst<
21982(outs),
21983(ins IntRegs:$Rs32, IntRegs:$Rt32),
21984"memw_rl($Rs32):at = $Rt32",
21985tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
21986let Inst{7-2} = 0b000010;
21987let Inst{13-13} = 0b0;
21988let Inst{31-21} = 0b10100000101;
21989let accessSize = WordAccess;
21990let isSolo = 1;
21991let mayStore = 1;
21992}
21993def S2_storew_rl_st_vi : HInst<
21994(outs),
21995(ins IntRegs:$Rs32, IntRegs:$Rt32),
21996"memw_rl($Rs32):st = $Rt32",
21997tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
21998let Inst{7-2} = 0b001010;
21999let Inst{13-13} = 0b0;
22000let Inst{31-21} = 0b10100000101;
22001let accessSize = WordAccess;
22002let isSolo = 1;
22003let mayStore = 1;
22004}
22005def S2_svsathb : HInst<
22006(outs IntRegs:$Rd32),
22007(ins IntRegs:$Rs32),
22008"$Rd32 = vsathb($Rs32)",
22009tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22010let Inst{13-5} = 0b000000000;
22011let Inst{31-21} = 0b10001100100;
22012let hasNewValue = 1;
22013let opNewValue = 0;
22014let Defs = [USR_OVF];
22015}
22016def S2_svsathub : HInst<
22017(outs IntRegs:$Rd32),
22018(ins IntRegs:$Rs32),
22019"$Rd32 = vsathub($Rs32)",
22020tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22021let Inst{13-5} = 0b000000010;
22022let Inst{31-21} = 0b10001100100;
22023let hasNewValue = 1;
22024let opNewValue = 0;
22025let Defs = [USR_OVF];
22026}
22027def S2_tableidxb : HInst<
22028(outs IntRegs:$Rx32),
22029(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22030"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
22031tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22032let Inst{31-22} = 0b1000011100;
22033let hasNewValue = 1;
22034let opNewValue = 0;
22035let prefersSlot3 = 1;
22036let Constraints = "$Rx32 = $Rx32in";
22037}
22038def S2_tableidxb_goodsyntax : HInst<
22039(outs IntRegs:$Rx32),
22040(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22041"$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
22042tc_bb831a7c, TypeS_2op> {
22043let hasNewValue = 1;
22044let opNewValue = 0;
22045let isPseudo = 1;
22046let isCodeGenOnly = 1;
22047let Constraints = "$Rx32 = $Rx32in";
22048}
22049def S2_tableidxd : HInst<
22050(outs IntRegs:$Rx32),
22051(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22052"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
22053tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22054let Inst{31-22} = 0b1000011111;
22055let hasNewValue = 1;
22056let opNewValue = 0;
22057let prefersSlot3 = 1;
22058let Constraints = "$Rx32 = $Rx32in";
22059}
22060def S2_tableidxd_goodsyntax : HInst<
22061(outs IntRegs:$Rx32),
22062(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22063"$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
22064tc_bb831a7c, TypeS_2op> {
22065let hasNewValue = 1;
22066let opNewValue = 0;
22067let isPseudo = 1;
22068let Constraints = "$Rx32 = $Rx32in";
22069}
22070def S2_tableidxh : HInst<
22071(outs IntRegs:$Rx32),
22072(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22073"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
22074tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22075let Inst{31-22} = 0b1000011101;
22076let hasNewValue = 1;
22077let opNewValue = 0;
22078let prefersSlot3 = 1;
22079let Constraints = "$Rx32 = $Rx32in";
22080}
22081def S2_tableidxh_goodsyntax : HInst<
22082(outs IntRegs:$Rx32),
22083(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22084"$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
22085tc_bb831a7c, TypeS_2op> {
22086let hasNewValue = 1;
22087let opNewValue = 0;
22088let isPseudo = 1;
22089let Constraints = "$Rx32 = $Rx32in";
22090}
22091def S2_tableidxw : HInst<
22092(outs IntRegs:$Rx32),
22093(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22094"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
22095tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22096let Inst{31-22} = 0b1000011110;
22097let hasNewValue = 1;
22098let opNewValue = 0;
22099let prefersSlot3 = 1;
22100let Constraints = "$Rx32 = $Rx32in";
22101}
22102def S2_tableidxw_goodsyntax : HInst<
22103(outs IntRegs:$Rx32),
22104(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22105"$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
22106tc_bb831a7c, TypeS_2op> {
22107let hasNewValue = 1;
22108let opNewValue = 0;
22109let isPseudo = 1;
22110let Constraints = "$Rx32 = $Rx32in";
22111}
22112def S2_togglebit_i : HInst<
22113(outs IntRegs:$Rd32),
22114(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22115"$Rd32 = togglebit($Rs32,#$Ii)",
22116tc_5da50c4b, TypeS_2op>, Enc_a05677 {
22117let Inst{7-5} = 0b010;
22118let Inst{13-13} = 0b0;
22119let Inst{31-21} = 0b10001100110;
22120let hasNewValue = 1;
22121let opNewValue = 0;
22122}
22123def S2_togglebit_r : HInst<
22124(outs IntRegs:$Rd32),
22125(ins IntRegs:$Rs32, IntRegs:$Rt32),
22126"$Rd32 = togglebit($Rs32,$Rt32)",
22127tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
22128let Inst{7-5} = 0b100;
22129let Inst{13-13} = 0b0;
22130let Inst{31-21} = 0b11000110100;
22131let hasNewValue = 1;
22132let opNewValue = 0;
22133}
22134def S2_tstbit_i : HInst<
22135(outs PredRegs:$Pd4),
22136(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22137"$Pd4 = tstbit($Rs32,#$Ii)",
22138tc_a1297125, TypeS_2op>, Enc_83ee64 {
22139let Inst{7-2} = 0b000000;
22140let Inst{13-13} = 0b0;
22141let Inst{31-21} = 0b10000101000;
22142}
22143def S2_tstbit_r : HInst<
22144(outs PredRegs:$Pd4),
22145(ins IntRegs:$Rs32, IntRegs:$Rt32),
22146"$Pd4 = tstbit($Rs32,$Rt32)",
22147tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22148let Inst{7-2} = 0b000000;
22149let Inst{13-13} = 0b0;
22150let Inst{31-21} = 0b11000111000;
22151}
22152def S2_valignib : HInst<
22153(outs DoubleRegs:$Rdd32),
22154(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
22155"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
22156tc_6fc5dbea, TypeS_3op>, Enc_729ff7 {
22157let Inst{13-13} = 0b0;
22158let Inst{31-21} = 0b11000000000;
22159}
22160def S2_valignrb : HInst<
22161(outs DoubleRegs:$Rdd32),
22162(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
22163"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
22164tc_6fc5dbea, TypeS_3op>, Enc_8c6530 {
22165let Inst{7-7} = 0b0;
22166let Inst{13-13} = 0b0;
22167let Inst{31-21} = 0b11000010000;
22168}
22169def S2_vcnegh : HInst<
22170(outs DoubleRegs:$Rdd32),
22171(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22172"$Rdd32 = vcnegh($Rss32,$Rt32)",
22173tc_8a825db2, TypeS_3op>, Enc_927852 {
22174let Inst{7-5} = 0b010;
22175let Inst{13-13} = 0b0;
22176let Inst{31-21} = 0b11000011110;
22177let prefersSlot3 = 1;
22178let Defs = [USR_OVF];
22179}
22180def S2_vcrotate : HInst<
22181(outs DoubleRegs:$Rdd32),
22182(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22183"$Rdd32 = vcrotate($Rss32,$Rt32)",
22184tc_0dfac0a7, TypeS_3op>, Enc_927852 {
22185let Inst{7-5} = 0b000;
22186let Inst{13-13} = 0b0;
22187let Inst{31-21} = 0b11000011110;
22188let prefersSlot3 = 1;
22189let Defs = [USR_OVF];
22190}
22191def S2_vrcnegh : HInst<
22192(outs DoubleRegs:$Rxx32),
22193(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
22194"$Rxx32 += vrcnegh($Rss32,$Rt32)",
22195tc_7f8ae742, TypeS_3op>, Enc_1aa186 {
22196let Inst{7-5} = 0b111;
22197let Inst{13-13} = 0b1;
22198let Inst{31-21} = 0b11001011001;
22199let prefersSlot3 = 1;
22200let Constraints = "$Rxx32 = $Rxx32in";
22201}
22202def S2_vrndpackwh : HInst<
22203(outs IntRegs:$Rd32),
22204(ins DoubleRegs:$Rss32),
22205"$Rd32 = vrndwh($Rss32)",
22206tc_e3d699e3, TypeS_2op>, Enc_90cd8b {
22207let Inst{13-5} = 0b000000100;
22208let Inst{31-21} = 0b10001000100;
22209let hasNewValue = 1;
22210let opNewValue = 0;
22211let prefersSlot3 = 1;
22212}
22213def S2_vrndpackwhs : HInst<
22214(outs IntRegs:$Rd32),
22215(ins DoubleRegs:$Rss32),
22216"$Rd32 = vrndwh($Rss32):sat",
22217tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
22218let Inst{13-5} = 0b000000110;
22219let Inst{31-21} = 0b10001000100;
22220let hasNewValue = 1;
22221let opNewValue = 0;
22222let prefersSlot3 = 1;
22223let Defs = [USR_OVF];
22224}
22225def S2_vsathb : HInst<
22226(outs IntRegs:$Rd32),
22227(ins DoubleRegs:$Rss32),
22228"$Rd32 = vsathb($Rss32)",
22229tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22230let Inst{13-5} = 0b000000110;
22231let Inst{31-21} = 0b10001000000;
22232let hasNewValue = 1;
22233let opNewValue = 0;
22234let Defs = [USR_OVF];
22235}
22236def S2_vsathb_nopack : HInst<
22237(outs DoubleRegs:$Rdd32),
22238(ins DoubleRegs:$Rss32),
22239"$Rdd32 = vsathb($Rss32)",
22240tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22241let Inst{13-5} = 0b000000111;
22242let Inst{31-21} = 0b10000000000;
22243let Defs = [USR_OVF];
22244}
22245def S2_vsathub : HInst<
22246(outs IntRegs:$Rd32),
22247(ins DoubleRegs:$Rss32),
22248"$Rd32 = vsathub($Rss32)",
22249tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22250let Inst{13-5} = 0b000000000;
22251let Inst{31-21} = 0b10001000000;
22252let hasNewValue = 1;
22253let opNewValue = 0;
22254let Defs = [USR_OVF];
22255}
22256def S2_vsathub_nopack : HInst<
22257(outs DoubleRegs:$Rdd32),
22258(ins DoubleRegs:$Rss32),
22259"$Rdd32 = vsathub($Rss32)",
22260tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22261let Inst{13-5} = 0b000000100;
22262let Inst{31-21} = 0b10000000000;
22263let Defs = [USR_OVF];
22264}
22265def S2_vsatwh : HInst<
22266(outs IntRegs:$Rd32),
22267(ins DoubleRegs:$Rss32),
22268"$Rd32 = vsatwh($Rss32)",
22269tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22270let Inst{13-5} = 0b000000010;
22271let Inst{31-21} = 0b10001000000;
22272let hasNewValue = 1;
22273let opNewValue = 0;
22274let Defs = [USR_OVF];
22275}
22276def S2_vsatwh_nopack : HInst<
22277(outs DoubleRegs:$Rdd32),
22278(ins DoubleRegs:$Rss32),
22279"$Rdd32 = vsatwh($Rss32)",
22280tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22281let Inst{13-5} = 0b000000110;
22282let Inst{31-21} = 0b10000000000;
22283let Defs = [USR_OVF];
22284}
22285def S2_vsatwuh : HInst<
22286(outs IntRegs:$Rd32),
22287(ins DoubleRegs:$Rss32),
22288"$Rd32 = vsatwuh($Rss32)",
22289tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22290let Inst{13-5} = 0b000000100;
22291let Inst{31-21} = 0b10001000000;
22292let hasNewValue = 1;
22293let opNewValue = 0;
22294let Defs = [USR_OVF];
22295}
22296def S2_vsatwuh_nopack : HInst<
22297(outs DoubleRegs:$Rdd32),
22298(ins DoubleRegs:$Rss32),
22299"$Rdd32 = vsatwuh($Rss32)",
22300tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22301let Inst{13-5} = 0b000000101;
22302let Inst{31-21} = 0b10000000000;
22303let Defs = [USR_OVF];
22304}
22305def S2_vsplatrb : HInst<
22306(outs IntRegs:$Rd32),
22307(ins IntRegs:$Rs32),
22308"$Rd32 = vsplatb($Rs32)",
22309tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22310let Inst{13-5} = 0b000000111;
22311let Inst{31-21} = 0b10001100010;
22312let hasNewValue = 1;
22313let opNewValue = 0;
22314let isAsCheapAsAMove = 1;
22315let isReMaterializable = 1;
22316}
22317def S2_vsplatrh : HInst<
22318(outs DoubleRegs:$Rdd32),
22319(ins IntRegs:$Rs32),
22320"$Rdd32 = vsplath($Rs32)",
22321tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22322let Inst{13-5} = 0b000000010;
22323let Inst{31-21} = 0b10000100010;
22324let isAsCheapAsAMove = 1;
22325let isReMaterializable = 1;
22326}
22327def S2_vspliceib : HInst<
22328(outs DoubleRegs:$Rdd32),
22329(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
22330"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
22331tc_6fc5dbea, TypeS_3op>, Enc_d50cd3 {
22332let Inst{13-13} = 0b0;
22333let Inst{31-21} = 0b11000000100;
22334}
22335def S2_vsplicerb : HInst<
22336(outs DoubleRegs:$Rdd32),
22337(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
22338"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
22339tc_6fc5dbea, TypeS_3op>, Enc_dbd70c {
22340let Inst{7-7} = 0b0;
22341let Inst{13-13} = 0b0;
22342let Inst{31-21} = 0b11000010100;
22343}
22344def S2_vsxtbh : HInst<
22345(outs DoubleRegs:$Rdd32),
22346(ins IntRegs:$Rs32),
22347"$Rdd32 = vsxtbh($Rs32)",
22348tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22349let Inst{13-5} = 0b000000000;
22350let Inst{31-21} = 0b10000100000;
22351let isAsCheapAsAMove = 1;
22352let isReMaterializable = 1;
22353}
22354def S2_vsxthw : HInst<
22355(outs DoubleRegs:$Rdd32),
22356(ins IntRegs:$Rs32),
22357"$Rdd32 = vsxthw($Rs32)",
22358tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22359let Inst{13-5} = 0b000000100;
22360let Inst{31-21} = 0b10000100000;
22361let isAsCheapAsAMove = 1;
22362let isReMaterializable = 1;
22363}
22364def S2_vtrunehb : HInst<
22365(outs IntRegs:$Rd32),
22366(ins DoubleRegs:$Rss32),
22367"$Rd32 = vtrunehb($Rss32)",
22368tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22369let Inst{13-5} = 0b000000010;
22370let Inst{31-21} = 0b10001000100;
22371let hasNewValue = 1;
22372let opNewValue = 0;
22373}
22374def S2_vtrunewh : HInst<
22375(outs DoubleRegs:$Rdd32),
22376(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22377"$Rdd32 = vtrunewh($Rss32,$Rtt32)",
22378tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22379let Inst{7-5} = 0b010;
22380let Inst{13-13} = 0b0;
22381let Inst{31-21} = 0b11000001100;
22382}
22383def S2_vtrunohb : HInst<
22384(outs IntRegs:$Rd32),
22385(ins DoubleRegs:$Rss32),
22386"$Rd32 = vtrunohb($Rss32)",
22387tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22388let Inst{13-5} = 0b000000000;
22389let Inst{31-21} = 0b10001000100;
22390let hasNewValue = 1;
22391let opNewValue = 0;
22392}
22393def S2_vtrunowh : HInst<
22394(outs DoubleRegs:$Rdd32),
22395(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22396"$Rdd32 = vtrunowh($Rss32,$Rtt32)",
22397tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22398let Inst{7-5} = 0b100;
22399let Inst{13-13} = 0b0;
22400let Inst{31-21} = 0b11000001100;
22401}
22402def S2_vzxtbh : HInst<
22403(outs DoubleRegs:$Rdd32),
22404(ins IntRegs:$Rs32),
22405"$Rdd32 = vzxtbh($Rs32)",
22406tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22407let Inst{13-5} = 0b000000010;
22408let Inst{31-21} = 0b10000100000;
22409let isAsCheapAsAMove = 1;
22410let isReMaterializable = 1;
22411}
22412def S2_vzxthw : HInst<
22413(outs DoubleRegs:$Rdd32),
22414(ins IntRegs:$Rs32),
22415"$Rdd32 = vzxthw($Rs32)",
22416tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22417let Inst{13-5} = 0b000000110;
22418let Inst{31-21} = 0b10000100000;
22419let isAsCheapAsAMove = 1;
22420let isReMaterializable = 1;
22421}
22422def S4_addaddi : HInst<
22423(outs IntRegs:$Rd32),
22424(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
22425"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
22426tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
22427let Inst{31-23} = 0b110110110;
22428let hasNewValue = 1;
22429let opNewValue = 0;
22430let prefersSlot3 = 1;
22431let isExtendable = 1;
22432let opExtendable = 3;
22433let isExtentSigned = 1;
22434let opExtentBits = 6;
22435let opExtentAlign = 0;
22436}
22437def S4_addi_asl_ri : HInst<
22438(outs IntRegs:$Rx32),
22439(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22440"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
22441tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22442let Inst{2-0} = 0b100;
22443let Inst{4-4} = 0b0;
22444let Inst{31-24} = 0b11011110;
22445let hasNewValue = 1;
22446let opNewValue = 0;
22447let prefersSlot3 = 1;
22448let isExtendable = 1;
22449let opExtendable = 1;
22450let isExtentSigned = 0;
22451let opExtentBits = 8;
22452let opExtentAlign = 0;
22453let Constraints = "$Rx32 = $Rx32in";
22454}
22455def S4_addi_lsr_ri : HInst<
22456(outs IntRegs:$Rx32),
22457(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22458"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
22459tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22460let Inst{2-0} = 0b100;
22461let Inst{4-4} = 0b1;
22462let Inst{31-24} = 0b11011110;
22463let hasNewValue = 1;
22464let opNewValue = 0;
22465let prefersSlot3 = 1;
22466let isExtendable = 1;
22467let opExtendable = 1;
22468let isExtentSigned = 0;
22469let opExtentBits = 8;
22470let opExtentAlign = 0;
22471let Constraints = "$Rx32 = $Rx32in";
22472}
22473def S4_andi_asl_ri : HInst<
22474(outs IntRegs:$Rx32),
22475(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22476"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
22477tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22478let Inst{2-0} = 0b000;
22479let Inst{4-4} = 0b0;
22480let Inst{31-24} = 0b11011110;
22481let hasNewValue = 1;
22482let opNewValue = 0;
22483let prefersSlot3 = 1;
22484let isExtendable = 1;
22485let opExtendable = 1;
22486let isExtentSigned = 0;
22487let opExtentBits = 8;
22488let opExtentAlign = 0;
22489let Constraints = "$Rx32 = $Rx32in";
22490}
22491def S4_andi_lsr_ri : HInst<
22492(outs IntRegs:$Rx32),
22493(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22494"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
22495tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22496let Inst{2-0} = 0b000;
22497let Inst{4-4} = 0b1;
22498let Inst{31-24} = 0b11011110;
22499let hasNewValue = 1;
22500let opNewValue = 0;
22501let prefersSlot3 = 1;
22502let isExtendable = 1;
22503let opExtendable = 1;
22504let isExtentSigned = 0;
22505let opExtentBits = 8;
22506let opExtentAlign = 0;
22507let Constraints = "$Rx32 = $Rx32in";
22508}
22509def S4_clbaddi : HInst<
22510(outs IntRegs:$Rd32),
22511(ins IntRegs:$Rs32, s6_0Imm:$Ii),
22512"$Rd32 = add(clb($Rs32),#$Ii)",
22513tc_a08b630b, TypeS_2op>, Enc_9fae8a {
22514let Inst{7-5} = 0b000;
22515let Inst{31-21} = 0b10001100001;
22516let hasNewValue = 1;
22517let opNewValue = 0;
22518let prefersSlot3 = 1;
22519}
22520def S4_clbpaddi : HInst<
22521(outs IntRegs:$Rd32),
22522(ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
22523"$Rd32 = add(clb($Rss32),#$Ii)",
22524tc_a08b630b, TypeS_2op>, Enc_a1640c {
22525let Inst{7-5} = 0b010;
22526let Inst{31-21} = 0b10001000011;
22527let hasNewValue = 1;
22528let opNewValue = 0;
22529let prefersSlot3 = 1;
22530}
22531def S4_clbpnorm : HInst<
22532(outs IntRegs:$Rd32),
22533(ins DoubleRegs:$Rss32),
22534"$Rd32 = normamt($Rss32)",
22535tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
22536let Inst{13-5} = 0b000000000;
22537let Inst{31-21} = 0b10001000011;
22538let hasNewValue = 1;
22539let opNewValue = 0;
22540let prefersSlot3 = 1;
22541}
22542def S4_extract : HInst<
22543(outs IntRegs:$Rd32),
22544(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
22545"$Rd32 = extract($Rs32,#$Ii,#$II)",
22546tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
22547let Inst{13-13} = 0b0;
22548let Inst{31-23} = 0b100011011;
22549let hasNewValue = 1;
22550let opNewValue = 0;
22551let prefersSlot3 = 1;
22552}
22553def S4_extract_rp : HInst<
22554(outs IntRegs:$Rd32),
22555(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
22556"$Rd32 = extract($Rs32,$Rtt32)",
22557tc_a08b630b, TypeS_3op>, Enc_e07374 {
22558let Inst{7-5} = 0b010;
22559let Inst{13-13} = 0b0;
22560let Inst{31-21} = 0b11001001000;
22561let hasNewValue = 1;
22562let opNewValue = 0;
22563let prefersSlot3 = 1;
22564}
22565def S4_extractp : HInst<
22566(outs DoubleRegs:$Rdd32),
22567(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
22568"$Rdd32 = extract($Rss32,#$Ii,#$II)",
22569tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
22570let Inst{31-24} = 0b10001010;
22571let prefersSlot3 = 1;
22572}
22573def S4_extractp_rp : HInst<
22574(outs DoubleRegs:$Rdd32),
22575(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22576"$Rdd32 = extract($Rss32,$Rtt32)",
22577tc_a08b630b, TypeS_3op>, Enc_a56825 {
22578let Inst{7-5} = 0b100;
22579let Inst{13-13} = 0b0;
22580let Inst{31-21} = 0b11000001110;
22581let prefersSlot3 = 1;
22582}
22583def S4_lsli : HInst<
22584(outs IntRegs:$Rd32),
22585(ins s6_0Imm:$Ii, IntRegs:$Rt32),
22586"$Rd32 = lsl(#$Ii,$Rt32)",
22587tc_5da50c4b, TypeS_3op>, Enc_fef969 {
22588let Inst{7-6} = 0b11;
22589let Inst{13-13} = 0b0;
22590let Inst{31-21} = 0b11000110100;
22591let hasNewValue = 1;
22592let opNewValue = 0;
22593}
22594def S4_ntstbit_i : HInst<
22595(outs PredRegs:$Pd4),
22596(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22597"$Pd4 = !tstbit($Rs32,#$Ii)",
22598tc_a1297125, TypeS_2op>, Enc_83ee64 {
22599let Inst{7-2} = 0b000000;
22600let Inst{13-13} = 0b0;
22601let Inst{31-21} = 0b10000101001;
22602}
22603def S4_ntstbit_r : HInst<
22604(outs PredRegs:$Pd4),
22605(ins IntRegs:$Rs32, IntRegs:$Rt32),
22606"$Pd4 = !tstbit($Rs32,$Rt32)",
22607tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22608let Inst{7-2} = 0b000000;
22609let Inst{13-13} = 0b0;
22610let Inst{31-21} = 0b11000111001;
22611}
22612def S4_or_andi : HInst<
22613(outs IntRegs:$Rx32),
22614(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22615"$Rx32 |= and($Rs32,#$Ii)",
22616tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22617let Inst{31-22} = 0b1101101000;
22618let hasNewValue = 1;
22619let opNewValue = 0;
22620let prefersSlot3 = 1;
22621let InputType = "imm";
22622let isExtendable = 1;
22623let opExtendable = 3;
22624let isExtentSigned = 1;
22625let opExtentBits = 10;
22626let opExtentAlign = 0;
22627let Constraints = "$Rx32 = $Rx32in";
22628}
22629def S4_or_andix : HInst<
22630(outs IntRegs:$Rx32),
22631(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
22632"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22633tc_a4e22bbd, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> {
22634let Inst{31-22} = 0b1101101001;
22635let hasNewValue = 1;
22636let opNewValue = 0;
22637let prefersSlot3 = 1;
22638let isExtendable = 1;
22639let opExtendable = 3;
22640let isExtentSigned = 1;
22641let opExtentBits = 10;
22642let opExtentAlign = 0;
22643let Constraints = "$Rx32 = $Rx32in";
22644}
22645def S4_or_ori : HInst<
22646(outs IntRegs:$Rx32),
22647(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22648"$Rx32 |= or($Rs32,#$Ii)",
22649tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22650let Inst{31-22} = 0b1101101010;
22651let hasNewValue = 1;
22652let opNewValue = 0;
22653let prefersSlot3 = 1;
22654let InputType = "imm";
22655let isExtendable = 1;
22656let opExtendable = 3;
22657let isExtentSigned = 1;
22658let opExtentBits = 10;
22659let opExtentAlign = 0;
22660let Constraints = "$Rx32 = $Rx32in";
22661}
22662def S4_ori_asl_ri : HInst<
22663(outs IntRegs:$Rx32),
22664(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22665"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22666tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22667let Inst{2-0} = 0b010;
22668let Inst{4-4} = 0b0;
22669let Inst{31-24} = 0b11011110;
22670let hasNewValue = 1;
22671let opNewValue = 0;
22672let prefersSlot3 = 1;
22673let isExtendable = 1;
22674let opExtendable = 1;
22675let isExtentSigned = 0;
22676let opExtentBits = 8;
22677let opExtentAlign = 0;
22678let Constraints = "$Rx32 = $Rx32in";
22679}
22680def S4_ori_lsr_ri : HInst<
22681(outs IntRegs:$Rx32),
22682(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22683"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22684tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22685let Inst{2-0} = 0b010;
22686let Inst{4-4} = 0b1;
22687let Inst{31-24} = 0b11011110;
22688let hasNewValue = 1;
22689let opNewValue = 0;
22690let prefersSlot3 = 1;
22691let isExtendable = 1;
22692let opExtendable = 1;
22693let isExtentSigned = 0;
22694let opExtentBits = 8;
22695let opExtentAlign = 0;
22696let Constraints = "$Rx32 = $Rx32in";
22697}
22698def S4_parity : HInst<
22699(outs IntRegs:$Rd32),
22700(ins IntRegs:$Rs32, IntRegs:$Rt32),
22701"$Rd32 = parity($Rs32,$Rt32)",
22702tc_a08b630b, TypeALU64>, Enc_5ab2be {
22703let Inst{7-5} = 0b000;
22704let Inst{13-13} = 0b0;
22705let Inst{31-21} = 0b11010101111;
22706let hasNewValue = 1;
22707let opNewValue = 0;
22708let prefersSlot3 = 1;
22709}
22710def S4_pstorerbf_abs : HInst<
22711(outs),
22712(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22713"if (!$Pv4) memb(#$Ii) = $Rt32",
22714tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
22715let Inst{2-2} = 0b1;
22716let Inst{7-7} = 0b1;
22717let Inst{13-13} = 0b0;
22718let Inst{31-18} = 0b10101111000000;
22719let isPredicated = 1;
22720let isPredicatedFalse = 1;
22721let addrMode = Absolute;
22722let accessSize = ByteAccess;
22723let isExtended = 1;
22724let mayStore = 1;
22725let BaseOpcode = "S2_storerbabs";
22726let CextOpcode = "S2_storerb";
22727let isNVStorable = 1;
22728let DecoderNamespace = "MustExtend";
22729let isExtendable = 1;
22730let opExtendable = 1;
22731let isExtentSigned = 0;
22732let opExtentBits = 6;
22733let opExtentAlign = 0;
22734}
22735def S4_pstorerbf_rr : HInst<
22736(outs),
22737(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22738"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22739tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
22740let Inst{31-21} = 0b00110101000;
22741let isPredicated = 1;
22742let isPredicatedFalse = 1;
22743let addrMode = BaseRegOffset;
22744let accessSize = ByteAccess;
22745let mayStore = 1;
22746let BaseOpcode = "S4_storerb_rr";
22747let CextOpcode = "S2_storerb";
22748let InputType = "reg";
22749let isNVStorable = 1;
22750}
22751def S4_pstorerbfnew_abs : HInst<
22752(outs),
22753(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22754"if (!$Pv4.new) memb(#$Ii) = $Rt32",
22755tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
22756let Inst{2-2} = 0b1;
22757let Inst{7-7} = 0b1;
22758let Inst{13-13} = 0b1;
22759let Inst{31-18} = 0b10101111000000;
22760let isPredicated = 1;
22761let isPredicatedFalse = 1;
22762let addrMode = Absolute;
22763let accessSize = ByteAccess;
22764let isPredicatedNew = 1;
22765let isExtended = 1;
22766let mayStore = 1;
22767let BaseOpcode = "S2_storerbabs";
22768let CextOpcode = "S2_storerb";
22769let isNVStorable = 1;
22770let DecoderNamespace = "MustExtend";
22771let isExtendable = 1;
22772let opExtendable = 1;
22773let isExtentSigned = 0;
22774let opExtentBits = 6;
22775let opExtentAlign = 0;
22776}
22777def S4_pstorerbfnew_io : HInst<
22778(outs),
22779(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22780"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22781tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22782let Inst{2-2} = 0b0;
22783let Inst{31-21} = 0b01000110000;
22784let isPredicated = 1;
22785let isPredicatedFalse = 1;
22786let addrMode = BaseImmOffset;
22787let accessSize = ByteAccess;
22788let isPredicatedNew = 1;
22789let mayStore = 1;
22790let BaseOpcode = "S2_storerb_io";
22791let CextOpcode = "S2_storerb";
22792let InputType = "imm";
22793let isNVStorable = 1;
22794let isExtendable = 1;
22795let opExtendable = 2;
22796let isExtentSigned = 0;
22797let opExtentBits = 6;
22798let opExtentAlign = 0;
22799}
22800def S4_pstorerbfnew_rr : HInst<
22801(outs),
22802(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22803"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22804tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
22805let Inst{31-21} = 0b00110111000;
22806let isPredicated = 1;
22807let isPredicatedFalse = 1;
22808let addrMode = BaseRegOffset;
22809let accessSize = ByteAccess;
22810let isPredicatedNew = 1;
22811let mayStore = 1;
22812let BaseOpcode = "S4_storerb_rr";
22813let CextOpcode = "S2_storerb";
22814let InputType = "reg";
22815let isNVStorable = 1;
22816}
22817def S4_pstorerbfnew_zomap : HInst<
22818(outs),
22819(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22820"if (!$Pv4.new) memb($Rs32) = $Rt32",
22821tc_a2b365d2, TypeMAPPING> {
22822let isPseudo = 1;
22823let isCodeGenOnly = 1;
22824}
22825def S4_pstorerbnewf_abs : HInst<
22826(outs),
22827(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22828"if (!$Pv4) memb(#$Ii) = $Nt8.new",
22829tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22830let Inst{2-2} = 0b1;
22831let Inst{7-7} = 0b1;
22832let Inst{13-11} = 0b000;
22833let Inst{31-18} = 0b10101111101000;
22834let isPredicated = 1;
22835let isPredicatedFalse = 1;
22836let addrMode = Absolute;
22837let accessSize = ByteAccess;
22838let isNVStore = 1;
22839let isNewValue = 1;
22840let isExtended = 1;
22841let isRestrictNoSlot1Store = 1;
22842let mayStore = 1;
22843let BaseOpcode = "S2_storerbabs";
22844let CextOpcode = "S2_storerb";
22845let DecoderNamespace = "MustExtend";
22846let isExtendable = 1;
22847let opExtendable = 1;
22848let isExtentSigned = 0;
22849let opExtentBits = 6;
22850let opExtentAlign = 0;
22851let opNewValue = 2;
22852}
22853def S4_pstorerbnewf_rr : HInst<
22854(outs),
22855(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22856"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22857tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22858let Inst{4-3} = 0b00;
22859let Inst{31-21} = 0b00110101101;
22860let isPredicated = 1;
22861let isPredicatedFalse = 1;
22862let addrMode = BaseRegOffset;
22863let accessSize = ByteAccess;
22864let isNVStore = 1;
22865let isNewValue = 1;
22866let isRestrictNoSlot1Store = 1;
22867let mayStore = 1;
22868let BaseOpcode = "S4_storerb_rr";
22869let CextOpcode = "S2_storerb";
22870let InputType = "reg";
22871let opNewValue = 4;
22872}
22873def S4_pstorerbnewfnew_abs : HInst<
22874(outs),
22875(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22876"if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
22877tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22878let Inst{2-2} = 0b1;
22879let Inst{7-7} = 0b1;
22880let Inst{13-11} = 0b100;
22881let Inst{31-18} = 0b10101111101000;
22882let isPredicated = 1;
22883let isPredicatedFalse = 1;
22884let addrMode = Absolute;
22885let accessSize = ByteAccess;
22886let isNVStore = 1;
22887let isPredicatedNew = 1;
22888let isNewValue = 1;
22889let isExtended = 1;
22890let isRestrictNoSlot1Store = 1;
22891let mayStore = 1;
22892let BaseOpcode = "S2_storerbabs";
22893let CextOpcode = "S2_storerb";
22894let DecoderNamespace = "MustExtend";
22895let isExtendable = 1;
22896let opExtendable = 1;
22897let isExtentSigned = 0;
22898let opExtentBits = 6;
22899let opExtentAlign = 0;
22900let opNewValue = 2;
22901}
22902def S4_pstorerbnewfnew_io : HInst<
22903(outs),
22904(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22905"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22906tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
22907let Inst{2-2} = 0b0;
22908let Inst{12-11} = 0b00;
22909let Inst{31-21} = 0b01000110101;
22910let isPredicated = 1;
22911let isPredicatedFalse = 1;
22912let addrMode = BaseImmOffset;
22913let accessSize = ByteAccess;
22914let isNVStore = 1;
22915let isPredicatedNew = 1;
22916let isNewValue = 1;
22917let isRestrictNoSlot1Store = 1;
22918let mayStore = 1;
22919let BaseOpcode = "S2_storerb_io";
22920let CextOpcode = "S2_storerb";
22921let InputType = "imm";
22922let isExtendable = 1;
22923let opExtendable = 2;
22924let isExtentSigned = 0;
22925let opExtentBits = 6;
22926let opExtentAlign = 0;
22927let opNewValue = 3;
22928}
22929def S4_pstorerbnewfnew_rr : HInst<
22930(outs),
22931(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22932"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22933tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
22934let Inst{4-3} = 0b00;
22935let Inst{31-21} = 0b00110111101;
22936let isPredicated = 1;
22937let isPredicatedFalse = 1;
22938let addrMode = BaseRegOffset;
22939let accessSize = ByteAccess;
22940let isNVStore = 1;
22941let isPredicatedNew = 1;
22942let isNewValue = 1;
22943let isRestrictNoSlot1Store = 1;
22944let mayStore = 1;
22945let BaseOpcode = "S4_storerb_rr";
22946let CextOpcode = "S2_storerb";
22947let InputType = "reg";
22948let opNewValue = 4;
22949}
22950def S4_pstorerbnewfnew_zomap : HInst<
22951(outs),
22952(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22953"if (!$Pv4.new) memb($Rs32) = $Nt8.new",
22954tc_92240447, TypeMAPPING> {
22955let isPseudo = 1;
22956let isCodeGenOnly = 1;
22957let opNewValue = 2;
22958}
22959def S4_pstorerbnewt_abs : HInst<
22960(outs),
22961(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22962"if ($Pv4) memb(#$Ii) = $Nt8.new",
22963tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22964let Inst{2-2} = 0b0;
22965let Inst{7-7} = 0b1;
22966let Inst{13-11} = 0b000;
22967let Inst{31-18} = 0b10101111101000;
22968let isPredicated = 1;
22969let addrMode = Absolute;
22970let accessSize = ByteAccess;
22971let isNVStore = 1;
22972let isNewValue = 1;
22973let isExtended = 1;
22974let isRestrictNoSlot1Store = 1;
22975let mayStore = 1;
22976let BaseOpcode = "S2_storerbabs";
22977let CextOpcode = "S2_storerb";
22978let DecoderNamespace = "MustExtend";
22979let isExtendable = 1;
22980let opExtendable = 1;
22981let isExtentSigned = 0;
22982let opExtentBits = 6;
22983let opExtentAlign = 0;
22984let opNewValue = 2;
22985}
22986def S4_pstorerbnewt_rr : HInst<
22987(outs),
22988(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22989"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22990tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22991let Inst{4-3} = 0b00;
22992let Inst{31-21} = 0b00110100101;
22993let isPredicated = 1;
22994let addrMode = BaseRegOffset;
22995let accessSize = ByteAccess;
22996let isNVStore = 1;
22997let isNewValue = 1;
22998let isRestrictNoSlot1Store = 1;
22999let mayStore = 1;
23000let BaseOpcode = "S4_storerb_rr";
23001let CextOpcode = "S2_storerb";
23002let InputType = "reg";
23003let opNewValue = 4;
23004}
23005def S4_pstorerbnewtnew_abs : HInst<
23006(outs),
23007(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23008"if ($Pv4.new) memb(#$Ii) = $Nt8.new",
23009tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23010let Inst{2-2} = 0b0;
23011let Inst{7-7} = 0b1;
23012let Inst{13-11} = 0b100;
23013let Inst{31-18} = 0b10101111101000;
23014let isPredicated = 1;
23015let addrMode = Absolute;
23016let accessSize = ByteAccess;
23017let isNVStore = 1;
23018let isPredicatedNew = 1;
23019let isNewValue = 1;
23020let isExtended = 1;
23021let isRestrictNoSlot1Store = 1;
23022let mayStore = 1;
23023let BaseOpcode = "S2_storerbabs";
23024let CextOpcode = "S2_storerb";
23025let DecoderNamespace = "MustExtend";
23026let isExtendable = 1;
23027let opExtendable = 1;
23028let isExtentSigned = 0;
23029let opExtentBits = 6;
23030let opExtentAlign = 0;
23031let opNewValue = 2;
23032}
23033def S4_pstorerbnewtnew_io : HInst<
23034(outs),
23035(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
23036"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
23037tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
23038let Inst{2-2} = 0b0;
23039let Inst{12-11} = 0b00;
23040let Inst{31-21} = 0b01000010101;
23041let isPredicated = 1;
23042let addrMode = BaseImmOffset;
23043let accessSize = ByteAccess;
23044let isNVStore = 1;
23045let isPredicatedNew = 1;
23046let isNewValue = 1;
23047let isRestrictNoSlot1Store = 1;
23048let mayStore = 1;
23049let BaseOpcode = "S2_storerb_io";
23050let CextOpcode = "S2_storerb";
23051let InputType = "imm";
23052let isExtendable = 1;
23053let opExtendable = 2;
23054let isExtentSigned = 0;
23055let opExtentBits = 6;
23056let opExtentAlign = 0;
23057let opNewValue = 3;
23058}
23059def S4_pstorerbnewtnew_rr : HInst<
23060(outs),
23061(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23062"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23063tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23064let Inst{4-3} = 0b00;
23065let Inst{31-21} = 0b00110110101;
23066let isPredicated = 1;
23067let addrMode = BaseRegOffset;
23068let accessSize = ByteAccess;
23069let isNVStore = 1;
23070let isPredicatedNew = 1;
23071let isNewValue = 1;
23072let isRestrictNoSlot1Store = 1;
23073let mayStore = 1;
23074let BaseOpcode = "S4_storerb_rr";
23075let CextOpcode = "S2_storerb";
23076let InputType = "reg";
23077let opNewValue = 4;
23078}
23079def S4_pstorerbnewtnew_zomap : HInst<
23080(outs),
23081(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23082"if ($Pv4.new) memb($Rs32) = $Nt8.new",
23083tc_92240447, TypeMAPPING> {
23084let isPseudo = 1;
23085let isCodeGenOnly = 1;
23086let opNewValue = 2;
23087}
23088def S4_pstorerbt_abs : HInst<
23089(outs),
23090(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23091"if ($Pv4) memb(#$Ii) = $Rt32",
23092tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23093let Inst{2-2} = 0b0;
23094let Inst{7-7} = 0b1;
23095let Inst{13-13} = 0b0;
23096let Inst{31-18} = 0b10101111000000;
23097let isPredicated = 1;
23098let addrMode = Absolute;
23099let accessSize = ByteAccess;
23100let isExtended = 1;
23101let mayStore = 1;
23102let BaseOpcode = "S2_storerbabs";
23103let CextOpcode = "S2_storerb";
23104let isNVStorable = 1;
23105let DecoderNamespace = "MustExtend";
23106let isExtendable = 1;
23107let opExtendable = 1;
23108let isExtentSigned = 0;
23109let opExtentBits = 6;
23110let opExtentAlign = 0;
23111}
23112def S4_pstorerbt_rr : HInst<
23113(outs),
23114(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23115"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23116tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23117let Inst{31-21} = 0b00110100000;
23118let isPredicated = 1;
23119let addrMode = BaseRegOffset;
23120let accessSize = ByteAccess;
23121let mayStore = 1;
23122let BaseOpcode = "S4_storerb_rr";
23123let CextOpcode = "S2_storerb";
23124let InputType = "reg";
23125let isNVStorable = 1;
23126}
23127def S4_pstorerbtnew_abs : HInst<
23128(outs),
23129(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23130"if ($Pv4.new) memb(#$Ii) = $Rt32",
23131tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23132let Inst{2-2} = 0b0;
23133let Inst{7-7} = 0b1;
23134let Inst{13-13} = 0b1;
23135let Inst{31-18} = 0b10101111000000;
23136let isPredicated = 1;
23137let addrMode = Absolute;
23138let accessSize = ByteAccess;
23139let isPredicatedNew = 1;
23140let isExtended = 1;
23141let mayStore = 1;
23142let BaseOpcode = "S2_storerbabs";
23143let CextOpcode = "S2_storerb";
23144let isNVStorable = 1;
23145let DecoderNamespace = "MustExtend";
23146let isExtendable = 1;
23147let opExtendable = 1;
23148let isExtentSigned = 0;
23149let opExtentBits = 6;
23150let opExtentAlign = 0;
23151}
23152def S4_pstorerbtnew_io : HInst<
23153(outs),
23154(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
23155"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
23156tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
23157let Inst{2-2} = 0b0;
23158let Inst{31-21} = 0b01000010000;
23159let isPredicated = 1;
23160let addrMode = BaseImmOffset;
23161let accessSize = ByteAccess;
23162let isPredicatedNew = 1;
23163let mayStore = 1;
23164let BaseOpcode = "S2_storerb_io";
23165let CextOpcode = "S2_storerb";
23166let InputType = "imm";
23167let isNVStorable = 1;
23168let isExtendable = 1;
23169let opExtendable = 2;
23170let isExtentSigned = 0;
23171let opExtentBits = 6;
23172let opExtentAlign = 0;
23173}
23174def S4_pstorerbtnew_rr : HInst<
23175(outs),
23176(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23177"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23178tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23179let Inst{31-21} = 0b00110110000;
23180let isPredicated = 1;
23181let addrMode = BaseRegOffset;
23182let accessSize = ByteAccess;
23183let isPredicatedNew = 1;
23184let mayStore = 1;
23185let BaseOpcode = "S4_storerb_rr";
23186let CextOpcode = "S2_storerb";
23187let InputType = "reg";
23188let isNVStorable = 1;
23189}
23190def S4_pstorerbtnew_zomap : HInst<
23191(outs),
23192(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23193"if ($Pv4.new) memb($Rs32) = $Rt32",
23194tc_a2b365d2, TypeMAPPING> {
23195let isPseudo = 1;
23196let isCodeGenOnly = 1;
23197}
23198def S4_pstorerdf_abs : HInst<
23199(outs),
23200(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23201"if (!$Pv4) memd(#$Ii) = $Rtt32",
23202tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23203let Inst{2-2} = 0b1;
23204let Inst{7-7} = 0b1;
23205let Inst{13-13} = 0b0;
23206let Inst{31-18} = 0b10101111110000;
23207let isPredicated = 1;
23208let isPredicatedFalse = 1;
23209let addrMode = Absolute;
23210let accessSize = DoubleWordAccess;
23211let isExtended = 1;
23212let mayStore = 1;
23213let BaseOpcode = "S2_storerdabs";
23214let CextOpcode = "S2_storerd";
23215let DecoderNamespace = "MustExtend";
23216let isExtendable = 1;
23217let opExtendable = 1;
23218let isExtentSigned = 0;
23219let opExtentBits = 6;
23220let opExtentAlign = 0;
23221}
23222def S4_pstorerdf_rr : HInst<
23223(outs),
23224(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23225"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23226tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23227let Inst{31-21} = 0b00110101110;
23228let isPredicated = 1;
23229let isPredicatedFalse = 1;
23230let addrMode = BaseRegOffset;
23231let accessSize = DoubleWordAccess;
23232let mayStore = 1;
23233let BaseOpcode = "S2_storerd_rr";
23234let CextOpcode = "S2_storerd";
23235let InputType = "reg";
23236}
23237def S4_pstorerdfnew_abs : HInst<
23238(outs),
23239(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23240"if (!$Pv4.new) memd(#$Ii) = $Rtt32",
23241tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23242let Inst{2-2} = 0b1;
23243let Inst{7-7} = 0b1;
23244let Inst{13-13} = 0b1;
23245let Inst{31-18} = 0b10101111110000;
23246let isPredicated = 1;
23247let isPredicatedFalse = 1;
23248let addrMode = Absolute;
23249let accessSize = DoubleWordAccess;
23250let isPredicatedNew = 1;
23251let isExtended = 1;
23252let mayStore = 1;
23253let BaseOpcode = "S2_storerdabs";
23254let CextOpcode = "S2_storerd";
23255let DecoderNamespace = "MustExtend";
23256let isExtendable = 1;
23257let opExtendable = 1;
23258let isExtentSigned = 0;
23259let opExtentBits = 6;
23260let opExtentAlign = 0;
23261}
23262def S4_pstorerdfnew_io : HInst<
23263(outs),
23264(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23265"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23266tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23267let Inst{2-2} = 0b0;
23268let Inst{31-21} = 0b01000110110;
23269let isPredicated = 1;
23270let isPredicatedFalse = 1;
23271let addrMode = BaseImmOffset;
23272let accessSize = DoubleWordAccess;
23273let isPredicatedNew = 1;
23274let mayStore = 1;
23275let BaseOpcode = "S2_storerd_io";
23276let CextOpcode = "S2_storerd";
23277let InputType = "imm";
23278let isExtendable = 1;
23279let opExtendable = 2;
23280let isExtentSigned = 0;
23281let opExtentBits = 9;
23282let opExtentAlign = 3;
23283}
23284def S4_pstorerdfnew_rr : HInst<
23285(outs),
23286(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23287"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23288tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23289let Inst{31-21} = 0b00110111110;
23290let isPredicated = 1;
23291let isPredicatedFalse = 1;
23292let addrMode = BaseRegOffset;
23293let accessSize = DoubleWordAccess;
23294let isPredicatedNew = 1;
23295let mayStore = 1;
23296let BaseOpcode = "S2_storerd_rr";
23297let CextOpcode = "S2_storerd";
23298let InputType = "reg";
23299}
23300def S4_pstorerdfnew_zomap : HInst<
23301(outs),
23302(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23303"if (!$Pv4.new) memd($Rs32) = $Rtt32",
23304tc_a2b365d2, TypeMAPPING> {
23305let isPseudo = 1;
23306let isCodeGenOnly = 1;
23307}
23308def S4_pstorerdt_abs : HInst<
23309(outs),
23310(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23311"if ($Pv4) memd(#$Ii) = $Rtt32",
23312tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23313let Inst{2-2} = 0b0;
23314let Inst{7-7} = 0b1;
23315let Inst{13-13} = 0b0;
23316let Inst{31-18} = 0b10101111110000;
23317let isPredicated = 1;
23318let addrMode = Absolute;
23319let accessSize = DoubleWordAccess;
23320let isExtended = 1;
23321let mayStore = 1;
23322let BaseOpcode = "S2_storerdabs";
23323let CextOpcode = "S2_storerd";
23324let DecoderNamespace = "MustExtend";
23325let isExtendable = 1;
23326let opExtendable = 1;
23327let isExtentSigned = 0;
23328let opExtentBits = 6;
23329let opExtentAlign = 0;
23330}
23331def S4_pstorerdt_rr : HInst<
23332(outs),
23333(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23334"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23335tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23336let Inst{31-21} = 0b00110100110;
23337let isPredicated = 1;
23338let addrMode = BaseRegOffset;
23339let accessSize = DoubleWordAccess;
23340let mayStore = 1;
23341let BaseOpcode = "S2_storerd_rr";
23342let CextOpcode = "S2_storerd";
23343let InputType = "reg";
23344}
23345def S4_pstorerdtnew_abs : HInst<
23346(outs),
23347(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23348"if ($Pv4.new) memd(#$Ii) = $Rtt32",
23349tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23350let Inst{2-2} = 0b0;
23351let Inst{7-7} = 0b1;
23352let Inst{13-13} = 0b1;
23353let Inst{31-18} = 0b10101111110000;
23354let isPredicated = 1;
23355let addrMode = Absolute;
23356let accessSize = DoubleWordAccess;
23357let isPredicatedNew = 1;
23358let isExtended = 1;
23359let mayStore = 1;
23360let BaseOpcode = "S2_storerdabs";
23361let CextOpcode = "S2_storerd";
23362let DecoderNamespace = "MustExtend";
23363let isExtendable = 1;
23364let opExtendable = 1;
23365let isExtentSigned = 0;
23366let opExtentBits = 6;
23367let opExtentAlign = 0;
23368}
23369def S4_pstorerdtnew_io : HInst<
23370(outs),
23371(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23372"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23373tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23374let Inst{2-2} = 0b0;
23375let Inst{31-21} = 0b01000010110;
23376let isPredicated = 1;
23377let addrMode = BaseImmOffset;
23378let accessSize = DoubleWordAccess;
23379let isPredicatedNew = 1;
23380let mayStore = 1;
23381let BaseOpcode = "S2_storerd_io";
23382let CextOpcode = "S2_storerd";
23383let InputType = "imm";
23384let isExtendable = 1;
23385let opExtendable = 2;
23386let isExtentSigned = 0;
23387let opExtentBits = 9;
23388let opExtentAlign = 3;
23389}
23390def S4_pstorerdtnew_rr : HInst<
23391(outs),
23392(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23393"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23394tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23395let Inst{31-21} = 0b00110110110;
23396let isPredicated = 1;
23397let addrMode = BaseRegOffset;
23398let accessSize = DoubleWordAccess;
23399let isPredicatedNew = 1;
23400let mayStore = 1;
23401let BaseOpcode = "S2_storerd_rr";
23402let CextOpcode = "S2_storerd";
23403let InputType = "reg";
23404}
23405def S4_pstorerdtnew_zomap : HInst<
23406(outs),
23407(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23408"if ($Pv4.new) memd($Rs32) = $Rtt32",
23409tc_a2b365d2, TypeMAPPING> {
23410let isPseudo = 1;
23411let isCodeGenOnly = 1;
23412}
23413def S4_pstorerff_abs : HInst<
23414(outs),
23415(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23416"if (!$Pv4) memh(#$Ii) = $Rt32.h",
23417tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23418let Inst{2-2} = 0b1;
23419let Inst{7-7} = 0b1;
23420let Inst{13-13} = 0b0;
23421let Inst{31-18} = 0b10101111011000;
23422let isPredicated = 1;
23423let isPredicatedFalse = 1;
23424let addrMode = Absolute;
23425let accessSize = HalfWordAccess;
23426let isExtended = 1;
23427let mayStore = 1;
23428let BaseOpcode = "S2_storerfabs";
23429let CextOpcode = "S2_storerf";
23430let DecoderNamespace = "MustExtend";
23431let isExtendable = 1;
23432let opExtendable = 1;
23433let isExtentSigned = 0;
23434let opExtentBits = 6;
23435let opExtentAlign = 0;
23436}
23437def S4_pstorerff_rr : HInst<
23438(outs),
23439(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23440"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23441tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23442let Inst{31-21} = 0b00110101011;
23443let isPredicated = 1;
23444let isPredicatedFalse = 1;
23445let addrMode = BaseRegOffset;
23446let accessSize = HalfWordAccess;
23447let mayStore = 1;
23448let BaseOpcode = "S4_storerf_rr";
23449let CextOpcode = "S2_storerf";
23450let InputType = "reg";
23451}
23452def S4_pstorerffnew_abs : HInst<
23453(outs),
23454(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23455"if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
23456tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23457let Inst{2-2} = 0b1;
23458let Inst{7-7} = 0b1;
23459let Inst{13-13} = 0b1;
23460let Inst{31-18} = 0b10101111011000;
23461let isPredicated = 1;
23462let isPredicatedFalse = 1;
23463let addrMode = Absolute;
23464let accessSize = HalfWordAccess;
23465let isPredicatedNew = 1;
23466let isExtended = 1;
23467let mayStore = 1;
23468let BaseOpcode = "S2_storerfabs";
23469let CextOpcode = "S2_storerf";
23470let DecoderNamespace = "MustExtend";
23471let isExtendable = 1;
23472let opExtendable = 1;
23473let isExtentSigned = 0;
23474let opExtentBits = 6;
23475let opExtentAlign = 0;
23476}
23477def S4_pstorerffnew_io : HInst<
23478(outs),
23479(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23480"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23481tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23482let Inst{2-2} = 0b0;
23483let Inst{31-21} = 0b01000110011;
23484let isPredicated = 1;
23485let isPredicatedFalse = 1;
23486let addrMode = BaseImmOffset;
23487let accessSize = HalfWordAccess;
23488let isPredicatedNew = 1;
23489let mayStore = 1;
23490let BaseOpcode = "S2_storerf_io";
23491let CextOpcode = "S2_storerf";
23492let InputType = "imm";
23493let isExtendable = 1;
23494let opExtendable = 2;
23495let isExtentSigned = 0;
23496let opExtentBits = 7;
23497let opExtentAlign = 1;
23498}
23499def S4_pstorerffnew_rr : HInst<
23500(outs),
23501(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23502"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23503tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23504let Inst{31-21} = 0b00110111011;
23505let isPredicated = 1;
23506let isPredicatedFalse = 1;
23507let addrMode = BaseRegOffset;
23508let accessSize = HalfWordAccess;
23509let isPredicatedNew = 1;
23510let mayStore = 1;
23511let BaseOpcode = "S4_storerf_rr";
23512let CextOpcode = "S2_storerf";
23513let InputType = "reg";
23514}
23515def S4_pstorerffnew_zomap : HInst<
23516(outs),
23517(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23518"if (!$Pv4.new) memh($Rs32) = $Rt32.h",
23519tc_a2b365d2, TypeMAPPING> {
23520let isPseudo = 1;
23521let isCodeGenOnly = 1;
23522}
23523def S4_pstorerft_abs : HInst<
23524(outs),
23525(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23526"if ($Pv4) memh(#$Ii) = $Rt32.h",
23527tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23528let Inst{2-2} = 0b0;
23529let Inst{7-7} = 0b1;
23530let Inst{13-13} = 0b0;
23531let Inst{31-18} = 0b10101111011000;
23532let isPredicated = 1;
23533let addrMode = Absolute;
23534let accessSize = HalfWordAccess;
23535let isExtended = 1;
23536let mayStore = 1;
23537let BaseOpcode = "S2_storerfabs";
23538let CextOpcode = "S2_storerf";
23539let DecoderNamespace = "MustExtend";
23540let isExtendable = 1;
23541let opExtendable = 1;
23542let isExtentSigned = 0;
23543let opExtentBits = 6;
23544let opExtentAlign = 0;
23545}
23546def S4_pstorerft_rr : HInst<
23547(outs),
23548(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23549"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23550tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23551let Inst{31-21} = 0b00110100011;
23552let isPredicated = 1;
23553let addrMode = BaseRegOffset;
23554let accessSize = HalfWordAccess;
23555let mayStore = 1;
23556let BaseOpcode = "S4_storerf_rr";
23557let CextOpcode = "S2_storerf";
23558let InputType = "reg";
23559}
23560def S4_pstorerftnew_abs : HInst<
23561(outs),
23562(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23563"if ($Pv4.new) memh(#$Ii) = $Rt32.h",
23564tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23565let Inst{2-2} = 0b0;
23566let Inst{7-7} = 0b1;
23567let Inst{13-13} = 0b1;
23568let Inst{31-18} = 0b10101111011000;
23569let isPredicated = 1;
23570let addrMode = Absolute;
23571let accessSize = HalfWordAccess;
23572let isPredicatedNew = 1;
23573let isExtended = 1;
23574let mayStore = 1;
23575let BaseOpcode = "S2_storerfabs";
23576let CextOpcode = "S2_storerf";
23577let DecoderNamespace = "MustExtend";
23578let isExtendable = 1;
23579let opExtendable = 1;
23580let isExtentSigned = 0;
23581let opExtentBits = 6;
23582let opExtentAlign = 0;
23583}
23584def S4_pstorerftnew_io : HInst<
23585(outs),
23586(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23587"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23588tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23589let Inst{2-2} = 0b0;
23590let Inst{31-21} = 0b01000010011;
23591let isPredicated = 1;
23592let addrMode = BaseImmOffset;
23593let accessSize = HalfWordAccess;
23594let isPredicatedNew = 1;
23595let mayStore = 1;
23596let BaseOpcode = "S2_storerf_io";
23597let CextOpcode = "S2_storerf";
23598let InputType = "imm";
23599let isExtendable = 1;
23600let opExtendable = 2;
23601let isExtentSigned = 0;
23602let opExtentBits = 7;
23603let opExtentAlign = 1;
23604}
23605def S4_pstorerftnew_rr : HInst<
23606(outs),
23607(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23608"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23609tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23610let Inst{31-21} = 0b00110110011;
23611let isPredicated = 1;
23612let addrMode = BaseRegOffset;
23613let accessSize = HalfWordAccess;
23614let isPredicatedNew = 1;
23615let mayStore = 1;
23616let BaseOpcode = "S4_storerf_rr";
23617let CextOpcode = "S2_storerf";
23618let InputType = "reg";
23619}
23620def S4_pstorerftnew_zomap : HInst<
23621(outs),
23622(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23623"if ($Pv4.new) memh($Rs32) = $Rt32.h",
23624tc_a2b365d2, TypeMAPPING> {
23625let isPseudo = 1;
23626let isCodeGenOnly = 1;
23627}
23628def S4_pstorerhf_abs : HInst<
23629(outs),
23630(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23631"if (!$Pv4) memh(#$Ii) = $Rt32",
23632tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23633let Inst{2-2} = 0b1;
23634let Inst{7-7} = 0b1;
23635let Inst{13-13} = 0b0;
23636let Inst{31-18} = 0b10101111010000;
23637let isPredicated = 1;
23638let isPredicatedFalse = 1;
23639let addrMode = Absolute;
23640let accessSize = HalfWordAccess;
23641let isExtended = 1;
23642let mayStore = 1;
23643let BaseOpcode = "S2_storerhabs";
23644let CextOpcode = "S2_storerh";
23645let isNVStorable = 1;
23646let DecoderNamespace = "MustExtend";
23647let isExtendable = 1;
23648let opExtendable = 1;
23649let isExtentSigned = 0;
23650let opExtentBits = 6;
23651let opExtentAlign = 0;
23652}
23653def S4_pstorerhf_rr : HInst<
23654(outs),
23655(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23656"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23657tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23658let Inst{31-21} = 0b00110101010;
23659let isPredicated = 1;
23660let isPredicatedFalse = 1;
23661let addrMode = BaseRegOffset;
23662let accessSize = HalfWordAccess;
23663let mayStore = 1;
23664let BaseOpcode = "S2_storerh_rr";
23665let CextOpcode = "S2_storerh";
23666let InputType = "reg";
23667let isNVStorable = 1;
23668}
23669def S4_pstorerhfnew_abs : HInst<
23670(outs),
23671(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23672"if (!$Pv4.new) memh(#$Ii) = $Rt32",
23673tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23674let Inst{2-2} = 0b1;
23675let Inst{7-7} = 0b1;
23676let Inst{13-13} = 0b1;
23677let Inst{31-18} = 0b10101111010000;
23678let isPredicated = 1;
23679let isPredicatedFalse = 1;
23680let addrMode = Absolute;
23681let accessSize = HalfWordAccess;
23682let isPredicatedNew = 1;
23683let isExtended = 1;
23684let mayStore = 1;
23685let BaseOpcode = "S2_storerhabs";
23686let CextOpcode = "S2_storerh";
23687let isNVStorable = 1;
23688let DecoderNamespace = "MustExtend";
23689let isExtendable = 1;
23690let opExtendable = 1;
23691let isExtentSigned = 0;
23692let opExtentBits = 6;
23693let opExtentAlign = 0;
23694}
23695def S4_pstorerhfnew_io : HInst<
23696(outs),
23697(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23698"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23699tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23700let Inst{2-2} = 0b0;
23701let Inst{31-21} = 0b01000110010;
23702let isPredicated = 1;
23703let isPredicatedFalse = 1;
23704let addrMode = BaseImmOffset;
23705let accessSize = HalfWordAccess;
23706let isPredicatedNew = 1;
23707let mayStore = 1;
23708let BaseOpcode = "S2_storerh_io";
23709let CextOpcode = "S2_storerh";
23710let InputType = "imm";
23711let isNVStorable = 1;
23712let isExtendable = 1;
23713let opExtendable = 2;
23714let isExtentSigned = 0;
23715let opExtentBits = 7;
23716let opExtentAlign = 1;
23717}
23718def S4_pstorerhfnew_rr : HInst<
23719(outs),
23720(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23721"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23722tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23723let Inst{31-21} = 0b00110111010;
23724let isPredicated = 1;
23725let isPredicatedFalse = 1;
23726let addrMode = BaseRegOffset;
23727let accessSize = HalfWordAccess;
23728let isPredicatedNew = 1;
23729let mayStore = 1;
23730let BaseOpcode = "S2_storerh_rr";
23731let CextOpcode = "S2_storerh";
23732let InputType = "reg";
23733let isNVStorable = 1;
23734}
23735def S4_pstorerhfnew_zomap : HInst<
23736(outs),
23737(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23738"if (!$Pv4.new) memh($Rs32) = $Rt32",
23739tc_a2b365d2, TypeMAPPING> {
23740let isPseudo = 1;
23741let isCodeGenOnly = 1;
23742}
23743def S4_pstorerhnewf_abs : HInst<
23744(outs),
23745(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23746"if (!$Pv4) memh(#$Ii) = $Nt8.new",
23747tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23748let Inst{2-2} = 0b1;
23749let Inst{7-7} = 0b1;
23750let Inst{13-11} = 0b001;
23751let Inst{31-18} = 0b10101111101000;
23752let isPredicated = 1;
23753let isPredicatedFalse = 1;
23754let addrMode = Absolute;
23755let accessSize = HalfWordAccess;
23756let isNVStore = 1;
23757let isNewValue = 1;
23758let isExtended = 1;
23759let isRestrictNoSlot1Store = 1;
23760let mayStore = 1;
23761let BaseOpcode = "S2_storerhabs";
23762let CextOpcode = "S2_storerh";
23763let DecoderNamespace = "MustExtend";
23764let isExtendable = 1;
23765let opExtendable = 1;
23766let isExtentSigned = 0;
23767let opExtentBits = 6;
23768let opExtentAlign = 0;
23769let opNewValue = 2;
23770}
23771def S4_pstorerhnewf_rr : HInst<
23772(outs),
23773(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23774"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23775tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23776let Inst{4-3} = 0b01;
23777let Inst{31-21} = 0b00110101101;
23778let isPredicated = 1;
23779let isPredicatedFalse = 1;
23780let addrMode = BaseRegOffset;
23781let accessSize = HalfWordAccess;
23782let isNVStore = 1;
23783let isNewValue = 1;
23784let isRestrictNoSlot1Store = 1;
23785let mayStore = 1;
23786let BaseOpcode = "S2_storerh_rr";
23787let CextOpcode = "S2_storerh";
23788let InputType = "reg";
23789let opNewValue = 4;
23790}
23791def S4_pstorerhnewfnew_abs : HInst<
23792(outs),
23793(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23794"if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
23795tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23796let Inst{2-2} = 0b1;
23797let Inst{7-7} = 0b1;
23798let Inst{13-11} = 0b101;
23799let Inst{31-18} = 0b10101111101000;
23800let isPredicated = 1;
23801let isPredicatedFalse = 1;
23802let addrMode = Absolute;
23803let accessSize = HalfWordAccess;
23804let isNVStore = 1;
23805let isPredicatedNew = 1;
23806let isNewValue = 1;
23807let isExtended = 1;
23808let isRestrictNoSlot1Store = 1;
23809let mayStore = 1;
23810let BaseOpcode = "S2_storerhabs";
23811let CextOpcode = "S2_storerh";
23812let DecoderNamespace = "MustExtend";
23813let isExtendable = 1;
23814let opExtendable = 1;
23815let isExtentSigned = 0;
23816let opExtentBits = 6;
23817let opExtentAlign = 0;
23818let opNewValue = 2;
23819}
23820def S4_pstorerhnewfnew_io : HInst<
23821(outs),
23822(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23823"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23824tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23825let Inst{2-2} = 0b0;
23826let Inst{12-11} = 0b01;
23827let Inst{31-21} = 0b01000110101;
23828let isPredicated = 1;
23829let isPredicatedFalse = 1;
23830let addrMode = BaseImmOffset;
23831let accessSize = HalfWordAccess;
23832let isNVStore = 1;
23833let isPredicatedNew = 1;
23834let isNewValue = 1;
23835let isRestrictNoSlot1Store = 1;
23836let mayStore = 1;
23837let BaseOpcode = "S2_storerh_io";
23838let CextOpcode = "S2_storerh";
23839let InputType = "imm";
23840let isExtendable = 1;
23841let opExtendable = 2;
23842let isExtentSigned = 0;
23843let opExtentBits = 7;
23844let opExtentAlign = 1;
23845let opNewValue = 3;
23846}
23847def S4_pstorerhnewfnew_rr : HInst<
23848(outs),
23849(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23850"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23851tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23852let Inst{4-3} = 0b01;
23853let Inst{31-21} = 0b00110111101;
23854let isPredicated = 1;
23855let isPredicatedFalse = 1;
23856let addrMode = BaseRegOffset;
23857let accessSize = HalfWordAccess;
23858let isNVStore = 1;
23859let isPredicatedNew = 1;
23860let isNewValue = 1;
23861let isRestrictNoSlot1Store = 1;
23862let mayStore = 1;
23863let BaseOpcode = "S2_storerh_rr";
23864let CextOpcode = "S2_storerh";
23865let InputType = "reg";
23866let opNewValue = 4;
23867}
23868def S4_pstorerhnewfnew_zomap : HInst<
23869(outs),
23870(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23871"if (!$Pv4.new) memh($Rs32) = $Nt8.new",
23872tc_92240447, TypeMAPPING> {
23873let isPseudo = 1;
23874let isCodeGenOnly = 1;
23875let opNewValue = 2;
23876}
23877def S4_pstorerhnewt_abs : HInst<
23878(outs),
23879(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23880"if ($Pv4) memh(#$Ii) = $Nt8.new",
23881tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23882let Inst{2-2} = 0b0;
23883let Inst{7-7} = 0b1;
23884let Inst{13-11} = 0b001;
23885let Inst{31-18} = 0b10101111101000;
23886let isPredicated = 1;
23887let addrMode = Absolute;
23888let accessSize = HalfWordAccess;
23889let isNVStore = 1;
23890let isNewValue = 1;
23891let isExtended = 1;
23892let isRestrictNoSlot1Store = 1;
23893let mayStore = 1;
23894let BaseOpcode = "S2_storerhabs";
23895let CextOpcode = "S2_storerh";
23896let DecoderNamespace = "MustExtend";
23897let isExtendable = 1;
23898let opExtendable = 1;
23899let isExtentSigned = 0;
23900let opExtentBits = 6;
23901let opExtentAlign = 0;
23902let opNewValue = 2;
23903}
23904def S4_pstorerhnewt_rr : HInst<
23905(outs),
23906(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23907"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23908tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23909let Inst{4-3} = 0b01;
23910let Inst{31-21} = 0b00110100101;
23911let isPredicated = 1;
23912let addrMode = BaseRegOffset;
23913let accessSize = HalfWordAccess;
23914let isNVStore = 1;
23915let isNewValue = 1;
23916let isRestrictNoSlot1Store = 1;
23917let mayStore = 1;
23918let BaseOpcode = "S2_storerh_rr";
23919let CextOpcode = "S2_storerh";
23920let InputType = "reg";
23921let opNewValue = 4;
23922}
23923def S4_pstorerhnewtnew_abs : HInst<
23924(outs),
23925(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23926"if ($Pv4.new) memh(#$Ii) = $Nt8.new",
23927tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23928let Inst{2-2} = 0b0;
23929let Inst{7-7} = 0b1;
23930let Inst{13-11} = 0b101;
23931let Inst{31-18} = 0b10101111101000;
23932let isPredicated = 1;
23933let addrMode = Absolute;
23934let accessSize = HalfWordAccess;
23935let isNVStore = 1;
23936let isPredicatedNew = 1;
23937let isNewValue = 1;
23938let isExtended = 1;
23939let isRestrictNoSlot1Store = 1;
23940let mayStore = 1;
23941let BaseOpcode = "S2_storerhabs";
23942let CextOpcode = "S2_storerh";
23943let DecoderNamespace = "MustExtend";
23944let isExtendable = 1;
23945let opExtendable = 1;
23946let isExtentSigned = 0;
23947let opExtentBits = 6;
23948let opExtentAlign = 0;
23949let opNewValue = 2;
23950}
23951def S4_pstorerhnewtnew_io : HInst<
23952(outs),
23953(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23954"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23955tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23956let Inst{2-2} = 0b0;
23957let Inst{12-11} = 0b01;
23958let Inst{31-21} = 0b01000010101;
23959let isPredicated = 1;
23960let addrMode = BaseImmOffset;
23961let accessSize = HalfWordAccess;
23962let isNVStore = 1;
23963let isPredicatedNew = 1;
23964let isNewValue = 1;
23965let isRestrictNoSlot1Store = 1;
23966let mayStore = 1;
23967let BaseOpcode = "S2_storerh_io";
23968let CextOpcode = "S2_storerh";
23969let InputType = "imm";
23970let isExtendable = 1;
23971let opExtendable = 2;
23972let isExtentSigned = 0;
23973let opExtentBits = 7;
23974let opExtentAlign = 1;
23975let opNewValue = 3;
23976}
23977def S4_pstorerhnewtnew_rr : HInst<
23978(outs),
23979(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23980"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23981tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23982let Inst{4-3} = 0b01;
23983let Inst{31-21} = 0b00110110101;
23984let isPredicated = 1;
23985let addrMode = BaseRegOffset;
23986let accessSize = HalfWordAccess;
23987let isNVStore = 1;
23988let isPredicatedNew = 1;
23989let isNewValue = 1;
23990let isRestrictNoSlot1Store = 1;
23991let mayStore = 1;
23992let BaseOpcode = "S2_storerh_rr";
23993let CextOpcode = "S2_storerh";
23994let InputType = "reg";
23995let opNewValue = 4;
23996}
23997def S4_pstorerhnewtnew_zomap : HInst<
23998(outs),
23999(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24000"if ($Pv4.new) memh($Rs32) = $Nt8.new",
24001tc_92240447, TypeMAPPING> {
24002let isPseudo = 1;
24003let isCodeGenOnly = 1;
24004let opNewValue = 2;
24005}
24006def S4_pstorerht_abs : HInst<
24007(outs),
24008(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24009"if ($Pv4) memh(#$Ii) = $Rt32",
24010tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24011let Inst{2-2} = 0b0;
24012let Inst{7-7} = 0b1;
24013let Inst{13-13} = 0b0;
24014let Inst{31-18} = 0b10101111010000;
24015let isPredicated = 1;
24016let addrMode = Absolute;
24017let accessSize = HalfWordAccess;
24018let isExtended = 1;
24019let mayStore = 1;
24020let BaseOpcode = "S2_storerhabs";
24021let CextOpcode = "S2_storerh";
24022let isNVStorable = 1;
24023let DecoderNamespace = "MustExtend";
24024let isExtendable = 1;
24025let opExtendable = 1;
24026let isExtentSigned = 0;
24027let opExtentBits = 6;
24028let opExtentAlign = 0;
24029}
24030def S4_pstorerht_rr : HInst<
24031(outs),
24032(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24033"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24034tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24035let Inst{31-21} = 0b00110100010;
24036let isPredicated = 1;
24037let addrMode = BaseRegOffset;
24038let accessSize = HalfWordAccess;
24039let mayStore = 1;
24040let BaseOpcode = "S2_storerh_rr";
24041let CextOpcode = "S2_storerh";
24042let InputType = "reg";
24043let isNVStorable = 1;
24044}
24045def S4_pstorerhtnew_abs : HInst<
24046(outs),
24047(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24048"if ($Pv4.new) memh(#$Ii) = $Rt32",
24049tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24050let Inst{2-2} = 0b0;
24051let Inst{7-7} = 0b1;
24052let Inst{13-13} = 0b1;
24053let Inst{31-18} = 0b10101111010000;
24054let isPredicated = 1;
24055let addrMode = Absolute;
24056let accessSize = HalfWordAccess;
24057let isPredicatedNew = 1;
24058let isExtended = 1;
24059let mayStore = 1;
24060let BaseOpcode = "S2_storerhabs";
24061let CextOpcode = "S2_storerh";
24062let isNVStorable = 1;
24063let DecoderNamespace = "MustExtend";
24064let isExtendable = 1;
24065let opExtendable = 1;
24066let isExtentSigned = 0;
24067let opExtentBits = 6;
24068let opExtentAlign = 0;
24069}
24070def S4_pstorerhtnew_io : HInst<
24071(outs),
24072(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
24073"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
24074tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
24075let Inst{2-2} = 0b0;
24076let Inst{31-21} = 0b01000010010;
24077let isPredicated = 1;
24078let addrMode = BaseImmOffset;
24079let accessSize = HalfWordAccess;
24080let isPredicatedNew = 1;
24081let mayStore = 1;
24082let BaseOpcode = "S2_storerh_io";
24083let CextOpcode = "S2_storerh";
24084let InputType = "imm";
24085let isNVStorable = 1;
24086let isExtendable = 1;
24087let opExtendable = 2;
24088let isExtentSigned = 0;
24089let opExtentBits = 7;
24090let opExtentAlign = 1;
24091}
24092def S4_pstorerhtnew_rr : HInst<
24093(outs),
24094(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24095"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24096tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24097let Inst{31-21} = 0b00110110010;
24098let isPredicated = 1;
24099let addrMode = BaseRegOffset;
24100let accessSize = HalfWordAccess;
24101let isPredicatedNew = 1;
24102let mayStore = 1;
24103let BaseOpcode = "S2_storerh_rr";
24104let CextOpcode = "S2_storerh";
24105let InputType = "reg";
24106let isNVStorable = 1;
24107}
24108def S4_pstorerhtnew_zomap : HInst<
24109(outs),
24110(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24111"if ($Pv4.new) memh($Rs32) = $Rt32",
24112tc_a2b365d2, TypeMAPPING> {
24113let isPseudo = 1;
24114let isCodeGenOnly = 1;
24115}
24116def S4_pstorerif_abs : HInst<
24117(outs),
24118(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24119"if (!$Pv4) memw(#$Ii) = $Rt32",
24120tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24121let Inst{2-2} = 0b1;
24122let Inst{7-7} = 0b1;
24123let Inst{13-13} = 0b0;
24124let Inst{31-18} = 0b10101111100000;
24125let isPredicated = 1;
24126let isPredicatedFalse = 1;
24127let addrMode = Absolute;
24128let accessSize = WordAccess;
24129let isExtended = 1;
24130let mayStore = 1;
24131let BaseOpcode = "S2_storeriabs";
24132let CextOpcode = "S2_storeri";
24133let isNVStorable = 1;
24134let DecoderNamespace = "MustExtend";
24135let isExtendable = 1;
24136let opExtendable = 1;
24137let isExtentSigned = 0;
24138let opExtentBits = 6;
24139let opExtentAlign = 0;
24140}
24141def S4_pstorerif_rr : HInst<
24142(outs),
24143(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24144"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24145tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24146let Inst{31-21} = 0b00110101100;
24147let isPredicated = 1;
24148let isPredicatedFalse = 1;
24149let addrMode = BaseRegOffset;
24150let accessSize = WordAccess;
24151let mayStore = 1;
24152let BaseOpcode = "S2_storeri_rr";
24153let CextOpcode = "S2_storeri";
24154let InputType = "reg";
24155let isNVStorable = 1;
24156}
24157def S4_pstorerifnew_abs : HInst<
24158(outs),
24159(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24160"if (!$Pv4.new) memw(#$Ii) = $Rt32",
24161tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24162let Inst{2-2} = 0b1;
24163let Inst{7-7} = 0b1;
24164let Inst{13-13} = 0b1;
24165let Inst{31-18} = 0b10101111100000;
24166let isPredicated = 1;
24167let isPredicatedFalse = 1;
24168let addrMode = Absolute;
24169let accessSize = WordAccess;
24170let isPredicatedNew = 1;
24171let isExtended = 1;
24172let mayStore = 1;
24173let BaseOpcode = "S2_storeriabs";
24174let CextOpcode = "S2_storeri";
24175let isNVStorable = 1;
24176let DecoderNamespace = "MustExtend";
24177let isExtendable = 1;
24178let opExtendable = 1;
24179let isExtentSigned = 0;
24180let opExtentBits = 6;
24181let opExtentAlign = 0;
24182}
24183def S4_pstorerifnew_io : HInst<
24184(outs),
24185(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24186"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24187tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24188let Inst{2-2} = 0b0;
24189let Inst{31-21} = 0b01000110100;
24190let isPredicated = 1;
24191let isPredicatedFalse = 1;
24192let addrMode = BaseImmOffset;
24193let accessSize = WordAccess;
24194let isPredicatedNew = 1;
24195let mayStore = 1;
24196let BaseOpcode = "S2_storeri_io";
24197let CextOpcode = "S2_storeri";
24198let InputType = "imm";
24199let isNVStorable = 1;
24200let isExtendable = 1;
24201let opExtendable = 2;
24202let isExtentSigned = 0;
24203let opExtentBits = 8;
24204let opExtentAlign = 2;
24205}
24206def S4_pstorerifnew_rr : HInst<
24207(outs),
24208(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24209"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24210tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24211let Inst{31-21} = 0b00110111100;
24212let isPredicated = 1;
24213let isPredicatedFalse = 1;
24214let addrMode = BaseRegOffset;
24215let accessSize = WordAccess;
24216let isPredicatedNew = 1;
24217let mayStore = 1;
24218let BaseOpcode = "S2_storeri_rr";
24219let CextOpcode = "S2_storeri";
24220let InputType = "reg";
24221let isNVStorable = 1;
24222}
24223def S4_pstorerifnew_zomap : HInst<
24224(outs),
24225(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24226"if (!$Pv4.new) memw($Rs32) = $Rt32",
24227tc_a2b365d2, TypeMAPPING> {
24228let isPseudo = 1;
24229let isCodeGenOnly = 1;
24230}
24231def S4_pstorerinewf_abs : HInst<
24232(outs),
24233(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24234"if (!$Pv4) memw(#$Ii) = $Nt8.new",
24235tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24236let Inst{2-2} = 0b1;
24237let Inst{7-7} = 0b1;
24238let Inst{13-11} = 0b010;
24239let Inst{31-18} = 0b10101111101000;
24240let isPredicated = 1;
24241let isPredicatedFalse = 1;
24242let addrMode = Absolute;
24243let accessSize = WordAccess;
24244let isNVStore = 1;
24245let isNewValue = 1;
24246let isExtended = 1;
24247let isRestrictNoSlot1Store = 1;
24248let mayStore = 1;
24249let BaseOpcode = "S2_storeriabs";
24250let CextOpcode = "S2_storeri";
24251let DecoderNamespace = "MustExtend";
24252let isExtendable = 1;
24253let opExtendable = 1;
24254let isExtentSigned = 0;
24255let opExtentBits = 6;
24256let opExtentAlign = 0;
24257let opNewValue = 2;
24258}
24259def S4_pstorerinewf_rr : HInst<
24260(outs),
24261(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24262"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24263tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24264let Inst{4-3} = 0b10;
24265let Inst{31-21} = 0b00110101101;
24266let isPredicated = 1;
24267let isPredicatedFalse = 1;
24268let addrMode = BaseRegOffset;
24269let accessSize = WordAccess;
24270let isNVStore = 1;
24271let isNewValue = 1;
24272let isRestrictNoSlot1Store = 1;
24273let mayStore = 1;
24274let BaseOpcode = "S2_storeri_rr";
24275let CextOpcode = "S2_storeri";
24276let InputType = "reg";
24277let opNewValue = 4;
24278}
24279def S4_pstorerinewfnew_abs : HInst<
24280(outs),
24281(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24282"if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
24283tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24284let Inst{2-2} = 0b1;
24285let Inst{7-7} = 0b1;
24286let Inst{13-11} = 0b110;
24287let Inst{31-18} = 0b10101111101000;
24288let isPredicated = 1;
24289let isPredicatedFalse = 1;
24290let addrMode = Absolute;
24291let accessSize = WordAccess;
24292let isNVStore = 1;
24293let isPredicatedNew = 1;
24294let isNewValue = 1;
24295let isExtended = 1;
24296let isRestrictNoSlot1Store = 1;
24297let mayStore = 1;
24298let BaseOpcode = "S2_storeriabs";
24299let CextOpcode = "S2_storeri";
24300let DecoderNamespace = "MustExtend";
24301let isExtendable = 1;
24302let opExtendable = 1;
24303let isExtentSigned = 0;
24304let opExtentBits = 6;
24305let opExtentAlign = 0;
24306let opNewValue = 2;
24307}
24308def S4_pstorerinewfnew_io : HInst<
24309(outs),
24310(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24311"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24312tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24313let Inst{2-2} = 0b0;
24314let Inst{12-11} = 0b10;
24315let Inst{31-21} = 0b01000110101;
24316let isPredicated = 1;
24317let isPredicatedFalse = 1;
24318let addrMode = BaseImmOffset;
24319let accessSize = WordAccess;
24320let isNVStore = 1;
24321let isPredicatedNew = 1;
24322let isNewValue = 1;
24323let isRestrictNoSlot1Store = 1;
24324let mayStore = 1;
24325let BaseOpcode = "S2_storeri_io";
24326let CextOpcode = "S2_storeri";
24327let InputType = "imm";
24328let isExtendable = 1;
24329let opExtendable = 2;
24330let isExtentSigned = 0;
24331let opExtentBits = 8;
24332let opExtentAlign = 2;
24333let opNewValue = 3;
24334}
24335def S4_pstorerinewfnew_rr : HInst<
24336(outs),
24337(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24338"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24339tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24340let Inst{4-3} = 0b10;
24341let Inst{31-21} = 0b00110111101;
24342let isPredicated = 1;
24343let isPredicatedFalse = 1;
24344let addrMode = BaseRegOffset;
24345let accessSize = WordAccess;
24346let isNVStore = 1;
24347let isPredicatedNew = 1;
24348let isNewValue = 1;
24349let isRestrictNoSlot1Store = 1;
24350let mayStore = 1;
24351let BaseOpcode = "S2_storeri_rr";
24352let CextOpcode = "S2_storeri";
24353let InputType = "reg";
24354let opNewValue = 4;
24355}
24356def S4_pstorerinewfnew_zomap : HInst<
24357(outs),
24358(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24359"if (!$Pv4.new) memw($Rs32) = $Nt8.new",
24360tc_92240447, TypeMAPPING> {
24361let isPseudo = 1;
24362let isCodeGenOnly = 1;
24363let opNewValue = 2;
24364}
24365def S4_pstorerinewt_abs : HInst<
24366(outs),
24367(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24368"if ($Pv4) memw(#$Ii) = $Nt8.new",
24369tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24370let Inst{2-2} = 0b0;
24371let Inst{7-7} = 0b1;
24372let Inst{13-11} = 0b010;
24373let Inst{31-18} = 0b10101111101000;
24374let isPredicated = 1;
24375let addrMode = Absolute;
24376let accessSize = WordAccess;
24377let isNVStore = 1;
24378let isNewValue = 1;
24379let isExtended = 1;
24380let isRestrictNoSlot1Store = 1;
24381let mayStore = 1;
24382let BaseOpcode = "S2_storeriabs";
24383let CextOpcode = "S2_storeri";
24384let DecoderNamespace = "MustExtend";
24385let isExtendable = 1;
24386let opExtendable = 1;
24387let isExtentSigned = 0;
24388let opExtentBits = 6;
24389let opExtentAlign = 0;
24390let opNewValue = 2;
24391}
24392def S4_pstorerinewt_rr : HInst<
24393(outs),
24394(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24395"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24396tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24397let Inst{4-3} = 0b10;
24398let Inst{31-21} = 0b00110100101;
24399let isPredicated = 1;
24400let addrMode = BaseRegOffset;
24401let accessSize = WordAccess;
24402let isNVStore = 1;
24403let isNewValue = 1;
24404let isRestrictNoSlot1Store = 1;
24405let mayStore = 1;
24406let BaseOpcode = "S2_storeri_rr";
24407let CextOpcode = "S2_storeri";
24408let InputType = "reg";
24409let opNewValue = 4;
24410}
24411def S4_pstorerinewtnew_abs : HInst<
24412(outs),
24413(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24414"if ($Pv4.new) memw(#$Ii) = $Nt8.new",
24415tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24416let Inst{2-2} = 0b0;
24417let Inst{7-7} = 0b1;
24418let Inst{13-11} = 0b110;
24419let Inst{31-18} = 0b10101111101000;
24420let isPredicated = 1;
24421let addrMode = Absolute;
24422let accessSize = WordAccess;
24423let isNVStore = 1;
24424let isPredicatedNew = 1;
24425let isNewValue = 1;
24426let isExtended = 1;
24427let isRestrictNoSlot1Store = 1;
24428let mayStore = 1;
24429let BaseOpcode = "S2_storeriabs";
24430let CextOpcode = "S2_storeri";
24431let DecoderNamespace = "MustExtend";
24432let isExtendable = 1;
24433let opExtendable = 1;
24434let isExtentSigned = 0;
24435let opExtentBits = 6;
24436let opExtentAlign = 0;
24437let opNewValue = 2;
24438}
24439def S4_pstorerinewtnew_io : HInst<
24440(outs),
24441(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24442"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24443tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24444let Inst{2-2} = 0b0;
24445let Inst{12-11} = 0b10;
24446let Inst{31-21} = 0b01000010101;
24447let isPredicated = 1;
24448let addrMode = BaseImmOffset;
24449let accessSize = WordAccess;
24450let isNVStore = 1;
24451let isPredicatedNew = 1;
24452let isNewValue = 1;
24453let isRestrictNoSlot1Store = 1;
24454let mayStore = 1;
24455let BaseOpcode = "S2_storeri_io";
24456let CextOpcode = "S2_storeri";
24457let InputType = "imm";
24458let isExtendable = 1;
24459let opExtendable = 2;
24460let isExtentSigned = 0;
24461let opExtentBits = 8;
24462let opExtentAlign = 2;
24463let opNewValue = 3;
24464}
24465def S4_pstorerinewtnew_rr : HInst<
24466(outs),
24467(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24468"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24469tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24470let Inst{4-3} = 0b10;
24471let Inst{31-21} = 0b00110110101;
24472let isPredicated = 1;
24473let addrMode = BaseRegOffset;
24474let accessSize = WordAccess;
24475let isNVStore = 1;
24476let isPredicatedNew = 1;
24477let isNewValue = 1;
24478let isRestrictNoSlot1Store = 1;
24479let mayStore = 1;
24480let BaseOpcode = "S2_storeri_rr";
24481let CextOpcode = "S2_storeri";
24482let InputType = "reg";
24483let opNewValue = 4;
24484}
24485def S4_pstorerinewtnew_zomap : HInst<
24486(outs),
24487(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24488"if ($Pv4.new) memw($Rs32) = $Nt8.new",
24489tc_92240447, TypeMAPPING> {
24490let isPseudo = 1;
24491let isCodeGenOnly = 1;
24492let opNewValue = 2;
24493}
24494def S4_pstorerit_abs : HInst<
24495(outs),
24496(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24497"if ($Pv4) memw(#$Ii) = $Rt32",
24498tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24499let Inst{2-2} = 0b0;
24500let Inst{7-7} = 0b1;
24501let Inst{13-13} = 0b0;
24502let Inst{31-18} = 0b10101111100000;
24503let isPredicated = 1;
24504let addrMode = Absolute;
24505let accessSize = WordAccess;
24506let isExtended = 1;
24507let mayStore = 1;
24508let BaseOpcode = "S2_storeriabs";
24509let CextOpcode = "S2_storeri";
24510let isNVStorable = 1;
24511let DecoderNamespace = "MustExtend";
24512let isExtendable = 1;
24513let opExtendable = 1;
24514let isExtentSigned = 0;
24515let opExtentBits = 6;
24516let opExtentAlign = 0;
24517}
24518def S4_pstorerit_rr : HInst<
24519(outs),
24520(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24521"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24522tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24523let Inst{31-21} = 0b00110100100;
24524let isPredicated = 1;
24525let addrMode = BaseRegOffset;
24526let accessSize = WordAccess;
24527let mayStore = 1;
24528let BaseOpcode = "S2_storeri_rr";
24529let CextOpcode = "S2_storeri";
24530let InputType = "reg";
24531let isNVStorable = 1;
24532}
24533def S4_pstoreritnew_abs : HInst<
24534(outs),
24535(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24536"if ($Pv4.new) memw(#$Ii) = $Rt32",
24537tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24538let Inst{2-2} = 0b0;
24539let Inst{7-7} = 0b1;
24540let Inst{13-13} = 0b1;
24541let Inst{31-18} = 0b10101111100000;
24542let isPredicated = 1;
24543let addrMode = Absolute;
24544let accessSize = WordAccess;
24545let isPredicatedNew = 1;
24546let isExtended = 1;
24547let mayStore = 1;
24548let BaseOpcode = "S2_storeriabs";
24549let CextOpcode = "S2_storeri";
24550let isNVStorable = 1;
24551let DecoderNamespace = "MustExtend";
24552let isExtendable = 1;
24553let opExtendable = 1;
24554let isExtentSigned = 0;
24555let opExtentBits = 6;
24556let opExtentAlign = 0;
24557}
24558def S4_pstoreritnew_io : HInst<
24559(outs),
24560(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24561"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24562tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24563let Inst{2-2} = 0b0;
24564let Inst{31-21} = 0b01000010100;
24565let isPredicated = 1;
24566let addrMode = BaseImmOffset;
24567let accessSize = WordAccess;
24568let isPredicatedNew = 1;
24569let mayStore = 1;
24570let BaseOpcode = "S2_storeri_io";
24571let CextOpcode = "S2_storeri";
24572let InputType = "imm";
24573let isNVStorable = 1;
24574let isExtendable = 1;
24575let opExtendable = 2;
24576let isExtentSigned = 0;
24577let opExtentBits = 8;
24578let opExtentAlign = 2;
24579}
24580def S4_pstoreritnew_rr : HInst<
24581(outs),
24582(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24583"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24584tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24585let Inst{31-21} = 0b00110110100;
24586let isPredicated = 1;
24587let addrMode = BaseRegOffset;
24588let accessSize = WordAccess;
24589let isPredicatedNew = 1;
24590let mayStore = 1;
24591let BaseOpcode = "S2_storeri_rr";
24592let CextOpcode = "S2_storeri";
24593let InputType = "reg";
24594let isNVStorable = 1;
24595}
24596def S4_pstoreritnew_zomap : HInst<
24597(outs),
24598(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24599"if ($Pv4.new) memw($Rs32) = $Rt32",
24600tc_a2b365d2, TypeMAPPING> {
24601let isPseudo = 1;
24602let isCodeGenOnly = 1;
24603}
24604def S4_stored_locked : HInst<
24605(outs PredRegs:$Pd4),
24606(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24607"memd_locked($Rs32,$Pd4) = $Rtt32",
24608tc_6f42bc60, TypeST>, Enc_d7dc10 {
24609let Inst{7-2} = 0b000000;
24610let Inst{13-13} = 0b0;
24611let Inst{31-21} = 0b10100000111;
24612let accessSize = DoubleWordAccess;
24613let isPredicateLate = 1;
24614let isSoloAX = 1;
24615let mayStore = 1;
24616}
24617def S4_stored_rl_at_vi : HInst<
24618(outs),
24619(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24620"memd_rl($Rs32):at = $Rtt32",
24621tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24622let Inst{7-2} = 0b000010;
24623let Inst{13-13} = 0b0;
24624let Inst{31-21} = 0b10100000111;
24625let accessSize = DoubleWordAccess;
24626let isSolo = 1;
24627let mayStore = 1;
24628}
24629def S4_stored_rl_st_vi : HInst<
24630(outs),
24631(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24632"memd_rl($Rs32):st = $Rtt32",
24633tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24634let Inst{7-2} = 0b001010;
24635let Inst{13-13} = 0b0;
24636let Inst{31-21} = 0b10100000111;
24637let accessSize = DoubleWordAccess;
24638let isSolo = 1;
24639let mayStore = 1;
24640}
24641def S4_storeirb_io : HInst<
24642(outs),
24643(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24644"memb($Rs32+#$Ii) = #$II",
24645tc_7c31e19a, TypeST>, Enc_8203bb, PredNewRel {
24646let Inst{31-21} = 0b00111100000;
24647let addrMode = BaseImmOffset;
24648let accessSize = ByteAccess;
24649let mayStore = 1;
24650let BaseOpcode = "S4_storeirb_io";
24651let CextOpcode = "S2_storerb";
24652let InputType = "imm";
24653let isPredicable = 1;
24654let isExtendable = 1;
24655let opExtendable = 2;
24656let isExtentSigned = 1;
24657let opExtentBits = 8;
24658let opExtentAlign = 0;
24659}
24660def S4_storeirb_zomap : HInst<
24661(outs),
24662(ins IntRegs:$Rs32, s8_0Imm:$II),
24663"memb($Rs32) = #$II",
24664tc_7c31e19a, TypeMAPPING> {
24665let isPseudo = 1;
24666let isCodeGenOnly = 1;
24667}
24668def S4_storeirbf_io : HInst<
24669(outs),
24670(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24671"if (!$Pv4) memb($Rs32+#$Ii) = #$II",
24672tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24673let Inst{31-21} = 0b00111000100;
24674let isPredicated = 1;
24675let isPredicatedFalse = 1;
24676let addrMode = BaseImmOffset;
24677let accessSize = ByteAccess;
24678let mayStore = 1;
24679let BaseOpcode = "S4_storeirb_io";
24680let CextOpcode = "S2_storerb";
24681let InputType = "imm";
24682let isExtendable = 1;
24683let opExtendable = 3;
24684let isExtentSigned = 1;
24685let opExtentBits = 6;
24686let opExtentAlign = 0;
24687}
24688def S4_storeirbf_zomap : HInst<
24689(outs),
24690(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24691"if (!$Pv4) memb($Rs32) = #$II",
24692tc_d03278fd, TypeMAPPING> {
24693let isPseudo = 1;
24694let isCodeGenOnly = 1;
24695}
24696def S4_storeirbfnew_io : HInst<
24697(outs),
24698(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24699"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
24700tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24701let Inst{31-21} = 0b00111001100;
24702let isPredicated = 1;
24703let isPredicatedFalse = 1;
24704let addrMode = BaseImmOffset;
24705let accessSize = ByteAccess;
24706let isPredicatedNew = 1;
24707let mayStore = 1;
24708let BaseOpcode = "S4_storeirb_io";
24709let CextOpcode = "S2_storerb";
24710let InputType = "imm";
24711let isExtendable = 1;
24712let opExtendable = 3;
24713let isExtentSigned = 1;
24714let opExtentBits = 6;
24715let opExtentAlign = 0;
24716}
24717def S4_storeirbfnew_zomap : HInst<
24718(outs),
24719(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24720"if (!$Pv4.new) memb($Rs32) = #$II",
24721tc_65cbd974, TypeMAPPING> {
24722let isPseudo = 1;
24723let isCodeGenOnly = 1;
24724}
24725def S4_storeirbt_io : HInst<
24726(outs),
24727(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24728"if ($Pv4) memb($Rs32+#$Ii) = #$II",
24729tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24730let Inst{31-21} = 0b00111000000;
24731let isPredicated = 1;
24732let addrMode = BaseImmOffset;
24733let accessSize = ByteAccess;
24734let mayStore = 1;
24735let BaseOpcode = "S4_storeirb_io";
24736let CextOpcode = "S2_storerb";
24737let InputType = "imm";
24738let isExtendable = 1;
24739let opExtendable = 3;
24740let isExtentSigned = 1;
24741let opExtentBits = 6;
24742let opExtentAlign = 0;
24743}
24744def S4_storeirbt_zomap : HInst<
24745(outs),
24746(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24747"if ($Pv4) memb($Rs32) = #$II",
24748tc_d03278fd, TypeMAPPING> {
24749let isPseudo = 1;
24750let isCodeGenOnly = 1;
24751}
24752def S4_storeirbtnew_io : HInst<
24753(outs),
24754(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24755"if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
24756tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24757let Inst{31-21} = 0b00111001000;
24758let isPredicated = 1;
24759let addrMode = BaseImmOffset;
24760let accessSize = ByteAccess;
24761let isPredicatedNew = 1;
24762let mayStore = 1;
24763let BaseOpcode = "S4_storeirb_io";
24764let CextOpcode = "S2_storerb";
24765let InputType = "imm";
24766let isExtendable = 1;
24767let opExtendable = 3;
24768let isExtentSigned = 1;
24769let opExtentBits = 6;
24770let opExtentAlign = 0;
24771}
24772def S4_storeirbtnew_zomap : HInst<
24773(outs),
24774(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24775"if ($Pv4.new) memb($Rs32) = #$II",
24776tc_65cbd974, TypeMAPPING> {
24777let isPseudo = 1;
24778let isCodeGenOnly = 1;
24779}
24780def S4_storeirh_io : HInst<
24781(outs),
24782(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24783"memh($Rs32+#$Ii) = #$II",
24784tc_7c31e19a, TypeST>, Enc_a803e0, PredNewRel {
24785let Inst{31-21} = 0b00111100001;
24786let addrMode = BaseImmOffset;
24787let accessSize = HalfWordAccess;
24788let mayStore = 1;
24789let BaseOpcode = "S4_storeirh_io";
24790let CextOpcode = "S2_storerh";
24791let InputType = "imm";
24792let isPredicable = 1;
24793let isExtendable = 1;
24794let opExtendable = 2;
24795let isExtentSigned = 1;
24796let opExtentBits = 8;
24797let opExtentAlign = 0;
24798}
24799def S4_storeirh_zomap : HInst<
24800(outs),
24801(ins IntRegs:$Rs32, s8_0Imm:$II),
24802"memh($Rs32) = #$II",
24803tc_7c31e19a, TypeMAPPING> {
24804let isPseudo = 1;
24805let isCodeGenOnly = 1;
24806}
24807def S4_storeirhf_io : HInst<
24808(outs),
24809(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24810"if (!$Pv4) memh($Rs32+#$Ii) = #$II",
24811tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24812let Inst{31-21} = 0b00111000101;
24813let isPredicated = 1;
24814let isPredicatedFalse = 1;
24815let addrMode = BaseImmOffset;
24816let accessSize = HalfWordAccess;
24817let mayStore = 1;
24818let BaseOpcode = "S4_storeirh_io";
24819let CextOpcode = "S2_storerh";
24820let InputType = "imm";
24821let isExtendable = 1;
24822let opExtendable = 3;
24823let isExtentSigned = 1;
24824let opExtentBits = 6;
24825let opExtentAlign = 0;
24826}
24827def S4_storeirhf_zomap : HInst<
24828(outs),
24829(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24830"if (!$Pv4) memh($Rs32) = #$II",
24831tc_d03278fd, TypeMAPPING> {
24832let isPseudo = 1;
24833let isCodeGenOnly = 1;
24834}
24835def S4_storeirhfnew_io : HInst<
24836(outs),
24837(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24838"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
24839tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24840let Inst{31-21} = 0b00111001101;
24841let isPredicated = 1;
24842let isPredicatedFalse = 1;
24843let addrMode = BaseImmOffset;
24844let accessSize = HalfWordAccess;
24845let isPredicatedNew = 1;
24846let mayStore = 1;
24847let BaseOpcode = "S4_storeirh_io";
24848let CextOpcode = "S2_storerh";
24849let InputType = "imm";
24850let isExtendable = 1;
24851let opExtendable = 3;
24852let isExtentSigned = 1;
24853let opExtentBits = 6;
24854let opExtentAlign = 0;
24855}
24856def S4_storeirhfnew_zomap : HInst<
24857(outs),
24858(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24859"if (!$Pv4.new) memh($Rs32) = #$II",
24860tc_65cbd974, TypeMAPPING> {
24861let isPseudo = 1;
24862let isCodeGenOnly = 1;
24863}
24864def S4_storeirht_io : HInst<
24865(outs),
24866(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24867"if ($Pv4) memh($Rs32+#$Ii) = #$II",
24868tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24869let Inst{31-21} = 0b00111000001;
24870let isPredicated = 1;
24871let addrMode = BaseImmOffset;
24872let accessSize = HalfWordAccess;
24873let mayStore = 1;
24874let BaseOpcode = "S4_storeirh_io";
24875let CextOpcode = "S2_storerh";
24876let InputType = "imm";
24877let isExtendable = 1;
24878let opExtendable = 3;
24879let isExtentSigned = 1;
24880let opExtentBits = 6;
24881let opExtentAlign = 0;
24882}
24883def S4_storeirht_zomap : HInst<
24884(outs),
24885(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24886"if ($Pv4) memh($Rs32) = #$II",
24887tc_d03278fd, TypeMAPPING> {
24888let isPseudo = 1;
24889let isCodeGenOnly = 1;
24890}
24891def S4_storeirhtnew_io : HInst<
24892(outs),
24893(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24894"if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
24895tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24896let Inst{31-21} = 0b00111001001;
24897let isPredicated = 1;
24898let addrMode = BaseImmOffset;
24899let accessSize = HalfWordAccess;
24900let isPredicatedNew = 1;
24901let mayStore = 1;
24902let BaseOpcode = "S4_storeirh_io";
24903let CextOpcode = "S2_storerh";
24904let InputType = "imm";
24905let isExtendable = 1;
24906let opExtendable = 3;
24907let isExtentSigned = 1;
24908let opExtentBits = 6;
24909let opExtentAlign = 0;
24910}
24911def S4_storeirhtnew_zomap : HInst<
24912(outs),
24913(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24914"if ($Pv4.new) memh($Rs32) = #$II",
24915tc_65cbd974, TypeMAPPING> {
24916let isPseudo = 1;
24917let isCodeGenOnly = 1;
24918}
24919def S4_storeiri_io : HInst<
24920(outs),
24921(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24922"memw($Rs32+#$Ii) = #$II",
24923tc_7c31e19a, TypeST>, Enc_f37377, PredNewRel {
24924let Inst{31-21} = 0b00111100010;
24925let addrMode = BaseImmOffset;
24926let accessSize = WordAccess;
24927let mayStore = 1;
24928let BaseOpcode = "S4_storeiri_io";
24929let CextOpcode = "S2_storeri";
24930let InputType = "imm";
24931let isPredicable = 1;
24932let isExtendable = 1;
24933let opExtendable = 2;
24934let isExtentSigned = 1;
24935let opExtentBits = 8;
24936let opExtentAlign = 0;
24937}
24938def S4_storeiri_zomap : HInst<
24939(outs),
24940(ins IntRegs:$Rs32, s8_0Imm:$II),
24941"memw($Rs32) = #$II",
24942tc_7c31e19a, TypeMAPPING> {
24943let isPseudo = 1;
24944let isCodeGenOnly = 1;
24945}
24946def S4_storeirif_io : HInst<
24947(outs),
24948(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24949"if (!$Pv4) memw($Rs32+#$Ii) = #$II",
24950tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24951let Inst{31-21} = 0b00111000110;
24952let isPredicated = 1;
24953let isPredicatedFalse = 1;
24954let addrMode = BaseImmOffset;
24955let accessSize = WordAccess;
24956let mayStore = 1;
24957let BaseOpcode = "S4_storeiri_io";
24958let CextOpcode = "S2_storeri";
24959let InputType = "imm";
24960let isExtendable = 1;
24961let opExtendable = 3;
24962let isExtentSigned = 1;
24963let opExtentBits = 6;
24964let opExtentAlign = 0;
24965}
24966def S4_storeirif_zomap : HInst<
24967(outs),
24968(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24969"if (!$Pv4) memw($Rs32) = #$II",
24970tc_d03278fd, TypeMAPPING> {
24971let isPseudo = 1;
24972let isCodeGenOnly = 1;
24973}
24974def S4_storeirifnew_io : HInst<
24975(outs),
24976(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24977"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
24978tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
24979let Inst{31-21} = 0b00111001110;
24980let isPredicated = 1;
24981let isPredicatedFalse = 1;
24982let addrMode = BaseImmOffset;
24983let accessSize = WordAccess;
24984let isPredicatedNew = 1;
24985let mayStore = 1;
24986let BaseOpcode = "S4_storeiri_io";
24987let CextOpcode = "S2_storeri";
24988let InputType = "imm";
24989let isExtendable = 1;
24990let opExtendable = 3;
24991let isExtentSigned = 1;
24992let opExtentBits = 6;
24993let opExtentAlign = 0;
24994}
24995def S4_storeirifnew_zomap : HInst<
24996(outs),
24997(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24998"if (!$Pv4.new) memw($Rs32) = #$II",
24999tc_65cbd974, TypeMAPPING> {
25000let isPseudo = 1;
25001let isCodeGenOnly = 1;
25002}
25003def S4_storeirit_io : HInst<
25004(outs),
25005(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
25006"if ($Pv4) memw($Rs32+#$Ii) = #$II",
25007tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
25008let Inst{31-21} = 0b00111000010;
25009let isPredicated = 1;
25010let addrMode = BaseImmOffset;
25011let accessSize = WordAccess;
25012let mayStore = 1;
25013let BaseOpcode = "S4_storeiri_io";
25014let CextOpcode = "S2_storeri";
25015let InputType = "imm";
25016let isExtendable = 1;
25017let opExtendable = 3;
25018let isExtentSigned = 1;
25019let opExtentBits = 6;
25020let opExtentAlign = 0;
25021}
25022def S4_storeirit_zomap : HInst<
25023(outs),
25024(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
25025"if ($Pv4) memw($Rs32) = #$II",
25026tc_d03278fd, TypeMAPPING> {
25027let isPseudo = 1;
25028let isCodeGenOnly = 1;
25029}
25030def S4_storeiritnew_io : HInst<
25031(outs),
25032(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
25033"if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
25034tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
25035let Inst{31-21} = 0b00111001010;
25036let isPredicated = 1;
25037let addrMode = BaseImmOffset;
25038let accessSize = WordAccess;
25039let isPredicatedNew = 1;
25040let mayStore = 1;
25041let BaseOpcode = "S4_storeiri_io";
25042let CextOpcode = "S2_storeri";
25043let InputType = "imm";
25044let isExtendable = 1;
25045let opExtendable = 3;
25046let isExtentSigned = 1;
25047let opExtentBits = 6;
25048let opExtentAlign = 0;
25049}
25050def S4_storeiritnew_zomap : HInst<
25051(outs),
25052(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
25053"if ($Pv4.new) memw($Rs32) = #$II",
25054tc_65cbd974, TypeMAPPING> {
25055let isPseudo = 1;
25056let isCodeGenOnly = 1;
25057}
25058def S4_storerb_ap : HInst<
25059(outs IntRegs:$Re32),
25060(ins u32_0Imm:$II, IntRegs:$Rt32),
25061"memb($Re32=#$II) = $Rt32",
25062tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25063let Inst{7-6} = 0b10;
25064let Inst{13-13} = 0b0;
25065let Inst{31-21} = 0b10101011000;
25066let addrMode = AbsoluteSet;
25067let accessSize = ByteAccess;
25068let isExtended = 1;
25069let mayStore = 1;
25070let BaseOpcode = "S2_storerb_ap";
25071let isNVStorable = 1;
25072let DecoderNamespace = "MustExtend";
25073let isExtendable = 1;
25074let opExtendable = 1;
25075let isExtentSigned = 0;
25076let opExtentBits = 6;
25077let opExtentAlign = 0;
25078}
25079def S4_storerb_rr : HInst<
25080(outs),
25081(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25082"memb($Rs32+$Ru32<<#$Ii) = $Rt32",
25083tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25084let Inst{6-5} = 0b00;
25085let Inst{31-21} = 0b00111011000;
25086let addrMode = BaseRegOffset;
25087let accessSize = ByteAccess;
25088let mayStore = 1;
25089let BaseOpcode = "S4_storerb_rr";
25090let CextOpcode = "S2_storerb";
25091let InputType = "reg";
25092let isNVStorable = 1;
25093let isPredicable = 1;
25094}
25095def S4_storerb_ur : HInst<
25096(outs),
25097(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25098"memb($Ru32<<#$Ii+#$II) = $Rt32",
25099tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25100let Inst{7-7} = 0b1;
25101let Inst{31-21} = 0b10101101000;
25102let addrMode = BaseLongOffset;
25103let accessSize = ByteAccess;
25104let isExtended = 1;
25105let mayStore = 1;
25106let BaseOpcode = "S4_storerb_ur";
25107let CextOpcode = "S2_storerb";
25108let InputType = "imm";
25109let isNVStorable = 1;
25110let DecoderNamespace = "MustExtend";
25111let isExtendable = 1;
25112let opExtendable = 2;
25113let isExtentSigned = 0;
25114let opExtentBits = 6;
25115let opExtentAlign = 0;
25116}
25117def S4_storerbnew_ap : HInst<
25118(outs IntRegs:$Re32),
25119(ins u32_0Imm:$II, IntRegs:$Nt8),
25120"memb($Re32=#$II) = $Nt8.new",
25121tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25122let Inst{7-6} = 0b10;
25123let Inst{13-11} = 0b000;
25124let Inst{31-21} = 0b10101011101;
25125let addrMode = AbsoluteSet;
25126let accessSize = ByteAccess;
25127let isNVStore = 1;
25128let isNewValue = 1;
25129let isExtended = 1;
25130let isRestrictNoSlot1Store = 1;
25131let mayStore = 1;
25132let BaseOpcode = "S2_storerb_ap";
25133let DecoderNamespace = "MustExtend";
25134let isExtendable = 1;
25135let opExtendable = 1;
25136let isExtentSigned = 0;
25137let opExtentBits = 6;
25138let opExtentAlign = 0;
25139let opNewValue = 2;
25140}
25141def S4_storerbnew_rr : HInst<
25142(outs),
25143(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25144"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25145tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25146let Inst{6-3} = 0b0000;
25147let Inst{31-21} = 0b00111011101;
25148let addrMode = BaseRegOffset;
25149let accessSize = ByteAccess;
25150let isNVStore = 1;
25151let isNewValue = 1;
25152let isRestrictNoSlot1Store = 1;
25153let mayStore = 1;
25154let BaseOpcode = "S4_storerb_rr";
25155let CextOpcode = "S2_storerb";
25156let InputType = "reg";
25157let isPredicable = 1;
25158let opNewValue = 3;
25159}
25160def S4_storerbnew_ur : HInst<
25161(outs),
25162(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25163"memb($Ru32<<#$Ii+#$II) = $Nt8.new",
25164tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25165let Inst{7-7} = 0b1;
25166let Inst{12-11} = 0b00;
25167let Inst{31-21} = 0b10101101101;
25168let addrMode = BaseLongOffset;
25169let accessSize = ByteAccess;
25170let isNVStore = 1;
25171let isNewValue = 1;
25172let isExtended = 1;
25173let isRestrictNoSlot1Store = 1;
25174let mayStore = 1;
25175let BaseOpcode = "S4_storerb_ur";
25176let CextOpcode = "S2_storerb";
25177let DecoderNamespace = "MustExtend";
25178let isExtendable = 1;
25179let opExtendable = 2;
25180let isExtentSigned = 0;
25181let opExtentBits = 6;
25182let opExtentAlign = 0;
25183let opNewValue = 3;
25184}
25185def S4_storerd_ap : HInst<
25186(outs IntRegs:$Re32),
25187(ins u32_0Imm:$II, DoubleRegs:$Rtt32),
25188"memd($Re32=#$II) = $Rtt32",
25189tc_bb07f2c5, TypeST>, Enc_c7a204 {
25190let Inst{7-6} = 0b10;
25191let Inst{13-13} = 0b0;
25192let Inst{31-21} = 0b10101011110;
25193let addrMode = AbsoluteSet;
25194let accessSize = DoubleWordAccess;
25195let isExtended = 1;
25196let mayStore = 1;
25197let BaseOpcode = "S4_storerd_ap";
25198let DecoderNamespace = "MustExtend";
25199let isExtendable = 1;
25200let opExtendable = 1;
25201let isExtentSigned = 0;
25202let opExtentBits = 6;
25203let opExtentAlign = 0;
25204}
25205def S4_storerd_rr : HInst<
25206(outs),
25207(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
25208"memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
25209tc_280f7fe1, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
25210let Inst{6-5} = 0b00;
25211let Inst{31-21} = 0b00111011110;
25212let addrMode = BaseRegOffset;
25213let accessSize = DoubleWordAccess;
25214let mayStore = 1;
25215let BaseOpcode = "S2_storerd_rr";
25216let CextOpcode = "S2_storerd";
25217let InputType = "reg";
25218let isPredicable = 1;
25219}
25220def S4_storerd_ur : HInst<
25221(outs),
25222(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
25223"memd($Ru32<<#$Ii+#$II) = $Rtt32",
25224tc_887d1bb7, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
25225let Inst{7-7} = 0b1;
25226let Inst{31-21} = 0b10101101110;
25227let addrMode = BaseLongOffset;
25228let accessSize = DoubleWordAccess;
25229let isExtended = 1;
25230let mayStore = 1;
25231let BaseOpcode = "S2_storerd_ur";
25232let CextOpcode = "S2_storerd";
25233let InputType = "imm";
25234let DecoderNamespace = "MustExtend";
25235let isExtendable = 1;
25236let opExtendable = 2;
25237let isExtentSigned = 0;
25238let opExtentBits = 6;
25239let opExtentAlign = 0;
25240}
25241def S4_storerf_ap : HInst<
25242(outs IntRegs:$Re32),
25243(ins u32_0Imm:$II, IntRegs:$Rt32),
25244"memh($Re32=#$II) = $Rt32.h",
25245tc_bb07f2c5, TypeST>, Enc_8bcba4 {
25246let Inst{7-6} = 0b10;
25247let Inst{13-13} = 0b0;
25248let Inst{31-21} = 0b10101011011;
25249let addrMode = AbsoluteSet;
25250let accessSize = HalfWordAccess;
25251let isExtended = 1;
25252let mayStore = 1;
25253let BaseOpcode = "S4_storerf_ap";
25254let DecoderNamespace = "MustExtend";
25255let isExtendable = 1;
25256let opExtendable = 1;
25257let isExtentSigned = 0;
25258let opExtentBits = 6;
25259let opExtentAlign = 0;
25260}
25261def S4_storerf_rr : HInst<
25262(outs),
25263(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25264"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
25265tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25266let Inst{6-5} = 0b00;
25267let Inst{31-21} = 0b00111011011;
25268let addrMode = BaseRegOffset;
25269let accessSize = HalfWordAccess;
25270let mayStore = 1;
25271let BaseOpcode = "S4_storerf_rr";
25272let CextOpcode = "S2_storerf";
25273let InputType = "reg";
25274let isPredicable = 1;
25275}
25276def S4_storerf_ur : HInst<
25277(outs),
25278(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25279"memh($Ru32<<#$Ii+#$II) = $Rt32.h",
25280tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25281let Inst{7-7} = 0b1;
25282let Inst{31-21} = 0b10101101011;
25283let addrMode = BaseLongOffset;
25284let accessSize = HalfWordAccess;
25285let isExtended = 1;
25286let mayStore = 1;
25287let BaseOpcode = "S4_storerf_rr";
25288let CextOpcode = "S2_storerf";
25289let InputType = "imm";
25290let DecoderNamespace = "MustExtend";
25291let isExtendable = 1;
25292let opExtendable = 2;
25293let isExtentSigned = 0;
25294let opExtentBits = 6;
25295let opExtentAlign = 0;
25296}
25297def S4_storerh_ap : HInst<
25298(outs IntRegs:$Re32),
25299(ins u32_0Imm:$II, IntRegs:$Rt32),
25300"memh($Re32=#$II) = $Rt32",
25301tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25302let Inst{7-6} = 0b10;
25303let Inst{13-13} = 0b0;
25304let Inst{31-21} = 0b10101011010;
25305let addrMode = AbsoluteSet;
25306let accessSize = HalfWordAccess;
25307let isExtended = 1;
25308let mayStore = 1;
25309let BaseOpcode = "S2_storerh_ap";
25310let isNVStorable = 1;
25311let DecoderNamespace = "MustExtend";
25312let isExtendable = 1;
25313let opExtendable = 1;
25314let isExtentSigned = 0;
25315let opExtentBits = 6;
25316let opExtentAlign = 0;
25317}
25318def S4_storerh_rr : HInst<
25319(outs),
25320(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25321"memh($Rs32+$Ru32<<#$Ii) = $Rt32",
25322tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25323let Inst{6-5} = 0b00;
25324let Inst{31-21} = 0b00111011010;
25325let addrMode = BaseRegOffset;
25326let accessSize = HalfWordAccess;
25327let mayStore = 1;
25328let BaseOpcode = "S2_storerh_rr";
25329let CextOpcode = "S2_storerh";
25330let InputType = "reg";
25331let isNVStorable = 1;
25332let isPredicable = 1;
25333}
25334def S4_storerh_ur : HInst<
25335(outs),
25336(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25337"memh($Ru32<<#$Ii+#$II) = $Rt32",
25338tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25339let Inst{7-7} = 0b1;
25340let Inst{31-21} = 0b10101101010;
25341let addrMode = BaseLongOffset;
25342let accessSize = HalfWordAccess;
25343let isExtended = 1;
25344let mayStore = 1;
25345let BaseOpcode = "S2_storerh_ur";
25346let CextOpcode = "S2_storerh";
25347let InputType = "imm";
25348let isNVStorable = 1;
25349let DecoderNamespace = "MustExtend";
25350let isExtendable = 1;
25351let opExtendable = 2;
25352let isExtentSigned = 0;
25353let opExtentBits = 6;
25354let opExtentAlign = 0;
25355}
25356def S4_storerhnew_ap : HInst<
25357(outs IntRegs:$Re32),
25358(ins u32_0Imm:$II, IntRegs:$Nt8),
25359"memh($Re32=#$II) = $Nt8.new",
25360tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25361let Inst{7-6} = 0b10;
25362let Inst{13-11} = 0b001;
25363let Inst{31-21} = 0b10101011101;
25364let addrMode = AbsoluteSet;
25365let accessSize = HalfWordAccess;
25366let isNVStore = 1;
25367let isNewValue = 1;
25368let isExtended = 1;
25369let isRestrictNoSlot1Store = 1;
25370let mayStore = 1;
25371let BaseOpcode = "S2_storerh_ap";
25372let DecoderNamespace = "MustExtend";
25373let isExtendable = 1;
25374let opExtendable = 1;
25375let isExtentSigned = 0;
25376let opExtentBits = 6;
25377let opExtentAlign = 0;
25378let opNewValue = 2;
25379}
25380def S4_storerhnew_rr : HInst<
25381(outs),
25382(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25383"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25384tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25385let Inst{6-3} = 0b0001;
25386let Inst{31-21} = 0b00111011101;
25387let addrMode = BaseRegOffset;
25388let accessSize = HalfWordAccess;
25389let isNVStore = 1;
25390let isNewValue = 1;
25391let isRestrictNoSlot1Store = 1;
25392let mayStore = 1;
25393let BaseOpcode = "S2_storerh_rr";
25394let CextOpcode = "S2_storerh";
25395let InputType = "reg";
25396let isPredicable = 1;
25397let opNewValue = 3;
25398}
25399def S4_storerhnew_ur : HInst<
25400(outs),
25401(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25402"memh($Ru32<<#$Ii+#$II) = $Nt8.new",
25403tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25404let Inst{7-7} = 0b1;
25405let Inst{12-11} = 0b01;
25406let Inst{31-21} = 0b10101101101;
25407let addrMode = BaseLongOffset;
25408let accessSize = HalfWordAccess;
25409let isNVStore = 1;
25410let isNewValue = 1;
25411let isExtended = 1;
25412let isRestrictNoSlot1Store = 1;
25413let mayStore = 1;
25414let BaseOpcode = "S2_storerh_ur";
25415let CextOpcode = "S2_storerh";
25416let DecoderNamespace = "MustExtend";
25417let isExtendable = 1;
25418let opExtendable = 2;
25419let isExtentSigned = 0;
25420let opExtentBits = 6;
25421let opExtentAlign = 0;
25422let opNewValue = 3;
25423}
25424def S4_storeri_ap : HInst<
25425(outs IntRegs:$Re32),
25426(ins u32_0Imm:$II, IntRegs:$Rt32),
25427"memw($Re32=#$II) = $Rt32",
25428tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25429let Inst{7-6} = 0b10;
25430let Inst{13-13} = 0b0;
25431let Inst{31-21} = 0b10101011100;
25432let addrMode = AbsoluteSet;
25433let accessSize = WordAccess;
25434let isExtended = 1;
25435let mayStore = 1;
25436let BaseOpcode = "S2_storeri_ap";
25437let isNVStorable = 1;
25438let DecoderNamespace = "MustExtend";
25439let isExtendable = 1;
25440let opExtendable = 1;
25441let isExtentSigned = 0;
25442let opExtentBits = 6;
25443let opExtentAlign = 0;
25444}
25445def S4_storeri_rr : HInst<
25446(outs),
25447(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25448"memw($Rs32+$Ru32<<#$Ii) = $Rt32",
25449tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25450let Inst{6-5} = 0b00;
25451let Inst{31-21} = 0b00111011100;
25452let addrMode = BaseRegOffset;
25453let accessSize = WordAccess;
25454let mayStore = 1;
25455let BaseOpcode = "S2_storeri_rr";
25456let CextOpcode = "S2_storeri";
25457let InputType = "reg";
25458let isNVStorable = 1;
25459let isPredicable = 1;
25460}
25461def S4_storeri_ur : HInst<
25462(outs),
25463(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25464"memw($Ru32<<#$Ii+#$II) = $Rt32",
25465tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25466let Inst{7-7} = 0b1;
25467let Inst{31-21} = 0b10101101100;
25468let addrMode = BaseLongOffset;
25469let accessSize = WordAccess;
25470let isExtended = 1;
25471let mayStore = 1;
25472let BaseOpcode = "S2_storeri_ur";
25473let CextOpcode = "S2_storeri";
25474let InputType = "imm";
25475let isNVStorable = 1;
25476let DecoderNamespace = "MustExtend";
25477let isExtendable = 1;
25478let opExtendable = 2;
25479let isExtentSigned = 0;
25480let opExtentBits = 6;
25481let opExtentAlign = 0;
25482}
25483def S4_storerinew_ap : HInst<
25484(outs IntRegs:$Re32),
25485(ins u32_0Imm:$II, IntRegs:$Nt8),
25486"memw($Re32=#$II) = $Nt8.new",
25487tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25488let Inst{7-6} = 0b10;
25489let Inst{13-11} = 0b010;
25490let Inst{31-21} = 0b10101011101;
25491let addrMode = AbsoluteSet;
25492let accessSize = WordAccess;
25493let isNVStore = 1;
25494let isNewValue = 1;
25495let isExtended = 1;
25496let isRestrictNoSlot1Store = 1;
25497let mayStore = 1;
25498let BaseOpcode = "S2_storeri_ap";
25499let DecoderNamespace = "MustExtend";
25500let isExtendable = 1;
25501let opExtendable = 1;
25502let isExtentSigned = 0;
25503let opExtentBits = 6;
25504let opExtentAlign = 0;
25505let opNewValue = 2;
25506}
25507def S4_storerinew_rr : HInst<
25508(outs),
25509(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25510"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25511tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25512let Inst{6-3} = 0b0010;
25513let Inst{31-21} = 0b00111011101;
25514let addrMode = BaseRegOffset;
25515let accessSize = WordAccess;
25516let isNVStore = 1;
25517let isNewValue = 1;
25518let isRestrictNoSlot1Store = 1;
25519let mayStore = 1;
25520let BaseOpcode = "S2_storeri_rr";
25521let CextOpcode = "S2_storeri";
25522let InputType = "reg";
25523let isPredicable = 1;
25524let opNewValue = 3;
25525}
25526def S4_storerinew_ur : HInst<
25527(outs),
25528(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25529"memw($Ru32<<#$Ii+#$II) = $Nt8.new",
25530tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25531let Inst{7-7} = 0b1;
25532let Inst{12-11} = 0b10;
25533let Inst{31-21} = 0b10101101101;
25534let addrMode = BaseLongOffset;
25535let accessSize = WordAccess;
25536let isNVStore = 1;
25537let isNewValue = 1;
25538let isExtended = 1;
25539let isRestrictNoSlot1Store = 1;
25540let mayStore = 1;
25541let BaseOpcode = "S2_storeri_ur";
25542let CextOpcode = "S2_storeri";
25543let DecoderNamespace = "MustExtend";
25544let isExtendable = 1;
25545let opExtendable = 2;
25546let isExtentSigned = 0;
25547let opExtentBits = 6;
25548let opExtentAlign = 0;
25549let opNewValue = 3;
25550}
25551def S4_subaddi : HInst<
25552(outs IntRegs:$Rd32),
25553(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
25554"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
25555tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
25556let Inst{31-23} = 0b110110111;
25557let hasNewValue = 1;
25558let opNewValue = 0;
25559let prefersSlot3 = 1;
25560let isExtendable = 1;
25561let opExtendable = 2;
25562let isExtentSigned = 1;
25563let opExtentBits = 6;
25564let opExtentAlign = 0;
25565}
25566def S4_subi_asl_ri : HInst<
25567(outs IntRegs:$Rx32),
25568(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25569"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
25570tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25571let Inst{2-0} = 0b110;
25572let Inst{4-4} = 0b0;
25573let Inst{31-24} = 0b11011110;
25574let hasNewValue = 1;
25575let opNewValue = 0;
25576let prefersSlot3 = 1;
25577let isExtendable = 1;
25578let opExtendable = 1;
25579let isExtentSigned = 0;
25580let opExtentBits = 8;
25581let opExtentAlign = 0;
25582let Constraints = "$Rx32 = $Rx32in";
25583}
25584def S4_subi_lsr_ri : HInst<
25585(outs IntRegs:$Rx32),
25586(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25587"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
25588tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25589let Inst{2-0} = 0b110;
25590let Inst{4-4} = 0b1;
25591let Inst{31-24} = 0b11011110;
25592let hasNewValue = 1;
25593let opNewValue = 0;
25594let prefersSlot3 = 1;
25595let isExtendable = 1;
25596let opExtendable = 1;
25597let isExtentSigned = 0;
25598let opExtentBits = 8;
25599let opExtentAlign = 0;
25600let Constraints = "$Rx32 = $Rx32in";
25601}
25602def S4_vrcrotate : HInst<
25603(outs DoubleRegs:$Rdd32),
25604(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25605"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
25606tc_f0cdeccf, TypeS_3op>, Enc_645d54 {
25607let Inst{7-6} = 0b11;
25608let Inst{31-21} = 0b11000011110;
25609let prefersSlot3 = 1;
25610}
25611def S4_vrcrotate_acc : HInst<
25612(outs DoubleRegs:$Rxx32),
25613(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25614"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
25615tc_a38c45dc, TypeS_3op>, Enc_b72622 {
25616let Inst{7-6} = 0b00;
25617let Inst{31-21} = 0b11001011101;
25618let prefersSlot3 = 1;
25619let Constraints = "$Rxx32 = $Rxx32in";
25620}
25621def S4_vxaddsubh : HInst<
25622(outs DoubleRegs:$Rdd32),
25623(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25624"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
25625tc_8a825db2, TypeS_3op>, Enc_a56825 {
25626let Inst{7-5} = 0b100;
25627let Inst{13-13} = 0b0;
25628let Inst{31-21} = 0b11000001010;
25629let prefersSlot3 = 1;
25630let Defs = [USR_OVF];
25631}
25632def S4_vxaddsubhr : HInst<
25633(outs DoubleRegs:$Rdd32),
25634(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25635"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
25636tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25637let Inst{7-5} = 0b000;
25638let Inst{13-13} = 0b0;
25639let Inst{31-21} = 0b11000001110;
25640let prefersSlot3 = 1;
25641let Defs = [USR_OVF];
25642}
25643def S4_vxaddsubw : HInst<
25644(outs DoubleRegs:$Rdd32),
25645(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25646"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
25647tc_8a825db2, TypeS_3op>, Enc_a56825 {
25648let Inst{7-5} = 0b000;
25649let Inst{13-13} = 0b0;
25650let Inst{31-21} = 0b11000001010;
25651let prefersSlot3 = 1;
25652let Defs = [USR_OVF];
25653}
25654def S4_vxsubaddh : HInst<
25655(outs DoubleRegs:$Rdd32),
25656(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25657"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
25658tc_8a825db2, TypeS_3op>, Enc_a56825 {
25659let Inst{7-5} = 0b110;
25660let Inst{13-13} = 0b0;
25661let Inst{31-21} = 0b11000001010;
25662let prefersSlot3 = 1;
25663let Defs = [USR_OVF];
25664}
25665def S4_vxsubaddhr : HInst<
25666(outs DoubleRegs:$Rdd32),
25667(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25668"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
25669tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25670let Inst{7-5} = 0b010;
25671let Inst{13-13} = 0b0;
25672let Inst{31-21} = 0b11000001110;
25673let prefersSlot3 = 1;
25674let Defs = [USR_OVF];
25675}
25676def S4_vxsubaddw : HInst<
25677(outs DoubleRegs:$Rdd32),
25678(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25679"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
25680tc_8a825db2, TypeS_3op>, Enc_a56825 {
25681let Inst{7-5} = 0b010;
25682let Inst{13-13} = 0b0;
25683let Inst{31-21} = 0b11000001010;
25684let prefersSlot3 = 1;
25685let Defs = [USR_OVF];
25686}
25687def S5_asrhub_rnd_sat : HInst<
25688(outs IntRegs:$Rd32),
25689(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25690"$Rd32 = vasrhub($Rss32,#$Ii):raw",
25691tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25692let Inst{7-5} = 0b100;
25693let Inst{13-12} = 0b00;
25694let Inst{31-21} = 0b10001000011;
25695let hasNewValue = 1;
25696let opNewValue = 0;
25697let prefersSlot3 = 1;
25698let Defs = [USR_OVF];
25699}
25700def S5_asrhub_rnd_sat_goodsyntax : HInst<
25701(outs IntRegs:$Rd32),
25702(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25703"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
25704tc_0dfac0a7, TypeS_2op> {
25705let hasNewValue = 1;
25706let opNewValue = 0;
25707let isPseudo = 1;
25708}
25709def S5_asrhub_sat : HInst<
25710(outs IntRegs:$Rd32),
25711(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25712"$Rd32 = vasrhub($Rss32,#$Ii):sat",
25713tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25714let Inst{7-5} = 0b101;
25715let Inst{13-12} = 0b00;
25716let Inst{31-21} = 0b10001000011;
25717let hasNewValue = 1;
25718let opNewValue = 0;
25719let prefersSlot3 = 1;
25720let Defs = [USR_OVF];
25721}
25722def S5_popcountp : HInst<
25723(outs IntRegs:$Rd32),
25724(ins DoubleRegs:$Rss32),
25725"$Rd32 = popcount($Rss32)",
25726tc_d3632d88, TypeS_2op>, Enc_90cd8b {
25727let Inst{13-5} = 0b000000011;
25728let Inst{31-21} = 0b10001000011;
25729let hasNewValue = 1;
25730let opNewValue = 0;
25731let prefersSlot3 = 1;
25732}
25733def S5_vasrhrnd : HInst<
25734(outs DoubleRegs:$Rdd32),
25735(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25736"$Rdd32 = vasrh($Rss32,#$Ii):raw",
25737tc_0dfac0a7, TypeS_2op>, Enc_12b6e9 {
25738let Inst{7-5} = 0b000;
25739let Inst{13-12} = 0b00;
25740let Inst{31-21} = 0b10000000001;
25741let prefersSlot3 = 1;
25742}
25743def S5_vasrhrnd_goodsyntax : HInst<
25744(outs DoubleRegs:$Rdd32),
25745(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25746"$Rdd32 = vasrh($Rss32,#$Ii):rnd",
25747tc_0dfac0a7, TypeS_2op> {
25748let isPseudo = 1;
25749}
25750def S6_allocframe_to_raw : HInst<
25751(outs),
25752(ins u11_3Imm:$Ii),
25753"allocframe(#$Ii)",
25754tc_934753bb, TypeMAPPING>, Requires<[HasV65]> {
25755let isPseudo = 1;
25756let isCodeGenOnly = 1;
25757}
25758def S6_rol_i_p : HInst<
25759(outs DoubleRegs:$Rdd32),
25760(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
25761"$Rdd32 = rol($Rss32,#$Ii)",
25762tc_407e96f9, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> {
25763let Inst{7-5} = 0b011;
25764let Inst{31-21} = 0b10000000000;
25765}
25766def S6_rol_i_p_acc : HInst<
25767(outs DoubleRegs:$Rxx32),
25768(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25769"$Rxx32 += rol($Rss32,#$Ii)",
25770tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25771let Inst{7-5} = 0b111;
25772let Inst{31-21} = 0b10000010000;
25773let prefersSlot3 = 1;
25774let Constraints = "$Rxx32 = $Rxx32in";
25775}
25776def S6_rol_i_p_and : HInst<
25777(outs DoubleRegs:$Rxx32),
25778(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25779"$Rxx32 &= rol($Rss32,#$Ii)",
25780tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25781let Inst{7-5} = 0b011;
25782let Inst{31-21} = 0b10000010010;
25783let prefersSlot3 = 1;
25784let Constraints = "$Rxx32 = $Rxx32in";
25785}
25786def S6_rol_i_p_nac : HInst<
25787(outs DoubleRegs:$Rxx32),
25788(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25789"$Rxx32 -= rol($Rss32,#$Ii)",
25790tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25791let Inst{7-5} = 0b011;
25792let Inst{31-21} = 0b10000010000;
25793let prefersSlot3 = 1;
25794let Constraints = "$Rxx32 = $Rxx32in";
25795}
25796def S6_rol_i_p_or : HInst<
25797(outs DoubleRegs:$Rxx32),
25798(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25799"$Rxx32 |= rol($Rss32,#$Ii)",
25800tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25801let Inst{7-5} = 0b111;
25802let Inst{31-21} = 0b10000010010;
25803let prefersSlot3 = 1;
25804let Constraints = "$Rxx32 = $Rxx32in";
25805}
25806def S6_rol_i_p_xacc : HInst<
25807(outs DoubleRegs:$Rxx32),
25808(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25809"$Rxx32 ^= rol($Rss32,#$Ii)",
25810tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25811let Inst{7-5} = 0b011;
25812let Inst{31-21} = 0b10000010100;
25813let prefersSlot3 = 1;
25814let Constraints = "$Rxx32 = $Rxx32in";
25815}
25816def S6_rol_i_r : HInst<
25817(outs IntRegs:$Rd32),
25818(ins IntRegs:$Rs32, u5_0Imm:$Ii),
25819"$Rd32 = rol($Rs32,#$Ii)",
25820tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV60]> {
25821let Inst{7-5} = 0b011;
25822let Inst{13-13} = 0b0;
25823let Inst{31-21} = 0b10001100000;
25824let hasNewValue = 1;
25825let opNewValue = 0;
25826}
25827def S6_rol_i_r_acc : HInst<
25828(outs IntRegs:$Rx32),
25829(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25830"$Rx32 += rol($Rs32,#$Ii)",
25831tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25832let Inst{7-5} = 0b111;
25833let Inst{13-13} = 0b0;
25834let Inst{31-21} = 0b10001110000;
25835let hasNewValue = 1;
25836let opNewValue = 0;
25837let prefersSlot3 = 1;
25838let Constraints = "$Rx32 = $Rx32in";
25839}
25840def S6_rol_i_r_and : HInst<
25841(outs IntRegs:$Rx32),
25842(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25843"$Rx32 &= rol($Rs32,#$Ii)",
25844tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25845let Inst{7-5} = 0b011;
25846let Inst{13-13} = 0b0;
25847let Inst{31-21} = 0b10001110010;
25848let hasNewValue = 1;
25849let opNewValue = 0;
25850let prefersSlot3 = 1;
25851let Constraints = "$Rx32 = $Rx32in";
25852}
25853def S6_rol_i_r_nac : HInst<
25854(outs IntRegs:$Rx32),
25855(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25856"$Rx32 -= rol($Rs32,#$Ii)",
25857tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25858let Inst{7-5} = 0b011;
25859let Inst{13-13} = 0b0;
25860let Inst{31-21} = 0b10001110000;
25861let hasNewValue = 1;
25862let opNewValue = 0;
25863let prefersSlot3 = 1;
25864let Constraints = "$Rx32 = $Rx32in";
25865}
25866def S6_rol_i_r_or : HInst<
25867(outs IntRegs:$Rx32),
25868(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25869"$Rx32 |= rol($Rs32,#$Ii)",
25870tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25871let Inst{7-5} = 0b111;
25872let Inst{13-13} = 0b0;
25873let Inst{31-21} = 0b10001110010;
25874let hasNewValue = 1;
25875let opNewValue = 0;
25876let prefersSlot3 = 1;
25877let Constraints = "$Rx32 = $Rx32in";
25878}
25879def S6_rol_i_r_xacc : HInst<
25880(outs IntRegs:$Rx32),
25881(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25882"$Rx32 ^= rol($Rs32,#$Ii)",
25883tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25884let Inst{7-5} = 0b011;
25885let Inst{13-13} = 0b0;
25886let Inst{31-21} = 0b10001110100;
25887let hasNewValue = 1;
25888let opNewValue = 0;
25889let prefersSlot3 = 1;
25890let Constraints = "$Rx32 = $Rx32in";
25891}
25892def S6_vsplatrbp : HInst<
25893(outs DoubleRegs:$Rdd32),
25894(ins IntRegs:$Rs32),
25895"$Rdd32 = vsplatb($Rs32)",
25896tc_ef921005, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> {
25897let Inst{13-5} = 0b000000100;
25898let Inst{31-21} = 0b10000100010;
25899}
25900def S6_vtrunehb_ppp : HInst<
25901(outs DoubleRegs:$Rdd32),
25902(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25903"$Rdd32 = vtrunehb($Rss32,$Rtt32)",
25904tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25905let Inst{7-5} = 0b011;
25906let Inst{13-13} = 0b0;
25907let Inst{31-21} = 0b11000001100;
25908}
25909def S6_vtrunohb_ppp : HInst<
25910(outs DoubleRegs:$Rdd32),
25911(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25912"$Rdd32 = vtrunohb($Rss32,$Rtt32)",
25913tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25914let Inst{7-5} = 0b101;
25915let Inst{13-13} = 0b0;
25916let Inst{31-21} = 0b11000001100;
25917}
25918def SA1_addi : HInst<
25919(outs GeneralSubRegs:$Rx16),
25920(ins GeneralSubRegs:$Rx16in, s32_0Imm:$Ii),
25921"$Rx16 = add($Rx16in,#$Ii)",
25922tc_5b347363, TypeSUBINSN>, Enc_93af4c {
25923let Inst{12-11} = 0b00;
25924let hasNewValue = 1;
25925let opNewValue = 0;
25926let AsmVariantName = "NonParsable";
25927let DecoderNamespace = "SUBINSN_A";
25928let isExtendable = 1;
25929let opExtendable = 2;
25930let isExtentSigned = 1;
25931let opExtentBits = 7;
25932let opExtentAlign = 0;
25933let Constraints = "$Rx16 = $Rx16in";
25934}
25935def SA1_addrx : HInst<
25936(outs GeneralSubRegs:$Rx16),
25937(ins GeneralSubRegs:$Rx16in, GeneralSubRegs:$Rs16),
25938"$Rx16 = add($Rx16in,$Rs16)",
25939tc_5b347363, TypeSUBINSN>, Enc_0527db {
25940let Inst{12-8} = 0b11000;
25941let hasNewValue = 1;
25942let opNewValue = 0;
25943let AsmVariantName = "NonParsable";
25944let DecoderNamespace = "SUBINSN_A";
25945let Constraints = "$Rx16 = $Rx16in";
25946}
25947def SA1_addsp : HInst<
25948(outs GeneralSubRegs:$Rd16),
25949(ins u6_2Imm:$Ii),
25950"$Rd16 = add(r29,#$Ii)",
25951tc_3d14a17b, TypeSUBINSN>, Enc_2df31d {
25952let Inst{12-10} = 0b011;
25953let hasNewValue = 1;
25954let opNewValue = 0;
25955let AsmVariantName = "NonParsable";
25956let Uses = [R29];
25957let DecoderNamespace = "SUBINSN_A";
25958}
25959def SA1_and1 : HInst<
25960(outs GeneralSubRegs:$Rd16),
25961(ins GeneralSubRegs:$Rs16),
25962"$Rd16 = and($Rs16,#1)",
25963tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
25964let Inst{12-8} = 0b10010;
25965let hasNewValue = 1;
25966let opNewValue = 0;
25967let AsmVariantName = "NonParsable";
25968let DecoderNamespace = "SUBINSN_A";
25969}
25970def SA1_clrf : HInst<
25971(outs GeneralSubRegs:$Rd16),
25972(ins),
25973"if (!p0) $Rd16 = #0",
25974tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25975let Inst{12-4} = 0b110100111;
25976let isPredicated = 1;
25977let isPredicatedFalse = 1;
25978let hasNewValue = 1;
25979let opNewValue = 0;
25980let AsmVariantName = "NonParsable";
25981let Uses = [P0];
25982let DecoderNamespace = "SUBINSN_A";
25983}
25984def SA1_clrfnew : HInst<
25985(outs GeneralSubRegs:$Rd16),
25986(ins),
25987"if (!p0.new) $Rd16 = #0",
25988tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
25989let Inst{12-4} = 0b110100101;
25990let isPredicated = 1;
25991let isPredicatedFalse = 1;
25992let hasNewValue = 1;
25993let opNewValue = 0;
25994let AsmVariantName = "NonParsable";
25995let isPredicatedNew = 1;
25996let Uses = [P0];
25997let DecoderNamespace = "SUBINSN_A";
25998}
25999def SA1_clrt : HInst<
26000(outs GeneralSubRegs:$Rd16),
26001(ins),
26002"if (p0) $Rd16 = #0",
26003tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
26004let Inst{12-4} = 0b110100110;
26005let isPredicated = 1;
26006let hasNewValue = 1;
26007let opNewValue = 0;
26008let AsmVariantName = "NonParsable";
26009let Uses = [P0];
26010let DecoderNamespace = "SUBINSN_A";
26011}
26012def SA1_clrtnew : HInst<
26013(outs GeneralSubRegs:$Rd16),
26014(ins),
26015"if (p0.new) $Rd16 = #0",
26016tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
26017let Inst{12-4} = 0b110100100;
26018let isPredicated = 1;
26019let hasNewValue = 1;
26020let opNewValue = 0;
26021let AsmVariantName = "NonParsable";
26022let isPredicatedNew = 1;
26023let Uses = [P0];
26024let DecoderNamespace = "SUBINSN_A";
26025}
26026def SA1_cmpeqi : HInst<
26027(outs),
26028(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
26029"p0 = cmp.eq($Rs16,#$Ii)",
26030tc_59a7822c, TypeSUBINSN>, Enc_63eaeb {
26031let Inst{3-2} = 0b00;
26032let Inst{12-8} = 0b11001;
26033let AsmVariantName = "NonParsable";
26034let Defs = [P0];
26035let DecoderNamespace = "SUBINSN_A";
26036}
26037def SA1_combine0i : HInst<
26038(outs GeneralDoubleLow8Regs:$Rdd8),
26039(ins u2_0Imm:$Ii),
26040"$Rdd8 = combine(#0,#$Ii)",
26041tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26042let Inst{4-3} = 0b00;
26043let Inst{12-7} = 0b111000;
26044let hasNewValue = 1;
26045let opNewValue = 0;
26046let AsmVariantName = "NonParsable";
26047let DecoderNamespace = "SUBINSN_A";
26048}
26049def SA1_combine1i : HInst<
26050(outs GeneralDoubleLow8Regs:$Rdd8),
26051(ins u2_0Imm:$Ii),
26052"$Rdd8 = combine(#1,#$Ii)",
26053tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26054let Inst{4-3} = 0b01;
26055let Inst{12-7} = 0b111000;
26056let hasNewValue = 1;
26057let opNewValue = 0;
26058let AsmVariantName = "NonParsable";
26059let DecoderNamespace = "SUBINSN_A";
26060}
26061def SA1_combine2i : HInst<
26062(outs GeneralDoubleLow8Regs:$Rdd8),
26063(ins u2_0Imm:$Ii),
26064"$Rdd8 = combine(#2,#$Ii)",
26065tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26066let Inst{4-3} = 0b10;
26067let Inst{12-7} = 0b111000;
26068let hasNewValue = 1;
26069let opNewValue = 0;
26070let AsmVariantName = "NonParsable";
26071let DecoderNamespace = "SUBINSN_A";
26072}
26073def SA1_combine3i : HInst<
26074(outs GeneralDoubleLow8Regs:$Rdd8),
26075(ins u2_0Imm:$Ii),
26076"$Rdd8 = combine(#3,#$Ii)",
26077tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26078let Inst{4-3} = 0b11;
26079let Inst{12-7} = 0b111000;
26080let hasNewValue = 1;
26081let opNewValue = 0;
26082let AsmVariantName = "NonParsable";
26083let DecoderNamespace = "SUBINSN_A";
26084}
26085def SA1_combinerz : HInst<
26086(outs GeneralDoubleLow8Regs:$Rdd8),
26087(ins GeneralSubRegs:$Rs16),
26088"$Rdd8 = combine($Rs16,#0)",
26089tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26090let Inst{3-3} = 0b1;
26091let Inst{12-8} = 0b11101;
26092let hasNewValue = 1;
26093let opNewValue = 0;
26094let AsmVariantName = "NonParsable";
26095let DecoderNamespace = "SUBINSN_A";
26096}
26097def SA1_combinezr : HInst<
26098(outs GeneralDoubleLow8Regs:$Rdd8),
26099(ins GeneralSubRegs:$Rs16),
26100"$Rdd8 = combine(#0,$Rs16)",
26101tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26102let Inst{3-3} = 0b0;
26103let Inst{12-8} = 0b11101;
26104let hasNewValue = 1;
26105let opNewValue = 0;
26106let AsmVariantName = "NonParsable";
26107let DecoderNamespace = "SUBINSN_A";
26108}
26109def SA1_dec : HInst<
26110(outs GeneralSubRegs:$Rd16),
26111(ins GeneralSubRegs:$Rs16, n1Const:$n1),
26112"$Rd16 = add($Rs16,#$n1)",
26113tc_5b347363, TypeSUBINSN>, Enc_ee5ed0 {
26114let Inst{12-8} = 0b10011;
26115let hasNewValue = 1;
26116let opNewValue = 0;
26117let AsmVariantName = "NonParsable";
26118let DecoderNamespace = "SUBINSN_A";
26119}
26120def SA1_inc : HInst<
26121(outs GeneralSubRegs:$Rd16),
26122(ins GeneralSubRegs:$Rs16),
26123"$Rd16 = add($Rs16,#1)",
26124tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26125let Inst{12-8} = 0b10001;
26126let hasNewValue = 1;
26127let opNewValue = 0;
26128let AsmVariantName = "NonParsable";
26129let DecoderNamespace = "SUBINSN_A";
26130}
26131def SA1_seti : HInst<
26132(outs GeneralSubRegs:$Rd16),
26133(ins u32_0Imm:$Ii),
26134"$Rd16 = #$Ii",
26135tc_3d14a17b, TypeSUBINSN>, Enc_e39bb2 {
26136let Inst{12-10} = 0b010;
26137let hasNewValue = 1;
26138let opNewValue = 0;
26139let AsmVariantName = "NonParsable";
26140let DecoderNamespace = "SUBINSN_A";
26141let isExtendable = 1;
26142let opExtendable = 1;
26143let isExtentSigned = 0;
26144let opExtentBits = 6;
26145let opExtentAlign = 0;
26146}
26147def SA1_setin1 : HInst<
26148(outs GeneralSubRegs:$Rd16),
26149(ins n1Const:$n1),
26150"$Rd16 = #$n1",
26151tc_3d14a17b, TypeSUBINSN>, Enc_7a0ea6 {
26152let Inst{12-4} = 0b110100000;
26153let hasNewValue = 1;
26154let opNewValue = 0;
26155let AsmVariantName = "NonParsable";
26156let DecoderNamespace = "SUBINSN_A";
26157}
26158def SA1_sxtb : HInst<
26159(outs GeneralSubRegs:$Rd16),
26160(ins GeneralSubRegs:$Rs16),
26161"$Rd16 = sxtb($Rs16)",
26162tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26163let Inst{12-8} = 0b10101;
26164let hasNewValue = 1;
26165let opNewValue = 0;
26166let AsmVariantName = "NonParsable";
26167let DecoderNamespace = "SUBINSN_A";
26168}
26169def SA1_sxth : HInst<
26170(outs GeneralSubRegs:$Rd16),
26171(ins GeneralSubRegs:$Rs16),
26172"$Rd16 = sxth($Rs16)",
26173tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26174let Inst{12-8} = 0b10100;
26175let hasNewValue = 1;
26176let opNewValue = 0;
26177let AsmVariantName = "NonParsable";
26178let DecoderNamespace = "SUBINSN_A";
26179}
26180def SA1_tfr : HInst<
26181(outs GeneralSubRegs:$Rd16),
26182(ins GeneralSubRegs:$Rs16),
26183"$Rd16 = $Rs16",
26184tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26185let Inst{12-8} = 0b10000;
26186let hasNewValue = 1;
26187let opNewValue = 0;
26188let AsmVariantName = "NonParsable";
26189let DecoderNamespace = "SUBINSN_A";
26190}
26191def SA1_zxtb : HInst<
26192(outs GeneralSubRegs:$Rd16),
26193(ins GeneralSubRegs:$Rs16),
26194"$Rd16 = and($Rs16,#255)",
26195tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26196let Inst{12-8} = 0b10111;
26197let hasNewValue = 1;
26198let opNewValue = 0;
26199let AsmVariantName = "NonParsable";
26200let DecoderNamespace = "SUBINSN_A";
26201}
26202def SA1_zxth : HInst<
26203(outs GeneralSubRegs:$Rd16),
26204(ins GeneralSubRegs:$Rs16),
26205"$Rd16 = zxth($Rs16)",
26206tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26207let Inst{12-8} = 0b10110;
26208let hasNewValue = 1;
26209let opNewValue = 0;
26210let AsmVariantName = "NonParsable";
26211let DecoderNamespace = "SUBINSN_A";
26212}
26213def SL1_loadri_io : HInst<
26214(outs GeneralSubRegs:$Rd16),
26215(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26216"$Rd16 = memw($Rs16+#$Ii)",
26217tc_4222e6bf, TypeSUBINSN>, Enc_53dca9 {
26218let Inst{12-12} = 0b0;
26219let hasNewValue = 1;
26220let opNewValue = 0;
26221let addrMode = BaseImmOffset;
26222let accessSize = WordAccess;
26223let AsmVariantName = "NonParsable";
26224let mayLoad = 1;
26225let DecoderNamespace = "SUBINSN_L1";
26226}
26227def SL1_loadrub_io : HInst<
26228(outs GeneralSubRegs:$Rd16),
26229(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26230"$Rd16 = memub($Rs16+#$Ii)",
26231tc_4222e6bf, TypeSUBINSN>, Enc_c175d0 {
26232let Inst{12-12} = 0b1;
26233let hasNewValue = 1;
26234let opNewValue = 0;
26235let addrMode = BaseImmOffset;
26236let accessSize = ByteAccess;
26237let AsmVariantName = "NonParsable";
26238let mayLoad = 1;
26239let DecoderNamespace = "SUBINSN_L1";
26240}
26241def SL2_deallocframe : HInst<
26242(outs),
26243(ins),
26244"deallocframe",
26245tc_937dd41c, TypeSUBINSN>, Enc_e3b0c4 {
26246let Inst{12-0} = 0b1111100000000;
26247let accessSize = DoubleWordAccess;
26248let AsmVariantName = "NonParsable";
26249let mayLoad = 1;
26250let Uses = [FRAMEKEY, R30];
26251let Defs = [R29, R30, R31];
26252let DecoderNamespace = "SUBINSN_L2";
26253}
26254def SL2_jumpr31 : HInst<
26255(outs),
26256(ins),
26257"jumpr r31",
26258tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26259let Inst{12-0} = 0b1111111000000;
26260let isTerminator = 1;
26261let isIndirectBranch = 1;
26262let AsmVariantName = "NonParsable";
26263let cofMax1 = 1;
26264let isReturn = 1;
26265let Uses = [R31];
26266let Defs = [PC];
26267let DecoderNamespace = "SUBINSN_L2";
26268}
26269def SL2_jumpr31_f : HInst<
26270(outs),
26271(ins),
26272"if (!p0) jumpr r31",
26273tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26274let Inst{12-0} = 0b1111111000101;
26275let isPredicated = 1;
26276let isPredicatedFalse = 1;
26277let isTerminator = 1;
26278let isIndirectBranch = 1;
26279let AsmVariantName = "NonParsable";
26280let cofMax1 = 1;
26281let isReturn = 1;
26282let Uses = [P0, R31];
26283let Defs = [PC];
26284let isTaken = Inst{4};
26285let DecoderNamespace = "SUBINSN_L2";
26286}
26287def SL2_jumpr31_fnew : HInst<
26288(outs),
26289(ins),
26290"if (!p0.new) jumpr:nt r31",
26291tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26292let Inst{12-0} = 0b1111111000111;
26293let isPredicated = 1;
26294let isPredicatedFalse = 1;
26295let isTerminator = 1;
26296let isIndirectBranch = 1;
26297let AsmVariantName = "NonParsable";
26298let isPredicatedNew = 1;
26299let cofMax1 = 1;
26300let isReturn = 1;
26301let Uses = [P0, R31];
26302let Defs = [PC];
26303let isTaken = Inst{4};
26304let DecoderNamespace = "SUBINSN_L2";
26305}
26306def SL2_jumpr31_t : HInst<
26307(outs),
26308(ins),
26309"if (p0) jumpr r31",
26310tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26311let Inst{12-0} = 0b1111111000100;
26312let isPredicated = 1;
26313let isTerminator = 1;
26314let isIndirectBranch = 1;
26315let AsmVariantName = "NonParsable";
26316let cofMax1 = 1;
26317let isReturn = 1;
26318let Uses = [P0, R31];
26319let Defs = [PC];
26320let isTaken = Inst{4};
26321let DecoderNamespace = "SUBINSN_L2";
26322}
26323def SL2_jumpr31_tnew : HInst<
26324(outs),
26325(ins),
26326"if (p0.new) jumpr:nt r31",
26327tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26328let Inst{12-0} = 0b1111111000110;
26329let isPredicated = 1;
26330let isTerminator = 1;
26331let isIndirectBranch = 1;
26332let AsmVariantName = "NonParsable";
26333let isPredicatedNew = 1;
26334let cofMax1 = 1;
26335let isReturn = 1;
26336let Uses = [P0, R31];
26337let Defs = [PC];
26338let isTaken = Inst{4};
26339let DecoderNamespace = "SUBINSN_L2";
26340}
26341def SL2_loadrb_io : HInst<
26342(outs GeneralSubRegs:$Rd16),
26343(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
26344"$Rd16 = memb($Rs16+#$Ii)",
26345tc_4222e6bf, TypeSUBINSN>, Enc_2fbf3c {
26346let Inst{12-11} = 0b10;
26347let hasNewValue = 1;
26348let opNewValue = 0;
26349let addrMode = BaseImmOffset;
26350let accessSize = ByteAccess;
26351let AsmVariantName = "NonParsable";
26352let mayLoad = 1;
26353let DecoderNamespace = "SUBINSN_L2";
26354}
26355def SL2_loadrd_sp : HInst<
26356(outs GeneralDoubleLow8Regs:$Rdd8),
26357(ins u5_3Imm:$Ii),
26358"$Rdd8 = memd(r29+#$Ii)",
26359tc_8a6d0d94, TypeSUBINSN>, Enc_86a14b {
26360let Inst{12-8} = 0b11110;
26361let hasNewValue = 1;
26362let opNewValue = 0;
26363let addrMode = BaseImmOffset;
26364let accessSize = DoubleWordAccess;
26365let AsmVariantName = "NonParsable";
26366let mayLoad = 1;
26367let Uses = [R29];
26368let DecoderNamespace = "SUBINSN_L2";
26369}
26370def SL2_loadrh_io : HInst<
26371(outs GeneralSubRegs:$Rd16),
26372(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26373"$Rd16 = memh($Rs16+#$Ii)",
26374tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26375let Inst{12-11} = 0b00;
26376let hasNewValue = 1;
26377let opNewValue = 0;
26378let addrMode = BaseImmOffset;
26379let accessSize = HalfWordAccess;
26380let AsmVariantName = "NonParsable";
26381let mayLoad = 1;
26382let DecoderNamespace = "SUBINSN_L2";
26383}
26384def SL2_loadri_sp : HInst<
26385(outs GeneralSubRegs:$Rd16),
26386(ins u5_2Imm:$Ii),
26387"$Rd16 = memw(r29+#$Ii)",
26388tc_8a6d0d94, TypeSUBINSN>, Enc_51635c {
26389let Inst{12-9} = 0b1110;
26390let hasNewValue = 1;
26391let opNewValue = 0;
26392let addrMode = BaseImmOffset;
26393let accessSize = WordAccess;
26394let AsmVariantName = "NonParsable";
26395let mayLoad = 1;
26396let Uses = [R29];
26397let DecoderNamespace = "SUBINSN_L2";
26398}
26399def SL2_loadruh_io : HInst<
26400(outs GeneralSubRegs:$Rd16),
26401(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26402"$Rd16 = memuh($Rs16+#$Ii)",
26403tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26404let Inst{12-11} = 0b01;
26405let hasNewValue = 1;
26406let opNewValue = 0;
26407let addrMode = BaseImmOffset;
26408let accessSize = HalfWordAccess;
26409let AsmVariantName = "NonParsable";
26410let mayLoad = 1;
26411let DecoderNamespace = "SUBINSN_L2";
26412}
26413def SL2_return : HInst<
26414(outs),
26415(ins),
26416"dealloc_return",
26417tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26418let Inst{12-0} = 0b1111101000000;
26419let isTerminator = 1;
26420let isIndirectBranch = 1;
26421let accessSize = DoubleWordAccess;
26422let AsmVariantName = "NonParsable";
26423let mayLoad = 1;
26424let cofMax1 = 1;
26425let isRestrictNoSlot1Store = 1;
26426let isReturn = 1;
26427let Uses = [FRAMEKEY, R30];
26428let Defs = [PC, R29, R30, R31];
26429let DecoderNamespace = "SUBINSN_L2";
26430}
26431def SL2_return_f : HInst<
26432(outs),
26433(ins),
26434"if (!p0) dealloc_return",
26435tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26436let Inst{12-0} = 0b1111101000101;
26437let isPredicated = 1;
26438let isPredicatedFalse = 1;
26439let isTerminator = 1;
26440let isIndirectBranch = 1;
26441let accessSize = DoubleWordAccess;
26442let AsmVariantName = "NonParsable";
26443let mayLoad = 1;
26444let cofMax1 = 1;
26445let isRestrictNoSlot1Store = 1;
26446let isReturn = 1;
26447let Uses = [FRAMEKEY, P0, R30];
26448let Defs = [PC, R29, R30, R31];
26449let isTaken = Inst{4};
26450let DecoderNamespace = "SUBINSN_L2";
26451}
26452def SL2_return_fnew : HInst<
26453(outs),
26454(ins),
26455"if (!p0.new) dealloc_return:nt",
26456tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26457let Inst{12-0} = 0b1111101000111;
26458let isPredicated = 1;
26459let isPredicatedFalse = 1;
26460let isTerminator = 1;
26461let isIndirectBranch = 1;
26462let accessSize = DoubleWordAccess;
26463let AsmVariantName = "NonParsable";
26464let isPredicatedNew = 1;
26465let mayLoad = 1;
26466let cofMax1 = 1;
26467let isRestrictNoSlot1Store = 1;
26468let isReturn = 1;
26469let Uses = [FRAMEKEY, P0, R30];
26470let Defs = [PC, R29, R30, R31];
26471let isTaken = Inst{4};
26472let DecoderNamespace = "SUBINSN_L2";
26473}
26474def SL2_return_t : HInst<
26475(outs),
26476(ins),
26477"if (p0) dealloc_return",
26478tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26479let Inst{12-0} = 0b1111101000100;
26480let isPredicated = 1;
26481let isTerminator = 1;
26482let isIndirectBranch = 1;
26483let accessSize = DoubleWordAccess;
26484let AsmVariantName = "NonParsable";
26485let mayLoad = 1;
26486let cofMax1 = 1;
26487let isRestrictNoSlot1Store = 1;
26488let isReturn = 1;
26489let Uses = [FRAMEKEY, P0, R30];
26490let Defs = [PC, R29, R30, R31];
26491let isTaken = Inst{4};
26492let DecoderNamespace = "SUBINSN_L2";
26493}
26494def SL2_return_tnew : HInst<
26495(outs),
26496(ins),
26497"if (p0.new) dealloc_return:nt",
26498tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26499let Inst{12-0} = 0b1111101000110;
26500let isPredicated = 1;
26501let isTerminator = 1;
26502let isIndirectBranch = 1;
26503let accessSize = DoubleWordAccess;
26504let AsmVariantName = "NonParsable";
26505let isPredicatedNew = 1;
26506let mayLoad = 1;
26507let cofMax1 = 1;
26508let isRestrictNoSlot1Store = 1;
26509let isReturn = 1;
26510let Uses = [FRAMEKEY, P0, R30];
26511let Defs = [PC, R29, R30, R31];
26512let isTaken = Inst{4};
26513let DecoderNamespace = "SUBINSN_L2";
26514}
26515def SS1_storeb_io : HInst<
26516(outs),
26517(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
26518"memb($Rs16+#$Ii) = $Rt16",
26519tc_ae5babd7, TypeSUBINSN>, Enc_b38ffc {
26520let Inst{12-12} = 0b1;
26521let addrMode = BaseImmOffset;
26522let accessSize = ByteAccess;
26523let AsmVariantName = "NonParsable";
26524let mayStore = 1;
26525let DecoderNamespace = "SUBINSN_S1";
26526}
26527def SS1_storew_io : HInst<
26528(outs),
26529(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
26530"memw($Rs16+#$Ii) = $Rt16",
26531tc_ae5babd7, TypeSUBINSN>, Enc_f55a0c {
26532let Inst{12-12} = 0b0;
26533let addrMode = BaseImmOffset;
26534let accessSize = WordAccess;
26535let AsmVariantName = "NonParsable";
26536let mayStore = 1;
26537let DecoderNamespace = "SUBINSN_S1";
26538}
26539def SS2_allocframe : HInst<
26540(outs),
26541(ins u5_3Imm:$Ii),
26542"allocframe(#$Ii)",
26543tc_1242dc2a, TypeSUBINSN>, Enc_6f70ca {
26544let Inst{3-0} = 0b0000;
26545let Inst{12-9} = 0b1110;
26546let addrMode = BaseImmOffset;
26547let accessSize = DoubleWordAccess;
26548let AsmVariantName = "NonParsable";
26549let mayStore = 1;
26550let Uses = [FRAMEKEY, FRAMELIMIT, R29, R30, R31];
26551let Defs = [R29, R30];
26552let DecoderNamespace = "SUBINSN_S2";
26553}
26554def SS2_storebi0 : HInst<
26555(outs),
26556(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26557"memb($Rs16+#$Ii) = #0",
26558tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26559let Inst{12-8} = 0b10010;
26560let addrMode = BaseImmOffset;
26561let accessSize = ByteAccess;
26562let AsmVariantName = "NonParsable";
26563let mayStore = 1;
26564let DecoderNamespace = "SUBINSN_S2";
26565}
26566def SS2_storebi1 : HInst<
26567(outs),
26568(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26569"memb($Rs16+#$Ii) = #1",
26570tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26571let Inst{12-8} = 0b10011;
26572let addrMode = BaseImmOffset;
26573let accessSize = ByteAccess;
26574let AsmVariantName = "NonParsable";
26575let mayStore = 1;
26576let DecoderNamespace = "SUBINSN_S2";
26577}
26578def SS2_stored_sp : HInst<
26579(outs),
26580(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
26581"memd(r29+#$Ii) = $Rtt8",
26582tc_0655b949, TypeSUBINSN>, Enc_b8309d {
26583let Inst{12-9} = 0b0101;
26584let addrMode = BaseImmOffset;
26585let accessSize = DoubleWordAccess;
26586let AsmVariantName = "NonParsable";
26587let mayStore = 1;
26588let Uses = [R29];
26589let DecoderNamespace = "SUBINSN_S2";
26590}
26591def SS2_storeh_io : HInst<
26592(outs),
26593(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
26594"memh($Rs16+#$Ii) = $Rt16",
26595tc_ae5babd7, TypeSUBINSN>, Enc_625deb {
26596let Inst{12-11} = 0b00;
26597let addrMode = BaseImmOffset;
26598let accessSize = HalfWordAccess;
26599let AsmVariantName = "NonParsable";
26600let mayStore = 1;
26601let DecoderNamespace = "SUBINSN_S2";
26602}
26603def SS2_storew_sp : HInst<
26604(outs),
26605(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
26606"memw(r29+#$Ii) = $Rt16",
26607tc_0655b949, TypeSUBINSN>, Enc_87c142 {
26608let Inst{12-9} = 0b0100;
26609let addrMode = BaseImmOffset;
26610let accessSize = WordAccess;
26611let AsmVariantName = "NonParsable";
26612let mayStore = 1;
26613let Uses = [R29];
26614let DecoderNamespace = "SUBINSN_S2";
26615}
26616def SS2_storewi0 : HInst<
26617(outs),
26618(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26619"memw($Rs16+#$Ii) = #0",
26620tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26621let Inst{12-8} = 0b10000;
26622let addrMode = BaseImmOffset;
26623let accessSize = WordAccess;
26624let AsmVariantName = "NonParsable";
26625let mayStore = 1;
26626let DecoderNamespace = "SUBINSN_S2";
26627}
26628def SS2_storewi1 : HInst<
26629(outs),
26630(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26631"memw($Rs16+#$Ii) = #1",
26632tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26633let Inst{12-8} = 0b10001;
26634let addrMode = BaseImmOffset;
26635let accessSize = WordAccess;
26636let AsmVariantName = "NonParsable";
26637let mayStore = 1;
26638let DecoderNamespace = "SUBINSN_S2";
26639}
26640def V6_MAP_equb : HInst<
26641(outs HvxQR:$Qd4),
26642(ins HvxVR:$Vu32, HvxVR:$Vv32),
26643"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
26644PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26645let hasNewValue = 1;
26646let opNewValue = 0;
26647let isCVI = 1;
26648let isPseudo = 1;
26649let isCodeGenOnly = 1;
26650let DecoderNamespace = "EXT_mmvec";
26651}
26652def V6_MAP_equb_and : HInst<
26653(outs HvxQR:$Qx4),
26654(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26655"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
26656PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26657let isCVI = 1;
26658let isPseudo = 1;
26659let isCodeGenOnly = 1;
26660let DecoderNamespace = "EXT_mmvec";
26661let Constraints = "$Qx4 = $Qx4in";
26662}
26663def V6_MAP_equb_ior : HInst<
26664(outs HvxQR:$Qx4),
26665(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26666"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
26667PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26668let isAccumulator = 1;
26669let isCVI = 1;
26670let isPseudo = 1;
26671let isCodeGenOnly = 1;
26672let DecoderNamespace = "EXT_mmvec";
26673let Constraints = "$Qx4 = $Qx4in";
26674}
26675def V6_MAP_equb_xor : HInst<
26676(outs HvxQR:$Qx4),
26677(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26678"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
26679PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26680let isCVI = 1;
26681let isPseudo = 1;
26682let isCodeGenOnly = 1;
26683let DecoderNamespace = "EXT_mmvec";
26684let Constraints = "$Qx4 = $Qx4in";
26685}
26686def V6_MAP_equh : HInst<
26687(outs HvxQR:$Qd4),
26688(ins HvxVR:$Vu32, HvxVR:$Vv32),
26689"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
26690PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26691let hasNewValue = 1;
26692let opNewValue = 0;
26693let isCVI = 1;
26694let isPseudo = 1;
26695let isCodeGenOnly = 1;
26696let DecoderNamespace = "EXT_mmvec";
26697}
26698def V6_MAP_equh_and : HInst<
26699(outs HvxQR:$Qx4),
26700(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26701"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
26702PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26703let isCVI = 1;
26704let isPseudo = 1;
26705let isCodeGenOnly = 1;
26706let DecoderNamespace = "EXT_mmvec";
26707let Constraints = "$Qx4 = $Qx4in";
26708}
26709def V6_MAP_equh_ior : HInst<
26710(outs HvxQR:$Qx4),
26711(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26712"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
26713PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26714let isAccumulator = 1;
26715let isCVI = 1;
26716let isPseudo = 1;
26717let isCodeGenOnly = 1;
26718let DecoderNamespace = "EXT_mmvec";
26719let Constraints = "$Qx4 = $Qx4in";
26720}
26721def V6_MAP_equh_xor : HInst<
26722(outs HvxQR:$Qx4),
26723(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26724"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
26725PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26726let isCVI = 1;
26727let isPseudo = 1;
26728let isCodeGenOnly = 1;
26729let DecoderNamespace = "EXT_mmvec";
26730let Constraints = "$Qx4 = $Qx4in";
26731}
26732def V6_MAP_equw : HInst<
26733(outs HvxQR:$Qd4),
26734(ins HvxVR:$Vu32, HvxVR:$Vv32),
26735"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
26736PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26737let hasNewValue = 1;
26738let opNewValue = 0;
26739let isCVI = 1;
26740let isPseudo = 1;
26741let isCodeGenOnly = 1;
26742let DecoderNamespace = "EXT_mmvec";
26743}
26744def V6_MAP_equw_and : HInst<
26745(outs HvxQR:$Qx4),
26746(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26747"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
26748PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26749let isCVI = 1;
26750let isPseudo = 1;
26751let isCodeGenOnly = 1;
26752let DecoderNamespace = "EXT_mmvec";
26753let Constraints = "$Qx4 = $Qx4in";
26754}
26755def V6_MAP_equw_ior : HInst<
26756(outs HvxQR:$Qx4),
26757(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26758"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
26759PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26760let isAccumulator = 1;
26761let isCVI = 1;
26762let isPseudo = 1;
26763let isCodeGenOnly = 1;
26764let DecoderNamespace = "EXT_mmvec";
26765let Constraints = "$Qx4 = $Qx4in";
26766}
26767def V6_MAP_equw_xor : HInst<
26768(outs HvxQR:$Qx4),
26769(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26770"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
26771PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26772let isCVI = 1;
26773let isPseudo = 1;
26774let isCodeGenOnly = 1;
26775let DecoderNamespace = "EXT_mmvec";
26776let Constraints = "$Qx4 = $Qx4in";
26777}
26778def V6_dbl_ld0 : HInst<
26779(outs HvxWR:$Vdd32),
26780(ins IntRegs:$Rt32),
26781"$Vdd32 = vmem($Rt32)",
26782PSEUDO, TypeMAPPING>, Requires<[UseHVXV73]> {
26783let hasNewValue = 1;
26784let opNewValue = 0;
26785let isCVLoad = 1;
26786let isCVI = 1;
26787let mayLoad = 1;
26788let isPseudo = 1;
26789let isCodeGenOnly = 1;
26790let DecoderNamespace = "EXT_mmvec";
26791}
26792def V6_dbl_st0 : HInst<
26793(outs),
26794(ins IntRegs:$Rt32, HvxWR:$Vss32),
26795"vmem($Rt32) = $Vss32",
26796PSEUDO, TypeMAPPING>, Requires<[UseHVXV73]> {
26797let isCVI = 1;
26798let mayStore = 1;
26799let isPseudo = 1;
26800let isCodeGenOnly = 1;
26801let DecoderNamespace = "EXT_mmvec";
26802}
26803def V6_extractw : HInst<
26804(outs IntRegs:$Rd32),
26805(ins HvxVR:$Vu32, IntRegs:$Rs32),
26806"$Rd32 = vextract($Vu32,$Rs32)",
26807tc_540c3da3, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
26808let Inst{7-5} = 0b001;
26809let Inst{13-13} = 0b0;
26810let Inst{31-21} = 0b10010010000;
26811let hasNewValue = 1;
26812let opNewValue = 0;
26813let isCVI = 1;
26814let isHVXALU = 1;
26815let isHVXALU2SRC = 1;
26816let isSolo = 1;
26817let mayLoad = 1;
26818let DecoderNamespace = "EXT_mmvec";
26819}
26820def V6_extractw_alt : HInst<
26821(outs IntRegs:$Rd32),
26822(ins HvxVR:$Vu32, IntRegs:$Rs32),
26823"$Rd32.w = vextract($Vu32,$Rs32)",
26824PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26825let hasNewValue = 1;
26826let opNewValue = 0;
26827let isCVI = 1;
26828let isPseudo = 1;
26829let isCodeGenOnly = 1;
26830let DecoderNamespace = "EXT_mmvec";
26831}
26832def V6_hi : HInst<
26833(outs HvxVR:$Vd32),
26834(ins HvxWR:$Vss32),
26835"$Vd32 = hi($Vss32)",
26836CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26837let hasNewValue = 1;
26838let opNewValue = 0;
26839let isCVI = 1;
26840let isPseudo = 1;
26841let DecoderNamespace = "EXT_mmvec";
26842}
26843def V6_ld0 : HInst<
26844(outs HvxVR:$Vd32),
26845(ins IntRegs:$Rt32),
26846"$Vd32 = vmem($Rt32)",
26847PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26848let hasNewValue = 1;
26849let opNewValue = 0;
26850let isCVI = 1;
26851let isPseudo = 1;
26852let isCodeGenOnly = 1;
26853let DecoderNamespace = "EXT_mmvec";
26854}
26855def V6_ldcnp0 : HInst<
26856(outs HvxVR:$Vd32),
26857(ins PredRegs:$Pv4, IntRegs:$Rt32),
26858"if (!$Pv4) $Vd32.cur = vmem($Rt32)",
26859PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26860let hasNewValue = 1;
26861let opNewValue = 0;
26862let isCVI = 1;
26863let isPseudo = 1;
26864let isCodeGenOnly = 1;
26865let DecoderNamespace = "EXT_mmvec";
26866}
26867def V6_ldcnpnt0 : HInst<
26868(outs HvxVR:$Vd32),
26869(ins PredRegs:$Pv4, IntRegs:$Rt32),
26870"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
26871PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26872let hasNewValue = 1;
26873let opNewValue = 0;
26874let isCVI = 1;
26875let isPseudo = 1;
26876let isCodeGenOnly = 1;
26877let DecoderNamespace = "EXT_mmvec";
26878}
26879def V6_ldcp0 : HInst<
26880(outs HvxVR:$Vd32),
26881(ins PredRegs:$Pv4, IntRegs:$Rt32),
26882"if ($Pv4) $Vd32.cur = vmem($Rt32)",
26883PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26884let hasNewValue = 1;
26885let opNewValue = 0;
26886let isCVI = 1;
26887let isPseudo = 1;
26888let isCodeGenOnly = 1;
26889let DecoderNamespace = "EXT_mmvec";
26890}
26891def V6_ldcpnt0 : HInst<
26892(outs HvxVR:$Vd32),
26893(ins PredRegs:$Pv4, IntRegs:$Rt32),
26894"if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
26895PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26896let hasNewValue = 1;
26897let opNewValue = 0;
26898let isCVI = 1;
26899let isPseudo = 1;
26900let isCodeGenOnly = 1;
26901let DecoderNamespace = "EXT_mmvec";
26902}
26903def V6_ldnp0 : HInst<
26904(outs HvxVR:$Vd32),
26905(ins PredRegs:$Pv4, IntRegs:$Rt32),
26906"if (!$Pv4) $Vd32 = vmem($Rt32)",
26907PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26908let hasNewValue = 1;
26909let opNewValue = 0;
26910let isCVI = 1;
26911let isPseudo = 1;
26912let isCodeGenOnly = 1;
26913let DecoderNamespace = "EXT_mmvec";
26914}
26915def V6_ldnpnt0 : HInst<
26916(outs HvxVR:$Vd32),
26917(ins PredRegs:$Pv4, IntRegs:$Rt32),
26918"if (!$Pv4) $Vd32 = vmem($Rt32):nt",
26919PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26920let hasNewValue = 1;
26921let opNewValue = 0;
26922let isCVI = 1;
26923let isPseudo = 1;
26924let isCodeGenOnly = 1;
26925let DecoderNamespace = "EXT_mmvec";
26926}
26927def V6_ldnt0 : HInst<
26928(outs HvxVR:$Vd32),
26929(ins IntRegs:$Rt32),
26930"$Vd32 = vmem($Rt32):nt",
26931PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26932let hasNewValue = 1;
26933let opNewValue = 0;
26934let isCVI = 1;
26935let isPseudo = 1;
26936let isCodeGenOnly = 1;
26937let DecoderNamespace = "EXT_mmvec";
26938}
26939def V6_ldp0 : HInst<
26940(outs HvxVR:$Vd32),
26941(ins PredRegs:$Pv4, IntRegs:$Rt32),
26942"if ($Pv4) $Vd32 = vmem($Rt32)",
26943PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26944let hasNewValue = 1;
26945let opNewValue = 0;
26946let isCVI = 1;
26947let isPseudo = 1;
26948let isCodeGenOnly = 1;
26949let DecoderNamespace = "EXT_mmvec";
26950}
26951def V6_ldpnt0 : HInst<
26952(outs HvxVR:$Vd32),
26953(ins PredRegs:$Pv4, IntRegs:$Rt32),
26954"if ($Pv4) $Vd32 = vmem($Rt32):nt",
26955PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26956let hasNewValue = 1;
26957let opNewValue = 0;
26958let isCVI = 1;
26959let isPseudo = 1;
26960let isCodeGenOnly = 1;
26961let DecoderNamespace = "EXT_mmvec";
26962}
26963def V6_ldtnp0 : HInst<
26964(outs HvxVR:$Vd32),
26965(ins PredRegs:$Pv4, IntRegs:$Rt32),
26966"if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
26967PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26968let hasNewValue = 1;
26969let opNewValue = 0;
26970let isCVI = 1;
26971let isPseudo = 1;
26972let isCodeGenOnly = 1;
26973let DecoderNamespace = "EXT_mmvec";
26974}
26975def V6_ldtnpnt0 : HInst<
26976(outs HvxVR:$Vd32),
26977(ins PredRegs:$Pv4, IntRegs:$Rt32),
26978"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
26979PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26980let hasNewValue = 1;
26981let opNewValue = 0;
26982let isCVI = 1;
26983let isPseudo = 1;
26984let isCodeGenOnly = 1;
26985let DecoderNamespace = "EXT_mmvec";
26986}
26987def V6_ldtp0 : HInst<
26988(outs HvxVR:$Vd32),
26989(ins PredRegs:$Pv4, IntRegs:$Rt32),
26990"if ($Pv4) $Vd32.tmp = vmem($Rt32)",
26991PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26992let hasNewValue = 1;
26993let opNewValue = 0;
26994let isCVI = 1;
26995let isPseudo = 1;
26996let isCodeGenOnly = 1;
26997let DecoderNamespace = "EXT_mmvec";
26998}
26999def V6_ldtpnt0 : HInst<
27000(outs HvxVR:$Vd32),
27001(ins PredRegs:$Pv4, IntRegs:$Rt32),
27002"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
27003PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
27004let hasNewValue = 1;
27005let opNewValue = 0;
27006let isCVI = 1;
27007let isPseudo = 1;
27008let isCodeGenOnly = 1;
27009let DecoderNamespace = "EXT_mmvec";
27010}
27011def V6_ldu0 : HInst<
27012(outs HvxVR:$Vd32),
27013(ins IntRegs:$Rt32),
27014"$Vd32 = vmemu($Rt32)",
27015PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
27016let hasNewValue = 1;
27017let opNewValue = 0;
27018let isCVI = 1;
27019let isPseudo = 1;
27020let isCodeGenOnly = 1;
27021let DecoderNamespace = "EXT_mmvec";
27022}
27023def V6_lo : HInst<
27024(outs HvxVR:$Vd32),
27025(ins HvxWR:$Vss32),
27026"$Vd32 = lo($Vss32)",
27027CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
27028let hasNewValue = 1;
27029let opNewValue = 0;
27030let isCVI = 1;
27031let isPseudo = 1;
27032let DecoderNamespace = "EXT_mmvec";
27033}
27034def V6_lvsplatb : HInst<
27035(outs HvxVR:$Vd32),
27036(ins IntRegs:$Rt32),
27037"$Vd32.b = vsplat($Rt32)",
27038tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
27039let Inst{13-5} = 0b000000010;
27040let Inst{31-21} = 0b00011001110;
27041let hasNewValue = 1;
27042let opNewValue = 0;
27043let isCVI = 1;
27044let DecoderNamespace = "EXT_mmvec";
27045}
27046def V6_lvsplath : HInst<
27047(outs HvxVR:$Vd32),
27048(ins IntRegs:$Rt32),
27049"$Vd32.h = vsplat($Rt32)",
27050tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
27051let Inst{13-5} = 0b000000001;
27052let Inst{31-21} = 0b00011001110;
27053let hasNewValue = 1;
27054let opNewValue = 0;
27055let isCVI = 1;
27056let DecoderNamespace = "EXT_mmvec";
27057}
27058def V6_lvsplatw : HInst<
27059(outs HvxVR:$Vd32),
27060(ins IntRegs:$Rt32),
27061"$Vd32 = vsplat($Rt32)",
27062tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
27063let Inst{13-5} = 0b000000001;
27064let Inst{31-21} = 0b00011001101;
27065let hasNewValue = 1;
27066let opNewValue = 0;
27067let isCVI = 1;
27068let DecoderNamespace = "EXT_mmvec";
27069}
27070def V6_pred_and : HInst<
27071(outs HvxQR:$Qd4),
27072(ins HvxQR:$Qs4, HvxQR:$Qt4),
27073"$Qd4 = and($Qs4,$Qt4)",
27074tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27075let Inst{7-2} = 0b000000;
27076let Inst{13-10} = 0b0000;
27077let Inst{21-16} = 0b000011;
27078let Inst{31-24} = 0b00011110;
27079let hasNewValue = 1;
27080let opNewValue = 0;
27081let isCVI = 1;
27082let DecoderNamespace = "EXT_mmvec";
27083}
27084def V6_pred_and_n : HInst<
27085(outs HvxQR:$Qd4),
27086(ins HvxQR:$Qs4, HvxQR:$Qt4),
27087"$Qd4 = and($Qs4,!$Qt4)",
27088tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27089let Inst{7-2} = 0b000101;
27090let Inst{13-10} = 0b0000;
27091let Inst{21-16} = 0b000011;
27092let Inst{31-24} = 0b00011110;
27093let hasNewValue = 1;
27094let opNewValue = 0;
27095let isCVI = 1;
27096let DecoderNamespace = "EXT_mmvec";
27097}
27098def V6_pred_not : HInst<
27099(outs HvxQR:$Qd4),
27100(ins HvxQR:$Qs4),
27101"$Qd4 = not($Qs4)",
27102tc_0ec46cf9, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
27103let Inst{7-2} = 0b000010;
27104let Inst{13-10} = 0b0000;
27105let Inst{31-16} = 0b0001111000000011;
27106let hasNewValue = 1;
27107let opNewValue = 0;
27108let isCVI = 1;
27109let isHVXALU = 1;
27110let isHVXALU2SRC = 1;
27111let DecoderNamespace = "EXT_mmvec";
27112}
27113def V6_pred_or : HInst<
27114(outs HvxQR:$Qd4),
27115(ins HvxQR:$Qs4, HvxQR:$Qt4),
27116"$Qd4 = or($Qs4,$Qt4)",
27117tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27118let Inst{7-2} = 0b000001;
27119let Inst{13-10} = 0b0000;
27120let Inst{21-16} = 0b000011;
27121let Inst{31-24} = 0b00011110;
27122let hasNewValue = 1;
27123let opNewValue = 0;
27124let isCVI = 1;
27125let DecoderNamespace = "EXT_mmvec";
27126}
27127def V6_pred_or_n : HInst<
27128(outs HvxQR:$Qd4),
27129(ins HvxQR:$Qs4, HvxQR:$Qt4),
27130"$Qd4 = or($Qs4,!$Qt4)",
27131tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27132let Inst{7-2} = 0b000100;
27133let Inst{13-10} = 0b0000;
27134let Inst{21-16} = 0b000011;
27135let Inst{31-24} = 0b00011110;
27136let hasNewValue = 1;
27137let opNewValue = 0;
27138let isCVI = 1;
27139let DecoderNamespace = "EXT_mmvec";
27140}
27141def V6_pred_scalar2 : HInst<
27142(outs HvxQR:$Qd4),
27143(ins IntRegs:$Rt32),
27144"$Qd4 = vsetq($Rt32)",
27145tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
27146let Inst{13-2} = 0b000000010001;
27147let Inst{31-21} = 0b00011001101;
27148let hasNewValue = 1;
27149let opNewValue = 0;
27150let isCVI = 1;
27151let DecoderNamespace = "EXT_mmvec";
27152}
27153def V6_pred_scalar2v2 : HInst<
27154(outs HvxQR:$Qd4),
27155(ins IntRegs:$Rt32),
27156"$Qd4 = vsetq2($Rt32)",
27157tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
27158let Inst{13-2} = 0b000000010011;
27159let Inst{31-21} = 0b00011001101;
27160let hasNewValue = 1;
27161let opNewValue = 0;
27162let isCVI = 1;
27163let DecoderNamespace = "EXT_mmvec";
27164}
27165def V6_pred_xor : HInst<
27166(outs HvxQR:$Qd4),
27167(ins HvxQR:$Qs4, HvxQR:$Qt4),
27168"$Qd4 = xor($Qs4,$Qt4)",
27169tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27170let Inst{7-2} = 0b000011;
27171let Inst{13-10} = 0b0000;
27172let Inst{21-16} = 0b000011;
27173let Inst{31-24} = 0b00011110;
27174let hasNewValue = 1;
27175let opNewValue = 0;
27176let isCVI = 1;
27177let DecoderNamespace = "EXT_mmvec";
27178}
27179def V6_shuffeqh : HInst<
27180(outs HvxQR:$Qd4),
27181(ins HvxQR:$Qs4, HvxQR:$Qt4),
27182"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
27183tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27184let Inst{7-2} = 0b000110;
27185let Inst{13-10} = 0b0000;
27186let Inst{21-16} = 0b000011;
27187let Inst{31-24} = 0b00011110;
27188let hasNewValue = 1;
27189let opNewValue = 0;
27190let isCVI = 1;
27191let DecoderNamespace = "EXT_mmvec";
27192}
27193def V6_shuffeqw : HInst<
27194(outs HvxQR:$Qd4),
27195(ins HvxQR:$Qs4, HvxQR:$Qt4),
27196"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
27197tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27198let Inst{7-2} = 0b000111;
27199let Inst{13-10} = 0b0000;
27200let Inst{21-16} = 0b000011;
27201let Inst{31-24} = 0b00011110;
27202let hasNewValue = 1;
27203let opNewValue = 0;
27204let isCVI = 1;
27205let DecoderNamespace = "EXT_mmvec";
27206}
27207def V6_st0 : HInst<
27208(outs),
27209(ins IntRegs:$Rt32, HvxVR:$Vs32),
27210"vmem($Rt32) = $Vs32",
27211PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27212let isCVI = 1;
27213let isPseudo = 1;
27214let isCodeGenOnly = 1;
27215let DecoderNamespace = "EXT_mmvec";
27216}
27217def V6_stn0 : HInst<
27218(outs),
27219(ins IntRegs:$Rt32, HvxVR:$Os8),
27220"vmem($Rt32) = $Os8.new",
27221PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27222let isCVI = 1;
27223let isPseudo = 1;
27224let isCodeGenOnly = 1;
27225let DecoderNamespace = "EXT_mmvec";
27226let opNewValue = 1;
27227}
27228def V6_stnnt0 : HInst<
27229(outs),
27230(ins IntRegs:$Rt32, HvxVR:$Os8),
27231"vmem($Rt32):nt = $Os8.new",
27232PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27233let isCVI = 1;
27234let isPseudo = 1;
27235let isCodeGenOnly = 1;
27236let DecoderNamespace = "EXT_mmvec";
27237let opNewValue = 1;
27238}
27239def V6_stnp0 : HInst<
27240(outs),
27241(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27242"if (!$Pv4) vmem($Rt32) = $Vs32",
27243PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27244let isCVI = 1;
27245let isPseudo = 1;
27246let isCodeGenOnly = 1;
27247let DecoderNamespace = "EXT_mmvec";
27248}
27249def V6_stnpnt0 : HInst<
27250(outs),
27251(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27252"if (!$Pv4) vmem($Rt32):nt = $Vs32",
27253PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27254let isCVI = 1;
27255let isPseudo = 1;
27256let isCodeGenOnly = 1;
27257let DecoderNamespace = "EXT_mmvec";
27258}
27259def V6_stnq0 : HInst<
27260(outs),
27261(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27262"if (!$Qv4) vmem($Rt32) = $Vs32",
27263PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27264let isCVI = 1;
27265let isPseudo = 1;
27266let isCodeGenOnly = 1;
27267let DecoderNamespace = "EXT_mmvec";
27268}
27269def V6_stnqnt0 : HInst<
27270(outs),
27271(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27272"if (!$Qv4) vmem($Rt32):nt = $Vs32",
27273PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27274let isCVI = 1;
27275let isPseudo = 1;
27276let isCodeGenOnly = 1;
27277let DecoderNamespace = "EXT_mmvec";
27278}
27279def V6_stnt0 : HInst<
27280(outs),
27281(ins IntRegs:$Rt32, HvxVR:$Vs32),
27282"vmem($Rt32):nt = $Vs32",
27283PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27284let isCVI = 1;
27285let isPseudo = 1;
27286let isCodeGenOnly = 1;
27287let DecoderNamespace = "EXT_mmvec";
27288}
27289def V6_stp0 : HInst<
27290(outs),
27291(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27292"if ($Pv4) vmem($Rt32) = $Vs32",
27293PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27294let isCVI = 1;
27295let isPseudo = 1;
27296let isCodeGenOnly = 1;
27297let DecoderNamespace = "EXT_mmvec";
27298}
27299def V6_stpnt0 : HInst<
27300(outs),
27301(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27302"if ($Pv4) vmem($Rt32):nt = $Vs32",
27303PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27304let isCVI = 1;
27305let isPseudo = 1;
27306let isCodeGenOnly = 1;
27307let DecoderNamespace = "EXT_mmvec";
27308}
27309def V6_stq0 : HInst<
27310(outs),
27311(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27312"if ($Qv4) vmem($Rt32) = $Vs32",
27313PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27314let isCVI = 1;
27315let isPseudo = 1;
27316let isCodeGenOnly = 1;
27317let DecoderNamespace = "EXT_mmvec";
27318}
27319def V6_stqnt0 : HInst<
27320(outs),
27321(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27322"if ($Qv4) vmem($Rt32):nt = $Vs32",
27323PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27324let isCVI = 1;
27325let isPseudo = 1;
27326let isCodeGenOnly = 1;
27327let DecoderNamespace = "EXT_mmvec";
27328}
27329def V6_stu0 : HInst<
27330(outs),
27331(ins IntRegs:$Rt32, HvxVR:$Vs32),
27332"vmemu($Rt32) = $Vs32",
27333PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27334let isCVI = 1;
27335let isPseudo = 1;
27336let isCodeGenOnly = 1;
27337let DecoderNamespace = "EXT_mmvec";
27338}
27339def V6_stunp0 : HInst<
27340(outs),
27341(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27342"if (!$Pv4) vmemu($Rt32) = $Vs32",
27343PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27344let isCVI = 1;
27345let isPseudo = 1;
27346let isCodeGenOnly = 1;
27347let DecoderNamespace = "EXT_mmvec";
27348}
27349def V6_stup0 : HInst<
27350(outs),
27351(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27352"if ($Pv4) vmemu($Rt32) = $Vs32",
27353PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27354let isCVI = 1;
27355let isPseudo = 1;
27356let isCodeGenOnly = 1;
27357let DecoderNamespace = "EXT_mmvec";
27358}
27359def V6_v10mpyubs10 : HInst<
27360(outs HvxWR:$Vdd32),
27361(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u1_0Imm:$Ii),
27362"$Vdd32.w = v10mpy($Vuu32.ub,$Vvv32.b,#$Ii)",
27363tc_f175e046, TypeCVI_VX>, Requires<[UseHVXV69]> {
27364let hasNewValue = 1;
27365let opNewValue = 0;
27366let isCVI = 1;
27367let isPseudo = 1;
27368let DecoderNamespace = "EXT_mmvec";
27369}
27370def V6_v10mpyubs10_vxx : HInst<
27371(outs HvxWR:$Vxx32),
27372(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u1_0Imm:$Ii),
27373"$Vxx32.w += v10mpy($Vuu32.ub,$Vvv32.b,#$Ii)",
27374tc_4942646a, TypeCVI_VX>, Requires<[UseHVXV69]> {
27375let hasNewValue = 1;
27376let opNewValue = 0;
27377let isAccumulator = 1;
27378let isCVI = 1;
27379let isPseudo = 1;
27380let DecoderNamespace = "EXT_mmvec";
27381let Constraints = "$Vxx32 = $Vxx32in";
27382}
27383def V6_v6mpyhubs10 : HInst<
27384(outs HvxWR:$Vdd32),
27385(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27386"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27387tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27388let Inst{7-7} = 0b1;
27389let Inst{13-13} = 0b1;
27390let Inst{31-21} = 0b00011111010;
27391let hasNewValue = 1;
27392let opNewValue = 0;
27393let isCVI = 1;
27394let DecoderNamespace = "EXT_mmvec";
27395}
27396def V6_v6mpyhubs10_alt : HInst<
27397(outs HvxWR:$Vdd32),
27398(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27399"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):h",
27400PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27401let hasNewValue = 1;
27402let opNewValue = 0;
27403let isCVI = 1;
27404let isPseudo = 1;
27405let isCodeGenOnly = 1;
27406let DecoderNamespace = "EXT_mmvec";
27407}
27408def V6_v6mpyhubs10_vxx : HInst<
27409(outs HvxWR:$Vxx32),
27410(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27411"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27412tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27413let Inst{7-7} = 0b1;
27414let Inst{13-13} = 0b1;
27415let Inst{31-21} = 0b00011111001;
27416let hasNewValue = 1;
27417let opNewValue = 0;
27418let isAccumulator = 1;
27419let isCVI = 1;
27420let DecoderNamespace = "EXT_mmvec";
27421let Constraints = "$Vxx32 = $Vxx32in";
27422}
27423def V6_v6mpyvubs10 : HInst<
27424(outs HvxWR:$Vdd32),
27425(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27426"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27427tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27428let Inst{7-7} = 0b0;
27429let Inst{13-13} = 0b1;
27430let Inst{31-21} = 0b00011111010;
27431let hasNewValue = 1;
27432let opNewValue = 0;
27433let isCVI = 1;
27434let DecoderNamespace = "EXT_mmvec";
27435}
27436def V6_v6mpyvubs10_alt : HInst<
27437(outs HvxWR:$Vdd32),
27438(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27439"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):v",
27440PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27441let hasNewValue = 1;
27442let opNewValue = 0;
27443let isCVI = 1;
27444let isPseudo = 1;
27445let isCodeGenOnly = 1;
27446let DecoderNamespace = "EXT_mmvec";
27447}
27448def V6_v6mpyvubs10_vxx : HInst<
27449(outs HvxWR:$Vxx32),
27450(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27451"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27452tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27453let Inst{7-7} = 0b0;
27454let Inst{13-13} = 0b1;
27455let Inst{31-21} = 0b00011111001;
27456let hasNewValue = 1;
27457let opNewValue = 0;
27458let isAccumulator = 1;
27459let isCVI = 1;
27460let DecoderNamespace = "EXT_mmvec";
27461let Constraints = "$Vxx32 = $Vxx32in";
27462}
27463def V6_vL32Ub_ai : HInst<
27464(outs HvxVR:$Vd32),
27465(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27466"$Vd32 = vmemu($Rt32+#$Ii)",
27467tc_a7e6707d, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]>, PostInc_BaseImm {
27468let Inst{7-5} = 0b111;
27469let Inst{12-11} = 0b00;
27470let Inst{31-21} = 0b00101000000;
27471let hasNewValue = 1;
27472let opNewValue = 0;
27473let addrMode = BaseImmOffset;
27474let accessSize = HVXVectorAccess;
27475let isCVLoad = 1;
27476let isCVI = 1;
27477let mayLoad = 1;
27478let isRestrictNoSlot1Store = 1;
27479let BaseOpcode = "V6_vL32Ub_ai";
27480let CextOpcode = "V6_vL32Ub";
27481let DecoderNamespace = "EXT_mmvec";
27482}
27483def V6_vL32Ub_pi : HInst<
27484(outs HvxVR:$Vd32, IntRegs:$Rx32),
27485(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27486"$Vd32 = vmemu($Rx32++#$Ii)",
27487tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]>, PostInc_BaseImm {
27488let Inst{7-5} = 0b111;
27489let Inst{13-11} = 0b000;
27490let Inst{31-21} = 0b00101001000;
27491let hasNewValue = 1;
27492let opNewValue = 0;
27493let addrMode = PostInc;
27494let accessSize = HVXVectorAccess;
27495let isCVLoad = 1;
27496let isCVI = 1;
27497let mayLoad = 1;
27498let isRestrictNoSlot1Store = 1;
27499let BaseOpcode = "V6_vL32b_pi";
27500let CextOpcode = "V6_vL32Ub";
27501let DecoderNamespace = "EXT_mmvec";
27502let Constraints = "$Rx32 = $Rx32in";
27503}
27504def V6_vL32Ub_ppu : HInst<
27505(outs HvxVR:$Vd32, IntRegs:$Rx32),
27506(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27507"$Vd32 = vmemu($Rx32++$Mu2)",
27508tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
27509let Inst{12-5} = 0b00000111;
27510let Inst{31-21} = 0b00101011000;
27511let hasNewValue = 1;
27512let opNewValue = 0;
27513let addrMode = PostInc;
27514let accessSize = HVXVectorAccess;
27515let isCVLoad = 1;
27516let isCVI = 1;
27517let mayLoad = 1;
27518let isRestrictNoSlot1Store = 1;
27519let DecoderNamespace = "EXT_mmvec";
27520let Constraints = "$Rx32 = $Rx32in";
27521}
27522def V6_vL32b_ai : HInst<
27523(outs HvxVR:$Vd32),
27524(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27525"$Vd32 = vmem($Rt32+#$Ii)",
27526tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27527let Inst{7-5} = 0b000;
27528let Inst{12-11} = 0b00;
27529let Inst{31-21} = 0b00101000000;
27530let hasNewValue = 1;
27531let opNewValue = 0;
27532let addrMode = BaseImmOffset;
27533let accessSize = HVXVectorAccess;
27534let isCVLoad = 1;
27535let isCVI = 1;
27536let isHVXALU = 1;
27537let mayLoad = 1;
27538let isRestrictNoSlot1Store = 1;
27539let BaseOpcode = "V6_vL32b_ai";
27540let CextOpcode = "V6_vL32b";
27541let isCVLoadable = 1;
27542let isPredicable = 1;
27543let DecoderNamespace = "EXT_mmvec";
27544}
27545def V6_vL32b_cur_ai : HInst<
27546(outs HvxVR:$Vd32),
27547(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27548"$Vd32.cur = vmem($Rt32+#$Ii)",
27549tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27550let Inst{7-5} = 0b001;
27551let Inst{12-11} = 0b00;
27552let Inst{31-21} = 0b00101000000;
27553let hasNewValue = 1;
27554let opNewValue = 0;
27555let addrMode = BaseImmOffset;
27556let accessSize = HVXVectorAccess;
27557let isCVLoad = 1;
27558let isCVI = 1;
27559let CVINew = 1;
27560let isHVXALU = 1;
27561let mayLoad = 1;
27562let isRestrictNoSlot1Store = 1;
27563let BaseOpcode = "V6_vL32b_cur_ai";
27564let CextOpcode = "V6_vL32b_cur";
27565let isPredicable = 1;
27566let DecoderNamespace = "EXT_mmvec";
27567}
27568def V6_vL32b_cur_npred_ai : HInst<
27569(outs HvxVR:$Vd32),
27570(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27571"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27572tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27573let Inst{7-5} = 0b101;
27574let Inst{31-21} = 0b00101000100;
27575let isPredicated = 1;
27576let isPredicatedFalse = 1;
27577let hasNewValue = 1;
27578let opNewValue = 0;
27579let addrMode = BaseImmOffset;
27580let accessSize = HVXVectorAccess;
27581let isCVLoad = 1;
27582let isCVI = 1;
27583let CVINew = 1;
27584let isHVXALU = 1;
27585let mayLoad = 1;
27586let isRestrictNoSlot1Store = 1;
27587let BaseOpcode = "V6_vL32b_cur_ai";
27588let DecoderNamespace = "EXT_mmvec";
27589}
27590def V6_vL32b_cur_npred_pi : HInst<
27591(outs HvxVR:$Vd32, IntRegs:$Rx32),
27592(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27593"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27594tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27595let Inst{7-5} = 0b101;
27596let Inst{13-13} = 0b0;
27597let Inst{31-21} = 0b00101001100;
27598let isPredicated = 1;
27599let isPredicatedFalse = 1;
27600let hasNewValue = 1;
27601let opNewValue = 0;
27602let addrMode = PostInc;
27603let accessSize = HVXVectorAccess;
27604let isCVLoad = 1;
27605let isCVI = 1;
27606let CVINew = 1;
27607let isHVXALU = 1;
27608let mayLoad = 1;
27609let isRestrictNoSlot1Store = 1;
27610let BaseOpcode = "V6_vL32b_cur_pi";
27611let DecoderNamespace = "EXT_mmvec";
27612let Constraints = "$Rx32 = $Rx32in";
27613}
27614def V6_vL32b_cur_npred_ppu : HInst<
27615(outs HvxVR:$Vd32, IntRegs:$Rx32),
27616(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27617"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27618tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27619let Inst{10-5} = 0b000101;
27620let Inst{31-21} = 0b00101011100;
27621let isPredicated = 1;
27622let isPredicatedFalse = 1;
27623let hasNewValue = 1;
27624let opNewValue = 0;
27625let addrMode = PostInc;
27626let accessSize = HVXVectorAccess;
27627let isCVLoad = 1;
27628let isCVI = 1;
27629let CVINew = 1;
27630let isHVXALU = 1;
27631let mayLoad = 1;
27632let isRestrictNoSlot1Store = 1;
27633let BaseOpcode = "V6_vL32b_cur_ppu";
27634let DecoderNamespace = "EXT_mmvec";
27635let Constraints = "$Rx32 = $Rx32in";
27636}
27637def V6_vL32b_cur_pi : HInst<
27638(outs HvxVR:$Vd32, IntRegs:$Rx32),
27639(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27640"$Vd32.cur = vmem($Rx32++#$Ii)",
27641tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27642let Inst{7-5} = 0b001;
27643let Inst{13-11} = 0b000;
27644let Inst{31-21} = 0b00101001000;
27645let hasNewValue = 1;
27646let opNewValue = 0;
27647let addrMode = PostInc;
27648let accessSize = HVXVectorAccess;
27649let isCVLoad = 1;
27650let isCVI = 1;
27651let CVINew = 1;
27652let isHVXALU = 1;
27653let mayLoad = 1;
27654let isRestrictNoSlot1Store = 1;
27655let BaseOpcode = "V6_vL32b_cur_pi";
27656let CextOpcode = "V6_vL32b_cur";
27657let isPredicable = 1;
27658let DecoderNamespace = "EXT_mmvec";
27659let Constraints = "$Rx32 = $Rx32in";
27660}
27661def V6_vL32b_cur_ppu : HInst<
27662(outs HvxVR:$Vd32, IntRegs:$Rx32),
27663(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27664"$Vd32.cur = vmem($Rx32++$Mu2)",
27665tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27666let Inst{12-5} = 0b00000001;
27667let Inst{31-21} = 0b00101011000;
27668let hasNewValue = 1;
27669let opNewValue = 0;
27670let addrMode = PostInc;
27671let accessSize = HVXVectorAccess;
27672let isCVLoad = 1;
27673let isCVI = 1;
27674let CVINew = 1;
27675let isHVXALU = 1;
27676let mayLoad = 1;
27677let isRestrictNoSlot1Store = 1;
27678let BaseOpcode = "V6_vL32b_cur_ppu";
27679let isPredicable = 1;
27680let DecoderNamespace = "EXT_mmvec";
27681let Constraints = "$Rx32 = $Rx32in";
27682}
27683def V6_vL32b_cur_pred_ai : HInst<
27684(outs HvxVR:$Vd32),
27685(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27686"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27687tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27688let Inst{7-5} = 0b100;
27689let Inst{31-21} = 0b00101000100;
27690let isPredicated = 1;
27691let hasNewValue = 1;
27692let opNewValue = 0;
27693let addrMode = BaseImmOffset;
27694let accessSize = HVXVectorAccess;
27695let isCVLoad = 1;
27696let isCVI = 1;
27697let CVINew = 1;
27698let isHVXALU = 1;
27699let mayLoad = 1;
27700let isRestrictNoSlot1Store = 1;
27701let BaseOpcode = "V6_vL32b_cur_ai";
27702let DecoderNamespace = "EXT_mmvec";
27703}
27704def V6_vL32b_cur_pred_pi : HInst<
27705(outs HvxVR:$Vd32, IntRegs:$Rx32),
27706(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27707"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27708tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27709let Inst{7-5} = 0b100;
27710let Inst{13-13} = 0b0;
27711let Inst{31-21} = 0b00101001100;
27712let isPredicated = 1;
27713let hasNewValue = 1;
27714let opNewValue = 0;
27715let addrMode = PostInc;
27716let accessSize = HVXVectorAccess;
27717let isCVLoad = 1;
27718let isCVI = 1;
27719let CVINew = 1;
27720let isHVXALU = 1;
27721let mayLoad = 1;
27722let isRestrictNoSlot1Store = 1;
27723let BaseOpcode = "V6_vL32b_cur_pi";
27724let DecoderNamespace = "EXT_mmvec";
27725let Constraints = "$Rx32 = $Rx32in";
27726}
27727def V6_vL32b_cur_pred_ppu : HInst<
27728(outs HvxVR:$Vd32, IntRegs:$Rx32),
27729(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27730"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27731tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27732let Inst{10-5} = 0b000100;
27733let Inst{31-21} = 0b00101011100;
27734let isPredicated = 1;
27735let hasNewValue = 1;
27736let opNewValue = 0;
27737let addrMode = PostInc;
27738let accessSize = HVXVectorAccess;
27739let isCVLoad = 1;
27740let isCVI = 1;
27741let CVINew = 1;
27742let isHVXALU = 1;
27743let mayLoad = 1;
27744let isRestrictNoSlot1Store = 1;
27745let BaseOpcode = "V6_vL32b_cur_ppu";
27746let DecoderNamespace = "EXT_mmvec";
27747let Constraints = "$Rx32 = $Rx32in";
27748}
27749def V6_vL32b_npred_ai : HInst<
27750(outs HvxVR:$Vd32),
27751(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27752"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27753tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27754let Inst{7-5} = 0b011;
27755let Inst{31-21} = 0b00101000100;
27756let isPredicated = 1;
27757let isPredicatedFalse = 1;
27758let hasNewValue = 1;
27759let opNewValue = 0;
27760let addrMode = BaseImmOffset;
27761let accessSize = HVXVectorAccess;
27762let isCVLoad = 1;
27763let isCVI = 1;
27764let isHVXALU = 1;
27765let mayLoad = 1;
27766let isRestrictNoSlot1Store = 1;
27767let BaseOpcode = "V6_vL32b_ai";
27768let DecoderNamespace = "EXT_mmvec";
27769}
27770def V6_vL32b_npred_pi : HInst<
27771(outs HvxVR:$Vd32, IntRegs:$Rx32),
27772(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27773"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27774tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27775let Inst{7-5} = 0b011;
27776let Inst{13-13} = 0b0;
27777let Inst{31-21} = 0b00101001100;
27778let isPredicated = 1;
27779let isPredicatedFalse = 1;
27780let hasNewValue = 1;
27781let opNewValue = 0;
27782let addrMode = PostInc;
27783let accessSize = HVXVectorAccess;
27784let isCVLoad = 1;
27785let isCVI = 1;
27786let isHVXALU = 1;
27787let mayLoad = 1;
27788let isRestrictNoSlot1Store = 1;
27789let BaseOpcode = "V6_vL32b_pi";
27790let DecoderNamespace = "EXT_mmvec";
27791let Constraints = "$Rx32 = $Rx32in";
27792}
27793def V6_vL32b_npred_ppu : HInst<
27794(outs HvxVR:$Vd32, IntRegs:$Rx32),
27795(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27796"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27797tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27798let Inst{10-5} = 0b000011;
27799let Inst{31-21} = 0b00101011100;
27800let isPredicated = 1;
27801let isPredicatedFalse = 1;
27802let hasNewValue = 1;
27803let opNewValue = 0;
27804let addrMode = PostInc;
27805let accessSize = HVXVectorAccess;
27806let isCVLoad = 1;
27807let isCVI = 1;
27808let isHVXALU = 1;
27809let mayLoad = 1;
27810let isRestrictNoSlot1Store = 1;
27811let BaseOpcode = "V6_vL32b_ppu";
27812let DecoderNamespace = "EXT_mmvec";
27813let Constraints = "$Rx32 = $Rx32in";
27814}
27815def V6_vL32b_nt_ai : HInst<
27816(outs HvxVR:$Vd32),
27817(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27818"$Vd32 = vmem($Rt32+#$Ii):nt",
27819tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27820let Inst{7-5} = 0b000;
27821let Inst{12-11} = 0b00;
27822let Inst{31-21} = 0b00101000010;
27823let hasNewValue = 1;
27824let opNewValue = 0;
27825let addrMode = BaseImmOffset;
27826let accessSize = HVXVectorAccess;
27827let isCVLoad = 1;
27828let isCVI = 1;
27829let isHVXALU = 1;
27830let mayLoad = 1;
27831let isNonTemporal = 1;
27832let isRestrictNoSlot1Store = 1;
27833let BaseOpcode = "V6_vL32b_nt_ai";
27834let CextOpcode = "V6_vL32b_nt";
27835let isCVLoadable = 1;
27836let isPredicable = 1;
27837let DecoderNamespace = "EXT_mmvec";
27838}
27839def V6_vL32b_nt_cur_ai : HInst<
27840(outs HvxVR:$Vd32),
27841(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27842"$Vd32.cur = vmem($Rt32+#$Ii):nt",
27843tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27844let Inst{7-5} = 0b001;
27845let Inst{12-11} = 0b00;
27846let Inst{31-21} = 0b00101000010;
27847let hasNewValue = 1;
27848let opNewValue = 0;
27849let addrMode = BaseImmOffset;
27850let accessSize = HVXVectorAccess;
27851let isCVLoad = 1;
27852let isCVI = 1;
27853let CVINew = 1;
27854let isHVXALU = 1;
27855let mayLoad = 1;
27856let isNonTemporal = 1;
27857let isRestrictNoSlot1Store = 1;
27858let BaseOpcode = "V6_vL32b_nt_cur_ai";
27859let CextOpcode = "V6_vL32b_nt_cur";
27860let isPredicable = 1;
27861let DecoderNamespace = "EXT_mmvec";
27862}
27863def V6_vL32b_nt_cur_npred_ai : HInst<
27864(outs HvxVR:$Vd32),
27865(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27866"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27867tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27868let Inst{7-5} = 0b101;
27869let Inst{31-21} = 0b00101000110;
27870let isPredicated = 1;
27871let isPredicatedFalse = 1;
27872let hasNewValue = 1;
27873let opNewValue = 0;
27874let addrMode = BaseImmOffset;
27875let accessSize = HVXVectorAccess;
27876let isCVLoad = 1;
27877let isCVI = 1;
27878let CVINew = 1;
27879let isHVXALU = 1;
27880let mayLoad = 1;
27881let isNonTemporal = 1;
27882let isRestrictNoSlot1Store = 1;
27883let BaseOpcode = "V6_vL32b_nt_cur_ai";
27884let DecoderNamespace = "EXT_mmvec";
27885}
27886def V6_vL32b_nt_cur_npred_pi : HInst<
27887(outs HvxVR:$Vd32, IntRegs:$Rx32),
27888(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27889"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27890tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27891let Inst{7-5} = 0b101;
27892let Inst{13-13} = 0b0;
27893let Inst{31-21} = 0b00101001110;
27894let isPredicated = 1;
27895let isPredicatedFalse = 1;
27896let hasNewValue = 1;
27897let opNewValue = 0;
27898let addrMode = PostInc;
27899let accessSize = HVXVectorAccess;
27900let isCVLoad = 1;
27901let isCVI = 1;
27902let CVINew = 1;
27903let isHVXALU = 1;
27904let mayLoad = 1;
27905let isNonTemporal = 1;
27906let isRestrictNoSlot1Store = 1;
27907let BaseOpcode = "V6_vL32b_nt_cur_pi";
27908let DecoderNamespace = "EXT_mmvec";
27909let Constraints = "$Rx32 = $Rx32in";
27910}
27911def V6_vL32b_nt_cur_npred_ppu : HInst<
27912(outs HvxVR:$Vd32, IntRegs:$Rx32),
27913(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27914"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27915tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27916let Inst{10-5} = 0b000101;
27917let Inst{31-21} = 0b00101011110;
27918let isPredicated = 1;
27919let isPredicatedFalse = 1;
27920let hasNewValue = 1;
27921let opNewValue = 0;
27922let addrMode = PostInc;
27923let accessSize = HVXVectorAccess;
27924let isCVLoad = 1;
27925let isCVI = 1;
27926let CVINew = 1;
27927let isHVXALU = 1;
27928let mayLoad = 1;
27929let isNonTemporal = 1;
27930let isRestrictNoSlot1Store = 1;
27931let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27932let DecoderNamespace = "EXT_mmvec";
27933let Constraints = "$Rx32 = $Rx32in";
27934}
27935def V6_vL32b_nt_cur_pi : HInst<
27936(outs HvxVR:$Vd32, IntRegs:$Rx32),
27937(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27938"$Vd32.cur = vmem($Rx32++#$Ii):nt",
27939tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27940let Inst{7-5} = 0b001;
27941let Inst{13-11} = 0b000;
27942let Inst{31-21} = 0b00101001010;
27943let hasNewValue = 1;
27944let opNewValue = 0;
27945let addrMode = PostInc;
27946let accessSize = HVXVectorAccess;
27947let isCVLoad = 1;
27948let isCVI = 1;
27949let CVINew = 1;
27950let isHVXALU = 1;
27951let mayLoad = 1;
27952let isNonTemporal = 1;
27953let isRestrictNoSlot1Store = 1;
27954let BaseOpcode = "V6_vL32b_nt_cur_pi";
27955let CextOpcode = "V6_vL32b_nt_cur";
27956let isPredicable = 1;
27957let DecoderNamespace = "EXT_mmvec";
27958let Constraints = "$Rx32 = $Rx32in";
27959}
27960def V6_vL32b_nt_cur_ppu : HInst<
27961(outs HvxVR:$Vd32, IntRegs:$Rx32),
27962(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27963"$Vd32.cur = vmem($Rx32++$Mu2):nt",
27964tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27965let Inst{12-5} = 0b00000001;
27966let Inst{31-21} = 0b00101011010;
27967let hasNewValue = 1;
27968let opNewValue = 0;
27969let addrMode = PostInc;
27970let accessSize = HVXVectorAccess;
27971let isCVLoad = 1;
27972let isCVI = 1;
27973let CVINew = 1;
27974let isHVXALU = 1;
27975let mayLoad = 1;
27976let isNonTemporal = 1;
27977let isRestrictNoSlot1Store = 1;
27978let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27979let isPredicable = 1;
27980let DecoderNamespace = "EXT_mmvec";
27981let Constraints = "$Rx32 = $Rx32in";
27982}
27983def V6_vL32b_nt_cur_pred_ai : HInst<
27984(outs HvxVR:$Vd32),
27985(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27986"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27987tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27988let Inst{7-5} = 0b100;
27989let Inst{31-21} = 0b00101000110;
27990let isPredicated = 1;
27991let hasNewValue = 1;
27992let opNewValue = 0;
27993let addrMode = BaseImmOffset;
27994let accessSize = HVXVectorAccess;
27995let isCVLoad = 1;
27996let isCVI = 1;
27997let CVINew = 1;
27998let isHVXALU = 1;
27999let mayLoad = 1;
28000let isNonTemporal = 1;
28001let isRestrictNoSlot1Store = 1;
28002let BaseOpcode = "V6_vL32b_nt_cur_ai";
28003let DecoderNamespace = "EXT_mmvec";
28004}
28005def V6_vL32b_nt_cur_pred_pi : HInst<
28006(outs HvxVR:$Vd32, IntRegs:$Rx32),
28007(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28008"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
28009tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28010let Inst{7-5} = 0b100;
28011let Inst{13-13} = 0b0;
28012let Inst{31-21} = 0b00101001110;
28013let isPredicated = 1;
28014let hasNewValue = 1;
28015let opNewValue = 0;
28016let addrMode = PostInc;
28017let accessSize = HVXVectorAccess;
28018let isCVLoad = 1;
28019let isCVI = 1;
28020let CVINew = 1;
28021let isHVXALU = 1;
28022let mayLoad = 1;
28023let isNonTemporal = 1;
28024let isRestrictNoSlot1Store = 1;
28025let BaseOpcode = "V6_vL32b_nt_cur_pi";
28026let DecoderNamespace = "EXT_mmvec";
28027let Constraints = "$Rx32 = $Rx32in";
28028}
28029def V6_vL32b_nt_cur_pred_ppu : HInst<
28030(outs HvxVR:$Vd32, IntRegs:$Rx32),
28031(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28032"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
28033tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28034let Inst{10-5} = 0b000100;
28035let Inst{31-21} = 0b00101011110;
28036let isPredicated = 1;
28037let hasNewValue = 1;
28038let opNewValue = 0;
28039let addrMode = PostInc;
28040let accessSize = HVXVectorAccess;
28041let isCVLoad = 1;
28042let isCVI = 1;
28043let CVINew = 1;
28044let isHVXALU = 1;
28045let mayLoad = 1;
28046let isNonTemporal = 1;
28047let isRestrictNoSlot1Store = 1;
28048let BaseOpcode = "V6_vL32b_nt_cur_ppu";
28049let DecoderNamespace = "EXT_mmvec";
28050let Constraints = "$Rx32 = $Rx32in";
28051}
28052def V6_vL32b_nt_npred_ai : HInst<
28053(outs HvxVR:$Vd32),
28054(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28055"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
28056tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28057let Inst{7-5} = 0b011;
28058let Inst{31-21} = 0b00101000110;
28059let isPredicated = 1;
28060let isPredicatedFalse = 1;
28061let hasNewValue = 1;
28062let opNewValue = 0;
28063let addrMode = BaseImmOffset;
28064let accessSize = HVXVectorAccess;
28065let isCVLoad = 1;
28066let isCVI = 1;
28067let isHVXALU = 1;
28068let mayLoad = 1;
28069let isNonTemporal = 1;
28070let isRestrictNoSlot1Store = 1;
28071let BaseOpcode = "V6_vL32b_nt_ai";
28072let DecoderNamespace = "EXT_mmvec";
28073}
28074def V6_vL32b_nt_npred_pi : HInst<
28075(outs HvxVR:$Vd32, IntRegs:$Rx32),
28076(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28077"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
28078tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28079let Inst{7-5} = 0b011;
28080let Inst{13-13} = 0b0;
28081let Inst{31-21} = 0b00101001110;
28082let isPredicated = 1;
28083let isPredicatedFalse = 1;
28084let hasNewValue = 1;
28085let opNewValue = 0;
28086let addrMode = PostInc;
28087let accessSize = HVXVectorAccess;
28088let isCVLoad = 1;
28089let isCVI = 1;
28090let isHVXALU = 1;
28091let mayLoad = 1;
28092let isNonTemporal = 1;
28093let isRestrictNoSlot1Store = 1;
28094let BaseOpcode = "V6_vL32b_nt_pi";
28095let DecoderNamespace = "EXT_mmvec";
28096let Constraints = "$Rx32 = $Rx32in";
28097}
28098def V6_vL32b_nt_npred_ppu : HInst<
28099(outs HvxVR:$Vd32, IntRegs:$Rx32),
28100(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28101"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28102tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28103let Inst{10-5} = 0b000011;
28104let Inst{31-21} = 0b00101011110;
28105let isPredicated = 1;
28106let isPredicatedFalse = 1;
28107let hasNewValue = 1;
28108let opNewValue = 0;
28109let addrMode = PostInc;
28110let accessSize = HVXVectorAccess;
28111let isCVLoad = 1;
28112let isCVI = 1;
28113let isHVXALU = 1;
28114let mayLoad = 1;
28115let isNonTemporal = 1;
28116let isRestrictNoSlot1Store = 1;
28117let BaseOpcode = "V6_vL32b_nt_ppu";
28118let DecoderNamespace = "EXT_mmvec";
28119let Constraints = "$Rx32 = $Rx32in";
28120}
28121def V6_vL32b_nt_pi : HInst<
28122(outs HvxVR:$Vd32, IntRegs:$Rx32),
28123(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28124"$Vd32 = vmem($Rx32++#$Ii):nt",
28125tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28126let Inst{7-5} = 0b000;
28127let Inst{13-11} = 0b000;
28128let Inst{31-21} = 0b00101001010;
28129let hasNewValue = 1;
28130let opNewValue = 0;
28131let addrMode = PostInc;
28132let accessSize = HVXVectorAccess;
28133let isCVLoad = 1;
28134let isCVI = 1;
28135let isHVXALU = 1;
28136let mayLoad = 1;
28137let isNonTemporal = 1;
28138let isRestrictNoSlot1Store = 1;
28139let BaseOpcode = "V6_vL32b_nt_pi";
28140let CextOpcode = "V6_vL32b_nt";
28141let isCVLoadable = 1;
28142let isPredicable = 1;
28143let DecoderNamespace = "EXT_mmvec";
28144let Constraints = "$Rx32 = $Rx32in";
28145}
28146def V6_vL32b_nt_ppu : HInst<
28147(outs HvxVR:$Vd32, IntRegs:$Rx32),
28148(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28149"$Vd32 = vmem($Rx32++$Mu2):nt",
28150tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28151let Inst{12-5} = 0b00000000;
28152let Inst{31-21} = 0b00101011010;
28153let hasNewValue = 1;
28154let opNewValue = 0;
28155let addrMode = PostInc;
28156let accessSize = HVXVectorAccess;
28157let isCVLoad = 1;
28158let isCVI = 1;
28159let isHVXALU = 1;
28160let mayLoad = 1;
28161let isNonTemporal = 1;
28162let isRestrictNoSlot1Store = 1;
28163let BaseOpcode = "V6_vL32b_nt_ppu";
28164let isCVLoadable = 1;
28165let isPredicable = 1;
28166let DecoderNamespace = "EXT_mmvec";
28167let Constraints = "$Rx32 = $Rx32in";
28168}
28169def V6_vL32b_nt_pred_ai : HInst<
28170(outs HvxVR:$Vd32),
28171(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28172"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
28173tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28174let Inst{7-5} = 0b010;
28175let Inst{31-21} = 0b00101000110;
28176let isPredicated = 1;
28177let hasNewValue = 1;
28178let opNewValue = 0;
28179let addrMode = BaseImmOffset;
28180let accessSize = HVXVectorAccess;
28181let isCVLoad = 1;
28182let isCVI = 1;
28183let isHVXALU = 1;
28184let mayLoad = 1;
28185let isNonTemporal = 1;
28186let isRestrictNoSlot1Store = 1;
28187let BaseOpcode = "V6_vL32b_nt_ai";
28188let DecoderNamespace = "EXT_mmvec";
28189}
28190def V6_vL32b_nt_pred_pi : HInst<
28191(outs HvxVR:$Vd32, IntRegs:$Rx32),
28192(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28193"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
28194tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28195let Inst{7-5} = 0b010;
28196let Inst{13-13} = 0b0;
28197let Inst{31-21} = 0b00101001110;
28198let isPredicated = 1;
28199let hasNewValue = 1;
28200let opNewValue = 0;
28201let addrMode = PostInc;
28202let accessSize = HVXVectorAccess;
28203let isCVLoad = 1;
28204let isCVI = 1;
28205let isHVXALU = 1;
28206let mayLoad = 1;
28207let isNonTemporal = 1;
28208let isRestrictNoSlot1Store = 1;
28209let BaseOpcode = "V6_vL32b_nt_pi";
28210let DecoderNamespace = "EXT_mmvec";
28211let Constraints = "$Rx32 = $Rx32in";
28212}
28213def V6_vL32b_nt_pred_ppu : HInst<
28214(outs HvxVR:$Vd32, IntRegs:$Rx32),
28215(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28216"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28217tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28218let Inst{10-5} = 0b000010;
28219let Inst{31-21} = 0b00101011110;
28220let isPredicated = 1;
28221let hasNewValue = 1;
28222let opNewValue = 0;
28223let addrMode = PostInc;
28224let accessSize = HVXVectorAccess;
28225let isCVLoad = 1;
28226let isCVI = 1;
28227let isHVXALU = 1;
28228let mayLoad = 1;
28229let isNonTemporal = 1;
28230let isRestrictNoSlot1Store = 1;
28231let BaseOpcode = "V6_vL32b_nt_ppu";
28232let DecoderNamespace = "EXT_mmvec";
28233let Constraints = "$Rx32 = $Rx32in";
28234}
28235def V6_vL32b_nt_tmp_ai : HInst<
28236(outs HvxVR:$Vd32),
28237(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28238"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
28239tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28240let Inst{7-5} = 0b010;
28241let Inst{12-11} = 0b00;
28242let Inst{31-21} = 0b00101000010;
28243let hasNewValue = 1;
28244let opNewValue = 0;
28245let addrMode = BaseImmOffset;
28246let accessSize = HVXVectorAccess;
28247let isCVLoad = 1;
28248let isCVI = 1;
28249let hasHvxTmp = 1;
28250let mayLoad = 1;
28251let isNonTemporal = 1;
28252let isRestrictNoSlot1Store = 1;
28253let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28254let CextOpcode = "V6_vL32b_nt_tmp";
28255let isPredicable = 1;
28256let DecoderNamespace = "EXT_mmvec";
28257}
28258def V6_vL32b_nt_tmp_npred_ai : HInst<
28259(outs HvxVR:$Vd32),
28260(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28261"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28262tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28263let Inst{7-5} = 0b111;
28264let Inst{31-21} = 0b00101000110;
28265let isPredicated = 1;
28266let isPredicatedFalse = 1;
28267let hasNewValue = 1;
28268let opNewValue = 0;
28269let addrMode = BaseImmOffset;
28270let accessSize = HVXVectorAccess;
28271let isCVLoad = 1;
28272let isCVI = 1;
28273let hasHvxTmp = 1;
28274let mayLoad = 1;
28275let isNonTemporal = 1;
28276let isRestrictNoSlot1Store = 1;
28277let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28278let DecoderNamespace = "EXT_mmvec";
28279}
28280def V6_vL32b_nt_tmp_npred_pi : HInst<
28281(outs HvxVR:$Vd32, IntRegs:$Rx32),
28282(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28283"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28284tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28285let Inst{7-5} = 0b111;
28286let Inst{13-13} = 0b0;
28287let Inst{31-21} = 0b00101001110;
28288let isPredicated = 1;
28289let isPredicatedFalse = 1;
28290let hasNewValue = 1;
28291let opNewValue = 0;
28292let addrMode = PostInc;
28293let accessSize = HVXVectorAccess;
28294let isCVLoad = 1;
28295let isCVI = 1;
28296let hasHvxTmp = 1;
28297let mayLoad = 1;
28298let isNonTemporal = 1;
28299let isRestrictNoSlot1Store = 1;
28300let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28301let DecoderNamespace = "EXT_mmvec";
28302let Constraints = "$Rx32 = $Rx32in";
28303}
28304def V6_vL32b_nt_tmp_npred_ppu : HInst<
28305(outs HvxVR:$Vd32, IntRegs:$Rx32),
28306(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28307"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28308tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28309let Inst{10-5} = 0b000111;
28310let Inst{31-21} = 0b00101011110;
28311let isPredicated = 1;
28312let isPredicatedFalse = 1;
28313let hasNewValue = 1;
28314let opNewValue = 0;
28315let addrMode = PostInc;
28316let accessSize = HVXVectorAccess;
28317let isCVLoad = 1;
28318let isCVI = 1;
28319let hasHvxTmp = 1;
28320let mayLoad = 1;
28321let isNonTemporal = 1;
28322let isRestrictNoSlot1Store = 1;
28323let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28324let DecoderNamespace = "EXT_mmvec";
28325let Constraints = "$Rx32 = $Rx32in";
28326}
28327def V6_vL32b_nt_tmp_pi : HInst<
28328(outs HvxVR:$Vd32, IntRegs:$Rx32),
28329(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28330"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
28331tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28332let Inst{7-5} = 0b010;
28333let Inst{13-11} = 0b000;
28334let Inst{31-21} = 0b00101001010;
28335let hasNewValue = 1;
28336let opNewValue = 0;
28337let addrMode = PostInc;
28338let accessSize = HVXVectorAccess;
28339let isCVLoad = 1;
28340let isCVI = 1;
28341let hasHvxTmp = 1;
28342let mayLoad = 1;
28343let isNonTemporal = 1;
28344let isRestrictNoSlot1Store = 1;
28345let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28346let CextOpcode = "V6_vL32b_nt_tmp";
28347let isPredicable = 1;
28348let DecoderNamespace = "EXT_mmvec";
28349let Constraints = "$Rx32 = $Rx32in";
28350}
28351def V6_vL32b_nt_tmp_ppu : HInst<
28352(outs HvxVR:$Vd32, IntRegs:$Rx32),
28353(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28354"$Vd32.tmp = vmem($Rx32++$Mu2):nt",
28355tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28356let Inst{12-5} = 0b00000010;
28357let Inst{31-21} = 0b00101011010;
28358let hasNewValue = 1;
28359let opNewValue = 0;
28360let addrMode = PostInc;
28361let accessSize = HVXVectorAccess;
28362let isCVLoad = 1;
28363let isCVI = 1;
28364let hasHvxTmp = 1;
28365let mayLoad = 1;
28366let isNonTemporal = 1;
28367let isRestrictNoSlot1Store = 1;
28368let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28369let isPredicable = 1;
28370let DecoderNamespace = "EXT_mmvec";
28371let Constraints = "$Rx32 = $Rx32in";
28372}
28373def V6_vL32b_nt_tmp_pred_ai : HInst<
28374(outs HvxVR:$Vd32),
28375(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28376"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28377tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28378let Inst{7-5} = 0b110;
28379let Inst{31-21} = 0b00101000110;
28380let isPredicated = 1;
28381let hasNewValue = 1;
28382let opNewValue = 0;
28383let addrMode = BaseImmOffset;
28384let accessSize = HVXVectorAccess;
28385let isCVLoad = 1;
28386let isCVI = 1;
28387let hasHvxTmp = 1;
28388let mayLoad = 1;
28389let isNonTemporal = 1;
28390let isRestrictNoSlot1Store = 1;
28391let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28392let DecoderNamespace = "EXT_mmvec";
28393}
28394def V6_vL32b_nt_tmp_pred_pi : HInst<
28395(outs HvxVR:$Vd32, IntRegs:$Rx32),
28396(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28397"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28398tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28399let Inst{7-5} = 0b110;
28400let Inst{13-13} = 0b0;
28401let Inst{31-21} = 0b00101001110;
28402let isPredicated = 1;
28403let hasNewValue = 1;
28404let opNewValue = 0;
28405let addrMode = PostInc;
28406let accessSize = HVXVectorAccess;
28407let isCVLoad = 1;
28408let isCVI = 1;
28409let hasHvxTmp = 1;
28410let mayLoad = 1;
28411let isNonTemporal = 1;
28412let isRestrictNoSlot1Store = 1;
28413let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28414let DecoderNamespace = "EXT_mmvec";
28415let Constraints = "$Rx32 = $Rx32in";
28416}
28417def V6_vL32b_nt_tmp_pred_ppu : HInst<
28418(outs HvxVR:$Vd32, IntRegs:$Rx32),
28419(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28420"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28421tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28422let Inst{10-5} = 0b000110;
28423let Inst{31-21} = 0b00101011110;
28424let isPredicated = 1;
28425let hasNewValue = 1;
28426let opNewValue = 0;
28427let addrMode = PostInc;
28428let accessSize = HVXVectorAccess;
28429let isCVLoad = 1;
28430let isCVI = 1;
28431let hasHvxTmp = 1;
28432let mayLoad = 1;
28433let isNonTemporal = 1;
28434let isRestrictNoSlot1Store = 1;
28435let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28436let DecoderNamespace = "EXT_mmvec";
28437let Constraints = "$Rx32 = $Rx32in";
28438}
28439def V6_vL32b_pi : HInst<
28440(outs HvxVR:$Vd32, IntRegs:$Rx32),
28441(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28442"$Vd32 = vmem($Rx32++#$Ii)",
28443tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28444let Inst{7-5} = 0b000;
28445let Inst{13-11} = 0b000;
28446let Inst{31-21} = 0b00101001000;
28447let hasNewValue = 1;
28448let opNewValue = 0;
28449let addrMode = PostInc;
28450let accessSize = HVXVectorAccess;
28451let isCVLoad = 1;
28452let isCVI = 1;
28453let isHVXALU = 1;
28454let mayLoad = 1;
28455let isRestrictNoSlot1Store = 1;
28456let BaseOpcode = "V6_vL32b_pi";
28457let CextOpcode = "V6_vL32b";
28458let isCVLoadable = 1;
28459let isPredicable = 1;
28460let DecoderNamespace = "EXT_mmvec";
28461let Constraints = "$Rx32 = $Rx32in";
28462}
28463def V6_vL32b_ppu : HInst<
28464(outs HvxVR:$Vd32, IntRegs:$Rx32),
28465(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28466"$Vd32 = vmem($Rx32++$Mu2)",
28467tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28468let Inst{12-5} = 0b00000000;
28469let Inst{31-21} = 0b00101011000;
28470let hasNewValue = 1;
28471let opNewValue = 0;
28472let addrMode = PostInc;
28473let accessSize = HVXVectorAccess;
28474let isCVLoad = 1;
28475let isCVI = 1;
28476let isHVXALU = 1;
28477let mayLoad = 1;
28478let isRestrictNoSlot1Store = 1;
28479let BaseOpcode = "V6_vL32b_ppu";
28480let isCVLoadable = 1;
28481let isPredicable = 1;
28482let DecoderNamespace = "EXT_mmvec";
28483let Constraints = "$Rx32 = $Rx32in";
28484}
28485def V6_vL32b_pred_ai : HInst<
28486(outs HvxVR:$Vd32),
28487(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28488"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
28489tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28490let Inst{7-5} = 0b010;
28491let Inst{31-21} = 0b00101000100;
28492let isPredicated = 1;
28493let hasNewValue = 1;
28494let opNewValue = 0;
28495let addrMode = BaseImmOffset;
28496let accessSize = HVXVectorAccess;
28497let isCVLoad = 1;
28498let isCVI = 1;
28499let isHVXALU = 1;
28500let mayLoad = 1;
28501let isRestrictNoSlot1Store = 1;
28502let BaseOpcode = "V6_vL32b_ai";
28503let DecoderNamespace = "EXT_mmvec";
28504}
28505def V6_vL32b_pred_pi : HInst<
28506(outs HvxVR:$Vd32, IntRegs:$Rx32),
28507(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28508"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
28509tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28510let Inst{7-5} = 0b010;
28511let Inst{13-13} = 0b0;
28512let Inst{31-21} = 0b00101001100;
28513let isPredicated = 1;
28514let hasNewValue = 1;
28515let opNewValue = 0;
28516let addrMode = PostInc;
28517let accessSize = HVXVectorAccess;
28518let isCVLoad = 1;
28519let isCVI = 1;
28520let isHVXALU = 1;
28521let mayLoad = 1;
28522let isRestrictNoSlot1Store = 1;
28523let BaseOpcode = "V6_vL32b_pi";
28524let DecoderNamespace = "EXT_mmvec";
28525let Constraints = "$Rx32 = $Rx32in";
28526}
28527def V6_vL32b_pred_ppu : HInst<
28528(outs HvxVR:$Vd32, IntRegs:$Rx32),
28529(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28530"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
28531tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28532let Inst{10-5} = 0b000010;
28533let Inst{31-21} = 0b00101011100;
28534let isPredicated = 1;
28535let hasNewValue = 1;
28536let opNewValue = 0;
28537let addrMode = PostInc;
28538let accessSize = HVXVectorAccess;
28539let isCVLoad = 1;
28540let isCVI = 1;
28541let isHVXALU = 1;
28542let mayLoad = 1;
28543let isRestrictNoSlot1Store = 1;
28544let BaseOpcode = "V6_vL32b_ppu";
28545let DecoderNamespace = "EXT_mmvec";
28546let Constraints = "$Rx32 = $Rx32in";
28547}
28548def V6_vL32b_tmp_ai : HInst<
28549(outs HvxVR:$Vd32),
28550(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28551"$Vd32.tmp = vmem($Rt32+#$Ii)",
28552tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28553let Inst{7-5} = 0b010;
28554let Inst{12-11} = 0b00;
28555let Inst{31-21} = 0b00101000000;
28556let hasNewValue = 1;
28557let opNewValue = 0;
28558let addrMode = BaseImmOffset;
28559let accessSize = HVXVectorAccess;
28560let isCVLoad = 1;
28561let isCVI = 1;
28562let hasHvxTmp = 1;
28563let mayLoad = 1;
28564let isRestrictNoSlot1Store = 1;
28565let BaseOpcode = "V6_vL32b_tmp_ai";
28566let CextOpcode = "V6_vL32b_tmp";
28567let isPredicable = 1;
28568let DecoderNamespace = "EXT_mmvec";
28569}
28570def V6_vL32b_tmp_npred_ai : HInst<
28571(outs HvxVR:$Vd32),
28572(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28573"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28574tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28575let Inst{7-5} = 0b111;
28576let Inst{31-21} = 0b00101000100;
28577let isPredicated = 1;
28578let isPredicatedFalse = 1;
28579let hasNewValue = 1;
28580let opNewValue = 0;
28581let addrMode = BaseImmOffset;
28582let accessSize = HVXVectorAccess;
28583let isCVLoad = 1;
28584let isCVI = 1;
28585let hasHvxTmp = 1;
28586let mayLoad = 1;
28587let isRestrictNoSlot1Store = 1;
28588let BaseOpcode = "V6_vL32b_tmp_ai";
28589let DecoderNamespace = "EXT_mmvec";
28590}
28591def V6_vL32b_tmp_npred_pi : HInst<
28592(outs HvxVR:$Vd32, IntRegs:$Rx32),
28593(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28594"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28595tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28596let Inst{7-5} = 0b111;
28597let Inst{13-13} = 0b0;
28598let Inst{31-21} = 0b00101001100;
28599let isPredicated = 1;
28600let isPredicatedFalse = 1;
28601let hasNewValue = 1;
28602let opNewValue = 0;
28603let addrMode = PostInc;
28604let accessSize = HVXVectorAccess;
28605let isCVLoad = 1;
28606let isCVI = 1;
28607let hasHvxTmp = 1;
28608let mayLoad = 1;
28609let isRestrictNoSlot1Store = 1;
28610let BaseOpcode = "V6_vL32b_tmp_pi";
28611let DecoderNamespace = "EXT_mmvec";
28612let Constraints = "$Rx32 = $Rx32in";
28613}
28614def V6_vL32b_tmp_npred_ppu : HInst<
28615(outs HvxVR:$Vd32, IntRegs:$Rx32),
28616(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28617"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28618tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28619let Inst{10-5} = 0b000111;
28620let Inst{31-21} = 0b00101011100;
28621let isPredicated = 1;
28622let isPredicatedFalse = 1;
28623let hasNewValue = 1;
28624let opNewValue = 0;
28625let addrMode = PostInc;
28626let accessSize = HVXVectorAccess;
28627let isCVLoad = 1;
28628let isCVI = 1;
28629let hasHvxTmp = 1;
28630let mayLoad = 1;
28631let isRestrictNoSlot1Store = 1;
28632let BaseOpcode = "V6_vL32b_tmp_ppu";
28633let DecoderNamespace = "EXT_mmvec";
28634let Constraints = "$Rx32 = $Rx32in";
28635}
28636def V6_vL32b_tmp_pi : HInst<
28637(outs HvxVR:$Vd32, IntRegs:$Rx32),
28638(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28639"$Vd32.tmp = vmem($Rx32++#$Ii)",
28640tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28641let Inst{7-5} = 0b010;
28642let Inst{13-11} = 0b000;
28643let Inst{31-21} = 0b00101001000;
28644let hasNewValue = 1;
28645let opNewValue = 0;
28646let addrMode = PostInc;
28647let accessSize = HVXVectorAccess;
28648let isCVLoad = 1;
28649let isCVI = 1;
28650let hasHvxTmp = 1;
28651let mayLoad = 1;
28652let isRestrictNoSlot1Store = 1;
28653let BaseOpcode = "V6_vL32b_tmp_pi";
28654let CextOpcode = "V6_vL32b_tmp";
28655let isPredicable = 1;
28656let DecoderNamespace = "EXT_mmvec";
28657let Constraints = "$Rx32 = $Rx32in";
28658}
28659def V6_vL32b_tmp_ppu : HInst<
28660(outs HvxVR:$Vd32, IntRegs:$Rx32),
28661(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28662"$Vd32.tmp = vmem($Rx32++$Mu2)",
28663tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28664let Inst{12-5} = 0b00000010;
28665let Inst{31-21} = 0b00101011000;
28666let hasNewValue = 1;
28667let opNewValue = 0;
28668let addrMode = PostInc;
28669let accessSize = HVXVectorAccess;
28670let isCVLoad = 1;
28671let isCVI = 1;
28672let hasHvxTmp = 1;
28673let mayLoad = 1;
28674let isRestrictNoSlot1Store = 1;
28675let BaseOpcode = "V6_vL32b_tmp_ppu";
28676let isPredicable = 1;
28677let DecoderNamespace = "EXT_mmvec";
28678let Constraints = "$Rx32 = $Rx32in";
28679}
28680def V6_vL32b_tmp_pred_ai : HInst<
28681(outs HvxVR:$Vd32),
28682(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28683"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28684tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28685let Inst{7-5} = 0b110;
28686let Inst{31-21} = 0b00101000100;
28687let isPredicated = 1;
28688let hasNewValue = 1;
28689let opNewValue = 0;
28690let addrMode = BaseImmOffset;
28691let accessSize = HVXVectorAccess;
28692let isCVLoad = 1;
28693let isCVI = 1;
28694let hasHvxTmp = 1;
28695let mayLoad = 1;
28696let isRestrictNoSlot1Store = 1;
28697let BaseOpcode = "V6_vL32b_tmp_ai";
28698let DecoderNamespace = "EXT_mmvec";
28699}
28700def V6_vL32b_tmp_pred_pi : HInst<
28701(outs HvxVR:$Vd32, IntRegs:$Rx32),
28702(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28703"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28704tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28705let Inst{7-5} = 0b110;
28706let Inst{13-13} = 0b0;
28707let Inst{31-21} = 0b00101001100;
28708let isPredicated = 1;
28709let hasNewValue = 1;
28710let opNewValue = 0;
28711let addrMode = PostInc;
28712let accessSize = HVXVectorAccess;
28713let isCVLoad = 1;
28714let isCVI = 1;
28715let hasHvxTmp = 1;
28716let mayLoad = 1;
28717let isRestrictNoSlot1Store = 1;
28718let BaseOpcode = "V6_vL32b_tmp_pi";
28719let DecoderNamespace = "EXT_mmvec";
28720let Constraints = "$Rx32 = $Rx32in";
28721}
28722def V6_vL32b_tmp_pred_ppu : HInst<
28723(outs HvxVR:$Vd32, IntRegs:$Rx32),
28724(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28725"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28726tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28727let Inst{10-5} = 0b000110;
28728let Inst{31-21} = 0b00101011100;
28729let isPredicated = 1;
28730let hasNewValue = 1;
28731let opNewValue = 0;
28732let addrMode = PostInc;
28733let accessSize = HVXVectorAccess;
28734let isCVLoad = 1;
28735let isCVI = 1;
28736let hasHvxTmp = 1;
28737let mayLoad = 1;
28738let isRestrictNoSlot1Store = 1;
28739let BaseOpcode = "V6_vL32b_tmp_ppu";
28740let DecoderNamespace = "EXT_mmvec";
28741let Constraints = "$Rx32 = $Rx32in";
28742}
28743def V6_vS32Ub_ai : HInst<
28744(outs),
28745(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28746"vmemu($Rt32+#$Ii) = $Vs32",
28747tc_f21e8abb, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28748let Inst{7-5} = 0b111;
28749let Inst{12-11} = 0b00;
28750let Inst{31-21} = 0b00101000001;
28751let addrMode = BaseImmOffset;
28752let accessSize = HVXVectorAccess;
28753let isCVI = 1;
28754let mayStore = 1;
28755let BaseOpcode = "V6_vS32Ub_ai";
28756let CextOpcode = "V6_vS32Ub";
28757let isPredicable = 1;
28758let DecoderNamespace = "EXT_mmvec";
28759}
28760def V6_vS32Ub_npred_ai : HInst<
28761(outs),
28762(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28763"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28764tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28765let Inst{7-5} = 0b111;
28766let Inst{31-21} = 0b00101000101;
28767let isPredicated = 1;
28768let isPredicatedFalse = 1;
28769let addrMode = BaseImmOffset;
28770let accessSize = HVXVectorAccess;
28771let isCVI = 1;
28772let mayStore = 1;
28773let BaseOpcode = "V6_vS32Ub_ai";
28774let DecoderNamespace = "EXT_mmvec";
28775}
28776def V6_vS32Ub_npred_pi : HInst<
28777(outs IntRegs:$Rx32),
28778(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28779"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28780tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28781let Inst{7-5} = 0b111;
28782let Inst{13-13} = 0b0;
28783let Inst{31-21} = 0b00101001101;
28784let isPredicated = 1;
28785let isPredicatedFalse = 1;
28786let addrMode = PostInc;
28787let accessSize = HVXVectorAccess;
28788let isCVI = 1;
28789let mayStore = 1;
28790let BaseOpcode = "V6_vS32Ub_pi";
28791let DecoderNamespace = "EXT_mmvec";
28792let Constraints = "$Rx32 = $Rx32in";
28793}
28794def V6_vS32Ub_npred_ppu : HInst<
28795(outs IntRegs:$Rx32),
28796(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28797"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28798tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28799let Inst{10-5} = 0b000111;
28800let Inst{31-21} = 0b00101011101;
28801let isPredicated = 1;
28802let isPredicatedFalse = 1;
28803let addrMode = PostInc;
28804let accessSize = HVXVectorAccess;
28805let isCVI = 1;
28806let mayStore = 1;
28807let BaseOpcode = "V6_vS32Ub_ppu";
28808let DecoderNamespace = "EXT_mmvec";
28809let Constraints = "$Rx32 = $Rx32in";
28810}
28811def V6_vS32Ub_pi : HInst<
28812(outs IntRegs:$Rx32),
28813(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28814"vmemu($Rx32++#$Ii) = $Vs32",
28815tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28816let Inst{7-5} = 0b111;
28817let Inst{13-11} = 0b000;
28818let Inst{31-21} = 0b00101001001;
28819let addrMode = PostInc;
28820let accessSize = HVXVectorAccess;
28821let isCVI = 1;
28822let mayStore = 1;
28823let BaseOpcode = "V6_vS32Ub_pi";
28824let CextOpcode = "V6_vS32Ub";
28825let isPredicable = 1;
28826let DecoderNamespace = "EXT_mmvec";
28827let Constraints = "$Rx32 = $Rx32in";
28828}
28829def V6_vS32Ub_ppu : HInst<
28830(outs IntRegs:$Rx32),
28831(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28832"vmemu($Rx32++$Mu2) = $Vs32",
28833tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28834let Inst{12-5} = 0b00000111;
28835let Inst{31-21} = 0b00101011001;
28836let addrMode = PostInc;
28837let accessSize = HVXVectorAccess;
28838let isCVI = 1;
28839let mayStore = 1;
28840let BaseOpcode = "V6_vS32Ub_ppu";
28841let isPredicable = 1;
28842let DecoderNamespace = "EXT_mmvec";
28843let Constraints = "$Rx32 = $Rx32in";
28844}
28845def V6_vS32Ub_pred_ai : HInst<
28846(outs),
28847(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28848"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28849tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28850let Inst{7-5} = 0b110;
28851let Inst{31-21} = 0b00101000101;
28852let isPredicated = 1;
28853let addrMode = BaseImmOffset;
28854let accessSize = HVXVectorAccess;
28855let isCVI = 1;
28856let mayStore = 1;
28857let BaseOpcode = "V6_vS32Ub_ai";
28858let DecoderNamespace = "EXT_mmvec";
28859}
28860def V6_vS32Ub_pred_pi : HInst<
28861(outs IntRegs:$Rx32),
28862(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28863"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28864tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28865let Inst{7-5} = 0b110;
28866let Inst{13-13} = 0b0;
28867let Inst{31-21} = 0b00101001101;
28868let isPredicated = 1;
28869let addrMode = PostInc;
28870let accessSize = HVXVectorAccess;
28871let isCVI = 1;
28872let mayStore = 1;
28873let BaseOpcode = "V6_vS32Ub_pi";
28874let DecoderNamespace = "EXT_mmvec";
28875let Constraints = "$Rx32 = $Rx32in";
28876}
28877def V6_vS32Ub_pred_ppu : HInst<
28878(outs IntRegs:$Rx32),
28879(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28880"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28881tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28882let Inst{10-5} = 0b000110;
28883let Inst{31-21} = 0b00101011101;
28884let isPredicated = 1;
28885let addrMode = PostInc;
28886let accessSize = HVXVectorAccess;
28887let isCVI = 1;
28888let mayStore = 1;
28889let BaseOpcode = "V6_vS32Ub_ppu";
28890let DecoderNamespace = "EXT_mmvec";
28891let Constraints = "$Rx32 = $Rx32in";
28892}
28893def V6_vS32b_ai : HInst<
28894(outs),
28895(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28896"vmem($Rt32+#$Ii) = $Vs32",
28897tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28898let Inst{7-5} = 0b000;
28899let Inst{12-11} = 0b00;
28900let Inst{31-21} = 0b00101000001;
28901let addrMode = BaseImmOffset;
28902let accessSize = HVXVectorAccess;
28903let isCVI = 1;
28904let isHVXALU = 1;
28905let mayStore = 1;
28906let BaseOpcode = "V6_vS32b_ai";
28907let CextOpcode = "V6_vS32b";
28908let isNVStorable = 1;
28909let isPredicable = 1;
28910let DecoderNamespace = "EXT_mmvec";
28911}
28912def V6_vS32b_new_ai : HInst<
28913(outs),
28914(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28915"vmem($Rt32+#$Ii) = $Os8.new",
28916tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28917let Inst{7-3} = 0b00100;
28918let Inst{12-11} = 0b00;
28919let Inst{31-21} = 0b00101000001;
28920let addrMode = BaseImmOffset;
28921let accessSize = HVXVectorAccess;
28922let isNVStore = 1;
28923let isCVI = 1;
28924let CVINew = 1;
28925let isNewValue = 1;
28926let mayStore = 1;
28927let BaseOpcode = "V6_vS32b_ai";
28928let CextOpcode = "V6_vS32b_new";
28929let isPredicable = 1;
28930let DecoderNamespace = "EXT_mmvec";
28931let opNewValue = 2;
28932}
28933def V6_vS32b_new_npred_ai : HInst<
28934(outs),
28935(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28936"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28937tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28938let Inst{7-3} = 0b01101;
28939let Inst{31-21} = 0b00101000101;
28940let isPredicated = 1;
28941let isPredicatedFalse = 1;
28942let addrMode = BaseImmOffset;
28943let accessSize = HVXVectorAccess;
28944let isNVStore = 1;
28945let isCVI = 1;
28946let CVINew = 1;
28947let isNewValue = 1;
28948let mayStore = 1;
28949let BaseOpcode = "V6_vS32b_ai";
28950let DecoderNamespace = "EXT_mmvec";
28951let opNewValue = 3;
28952}
28953def V6_vS32b_new_npred_pi : HInst<
28954(outs IntRegs:$Rx32),
28955(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28956"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28957tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28958let Inst{7-3} = 0b01101;
28959let Inst{13-13} = 0b0;
28960let Inst{31-21} = 0b00101001101;
28961let isPredicated = 1;
28962let isPredicatedFalse = 1;
28963let addrMode = PostInc;
28964let accessSize = HVXVectorAccess;
28965let isNVStore = 1;
28966let isCVI = 1;
28967let CVINew = 1;
28968let isNewValue = 1;
28969let mayStore = 1;
28970let BaseOpcode = "V6_vS32b_pi";
28971let DecoderNamespace = "EXT_mmvec";
28972let opNewValue = 4;
28973let Constraints = "$Rx32 = $Rx32in";
28974}
28975def V6_vS32b_new_npred_ppu : HInst<
28976(outs IntRegs:$Rx32),
28977(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28978"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28979tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28980let Inst{10-3} = 0b00001101;
28981let Inst{31-21} = 0b00101011101;
28982let isPredicated = 1;
28983let isPredicatedFalse = 1;
28984let addrMode = PostInc;
28985let accessSize = HVXVectorAccess;
28986let isNVStore = 1;
28987let isCVI = 1;
28988let CVINew = 1;
28989let isNewValue = 1;
28990let mayStore = 1;
28991let BaseOpcode = "V6_vS32b_ppu";
28992let DecoderNamespace = "EXT_mmvec";
28993let opNewValue = 4;
28994let Constraints = "$Rx32 = $Rx32in";
28995}
28996def V6_vS32b_new_pi : HInst<
28997(outs IntRegs:$Rx32),
28998(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28999"vmem($Rx32++#$Ii) = $Os8.new",
29000tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29001let Inst{7-3} = 0b00100;
29002let Inst{13-11} = 0b000;
29003let Inst{31-21} = 0b00101001001;
29004let addrMode = PostInc;
29005let accessSize = HVXVectorAccess;
29006let isNVStore = 1;
29007let isCVI = 1;
29008let CVINew = 1;
29009let isNewValue = 1;
29010let mayStore = 1;
29011let BaseOpcode = "V6_vS32b_pi";
29012let CextOpcode = "V6_vS32b_new";
29013let isPredicable = 1;
29014let DecoderNamespace = "EXT_mmvec";
29015let opNewValue = 3;
29016let Constraints = "$Rx32 = $Rx32in";
29017}
29018def V6_vS32b_new_ppu : HInst<
29019(outs IntRegs:$Rx32),
29020(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29021"vmem($Rx32++$Mu2) = $Os8.new",
29022tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
29023let Inst{12-3} = 0b0000000100;
29024let Inst{31-21} = 0b00101011001;
29025let addrMode = PostInc;
29026let accessSize = HVXVectorAccess;
29027let isNVStore = 1;
29028let isCVI = 1;
29029let CVINew = 1;
29030let isNewValue = 1;
29031let mayStore = 1;
29032let BaseOpcode = "V6_vS32b_ppu";
29033let isPredicable = 1;
29034let DecoderNamespace = "EXT_mmvec";
29035let opNewValue = 3;
29036let Constraints = "$Rx32 = $Rx32in";
29037}
29038def V6_vS32b_new_pred_ai : HInst<
29039(outs),
29040(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29041"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
29042tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29043let Inst{7-3} = 0b01000;
29044let Inst{31-21} = 0b00101000101;
29045let isPredicated = 1;
29046let addrMode = BaseImmOffset;
29047let accessSize = HVXVectorAccess;
29048let isNVStore = 1;
29049let isCVI = 1;
29050let CVINew = 1;
29051let isNewValue = 1;
29052let mayStore = 1;
29053let BaseOpcode = "V6_vS32b_ai";
29054let DecoderNamespace = "EXT_mmvec";
29055let opNewValue = 3;
29056}
29057def V6_vS32b_new_pred_pi : HInst<
29058(outs IntRegs:$Rx32),
29059(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29060"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
29061tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29062let Inst{7-3} = 0b01000;
29063let Inst{13-13} = 0b0;
29064let Inst{31-21} = 0b00101001101;
29065let isPredicated = 1;
29066let addrMode = PostInc;
29067let accessSize = HVXVectorAccess;
29068let isNVStore = 1;
29069let isCVI = 1;
29070let CVINew = 1;
29071let isNewValue = 1;
29072let mayStore = 1;
29073let BaseOpcode = "V6_vS32b_pi";
29074let DecoderNamespace = "EXT_mmvec";
29075let opNewValue = 4;
29076let Constraints = "$Rx32 = $Rx32in";
29077}
29078def V6_vS32b_new_pred_ppu : HInst<
29079(outs IntRegs:$Rx32),
29080(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29081"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
29082tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29083let Inst{10-3} = 0b00001000;
29084let Inst{31-21} = 0b00101011101;
29085let isPredicated = 1;
29086let addrMode = PostInc;
29087let accessSize = HVXVectorAccess;
29088let isNVStore = 1;
29089let isCVI = 1;
29090let CVINew = 1;
29091let isNewValue = 1;
29092let mayStore = 1;
29093let BaseOpcode = "V6_vS32b_ppu";
29094let DecoderNamespace = "EXT_mmvec";
29095let opNewValue = 4;
29096let Constraints = "$Rx32 = $Rx32in";
29097}
29098def V6_vS32b_npred_ai : HInst<
29099(outs),
29100(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29101"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
29102tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29103let Inst{7-5} = 0b001;
29104let Inst{31-21} = 0b00101000101;
29105let isPredicated = 1;
29106let isPredicatedFalse = 1;
29107let addrMode = BaseImmOffset;
29108let accessSize = HVXVectorAccess;
29109let isCVI = 1;
29110let isHVXALU = 1;
29111let mayStore = 1;
29112let BaseOpcode = "V6_vS32b_ai";
29113let isNVStorable = 1;
29114let DecoderNamespace = "EXT_mmvec";
29115}
29116def V6_vS32b_npred_pi : HInst<
29117(outs IntRegs:$Rx32),
29118(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29119"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
29120tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29121let Inst{7-5} = 0b001;
29122let Inst{13-13} = 0b0;
29123let Inst{31-21} = 0b00101001101;
29124let isPredicated = 1;
29125let isPredicatedFalse = 1;
29126let addrMode = PostInc;
29127let accessSize = HVXVectorAccess;
29128let isCVI = 1;
29129let isHVXALU = 1;
29130let mayStore = 1;
29131let BaseOpcode = "V6_vS32b_pi";
29132let isNVStorable = 1;
29133let DecoderNamespace = "EXT_mmvec";
29134let Constraints = "$Rx32 = $Rx32in";
29135}
29136def V6_vS32b_npred_ppu : HInst<
29137(outs IntRegs:$Rx32),
29138(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29139"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
29140tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29141let Inst{10-5} = 0b000001;
29142let Inst{31-21} = 0b00101011101;
29143let isPredicated = 1;
29144let isPredicatedFalse = 1;
29145let addrMode = PostInc;
29146let accessSize = HVXVectorAccess;
29147let isCVI = 1;
29148let isHVXALU = 1;
29149let mayStore = 1;
29150let BaseOpcode = "V6_vS32b_ppu";
29151let isNVStorable = 1;
29152let DecoderNamespace = "EXT_mmvec";
29153let Constraints = "$Rx32 = $Rx32in";
29154}
29155def V6_vS32b_nqpred_ai : HInst<
29156(outs),
29157(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29158"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
29159tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29160let Inst{7-5} = 0b001;
29161let Inst{31-21} = 0b00101000100;
29162let addrMode = BaseImmOffset;
29163let accessSize = HVXVectorAccess;
29164let isCVI = 1;
29165let isHVXALU = 1;
29166let mayStore = 1;
29167let DecoderNamespace = "EXT_mmvec";
29168}
29169def V6_vS32b_nqpred_pi : HInst<
29170(outs IntRegs:$Rx32),
29171(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29172"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
29173tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29174let Inst{7-5} = 0b001;
29175let Inst{13-13} = 0b0;
29176let Inst{31-21} = 0b00101001100;
29177let addrMode = PostInc;
29178let accessSize = HVXVectorAccess;
29179let isCVI = 1;
29180let isHVXALU = 1;
29181let mayStore = 1;
29182let DecoderNamespace = "EXT_mmvec";
29183let Constraints = "$Rx32 = $Rx32in";
29184}
29185def V6_vS32b_nqpred_ppu : HInst<
29186(outs IntRegs:$Rx32),
29187(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29188"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
29189tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29190let Inst{10-5} = 0b000001;
29191let Inst{31-21} = 0b00101011100;
29192let addrMode = PostInc;
29193let accessSize = HVXVectorAccess;
29194let isCVI = 1;
29195let isHVXALU = 1;
29196let mayStore = 1;
29197let DecoderNamespace = "EXT_mmvec";
29198let Constraints = "$Rx32 = $Rx32in";
29199}
29200def V6_vS32b_nt_ai : HInst<
29201(outs),
29202(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29203"vmem($Rt32+#$Ii):nt = $Vs32",
29204tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29205let Inst{7-5} = 0b000;
29206let Inst{12-11} = 0b00;
29207let Inst{31-21} = 0b00101000011;
29208let addrMode = BaseImmOffset;
29209let accessSize = HVXVectorAccess;
29210let isCVI = 1;
29211let isHVXALU = 1;
29212let isNonTemporal = 1;
29213let mayStore = 1;
29214let BaseOpcode = "V6_vS32b_ai";
29215let CextOpcode = "V6_vS32b_nt";
29216let isNVStorable = 1;
29217let isPredicable = 1;
29218let DecoderNamespace = "EXT_mmvec";
29219}
29220def V6_vS32b_nt_new_ai : HInst<
29221(outs),
29222(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29223"vmem($Rt32+#$Ii):nt = $Os8.new",
29224tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29225let Inst{7-3} = 0b00100;
29226let Inst{12-11} = 0b00;
29227let Inst{31-21} = 0b00101000011;
29228let addrMode = BaseImmOffset;
29229let accessSize = HVXVectorAccess;
29230let isNVStore = 1;
29231let isCVI = 1;
29232let CVINew = 1;
29233let isNewValue = 1;
29234let isNonTemporal = 1;
29235let mayStore = 1;
29236let BaseOpcode = "V6_vS32b_ai";
29237let CextOpcode = "V6_vS32b_nt_new";
29238let isPredicable = 1;
29239let DecoderNamespace = "EXT_mmvec";
29240let opNewValue = 2;
29241}
29242def V6_vS32b_nt_new_npred_ai : HInst<
29243(outs),
29244(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29245"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29246tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29247let Inst{7-3} = 0b01111;
29248let Inst{31-21} = 0b00101000111;
29249let isPredicated = 1;
29250let isPredicatedFalse = 1;
29251let addrMode = BaseImmOffset;
29252let accessSize = HVXVectorAccess;
29253let isNVStore = 1;
29254let isCVI = 1;
29255let CVINew = 1;
29256let isNewValue = 1;
29257let isNonTemporal = 1;
29258let mayStore = 1;
29259let BaseOpcode = "V6_vS32b_ai";
29260let DecoderNamespace = "EXT_mmvec";
29261let opNewValue = 3;
29262}
29263def V6_vS32b_nt_new_npred_pi : HInst<
29264(outs IntRegs:$Rx32),
29265(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29266"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29267tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29268let Inst{7-3} = 0b01111;
29269let Inst{13-13} = 0b0;
29270let Inst{31-21} = 0b00101001111;
29271let isPredicated = 1;
29272let isPredicatedFalse = 1;
29273let addrMode = PostInc;
29274let accessSize = HVXVectorAccess;
29275let isNVStore = 1;
29276let isCVI = 1;
29277let CVINew = 1;
29278let isNewValue = 1;
29279let isNonTemporal = 1;
29280let mayStore = 1;
29281let BaseOpcode = "V6_vS32b_pi";
29282let DecoderNamespace = "EXT_mmvec";
29283let opNewValue = 4;
29284let Constraints = "$Rx32 = $Rx32in";
29285}
29286def V6_vS32b_nt_new_npred_ppu : HInst<
29287(outs IntRegs:$Rx32),
29288(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29289"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29290tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29291let Inst{10-3} = 0b00001111;
29292let Inst{31-21} = 0b00101011111;
29293let isPredicated = 1;
29294let isPredicatedFalse = 1;
29295let addrMode = PostInc;
29296let accessSize = HVXVectorAccess;
29297let isNVStore = 1;
29298let isCVI = 1;
29299let CVINew = 1;
29300let isNewValue = 1;
29301let isNonTemporal = 1;
29302let mayStore = 1;
29303let BaseOpcode = "V6_vS32b_ppu";
29304let DecoderNamespace = "EXT_mmvec";
29305let opNewValue = 4;
29306let Constraints = "$Rx32 = $Rx32in";
29307}
29308def V6_vS32b_nt_new_pi : HInst<
29309(outs IntRegs:$Rx32),
29310(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29311"vmem($Rx32++#$Ii):nt = $Os8.new",
29312tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29313let Inst{7-3} = 0b00100;
29314let Inst{13-11} = 0b000;
29315let Inst{31-21} = 0b00101001011;
29316let addrMode = PostInc;
29317let accessSize = HVXVectorAccess;
29318let isNVStore = 1;
29319let isCVI = 1;
29320let CVINew = 1;
29321let isNewValue = 1;
29322let isNonTemporal = 1;
29323let mayStore = 1;
29324let BaseOpcode = "V6_vS32b_pi";
29325let CextOpcode = "V6_vS32b_nt_new";
29326let isPredicable = 1;
29327let DecoderNamespace = "EXT_mmvec";
29328let opNewValue = 3;
29329let Constraints = "$Rx32 = $Rx32in";
29330}
29331def V6_vS32b_nt_new_ppu : HInst<
29332(outs IntRegs:$Rx32),
29333(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29334"vmem($Rx32++$Mu2):nt = $Os8.new",
29335tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
29336let Inst{12-3} = 0b0000000100;
29337let Inst{31-21} = 0b00101011011;
29338let addrMode = PostInc;
29339let accessSize = HVXVectorAccess;
29340let isNVStore = 1;
29341let isCVI = 1;
29342let CVINew = 1;
29343let isNewValue = 1;
29344let isNonTemporal = 1;
29345let mayStore = 1;
29346let BaseOpcode = "V6_vS32b_ppu";
29347let isPredicable = 1;
29348let DecoderNamespace = "EXT_mmvec";
29349let opNewValue = 3;
29350let Constraints = "$Rx32 = $Rx32in";
29351}
29352def V6_vS32b_nt_new_pred_ai : HInst<
29353(outs),
29354(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29355"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29356tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29357let Inst{7-3} = 0b01010;
29358let Inst{31-21} = 0b00101000111;
29359let isPredicated = 1;
29360let addrMode = BaseImmOffset;
29361let accessSize = HVXVectorAccess;
29362let isNVStore = 1;
29363let isCVI = 1;
29364let CVINew = 1;
29365let isNewValue = 1;
29366let isNonTemporal = 1;
29367let mayStore = 1;
29368let BaseOpcode = "V6_vS32b_ai";
29369let DecoderNamespace = "EXT_mmvec";
29370let opNewValue = 3;
29371}
29372def V6_vS32b_nt_new_pred_pi : HInst<
29373(outs IntRegs:$Rx32),
29374(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29375"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29376tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29377let Inst{7-3} = 0b01010;
29378let Inst{13-13} = 0b0;
29379let Inst{31-21} = 0b00101001111;
29380let isPredicated = 1;
29381let addrMode = PostInc;
29382let accessSize = HVXVectorAccess;
29383let isNVStore = 1;
29384let isCVI = 1;
29385let CVINew = 1;
29386let isNewValue = 1;
29387let isNonTemporal = 1;
29388let mayStore = 1;
29389let BaseOpcode = "V6_vS32b_pi";
29390let DecoderNamespace = "EXT_mmvec";
29391let opNewValue = 4;
29392let Constraints = "$Rx32 = $Rx32in";
29393}
29394def V6_vS32b_nt_new_pred_ppu : HInst<
29395(outs IntRegs:$Rx32),
29396(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29397"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29398tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29399let Inst{10-3} = 0b00001010;
29400let Inst{31-21} = 0b00101011111;
29401let isPredicated = 1;
29402let addrMode = PostInc;
29403let accessSize = HVXVectorAccess;
29404let isNVStore = 1;
29405let isCVI = 1;
29406let CVINew = 1;
29407let isNewValue = 1;
29408let isNonTemporal = 1;
29409let mayStore = 1;
29410let BaseOpcode = "V6_vS32b_ppu";
29411let DecoderNamespace = "EXT_mmvec";
29412let opNewValue = 4;
29413let Constraints = "$Rx32 = $Rx32in";
29414}
29415def V6_vS32b_nt_npred_ai : HInst<
29416(outs),
29417(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29418"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29419tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29420let Inst{7-5} = 0b001;
29421let Inst{31-21} = 0b00101000111;
29422let isPredicated = 1;
29423let isPredicatedFalse = 1;
29424let addrMode = BaseImmOffset;
29425let accessSize = HVXVectorAccess;
29426let isCVI = 1;
29427let isHVXALU = 1;
29428let isNonTemporal = 1;
29429let mayStore = 1;
29430let BaseOpcode = "V6_vS32b_ai";
29431let isNVStorable = 1;
29432let DecoderNamespace = "EXT_mmvec";
29433}
29434def V6_vS32b_nt_npred_pi : HInst<
29435(outs IntRegs:$Rx32),
29436(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29437"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29438tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29439let Inst{7-5} = 0b001;
29440let Inst{13-13} = 0b0;
29441let Inst{31-21} = 0b00101001111;
29442let isPredicated = 1;
29443let isPredicatedFalse = 1;
29444let addrMode = PostInc;
29445let accessSize = HVXVectorAccess;
29446let isCVI = 1;
29447let isHVXALU = 1;
29448let isNonTemporal = 1;
29449let mayStore = 1;
29450let BaseOpcode = "V6_vS32b_pi";
29451let isNVStorable = 1;
29452let DecoderNamespace = "EXT_mmvec";
29453let Constraints = "$Rx32 = $Rx32in";
29454}
29455def V6_vS32b_nt_npred_ppu : HInst<
29456(outs IntRegs:$Rx32),
29457(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29458"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29459tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29460let Inst{10-5} = 0b000001;
29461let Inst{31-21} = 0b00101011111;
29462let isPredicated = 1;
29463let isPredicatedFalse = 1;
29464let addrMode = PostInc;
29465let accessSize = HVXVectorAccess;
29466let isCVI = 1;
29467let isHVXALU = 1;
29468let isNonTemporal = 1;
29469let mayStore = 1;
29470let BaseOpcode = "V6_vS32b_ppu";
29471let isNVStorable = 1;
29472let DecoderNamespace = "EXT_mmvec";
29473let Constraints = "$Rx32 = $Rx32in";
29474}
29475def V6_vS32b_nt_nqpred_ai : HInst<
29476(outs),
29477(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29478"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29479tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29480let Inst{7-5} = 0b001;
29481let Inst{31-21} = 0b00101000110;
29482let addrMode = BaseImmOffset;
29483let accessSize = HVXVectorAccess;
29484let isCVI = 1;
29485let isHVXALU = 1;
29486let isNonTemporal = 1;
29487let mayStore = 1;
29488let DecoderNamespace = "EXT_mmvec";
29489}
29490def V6_vS32b_nt_nqpred_pi : HInst<
29491(outs IntRegs:$Rx32),
29492(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29493"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29494tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29495let Inst{7-5} = 0b001;
29496let Inst{13-13} = 0b0;
29497let Inst{31-21} = 0b00101001110;
29498let addrMode = PostInc;
29499let accessSize = HVXVectorAccess;
29500let isCVI = 1;
29501let isHVXALU = 1;
29502let isNonTemporal = 1;
29503let mayStore = 1;
29504let DecoderNamespace = "EXT_mmvec";
29505let Constraints = "$Rx32 = $Rx32in";
29506}
29507def V6_vS32b_nt_nqpred_ppu : HInst<
29508(outs IntRegs:$Rx32),
29509(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29510"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29511tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29512let Inst{10-5} = 0b000001;
29513let Inst{31-21} = 0b00101011110;
29514let addrMode = PostInc;
29515let accessSize = HVXVectorAccess;
29516let isCVI = 1;
29517let isHVXALU = 1;
29518let isNonTemporal = 1;
29519let mayStore = 1;
29520let DecoderNamespace = "EXT_mmvec";
29521let Constraints = "$Rx32 = $Rx32in";
29522}
29523def V6_vS32b_nt_pi : HInst<
29524(outs IntRegs:$Rx32),
29525(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29526"vmem($Rx32++#$Ii):nt = $Vs32",
29527tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29528let Inst{7-5} = 0b000;
29529let Inst{13-11} = 0b000;
29530let Inst{31-21} = 0b00101001011;
29531let addrMode = PostInc;
29532let accessSize = HVXVectorAccess;
29533let isCVI = 1;
29534let isHVXALU = 1;
29535let isNonTemporal = 1;
29536let mayStore = 1;
29537let BaseOpcode = "V6_vS32b_pi";
29538let CextOpcode = "V6_vS32b_nt";
29539let isNVStorable = 1;
29540let isPredicable = 1;
29541let DecoderNamespace = "EXT_mmvec";
29542let Constraints = "$Rx32 = $Rx32in";
29543}
29544def V6_vS32b_nt_ppu : HInst<
29545(outs IntRegs:$Rx32),
29546(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29547"vmem($Rx32++$Mu2):nt = $Vs32",
29548tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29549let Inst{12-5} = 0b00000000;
29550let Inst{31-21} = 0b00101011011;
29551let addrMode = PostInc;
29552let accessSize = HVXVectorAccess;
29553let isCVI = 1;
29554let isHVXALU = 1;
29555let isNonTemporal = 1;
29556let mayStore = 1;
29557let BaseOpcode = "V6_vS32b_ppu";
29558let isNVStorable = 1;
29559let isPredicable = 1;
29560let DecoderNamespace = "EXT_mmvec";
29561let Constraints = "$Rx32 = $Rx32in";
29562}
29563def V6_vS32b_nt_pred_ai : HInst<
29564(outs),
29565(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29566"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29567tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29568let Inst{7-5} = 0b000;
29569let Inst{31-21} = 0b00101000111;
29570let isPredicated = 1;
29571let addrMode = BaseImmOffset;
29572let accessSize = HVXVectorAccess;
29573let isCVI = 1;
29574let isHVXALU = 1;
29575let isNonTemporal = 1;
29576let mayStore = 1;
29577let BaseOpcode = "V6_vS32b_ai";
29578let isNVStorable = 1;
29579let DecoderNamespace = "EXT_mmvec";
29580}
29581def V6_vS32b_nt_pred_pi : HInst<
29582(outs IntRegs:$Rx32),
29583(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29584"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29585tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29586let Inst{7-5} = 0b000;
29587let Inst{13-13} = 0b0;
29588let Inst{31-21} = 0b00101001111;
29589let isPredicated = 1;
29590let addrMode = PostInc;
29591let accessSize = HVXVectorAccess;
29592let isCVI = 1;
29593let isHVXALU = 1;
29594let isNonTemporal = 1;
29595let mayStore = 1;
29596let BaseOpcode = "V6_vS32b_pi";
29597let isNVStorable = 1;
29598let DecoderNamespace = "EXT_mmvec";
29599let Constraints = "$Rx32 = $Rx32in";
29600}
29601def V6_vS32b_nt_pred_ppu : HInst<
29602(outs IntRegs:$Rx32),
29603(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29604"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29605tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29606let Inst{10-5} = 0b000000;
29607let Inst{31-21} = 0b00101011111;
29608let isPredicated = 1;
29609let addrMode = PostInc;
29610let accessSize = HVXVectorAccess;
29611let isCVI = 1;
29612let isHVXALU = 1;
29613let isNonTemporal = 1;
29614let mayStore = 1;
29615let BaseOpcode = "V6_vS32b_ppu";
29616let isNVStorable = 1;
29617let DecoderNamespace = "EXT_mmvec";
29618let Constraints = "$Rx32 = $Rx32in";
29619}
29620def V6_vS32b_nt_qpred_ai : HInst<
29621(outs),
29622(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29623"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29624tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29625let Inst{7-5} = 0b000;
29626let Inst{31-21} = 0b00101000110;
29627let addrMode = BaseImmOffset;
29628let accessSize = HVXVectorAccess;
29629let isCVI = 1;
29630let isHVXALU = 1;
29631let isNonTemporal = 1;
29632let mayStore = 1;
29633let DecoderNamespace = "EXT_mmvec";
29634}
29635def V6_vS32b_nt_qpred_pi : HInst<
29636(outs IntRegs:$Rx32),
29637(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29638"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29639tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29640let Inst{7-5} = 0b000;
29641let Inst{13-13} = 0b0;
29642let Inst{31-21} = 0b00101001110;
29643let addrMode = PostInc;
29644let accessSize = HVXVectorAccess;
29645let isCVI = 1;
29646let isHVXALU = 1;
29647let isNonTemporal = 1;
29648let mayStore = 1;
29649let DecoderNamespace = "EXT_mmvec";
29650let Constraints = "$Rx32 = $Rx32in";
29651}
29652def V6_vS32b_nt_qpred_ppu : HInst<
29653(outs IntRegs:$Rx32),
29654(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29655"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29656tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29657let Inst{10-5} = 0b000000;
29658let Inst{31-21} = 0b00101011110;
29659let addrMode = PostInc;
29660let accessSize = HVXVectorAccess;
29661let isCVI = 1;
29662let isHVXALU = 1;
29663let isNonTemporal = 1;
29664let mayStore = 1;
29665let DecoderNamespace = "EXT_mmvec";
29666let Constraints = "$Rx32 = $Rx32in";
29667}
29668def V6_vS32b_pi : HInst<
29669(outs IntRegs:$Rx32),
29670(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29671"vmem($Rx32++#$Ii) = $Vs32",
29672tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29673let Inst{7-5} = 0b000;
29674let Inst{13-11} = 0b000;
29675let Inst{31-21} = 0b00101001001;
29676let addrMode = PostInc;
29677let accessSize = HVXVectorAccess;
29678let isCVI = 1;
29679let isHVXALU = 1;
29680let mayStore = 1;
29681let BaseOpcode = "V6_vS32b_pi";
29682let CextOpcode = "V6_vS32b";
29683let isNVStorable = 1;
29684let isPredicable = 1;
29685let DecoderNamespace = "EXT_mmvec";
29686let Constraints = "$Rx32 = $Rx32in";
29687}
29688def V6_vS32b_ppu : HInst<
29689(outs IntRegs:$Rx32),
29690(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29691"vmem($Rx32++$Mu2) = $Vs32",
29692tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29693let Inst{12-5} = 0b00000000;
29694let Inst{31-21} = 0b00101011001;
29695let addrMode = PostInc;
29696let accessSize = HVXVectorAccess;
29697let isCVI = 1;
29698let isHVXALU = 1;
29699let mayStore = 1;
29700let BaseOpcode = "V6_vS32b_ppu";
29701let isNVStorable = 1;
29702let isPredicable = 1;
29703let DecoderNamespace = "EXT_mmvec";
29704let Constraints = "$Rx32 = $Rx32in";
29705}
29706def V6_vS32b_pred_ai : HInst<
29707(outs),
29708(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29709"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
29710tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29711let Inst{7-5} = 0b000;
29712let Inst{31-21} = 0b00101000101;
29713let isPredicated = 1;
29714let addrMode = BaseImmOffset;
29715let accessSize = HVXVectorAccess;
29716let isCVI = 1;
29717let isHVXALU = 1;
29718let mayStore = 1;
29719let BaseOpcode = "V6_vS32b_ai";
29720let isNVStorable = 1;
29721let DecoderNamespace = "EXT_mmvec";
29722}
29723def V6_vS32b_pred_pi : HInst<
29724(outs IntRegs:$Rx32),
29725(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29726"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
29727tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29728let Inst{7-5} = 0b000;
29729let Inst{13-13} = 0b0;
29730let Inst{31-21} = 0b00101001101;
29731let isPredicated = 1;
29732let addrMode = PostInc;
29733let accessSize = HVXVectorAccess;
29734let isCVI = 1;
29735let isHVXALU = 1;
29736let mayStore = 1;
29737let BaseOpcode = "V6_vS32b_pi";
29738let isNVStorable = 1;
29739let DecoderNamespace = "EXT_mmvec";
29740let Constraints = "$Rx32 = $Rx32in";
29741}
29742def V6_vS32b_pred_ppu : HInst<
29743(outs IntRegs:$Rx32),
29744(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29745"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
29746tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29747let Inst{10-5} = 0b000000;
29748let Inst{31-21} = 0b00101011101;
29749let isPredicated = 1;
29750let addrMode = PostInc;
29751let accessSize = HVXVectorAccess;
29752let isCVI = 1;
29753let isHVXALU = 1;
29754let mayStore = 1;
29755let BaseOpcode = "V6_vS32b_ppu";
29756let isNVStorable = 1;
29757let DecoderNamespace = "EXT_mmvec";
29758let Constraints = "$Rx32 = $Rx32in";
29759}
29760def V6_vS32b_qpred_ai : HInst<
29761(outs),
29762(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29763"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
29764tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29765let Inst{7-5} = 0b000;
29766let Inst{31-21} = 0b00101000100;
29767let addrMode = BaseImmOffset;
29768let accessSize = HVXVectorAccess;
29769let isCVI = 1;
29770let isHVXALU = 1;
29771let mayStore = 1;
29772let DecoderNamespace = "EXT_mmvec";
29773}
29774def V6_vS32b_qpred_pi : HInst<
29775(outs IntRegs:$Rx32),
29776(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29777"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
29778tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29779let Inst{7-5} = 0b000;
29780let Inst{13-13} = 0b0;
29781let Inst{31-21} = 0b00101001100;
29782let addrMode = PostInc;
29783let accessSize = HVXVectorAccess;
29784let isCVI = 1;
29785let isHVXALU = 1;
29786let mayStore = 1;
29787let DecoderNamespace = "EXT_mmvec";
29788let Constraints = "$Rx32 = $Rx32in";
29789}
29790def V6_vS32b_qpred_ppu : HInst<
29791(outs IntRegs:$Rx32),
29792(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29793"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
29794tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29795let Inst{10-5} = 0b000000;
29796let Inst{31-21} = 0b00101011100;
29797let addrMode = PostInc;
29798let accessSize = HVXVectorAccess;
29799let isCVI = 1;
29800let isHVXALU = 1;
29801let mayStore = 1;
29802let DecoderNamespace = "EXT_mmvec";
29803let Constraints = "$Rx32 = $Rx32in";
29804}
29805def V6_vS32b_srls_ai : HInst<
29806(outs),
29807(ins IntRegs:$Rt32, s4_0Imm:$Ii),
29808"vmem($Rt32+#$Ii):scatter_release",
29809tc_3ce09744, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
29810let Inst{7-0} = 0b00101000;
29811let Inst{12-11} = 0b00;
29812let Inst{31-21} = 0b00101000001;
29813let addrMode = BaseImmOffset;
29814let accessSize = HVXVectorAccess;
29815let isCVI = 1;
29816let CVINew = 1;
29817let mayStore = 1;
29818let DecoderNamespace = "EXT_mmvec";
29819}
29820def V6_vS32b_srls_pi : HInst<
29821(outs IntRegs:$Rx32),
29822(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
29823"vmem($Rx32++#$Ii):scatter_release",
29824tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
29825let Inst{7-0} = 0b00101000;
29826let Inst{13-11} = 0b000;
29827let Inst{31-21} = 0b00101001001;
29828let addrMode = PostInc;
29829let accessSize = HVXVectorAccess;
29830let isCVI = 1;
29831let CVINew = 1;
29832let mayStore = 1;
29833let DecoderNamespace = "EXT_mmvec";
29834let Constraints = "$Rx32 = $Rx32in";
29835}
29836def V6_vS32b_srls_ppu : HInst<
29837(outs IntRegs:$Rx32),
29838(ins IntRegs:$Rx32in, ModRegs:$Mu2),
29839"vmem($Rx32++$Mu2):scatter_release",
29840tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
29841let Inst{12-0} = 0b0000000101000;
29842let Inst{31-21} = 0b00101011001;
29843let addrMode = PostInc;
29844let accessSize = HVXVectorAccess;
29845let isCVI = 1;
29846let CVINew = 1;
29847let mayStore = 1;
29848let DecoderNamespace = "EXT_mmvec";
29849let Constraints = "$Rx32 = $Rx32in";
29850}
29851def V6_vabs_hf : HInst<
29852(outs HvxVR:$Vd32),
29853(ins HvxVR:$Vu32),
29854"$Vd32.hf = vabs($Vu32.hf)",
29855tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
29856let Inst{7-5} = 0b100;
29857let Inst{13-13} = 0b1;
29858let Inst{31-16} = 0b0001111000000110;
29859let hasNewValue = 1;
29860let opNewValue = 0;
29861let isCVI = 1;
29862let DecoderNamespace = "EXT_mmvec";
29863}
29864def V6_vabs_sf : HInst<
29865(outs HvxVR:$Vd32),
29866(ins HvxVR:$Vu32),
29867"$Vd32.sf = vabs($Vu32.sf)",
29868tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
29869let Inst{7-5} = 0b101;
29870let Inst{13-13} = 0b1;
29871let Inst{31-16} = 0b0001111000000110;
29872let hasNewValue = 1;
29873let opNewValue = 0;
29874let isCVI = 1;
29875let DecoderNamespace = "EXT_mmvec";
29876}
29877def V6_vabsb : HInst<
29878(outs HvxVR:$Vd32),
29879(ins HvxVR:$Vu32),
29880"$Vd32.b = vabs($Vu32.b)",
29881tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29882let Inst{7-5} = 0b100;
29883let Inst{13-13} = 0b0;
29884let Inst{31-16} = 0b0001111000000001;
29885let hasNewValue = 1;
29886let opNewValue = 0;
29887let isCVI = 1;
29888let isHVXALU = 1;
29889let isHVXALU2SRC = 1;
29890let DecoderNamespace = "EXT_mmvec";
29891}
29892def V6_vabsb_alt : HInst<
29893(outs HvxVR:$Vd32),
29894(ins HvxVR:$Vu32),
29895"$Vd32 = vabsb($Vu32)",
29896PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29897let hasNewValue = 1;
29898let opNewValue = 0;
29899let isCVI = 1;
29900let isPseudo = 1;
29901let isCodeGenOnly = 1;
29902let DecoderNamespace = "EXT_mmvec";
29903}
29904def V6_vabsb_sat : HInst<
29905(outs HvxVR:$Vd32),
29906(ins HvxVR:$Vu32),
29907"$Vd32.b = vabs($Vu32.b):sat",
29908tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29909let Inst{7-5} = 0b101;
29910let Inst{13-13} = 0b0;
29911let Inst{31-16} = 0b0001111000000001;
29912let hasNewValue = 1;
29913let opNewValue = 0;
29914let isCVI = 1;
29915let isHVXALU = 1;
29916let isHVXALU2SRC = 1;
29917let DecoderNamespace = "EXT_mmvec";
29918}
29919def V6_vabsb_sat_alt : HInst<
29920(outs HvxVR:$Vd32),
29921(ins HvxVR:$Vu32),
29922"$Vd32 = vabsb($Vu32):sat",
29923PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29924let hasNewValue = 1;
29925let opNewValue = 0;
29926let isCVI = 1;
29927let isPseudo = 1;
29928let isCodeGenOnly = 1;
29929let DecoderNamespace = "EXT_mmvec";
29930}
29931def V6_vabsdiffh : HInst<
29932(outs HvxVR:$Vd32),
29933(ins HvxVR:$Vu32, HvxVR:$Vv32),
29934"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
29935tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29936let Inst{7-5} = 0b001;
29937let Inst{13-13} = 0b0;
29938let Inst{31-21} = 0b00011100110;
29939let hasNewValue = 1;
29940let opNewValue = 0;
29941let isCVI = 1;
29942let DecoderNamespace = "EXT_mmvec";
29943}
29944def V6_vabsdiffh_alt : HInst<
29945(outs HvxVR:$Vd32),
29946(ins HvxVR:$Vu32, HvxVR:$Vv32),
29947"$Vd32 = vabsdiffh($Vu32,$Vv32)",
29948PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29949let hasNewValue = 1;
29950let opNewValue = 0;
29951let isCVI = 1;
29952let isPseudo = 1;
29953let isCodeGenOnly = 1;
29954let DecoderNamespace = "EXT_mmvec";
29955}
29956def V6_vabsdiffub : HInst<
29957(outs HvxVR:$Vd32),
29958(ins HvxVR:$Vu32, HvxVR:$Vv32),
29959"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
29960tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29961let Inst{7-5} = 0b000;
29962let Inst{13-13} = 0b0;
29963let Inst{31-21} = 0b00011100110;
29964let hasNewValue = 1;
29965let opNewValue = 0;
29966let isCVI = 1;
29967let DecoderNamespace = "EXT_mmvec";
29968}
29969def V6_vabsdiffub_alt : HInst<
29970(outs HvxVR:$Vd32),
29971(ins HvxVR:$Vu32, HvxVR:$Vv32),
29972"$Vd32 = vabsdiffub($Vu32,$Vv32)",
29973PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29974let hasNewValue = 1;
29975let opNewValue = 0;
29976let isCVI = 1;
29977let isPseudo = 1;
29978let isCodeGenOnly = 1;
29979let DecoderNamespace = "EXT_mmvec";
29980}
29981def V6_vabsdiffuh : HInst<
29982(outs HvxVR:$Vd32),
29983(ins HvxVR:$Vu32, HvxVR:$Vv32),
29984"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
29985tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29986let Inst{7-5} = 0b010;
29987let Inst{13-13} = 0b0;
29988let Inst{31-21} = 0b00011100110;
29989let hasNewValue = 1;
29990let opNewValue = 0;
29991let isCVI = 1;
29992let DecoderNamespace = "EXT_mmvec";
29993}
29994def V6_vabsdiffuh_alt : HInst<
29995(outs HvxVR:$Vd32),
29996(ins HvxVR:$Vu32, HvxVR:$Vv32),
29997"$Vd32 = vabsdiffuh($Vu32,$Vv32)",
29998PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29999let hasNewValue = 1;
30000let opNewValue = 0;
30001let isCVI = 1;
30002let isPseudo = 1;
30003let isCodeGenOnly = 1;
30004let DecoderNamespace = "EXT_mmvec";
30005}
30006def V6_vabsdiffw : HInst<
30007(outs HvxVR:$Vd32),
30008(ins HvxVR:$Vu32, HvxVR:$Vv32),
30009"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
30010tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
30011let Inst{7-5} = 0b011;
30012let Inst{13-13} = 0b0;
30013let Inst{31-21} = 0b00011100110;
30014let hasNewValue = 1;
30015let opNewValue = 0;
30016let isCVI = 1;
30017let DecoderNamespace = "EXT_mmvec";
30018}
30019def V6_vabsdiffw_alt : HInst<
30020(outs HvxVR:$Vd32),
30021(ins HvxVR:$Vu32, HvxVR:$Vv32),
30022"$Vd32 = vabsdiffw($Vu32,$Vv32)",
30023PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30024let hasNewValue = 1;
30025let opNewValue = 0;
30026let isCVI = 1;
30027let isPseudo = 1;
30028let isCodeGenOnly = 1;
30029let DecoderNamespace = "EXT_mmvec";
30030}
30031def V6_vabsh : HInst<
30032(outs HvxVR:$Vd32),
30033(ins HvxVR:$Vu32),
30034"$Vd32.h = vabs($Vu32.h)",
30035tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30036let Inst{7-5} = 0b000;
30037let Inst{13-13} = 0b0;
30038let Inst{31-16} = 0b0001111000000000;
30039let hasNewValue = 1;
30040let opNewValue = 0;
30041let isCVI = 1;
30042let isHVXALU = 1;
30043let isHVXALU2SRC = 1;
30044let DecoderNamespace = "EXT_mmvec";
30045}
30046def V6_vabsh_alt : HInst<
30047(outs HvxVR:$Vd32),
30048(ins HvxVR:$Vu32),
30049"$Vd32 = vabsh($Vu32)",
30050PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30051let hasNewValue = 1;
30052let opNewValue = 0;
30053let isCVI = 1;
30054let isPseudo = 1;
30055let isCodeGenOnly = 1;
30056let DecoderNamespace = "EXT_mmvec";
30057}
30058def V6_vabsh_sat : HInst<
30059(outs HvxVR:$Vd32),
30060(ins HvxVR:$Vu32),
30061"$Vd32.h = vabs($Vu32.h):sat",
30062tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30063let Inst{7-5} = 0b001;
30064let Inst{13-13} = 0b0;
30065let Inst{31-16} = 0b0001111000000000;
30066let hasNewValue = 1;
30067let opNewValue = 0;
30068let isCVI = 1;
30069let isHVXALU = 1;
30070let isHVXALU2SRC = 1;
30071let DecoderNamespace = "EXT_mmvec";
30072}
30073def V6_vabsh_sat_alt : HInst<
30074(outs HvxVR:$Vd32),
30075(ins HvxVR:$Vu32),
30076"$Vd32 = vabsh($Vu32):sat",
30077PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30078let hasNewValue = 1;
30079let opNewValue = 0;
30080let isCVI = 1;
30081let isPseudo = 1;
30082let isCodeGenOnly = 1;
30083let DecoderNamespace = "EXT_mmvec";
30084}
30085def V6_vabsub_alt : HInst<
30086(outs HvxVR:$Vd32),
30087(ins HvxVR:$Vu32),
30088"$Vd32.ub = vabs($Vu32.b)",
30089tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
30090let hasNewValue = 1;
30091let opNewValue = 0;
30092let isCVI = 1;
30093let isPseudo = 1;
30094let isCodeGenOnly = 1;
30095let DecoderNamespace = "EXT_mmvec";
30096}
30097def V6_vabsuh_alt : HInst<
30098(outs HvxVR:$Vd32),
30099(ins HvxVR:$Vu32),
30100"$Vd32.uh = vabs($Vu32.h)",
30101tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
30102let hasNewValue = 1;
30103let opNewValue = 0;
30104let isCVI = 1;
30105let isPseudo = 1;
30106let isCodeGenOnly = 1;
30107let DecoderNamespace = "EXT_mmvec";
30108}
30109def V6_vabsuw_alt : HInst<
30110(outs HvxVR:$Vd32),
30111(ins HvxVR:$Vu32),
30112"$Vd32.uw = vabs($Vu32.w)",
30113tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
30114let hasNewValue = 1;
30115let opNewValue = 0;
30116let isCVI = 1;
30117let isPseudo = 1;
30118let isCodeGenOnly = 1;
30119let DecoderNamespace = "EXT_mmvec";
30120}
30121def V6_vabsw : HInst<
30122(outs HvxVR:$Vd32),
30123(ins HvxVR:$Vu32),
30124"$Vd32.w = vabs($Vu32.w)",
30125tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30126let Inst{7-5} = 0b010;
30127let Inst{13-13} = 0b0;
30128let Inst{31-16} = 0b0001111000000000;
30129let hasNewValue = 1;
30130let opNewValue = 0;
30131let isCVI = 1;
30132let isHVXALU = 1;
30133let isHVXALU2SRC = 1;
30134let DecoderNamespace = "EXT_mmvec";
30135}
30136def V6_vabsw_alt : HInst<
30137(outs HvxVR:$Vd32),
30138(ins HvxVR:$Vu32),
30139"$Vd32 = vabsw($Vu32)",
30140PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30141let hasNewValue = 1;
30142let opNewValue = 0;
30143let isCVI = 1;
30144let isPseudo = 1;
30145let isCodeGenOnly = 1;
30146let DecoderNamespace = "EXT_mmvec";
30147}
30148def V6_vabsw_sat : HInst<
30149(outs HvxVR:$Vd32),
30150(ins HvxVR:$Vu32),
30151"$Vd32.w = vabs($Vu32.w):sat",
30152tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30153let Inst{7-5} = 0b011;
30154let Inst{13-13} = 0b0;
30155let Inst{31-16} = 0b0001111000000000;
30156let hasNewValue = 1;
30157let opNewValue = 0;
30158let isCVI = 1;
30159let isHVXALU = 1;
30160let isHVXALU2SRC = 1;
30161let DecoderNamespace = "EXT_mmvec";
30162}
30163def V6_vabsw_sat_alt : HInst<
30164(outs HvxVR:$Vd32),
30165(ins HvxVR:$Vu32),
30166"$Vd32 = vabsw($Vu32):sat",
30167PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30168let hasNewValue = 1;
30169let opNewValue = 0;
30170let isCVI = 1;
30171let isPseudo = 1;
30172let isCodeGenOnly = 1;
30173let DecoderNamespace = "EXT_mmvec";
30174}
30175def V6_vadd_hf : HInst<
30176(outs HvxVR:$Vd32),
30177(ins HvxVR:$Vu32, HvxVR:$Vv32),
30178"$Vd32.qf16 = vadd($Vu32.hf,$Vv32.hf)",
30179tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30180let Inst{7-5} = 0b011;
30181let Inst{13-13} = 0b1;
30182let Inst{31-21} = 0b00011111011;
30183let hasNewValue = 1;
30184let opNewValue = 0;
30185let isCVI = 1;
30186let DecoderNamespace = "EXT_mmvec";
30187}
30188def V6_vadd_hf_hf : HInst<
30189(outs HvxVR:$Vd32),
30190(ins HvxVR:$Vu32, HvxVR:$Vv32),
30191"$Vd32.hf = vadd($Vu32.hf,$Vv32.hf)",
30192tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30193let Inst{7-5} = 0b111;
30194let Inst{13-13} = 0b1;
30195let Inst{31-21} = 0b00011111101;
30196let hasNewValue = 1;
30197let opNewValue = 0;
30198let isCVI = 1;
30199let DecoderNamespace = "EXT_mmvec";
30200}
30201def V6_vadd_qf16 : HInst<
30202(outs HvxVR:$Vd32),
30203(ins HvxVR:$Vu32, HvxVR:$Vv32),
30204"$Vd32.qf16 = vadd($Vu32.qf16,$Vv32.qf16)",
30205tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30206let Inst{7-5} = 0b010;
30207let Inst{13-13} = 0b1;
30208let Inst{31-21} = 0b00011111011;
30209let hasNewValue = 1;
30210let opNewValue = 0;
30211let isCVI = 1;
30212let DecoderNamespace = "EXT_mmvec";
30213}
30214def V6_vadd_qf16_mix : HInst<
30215(outs HvxVR:$Vd32),
30216(ins HvxVR:$Vu32, HvxVR:$Vv32),
30217"$Vd32.qf16 = vadd($Vu32.qf16,$Vv32.hf)",
30218tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30219let Inst{7-5} = 0b100;
30220let Inst{13-13} = 0b1;
30221let Inst{31-21} = 0b00011111011;
30222let hasNewValue = 1;
30223let opNewValue = 0;
30224let isCVI = 1;
30225let DecoderNamespace = "EXT_mmvec";
30226}
30227def V6_vadd_qf32 : HInst<
30228(outs HvxVR:$Vd32),
30229(ins HvxVR:$Vu32, HvxVR:$Vv32),
30230"$Vd32.qf32 = vadd($Vu32.qf32,$Vv32.qf32)",
30231tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30232let Inst{7-5} = 0b000;
30233let Inst{13-13} = 0b1;
30234let Inst{31-21} = 0b00011111101;
30235let hasNewValue = 1;
30236let opNewValue = 0;
30237let isCVI = 1;
30238let DecoderNamespace = "EXT_mmvec";
30239}
30240def V6_vadd_qf32_mix : HInst<
30241(outs HvxVR:$Vd32),
30242(ins HvxVR:$Vu32, HvxVR:$Vv32),
30243"$Vd32.qf32 = vadd($Vu32.qf32,$Vv32.sf)",
30244tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30245let Inst{7-5} = 0b010;
30246let Inst{13-13} = 0b1;
30247let Inst{31-21} = 0b00011111101;
30248let hasNewValue = 1;
30249let opNewValue = 0;
30250let isCVI = 1;
30251let DecoderNamespace = "EXT_mmvec";
30252}
30253def V6_vadd_sf : HInst<
30254(outs HvxVR:$Vd32),
30255(ins HvxVR:$Vu32, HvxVR:$Vv32),
30256"$Vd32.qf32 = vadd($Vu32.sf,$Vv32.sf)",
30257tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30258let Inst{7-5} = 0b001;
30259let Inst{13-13} = 0b1;
30260let Inst{31-21} = 0b00011111101;
30261let hasNewValue = 1;
30262let opNewValue = 0;
30263let isCVI = 1;
30264let DecoderNamespace = "EXT_mmvec";
30265}
30266def V6_vadd_sf_bf : HInst<
30267(outs HvxWR:$Vdd32),
30268(ins HvxVR:$Vu32, HvxVR:$Vv32),
30269"$Vdd32.sf = vadd($Vu32.bf,$Vv32.bf)",
30270tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV73,UseHVXIEEEFP]> {
30271let Inst{7-5} = 0b110;
30272let Inst{13-13} = 0b1;
30273let Inst{31-21} = 0b00011101010;
30274let hasNewValue = 1;
30275let opNewValue = 0;
30276let isCVI = 1;
30277let DecoderNamespace = "EXT_mmvec";
30278}
30279def V6_vadd_sf_hf : HInst<
30280(outs HvxWR:$Vdd32),
30281(ins HvxVR:$Vu32, HvxVR:$Vv32),
30282"$Vdd32.sf = vadd($Vu32.hf,$Vv32.hf)",
30283tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30284let Inst{7-5} = 0b100;
30285let Inst{13-13} = 0b1;
30286let Inst{31-21} = 0b00011111100;
30287let hasNewValue = 1;
30288let opNewValue = 0;
30289let isCVI = 1;
30290let DecoderNamespace = "EXT_mmvec";
30291}
30292def V6_vadd_sf_sf : HInst<
30293(outs HvxVR:$Vd32),
30294(ins HvxVR:$Vu32, HvxVR:$Vv32),
30295"$Vd32.sf = vadd($Vu32.sf,$Vv32.sf)",
30296tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30297let Inst{7-5} = 0b110;
30298let Inst{13-13} = 0b1;
30299let Inst{31-21} = 0b00011111100;
30300let hasNewValue = 1;
30301let opNewValue = 0;
30302let isCVI = 1;
30303let DecoderNamespace = "EXT_mmvec";
30304}
30305def V6_vaddb : HInst<
30306(outs HvxVR:$Vd32),
30307(ins HvxVR:$Vu32, HvxVR:$Vv32),
30308"$Vd32.b = vadd($Vu32.b,$Vv32.b)",
30309tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30310let Inst{7-5} = 0b110;
30311let Inst{13-13} = 0b0;
30312let Inst{31-21} = 0b00011111101;
30313let hasNewValue = 1;
30314let opNewValue = 0;
30315let isCVI = 1;
30316let isHVXALU = 1;
30317let isHVXALU2SRC = 1;
30318let DecoderNamespace = "EXT_mmvec";
30319}
30320def V6_vaddb_alt : HInst<
30321(outs HvxVR:$Vd32),
30322(ins HvxVR:$Vu32, HvxVR:$Vv32),
30323"$Vd32 = vaddb($Vu32,$Vv32)",
30324PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30325let hasNewValue = 1;
30326let opNewValue = 0;
30327let isCVI = 1;
30328let isPseudo = 1;
30329let isCodeGenOnly = 1;
30330let DecoderNamespace = "EXT_mmvec";
30331}
30332def V6_vaddb_dv : HInst<
30333(outs HvxWR:$Vdd32),
30334(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30335"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
30336tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30337let Inst{7-5} = 0b100;
30338let Inst{13-13} = 0b0;
30339let Inst{31-21} = 0b00011100011;
30340let hasNewValue = 1;
30341let opNewValue = 0;
30342let isCVI = 1;
30343let DecoderNamespace = "EXT_mmvec";
30344}
30345def V6_vaddb_dv_alt : HInst<
30346(outs HvxWR:$Vdd32),
30347(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30348"$Vdd32 = vaddb($Vuu32,$Vvv32)",
30349PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30350let hasNewValue = 1;
30351let opNewValue = 0;
30352let isCVI = 1;
30353let isPseudo = 1;
30354let isCodeGenOnly = 1;
30355let DecoderNamespace = "EXT_mmvec";
30356}
30357def V6_vaddbnq : HInst<
30358(outs HvxVR:$Vx32),
30359(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30360"if (!$Qv4) $Vx32.b += $Vu32.b",
30361tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30362let Inst{7-5} = 0b011;
30363let Inst{13-13} = 0b1;
30364let Inst{21-16} = 0b000001;
30365let Inst{31-24} = 0b00011110;
30366let hasNewValue = 1;
30367let opNewValue = 0;
30368let isAccumulator = 1;
30369let isCVI = 1;
30370let isHVXALU = 1;
30371let isHVXALU2SRC = 1;
30372let DecoderNamespace = "EXT_mmvec";
30373let Constraints = "$Vx32 = $Vx32in";
30374}
30375def V6_vaddbnq_alt : HInst<
30376(outs HvxVR:$Vx32),
30377(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30378"if (!$Qv4.b) $Vx32.b += $Vu32.b",
30379PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30380let hasNewValue = 1;
30381let opNewValue = 0;
30382let isAccumulator = 1;
30383let isCVI = 1;
30384let isPseudo = 1;
30385let isCodeGenOnly = 1;
30386let DecoderNamespace = "EXT_mmvec";
30387let Constraints = "$Vx32 = $Vx32in";
30388}
30389def V6_vaddbq : HInst<
30390(outs HvxVR:$Vx32),
30391(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30392"if ($Qv4) $Vx32.b += $Vu32.b",
30393tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30394let Inst{7-5} = 0b000;
30395let Inst{13-13} = 0b1;
30396let Inst{21-16} = 0b000001;
30397let Inst{31-24} = 0b00011110;
30398let hasNewValue = 1;
30399let opNewValue = 0;
30400let isAccumulator = 1;
30401let isCVI = 1;
30402let isHVXALU = 1;
30403let isHVXALU2SRC = 1;
30404let DecoderNamespace = "EXT_mmvec";
30405let Constraints = "$Vx32 = $Vx32in";
30406}
30407def V6_vaddbq_alt : HInst<
30408(outs HvxVR:$Vx32),
30409(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30410"if ($Qv4.b) $Vx32.b += $Vu32.b",
30411PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30412let hasNewValue = 1;
30413let opNewValue = 0;
30414let isAccumulator = 1;
30415let isCVI = 1;
30416let isPseudo = 1;
30417let isCodeGenOnly = 1;
30418let DecoderNamespace = "EXT_mmvec";
30419let Constraints = "$Vx32 = $Vx32in";
30420}
30421def V6_vaddbsat : HInst<
30422(outs HvxVR:$Vd32),
30423(ins HvxVR:$Vu32, HvxVR:$Vv32),
30424"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
30425tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30426let Inst{7-5} = 0b000;
30427let Inst{13-13} = 0b0;
30428let Inst{31-21} = 0b00011111000;
30429let hasNewValue = 1;
30430let opNewValue = 0;
30431let isCVI = 1;
30432let isHVXALU = 1;
30433let isHVXALU2SRC = 1;
30434let DecoderNamespace = "EXT_mmvec";
30435}
30436def V6_vaddbsat_alt : HInst<
30437(outs HvxVR:$Vd32),
30438(ins HvxVR:$Vu32, HvxVR:$Vv32),
30439"$Vd32 = vaddb($Vu32,$Vv32):sat",
30440PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30441let hasNewValue = 1;
30442let opNewValue = 0;
30443let isCVI = 1;
30444let isPseudo = 1;
30445let isCodeGenOnly = 1;
30446let DecoderNamespace = "EXT_mmvec";
30447}
30448def V6_vaddbsat_dv : HInst<
30449(outs HvxWR:$Vdd32),
30450(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30451"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
30452tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
30453let Inst{7-5} = 0b000;
30454let Inst{13-13} = 0b0;
30455let Inst{31-21} = 0b00011110101;
30456let hasNewValue = 1;
30457let opNewValue = 0;
30458let isCVI = 1;
30459let DecoderNamespace = "EXT_mmvec";
30460}
30461def V6_vaddbsat_dv_alt : HInst<
30462(outs HvxWR:$Vdd32),
30463(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30464"$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
30465PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30466let hasNewValue = 1;
30467let opNewValue = 0;
30468let isCVI = 1;
30469let isPseudo = 1;
30470let isCodeGenOnly = 1;
30471let DecoderNamespace = "EXT_mmvec";
30472}
30473def V6_vaddcarry : HInst<
30474(outs HvxVR:$Vd32, HvxQR:$Qx4),
30475(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
30476"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
30477tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
30478let Inst{7-7} = 0b0;
30479let Inst{13-13} = 0b1;
30480let Inst{31-21} = 0b00011100101;
30481let hasNewValue = 1;
30482let opNewValue = 0;
30483let isCVI = 1;
30484let isHVXALU = 1;
30485let isHVXALU2SRC = 1;
30486let DecoderNamespace = "EXT_mmvec";
30487let Constraints = "$Qx4 = $Qx4in";
30488}
30489def V6_vaddcarryo : HInst<
30490(outs HvxVR:$Vd32, HvxQR:$Qe4),
30491(ins HvxVR:$Vu32, HvxVR:$Vv32),
30492"$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry",
30493tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
30494let Inst{7-7} = 0b0;
30495let Inst{13-13} = 0b1;
30496let Inst{31-21} = 0b00011101101;
30497let hasNewValue = 1;
30498let opNewValue = 0;
30499let isCVI = 1;
30500let isHVXALU = 1;
30501let isHVXALU2SRC = 1;
30502let DecoderNamespace = "EXT_mmvec";
30503}
30504def V6_vaddcarrysat : HInst<
30505(outs HvxVR:$Vd32),
30506(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qs4),
30507"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qs4):carry:sat",
30508tc_257f6f7c, TypeCVI_VA>, Enc_e0820b, Requires<[UseHVXV66]> {
30509let Inst{7-7} = 0b0;
30510let Inst{13-13} = 0b1;
30511let Inst{31-21} = 0b00011101100;
30512let hasNewValue = 1;
30513let opNewValue = 0;
30514let isCVI = 1;
30515let isHVXALU = 1;
30516let isHVXALU2SRC = 1;
30517let DecoderNamespace = "EXT_mmvec";
30518}
30519def V6_vaddclbh : HInst<
30520(outs HvxVR:$Vd32),
30521(ins HvxVR:$Vu32, HvxVR:$Vv32),
30522"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
30523tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30524let Inst{7-5} = 0b000;
30525let Inst{13-13} = 0b1;
30526let Inst{31-21} = 0b00011111000;
30527let hasNewValue = 1;
30528let opNewValue = 0;
30529let isCVI = 1;
30530let DecoderNamespace = "EXT_mmvec";
30531}
30532def V6_vaddclbw : HInst<
30533(outs HvxVR:$Vd32),
30534(ins HvxVR:$Vu32, HvxVR:$Vv32),
30535"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
30536tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30537let Inst{7-5} = 0b001;
30538let Inst{13-13} = 0b1;
30539let Inst{31-21} = 0b00011111000;
30540let hasNewValue = 1;
30541let opNewValue = 0;
30542let isCVI = 1;
30543let DecoderNamespace = "EXT_mmvec";
30544}
30545def V6_vaddh : HInst<
30546(outs HvxVR:$Vd32),
30547(ins HvxVR:$Vu32, HvxVR:$Vv32),
30548"$Vd32.h = vadd($Vu32.h,$Vv32.h)",
30549tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30550let Inst{7-5} = 0b111;
30551let Inst{13-13} = 0b0;
30552let Inst{31-21} = 0b00011111101;
30553let hasNewValue = 1;
30554let opNewValue = 0;
30555let isCVI = 1;
30556let isHVXALU = 1;
30557let isHVXALU2SRC = 1;
30558let DecoderNamespace = "EXT_mmvec";
30559}
30560def V6_vaddh_alt : HInst<
30561(outs HvxVR:$Vd32),
30562(ins HvxVR:$Vu32, HvxVR:$Vv32),
30563"$Vd32 = vaddh($Vu32,$Vv32)",
30564PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30565let hasNewValue = 1;
30566let opNewValue = 0;
30567let isCVI = 1;
30568let isPseudo = 1;
30569let isCodeGenOnly = 1;
30570let DecoderNamespace = "EXT_mmvec";
30571}
30572def V6_vaddh_dv : HInst<
30573(outs HvxWR:$Vdd32),
30574(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30575"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
30576tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30577let Inst{7-5} = 0b101;
30578let Inst{13-13} = 0b0;
30579let Inst{31-21} = 0b00011100011;
30580let hasNewValue = 1;
30581let opNewValue = 0;
30582let isCVI = 1;
30583let DecoderNamespace = "EXT_mmvec";
30584}
30585def V6_vaddh_dv_alt : HInst<
30586(outs HvxWR:$Vdd32),
30587(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30588"$Vdd32 = vaddh($Vuu32,$Vvv32)",
30589PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30590let hasNewValue = 1;
30591let opNewValue = 0;
30592let isCVI = 1;
30593let isPseudo = 1;
30594let isCodeGenOnly = 1;
30595let DecoderNamespace = "EXT_mmvec";
30596}
30597def V6_vaddhnq : HInst<
30598(outs HvxVR:$Vx32),
30599(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30600"if (!$Qv4) $Vx32.h += $Vu32.h",
30601tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30602let Inst{7-5} = 0b100;
30603let Inst{13-13} = 0b1;
30604let Inst{21-16} = 0b000001;
30605let Inst{31-24} = 0b00011110;
30606let hasNewValue = 1;
30607let opNewValue = 0;
30608let isAccumulator = 1;
30609let isCVI = 1;
30610let isHVXALU = 1;
30611let isHVXALU2SRC = 1;
30612let DecoderNamespace = "EXT_mmvec";
30613let Constraints = "$Vx32 = $Vx32in";
30614}
30615def V6_vaddhnq_alt : HInst<
30616(outs HvxVR:$Vx32),
30617(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30618"if (!$Qv4.h) $Vx32.h += $Vu32.h",
30619PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30620let hasNewValue = 1;
30621let opNewValue = 0;
30622let isAccumulator = 1;
30623let isCVI = 1;
30624let isPseudo = 1;
30625let isCodeGenOnly = 1;
30626let DecoderNamespace = "EXT_mmvec";
30627let Constraints = "$Vx32 = $Vx32in";
30628}
30629def V6_vaddhq : HInst<
30630(outs HvxVR:$Vx32),
30631(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30632"if ($Qv4) $Vx32.h += $Vu32.h",
30633tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30634let Inst{7-5} = 0b001;
30635let Inst{13-13} = 0b1;
30636let Inst{21-16} = 0b000001;
30637let Inst{31-24} = 0b00011110;
30638let hasNewValue = 1;
30639let opNewValue = 0;
30640let isAccumulator = 1;
30641let isCVI = 1;
30642let isHVXALU = 1;
30643let isHVXALU2SRC = 1;
30644let DecoderNamespace = "EXT_mmvec";
30645let Constraints = "$Vx32 = $Vx32in";
30646}
30647def V6_vaddhq_alt : HInst<
30648(outs HvxVR:$Vx32),
30649(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30650"if ($Qv4.h) $Vx32.h += $Vu32.h",
30651PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30652let hasNewValue = 1;
30653let opNewValue = 0;
30654let isAccumulator = 1;
30655let isCVI = 1;
30656let isPseudo = 1;
30657let isCodeGenOnly = 1;
30658let DecoderNamespace = "EXT_mmvec";
30659let Constraints = "$Vx32 = $Vx32in";
30660}
30661def V6_vaddhsat : HInst<
30662(outs HvxVR:$Vd32),
30663(ins HvxVR:$Vu32, HvxVR:$Vv32),
30664"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
30665tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30666let Inst{7-5} = 0b011;
30667let Inst{13-13} = 0b0;
30668let Inst{31-21} = 0b00011100010;
30669let hasNewValue = 1;
30670let opNewValue = 0;
30671let isCVI = 1;
30672let isHVXALU = 1;
30673let isHVXALU2SRC = 1;
30674let DecoderNamespace = "EXT_mmvec";
30675}
30676def V6_vaddhsat_alt : HInst<
30677(outs HvxVR:$Vd32),
30678(ins HvxVR:$Vu32, HvxVR:$Vv32),
30679"$Vd32 = vaddh($Vu32,$Vv32):sat",
30680PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30681let hasNewValue = 1;
30682let opNewValue = 0;
30683let isCVI = 1;
30684let isPseudo = 1;
30685let isCodeGenOnly = 1;
30686let DecoderNamespace = "EXT_mmvec";
30687}
30688def V6_vaddhsat_dv : HInst<
30689(outs HvxWR:$Vdd32),
30690(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30691"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
30692tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30693let Inst{7-5} = 0b001;
30694let Inst{13-13} = 0b0;
30695let Inst{31-21} = 0b00011100100;
30696let hasNewValue = 1;
30697let opNewValue = 0;
30698let isCVI = 1;
30699let DecoderNamespace = "EXT_mmvec";
30700}
30701def V6_vaddhsat_dv_alt : HInst<
30702(outs HvxWR:$Vdd32),
30703(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30704"$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
30705PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30706let hasNewValue = 1;
30707let opNewValue = 0;
30708let isCVI = 1;
30709let isPseudo = 1;
30710let isCodeGenOnly = 1;
30711let DecoderNamespace = "EXT_mmvec";
30712}
30713def V6_vaddhw : HInst<
30714(outs HvxWR:$Vdd32),
30715(ins HvxVR:$Vu32, HvxVR:$Vv32),
30716"$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
30717tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30718let Inst{7-5} = 0b100;
30719let Inst{13-13} = 0b0;
30720let Inst{31-21} = 0b00011100101;
30721let hasNewValue = 1;
30722let opNewValue = 0;
30723let isCVI = 1;
30724let DecoderNamespace = "EXT_mmvec";
30725}
30726def V6_vaddhw_acc : HInst<
30727(outs HvxWR:$Vxx32),
30728(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30729"$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
30730tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30731let Inst{7-5} = 0b010;
30732let Inst{13-13} = 0b1;
30733let Inst{31-21} = 0b00011100001;
30734let hasNewValue = 1;
30735let opNewValue = 0;
30736let isAccumulator = 1;
30737let isCVI = 1;
30738let DecoderNamespace = "EXT_mmvec";
30739let Constraints = "$Vxx32 = $Vxx32in";
30740}
30741def V6_vaddhw_acc_alt : HInst<
30742(outs HvxWR:$Vxx32),
30743(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30744"$Vxx32 += vaddh($Vu32,$Vv32)",
30745PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30746let hasNewValue = 1;
30747let opNewValue = 0;
30748let isAccumulator = 1;
30749let isCVI = 1;
30750let isPseudo = 1;
30751let isCodeGenOnly = 1;
30752let DecoderNamespace = "EXT_mmvec";
30753let Constraints = "$Vxx32 = $Vxx32in";
30754}
30755def V6_vaddhw_alt : HInst<
30756(outs HvxWR:$Vdd32),
30757(ins HvxVR:$Vu32, HvxVR:$Vv32),
30758"$Vdd32 = vaddh($Vu32,$Vv32)",
30759PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30760let hasNewValue = 1;
30761let opNewValue = 0;
30762let isCVI = 1;
30763let isPseudo = 1;
30764let isCodeGenOnly = 1;
30765let DecoderNamespace = "EXT_mmvec";
30766}
30767def V6_vaddubh : HInst<
30768(outs HvxWR:$Vdd32),
30769(ins HvxVR:$Vu32, HvxVR:$Vv32),
30770"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
30771tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30772let Inst{7-5} = 0b010;
30773let Inst{13-13} = 0b0;
30774let Inst{31-21} = 0b00011100101;
30775let hasNewValue = 1;
30776let opNewValue = 0;
30777let isCVI = 1;
30778let DecoderNamespace = "EXT_mmvec";
30779}
30780def V6_vaddubh_acc : HInst<
30781(outs HvxWR:$Vxx32),
30782(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30783"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
30784tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30785let Inst{7-5} = 0b101;
30786let Inst{13-13} = 0b1;
30787let Inst{31-21} = 0b00011100010;
30788let hasNewValue = 1;
30789let opNewValue = 0;
30790let isAccumulator = 1;
30791let isCVI = 1;
30792let DecoderNamespace = "EXT_mmvec";
30793let Constraints = "$Vxx32 = $Vxx32in";
30794}
30795def V6_vaddubh_acc_alt : HInst<
30796(outs HvxWR:$Vxx32),
30797(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30798"$Vxx32 += vaddub($Vu32,$Vv32)",
30799PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30800let hasNewValue = 1;
30801let opNewValue = 0;
30802let isAccumulator = 1;
30803let isCVI = 1;
30804let isPseudo = 1;
30805let isCodeGenOnly = 1;
30806let DecoderNamespace = "EXT_mmvec";
30807let Constraints = "$Vxx32 = $Vxx32in";
30808}
30809def V6_vaddubh_alt : HInst<
30810(outs HvxWR:$Vdd32),
30811(ins HvxVR:$Vu32, HvxVR:$Vv32),
30812"$Vdd32 = vaddub($Vu32,$Vv32)",
30813PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30814let hasNewValue = 1;
30815let opNewValue = 0;
30816let isCVI = 1;
30817let isPseudo = 1;
30818let isCodeGenOnly = 1;
30819let DecoderNamespace = "EXT_mmvec";
30820}
30821def V6_vaddubsat : HInst<
30822(outs HvxVR:$Vd32),
30823(ins HvxVR:$Vu32, HvxVR:$Vv32),
30824"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
30825tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30826let Inst{7-5} = 0b001;
30827let Inst{13-13} = 0b0;
30828let Inst{31-21} = 0b00011100010;
30829let hasNewValue = 1;
30830let opNewValue = 0;
30831let isCVI = 1;
30832let isHVXALU = 1;
30833let isHVXALU2SRC = 1;
30834let DecoderNamespace = "EXT_mmvec";
30835}
30836def V6_vaddubsat_alt : HInst<
30837(outs HvxVR:$Vd32),
30838(ins HvxVR:$Vu32, HvxVR:$Vv32),
30839"$Vd32 = vaddub($Vu32,$Vv32):sat",
30840PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30841let hasNewValue = 1;
30842let opNewValue = 0;
30843let isCVI = 1;
30844let isPseudo = 1;
30845let isCodeGenOnly = 1;
30846let DecoderNamespace = "EXT_mmvec";
30847}
30848def V6_vaddubsat_dv : HInst<
30849(outs HvxWR:$Vdd32),
30850(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30851"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
30852tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30853let Inst{7-5} = 0b111;
30854let Inst{13-13} = 0b0;
30855let Inst{31-21} = 0b00011100011;
30856let hasNewValue = 1;
30857let opNewValue = 0;
30858let isCVI = 1;
30859let DecoderNamespace = "EXT_mmvec";
30860}
30861def V6_vaddubsat_dv_alt : HInst<
30862(outs HvxWR:$Vdd32),
30863(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30864"$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
30865PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30866let hasNewValue = 1;
30867let opNewValue = 0;
30868let isCVI = 1;
30869let isPseudo = 1;
30870let isCodeGenOnly = 1;
30871let DecoderNamespace = "EXT_mmvec";
30872}
30873def V6_vaddububb_sat : HInst<
30874(outs HvxVR:$Vd32),
30875(ins HvxVR:$Vu32, HvxVR:$Vv32),
30876"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
30877tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30878let Inst{7-5} = 0b100;
30879let Inst{13-13} = 0b0;
30880let Inst{31-21} = 0b00011110101;
30881let hasNewValue = 1;
30882let opNewValue = 0;
30883let isCVI = 1;
30884let isHVXALU = 1;
30885let isHVXALU2SRC = 1;
30886let DecoderNamespace = "EXT_mmvec";
30887}
30888def V6_vadduhsat : HInst<
30889(outs HvxVR:$Vd32),
30890(ins HvxVR:$Vu32, HvxVR:$Vv32),
30891"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
30892tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30893let Inst{7-5} = 0b010;
30894let Inst{13-13} = 0b0;
30895let Inst{31-21} = 0b00011100010;
30896let hasNewValue = 1;
30897let opNewValue = 0;
30898let isCVI = 1;
30899let isHVXALU = 1;
30900let isHVXALU2SRC = 1;
30901let DecoderNamespace = "EXT_mmvec";
30902}
30903def V6_vadduhsat_alt : HInst<
30904(outs HvxVR:$Vd32),
30905(ins HvxVR:$Vu32, HvxVR:$Vv32),
30906"$Vd32 = vadduh($Vu32,$Vv32):sat",
30907PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30908let hasNewValue = 1;
30909let opNewValue = 0;
30910let isCVI = 1;
30911let isPseudo = 1;
30912let isCodeGenOnly = 1;
30913let DecoderNamespace = "EXT_mmvec";
30914}
30915def V6_vadduhsat_dv : HInst<
30916(outs HvxWR:$Vdd32),
30917(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30918"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
30919tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30920let Inst{7-5} = 0b000;
30921let Inst{13-13} = 0b0;
30922let Inst{31-21} = 0b00011100100;
30923let hasNewValue = 1;
30924let opNewValue = 0;
30925let isCVI = 1;
30926let DecoderNamespace = "EXT_mmvec";
30927}
30928def V6_vadduhsat_dv_alt : HInst<
30929(outs HvxWR:$Vdd32),
30930(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30931"$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
30932PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30933let hasNewValue = 1;
30934let opNewValue = 0;
30935let isCVI = 1;
30936let isPseudo = 1;
30937let isCodeGenOnly = 1;
30938let DecoderNamespace = "EXT_mmvec";
30939}
30940def V6_vadduhw : HInst<
30941(outs HvxWR:$Vdd32),
30942(ins HvxVR:$Vu32, HvxVR:$Vv32),
30943"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
30944tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30945let Inst{7-5} = 0b011;
30946let Inst{13-13} = 0b0;
30947let Inst{31-21} = 0b00011100101;
30948let hasNewValue = 1;
30949let opNewValue = 0;
30950let isCVI = 1;
30951let DecoderNamespace = "EXT_mmvec";
30952}
30953def V6_vadduhw_acc : HInst<
30954(outs HvxWR:$Vxx32),
30955(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30956"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
30957tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30958let Inst{7-5} = 0b100;
30959let Inst{13-13} = 0b1;
30960let Inst{31-21} = 0b00011100010;
30961let hasNewValue = 1;
30962let opNewValue = 0;
30963let isAccumulator = 1;
30964let isCVI = 1;
30965let DecoderNamespace = "EXT_mmvec";
30966let Constraints = "$Vxx32 = $Vxx32in";
30967}
30968def V6_vadduhw_acc_alt : HInst<
30969(outs HvxWR:$Vxx32),
30970(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30971"$Vxx32 += vadduh($Vu32,$Vv32)",
30972PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30973let hasNewValue = 1;
30974let opNewValue = 0;
30975let isAccumulator = 1;
30976let isCVI = 1;
30977let isPseudo = 1;
30978let isCodeGenOnly = 1;
30979let DecoderNamespace = "EXT_mmvec";
30980let Constraints = "$Vxx32 = $Vxx32in";
30981}
30982def V6_vadduhw_alt : HInst<
30983(outs HvxWR:$Vdd32),
30984(ins HvxVR:$Vu32, HvxVR:$Vv32),
30985"$Vdd32 = vadduh($Vu32,$Vv32)",
30986PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30987let hasNewValue = 1;
30988let opNewValue = 0;
30989let isCVI = 1;
30990let isPseudo = 1;
30991let isCodeGenOnly = 1;
30992let DecoderNamespace = "EXT_mmvec";
30993}
30994def V6_vadduwsat : HInst<
30995(outs HvxVR:$Vd32),
30996(ins HvxVR:$Vu32, HvxVR:$Vv32),
30997"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
30998tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30999let Inst{7-5} = 0b001;
31000let Inst{13-13} = 0b0;
31001let Inst{31-21} = 0b00011111011;
31002let hasNewValue = 1;
31003let opNewValue = 0;
31004let isCVI = 1;
31005let isHVXALU = 1;
31006let isHVXALU2SRC = 1;
31007let DecoderNamespace = "EXT_mmvec";
31008}
31009def V6_vadduwsat_alt : HInst<
31010(outs HvxVR:$Vd32),
31011(ins HvxVR:$Vu32, HvxVR:$Vv32),
31012"$Vd32 = vadduw($Vu32,$Vv32):sat",
31013PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31014let hasNewValue = 1;
31015let opNewValue = 0;
31016let isCVI = 1;
31017let isPseudo = 1;
31018let isCodeGenOnly = 1;
31019let DecoderNamespace = "EXT_mmvec";
31020}
31021def V6_vadduwsat_dv : HInst<
31022(outs HvxWR:$Vdd32),
31023(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31024"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
31025tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
31026let Inst{7-5} = 0b010;
31027let Inst{13-13} = 0b0;
31028let Inst{31-21} = 0b00011110101;
31029let hasNewValue = 1;
31030let opNewValue = 0;
31031let isCVI = 1;
31032let DecoderNamespace = "EXT_mmvec";
31033}
31034def V6_vadduwsat_dv_alt : HInst<
31035(outs HvxWR:$Vdd32),
31036(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31037"$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
31038PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31039let hasNewValue = 1;
31040let opNewValue = 0;
31041let isCVI = 1;
31042let isPseudo = 1;
31043let isCodeGenOnly = 1;
31044let DecoderNamespace = "EXT_mmvec";
31045}
31046def V6_vaddw : HInst<
31047(outs HvxVR:$Vd32),
31048(ins HvxVR:$Vu32, HvxVR:$Vv32),
31049"$Vd32.w = vadd($Vu32.w,$Vv32.w)",
31050tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31051let Inst{7-5} = 0b000;
31052let Inst{13-13} = 0b0;
31053let Inst{31-21} = 0b00011100010;
31054let hasNewValue = 1;
31055let opNewValue = 0;
31056let isCVI = 1;
31057let isHVXALU = 1;
31058let isHVXALU2SRC = 1;
31059let DecoderNamespace = "EXT_mmvec";
31060}
31061def V6_vaddw_alt : HInst<
31062(outs HvxVR:$Vd32),
31063(ins HvxVR:$Vu32, HvxVR:$Vv32),
31064"$Vd32 = vaddw($Vu32,$Vv32)",
31065PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31066let hasNewValue = 1;
31067let opNewValue = 0;
31068let isCVI = 1;
31069let isPseudo = 1;
31070let isCodeGenOnly = 1;
31071let DecoderNamespace = "EXT_mmvec";
31072}
31073def V6_vaddw_dv : HInst<
31074(outs HvxWR:$Vdd32),
31075(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31076"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
31077tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
31078let Inst{7-5} = 0b110;
31079let Inst{13-13} = 0b0;
31080let Inst{31-21} = 0b00011100011;
31081let hasNewValue = 1;
31082let opNewValue = 0;
31083let isCVI = 1;
31084let DecoderNamespace = "EXT_mmvec";
31085}
31086def V6_vaddw_dv_alt : HInst<
31087(outs HvxWR:$Vdd32),
31088(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31089"$Vdd32 = vaddw($Vuu32,$Vvv32)",
31090PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31091let hasNewValue = 1;
31092let opNewValue = 0;
31093let isCVI = 1;
31094let isPseudo = 1;
31095let isCodeGenOnly = 1;
31096let DecoderNamespace = "EXT_mmvec";
31097}
31098def V6_vaddwnq : HInst<
31099(outs HvxVR:$Vx32),
31100(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31101"if (!$Qv4) $Vx32.w += $Vu32.w",
31102tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
31103let Inst{7-5} = 0b101;
31104let Inst{13-13} = 0b1;
31105let Inst{21-16} = 0b000001;
31106let Inst{31-24} = 0b00011110;
31107let hasNewValue = 1;
31108let opNewValue = 0;
31109let isAccumulator = 1;
31110let isCVI = 1;
31111let isHVXALU = 1;
31112let isHVXALU2SRC = 1;
31113let DecoderNamespace = "EXT_mmvec";
31114let Constraints = "$Vx32 = $Vx32in";
31115}
31116def V6_vaddwnq_alt : HInst<
31117(outs HvxVR:$Vx32),
31118(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31119"if (!$Qv4.w) $Vx32.w += $Vu32.w",
31120PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31121let hasNewValue = 1;
31122let opNewValue = 0;
31123let isAccumulator = 1;
31124let isCVI = 1;
31125let isPseudo = 1;
31126let isCodeGenOnly = 1;
31127let DecoderNamespace = "EXT_mmvec";
31128let Constraints = "$Vx32 = $Vx32in";
31129}
31130def V6_vaddwq : HInst<
31131(outs HvxVR:$Vx32),
31132(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31133"if ($Qv4) $Vx32.w += $Vu32.w",
31134tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
31135let Inst{7-5} = 0b010;
31136let Inst{13-13} = 0b1;
31137let Inst{21-16} = 0b000001;
31138let Inst{31-24} = 0b00011110;
31139let hasNewValue = 1;
31140let opNewValue = 0;
31141let isAccumulator = 1;
31142let isCVI = 1;
31143let isHVXALU = 1;
31144let isHVXALU2SRC = 1;
31145let DecoderNamespace = "EXT_mmvec";
31146let Constraints = "$Vx32 = $Vx32in";
31147}
31148def V6_vaddwq_alt : HInst<
31149(outs HvxVR:$Vx32),
31150(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31151"if ($Qv4.w) $Vx32.w += $Vu32.w",
31152PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31153let hasNewValue = 1;
31154let opNewValue = 0;
31155let isAccumulator = 1;
31156let isCVI = 1;
31157let isPseudo = 1;
31158let isCodeGenOnly = 1;
31159let DecoderNamespace = "EXT_mmvec";
31160let Constraints = "$Vx32 = $Vx32in";
31161}
31162def V6_vaddwsat : HInst<
31163(outs HvxVR:$Vd32),
31164(ins HvxVR:$Vu32, HvxVR:$Vv32),
31165"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
31166tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31167let Inst{7-5} = 0b100;
31168let Inst{13-13} = 0b0;
31169let Inst{31-21} = 0b00011100010;
31170let hasNewValue = 1;
31171let opNewValue = 0;
31172let isCVI = 1;
31173let isHVXALU = 1;
31174let isHVXALU2SRC = 1;
31175let DecoderNamespace = "EXT_mmvec";
31176}
31177def V6_vaddwsat_alt : HInst<
31178(outs HvxVR:$Vd32),
31179(ins HvxVR:$Vu32, HvxVR:$Vv32),
31180"$Vd32 = vaddw($Vu32,$Vv32):sat",
31181PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31182let hasNewValue = 1;
31183let opNewValue = 0;
31184let isCVI = 1;
31185let isPseudo = 1;
31186let isCodeGenOnly = 1;
31187let DecoderNamespace = "EXT_mmvec";
31188}
31189def V6_vaddwsat_dv : HInst<
31190(outs HvxWR:$Vdd32),
31191(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31192"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
31193tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
31194let Inst{7-5} = 0b010;
31195let Inst{13-13} = 0b0;
31196let Inst{31-21} = 0b00011100100;
31197let hasNewValue = 1;
31198let opNewValue = 0;
31199let isCVI = 1;
31200let DecoderNamespace = "EXT_mmvec";
31201}
31202def V6_vaddwsat_dv_alt : HInst<
31203(outs HvxWR:$Vdd32),
31204(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31205"$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
31206PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31207let hasNewValue = 1;
31208let opNewValue = 0;
31209let isCVI = 1;
31210let isPseudo = 1;
31211let isCodeGenOnly = 1;
31212let DecoderNamespace = "EXT_mmvec";
31213}
31214def V6_valignb : HInst<
31215(outs HvxVR:$Vd32),
31216(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31217"$Vd32 = valign($Vu32,$Vv32,$Rt8)",
31218tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
31219let Inst{7-5} = 0b000;
31220let Inst{13-13} = 0b0;
31221let Inst{31-24} = 0b00011011;
31222let hasNewValue = 1;
31223let opNewValue = 0;
31224let isCVI = 1;
31225let DecoderNamespace = "EXT_mmvec";
31226}
31227def V6_valignbi : HInst<
31228(outs HvxVR:$Vd32),
31229(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
31230"$Vd32 = valign($Vu32,$Vv32,#$Ii)",
31231tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
31232let Inst{13-13} = 0b1;
31233let Inst{31-21} = 0b00011110001;
31234let hasNewValue = 1;
31235let opNewValue = 0;
31236let isCVI = 1;
31237let DecoderNamespace = "EXT_mmvec";
31238}
31239def V6_vand : HInst<
31240(outs HvxVR:$Vd32),
31241(ins HvxVR:$Vu32, HvxVR:$Vv32),
31242"$Vd32 = vand($Vu32,$Vv32)",
31243tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31244let Inst{7-5} = 0b101;
31245let Inst{13-13} = 0b0;
31246let Inst{31-21} = 0b00011100001;
31247let hasNewValue = 1;
31248let opNewValue = 0;
31249let isCVI = 1;
31250let isHVXALU = 1;
31251let isHVXALU2SRC = 1;
31252let DecoderNamespace = "EXT_mmvec";
31253}
31254def V6_vandnqrt : HInst<
31255(outs HvxVR:$Vd32),
31256(ins HvxQR:$Qu4, IntRegs:$Rt32),
31257"$Vd32 = vand(!$Qu4,$Rt32)",
31258tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV62]> {
31259let Inst{7-5} = 0b101;
31260let Inst{13-10} = 0b0001;
31261let Inst{31-21} = 0b00011001101;
31262let hasNewValue = 1;
31263let opNewValue = 0;
31264let isCVI = 1;
31265let DecoderNamespace = "EXT_mmvec";
31266}
31267def V6_vandnqrt_acc : HInst<
31268(outs HvxVR:$Vx32),
31269(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31270"$Vx32 |= vand(!$Qu4,$Rt32)",
31271tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV62]> {
31272let Inst{7-5} = 0b011;
31273let Inst{13-10} = 0b1001;
31274let Inst{31-21} = 0b00011001011;
31275let hasNewValue = 1;
31276let opNewValue = 0;
31277let isAccumulator = 1;
31278let isCVI = 1;
31279let DecoderNamespace = "EXT_mmvec";
31280let Constraints = "$Vx32 = $Vx32in";
31281}
31282def V6_vandnqrt_acc_alt : HInst<
31283(outs HvxVR:$Vx32),
31284(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31285"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
31286PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31287let hasNewValue = 1;
31288let opNewValue = 0;
31289let isAccumulator = 1;
31290let isCVI = 1;
31291let isPseudo = 1;
31292let isCodeGenOnly = 1;
31293let DecoderNamespace = "EXT_mmvec";
31294let Constraints = "$Vx32 = $Vx32in";
31295}
31296def V6_vandnqrt_alt : HInst<
31297(outs HvxVR:$Vd32),
31298(ins HvxQR:$Qu4, IntRegs:$Rt32),
31299"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
31300PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31301let hasNewValue = 1;
31302let opNewValue = 0;
31303let isCVI = 1;
31304let isPseudo = 1;
31305let isCodeGenOnly = 1;
31306let DecoderNamespace = "EXT_mmvec";
31307}
31308def V6_vandqrt : HInst<
31309(outs HvxVR:$Vd32),
31310(ins HvxQR:$Qu4, IntRegs:$Rt32),
31311"$Vd32 = vand($Qu4,$Rt32)",
31312tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
31313let Inst{7-5} = 0b101;
31314let Inst{13-10} = 0b0000;
31315let Inst{31-21} = 0b00011001101;
31316let hasNewValue = 1;
31317let opNewValue = 0;
31318let isCVI = 1;
31319let DecoderNamespace = "EXT_mmvec";
31320}
31321def V6_vandqrt_acc : HInst<
31322(outs HvxVR:$Vx32),
31323(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31324"$Vx32 |= vand($Qu4,$Rt32)",
31325tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
31326let Inst{7-5} = 0b011;
31327let Inst{13-10} = 0b1000;
31328let Inst{31-21} = 0b00011001011;
31329let hasNewValue = 1;
31330let opNewValue = 0;
31331let isAccumulator = 1;
31332let isCVI = 1;
31333let DecoderNamespace = "EXT_mmvec";
31334let Constraints = "$Vx32 = $Vx32in";
31335}
31336def V6_vandqrt_acc_alt : HInst<
31337(outs HvxVR:$Vx32),
31338(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31339"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
31340PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31341let hasNewValue = 1;
31342let opNewValue = 0;
31343let isAccumulator = 1;
31344let isCVI = 1;
31345let isPseudo = 1;
31346let isCodeGenOnly = 1;
31347let DecoderNamespace = "EXT_mmvec";
31348let Constraints = "$Vx32 = $Vx32in";
31349}
31350def V6_vandqrt_alt : HInst<
31351(outs HvxVR:$Vd32),
31352(ins HvxQR:$Qu4, IntRegs:$Rt32),
31353"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
31354PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31355let hasNewValue = 1;
31356let opNewValue = 0;
31357let isCVI = 1;
31358let isPseudo = 1;
31359let isCodeGenOnly = 1;
31360let DecoderNamespace = "EXT_mmvec";
31361}
31362def V6_vandvnqv : HInst<
31363(outs HvxVR:$Vd32),
31364(ins HvxQR:$Qv4, HvxVR:$Vu32),
31365"$Vd32 = vand(!$Qv4,$Vu32)",
31366tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31367let Inst{7-5} = 0b001;
31368let Inst{13-13} = 0b1;
31369let Inst{21-16} = 0b000011;
31370let Inst{31-24} = 0b00011110;
31371let hasNewValue = 1;
31372let opNewValue = 0;
31373let isCVI = 1;
31374let isHVXALU = 1;
31375let isHVXALU2SRC = 1;
31376let DecoderNamespace = "EXT_mmvec";
31377}
31378def V6_vandvqv : HInst<
31379(outs HvxVR:$Vd32),
31380(ins HvxQR:$Qv4, HvxVR:$Vu32),
31381"$Vd32 = vand($Qv4,$Vu32)",
31382tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31383let Inst{7-5} = 0b000;
31384let Inst{13-13} = 0b1;
31385let Inst{21-16} = 0b000011;
31386let Inst{31-24} = 0b00011110;
31387let hasNewValue = 1;
31388let opNewValue = 0;
31389let isCVI = 1;
31390let isHVXALU = 1;
31391let isHVXALU2SRC = 1;
31392let DecoderNamespace = "EXT_mmvec";
31393}
31394def V6_vandvrt : HInst<
31395(outs HvxQR:$Qd4),
31396(ins HvxVR:$Vu32, IntRegs:$Rt32),
31397"$Qd4 = vand($Vu32,$Rt32)",
31398tc_ac4046bc, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
31399let Inst{7-2} = 0b010010;
31400let Inst{13-13} = 0b0;
31401let Inst{31-21} = 0b00011001101;
31402let hasNewValue = 1;
31403let opNewValue = 0;
31404let isCVI = 1;
31405let DecoderNamespace = "EXT_mmvec";
31406}
31407def V6_vandvrt_acc : HInst<
31408(outs HvxQR:$Qx4),
31409(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31410"$Qx4 |= vand($Vu32,$Rt32)",
31411tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
31412let Inst{7-2} = 0b100000;
31413let Inst{13-13} = 0b1;
31414let Inst{31-21} = 0b00011001011;
31415let isAccumulator = 1;
31416let isCVI = 1;
31417let DecoderNamespace = "EXT_mmvec";
31418let Constraints = "$Qx4 = $Qx4in";
31419}
31420def V6_vandvrt_acc_alt : HInst<
31421(outs HvxQR:$Qx4),
31422(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31423"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
31424PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31425let isAccumulator = 1;
31426let isCVI = 1;
31427let isPseudo = 1;
31428let isCodeGenOnly = 1;
31429let DecoderNamespace = "EXT_mmvec";
31430let Constraints = "$Qx4 = $Qx4in";
31431}
31432def V6_vandvrt_alt : HInst<
31433(outs HvxQR:$Qd4),
31434(ins HvxVR:$Vu32, IntRegs:$Rt32),
31435"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
31436PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31437let hasNewValue = 1;
31438let opNewValue = 0;
31439let isCVI = 1;
31440let isPseudo = 1;
31441let isCodeGenOnly = 1;
31442let DecoderNamespace = "EXT_mmvec";
31443}
31444def V6_vaslh : HInst<
31445(outs HvxVR:$Vd32),
31446(ins HvxVR:$Vu32, IntRegs:$Rt32),
31447"$Vd32.h = vasl($Vu32.h,$Rt32)",
31448tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31449let Inst{7-5} = 0b000;
31450let Inst{13-13} = 0b0;
31451let Inst{31-21} = 0b00011001100;
31452let hasNewValue = 1;
31453let opNewValue = 0;
31454let isCVI = 1;
31455let DecoderNamespace = "EXT_mmvec";
31456}
31457def V6_vaslh_acc : HInst<
31458(outs HvxVR:$Vx32),
31459(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31460"$Vx32.h += vasl($Vu32.h,$Rt32)",
31461tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31462let Inst{7-5} = 0b101;
31463let Inst{13-13} = 0b1;
31464let Inst{31-21} = 0b00011001101;
31465let hasNewValue = 1;
31466let opNewValue = 0;
31467let isAccumulator = 1;
31468let isCVI = 1;
31469let DecoderNamespace = "EXT_mmvec";
31470let Constraints = "$Vx32 = $Vx32in";
31471}
31472def V6_vaslh_acc_alt : HInst<
31473(outs HvxVR:$Vx32),
31474(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31475"$Vx32 += vaslh($Vu32,$Rt32)",
31476PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31477let hasNewValue = 1;
31478let opNewValue = 0;
31479let isAccumulator = 1;
31480let isCVI = 1;
31481let isPseudo = 1;
31482let isCodeGenOnly = 1;
31483let DecoderNamespace = "EXT_mmvec";
31484let Constraints = "$Vx32 = $Vx32in";
31485}
31486def V6_vaslh_alt : HInst<
31487(outs HvxVR:$Vd32),
31488(ins HvxVR:$Vu32, IntRegs:$Rt32),
31489"$Vd32 = vaslh($Vu32,$Rt32)",
31490PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31491let hasNewValue = 1;
31492let opNewValue = 0;
31493let isCVI = 1;
31494let isPseudo = 1;
31495let isCodeGenOnly = 1;
31496let DecoderNamespace = "EXT_mmvec";
31497}
31498def V6_vaslhv : HInst<
31499(outs HvxVR:$Vd32),
31500(ins HvxVR:$Vu32, HvxVR:$Vv32),
31501"$Vd32.h = vasl($Vu32.h,$Vv32.h)",
31502tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31503let Inst{7-5} = 0b101;
31504let Inst{13-13} = 0b0;
31505let Inst{31-21} = 0b00011111101;
31506let hasNewValue = 1;
31507let opNewValue = 0;
31508let isCVI = 1;
31509let DecoderNamespace = "EXT_mmvec";
31510}
31511def V6_vaslhv_alt : HInst<
31512(outs HvxVR:$Vd32),
31513(ins HvxVR:$Vu32, HvxVR:$Vv32),
31514"$Vd32 = vaslh($Vu32,$Vv32)",
31515PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31516let hasNewValue = 1;
31517let opNewValue = 0;
31518let isCVI = 1;
31519let isPseudo = 1;
31520let isCodeGenOnly = 1;
31521let DecoderNamespace = "EXT_mmvec";
31522}
31523def V6_vaslw : HInst<
31524(outs HvxVR:$Vd32),
31525(ins HvxVR:$Vu32, IntRegs:$Rt32),
31526"$Vd32.w = vasl($Vu32.w,$Rt32)",
31527tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31528let Inst{7-5} = 0b111;
31529let Inst{13-13} = 0b0;
31530let Inst{31-21} = 0b00011001011;
31531let hasNewValue = 1;
31532let opNewValue = 0;
31533let isCVI = 1;
31534let DecoderNamespace = "EXT_mmvec";
31535}
31536def V6_vaslw_acc : HInst<
31537(outs HvxVR:$Vx32),
31538(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31539"$Vx32.w += vasl($Vu32.w,$Rt32)",
31540tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31541let Inst{7-5} = 0b010;
31542let Inst{13-13} = 0b1;
31543let Inst{31-21} = 0b00011001011;
31544let hasNewValue = 1;
31545let opNewValue = 0;
31546let isAccumulator = 1;
31547let isCVI = 1;
31548let DecoderNamespace = "EXT_mmvec";
31549let Constraints = "$Vx32 = $Vx32in";
31550}
31551def V6_vaslw_acc_alt : HInst<
31552(outs HvxVR:$Vx32),
31553(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31554"$Vx32 += vaslw($Vu32,$Rt32)",
31555PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31556let hasNewValue = 1;
31557let opNewValue = 0;
31558let isAccumulator = 1;
31559let isCVI = 1;
31560let isPseudo = 1;
31561let isCodeGenOnly = 1;
31562let DecoderNamespace = "EXT_mmvec";
31563let Constraints = "$Vx32 = $Vx32in";
31564}
31565def V6_vaslw_alt : HInst<
31566(outs HvxVR:$Vd32),
31567(ins HvxVR:$Vu32, IntRegs:$Rt32),
31568"$Vd32 = vaslw($Vu32,$Rt32)",
31569PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31570let hasNewValue = 1;
31571let opNewValue = 0;
31572let isCVI = 1;
31573let isPseudo = 1;
31574let isCodeGenOnly = 1;
31575let DecoderNamespace = "EXT_mmvec";
31576}
31577def V6_vaslwv : HInst<
31578(outs HvxVR:$Vd32),
31579(ins HvxVR:$Vu32, HvxVR:$Vv32),
31580"$Vd32.w = vasl($Vu32.w,$Vv32.w)",
31581tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31582let Inst{7-5} = 0b100;
31583let Inst{13-13} = 0b0;
31584let Inst{31-21} = 0b00011111101;
31585let hasNewValue = 1;
31586let opNewValue = 0;
31587let isCVI = 1;
31588let DecoderNamespace = "EXT_mmvec";
31589}
31590def V6_vaslwv_alt : HInst<
31591(outs HvxVR:$Vd32),
31592(ins HvxVR:$Vu32, HvxVR:$Vv32),
31593"$Vd32 = vaslw($Vu32,$Vv32)",
31594PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31595let hasNewValue = 1;
31596let opNewValue = 0;
31597let isCVI = 1;
31598let isPseudo = 1;
31599let isCodeGenOnly = 1;
31600let DecoderNamespace = "EXT_mmvec";
31601}
31602def V6_vasr_into : HInst<
31603(outs HvxWR:$Vxx32),
31604(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31605"$Vxx32.w = vasrinto($Vu32.w,$Vv32.w)",
31606tc_df80eeb0, TypeCVI_VP_VS>, Enc_3fc427, Requires<[UseHVXV66]> {
31607let Inst{7-5} = 0b111;
31608let Inst{13-13} = 0b1;
31609let Inst{31-21} = 0b00011010101;
31610let hasNewValue = 1;
31611let opNewValue = 0;
31612let isCVI = 1;
31613let DecoderNamespace = "EXT_mmvec";
31614let Constraints = "$Vxx32 = $Vxx32in";
31615}
31616def V6_vasr_into_alt : HInst<
31617(outs HvxWR:$Vxx32),
31618(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31619"$Vxx32 = vasrinto($Vu32,$Vv32)",
31620PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
31621let hasNewValue = 1;
31622let opNewValue = 0;
31623let isCVI = 1;
31624let isPseudo = 1;
31625let isCodeGenOnly = 1;
31626let DecoderNamespace = "EXT_mmvec";
31627let Constraints = "$Vxx32 = $Vxx32in";
31628}
31629def V6_vasrh : HInst<
31630(outs HvxVR:$Vd32),
31631(ins HvxVR:$Vu32, IntRegs:$Rt32),
31632"$Vd32.h = vasr($Vu32.h,$Rt32)",
31633tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31634let Inst{7-5} = 0b110;
31635let Inst{13-13} = 0b0;
31636let Inst{31-21} = 0b00011001011;
31637let hasNewValue = 1;
31638let opNewValue = 0;
31639let isCVI = 1;
31640let DecoderNamespace = "EXT_mmvec";
31641}
31642def V6_vasrh_acc : HInst<
31643(outs HvxVR:$Vx32),
31644(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31645"$Vx32.h += vasr($Vu32.h,$Rt32)",
31646tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31647let Inst{7-5} = 0b111;
31648let Inst{13-13} = 0b1;
31649let Inst{31-21} = 0b00011001100;
31650let hasNewValue = 1;
31651let opNewValue = 0;
31652let isAccumulator = 1;
31653let isCVI = 1;
31654let DecoderNamespace = "EXT_mmvec";
31655let Constraints = "$Vx32 = $Vx32in";
31656}
31657def V6_vasrh_acc_alt : HInst<
31658(outs HvxVR:$Vx32),
31659(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31660"$Vx32 += vasrh($Vu32,$Rt32)",
31661PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31662let hasNewValue = 1;
31663let opNewValue = 0;
31664let isAccumulator = 1;
31665let isCVI = 1;
31666let isPseudo = 1;
31667let isCodeGenOnly = 1;
31668let DecoderNamespace = "EXT_mmvec";
31669let Constraints = "$Vx32 = $Vx32in";
31670}
31671def V6_vasrh_alt : HInst<
31672(outs HvxVR:$Vd32),
31673(ins HvxVR:$Vu32, IntRegs:$Rt32),
31674"$Vd32 = vasrh($Vu32,$Rt32)",
31675PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31676let hasNewValue = 1;
31677let opNewValue = 0;
31678let isCVI = 1;
31679let isPseudo = 1;
31680let isCodeGenOnly = 1;
31681let DecoderNamespace = "EXT_mmvec";
31682}
31683def V6_vasrhbrndsat : HInst<
31684(outs HvxVR:$Vd32),
31685(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31686"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31687tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31688let Inst{7-5} = 0b000;
31689let Inst{13-13} = 0b1;
31690let Inst{31-24} = 0b00011011;
31691let hasNewValue = 1;
31692let opNewValue = 0;
31693let isCVI = 1;
31694let DecoderNamespace = "EXT_mmvec";
31695}
31696def V6_vasrhbsat : HInst<
31697(outs HvxVR:$Vd32),
31698(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31699"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31700tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31701let Inst{7-5} = 0b000;
31702let Inst{13-13} = 0b0;
31703let Inst{31-24} = 0b00011000;
31704let hasNewValue = 1;
31705let opNewValue = 0;
31706let isCVI = 1;
31707let DecoderNamespace = "EXT_mmvec";
31708}
31709def V6_vasrhubrndsat : HInst<
31710(outs HvxVR:$Vd32),
31711(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31712"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31713tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31714let Inst{7-5} = 0b111;
31715let Inst{13-13} = 0b0;
31716let Inst{31-24} = 0b00011011;
31717let hasNewValue = 1;
31718let opNewValue = 0;
31719let isCVI = 1;
31720let DecoderNamespace = "EXT_mmvec";
31721}
31722def V6_vasrhubsat : HInst<
31723(outs HvxVR:$Vd32),
31724(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31725"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31726tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31727let Inst{7-5} = 0b110;
31728let Inst{13-13} = 0b0;
31729let Inst{31-24} = 0b00011011;
31730let hasNewValue = 1;
31731let opNewValue = 0;
31732let isCVI = 1;
31733let DecoderNamespace = "EXT_mmvec";
31734}
31735def V6_vasrhv : HInst<
31736(outs HvxVR:$Vd32),
31737(ins HvxVR:$Vu32, HvxVR:$Vv32),
31738"$Vd32.h = vasr($Vu32.h,$Vv32.h)",
31739tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31740let Inst{7-5} = 0b011;
31741let Inst{13-13} = 0b0;
31742let Inst{31-21} = 0b00011111101;
31743let hasNewValue = 1;
31744let opNewValue = 0;
31745let isCVI = 1;
31746let DecoderNamespace = "EXT_mmvec";
31747}
31748def V6_vasrhv_alt : HInst<
31749(outs HvxVR:$Vd32),
31750(ins HvxVR:$Vu32, HvxVR:$Vv32),
31751"$Vd32 = vasrh($Vu32,$Vv32)",
31752PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31753let hasNewValue = 1;
31754let opNewValue = 0;
31755let isCVI = 1;
31756let isPseudo = 1;
31757let isCodeGenOnly = 1;
31758let DecoderNamespace = "EXT_mmvec";
31759}
31760def V6_vasruhubrndsat : HInst<
31761(outs HvxVR:$Vd32),
31762(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31763"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
31764tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31765let Inst{7-5} = 0b111;
31766let Inst{13-13} = 0b0;
31767let Inst{31-24} = 0b00011000;
31768let hasNewValue = 1;
31769let opNewValue = 0;
31770let isCVI = 1;
31771let DecoderNamespace = "EXT_mmvec";
31772}
31773def V6_vasruhubsat : HInst<
31774(outs HvxVR:$Vd32),
31775(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31776"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
31777tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31778let Inst{7-5} = 0b101;
31779let Inst{13-13} = 0b1;
31780let Inst{31-24} = 0b00011000;
31781let hasNewValue = 1;
31782let opNewValue = 0;
31783let isCVI = 1;
31784let DecoderNamespace = "EXT_mmvec";
31785}
31786def V6_vasruwuhrndsat : HInst<
31787(outs HvxVR:$Vd32),
31788(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31789"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
31790tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31791let Inst{7-5} = 0b001;
31792let Inst{13-13} = 0b0;
31793let Inst{31-24} = 0b00011000;
31794let hasNewValue = 1;
31795let opNewValue = 0;
31796let isCVI = 1;
31797let DecoderNamespace = "EXT_mmvec";
31798}
31799def V6_vasruwuhsat : HInst<
31800(outs HvxVR:$Vd32),
31801(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31802"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
31803tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31804let Inst{7-5} = 0b100;
31805let Inst{13-13} = 0b1;
31806let Inst{31-24} = 0b00011000;
31807let hasNewValue = 1;
31808let opNewValue = 0;
31809let isCVI = 1;
31810let DecoderNamespace = "EXT_mmvec";
31811}
31812def V6_vasrvuhubrndsat : HInst<
31813(outs HvxVR:$Vd32),
31814(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31815"$Vd32.ub = vasr($Vuu32.uh,$Vv32.ub):rnd:sat",
31816tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31817let Inst{7-5} = 0b011;
31818let Inst{13-13} = 0b0;
31819let Inst{31-21} = 0b00011101000;
31820let hasNewValue = 1;
31821let opNewValue = 0;
31822let isCVI = 1;
31823let hasUnaryRestriction = 1;
31824let DecoderNamespace = "EXT_mmvec";
31825}
31826def V6_vasrvuhubsat : HInst<
31827(outs HvxVR:$Vd32),
31828(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31829"$Vd32.ub = vasr($Vuu32.uh,$Vv32.ub):sat",
31830tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31831let Inst{7-5} = 0b010;
31832let Inst{13-13} = 0b0;
31833let Inst{31-21} = 0b00011101000;
31834let hasNewValue = 1;
31835let opNewValue = 0;
31836let isCVI = 1;
31837let hasUnaryRestriction = 1;
31838let DecoderNamespace = "EXT_mmvec";
31839}
31840def V6_vasrvwuhrndsat : HInst<
31841(outs HvxVR:$Vd32),
31842(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31843"$Vd32.uh = vasr($Vuu32.w,$Vv32.uh):rnd:sat",
31844tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31845let Inst{7-5} = 0b001;
31846let Inst{13-13} = 0b0;
31847let Inst{31-21} = 0b00011101000;
31848let hasNewValue = 1;
31849let opNewValue = 0;
31850let isCVI = 1;
31851let hasUnaryRestriction = 1;
31852let DecoderNamespace = "EXT_mmvec";
31853}
31854def V6_vasrvwuhsat : HInst<
31855(outs HvxVR:$Vd32),
31856(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31857"$Vd32.uh = vasr($Vuu32.w,$Vv32.uh):sat",
31858tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31859let Inst{7-5} = 0b000;
31860let Inst{13-13} = 0b0;
31861let Inst{31-21} = 0b00011101000;
31862let hasNewValue = 1;
31863let opNewValue = 0;
31864let isCVI = 1;
31865let hasUnaryRestriction = 1;
31866let DecoderNamespace = "EXT_mmvec";
31867}
31868def V6_vasrw : HInst<
31869(outs HvxVR:$Vd32),
31870(ins HvxVR:$Vu32, IntRegs:$Rt32),
31871"$Vd32.w = vasr($Vu32.w,$Rt32)",
31872tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31873let Inst{7-5} = 0b101;
31874let Inst{13-13} = 0b0;
31875let Inst{31-21} = 0b00011001011;
31876let hasNewValue = 1;
31877let opNewValue = 0;
31878let isCVI = 1;
31879let DecoderNamespace = "EXT_mmvec";
31880}
31881def V6_vasrw_acc : HInst<
31882(outs HvxVR:$Vx32),
31883(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31884"$Vx32.w += vasr($Vu32.w,$Rt32)",
31885tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31886let Inst{7-5} = 0b101;
31887let Inst{13-13} = 0b1;
31888let Inst{31-21} = 0b00011001011;
31889let hasNewValue = 1;
31890let opNewValue = 0;
31891let isAccumulator = 1;
31892let isCVI = 1;
31893let DecoderNamespace = "EXT_mmvec";
31894let Constraints = "$Vx32 = $Vx32in";
31895}
31896def V6_vasrw_acc_alt : HInst<
31897(outs HvxVR:$Vx32),
31898(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31899"$Vx32 += vasrw($Vu32,$Rt32)",
31900PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31901let hasNewValue = 1;
31902let opNewValue = 0;
31903let isAccumulator = 1;
31904let isCVI = 1;
31905let isPseudo = 1;
31906let isCodeGenOnly = 1;
31907let DecoderNamespace = "EXT_mmvec";
31908let Constraints = "$Vx32 = $Vx32in";
31909}
31910def V6_vasrw_alt : HInst<
31911(outs HvxVR:$Vd32),
31912(ins HvxVR:$Vu32, IntRegs:$Rt32),
31913"$Vd32 = vasrw($Vu32,$Rt32)",
31914PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31915let hasNewValue = 1;
31916let opNewValue = 0;
31917let isCVI = 1;
31918let isPseudo = 1;
31919let isCodeGenOnly = 1;
31920let DecoderNamespace = "EXT_mmvec";
31921}
31922def V6_vasrwh : HInst<
31923(outs HvxVR:$Vd32),
31924(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31925"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
31926tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31927let Inst{7-5} = 0b010;
31928let Inst{13-13} = 0b0;
31929let Inst{31-24} = 0b00011011;
31930let hasNewValue = 1;
31931let opNewValue = 0;
31932let isCVI = 1;
31933let DecoderNamespace = "EXT_mmvec";
31934}
31935def V6_vasrwhrndsat : HInst<
31936(outs HvxVR:$Vd32),
31937(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31938"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31939tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31940let Inst{7-5} = 0b100;
31941let Inst{13-13} = 0b0;
31942let Inst{31-24} = 0b00011011;
31943let hasNewValue = 1;
31944let opNewValue = 0;
31945let isCVI = 1;
31946let DecoderNamespace = "EXT_mmvec";
31947}
31948def V6_vasrwhsat : HInst<
31949(outs HvxVR:$Vd32),
31950(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31951"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31952tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31953let Inst{7-5} = 0b011;
31954let Inst{13-13} = 0b0;
31955let Inst{31-24} = 0b00011011;
31956let hasNewValue = 1;
31957let opNewValue = 0;
31958let isCVI = 1;
31959let DecoderNamespace = "EXT_mmvec";
31960}
31961def V6_vasrwuhrndsat : HInst<
31962(outs HvxVR:$Vd32),
31963(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31964"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31965tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31966let Inst{7-5} = 0b010;
31967let Inst{13-13} = 0b0;
31968let Inst{31-24} = 0b00011000;
31969let hasNewValue = 1;
31970let opNewValue = 0;
31971let isCVI = 1;
31972let DecoderNamespace = "EXT_mmvec";
31973}
31974def V6_vasrwuhsat : HInst<
31975(outs HvxVR:$Vd32),
31976(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31977"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31978tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31979let Inst{7-5} = 0b101;
31980let Inst{13-13} = 0b0;
31981let Inst{31-24} = 0b00011011;
31982let hasNewValue = 1;
31983let opNewValue = 0;
31984let isCVI = 1;
31985let DecoderNamespace = "EXT_mmvec";
31986}
31987def V6_vasrwv : HInst<
31988(outs HvxVR:$Vd32),
31989(ins HvxVR:$Vu32, HvxVR:$Vv32),
31990"$Vd32.w = vasr($Vu32.w,$Vv32.w)",
31991tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31992let Inst{7-5} = 0b000;
31993let Inst{13-13} = 0b0;
31994let Inst{31-21} = 0b00011111101;
31995let hasNewValue = 1;
31996let opNewValue = 0;
31997let isCVI = 1;
31998let DecoderNamespace = "EXT_mmvec";
31999}
32000def V6_vasrwv_alt : HInst<
32001(outs HvxVR:$Vd32),
32002(ins HvxVR:$Vu32, HvxVR:$Vv32),
32003"$Vd32 = vasrw($Vu32,$Vv32)",
32004PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32005let hasNewValue = 1;
32006let opNewValue = 0;
32007let isCVI = 1;
32008let isPseudo = 1;
32009let isCodeGenOnly = 1;
32010let DecoderNamespace = "EXT_mmvec";
32011}
32012def V6_vassign : HInst<
32013(outs HvxVR:$Vd32),
32014(ins HvxVR:$Vu32),
32015"$Vd32 = $Vu32",
32016tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
32017let Inst{7-5} = 0b111;
32018let Inst{13-13} = 0b1;
32019let Inst{31-16} = 0b0001111000000011;
32020let hasNewValue = 1;
32021let opNewValue = 0;
32022let isCVI = 1;
32023let isHVXALU = 1;
32024let DecoderNamespace = "EXT_mmvec";
32025}
32026def V6_vassign_fp : HInst<
32027(outs HvxVR:$Vd32),
32028(ins HvxVR:$Vu32),
32029"$Vd32.w = vfmv($Vu32.w)",
32030tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32031let Inst{7-5} = 0b001;
32032let Inst{13-13} = 0b1;
32033let Inst{31-16} = 0b0001111000000110;
32034let hasNewValue = 1;
32035let opNewValue = 0;
32036let isCVI = 1;
32037let DecoderNamespace = "EXT_mmvec";
32038}
32039def V6_vassign_tmp : HInst<
32040(outs HvxVR:$Vd32),
32041(ins HvxVR:$Vu32),
32042"$Vd32.tmp = $Vu32",
32043tc_e2fdd6e6, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV69]> {
32044let Inst{7-5} = 0b110;
32045let Inst{13-13} = 0b0;
32046let Inst{31-16} = 0b0001111000000001;
32047let hasNewValue = 1;
32048let opNewValue = 0;
32049let isCVI = 1;
32050let hasHvxTmp = 1;
32051let DecoderNamespace = "EXT_mmvec";
32052}
32053def V6_vassignp : HInst<
32054(outs HvxWR:$Vdd32),
32055(ins HvxWR:$Vuu32),
32056"$Vdd32 = $Vuu32",
32057CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
32058let hasNewValue = 1;
32059let opNewValue = 0;
32060let isCVI = 1;
32061let isPseudo = 1;
32062let DecoderNamespace = "EXT_mmvec";
32063}
32064def V6_vavgb : HInst<
32065(outs HvxVR:$Vd32),
32066(ins HvxVR:$Vu32, HvxVR:$Vv32),
32067"$Vd32.b = vavg($Vu32.b,$Vv32.b)",
32068tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32069let Inst{7-5} = 0b100;
32070let Inst{13-13} = 0b1;
32071let Inst{31-21} = 0b00011111000;
32072let hasNewValue = 1;
32073let opNewValue = 0;
32074let isCVI = 1;
32075let isHVXALU = 1;
32076let isHVXALU2SRC = 1;
32077let DecoderNamespace = "EXT_mmvec";
32078}
32079def V6_vavgb_alt : HInst<
32080(outs HvxVR:$Vd32),
32081(ins HvxVR:$Vu32, HvxVR:$Vv32),
32082"$Vd32 = vavgb($Vu32,$Vv32)",
32083PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32084let hasNewValue = 1;
32085let opNewValue = 0;
32086let isCVI = 1;
32087let isPseudo = 1;
32088let isCodeGenOnly = 1;
32089let DecoderNamespace = "EXT_mmvec";
32090}
32091def V6_vavgbrnd : HInst<
32092(outs HvxVR:$Vd32),
32093(ins HvxVR:$Vu32, HvxVR:$Vv32),
32094"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
32095tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32096let Inst{7-5} = 0b101;
32097let Inst{13-13} = 0b1;
32098let Inst{31-21} = 0b00011111000;
32099let hasNewValue = 1;
32100let opNewValue = 0;
32101let isCVI = 1;
32102let isHVXALU = 1;
32103let isHVXALU2SRC = 1;
32104let DecoderNamespace = "EXT_mmvec";
32105}
32106def V6_vavgbrnd_alt : HInst<
32107(outs HvxVR:$Vd32),
32108(ins HvxVR:$Vu32, HvxVR:$Vv32),
32109"$Vd32 = vavgb($Vu32,$Vv32):rnd",
32110PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32111let hasNewValue = 1;
32112let opNewValue = 0;
32113let isCVI = 1;
32114let isPseudo = 1;
32115let isCodeGenOnly = 1;
32116let DecoderNamespace = "EXT_mmvec";
32117}
32118def V6_vavgh : HInst<
32119(outs HvxVR:$Vd32),
32120(ins HvxVR:$Vu32, HvxVR:$Vv32),
32121"$Vd32.h = vavg($Vu32.h,$Vv32.h)",
32122tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32123let Inst{7-5} = 0b110;
32124let Inst{13-13} = 0b0;
32125let Inst{31-21} = 0b00011100110;
32126let hasNewValue = 1;
32127let opNewValue = 0;
32128let isCVI = 1;
32129let isHVXALU = 1;
32130let isHVXALU2SRC = 1;
32131let DecoderNamespace = "EXT_mmvec";
32132}
32133def V6_vavgh_alt : HInst<
32134(outs HvxVR:$Vd32),
32135(ins HvxVR:$Vu32, HvxVR:$Vv32),
32136"$Vd32 = vavgh($Vu32,$Vv32)",
32137PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32138let hasNewValue = 1;
32139let opNewValue = 0;
32140let isCVI = 1;
32141let isPseudo = 1;
32142let isCodeGenOnly = 1;
32143let DecoderNamespace = "EXT_mmvec";
32144}
32145def V6_vavghrnd : HInst<
32146(outs HvxVR:$Vd32),
32147(ins HvxVR:$Vu32, HvxVR:$Vv32),
32148"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
32149tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32150let Inst{7-5} = 0b101;
32151let Inst{13-13} = 0b0;
32152let Inst{31-21} = 0b00011100111;
32153let hasNewValue = 1;
32154let opNewValue = 0;
32155let isCVI = 1;
32156let isHVXALU = 1;
32157let isHVXALU2SRC = 1;
32158let DecoderNamespace = "EXT_mmvec";
32159}
32160def V6_vavghrnd_alt : HInst<
32161(outs HvxVR:$Vd32),
32162(ins HvxVR:$Vu32, HvxVR:$Vv32),
32163"$Vd32 = vavgh($Vu32,$Vv32):rnd",
32164PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32165let hasNewValue = 1;
32166let opNewValue = 0;
32167let isCVI = 1;
32168let isPseudo = 1;
32169let isCodeGenOnly = 1;
32170let DecoderNamespace = "EXT_mmvec";
32171}
32172def V6_vavgub : HInst<
32173(outs HvxVR:$Vd32),
32174(ins HvxVR:$Vu32, HvxVR:$Vv32),
32175"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
32176tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32177let Inst{7-5} = 0b100;
32178let Inst{13-13} = 0b0;
32179let Inst{31-21} = 0b00011100110;
32180let hasNewValue = 1;
32181let opNewValue = 0;
32182let isCVI = 1;
32183let isHVXALU = 1;
32184let isHVXALU2SRC = 1;
32185let DecoderNamespace = "EXT_mmvec";
32186}
32187def V6_vavgub_alt : HInst<
32188(outs HvxVR:$Vd32),
32189(ins HvxVR:$Vu32, HvxVR:$Vv32),
32190"$Vd32 = vavgub($Vu32,$Vv32)",
32191PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32192let hasNewValue = 1;
32193let opNewValue = 0;
32194let isCVI = 1;
32195let isPseudo = 1;
32196let isCodeGenOnly = 1;
32197let DecoderNamespace = "EXT_mmvec";
32198}
32199def V6_vavgubrnd : HInst<
32200(outs HvxVR:$Vd32),
32201(ins HvxVR:$Vu32, HvxVR:$Vv32),
32202"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
32203tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32204let Inst{7-5} = 0b011;
32205let Inst{13-13} = 0b0;
32206let Inst{31-21} = 0b00011100111;
32207let hasNewValue = 1;
32208let opNewValue = 0;
32209let isCVI = 1;
32210let isHVXALU = 1;
32211let isHVXALU2SRC = 1;
32212let DecoderNamespace = "EXT_mmvec";
32213}
32214def V6_vavgubrnd_alt : HInst<
32215(outs HvxVR:$Vd32),
32216(ins HvxVR:$Vu32, HvxVR:$Vv32),
32217"$Vd32 = vavgub($Vu32,$Vv32):rnd",
32218PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32219let hasNewValue = 1;
32220let opNewValue = 0;
32221let isCVI = 1;
32222let isPseudo = 1;
32223let isCodeGenOnly = 1;
32224let DecoderNamespace = "EXT_mmvec";
32225}
32226def V6_vavguh : HInst<
32227(outs HvxVR:$Vd32),
32228(ins HvxVR:$Vu32, HvxVR:$Vv32),
32229"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
32230tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32231let Inst{7-5} = 0b101;
32232let Inst{13-13} = 0b0;
32233let Inst{31-21} = 0b00011100110;
32234let hasNewValue = 1;
32235let opNewValue = 0;
32236let isCVI = 1;
32237let isHVXALU = 1;
32238let isHVXALU2SRC = 1;
32239let DecoderNamespace = "EXT_mmvec";
32240}
32241def V6_vavguh_alt : HInst<
32242(outs HvxVR:$Vd32),
32243(ins HvxVR:$Vu32, HvxVR:$Vv32),
32244"$Vd32 = vavguh($Vu32,$Vv32)",
32245PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32246let hasNewValue = 1;
32247let opNewValue = 0;
32248let isCVI = 1;
32249let isPseudo = 1;
32250let isCodeGenOnly = 1;
32251let DecoderNamespace = "EXT_mmvec";
32252}
32253def V6_vavguhrnd : HInst<
32254(outs HvxVR:$Vd32),
32255(ins HvxVR:$Vu32, HvxVR:$Vv32),
32256"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
32257tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32258let Inst{7-5} = 0b100;
32259let Inst{13-13} = 0b0;
32260let Inst{31-21} = 0b00011100111;
32261let hasNewValue = 1;
32262let opNewValue = 0;
32263let isCVI = 1;
32264let isHVXALU = 1;
32265let isHVXALU2SRC = 1;
32266let DecoderNamespace = "EXT_mmvec";
32267}
32268def V6_vavguhrnd_alt : HInst<
32269(outs HvxVR:$Vd32),
32270(ins HvxVR:$Vu32, HvxVR:$Vv32),
32271"$Vd32 = vavguh($Vu32,$Vv32):rnd",
32272PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32273let hasNewValue = 1;
32274let opNewValue = 0;
32275let isCVI = 1;
32276let isPseudo = 1;
32277let isCodeGenOnly = 1;
32278let DecoderNamespace = "EXT_mmvec";
32279}
32280def V6_vavguw : HInst<
32281(outs HvxVR:$Vd32),
32282(ins HvxVR:$Vu32, HvxVR:$Vv32),
32283"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
32284tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32285let Inst{7-5} = 0b010;
32286let Inst{13-13} = 0b1;
32287let Inst{31-21} = 0b00011111000;
32288let hasNewValue = 1;
32289let opNewValue = 0;
32290let isCVI = 1;
32291let isHVXALU = 1;
32292let isHVXALU2SRC = 1;
32293let DecoderNamespace = "EXT_mmvec";
32294}
32295def V6_vavguw_alt : HInst<
32296(outs HvxVR:$Vd32),
32297(ins HvxVR:$Vu32, HvxVR:$Vv32),
32298"$Vd32 = vavguw($Vu32,$Vv32)",
32299PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32300let hasNewValue = 1;
32301let opNewValue = 0;
32302let isCVI = 1;
32303let isPseudo = 1;
32304let isCodeGenOnly = 1;
32305let DecoderNamespace = "EXT_mmvec";
32306}
32307def V6_vavguwrnd : HInst<
32308(outs HvxVR:$Vd32),
32309(ins HvxVR:$Vu32, HvxVR:$Vv32),
32310"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
32311tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32312let Inst{7-5} = 0b011;
32313let Inst{13-13} = 0b1;
32314let Inst{31-21} = 0b00011111000;
32315let hasNewValue = 1;
32316let opNewValue = 0;
32317let isCVI = 1;
32318let isHVXALU = 1;
32319let isHVXALU2SRC = 1;
32320let DecoderNamespace = "EXT_mmvec";
32321}
32322def V6_vavguwrnd_alt : HInst<
32323(outs HvxVR:$Vd32),
32324(ins HvxVR:$Vu32, HvxVR:$Vv32),
32325"$Vd32 = vavguw($Vu32,$Vv32):rnd",
32326PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32327let hasNewValue = 1;
32328let opNewValue = 0;
32329let isCVI = 1;
32330let isPseudo = 1;
32331let isCodeGenOnly = 1;
32332let DecoderNamespace = "EXT_mmvec";
32333}
32334def V6_vavgw : HInst<
32335(outs HvxVR:$Vd32),
32336(ins HvxVR:$Vu32, HvxVR:$Vv32),
32337"$Vd32.w = vavg($Vu32.w,$Vv32.w)",
32338tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32339let Inst{7-5} = 0b111;
32340let Inst{13-13} = 0b0;
32341let Inst{31-21} = 0b00011100110;
32342let hasNewValue = 1;
32343let opNewValue = 0;
32344let isCVI = 1;
32345let isHVXALU = 1;
32346let isHVXALU2SRC = 1;
32347let DecoderNamespace = "EXT_mmvec";
32348}
32349def V6_vavgw_alt : HInst<
32350(outs HvxVR:$Vd32),
32351(ins HvxVR:$Vu32, HvxVR:$Vv32),
32352"$Vd32 = vavgw($Vu32,$Vv32)",
32353PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32354let hasNewValue = 1;
32355let opNewValue = 0;
32356let isCVI = 1;
32357let isPseudo = 1;
32358let isCodeGenOnly = 1;
32359let DecoderNamespace = "EXT_mmvec";
32360}
32361def V6_vavgwrnd : HInst<
32362(outs HvxVR:$Vd32),
32363(ins HvxVR:$Vu32, HvxVR:$Vv32),
32364"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
32365tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32366let Inst{7-5} = 0b110;
32367let Inst{13-13} = 0b0;
32368let Inst{31-21} = 0b00011100111;
32369let hasNewValue = 1;
32370let opNewValue = 0;
32371let isCVI = 1;
32372let isHVXALU = 1;
32373let isHVXALU2SRC = 1;
32374let DecoderNamespace = "EXT_mmvec";
32375}
32376def V6_vavgwrnd_alt : HInst<
32377(outs HvxVR:$Vd32),
32378(ins HvxVR:$Vu32, HvxVR:$Vv32),
32379"$Vd32 = vavgw($Vu32,$Vv32):rnd",
32380PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32381let hasNewValue = 1;
32382let opNewValue = 0;
32383let isCVI = 1;
32384let isPseudo = 1;
32385let isCodeGenOnly = 1;
32386let DecoderNamespace = "EXT_mmvec";
32387}
32388def V6_vccombine : HInst<
32389(outs HvxWR:$Vdd32),
32390(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
32391"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
32392tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
32393let Inst{7-7} = 0b0;
32394let Inst{13-13} = 0b0;
32395let Inst{31-21} = 0b00011010011;
32396let isPredicated = 1;
32397let hasNewValue = 1;
32398let opNewValue = 0;
32399let isCVI = 1;
32400let DecoderNamespace = "EXT_mmvec";
32401}
32402def V6_vcl0h : HInst<
32403(outs HvxVR:$Vd32),
32404(ins HvxVR:$Vu32),
32405"$Vd32.uh = vcl0($Vu32.uh)",
32406tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
32407let Inst{7-5} = 0b111;
32408let Inst{13-13} = 0b0;
32409let Inst{31-16} = 0b0001111000000010;
32410let hasNewValue = 1;
32411let opNewValue = 0;
32412let isCVI = 1;
32413let DecoderNamespace = "EXT_mmvec";
32414}
32415def V6_vcl0h_alt : HInst<
32416(outs HvxVR:$Vd32),
32417(ins HvxVR:$Vu32),
32418"$Vd32 = vcl0h($Vu32)",
32419PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32420let hasNewValue = 1;
32421let opNewValue = 0;
32422let isCVI = 1;
32423let isPseudo = 1;
32424let isCodeGenOnly = 1;
32425let DecoderNamespace = "EXT_mmvec";
32426}
32427def V6_vcl0w : HInst<
32428(outs HvxVR:$Vd32),
32429(ins HvxVR:$Vu32),
32430"$Vd32.uw = vcl0($Vu32.uw)",
32431tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
32432let Inst{7-5} = 0b101;
32433let Inst{13-13} = 0b0;
32434let Inst{31-16} = 0b0001111000000010;
32435let hasNewValue = 1;
32436let opNewValue = 0;
32437let isCVI = 1;
32438let DecoderNamespace = "EXT_mmvec";
32439}
32440def V6_vcl0w_alt : HInst<
32441(outs HvxVR:$Vd32),
32442(ins HvxVR:$Vu32),
32443"$Vd32 = vcl0w($Vu32)",
32444PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32445let hasNewValue = 1;
32446let opNewValue = 0;
32447let isCVI = 1;
32448let isPseudo = 1;
32449let isCodeGenOnly = 1;
32450let DecoderNamespace = "EXT_mmvec";
32451}
32452def V6_vcmov : HInst<
32453(outs HvxVR:$Vd32),
32454(ins PredRegs:$Ps4, HvxVR:$Vu32),
32455"if ($Ps4) $Vd32 = $Vu32",
32456tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
32457let Inst{7-7} = 0b0;
32458let Inst{13-13} = 0b0;
32459let Inst{31-16} = 0b0001101000000000;
32460let isPredicated = 1;
32461let hasNewValue = 1;
32462let opNewValue = 0;
32463let isCVI = 1;
32464let isHVXALU = 1;
32465let DecoderNamespace = "EXT_mmvec";
32466}
32467def V6_vcombine : HInst<
32468(outs HvxWR:$Vdd32),
32469(ins HvxVR:$Vu32, HvxVR:$Vv32),
32470"$Vdd32 = vcombine($Vu32,$Vv32)",
32471tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
32472let Inst{7-5} = 0b111;
32473let Inst{13-13} = 0b0;
32474let Inst{31-21} = 0b00011111010;
32475let hasNewValue = 1;
32476let opNewValue = 0;
32477let isCVI = 1;
32478let isRegSequence = 1;
32479let DecoderNamespace = "EXT_mmvec";
32480}
32481def V6_vcombine_tmp : HInst<
32482(outs HvxWR:$Vdd32),
32483(ins HvxVR:$Vu32, HvxVR:$Vv32),
32484"$Vdd32.tmp = vcombine($Vu32,$Vv32)",
32485tc_531b383c, TypeCVI_VX>, Enc_71bb9b, Requires<[UseHVXV69]> {
32486let Inst{7-5} = 0b111;
32487let Inst{13-13} = 0b0;
32488let Inst{31-21} = 0b00011110101;
32489let hasNewValue = 1;
32490let opNewValue = 0;
32491let isCVI = 1;
32492let hasHvxTmp = 1;
32493let DecoderNamespace = "EXT_mmvec";
32494}
32495def V6_vconv_h_hf : HInst<
32496(outs HvxVR:$Vd32),
32497(ins HvxVR:$Vu32),
32498"$Vd32.h = $Vu32.hf",
32499tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32500let Inst{7-5} = 0b010;
32501let Inst{13-13} = 0b1;
32502let Inst{31-16} = 0b0001111000000101;
32503let hasNewValue = 1;
32504let opNewValue = 0;
32505let isCVI = 1;
32506let DecoderNamespace = "EXT_mmvec";
32507}
32508def V6_vconv_hf_h : HInst<
32509(outs HvxVR:$Vd32),
32510(ins HvxVR:$Vu32),
32511"$Vd32.hf = $Vu32.h",
32512tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32513let Inst{7-5} = 0b100;
32514let Inst{13-13} = 0b1;
32515let Inst{31-16} = 0b0001111000000101;
32516let hasNewValue = 1;
32517let opNewValue = 0;
32518let isCVI = 1;
32519let DecoderNamespace = "EXT_mmvec";
32520}
32521def V6_vconv_hf_qf16 : HInst<
32522(outs HvxVR:$Vd32),
32523(ins HvxVR:$Vu32),
32524"$Vd32.hf = $Vu32.qf16",
32525tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV68,UseHVXQFloat]> {
32526let Inst{7-5} = 0b011;
32527let Inst{13-13} = 0b1;
32528let Inst{31-16} = 0b0001111000000100;
32529let hasNewValue = 1;
32530let opNewValue = 0;
32531let isCVI = 1;
32532let DecoderNamespace = "EXT_mmvec";
32533}
32534def V6_vconv_hf_qf32 : HInst<
32535(outs HvxVR:$Vd32),
32536(ins HvxWR:$Vuu32),
32537"$Vd32.hf = $Vuu32.qf32",
32538tc_51d0ecc3, TypeCVI_VS>, Enc_a33d04, Requires<[UseHVXV68,UseHVXQFloat]> {
32539let Inst{7-5} = 0b110;
32540let Inst{13-13} = 0b1;
32541let Inst{31-16} = 0b0001111000000100;
32542let hasNewValue = 1;
32543let opNewValue = 0;
32544let isCVI = 1;
32545let DecoderNamespace = "EXT_mmvec";
32546}
32547def V6_vconv_sf_qf32 : HInst<
32548(outs HvxVR:$Vd32),
32549(ins HvxVR:$Vu32),
32550"$Vd32.sf = $Vu32.qf32",
32551tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV68,UseHVXQFloat]> {
32552let Inst{7-5} = 0b000;
32553let Inst{13-13} = 0b1;
32554let Inst{31-16} = 0b0001111000000100;
32555let hasNewValue = 1;
32556let opNewValue = 0;
32557let isCVI = 1;
32558let DecoderNamespace = "EXT_mmvec";
32559}
32560def V6_vconv_sf_w : HInst<
32561(outs HvxVR:$Vd32),
32562(ins HvxVR:$Vu32),
32563"$Vd32.sf = $Vu32.w",
32564tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32565let Inst{7-5} = 0b011;
32566let Inst{13-13} = 0b1;
32567let Inst{31-16} = 0b0001111000000101;
32568let hasNewValue = 1;
32569let opNewValue = 0;
32570let isCVI = 1;
32571let DecoderNamespace = "EXT_mmvec";
32572}
32573def V6_vconv_w_sf : HInst<
32574(outs HvxVR:$Vd32),
32575(ins HvxVR:$Vu32),
32576"$Vd32.w = $Vu32.sf",
32577tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32578let Inst{7-5} = 0b001;
32579let Inst{13-13} = 0b1;
32580let Inst{31-16} = 0b0001111000000101;
32581let hasNewValue = 1;
32582let opNewValue = 0;
32583let isCVI = 1;
32584let DecoderNamespace = "EXT_mmvec";
32585}
32586def V6_vcvt_b_hf : HInst<
32587(outs HvxVR:$Vd32),
32588(ins HvxVR:$Vu32, HvxVR:$Vv32),
32589"$Vd32.b = vcvt($Vu32.hf,$Vv32.hf)",
32590tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32591let Inst{7-5} = 0b110;
32592let Inst{13-13} = 0b1;
32593let Inst{31-21} = 0b00011111110;
32594let hasNewValue = 1;
32595let opNewValue = 0;
32596let isCVI = 1;
32597let DecoderNamespace = "EXT_mmvec";
32598}
32599def V6_vcvt_bf_sf : HInst<
32600(outs HvxVR:$Vd32),
32601(ins HvxVR:$Vu32, HvxVR:$Vv32),
32602"$Vd32.bf = vcvt($Vu32.sf,$Vv32.sf)",
32603tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV73,UseHVXIEEEFP]> {
32604let Inst{7-5} = 0b011;
32605let Inst{13-13} = 0b1;
32606let Inst{31-21} = 0b00011101010;
32607let hasNewValue = 1;
32608let opNewValue = 0;
32609let isCVI = 1;
32610let DecoderNamespace = "EXT_mmvec";
32611}
32612def V6_vcvt_h_hf : HInst<
32613(outs HvxVR:$Vd32),
32614(ins HvxVR:$Vu32),
32615"$Vd32.h = vcvt($Vu32.hf)",
32616tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32617let Inst{7-5} = 0b000;
32618let Inst{13-13} = 0b1;
32619let Inst{31-16} = 0b0001111000000110;
32620let hasNewValue = 1;
32621let opNewValue = 0;
32622let isCVI = 1;
32623let DecoderNamespace = "EXT_mmvec";
32624}
32625def V6_vcvt_hf_b : HInst<
32626(outs HvxWR:$Vdd32),
32627(ins HvxVR:$Vu32),
32628"$Vdd32.hf = vcvt($Vu32.b)",
32629tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32630let Inst{7-5} = 0b010;
32631let Inst{13-13} = 0b1;
32632let Inst{31-16} = 0b0001111000000100;
32633let hasNewValue = 1;
32634let opNewValue = 0;
32635let isCVI = 1;
32636let DecoderNamespace = "EXT_mmvec";
32637}
32638def V6_vcvt_hf_h : HInst<
32639(outs HvxVR:$Vd32),
32640(ins HvxVR:$Vu32),
32641"$Vd32.hf = vcvt($Vu32.h)",
32642tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32643let Inst{7-5} = 0b111;
32644let Inst{13-13} = 0b1;
32645let Inst{31-16} = 0b0001111000000100;
32646let hasNewValue = 1;
32647let opNewValue = 0;
32648let isCVI = 1;
32649let DecoderNamespace = "EXT_mmvec";
32650}
32651def V6_vcvt_hf_sf : HInst<
32652(outs HvxVR:$Vd32),
32653(ins HvxVR:$Vu32, HvxVR:$Vv32),
32654"$Vd32.hf = vcvt($Vu32.sf,$Vv32.sf)",
32655tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32656let Inst{7-5} = 0b001;
32657let Inst{13-13} = 0b1;
32658let Inst{31-21} = 0b00011111011;
32659let hasNewValue = 1;
32660let opNewValue = 0;
32661let isCVI = 1;
32662let DecoderNamespace = "EXT_mmvec";
32663}
32664def V6_vcvt_hf_ub : HInst<
32665(outs HvxWR:$Vdd32),
32666(ins HvxVR:$Vu32),
32667"$Vdd32.hf = vcvt($Vu32.ub)",
32668tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32669let Inst{7-5} = 0b001;
32670let Inst{13-13} = 0b1;
32671let Inst{31-16} = 0b0001111000000100;
32672let hasNewValue = 1;
32673let opNewValue = 0;
32674let isCVI = 1;
32675let DecoderNamespace = "EXT_mmvec";
32676}
32677def V6_vcvt_hf_uh : HInst<
32678(outs HvxVR:$Vd32),
32679(ins HvxVR:$Vu32),
32680"$Vd32.hf = vcvt($Vu32.uh)",
32681tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32682let Inst{7-5} = 0b101;
32683let Inst{13-13} = 0b1;
32684let Inst{31-16} = 0b0001111000000100;
32685let hasNewValue = 1;
32686let opNewValue = 0;
32687let isCVI = 1;
32688let DecoderNamespace = "EXT_mmvec";
32689}
32690def V6_vcvt_sf_hf : HInst<
32691(outs HvxWR:$Vdd32),
32692(ins HvxVR:$Vu32),
32693"$Vdd32.sf = vcvt($Vu32.hf)",
32694tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32695let Inst{7-5} = 0b100;
32696let Inst{13-13} = 0b1;
32697let Inst{31-16} = 0b0001111000000100;
32698let hasNewValue = 1;
32699let opNewValue = 0;
32700let isCVI = 1;
32701let DecoderNamespace = "EXT_mmvec";
32702}
32703def V6_vcvt_ub_hf : HInst<
32704(outs HvxVR:$Vd32),
32705(ins HvxVR:$Vu32, HvxVR:$Vv32),
32706"$Vd32.ub = vcvt($Vu32.hf,$Vv32.hf)",
32707tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32708let Inst{7-5} = 0b101;
32709let Inst{13-13} = 0b1;
32710let Inst{31-21} = 0b00011111110;
32711let hasNewValue = 1;
32712let opNewValue = 0;
32713let isCVI = 1;
32714let DecoderNamespace = "EXT_mmvec";
32715}
32716def V6_vcvt_uh_hf : HInst<
32717(outs HvxVR:$Vd32),
32718(ins HvxVR:$Vu32),
32719"$Vd32.uh = vcvt($Vu32.hf)",
32720tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32721let Inst{7-5} = 0b000;
32722let Inst{13-13} = 0b1;
32723let Inst{31-16} = 0b0001111000000101;
32724let hasNewValue = 1;
32725let opNewValue = 0;
32726let isCVI = 1;
32727let DecoderNamespace = "EXT_mmvec";
32728}
32729def V6_vd0 : HInst<
32730(outs HvxVR:$Vd32),
32731(ins),
32732"$Vd32 = #0",
32733CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
32734let hasNewValue = 1;
32735let opNewValue = 0;
32736let isCVI = 1;
32737let isPseudo = 1;
32738let isCodeGenOnly = 1;
32739let DecoderNamespace = "EXT_mmvec";
32740}
32741def V6_vdd0 : HInst<
32742(outs HvxWR:$Vdd32),
32743(ins),
32744"$Vdd32 = #0",
32745tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> {
32746let hasNewValue = 1;
32747let opNewValue = 0;
32748let isCVI = 1;
32749let isPseudo = 1;
32750let isCodeGenOnly = 1;
32751let DecoderNamespace = "EXT_mmvec";
32752}
32753def V6_vdeal : HInst<
32754(outs HvxVR:$Vy32, HvxVR:$Vx32),
32755(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
32756"vdeal($Vy32,$Vx32,$Rt32)",
32757tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
32758let Inst{7-5} = 0b010;
32759let Inst{13-13} = 0b1;
32760let Inst{31-21} = 0b00011001111;
32761let hasNewValue = 1;
32762let opNewValue = 0;
32763let hasNewValue2 = 1;
32764let opNewValue2 = 1;
32765let isCVI = 1;
32766let DecoderNamespace = "EXT_mmvec";
32767let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
32768}
32769def V6_vdealb : HInst<
32770(outs HvxVR:$Vd32),
32771(ins HvxVR:$Vu32),
32772"$Vd32.b = vdeal($Vu32.b)",
32773tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32774let Inst{7-5} = 0b111;
32775let Inst{13-13} = 0b0;
32776let Inst{31-16} = 0b0001111000000000;
32777let hasNewValue = 1;
32778let opNewValue = 0;
32779let isCVI = 1;
32780let DecoderNamespace = "EXT_mmvec";
32781}
32782def V6_vdealb4w : HInst<
32783(outs HvxVR:$Vd32),
32784(ins HvxVR:$Vu32, HvxVR:$Vv32),
32785"$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
32786tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32787let Inst{7-5} = 0b111;
32788let Inst{13-13} = 0b0;
32789let Inst{31-21} = 0b00011111001;
32790let hasNewValue = 1;
32791let opNewValue = 0;
32792let isCVI = 1;
32793let DecoderNamespace = "EXT_mmvec";
32794}
32795def V6_vdealb4w_alt : HInst<
32796(outs HvxVR:$Vd32),
32797(ins HvxVR:$Vu32, HvxVR:$Vv32),
32798"$Vd32 = vdealb4w($Vu32,$Vv32)",
32799PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32800let hasNewValue = 1;
32801let opNewValue = 0;
32802let isCVI = 1;
32803let isPseudo = 1;
32804let isCodeGenOnly = 1;
32805let DecoderNamespace = "EXT_mmvec";
32806}
32807def V6_vdealb_alt : HInst<
32808(outs HvxVR:$Vd32),
32809(ins HvxVR:$Vu32),
32810"$Vd32 = vdealb($Vu32)",
32811PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32812let hasNewValue = 1;
32813let opNewValue = 0;
32814let isCVI = 1;
32815let isPseudo = 1;
32816let isCodeGenOnly = 1;
32817let DecoderNamespace = "EXT_mmvec";
32818}
32819def V6_vdealh : HInst<
32820(outs HvxVR:$Vd32),
32821(ins HvxVR:$Vu32),
32822"$Vd32.h = vdeal($Vu32.h)",
32823tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32824let Inst{7-5} = 0b110;
32825let Inst{13-13} = 0b0;
32826let Inst{31-16} = 0b0001111000000000;
32827let hasNewValue = 1;
32828let opNewValue = 0;
32829let isCVI = 1;
32830let DecoderNamespace = "EXT_mmvec";
32831}
32832def V6_vdealh_alt : HInst<
32833(outs HvxVR:$Vd32),
32834(ins HvxVR:$Vu32),
32835"$Vd32 = vdealh($Vu32)",
32836PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32837let hasNewValue = 1;
32838let opNewValue = 0;
32839let isCVI = 1;
32840let isPseudo = 1;
32841let isCodeGenOnly = 1;
32842let DecoderNamespace = "EXT_mmvec";
32843}
32844def V6_vdealvdd : HInst<
32845(outs HvxWR:$Vdd32),
32846(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32847"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
32848tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
32849let Inst{7-5} = 0b100;
32850let Inst{13-13} = 0b1;
32851let Inst{31-24} = 0b00011011;
32852let hasNewValue = 1;
32853let opNewValue = 0;
32854let isCVI = 1;
32855let DecoderNamespace = "EXT_mmvec";
32856}
32857def V6_vdelta : HInst<
32858(outs HvxVR:$Vd32),
32859(ins HvxVR:$Vu32, HvxVR:$Vv32),
32860"$Vd32 = vdelta($Vu32,$Vv32)",
32861tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32862let Inst{7-5} = 0b001;
32863let Inst{13-13} = 0b0;
32864let Inst{31-21} = 0b00011111001;
32865let hasNewValue = 1;
32866let opNewValue = 0;
32867let isCVI = 1;
32868let DecoderNamespace = "EXT_mmvec";
32869}
32870def V6_vdmpy_sf_hf : HInst<
32871(outs HvxVR:$Vd32),
32872(ins HvxVR:$Vu32, HvxVR:$Vv32),
32873"$Vd32.sf = vdmpy($Vu32.hf,$Vv32.hf)",
32874tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32875let Inst{7-5} = 0b110;
32876let Inst{13-13} = 0b1;
32877let Inst{31-21} = 0b00011111101;
32878let hasNewValue = 1;
32879let opNewValue = 0;
32880let isCVI = 1;
32881let DecoderNamespace = "EXT_mmvec";
32882}
32883def V6_vdmpy_sf_hf_acc : HInst<
32884(outs HvxVR:$Vx32),
32885(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
32886"$Vx32.sf += vdmpy($Vu32.hf,$Vv32.hf)",
32887tc_a19b9305, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32888let Inst{7-5} = 0b011;
32889let Inst{13-13} = 0b1;
32890let Inst{31-21} = 0b00011100010;
32891let hasNewValue = 1;
32892let opNewValue = 0;
32893let isAccumulator = 1;
32894let isCVI = 1;
32895let DecoderNamespace = "EXT_mmvec";
32896let Constraints = "$Vx32 = $Vx32in";
32897}
32898def V6_vdmpybus : HInst<
32899(outs HvxVR:$Vd32),
32900(ins HvxVR:$Vu32, IntRegs:$Rt32),
32901"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
32902tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32903let Inst{7-5} = 0b110;
32904let Inst{13-13} = 0b0;
32905let Inst{31-21} = 0b00011001000;
32906let hasNewValue = 1;
32907let opNewValue = 0;
32908let isCVI = 1;
32909let DecoderNamespace = "EXT_mmvec";
32910}
32911def V6_vdmpybus_acc : HInst<
32912(outs HvxVR:$Vx32),
32913(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32914"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
32915tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32916let Inst{7-5} = 0b110;
32917let Inst{13-13} = 0b1;
32918let Inst{31-21} = 0b00011001000;
32919let hasNewValue = 1;
32920let opNewValue = 0;
32921let isAccumulator = 1;
32922let isCVI = 1;
32923let DecoderNamespace = "EXT_mmvec";
32924let Constraints = "$Vx32 = $Vx32in";
32925}
32926def V6_vdmpybus_acc_alt : HInst<
32927(outs HvxVR:$Vx32),
32928(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32929"$Vx32 += vdmpybus($Vu32,$Rt32)",
32930PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32931let hasNewValue = 1;
32932let opNewValue = 0;
32933let isAccumulator = 1;
32934let isCVI = 1;
32935let isPseudo = 1;
32936let isCodeGenOnly = 1;
32937let DecoderNamespace = "EXT_mmvec";
32938let Constraints = "$Vx32 = $Vx32in";
32939}
32940def V6_vdmpybus_alt : HInst<
32941(outs HvxVR:$Vd32),
32942(ins HvxVR:$Vu32, IntRegs:$Rt32),
32943"$Vd32 = vdmpybus($Vu32,$Rt32)",
32944PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32945let hasNewValue = 1;
32946let opNewValue = 0;
32947let isCVI = 1;
32948let isPseudo = 1;
32949let isCodeGenOnly = 1;
32950let DecoderNamespace = "EXT_mmvec";
32951}
32952def V6_vdmpybus_dv : HInst<
32953(outs HvxWR:$Vdd32),
32954(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32955"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
32956tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32957let Inst{7-5} = 0b111;
32958let Inst{13-13} = 0b0;
32959let Inst{31-21} = 0b00011001000;
32960let hasNewValue = 1;
32961let opNewValue = 0;
32962let isCVI = 1;
32963let DecoderNamespace = "EXT_mmvec";
32964}
32965def V6_vdmpybus_dv_acc : HInst<
32966(outs HvxWR:$Vxx32),
32967(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32968"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
32969tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32970let Inst{7-5} = 0b111;
32971let Inst{13-13} = 0b1;
32972let Inst{31-21} = 0b00011001000;
32973let hasNewValue = 1;
32974let opNewValue = 0;
32975let isAccumulator = 1;
32976let isCVI = 1;
32977let DecoderNamespace = "EXT_mmvec";
32978let Constraints = "$Vxx32 = $Vxx32in";
32979}
32980def V6_vdmpybus_dv_acc_alt : HInst<
32981(outs HvxWR:$Vxx32),
32982(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32983"$Vxx32 += vdmpybus($Vuu32,$Rt32)",
32984PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32985let hasNewValue = 1;
32986let opNewValue = 0;
32987let isAccumulator = 1;
32988let isCVI = 1;
32989let isPseudo = 1;
32990let isCodeGenOnly = 1;
32991let DecoderNamespace = "EXT_mmvec";
32992let Constraints = "$Vxx32 = $Vxx32in";
32993}
32994def V6_vdmpybus_dv_alt : HInst<
32995(outs HvxWR:$Vdd32),
32996(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32997"$Vdd32 = vdmpybus($Vuu32,$Rt32)",
32998PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32999let hasNewValue = 1;
33000let opNewValue = 0;
33001let isCVI = 1;
33002let isPseudo = 1;
33003let isCodeGenOnly = 1;
33004let DecoderNamespace = "EXT_mmvec";
33005}
33006def V6_vdmpyhb : HInst<
33007(outs HvxVR:$Vd32),
33008(ins HvxVR:$Vu32, IntRegs:$Rt32),
33009"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
33010tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33011let Inst{7-5} = 0b010;
33012let Inst{13-13} = 0b0;
33013let Inst{31-21} = 0b00011001000;
33014let hasNewValue = 1;
33015let opNewValue = 0;
33016let isCVI = 1;
33017let DecoderNamespace = "EXT_mmvec";
33018}
33019def V6_vdmpyhb_acc : HInst<
33020(outs HvxVR:$Vx32),
33021(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33022"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
33023tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33024let Inst{7-5} = 0b011;
33025let Inst{13-13} = 0b1;
33026let Inst{31-21} = 0b00011001000;
33027let hasNewValue = 1;
33028let opNewValue = 0;
33029let isAccumulator = 1;
33030let isCVI = 1;
33031let DecoderNamespace = "EXT_mmvec";
33032let Constraints = "$Vx32 = $Vx32in";
33033}
33034def V6_vdmpyhb_acc_alt : HInst<
33035(outs HvxVR:$Vx32),
33036(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33037"$Vx32 += vdmpyhb($Vu32,$Rt32)",
33038PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33039let hasNewValue = 1;
33040let opNewValue = 0;
33041let isAccumulator = 1;
33042let isCVI = 1;
33043let isPseudo = 1;
33044let isCodeGenOnly = 1;
33045let DecoderNamespace = "EXT_mmvec";
33046let Constraints = "$Vx32 = $Vx32in";
33047}
33048def V6_vdmpyhb_alt : HInst<
33049(outs HvxVR:$Vd32),
33050(ins HvxVR:$Vu32, IntRegs:$Rt32),
33051"$Vd32 = vdmpyhb($Vu32,$Rt32)",
33052PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33053let hasNewValue = 1;
33054let opNewValue = 0;
33055let isCVI = 1;
33056let isPseudo = 1;
33057let isCodeGenOnly = 1;
33058let DecoderNamespace = "EXT_mmvec";
33059}
33060def V6_vdmpyhb_dv : HInst<
33061(outs HvxWR:$Vdd32),
33062(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33063"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
33064tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33065let Inst{7-5} = 0b100;
33066let Inst{13-13} = 0b0;
33067let Inst{31-21} = 0b00011001001;
33068let hasNewValue = 1;
33069let opNewValue = 0;
33070let isCVI = 1;
33071let DecoderNamespace = "EXT_mmvec";
33072}
33073def V6_vdmpyhb_dv_acc : HInst<
33074(outs HvxWR:$Vxx32),
33075(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33076"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
33077tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33078let Inst{7-5} = 0b100;
33079let Inst{13-13} = 0b1;
33080let Inst{31-21} = 0b00011001001;
33081let hasNewValue = 1;
33082let opNewValue = 0;
33083let isAccumulator = 1;
33084let isCVI = 1;
33085let DecoderNamespace = "EXT_mmvec";
33086let Constraints = "$Vxx32 = $Vxx32in";
33087}
33088def V6_vdmpyhb_dv_acc_alt : HInst<
33089(outs HvxWR:$Vxx32),
33090(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33091"$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
33092PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33093let hasNewValue = 1;
33094let opNewValue = 0;
33095let isAccumulator = 1;
33096let isCVI = 1;
33097let isPseudo = 1;
33098let isCodeGenOnly = 1;
33099let DecoderNamespace = "EXT_mmvec";
33100let Constraints = "$Vxx32 = $Vxx32in";
33101}
33102def V6_vdmpyhb_dv_alt : HInst<
33103(outs HvxWR:$Vdd32),
33104(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33105"$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
33106PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33107let hasNewValue = 1;
33108let opNewValue = 0;
33109let isCVI = 1;
33110let isPseudo = 1;
33111let isCodeGenOnly = 1;
33112let DecoderNamespace = "EXT_mmvec";
33113}
33114def V6_vdmpyhisat : HInst<
33115(outs HvxVR:$Vd32),
33116(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33117"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
33118tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
33119let Inst{7-5} = 0b011;
33120let Inst{13-13} = 0b0;
33121let Inst{31-21} = 0b00011001001;
33122let hasNewValue = 1;
33123let opNewValue = 0;
33124let isCVI = 1;
33125let DecoderNamespace = "EXT_mmvec";
33126}
33127def V6_vdmpyhisat_acc : HInst<
33128(outs HvxVR:$Vx32),
33129(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33130"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
33131tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
33132let Inst{7-5} = 0b010;
33133let Inst{13-13} = 0b1;
33134let Inst{31-21} = 0b00011001001;
33135let hasNewValue = 1;
33136let opNewValue = 0;
33137let isAccumulator = 1;
33138let isCVI = 1;
33139let DecoderNamespace = "EXT_mmvec";
33140let Constraints = "$Vx32 = $Vx32in";
33141}
33142def V6_vdmpyhisat_acc_alt : HInst<
33143(outs HvxVR:$Vx32),
33144(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33145"$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
33146PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33147let hasNewValue = 1;
33148let opNewValue = 0;
33149let isAccumulator = 1;
33150let isCVI = 1;
33151let isPseudo = 1;
33152let isCodeGenOnly = 1;
33153let DecoderNamespace = "EXT_mmvec";
33154let Constraints = "$Vx32 = $Vx32in";
33155}
33156def V6_vdmpyhisat_alt : HInst<
33157(outs HvxVR:$Vd32),
33158(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33159"$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
33160PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33161let hasNewValue = 1;
33162let opNewValue = 0;
33163let isCVI = 1;
33164let isPseudo = 1;
33165let isCodeGenOnly = 1;
33166let DecoderNamespace = "EXT_mmvec";
33167}
33168def V6_vdmpyhsat : HInst<
33169(outs HvxVR:$Vd32),
33170(ins HvxVR:$Vu32, IntRegs:$Rt32),
33171"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
33172tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33173let Inst{7-5} = 0b010;
33174let Inst{13-13} = 0b0;
33175let Inst{31-21} = 0b00011001001;
33176let hasNewValue = 1;
33177let opNewValue = 0;
33178let isCVI = 1;
33179let DecoderNamespace = "EXT_mmvec";
33180}
33181def V6_vdmpyhsat_acc : HInst<
33182(outs HvxVR:$Vx32),
33183(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33184"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
33185tc_72e2b393, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33186let Inst{7-5} = 0b011;
33187let Inst{13-13} = 0b1;
33188let Inst{31-21} = 0b00011001001;
33189let hasNewValue = 1;
33190let opNewValue = 0;
33191let isAccumulator = 1;
33192let isCVI = 1;
33193let DecoderNamespace = "EXT_mmvec";
33194let Constraints = "$Vx32 = $Vx32in";
33195}
33196def V6_vdmpyhsat_acc_alt : HInst<
33197(outs HvxVR:$Vx32),
33198(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33199"$Vx32 += vdmpyh($Vu32,$Rt32):sat",
33200PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33201let hasNewValue = 1;
33202let opNewValue = 0;
33203let isAccumulator = 1;
33204let isCVI = 1;
33205let isPseudo = 1;
33206let isCodeGenOnly = 1;
33207let DecoderNamespace = "EXT_mmvec";
33208let Constraints = "$Vx32 = $Vx32in";
33209}
33210def V6_vdmpyhsat_alt : HInst<
33211(outs HvxVR:$Vd32),
33212(ins HvxVR:$Vu32, IntRegs:$Rt32),
33213"$Vd32 = vdmpyh($Vu32,$Rt32):sat",
33214PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33215let hasNewValue = 1;
33216let opNewValue = 0;
33217let isCVI = 1;
33218let isPseudo = 1;
33219let isCodeGenOnly = 1;
33220let DecoderNamespace = "EXT_mmvec";
33221}
33222def V6_vdmpyhsuisat : HInst<
33223(outs HvxVR:$Vd32),
33224(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33225"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
33226tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
33227let Inst{7-5} = 0b001;
33228let Inst{13-13} = 0b0;
33229let Inst{31-21} = 0b00011001001;
33230let hasNewValue = 1;
33231let opNewValue = 0;
33232let isCVI = 1;
33233let DecoderNamespace = "EXT_mmvec";
33234}
33235def V6_vdmpyhsuisat_acc : HInst<
33236(outs HvxVR:$Vx32),
33237(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33238"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
33239tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
33240let Inst{7-5} = 0b001;
33241let Inst{13-13} = 0b1;
33242let Inst{31-21} = 0b00011001001;
33243let hasNewValue = 1;
33244let opNewValue = 0;
33245let isAccumulator = 1;
33246let isCVI = 1;
33247let DecoderNamespace = "EXT_mmvec";
33248let Constraints = "$Vx32 = $Vx32in";
33249}
33250def V6_vdmpyhsuisat_acc_alt : HInst<
33251(outs HvxVR:$Vx32),
33252(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33253"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
33254PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33255let hasNewValue = 1;
33256let opNewValue = 0;
33257let isAccumulator = 1;
33258let isCVI = 1;
33259let isPseudo = 1;
33260let isCodeGenOnly = 1;
33261let DecoderNamespace = "EXT_mmvec";
33262let Constraints = "$Vx32 = $Vx32in";
33263}
33264def V6_vdmpyhsuisat_alt : HInst<
33265(outs HvxVR:$Vd32),
33266(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33267"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
33268PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33269let hasNewValue = 1;
33270let opNewValue = 0;
33271let isCVI = 1;
33272let isPseudo = 1;
33273let isCodeGenOnly = 1;
33274let DecoderNamespace = "EXT_mmvec";
33275}
33276def V6_vdmpyhsusat : HInst<
33277(outs HvxVR:$Vd32),
33278(ins HvxVR:$Vu32, IntRegs:$Rt32),
33279"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
33280tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33281let Inst{7-5} = 0b000;
33282let Inst{13-13} = 0b0;
33283let Inst{31-21} = 0b00011001001;
33284let hasNewValue = 1;
33285let opNewValue = 0;
33286let isCVI = 1;
33287let DecoderNamespace = "EXT_mmvec";
33288}
33289def V6_vdmpyhsusat_acc : HInst<
33290(outs HvxVR:$Vx32),
33291(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33292"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
33293tc_72e2b393, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33294let Inst{7-5} = 0b000;
33295let Inst{13-13} = 0b1;
33296let Inst{31-21} = 0b00011001001;
33297let hasNewValue = 1;
33298let opNewValue = 0;
33299let isAccumulator = 1;
33300let isCVI = 1;
33301let DecoderNamespace = "EXT_mmvec";
33302let Constraints = "$Vx32 = $Vx32in";
33303}
33304def V6_vdmpyhsusat_acc_alt : HInst<
33305(outs HvxVR:$Vx32),
33306(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33307"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
33308PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33309let hasNewValue = 1;
33310let opNewValue = 0;
33311let isAccumulator = 1;
33312let isCVI = 1;
33313let isPseudo = 1;
33314let isCodeGenOnly = 1;
33315let DecoderNamespace = "EXT_mmvec";
33316let Constraints = "$Vx32 = $Vx32in";
33317}
33318def V6_vdmpyhsusat_alt : HInst<
33319(outs HvxVR:$Vd32),
33320(ins HvxVR:$Vu32, IntRegs:$Rt32),
33321"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
33322PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33323let hasNewValue = 1;
33324let opNewValue = 0;
33325let isCVI = 1;
33326let isPseudo = 1;
33327let isCodeGenOnly = 1;
33328let DecoderNamespace = "EXT_mmvec";
33329}
33330def V6_vdmpyhvsat : HInst<
33331(outs HvxVR:$Vd32),
33332(ins HvxVR:$Vu32, HvxVR:$Vv32),
33333"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
33334tc_73efe966, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
33335let Inst{7-5} = 0b011;
33336let Inst{13-13} = 0b0;
33337let Inst{31-21} = 0b00011100000;
33338let hasNewValue = 1;
33339let opNewValue = 0;
33340let isCVI = 1;
33341let DecoderNamespace = "EXT_mmvec";
33342}
33343def V6_vdmpyhvsat_acc : HInst<
33344(outs HvxVR:$Vx32),
33345(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33346"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
33347tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33348let Inst{7-5} = 0b011;
33349let Inst{13-13} = 0b1;
33350let Inst{31-21} = 0b00011100000;
33351let hasNewValue = 1;
33352let opNewValue = 0;
33353let isAccumulator = 1;
33354let isCVI = 1;
33355let DecoderNamespace = "EXT_mmvec";
33356let Constraints = "$Vx32 = $Vx32in";
33357}
33358def V6_vdmpyhvsat_acc_alt : HInst<
33359(outs HvxVR:$Vx32),
33360(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33361"$Vx32 += vdmpyh($Vu32,$Vv32):sat",
33362PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33363let hasNewValue = 1;
33364let opNewValue = 0;
33365let isAccumulator = 1;
33366let isCVI = 1;
33367let isPseudo = 1;
33368let isCodeGenOnly = 1;
33369let DecoderNamespace = "EXT_mmvec";
33370let Constraints = "$Vx32 = $Vx32in";
33371}
33372def V6_vdmpyhvsat_alt : HInst<
33373(outs HvxVR:$Vd32),
33374(ins HvxVR:$Vu32, HvxVR:$Vv32),
33375"$Vd32 = vdmpyh($Vu32,$Vv32):sat",
33376PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33377let hasNewValue = 1;
33378let opNewValue = 0;
33379let isCVI = 1;
33380let isPseudo = 1;
33381let isCodeGenOnly = 1;
33382let DecoderNamespace = "EXT_mmvec";
33383}
33384def V6_vdsaduh : HInst<
33385(outs HvxWR:$Vdd32),
33386(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33387"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
33388tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33389let Inst{7-5} = 0b101;
33390let Inst{13-13} = 0b0;
33391let Inst{31-21} = 0b00011001000;
33392let hasNewValue = 1;
33393let opNewValue = 0;
33394let isCVI = 1;
33395let DecoderNamespace = "EXT_mmvec";
33396}
33397def V6_vdsaduh_acc : HInst<
33398(outs HvxWR:$Vxx32),
33399(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33400"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
33401tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33402let Inst{7-5} = 0b000;
33403let Inst{13-13} = 0b1;
33404let Inst{31-21} = 0b00011001011;
33405let hasNewValue = 1;
33406let opNewValue = 0;
33407let isAccumulator = 1;
33408let isCVI = 1;
33409let DecoderNamespace = "EXT_mmvec";
33410let Constraints = "$Vxx32 = $Vxx32in";
33411}
33412def V6_vdsaduh_acc_alt : HInst<
33413(outs HvxWR:$Vxx32),
33414(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33415"$Vxx32 += vdsaduh($Vuu32,$Rt32)",
33416PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33417let hasNewValue = 1;
33418let opNewValue = 0;
33419let isAccumulator = 1;
33420let isCVI = 1;
33421let isPseudo = 1;
33422let isCodeGenOnly = 1;
33423let DecoderNamespace = "EXT_mmvec";
33424let Constraints = "$Vxx32 = $Vxx32in";
33425}
33426def V6_vdsaduh_alt : HInst<
33427(outs HvxWR:$Vdd32),
33428(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33429"$Vdd32 = vdsaduh($Vuu32,$Rt32)",
33430PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33431let hasNewValue = 1;
33432let opNewValue = 0;
33433let isCVI = 1;
33434let isPseudo = 1;
33435let isCodeGenOnly = 1;
33436let DecoderNamespace = "EXT_mmvec";
33437}
33438def V6_veqb : HInst<
33439(outs HvxQR:$Qd4),
33440(ins HvxVR:$Vu32, HvxVR:$Vv32),
33441"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
33442tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33443let Inst{7-2} = 0b000000;
33444let Inst{13-13} = 0b0;
33445let Inst{31-21} = 0b00011111100;
33446let hasNewValue = 1;
33447let opNewValue = 0;
33448let isCVI = 1;
33449let isHVXALU = 1;
33450let isHVXALU2SRC = 1;
33451let DecoderNamespace = "EXT_mmvec";
33452}
33453def V6_veqb_and : HInst<
33454(outs HvxQR:$Qx4),
33455(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33456"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
33457tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33458let Inst{7-2} = 0b000000;
33459let Inst{13-13} = 0b1;
33460let Inst{31-21} = 0b00011100100;
33461let isCVI = 1;
33462let isHVXALU = 1;
33463let isHVXALU2SRC = 1;
33464let DecoderNamespace = "EXT_mmvec";
33465let Constraints = "$Qx4 = $Qx4in";
33466}
33467def V6_veqb_or : HInst<
33468(outs HvxQR:$Qx4),
33469(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33470"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
33471tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33472let Inst{7-2} = 0b010000;
33473let Inst{13-13} = 0b1;
33474let Inst{31-21} = 0b00011100100;
33475let isAccumulator = 1;
33476let isCVI = 1;
33477let isHVXALU = 1;
33478let isHVXALU2SRC = 1;
33479let DecoderNamespace = "EXT_mmvec";
33480let Constraints = "$Qx4 = $Qx4in";
33481}
33482def V6_veqb_xor : HInst<
33483(outs HvxQR:$Qx4),
33484(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33485"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
33486tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33487let Inst{7-2} = 0b100000;
33488let Inst{13-13} = 0b1;
33489let Inst{31-21} = 0b00011100100;
33490let isCVI = 1;
33491let isHVXALU = 1;
33492let isHVXALU2SRC = 1;
33493let DecoderNamespace = "EXT_mmvec";
33494let Constraints = "$Qx4 = $Qx4in";
33495}
33496def V6_veqh : HInst<
33497(outs HvxQR:$Qd4),
33498(ins HvxVR:$Vu32, HvxVR:$Vv32),
33499"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
33500tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33501let Inst{7-2} = 0b000001;
33502let Inst{13-13} = 0b0;
33503let Inst{31-21} = 0b00011111100;
33504let hasNewValue = 1;
33505let opNewValue = 0;
33506let isCVI = 1;
33507let isHVXALU = 1;
33508let isHVXALU2SRC = 1;
33509let DecoderNamespace = "EXT_mmvec";
33510}
33511def V6_veqh_and : HInst<
33512(outs HvxQR:$Qx4),
33513(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33514"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
33515tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33516let Inst{7-2} = 0b000001;
33517let Inst{13-13} = 0b1;
33518let Inst{31-21} = 0b00011100100;
33519let isCVI = 1;
33520let isHVXALU = 1;
33521let isHVXALU2SRC = 1;
33522let DecoderNamespace = "EXT_mmvec";
33523let Constraints = "$Qx4 = $Qx4in";
33524}
33525def V6_veqh_or : HInst<
33526(outs HvxQR:$Qx4),
33527(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33528"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
33529tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33530let Inst{7-2} = 0b010001;
33531let Inst{13-13} = 0b1;
33532let Inst{31-21} = 0b00011100100;
33533let isAccumulator = 1;
33534let isCVI = 1;
33535let isHVXALU = 1;
33536let isHVXALU2SRC = 1;
33537let DecoderNamespace = "EXT_mmvec";
33538let Constraints = "$Qx4 = $Qx4in";
33539}
33540def V6_veqh_xor : HInst<
33541(outs HvxQR:$Qx4),
33542(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33543"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
33544tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33545let Inst{7-2} = 0b100001;
33546let Inst{13-13} = 0b1;
33547let Inst{31-21} = 0b00011100100;
33548let isCVI = 1;
33549let isHVXALU = 1;
33550let isHVXALU2SRC = 1;
33551let DecoderNamespace = "EXT_mmvec";
33552let Constraints = "$Qx4 = $Qx4in";
33553}
33554def V6_veqw : HInst<
33555(outs HvxQR:$Qd4),
33556(ins HvxVR:$Vu32, HvxVR:$Vv32),
33557"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
33558tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33559let Inst{7-2} = 0b000010;
33560let Inst{13-13} = 0b0;
33561let Inst{31-21} = 0b00011111100;
33562let hasNewValue = 1;
33563let opNewValue = 0;
33564let isCVI = 1;
33565let isHVXALU = 1;
33566let isHVXALU2SRC = 1;
33567let DecoderNamespace = "EXT_mmvec";
33568}
33569def V6_veqw_and : HInst<
33570(outs HvxQR:$Qx4),
33571(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33572"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
33573tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33574let Inst{7-2} = 0b000010;
33575let Inst{13-13} = 0b1;
33576let Inst{31-21} = 0b00011100100;
33577let isCVI = 1;
33578let isHVXALU = 1;
33579let isHVXALU2SRC = 1;
33580let DecoderNamespace = "EXT_mmvec";
33581let Constraints = "$Qx4 = $Qx4in";
33582}
33583def V6_veqw_or : HInst<
33584(outs HvxQR:$Qx4),
33585(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33586"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
33587tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33588let Inst{7-2} = 0b010010;
33589let Inst{13-13} = 0b1;
33590let Inst{31-21} = 0b00011100100;
33591let isAccumulator = 1;
33592let isCVI = 1;
33593let isHVXALU = 1;
33594let isHVXALU2SRC = 1;
33595let DecoderNamespace = "EXT_mmvec";
33596let Constraints = "$Qx4 = $Qx4in";
33597}
33598def V6_veqw_xor : HInst<
33599(outs HvxQR:$Qx4),
33600(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33601"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
33602tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33603let Inst{7-2} = 0b100010;
33604let Inst{13-13} = 0b1;
33605let Inst{31-21} = 0b00011100100;
33606let isCVI = 1;
33607let isHVXALU = 1;
33608let isHVXALU2SRC = 1;
33609let DecoderNamespace = "EXT_mmvec";
33610let Constraints = "$Qx4 = $Qx4in";
33611}
33612def V6_vfmax_hf : HInst<
33613(outs HvxVR:$Vd32),
33614(ins HvxVR:$Vu32, HvxVR:$Vv32),
33615"$Vd32.hf = vfmax($Vu32.hf,$Vv32.hf)",
33616tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33617let Inst{7-5} = 0b010;
33618let Inst{13-13} = 0b1;
33619let Inst{31-21} = 0b00011100011;
33620let hasNewValue = 1;
33621let opNewValue = 0;
33622let isCVI = 1;
33623let DecoderNamespace = "EXT_mmvec";
33624}
33625def V6_vfmax_sf : HInst<
33626(outs HvxVR:$Vd32),
33627(ins HvxVR:$Vu32, HvxVR:$Vv32),
33628"$Vd32.sf = vfmax($Vu32.sf,$Vv32.sf)",
33629tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33630let Inst{7-5} = 0b011;
33631let Inst{13-13} = 0b1;
33632let Inst{31-21} = 0b00011100011;
33633let hasNewValue = 1;
33634let opNewValue = 0;
33635let isCVI = 1;
33636let DecoderNamespace = "EXT_mmvec";
33637}
33638def V6_vfmin_hf : HInst<
33639(outs HvxVR:$Vd32),
33640(ins HvxVR:$Vu32, HvxVR:$Vv32),
33641"$Vd32.hf = vfmin($Vu32.hf,$Vv32.hf)",
33642tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33643let Inst{7-5} = 0b000;
33644let Inst{13-13} = 0b1;
33645let Inst{31-21} = 0b00011100011;
33646let hasNewValue = 1;
33647let opNewValue = 0;
33648let isCVI = 1;
33649let DecoderNamespace = "EXT_mmvec";
33650}
33651def V6_vfmin_sf : HInst<
33652(outs HvxVR:$Vd32),
33653(ins HvxVR:$Vu32, HvxVR:$Vv32),
33654"$Vd32.sf = vfmin($Vu32.sf,$Vv32.sf)",
33655tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33656let Inst{7-5} = 0b001;
33657let Inst{13-13} = 0b1;
33658let Inst{31-21} = 0b00011100011;
33659let hasNewValue = 1;
33660let opNewValue = 0;
33661let isCVI = 1;
33662let DecoderNamespace = "EXT_mmvec";
33663}
33664def V6_vfneg_hf : HInst<
33665(outs HvxVR:$Vd32),
33666(ins HvxVR:$Vu32),
33667"$Vd32.hf = vfneg($Vu32.hf)",
33668tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33669let Inst{7-5} = 0b010;
33670let Inst{13-13} = 0b1;
33671let Inst{31-16} = 0b0001111000000110;
33672let hasNewValue = 1;
33673let opNewValue = 0;
33674let isCVI = 1;
33675let DecoderNamespace = "EXT_mmvec";
33676}
33677def V6_vfneg_sf : HInst<
33678(outs HvxVR:$Vd32),
33679(ins HvxVR:$Vu32),
33680"$Vd32.sf = vfneg($Vu32.sf)",
33681tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33682let Inst{7-5} = 0b011;
33683let Inst{13-13} = 0b1;
33684let Inst{31-16} = 0b0001111000000110;
33685let hasNewValue = 1;
33686let opNewValue = 0;
33687let isCVI = 1;
33688let DecoderNamespace = "EXT_mmvec";
33689}
33690def V6_vgathermh : HInst<
33691(outs),
33692(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33693"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33694tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
33695let Inst{12-5} = 0b00001000;
33696let Inst{31-21} = 0b00101111000;
33697let hasNewValue = 1;
33698let opNewValue = 0;
33699let accessSize = HalfWordAccess;
33700let isCVLoad = 1;
33701let isCVI = 1;
33702let isHVXALU = 1;
33703let mayLoad = 1;
33704let Defs = [VTMP];
33705let DecoderNamespace = "EXT_mmvec";
33706}
33707def V6_vgathermhq : HInst<
33708(outs),
33709(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33710"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33711tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
33712let Inst{12-7} = 0b001010;
33713let Inst{31-21} = 0b00101111000;
33714let hasNewValue = 1;
33715let opNewValue = 0;
33716let accessSize = HalfWordAccess;
33717let isCVLoad = 1;
33718let isCVI = 1;
33719let isHVXALU = 1;
33720let mayLoad = 1;
33721let Defs = [VTMP];
33722let DecoderNamespace = "EXT_mmvec";
33723}
33724def V6_vgathermhw : HInst<
33725(outs),
33726(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
33727"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33728tc_7095ecba, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> {
33729let Inst{12-5} = 0b00010000;
33730let Inst{31-21} = 0b00101111000;
33731let hasNewValue = 1;
33732let opNewValue = 0;
33733let accessSize = HalfWordAccess;
33734let isCVLoad = 1;
33735let isCVI = 1;
33736let mayLoad = 1;
33737let Defs = [VTMP];
33738let DecoderNamespace = "EXT_mmvec";
33739}
33740def V6_vgathermhwq : HInst<
33741(outs),
33742(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
33743"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33744tc_a69eeee1, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> {
33745let Inst{12-7} = 0b001100;
33746let Inst{31-21} = 0b00101111000;
33747let hasNewValue = 1;
33748let opNewValue = 0;
33749let accessSize = HalfWordAccess;
33750let isCVLoad = 1;
33751let isCVI = 1;
33752let mayLoad = 1;
33753let Defs = [VTMP];
33754let DecoderNamespace = "EXT_mmvec";
33755}
33756def V6_vgathermw : HInst<
33757(outs),
33758(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33759"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
33760tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
33761let Inst{12-5} = 0b00000000;
33762let Inst{31-21} = 0b00101111000;
33763let hasNewValue = 1;
33764let opNewValue = 0;
33765let accessSize = WordAccess;
33766let isCVLoad = 1;
33767let isCVI = 1;
33768let isHVXALU = 1;
33769let mayLoad = 1;
33770let Defs = [VTMP];
33771let DecoderNamespace = "EXT_mmvec";
33772}
33773def V6_vgathermwq : HInst<
33774(outs),
33775(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33776"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
33777tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
33778let Inst{12-7} = 0b001000;
33779let Inst{31-21} = 0b00101111000;
33780let hasNewValue = 1;
33781let opNewValue = 0;
33782let accessSize = WordAccess;
33783let isCVLoad = 1;
33784let isCVI = 1;
33785let isHVXALU = 1;
33786let mayLoad = 1;
33787let Defs = [VTMP];
33788let DecoderNamespace = "EXT_mmvec";
33789}
33790def V6_vgtb : HInst<
33791(outs HvxQR:$Qd4),
33792(ins HvxVR:$Vu32, HvxVR:$Vv32),
33793"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
33794tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33795let Inst{7-2} = 0b000100;
33796let Inst{13-13} = 0b0;
33797let Inst{31-21} = 0b00011111100;
33798let hasNewValue = 1;
33799let opNewValue = 0;
33800let isCVI = 1;
33801let isHVXALU = 1;
33802let isHVXALU2SRC = 1;
33803let DecoderNamespace = "EXT_mmvec";
33804}
33805def V6_vgtb_and : HInst<
33806(outs HvxQR:$Qx4),
33807(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33808"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
33809tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33810let Inst{7-2} = 0b000100;
33811let Inst{13-13} = 0b1;
33812let Inst{31-21} = 0b00011100100;
33813let isCVI = 1;
33814let isHVXALU = 1;
33815let isHVXALU2SRC = 1;
33816let DecoderNamespace = "EXT_mmvec";
33817let Constraints = "$Qx4 = $Qx4in";
33818}
33819def V6_vgtb_or : HInst<
33820(outs HvxQR:$Qx4),
33821(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33822"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
33823tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33824let Inst{7-2} = 0b010100;
33825let Inst{13-13} = 0b1;
33826let Inst{31-21} = 0b00011100100;
33827let isAccumulator = 1;
33828let isCVI = 1;
33829let isHVXALU = 1;
33830let isHVXALU2SRC = 1;
33831let DecoderNamespace = "EXT_mmvec";
33832let Constraints = "$Qx4 = $Qx4in";
33833}
33834def V6_vgtb_xor : HInst<
33835(outs HvxQR:$Qx4),
33836(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33837"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
33838tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33839let Inst{7-2} = 0b100100;
33840let Inst{13-13} = 0b1;
33841let Inst{31-21} = 0b00011100100;
33842let isCVI = 1;
33843let isHVXALU = 1;
33844let isHVXALU2SRC = 1;
33845let DecoderNamespace = "EXT_mmvec";
33846let Constraints = "$Qx4 = $Qx4in";
33847}
33848def V6_vgtbf : HInst<
33849(outs HvxQR:$Qd4),
33850(ins HvxVR:$Vu32, HvxVR:$Vv32),
33851"$Qd4 = vcmp.gt($Vu32.bf,$Vv32.bf)",
33852tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV73,UseHVXQFloat]> {
33853let Inst{7-2} = 0b011110;
33854let Inst{13-13} = 0b1;
33855let Inst{31-21} = 0b00011100100;
33856let hasNewValue = 1;
33857let opNewValue = 0;
33858let isCVI = 1;
33859let isHVXALU = 1;
33860let isHVXALU2SRC = 1;
33861let DecoderNamespace = "EXT_mmvec";
33862}
33863def V6_vgtbf_and : HInst<
33864(outs HvxQR:$Qx4),
33865(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33866"$Qx4 &= vcmp.gt($Vu32.bf,$Vv32.bf)",
33867tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV73,UseHVXQFloat]> {
33868let Inst{7-2} = 0b110100;
33869let Inst{13-13} = 0b1;
33870let Inst{31-21} = 0b00011100100;
33871let isCVI = 1;
33872let isHVXALU = 1;
33873let isHVXALU2SRC = 1;
33874let DecoderNamespace = "EXT_mmvec";
33875let Constraints = "$Qx4 = $Qx4in";
33876}
33877def V6_vgtbf_or : HInst<
33878(outs HvxQR:$Qx4),
33879(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33880"$Qx4 |= vcmp.gt($Vu32.bf,$Vv32.bf)",
33881tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV73,UseHVXQFloat]> {
33882let Inst{7-2} = 0b001110;
33883let Inst{13-13} = 0b1;
33884let Inst{31-21} = 0b00011100100;
33885let isAccumulator = 1;
33886let isCVI = 1;
33887let isHVXALU = 1;
33888let isHVXALU2SRC = 1;
33889let DecoderNamespace = "EXT_mmvec";
33890let Constraints = "$Qx4 = $Qx4in";
33891}
33892def V6_vgtbf_xor : HInst<
33893(outs HvxQR:$Qx4),
33894(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33895"$Qx4 ^= vcmp.gt($Vu32.bf,$Vv32.bf)",
33896tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV73,UseHVXQFloat]> {
33897let Inst{7-2} = 0b111100;
33898let Inst{13-13} = 0b1;
33899let Inst{31-21} = 0b00011100100;
33900let isCVI = 1;
33901let isHVXALU = 1;
33902let isHVXALU2SRC = 1;
33903let DecoderNamespace = "EXT_mmvec";
33904let Constraints = "$Qx4 = $Qx4in";
33905}
33906def V6_vgth : HInst<
33907(outs HvxQR:$Qd4),
33908(ins HvxVR:$Vu32, HvxVR:$Vv32),
33909"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
33910tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33911let Inst{7-2} = 0b000101;
33912let Inst{13-13} = 0b0;
33913let Inst{31-21} = 0b00011111100;
33914let hasNewValue = 1;
33915let opNewValue = 0;
33916let isCVI = 1;
33917let isHVXALU = 1;
33918let isHVXALU2SRC = 1;
33919let DecoderNamespace = "EXT_mmvec";
33920}
33921def V6_vgth_and : HInst<
33922(outs HvxQR:$Qx4),
33923(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33924"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
33925tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33926let Inst{7-2} = 0b000101;
33927let Inst{13-13} = 0b1;
33928let Inst{31-21} = 0b00011100100;
33929let isCVI = 1;
33930let isHVXALU = 1;
33931let isHVXALU2SRC = 1;
33932let DecoderNamespace = "EXT_mmvec";
33933let Constraints = "$Qx4 = $Qx4in";
33934}
33935def V6_vgth_or : HInst<
33936(outs HvxQR:$Qx4),
33937(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33938"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
33939tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33940let Inst{7-2} = 0b010101;
33941let Inst{13-13} = 0b1;
33942let Inst{31-21} = 0b00011100100;
33943let isAccumulator = 1;
33944let isCVI = 1;
33945let isHVXALU = 1;
33946let isHVXALU2SRC = 1;
33947let DecoderNamespace = "EXT_mmvec";
33948let Constraints = "$Qx4 = $Qx4in";
33949}
33950def V6_vgth_xor : HInst<
33951(outs HvxQR:$Qx4),
33952(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33953"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
33954tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33955let Inst{7-2} = 0b100101;
33956let Inst{13-13} = 0b1;
33957let Inst{31-21} = 0b00011100100;
33958let isCVI = 1;
33959let isHVXALU = 1;
33960let isHVXALU2SRC = 1;
33961let DecoderNamespace = "EXT_mmvec";
33962let Constraints = "$Qx4 = $Qx4in";
33963}
33964def V6_vgthf : HInst<
33965(outs HvxQR:$Qd4),
33966(ins HvxVR:$Vu32, HvxVR:$Vv32),
33967"$Qd4 = vcmp.gt($Vu32.hf,$Vv32.hf)",
33968tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33969let Inst{7-2} = 0b011101;
33970let Inst{13-13} = 0b1;
33971let Inst{31-21} = 0b00011100100;
33972let hasNewValue = 1;
33973let opNewValue = 0;
33974let isCVI = 1;
33975let isHVXALU = 1;
33976let isHVXALU2SRC = 1;
33977let DecoderNamespace = "EXT_mmvec";
33978}
33979def V6_vgthf_and : HInst<
33980(outs HvxQR:$Qx4),
33981(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33982"$Qx4 &= vcmp.gt($Vu32.hf,$Vv32.hf)",
33983tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33984let Inst{7-2} = 0b110011;
33985let Inst{13-13} = 0b1;
33986let Inst{31-21} = 0b00011100100;
33987let isCVI = 1;
33988let isHVXALU = 1;
33989let isHVXALU2SRC = 1;
33990let DecoderNamespace = "EXT_mmvec";
33991let Constraints = "$Qx4 = $Qx4in";
33992}
33993def V6_vgthf_or : HInst<
33994(outs HvxQR:$Qx4),
33995(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33996"$Qx4 |= vcmp.gt($Vu32.hf,$Vv32.hf)",
33997tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33998let Inst{7-2} = 0b001101;
33999let Inst{13-13} = 0b1;
34000let Inst{31-21} = 0b00011100100;
34001let isAccumulator = 1;
34002let isCVI = 1;
34003let isHVXALU = 1;
34004let isHVXALU2SRC = 1;
34005let DecoderNamespace = "EXT_mmvec";
34006let Constraints = "$Qx4 = $Qx4in";
34007}
34008def V6_vgthf_xor : HInst<
34009(outs HvxQR:$Qx4),
34010(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34011"$Qx4 ^= vcmp.gt($Vu32.hf,$Vv32.hf)",
34012tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34013let Inst{7-2} = 0b111011;
34014let Inst{13-13} = 0b1;
34015let Inst{31-21} = 0b00011100100;
34016let isCVI = 1;
34017let isHVXALU = 1;
34018let isHVXALU2SRC = 1;
34019let DecoderNamespace = "EXT_mmvec";
34020let Constraints = "$Qx4 = $Qx4in";
34021}
34022def V6_vgtsf : HInst<
34023(outs HvxQR:$Qd4),
34024(ins HvxVR:$Vu32, HvxVR:$Vv32),
34025"$Qd4 = vcmp.gt($Vu32.sf,$Vv32.sf)",
34026tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34027let Inst{7-2} = 0b011100;
34028let Inst{13-13} = 0b1;
34029let Inst{31-21} = 0b00011100100;
34030let hasNewValue = 1;
34031let opNewValue = 0;
34032let isCVI = 1;
34033let isHVXALU = 1;
34034let isHVXALU2SRC = 1;
34035let DecoderNamespace = "EXT_mmvec";
34036}
34037def V6_vgtsf_and : HInst<
34038(outs HvxQR:$Qx4),
34039(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34040"$Qx4 &= vcmp.gt($Vu32.sf,$Vv32.sf)",
34041tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34042let Inst{7-2} = 0b110010;
34043let Inst{13-13} = 0b1;
34044let Inst{31-21} = 0b00011100100;
34045let isCVI = 1;
34046let isHVXALU = 1;
34047let isHVXALU2SRC = 1;
34048let DecoderNamespace = "EXT_mmvec";
34049let Constraints = "$Qx4 = $Qx4in";
34050}
34051def V6_vgtsf_or : HInst<
34052(outs HvxQR:$Qx4),
34053(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34054"$Qx4 |= vcmp.gt($Vu32.sf,$Vv32.sf)",
34055tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34056let Inst{7-2} = 0b001100;
34057let Inst{13-13} = 0b1;
34058let Inst{31-21} = 0b00011100100;
34059let isAccumulator = 1;
34060let isCVI = 1;
34061let isHVXALU = 1;
34062let isHVXALU2SRC = 1;
34063let DecoderNamespace = "EXT_mmvec";
34064let Constraints = "$Qx4 = $Qx4in";
34065}
34066def V6_vgtsf_xor : HInst<
34067(outs HvxQR:$Qx4),
34068(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34069"$Qx4 ^= vcmp.gt($Vu32.sf,$Vv32.sf)",
34070tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34071let Inst{7-2} = 0b111010;
34072let Inst{13-13} = 0b1;
34073let Inst{31-21} = 0b00011100100;
34074let isCVI = 1;
34075let isHVXALU = 1;
34076let isHVXALU2SRC = 1;
34077let DecoderNamespace = "EXT_mmvec";
34078let Constraints = "$Qx4 = $Qx4in";
34079}
34080def V6_vgtub : HInst<
34081(outs HvxQR:$Qd4),
34082(ins HvxVR:$Vu32, HvxVR:$Vv32),
34083"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
34084tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34085let Inst{7-2} = 0b001000;
34086let Inst{13-13} = 0b0;
34087let Inst{31-21} = 0b00011111100;
34088let hasNewValue = 1;
34089let opNewValue = 0;
34090let isCVI = 1;
34091let isHVXALU = 1;
34092let isHVXALU2SRC = 1;
34093let DecoderNamespace = "EXT_mmvec";
34094}
34095def V6_vgtub_and : HInst<
34096(outs HvxQR:$Qx4),
34097(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34098"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
34099tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34100let Inst{7-2} = 0b001000;
34101let Inst{13-13} = 0b1;
34102let Inst{31-21} = 0b00011100100;
34103let isCVI = 1;
34104let isHVXALU = 1;
34105let isHVXALU2SRC = 1;
34106let DecoderNamespace = "EXT_mmvec";
34107let Constraints = "$Qx4 = $Qx4in";
34108}
34109def V6_vgtub_or : HInst<
34110(outs HvxQR:$Qx4),
34111(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34112"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
34113tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34114let Inst{7-2} = 0b011000;
34115let Inst{13-13} = 0b1;
34116let Inst{31-21} = 0b00011100100;
34117let isAccumulator = 1;
34118let isCVI = 1;
34119let isHVXALU = 1;
34120let isHVXALU2SRC = 1;
34121let DecoderNamespace = "EXT_mmvec";
34122let Constraints = "$Qx4 = $Qx4in";
34123}
34124def V6_vgtub_xor : HInst<
34125(outs HvxQR:$Qx4),
34126(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34127"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
34128tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34129let Inst{7-2} = 0b101000;
34130let Inst{13-13} = 0b1;
34131let Inst{31-21} = 0b00011100100;
34132let isCVI = 1;
34133let isHVXALU = 1;
34134let isHVXALU2SRC = 1;
34135let DecoderNamespace = "EXT_mmvec";
34136let Constraints = "$Qx4 = $Qx4in";
34137}
34138def V6_vgtuh : HInst<
34139(outs HvxQR:$Qd4),
34140(ins HvxVR:$Vu32, HvxVR:$Vv32),
34141"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
34142tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34143let Inst{7-2} = 0b001001;
34144let Inst{13-13} = 0b0;
34145let Inst{31-21} = 0b00011111100;
34146let hasNewValue = 1;
34147let opNewValue = 0;
34148let isCVI = 1;
34149let isHVXALU = 1;
34150let isHVXALU2SRC = 1;
34151let DecoderNamespace = "EXT_mmvec";
34152}
34153def V6_vgtuh_and : HInst<
34154(outs HvxQR:$Qx4),
34155(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34156"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
34157tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34158let Inst{7-2} = 0b001001;
34159let Inst{13-13} = 0b1;
34160let Inst{31-21} = 0b00011100100;
34161let isCVI = 1;
34162let isHVXALU = 1;
34163let isHVXALU2SRC = 1;
34164let DecoderNamespace = "EXT_mmvec";
34165let Constraints = "$Qx4 = $Qx4in";
34166}
34167def V6_vgtuh_or : HInst<
34168(outs HvxQR:$Qx4),
34169(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34170"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
34171tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34172let Inst{7-2} = 0b011001;
34173let Inst{13-13} = 0b1;
34174let Inst{31-21} = 0b00011100100;
34175let isAccumulator = 1;
34176let isCVI = 1;
34177let isHVXALU = 1;
34178let isHVXALU2SRC = 1;
34179let DecoderNamespace = "EXT_mmvec";
34180let Constraints = "$Qx4 = $Qx4in";
34181}
34182def V6_vgtuh_xor : HInst<
34183(outs HvxQR:$Qx4),
34184(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34185"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
34186tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34187let Inst{7-2} = 0b101001;
34188let Inst{13-13} = 0b1;
34189let Inst{31-21} = 0b00011100100;
34190let isCVI = 1;
34191let isHVXALU = 1;
34192let isHVXALU2SRC = 1;
34193let DecoderNamespace = "EXT_mmvec";
34194let Constraints = "$Qx4 = $Qx4in";
34195}
34196def V6_vgtuw : HInst<
34197(outs HvxQR:$Qd4),
34198(ins HvxVR:$Vu32, HvxVR:$Vv32),
34199"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
34200tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34201let Inst{7-2} = 0b001010;
34202let Inst{13-13} = 0b0;
34203let Inst{31-21} = 0b00011111100;
34204let hasNewValue = 1;
34205let opNewValue = 0;
34206let isCVI = 1;
34207let isHVXALU = 1;
34208let isHVXALU2SRC = 1;
34209let DecoderNamespace = "EXT_mmvec";
34210}
34211def V6_vgtuw_and : HInst<
34212(outs HvxQR:$Qx4),
34213(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34214"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
34215tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34216let Inst{7-2} = 0b001010;
34217let Inst{13-13} = 0b1;
34218let Inst{31-21} = 0b00011100100;
34219let isCVI = 1;
34220let isHVXALU = 1;
34221let isHVXALU2SRC = 1;
34222let DecoderNamespace = "EXT_mmvec";
34223let Constraints = "$Qx4 = $Qx4in";
34224}
34225def V6_vgtuw_or : HInst<
34226(outs HvxQR:$Qx4),
34227(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34228"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
34229tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34230let Inst{7-2} = 0b011010;
34231let Inst{13-13} = 0b1;
34232let Inst{31-21} = 0b00011100100;
34233let isAccumulator = 1;
34234let isCVI = 1;
34235let isHVXALU = 1;
34236let isHVXALU2SRC = 1;
34237let DecoderNamespace = "EXT_mmvec";
34238let Constraints = "$Qx4 = $Qx4in";
34239}
34240def V6_vgtuw_xor : HInst<
34241(outs HvxQR:$Qx4),
34242(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34243"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
34244tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34245let Inst{7-2} = 0b101010;
34246let Inst{13-13} = 0b1;
34247let Inst{31-21} = 0b00011100100;
34248let isCVI = 1;
34249let isHVXALU = 1;
34250let isHVXALU2SRC = 1;
34251let DecoderNamespace = "EXT_mmvec";
34252let Constraints = "$Qx4 = $Qx4in";
34253}
34254def V6_vgtw : HInst<
34255(outs HvxQR:$Qd4),
34256(ins HvxVR:$Vu32, HvxVR:$Vv32),
34257"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
34258tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34259let Inst{7-2} = 0b000110;
34260let Inst{13-13} = 0b0;
34261let Inst{31-21} = 0b00011111100;
34262let hasNewValue = 1;
34263let opNewValue = 0;
34264let isCVI = 1;
34265let isHVXALU = 1;
34266let isHVXALU2SRC = 1;
34267let DecoderNamespace = "EXT_mmvec";
34268}
34269def V6_vgtw_and : HInst<
34270(outs HvxQR:$Qx4),
34271(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34272"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
34273tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34274let Inst{7-2} = 0b000110;
34275let Inst{13-13} = 0b1;
34276let Inst{31-21} = 0b00011100100;
34277let isCVI = 1;
34278let isHVXALU = 1;
34279let isHVXALU2SRC = 1;
34280let DecoderNamespace = "EXT_mmvec";
34281let Constraints = "$Qx4 = $Qx4in";
34282}
34283def V6_vgtw_or : HInst<
34284(outs HvxQR:$Qx4),
34285(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34286"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
34287tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34288let Inst{7-2} = 0b010110;
34289let Inst{13-13} = 0b1;
34290let Inst{31-21} = 0b00011100100;
34291let isAccumulator = 1;
34292let isCVI = 1;
34293let isHVXALU = 1;
34294let isHVXALU2SRC = 1;
34295let DecoderNamespace = "EXT_mmvec";
34296let Constraints = "$Qx4 = $Qx4in";
34297}
34298def V6_vgtw_xor : HInst<
34299(outs HvxQR:$Qx4),
34300(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34301"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
34302tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34303let Inst{7-2} = 0b100110;
34304let Inst{13-13} = 0b1;
34305let Inst{31-21} = 0b00011100100;
34306let isCVI = 1;
34307let isHVXALU = 1;
34308let isHVXALU2SRC = 1;
34309let DecoderNamespace = "EXT_mmvec";
34310let Constraints = "$Qx4 = $Qx4in";
34311}
34312def V6_vhist : HInst<
34313(outs),
34314(ins),
34315"vhist",
34316tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
34317let Inst{13-0} = 0b10000010000000;
34318let Inst{31-16} = 0b0001111000000000;
34319let isCVI = 1;
34320let DecoderNamespace = "EXT_mmvec";
34321}
34322def V6_vhistq : HInst<
34323(outs),
34324(ins HvxQR:$Qv4),
34325"vhist($Qv4)",
34326tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
34327let Inst{13-0} = 0b10000010000000;
34328let Inst{21-16} = 0b000010;
34329let Inst{31-24} = 0b00011110;
34330let isCVI = 1;
34331let DecoderNamespace = "EXT_mmvec";
34332}
34333def V6_vinsertwr : HInst<
34334(outs HvxVR:$Vx32),
34335(ins HvxVR:$Vx32in, IntRegs:$Rt32),
34336"$Vx32.w = vinsert($Rt32)",
34337tc_ac4046bc, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
34338let Inst{13-5} = 0b100000001;
34339let Inst{31-21} = 0b00011001101;
34340let hasNewValue = 1;
34341let opNewValue = 0;
34342let isCVI = 1;
34343let DecoderNamespace = "EXT_mmvec";
34344let Constraints = "$Vx32 = $Vx32in";
34345}
34346def V6_vlalignb : HInst<
34347(outs HvxVR:$Vd32),
34348(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34349"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
34350tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
34351let Inst{7-5} = 0b001;
34352let Inst{13-13} = 0b0;
34353let Inst{31-24} = 0b00011011;
34354let hasNewValue = 1;
34355let opNewValue = 0;
34356let isCVI = 1;
34357let DecoderNamespace = "EXT_mmvec";
34358}
34359def V6_vlalignbi : HInst<
34360(outs HvxVR:$Vd32),
34361(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34362"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
34363tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
34364let Inst{13-13} = 0b1;
34365let Inst{31-21} = 0b00011110011;
34366let hasNewValue = 1;
34367let opNewValue = 0;
34368let isCVI = 1;
34369let DecoderNamespace = "EXT_mmvec";
34370}
34371def V6_vlsrb : HInst<
34372(outs HvxVR:$Vd32),
34373(ins HvxVR:$Vu32, IntRegs:$Rt32),
34374"$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
34375tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
34376let Inst{7-5} = 0b011;
34377let Inst{13-13} = 0b0;
34378let Inst{31-21} = 0b00011001100;
34379let hasNewValue = 1;
34380let opNewValue = 0;
34381let isCVI = 1;
34382let DecoderNamespace = "EXT_mmvec";
34383}
34384def V6_vlsrh : HInst<
34385(outs HvxVR:$Vd32),
34386(ins HvxVR:$Vu32, IntRegs:$Rt32),
34387"$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
34388tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
34389let Inst{7-5} = 0b010;
34390let Inst{13-13} = 0b0;
34391let Inst{31-21} = 0b00011001100;
34392let hasNewValue = 1;
34393let opNewValue = 0;
34394let isCVI = 1;
34395let DecoderNamespace = "EXT_mmvec";
34396}
34397def V6_vlsrh_alt : HInst<
34398(outs HvxVR:$Vd32),
34399(ins HvxVR:$Vu32, IntRegs:$Rt32),
34400"$Vd32 = vlsrh($Vu32,$Rt32)",
34401PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34402let hasNewValue = 1;
34403let opNewValue = 0;
34404let isCVI = 1;
34405let isPseudo = 1;
34406let isCodeGenOnly = 1;
34407let DecoderNamespace = "EXT_mmvec";
34408}
34409def V6_vlsrhv : HInst<
34410(outs HvxVR:$Vd32),
34411(ins HvxVR:$Vu32, HvxVR:$Vv32),
34412"$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
34413tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
34414let Inst{7-5} = 0b010;
34415let Inst{13-13} = 0b0;
34416let Inst{31-21} = 0b00011111101;
34417let hasNewValue = 1;
34418let opNewValue = 0;
34419let isCVI = 1;
34420let DecoderNamespace = "EXT_mmvec";
34421}
34422def V6_vlsrhv_alt : HInst<
34423(outs HvxVR:$Vd32),
34424(ins HvxVR:$Vu32, HvxVR:$Vv32),
34425"$Vd32 = vlsrh($Vu32,$Vv32)",
34426PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34427let hasNewValue = 1;
34428let opNewValue = 0;
34429let isCVI = 1;
34430let isPseudo = 1;
34431let isCodeGenOnly = 1;
34432let DecoderNamespace = "EXT_mmvec";
34433}
34434def V6_vlsrw : HInst<
34435(outs HvxVR:$Vd32),
34436(ins HvxVR:$Vu32, IntRegs:$Rt32),
34437"$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
34438tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
34439let Inst{7-5} = 0b001;
34440let Inst{13-13} = 0b0;
34441let Inst{31-21} = 0b00011001100;
34442let hasNewValue = 1;
34443let opNewValue = 0;
34444let isCVI = 1;
34445let DecoderNamespace = "EXT_mmvec";
34446}
34447def V6_vlsrw_alt : HInst<
34448(outs HvxVR:$Vd32),
34449(ins HvxVR:$Vu32, IntRegs:$Rt32),
34450"$Vd32 = vlsrw($Vu32,$Rt32)",
34451PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34452let hasNewValue = 1;
34453let opNewValue = 0;
34454let isCVI = 1;
34455let isPseudo = 1;
34456let isCodeGenOnly = 1;
34457let DecoderNamespace = "EXT_mmvec";
34458}
34459def V6_vlsrwv : HInst<
34460(outs HvxVR:$Vd32),
34461(ins HvxVR:$Vu32, HvxVR:$Vv32),
34462"$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
34463tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
34464let Inst{7-5} = 0b001;
34465let Inst{13-13} = 0b0;
34466let Inst{31-21} = 0b00011111101;
34467let hasNewValue = 1;
34468let opNewValue = 0;
34469let isCVI = 1;
34470let DecoderNamespace = "EXT_mmvec";
34471}
34472def V6_vlsrwv_alt : HInst<
34473(outs HvxVR:$Vd32),
34474(ins HvxVR:$Vu32, HvxVR:$Vv32),
34475"$Vd32 = vlsrw($Vu32,$Vv32)",
34476PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34477let hasNewValue = 1;
34478let opNewValue = 0;
34479let isCVI = 1;
34480let isPseudo = 1;
34481let isCodeGenOnly = 1;
34482let DecoderNamespace = "EXT_mmvec";
34483}
34484def V6_vlut4 : HInst<
34485(outs HvxVR:$Vd32),
34486(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34487"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
34488tc_f1de44ef, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
34489let Inst{7-5} = 0b100;
34490let Inst{13-13} = 0b0;
34491let Inst{31-21} = 0b00011001011;
34492let hasNewValue = 1;
34493let opNewValue = 0;
34494let isCVI = 1;
34495let DecoderNamespace = "EXT_mmvec";
34496}
34497def V6_vlutvvb : HInst<
34498(outs HvxVR:$Vd32),
34499(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34500"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
34501tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
34502let Inst{7-5} = 0b001;
34503let Inst{13-13} = 0b1;
34504let Inst{31-24} = 0b00011011;
34505let hasNewValue = 1;
34506let opNewValue = 0;
34507let isCVI = 1;
34508let DecoderNamespace = "EXT_mmvec";
34509}
34510def V6_vlutvvb_nm : HInst<
34511(outs HvxVR:$Vd32),
34512(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34513"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
34514tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
34515let Inst{7-5} = 0b011;
34516let Inst{13-13} = 0b0;
34517let Inst{31-24} = 0b00011000;
34518let hasNewValue = 1;
34519let opNewValue = 0;
34520let isCVI = 1;
34521let DecoderNamespace = "EXT_mmvec";
34522}
34523def V6_vlutvvb_oracc : HInst<
34524(outs HvxVR:$Vx32),
34525(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34526"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
34527tc_9d1dc972, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
34528let Inst{7-5} = 0b101;
34529let Inst{13-13} = 0b1;
34530let Inst{31-24} = 0b00011011;
34531let hasNewValue = 1;
34532let opNewValue = 0;
34533let isAccumulator = 1;
34534let isCVI = 1;
34535let DecoderNamespace = "EXT_mmvec";
34536let Constraints = "$Vx32 = $Vx32in";
34537}
34538def V6_vlutvvb_oracci : HInst<
34539(outs HvxVR:$Vx32),
34540(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34541"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
34542tc_9d1dc972, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
34543let Inst{13-13} = 0b1;
34544let Inst{31-21} = 0b00011100110;
34545let hasNewValue = 1;
34546let opNewValue = 0;
34547let isAccumulator = 1;
34548let isCVI = 1;
34549let DecoderNamespace = "EXT_mmvec";
34550let Constraints = "$Vx32 = $Vx32in";
34551}
34552def V6_vlutvvbi : HInst<
34553(outs HvxVR:$Vd32),
34554(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34555"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
34556tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
34557let Inst{13-13} = 0b0;
34558let Inst{31-21} = 0b00011110001;
34559let hasNewValue = 1;
34560let opNewValue = 0;
34561let isCVI = 1;
34562let DecoderNamespace = "EXT_mmvec";
34563}
34564def V6_vlutvwh : HInst<
34565(outs HvxWR:$Vdd32),
34566(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34567"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
34568tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
34569let Inst{7-5} = 0b110;
34570let Inst{13-13} = 0b1;
34571let Inst{31-24} = 0b00011011;
34572let hasNewValue = 1;
34573let opNewValue = 0;
34574let isCVI = 1;
34575let DecoderNamespace = "EXT_mmvec";
34576}
34577def V6_vlutvwh_nm : HInst<
34578(outs HvxWR:$Vdd32),
34579(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34580"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
34581tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
34582let Inst{7-5} = 0b100;
34583let Inst{13-13} = 0b0;
34584let Inst{31-24} = 0b00011000;
34585let hasNewValue = 1;
34586let opNewValue = 0;
34587let isCVI = 1;
34588let DecoderNamespace = "EXT_mmvec";
34589}
34590def V6_vlutvwh_oracc : HInst<
34591(outs HvxWR:$Vxx32),
34592(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34593"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
34594tc_9d1dc972, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
34595let Inst{7-5} = 0b111;
34596let Inst{13-13} = 0b1;
34597let Inst{31-24} = 0b00011011;
34598let hasNewValue = 1;
34599let opNewValue = 0;
34600let isAccumulator = 1;
34601let isCVI = 1;
34602let DecoderNamespace = "EXT_mmvec";
34603let Constraints = "$Vxx32 = $Vxx32in";
34604}
34605def V6_vlutvwh_oracci : HInst<
34606(outs HvxWR:$Vxx32),
34607(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34608"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
34609tc_9d1dc972, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
34610let Inst{13-13} = 0b1;
34611let Inst{31-21} = 0b00011100111;
34612let hasNewValue = 1;
34613let opNewValue = 0;
34614let isAccumulator = 1;
34615let isCVI = 1;
34616let DecoderNamespace = "EXT_mmvec";
34617let Constraints = "$Vxx32 = $Vxx32in";
34618}
34619def V6_vlutvwhi : HInst<
34620(outs HvxWR:$Vdd32),
34621(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34622"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
34623tc_87adc037, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
34624let Inst{13-13} = 0b0;
34625let Inst{31-21} = 0b00011110011;
34626let hasNewValue = 1;
34627let opNewValue = 0;
34628let isCVI = 1;
34629let DecoderNamespace = "EXT_mmvec";
34630}
34631def V6_vmax_bf : HInst<
34632(outs HvxVR:$Vd32),
34633(ins HvxVR:$Vu32, HvxVR:$Vv32),
34634"$Vd32.bf = vmax($Vu32.bf,$Vv32.bf)",
34635tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV73,UseHVXIEEEFP]> {
34636let Inst{7-5} = 0b111;
34637let Inst{13-13} = 0b1;
34638let Inst{31-21} = 0b00011101010;
34639let hasNewValue = 1;
34640let opNewValue = 0;
34641let isCVI = 1;
34642let DecoderNamespace = "EXT_mmvec";
34643}
34644def V6_vmax_hf : HInst<
34645(outs HvxVR:$Vd32),
34646(ins HvxVR:$Vu32, HvxVR:$Vv32),
34647"$Vd32.hf = vmax($Vu32.hf,$Vv32.hf)",
34648tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34649let Inst{7-5} = 0b011;
34650let Inst{13-13} = 0b1;
34651let Inst{31-21} = 0b00011111110;
34652let hasNewValue = 1;
34653let opNewValue = 0;
34654let isCVI = 1;
34655let isHVXALU = 1;
34656let isHVXALU2SRC = 1;
34657let DecoderNamespace = "EXT_mmvec";
34658}
34659def V6_vmax_sf : HInst<
34660(outs HvxVR:$Vd32),
34661(ins HvxVR:$Vu32, HvxVR:$Vv32),
34662"$Vd32.sf = vmax($Vu32.sf,$Vv32.sf)",
34663tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34664let Inst{7-5} = 0b001;
34665let Inst{13-13} = 0b1;
34666let Inst{31-21} = 0b00011111110;
34667let hasNewValue = 1;
34668let opNewValue = 0;
34669let isCVI = 1;
34670let isHVXALU = 1;
34671let isHVXALU2SRC = 1;
34672let DecoderNamespace = "EXT_mmvec";
34673}
34674def V6_vmaxb : HInst<
34675(outs HvxVR:$Vd32),
34676(ins HvxVR:$Vu32, HvxVR:$Vv32),
34677"$Vd32.b = vmax($Vu32.b,$Vv32.b)",
34678tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
34679let Inst{7-5} = 0b101;
34680let Inst{13-13} = 0b0;
34681let Inst{31-21} = 0b00011111001;
34682let hasNewValue = 1;
34683let opNewValue = 0;
34684let isCVI = 1;
34685let isHVXALU = 1;
34686let isHVXALU2SRC = 1;
34687let DecoderNamespace = "EXT_mmvec";
34688}
34689def V6_vmaxb_alt : HInst<
34690(outs HvxVR:$Vd32),
34691(ins HvxVR:$Vu32, HvxVR:$Vv32),
34692"$Vd32 = vmaxb($Vu32,$Vv32)",
34693PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34694let hasNewValue = 1;
34695let opNewValue = 0;
34696let isCVI = 1;
34697let isPseudo = 1;
34698let isCodeGenOnly = 1;
34699let DecoderNamespace = "EXT_mmvec";
34700}
34701def V6_vmaxh : HInst<
34702(outs HvxVR:$Vd32),
34703(ins HvxVR:$Vu32, HvxVR:$Vv32),
34704"$Vd32.h = vmax($Vu32.h,$Vv32.h)",
34705tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34706let Inst{7-5} = 0b111;
34707let Inst{13-13} = 0b0;
34708let Inst{31-21} = 0b00011111000;
34709let hasNewValue = 1;
34710let opNewValue = 0;
34711let isCVI = 1;
34712let isHVXALU = 1;
34713let isHVXALU2SRC = 1;
34714let DecoderNamespace = "EXT_mmvec";
34715}
34716def V6_vmaxh_alt : HInst<
34717(outs HvxVR:$Vd32),
34718(ins HvxVR:$Vu32, HvxVR:$Vv32),
34719"$Vd32 = vmaxh($Vu32,$Vv32)",
34720PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34721let hasNewValue = 1;
34722let opNewValue = 0;
34723let isCVI = 1;
34724let isPseudo = 1;
34725let isCodeGenOnly = 1;
34726let DecoderNamespace = "EXT_mmvec";
34727}
34728def V6_vmaxub : HInst<
34729(outs HvxVR:$Vd32),
34730(ins HvxVR:$Vu32, HvxVR:$Vv32),
34731"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
34732tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34733let Inst{7-5} = 0b101;
34734let Inst{13-13} = 0b0;
34735let Inst{31-21} = 0b00011111000;
34736let hasNewValue = 1;
34737let opNewValue = 0;
34738let isCVI = 1;
34739let isHVXALU = 1;
34740let isHVXALU2SRC = 1;
34741let DecoderNamespace = "EXT_mmvec";
34742}
34743def V6_vmaxub_alt : HInst<
34744(outs HvxVR:$Vd32),
34745(ins HvxVR:$Vu32, HvxVR:$Vv32),
34746"$Vd32 = vmaxub($Vu32,$Vv32)",
34747PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34748let hasNewValue = 1;
34749let opNewValue = 0;
34750let isCVI = 1;
34751let isPseudo = 1;
34752let isCodeGenOnly = 1;
34753let DecoderNamespace = "EXT_mmvec";
34754}
34755def V6_vmaxuh : HInst<
34756(outs HvxVR:$Vd32),
34757(ins HvxVR:$Vu32, HvxVR:$Vv32),
34758"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
34759tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34760let Inst{7-5} = 0b110;
34761let Inst{13-13} = 0b0;
34762let Inst{31-21} = 0b00011111000;
34763let hasNewValue = 1;
34764let opNewValue = 0;
34765let isCVI = 1;
34766let isHVXALU = 1;
34767let isHVXALU2SRC = 1;
34768let DecoderNamespace = "EXT_mmvec";
34769}
34770def V6_vmaxuh_alt : HInst<
34771(outs HvxVR:$Vd32),
34772(ins HvxVR:$Vu32, HvxVR:$Vv32),
34773"$Vd32 = vmaxuh($Vu32,$Vv32)",
34774PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34775let hasNewValue = 1;
34776let opNewValue = 0;
34777let isCVI = 1;
34778let isPseudo = 1;
34779let isCodeGenOnly = 1;
34780let DecoderNamespace = "EXT_mmvec";
34781}
34782def V6_vmaxw : HInst<
34783(outs HvxVR:$Vd32),
34784(ins HvxVR:$Vu32, HvxVR:$Vv32),
34785"$Vd32.w = vmax($Vu32.w,$Vv32.w)",
34786tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34787let Inst{7-5} = 0b000;
34788let Inst{13-13} = 0b0;
34789let Inst{31-21} = 0b00011111001;
34790let hasNewValue = 1;
34791let opNewValue = 0;
34792let isCVI = 1;
34793let isHVXALU = 1;
34794let isHVXALU2SRC = 1;
34795let DecoderNamespace = "EXT_mmvec";
34796}
34797def V6_vmaxw_alt : HInst<
34798(outs HvxVR:$Vd32),
34799(ins HvxVR:$Vu32, HvxVR:$Vv32),
34800"$Vd32 = vmaxw($Vu32,$Vv32)",
34801PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34802let hasNewValue = 1;
34803let opNewValue = 0;
34804let isCVI = 1;
34805let isPseudo = 1;
34806let isCodeGenOnly = 1;
34807let DecoderNamespace = "EXT_mmvec";
34808}
34809def V6_vmin_bf : HInst<
34810(outs HvxVR:$Vd32),
34811(ins HvxVR:$Vu32, HvxVR:$Vv32),
34812"$Vd32.bf = vmin($Vu32.bf,$Vv32.bf)",
34813tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV73,UseHVXIEEEFP]> {
34814let Inst{7-5} = 0b000;
34815let Inst{13-13} = 0b1;
34816let Inst{31-21} = 0b00011101010;
34817let hasNewValue = 1;
34818let opNewValue = 0;
34819let isCVI = 1;
34820let DecoderNamespace = "EXT_mmvec";
34821}
34822def V6_vmin_hf : HInst<
34823(outs HvxVR:$Vd32),
34824(ins HvxVR:$Vu32, HvxVR:$Vv32),
34825"$Vd32.hf = vmin($Vu32.hf,$Vv32.hf)",
34826tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34827let Inst{7-5} = 0b100;
34828let Inst{13-13} = 0b1;
34829let Inst{31-21} = 0b00011111110;
34830let hasNewValue = 1;
34831let opNewValue = 0;
34832let isCVI = 1;
34833let isHVXALU = 1;
34834let isHVXALU2SRC = 1;
34835let DecoderNamespace = "EXT_mmvec";
34836}
34837def V6_vmin_sf : HInst<
34838(outs HvxVR:$Vd32),
34839(ins HvxVR:$Vu32, HvxVR:$Vv32),
34840"$Vd32.sf = vmin($Vu32.sf,$Vv32.sf)",
34841tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34842let Inst{7-5} = 0b010;
34843let Inst{13-13} = 0b1;
34844let Inst{31-21} = 0b00011111110;
34845let hasNewValue = 1;
34846let opNewValue = 0;
34847let isCVI = 1;
34848let isHVXALU = 1;
34849let isHVXALU2SRC = 1;
34850let DecoderNamespace = "EXT_mmvec";
34851}
34852def V6_vminb : HInst<
34853(outs HvxVR:$Vd32),
34854(ins HvxVR:$Vu32, HvxVR:$Vv32),
34855"$Vd32.b = vmin($Vu32.b,$Vv32.b)",
34856tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
34857let Inst{7-5} = 0b100;
34858let Inst{13-13} = 0b0;
34859let Inst{31-21} = 0b00011111001;
34860let hasNewValue = 1;
34861let opNewValue = 0;
34862let isCVI = 1;
34863let isHVXALU = 1;
34864let isHVXALU2SRC = 1;
34865let DecoderNamespace = "EXT_mmvec";
34866}
34867def V6_vminb_alt : HInst<
34868(outs HvxVR:$Vd32),
34869(ins HvxVR:$Vu32, HvxVR:$Vv32),
34870"$Vd32 = vminb($Vu32,$Vv32)",
34871PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34872let hasNewValue = 1;
34873let opNewValue = 0;
34874let isCVI = 1;
34875let isPseudo = 1;
34876let isCodeGenOnly = 1;
34877let DecoderNamespace = "EXT_mmvec";
34878}
34879def V6_vminh : HInst<
34880(outs HvxVR:$Vd32),
34881(ins HvxVR:$Vu32, HvxVR:$Vv32),
34882"$Vd32.h = vmin($Vu32.h,$Vv32.h)",
34883tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34884let Inst{7-5} = 0b011;
34885let Inst{13-13} = 0b0;
34886let Inst{31-21} = 0b00011111000;
34887let hasNewValue = 1;
34888let opNewValue = 0;
34889let isCVI = 1;
34890let isHVXALU = 1;
34891let isHVXALU2SRC = 1;
34892let DecoderNamespace = "EXT_mmvec";
34893}
34894def V6_vminh_alt : HInst<
34895(outs HvxVR:$Vd32),
34896(ins HvxVR:$Vu32, HvxVR:$Vv32),
34897"$Vd32 = vminh($Vu32,$Vv32)",
34898PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34899let hasNewValue = 1;
34900let opNewValue = 0;
34901let isCVI = 1;
34902let isPseudo = 1;
34903let isCodeGenOnly = 1;
34904let DecoderNamespace = "EXT_mmvec";
34905}
34906def V6_vminub : HInst<
34907(outs HvxVR:$Vd32),
34908(ins HvxVR:$Vu32, HvxVR:$Vv32),
34909"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
34910tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34911let Inst{7-5} = 0b001;
34912let Inst{13-13} = 0b0;
34913let Inst{31-21} = 0b00011111000;
34914let hasNewValue = 1;
34915let opNewValue = 0;
34916let isCVI = 1;
34917let isHVXALU = 1;
34918let isHVXALU2SRC = 1;
34919let DecoderNamespace = "EXT_mmvec";
34920}
34921def V6_vminub_alt : HInst<
34922(outs HvxVR:$Vd32),
34923(ins HvxVR:$Vu32, HvxVR:$Vv32),
34924"$Vd32 = vminub($Vu32,$Vv32)",
34925PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34926let hasNewValue = 1;
34927let opNewValue = 0;
34928let isCVI = 1;
34929let isPseudo = 1;
34930let isCodeGenOnly = 1;
34931let DecoderNamespace = "EXT_mmvec";
34932}
34933def V6_vminuh : HInst<
34934(outs HvxVR:$Vd32),
34935(ins HvxVR:$Vu32, HvxVR:$Vv32),
34936"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
34937tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34938let Inst{7-5} = 0b010;
34939let Inst{13-13} = 0b0;
34940let Inst{31-21} = 0b00011111000;
34941let hasNewValue = 1;
34942let opNewValue = 0;
34943let isCVI = 1;
34944let isHVXALU = 1;
34945let isHVXALU2SRC = 1;
34946let DecoderNamespace = "EXT_mmvec";
34947}
34948def V6_vminuh_alt : HInst<
34949(outs HvxVR:$Vd32),
34950(ins HvxVR:$Vu32, HvxVR:$Vv32),
34951"$Vd32 = vminuh($Vu32,$Vv32)",
34952PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34953let hasNewValue = 1;
34954let opNewValue = 0;
34955let isCVI = 1;
34956let isPseudo = 1;
34957let isCodeGenOnly = 1;
34958let DecoderNamespace = "EXT_mmvec";
34959}
34960def V6_vminw : HInst<
34961(outs HvxVR:$Vd32),
34962(ins HvxVR:$Vu32, HvxVR:$Vv32),
34963"$Vd32.w = vmin($Vu32.w,$Vv32.w)",
34964tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34965let Inst{7-5} = 0b100;
34966let Inst{13-13} = 0b0;
34967let Inst{31-21} = 0b00011111000;
34968let hasNewValue = 1;
34969let opNewValue = 0;
34970let isCVI = 1;
34971let isHVXALU = 1;
34972let isHVXALU2SRC = 1;
34973let DecoderNamespace = "EXT_mmvec";
34974}
34975def V6_vminw_alt : HInst<
34976(outs HvxVR:$Vd32),
34977(ins HvxVR:$Vu32, HvxVR:$Vv32),
34978"$Vd32 = vminw($Vu32,$Vv32)",
34979PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34980let hasNewValue = 1;
34981let opNewValue = 0;
34982let isCVI = 1;
34983let isPseudo = 1;
34984let isCodeGenOnly = 1;
34985let DecoderNamespace = "EXT_mmvec";
34986}
34987def V6_vmpabus : HInst<
34988(outs HvxWR:$Vdd32),
34989(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34990"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
34991tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
34992let Inst{7-5} = 0b110;
34993let Inst{13-13} = 0b0;
34994let Inst{31-21} = 0b00011001001;
34995let hasNewValue = 1;
34996let opNewValue = 0;
34997let isCVI = 1;
34998let DecoderNamespace = "EXT_mmvec";
34999}
35000def V6_vmpabus_acc : HInst<
35001(outs HvxWR:$Vxx32),
35002(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35003"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
35004tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
35005let Inst{7-5} = 0b110;
35006let Inst{13-13} = 0b1;
35007let Inst{31-21} = 0b00011001001;
35008let hasNewValue = 1;
35009let opNewValue = 0;
35010let isAccumulator = 1;
35011let isCVI = 1;
35012let DecoderNamespace = "EXT_mmvec";
35013let Constraints = "$Vxx32 = $Vxx32in";
35014}
35015def V6_vmpabus_acc_alt : HInst<
35016(outs HvxWR:$Vxx32),
35017(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35018"$Vxx32 += vmpabus($Vuu32,$Rt32)",
35019PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35020let hasNewValue = 1;
35021let opNewValue = 0;
35022let isAccumulator = 1;
35023let isCVI = 1;
35024let isPseudo = 1;
35025let isCodeGenOnly = 1;
35026let DecoderNamespace = "EXT_mmvec";
35027let Constraints = "$Vxx32 = $Vxx32in";
35028}
35029def V6_vmpabus_alt : HInst<
35030(outs HvxWR:$Vdd32),
35031(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35032"$Vdd32 = vmpabus($Vuu32,$Rt32)",
35033PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35034let hasNewValue = 1;
35035let opNewValue = 0;
35036let isCVI = 1;
35037let isPseudo = 1;
35038let isCodeGenOnly = 1;
35039let DecoderNamespace = "EXT_mmvec";
35040}
35041def V6_vmpabusv : HInst<
35042(outs HvxWR:$Vdd32),
35043(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35044"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
35045tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
35046let Inst{7-5} = 0b011;
35047let Inst{13-13} = 0b0;
35048let Inst{31-21} = 0b00011100001;
35049let hasNewValue = 1;
35050let opNewValue = 0;
35051let isCVI = 1;
35052let DecoderNamespace = "EXT_mmvec";
35053}
35054def V6_vmpabusv_alt : HInst<
35055(outs HvxWR:$Vdd32),
35056(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35057"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
35058PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35059let hasNewValue = 1;
35060let opNewValue = 0;
35061let isCVI = 1;
35062let isPseudo = 1;
35063let isCodeGenOnly = 1;
35064let DecoderNamespace = "EXT_mmvec";
35065}
35066def V6_vmpabuu : HInst<
35067(outs HvxWR:$Vdd32),
35068(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35069"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
35070tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
35071let Inst{7-5} = 0b011;
35072let Inst{13-13} = 0b0;
35073let Inst{31-21} = 0b00011001011;
35074let hasNewValue = 1;
35075let opNewValue = 0;
35076let isCVI = 1;
35077let DecoderNamespace = "EXT_mmvec";
35078}
35079def V6_vmpabuu_acc : HInst<
35080(outs HvxWR:$Vxx32),
35081(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35082"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
35083tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
35084let Inst{7-5} = 0b100;
35085let Inst{13-13} = 0b1;
35086let Inst{31-21} = 0b00011001101;
35087let hasNewValue = 1;
35088let opNewValue = 0;
35089let isAccumulator = 1;
35090let isCVI = 1;
35091let DecoderNamespace = "EXT_mmvec";
35092let Constraints = "$Vxx32 = $Vxx32in";
35093}
35094def V6_vmpabuu_acc_alt : HInst<
35095(outs HvxWR:$Vxx32),
35096(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35097"$Vxx32 += vmpabuu($Vuu32,$Rt32)",
35098PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35099let hasNewValue = 1;
35100let opNewValue = 0;
35101let isAccumulator = 1;
35102let isCVI = 1;
35103let isPseudo = 1;
35104let isCodeGenOnly = 1;
35105let DecoderNamespace = "EXT_mmvec";
35106let Constraints = "$Vxx32 = $Vxx32in";
35107}
35108def V6_vmpabuu_alt : HInst<
35109(outs HvxWR:$Vdd32),
35110(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35111"$Vdd32 = vmpabuu($Vuu32,$Rt32)",
35112PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35113let hasNewValue = 1;
35114let opNewValue = 0;
35115let isCVI = 1;
35116let isPseudo = 1;
35117let isCodeGenOnly = 1;
35118let DecoderNamespace = "EXT_mmvec";
35119}
35120def V6_vmpabuuv : HInst<
35121(outs HvxWR:$Vdd32),
35122(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35123"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
35124tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
35125let Inst{7-5} = 0b111;
35126let Inst{13-13} = 0b0;
35127let Inst{31-21} = 0b00011100111;
35128let hasNewValue = 1;
35129let opNewValue = 0;
35130let isCVI = 1;
35131let DecoderNamespace = "EXT_mmvec";
35132}
35133def V6_vmpabuuv_alt : HInst<
35134(outs HvxWR:$Vdd32),
35135(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35136"$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
35137PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35138let hasNewValue = 1;
35139let opNewValue = 0;
35140let isCVI = 1;
35141let isPseudo = 1;
35142let isCodeGenOnly = 1;
35143let DecoderNamespace = "EXT_mmvec";
35144}
35145def V6_vmpahb : HInst<
35146(outs HvxWR:$Vdd32),
35147(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35148"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
35149tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
35150let Inst{7-5} = 0b111;
35151let Inst{13-13} = 0b0;
35152let Inst{31-21} = 0b00011001001;
35153let hasNewValue = 1;
35154let opNewValue = 0;
35155let isCVI = 1;
35156let DecoderNamespace = "EXT_mmvec";
35157}
35158def V6_vmpahb_acc : HInst<
35159(outs HvxWR:$Vxx32),
35160(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35161"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
35162tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
35163let Inst{7-5} = 0b111;
35164let Inst{13-13} = 0b1;
35165let Inst{31-21} = 0b00011001001;
35166let hasNewValue = 1;
35167let opNewValue = 0;
35168let isAccumulator = 1;
35169let isCVI = 1;
35170let DecoderNamespace = "EXT_mmvec";
35171let Constraints = "$Vxx32 = $Vxx32in";
35172}
35173def V6_vmpahb_acc_alt : HInst<
35174(outs HvxWR:$Vxx32),
35175(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35176"$Vxx32 += vmpahb($Vuu32,$Rt32)",
35177PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35178let hasNewValue = 1;
35179let opNewValue = 0;
35180let isAccumulator = 1;
35181let isCVI = 1;
35182let isPseudo = 1;
35183let isCodeGenOnly = 1;
35184let DecoderNamespace = "EXT_mmvec";
35185let Constraints = "$Vxx32 = $Vxx32in";
35186}
35187def V6_vmpahb_alt : HInst<
35188(outs HvxWR:$Vdd32),
35189(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35190"$Vdd32 = vmpahb($Vuu32,$Rt32)",
35191PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35192let hasNewValue = 1;
35193let opNewValue = 0;
35194let isCVI = 1;
35195let isPseudo = 1;
35196let isCodeGenOnly = 1;
35197let DecoderNamespace = "EXT_mmvec";
35198}
35199def V6_vmpahhsat : HInst<
35200(outs HvxVR:$Vx32),
35201(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35202"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
35203tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
35204let Inst{7-5} = 0b100;
35205let Inst{13-13} = 0b1;
35206let Inst{31-21} = 0b00011001100;
35207let hasNewValue = 1;
35208let opNewValue = 0;
35209let isCVI = 1;
35210let DecoderNamespace = "EXT_mmvec";
35211let Constraints = "$Vx32 = $Vx32in";
35212}
35213def V6_vmpauhb : HInst<
35214(outs HvxWR:$Vdd32),
35215(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35216"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
35217tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
35218let Inst{7-5} = 0b101;
35219let Inst{13-13} = 0b0;
35220let Inst{31-21} = 0b00011001100;
35221let hasNewValue = 1;
35222let opNewValue = 0;
35223let isCVI = 1;
35224let DecoderNamespace = "EXT_mmvec";
35225}
35226def V6_vmpauhb_acc : HInst<
35227(outs HvxWR:$Vxx32),
35228(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35229"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
35230tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
35231let Inst{7-5} = 0b010;
35232let Inst{13-13} = 0b1;
35233let Inst{31-21} = 0b00011001100;
35234let hasNewValue = 1;
35235let opNewValue = 0;
35236let isAccumulator = 1;
35237let isCVI = 1;
35238let DecoderNamespace = "EXT_mmvec";
35239let Constraints = "$Vxx32 = $Vxx32in";
35240}
35241def V6_vmpauhb_acc_alt : HInst<
35242(outs HvxWR:$Vxx32),
35243(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35244"$Vxx32 += vmpauhb($Vuu32,$Rt32)",
35245PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35246let hasNewValue = 1;
35247let opNewValue = 0;
35248let isAccumulator = 1;
35249let isCVI = 1;
35250let isPseudo = 1;
35251let isCodeGenOnly = 1;
35252let DecoderNamespace = "EXT_mmvec";
35253let Constraints = "$Vxx32 = $Vxx32in";
35254}
35255def V6_vmpauhb_alt : HInst<
35256(outs HvxWR:$Vdd32),
35257(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35258"$Vdd32 = vmpauhb($Vuu32,$Rt32)",
35259PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35260let hasNewValue = 1;
35261let opNewValue = 0;
35262let isCVI = 1;
35263let isPseudo = 1;
35264let isCodeGenOnly = 1;
35265let DecoderNamespace = "EXT_mmvec";
35266}
35267def V6_vmpauhuhsat : HInst<
35268(outs HvxVR:$Vx32),
35269(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35270"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
35271tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
35272let Inst{7-5} = 0b101;
35273let Inst{13-13} = 0b1;
35274let Inst{31-21} = 0b00011001100;
35275let hasNewValue = 1;
35276let opNewValue = 0;
35277let isCVI = 1;
35278let DecoderNamespace = "EXT_mmvec";
35279let Constraints = "$Vx32 = $Vx32in";
35280}
35281def V6_vmpsuhuhsat : HInst<
35282(outs HvxVR:$Vx32),
35283(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35284"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
35285tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
35286let Inst{7-5} = 0b110;
35287let Inst{13-13} = 0b1;
35288let Inst{31-21} = 0b00011001100;
35289let hasNewValue = 1;
35290let opNewValue = 0;
35291let isCVI = 1;
35292let DecoderNamespace = "EXT_mmvec";
35293let Constraints = "$Vx32 = $Vx32in";
35294}
35295def V6_vmpy_hf_hf : HInst<
35296(outs HvxVR:$Vd32),
35297(ins HvxVR:$Vu32, HvxVR:$Vv32),
35298"$Vd32.hf = vmpy($Vu32.hf,$Vv32.hf)",
35299tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35300let Inst{7-5} = 0b011;
35301let Inst{13-13} = 0b1;
35302let Inst{31-21} = 0b00011111100;
35303let hasNewValue = 1;
35304let opNewValue = 0;
35305let isCVI = 1;
35306let DecoderNamespace = "EXT_mmvec";
35307}
35308def V6_vmpy_hf_hf_acc : HInst<
35309(outs HvxVR:$Vx32),
35310(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35311"$Vx32.hf += vmpy($Vu32.hf,$Vv32.hf)",
35312tc_a19b9305, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35313let Inst{7-5} = 0b010;
35314let Inst{13-13} = 0b1;
35315let Inst{31-21} = 0b00011100010;
35316let hasNewValue = 1;
35317let opNewValue = 0;
35318let isAccumulator = 1;
35319let isCVI = 1;
35320let DecoderNamespace = "EXT_mmvec";
35321let Constraints = "$Vx32 = $Vx32in";
35322}
35323def V6_vmpy_qf16 : HInst<
35324(outs HvxVR:$Vd32),
35325(ins HvxVR:$Vu32, HvxVR:$Vv32),
35326"$Vd32.qf16 = vmpy($Vu32.qf16,$Vv32.qf16)",
35327tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35328let Inst{7-5} = 0b011;
35329let Inst{13-13} = 0b1;
35330let Inst{31-21} = 0b00011111111;
35331let hasNewValue = 1;
35332let opNewValue = 0;
35333let isCVI = 1;
35334let DecoderNamespace = "EXT_mmvec";
35335}
35336def V6_vmpy_qf16_hf : HInst<
35337(outs HvxVR:$Vd32),
35338(ins HvxVR:$Vu32, HvxVR:$Vv32),
35339"$Vd32.qf16 = vmpy($Vu32.hf,$Vv32.hf)",
35340tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35341let Inst{7-5} = 0b100;
35342let Inst{13-13} = 0b1;
35343let Inst{31-21} = 0b00011111111;
35344let hasNewValue = 1;
35345let opNewValue = 0;
35346let isCVI = 1;
35347let DecoderNamespace = "EXT_mmvec";
35348}
35349def V6_vmpy_qf16_mix_hf : HInst<
35350(outs HvxVR:$Vd32),
35351(ins HvxVR:$Vu32, HvxVR:$Vv32),
35352"$Vd32.qf16 = vmpy($Vu32.qf16,$Vv32.hf)",
35353tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35354let Inst{7-5} = 0b101;
35355let Inst{13-13} = 0b1;
35356let Inst{31-21} = 0b00011111111;
35357let hasNewValue = 1;
35358let opNewValue = 0;
35359let isCVI = 1;
35360let DecoderNamespace = "EXT_mmvec";
35361}
35362def V6_vmpy_qf32 : HInst<
35363(outs HvxVR:$Vd32),
35364(ins HvxVR:$Vu32, HvxVR:$Vv32),
35365"$Vd32.qf32 = vmpy($Vu32.qf32,$Vv32.qf32)",
35366tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35367let Inst{7-5} = 0b000;
35368let Inst{13-13} = 0b1;
35369let Inst{31-21} = 0b00011111111;
35370let hasNewValue = 1;
35371let opNewValue = 0;
35372let isCVI = 1;
35373let DecoderNamespace = "EXT_mmvec";
35374}
35375def V6_vmpy_qf32_hf : HInst<
35376(outs HvxWR:$Vdd32),
35377(ins HvxVR:$Vu32, HvxVR:$Vv32),
35378"$Vdd32.qf32 = vmpy($Vu32.hf,$Vv32.hf)",
35379tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
35380let Inst{7-5} = 0b111;
35381let Inst{13-13} = 0b1;
35382let Inst{31-21} = 0b00011111111;
35383let hasNewValue = 1;
35384let opNewValue = 0;
35385let isCVI = 1;
35386let DecoderNamespace = "EXT_mmvec";
35387}
35388def V6_vmpy_qf32_mix_hf : HInst<
35389(outs HvxWR:$Vdd32),
35390(ins HvxVR:$Vu32, HvxVR:$Vv32),
35391"$Vdd32.qf32 = vmpy($Vu32.qf16,$Vv32.hf)",
35392tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
35393let Inst{7-5} = 0b000;
35394let Inst{13-13} = 0b1;
35395let Inst{31-21} = 0b00011111100;
35396let hasNewValue = 1;
35397let opNewValue = 0;
35398let isCVI = 1;
35399let DecoderNamespace = "EXT_mmvec";
35400}
35401def V6_vmpy_qf32_qf16 : HInst<
35402(outs HvxWR:$Vdd32),
35403(ins HvxVR:$Vu32, HvxVR:$Vv32),
35404"$Vdd32.qf32 = vmpy($Vu32.qf16,$Vv32.qf16)",
35405tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
35406let Inst{7-5} = 0b110;
35407let Inst{13-13} = 0b1;
35408let Inst{31-21} = 0b00011111111;
35409let hasNewValue = 1;
35410let opNewValue = 0;
35411let isCVI = 1;
35412let DecoderNamespace = "EXT_mmvec";
35413}
35414def V6_vmpy_qf32_sf : HInst<
35415(outs HvxVR:$Vd32),
35416(ins HvxVR:$Vu32, HvxVR:$Vv32),
35417"$Vd32.qf32 = vmpy($Vu32.sf,$Vv32.sf)",
35418tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35419let Inst{7-5} = 0b001;
35420let Inst{13-13} = 0b1;
35421let Inst{31-21} = 0b00011111111;
35422let hasNewValue = 1;
35423let opNewValue = 0;
35424let isCVI = 1;
35425let DecoderNamespace = "EXT_mmvec";
35426}
35427def V6_vmpy_sf_bf : HInst<
35428(outs HvxWR:$Vdd32),
35429(ins HvxVR:$Vu32, HvxVR:$Vv32),
35430"$Vdd32.sf = vmpy($Vu32.bf,$Vv32.bf)",
35431tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV73,UseHVXIEEEFP]> {
35432let Inst{7-5} = 0b100;
35433let Inst{13-13} = 0b1;
35434let Inst{31-21} = 0b00011101010;
35435let hasNewValue = 1;
35436let opNewValue = 0;
35437let isCVI = 1;
35438let DecoderNamespace = "EXT_mmvec";
35439}
35440def V6_vmpy_sf_bf_acc : HInst<
35441(outs HvxWR:$Vxx32),
35442(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35443"$Vxx32.sf += vmpy($Vu32.bf,$Vv32.bf)",
35444tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV73,UseHVXIEEEFP]> {
35445let Inst{7-5} = 0b000;
35446let Inst{13-13} = 0b1;
35447let Inst{31-21} = 0b00011101000;
35448let hasNewValue = 1;
35449let opNewValue = 0;
35450let isAccumulator = 1;
35451let isCVI = 1;
35452let DecoderNamespace = "EXT_mmvec";
35453let Constraints = "$Vxx32 = $Vxx32in";
35454}
35455def V6_vmpy_sf_hf : HInst<
35456(outs HvxWR:$Vdd32),
35457(ins HvxVR:$Vu32, HvxVR:$Vv32),
35458"$Vdd32.sf = vmpy($Vu32.hf,$Vv32.hf)",
35459tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35460let Inst{7-5} = 0b010;
35461let Inst{13-13} = 0b1;
35462let Inst{31-21} = 0b00011111100;
35463let hasNewValue = 1;
35464let opNewValue = 0;
35465let isCVI = 1;
35466let DecoderNamespace = "EXT_mmvec";
35467}
35468def V6_vmpy_sf_hf_acc : HInst<
35469(outs HvxWR:$Vxx32),
35470(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35471"$Vxx32.sf += vmpy($Vu32.hf,$Vv32.hf)",
35472tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35473let Inst{7-5} = 0b001;
35474let Inst{13-13} = 0b1;
35475let Inst{31-21} = 0b00011100010;
35476let hasNewValue = 1;
35477let opNewValue = 0;
35478let isAccumulator = 1;
35479let isCVI = 1;
35480let DecoderNamespace = "EXT_mmvec";
35481let Constraints = "$Vxx32 = $Vxx32in";
35482}
35483def V6_vmpy_sf_sf : HInst<
35484(outs HvxVR:$Vd32),
35485(ins HvxVR:$Vu32, HvxVR:$Vv32),
35486"$Vd32.sf = vmpy($Vu32.sf,$Vv32.sf)",
35487tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35488let Inst{7-5} = 0b001;
35489let Inst{13-13} = 0b1;
35490let Inst{31-21} = 0b00011111100;
35491let hasNewValue = 1;
35492let opNewValue = 0;
35493let isCVI = 1;
35494let DecoderNamespace = "EXT_mmvec";
35495}
35496def V6_vmpybus : HInst<
35497(outs HvxWR:$Vdd32),
35498(ins HvxVR:$Vu32, IntRegs:$Rt32),
35499"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
35500tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35501let Inst{7-5} = 0b101;
35502let Inst{13-13} = 0b0;
35503let Inst{31-21} = 0b00011001001;
35504let hasNewValue = 1;
35505let opNewValue = 0;
35506let isCVI = 1;
35507let DecoderNamespace = "EXT_mmvec";
35508}
35509def V6_vmpybus_acc : HInst<
35510(outs HvxWR:$Vxx32),
35511(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35512"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
35513tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35514let Inst{7-5} = 0b101;
35515let Inst{13-13} = 0b1;
35516let Inst{31-21} = 0b00011001001;
35517let hasNewValue = 1;
35518let opNewValue = 0;
35519let isAccumulator = 1;
35520let isCVI = 1;
35521let DecoderNamespace = "EXT_mmvec";
35522let Constraints = "$Vxx32 = $Vxx32in";
35523}
35524def V6_vmpybus_acc_alt : HInst<
35525(outs HvxWR:$Vxx32),
35526(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35527"$Vxx32 += vmpybus($Vu32,$Rt32)",
35528PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35529let hasNewValue = 1;
35530let opNewValue = 0;
35531let isAccumulator = 1;
35532let isCVI = 1;
35533let isPseudo = 1;
35534let isCodeGenOnly = 1;
35535let DecoderNamespace = "EXT_mmvec";
35536let Constraints = "$Vxx32 = $Vxx32in";
35537}
35538def V6_vmpybus_alt : HInst<
35539(outs HvxWR:$Vdd32),
35540(ins HvxVR:$Vu32, IntRegs:$Rt32),
35541"$Vdd32 = vmpybus($Vu32,$Rt32)",
35542PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35543let hasNewValue = 1;
35544let opNewValue = 0;
35545let isCVI = 1;
35546let isPseudo = 1;
35547let isCodeGenOnly = 1;
35548let DecoderNamespace = "EXT_mmvec";
35549}
35550def V6_vmpybusv : HInst<
35551(outs HvxWR:$Vdd32),
35552(ins HvxVR:$Vu32, HvxVR:$Vv32),
35553"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
35554tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35555let Inst{7-5} = 0b110;
35556let Inst{13-13} = 0b0;
35557let Inst{31-21} = 0b00011100000;
35558let hasNewValue = 1;
35559let opNewValue = 0;
35560let isCVI = 1;
35561let DecoderNamespace = "EXT_mmvec";
35562}
35563def V6_vmpybusv_acc : HInst<
35564(outs HvxWR:$Vxx32),
35565(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35566"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
35567tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35568let Inst{7-5} = 0b110;
35569let Inst{13-13} = 0b1;
35570let Inst{31-21} = 0b00011100000;
35571let hasNewValue = 1;
35572let opNewValue = 0;
35573let isAccumulator = 1;
35574let isCVI = 1;
35575let DecoderNamespace = "EXT_mmvec";
35576let Constraints = "$Vxx32 = $Vxx32in";
35577}
35578def V6_vmpybusv_acc_alt : HInst<
35579(outs HvxWR:$Vxx32),
35580(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35581"$Vxx32 += vmpybus($Vu32,$Vv32)",
35582PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35583let hasNewValue = 1;
35584let opNewValue = 0;
35585let isAccumulator = 1;
35586let isCVI = 1;
35587let isPseudo = 1;
35588let isCodeGenOnly = 1;
35589let DecoderNamespace = "EXT_mmvec";
35590let Constraints = "$Vxx32 = $Vxx32in";
35591}
35592def V6_vmpybusv_alt : HInst<
35593(outs HvxWR:$Vdd32),
35594(ins HvxVR:$Vu32, HvxVR:$Vv32),
35595"$Vdd32 = vmpybus($Vu32,$Vv32)",
35596PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35597let hasNewValue = 1;
35598let opNewValue = 0;
35599let isCVI = 1;
35600let isPseudo = 1;
35601let isCodeGenOnly = 1;
35602let DecoderNamespace = "EXT_mmvec";
35603}
35604def V6_vmpybv : HInst<
35605(outs HvxWR:$Vdd32),
35606(ins HvxVR:$Vu32, HvxVR:$Vv32),
35607"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
35608tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35609let Inst{7-5} = 0b100;
35610let Inst{13-13} = 0b0;
35611let Inst{31-21} = 0b00011100000;
35612let hasNewValue = 1;
35613let opNewValue = 0;
35614let isCVI = 1;
35615let DecoderNamespace = "EXT_mmvec";
35616}
35617def V6_vmpybv_acc : HInst<
35618(outs HvxWR:$Vxx32),
35619(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35620"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
35621tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35622let Inst{7-5} = 0b100;
35623let Inst{13-13} = 0b1;
35624let Inst{31-21} = 0b00011100000;
35625let hasNewValue = 1;
35626let opNewValue = 0;
35627let isAccumulator = 1;
35628let isCVI = 1;
35629let DecoderNamespace = "EXT_mmvec";
35630let Constraints = "$Vxx32 = $Vxx32in";
35631}
35632def V6_vmpybv_acc_alt : HInst<
35633(outs HvxWR:$Vxx32),
35634(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35635"$Vxx32 += vmpyb($Vu32,$Vv32)",
35636PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35637let hasNewValue = 1;
35638let opNewValue = 0;
35639let isAccumulator = 1;
35640let isCVI = 1;
35641let isPseudo = 1;
35642let isCodeGenOnly = 1;
35643let DecoderNamespace = "EXT_mmvec";
35644let Constraints = "$Vxx32 = $Vxx32in";
35645}
35646def V6_vmpybv_alt : HInst<
35647(outs HvxWR:$Vdd32),
35648(ins HvxVR:$Vu32, HvxVR:$Vv32),
35649"$Vdd32 = vmpyb($Vu32,$Vv32)",
35650PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35651let hasNewValue = 1;
35652let opNewValue = 0;
35653let isCVI = 1;
35654let isPseudo = 1;
35655let isCodeGenOnly = 1;
35656let DecoderNamespace = "EXT_mmvec";
35657}
35658def V6_vmpyewuh : HInst<
35659(outs HvxVR:$Vd32),
35660(ins HvxVR:$Vu32, HvxVR:$Vv32),
35661"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
35662tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35663let Inst{7-5} = 0b101;
35664let Inst{13-13} = 0b0;
35665let Inst{31-21} = 0b00011111111;
35666let hasNewValue = 1;
35667let opNewValue = 0;
35668let isCVI = 1;
35669let DecoderNamespace = "EXT_mmvec";
35670}
35671def V6_vmpyewuh_64 : HInst<
35672(outs HvxWR:$Vdd32),
35673(ins HvxVR:$Vu32, HvxVR:$Vv32),
35674"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
35675tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
35676let Inst{7-5} = 0b110;
35677let Inst{13-13} = 0b0;
35678let Inst{31-21} = 0b00011110101;
35679let hasNewValue = 1;
35680let opNewValue = 0;
35681let isCVI = 1;
35682let DecoderNamespace = "EXT_mmvec";
35683}
35684def V6_vmpyewuh_alt : HInst<
35685(outs HvxVR:$Vd32),
35686(ins HvxVR:$Vu32, HvxVR:$Vv32),
35687"$Vd32 = vmpyewuh($Vu32,$Vv32)",
35688PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35689let hasNewValue = 1;
35690let opNewValue = 0;
35691let isCVI = 1;
35692let isPseudo = 1;
35693let isCodeGenOnly = 1;
35694let DecoderNamespace = "EXT_mmvec";
35695}
35696def V6_vmpyh : HInst<
35697(outs HvxWR:$Vdd32),
35698(ins HvxVR:$Vu32, IntRegs:$Rt32),
35699"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
35700tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35701let Inst{7-5} = 0b000;
35702let Inst{13-13} = 0b0;
35703let Inst{31-21} = 0b00011001010;
35704let hasNewValue = 1;
35705let opNewValue = 0;
35706let isCVI = 1;
35707let DecoderNamespace = "EXT_mmvec";
35708}
35709def V6_vmpyh_acc : HInst<
35710(outs HvxWR:$Vxx32),
35711(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35712"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
35713tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
35714let Inst{7-5} = 0b110;
35715let Inst{13-13} = 0b1;
35716let Inst{31-21} = 0b00011001101;
35717let hasNewValue = 1;
35718let opNewValue = 0;
35719let isAccumulator = 1;
35720let isCVI = 1;
35721let DecoderNamespace = "EXT_mmvec";
35722let Constraints = "$Vxx32 = $Vxx32in";
35723}
35724def V6_vmpyh_acc_alt : HInst<
35725(outs HvxWR:$Vxx32),
35726(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35727"$Vxx32 += vmpyh($Vu32,$Rt32)",
35728PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35729let hasNewValue = 1;
35730let opNewValue = 0;
35731let isAccumulator = 1;
35732let isCVI = 1;
35733let isPseudo = 1;
35734let isCodeGenOnly = 1;
35735let DecoderNamespace = "EXT_mmvec";
35736let Constraints = "$Vxx32 = $Vxx32in";
35737}
35738def V6_vmpyh_alt : HInst<
35739(outs HvxWR:$Vdd32),
35740(ins HvxVR:$Vu32, IntRegs:$Rt32),
35741"$Vdd32 = vmpyh($Vu32,$Rt32)",
35742PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35743let hasNewValue = 1;
35744let opNewValue = 0;
35745let isCVI = 1;
35746let isPseudo = 1;
35747let isCodeGenOnly = 1;
35748let DecoderNamespace = "EXT_mmvec";
35749}
35750def V6_vmpyhsat_acc : HInst<
35751(outs HvxWR:$Vxx32),
35752(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35753"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
35754tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35755let Inst{7-5} = 0b000;
35756let Inst{13-13} = 0b1;
35757let Inst{31-21} = 0b00011001010;
35758let hasNewValue = 1;
35759let opNewValue = 0;
35760let isAccumulator = 1;
35761let isCVI = 1;
35762let DecoderNamespace = "EXT_mmvec";
35763let Constraints = "$Vxx32 = $Vxx32in";
35764}
35765def V6_vmpyhsat_acc_alt : HInst<
35766(outs HvxWR:$Vxx32),
35767(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35768"$Vxx32 += vmpyh($Vu32,$Rt32):sat",
35769PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35770let hasNewValue = 1;
35771let opNewValue = 0;
35772let isAccumulator = 1;
35773let isCVI = 1;
35774let isPseudo = 1;
35775let isCodeGenOnly = 1;
35776let DecoderNamespace = "EXT_mmvec";
35777let Constraints = "$Vxx32 = $Vxx32in";
35778}
35779def V6_vmpyhsrs : HInst<
35780(outs HvxVR:$Vd32),
35781(ins HvxVR:$Vu32, IntRegs:$Rt32),
35782"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
35783tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35784let Inst{7-5} = 0b010;
35785let Inst{13-13} = 0b0;
35786let Inst{31-21} = 0b00011001010;
35787let hasNewValue = 1;
35788let opNewValue = 0;
35789let isCVI = 1;
35790let DecoderNamespace = "EXT_mmvec";
35791}
35792def V6_vmpyhsrs_alt : HInst<
35793(outs HvxVR:$Vd32),
35794(ins HvxVR:$Vu32, IntRegs:$Rt32),
35795"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
35796PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35797let hasNewValue = 1;
35798let opNewValue = 0;
35799let isCVI = 1;
35800let isPseudo = 1;
35801let isCodeGenOnly = 1;
35802let DecoderNamespace = "EXT_mmvec";
35803}
35804def V6_vmpyhss : HInst<
35805(outs HvxVR:$Vd32),
35806(ins HvxVR:$Vu32, IntRegs:$Rt32),
35807"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
35808tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35809let Inst{7-5} = 0b001;
35810let Inst{13-13} = 0b0;
35811let Inst{31-21} = 0b00011001010;
35812let hasNewValue = 1;
35813let opNewValue = 0;
35814let isCVI = 1;
35815let DecoderNamespace = "EXT_mmvec";
35816}
35817def V6_vmpyhss_alt : HInst<
35818(outs HvxVR:$Vd32),
35819(ins HvxVR:$Vu32, IntRegs:$Rt32),
35820"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
35821PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35822let hasNewValue = 1;
35823let opNewValue = 0;
35824let isCVI = 1;
35825let isPseudo = 1;
35826let isCodeGenOnly = 1;
35827let DecoderNamespace = "EXT_mmvec";
35828}
35829def V6_vmpyhus : HInst<
35830(outs HvxWR:$Vdd32),
35831(ins HvxVR:$Vu32, HvxVR:$Vv32),
35832"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
35833tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35834let Inst{7-5} = 0b010;
35835let Inst{13-13} = 0b0;
35836let Inst{31-21} = 0b00011100001;
35837let hasNewValue = 1;
35838let opNewValue = 0;
35839let isCVI = 1;
35840let DecoderNamespace = "EXT_mmvec";
35841}
35842def V6_vmpyhus_acc : HInst<
35843(outs HvxWR:$Vxx32),
35844(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35845"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
35846tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35847let Inst{7-5} = 0b001;
35848let Inst{13-13} = 0b1;
35849let Inst{31-21} = 0b00011100001;
35850let hasNewValue = 1;
35851let opNewValue = 0;
35852let isAccumulator = 1;
35853let isCVI = 1;
35854let DecoderNamespace = "EXT_mmvec";
35855let Constraints = "$Vxx32 = $Vxx32in";
35856}
35857def V6_vmpyhus_acc_alt : HInst<
35858(outs HvxWR:$Vxx32),
35859(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35860"$Vxx32 += vmpyhus($Vu32,$Vv32)",
35861PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35862let hasNewValue = 1;
35863let opNewValue = 0;
35864let isAccumulator = 1;
35865let isCVI = 1;
35866let isPseudo = 1;
35867let isCodeGenOnly = 1;
35868let DecoderNamespace = "EXT_mmvec";
35869let Constraints = "$Vxx32 = $Vxx32in";
35870}
35871def V6_vmpyhus_alt : HInst<
35872(outs HvxWR:$Vdd32),
35873(ins HvxVR:$Vu32, HvxVR:$Vv32),
35874"$Vdd32 = vmpyhus($Vu32,$Vv32)",
35875PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35876let hasNewValue = 1;
35877let opNewValue = 0;
35878let isCVI = 1;
35879let isPseudo = 1;
35880let isCodeGenOnly = 1;
35881let DecoderNamespace = "EXT_mmvec";
35882}
35883def V6_vmpyhv : HInst<
35884(outs HvxWR:$Vdd32),
35885(ins HvxVR:$Vu32, HvxVR:$Vv32),
35886"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
35887tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35888let Inst{7-5} = 0b111;
35889let Inst{13-13} = 0b0;
35890let Inst{31-21} = 0b00011100000;
35891let hasNewValue = 1;
35892let opNewValue = 0;
35893let isCVI = 1;
35894let DecoderNamespace = "EXT_mmvec";
35895}
35896def V6_vmpyhv_acc : HInst<
35897(outs HvxWR:$Vxx32),
35898(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35899"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
35900tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35901let Inst{7-5} = 0b111;
35902let Inst{13-13} = 0b1;
35903let Inst{31-21} = 0b00011100000;
35904let hasNewValue = 1;
35905let opNewValue = 0;
35906let isAccumulator = 1;
35907let isCVI = 1;
35908let DecoderNamespace = "EXT_mmvec";
35909let Constraints = "$Vxx32 = $Vxx32in";
35910}
35911def V6_vmpyhv_acc_alt : HInst<
35912(outs HvxWR:$Vxx32),
35913(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35914"$Vxx32 += vmpyh($Vu32,$Vv32)",
35915PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35916let hasNewValue = 1;
35917let opNewValue = 0;
35918let isAccumulator = 1;
35919let isCVI = 1;
35920let isPseudo = 1;
35921let isCodeGenOnly = 1;
35922let DecoderNamespace = "EXT_mmvec";
35923let Constraints = "$Vxx32 = $Vxx32in";
35924}
35925def V6_vmpyhv_alt : HInst<
35926(outs HvxWR:$Vdd32),
35927(ins HvxVR:$Vu32, HvxVR:$Vv32),
35928"$Vdd32 = vmpyh($Vu32,$Vv32)",
35929PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35930let hasNewValue = 1;
35931let opNewValue = 0;
35932let isCVI = 1;
35933let isPseudo = 1;
35934let isCodeGenOnly = 1;
35935let DecoderNamespace = "EXT_mmvec";
35936}
35937def V6_vmpyhvsrs : HInst<
35938(outs HvxVR:$Vd32),
35939(ins HvxVR:$Vu32, HvxVR:$Vv32),
35940"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
35941tc_73efe966, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35942let Inst{7-5} = 0b001;
35943let Inst{13-13} = 0b0;
35944let Inst{31-21} = 0b00011100001;
35945let hasNewValue = 1;
35946let opNewValue = 0;
35947let isCVI = 1;
35948let DecoderNamespace = "EXT_mmvec";
35949}
35950def V6_vmpyhvsrs_alt : HInst<
35951(outs HvxVR:$Vd32),
35952(ins HvxVR:$Vu32, HvxVR:$Vv32),
35953"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
35954PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35955let hasNewValue = 1;
35956let opNewValue = 0;
35957let isCVI = 1;
35958let isPseudo = 1;
35959let isCodeGenOnly = 1;
35960let DecoderNamespace = "EXT_mmvec";
35961}
35962def V6_vmpyieoh : HInst<
35963(outs HvxVR:$Vd32),
35964(ins HvxVR:$Vu32, HvxVR:$Vv32),
35965"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
35966tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35967let Inst{7-5} = 0b000;
35968let Inst{13-13} = 0b0;
35969let Inst{31-21} = 0b00011111011;
35970let hasNewValue = 1;
35971let opNewValue = 0;
35972let isCVI = 1;
35973let DecoderNamespace = "EXT_mmvec";
35974}
35975def V6_vmpyiewh_acc : HInst<
35976(outs HvxVR:$Vx32),
35977(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35978"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
35979tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35980let Inst{7-5} = 0b000;
35981let Inst{13-13} = 0b1;
35982let Inst{31-21} = 0b00011100010;
35983let hasNewValue = 1;
35984let opNewValue = 0;
35985let isAccumulator = 1;
35986let isCVI = 1;
35987let DecoderNamespace = "EXT_mmvec";
35988let Constraints = "$Vx32 = $Vx32in";
35989}
35990def V6_vmpyiewh_acc_alt : HInst<
35991(outs HvxVR:$Vx32),
35992(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35993"$Vx32 += vmpyiewh($Vu32,$Vv32)",
35994PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35995let hasNewValue = 1;
35996let opNewValue = 0;
35997let isAccumulator = 1;
35998let isCVI = 1;
35999let isPseudo = 1;
36000let isCodeGenOnly = 1;
36001let DecoderNamespace = "EXT_mmvec";
36002let Constraints = "$Vx32 = $Vx32in";
36003}
36004def V6_vmpyiewuh : HInst<
36005(outs HvxVR:$Vd32),
36006(ins HvxVR:$Vu32, HvxVR:$Vv32),
36007"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
36008tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36009let Inst{7-5} = 0b000;
36010let Inst{13-13} = 0b0;
36011let Inst{31-21} = 0b00011111110;
36012let hasNewValue = 1;
36013let opNewValue = 0;
36014let isCVI = 1;
36015let DecoderNamespace = "EXT_mmvec";
36016}
36017def V6_vmpyiewuh_acc : HInst<
36018(outs HvxVR:$Vx32),
36019(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36020"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
36021tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36022let Inst{7-5} = 0b101;
36023let Inst{13-13} = 0b1;
36024let Inst{31-21} = 0b00011100001;
36025let hasNewValue = 1;
36026let opNewValue = 0;
36027let isAccumulator = 1;
36028let isCVI = 1;
36029let DecoderNamespace = "EXT_mmvec";
36030let Constraints = "$Vx32 = $Vx32in";
36031}
36032def V6_vmpyiewuh_acc_alt : HInst<
36033(outs HvxVR:$Vx32),
36034(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36035"$Vx32 += vmpyiewuh($Vu32,$Vv32)",
36036PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36037let hasNewValue = 1;
36038let opNewValue = 0;
36039let isAccumulator = 1;
36040let isCVI = 1;
36041let isPseudo = 1;
36042let isCodeGenOnly = 1;
36043let DecoderNamespace = "EXT_mmvec";
36044let Constraints = "$Vx32 = $Vx32in";
36045}
36046def V6_vmpyiewuh_alt : HInst<
36047(outs HvxVR:$Vd32),
36048(ins HvxVR:$Vu32, HvxVR:$Vv32),
36049"$Vd32 = vmpyiewuh($Vu32,$Vv32)",
36050PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36051let hasNewValue = 1;
36052let opNewValue = 0;
36053let isCVI = 1;
36054let isPseudo = 1;
36055let isCodeGenOnly = 1;
36056let DecoderNamespace = "EXT_mmvec";
36057}
36058def V6_vmpyih : HInst<
36059(outs HvxVR:$Vd32),
36060(ins HvxVR:$Vu32, HvxVR:$Vv32),
36061"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
36062tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36063let Inst{7-5} = 0b100;
36064let Inst{13-13} = 0b0;
36065let Inst{31-21} = 0b00011100001;
36066let hasNewValue = 1;
36067let opNewValue = 0;
36068let isCVI = 1;
36069let DecoderNamespace = "EXT_mmvec";
36070}
36071def V6_vmpyih_acc : HInst<
36072(outs HvxVR:$Vx32),
36073(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36074"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
36075tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36076let Inst{7-5} = 0b100;
36077let Inst{13-13} = 0b1;
36078let Inst{31-21} = 0b00011100001;
36079let hasNewValue = 1;
36080let opNewValue = 0;
36081let isAccumulator = 1;
36082let isCVI = 1;
36083let DecoderNamespace = "EXT_mmvec";
36084let Constraints = "$Vx32 = $Vx32in";
36085}
36086def V6_vmpyih_acc_alt : HInst<
36087(outs HvxVR:$Vx32),
36088(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36089"$Vx32 += vmpyih($Vu32,$Vv32)",
36090PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36091let hasNewValue = 1;
36092let opNewValue = 0;
36093let isAccumulator = 1;
36094let isCVI = 1;
36095let isPseudo = 1;
36096let isCodeGenOnly = 1;
36097let DecoderNamespace = "EXT_mmvec";
36098let Constraints = "$Vx32 = $Vx32in";
36099}
36100def V6_vmpyih_alt : HInst<
36101(outs HvxVR:$Vd32),
36102(ins HvxVR:$Vu32, HvxVR:$Vv32),
36103"$Vd32 = vmpyih($Vu32,$Vv32)",
36104PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36105let hasNewValue = 1;
36106let opNewValue = 0;
36107let isCVI = 1;
36108let isPseudo = 1;
36109let isCodeGenOnly = 1;
36110let DecoderNamespace = "EXT_mmvec";
36111}
36112def V6_vmpyihb : HInst<
36113(outs HvxVR:$Vd32),
36114(ins HvxVR:$Vu32, IntRegs:$Rt32),
36115"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
36116tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
36117let Inst{7-5} = 0b000;
36118let Inst{13-13} = 0b0;
36119let Inst{31-21} = 0b00011001011;
36120let hasNewValue = 1;
36121let opNewValue = 0;
36122let isCVI = 1;
36123let DecoderNamespace = "EXT_mmvec";
36124}
36125def V6_vmpyihb_acc : HInst<
36126(outs HvxVR:$Vx32),
36127(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36128"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
36129tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
36130let Inst{7-5} = 0b001;
36131let Inst{13-13} = 0b1;
36132let Inst{31-21} = 0b00011001011;
36133let hasNewValue = 1;
36134let opNewValue = 0;
36135let isAccumulator = 1;
36136let isCVI = 1;
36137let DecoderNamespace = "EXT_mmvec";
36138let Constraints = "$Vx32 = $Vx32in";
36139}
36140def V6_vmpyihb_acc_alt : HInst<
36141(outs HvxVR:$Vx32),
36142(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36143"$Vx32 += vmpyihb($Vu32,$Rt32)",
36144PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36145let hasNewValue = 1;
36146let opNewValue = 0;
36147let isAccumulator = 1;
36148let isCVI = 1;
36149let isPseudo = 1;
36150let isCodeGenOnly = 1;
36151let DecoderNamespace = "EXT_mmvec";
36152let Constraints = "$Vx32 = $Vx32in";
36153}
36154def V6_vmpyihb_alt : HInst<
36155(outs HvxVR:$Vd32),
36156(ins HvxVR:$Vu32, IntRegs:$Rt32),
36157"$Vd32 = vmpyihb($Vu32,$Rt32)",
36158PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36159let hasNewValue = 1;
36160let opNewValue = 0;
36161let isCVI = 1;
36162let isPseudo = 1;
36163let isCodeGenOnly = 1;
36164let DecoderNamespace = "EXT_mmvec";
36165}
36166def V6_vmpyiowh : HInst<
36167(outs HvxVR:$Vd32),
36168(ins HvxVR:$Vu32, HvxVR:$Vv32),
36169"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
36170tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36171let Inst{7-5} = 0b001;
36172let Inst{13-13} = 0b0;
36173let Inst{31-21} = 0b00011111110;
36174let hasNewValue = 1;
36175let opNewValue = 0;
36176let isCVI = 1;
36177let DecoderNamespace = "EXT_mmvec";
36178}
36179def V6_vmpyiowh_alt : HInst<
36180(outs HvxVR:$Vd32),
36181(ins HvxVR:$Vu32, HvxVR:$Vv32),
36182"$Vd32 = vmpyiowh($Vu32,$Vv32)",
36183PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36184let hasNewValue = 1;
36185let opNewValue = 0;
36186let isCVI = 1;
36187let isPseudo = 1;
36188let isCodeGenOnly = 1;
36189let DecoderNamespace = "EXT_mmvec";
36190}
36191def V6_vmpyiwb : HInst<
36192(outs HvxVR:$Vd32),
36193(ins HvxVR:$Vu32, IntRegs:$Rt32),
36194"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
36195tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
36196let Inst{7-5} = 0b000;
36197let Inst{13-13} = 0b0;
36198let Inst{31-21} = 0b00011001101;
36199let hasNewValue = 1;
36200let opNewValue = 0;
36201let isCVI = 1;
36202let DecoderNamespace = "EXT_mmvec";
36203}
36204def V6_vmpyiwb_acc : HInst<
36205(outs HvxVR:$Vx32),
36206(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36207"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
36208tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
36209let Inst{7-5} = 0b010;
36210let Inst{13-13} = 0b1;
36211let Inst{31-21} = 0b00011001010;
36212let hasNewValue = 1;
36213let opNewValue = 0;
36214let isAccumulator = 1;
36215let isCVI = 1;
36216let DecoderNamespace = "EXT_mmvec";
36217let Constraints = "$Vx32 = $Vx32in";
36218}
36219def V6_vmpyiwb_acc_alt : HInst<
36220(outs HvxVR:$Vx32),
36221(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36222"$Vx32 += vmpyiwb($Vu32,$Rt32)",
36223PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36224let hasNewValue = 1;
36225let opNewValue = 0;
36226let isAccumulator = 1;
36227let isCVI = 1;
36228let isPseudo = 1;
36229let isCodeGenOnly = 1;
36230let DecoderNamespace = "EXT_mmvec";
36231let Constraints = "$Vx32 = $Vx32in";
36232}
36233def V6_vmpyiwb_alt : HInst<
36234(outs HvxVR:$Vd32),
36235(ins HvxVR:$Vu32, IntRegs:$Rt32),
36236"$Vd32 = vmpyiwb($Vu32,$Rt32)",
36237PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36238let hasNewValue = 1;
36239let opNewValue = 0;
36240let isCVI = 1;
36241let isPseudo = 1;
36242let isCodeGenOnly = 1;
36243let DecoderNamespace = "EXT_mmvec";
36244}
36245def V6_vmpyiwh : HInst<
36246(outs HvxVR:$Vd32),
36247(ins HvxVR:$Vu32, IntRegs:$Rt32),
36248"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
36249tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
36250let Inst{7-5} = 0b111;
36251let Inst{13-13} = 0b0;
36252let Inst{31-21} = 0b00011001100;
36253let hasNewValue = 1;
36254let opNewValue = 0;
36255let isCVI = 1;
36256let DecoderNamespace = "EXT_mmvec";
36257}
36258def V6_vmpyiwh_acc : HInst<
36259(outs HvxVR:$Vx32),
36260(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36261"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
36262tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
36263let Inst{7-5} = 0b011;
36264let Inst{13-13} = 0b1;
36265let Inst{31-21} = 0b00011001010;
36266let hasNewValue = 1;
36267let opNewValue = 0;
36268let isAccumulator = 1;
36269let isCVI = 1;
36270let DecoderNamespace = "EXT_mmvec";
36271let Constraints = "$Vx32 = $Vx32in";
36272}
36273def V6_vmpyiwh_acc_alt : HInst<
36274(outs HvxVR:$Vx32),
36275(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36276"$Vx32 += vmpyiwh($Vu32,$Rt32)",
36277PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36278let hasNewValue = 1;
36279let opNewValue = 0;
36280let isAccumulator = 1;
36281let isCVI = 1;
36282let isPseudo = 1;
36283let isCodeGenOnly = 1;
36284let DecoderNamespace = "EXT_mmvec";
36285let Constraints = "$Vx32 = $Vx32in";
36286}
36287def V6_vmpyiwh_alt : HInst<
36288(outs HvxVR:$Vd32),
36289(ins HvxVR:$Vu32, IntRegs:$Rt32),
36290"$Vd32 = vmpyiwh($Vu32,$Rt32)",
36291PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36292let hasNewValue = 1;
36293let opNewValue = 0;
36294let isCVI = 1;
36295let isPseudo = 1;
36296let isCodeGenOnly = 1;
36297let DecoderNamespace = "EXT_mmvec";
36298}
36299def V6_vmpyiwub : HInst<
36300(outs HvxVR:$Vd32),
36301(ins HvxVR:$Vu32, IntRegs:$Rt32),
36302"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
36303tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
36304let Inst{7-5} = 0b110;
36305let Inst{13-13} = 0b0;
36306let Inst{31-21} = 0b00011001100;
36307let hasNewValue = 1;
36308let opNewValue = 0;
36309let isCVI = 1;
36310let DecoderNamespace = "EXT_mmvec";
36311}
36312def V6_vmpyiwub_acc : HInst<
36313(outs HvxVR:$Vx32),
36314(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36315"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
36316tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
36317let Inst{7-5} = 0b001;
36318let Inst{13-13} = 0b1;
36319let Inst{31-21} = 0b00011001100;
36320let hasNewValue = 1;
36321let opNewValue = 0;
36322let isAccumulator = 1;
36323let isCVI = 1;
36324let DecoderNamespace = "EXT_mmvec";
36325let Constraints = "$Vx32 = $Vx32in";
36326}
36327def V6_vmpyiwub_acc_alt : HInst<
36328(outs HvxVR:$Vx32),
36329(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36330"$Vx32 += vmpyiwub($Vu32,$Rt32)",
36331PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36332let hasNewValue = 1;
36333let opNewValue = 0;
36334let isAccumulator = 1;
36335let isCVI = 1;
36336let isPseudo = 1;
36337let isCodeGenOnly = 1;
36338let DecoderNamespace = "EXT_mmvec";
36339let Constraints = "$Vx32 = $Vx32in";
36340}
36341def V6_vmpyiwub_alt : HInst<
36342(outs HvxVR:$Vd32),
36343(ins HvxVR:$Vu32, IntRegs:$Rt32),
36344"$Vd32 = vmpyiwub($Vu32,$Rt32)",
36345PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36346let hasNewValue = 1;
36347let opNewValue = 0;
36348let isCVI = 1;
36349let isPseudo = 1;
36350let isCodeGenOnly = 1;
36351let DecoderNamespace = "EXT_mmvec";
36352}
36353def V6_vmpyowh : HInst<
36354(outs HvxVR:$Vd32),
36355(ins HvxVR:$Vu32, HvxVR:$Vv32),
36356"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
36357tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36358let Inst{7-5} = 0b111;
36359let Inst{13-13} = 0b0;
36360let Inst{31-21} = 0b00011111111;
36361let hasNewValue = 1;
36362let opNewValue = 0;
36363let isCVI = 1;
36364let DecoderNamespace = "EXT_mmvec";
36365}
36366def V6_vmpyowh_64_acc : HInst<
36367(outs HvxWR:$Vxx32),
36368(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36369"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
36370tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
36371let Inst{7-5} = 0b011;
36372let Inst{13-13} = 0b1;
36373let Inst{31-21} = 0b00011100001;
36374let hasNewValue = 1;
36375let opNewValue = 0;
36376let isAccumulator = 1;
36377let isCVI = 1;
36378let DecoderNamespace = "EXT_mmvec";
36379let Constraints = "$Vxx32 = $Vxx32in";
36380}
36381def V6_vmpyowh_alt : HInst<
36382(outs HvxVR:$Vd32),
36383(ins HvxVR:$Vu32, HvxVR:$Vv32),
36384"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
36385PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36386let hasNewValue = 1;
36387let opNewValue = 0;
36388let isCVI = 1;
36389let isPseudo = 1;
36390let isCodeGenOnly = 1;
36391let DecoderNamespace = "EXT_mmvec";
36392}
36393def V6_vmpyowh_rnd : HInst<
36394(outs HvxVR:$Vd32),
36395(ins HvxVR:$Vu32, HvxVR:$Vv32),
36396"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
36397tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36398let Inst{7-5} = 0b000;
36399let Inst{13-13} = 0b0;
36400let Inst{31-21} = 0b00011111010;
36401let hasNewValue = 1;
36402let opNewValue = 0;
36403let isCVI = 1;
36404let DecoderNamespace = "EXT_mmvec";
36405}
36406def V6_vmpyowh_rnd_alt : HInst<
36407(outs HvxVR:$Vd32),
36408(ins HvxVR:$Vu32, HvxVR:$Vv32),
36409"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
36410PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36411let hasNewValue = 1;
36412let opNewValue = 0;
36413let isCVI = 1;
36414let isPseudo = 1;
36415let isCodeGenOnly = 1;
36416let DecoderNamespace = "EXT_mmvec";
36417}
36418def V6_vmpyowh_rnd_sacc : HInst<
36419(outs HvxVR:$Vx32),
36420(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36421"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
36422tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36423let Inst{7-5} = 0b111;
36424let Inst{13-13} = 0b1;
36425let Inst{31-21} = 0b00011100001;
36426let hasNewValue = 1;
36427let opNewValue = 0;
36428let isAccumulator = 1;
36429let isCVI = 1;
36430let DecoderNamespace = "EXT_mmvec";
36431let Constraints = "$Vx32 = $Vx32in";
36432}
36433def V6_vmpyowh_rnd_sacc_alt : HInst<
36434(outs HvxVR:$Vx32),
36435(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36436"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
36437PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36438let hasNewValue = 1;
36439let opNewValue = 0;
36440let isAccumulator = 1;
36441let isCVI = 1;
36442let isPseudo = 1;
36443let DecoderNamespace = "EXT_mmvec";
36444let Constraints = "$Vx32 = $Vx32in";
36445}
36446def V6_vmpyowh_sacc : HInst<
36447(outs HvxVR:$Vx32),
36448(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36449"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
36450tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36451let Inst{7-5} = 0b110;
36452let Inst{13-13} = 0b1;
36453let Inst{31-21} = 0b00011100001;
36454let hasNewValue = 1;
36455let opNewValue = 0;
36456let isAccumulator = 1;
36457let isCVI = 1;
36458let DecoderNamespace = "EXT_mmvec";
36459let Constraints = "$Vx32 = $Vx32in";
36460}
36461def V6_vmpyowh_sacc_alt : HInst<
36462(outs HvxVR:$Vx32),
36463(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36464"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
36465PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36466let hasNewValue = 1;
36467let opNewValue = 0;
36468let isAccumulator = 1;
36469let isCVI = 1;
36470let isPseudo = 1;
36471let DecoderNamespace = "EXT_mmvec";
36472let Constraints = "$Vx32 = $Vx32in";
36473}
36474def V6_vmpyub : HInst<
36475(outs HvxWR:$Vdd32),
36476(ins HvxVR:$Vu32, IntRegs:$Rt32),
36477"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
36478tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
36479let Inst{7-5} = 0b000;
36480let Inst{13-13} = 0b0;
36481let Inst{31-21} = 0b00011001110;
36482let hasNewValue = 1;
36483let opNewValue = 0;
36484let isCVI = 1;
36485let DecoderNamespace = "EXT_mmvec";
36486}
36487def V6_vmpyub_acc : HInst<
36488(outs HvxWR:$Vxx32),
36489(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36490"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
36491tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
36492let Inst{7-5} = 0b000;
36493let Inst{13-13} = 0b1;
36494let Inst{31-21} = 0b00011001100;
36495let hasNewValue = 1;
36496let opNewValue = 0;
36497let isAccumulator = 1;
36498let isCVI = 1;
36499let DecoderNamespace = "EXT_mmvec";
36500let Constraints = "$Vxx32 = $Vxx32in";
36501}
36502def V6_vmpyub_acc_alt : HInst<
36503(outs HvxWR:$Vxx32),
36504(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36505"$Vxx32 += vmpyub($Vu32,$Rt32)",
36506PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36507let hasNewValue = 1;
36508let opNewValue = 0;
36509let isAccumulator = 1;
36510let isCVI = 1;
36511let isPseudo = 1;
36512let isCodeGenOnly = 1;
36513let DecoderNamespace = "EXT_mmvec";
36514let Constraints = "$Vxx32 = $Vxx32in";
36515}
36516def V6_vmpyub_alt : HInst<
36517(outs HvxWR:$Vdd32),
36518(ins HvxVR:$Vu32, IntRegs:$Rt32),
36519"$Vdd32 = vmpyub($Vu32,$Rt32)",
36520PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36521let hasNewValue = 1;
36522let opNewValue = 0;
36523let isCVI = 1;
36524let isPseudo = 1;
36525let isCodeGenOnly = 1;
36526let DecoderNamespace = "EXT_mmvec";
36527}
36528def V6_vmpyubv : HInst<
36529(outs HvxWR:$Vdd32),
36530(ins HvxVR:$Vu32, HvxVR:$Vv32),
36531"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
36532tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36533let Inst{7-5} = 0b101;
36534let Inst{13-13} = 0b0;
36535let Inst{31-21} = 0b00011100000;
36536let hasNewValue = 1;
36537let opNewValue = 0;
36538let isCVI = 1;
36539let DecoderNamespace = "EXT_mmvec";
36540}
36541def V6_vmpyubv_acc : HInst<
36542(outs HvxWR:$Vxx32),
36543(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36544"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
36545tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
36546let Inst{7-5} = 0b101;
36547let Inst{13-13} = 0b1;
36548let Inst{31-21} = 0b00011100000;
36549let hasNewValue = 1;
36550let opNewValue = 0;
36551let isAccumulator = 1;
36552let isCVI = 1;
36553let DecoderNamespace = "EXT_mmvec";
36554let Constraints = "$Vxx32 = $Vxx32in";
36555}
36556def V6_vmpyubv_acc_alt : HInst<
36557(outs HvxWR:$Vxx32),
36558(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36559"$Vxx32 += vmpyub($Vu32,$Vv32)",
36560PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36561let hasNewValue = 1;
36562let opNewValue = 0;
36563let isAccumulator = 1;
36564let isCVI = 1;
36565let isPseudo = 1;
36566let isCodeGenOnly = 1;
36567let DecoderNamespace = "EXT_mmvec";
36568let Constraints = "$Vxx32 = $Vxx32in";
36569}
36570def V6_vmpyubv_alt : HInst<
36571(outs HvxWR:$Vdd32),
36572(ins HvxVR:$Vu32, HvxVR:$Vv32),
36573"$Vdd32 = vmpyub($Vu32,$Vv32)",
36574PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36575let hasNewValue = 1;
36576let opNewValue = 0;
36577let isCVI = 1;
36578let isPseudo = 1;
36579let isCodeGenOnly = 1;
36580let DecoderNamespace = "EXT_mmvec";
36581}
36582def V6_vmpyuh : HInst<
36583(outs HvxWR:$Vdd32),
36584(ins HvxVR:$Vu32, IntRegs:$Rt32),
36585"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
36586tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
36587let Inst{7-5} = 0b011;
36588let Inst{13-13} = 0b0;
36589let Inst{31-21} = 0b00011001010;
36590let hasNewValue = 1;
36591let opNewValue = 0;
36592let isCVI = 1;
36593let DecoderNamespace = "EXT_mmvec";
36594}
36595def V6_vmpyuh_acc : HInst<
36596(outs HvxWR:$Vxx32),
36597(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36598"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
36599tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
36600let Inst{7-5} = 0b001;
36601let Inst{13-13} = 0b1;
36602let Inst{31-21} = 0b00011001010;
36603let hasNewValue = 1;
36604let opNewValue = 0;
36605let isAccumulator = 1;
36606let isCVI = 1;
36607let DecoderNamespace = "EXT_mmvec";
36608let Constraints = "$Vxx32 = $Vxx32in";
36609}
36610def V6_vmpyuh_acc_alt : HInst<
36611(outs HvxWR:$Vxx32),
36612(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36613"$Vxx32 += vmpyuh($Vu32,$Rt32)",
36614PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36615let hasNewValue = 1;
36616let opNewValue = 0;
36617let isAccumulator = 1;
36618let isCVI = 1;
36619let isPseudo = 1;
36620let isCodeGenOnly = 1;
36621let DecoderNamespace = "EXT_mmvec";
36622let Constraints = "$Vxx32 = $Vxx32in";
36623}
36624def V6_vmpyuh_alt : HInst<
36625(outs HvxWR:$Vdd32),
36626(ins HvxVR:$Vu32, IntRegs:$Rt32),
36627"$Vdd32 = vmpyuh($Vu32,$Rt32)",
36628PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36629let hasNewValue = 1;
36630let opNewValue = 0;
36631let isCVI = 1;
36632let isPseudo = 1;
36633let isCodeGenOnly = 1;
36634let DecoderNamespace = "EXT_mmvec";
36635}
36636def V6_vmpyuhe : HInst<
36637(outs HvxVR:$Vd32),
36638(ins HvxVR:$Vu32, IntRegs:$Rt32),
36639"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
36640tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
36641let Inst{7-5} = 0b010;
36642let Inst{13-13} = 0b0;
36643let Inst{31-21} = 0b00011001011;
36644let hasNewValue = 1;
36645let opNewValue = 0;
36646let isCVI = 1;
36647let DecoderNamespace = "EXT_mmvec";
36648}
36649def V6_vmpyuhe_acc : HInst<
36650(outs HvxVR:$Vx32),
36651(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36652"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
36653tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
36654let Inst{7-5} = 0b011;
36655let Inst{13-13} = 0b1;
36656let Inst{31-21} = 0b00011001100;
36657let hasNewValue = 1;
36658let opNewValue = 0;
36659let isAccumulator = 1;
36660let isCVI = 1;
36661let DecoderNamespace = "EXT_mmvec";
36662let Constraints = "$Vx32 = $Vx32in";
36663}
36664def V6_vmpyuhv : HInst<
36665(outs HvxWR:$Vdd32),
36666(ins HvxVR:$Vu32, HvxVR:$Vv32),
36667"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
36668tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36669let Inst{7-5} = 0b000;
36670let Inst{13-13} = 0b0;
36671let Inst{31-21} = 0b00011100001;
36672let hasNewValue = 1;
36673let opNewValue = 0;
36674let isCVI = 1;
36675let DecoderNamespace = "EXT_mmvec";
36676}
36677def V6_vmpyuhv_acc : HInst<
36678(outs HvxWR:$Vxx32),
36679(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36680"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
36681tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
36682let Inst{7-5} = 0b000;
36683let Inst{13-13} = 0b1;
36684let Inst{31-21} = 0b00011100001;
36685let hasNewValue = 1;
36686let opNewValue = 0;
36687let isAccumulator = 1;
36688let isCVI = 1;
36689let DecoderNamespace = "EXT_mmvec";
36690let Constraints = "$Vxx32 = $Vxx32in";
36691}
36692def V6_vmpyuhv_acc_alt : HInst<
36693(outs HvxWR:$Vxx32),
36694(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36695"$Vxx32 += vmpyuh($Vu32,$Vv32)",
36696PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36697let hasNewValue = 1;
36698let opNewValue = 0;
36699let isAccumulator = 1;
36700let isCVI = 1;
36701let isPseudo = 1;
36702let isCodeGenOnly = 1;
36703let DecoderNamespace = "EXT_mmvec";
36704let Constraints = "$Vxx32 = $Vxx32in";
36705}
36706def V6_vmpyuhv_alt : HInst<
36707(outs HvxWR:$Vdd32),
36708(ins HvxVR:$Vu32, HvxVR:$Vv32),
36709"$Vdd32 = vmpyuh($Vu32,$Vv32)",
36710PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36711let hasNewValue = 1;
36712let opNewValue = 0;
36713let isCVI = 1;
36714let isPseudo = 1;
36715let isCodeGenOnly = 1;
36716let DecoderNamespace = "EXT_mmvec";
36717}
36718def V6_vmpyuhvs : HInst<
36719(outs HvxVR:$Vd32),
36720(ins HvxVR:$Vu32, HvxVR:$Vv32),
36721"$Vd32.uh = vmpy($Vu32.uh,$Vv32.uh):>>16",
36722tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV69]> {
36723let Inst{7-5} = 0b111;
36724let Inst{13-13} = 0b1;
36725let Inst{31-21} = 0b00011111110;
36726let hasNewValue = 1;
36727let opNewValue = 0;
36728let isCVI = 1;
36729let DecoderNamespace = "EXT_mmvec";
36730}
36731def V6_vmux : HInst<
36732(outs HvxVR:$Vd32),
36733(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
36734"$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
36735tc_257f6f7c, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
36736let Inst{7-7} = 0b0;
36737let Inst{13-13} = 0b1;
36738let Inst{31-21} = 0b00011110111;
36739let hasNewValue = 1;
36740let opNewValue = 0;
36741let isCVI = 1;
36742let isHVXALU = 1;
36743let isHVXALU2SRC = 1;
36744let DecoderNamespace = "EXT_mmvec";
36745}
36746def V6_vnavgb : HInst<
36747(outs HvxVR:$Vd32),
36748(ins HvxVR:$Vu32, HvxVR:$Vv32),
36749"$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
36750tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
36751let Inst{7-5} = 0b110;
36752let Inst{13-13} = 0b1;
36753let Inst{31-21} = 0b00011111000;
36754let hasNewValue = 1;
36755let opNewValue = 0;
36756let isCVI = 1;
36757let isHVXALU = 1;
36758let isHVXALU2SRC = 1;
36759let DecoderNamespace = "EXT_mmvec";
36760}
36761def V6_vnavgb_alt : HInst<
36762(outs HvxVR:$Vd32),
36763(ins HvxVR:$Vu32, HvxVR:$Vv32),
36764"$Vd32 = vnavgb($Vu32,$Vv32)",
36765PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36766let hasNewValue = 1;
36767let opNewValue = 0;
36768let isCVI = 1;
36769let isPseudo = 1;
36770let isCodeGenOnly = 1;
36771let DecoderNamespace = "EXT_mmvec";
36772}
36773def V6_vnavgh : HInst<
36774(outs HvxVR:$Vd32),
36775(ins HvxVR:$Vu32, HvxVR:$Vv32),
36776"$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
36777tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36778let Inst{7-5} = 0b001;
36779let Inst{13-13} = 0b0;
36780let Inst{31-21} = 0b00011100111;
36781let hasNewValue = 1;
36782let opNewValue = 0;
36783let isCVI = 1;
36784let isHVXALU = 1;
36785let isHVXALU2SRC = 1;
36786let DecoderNamespace = "EXT_mmvec";
36787}
36788def V6_vnavgh_alt : HInst<
36789(outs HvxVR:$Vd32),
36790(ins HvxVR:$Vu32, HvxVR:$Vv32),
36791"$Vd32 = vnavgh($Vu32,$Vv32)",
36792PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36793let hasNewValue = 1;
36794let opNewValue = 0;
36795let isCVI = 1;
36796let isPseudo = 1;
36797let isCodeGenOnly = 1;
36798let DecoderNamespace = "EXT_mmvec";
36799}
36800def V6_vnavgub : HInst<
36801(outs HvxVR:$Vd32),
36802(ins HvxVR:$Vu32, HvxVR:$Vv32),
36803"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
36804tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36805let Inst{7-5} = 0b000;
36806let Inst{13-13} = 0b0;
36807let Inst{31-21} = 0b00011100111;
36808let hasNewValue = 1;
36809let opNewValue = 0;
36810let isCVI = 1;
36811let isHVXALU = 1;
36812let isHVXALU2SRC = 1;
36813let DecoderNamespace = "EXT_mmvec";
36814}
36815def V6_vnavgub_alt : HInst<
36816(outs HvxVR:$Vd32),
36817(ins HvxVR:$Vu32, HvxVR:$Vv32),
36818"$Vd32 = vnavgub($Vu32,$Vv32)",
36819PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36820let hasNewValue = 1;
36821let opNewValue = 0;
36822let isCVI = 1;
36823let isPseudo = 1;
36824let isCodeGenOnly = 1;
36825let DecoderNamespace = "EXT_mmvec";
36826}
36827def V6_vnavgw : HInst<
36828(outs HvxVR:$Vd32),
36829(ins HvxVR:$Vu32, HvxVR:$Vv32),
36830"$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
36831tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36832let Inst{7-5} = 0b010;
36833let Inst{13-13} = 0b0;
36834let Inst{31-21} = 0b00011100111;
36835let hasNewValue = 1;
36836let opNewValue = 0;
36837let isCVI = 1;
36838let isHVXALU = 1;
36839let isHVXALU2SRC = 1;
36840let DecoderNamespace = "EXT_mmvec";
36841}
36842def V6_vnavgw_alt : HInst<
36843(outs HvxVR:$Vd32),
36844(ins HvxVR:$Vu32, HvxVR:$Vv32),
36845"$Vd32 = vnavgw($Vu32,$Vv32)",
36846PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36847let hasNewValue = 1;
36848let opNewValue = 0;
36849let isCVI = 1;
36850let isPseudo = 1;
36851let isCodeGenOnly = 1;
36852let DecoderNamespace = "EXT_mmvec";
36853}
36854def V6_vnccombine : HInst<
36855(outs HvxWR:$Vdd32),
36856(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
36857"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
36858tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
36859let Inst{7-7} = 0b0;
36860let Inst{13-13} = 0b0;
36861let Inst{31-21} = 0b00011010010;
36862let isPredicated = 1;
36863let isPredicatedFalse = 1;
36864let hasNewValue = 1;
36865let opNewValue = 0;
36866let isCVI = 1;
36867let DecoderNamespace = "EXT_mmvec";
36868}
36869def V6_vncmov : HInst<
36870(outs HvxVR:$Vd32),
36871(ins PredRegs:$Ps4, HvxVR:$Vu32),
36872"if (!$Ps4) $Vd32 = $Vu32",
36873tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
36874let Inst{7-7} = 0b0;
36875let Inst{13-13} = 0b0;
36876let Inst{31-16} = 0b0001101000100000;
36877let isPredicated = 1;
36878let isPredicatedFalse = 1;
36879let hasNewValue = 1;
36880let opNewValue = 0;
36881let isCVI = 1;
36882let isHVXALU = 1;
36883let DecoderNamespace = "EXT_mmvec";
36884}
36885def V6_vnormamth : HInst<
36886(outs HvxVR:$Vd32),
36887(ins HvxVR:$Vu32),
36888"$Vd32.h = vnormamt($Vu32.h)",
36889tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
36890let Inst{7-5} = 0b101;
36891let Inst{13-13} = 0b0;
36892let Inst{31-16} = 0b0001111000000011;
36893let hasNewValue = 1;
36894let opNewValue = 0;
36895let isCVI = 1;
36896let DecoderNamespace = "EXT_mmvec";
36897}
36898def V6_vnormamth_alt : HInst<
36899(outs HvxVR:$Vd32),
36900(ins HvxVR:$Vu32),
36901"$Vd32 = vnormamth($Vu32)",
36902PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36903let hasNewValue = 1;
36904let opNewValue = 0;
36905let isCVI = 1;
36906let isPseudo = 1;
36907let isCodeGenOnly = 1;
36908let DecoderNamespace = "EXT_mmvec";
36909}
36910def V6_vnormamtw : HInst<
36911(outs HvxVR:$Vd32),
36912(ins HvxVR:$Vu32),
36913"$Vd32.w = vnormamt($Vu32.w)",
36914tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
36915let Inst{7-5} = 0b100;
36916let Inst{13-13} = 0b0;
36917let Inst{31-16} = 0b0001111000000011;
36918let hasNewValue = 1;
36919let opNewValue = 0;
36920let isCVI = 1;
36921let DecoderNamespace = "EXT_mmvec";
36922}
36923def V6_vnormamtw_alt : HInst<
36924(outs HvxVR:$Vd32),
36925(ins HvxVR:$Vu32),
36926"$Vd32 = vnormamtw($Vu32)",
36927PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36928let hasNewValue = 1;
36929let opNewValue = 0;
36930let isCVI = 1;
36931let isPseudo = 1;
36932let isCodeGenOnly = 1;
36933let DecoderNamespace = "EXT_mmvec";
36934}
36935def V6_vnot : HInst<
36936(outs HvxVR:$Vd32),
36937(ins HvxVR:$Vu32),
36938"$Vd32 = vnot($Vu32)",
36939tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
36940let Inst{7-5} = 0b100;
36941let Inst{13-13} = 0b0;
36942let Inst{31-16} = 0b0001111000000000;
36943let hasNewValue = 1;
36944let opNewValue = 0;
36945let isCVI = 1;
36946let isHVXALU = 1;
36947let isHVXALU2SRC = 1;
36948let DecoderNamespace = "EXT_mmvec";
36949}
36950def V6_vor : HInst<
36951(outs HvxVR:$Vd32),
36952(ins HvxVR:$Vu32, HvxVR:$Vv32),
36953"$Vd32 = vor($Vu32,$Vv32)",
36954tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36955let Inst{7-5} = 0b110;
36956let Inst{13-13} = 0b0;
36957let Inst{31-21} = 0b00011100001;
36958let hasNewValue = 1;
36959let opNewValue = 0;
36960let isCVI = 1;
36961let isHVXALU = 1;
36962let isHVXALU2SRC = 1;
36963let DecoderNamespace = "EXT_mmvec";
36964}
36965def V6_vpackeb : HInst<
36966(outs HvxVR:$Vd32),
36967(ins HvxVR:$Vu32, HvxVR:$Vv32),
36968"$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
36969tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36970let Inst{7-5} = 0b010;
36971let Inst{13-13} = 0b0;
36972let Inst{31-21} = 0b00011111110;
36973let hasNewValue = 1;
36974let opNewValue = 0;
36975let isCVI = 1;
36976let DecoderNamespace = "EXT_mmvec";
36977}
36978def V6_vpackeb_alt : HInst<
36979(outs HvxVR:$Vd32),
36980(ins HvxVR:$Vu32, HvxVR:$Vv32),
36981"$Vd32 = vpackeb($Vu32,$Vv32)",
36982PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36983let hasNewValue = 1;
36984let opNewValue = 0;
36985let isCVI = 1;
36986let isPseudo = 1;
36987let isCodeGenOnly = 1;
36988let DecoderNamespace = "EXT_mmvec";
36989}
36990def V6_vpackeh : HInst<
36991(outs HvxVR:$Vd32),
36992(ins HvxVR:$Vu32, HvxVR:$Vv32),
36993"$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
36994tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36995let Inst{7-5} = 0b011;
36996let Inst{13-13} = 0b0;
36997let Inst{31-21} = 0b00011111110;
36998let hasNewValue = 1;
36999let opNewValue = 0;
37000let isCVI = 1;
37001let DecoderNamespace = "EXT_mmvec";
37002}
37003def V6_vpackeh_alt : HInst<
37004(outs HvxVR:$Vd32),
37005(ins HvxVR:$Vu32, HvxVR:$Vv32),
37006"$Vd32 = vpackeh($Vu32,$Vv32)",
37007PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37008let hasNewValue = 1;
37009let opNewValue = 0;
37010let isCVI = 1;
37011let isPseudo = 1;
37012let isCodeGenOnly = 1;
37013let DecoderNamespace = "EXT_mmvec";
37014}
37015def V6_vpackhb_sat : HInst<
37016(outs HvxVR:$Vd32),
37017(ins HvxVR:$Vu32, HvxVR:$Vv32),
37018"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
37019tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37020let Inst{7-5} = 0b110;
37021let Inst{13-13} = 0b0;
37022let Inst{31-21} = 0b00011111110;
37023let hasNewValue = 1;
37024let opNewValue = 0;
37025let isCVI = 1;
37026let DecoderNamespace = "EXT_mmvec";
37027}
37028def V6_vpackhb_sat_alt : HInst<
37029(outs HvxVR:$Vd32),
37030(ins HvxVR:$Vu32, HvxVR:$Vv32),
37031"$Vd32 = vpackhb($Vu32,$Vv32):sat",
37032PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37033let hasNewValue = 1;
37034let opNewValue = 0;
37035let isCVI = 1;
37036let isPseudo = 1;
37037let isCodeGenOnly = 1;
37038let DecoderNamespace = "EXT_mmvec";
37039}
37040def V6_vpackhub_sat : HInst<
37041(outs HvxVR:$Vd32),
37042(ins HvxVR:$Vu32, HvxVR:$Vv32),
37043"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
37044tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37045let Inst{7-5} = 0b101;
37046let Inst{13-13} = 0b0;
37047let Inst{31-21} = 0b00011111110;
37048let hasNewValue = 1;
37049let opNewValue = 0;
37050let isCVI = 1;
37051let DecoderNamespace = "EXT_mmvec";
37052}
37053def V6_vpackhub_sat_alt : HInst<
37054(outs HvxVR:$Vd32),
37055(ins HvxVR:$Vu32, HvxVR:$Vv32),
37056"$Vd32 = vpackhub($Vu32,$Vv32):sat",
37057PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37058let hasNewValue = 1;
37059let opNewValue = 0;
37060let isCVI = 1;
37061let isPseudo = 1;
37062let isCodeGenOnly = 1;
37063let DecoderNamespace = "EXT_mmvec";
37064}
37065def V6_vpackob : HInst<
37066(outs HvxVR:$Vd32),
37067(ins HvxVR:$Vu32, HvxVR:$Vv32),
37068"$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
37069tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37070let Inst{7-5} = 0b001;
37071let Inst{13-13} = 0b0;
37072let Inst{31-21} = 0b00011111111;
37073let hasNewValue = 1;
37074let opNewValue = 0;
37075let isCVI = 1;
37076let DecoderNamespace = "EXT_mmvec";
37077}
37078def V6_vpackob_alt : HInst<
37079(outs HvxVR:$Vd32),
37080(ins HvxVR:$Vu32, HvxVR:$Vv32),
37081"$Vd32 = vpackob($Vu32,$Vv32)",
37082PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37083let hasNewValue = 1;
37084let opNewValue = 0;
37085let isCVI = 1;
37086let isPseudo = 1;
37087let isCodeGenOnly = 1;
37088let DecoderNamespace = "EXT_mmvec";
37089}
37090def V6_vpackoh : HInst<
37091(outs HvxVR:$Vd32),
37092(ins HvxVR:$Vu32, HvxVR:$Vv32),
37093"$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
37094tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37095let Inst{7-5} = 0b010;
37096let Inst{13-13} = 0b0;
37097let Inst{31-21} = 0b00011111111;
37098let hasNewValue = 1;
37099let opNewValue = 0;
37100let isCVI = 1;
37101let DecoderNamespace = "EXT_mmvec";
37102}
37103def V6_vpackoh_alt : HInst<
37104(outs HvxVR:$Vd32),
37105(ins HvxVR:$Vu32, HvxVR:$Vv32),
37106"$Vd32 = vpackoh($Vu32,$Vv32)",
37107PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37108let hasNewValue = 1;
37109let opNewValue = 0;
37110let isCVI = 1;
37111let isPseudo = 1;
37112let isCodeGenOnly = 1;
37113let DecoderNamespace = "EXT_mmvec";
37114}
37115def V6_vpackwh_sat : HInst<
37116(outs HvxVR:$Vd32),
37117(ins HvxVR:$Vu32, HvxVR:$Vv32),
37118"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
37119tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37120let Inst{7-5} = 0b000;
37121let Inst{13-13} = 0b0;
37122let Inst{31-21} = 0b00011111111;
37123let hasNewValue = 1;
37124let opNewValue = 0;
37125let isCVI = 1;
37126let DecoderNamespace = "EXT_mmvec";
37127}
37128def V6_vpackwh_sat_alt : HInst<
37129(outs HvxVR:$Vd32),
37130(ins HvxVR:$Vu32, HvxVR:$Vv32),
37131"$Vd32 = vpackwh($Vu32,$Vv32):sat",
37132PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37133let hasNewValue = 1;
37134let opNewValue = 0;
37135let isCVI = 1;
37136let isPseudo = 1;
37137let isCodeGenOnly = 1;
37138let DecoderNamespace = "EXT_mmvec";
37139}
37140def V6_vpackwuh_sat : HInst<
37141(outs HvxVR:$Vd32),
37142(ins HvxVR:$Vu32, HvxVR:$Vv32),
37143"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
37144tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37145let Inst{7-5} = 0b111;
37146let Inst{13-13} = 0b0;
37147let Inst{31-21} = 0b00011111110;
37148let hasNewValue = 1;
37149let opNewValue = 0;
37150let isCVI = 1;
37151let DecoderNamespace = "EXT_mmvec";
37152}
37153def V6_vpackwuh_sat_alt : HInst<
37154(outs HvxVR:$Vd32),
37155(ins HvxVR:$Vu32, HvxVR:$Vv32),
37156"$Vd32 = vpackwuh($Vu32,$Vv32):sat",
37157PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37158let hasNewValue = 1;
37159let opNewValue = 0;
37160let isCVI = 1;
37161let isPseudo = 1;
37162let isCodeGenOnly = 1;
37163let DecoderNamespace = "EXT_mmvec";
37164}
37165def V6_vpopcounth : HInst<
37166(outs HvxVR:$Vd32),
37167(ins HvxVR:$Vu32),
37168"$Vd32.h = vpopcount($Vu32.h)",
37169tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
37170let Inst{7-5} = 0b110;
37171let Inst{13-13} = 0b0;
37172let Inst{31-16} = 0b0001111000000010;
37173let hasNewValue = 1;
37174let opNewValue = 0;
37175let isCVI = 1;
37176let DecoderNamespace = "EXT_mmvec";
37177}
37178def V6_vpopcounth_alt : HInst<
37179(outs HvxVR:$Vd32),
37180(ins HvxVR:$Vu32),
37181"$Vd32 = vpopcounth($Vu32)",
37182PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37183let hasNewValue = 1;
37184let opNewValue = 0;
37185let isCVI = 1;
37186let isPseudo = 1;
37187let isCodeGenOnly = 1;
37188let DecoderNamespace = "EXT_mmvec";
37189}
37190def V6_vprefixqb : HInst<
37191(outs HvxVR:$Vd32),
37192(ins HvxQR:$Qv4),
37193"$Vd32.b = prefixsum($Qv4)",
37194tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
37195let Inst{13-5} = 0b100000010;
37196let Inst{21-16} = 0b000011;
37197let Inst{31-24} = 0b00011110;
37198let hasNewValue = 1;
37199let opNewValue = 0;
37200let isCVI = 1;
37201let DecoderNamespace = "EXT_mmvec";
37202}
37203def V6_vprefixqh : HInst<
37204(outs HvxVR:$Vd32),
37205(ins HvxQR:$Qv4),
37206"$Vd32.h = prefixsum($Qv4)",
37207tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
37208let Inst{13-5} = 0b100001010;
37209let Inst{21-16} = 0b000011;
37210let Inst{31-24} = 0b00011110;
37211let hasNewValue = 1;
37212let opNewValue = 0;
37213let isCVI = 1;
37214let DecoderNamespace = "EXT_mmvec";
37215}
37216def V6_vprefixqw : HInst<
37217(outs HvxVR:$Vd32),
37218(ins HvxQR:$Qv4),
37219"$Vd32.w = prefixsum($Qv4)",
37220tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
37221let Inst{13-5} = 0b100010010;
37222let Inst{21-16} = 0b000011;
37223let Inst{31-24} = 0b00011110;
37224let hasNewValue = 1;
37225let opNewValue = 0;
37226let isCVI = 1;
37227let DecoderNamespace = "EXT_mmvec";
37228}
37229def V6_vrdelta : HInst<
37230(outs HvxVR:$Vd32),
37231(ins HvxVR:$Vu32, HvxVR:$Vv32),
37232"$Vd32 = vrdelta($Vu32,$Vv32)",
37233tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37234let Inst{7-5} = 0b011;
37235let Inst{13-13} = 0b0;
37236let Inst{31-21} = 0b00011111001;
37237let hasNewValue = 1;
37238let opNewValue = 0;
37239let isCVI = 1;
37240let DecoderNamespace = "EXT_mmvec";
37241}
37242def V6_vrmpybub_rtt : HInst<
37243(outs HvxWR:$Vdd32),
37244(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37245"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
37246tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
37247let Inst{7-5} = 0b101;
37248let Inst{13-13} = 0b0;
37249let Inst{31-21} = 0b00011001110;
37250let hasNewValue = 1;
37251let opNewValue = 0;
37252let isCVI = 1;
37253let DecoderNamespace = "EXT_mmvec";
37254}
37255def V6_vrmpybub_rtt_acc : HInst<
37256(outs HvxWR:$Vxx32),
37257(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37258"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
37259tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
37260let Inst{7-5} = 0b000;
37261let Inst{13-13} = 0b1;
37262let Inst{31-21} = 0b00011001101;
37263let hasNewValue = 1;
37264let opNewValue = 0;
37265let isAccumulator = 1;
37266let isCVI = 1;
37267let DecoderNamespace = "EXT_mmvec";
37268let Constraints = "$Vxx32 = $Vxx32in";
37269}
37270def V6_vrmpybub_rtt_acc_alt : HInst<
37271(outs HvxWR:$Vxx32),
37272(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37273"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
37274PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37275let hasNewValue = 1;
37276let opNewValue = 0;
37277let isAccumulator = 1;
37278let isCVI = 1;
37279let isPseudo = 1;
37280let isCodeGenOnly = 1;
37281let DecoderNamespace = "EXT_mmvec";
37282let Constraints = "$Vxx32 = $Vxx32in";
37283}
37284def V6_vrmpybub_rtt_alt : HInst<
37285(outs HvxWR:$Vdd32),
37286(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37287"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
37288PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37289let hasNewValue = 1;
37290let opNewValue = 0;
37291let isCVI = 1;
37292let isPseudo = 1;
37293let isCodeGenOnly = 1;
37294let DecoderNamespace = "EXT_mmvec";
37295}
37296def V6_vrmpybus : HInst<
37297(outs HvxVR:$Vd32),
37298(ins HvxVR:$Vu32, IntRegs:$Rt32),
37299"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
37300tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
37301let Inst{7-5} = 0b100;
37302let Inst{13-13} = 0b0;
37303let Inst{31-21} = 0b00011001000;
37304let hasNewValue = 1;
37305let opNewValue = 0;
37306let isCVI = 1;
37307let DecoderNamespace = "EXT_mmvec";
37308}
37309def V6_vrmpybus_acc : HInst<
37310(outs HvxVR:$Vx32),
37311(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37312"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
37313tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
37314let Inst{7-5} = 0b101;
37315let Inst{13-13} = 0b1;
37316let Inst{31-21} = 0b00011001000;
37317let hasNewValue = 1;
37318let opNewValue = 0;
37319let isAccumulator = 1;
37320let isCVI = 1;
37321let DecoderNamespace = "EXT_mmvec";
37322let Constraints = "$Vx32 = $Vx32in";
37323}
37324def V6_vrmpybus_acc_alt : HInst<
37325(outs HvxVR:$Vx32),
37326(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37327"$Vx32 += vrmpybus($Vu32,$Rt32)",
37328PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37329let hasNewValue = 1;
37330let opNewValue = 0;
37331let isAccumulator = 1;
37332let isCVI = 1;
37333let isPseudo = 1;
37334let isCodeGenOnly = 1;
37335let DecoderNamespace = "EXT_mmvec";
37336let Constraints = "$Vx32 = $Vx32in";
37337}
37338def V6_vrmpybus_alt : HInst<
37339(outs HvxVR:$Vd32),
37340(ins HvxVR:$Vu32, IntRegs:$Rt32),
37341"$Vd32 = vrmpybus($Vu32,$Rt32)",
37342PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37343let hasNewValue = 1;
37344let opNewValue = 0;
37345let isCVI = 1;
37346let isPseudo = 1;
37347let isCodeGenOnly = 1;
37348let DecoderNamespace = "EXT_mmvec";
37349}
37350def V6_vrmpybusi : HInst<
37351(outs HvxWR:$Vdd32),
37352(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37353"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
37354tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
37355let Inst{7-6} = 0b10;
37356let Inst{13-13} = 0b0;
37357let Inst{31-21} = 0b00011001010;
37358let hasNewValue = 1;
37359let opNewValue = 0;
37360let isCVI = 1;
37361let DecoderNamespace = "EXT_mmvec";
37362}
37363def V6_vrmpybusi_acc : HInst<
37364(outs HvxWR:$Vxx32),
37365(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37366"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
37367tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
37368let Inst{7-6} = 0b10;
37369let Inst{13-13} = 0b1;
37370let Inst{31-21} = 0b00011001010;
37371let hasNewValue = 1;
37372let opNewValue = 0;
37373let isAccumulator = 1;
37374let isCVI = 1;
37375let DecoderNamespace = "EXT_mmvec";
37376let Constraints = "$Vxx32 = $Vxx32in";
37377}
37378def V6_vrmpybusi_acc_alt : HInst<
37379(outs HvxWR:$Vxx32),
37380(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37381"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
37382PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37383let hasNewValue = 1;
37384let opNewValue = 0;
37385let isAccumulator = 1;
37386let isCVI = 1;
37387let isPseudo = 1;
37388let isCodeGenOnly = 1;
37389let DecoderNamespace = "EXT_mmvec";
37390let Constraints = "$Vxx32 = $Vxx32in";
37391}
37392def V6_vrmpybusi_alt : HInst<
37393(outs HvxWR:$Vdd32),
37394(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37395"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
37396PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37397let hasNewValue = 1;
37398let opNewValue = 0;
37399let isCVI = 1;
37400let isPseudo = 1;
37401let isCodeGenOnly = 1;
37402let DecoderNamespace = "EXT_mmvec";
37403}
37404def V6_vrmpybusv : HInst<
37405(outs HvxVR:$Vd32),
37406(ins HvxVR:$Vu32, HvxVR:$Vv32),
37407"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
37408tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
37409let Inst{7-5} = 0b010;
37410let Inst{13-13} = 0b0;
37411let Inst{31-21} = 0b00011100000;
37412let hasNewValue = 1;
37413let opNewValue = 0;
37414let isCVI = 1;
37415let DecoderNamespace = "EXT_mmvec";
37416}
37417def V6_vrmpybusv_acc : HInst<
37418(outs HvxVR:$Vx32),
37419(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37420"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
37421tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
37422let Inst{7-5} = 0b010;
37423let Inst{13-13} = 0b1;
37424let Inst{31-21} = 0b00011100000;
37425let hasNewValue = 1;
37426let opNewValue = 0;
37427let isAccumulator = 1;
37428let isCVI = 1;
37429let DecoderNamespace = "EXT_mmvec";
37430let Constraints = "$Vx32 = $Vx32in";
37431}
37432def V6_vrmpybusv_acc_alt : HInst<
37433(outs HvxVR:$Vx32),
37434(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37435"$Vx32 += vrmpybus($Vu32,$Vv32)",
37436PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37437let hasNewValue = 1;
37438let opNewValue = 0;
37439let isAccumulator = 1;
37440let isCVI = 1;
37441let isPseudo = 1;
37442let isCodeGenOnly = 1;
37443let DecoderNamespace = "EXT_mmvec";
37444let Constraints = "$Vx32 = $Vx32in";
37445}
37446def V6_vrmpybusv_alt : HInst<
37447(outs HvxVR:$Vd32),
37448(ins HvxVR:$Vu32, HvxVR:$Vv32),
37449"$Vd32 = vrmpybus($Vu32,$Vv32)",
37450PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37451let hasNewValue = 1;
37452let opNewValue = 0;
37453let isCVI = 1;
37454let isPseudo = 1;
37455let isCodeGenOnly = 1;
37456let DecoderNamespace = "EXT_mmvec";
37457}
37458def V6_vrmpybv : HInst<
37459(outs HvxVR:$Vd32),
37460(ins HvxVR:$Vu32, HvxVR:$Vv32),
37461"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
37462tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
37463let Inst{7-5} = 0b001;
37464let Inst{13-13} = 0b0;
37465let Inst{31-21} = 0b00011100000;
37466let hasNewValue = 1;
37467let opNewValue = 0;
37468let isCVI = 1;
37469let DecoderNamespace = "EXT_mmvec";
37470}
37471def V6_vrmpybv_acc : HInst<
37472(outs HvxVR:$Vx32),
37473(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37474"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
37475tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
37476let Inst{7-5} = 0b001;
37477let Inst{13-13} = 0b1;
37478let Inst{31-21} = 0b00011100000;
37479let hasNewValue = 1;
37480let opNewValue = 0;
37481let isAccumulator = 1;
37482let isCVI = 1;
37483let DecoderNamespace = "EXT_mmvec";
37484let Constraints = "$Vx32 = $Vx32in";
37485}
37486def V6_vrmpybv_acc_alt : HInst<
37487(outs HvxVR:$Vx32),
37488(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37489"$Vx32 += vrmpyb($Vu32,$Vv32)",
37490PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37491let hasNewValue = 1;
37492let opNewValue = 0;
37493let isAccumulator = 1;
37494let isCVI = 1;
37495let isPseudo = 1;
37496let isCodeGenOnly = 1;
37497let DecoderNamespace = "EXT_mmvec";
37498let Constraints = "$Vx32 = $Vx32in";
37499}
37500def V6_vrmpybv_alt : HInst<
37501(outs HvxVR:$Vd32),
37502(ins HvxVR:$Vu32, HvxVR:$Vv32),
37503"$Vd32 = vrmpyb($Vu32,$Vv32)",
37504PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37505let hasNewValue = 1;
37506let opNewValue = 0;
37507let isCVI = 1;
37508let isPseudo = 1;
37509let isCodeGenOnly = 1;
37510let DecoderNamespace = "EXT_mmvec";
37511}
37512def V6_vrmpyub : HInst<
37513(outs HvxVR:$Vd32),
37514(ins HvxVR:$Vu32, IntRegs:$Rt32),
37515"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
37516tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
37517let Inst{7-5} = 0b011;
37518let Inst{13-13} = 0b0;
37519let Inst{31-21} = 0b00011001000;
37520let hasNewValue = 1;
37521let opNewValue = 0;
37522let isCVI = 1;
37523let DecoderNamespace = "EXT_mmvec";
37524}
37525def V6_vrmpyub_acc : HInst<
37526(outs HvxVR:$Vx32),
37527(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37528"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
37529tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
37530let Inst{7-5} = 0b100;
37531let Inst{13-13} = 0b1;
37532let Inst{31-21} = 0b00011001000;
37533let hasNewValue = 1;
37534let opNewValue = 0;
37535let isAccumulator = 1;
37536let isCVI = 1;
37537let DecoderNamespace = "EXT_mmvec";
37538let Constraints = "$Vx32 = $Vx32in";
37539}
37540def V6_vrmpyub_acc_alt : HInst<
37541(outs HvxVR:$Vx32),
37542(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37543"$Vx32 += vrmpyub($Vu32,$Rt32)",
37544PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37545let hasNewValue = 1;
37546let opNewValue = 0;
37547let isAccumulator = 1;
37548let isCVI = 1;
37549let isPseudo = 1;
37550let isCodeGenOnly = 1;
37551let DecoderNamespace = "EXT_mmvec";
37552let Constraints = "$Vx32 = $Vx32in";
37553}
37554def V6_vrmpyub_alt : HInst<
37555(outs HvxVR:$Vd32),
37556(ins HvxVR:$Vu32, IntRegs:$Rt32),
37557"$Vd32 = vrmpyub($Vu32,$Rt32)",
37558PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37559let hasNewValue = 1;
37560let opNewValue = 0;
37561let isCVI = 1;
37562let isPseudo = 1;
37563let isCodeGenOnly = 1;
37564let DecoderNamespace = "EXT_mmvec";
37565}
37566def V6_vrmpyub_rtt : HInst<
37567(outs HvxWR:$Vdd32),
37568(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37569"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
37570tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
37571let Inst{7-5} = 0b100;
37572let Inst{13-13} = 0b0;
37573let Inst{31-21} = 0b00011001110;
37574let hasNewValue = 1;
37575let opNewValue = 0;
37576let isCVI = 1;
37577let DecoderNamespace = "EXT_mmvec";
37578}
37579def V6_vrmpyub_rtt_acc : HInst<
37580(outs HvxWR:$Vxx32),
37581(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37582"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
37583tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
37584let Inst{7-5} = 0b111;
37585let Inst{13-13} = 0b1;
37586let Inst{31-21} = 0b00011001101;
37587let hasNewValue = 1;
37588let opNewValue = 0;
37589let isAccumulator = 1;
37590let isCVI = 1;
37591let DecoderNamespace = "EXT_mmvec";
37592let Constraints = "$Vxx32 = $Vxx32in";
37593}
37594def V6_vrmpyub_rtt_acc_alt : HInst<
37595(outs HvxWR:$Vxx32),
37596(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37597"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
37598PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37599let hasNewValue = 1;
37600let opNewValue = 0;
37601let isAccumulator = 1;
37602let isCVI = 1;
37603let isPseudo = 1;
37604let isCodeGenOnly = 1;
37605let DecoderNamespace = "EXT_mmvec";
37606let Constraints = "$Vxx32 = $Vxx32in";
37607}
37608def V6_vrmpyub_rtt_alt : HInst<
37609(outs HvxWR:$Vdd32),
37610(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37611"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
37612PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37613let hasNewValue = 1;
37614let opNewValue = 0;
37615let isCVI = 1;
37616let isPseudo = 1;
37617let isCodeGenOnly = 1;
37618let DecoderNamespace = "EXT_mmvec";
37619}
37620def V6_vrmpyubi : HInst<
37621(outs HvxWR:$Vdd32),
37622(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37623"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
37624tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
37625let Inst{7-6} = 0b11;
37626let Inst{13-13} = 0b0;
37627let Inst{31-21} = 0b00011001101;
37628let hasNewValue = 1;
37629let opNewValue = 0;
37630let isCVI = 1;
37631let DecoderNamespace = "EXT_mmvec";
37632}
37633def V6_vrmpyubi_acc : HInst<
37634(outs HvxWR:$Vxx32),
37635(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37636"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
37637tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
37638let Inst{7-6} = 0b11;
37639let Inst{13-13} = 0b1;
37640let Inst{31-21} = 0b00011001011;
37641let hasNewValue = 1;
37642let opNewValue = 0;
37643let isAccumulator = 1;
37644let isCVI = 1;
37645let DecoderNamespace = "EXT_mmvec";
37646let Constraints = "$Vxx32 = $Vxx32in";
37647}
37648def V6_vrmpyubi_acc_alt : HInst<
37649(outs HvxWR:$Vxx32),
37650(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37651"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
37652PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37653let hasNewValue = 1;
37654let opNewValue = 0;
37655let isAccumulator = 1;
37656let isCVI = 1;
37657let isPseudo = 1;
37658let isCodeGenOnly = 1;
37659let DecoderNamespace = "EXT_mmvec";
37660let Constraints = "$Vxx32 = $Vxx32in";
37661}
37662def V6_vrmpyubi_alt : HInst<
37663(outs HvxWR:$Vdd32),
37664(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37665"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
37666PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37667let hasNewValue = 1;
37668let opNewValue = 0;
37669let isCVI = 1;
37670let isPseudo = 1;
37671let isCodeGenOnly = 1;
37672let DecoderNamespace = "EXT_mmvec";
37673}
37674def V6_vrmpyubv : HInst<
37675(outs HvxVR:$Vd32),
37676(ins HvxVR:$Vu32, HvxVR:$Vv32),
37677"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
37678tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
37679let Inst{7-5} = 0b000;
37680let Inst{13-13} = 0b0;
37681let Inst{31-21} = 0b00011100000;
37682let hasNewValue = 1;
37683let opNewValue = 0;
37684let isCVI = 1;
37685let DecoderNamespace = "EXT_mmvec";
37686}
37687def V6_vrmpyubv_acc : HInst<
37688(outs HvxVR:$Vx32),
37689(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37690"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
37691tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
37692let Inst{7-5} = 0b000;
37693let Inst{13-13} = 0b1;
37694let Inst{31-21} = 0b00011100000;
37695let hasNewValue = 1;
37696let opNewValue = 0;
37697let isAccumulator = 1;
37698let isCVI = 1;
37699let DecoderNamespace = "EXT_mmvec";
37700let Constraints = "$Vx32 = $Vx32in";
37701}
37702def V6_vrmpyubv_acc_alt : HInst<
37703(outs HvxVR:$Vx32),
37704(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37705"$Vx32 += vrmpyub($Vu32,$Vv32)",
37706PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37707let hasNewValue = 1;
37708let opNewValue = 0;
37709let isAccumulator = 1;
37710let isCVI = 1;
37711let isPseudo = 1;
37712let isCodeGenOnly = 1;
37713let DecoderNamespace = "EXT_mmvec";
37714let Constraints = "$Vx32 = $Vx32in";
37715}
37716def V6_vrmpyubv_alt : HInst<
37717(outs HvxVR:$Vd32),
37718(ins HvxVR:$Vu32, HvxVR:$Vv32),
37719"$Vd32 = vrmpyub($Vu32,$Vv32)",
37720PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37721let hasNewValue = 1;
37722let opNewValue = 0;
37723let isCVI = 1;
37724let isPseudo = 1;
37725let isCodeGenOnly = 1;
37726let DecoderNamespace = "EXT_mmvec";
37727}
37728def V6_vrmpyzbb_rt : HInst<
37729(outs HvxVQR:$Vdddd32),
37730(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37731"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.b)",
37732tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37733let Inst{7-5} = 0b000;
37734let Inst{13-13} = 0b0;
37735let Inst{31-19} = 0b0001100111101;
37736let hasNewValue = 1;
37737let opNewValue = 0;
37738let isCVI = 1;
37739let DecoderNamespace = "EXT_mmvec";
37740}
37741def V6_vrmpyzbb_rt_acc : HInst<
37742(outs HvxVQR:$Vyyyy32),
37743(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37744"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.b)",
37745tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37746let Inst{7-5} = 0b010;
37747let Inst{13-13} = 0b1;
37748let Inst{31-19} = 0b0001100111000;
37749let hasNewValue = 1;
37750let opNewValue = 0;
37751let isAccumulator = 1;
37752let isCVI = 1;
37753let DecoderNamespace = "EXT_mmvec";
37754let Constraints = "$Vyyyy32 = $Vyyyy32in";
37755}
37756def V6_vrmpyzbb_rx : HInst<
37757(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37758(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37759"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)",
37760tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37761let Inst{7-5} = 0b000;
37762let Inst{13-13} = 0b0;
37763let Inst{31-19} = 0b0001100111100;
37764let hasNewValue = 1;
37765let opNewValue = 0;
37766let isCVI = 1;
37767let DecoderNamespace = "EXT_mmvec";
37768let Constraints = "$Rx8 = $Rx8in";
37769}
37770def V6_vrmpyzbb_rx_acc : HInst<
37771(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37772(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37773"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)",
37774tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37775let Inst{7-5} = 0b010;
37776let Inst{13-13} = 0b1;
37777let Inst{31-19} = 0b0001100111001;
37778let hasNewValue = 1;
37779let opNewValue = 0;
37780let isAccumulator = 1;
37781let isCVI = 1;
37782let DecoderNamespace = "EXT_mmvec";
37783let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37784}
37785def V6_vrmpyzbub_rt : HInst<
37786(outs HvxVQR:$Vdddd32),
37787(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37788"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.ub)",
37789tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37790let Inst{7-5} = 0b010;
37791let Inst{13-13} = 0b0;
37792let Inst{31-19} = 0b0001100111111;
37793let hasNewValue = 1;
37794let opNewValue = 0;
37795let isCVI = 1;
37796let DecoderNamespace = "EXT_mmvec";
37797}
37798def V6_vrmpyzbub_rt_acc : HInst<
37799(outs HvxVQR:$Vyyyy32),
37800(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37801"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.ub)",
37802tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37803let Inst{7-5} = 0b001;
37804let Inst{13-13} = 0b1;
37805let Inst{31-19} = 0b0001100111010;
37806let hasNewValue = 1;
37807let opNewValue = 0;
37808let isAccumulator = 1;
37809let isCVI = 1;
37810let DecoderNamespace = "EXT_mmvec";
37811let Constraints = "$Vyyyy32 = $Vyyyy32in";
37812}
37813def V6_vrmpyzbub_rx : HInst<
37814(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37815(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37816"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)",
37817tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37818let Inst{7-5} = 0b010;
37819let Inst{13-13} = 0b0;
37820let Inst{31-19} = 0b0001100111110;
37821let hasNewValue = 1;
37822let opNewValue = 0;
37823let isCVI = 1;
37824let DecoderNamespace = "EXT_mmvec";
37825let Constraints = "$Rx8 = $Rx8in";
37826}
37827def V6_vrmpyzbub_rx_acc : HInst<
37828(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37829(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37830"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)",
37831tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37832let Inst{7-5} = 0b001;
37833let Inst{13-13} = 0b1;
37834let Inst{31-19} = 0b0001100111011;
37835let hasNewValue = 1;
37836let opNewValue = 0;
37837let isAccumulator = 1;
37838let isCVI = 1;
37839let DecoderNamespace = "EXT_mmvec";
37840let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37841}
37842def V6_vrmpyzcb_rt : HInst<
37843(outs HvxVQR:$Vdddd32),
37844(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37845"$Vdddd32.w = vr16mpyz($Vu32.c,$Rt8.b)",
37846tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37847let Inst{7-5} = 0b001;
37848let Inst{13-13} = 0b0;
37849let Inst{31-19} = 0b0001100111101;
37850let hasNewValue = 1;
37851let opNewValue = 0;
37852let isCVI = 1;
37853let DecoderNamespace = "EXT_mmvec";
37854}
37855def V6_vrmpyzcb_rt_acc : HInst<
37856(outs HvxVQR:$Vyyyy32),
37857(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37858"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rt8.b)",
37859tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37860let Inst{7-5} = 0b011;
37861let Inst{13-13} = 0b1;
37862let Inst{31-19} = 0b0001100111000;
37863let hasNewValue = 1;
37864let opNewValue = 0;
37865let isAccumulator = 1;
37866let isCVI = 1;
37867let DecoderNamespace = "EXT_mmvec";
37868let Constraints = "$Vyyyy32 = $Vyyyy32in";
37869}
37870def V6_vrmpyzcb_rx : HInst<
37871(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37872(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37873"$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)",
37874tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37875let Inst{7-5} = 0b001;
37876let Inst{13-13} = 0b0;
37877let Inst{31-19} = 0b0001100111100;
37878let hasNewValue = 1;
37879let opNewValue = 0;
37880let isCVI = 1;
37881let DecoderNamespace = "EXT_mmvec";
37882let Constraints = "$Rx8 = $Rx8in";
37883}
37884def V6_vrmpyzcb_rx_acc : HInst<
37885(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37886(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37887"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)",
37888tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37889let Inst{7-5} = 0b011;
37890let Inst{13-13} = 0b1;
37891let Inst{31-19} = 0b0001100111001;
37892let hasNewValue = 1;
37893let opNewValue = 0;
37894let isAccumulator = 1;
37895let isCVI = 1;
37896let DecoderNamespace = "EXT_mmvec";
37897let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37898}
37899def V6_vrmpyzcbs_rt : HInst<
37900(outs HvxVQR:$Vdddd32),
37901(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37902"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rt8.b)",
37903tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37904let Inst{7-5} = 0b010;
37905let Inst{13-13} = 0b0;
37906let Inst{31-19} = 0b0001100111101;
37907let hasNewValue = 1;
37908let opNewValue = 0;
37909let isCVI = 1;
37910let DecoderNamespace = "EXT_mmvec";
37911}
37912def V6_vrmpyzcbs_rt_acc : HInst<
37913(outs HvxVQR:$Vyyyy32),
37914(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37915"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rt8.b)",
37916tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37917let Inst{7-5} = 0b001;
37918let Inst{13-13} = 0b1;
37919let Inst{31-19} = 0b0001100111000;
37920let hasNewValue = 1;
37921let opNewValue = 0;
37922let isAccumulator = 1;
37923let isCVI = 1;
37924let DecoderNamespace = "EXT_mmvec";
37925let Constraints = "$Vyyyy32 = $Vyyyy32in";
37926}
37927def V6_vrmpyzcbs_rx : HInst<
37928(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37929(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37930"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)",
37931tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37932let Inst{7-5} = 0b010;
37933let Inst{13-13} = 0b0;
37934let Inst{31-19} = 0b0001100111100;
37935let hasNewValue = 1;
37936let opNewValue = 0;
37937let isCVI = 1;
37938let DecoderNamespace = "EXT_mmvec";
37939let Constraints = "$Rx8 = $Rx8in";
37940}
37941def V6_vrmpyzcbs_rx_acc : HInst<
37942(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37943(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37944"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)",
37945tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37946let Inst{7-5} = 0b001;
37947let Inst{13-13} = 0b1;
37948let Inst{31-19} = 0b0001100111001;
37949let hasNewValue = 1;
37950let opNewValue = 0;
37951let isAccumulator = 1;
37952let isCVI = 1;
37953let DecoderNamespace = "EXT_mmvec";
37954let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37955}
37956def V6_vrmpyznb_rt : HInst<
37957(outs HvxVQR:$Vdddd32),
37958(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37959"$Vdddd32.w = vr8mpyz($Vu32.n,$Rt8.b)",
37960tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37961let Inst{7-5} = 0b000;
37962let Inst{13-13} = 0b0;
37963let Inst{31-19} = 0b0001100111111;
37964let hasNewValue = 1;
37965let opNewValue = 0;
37966let isCVI = 1;
37967let DecoderNamespace = "EXT_mmvec";
37968}
37969def V6_vrmpyznb_rt_acc : HInst<
37970(outs HvxVQR:$Vyyyy32),
37971(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37972"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rt8.b)",
37973tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37974let Inst{7-5} = 0b010;
37975let Inst{13-13} = 0b1;
37976let Inst{31-19} = 0b0001100111010;
37977let hasNewValue = 1;
37978let opNewValue = 0;
37979let isAccumulator = 1;
37980let isCVI = 1;
37981let DecoderNamespace = "EXT_mmvec";
37982let Constraints = "$Vyyyy32 = $Vyyyy32in";
37983}
37984def V6_vrmpyznb_rx : HInst<
37985(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37986(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37987"$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)",
37988tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37989let Inst{7-5} = 0b000;
37990let Inst{13-13} = 0b0;
37991let Inst{31-19} = 0b0001100111110;
37992let hasNewValue = 1;
37993let opNewValue = 0;
37994let isCVI = 1;
37995let DecoderNamespace = "EXT_mmvec";
37996let Constraints = "$Rx8 = $Rx8in";
37997}
37998def V6_vrmpyznb_rx_acc : HInst<
37999(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
38000(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
38001"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)",
38002tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
38003let Inst{7-5} = 0b010;
38004let Inst{13-13} = 0b1;
38005let Inst{31-19} = 0b0001100111011;
38006let hasNewValue = 1;
38007let opNewValue = 0;
38008let isAccumulator = 1;
38009let isCVI = 1;
38010let DecoderNamespace = "EXT_mmvec";
38011let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
38012}
38013def V6_vror : HInst<
38014(outs HvxVR:$Vd32),
38015(ins HvxVR:$Vu32, IntRegs:$Rt32),
38016"$Vd32 = vror($Vu32,$Rt32)",
38017tc_6e7fa133, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
38018let Inst{7-5} = 0b001;
38019let Inst{13-13} = 0b0;
38020let Inst{31-21} = 0b00011001011;
38021let hasNewValue = 1;
38022let opNewValue = 0;
38023let isCVI = 1;
38024let DecoderNamespace = "EXT_mmvec";
38025}
38026def V6_vrotr : HInst<
38027(outs HvxVR:$Vd32),
38028(ins HvxVR:$Vu32, HvxVR:$Vv32),
38029"$Vd32.uw = vrotr($Vu32.uw,$Vv32.uw)",
38030tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV66]> {
38031let Inst{7-5} = 0b111;
38032let Inst{13-13} = 0b1;
38033let Inst{31-21} = 0b00011010100;
38034let hasNewValue = 1;
38035let opNewValue = 0;
38036let isCVI = 1;
38037let DecoderNamespace = "EXT_mmvec";
38038}
38039def V6_vrotr_alt : HInst<
38040(outs HvxVR:$Vd32),
38041(ins HvxVR:$Vu32, HvxVR:$Vv32),
38042"$Vd32 = vrotr($Vu32,$Vv32)",
38043PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
38044let hasNewValue = 1;
38045let opNewValue = 0;
38046let isCVI = 1;
38047let isPseudo = 1;
38048let isCodeGenOnly = 1;
38049let DecoderNamespace = "EXT_mmvec";
38050}
38051def V6_vroundhb : HInst<
38052(outs HvxVR:$Vd32),
38053(ins HvxVR:$Vu32, HvxVR:$Vv32),
38054"$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
38055tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38056let Inst{7-5} = 0b110;
38057let Inst{13-13} = 0b0;
38058let Inst{31-21} = 0b00011111011;
38059let hasNewValue = 1;
38060let opNewValue = 0;
38061let isCVI = 1;
38062let DecoderNamespace = "EXT_mmvec";
38063}
38064def V6_vroundhb_alt : HInst<
38065(outs HvxVR:$Vd32),
38066(ins HvxVR:$Vu32, HvxVR:$Vv32),
38067"$Vd32 = vroundhb($Vu32,$Vv32):sat",
38068PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38069let hasNewValue = 1;
38070let opNewValue = 0;
38071let isCVI = 1;
38072let isPseudo = 1;
38073let isCodeGenOnly = 1;
38074let DecoderNamespace = "EXT_mmvec";
38075}
38076def V6_vroundhub : HInst<
38077(outs HvxVR:$Vd32),
38078(ins HvxVR:$Vu32, HvxVR:$Vv32),
38079"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
38080tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38081let Inst{7-5} = 0b111;
38082let Inst{13-13} = 0b0;
38083let Inst{31-21} = 0b00011111011;
38084let hasNewValue = 1;
38085let opNewValue = 0;
38086let isCVI = 1;
38087let DecoderNamespace = "EXT_mmvec";
38088}
38089def V6_vroundhub_alt : HInst<
38090(outs HvxVR:$Vd32),
38091(ins HvxVR:$Vu32, HvxVR:$Vv32),
38092"$Vd32 = vroundhub($Vu32,$Vv32):sat",
38093PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38094let hasNewValue = 1;
38095let opNewValue = 0;
38096let isCVI = 1;
38097let isPseudo = 1;
38098let isCodeGenOnly = 1;
38099let DecoderNamespace = "EXT_mmvec";
38100}
38101def V6_vrounduhub : HInst<
38102(outs HvxVR:$Vd32),
38103(ins HvxVR:$Vu32, HvxVR:$Vv32),
38104"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
38105tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
38106let Inst{7-5} = 0b011;
38107let Inst{13-13} = 0b0;
38108let Inst{31-21} = 0b00011111111;
38109let hasNewValue = 1;
38110let opNewValue = 0;
38111let isCVI = 1;
38112let DecoderNamespace = "EXT_mmvec";
38113}
38114def V6_vrounduhub_alt : HInst<
38115(outs HvxVR:$Vd32),
38116(ins HvxVR:$Vu32, HvxVR:$Vv32),
38117"$Vd32 = vrounduhub($Vu32,$Vv32):sat",
38118PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38119let hasNewValue = 1;
38120let opNewValue = 0;
38121let isCVI = 1;
38122let isPseudo = 1;
38123let isCodeGenOnly = 1;
38124let DecoderNamespace = "EXT_mmvec";
38125}
38126def V6_vrounduwuh : HInst<
38127(outs HvxVR:$Vd32),
38128(ins HvxVR:$Vu32, HvxVR:$Vv32),
38129"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
38130tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
38131let Inst{7-5} = 0b100;
38132let Inst{13-13} = 0b0;
38133let Inst{31-21} = 0b00011111111;
38134let hasNewValue = 1;
38135let opNewValue = 0;
38136let isCVI = 1;
38137let DecoderNamespace = "EXT_mmvec";
38138}
38139def V6_vrounduwuh_alt : HInst<
38140(outs HvxVR:$Vd32),
38141(ins HvxVR:$Vu32, HvxVR:$Vv32),
38142"$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
38143PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38144let hasNewValue = 1;
38145let opNewValue = 0;
38146let isCVI = 1;
38147let isPseudo = 1;
38148let isCodeGenOnly = 1;
38149let DecoderNamespace = "EXT_mmvec";
38150}
38151def V6_vroundwh : HInst<
38152(outs HvxVR:$Vd32),
38153(ins HvxVR:$Vu32, HvxVR:$Vv32),
38154"$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
38155tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38156let Inst{7-5} = 0b100;
38157let Inst{13-13} = 0b0;
38158let Inst{31-21} = 0b00011111011;
38159let hasNewValue = 1;
38160let opNewValue = 0;
38161let isCVI = 1;
38162let DecoderNamespace = "EXT_mmvec";
38163}
38164def V6_vroundwh_alt : HInst<
38165(outs HvxVR:$Vd32),
38166(ins HvxVR:$Vu32, HvxVR:$Vv32),
38167"$Vd32 = vroundwh($Vu32,$Vv32):sat",
38168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38169let hasNewValue = 1;
38170let opNewValue = 0;
38171let isCVI = 1;
38172let isPseudo = 1;
38173let isCodeGenOnly = 1;
38174let DecoderNamespace = "EXT_mmvec";
38175}
38176def V6_vroundwuh : HInst<
38177(outs HvxVR:$Vd32),
38178(ins HvxVR:$Vu32, HvxVR:$Vv32),
38179"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
38180tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38181let Inst{7-5} = 0b101;
38182let Inst{13-13} = 0b0;
38183let Inst{31-21} = 0b00011111011;
38184let hasNewValue = 1;
38185let opNewValue = 0;
38186let isCVI = 1;
38187let DecoderNamespace = "EXT_mmvec";
38188}
38189def V6_vroundwuh_alt : HInst<
38190(outs HvxVR:$Vd32),
38191(ins HvxVR:$Vu32, HvxVR:$Vv32),
38192"$Vd32 = vroundwuh($Vu32,$Vv32):sat",
38193PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38194let hasNewValue = 1;
38195let opNewValue = 0;
38196let isCVI = 1;
38197let isPseudo = 1;
38198let isCodeGenOnly = 1;
38199let DecoderNamespace = "EXT_mmvec";
38200}
38201def V6_vrsadubi : HInst<
38202(outs HvxWR:$Vdd32),
38203(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38204"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
38205tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
38206let Inst{7-6} = 0b11;
38207let Inst{13-13} = 0b0;
38208let Inst{31-21} = 0b00011001010;
38209let hasNewValue = 1;
38210let opNewValue = 0;
38211let isCVI = 1;
38212let DecoderNamespace = "EXT_mmvec";
38213}
38214def V6_vrsadubi_acc : HInst<
38215(outs HvxWR:$Vxx32),
38216(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38217"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
38218tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
38219let Inst{7-6} = 0b11;
38220let Inst{13-13} = 0b1;
38221let Inst{31-21} = 0b00011001010;
38222let hasNewValue = 1;
38223let opNewValue = 0;
38224let isAccumulator = 1;
38225let isCVI = 1;
38226let DecoderNamespace = "EXT_mmvec";
38227let Constraints = "$Vxx32 = $Vxx32in";
38228}
38229def V6_vrsadubi_acc_alt : HInst<
38230(outs HvxWR:$Vxx32),
38231(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38232"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
38233PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38234let hasNewValue = 1;
38235let opNewValue = 0;
38236let isAccumulator = 1;
38237let isCVI = 1;
38238let isPseudo = 1;
38239let isCodeGenOnly = 1;
38240let DecoderNamespace = "EXT_mmvec";
38241let Constraints = "$Vxx32 = $Vxx32in";
38242}
38243def V6_vrsadubi_alt : HInst<
38244(outs HvxWR:$Vdd32),
38245(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38246"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
38247PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38248let hasNewValue = 1;
38249let opNewValue = 0;
38250let isCVI = 1;
38251let isPseudo = 1;
38252let isCodeGenOnly = 1;
38253let DecoderNamespace = "EXT_mmvec";
38254}
38255def V6_vsatdw : HInst<
38256(outs HvxVR:$Vd32),
38257(ins HvxVR:$Vu32, HvxVR:$Vv32),
38258"$Vd32.w = vsatdw($Vu32.w,$Vv32.w)",
38259tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV66]> {
38260let Inst{7-5} = 0b111;
38261let Inst{13-13} = 0b1;
38262let Inst{31-21} = 0b00011101100;
38263let hasNewValue = 1;
38264let opNewValue = 0;
38265let isCVI = 1;
38266let isHVXALU = 1;
38267let isHVXALU2SRC = 1;
38268let DecoderNamespace = "EXT_mmvec";
38269}
38270def V6_vsathub : HInst<
38271(outs HvxVR:$Vd32),
38272(ins HvxVR:$Vu32, HvxVR:$Vv32),
38273"$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
38274tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38275let Inst{7-5} = 0b010;
38276let Inst{13-13} = 0b0;
38277let Inst{31-21} = 0b00011111011;
38278let hasNewValue = 1;
38279let opNewValue = 0;
38280let isCVI = 1;
38281let isHVXALU = 1;
38282let isHVXALU2SRC = 1;
38283let DecoderNamespace = "EXT_mmvec";
38284}
38285def V6_vsathub_alt : HInst<
38286(outs HvxVR:$Vd32),
38287(ins HvxVR:$Vu32, HvxVR:$Vv32),
38288"$Vd32 = vsathub($Vu32,$Vv32)",
38289PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38290let hasNewValue = 1;
38291let opNewValue = 0;
38292let isCVI = 1;
38293let isPseudo = 1;
38294let isCodeGenOnly = 1;
38295let DecoderNamespace = "EXT_mmvec";
38296}
38297def V6_vsatuwuh : HInst<
38298(outs HvxVR:$Vd32),
38299(ins HvxVR:$Vu32, HvxVR:$Vv32),
38300"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
38301tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
38302let Inst{7-5} = 0b110;
38303let Inst{13-13} = 0b0;
38304let Inst{31-21} = 0b00011111001;
38305let hasNewValue = 1;
38306let opNewValue = 0;
38307let isCVI = 1;
38308let isHVXALU = 1;
38309let isHVXALU2SRC = 1;
38310let DecoderNamespace = "EXT_mmvec";
38311}
38312def V6_vsatuwuh_alt : HInst<
38313(outs HvxVR:$Vd32),
38314(ins HvxVR:$Vu32, HvxVR:$Vv32),
38315"$Vd32 = vsatuwuh($Vu32,$Vv32)",
38316PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38317let hasNewValue = 1;
38318let opNewValue = 0;
38319let isCVI = 1;
38320let isPseudo = 1;
38321let isCodeGenOnly = 1;
38322let DecoderNamespace = "EXT_mmvec";
38323}
38324def V6_vsatwh : HInst<
38325(outs HvxVR:$Vd32),
38326(ins HvxVR:$Vu32, HvxVR:$Vv32),
38327"$Vd32.h = vsat($Vu32.w,$Vv32.w)",
38328tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38329let Inst{7-5} = 0b011;
38330let Inst{13-13} = 0b0;
38331let Inst{31-21} = 0b00011111011;
38332let hasNewValue = 1;
38333let opNewValue = 0;
38334let isCVI = 1;
38335let isHVXALU = 1;
38336let isHVXALU2SRC = 1;
38337let DecoderNamespace = "EXT_mmvec";
38338}
38339def V6_vsatwh_alt : HInst<
38340(outs HvxVR:$Vd32),
38341(ins HvxVR:$Vu32, HvxVR:$Vv32),
38342"$Vd32 = vsatwh($Vu32,$Vv32)",
38343PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38344let hasNewValue = 1;
38345let opNewValue = 0;
38346let isCVI = 1;
38347let isPseudo = 1;
38348let isCodeGenOnly = 1;
38349let DecoderNamespace = "EXT_mmvec";
38350}
38351def V6_vsb : HInst<
38352(outs HvxWR:$Vdd32),
38353(ins HvxVR:$Vu32),
38354"$Vdd32.h = vsxt($Vu32.b)",
38355tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38356let Inst{7-5} = 0b011;
38357let Inst{13-13} = 0b0;
38358let Inst{31-16} = 0b0001111000000010;
38359let hasNewValue = 1;
38360let opNewValue = 0;
38361let isCVI = 1;
38362let DecoderNamespace = "EXT_mmvec";
38363}
38364def V6_vsb_alt : HInst<
38365(outs HvxWR:$Vdd32),
38366(ins HvxVR:$Vu32),
38367"$Vdd32 = vsxtb($Vu32)",
38368PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38369let hasNewValue = 1;
38370let opNewValue = 0;
38371let isCVI = 1;
38372let isPseudo = 1;
38373let isCodeGenOnly = 1;
38374let DecoderNamespace = "EXT_mmvec";
38375}
38376def V6_vscattermh : HInst<
38377(outs),
38378(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38379"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
38380tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38381let Inst{7-5} = 0b001;
38382let Inst{31-21} = 0b00101111001;
38383let accessSize = HalfWordAccess;
38384let isCVI = 1;
38385let isHVXALU = 1;
38386let isHVXALU2SRC = 1;
38387let mayStore = 1;
38388let DecoderNamespace = "EXT_mmvec";
38389}
38390def V6_vscattermh_add : HInst<
38391(outs),
38392(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38393"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
38394tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38395let Inst{7-5} = 0b101;
38396let Inst{31-21} = 0b00101111001;
38397let accessSize = HalfWordAccess;
38398let isAccumulator = 1;
38399let isCVI = 1;
38400let isHVXALU = 1;
38401let isHVXALU2SRC = 1;
38402let mayStore = 1;
38403let DecoderNamespace = "EXT_mmvec";
38404}
38405def V6_vscattermh_add_alt : HInst<
38406(outs),
38407(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38408"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
38409PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38410let isAccumulator = 1;
38411let isCVI = 1;
38412let isPseudo = 1;
38413let isCodeGenOnly = 1;
38414let DecoderNamespace = "EXT_mmvec";
38415}
38416def V6_vscattermh_alt : HInst<
38417(outs),
38418(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38419"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
38420PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38421let isCVI = 1;
38422let isPseudo = 1;
38423let isCodeGenOnly = 1;
38424let DecoderNamespace = "EXT_mmvec";
38425}
38426def V6_vscattermhq : HInst<
38427(outs),
38428(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38429"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
38430tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
38431let Inst{7-7} = 0b1;
38432let Inst{31-21} = 0b00101111100;
38433let accessSize = HalfWordAccess;
38434let isCVI = 1;
38435let isHVXALU = 1;
38436let isHVXALU2SRC = 1;
38437let mayStore = 1;
38438let DecoderNamespace = "EXT_mmvec";
38439}
38440def V6_vscattermhq_alt : HInst<
38441(outs),
38442(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38443"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
38444PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38445let isCVI = 1;
38446let isPseudo = 1;
38447let isCodeGenOnly = 1;
38448let DecoderNamespace = "EXT_mmvec";
38449}
38450def V6_vscattermhw : HInst<
38451(outs),
38452(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38453"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
38454tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
38455let Inst{7-5} = 0b010;
38456let Inst{31-21} = 0b00101111001;
38457let accessSize = HalfWordAccess;
38458let isCVI = 1;
38459let mayStore = 1;
38460let DecoderNamespace = "EXT_mmvec";
38461}
38462def V6_vscattermhw_add : HInst<
38463(outs),
38464(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38465"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
38466tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
38467let Inst{7-5} = 0b110;
38468let Inst{31-21} = 0b00101111001;
38469let accessSize = HalfWordAccess;
38470let isAccumulator = 1;
38471let isCVI = 1;
38472let mayStore = 1;
38473let DecoderNamespace = "EXT_mmvec";
38474}
38475def V6_vscattermhwq : HInst<
38476(outs),
38477(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38478"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
38479tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
38480let Inst{7-7} = 0b0;
38481let Inst{31-21} = 0b00101111101;
38482let accessSize = HalfWordAccess;
38483let isCVI = 1;
38484let mayStore = 1;
38485let DecoderNamespace = "EXT_mmvec";
38486}
38487def V6_vscattermw : HInst<
38488(outs),
38489(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38490"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
38491tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38492let Inst{7-5} = 0b000;
38493let Inst{31-21} = 0b00101111001;
38494let accessSize = WordAccess;
38495let isCVI = 1;
38496let isHVXALU = 1;
38497let isHVXALU2SRC = 1;
38498let mayStore = 1;
38499let DecoderNamespace = "EXT_mmvec";
38500}
38501def V6_vscattermw_add : HInst<
38502(outs),
38503(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38504"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
38505tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38506let Inst{7-5} = 0b100;
38507let Inst{31-21} = 0b00101111001;
38508let accessSize = WordAccess;
38509let isAccumulator = 1;
38510let isCVI = 1;
38511let isHVXALU = 1;
38512let isHVXALU2SRC = 1;
38513let mayStore = 1;
38514let DecoderNamespace = "EXT_mmvec";
38515}
38516def V6_vscattermw_add_alt : HInst<
38517(outs),
38518(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38519"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
38520PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38521let isAccumulator = 1;
38522let isCVI = 1;
38523let isPseudo = 1;
38524let isCodeGenOnly = 1;
38525let DecoderNamespace = "EXT_mmvec";
38526}
38527def V6_vscattermw_alt : HInst<
38528(outs),
38529(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38530"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
38531PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38532let isCVI = 1;
38533let isPseudo = 1;
38534let isCodeGenOnly = 1;
38535let DecoderNamespace = "EXT_mmvec";
38536}
38537def V6_vscattermwh_add_alt : HInst<
38538(outs),
38539(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38540"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
38541PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38542let isAccumulator = 1;
38543let isCVI = 1;
38544let isPseudo = 1;
38545let isCodeGenOnly = 1;
38546let DecoderNamespace = "EXT_mmvec";
38547}
38548def V6_vscattermwh_alt : HInst<
38549(outs),
38550(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38551"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
38552PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38553let isCVI = 1;
38554let isPseudo = 1;
38555let isCodeGenOnly = 1;
38556let DecoderNamespace = "EXT_mmvec";
38557}
38558def V6_vscattermwhq_alt : HInst<
38559(outs),
38560(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38561"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
38562PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38563let isCVI = 1;
38564let isPseudo = 1;
38565let isCodeGenOnly = 1;
38566let DecoderNamespace = "EXT_mmvec";
38567}
38568def V6_vscattermwq : HInst<
38569(outs),
38570(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38571"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
38572tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
38573let Inst{7-7} = 0b0;
38574let Inst{31-21} = 0b00101111100;
38575let accessSize = WordAccess;
38576let isCVI = 1;
38577let isHVXALU = 1;
38578let isHVXALU2SRC = 1;
38579let mayStore = 1;
38580let DecoderNamespace = "EXT_mmvec";
38581}
38582def V6_vscattermwq_alt : HInst<
38583(outs),
38584(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38585"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
38586PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38587let isCVI = 1;
38588let isPseudo = 1;
38589let isCodeGenOnly = 1;
38590let DecoderNamespace = "EXT_mmvec";
38591}
38592def V6_vsh : HInst<
38593(outs HvxWR:$Vdd32),
38594(ins HvxVR:$Vu32),
38595"$Vdd32.w = vsxt($Vu32.h)",
38596tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38597let Inst{7-5} = 0b100;
38598let Inst{13-13} = 0b0;
38599let Inst{31-16} = 0b0001111000000010;
38600let hasNewValue = 1;
38601let opNewValue = 0;
38602let isCVI = 1;
38603let DecoderNamespace = "EXT_mmvec";
38604}
38605def V6_vsh_alt : HInst<
38606(outs HvxWR:$Vdd32),
38607(ins HvxVR:$Vu32),
38608"$Vdd32 = vsxth($Vu32)",
38609PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38610let hasNewValue = 1;
38611let opNewValue = 0;
38612let isCVI = 1;
38613let isPseudo = 1;
38614let isCodeGenOnly = 1;
38615let DecoderNamespace = "EXT_mmvec";
38616}
38617def V6_vshufeh : HInst<
38618(outs HvxVR:$Vd32),
38619(ins HvxVR:$Vu32, HvxVR:$Vv32),
38620"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
38621tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38622let Inst{7-5} = 0b011;
38623let Inst{13-13} = 0b0;
38624let Inst{31-21} = 0b00011111010;
38625let hasNewValue = 1;
38626let opNewValue = 0;
38627let isCVI = 1;
38628let isHVXALU = 1;
38629let isHVXALU2SRC = 1;
38630let DecoderNamespace = "EXT_mmvec";
38631}
38632def V6_vshufeh_alt : HInst<
38633(outs HvxVR:$Vd32),
38634(ins HvxVR:$Vu32, HvxVR:$Vv32),
38635"$Vd32 = vshuffeh($Vu32,$Vv32)",
38636PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38637let hasNewValue = 1;
38638let opNewValue = 0;
38639let isCVI = 1;
38640let isPseudo = 1;
38641let isCodeGenOnly = 1;
38642let DecoderNamespace = "EXT_mmvec";
38643}
38644def V6_vshuff : HInst<
38645(outs HvxVR:$Vy32, HvxVR:$Vx32),
38646(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
38647"vshuff($Vy32,$Vx32,$Rt32)",
38648tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
38649let Inst{7-5} = 0b001;
38650let Inst{13-13} = 0b1;
38651let Inst{31-21} = 0b00011001111;
38652let hasNewValue = 1;
38653let opNewValue = 0;
38654let hasNewValue2 = 1;
38655let opNewValue2 = 1;
38656let isCVI = 1;
38657let DecoderNamespace = "EXT_mmvec";
38658let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
38659}
38660def V6_vshuffb : HInst<
38661(outs HvxVR:$Vd32),
38662(ins HvxVR:$Vu32),
38663"$Vd32.b = vshuff($Vu32.b)",
38664tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
38665let Inst{7-5} = 0b000;
38666let Inst{13-13} = 0b0;
38667let Inst{31-16} = 0b0001111000000010;
38668let hasNewValue = 1;
38669let opNewValue = 0;
38670let isCVI = 1;
38671let DecoderNamespace = "EXT_mmvec";
38672}
38673def V6_vshuffb_alt : HInst<
38674(outs HvxVR:$Vd32),
38675(ins HvxVR:$Vu32),
38676"$Vd32 = vshuffb($Vu32)",
38677PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38678let hasNewValue = 1;
38679let opNewValue = 0;
38680let isCVI = 1;
38681let isPseudo = 1;
38682let isCodeGenOnly = 1;
38683let DecoderNamespace = "EXT_mmvec";
38684}
38685def V6_vshuffeb : HInst<
38686(outs HvxVR:$Vd32),
38687(ins HvxVR:$Vu32, HvxVR:$Vv32),
38688"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
38689tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38690let Inst{7-5} = 0b001;
38691let Inst{13-13} = 0b0;
38692let Inst{31-21} = 0b00011111010;
38693let hasNewValue = 1;
38694let opNewValue = 0;
38695let isCVI = 1;
38696let isHVXALU = 1;
38697let isHVXALU2SRC = 1;
38698let DecoderNamespace = "EXT_mmvec";
38699}
38700def V6_vshuffeb_alt : HInst<
38701(outs HvxVR:$Vd32),
38702(ins HvxVR:$Vu32, HvxVR:$Vv32),
38703"$Vd32 = vshuffeb($Vu32,$Vv32)",
38704PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38705let hasNewValue = 1;
38706let opNewValue = 0;
38707let isCVI = 1;
38708let isPseudo = 1;
38709let isCodeGenOnly = 1;
38710let DecoderNamespace = "EXT_mmvec";
38711}
38712def V6_vshuffh : HInst<
38713(outs HvxVR:$Vd32),
38714(ins HvxVR:$Vu32),
38715"$Vd32.h = vshuff($Vu32.h)",
38716tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
38717let Inst{7-5} = 0b111;
38718let Inst{13-13} = 0b0;
38719let Inst{31-16} = 0b0001111000000001;
38720let hasNewValue = 1;
38721let opNewValue = 0;
38722let isCVI = 1;
38723let DecoderNamespace = "EXT_mmvec";
38724}
38725def V6_vshuffh_alt : HInst<
38726(outs HvxVR:$Vd32),
38727(ins HvxVR:$Vu32),
38728"$Vd32 = vshuffh($Vu32)",
38729PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38730let hasNewValue = 1;
38731let opNewValue = 0;
38732let isCVI = 1;
38733let isPseudo = 1;
38734let isCodeGenOnly = 1;
38735let DecoderNamespace = "EXT_mmvec";
38736}
38737def V6_vshuffob : HInst<
38738(outs HvxVR:$Vd32),
38739(ins HvxVR:$Vu32, HvxVR:$Vv32),
38740"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
38741tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38742let Inst{7-5} = 0b010;
38743let Inst{13-13} = 0b0;
38744let Inst{31-21} = 0b00011111010;
38745let hasNewValue = 1;
38746let opNewValue = 0;
38747let isCVI = 1;
38748let isHVXALU = 1;
38749let isHVXALU2SRC = 1;
38750let DecoderNamespace = "EXT_mmvec";
38751}
38752def V6_vshuffob_alt : HInst<
38753(outs HvxVR:$Vd32),
38754(ins HvxVR:$Vu32, HvxVR:$Vv32),
38755"$Vd32 = vshuffob($Vu32,$Vv32)",
38756PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38757let hasNewValue = 1;
38758let opNewValue = 0;
38759let isCVI = 1;
38760let isPseudo = 1;
38761let isCodeGenOnly = 1;
38762let DecoderNamespace = "EXT_mmvec";
38763}
38764def V6_vshuffvdd : HInst<
38765(outs HvxWR:$Vdd32),
38766(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
38767"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
38768tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
38769let Inst{7-5} = 0b011;
38770let Inst{13-13} = 0b1;
38771let Inst{31-24} = 0b00011011;
38772let hasNewValue = 1;
38773let opNewValue = 0;
38774let isCVI = 1;
38775let DecoderNamespace = "EXT_mmvec";
38776}
38777def V6_vshufoeb : HInst<
38778(outs HvxWR:$Vdd32),
38779(ins HvxVR:$Vu32, HvxVR:$Vv32),
38780"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
38781tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38782let Inst{7-5} = 0b110;
38783let Inst{13-13} = 0b0;
38784let Inst{31-21} = 0b00011111010;
38785let hasNewValue = 1;
38786let opNewValue = 0;
38787let isCVI = 1;
38788let DecoderNamespace = "EXT_mmvec";
38789}
38790def V6_vshufoeb_alt : HInst<
38791(outs HvxWR:$Vdd32),
38792(ins HvxVR:$Vu32, HvxVR:$Vv32),
38793"$Vdd32 = vshuffoeb($Vu32,$Vv32)",
38794PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38795let hasNewValue = 1;
38796let opNewValue = 0;
38797let isCVI = 1;
38798let isPseudo = 1;
38799let isCodeGenOnly = 1;
38800let DecoderNamespace = "EXT_mmvec";
38801}
38802def V6_vshufoeh : HInst<
38803(outs HvxWR:$Vdd32),
38804(ins HvxVR:$Vu32, HvxVR:$Vv32),
38805"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
38806tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38807let Inst{7-5} = 0b101;
38808let Inst{13-13} = 0b0;
38809let Inst{31-21} = 0b00011111010;
38810let hasNewValue = 1;
38811let opNewValue = 0;
38812let isCVI = 1;
38813let DecoderNamespace = "EXT_mmvec";
38814}
38815def V6_vshufoeh_alt : HInst<
38816(outs HvxWR:$Vdd32),
38817(ins HvxVR:$Vu32, HvxVR:$Vv32),
38818"$Vdd32 = vshuffoeh($Vu32,$Vv32)",
38819PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38820let hasNewValue = 1;
38821let opNewValue = 0;
38822let isCVI = 1;
38823let isPseudo = 1;
38824let isCodeGenOnly = 1;
38825let DecoderNamespace = "EXT_mmvec";
38826}
38827def V6_vshufoh : HInst<
38828(outs HvxVR:$Vd32),
38829(ins HvxVR:$Vu32, HvxVR:$Vv32),
38830"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
38831tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38832let Inst{7-5} = 0b100;
38833let Inst{13-13} = 0b0;
38834let Inst{31-21} = 0b00011111010;
38835let hasNewValue = 1;
38836let opNewValue = 0;
38837let isCVI = 1;
38838let isHVXALU = 1;
38839let isHVXALU2SRC = 1;
38840let DecoderNamespace = "EXT_mmvec";
38841}
38842def V6_vshufoh_alt : HInst<
38843(outs HvxVR:$Vd32),
38844(ins HvxVR:$Vu32, HvxVR:$Vv32),
38845"$Vd32 = vshuffoh($Vu32,$Vv32)",
38846PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38847let hasNewValue = 1;
38848let opNewValue = 0;
38849let isCVI = 1;
38850let isPseudo = 1;
38851let isCodeGenOnly = 1;
38852let DecoderNamespace = "EXT_mmvec";
38853}
38854def V6_vsub_hf : HInst<
38855(outs HvxVR:$Vd32),
38856(ins HvxVR:$Vu32, HvxVR:$Vv32),
38857"$Vd32.qf16 = vsub($Vu32.hf,$Vv32.hf)",
38858tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38859let Inst{7-5} = 0b110;
38860let Inst{13-13} = 0b1;
38861let Inst{31-21} = 0b00011111011;
38862let hasNewValue = 1;
38863let opNewValue = 0;
38864let isCVI = 1;
38865let DecoderNamespace = "EXT_mmvec";
38866}
38867def V6_vsub_hf_hf : HInst<
38868(outs HvxVR:$Vd32),
38869(ins HvxVR:$Vu32, HvxVR:$Vv32),
38870"$Vd32.hf = vsub($Vu32.hf,$Vv32.hf)",
38871tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38872let Inst{7-5} = 0b000;
38873let Inst{13-13} = 0b1;
38874let Inst{31-21} = 0b00011111011;
38875let hasNewValue = 1;
38876let opNewValue = 0;
38877let isCVI = 1;
38878let DecoderNamespace = "EXT_mmvec";
38879}
38880def V6_vsub_qf16 : HInst<
38881(outs HvxVR:$Vd32),
38882(ins HvxVR:$Vu32, HvxVR:$Vv32),
38883"$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.qf16)",
38884tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38885let Inst{7-5} = 0b101;
38886let Inst{13-13} = 0b1;
38887let Inst{31-21} = 0b00011111011;
38888let hasNewValue = 1;
38889let opNewValue = 0;
38890let isCVI = 1;
38891let DecoderNamespace = "EXT_mmvec";
38892}
38893def V6_vsub_qf16_mix : HInst<
38894(outs HvxVR:$Vd32),
38895(ins HvxVR:$Vu32, HvxVR:$Vv32),
38896"$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.hf)",
38897tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38898let Inst{7-5} = 0b111;
38899let Inst{13-13} = 0b1;
38900let Inst{31-21} = 0b00011111011;
38901let hasNewValue = 1;
38902let opNewValue = 0;
38903let isCVI = 1;
38904let DecoderNamespace = "EXT_mmvec";
38905}
38906def V6_vsub_qf32 : HInst<
38907(outs HvxVR:$Vd32),
38908(ins HvxVR:$Vu32, HvxVR:$Vv32),
38909"$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.qf32)",
38910tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38911let Inst{7-5} = 0b011;
38912let Inst{13-13} = 0b1;
38913let Inst{31-21} = 0b00011111101;
38914let hasNewValue = 1;
38915let opNewValue = 0;
38916let isCVI = 1;
38917let DecoderNamespace = "EXT_mmvec";
38918}
38919def V6_vsub_qf32_mix : HInst<
38920(outs HvxVR:$Vd32),
38921(ins HvxVR:$Vu32, HvxVR:$Vv32),
38922"$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.sf)",
38923tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38924let Inst{7-5} = 0b101;
38925let Inst{13-13} = 0b1;
38926let Inst{31-21} = 0b00011111101;
38927let hasNewValue = 1;
38928let opNewValue = 0;
38929let isCVI = 1;
38930let DecoderNamespace = "EXT_mmvec";
38931}
38932def V6_vsub_sf : HInst<
38933(outs HvxVR:$Vd32),
38934(ins HvxVR:$Vu32, HvxVR:$Vv32),
38935"$Vd32.qf32 = vsub($Vu32.sf,$Vv32.sf)",
38936tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38937let Inst{7-5} = 0b100;
38938let Inst{13-13} = 0b1;
38939let Inst{31-21} = 0b00011111101;
38940let hasNewValue = 1;
38941let opNewValue = 0;
38942let isCVI = 1;
38943let DecoderNamespace = "EXT_mmvec";
38944}
38945def V6_vsub_sf_bf : HInst<
38946(outs HvxWR:$Vdd32),
38947(ins HvxVR:$Vu32, HvxVR:$Vv32),
38948"$Vdd32.sf = vsub($Vu32.bf,$Vv32.bf)",
38949tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV73,UseHVXIEEEFP]> {
38950let Inst{7-5} = 0b101;
38951let Inst{13-13} = 0b1;
38952let Inst{31-21} = 0b00011101010;
38953let hasNewValue = 1;
38954let opNewValue = 0;
38955let isCVI = 1;
38956let DecoderNamespace = "EXT_mmvec";
38957}
38958def V6_vsub_sf_hf : HInst<
38959(outs HvxWR:$Vdd32),
38960(ins HvxVR:$Vu32, HvxVR:$Vv32),
38961"$Vdd32.sf = vsub($Vu32.hf,$Vv32.hf)",
38962tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38963let Inst{7-5} = 0b101;
38964let Inst{13-13} = 0b1;
38965let Inst{31-21} = 0b00011111100;
38966let hasNewValue = 1;
38967let opNewValue = 0;
38968let isCVI = 1;
38969let DecoderNamespace = "EXT_mmvec";
38970}
38971def V6_vsub_sf_sf : HInst<
38972(outs HvxVR:$Vd32),
38973(ins HvxVR:$Vu32, HvxVR:$Vv32),
38974"$Vd32.sf = vsub($Vu32.sf,$Vv32.sf)",
38975tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38976let Inst{7-5} = 0b111;
38977let Inst{13-13} = 0b1;
38978let Inst{31-21} = 0b00011111100;
38979let hasNewValue = 1;
38980let opNewValue = 0;
38981let isCVI = 1;
38982let DecoderNamespace = "EXT_mmvec";
38983}
38984def V6_vsubb : HInst<
38985(outs HvxVR:$Vd32),
38986(ins HvxVR:$Vu32, HvxVR:$Vv32),
38987"$Vd32.b = vsub($Vu32.b,$Vv32.b)",
38988tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38989let Inst{7-5} = 0b101;
38990let Inst{13-13} = 0b0;
38991let Inst{31-21} = 0b00011100010;
38992let hasNewValue = 1;
38993let opNewValue = 0;
38994let isCVI = 1;
38995let isHVXALU = 1;
38996let isHVXALU2SRC = 1;
38997let DecoderNamespace = "EXT_mmvec";
38998}
38999def V6_vsubb_alt : HInst<
39000(outs HvxVR:$Vd32),
39001(ins HvxVR:$Vu32, HvxVR:$Vv32),
39002"$Vd32 = vsubb($Vu32,$Vv32)",
39003PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39004let hasNewValue = 1;
39005let opNewValue = 0;
39006let isCVI = 1;
39007let isPseudo = 1;
39008let isCodeGenOnly = 1;
39009let DecoderNamespace = "EXT_mmvec";
39010}
39011def V6_vsubb_dv : HInst<
39012(outs HvxWR:$Vdd32),
39013(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39014"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
39015tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39016let Inst{7-5} = 0b011;
39017let Inst{13-13} = 0b0;
39018let Inst{31-21} = 0b00011100100;
39019let hasNewValue = 1;
39020let opNewValue = 0;
39021let isCVI = 1;
39022let DecoderNamespace = "EXT_mmvec";
39023}
39024def V6_vsubb_dv_alt : HInst<
39025(outs HvxWR:$Vdd32),
39026(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39027"$Vdd32 = vsubb($Vuu32,$Vvv32)",
39028PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39029let hasNewValue = 1;
39030let opNewValue = 0;
39031let isCVI = 1;
39032let isPseudo = 1;
39033let isCodeGenOnly = 1;
39034let DecoderNamespace = "EXT_mmvec";
39035}
39036def V6_vsubbnq : HInst<
39037(outs HvxVR:$Vx32),
39038(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39039"if (!$Qv4) $Vx32.b -= $Vu32.b",
39040tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39041let Inst{7-5} = 0b001;
39042let Inst{13-13} = 0b1;
39043let Inst{21-16} = 0b000010;
39044let Inst{31-24} = 0b00011110;
39045let hasNewValue = 1;
39046let opNewValue = 0;
39047let isCVI = 1;
39048let isHVXALU = 1;
39049let isHVXALU2SRC = 1;
39050let DecoderNamespace = "EXT_mmvec";
39051let Constraints = "$Vx32 = $Vx32in";
39052}
39053def V6_vsubbnq_alt : HInst<
39054(outs HvxVR:$Vx32),
39055(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39056"if (!$Qv4.b) $Vx32.b -= $Vu32.b",
39057PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39058let hasNewValue = 1;
39059let opNewValue = 0;
39060let isCVI = 1;
39061let isPseudo = 1;
39062let isCodeGenOnly = 1;
39063let DecoderNamespace = "EXT_mmvec";
39064let Constraints = "$Vx32 = $Vx32in";
39065}
39066def V6_vsubbq : HInst<
39067(outs HvxVR:$Vx32),
39068(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39069"if ($Qv4) $Vx32.b -= $Vu32.b",
39070tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39071let Inst{7-5} = 0b110;
39072let Inst{13-13} = 0b1;
39073let Inst{21-16} = 0b000001;
39074let Inst{31-24} = 0b00011110;
39075let hasNewValue = 1;
39076let opNewValue = 0;
39077let isCVI = 1;
39078let isHVXALU = 1;
39079let isHVXALU2SRC = 1;
39080let DecoderNamespace = "EXT_mmvec";
39081let Constraints = "$Vx32 = $Vx32in";
39082}
39083def V6_vsubbq_alt : HInst<
39084(outs HvxVR:$Vx32),
39085(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39086"if ($Qv4.b) $Vx32.b -= $Vu32.b",
39087PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39088let hasNewValue = 1;
39089let opNewValue = 0;
39090let isCVI = 1;
39091let isPseudo = 1;
39092let isCodeGenOnly = 1;
39093let DecoderNamespace = "EXT_mmvec";
39094let Constraints = "$Vx32 = $Vx32in";
39095}
39096def V6_vsubbsat : HInst<
39097(outs HvxVR:$Vd32),
39098(ins HvxVR:$Vu32, HvxVR:$Vv32),
39099"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
39100tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
39101let Inst{7-5} = 0b010;
39102let Inst{13-13} = 0b0;
39103let Inst{31-21} = 0b00011111001;
39104let hasNewValue = 1;
39105let opNewValue = 0;
39106let isCVI = 1;
39107let isHVXALU = 1;
39108let isHVXALU2SRC = 1;
39109let DecoderNamespace = "EXT_mmvec";
39110}
39111def V6_vsubbsat_alt : HInst<
39112(outs HvxVR:$Vd32),
39113(ins HvxVR:$Vu32, HvxVR:$Vv32),
39114"$Vd32 = vsubb($Vu32,$Vv32):sat",
39115PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39116let hasNewValue = 1;
39117let opNewValue = 0;
39118let isCVI = 1;
39119let isPseudo = 1;
39120let isCodeGenOnly = 1;
39121let DecoderNamespace = "EXT_mmvec";
39122}
39123def V6_vsubbsat_dv : HInst<
39124(outs HvxWR:$Vdd32),
39125(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39126"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
39127tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
39128let Inst{7-5} = 0b001;
39129let Inst{13-13} = 0b0;
39130let Inst{31-21} = 0b00011110101;
39131let hasNewValue = 1;
39132let opNewValue = 0;
39133let isCVI = 1;
39134let DecoderNamespace = "EXT_mmvec";
39135}
39136def V6_vsubbsat_dv_alt : HInst<
39137(outs HvxWR:$Vdd32),
39138(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39139"$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
39140PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39141let hasNewValue = 1;
39142let opNewValue = 0;
39143let isCVI = 1;
39144let isPseudo = 1;
39145let isCodeGenOnly = 1;
39146let DecoderNamespace = "EXT_mmvec";
39147}
39148def V6_vsubcarry : HInst<
39149(outs HvxVR:$Vd32, HvxQR:$Qx4),
39150(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
39151"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
39152tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
39153let Inst{7-7} = 0b1;
39154let Inst{13-13} = 0b1;
39155let Inst{31-21} = 0b00011100101;
39156let hasNewValue = 1;
39157let opNewValue = 0;
39158let isCVI = 1;
39159let isHVXALU = 1;
39160let isHVXALU2SRC = 1;
39161let DecoderNamespace = "EXT_mmvec";
39162let Constraints = "$Qx4 = $Qx4in";
39163}
39164def V6_vsubcarryo : HInst<
39165(outs HvxVR:$Vd32, HvxQR:$Qe4),
39166(ins HvxVR:$Vu32, HvxVR:$Vv32),
39167"$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry",
39168tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
39169let Inst{7-7} = 0b1;
39170let Inst{13-13} = 0b1;
39171let Inst{31-21} = 0b00011101101;
39172let hasNewValue = 1;
39173let opNewValue = 0;
39174let isCVI = 1;
39175let isHVXALU = 1;
39176let isHVXALU2SRC = 1;
39177let DecoderNamespace = "EXT_mmvec";
39178}
39179def V6_vsubh : HInst<
39180(outs HvxVR:$Vd32),
39181(ins HvxVR:$Vu32, HvxVR:$Vv32),
39182"$Vd32.h = vsub($Vu32.h,$Vv32.h)",
39183tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39184let Inst{7-5} = 0b110;
39185let Inst{13-13} = 0b0;
39186let Inst{31-21} = 0b00011100010;
39187let hasNewValue = 1;
39188let opNewValue = 0;
39189let isCVI = 1;
39190let isHVXALU = 1;
39191let isHVXALU2SRC = 1;
39192let DecoderNamespace = "EXT_mmvec";
39193}
39194def V6_vsubh_alt : HInst<
39195(outs HvxVR:$Vd32),
39196(ins HvxVR:$Vu32, HvxVR:$Vv32),
39197"$Vd32 = vsubh($Vu32,$Vv32)",
39198PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39199let hasNewValue = 1;
39200let opNewValue = 0;
39201let isCVI = 1;
39202let isPseudo = 1;
39203let isCodeGenOnly = 1;
39204let DecoderNamespace = "EXT_mmvec";
39205}
39206def V6_vsubh_dv : HInst<
39207(outs HvxWR:$Vdd32),
39208(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39209"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
39210tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39211let Inst{7-5} = 0b100;
39212let Inst{13-13} = 0b0;
39213let Inst{31-21} = 0b00011100100;
39214let hasNewValue = 1;
39215let opNewValue = 0;
39216let isCVI = 1;
39217let DecoderNamespace = "EXT_mmvec";
39218}
39219def V6_vsubh_dv_alt : HInst<
39220(outs HvxWR:$Vdd32),
39221(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39222"$Vdd32 = vsubh($Vuu32,$Vvv32)",
39223PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39224let hasNewValue = 1;
39225let opNewValue = 0;
39226let isCVI = 1;
39227let isPseudo = 1;
39228let isCodeGenOnly = 1;
39229let DecoderNamespace = "EXT_mmvec";
39230}
39231def V6_vsubhnq : HInst<
39232(outs HvxVR:$Vx32),
39233(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39234"if (!$Qv4) $Vx32.h -= $Vu32.h",
39235tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39236let Inst{7-5} = 0b010;
39237let Inst{13-13} = 0b1;
39238let Inst{21-16} = 0b000010;
39239let Inst{31-24} = 0b00011110;
39240let hasNewValue = 1;
39241let opNewValue = 0;
39242let isCVI = 1;
39243let isHVXALU = 1;
39244let isHVXALU2SRC = 1;
39245let DecoderNamespace = "EXT_mmvec";
39246let Constraints = "$Vx32 = $Vx32in";
39247}
39248def V6_vsubhnq_alt : HInst<
39249(outs HvxVR:$Vx32),
39250(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39251"if (!$Qv4.h) $Vx32.h -= $Vu32.h",
39252PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39253let hasNewValue = 1;
39254let opNewValue = 0;
39255let isCVI = 1;
39256let isPseudo = 1;
39257let isCodeGenOnly = 1;
39258let DecoderNamespace = "EXT_mmvec";
39259let Constraints = "$Vx32 = $Vx32in";
39260}
39261def V6_vsubhq : HInst<
39262(outs HvxVR:$Vx32),
39263(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39264"if ($Qv4) $Vx32.h -= $Vu32.h",
39265tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39266let Inst{7-5} = 0b111;
39267let Inst{13-13} = 0b1;
39268let Inst{21-16} = 0b000001;
39269let Inst{31-24} = 0b00011110;
39270let hasNewValue = 1;
39271let opNewValue = 0;
39272let isCVI = 1;
39273let isHVXALU = 1;
39274let isHVXALU2SRC = 1;
39275let DecoderNamespace = "EXT_mmvec";
39276let Constraints = "$Vx32 = $Vx32in";
39277}
39278def V6_vsubhq_alt : HInst<
39279(outs HvxVR:$Vx32),
39280(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39281"if ($Qv4.h) $Vx32.h -= $Vu32.h",
39282PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39283let hasNewValue = 1;
39284let opNewValue = 0;
39285let isCVI = 1;
39286let isPseudo = 1;
39287let isCodeGenOnly = 1;
39288let DecoderNamespace = "EXT_mmvec";
39289let Constraints = "$Vx32 = $Vx32in";
39290}
39291def V6_vsubhsat : HInst<
39292(outs HvxVR:$Vd32),
39293(ins HvxVR:$Vu32, HvxVR:$Vv32),
39294"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
39295tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39296let Inst{7-5} = 0b010;
39297let Inst{13-13} = 0b0;
39298let Inst{31-21} = 0b00011100011;
39299let hasNewValue = 1;
39300let opNewValue = 0;
39301let isCVI = 1;
39302let isHVXALU = 1;
39303let isHVXALU2SRC = 1;
39304let DecoderNamespace = "EXT_mmvec";
39305}
39306def V6_vsubhsat_alt : HInst<
39307(outs HvxVR:$Vd32),
39308(ins HvxVR:$Vu32, HvxVR:$Vv32),
39309"$Vd32 = vsubh($Vu32,$Vv32):sat",
39310PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39311let hasNewValue = 1;
39312let opNewValue = 0;
39313let isCVI = 1;
39314let isPseudo = 1;
39315let isCodeGenOnly = 1;
39316let DecoderNamespace = "EXT_mmvec";
39317}
39318def V6_vsubhsat_dv : HInst<
39319(outs HvxWR:$Vdd32),
39320(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39321"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
39322tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39323let Inst{7-5} = 0b000;
39324let Inst{13-13} = 0b0;
39325let Inst{31-21} = 0b00011100101;
39326let hasNewValue = 1;
39327let opNewValue = 0;
39328let isCVI = 1;
39329let DecoderNamespace = "EXT_mmvec";
39330}
39331def V6_vsubhsat_dv_alt : HInst<
39332(outs HvxWR:$Vdd32),
39333(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39334"$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
39335PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39336let hasNewValue = 1;
39337let opNewValue = 0;
39338let isCVI = 1;
39339let isPseudo = 1;
39340let isCodeGenOnly = 1;
39341let DecoderNamespace = "EXT_mmvec";
39342}
39343def V6_vsubhw : HInst<
39344(outs HvxWR:$Vdd32),
39345(ins HvxVR:$Vu32, HvxVR:$Vv32),
39346"$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
39347tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
39348let Inst{7-5} = 0b111;
39349let Inst{13-13} = 0b0;
39350let Inst{31-21} = 0b00011100101;
39351let hasNewValue = 1;
39352let opNewValue = 0;
39353let isCVI = 1;
39354let DecoderNamespace = "EXT_mmvec";
39355}
39356def V6_vsubhw_alt : HInst<
39357(outs HvxWR:$Vdd32),
39358(ins HvxVR:$Vu32, HvxVR:$Vv32),
39359"$Vdd32 = vsubh($Vu32,$Vv32)",
39360PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39361let hasNewValue = 1;
39362let opNewValue = 0;
39363let isCVI = 1;
39364let isPseudo = 1;
39365let isCodeGenOnly = 1;
39366let DecoderNamespace = "EXT_mmvec";
39367}
39368def V6_vsububh : HInst<
39369(outs HvxWR:$Vdd32),
39370(ins HvxVR:$Vu32, HvxVR:$Vv32),
39371"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
39372tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
39373let Inst{7-5} = 0b101;
39374let Inst{13-13} = 0b0;
39375let Inst{31-21} = 0b00011100101;
39376let hasNewValue = 1;
39377let opNewValue = 0;
39378let isCVI = 1;
39379let DecoderNamespace = "EXT_mmvec";
39380}
39381def V6_vsububh_alt : HInst<
39382(outs HvxWR:$Vdd32),
39383(ins HvxVR:$Vu32, HvxVR:$Vv32),
39384"$Vdd32 = vsubub($Vu32,$Vv32)",
39385PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39386let hasNewValue = 1;
39387let opNewValue = 0;
39388let isCVI = 1;
39389let isPseudo = 1;
39390let isCodeGenOnly = 1;
39391let DecoderNamespace = "EXT_mmvec";
39392}
39393def V6_vsububsat : HInst<
39394(outs HvxVR:$Vd32),
39395(ins HvxVR:$Vu32, HvxVR:$Vv32),
39396"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
39397tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39398let Inst{7-5} = 0b000;
39399let Inst{13-13} = 0b0;
39400let Inst{31-21} = 0b00011100011;
39401let hasNewValue = 1;
39402let opNewValue = 0;
39403let isCVI = 1;
39404let isHVXALU = 1;
39405let isHVXALU2SRC = 1;
39406let DecoderNamespace = "EXT_mmvec";
39407}
39408def V6_vsububsat_alt : HInst<
39409(outs HvxVR:$Vd32),
39410(ins HvxVR:$Vu32, HvxVR:$Vv32),
39411"$Vd32 = vsubub($Vu32,$Vv32):sat",
39412PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39413let hasNewValue = 1;
39414let opNewValue = 0;
39415let isCVI = 1;
39416let isPseudo = 1;
39417let isCodeGenOnly = 1;
39418let DecoderNamespace = "EXT_mmvec";
39419}
39420def V6_vsububsat_dv : HInst<
39421(outs HvxWR:$Vdd32),
39422(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39423"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
39424tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39425let Inst{7-5} = 0b110;
39426let Inst{13-13} = 0b0;
39427let Inst{31-21} = 0b00011100100;
39428let hasNewValue = 1;
39429let opNewValue = 0;
39430let isCVI = 1;
39431let DecoderNamespace = "EXT_mmvec";
39432}
39433def V6_vsububsat_dv_alt : HInst<
39434(outs HvxWR:$Vdd32),
39435(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39436"$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
39437PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39438let hasNewValue = 1;
39439let opNewValue = 0;
39440let isCVI = 1;
39441let isPseudo = 1;
39442let isCodeGenOnly = 1;
39443let DecoderNamespace = "EXT_mmvec";
39444}
39445def V6_vsubububb_sat : HInst<
39446(outs HvxVR:$Vd32),
39447(ins HvxVR:$Vu32, HvxVR:$Vv32),
39448"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
39449tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
39450let Inst{7-5} = 0b101;
39451let Inst{13-13} = 0b0;
39452let Inst{31-21} = 0b00011110101;
39453let hasNewValue = 1;
39454let opNewValue = 0;
39455let isCVI = 1;
39456let isHVXALU = 1;
39457let isHVXALU2SRC = 1;
39458let DecoderNamespace = "EXT_mmvec";
39459}
39460def V6_vsubuhsat : HInst<
39461(outs HvxVR:$Vd32),
39462(ins HvxVR:$Vu32, HvxVR:$Vv32),
39463"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
39464tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39465let Inst{7-5} = 0b001;
39466let Inst{13-13} = 0b0;
39467let Inst{31-21} = 0b00011100011;
39468let hasNewValue = 1;
39469let opNewValue = 0;
39470let isCVI = 1;
39471let isHVXALU = 1;
39472let isHVXALU2SRC = 1;
39473let DecoderNamespace = "EXT_mmvec";
39474}
39475def V6_vsubuhsat_alt : HInst<
39476(outs HvxVR:$Vd32),
39477(ins HvxVR:$Vu32, HvxVR:$Vv32),
39478"$Vd32 = vsubuh($Vu32,$Vv32):sat",
39479PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39480let hasNewValue = 1;
39481let opNewValue = 0;
39482let isCVI = 1;
39483let isPseudo = 1;
39484let isCodeGenOnly = 1;
39485let DecoderNamespace = "EXT_mmvec";
39486}
39487def V6_vsubuhsat_dv : HInst<
39488(outs HvxWR:$Vdd32),
39489(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39490"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
39491tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39492let Inst{7-5} = 0b111;
39493let Inst{13-13} = 0b0;
39494let Inst{31-21} = 0b00011100100;
39495let hasNewValue = 1;
39496let opNewValue = 0;
39497let isCVI = 1;
39498let DecoderNamespace = "EXT_mmvec";
39499}
39500def V6_vsubuhsat_dv_alt : HInst<
39501(outs HvxWR:$Vdd32),
39502(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39503"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
39504PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39505let hasNewValue = 1;
39506let opNewValue = 0;
39507let isCVI = 1;
39508let isPseudo = 1;
39509let isCodeGenOnly = 1;
39510let DecoderNamespace = "EXT_mmvec";
39511}
39512def V6_vsubuhw : HInst<
39513(outs HvxWR:$Vdd32),
39514(ins HvxVR:$Vu32, HvxVR:$Vv32),
39515"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
39516tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
39517let Inst{7-5} = 0b110;
39518let Inst{13-13} = 0b0;
39519let Inst{31-21} = 0b00011100101;
39520let hasNewValue = 1;
39521let opNewValue = 0;
39522let isCVI = 1;
39523let DecoderNamespace = "EXT_mmvec";
39524}
39525def V6_vsubuhw_alt : HInst<
39526(outs HvxWR:$Vdd32),
39527(ins HvxVR:$Vu32, HvxVR:$Vv32),
39528"$Vdd32 = vsubuh($Vu32,$Vv32)",
39529PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39530let hasNewValue = 1;
39531let opNewValue = 0;
39532let isCVI = 1;
39533let isPseudo = 1;
39534let isCodeGenOnly = 1;
39535let DecoderNamespace = "EXT_mmvec";
39536}
39537def V6_vsubuwsat : HInst<
39538(outs HvxVR:$Vd32),
39539(ins HvxVR:$Vu32, HvxVR:$Vv32),
39540"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
39541tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
39542let Inst{7-5} = 0b100;
39543let Inst{13-13} = 0b0;
39544let Inst{31-21} = 0b00011111110;
39545let hasNewValue = 1;
39546let opNewValue = 0;
39547let isCVI = 1;
39548let isHVXALU = 1;
39549let isHVXALU2SRC = 1;
39550let DecoderNamespace = "EXT_mmvec";
39551}
39552def V6_vsubuwsat_alt : HInst<
39553(outs HvxVR:$Vd32),
39554(ins HvxVR:$Vu32, HvxVR:$Vv32),
39555"$Vd32 = vsubuw($Vu32,$Vv32):sat",
39556PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39557let hasNewValue = 1;
39558let opNewValue = 0;
39559let isCVI = 1;
39560let isPseudo = 1;
39561let isCodeGenOnly = 1;
39562let DecoderNamespace = "EXT_mmvec";
39563}
39564def V6_vsubuwsat_dv : HInst<
39565(outs HvxWR:$Vdd32),
39566(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39567"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
39568tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
39569let Inst{7-5} = 0b011;
39570let Inst{13-13} = 0b0;
39571let Inst{31-21} = 0b00011110101;
39572let hasNewValue = 1;
39573let opNewValue = 0;
39574let isCVI = 1;
39575let DecoderNamespace = "EXT_mmvec";
39576}
39577def V6_vsubuwsat_dv_alt : HInst<
39578(outs HvxWR:$Vdd32),
39579(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39580"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
39581PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39582let hasNewValue = 1;
39583let opNewValue = 0;
39584let isCVI = 1;
39585let isPseudo = 1;
39586let isCodeGenOnly = 1;
39587let DecoderNamespace = "EXT_mmvec";
39588}
39589def V6_vsubw : HInst<
39590(outs HvxVR:$Vd32),
39591(ins HvxVR:$Vu32, HvxVR:$Vv32),
39592"$Vd32.w = vsub($Vu32.w,$Vv32.w)",
39593tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39594let Inst{7-5} = 0b111;
39595let Inst{13-13} = 0b0;
39596let Inst{31-21} = 0b00011100010;
39597let hasNewValue = 1;
39598let opNewValue = 0;
39599let isCVI = 1;
39600let isHVXALU = 1;
39601let isHVXALU2SRC = 1;
39602let DecoderNamespace = "EXT_mmvec";
39603}
39604def V6_vsubw_alt : HInst<
39605(outs HvxVR:$Vd32),
39606(ins HvxVR:$Vu32, HvxVR:$Vv32),
39607"$Vd32 = vsubw($Vu32,$Vv32)",
39608PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39609let hasNewValue = 1;
39610let opNewValue = 0;
39611let isCVI = 1;
39612let isPseudo = 1;
39613let isCodeGenOnly = 1;
39614let DecoderNamespace = "EXT_mmvec";
39615}
39616def V6_vsubw_dv : HInst<
39617(outs HvxWR:$Vdd32),
39618(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39619"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
39620tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39621let Inst{7-5} = 0b101;
39622let Inst{13-13} = 0b0;
39623let Inst{31-21} = 0b00011100100;
39624let hasNewValue = 1;
39625let opNewValue = 0;
39626let isCVI = 1;
39627let DecoderNamespace = "EXT_mmvec";
39628}
39629def V6_vsubw_dv_alt : HInst<
39630(outs HvxWR:$Vdd32),
39631(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39632"$Vdd32 = vsubw($Vuu32,$Vvv32)",
39633PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39634let hasNewValue = 1;
39635let opNewValue = 0;
39636let isCVI = 1;
39637let isPseudo = 1;
39638let isCodeGenOnly = 1;
39639let DecoderNamespace = "EXT_mmvec";
39640}
39641def V6_vsubwnq : HInst<
39642(outs HvxVR:$Vx32),
39643(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39644"if (!$Qv4) $Vx32.w -= $Vu32.w",
39645tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39646let Inst{7-5} = 0b011;
39647let Inst{13-13} = 0b1;
39648let Inst{21-16} = 0b000010;
39649let Inst{31-24} = 0b00011110;
39650let hasNewValue = 1;
39651let opNewValue = 0;
39652let isCVI = 1;
39653let isHVXALU = 1;
39654let isHVXALU2SRC = 1;
39655let DecoderNamespace = "EXT_mmvec";
39656let Constraints = "$Vx32 = $Vx32in";
39657}
39658def V6_vsubwnq_alt : HInst<
39659(outs HvxVR:$Vx32),
39660(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39661"if (!$Qv4.w) $Vx32.w -= $Vu32.w",
39662PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39663let hasNewValue = 1;
39664let opNewValue = 0;
39665let isCVI = 1;
39666let isPseudo = 1;
39667let isCodeGenOnly = 1;
39668let DecoderNamespace = "EXT_mmvec";
39669let Constraints = "$Vx32 = $Vx32in";
39670}
39671def V6_vsubwq : HInst<
39672(outs HvxVR:$Vx32),
39673(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39674"if ($Qv4) $Vx32.w -= $Vu32.w",
39675tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39676let Inst{7-5} = 0b000;
39677let Inst{13-13} = 0b1;
39678let Inst{21-16} = 0b000010;
39679let Inst{31-24} = 0b00011110;
39680let hasNewValue = 1;
39681let opNewValue = 0;
39682let isCVI = 1;
39683let isHVXALU = 1;
39684let isHVXALU2SRC = 1;
39685let DecoderNamespace = "EXT_mmvec";
39686let Constraints = "$Vx32 = $Vx32in";
39687}
39688def V6_vsubwq_alt : HInst<
39689(outs HvxVR:$Vx32),
39690(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39691"if ($Qv4.w) $Vx32.w -= $Vu32.w",
39692PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39693let hasNewValue = 1;
39694let opNewValue = 0;
39695let isCVI = 1;
39696let isPseudo = 1;
39697let isCodeGenOnly = 1;
39698let DecoderNamespace = "EXT_mmvec";
39699let Constraints = "$Vx32 = $Vx32in";
39700}
39701def V6_vsubwsat : HInst<
39702(outs HvxVR:$Vd32),
39703(ins HvxVR:$Vu32, HvxVR:$Vv32),
39704"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
39705tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39706let Inst{7-5} = 0b011;
39707let Inst{13-13} = 0b0;
39708let Inst{31-21} = 0b00011100011;
39709let hasNewValue = 1;
39710let opNewValue = 0;
39711let isCVI = 1;
39712let isHVXALU = 1;
39713let isHVXALU2SRC = 1;
39714let DecoderNamespace = "EXT_mmvec";
39715}
39716def V6_vsubwsat_alt : HInst<
39717(outs HvxVR:$Vd32),
39718(ins HvxVR:$Vu32, HvxVR:$Vv32),
39719"$Vd32 = vsubw($Vu32,$Vv32):sat",
39720PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39721let hasNewValue = 1;
39722let opNewValue = 0;
39723let isCVI = 1;
39724let isPseudo = 1;
39725let isCodeGenOnly = 1;
39726let DecoderNamespace = "EXT_mmvec";
39727}
39728def V6_vsubwsat_dv : HInst<
39729(outs HvxWR:$Vdd32),
39730(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39731"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
39732tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39733let Inst{7-5} = 0b001;
39734let Inst{13-13} = 0b0;
39735let Inst{31-21} = 0b00011100101;
39736let hasNewValue = 1;
39737let opNewValue = 0;
39738let isCVI = 1;
39739let DecoderNamespace = "EXT_mmvec";
39740}
39741def V6_vsubwsat_dv_alt : HInst<
39742(outs HvxWR:$Vdd32),
39743(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39744"$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
39745PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39746let hasNewValue = 1;
39747let opNewValue = 0;
39748let isCVI = 1;
39749let isPseudo = 1;
39750let isCodeGenOnly = 1;
39751let DecoderNamespace = "EXT_mmvec";
39752}
39753def V6_vswap : HInst<
39754(outs HvxWR:$Vdd32),
39755(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
39756"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
39757tc_71646d06, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
39758let Inst{7-7} = 0b0;
39759let Inst{13-13} = 0b1;
39760let Inst{31-21} = 0b00011110101;
39761let hasNewValue = 1;
39762let opNewValue = 0;
39763let isCVI = 1;
39764let DecoderNamespace = "EXT_mmvec";
39765}
39766def V6_vtmpyb : HInst<
39767(outs HvxWR:$Vdd32),
39768(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39769"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
39770tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39771let Inst{7-5} = 0b000;
39772let Inst{13-13} = 0b0;
39773let Inst{31-21} = 0b00011001000;
39774let hasNewValue = 1;
39775let opNewValue = 0;
39776let isCVI = 1;
39777let DecoderNamespace = "EXT_mmvec";
39778}
39779def V6_vtmpyb_acc : HInst<
39780(outs HvxWR:$Vxx32),
39781(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39782"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
39783tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39784let Inst{7-5} = 0b000;
39785let Inst{13-13} = 0b1;
39786let Inst{31-21} = 0b00011001000;
39787let hasNewValue = 1;
39788let opNewValue = 0;
39789let isAccumulator = 1;
39790let isCVI = 1;
39791let DecoderNamespace = "EXT_mmvec";
39792let Constraints = "$Vxx32 = $Vxx32in";
39793}
39794def V6_vtmpyb_acc_alt : HInst<
39795(outs HvxWR:$Vxx32),
39796(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39797"$Vxx32 += vtmpyb($Vuu32,$Rt32)",
39798PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39799let hasNewValue = 1;
39800let opNewValue = 0;
39801let isAccumulator = 1;
39802let isCVI = 1;
39803let isPseudo = 1;
39804let isCodeGenOnly = 1;
39805let DecoderNamespace = "EXT_mmvec";
39806let Constraints = "$Vxx32 = $Vxx32in";
39807}
39808def V6_vtmpyb_alt : HInst<
39809(outs HvxWR:$Vdd32),
39810(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39811"$Vdd32 = vtmpyb($Vuu32,$Rt32)",
39812PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39813let hasNewValue = 1;
39814let opNewValue = 0;
39815let isCVI = 1;
39816let isPseudo = 1;
39817let isCodeGenOnly = 1;
39818let DecoderNamespace = "EXT_mmvec";
39819}
39820def V6_vtmpybus : HInst<
39821(outs HvxWR:$Vdd32),
39822(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39823"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
39824tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39825let Inst{7-5} = 0b001;
39826let Inst{13-13} = 0b0;
39827let Inst{31-21} = 0b00011001000;
39828let hasNewValue = 1;
39829let opNewValue = 0;
39830let isCVI = 1;
39831let DecoderNamespace = "EXT_mmvec";
39832}
39833def V6_vtmpybus_acc : HInst<
39834(outs HvxWR:$Vxx32),
39835(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39836"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
39837tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39838let Inst{7-5} = 0b001;
39839let Inst{13-13} = 0b1;
39840let Inst{31-21} = 0b00011001000;
39841let hasNewValue = 1;
39842let opNewValue = 0;
39843let isAccumulator = 1;
39844let isCVI = 1;
39845let DecoderNamespace = "EXT_mmvec";
39846let Constraints = "$Vxx32 = $Vxx32in";
39847}
39848def V6_vtmpybus_acc_alt : HInst<
39849(outs HvxWR:$Vxx32),
39850(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39851"$Vxx32 += vtmpybus($Vuu32,$Rt32)",
39852PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39853let hasNewValue = 1;
39854let opNewValue = 0;
39855let isAccumulator = 1;
39856let isCVI = 1;
39857let isPseudo = 1;
39858let isCodeGenOnly = 1;
39859let DecoderNamespace = "EXT_mmvec";
39860let Constraints = "$Vxx32 = $Vxx32in";
39861}
39862def V6_vtmpybus_alt : HInst<
39863(outs HvxWR:$Vdd32),
39864(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39865"$Vdd32 = vtmpybus($Vuu32,$Rt32)",
39866PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39867let hasNewValue = 1;
39868let opNewValue = 0;
39869let isCVI = 1;
39870let isPseudo = 1;
39871let isCodeGenOnly = 1;
39872let DecoderNamespace = "EXT_mmvec";
39873}
39874def V6_vtmpyhb : HInst<
39875(outs HvxWR:$Vdd32),
39876(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39877"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
39878tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39879let Inst{7-5} = 0b100;
39880let Inst{13-13} = 0b0;
39881let Inst{31-21} = 0b00011001101;
39882let hasNewValue = 1;
39883let opNewValue = 0;
39884let isCVI = 1;
39885let DecoderNamespace = "EXT_mmvec";
39886}
39887def V6_vtmpyhb_acc : HInst<
39888(outs HvxWR:$Vxx32),
39889(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39890"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
39891tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39892let Inst{7-5} = 0b010;
39893let Inst{13-13} = 0b1;
39894let Inst{31-21} = 0b00011001000;
39895let hasNewValue = 1;
39896let opNewValue = 0;
39897let isAccumulator = 1;
39898let isCVI = 1;
39899let DecoderNamespace = "EXT_mmvec";
39900let Constraints = "$Vxx32 = $Vxx32in";
39901}
39902def V6_vtmpyhb_acc_alt : HInst<
39903(outs HvxWR:$Vxx32),
39904(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39905"$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
39906PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39907let hasNewValue = 1;
39908let opNewValue = 0;
39909let isAccumulator = 1;
39910let isCVI = 1;
39911let isPseudo = 1;
39912let isCodeGenOnly = 1;
39913let DecoderNamespace = "EXT_mmvec";
39914let Constraints = "$Vxx32 = $Vxx32in";
39915}
39916def V6_vtmpyhb_alt : HInst<
39917(outs HvxWR:$Vdd32),
39918(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39919"$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
39920PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39921let hasNewValue = 1;
39922let opNewValue = 0;
39923let isCVI = 1;
39924let isPseudo = 1;
39925let isCodeGenOnly = 1;
39926let DecoderNamespace = "EXT_mmvec";
39927}
39928def V6_vtran2x2_map : HInst<
39929(outs HvxVR:$Vy32, HvxVR:$Vx32),
39930(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
39931"vtrans2x2($Vy32,$Vx32,$Rt32)",
39932PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39933let hasNewValue = 1;
39934let opNewValue = 0;
39935let hasNewValue2 = 1;
39936let opNewValue2 = 1;
39937let isCVI = 1;
39938let isPseudo = 1;
39939let isCodeGenOnly = 1;
39940let DecoderNamespace = "EXT_mmvec";
39941let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
39942}
39943def V6_vunpackb : HInst<
39944(outs HvxWR:$Vdd32),
39945(ins HvxVR:$Vu32),
39946"$Vdd32.h = vunpack($Vu32.b)",
39947tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39948let Inst{7-5} = 0b010;
39949let Inst{13-13} = 0b0;
39950let Inst{31-16} = 0b0001111000000001;
39951let hasNewValue = 1;
39952let opNewValue = 0;
39953let isCVI = 1;
39954let DecoderNamespace = "EXT_mmvec";
39955}
39956def V6_vunpackb_alt : HInst<
39957(outs HvxWR:$Vdd32),
39958(ins HvxVR:$Vu32),
39959"$Vdd32 = vunpackb($Vu32)",
39960PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39961let hasNewValue = 1;
39962let opNewValue = 0;
39963let isCVI = 1;
39964let isPseudo = 1;
39965let isCodeGenOnly = 1;
39966let DecoderNamespace = "EXT_mmvec";
39967}
39968def V6_vunpackh : HInst<
39969(outs HvxWR:$Vdd32),
39970(ins HvxVR:$Vu32),
39971"$Vdd32.w = vunpack($Vu32.h)",
39972tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39973let Inst{7-5} = 0b011;
39974let Inst{13-13} = 0b0;
39975let Inst{31-16} = 0b0001111000000001;
39976let hasNewValue = 1;
39977let opNewValue = 0;
39978let isCVI = 1;
39979let DecoderNamespace = "EXT_mmvec";
39980}
39981def V6_vunpackh_alt : HInst<
39982(outs HvxWR:$Vdd32),
39983(ins HvxVR:$Vu32),
39984"$Vdd32 = vunpackh($Vu32)",
39985PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39986let hasNewValue = 1;
39987let opNewValue = 0;
39988let isCVI = 1;
39989let isPseudo = 1;
39990let isCodeGenOnly = 1;
39991let DecoderNamespace = "EXT_mmvec";
39992}
39993def V6_vunpackob : HInst<
39994(outs HvxWR:$Vxx32),
39995(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
39996"$Vxx32.h |= vunpacko($Vu32.b)",
39997tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
39998let Inst{7-5} = 0b000;
39999let Inst{13-13} = 0b1;
40000let Inst{31-16} = 0b0001111000000000;
40001let hasNewValue = 1;
40002let opNewValue = 0;
40003let isAccumulator = 1;
40004let isCVI = 1;
40005let DecoderNamespace = "EXT_mmvec";
40006let Constraints = "$Vxx32 = $Vxx32in";
40007}
40008def V6_vunpackob_alt : HInst<
40009(outs HvxWR:$Vxx32),
40010(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
40011"$Vxx32 |= vunpackob($Vu32)",
40012PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40013let hasNewValue = 1;
40014let opNewValue = 0;
40015let isAccumulator = 1;
40016let isCVI = 1;
40017let isPseudo = 1;
40018let DecoderNamespace = "EXT_mmvec";
40019let Constraints = "$Vxx32 = $Vxx32in";
40020}
40021def V6_vunpackoh : HInst<
40022(outs HvxWR:$Vxx32),
40023(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
40024"$Vxx32.w |= vunpacko($Vu32.h)",
40025tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
40026let Inst{7-5} = 0b001;
40027let Inst{13-13} = 0b1;
40028let Inst{31-16} = 0b0001111000000000;
40029let hasNewValue = 1;
40030let opNewValue = 0;
40031let isAccumulator = 1;
40032let isCVI = 1;
40033let DecoderNamespace = "EXT_mmvec";
40034let Constraints = "$Vxx32 = $Vxx32in";
40035}
40036def V6_vunpackoh_alt : HInst<
40037(outs HvxWR:$Vxx32),
40038(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
40039"$Vxx32 |= vunpackoh($Vu32)",
40040PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40041let hasNewValue = 1;
40042let opNewValue = 0;
40043let isAccumulator = 1;
40044let isCVI = 1;
40045let isPseudo = 1;
40046let isCodeGenOnly = 1;
40047let DecoderNamespace = "EXT_mmvec";
40048let Constraints = "$Vxx32 = $Vxx32in";
40049}
40050def V6_vunpackub : HInst<
40051(outs HvxWR:$Vdd32),
40052(ins HvxVR:$Vu32),
40053"$Vdd32.uh = vunpack($Vu32.ub)",
40054tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
40055let Inst{7-5} = 0b000;
40056let Inst{13-13} = 0b0;
40057let Inst{31-16} = 0b0001111000000001;
40058let hasNewValue = 1;
40059let opNewValue = 0;
40060let isCVI = 1;
40061let DecoderNamespace = "EXT_mmvec";
40062}
40063def V6_vunpackub_alt : HInst<
40064(outs HvxWR:$Vdd32),
40065(ins HvxVR:$Vu32),
40066"$Vdd32 = vunpackub($Vu32)",
40067PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40068let hasNewValue = 1;
40069let opNewValue = 0;
40070let isCVI = 1;
40071let isPseudo = 1;
40072let isCodeGenOnly = 1;
40073let DecoderNamespace = "EXT_mmvec";
40074}
40075def V6_vunpackuh : HInst<
40076(outs HvxWR:$Vdd32),
40077(ins HvxVR:$Vu32),
40078"$Vdd32.uw = vunpack($Vu32.uh)",
40079tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
40080let Inst{7-5} = 0b001;
40081let Inst{13-13} = 0b0;
40082let Inst{31-16} = 0b0001111000000001;
40083let hasNewValue = 1;
40084let opNewValue = 0;
40085let isCVI = 1;
40086let DecoderNamespace = "EXT_mmvec";
40087}
40088def V6_vunpackuh_alt : HInst<
40089(outs HvxWR:$Vdd32),
40090(ins HvxVR:$Vu32),
40091"$Vdd32 = vunpackuh($Vu32)",
40092PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40093let hasNewValue = 1;
40094let opNewValue = 0;
40095let isCVI = 1;
40096let isPseudo = 1;
40097let isCodeGenOnly = 1;
40098let DecoderNamespace = "EXT_mmvec";
40099}
40100def V6_vwhist128 : HInst<
40101(outs),
40102(ins),
40103"vwhist128",
40104tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
40105let Inst{13-0} = 0b10010010000000;
40106let Inst{31-16} = 0b0001111000000000;
40107let isCVI = 1;
40108let DecoderNamespace = "EXT_mmvec";
40109}
40110def V6_vwhist128m : HInst<
40111(outs),
40112(ins u1_0Imm:$Ii),
40113"vwhist128(#$Ii)",
40114tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
40115let Inst{7-0} = 0b10000000;
40116let Inst{13-9} = 0b10011;
40117let Inst{31-16} = 0b0001111000000000;
40118let isCVI = 1;
40119let DecoderNamespace = "EXT_mmvec";
40120}
40121def V6_vwhist128q : HInst<
40122(outs),
40123(ins HvxQR:$Qv4),
40124"vwhist128($Qv4)",
40125tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
40126let Inst{13-0} = 0b10010010000000;
40127let Inst{21-16} = 0b000010;
40128let Inst{31-24} = 0b00011110;
40129let isCVI = 1;
40130let DecoderNamespace = "EXT_mmvec";
40131}
40132def V6_vwhist128qm : HInst<
40133(outs),
40134(ins HvxQR:$Qv4, u1_0Imm:$Ii),
40135"vwhist128($Qv4,#$Ii)",
40136tc_767c4e9d, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
40137let Inst{7-0} = 0b10000000;
40138let Inst{13-9} = 0b10011;
40139let Inst{21-16} = 0b000010;
40140let Inst{31-24} = 0b00011110;
40141let isCVI = 1;
40142let DecoderNamespace = "EXT_mmvec";
40143}
40144def V6_vwhist256 : HInst<
40145(outs),
40146(ins),
40147"vwhist256",
40148tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
40149let Inst{13-0} = 0b10001010000000;
40150let Inst{31-16} = 0b0001111000000000;
40151let isCVI = 1;
40152let DecoderNamespace = "EXT_mmvec";
40153}
40154def V6_vwhist256_sat : HInst<
40155(outs),
40156(ins),
40157"vwhist256:sat",
40158tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
40159let Inst{13-0} = 0b10001110000000;
40160let Inst{31-16} = 0b0001111000000000;
40161let isCVI = 1;
40162let DecoderNamespace = "EXT_mmvec";
40163}
40164def V6_vwhist256q : HInst<
40165(outs),
40166(ins HvxQR:$Qv4),
40167"vwhist256($Qv4)",
40168tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
40169let Inst{13-0} = 0b10001010000000;
40170let Inst{21-16} = 0b000010;
40171let Inst{31-24} = 0b00011110;
40172let isCVI = 1;
40173let DecoderNamespace = "EXT_mmvec";
40174}
40175def V6_vwhist256q_sat : HInst<
40176(outs),
40177(ins HvxQR:$Qv4),
40178"vwhist256($Qv4):sat",
40179tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
40180let Inst{13-0} = 0b10001110000000;
40181let Inst{21-16} = 0b000010;
40182let Inst{31-24} = 0b00011110;
40183let isCVI = 1;
40184let DecoderNamespace = "EXT_mmvec";
40185}
40186def V6_vxor : HInst<
40187(outs HvxVR:$Vd32),
40188(ins HvxVR:$Vu32, HvxVR:$Vv32),
40189"$Vd32 = vxor($Vu32,$Vv32)",
40190tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
40191let Inst{7-5} = 0b111;
40192let Inst{13-13} = 0b0;
40193let Inst{31-21} = 0b00011100001;
40194let hasNewValue = 1;
40195let opNewValue = 0;
40196let isCVI = 1;
40197let isHVXALU = 1;
40198let isHVXALU2SRC = 1;
40199let DecoderNamespace = "EXT_mmvec";
40200}
40201def V6_vzb : HInst<
40202(outs HvxWR:$Vdd32),
40203(ins HvxVR:$Vu32),
40204"$Vdd32.uh = vzxt($Vu32.ub)",
40205tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
40206let Inst{7-5} = 0b001;
40207let Inst{13-13} = 0b0;
40208let Inst{31-16} = 0b0001111000000010;
40209let hasNewValue = 1;
40210let opNewValue = 0;
40211let isCVI = 1;
40212let DecoderNamespace = "EXT_mmvec";
40213}
40214def V6_vzb_alt : HInst<
40215(outs HvxWR:$Vdd32),
40216(ins HvxVR:$Vu32),
40217"$Vdd32 = vzxtb($Vu32)",
40218PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40219let hasNewValue = 1;
40220let opNewValue = 0;
40221let isCVI = 1;
40222let isPseudo = 1;
40223let isCodeGenOnly = 1;
40224let DecoderNamespace = "EXT_mmvec";
40225}
40226def V6_vzh : HInst<
40227(outs HvxWR:$Vdd32),
40228(ins HvxVR:$Vu32),
40229"$Vdd32.uw = vzxt($Vu32.uh)",
40230tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
40231let Inst{7-5} = 0b010;
40232let Inst{13-13} = 0b0;
40233let Inst{31-16} = 0b0001111000000010;
40234let hasNewValue = 1;
40235let opNewValue = 0;
40236let isCVI = 1;
40237let DecoderNamespace = "EXT_mmvec";
40238}
40239def V6_vzh_alt : HInst<
40240(outs HvxWR:$Vdd32),
40241(ins HvxVR:$Vu32),
40242"$Vdd32 = vzxth($Vu32)",
40243PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40244let hasNewValue = 1;
40245let opNewValue = 0;
40246let isCVI = 1;
40247let isPseudo = 1;
40248let isCodeGenOnly = 1;
40249let DecoderNamespace = "EXT_mmvec";
40250}
40251def V6_zLd_ai : HInst<
40252(outs),
40253(ins IntRegs:$Rt32, s4_0Imm:$Ii),
40254"z = vmem($Rt32+#$Ii)",
40255tc_e699ae41, TypeCVI_ZW>, Enc_ff3442, Requires<[UseHVXV66,UseZReg]>, PostInc_BaseImm {
40256let Inst{7-0} = 0b00000000;
40257let Inst{12-11} = 0b00;
40258let Inst{31-21} = 0b00101100000;
40259let addrMode = BaseImmOffset;
40260let isCVI = 1;
40261let mayLoad = 1;
40262let isRestrictNoSlot1Store = 1;
40263let CextOpcode = "V6_zLd";
40264let DecoderNamespace = "EXT_mmvec";
40265}
40266def V6_zLd_pi : HInst<
40267(outs IntRegs:$Rx32),
40268(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
40269"z = vmem($Rx32++#$Ii)",
40270tc_a0dbea28, TypeCVI_ZW>, Enc_6c9ee0, Requires<[UseHVXV66,UseZReg]>, PostInc_BaseImm {
40271let Inst{7-0} = 0b00000000;
40272let Inst{13-11} = 0b000;
40273let Inst{31-21} = 0b00101101000;
40274let addrMode = PostInc;
40275let isCVI = 1;
40276let mayLoad = 1;
40277let isRestrictNoSlot1Store = 1;
40278let CextOpcode = "V6_zLd";
40279let DecoderNamespace = "EXT_mmvec";
40280let Constraints = "$Rx32 = $Rx32in";
40281}
40282def V6_zLd_ppu : HInst<
40283(outs IntRegs:$Rx32),
40284(ins IntRegs:$Rx32in, ModRegs:$Mu2),
40285"z = vmem($Rx32++$Mu2)",
40286tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> {
40287let Inst{12-0} = 0b0000000000001;
40288let Inst{31-21} = 0b00101101000;
40289let addrMode = PostInc;
40290let isCVI = 1;
40291let mayLoad = 1;
40292let isRestrictNoSlot1Store = 1;
40293let DecoderNamespace = "EXT_mmvec";
40294let Constraints = "$Rx32 = $Rx32in";
40295}
40296def V6_zLd_pred_ai : HInst<
40297(outs),
40298(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
40299"if ($Pv4) z = vmem($Rt32+#$Ii)",
40300tc_dd5b0695, TypeCVI_ZW>, Enc_ef601b, Requires<[UseHVXV66,UseZReg]> {
40301let Inst{7-0} = 0b00000000;
40302let Inst{31-21} = 0b00101100100;
40303let isPredicated = 1;
40304let addrMode = BaseImmOffset;
40305let isCVI = 1;
40306let mayLoad = 1;
40307let isRestrictNoSlot1Store = 1;
40308let DecoderNamespace = "EXT_mmvec";
40309}
40310def V6_zLd_pred_pi : HInst<
40311(outs IntRegs:$Rx32),
40312(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
40313"if ($Pv4) z = vmem($Rx32++#$Ii)",
40314tc_3ad719fb, TypeCVI_ZW>, Enc_6baed4, Requires<[UseHVXV66,UseZReg]> {
40315let Inst{7-0} = 0b00000000;
40316let Inst{13-13} = 0b0;
40317let Inst{31-21} = 0b00101101100;
40318let isPredicated = 1;
40319let addrMode = PostInc;
40320let isCVI = 1;
40321let mayLoad = 1;
40322let isRestrictNoSlot1Store = 1;
40323let DecoderNamespace = "EXT_mmvec";
40324let Constraints = "$Rx32 = $Rx32in";
40325}
40326def V6_zLd_pred_ppu : HInst<
40327(outs IntRegs:$Rx32),
40328(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
40329"if ($Pv4) z = vmem($Rx32++$Mu2)",
40330tc_3ad719fb, TypeCVI_ZW>, Enc_691712, Requires<[UseHVXV66,UseZReg]> {
40331let Inst{10-0} = 0b00000000001;
40332let Inst{31-21} = 0b00101101100;
40333let isPredicated = 1;
40334let addrMode = PostInc;
40335let isCVI = 1;
40336let mayLoad = 1;
40337let isRestrictNoSlot1Store = 1;
40338let DecoderNamespace = "EXT_mmvec";
40339let Constraints = "$Rx32 = $Rx32in";
40340}
40341def V6_zextract : HInst<
40342(outs HvxVR:$Vd32),
40343(ins IntRegs:$Rt32),
40344"$Vd32 = zextract($Rt32)",
40345tc_5bf8afbb, TypeCVI_VP>, Enc_a5ed8a, Requires<[UseHVXV66,UseZReg]> {
40346let Inst{13-5} = 0b000001001;
40347let Inst{31-21} = 0b00011001101;
40348let hasNewValue = 1;
40349let opNewValue = 0;
40350let isCVI = 1;
40351let DecoderNamespace = "EXT_mmvec";
40352}
40353def V6_zld0 : HInst<
40354(outs),
40355(ins IntRegs:$Rt32),
40356"z = vmem($Rt32)",
40357PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
40358let isCVI = 1;
40359let isPseudo = 1;
40360let isCodeGenOnly = 1;
40361let DecoderNamespace = "EXT_mmvec";
40362}
40363def V6_zldp0 : HInst<
40364(outs),
40365(ins PredRegs:$Pv4, IntRegs:$Rt32),
40366"if ($Pv4) z = vmem($Rt32)",
40367PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
40368let isCVI = 1;
40369let isPseudo = 1;
40370let isCodeGenOnly = 1;
40371let DecoderNamespace = "EXT_mmvec";
40372}
40373def Y2_barrier : HInst<
40374(outs),
40375(ins),
40376"barrier",
40377tc_77f94a5e, TypeST>, Enc_e3b0c4 {
40378let Inst{13-0} = 0b00000000000000;
40379let Inst{31-16} = 0b1010100000000000;
40380let isSoloAX = 1;
40381let hasSideEffects = 1;
40382}
40383def Y2_break : HInst<
40384(outs),
40385(ins),
40386"brkpt",
40387tc_55255f2b, TypeCR>, Enc_e3b0c4 {
40388let Inst{13-0} = 0b00000000000000;
40389let Inst{31-16} = 0b0110110000100000;
40390let isSolo = 1;
40391}
40392def Y2_crswap0 : HInst<
40393(outs IntRegs:$Rx32),
40394(ins IntRegs:$Rx32in),
40395"crswap($Rx32,sgp0)",
40396tc_7dc63b5c, TypeCR>, Enc_403871 {
40397let Inst{13-0} = 0b00000000000000;
40398let Inst{31-21} = 0b01100101000;
40399let hasNewValue = 1;
40400let opNewValue = 0;
40401let Uses = [SGP0];
40402let Defs = [SGP0];
40403let Constraints = "$Rx32 = $Rx32in";
40404}
40405def Y2_crswap_old : HInst<
40406(outs IntRegs:$Rx32),
40407(ins IntRegs:$Rx32in),
40408"crswap($Rx32,sgp)",
40409tc_7dc63b5c, TypeMAPPING> {
40410let hasNewValue = 1;
40411let opNewValue = 0;
40412let isPseudo = 1;
40413let isCodeGenOnly = 1;
40414let Constraints = "$Rx32 = $Rx32in";
40415}
40416def Y2_dccleana : HInst<
40417(outs),
40418(ins IntRegs:$Rs32),
40419"dccleana($Rs32)",
40420tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40421let Inst{13-0} = 0b00000000000000;
40422let Inst{31-21} = 0b10100000000;
40423let isRestrictSlot1AOK = 1;
40424let hasSideEffects = 1;
40425}
40426def Y2_dccleaninva : HInst<
40427(outs),
40428(ins IntRegs:$Rs32),
40429"dccleaninva($Rs32)",
40430tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40431let Inst{13-0} = 0b00000000000000;
40432let Inst{31-21} = 0b10100000010;
40433let isRestrictSlot1AOK = 1;
40434let hasSideEffects = 1;
40435}
40436def Y2_dcfetch : HInst<
40437(outs),
40438(ins IntRegs:$Rs32),
40439"dcfetch($Rs32)",
40440tc_d45ba9cd, TypeMAPPING> {
40441let hasSideEffects = 1;
40442let isPseudo = 1;
40443let isCodeGenOnly = 1;
40444}
40445def Y2_dcfetchbo : HInst<
40446(outs),
40447(ins IntRegs:$Rs32, u11_3Imm:$Ii),
40448"dcfetch($Rs32+#$Ii)",
40449tc_2237d952, TypeLD>, Enc_2d829e {
40450let Inst{13-11} = 0b000;
40451let Inst{31-21} = 0b10010100000;
40452let addrMode = BaseImmOffset;
40453let isRestrictNoSlot1Store = 1;
40454let hasSideEffects = 1;
40455}
40456def Y2_dcinva : HInst<
40457(outs),
40458(ins IntRegs:$Rs32),
40459"dcinva($Rs32)",
40460tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40461let Inst{13-0} = 0b00000000000000;
40462let Inst{31-21} = 0b10100000001;
40463let isRestrictSlot1AOK = 1;
40464let hasSideEffects = 1;
40465}
40466def Y2_dczeroa : HInst<
40467(outs),
40468(ins IntRegs:$Rs32),
40469"dczeroa($Rs32)",
40470tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40471let Inst{13-0} = 0b00000000000000;
40472let Inst{31-21} = 0b10100000110;
40473let isRestrictSlot1AOK = 1;
40474let mayStore = 1;
40475let hasSideEffects = 1;
40476}
40477def Y2_icinva : HInst<
40478(outs),
40479(ins IntRegs:$Rs32),
40480"icinva($Rs32)",
40481tc_0ba0d5da, TypeJ>, Enc_ecbcc8 {
40482let Inst{13-0} = 0b00000000000000;
40483let Inst{31-21} = 0b01010110110;
40484let isSolo = 1;
40485}
40486def Y2_isync : HInst<
40487(outs),
40488(ins),
40489"isync",
40490tc_9b34f5e0, TypeJ>, Enc_e3b0c4 {
40491let Inst{13-0} = 0b00000000000010;
40492let Inst{31-16} = 0b0101011111000000;
40493let isSolo = 1;
40494}
40495def Y2_k1lock_map : HInst<
40496(outs),
40497(ins),
40498"k1lock",
40499PSEUDO, TypeMAPPING>, Requires<[HasV65]> {
40500let isPseudo = 1;
40501let isCodeGenOnly = 1;
40502}
40503def Y2_k1unlock_map : HInst<
40504(outs),
40505(ins),
40506"k1unlock",
40507PSEUDO, TypeMAPPING>, Requires<[HasV65]> {
40508let isPseudo = 1;
40509let isCodeGenOnly = 1;
40510}
40511def Y2_syncht : HInst<
40512(outs),
40513(ins),
40514"syncht",
40515tc_77f94a5e, TypeST>, Enc_e3b0c4 {
40516let Inst{13-0} = 0b00000000000000;
40517let Inst{31-16} = 0b1010100001000000;
40518let isSolo = 1;
40519}
40520def Y2_tfrscrr : HInst<
40521(outs IntRegs:$Rd32),
40522(ins SysRegs:$Ss128),
40523"$Rd32 = $Ss128",
40524tc_fae9dfa5, TypeCR>, Enc_7d1542 {
40525let Inst{13-5} = 0b000000000;
40526let Inst{31-23} = 0b011011101;
40527let hasNewValue = 1;
40528let opNewValue = 0;
40529}
40530def Y2_tfrsrcr : HInst<
40531(outs SysRegs:$Sd128),
40532(ins IntRegs:$Rs32),
40533"$Sd128 = $Rs32",
40534tc_6ae3426b, TypeCR>, Enc_8f7633 {
40535let Inst{13-7} = 0b0000000;
40536let Inst{31-21} = 0b01100111000;
40537let hasNewValue = 1;
40538let opNewValue = 0;
40539}
40540def Y2_wait : HInst<
40541(outs),
40542(ins IntRegs:$Rs32),
40543"wait($Rs32)",
40544tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> {
40545let Inst{13-0} = 0b00000000000000;
40546let Inst{31-21} = 0b01100100010;
40547let isSolo = 1;
40548}
40549def Y4_crswap1 : HInst<
40550(outs IntRegs:$Rx32),
40551(ins IntRegs:$Rx32in),
40552"crswap($Rx32,sgp1)",
40553tc_7dc63b5c, TypeCR>, Enc_403871 {
40554let Inst{13-0} = 0b00000000000000;
40555let Inst{31-21} = 0b01100101001;
40556let hasNewValue = 1;
40557let opNewValue = 0;
40558let Uses = [SGP1];
40559let Defs = [SGP1];
40560let Constraints = "$Rx32 = $Rx32in";
40561}
40562def Y4_crswap10 : HInst<
40563(outs DoubleRegs:$Rxx32),
40564(ins DoubleRegs:$Rxx32in, sgp10Const:$sgp10),
40565"crswap($Rxx32,$sgp10)",
40566tc_27106296, TypeCR>, Enc_d0fe02 {
40567let Inst{13-0} = 0b00000000000000;
40568let Inst{31-21} = 0b01101101100;
40569let Uses = [SGP0, SGP1];
40570let Defs = [SGP0, SGP1];
40571let Constraints = "$Rxx32 = $Rxx32in";
40572}
40573def Y4_l2fetch : HInst<
40574(outs),
40575(ins IntRegs:$Rs32, IntRegs:$Rt32),
40576"l2fetch($Rs32,$Rt32)",
40577tc_a3070909, TypeST>, Enc_ca3887 {
40578let Inst{7-0} = 0b00000000;
40579let Inst{13-13} = 0b0;
40580let Inst{31-21} = 0b10100110000;
40581let isSoloAX = 1;
40582let hasSideEffects = 1;
40583let mayStore = 1;
40584}
40585def Y4_tfrscpp : HInst<
40586(outs DoubleRegs:$Rdd32),
40587(ins SysRegs64:$Sss128),
40588"$Rdd32 = $Sss128",
40589tc_fae9dfa5, TypeCR>, Enc_e32517 {
40590let Inst{13-5} = 0b000000000;
40591let Inst{31-23} = 0b011011110;
40592}
40593def Y4_tfrspcp : HInst<
40594(outs SysRegs64:$Sdd128),
40595(ins DoubleRegs:$Rss32),
40596"$Sdd128 = $Rss32",
40597tc_6ae3426b, TypeCR>, Enc_a705fc {
40598let Inst{13-7} = 0b0000000;
40599let Inst{31-21} = 0b01101101000;
40600let hasNewValue = 1;
40601let opNewValue = 0;
40602}
40603def Y4_trace : HInst<
40604(outs),
40605(ins IntRegs:$Rs32),
40606"trace($Rs32)",
40607tc_d7718fbe, TypeCR>, Enc_ecbcc8 {
40608let Inst{13-0} = 0b00000000000000;
40609let Inst{31-21} = 0b01100010010;
40610let isSoloAX = 1;
40611}
40612def Y5_l2fetch : HInst<
40613(outs),
40614(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
40615"l2fetch($Rs32,$Rtt32)",
40616tc_a3070909, TypeST>, Enc_e6abcf {
40617let Inst{7-0} = 0b00000000;
40618let Inst{13-13} = 0b0;
40619let Inst{31-21} = 0b10100110100;
40620let isSoloAX = 1;
40621let hasSideEffects = 1;
40622let mayStore = 1;
40623}
40624def Y6_diag : HInst<
40625(outs),
40626(ins IntRegs:$Rs32),
40627"diag($Rs32)",
40628tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV67]> {
40629let Inst{13-0} = 0b00000000100000;
40630let Inst{31-21} = 0b01100010010;
40631}
40632def Y6_diag0 : HInst<
40633(outs),
40634(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
40635"diag0($Rss32,$Rtt32)",
40636tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
40637let Inst{7-0} = 0b01000000;
40638let Inst{13-13} = 0b0;
40639let Inst{31-21} = 0b01100010010;
40640}
40641def Y6_diag1 : HInst<
40642(outs),
40643(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
40644"diag1($Rss32,$Rtt32)",
40645tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
40646let Inst{7-0} = 0b01100000;
40647let Inst{13-13} = 0b0;
40648let Inst{31-21} = 0b01100010010;
40649}
40650def Y6_dmlink : HInst<
40651(outs),
40652(ins IntRegs:$Rs32, IntRegs:$Rt32),
40653"dmlink($Rs32,$Rt32)",
40654tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
40655let Inst{7-0} = 0b01000000;
40656let Inst{13-13} = 0b0;
40657let Inst{31-21} = 0b10100110000;
40658let hasSideEffects = 1;
40659let isSolo = 1;
40660let mayStore = 1;
40661}
40662def Y6_dmpause : HInst<
40663(outs IntRegs:$Rd32),
40664(ins),
40665"$Rd32 = dmpause",
40666tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
40667let Inst{13-5} = 0b000000011;
40668let Inst{31-16} = 0b1010100000000000;
40669let hasNewValue = 1;
40670let opNewValue = 0;
40671let hasSideEffects = 1;
40672let isSolo = 1;
40673}
40674def Y6_dmpoll : HInst<
40675(outs IntRegs:$Rd32),
40676(ins),
40677"$Rd32 = dmpoll",
40678tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
40679let Inst{13-5} = 0b000000010;
40680let Inst{31-16} = 0b1010100000000000;
40681let hasNewValue = 1;
40682let opNewValue = 0;
40683let hasSideEffects = 1;
40684let isSolo = 1;
40685}
40686def Y6_dmresume : HInst<
40687(outs),
40688(ins IntRegs:$Rs32),
40689"dmresume($Rs32)",
40690tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
40691let Inst{13-0} = 0b00000010000000;
40692let Inst{31-21} = 0b10100110000;
40693let hasSideEffects = 1;
40694let isSolo = 1;
40695}
40696def Y6_dmstart : HInst<
40697(outs),
40698(ins IntRegs:$Rs32),
40699"dmstart($Rs32)",
40700tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
40701let Inst{13-0} = 0b00000000100000;
40702let Inst{31-21} = 0b10100110000;
40703let hasSideEffects = 1;
40704let isSolo = 1;
40705}
40706def Y6_dmwait : HInst<
40707(outs IntRegs:$Rd32),
40708(ins),
40709"$Rd32 = dmwait",
40710tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
40711let Inst{13-5} = 0b000000001;
40712let Inst{31-16} = 0b1010100000000000;
40713let hasNewValue = 1;
40714let opNewValue = 0;
40715let hasSideEffects = 1;
40716let isSolo = 1;
40717}
40718def dep_A2_addsat : HInst<
40719(outs IntRegs:$Rd32),
40720(ins IntRegs:$Rs32, IntRegs:$Rt32),
40721"$Rd32 = add($Rs32,$Rt32):sat:deprecated",
40722tc_8a825db2, TypeALU64>, Enc_5ab2be {
40723let Inst{7-5} = 0b000;
40724let Inst{13-13} = 0b0;
40725let Inst{31-21} = 0b11010101100;
40726let hasNewValue = 1;
40727let opNewValue = 0;
40728let prefersSlot3 = 1;
40729let Defs = [USR_OVF];
40730}
40731def dep_A2_subsat : HInst<
40732(outs IntRegs:$Rd32),
40733(ins IntRegs:$Rt32, IntRegs:$Rs32),
40734"$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
40735tc_8a825db2, TypeALU64>, Enc_bd6011 {
40736let Inst{7-5} = 0b100;
40737let Inst{13-13} = 0b0;
40738let Inst{31-21} = 0b11010101100;
40739let hasNewValue = 1;
40740let opNewValue = 0;
40741let prefersSlot3 = 1;
40742let Defs = [USR_OVF];
40743}
40744def dep_S2_packhl : HInst<
40745(outs DoubleRegs:$Rdd32),
40746(ins IntRegs:$Rs32, IntRegs:$Rt32),
40747"$Rdd32 = packhl($Rs32,$Rt32):deprecated",
40748tc_5da50c4b, TypeALU64>, Enc_be32a5 {
40749let Inst{7-5} = 0b000;
40750let Inst{13-13} = 0b0;
40751let Inst{31-21} = 0b11010100000;
40752}
40753def dup_A2_add : HInst<
40754(outs IntRegs:$Rd32),
40755(ins IntRegs:$Rs32, IntRegs:$Rt32),
40756"$Rd32 = add($Rs32,$Rt32)",
40757tc_388f9897, TypeALU32_3op>, Requires<[HasV73]> {
40758let hasNewValue = 1;
40759let opNewValue = 0;
40760let AsmVariantName = "NonParsable";
40761let isPseudo = 1;
40762}
40763def dup_A2_addi : HInst<
40764(outs IntRegs:$Rd32),
40765(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40766"$Rd32 = add($Rs32,#$Ii)",
40767tc_388f9897, TypeALU32_ADDI>, Requires<[HasV73]> {
40768let hasNewValue = 1;
40769let opNewValue = 0;
40770let AsmVariantName = "NonParsable";
40771let isPseudo = 1;
40772let isExtendable = 1;
40773let opExtendable = 2;
40774let isExtentSigned = 1;
40775let opExtentBits = 16;
40776let opExtentAlign = 0;
40777}
40778def dup_A2_andir : HInst<
40779(outs IntRegs:$Rd32),
40780(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40781"$Rd32 = and($Rs32,#$Ii)",
40782tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40783let hasNewValue = 1;
40784let opNewValue = 0;
40785let AsmVariantName = "NonParsable";
40786let isPseudo = 1;
40787let isExtendable = 1;
40788let opExtendable = 2;
40789let isExtentSigned = 1;
40790let opExtentBits = 10;
40791let opExtentAlign = 0;
40792}
40793def dup_A2_combineii : HInst<
40794(outs DoubleRegs:$Rdd32),
40795(ins s32_0Imm:$Ii, s8_0Imm:$II),
40796"$Rdd32 = combine(#$Ii,#$II)",
40797tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40798let AsmVariantName = "NonParsable";
40799let isPseudo = 1;
40800let isExtendable = 1;
40801let opExtendable = 1;
40802let isExtentSigned = 1;
40803let opExtentBits = 8;
40804let opExtentAlign = 0;
40805}
40806def dup_A2_sxtb : HInst<
40807(outs IntRegs:$Rd32),
40808(ins IntRegs:$Rs32),
40809"$Rd32 = sxtb($Rs32)",
40810tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
40811let hasNewValue = 1;
40812let opNewValue = 0;
40813let AsmVariantName = "NonParsable";
40814let isPseudo = 1;
40815}
40816def dup_A2_sxth : HInst<
40817(outs IntRegs:$Rd32),
40818(ins IntRegs:$Rs32),
40819"$Rd32 = sxth($Rs32)",
40820tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
40821let hasNewValue = 1;
40822let opNewValue = 0;
40823let AsmVariantName = "NonParsable";
40824let isPseudo = 1;
40825}
40826def dup_A2_tfr : HInst<
40827(outs IntRegs:$Rd32),
40828(ins IntRegs:$Rs32),
40829"$Rd32 = $Rs32",
40830tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
40831let hasNewValue = 1;
40832let opNewValue = 0;
40833let AsmVariantName = "NonParsable";
40834let isPseudo = 1;
40835}
40836def dup_A2_tfrsi : HInst<
40837(outs IntRegs:$Rd32),
40838(ins s32_0Imm:$Ii),
40839"$Rd32 = #$Ii",
40840tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
40841let hasNewValue = 1;
40842let opNewValue = 0;
40843let AsmVariantName = "NonParsable";
40844let isPseudo = 1;
40845let isExtendable = 1;
40846let opExtendable = 1;
40847let isExtentSigned = 1;
40848let opExtentBits = 16;
40849let opExtentAlign = 0;
40850}
40851def dup_A2_zxtb : HInst<
40852(outs IntRegs:$Rd32),
40853(ins IntRegs:$Rs32),
40854"$Rd32 = zxtb($Rs32)",
40855PSEUDO, TypeMAPPING>, Requires<[HasV73]> {
40856let hasNewValue = 1;
40857let opNewValue = 0;
40858let AsmVariantName = "NonParsable";
40859let isPseudo = 1;
40860}
40861def dup_A2_zxth : HInst<
40862(outs IntRegs:$Rd32),
40863(ins IntRegs:$Rs32),
40864"$Rd32 = zxth($Rs32)",
40865tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
40866let hasNewValue = 1;
40867let opNewValue = 0;
40868let AsmVariantName = "NonParsable";
40869let isPseudo = 1;
40870}
40871def dup_A4_combineii : HInst<
40872(outs DoubleRegs:$Rdd32),
40873(ins s8_0Imm:$Ii, u32_0Imm:$II),
40874"$Rdd32 = combine(#$Ii,#$II)",
40875tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40876let AsmVariantName = "NonParsable";
40877let isPseudo = 1;
40878let isExtendable = 1;
40879let opExtendable = 2;
40880let isExtentSigned = 0;
40881let opExtentBits = 6;
40882let opExtentAlign = 0;
40883}
40884def dup_A4_combineir : HInst<
40885(outs DoubleRegs:$Rdd32),
40886(ins s32_0Imm:$Ii, IntRegs:$Rs32),
40887"$Rdd32 = combine(#$Ii,$Rs32)",
40888tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40889let AsmVariantName = "NonParsable";
40890let isPseudo = 1;
40891let isExtendable = 1;
40892let opExtendable = 1;
40893let isExtentSigned = 1;
40894let opExtentBits = 8;
40895let opExtentAlign = 0;
40896}
40897def dup_A4_combineri : HInst<
40898(outs DoubleRegs:$Rdd32),
40899(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40900"$Rdd32 = combine($Rs32,#$Ii)",
40901tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40902let AsmVariantName = "NonParsable";
40903let isPseudo = 1;
40904let isExtendable = 1;
40905let opExtendable = 2;
40906let isExtentSigned = 1;
40907let opExtentBits = 8;
40908let opExtentAlign = 0;
40909}
40910def dup_C2_cmoveif : HInst<
40911(outs IntRegs:$Rd32),
40912(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40913"if (!$Pu4) $Rd32 = #$Ii",
40914tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40915let isPredicated = 1;
40916let isPredicatedFalse = 1;
40917let hasNewValue = 1;
40918let opNewValue = 0;
40919let AsmVariantName = "NonParsable";
40920let isPseudo = 1;
40921let isExtendable = 1;
40922let opExtendable = 2;
40923let isExtentSigned = 1;
40924let opExtentBits = 12;
40925let opExtentAlign = 0;
40926}
40927def dup_C2_cmoveit : HInst<
40928(outs IntRegs:$Rd32),
40929(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40930"if ($Pu4) $Rd32 = #$Ii",
40931tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40932let isPredicated = 1;
40933let hasNewValue = 1;
40934let opNewValue = 0;
40935let AsmVariantName = "NonParsable";
40936let isPseudo = 1;
40937let isExtendable = 1;
40938let opExtendable = 2;
40939let isExtentSigned = 1;
40940let opExtentBits = 12;
40941let opExtentAlign = 0;
40942}
40943def dup_C2_cmovenewif : HInst<
40944(outs IntRegs:$Rd32),
40945(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40946"if (!$Pu4.new) $Rd32 = #$Ii",
40947tc_4ac61d92, TypeALU32_2op>, Requires<[HasV73]> {
40948let isPredicated = 1;
40949let isPredicatedFalse = 1;
40950let hasNewValue = 1;
40951let opNewValue = 0;
40952let AsmVariantName = "NonParsable";
40953let isPredicatedNew = 1;
40954let isPseudo = 1;
40955let isExtendable = 1;
40956let opExtendable = 2;
40957let isExtentSigned = 1;
40958let opExtentBits = 12;
40959let opExtentAlign = 0;
40960}
40961def dup_C2_cmovenewit : HInst<
40962(outs IntRegs:$Rd32),
40963(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40964"if ($Pu4.new) $Rd32 = #$Ii",
40965tc_4ac61d92, TypeALU32_2op>, Requires<[HasV73]> {
40966let isPredicated = 1;
40967let hasNewValue = 1;
40968let opNewValue = 0;
40969let AsmVariantName = "NonParsable";
40970let isPredicatedNew = 1;
40971let isPseudo = 1;
40972let isExtendable = 1;
40973let opExtendable = 2;
40974let isExtentSigned = 1;
40975let opExtentBits = 12;
40976let opExtentAlign = 0;
40977}
40978def dup_C2_cmpeqi : HInst<
40979(outs PredRegs:$Pd4),
40980(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40981"$Pd4 = cmp.eq($Rs32,#$Ii)",
40982tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
40983let AsmVariantName = "NonParsable";
40984let isPseudo = 1;
40985let isExtendable = 1;
40986let opExtendable = 2;
40987let isExtentSigned = 1;
40988let opExtentBits = 10;
40989let opExtentAlign = 0;
40990}
40991def dup_L2_deallocframe : HInst<
40992(outs DoubleRegs:$Rdd32),
40993(ins IntRegs:$Rs32),
40994"$Rdd32 = deallocframe($Rs32):raw",
40995tc_aee6250c, TypeLD>, Requires<[HasV73]> {
40996let accessSize = DoubleWordAccess;
40997let AsmVariantName = "NonParsable";
40998let mayLoad = 1;
40999let Uses = [FRAMEKEY];
41000let Defs = [R29];
41001let isPseudo = 1;
41002}
41003def dup_L2_loadrb_io : HInst<
41004(outs IntRegs:$Rd32),
41005(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41006"$Rd32 = memb($Rs32+#$Ii)",
41007tc_eed07714, TypeLD>, Requires<[HasV73]> {
41008let hasNewValue = 1;
41009let opNewValue = 0;
41010let addrMode = BaseImmOffset;
41011let accessSize = ByteAccess;
41012let AsmVariantName = "NonParsable";
41013let mayLoad = 1;
41014let isPseudo = 1;
41015let isExtendable = 1;
41016let opExtendable = 2;
41017let isExtentSigned = 1;
41018let opExtentBits = 11;
41019let opExtentAlign = 0;
41020}
41021def dup_L2_loadrd_io : HInst<
41022(outs DoubleRegs:$Rdd32),
41023(ins IntRegs:$Rs32, s29_3Imm:$Ii),
41024"$Rdd32 = memd($Rs32+#$Ii)",
41025tc_eed07714, TypeLD>, Requires<[HasV73]> {
41026let addrMode = BaseImmOffset;
41027let accessSize = DoubleWordAccess;
41028let AsmVariantName = "NonParsable";
41029let mayLoad = 1;
41030let isPseudo = 1;
41031let isExtendable = 1;
41032let opExtendable = 2;
41033let isExtentSigned = 1;
41034let opExtentBits = 14;
41035let opExtentAlign = 3;
41036}
41037def dup_L2_loadrh_io : HInst<
41038(outs IntRegs:$Rd32),
41039(ins IntRegs:$Rs32, s31_1Imm:$Ii),
41040"$Rd32 = memh($Rs32+#$Ii)",
41041tc_eed07714, TypeLD>, Requires<[HasV73]> {
41042let hasNewValue = 1;
41043let opNewValue = 0;
41044let addrMode = BaseImmOffset;
41045let accessSize = HalfWordAccess;
41046let AsmVariantName = "NonParsable";
41047let mayLoad = 1;
41048let isPseudo = 1;
41049let isExtendable = 1;
41050let opExtendable = 2;
41051let isExtentSigned = 1;
41052let opExtentBits = 12;
41053let opExtentAlign = 1;
41054}
41055def dup_L2_loadri_io : HInst<
41056(outs IntRegs:$Rd32),
41057(ins IntRegs:$Rs32, s30_2Imm:$Ii),
41058"$Rd32 = memw($Rs32+#$Ii)",
41059tc_eed07714, TypeLD>, Requires<[HasV73]> {
41060let hasNewValue = 1;
41061let opNewValue = 0;
41062let addrMode = BaseImmOffset;
41063let accessSize = WordAccess;
41064let AsmVariantName = "NonParsable";
41065let mayLoad = 1;
41066let isPseudo = 1;
41067let isExtendable = 1;
41068let opExtendable = 2;
41069let isExtentSigned = 1;
41070let opExtentBits = 13;
41071let opExtentAlign = 2;
41072}
41073def dup_L2_loadrub_io : HInst<
41074(outs IntRegs:$Rd32),
41075(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41076"$Rd32 = memub($Rs32+#$Ii)",
41077tc_eed07714, TypeLD>, Requires<[HasV73]> {
41078let hasNewValue = 1;
41079let opNewValue = 0;
41080let addrMode = BaseImmOffset;
41081let accessSize = ByteAccess;
41082let AsmVariantName = "NonParsable";
41083let mayLoad = 1;
41084let isPseudo = 1;
41085let isExtendable = 1;
41086let opExtendable = 2;
41087let isExtentSigned = 1;
41088let opExtentBits = 11;
41089let opExtentAlign = 0;
41090}
41091def dup_L2_loadruh_io : HInst<
41092(outs IntRegs:$Rd32),
41093(ins IntRegs:$Rs32, s31_1Imm:$Ii),
41094"$Rd32 = memuh($Rs32+#$Ii)",
41095tc_eed07714, TypeLD>, Requires<[HasV73]> {
41096let hasNewValue = 1;
41097let opNewValue = 0;
41098let addrMode = BaseImmOffset;
41099let accessSize = HalfWordAccess;
41100let AsmVariantName = "NonParsable";
41101let mayLoad = 1;
41102let isPseudo = 1;
41103let isExtendable = 1;
41104let opExtendable = 2;
41105let isExtentSigned = 1;
41106let opExtentBits = 12;
41107let opExtentAlign = 1;
41108}
41109def dup_S2_allocframe : HInst<
41110(outs IntRegs:$Rx32),
41111(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
41112"allocframe($Rx32,#$Ii):raw",
41113tc_74a42bda, TypeST>, Requires<[HasV73]> {
41114let hasNewValue = 1;
41115let opNewValue = 0;
41116let addrMode = BaseImmOffset;
41117let accessSize = DoubleWordAccess;
41118let AsmVariantName = "NonParsable";
41119let mayStore = 1;
41120let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
41121let Defs = [R30];
41122let isPseudo = 1;
41123let Constraints = "$Rx32 = $Rx32in";
41124}
41125def dup_S2_storerb_io : HInst<
41126(outs),
41127(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
41128"memb($Rs32+#$Ii) = $Rt32",
41129tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41130let addrMode = BaseImmOffset;
41131let accessSize = ByteAccess;
41132let AsmVariantName = "NonParsable";
41133let mayStore = 1;
41134let isPseudo = 1;
41135let isExtendable = 1;
41136let opExtendable = 1;
41137let isExtentSigned = 1;
41138let opExtentBits = 11;
41139let opExtentAlign = 0;
41140}
41141def dup_S2_storerd_io : HInst<
41142(outs),
41143(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
41144"memd($Rs32+#$Ii) = $Rtt32",
41145tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41146let addrMode = BaseImmOffset;
41147let accessSize = DoubleWordAccess;
41148let AsmVariantName = "NonParsable";
41149let mayStore = 1;
41150let isPseudo = 1;
41151let isExtendable = 1;
41152let opExtendable = 1;
41153let isExtentSigned = 1;
41154let opExtentBits = 14;
41155let opExtentAlign = 3;
41156}
41157def dup_S2_storerh_io : HInst<
41158(outs),
41159(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
41160"memh($Rs32+#$Ii) = $Rt32",
41161tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41162let addrMode = BaseImmOffset;
41163let accessSize = HalfWordAccess;
41164let AsmVariantName = "NonParsable";
41165let mayStore = 1;
41166let isPseudo = 1;
41167let isExtendable = 1;
41168let opExtendable = 1;
41169let isExtentSigned = 1;
41170let opExtentBits = 12;
41171let opExtentAlign = 1;
41172}
41173def dup_S2_storeri_io : HInst<
41174(outs),
41175(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
41176"memw($Rs32+#$Ii) = $Rt32",
41177tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41178let addrMode = BaseImmOffset;
41179let accessSize = WordAccess;
41180let AsmVariantName = "NonParsable";
41181let mayStore = 1;
41182let isPseudo = 1;
41183let isExtendable = 1;
41184let opExtendable = 1;
41185let isExtentSigned = 1;
41186let opExtentBits = 13;
41187let opExtentAlign = 2;
41188}
41189def dup_S4_storeirb_io : HInst<
41190(outs),
41191(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
41192"memb($Rs32+#$Ii) = #$II",
41193tc_838c4d7a, TypeV4LDST>, Requires<[HasV73]> {
41194let addrMode = BaseImmOffset;
41195let accessSize = ByteAccess;
41196let AsmVariantName = "NonParsable";
41197let mayStore = 1;
41198let isPseudo = 1;
41199let isExtendable = 1;
41200let opExtendable = 2;
41201let isExtentSigned = 1;
41202let opExtentBits = 8;
41203let opExtentAlign = 0;
41204}
41205def dup_S4_storeiri_io : HInst<
41206(outs),
41207(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
41208"memw($Rs32+#$Ii) = #$II",
41209tc_838c4d7a, TypeV4LDST>, Requires<[HasV73]> {
41210let addrMode = BaseImmOffset;
41211let accessSize = WordAccess;
41212let AsmVariantName = "NonParsable";
41213let mayStore = 1;
41214let isPseudo = 1;
41215let isExtendable = 1;
41216let opExtendable = 2;
41217let isExtentSigned = 1;
41218let opExtentBits = 8;
41219let opExtentAlign = 0;
41220}
41221