xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (revision d5b0e70f7e04d971691517ce1304d86a1e367e2e) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11def A2_abs : HInst<
12(outs IntRegs:$Rd32),
13(ins IntRegs:$Rs32),
14"$Rd32 = abs($Rs32)",
15tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
16let Inst{13-5} = 0b000000100;
17let Inst{31-21} = 0b10001100100;
18let hasNewValue = 1;
19let opNewValue = 0;
20let prefersSlot3 = 1;
21}
22def A2_absp : HInst<
23(outs DoubleRegs:$Rdd32),
24(ins DoubleRegs:$Rss32),
25"$Rdd32 = abs($Rss32)",
26tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
27let Inst{13-5} = 0b000000110;
28let Inst{31-21} = 0b10000000100;
29let prefersSlot3 = 1;
30}
31def A2_abssat : HInst<
32(outs IntRegs:$Rd32),
33(ins IntRegs:$Rs32),
34"$Rd32 = abs($Rs32):sat",
35tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
36let Inst{13-5} = 0b000000101;
37let Inst{31-21} = 0b10001100100;
38let hasNewValue = 1;
39let opNewValue = 0;
40let prefersSlot3 = 1;
41let Defs = [USR_OVF];
42}
43def A2_add : HInst<
44(outs IntRegs:$Rd32),
45(ins IntRegs:$Rs32, IntRegs:$Rt32),
46"$Rd32 = add($Rs32,$Rt32)",
47tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
48let Inst{7-5} = 0b000;
49let Inst{13-13} = 0b0;
50let Inst{31-21} = 0b11110011000;
51let hasNewValue = 1;
52let opNewValue = 0;
53let BaseOpcode = "A2_add";
54let CextOpcode = "A2_add";
55let InputType = "reg";
56let isCommutable = 1;
57let isPredicable = 1;
58}
59def A2_addh_h16_hh : HInst<
60(outs IntRegs:$Rd32),
61(ins IntRegs:$Rt32, IntRegs:$Rs32),
62"$Rd32 = add($Rt32.h,$Rs32.h):<<16",
63tc_01d44cb2, TypeALU64>, Enc_bd6011 {
64let Inst{7-5} = 0b011;
65let Inst{13-13} = 0b0;
66let Inst{31-21} = 0b11010101010;
67let hasNewValue = 1;
68let opNewValue = 0;
69let prefersSlot3 = 1;
70}
71def A2_addh_h16_hl : HInst<
72(outs IntRegs:$Rd32),
73(ins IntRegs:$Rt32, IntRegs:$Rs32),
74"$Rd32 = add($Rt32.h,$Rs32.l):<<16",
75tc_01d44cb2, TypeALU64>, Enc_bd6011 {
76let Inst{7-5} = 0b010;
77let Inst{13-13} = 0b0;
78let Inst{31-21} = 0b11010101010;
79let hasNewValue = 1;
80let opNewValue = 0;
81let prefersSlot3 = 1;
82}
83def A2_addh_h16_lh : HInst<
84(outs IntRegs:$Rd32),
85(ins IntRegs:$Rt32, IntRegs:$Rs32),
86"$Rd32 = add($Rt32.l,$Rs32.h):<<16",
87tc_01d44cb2, TypeALU64>, Enc_bd6011 {
88let Inst{7-5} = 0b001;
89let Inst{13-13} = 0b0;
90let Inst{31-21} = 0b11010101010;
91let hasNewValue = 1;
92let opNewValue = 0;
93let prefersSlot3 = 1;
94}
95def A2_addh_h16_ll : HInst<
96(outs IntRegs:$Rd32),
97(ins IntRegs:$Rt32, IntRegs:$Rs32),
98"$Rd32 = add($Rt32.l,$Rs32.l):<<16",
99tc_01d44cb2, TypeALU64>, Enc_bd6011 {
100let Inst{7-5} = 0b000;
101let Inst{13-13} = 0b0;
102let Inst{31-21} = 0b11010101010;
103let hasNewValue = 1;
104let opNewValue = 0;
105let prefersSlot3 = 1;
106}
107def A2_addh_h16_sat_hh : HInst<
108(outs IntRegs:$Rd32),
109(ins IntRegs:$Rt32, IntRegs:$Rs32),
110"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
111tc_8a825db2, TypeALU64>, Enc_bd6011 {
112let Inst{7-5} = 0b111;
113let Inst{13-13} = 0b0;
114let Inst{31-21} = 0b11010101010;
115let hasNewValue = 1;
116let opNewValue = 0;
117let prefersSlot3 = 1;
118let Defs = [USR_OVF];
119}
120def A2_addh_h16_sat_hl : HInst<
121(outs IntRegs:$Rd32),
122(ins IntRegs:$Rt32, IntRegs:$Rs32),
123"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
124tc_8a825db2, TypeALU64>, Enc_bd6011 {
125let Inst{7-5} = 0b110;
126let Inst{13-13} = 0b0;
127let Inst{31-21} = 0b11010101010;
128let hasNewValue = 1;
129let opNewValue = 0;
130let prefersSlot3 = 1;
131let Defs = [USR_OVF];
132}
133def A2_addh_h16_sat_lh : HInst<
134(outs IntRegs:$Rd32),
135(ins IntRegs:$Rt32, IntRegs:$Rs32),
136"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
137tc_8a825db2, TypeALU64>, Enc_bd6011 {
138let Inst{7-5} = 0b101;
139let Inst{13-13} = 0b0;
140let Inst{31-21} = 0b11010101010;
141let hasNewValue = 1;
142let opNewValue = 0;
143let prefersSlot3 = 1;
144let Defs = [USR_OVF];
145}
146def A2_addh_h16_sat_ll : HInst<
147(outs IntRegs:$Rd32),
148(ins IntRegs:$Rt32, IntRegs:$Rs32),
149"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
150tc_8a825db2, TypeALU64>, Enc_bd6011 {
151let Inst{7-5} = 0b100;
152let Inst{13-13} = 0b0;
153let Inst{31-21} = 0b11010101010;
154let hasNewValue = 1;
155let opNewValue = 0;
156let prefersSlot3 = 1;
157let Defs = [USR_OVF];
158}
159def A2_addh_l16_hl : HInst<
160(outs IntRegs:$Rd32),
161(ins IntRegs:$Rt32, IntRegs:$Rs32),
162"$Rd32 = add($Rt32.l,$Rs32.h)",
163tc_f34c1c21, TypeALU64>, Enc_bd6011 {
164let Inst{7-5} = 0b010;
165let Inst{13-13} = 0b0;
166let Inst{31-21} = 0b11010101000;
167let hasNewValue = 1;
168let opNewValue = 0;
169let prefersSlot3 = 1;
170}
171def A2_addh_l16_ll : HInst<
172(outs IntRegs:$Rd32),
173(ins IntRegs:$Rt32, IntRegs:$Rs32),
174"$Rd32 = add($Rt32.l,$Rs32.l)",
175tc_f34c1c21, TypeALU64>, Enc_bd6011 {
176let Inst{7-5} = 0b000;
177let Inst{13-13} = 0b0;
178let Inst{31-21} = 0b11010101000;
179let hasNewValue = 1;
180let opNewValue = 0;
181let prefersSlot3 = 1;
182}
183def A2_addh_l16_sat_hl : HInst<
184(outs IntRegs:$Rd32),
185(ins IntRegs:$Rt32, IntRegs:$Rs32),
186"$Rd32 = add($Rt32.l,$Rs32.h):sat",
187tc_8a825db2, TypeALU64>, Enc_bd6011 {
188let Inst{7-5} = 0b110;
189let Inst{13-13} = 0b0;
190let Inst{31-21} = 0b11010101000;
191let hasNewValue = 1;
192let opNewValue = 0;
193let prefersSlot3 = 1;
194let Defs = [USR_OVF];
195}
196def A2_addh_l16_sat_ll : HInst<
197(outs IntRegs:$Rd32),
198(ins IntRegs:$Rt32, IntRegs:$Rs32),
199"$Rd32 = add($Rt32.l,$Rs32.l):sat",
200tc_8a825db2, TypeALU64>, Enc_bd6011 {
201let Inst{7-5} = 0b100;
202let Inst{13-13} = 0b0;
203let Inst{31-21} = 0b11010101000;
204let hasNewValue = 1;
205let opNewValue = 0;
206let prefersSlot3 = 1;
207let Defs = [USR_OVF];
208}
209def A2_addi : HInst<
210(outs IntRegs:$Rd32),
211(ins IntRegs:$Rs32, s32_0Imm:$Ii),
212"$Rd32 = add($Rs32,#$Ii)",
213tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
214let Inst{31-28} = 0b1011;
215let hasNewValue = 1;
216let opNewValue = 0;
217let BaseOpcode = "A2_addi";
218let CextOpcode = "A2_add";
219let InputType = "imm";
220let isAdd = 1;
221let isPredicable = 1;
222let isExtendable = 1;
223let opExtendable = 2;
224let isExtentSigned = 1;
225let opExtentBits = 16;
226let opExtentAlign = 0;
227}
228def A2_addp : HInst<
229(outs DoubleRegs:$Rdd32),
230(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
231"$Rdd32 = add($Rss32,$Rtt32)",
232tc_5da50c4b, TypeALU64>, Enc_a56825 {
233let Inst{7-5} = 0b111;
234let Inst{13-13} = 0b0;
235let Inst{31-21} = 0b11010011000;
236let isAdd = 1;
237let isCommutable = 1;
238}
239def A2_addpsat : HInst<
240(outs DoubleRegs:$Rdd32),
241(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
242"$Rdd32 = add($Rss32,$Rtt32):sat",
243tc_8a825db2, TypeALU64>, Enc_a56825 {
244let Inst{7-5} = 0b101;
245let Inst{13-13} = 0b0;
246let Inst{31-21} = 0b11010011011;
247let prefersSlot3 = 1;
248let Defs = [USR_OVF];
249let isCommutable = 1;
250}
251def A2_addsat : HInst<
252(outs IntRegs:$Rd32),
253(ins IntRegs:$Rs32, IntRegs:$Rt32),
254"$Rd32 = add($Rs32,$Rt32):sat",
255tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
256let Inst{7-5} = 0b000;
257let Inst{13-13} = 0b0;
258let Inst{31-21} = 0b11110110010;
259let hasNewValue = 1;
260let opNewValue = 0;
261let prefersSlot3 = 1;
262let Defs = [USR_OVF];
263let InputType = "reg";
264let isCommutable = 1;
265}
266def A2_addsp : HInst<
267(outs DoubleRegs:$Rdd32),
268(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
269"$Rdd32 = add($Rs32,$Rtt32)",
270tc_01d44cb2, TypeALU64> {
271let isPseudo = 1;
272}
273def A2_addsph : HInst<
274(outs DoubleRegs:$Rdd32),
275(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
276"$Rdd32 = add($Rss32,$Rtt32):raw:hi",
277tc_01d44cb2, TypeALU64>, Enc_a56825 {
278let Inst{7-5} = 0b111;
279let Inst{13-13} = 0b0;
280let Inst{31-21} = 0b11010011011;
281let prefersSlot3 = 1;
282}
283def A2_addspl : HInst<
284(outs DoubleRegs:$Rdd32),
285(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
286"$Rdd32 = add($Rss32,$Rtt32):raw:lo",
287tc_01d44cb2, TypeALU64>, Enc_a56825 {
288let Inst{7-5} = 0b110;
289let Inst{13-13} = 0b0;
290let Inst{31-21} = 0b11010011011;
291let prefersSlot3 = 1;
292}
293def A2_and : HInst<
294(outs IntRegs:$Rd32),
295(ins IntRegs:$Rs32, IntRegs:$Rt32),
296"$Rd32 = and($Rs32,$Rt32)",
297tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
298let Inst{7-5} = 0b000;
299let Inst{13-13} = 0b0;
300let Inst{31-21} = 0b11110001000;
301let hasNewValue = 1;
302let opNewValue = 0;
303let BaseOpcode = "A2_and";
304let CextOpcode = "A2_and";
305let InputType = "reg";
306let isCommutable = 1;
307let isPredicable = 1;
308}
309def A2_andir : HInst<
310(outs IntRegs:$Rd32),
311(ins IntRegs:$Rs32, s32_0Imm:$Ii),
312"$Rd32 = and($Rs32,#$Ii)",
313tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
314let Inst{31-22} = 0b0111011000;
315let hasNewValue = 1;
316let opNewValue = 0;
317let CextOpcode = "A2_and";
318let InputType = "imm";
319let isExtendable = 1;
320let opExtendable = 2;
321let isExtentSigned = 1;
322let opExtentBits = 10;
323let opExtentAlign = 0;
324}
325def A2_andp : HInst<
326(outs DoubleRegs:$Rdd32),
327(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
328"$Rdd32 = and($Rss32,$Rtt32)",
329tc_5da50c4b, TypeALU64>, Enc_a56825 {
330let Inst{7-5} = 0b000;
331let Inst{13-13} = 0b0;
332let Inst{31-21} = 0b11010011111;
333let isCommutable = 1;
334}
335def A2_aslh : HInst<
336(outs IntRegs:$Rd32),
337(ins IntRegs:$Rs32),
338"$Rd32 = aslh($Rs32)",
339tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
340let Inst{13-5} = 0b000000000;
341let Inst{31-21} = 0b01110000000;
342let hasNewValue = 1;
343let opNewValue = 0;
344let BaseOpcode = "A2_aslh";
345let isPredicable = 1;
346}
347def A2_asrh : HInst<
348(outs IntRegs:$Rd32),
349(ins IntRegs:$Rs32),
350"$Rd32 = asrh($Rs32)",
351tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
352let Inst{13-5} = 0b000000000;
353let Inst{31-21} = 0b01110000001;
354let hasNewValue = 1;
355let opNewValue = 0;
356let BaseOpcode = "A2_asrh";
357let isPredicable = 1;
358}
359def A2_combine_hh : HInst<
360(outs IntRegs:$Rd32),
361(ins IntRegs:$Rt32, IntRegs:$Rs32),
362"$Rd32 = combine($Rt32.h,$Rs32.h)",
363tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
364let Inst{7-5} = 0b000;
365let Inst{13-13} = 0b0;
366let Inst{31-21} = 0b11110011100;
367let hasNewValue = 1;
368let opNewValue = 0;
369let InputType = "reg";
370}
371def A2_combine_hl : HInst<
372(outs IntRegs:$Rd32),
373(ins IntRegs:$Rt32, IntRegs:$Rs32),
374"$Rd32 = combine($Rt32.h,$Rs32.l)",
375tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
376let Inst{7-5} = 0b000;
377let Inst{13-13} = 0b0;
378let Inst{31-21} = 0b11110011101;
379let hasNewValue = 1;
380let opNewValue = 0;
381let InputType = "reg";
382}
383def A2_combine_lh : HInst<
384(outs IntRegs:$Rd32),
385(ins IntRegs:$Rt32, IntRegs:$Rs32),
386"$Rd32 = combine($Rt32.l,$Rs32.h)",
387tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
388let Inst{7-5} = 0b000;
389let Inst{13-13} = 0b0;
390let Inst{31-21} = 0b11110011110;
391let hasNewValue = 1;
392let opNewValue = 0;
393let InputType = "reg";
394}
395def A2_combine_ll : HInst<
396(outs IntRegs:$Rd32),
397(ins IntRegs:$Rt32, IntRegs:$Rs32),
398"$Rd32 = combine($Rt32.l,$Rs32.l)",
399tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
400let Inst{7-5} = 0b000;
401let Inst{13-13} = 0b0;
402let Inst{31-21} = 0b11110011111;
403let hasNewValue = 1;
404let opNewValue = 0;
405let InputType = "reg";
406}
407def A2_combineii : HInst<
408(outs DoubleRegs:$Rdd32),
409(ins s32_0Imm:$Ii, s8_0Imm:$II),
410"$Rdd32 = combine(#$Ii,#$II)",
411tc_713b66bf, TypeALU32_2op>, Enc_18c338 {
412let Inst{31-23} = 0b011111000;
413let isAsCheapAsAMove = 1;
414let isMoveImm = 1;
415let isReMaterializable = 1;
416let isExtendable = 1;
417let opExtendable = 1;
418let isExtentSigned = 1;
419let opExtentBits = 8;
420let opExtentAlign = 0;
421}
422def A2_combinew : HInst<
423(outs DoubleRegs:$Rdd32),
424(ins IntRegs:$Rs32, IntRegs:$Rt32),
425"$Rdd32 = combine($Rs32,$Rt32)",
426tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel {
427let Inst{7-5} = 0b000;
428let Inst{13-13} = 0b0;
429let Inst{31-21} = 0b11110101000;
430let BaseOpcode = "A2_combinew";
431let InputType = "reg";
432let isPredicable = 1;
433}
434def A2_max : HInst<
435(outs IntRegs:$Rd32),
436(ins IntRegs:$Rs32, IntRegs:$Rt32),
437"$Rd32 = max($Rs32,$Rt32)",
438tc_8a825db2, TypeALU64>, Enc_5ab2be {
439let Inst{7-5} = 0b000;
440let Inst{13-13} = 0b0;
441let Inst{31-21} = 0b11010101110;
442let hasNewValue = 1;
443let opNewValue = 0;
444let prefersSlot3 = 1;
445}
446def A2_maxp : HInst<
447(outs DoubleRegs:$Rdd32),
448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
449"$Rdd32 = max($Rss32,$Rtt32)",
450tc_8a825db2, TypeALU64>, Enc_a56825 {
451let Inst{7-5} = 0b100;
452let Inst{13-13} = 0b0;
453let Inst{31-21} = 0b11010011110;
454let prefersSlot3 = 1;
455}
456def A2_maxu : HInst<
457(outs IntRegs:$Rd32),
458(ins IntRegs:$Rs32, IntRegs:$Rt32),
459"$Rd32 = maxu($Rs32,$Rt32)",
460tc_8a825db2, TypeALU64>, Enc_5ab2be {
461let Inst{7-5} = 0b100;
462let Inst{13-13} = 0b0;
463let Inst{31-21} = 0b11010101110;
464let hasNewValue = 1;
465let opNewValue = 0;
466let prefersSlot3 = 1;
467}
468def A2_maxup : HInst<
469(outs DoubleRegs:$Rdd32),
470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
471"$Rdd32 = maxu($Rss32,$Rtt32)",
472tc_8a825db2, TypeALU64>, Enc_a56825 {
473let Inst{7-5} = 0b101;
474let Inst{13-13} = 0b0;
475let Inst{31-21} = 0b11010011110;
476let prefersSlot3 = 1;
477}
478def A2_min : HInst<
479(outs IntRegs:$Rd32),
480(ins IntRegs:$Rt32, IntRegs:$Rs32),
481"$Rd32 = min($Rt32,$Rs32)",
482tc_8a825db2, TypeALU64>, Enc_bd6011 {
483let Inst{7-5} = 0b000;
484let Inst{13-13} = 0b0;
485let Inst{31-21} = 0b11010101101;
486let hasNewValue = 1;
487let opNewValue = 0;
488let prefersSlot3 = 1;
489}
490def A2_minp : HInst<
491(outs DoubleRegs:$Rdd32),
492(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
493"$Rdd32 = min($Rtt32,$Rss32)",
494tc_8a825db2, TypeALU64>, Enc_ea23e4 {
495let Inst{7-5} = 0b110;
496let Inst{13-13} = 0b0;
497let Inst{31-21} = 0b11010011101;
498let prefersSlot3 = 1;
499}
500def A2_minu : HInst<
501(outs IntRegs:$Rd32),
502(ins IntRegs:$Rt32, IntRegs:$Rs32),
503"$Rd32 = minu($Rt32,$Rs32)",
504tc_8a825db2, TypeALU64>, Enc_bd6011 {
505let Inst{7-5} = 0b100;
506let Inst{13-13} = 0b0;
507let Inst{31-21} = 0b11010101101;
508let hasNewValue = 1;
509let opNewValue = 0;
510let prefersSlot3 = 1;
511}
512def A2_minup : HInst<
513(outs DoubleRegs:$Rdd32),
514(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
515"$Rdd32 = minu($Rtt32,$Rss32)",
516tc_8a825db2, TypeALU64>, Enc_ea23e4 {
517let Inst{7-5} = 0b111;
518let Inst{13-13} = 0b0;
519let Inst{31-21} = 0b11010011101;
520let prefersSlot3 = 1;
521}
522def A2_neg : HInst<
523(outs IntRegs:$Rd32),
524(ins IntRegs:$Rs32),
525"$Rd32 = neg($Rs32)",
526tc_c57d9f39, TypeALU32_2op> {
527let hasNewValue = 1;
528let opNewValue = 0;
529let isPseudo = 1;
530let isCodeGenOnly = 1;
531}
532def A2_negp : HInst<
533(outs DoubleRegs:$Rdd32),
534(ins DoubleRegs:$Rss32),
535"$Rdd32 = neg($Rss32)",
536tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
537let Inst{13-5} = 0b000000101;
538let Inst{31-21} = 0b10000000100;
539}
540def A2_negsat : HInst<
541(outs IntRegs:$Rd32),
542(ins IntRegs:$Rs32),
543"$Rd32 = neg($Rs32):sat",
544tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
545let Inst{13-5} = 0b000000110;
546let Inst{31-21} = 0b10001100100;
547let hasNewValue = 1;
548let opNewValue = 0;
549let prefersSlot3 = 1;
550let Defs = [USR_OVF];
551}
552def A2_nop : HInst<
553(outs),
554(ins),
555"nop",
556tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 {
557let Inst{13-0} = 0b00000000000000;
558let Inst{31-16} = 0b0111111100000000;
559}
560def A2_not : HInst<
561(outs IntRegs:$Rd32),
562(ins IntRegs:$Rs32),
563"$Rd32 = not($Rs32)",
564tc_c57d9f39, TypeALU32_2op> {
565let hasNewValue = 1;
566let opNewValue = 0;
567let isPseudo = 1;
568let isCodeGenOnly = 1;
569}
570def A2_notp : HInst<
571(outs DoubleRegs:$Rdd32),
572(ins DoubleRegs:$Rss32),
573"$Rdd32 = not($Rss32)",
574tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
575let Inst{13-5} = 0b000000100;
576let Inst{31-21} = 0b10000000100;
577}
578def A2_or : HInst<
579(outs IntRegs:$Rd32),
580(ins IntRegs:$Rs32, IntRegs:$Rt32),
581"$Rd32 = or($Rs32,$Rt32)",
582tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
583let Inst{7-5} = 0b000;
584let Inst{13-13} = 0b0;
585let Inst{31-21} = 0b11110001001;
586let hasNewValue = 1;
587let opNewValue = 0;
588let BaseOpcode = "A2_or";
589let CextOpcode = "A2_or";
590let InputType = "reg";
591let isCommutable = 1;
592let isPredicable = 1;
593}
594def A2_orir : HInst<
595(outs IntRegs:$Rd32),
596(ins IntRegs:$Rs32, s32_0Imm:$Ii),
597"$Rd32 = or($Rs32,#$Ii)",
598tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
599let Inst{31-22} = 0b0111011010;
600let hasNewValue = 1;
601let opNewValue = 0;
602let CextOpcode = "A2_or";
603let InputType = "imm";
604let isExtendable = 1;
605let opExtendable = 2;
606let isExtentSigned = 1;
607let opExtentBits = 10;
608let opExtentAlign = 0;
609}
610def A2_orp : HInst<
611(outs DoubleRegs:$Rdd32),
612(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
613"$Rdd32 = or($Rss32,$Rtt32)",
614tc_5da50c4b, TypeALU64>, Enc_a56825 {
615let Inst{7-5} = 0b010;
616let Inst{13-13} = 0b0;
617let Inst{31-21} = 0b11010011111;
618let isCommutable = 1;
619}
620def A2_paddf : HInst<
621(outs IntRegs:$Rd32),
622(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
623"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
624tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
625let Inst{7-7} = 0b1;
626let Inst{13-13} = 0b0;
627let Inst{31-21} = 0b11111011000;
628let isPredicated = 1;
629let isPredicatedFalse = 1;
630let hasNewValue = 1;
631let opNewValue = 0;
632let BaseOpcode = "A2_add";
633let CextOpcode = "A2_add";
634let InputType = "reg";
635}
636def A2_paddfnew : HInst<
637(outs IntRegs:$Rd32),
638(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
639"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
640tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
641let Inst{7-7} = 0b1;
642let Inst{13-13} = 0b1;
643let Inst{31-21} = 0b11111011000;
644let isPredicated = 1;
645let isPredicatedFalse = 1;
646let hasNewValue = 1;
647let opNewValue = 0;
648let isPredicatedNew = 1;
649let BaseOpcode = "A2_add";
650let CextOpcode = "A2_add";
651let InputType = "reg";
652}
653def A2_paddif : HInst<
654(outs IntRegs:$Rd32),
655(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
656"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
657tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
658let Inst{13-13} = 0b0;
659let Inst{31-23} = 0b011101001;
660let isPredicated = 1;
661let isPredicatedFalse = 1;
662let hasNewValue = 1;
663let opNewValue = 0;
664let BaseOpcode = "A2_addi";
665let CextOpcode = "A2_add";
666let InputType = "imm";
667let isExtendable = 1;
668let opExtendable = 3;
669let isExtentSigned = 1;
670let opExtentBits = 8;
671let opExtentAlign = 0;
672}
673def A2_paddifnew : HInst<
674(outs IntRegs:$Rd32),
675(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
676"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
677tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
678let Inst{13-13} = 0b1;
679let Inst{31-23} = 0b011101001;
680let isPredicated = 1;
681let isPredicatedFalse = 1;
682let hasNewValue = 1;
683let opNewValue = 0;
684let isPredicatedNew = 1;
685let BaseOpcode = "A2_addi";
686let CextOpcode = "A2_add";
687let InputType = "imm";
688let isExtendable = 1;
689let opExtendable = 3;
690let isExtentSigned = 1;
691let opExtentBits = 8;
692let opExtentAlign = 0;
693}
694def A2_paddit : HInst<
695(outs IntRegs:$Rd32),
696(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
697"if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
698tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
699let Inst{13-13} = 0b0;
700let Inst{31-23} = 0b011101000;
701let isPredicated = 1;
702let hasNewValue = 1;
703let opNewValue = 0;
704let BaseOpcode = "A2_addi";
705let CextOpcode = "A2_add";
706let InputType = "imm";
707let isExtendable = 1;
708let opExtendable = 3;
709let isExtentSigned = 1;
710let opExtentBits = 8;
711let opExtentAlign = 0;
712}
713def A2_padditnew : HInst<
714(outs IntRegs:$Rd32),
715(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
716"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
717tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
718let Inst{13-13} = 0b1;
719let Inst{31-23} = 0b011101000;
720let isPredicated = 1;
721let hasNewValue = 1;
722let opNewValue = 0;
723let isPredicatedNew = 1;
724let BaseOpcode = "A2_addi";
725let CextOpcode = "A2_add";
726let InputType = "imm";
727let isExtendable = 1;
728let opExtendable = 3;
729let isExtentSigned = 1;
730let opExtentBits = 8;
731let opExtentAlign = 0;
732}
733def A2_paddt : HInst<
734(outs IntRegs:$Rd32),
735(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
736"if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
737tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
738let Inst{7-7} = 0b0;
739let Inst{13-13} = 0b0;
740let Inst{31-21} = 0b11111011000;
741let isPredicated = 1;
742let hasNewValue = 1;
743let opNewValue = 0;
744let BaseOpcode = "A2_add";
745let CextOpcode = "A2_add";
746let InputType = "reg";
747}
748def A2_paddtnew : HInst<
749(outs IntRegs:$Rd32),
750(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
751"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
752tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
753let Inst{7-7} = 0b0;
754let Inst{13-13} = 0b1;
755let Inst{31-21} = 0b11111011000;
756let isPredicated = 1;
757let hasNewValue = 1;
758let opNewValue = 0;
759let isPredicatedNew = 1;
760let BaseOpcode = "A2_add";
761let CextOpcode = "A2_add";
762let InputType = "reg";
763}
764def A2_pandf : HInst<
765(outs IntRegs:$Rd32),
766(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
767"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
768tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
769let Inst{7-7} = 0b1;
770let Inst{13-13} = 0b0;
771let Inst{31-21} = 0b11111001000;
772let isPredicated = 1;
773let isPredicatedFalse = 1;
774let hasNewValue = 1;
775let opNewValue = 0;
776let BaseOpcode = "A2_and";
777}
778def A2_pandfnew : HInst<
779(outs IntRegs:$Rd32),
780(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
781"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
782tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
783let Inst{7-7} = 0b1;
784let Inst{13-13} = 0b1;
785let Inst{31-21} = 0b11111001000;
786let isPredicated = 1;
787let isPredicatedFalse = 1;
788let hasNewValue = 1;
789let opNewValue = 0;
790let isPredicatedNew = 1;
791let BaseOpcode = "A2_and";
792}
793def A2_pandt : HInst<
794(outs IntRegs:$Rd32),
795(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
796"if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
797tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
798let Inst{7-7} = 0b0;
799let Inst{13-13} = 0b0;
800let Inst{31-21} = 0b11111001000;
801let isPredicated = 1;
802let hasNewValue = 1;
803let opNewValue = 0;
804let BaseOpcode = "A2_and";
805}
806def A2_pandtnew : HInst<
807(outs IntRegs:$Rd32),
808(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
809"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
810tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
811let Inst{7-7} = 0b0;
812let Inst{13-13} = 0b1;
813let Inst{31-21} = 0b11111001000;
814let isPredicated = 1;
815let hasNewValue = 1;
816let opNewValue = 0;
817let isPredicatedNew = 1;
818let BaseOpcode = "A2_and";
819}
820def A2_porf : HInst<
821(outs IntRegs:$Rd32),
822(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
823"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
824tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
825let Inst{7-7} = 0b1;
826let Inst{13-13} = 0b0;
827let Inst{31-21} = 0b11111001001;
828let isPredicated = 1;
829let isPredicatedFalse = 1;
830let hasNewValue = 1;
831let opNewValue = 0;
832let BaseOpcode = "A2_or";
833}
834def A2_porfnew : HInst<
835(outs IntRegs:$Rd32),
836(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
837"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
838tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
839let Inst{7-7} = 0b1;
840let Inst{13-13} = 0b1;
841let Inst{31-21} = 0b11111001001;
842let isPredicated = 1;
843let isPredicatedFalse = 1;
844let hasNewValue = 1;
845let opNewValue = 0;
846let isPredicatedNew = 1;
847let BaseOpcode = "A2_or";
848}
849def A2_port : HInst<
850(outs IntRegs:$Rd32),
851(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
852"if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
853tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
854let Inst{7-7} = 0b0;
855let Inst{13-13} = 0b0;
856let Inst{31-21} = 0b11111001001;
857let isPredicated = 1;
858let hasNewValue = 1;
859let opNewValue = 0;
860let BaseOpcode = "A2_or";
861}
862def A2_portnew : HInst<
863(outs IntRegs:$Rd32),
864(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
865"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
866tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
867let Inst{7-7} = 0b0;
868let Inst{13-13} = 0b1;
869let Inst{31-21} = 0b11111001001;
870let isPredicated = 1;
871let hasNewValue = 1;
872let opNewValue = 0;
873let isPredicatedNew = 1;
874let BaseOpcode = "A2_or";
875}
876def A2_psubf : HInst<
877(outs IntRegs:$Rd32),
878(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
879"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
880tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
881let Inst{7-7} = 0b1;
882let Inst{13-13} = 0b0;
883let Inst{31-21} = 0b11111011001;
884let isPredicated = 1;
885let isPredicatedFalse = 1;
886let hasNewValue = 1;
887let opNewValue = 0;
888let BaseOpcode = "A2_sub";
889}
890def A2_psubfnew : HInst<
891(outs IntRegs:$Rd32),
892(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
893"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
894tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
895let Inst{7-7} = 0b1;
896let Inst{13-13} = 0b1;
897let Inst{31-21} = 0b11111011001;
898let isPredicated = 1;
899let isPredicatedFalse = 1;
900let hasNewValue = 1;
901let opNewValue = 0;
902let isPredicatedNew = 1;
903let BaseOpcode = "A2_sub";
904}
905def A2_psubt : HInst<
906(outs IntRegs:$Rd32),
907(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
908"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
909tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
910let Inst{7-7} = 0b0;
911let Inst{13-13} = 0b0;
912let Inst{31-21} = 0b11111011001;
913let isPredicated = 1;
914let hasNewValue = 1;
915let opNewValue = 0;
916let BaseOpcode = "A2_sub";
917}
918def A2_psubtnew : HInst<
919(outs IntRegs:$Rd32),
920(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
921"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
922tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
923let Inst{7-7} = 0b0;
924let Inst{13-13} = 0b1;
925let Inst{31-21} = 0b11111011001;
926let isPredicated = 1;
927let hasNewValue = 1;
928let opNewValue = 0;
929let isPredicatedNew = 1;
930let BaseOpcode = "A2_sub";
931}
932def A2_pxorf : HInst<
933(outs IntRegs:$Rd32),
934(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
935"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
936tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
937let Inst{7-7} = 0b1;
938let Inst{13-13} = 0b0;
939let Inst{31-21} = 0b11111001011;
940let isPredicated = 1;
941let isPredicatedFalse = 1;
942let hasNewValue = 1;
943let opNewValue = 0;
944let BaseOpcode = "A2_xor";
945}
946def A2_pxorfnew : HInst<
947(outs IntRegs:$Rd32),
948(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
949"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
950tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
951let Inst{7-7} = 0b1;
952let Inst{13-13} = 0b1;
953let Inst{31-21} = 0b11111001011;
954let isPredicated = 1;
955let isPredicatedFalse = 1;
956let hasNewValue = 1;
957let opNewValue = 0;
958let isPredicatedNew = 1;
959let BaseOpcode = "A2_xor";
960}
961def A2_pxort : HInst<
962(outs IntRegs:$Rd32),
963(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
964"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
965tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
966let Inst{7-7} = 0b0;
967let Inst{13-13} = 0b0;
968let Inst{31-21} = 0b11111001011;
969let isPredicated = 1;
970let hasNewValue = 1;
971let opNewValue = 0;
972let BaseOpcode = "A2_xor";
973}
974def A2_pxortnew : HInst<
975(outs IntRegs:$Rd32),
976(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
977"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
978tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
979let Inst{7-7} = 0b0;
980let Inst{13-13} = 0b1;
981let Inst{31-21} = 0b11111001011;
982let isPredicated = 1;
983let hasNewValue = 1;
984let opNewValue = 0;
985let isPredicatedNew = 1;
986let BaseOpcode = "A2_xor";
987}
988def A2_roundsat : HInst<
989(outs IntRegs:$Rd32),
990(ins DoubleRegs:$Rss32),
991"$Rd32 = round($Rss32):sat",
992tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
993let Inst{13-5} = 0b000000001;
994let Inst{31-21} = 0b10001000110;
995let hasNewValue = 1;
996let opNewValue = 0;
997let prefersSlot3 = 1;
998let Defs = [USR_OVF];
999}
1000def A2_sat : HInst<
1001(outs IntRegs:$Rd32),
1002(ins DoubleRegs:$Rss32),
1003"$Rd32 = sat($Rss32)",
1004tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
1005let Inst{13-5} = 0b000000000;
1006let Inst{31-21} = 0b10001000110;
1007let hasNewValue = 1;
1008let opNewValue = 0;
1009let Defs = [USR_OVF];
1010}
1011def A2_satb : HInst<
1012(outs IntRegs:$Rd32),
1013(ins IntRegs:$Rs32),
1014"$Rd32 = satb($Rs32)",
1015tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1016let Inst{13-5} = 0b000000111;
1017let Inst{31-21} = 0b10001100110;
1018let hasNewValue = 1;
1019let opNewValue = 0;
1020let Defs = [USR_OVF];
1021}
1022def A2_sath : HInst<
1023(outs IntRegs:$Rd32),
1024(ins IntRegs:$Rs32),
1025"$Rd32 = sath($Rs32)",
1026tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1027let Inst{13-5} = 0b000000100;
1028let Inst{31-21} = 0b10001100110;
1029let hasNewValue = 1;
1030let opNewValue = 0;
1031let Defs = [USR_OVF];
1032}
1033def A2_satub : HInst<
1034(outs IntRegs:$Rd32),
1035(ins IntRegs:$Rs32),
1036"$Rd32 = satub($Rs32)",
1037tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1038let Inst{13-5} = 0b000000110;
1039let Inst{31-21} = 0b10001100110;
1040let hasNewValue = 1;
1041let opNewValue = 0;
1042let Defs = [USR_OVF];
1043}
1044def A2_satuh : HInst<
1045(outs IntRegs:$Rd32),
1046(ins IntRegs:$Rs32),
1047"$Rd32 = satuh($Rs32)",
1048tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1049let Inst{13-5} = 0b000000101;
1050let Inst{31-21} = 0b10001100110;
1051let hasNewValue = 1;
1052let opNewValue = 0;
1053let Defs = [USR_OVF];
1054}
1055def A2_sub : HInst<
1056(outs IntRegs:$Rd32),
1057(ins IntRegs:$Rt32, IntRegs:$Rs32),
1058"$Rd32 = sub($Rt32,$Rs32)",
1059tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
1060let Inst{7-5} = 0b000;
1061let Inst{13-13} = 0b0;
1062let Inst{31-21} = 0b11110011001;
1063let hasNewValue = 1;
1064let opNewValue = 0;
1065let BaseOpcode = "A2_sub";
1066let CextOpcode = "A2_sub";
1067let InputType = "reg";
1068let isPredicable = 1;
1069}
1070def A2_subh_h16_hh : HInst<
1071(outs IntRegs:$Rd32),
1072(ins IntRegs:$Rt32, IntRegs:$Rs32),
1073"$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
1074tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1075let Inst{7-5} = 0b011;
1076let Inst{13-13} = 0b0;
1077let Inst{31-21} = 0b11010101011;
1078let hasNewValue = 1;
1079let opNewValue = 0;
1080let prefersSlot3 = 1;
1081}
1082def A2_subh_h16_hl : HInst<
1083(outs IntRegs:$Rd32),
1084(ins IntRegs:$Rt32, IntRegs:$Rs32),
1085"$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
1086tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1087let Inst{7-5} = 0b010;
1088let Inst{13-13} = 0b0;
1089let Inst{31-21} = 0b11010101011;
1090let hasNewValue = 1;
1091let opNewValue = 0;
1092let prefersSlot3 = 1;
1093}
1094def A2_subh_h16_lh : HInst<
1095(outs IntRegs:$Rd32),
1096(ins IntRegs:$Rt32, IntRegs:$Rs32),
1097"$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
1098tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1099let Inst{7-5} = 0b001;
1100let Inst{13-13} = 0b0;
1101let Inst{31-21} = 0b11010101011;
1102let hasNewValue = 1;
1103let opNewValue = 0;
1104let prefersSlot3 = 1;
1105}
1106def A2_subh_h16_ll : HInst<
1107(outs IntRegs:$Rd32),
1108(ins IntRegs:$Rt32, IntRegs:$Rs32),
1109"$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
1110tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1111let Inst{7-5} = 0b000;
1112let Inst{13-13} = 0b0;
1113let Inst{31-21} = 0b11010101011;
1114let hasNewValue = 1;
1115let opNewValue = 0;
1116let prefersSlot3 = 1;
1117}
1118def A2_subh_h16_sat_hh : HInst<
1119(outs IntRegs:$Rd32),
1120(ins IntRegs:$Rt32, IntRegs:$Rs32),
1121"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
1122tc_8a825db2, TypeALU64>, Enc_bd6011 {
1123let Inst{7-5} = 0b111;
1124let Inst{13-13} = 0b0;
1125let Inst{31-21} = 0b11010101011;
1126let hasNewValue = 1;
1127let opNewValue = 0;
1128let prefersSlot3 = 1;
1129let Defs = [USR_OVF];
1130}
1131def A2_subh_h16_sat_hl : HInst<
1132(outs IntRegs:$Rd32),
1133(ins IntRegs:$Rt32, IntRegs:$Rs32),
1134"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
1135tc_8a825db2, TypeALU64>, Enc_bd6011 {
1136let Inst{7-5} = 0b110;
1137let Inst{13-13} = 0b0;
1138let Inst{31-21} = 0b11010101011;
1139let hasNewValue = 1;
1140let opNewValue = 0;
1141let prefersSlot3 = 1;
1142let Defs = [USR_OVF];
1143}
1144def A2_subh_h16_sat_lh : HInst<
1145(outs IntRegs:$Rd32),
1146(ins IntRegs:$Rt32, IntRegs:$Rs32),
1147"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
1148tc_8a825db2, TypeALU64>, Enc_bd6011 {
1149let Inst{7-5} = 0b101;
1150let Inst{13-13} = 0b0;
1151let Inst{31-21} = 0b11010101011;
1152let hasNewValue = 1;
1153let opNewValue = 0;
1154let prefersSlot3 = 1;
1155let Defs = [USR_OVF];
1156}
1157def A2_subh_h16_sat_ll : HInst<
1158(outs IntRegs:$Rd32),
1159(ins IntRegs:$Rt32, IntRegs:$Rs32),
1160"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
1161tc_8a825db2, TypeALU64>, Enc_bd6011 {
1162let Inst{7-5} = 0b100;
1163let Inst{13-13} = 0b0;
1164let Inst{31-21} = 0b11010101011;
1165let hasNewValue = 1;
1166let opNewValue = 0;
1167let prefersSlot3 = 1;
1168let Defs = [USR_OVF];
1169}
1170def A2_subh_l16_hl : HInst<
1171(outs IntRegs:$Rd32),
1172(ins IntRegs:$Rt32, IntRegs:$Rs32),
1173"$Rd32 = sub($Rt32.l,$Rs32.h)",
1174tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1175let Inst{7-5} = 0b010;
1176let Inst{13-13} = 0b0;
1177let Inst{31-21} = 0b11010101001;
1178let hasNewValue = 1;
1179let opNewValue = 0;
1180let prefersSlot3 = 1;
1181}
1182def A2_subh_l16_ll : HInst<
1183(outs IntRegs:$Rd32),
1184(ins IntRegs:$Rt32, IntRegs:$Rs32),
1185"$Rd32 = sub($Rt32.l,$Rs32.l)",
1186tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1187let Inst{7-5} = 0b000;
1188let Inst{13-13} = 0b0;
1189let Inst{31-21} = 0b11010101001;
1190let hasNewValue = 1;
1191let opNewValue = 0;
1192let prefersSlot3 = 1;
1193}
1194def A2_subh_l16_sat_hl : HInst<
1195(outs IntRegs:$Rd32),
1196(ins IntRegs:$Rt32, IntRegs:$Rs32),
1197"$Rd32 = sub($Rt32.l,$Rs32.h):sat",
1198tc_8a825db2, TypeALU64>, Enc_bd6011 {
1199let Inst{7-5} = 0b110;
1200let Inst{13-13} = 0b0;
1201let Inst{31-21} = 0b11010101001;
1202let hasNewValue = 1;
1203let opNewValue = 0;
1204let prefersSlot3 = 1;
1205let Defs = [USR_OVF];
1206}
1207def A2_subh_l16_sat_ll : HInst<
1208(outs IntRegs:$Rd32),
1209(ins IntRegs:$Rt32, IntRegs:$Rs32),
1210"$Rd32 = sub($Rt32.l,$Rs32.l):sat",
1211tc_8a825db2, TypeALU64>, Enc_bd6011 {
1212let Inst{7-5} = 0b100;
1213let Inst{13-13} = 0b0;
1214let Inst{31-21} = 0b11010101001;
1215let hasNewValue = 1;
1216let opNewValue = 0;
1217let prefersSlot3 = 1;
1218let Defs = [USR_OVF];
1219}
1220def A2_subp : HInst<
1221(outs DoubleRegs:$Rdd32),
1222(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1223"$Rdd32 = sub($Rtt32,$Rss32)",
1224tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
1225let Inst{7-5} = 0b111;
1226let Inst{13-13} = 0b0;
1227let Inst{31-21} = 0b11010011001;
1228}
1229def A2_subri : HInst<
1230(outs IntRegs:$Rd32),
1231(ins s32_0Imm:$Ii, IntRegs:$Rs32),
1232"$Rd32 = sub(#$Ii,$Rs32)",
1233tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
1234let Inst{31-22} = 0b0111011001;
1235let hasNewValue = 1;
1236let opNewValue = 0;
1237let CextOpcode = "A2_sub";
1238let InputType = "imm";
1239let isExtendable = 1;
1240let opExtendable = 1;
1241let isExtentSigned = 1;
1242let opExtentBits = 10;
1243let opExtentAlign = 0;
1244}
1245def A2_subsat : HInst<
1246(outs IntRegs:$Rd32),
1247(ins IntRegs:$Rt32, IntRegs:$Rs32),
1248"$Rd32 = sub($Rt32,$Rs32):sat",
1249tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1250let Inst{7-5} = 0b000;
1251let Inst{13-13} = 0b0;
1252let Inst{31-21} = 0b11110110110;
1253let hasNewValue = 1;
1254let opNewValue = 0;
1255let prefersSlot3 = 1;
1256let Defs = [USR_OVF];
1257let InputType = "reg";
1258}
1259def A2_svaddh : HInst<
1260(outs IntRegs:$Rd32),
1261(ins IntRegs:$Rs32, IntRegs:$Rt32),
1262"$Rd32 = vaddh($Rs32,$Rt32)",
1263tc_713b66bf, TypeALU32_3op>, Enc_5ab2be {
1264let Inst{7-5} = 0b000;
1265let Inst{13-13} = 0b0;
1266let Inst{31-21} = 0b11110110000;
1267let hasNewValue = 1;
1268let opNewValue = 0;
1269let InputType = "reg";
1270let isCommutable = 1;
1271}
1272def A2_svaddhs : HInst<
1273(outs IntRegs:$Rd32),
1274(ins IntRegs:$Rs32, IntRegs:$Rt32),
1275"$Rd32 = vaddh($Rs32,$Rt32):sat",
1276tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1277let Inst{7-5} = 0b000;
1278let Inst{13-13} = 0b0;
1279let Inst{31-21} = 0b11110110001;
1280let hasNewValue = 1;
1281let opNewValue = 0;
1282let prefersSlot3 = 1;
1283let Defs = [USR_OVF];
1284let InputType = "reg";
1285let isCommutable = 1;
1286}
1287def A2_svadduhs : HInst<
1288(outs IntRegs:$Rd32),
1289(ins IntRegs:$Rs32, IntRegs:$Rt32),
1290"$Rd32 = vadduh($Rs32,$Rt32):sat",
1291tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1292let Inst{7-5} = 0b000;
1293let Inst{13-13} = 0b0;
1294let Inst{31-21} = 0b11110110011;
1295let hasNewValue = 1;
1296let opNewValue = 0;
1297let prefersSlot3 = 1;
1298let Defs = [USR_OVF];
1299let InputType = "reg";
1300let isCommutable = 1;
1301}
1302def A2_svavgh : HInst<
1303(outs IntRegs:$Rd32),
1304(ins IntRegs:$Rs32, IntRegs:$Rt32),
1305"$Rd32 = vavgh($Rs32,$Rt32)",
1306tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be {
1307let Inst{7-5} = 0b000;
1308let Inst{13-13} = 0b0;
1309let Inst{31-21} = 0b11110111000;
1310let hasNewValue = 1;
1311let opNewValue = 0;
1312let prefersSlot3 = 1;
1313let InputType = "reg";
1314let isCommutable = 1;
1315}
1316def A2_svavghs : HInst<
1317(outs IntRegs:$Rd32),
1318(ins IntRegs:$Rs32, IntRegs:$Rt32),
1319"$Rd32 = vavgh($Rs32,$Rt32):rnd",
1320tc_84a7500d, TypeALU32_3op>, Enc_5ab2be {
1321let Inst{7-5} = 0b000;
1322let Inst{13-13} = 0b0;
1323let Inst{31-21} = 0b11110111001;
1324let hasNewValue = 1;
1325let opNewValue = 0;
1326let prefersSlot3 = 1;
1327let InputType = "reg";
1328let isCommutable = 1;
1329}
1330def A2_svnavgh : HInst<
1331(outs IntRegs:$Rd32),
1332(ins IntRegs:$Rt32, IntRegs:$Rs32),
1333"$Rd32 = vnavgh($Rt32,$Rs32)",
1334tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 {
1335let Inst{7-5} = 0b000;
1336let Inst{13-13} = 0b0;
1337let Inst{31-21} = 0b11110111011;
1338let hasNewValue = 1;
1339let opNewValue = 0;
1340let prefersSlot3 = 1;
1341let InputType = "reg";
1342}
1343def A2_svsubh : HInst<
1344(outs IntRegs:$Rd32),
1345(ins IntRegs:$Rt32, IntRegs:$Rs32),
1346"$Rd32 = vsubh($Rt32,$Rs32)",
1347tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
1348let Inst{7-5} = 0b000;
1349let Inst{13-13} = 0b0;
1350let Inst{31-21} = 0b11110110100;
1351let hasNewValue = 1;
1352let opNewValue = 0;
1353let InputType = "reg";
1354}
1355def A2_svsubhs : HInst<
1356(outs IntRegs:$Rd32),
1357(ins IntRegs:$Rt32, IntRegs:$Rs32),
1358"$Rd32 = vsubh($Rt32,$Rs32):sat",
1359tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1360let Inst{7-5} = 0b000;
1361let Inst{13-13} = 0b0;
1362let Inst{31-21} = 0b11110110101;
1363let hasNewValue = 1;
1364let opNewValue = 0;
1365let prefersSlot3 = 1;
1366let Defs = [USR_OVF];
1367let InputType = "reg";
1368}
1369def A2_svsubuhs : HInst<
1370(outs IntRegs:$Rd32),
1371(ins IntRegs:$Rt32, IntRegs:$Rs32),
1372"$Rd32 = vsubuh($Rt32,$Rs32):sat",
1373tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1374let Inst{7-5} = 0b000;
1375let Inst{13-13} = 0b0;
1376let Inst{31-21} = 0b11110110111;
1377let hasNewValue = 1;
1378let opNewValue = 0;
1379let prefersSlot3 = 1;
1380let Defs = [USR_OVF];
1381let InputType = "reg";
1382}
1383def A2_swiz : HInst<
1384(outs IntRegs:$Rd32),
1385(ins IntRegs:$Rs32),
1386"$Rd32 = swiz($Rs32)",
1387tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1388let Inst{13-5} = 0b000000111;
1389let Inst{31-21} = 0b10001100100;
1390let hasNewValue = 1;
1391let opNewValue = 0;
1392}
1393def A2_sxtb : HInst<
1394(outs IntRegs:$Rd32),
1395(ins IntRegs:$Rs32),
1396"$Rd32 = sxtb($Rs32)",
1397tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1398let Inst{13-5} = 0b000000000;
1399let Inst{31-21} = 0b01110000101;
1400let hasNewValue = 1;
1401let opNewValue = 0;
1402let BaseOpcode = "A2_sxtb";
1403let isPredicable = 1;
1404}
1405def A2_sxth : HInst<
1406(outs IntRegs:$Rd32),
1407(ins IntRegs:$Rs32),
1408"$Rd32 = sxth($Rs32)",
1409tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1410let Inst{13-5} = 0b000000000;
1411let Inst{31-21} = 0b01110000111;
1412let hasNewValue = 1;
1413let opNewValue = 0;
1414let BaseOpcode = "A2_sxth";
1415let isPredicable = 1;
1416}
1417def A2_sxtw : HInst<
1418(outs DoubleRegs:$Rdd32),
1419(ins IntRegs:$Rs32),
1420"$Rdd32 = sxtw($Rs32)",
1421tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
1422let Inst{13-5} = 0b000000000;
1423let Inst{31-21} = 0b10000100010;
1424}
1425def A2_tfr : HInst<
1426(outs IntRegs:$Rd32),
1427(ins IntRegs:$Rs32),
1428"$Rd32 = $Rs32",
1429tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1430let Inst{13-5} = 0b000000000;
1431let Inst{31-21} = 0b01110000011;
1432let hasNewValue = 1;
1433let opNewValue = 0;
1434let BaseOpcode = "A2_tfr";
1435let InputType = "reg";
1436let isPredicable = 1;
1437}
1438def A2_tfrcrr : HInst<
1439(outs IntRegs:$Rd32),
1440(ins CtrRegs:$Cs32),
1441"$Rd32 = $Cs32",
1442tc_7476d766, TypeCR>, Enc_0cb018 {
1443let Inst{13-5} = 0b000000000;
1444let Inst{31-21} = 0b01101010000;
1445let hasNewValue = 1;
1446let opNewValue = 0;
1447}
1448def A2_tfrf : HInst<
1449(outs IntRegs:$Rd32),
1450(ins PredRegs:$Pu4, IntRegs:$Rs32),
1451"if (!$Pu4) $Rd32 = $Rs32",
1452tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1453let isPredicated = 1;
1454let isPredicatedFalse = 1;
1455let hasNewValue = 1;
1456let opNewValue = 0;
1457let BaseOpcode = "A2_tfr";
1458let CextOpcode = "A2_tfr";
1459let InputType = "reg";
1460let isPseudo = 1;
1461let isCodeGenOnly = 1;
1462}
1463def A2_tfrfnew : HInst<
1464(outs IntRegs:$Rd32),
1465(ins PredRegs:$Pu4, IntRegs:$Rs32),
1466"if (!$Pu4.new) $Rd32 = $Rs32",
1467tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1468let isPredicated = 1;
1469let isPredicatedFalse = 1;
1470let hasNewValue = 1;
1471let opNewValue = 0;
1472let isPredicatedNew = 1;
1473let BaseOpcode = "A2_tfr";
1474let CextOpcode = "A2_tfr";
1475let InputType = "reg";
1476let isPseudo = 1;
1477let isCodeGenOnly = 1;
1478}
1479def A2_tfrih : HInst<
1480(outs IntRegs:$Rx32),
1481(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1482"$Rx32.h = #$Ii",
1483tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1484let Inst{21-21} = 0b1;
1485let Inst{31-24} = 0b01110010;
1486let hasNewValue = 1;
1487let opNewValue = 0;
1488let Constraints = "$Rx32 = $Rx32in";
1489}
1490def A2_tfril : HInst<
1491(outs IntRegs:$Rx32),
1492(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1493"$Rx32.l = #$Ii",
1494tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1495let Inst{21-21} = 0b1;
1496let Inst{31-24} = 0b01110001;
1497let hasNewValue = 1;
1498let opNewValue = 0;
1499let Constraints = "$Rx32 = $Rx32in";
1500}
1501def A2_tfrp : HInst<
1502(outs DoubleRegs:$Rdd32),
1503(ins DoubleRegs:$Rss32),
1504"$Rdd32 = $Rss32",
1505tc_713b66bf, TypeALU32_2op>, PredNewRel {
1506let BaseOpcode = "A2_tfrp";
1507let isPredicable = 1;
1508let isPseudo = 1;
1509}
1510def A2_tfrpf : HInst<
1511(outs DoubleRegs:$Rdd32),
1512(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1513"if (!$Pu4) $Rdd32 = $Rss32",
1514tc_713b66bf, TypeALU32_2op>, PredNewRel {
1515let isPredicated = 1;
1516let isPredicatedFalse = 1;
1517let BaseOpcode = "A2_tfrp";
1518let isPseudo = 1;
1519}
1520def A2_tfrpfnew : HInst<
1521(outs DoubleRegs:$Rdd32),
1522(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1523"if (!$Pu4.new) $Rdd32 = $Rss32",
1524tc_86173609, TypeALU32_2op>, PredNewRel {
1525let isPredicated = 1;
1526let isPredicatedFalse = 1;
1527let isPredicatedNew = 1;
1528let BaseOpcode = "A2_tfrp";
1529let isPseudo = 1;
1530}
1531def A2_tfrpi : HInst<
1532(outs DoubleRegs:$Rdd32),
1533(ins s8_0Imm:$Ii),
1534"$Rdd32 = #$Ii",
1535tc_713b66bf, TypeALU64> {
1536let isAsCheapAsAMove = 1;
1537let isMoveImm = 1;
1538let isReMaterializable = 1;
1539let isPseudo = 1;
1540}
1541def A2_tfrpt : HInst<
1542(outs DoubleRegs:$Rdd32),
1543(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1544"if ($Pu4) $Rdd32 = $Rss32",
1545tc_713b66bf, TypeALU32_2op>, PredNewRel {
1546let isPredicated = 1;
1547let BaseOpcode = "A2_tfrp";
1548let isPseudo = 1;
1549}
1550def A2_tfrptnew : HInst<
1551(outs DoubleRegs:$Rdd32),
1552(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1553"if ($Pu4.new) $Rdd32 = $Rss32",
1554tc_86173609, TypeALU32_2op>, PredNewRel {
1555let isPredicated = 1;
1556let isPredicatedNew = 1;
1557let BaseOpcode = "A2_tfrp";
1558let isPseudo = 1;
1559}
1560def A2_tfrrcr : HInst<
1561(outs CtrRegs:$Cd32),
1562(ins IntRegs:$Rs32),
1563"$Cd32 = $Rs32",
1564tc_49fdfd4b, TypeCR>, Enc_bd811a {
1565let Inst{13-5} = 0b000000000;
1566let Inst{31-21} = 0b01100010001;
1567let hasNewValue = 1;
1568let opNewValue = 0;
1569}
1570def A2_tfrsi : HInst<
1571(outs IntRegs:$Rd32),
1572(ins s32_0Imm:$Ii),
1573"$Rd32 = #$Ii",
1574tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
1575let Inst{21-21} = 0b0;
1576let Inst{31-24} = 0b01111000;
1577let hasNewValue = 1;
1578let opNewValue = 0;
1579let BaseOpcode = "A2_tfrsi";
1580let CextOpcode = "A2_tfr";
1581let InputType = "imm";
1582let isAsCheapAsAMove = 1;
1583let isMoveImm = 1;
1584let isPredicable = 1;
1585let isReMaterializable = 1;
1586let isExtendable = 1;
1587let opExtendable = 1;
1588let isExtentSigned = 1;
1589let opExtentBits = 16;
1590let opExtentAlign = 0;
1591}
1592def A2_tfrt : HInst<
1593(outs IntRegs:$Rd32),
1594(ins PredRegs:$Pu4, IntRegs:$Rs32),
1595"if ($Pu4) $Rd32 = $Rs32",
1596tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1597let isPredicated = 1;
1598let hasNewValue = 1;
1599let opNewValue = 0;
1600let BaseOpcode = "A2_tfr";
1601let CextOpcode = "A2_tfr";
1602let InputType = "reg";
1603let isPseudo = 1;
1604let isCodeGenOnly = 1;
1605}
1606def A2_tfrtnew : HInst<
1607(outs IntRegs:$Rd32),
1608(ins PredRegs:$Pu4, IntRegs:$Rs32),
1609"if ($Pu4.new) $Rd32 = $Rs32",
1610tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1611let isPredicated = 1;
1612let hasNewValue = 1;
1613let opNewValue = 0;
1614let isPredicatedNew = 1;
1615let BaseOpcode = "A2_tfr";
1616let CextOpcode = "A2_tfr";
1617let InputType = "reg";
1618let isPseudo = 1;
1619let isCodeGenOnly = 1;
1620}
1621def A2_vabsh : HInst<
1622(outs DoubleRegs:$Rdd32),
1623(ins DoubleRegs:$Rss32),
1624"$Rdd32 = vabsh($Rss32)",
1625tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1626let Inst{13-5} = 0b000000100;
1627let Inst{31-21} = 0b10000000010;
1628let prefersSlot3 = 1;
1629}
1630def A2_vabshsat : HInst<
1631(outs DoubleRegs:$Rdd32),
1632(ins DoubleRegs:$Rss32),
1633"$Rdd32 = vabsh($Rss32):sat",
1634tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1635let Inst{13-5} = 0b000000101;
1636let Inst{31-21} = 0b10000000010;
1637let prefersSlot3 = 1;
1638let Defs = [USR_OVF];
1639}
1640def A2_vabsw : HInst<
1641(outs DoubleRegs:$Rdd32),
1642(ins DoubleRegs:$Rss32),
1643"$Rdd32 = vabsw($Rss32)",
1644tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1645let Inst{13-5} = 0b000000110;
1646let Inst{31-21} = 0b10000000010;
1647let prefersSlot3 = 1;
1648}
1649def A2_vabswsat : HInst<
1650(outs DoubleRegs:$Rdd32),
1651(ins DoubleRegs:$Rss32),
1652"$Rdd32 = vabsw($Rss32):sat",
1653tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1654let Inst{13-5} = 0b000000111;
1655let Inst{31-21} = 0b10000000010;
1656let prefersSlot3 = 1;
1657let Defs = [USR_OVF];
1658}
1659def A2_vaddb_map : HInst<
1660(outs DoubleRegs:$Rdd32),
1661(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1662"$Rdd32 = vaddb($Rss32,$Rtt32)",
1663tc_5da50c4b, TypeMAPPING> {
1664let isPseudo = 1;
1665let isCodeGenOnly = 1;
1666}
1667def A2_vaddh : HInst<
1668(outs DoubleRegs:$Rdd32),
1669(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1670"$Rdd32 = vaddh($Rss32,$Rtt32)",
1671tc_5da50c4b, TypeALU64>, Enc_a56825 {
1672let Inst{7-5} = 0b010;
1673let Inst{13-13} = 0b0;
1674let Inst{31-21} = 0b11010011000;
1675}
1676def A2_vaddhs : HInst<
1677(outs DoubleRegs:$Rdd32),
1678(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1679"$Rdd32 = vaddh($Rss32,$Rtt32):sat",
1680tc_8a825db2, TypeALU64>, Enc_a56825 {
1681let Inst{7-5} = 0b011;
1682let Inst{13-13} = 0b0;
1683let Inst{31-21} = 0b11010011000;
1684let prefersSlot3 = 1;
1685let Defs = [USR_OVF];
1686}
1687def A2_vaddub : HInst<
1688(outs DoubleRegs:$Rdd32),
1689(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1690"$Rdd32 = vaddub($Rss32,$Rtt32)",
1691tc_5da50c4b, TypeALU64>, Enc_a56825 {
1692let Inst{7-5} = 0b000;
1693let Inst{13-13} = 0b0;
1694let Inst{31-21} = 0b11010011000;
1695}
1696def A2_vaddubs : HInst<
1697(outs DoubleRegs:$Rdd32),
1698(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1699"$Rdd32 = vaddub($Rss32,$Rtt32):sat",
1700tc_8a825db2, TypeALU64>, Enc_a56825 {
1701let Inst{7-5} = 0b001;
1702let Inst{13-13} = 0b0;
1703let Inst{31-21} = 0b11010011000;
1704let prefersSlot3 = 1;
1705let Defs = [USR_OVF];
1706}
1707def A2_vadduhs : HInst<
1708(outs DoubleRegs:$Rdd32),
1709(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1710"$Rdd32 = vadduh($Rss32,$Rtt32):sat",
1711tc_8a825db2, TypeALU64>, Enc_a56825 {
1712let Inst{7-5} = 0b100;
1713let Inst{13-13} = 0b0;
1714let Inst{31-21} = 0b11010011000;
1715let prefersSlot3 = 1;
1716let Defs = [USR_OVF];
1717}
1718def A2_vaddw : HInst<
1719(outs DoubleRegs:$Rdd32),
1720(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1721"$Rdd32 = vaddw($Rss32,$Rtt32)",
1722tc_5da50c4b, TypeALU64>, Enc_a56825 {
1723let Inst{7-5} = 0b101;
1724let Inst{13-13} = 0b0;
1725let Inst{31-21} = 0b11010011000;
1726}
1727def A2_vaddws : HInst<
1728(outs DoubleRegs:$Rdd32),
1729(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1730"$Rdd32 = vaddw($Rss32,$Rtt32):sat",
1731tc_8a825db2, TypeALU64>, Enc_a56825 {
1732let Inst{7-5} = 0b110;
1733let Inst{13-13} = 0b0;
1734let Inst{31-21} = 0b11010011000;
1735let prefersSlot3 = 1;
1736let Defs = [USR_OVF];
1737}
1738def A2_vavgh : HInst<
1739(outs DoubleRegs:$Rdd32),
1740(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1741"$Rdd32 = vavgh($Rss32,$Rtt32)",
1742tc_f098b237, TypeALU64>, Enc_a56825 {
1743let Inst{7-5} = 0b010;
1744let Inst{13-13} = 0b0;
1745let Inst{31-21} = 0b11010011010;
1746let prefersSlot3 = 1;
1747}
1748def A2_vavghcr : HInst<
1749(outs DoubleRegs:$Rdd32),
1750(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1751"$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
1752tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1753let Inst{7-5} = 0b100;
1754let Inst{13-13} = 0b0;
1755let Inst{31-21} = 0b11010011010;
1756let prefersSlot3 = 1;
1757}
1758def A2_vavghr : HInst<
1759(outs DoubleRegs:$Rdd32),
1760(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1761"$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
1762tc_20131976, TypeALU64>, Enc_a56825 {
1763let Inst{7-5} = 0b011;
1764let Inst{13-13} = 0b0;
1765let Inst{31-21} = 0b11010011010;
1766let prefersSlot3 = 1;
1767}
1768def A2_vavgub : HInst<
1769(outs DoubleRegs:$Rdd32),
1770(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1771"$Rdd32 = vavgub($Rss32,$Rtt32)",
1772tc_f098b237, TypeALU64>, Enc_a56825 {
1773let Inst{7-5} = 0b000;
1774let Inst{13-13} = 0b0;
1775let Inst{31-21} = 0b11010011010;
1776let prefersSlot3 = 1;
1777}
1778def A2_vavgubr : HInst<
1779(outs DoubleRegs:$Rdd32),
1780(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1781"$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
1782tc_20131976, TypeALU64>, Enc_a56825 {
1783let Inst{7-5} = 0b001;
1784let Inst{13-13} = 0b0;
1785let Inst{31-21} = 0b11010011010;
1786let prefersSlot3 = 1;
1787}
1788def A2_vavguh : HInst<
1789(outs DoubleRegs:$Rdd32),
1790(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1791"$Rdd32 = vavguh($Rss32,$Rtt32)",
1792tc_f098b237, TypeALU64>, Enc_a56825 {
1793let Inst{7-5} = 0b101;
1794let Inst{13-13} = 0b0;
1795let Inst{31-21} = 0b11010011010;
1796let prefersSlot3 = 1;
1797}
1798def A2_vavguhr : HInst<
1799(outs DoubleRegs:$Rdd32),
1800(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1801"$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
1802tc_20131976, TypeALU64>, Enc_a56825 {
1803let Inst{7-5} = 0b110;
1804let Inst{13-13} = 0b0;
1805let Inst{31-21} = 0b11010011010;
1806let prefersSlot3 = 1;
1807}
1808def A2_vavguw : HInst<
1809(outs DoubleRegs:$Rdd32),
1810(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1811"$Rdd32 = vavguw($Rss32,$Rtt32)",
1812tc_f098b237, TypeALU64>, Enc_a56825 {
1813let Inst{7-5} = 0b011;
1814let Inst{13-13} = 0b0;
1815let Inst{31-21} = 0b11010011011;
1816let prefersSlot3 = 1;
1817}
1818def A2_vavguwr : HInst<
1819(outs DoubleRegs:$Rdd32),
1820(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1821"$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
1822tc_20131976, TypeALU64>, Enc_a56825 {
1823let Inst{7-5} = 0b100;
1824let Inst{13-13} = 0b0;
1825let Inst{31-21} = 0b11010011011;
1826let prefersSlot3 = 1;
1827}
1828def A2_vavgw : HInst<
1829(outs DoubleRegs:$Rdd32),
1830(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1831"$Rdd32 = vavgw($Rss32,$Rtt32)",
1832tc_f098b237, TypeALU64>, Enc_a56825 {
1833let Inst{7-5} = 0b000;
1834let Inst{13-13} = 0b0;
1835let Inst{31-21} = 0b11010011011;
1836let prefersSlot3 = 1;
1837}
1838def A2_vavgwcr : HInst<
1839(outs DoubleRegs:$Rdd32),
1840(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1841"$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
1842tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1843let Inst{7-5} = 0b010;
1844let Inst{13-13} = 0b0;
1845let Inst{31-21} = 0b11010011011;
1846let prefersSlot3 = 1;
1847}
1848def A2_vavgwr : HInst<
1849(outs DoubleRegs:$Rdd32),
1850(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1851"$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
1852tc_20131976, TypeALU64>, Enc_a56825 {
1853let Inst{7-5} = 0b001;
1854let Inst{13-13} = 0b0;
1855let Inst{31-21} = 0b11010011011;
1856let prefersSlot3 = 1;
1857}
1858def A2_vcmpbeq : HInst<
1859(outs PredRegs:$Pd4),
1860(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1861"$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
1862tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1863let Inst{7-2} = 0b110000;
1864let Inst{13-13} = 0b0;
1865let Inst{31-21} = 0b11010010000;
1866}
1867def A2_vcmpbgtu : HInst<
1868(outs PredRegs:$Pd4),
1869(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1870"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
1871tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1872let Inst{7-2} = 0b111000;
1873let Inst{13-13} = 0b0;
1874let Inst{31-21} = 0b11010010000;
1875}
1876def A2_vcmpheq : HInst<
1877(outs PredRegs:$Pd4),
1878(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1879"$Pd4 = vcmph.eq($Rss32,$Rtt32)",
1880tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1881let Inst{7-2} = 0b011000;
1882let Inst{13-13} = 0b0;
1883let Inst{31-21} = 0b11010010000;
1884}
1885def A2_vcmphgt : HInst<
1886(outs PredRegs:$Pd4),
1887(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1888"$Pd4 = vcmph.gt($Rss32,$Rtt32)",
1889tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1890let Inst{7-2} = 0b100000;
1891let Inst{13-13} = 0b0;
1892let Inst{31-21} = 0b11010010000;
1893}
1894def A2_vcmphgtu : HInst<
1895(outs PredRegs:$Pd4),
1896(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1897"$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
1898tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1899let Inst{7-2} = 0b101000;
1900let Inst{13-13} = 0b0;
1901let Inst{31-21} = 0b11010010000;
1902}
1903def A2_vcmpweq : HInst<
1904(outs PredRegs:$Pd4),
1905(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1906"$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
1907tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1908let Inst{7-2} = 0b000000;
1909let Inst{13-13} = 0b0;
1910let Inst{31-21} = 0b11010010000;
1911}
1912def A2_vcmpwgt : HInst<
1913(outs PredRegs:$Pd4),
1914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1915"$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
1916tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1917let Inst{7-2} = 0b001000;
1918let Inst{13-13} = 0b0;
1919let Inst{31-21} = 0b11010010000;
1920}
1921def A2_vcmpwgtu : HInst<
1922(outs PredRegs:$Pd4),
1923(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1924"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
1925tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1926let Inst{7-2} = 0b010000;
1927let Inst{13-13} = 0b0;
1928let Inst{31-21} = 0b11010010000;
1929}
1930def A2_vconj : HInst<
1931(outs DoubleRegs:$Rdd32),
1932(ins DoubleRegs:$Rss32),
1933"$Rdd32 = vconj($Rss32):sat",
1934tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1935let Inst{13-5} = 0b000000111;
1936let Inst{31-21} = 0b10000000100;
1937let prefersSlot3 = 1;
1938let Defs = [USR_OVF];
1939}
1940def A2_vmaxb : HInst<
1941(outs DoubleRegs:$Rdd32),
1942(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1943"$Rdd32 = vmaxb($Rtt32,$Rss32)",
1944tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1945let Inst{7-5} = 0b110;
1946let Inst{13-13} = 0b0;
1947let Inst{31-21} = 0b11010011110;
1948let prefersSlot3 = 1;
1949}
1950def A2_vmaxh : HInst<
1951(outs DoubleRegs:$Rdd32),
1952(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1953"$Rdd32 = vmaxh($Rtt32,$Rss32)",
1954tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1955let Inst{7-5} = 0b001;
1956let Inst{13-13} = 0b0;
1957let Inst{31-21} = 0b11010011110;
1958let prefersSlot3 = 1;
1959}
1960def A2_vmaxub : HInst<
1961(outs DoubleRegs:$Rdd32),
1962(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1963"$Rdd32 = vmaxub($Rtt32,$Rss32)",
1964tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1965let Inst{7-5} = 0b000;
1966let Inst{13-13} = 0b0;
1967let Inst{31-21} = 0b11010011110;
1968let prefersSlot3 = 1;
1969}
1970def A2_vmaxuh : HInst<
1971(outs DoubleRegs:$Rdd32),
1972(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1973"$Rdd32 = vmaxuh($Rtt32,$Rss32)",
1974tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1975let Inst{7-5} = 0b010;
1976let Inst{13-13} = 0b0;
1977let Inst{31-21} = 0b11010011110;
1978let prefersSlot3 = 1;
1979}
1980def A2_vmaxuw : HInst<
1981(outs DoubleRegs:$Rdd32),
1982(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1983"$Rdd32 = vmaxuw($Rtt32,$Rss32)",
1984tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1985let Inst{7-5} = 0b101;
1986let Inst{13-13} = 0b0;
1987let Inst{31-21} = 0b11010011101;
1988let prefersSlot3 = 1;
1989}
1990def A2_vmaxw : HInst<
1991(outs DoubleRegs:$Rdd32),
1992(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1993"$Rdd32 = vmaxw($Rtt32,$Rss32)",
1994tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1995let Inst{7-5} = 0b011;
1996let Inst{13-13} = 0b0;
1997let Inst{31-21} = 0b11010011110;
1998let prefersSlot3 = 1;
1999}
2000def A2_vminb : HInst<
2001(outs DoubleRegs:$Rdd32),
2002(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2003"$Rdd32 = vminb($Rtt32,$Rss32)",
2004tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2005let Inst{7-5} = 0b111;
2006let Inst{13-13} = 0b0;
2007let Inst{31-21} = 0b11010011110;
2008let prefersSlot3 = 1;
2009}
2010def A2_vminh : HInst<
2011(outs DoubleRegs:$Rdd32),
2012(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2013"$Rdd32 = vminh($Rtt32,$Rss32)",
2014tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2015let Inst{7-5} = 0b001;
2016let Inst{13-13} = 0b0;
2017let Inst{31-21} = 0b11010011101;
2018let prefersSlot3 = 1;
2019}
2020def A2_vminub : HInst<
2021(outs DoubleRegs:$Rdd32),
2022(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2023"$Rdd32 = vminub($Rtt32,$Rss32)",
2024tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2025let Inst{7-5} = 0b000;
2026let Inst{13-13} = 0b0;
2027let Inst{31-21} = 0b11010011101;
2028let prefersSlot3 = 1;
2029}
2030def A2_vminuh : HInst<
2031(outs DoubleRegs:$Rdd32),
2032(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2033"$Rdd32 = vminuh($Rtt32,$Rss32)",
2034tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2035let Inst{7-5} = 0b010;
2036let Inst{13-13} = 0b0;
2037let Inst{31-21} = 0b11010011101;
2038let prefersSlot3 = 1;
2039}
2040def A2_vminuw : HInst<
2041(outs DoubleRegs:$Rdd32),
2042(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2043"$Rdd32 = vminuw($Rtt32,$Rss32)",
2044tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2045let Inst{7-5} = 0b100;
2046let Inst{13-13} = 0b0;
2047let Inst{31-21} = 0b11010011101;
2048let prefersSlot3 = 1;
2049}
2050def A2_vminw : HInst<
2051(outs DoubleRegs:$Rdd32),
2052(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2053"$Rdd32 = vminw($Rtt32,$Rss32)",
2054tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2055let Inst{7-5} = 0b011;
2056let Inst{13-13} = 0b0;
2057let Inst{31-21} = 0b11010011101;
2058let prefersSlot3 = 1;
2059}
2060def A2_vnavgh : HInst<
2061(outs DoubleRegs:$Rdd32),
2062(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2063"$Rdd32 = vnavgh($Rtt32,$Rss32)",
2064tc_f098b237, TypeALU64>, Enc_ea23e4 {
2065let Inst{7-5} = 0b000;
2066let Inst{13-13} = 0b0;
2067let Inst{31-21} = 0b11010011100;
2068let prefersSlot3 = 1;
2069}
2070def A2_vnavghcr : HInst<
2071(outs DoubleRegs:$Rdd32),
2072(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2073"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
2074tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2075let Inst{7-5} = 0b010;
2076let Inst{13-13} = 0b0;
2077let Inst{31-21} = 0b11010011100;
2078let prefersSlot3 = 1;
2079let Defs = [USR_OVF];
2080}
2081def A2_vnavghr : HInst<
2082(outs DoubleRegs:$Rdd32),
2083(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2084"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
2085tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2086let Inst{7-5} = 0b001;
2087let Inst{13-13} = 0b0;
2088let Inst{31-21} = 0b11010011100;
2089let prefersSlot3 = 1;
2090let Defs = [USR_OVF];
2091}
2092def A2_vnavgw : HInst<
2093(outs DoubleRegs:$Rdd32),
2094(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2095"$Rdd32 = vnavgw($Rtt32,$Rss32)",
2096tc_f098b237, TypeALU64>, Enc_ea23e4 {
2097let Inst{7-5} = 0b011;
2098let Inst{13-13} = 0b0;
2099let Inst{31-21} = 0b11010011100;
2100let prefersSlot3 = 1;
2101}
2102def A2_vnavgwcr : HInst<
2103(outs DoubleRegs:$Rdd32),
2104(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2105"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
2106tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2107let Inst{7-5} = 0b110;
2108let Inst{13-13} = 0b0;
2109let Inst{31-21} = 0b11010011100;
2110let prefersSlot3 = 1;
2111let Defs = [USR_OVF];
2112}
2113def A2_vnavgwr : HInst<
2114(outs DoubleRegs:$Rdd32),
2115(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2116"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
2117tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2118let Inst{7-5} = 0b100;
2119let Inst{13-13} = 0b0;
2120let Inst{31-21} = 0b11010011100;
2121let prefersSlot3 = 1;
2122let Defs = [USR_OVF];
2123}
2124def A2_vraddub : HInst<
2125(outs DoubleRegs:$Rdd32),
2126(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2127"$Rdd32 = vraddub($Rss32,$Rtt32)",
2128tc_c21d7447, TypeM>, Enc_a56825 {
2129let Inst{7-5} = 0b001;
2130let Inst{13-13} = 0b0;
2131let Inst{31-21} = 0b11101000010;
2132let prefersSlot3 = 1;
2133}
2134def A2_vraddub_acc : HInst<
2135(outs DoubleRegs:$Rxx32),
2136(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2137"$Rxx32 += vraddub($Rss32,$Rtt32)",
2138tc_7f8ae742, TypeM>, Enc_88c16c {
2139let Inst{7-5} = 0b001;
2140let Inst{13-13} = 0b0;
2141let Inst{31-21} = 0b11101010010;
2142let prefersSlot3 = 1;
2143let Constraints = "$Rxx32 = $Rxx32in";
2144}
2145def A2_vrsadub : HInst<
2146(outs DoubleRegs:$Rdd32),
2147(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2148"$Rdd32 = vrsadub($Rss32,$Rtt32)",
2149tc_c21d7447, TypeM>, Enc_a56825 {
2150let Inst{7-5} = 0b010;
2151let Inst{13-13} = 0b0;
2152let Inst{31-21} = 0b11101000010;
2153let prefersSlot3 = 1;
2154}
2155def A2_vrsadub_acc : HInst<
2156(outs DoubleRegs:$Rxx32),
2157(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2158"$Rxx32 += vrsadub($Rss32,$Rtt32)",
2159tc_7f8ae742, TypeM>, Enc_88c16c {
2160let Inst{7-5} = 0b010;
2161let Inst{13-13} = 0b0;
2162let Inst{31-21} = 0b11101010010;
2163let prefersSlot3 = 1;
2164let Constraints = "$Rxx32 = $Rxx32in";
2165}
2166def A2_vsubb_map : HInst<
2167(outs DoubleRegs:$Rdd32),
2168(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2169"$Rdd32 = vsubb($Rss32,$Rtt32)",
2170tc_5da50c4b, TypeMAPPING> {
2171let isPseudo = 1;
2172let isCodeGenOnly = 1;
2173}
2174def A2_vsubh : HInst<
2175(outs DoubleRegs:$Rdd32),
2176(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2177"$Rdd32 = vsubh($Rtt32,$Rss32)",
2178tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2179let Inst{7-5} = 0b010;
2180let Inst{13-13} = 0b0;
2181let Inst{31-21} = 0b11010011001;
2182}
2183def A2_vsubhs : HInst<
2184(outs DoubleRegs:$Rdd32),
2185(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2186"$Rdd32 = vsubh($Rtt32,$Rss32):sat",
2187tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2188let Inst{7-5} = 0b011;
2189let Inst{13-13} = 0b0;
2190let Inst{31-21} = 0b11010011001;
2191let prefersSlot3 = 1;
2192let Defs = [USR_OVF];
2193}
2194def A2_vsubub : HInst<
2195(outs DoubleRegs:$Rdd32),
2196(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2197"$Rdd32 = vsubub($Rtt32,$Rss32)",
2198tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2199let Inst{7-5} = 0b000;
2200let Inst{13-13} = 0b0;
2201let Inst{31-21} = 0b11010011001;
2202}
2203def A2_vsububs : HInst<
2204(outs DoubleRegs:$Rdd32),
2205(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2206"$Rdd32 = vsubub($Rtt32,$Rss32):sat",
2207tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2208let Inst{7-5} = 0b001;
2209let Inst{13-13} = 0b0;
2210let Inst{31-21} = 0b11010011001;
2211let prefersSlot3 = 1;
2212let Defs = [USR_OVF];
2213}
2214def A2_vsubuhs : HInst<
2215(outs DoubleRegs:$Rdd32),
2216(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2217"$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
2218tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2219let Inst{7-5} = 0b100;
2220let Inst{13-13} = 0b0;
2221let Inst{31-21} = 0b11010011001;
2222let prefersSlot3 = 1;
2223let Defs = [USR_OVF];
2224}
2225def A2_vsubw : HInst<
2226(outs DoubleRegs:$Rdd32),
2227(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2228"$Rdd32 = vsubw($Rtt32,$Rss32)",
2229tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2230let Inst{7-5} = 0b101;
2231let Inst{13-13} = 0b0;
2232let Inst{31-21} = 0b11010011001;
2233}
2234def A2_vsubws : HInst<
2235(outs DoubleRegs:$Rdd32),
2236(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2237"$Rdd32 = vsubw($Rtt32,$Rss32):sat",
2238tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2239let Inst{7-5} = 0b110;
2240let Inst{13-13} = 0b0;
2241let Inst{31-21} = 0b11010011001;
2242let prefersSlot3 = 1;
2243let Defs = [USR_OVF];
2244}
2245def A2_xor : HInst<
2246(outs IntRegs:$Rd32),
2247(ins IntRegs:$Rs32, IntRegs:$Rt32),
2248"$Rd32 = xor($Rs32,$Rt32)",
2249tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
2250let Inst{7-5} = 0b000;
2251let Inst{13-13} = 0b0;
2252let Inst{31-21} = 0b11110001011;
2253let hasNewValue = 1;
2254let opNewValue = 0;
2255let BaseOpcode = "A2_xor";
2256let InputType = "reg";
2257let isCommutable = 1;
2258let isPredicable = 1;
2259}
2260def A2_xorp : HInst<
2261(outs DoubleRegs:$Rdd32),
2262(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2263"$Rdd32 = xor($Rss32,$Rtt32)",
2264tc_5da50c4b, TypeALU64>, Enc_a56825 {
2265let Inst{7-5} = 0b100;
2266let Inst{13-13} = 0b0;
2267let Inst{31-21} = 0b11010011111;
2268let isCommutable = 1;
2269}
2270def A2_zxtb : HInst<
2271(outs IntRegs:$Rd32),
2272(ins IntRegs:$Rs32),
2273"$Rd32 = zxtb($Rs32)",
2274tc_713b66bf, TypeALU32_2op>, PredNewRel {
2275let hasNewValue = 1;
2276let opNewValue = 0;
2277let BaseOpcode = "A2_zxtb";
2278let isPredicable = 1;
2279let isPseudo = 1;
2280let isCodeGenOnly = 1;
2281}
2282def A2_zxth : HInst<
2283(outs IntRegs:$Rd32),
2284(ins IntRegs:$Rs32),
2285"$Rd32 = zxth($Rs32)",
2286tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
2287let Inst{13-5} = 0b000000000;
2288let Inst{31-21} = 0b01110000110;
2289let hasNewValue = 1;
2290let opNewValue = 0;
2291let BaseOpcode = "A2_zxth";
2292let isPredicable = 1;
2293}
2294def A4_addp_c : HInst<
2295(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
2296(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
2297"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
2298tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
2299let Inst{7-7} = 0b0;
2300let Inst{13-13} = 0b0;
2301let Inst{31-21} = 0b11000010110;
2302let isPredicateLate = 1;
2303let Constraints = "$Px4 = $Px4in";
2304}
2305def A4_andn : HInst<
2306(outs IntRegs:$Rd32),
2307(ins IntRegs:$Rt32, IntRegs:$Rs32),
2308"$Rd32 = and($Rt32,~$Rs32)",
2309tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2310let Inst{7-5} = 0b000;
2311let Inst{13-13} = 0b0;
2312let Inst{31-21} = 0b11110001100;
2313let hasNewValue = 1;
2314let opNewValue = 0;
2315let InputType = "reg";
2316}
2317def A4_andnp : HInst<
2318(outs DoubleRegs:$Rdd32),
2319(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2320"$Rdd32 = and($Rtt32,~$Rss32)",
2321tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2322let Inst{7-5} = 0b001;
2323let Inst{13-13} = 0b0;
2324let Inst{31-21} = 0b11010011111;
2325}
2326def A4_bitsplit : HInst<
2327(outs DoubleRegs:$Rdd32),
2328(ins IntRegs:$Rs32, IntRegs:$Rt32),
2329"$Rdd32 = bitsplit($Rs32,$Rt32)",
2330tc_f34c1c21, TypeALU64>, Enc_be32a5 {
2331let Inst{7-5} = 0b000;
2332let Inst{13-13} = 0b0;
2333let Inst{31-21} = 0b11010100001;
2334let prefersSlot3 = 1;
2335}
2336def A4_bitspliti : HInst<
2337(outs DoubleRegs:$Rdd32),
2338(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2339"$Rdd32 = bitsplit($Rs32,#$Ii)",
2340tc_f34c1c21, TypeS_2op>, Enc_311abd {
2341let Inst{7-5} = 0b100;
2342let Inst{13-13} = 0b0;
2343let Inst{31-21} = 0b10001000110;
2344let prefersSlot3 = 1;
2345}
2346def A4_boundscheck : HInst<
2347(outs PredRegs:$Pd4),
2348(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
2349"$Pd4 = boundscheck($Rs32,$Rtt32)",
2350tc_4a55d03c, TypeALU64> {
2351let isPseudo = 1;
2352}
2353def A4_boundscheck_hi : HInst<
2354(outs PredRegs:$Pd4),
2355(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2356"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
2357tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2358let Inst{7-2} = 0b101000;
2359let Inst{13-13} = 0b1;
2360let Inst{31-21} = 0b11010010000;
2361}
2362def A4_boundscheck_lo : HInst<
2363(outs PredRegs:$Pd4),
2364(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2365"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
2366tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2367let Inst{7-2} = 0b100000;
2368let Inst{13-13} = 0b1;
2369let Inst{31-21} = 0b11010010000;
2370}
2371def A4_cmpbeq : HInst<
2372(outs PredRegs:$Pd4),
2373(ins IntRegs:$Rs32, IntRegs:$Rt32),
2374"$Pd4 = cmpb.eq($Rs32,$Rt32)",
2375tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2376let Inst{7-2} = 0b110000;
2377let Inst{13-13} = 0b0;
2378let Inst{31-21} = 0b11000111110;
2379let CextOpcode = "A4_cmpbeq";
2380let InputType = "reg";
2381let isCommutable = 1;
2382let isCompare = 1;
2383}
2384def A4_cmpbeqi : HInst<
2385(outs PredRegs:$Pd4),
2386(ins IntRegs:$Rs32, u8_0Imm:$Ii),
2387"$Pd4 = cmpb.eq($Rs32,#$Ii)",
2388tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2389let Inst{4-2} = 0b000;
2390let Inst{13-13} = 0b0;
2391let Inst{31-21} = 0b11011101000;
2392let CextOpcode = "A4_cmpbeq";
2393let InputType = "imm";
2394let isCommutable = 1;
2395let isCompare = 1;
2396}
2397def A4_cmpbgt : HInst<
2398(outs PredRegs:$Pd4),
2399(ins IntRegs:$Rs32, IntRegs:$Rt32),
2400"$Pd4 = cmpb.gt($Rs32,$Rt32)",
2401tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2402let Inst{7-2} = 0b010000;
2403let Inst{13-13} = 0b0;
2404let Inst{31-21} = 0b11000111110;
2405let CextOpcode = "A4_cmpbgt";
2406let InputType = "reg";
2407let isCompare = 1;
2408}
2409def A4_cmpbgti : HInst<
2410(outs PredRegs:$Pd4),
2411(ins IntRegs:$Rs32, s8_0Imm:$Ii),
2412"$Pd4 = cmpb.gt($Rs32,#$Ii)",
2413tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2414let Inst{4-2} = 0b000;
2415let Inst{13-13} = 0b0;
2416let Inst{31-21} = 0b11011101001;
2417let CextOpcode = "A4_cmpbgt";
2418let InputType = "imm";
2419let isCompare = 1;
2420}
2421def A4_cmpbgtu : HInst<
2422(outs PredRegs:$Pd4),
2423(ins IntRegs:$Rs32, IntRegs:$Rt32),
2424"$Pd4 = cmpb.gtu($Rs32,$Rt32)",
2425tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2426let Inst{7-2} = 0b111000;
2427let Inst{13-13} = 0b0;
2428let Inst{31-21} = 0b11000111110;
2429let CextOpcode = "A4_cmpbgtu";
2430let InputType = "reg";
2431let isCompare = 1;
2432}
2433def A4_cmpbgtui : HInst<
2434(outs PredRegs:$Pd4),
2435(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2436"$Pd4 = cmpb.gtu($Rs32,#$Ii)",
2437tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2438let Inst{4-2} = 0b000;
2439let Inst{13-12} = 0b00;
2440let Inst{31-21} = 0b11011101010;
2441let CextOpcode = "A4_cmpbgtu";
2442let InputType = "imm";
2443let isCompare = 1;
2444let isExtendable = 1;
2445let opExtendable = 2;
2446let isExtentSigned = 0;
2447let opExtentBits = 7;
2448let opExtentAlign = 0;
2449}
2450def A4_cmpheq : HInst<
2451(outs PredRegs:$Pd4),
2452(ins IntRegs:$Rs32, IntRegs:$Rt32),
2453"$Pd4 = cmph.eq($Rs32,$Rt32)",
2454tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2455let Inst{7-2} = 0b011000;
2456let Inst{13-13} = 0b0;
2457let Inst{31-21} = 0b11000111110;
2458let CextOpcode = "A4_cmpheq";
2459let InputType = "reg";
2460let isCommutable = 1;
2461let isCompare = 1;
2462}
2463def A4_cmpheqi : HInst<
2464(outs PredRegs:$Pd4),
2465(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2466"$Pd4 = cmph.eq($Rs32,#$Ii)",
2467tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2468let Inst{4-2} = 0b010;
2469let Inst{13-13} = 0b0;
2470let Inst{31-21} = 0b11011101000;
2471let CextOpcode = "A4_cmpheq";
2472let InputType = "imm";
2473let isCommutable = 1;
2474let isCompare = 1;
2475let isExtendable = 1;
2476let opExtendable = 2;
2477let isExtentSigned = 1;
2478let opExtentBits = 8;
2479let opExtentAlign = 0;
2480}
2481def A4_cmphgt : HInst<
2482(outs PredRegs:$Pd4),
2483(ins IntRegs:$Rs32, IntRegs:$Rt32),
2484"$Pd4 = cmph.gt($Rs32,$Rt32)",
2485tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2486let Inst{7-2} = 0b100000;
2487let Inst{13-13} = 0b0;
2488let Inst{31-21} = 0b11000111110;
2489let CextOpcode = "A4_cmphgt";
2490let InputType = "reg";
2491let isCompare = 1;
2492}
2493def A4_cmphgti : HInst<
2494(outs PredRegs:$Pd4),
2495(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2496"$Pd4 = cmph.gt($Rs32,#$Ii)",
2497tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2498let Inst{4-2} = 0b010;
2499let Inst{13-13} = 0b0;
2500let Inst{31-21} = 0b11011101001;
2501let CextOpcode = "A4_cmphgt";
2502let InputType = "imm";
2503let isCompare = 1;
2504let isExtendable = 1;
2505let opExtendable = 2;
2506let isExtentSigned = 1;
2507let opExtentBits = 8;
2508let opExtentAlign = 0;
2509}
2510def A4_cmphgtu : HInst<
2511(outs PredRegs:$Pd4),
2512(ins IntRegs:$Rs32, IntRegs:$Rt32),
2513"$Pd4 = cmph.gtu($Rs32,$Rt32)",
2514tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2515let Inst{7-2} = 0b101000;
2516let Inst{13-13} = 0b0;
2517let Inst{31-21} = 0b11000111110;
2518let CextOpcode = "A4_cmphgtu";
2519let InputType = "reg";
2520let isCompare = 1;
2521}
2522def A4_cmphgtui : HInst<
2523(outs PredRegs:$Pd4),
2524(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2525"$Pd4 = cmph.gtu($Rs32,#$Ii)",
2526tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2527let Inst{4-2} = 0b010;
2528let Inst{13-12} = 0b00;
2529let Inst{31-21} = 0b11011101010;
2530let CextOpcode = "A4_cmphgtu";
2531let InputType = "imm";
2532let isCompare = 1;
2533let isExtendable = 1;
2534let opExtendable = 2;
2535let isExtentSigned = 0;
2536let opExtentBits = 7;
2537let opExtentAlign = 0;
2538}
2539def A4_combineii : HInst<
2540(outs DoubleRegs:$Rdd32),
2541(ins s8_0Imm:$Ii, u32_0Imm:$II),
2542"$Rdd32 = combine(#$Ii,#$II)",
2543tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 {
2544let Inst{31-21} = 0b01111100100;
2545let isExtendable = 1;
2546let opExtendable = 2;
2547let isExtentSigned = 0;
2548let opExtentBits = 6;
2549let opExtentAlign = 0;
2550}
2551def A4_combineir : HInst<
2552(outs DoubleRegs:$Rdd32),
2553(ins s32_0Imm:$Ii, IntRegs:$Rs32),
2554"$Rdd32 = combine(#$Ii,$Rs32)",
2555tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2556let Inst{13-13} = 0b1;
2557let Inst{31-21} = 0b01110011001;
2558let isExtendable = 1;
2559let opExtendable = 1;
2560let isExtentSigned = 1;
2561let opExtentBits = 8;
2562let opExtentAlign = 0;
2563}
2564def A4_combineri : HInst<
2565(outs DoubleRegs:$Rdd32),
2566(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2567"$Rdd32 = combine($Rs32,#$Ii)",
2568tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2569let Inst{13-13} = 0b1;
2570let Inst{31-21} = 0b01110011000;
2571let isExtendable = 1;
2572let opExtendable = 2;
2573let isExtentSigned = 1;
2574let opExtentBits = 8;
2575let opExtentAlign = 0;
2576}
2577def A4_cround_ri : HInst<
2578(outs IntRegs:$Rd32),
2579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2580"$Rd32 = cround($Rs32,#$Ii)",
2581tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
2582let Inst{7-5} = 0b000;
2583let Inst{13-13} = 0b0;
2584let Inst{31-21} = 0b10001100111;
2585let hasNewValue = 1;
2586let opNewValue = 0;
2587let prefersSlot3 = 1;
2588}
2589def A4_cround_rr : HInst<
2590(outs IntRegs:$Rd32),
2591(ins IntRegs:$Rs32, IntRegs:$Rt32),
2592"$Rd32 = cround($Rs32,$Rt32)",
2593tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
2594let Inst{7-5} = 0b000;
2595let Inst{13-13} = 0b0;
2596let Inst{31-21} = 0b11000110110;
2597let hasNewValue = 1;
2598let opNewValue = 0;
2599let prefersSlot3 = 1;
2600}
2601def A4_ext : HInst<
2602(outs),
2603(ins u26_6Imm:$Ii),
2604"immext(#$Ii)",
2605tc_112d30d6, TypeEXTENDER>, Enc_2b518f {
2606let Inst{31-28} = 0b0000;
2607}
2608def A4_modwrapu : HInst<
2609(outs IntRegs:$Rd32),
2610(ins IntRegs:$Rs32, IntRegs:$Rt32),
2611"$Rd32 = modwrap($Rs32,$Rt32)",
2612tc_8a825db2, TypeALU64>, Enc_5ab2be {
2613let Inst{7-5} = 0b111;
2614let Inst{13-13} = 0b0;
2615let Inst{31-21} = 0b11010011111;
2616let hasNewValue = 1;
2617let opNewValue = 0;
2618let prefersSlot3 = 1;
2619}
2620def A4_orn : HInst<
2621(outs IntRegs:$Rd32),
2622(ins IntRegs:$Rt32, IntRegs:$Rs32),
2623"$Rd32 = or($Rt32,~$Rs32)",
2624tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2625let Inst{7-5} = 0b000;
2626let Inst{13-13} = 0b0;
2627let Inst{31-21} = 0b11110001101;
2628let hasNewValue = 1;
2629let opNewValue = 0;
2630let InputType = "reg";
2631}
2632def A4_ornp : HInst<
2633(outs DoubleRegs:$Rdd32),
2634(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2635"$Rdd32 = or($Rtt32,~$Rss32)",
2636tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2637let Inst{7-5} = 0b011;
2638let Inst{13-13} = 0b0;
2639let Inst{31-21} = 0b11010011111;
2640}
2641def A4_paslhf : HInst<
2642(outs IntRegs:$Rd32),
2643(ins PredRegs:$Pu4, IntRegs:$Rs32),
2644"if (!$Pu4) $Rd32 = aslh($Rs32)",
2645tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2646let Inst{7-5} = 0b000;
2647let Inst{13-10} = 0b1010;
2648let Inst{31-21} = 0b01110000000;
2649let isPredicated = 1;
2650let isPredicatedFalse = 1;
2651let hasNewValue = 1;
2652let opNewValue = 0;
2653let BaseOpcode = "A2_aslh";
2654}
2655def A4_paslhfnew : HInst<
2656(outs IntRegs:$Rd32),
2657(ins PredRegs:$Pu4, IntRegs:$Rs32),
2658"if (!$Pu4.new) $Rd32 = aslh($Rs32)",
2659tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2660let Inst{7-5} = 0b000;
2661let Inst{13-10} = 0b1011;
2662let Inst{31-21} = 0b01110000000;
2663let isPredicated = 1;
2664let isPredicatedFalse = 1;
2665let hasNewValue = 1;
2666let opNewValue = 0;
2667let isPredicatedNew = 1;
2668let BaseOpcode = "A2_aslh";
2669}
2670def A4_paslht : HInst<
2671(outs IntRegs:$Rd32),
2672(ins PredRegs:$Pu4, IntRegs:$Rs32),
2673"if ($Pu4) $Rd32 = aslh($Rs32)",
2674tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2675let Inst{7-5} = 0b000;
2676let Inst{13-10} = 0b1000;
2677let Inst{31-21} = 0b01110000000;
2678let isPredicated = 1;
2679let hasNewValue = 1;
2680let opNewValue = 0;
2681let BaseOpcode = "A2_aslh";
2682}
2683def A4_paslhtnew : HInst<
2684(outs IntRegs:$Rd32),
2685(ins PredRegs:$Pu4, IntRegs:$Rs32),
2686"if ($Pu4.new) $Rd32 = aslh($Rs32)",
2687tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2688let Inst{7-5} = 0b000;
2689let Inst{13-10} = 0b1001;
2690let Inst{31-21} = 0b01110000000;
2691let isPredicated = 1;
2692let hasNewValue = 1;
2693let opNewValue = 0;
2694let isPredicatedNew = 1;
2695let BaseOpcode = "A2_aslh";
2696}
2697def A4_pasrhf : HInst<
2698(outs IntRegs:$Rd32),
2699(ins PredRegs:$Pu4, IntRegs:$Rs32),
2700"if (!$Pu4) $Rd32 = asrh($Rs32)",
2701tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2702let Inst{7-5} = 0b000;
2703let Inst{13-10} = 0b1010;
2704let Inst{31-21} = 0b01110000001;
2705let isPredicated = 1;
2706let isPredicatedFalse = 1;
2707let hasNewValue = 1;
2708let opNewValue = 0;
2709let BaseOpcode = "A2_asrh";
2710}
2711def A4_pasrhfnew : HInst<
2712(outs IntRegs:$Rd32),
2713(ins PredRegs:$Pu4, IntRegs:$Rs32),
2714"if (!$Pu4.new) $Rd32 = asrh($Rs32)",
2715tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2716let Inst{7-5} = 0b000;
2717let Inst{13-10} = 0b1011;
2718let Inst{31-21} = 0b01110000001;
2719let isPredicated = 1;
2720let isPredicatedFalse = 1;
2721let hasNewValue = 1;
2722let opNewValue = 0;
2723let isPredicatedNew = 1;
2724let BaseOpcode = "A2_asrh";
2725}
2726def A4_pasrht : HInst<
2727(outs IntRegs:$Rd32),
2728(ins PredRegs:$Pu4, IntRegs:$Rs32),
2729"if ($Pu4) $Rd32 = asrh($Rs32)",
2730tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2731let Inst{7-5} = 0b000;
2732let Inst{13-10} = 0b1000;
2733let Inst{31-21} = 0b01110000001;
2734let isPredicated = 1;
2735let hasNewValue = 1;
2736let opNewValue = 0;
2737let BaseOpcode = "A2_asrh";
2738}
2739def A4_pasrhtnew : HInst<
2740(outs IntRegs:$Rd32),
2741(ins PredRegs:$Pu4, IntRegs:$Rs32),
2742"if ($Pu4.new) $Rd32 = asrh($Rs32)",
2743tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2744let Inst{7-5} = 0b000;
2745let Inst{13-10} = 0b1001;
2746let Inst{31-21} = 0b01110000001;
2747let isPredicated = 1;
2748let hasNewValue = 1;
2749let opNewValue = 0;
2750let isPredicatedNew = 1;
2751let BaseOpcode = "A2_asrh";
2752}
2753def A4_psxtbf : HInst<
2754(outs IntRegs:$Rd32),
2755(ins PredRegs:$Pu4, IntRegs:$Rs32),
2756"if (!$Pu4) $Rd32 = sxtb($Rs32)",
2757tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2758let Inst{7-5} = 0b000;
2759let Inst{13-10} = 0b1010;
2760let Inst{31-21} = 0b01110000101;
2761let isPredicated = 1;
2762let isPredicatedFalse = 1;
2763let hasNewValue = 1;
2764let opNewValue = 0;
2765let BaseOpcode = "A2_sxtb";
2766}
2767def A4_psxtbfnew : HInst<
2768(outs IntRegs:$Rd32),
2769(ins PredRegs:$Pu4, IntRegs:$Rs32),
2770"if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
2771tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2772let Inst{7-5} = 0b000;
2773let Inst{13-10} = 0b1011;
2774let Inst{31-21} = 0b01110000101;
2775let isPredicated = 1;
2776let isPredicatedFalse = 1;
2777let hasNewValue = 1;
2778let opNewValue = 0;
2779let isPredicatedNew = 1;
2780let BaseOpcode = "A2_sxtb";
2781}
2782def A4_psxtbt : HInst<
2783(outs IntRegs:$Rd32),
2784(ins PredRegs:$Pu4, IntRegs:$Rs32),
2785"if ($Pu4) $Rd32 = sxtb($Rs32)",
2786tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2787let Inst{7-5} = 0b000;
2788let Inst{13-10} = 0b1000;
2789let Inst{31-21} = 0b01110000101;
2790let isPredicated = 1;
2791let hasNewValue = 1;
2792let opNewValue = 0;
2793let BaseOpcode = "A2_sxtb";
2794}
2795def A4_psxtbtnew : HInst<
2796(outs IntRegs:$Rd32),
2797(ins PredRegs:$Pu4, IntRegs:$Rs32),
2798"if ($Pu4.new) $Rd32 = sxtb($Rs32)",
2799tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2800let Inst{7-5} = 0b000;
2801let Inst{13-10} = 0b1001;
2802let Inst{31-21} = 0b01110000101;
2803let isPredicated = 1;
2804let hasNewValue = 1;
2805let opNewValue = 0;
2806let isPredicatedNew = 1;
2807let BaseOpcode = "A2_sxtb";
2808}
2809def A4_psxthf : HInst<
2810(outs IntRegs:$Rd32),
2811(ins PredRegs:$Pu4, IntRegs:$Rs32),
2812"if (!$Pu4) $Rd32 = sxth($Rs32)",
2813tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2814let Inst{7-5} = 0b000;
2815let Inst{13-10} = 0b1010;
2816let Inst{31-21} = 0b01110000111;
2817let isPredicated = 1;
2818let isPredicatedFalse = 1;
2819let hasNewValue = 1;
2820let opNewValue = 0;
2821let BaseOpcode = "A2_sxth";
2822}
2823def A4_psxthfnew : HInst<
2824(outs IntRegs:$Rd32),
2825(ins PredRegs:$Pu4, IntRegs:$Rs32),
2826"if (!$Pu4.new) $Rd32 = sxth($Rs32)",
2827tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2828let Inst{7-5} = 0b000;
2829let Inst{13-10} = 0b1011;
2830let Inst{31-21} = 0b01110000111;
2831let isPredicated = 1;
2832let isPredicatedFalse = 1;
2833let hasNewValue = 1;
2834let opNewValue = 0;
2835let isPredicatedNew = 1;
2836let BaseOpcode = "A2_sxth";
2837}
2838def A4_psxtht : HInst<
2839(outs IntRegs:$Rd32),
2840(ins PredRegs:$Pu4, IntRegs:$Rs32),
2841"if ($Pu4) $Rd32 = sxth($Rs32)",
2842tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2843let Inst{7-5} = 0b000;
2844let Inst{13-10} = 0b1000;
2845let Inst{31-21} = 0b01110000111;
2846let isPredicated = 1;
2847let hasNewValue = 1;
2848let opNewValue = 0;
2849let BaseOpcode = "A2_sxth";
2850}
2851def A4_psxthtnew : HInst<
2852(outs IntRegs:$Rd32),
2853(ins PredRegs:$Pu4, IntRegs:$Rs32),
2854"if ($Pu4.new) $Rd32 = sxth($Rs32)",
2855tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2856let Inst{7-5} = 0b000;
2857let Inst{13-10} = 0b1001;
2858let Inst{31-21} = 0b01110000111;
2859let isPredicated = 1;
2860let hasNewValue = 1;
2861let opNewValue = 0;
2862let isPredicatedNew = 1;
2863let BaseOpcode = "A2_sxth";
2864}
2865def A4_pzxtbf : HInst<
2866(outs IntRegs:$Rd32),
2867(ins PredRegs:$Pu4, IntRegs:$Rs32),
2868"if (!$Pu4) $Rd32 = zxtb($Rs32)",
2869tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2870let Inst{7-5} = 0b000;
2871let Inst{13-10} = 0b1010;
2872let Inst{31-21} = 0b01110000100;
2873let isPredicated = 1;
2874let isPredicatedFalse = 1;
2875let hasNewValue = 1;
2876let opNewValue = 0;
2877let BaseOpcode = "A2_zxtb";
2878}
2879def A4_pzxtbfnew : HInst<
2880(outs IntRegs:$Rd32),
2881(ins PredRegs:$Pu4, IntRegs:$Rs32),
2882"if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
2883tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2884let Inst{7-5} = 0b000;
2885let Inst{13-10} = 0b1011;
2886let Inst{31-21} = 0b01110000100;
2887let isPredicated = 1;
2888let isPredicatedFalse = 1;
2889let hasNewValue = 1;
2890let opNewValue = 0;
2891let isPredicatedNew = 1;
2892let BaseOpcode = "A2_zxtb";
2893}
2894def A4_pzxtbt : HInst<
2895(outs IntRegs:$Rd32),
2896(ins PredRegs:$Pu4, IntRegs:$Rs32),
2897"if ($Pu4) $Rd32 = zxtb($Rs32)",
2898tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2899let Inst{7-5} = 0b000;
2900let Inst{13-10} = 0b1000;
2901let Inst{31-21} = 0b01110000100;
2902let isPredicated = 1;
2903let hasNewValue = 1;
2904let opNewValue = 0;
2905let BaseOpcode = "A2_zxtb";
2906}
2907def A4_pzxtbtnew : HInst<
2908(outs IntRegs:$Rd32),
2909(ins PredRegs:$Pu4, IntRegs:$Rs32),
2910"if ($Pu4.new) $Rd32 = zxtb($Rs32)",
2911tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2912let Inst{7-5} = 0b000;
2913let Inst{13-10} = 0b1001;
2914let Inst{31-21} = 0b01110000100;
2915let isPredicated = 1;
2916let hasNewValue = 1;
2917let opNewValue = 0;
2918let isPredicatedNew = 1;
2919let BaseOpcode = "A2_zxtb";
2920}
2921def A4_pzxthf : HInst<
2922(outs IntRegs:$Rd32),
2923(ins PredRegs:$Pu4, IntRegs:$Rs32),
2924"if (!$Pu4) $Rd32 = zxth($Rs32)",
2925tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2926let Inst{7-5} = 0b000;
2927let Inst{13-10} = 0b1010;
2928let Inst{31-21} = 0b01110000110;
2929let isPredicated = 1;
2930let isPredicatedFalse = 1;
2931let hasNewValue = 1;
2932let opNewValue = 0;
2933let BaseOpcode = "A2_zxth";
2934}
2935def A4_pzxthfnew : HInst<
2936(outs IntRegs:$Rd32),
2937(ins PredRegs:$Pu4, IntRegs:$Rs32),
2938"if (!$Pu4.new) $Rd32 = zxth($Rs32)",
2939tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2940let Inst{7-5} = 0b000;
2941let Inst{13-10} = 0b1011;
2942let Inst{31-21} = 0b01110000110;
2943let isPredicated = 1;
2944let isPredicatedFalse = 1;
2945let hasNewValue = 1;
2946let opNewValue = 0;
2947let isPredicatedNew = 1;
2948let BaseOpcode = "A2_zxth";
2949}
2950def A4_pzxtht : HInst<
2951(outs IntRegs:$Rd32),
2952(ins PredRegs:$Pu4, IntRegs:$Rs32),
2953"if ($Pu4) $Rd32 = zxth($Rs32)",
2954tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2955let Inst{7-5} = 0b000;
2956let Inst{13-10} = 0b1000;
2957let Inst{31-21} = 0b01110000110;
2958let isPredicated = 1;
2959let hasNewValue = 1;
2960let opNewValue = 0;
2961let BaseOpcode = "A2_zxth";
2962}
2963def A4_pzxthtnew : HInst<
2964(outs IntRegs:$Rd32),
2965(ins PredRegs:$Pu4, IntRegs:$Rs32),
2966"if ($Pu4.new) $Rd32 = zxth($Rs32)",
2967tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2968let Inst{7-5} = 0b000;
2969let Inst{13-10} = 0b1001;
2970let Inst{31-21} = 0b01110000110;
2971let isPredicated = 1;
2972let hasNewValue = 1;
2973let opNewValue = 0;
2974let isPredicatedNew = 1;
2975let BaseOpcode = "A2_zxth";
2976}
2977def A4_rcmpeq : HInst<
2978(outs IntRegs:$Rd32),
2979(ins IntRegs:$Rs32, IntRegs:$Rt32),
2980"$Rd32 = cmp.eq($Rs32,$Rt32)",
2981tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
2982let Inst{7-5} = 0b000;
2983let Inst{13-13} = 0b0;
2984let Inst{31-21} = 0b11110011010;
2985let hasNewValue = 1;
2986let opNewValue = 0;
2987let CextOpcode = "A4_rcmpeq";
2988let InputType = "reg";
2989let isCommutable = 1;
2990}
2991def A4_rcmpeqi : HInst<
2992(outs IntRegs:$Rd32),
2993(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2994"$Rd32 = cmp.eq($Rs32,#$Ii)",
2995tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
2996let Inst{13-13} = 0b1;
2997let Inst{31-21} = 0b01110011010;
2998let hasNewValue = 1;
2999let opNewValue = 0;
3000let CextOpcode = "A4_rcmpeqi";
3001let InputType = "imm";
3002let isExtendable = 1;
3003let opExtendable = 2;
3004let isExtentSigned = 1;
3005let opExtentBits = 8;
3006let opExtentAlign = 0;
3007}
3008def A4_rcmpneq : HInst<
3009(outs IntRegs:$Rd32),
3010(ins IntRegs:$Rs32, IntRegs:$Rt32),
3011"$Rd32 = !cmp.eq($Rs32,$Rt32)",
3012tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
3013let Inst{7-5} = 0b000;
3014let Inst{13-13} = 0b0;
3015let Inst{31-21} = 0b11110011011;
3016let hasNewValue = 1;
3017let opNewValue = 0;
3018let CextOpcode = "A4_rcmpneq";
3019let InputType = "reg";
3020let isCommutable = 1;
3021}
3022def A4_rcmpneqi : HInst<
3023(outs IntRegs:$Rd32),
3024(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3025"$Rd32 = !cmp.eq($Rs32,#$Ii)",
3026tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
3027let Inst{13-13} = 0b1;
3028let Inst{31-21} = 0b01110011011;
3029let hasNewValue = 1;
3030let opNewValue = 0;
3031let CextOpcode = "A4_rcmpeqi";
3032let InputType = "imm";
3033let isExtendable = 1;
3034let opExtendable = 2;
3035let isExtentSigned = 1;
3036let opExtentBits = 8;
3037let opExtentAlign = 0;
3038}
3039def A4_round_ri : HInst<
3040(outs IntRegs:$Rd32),
3041(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3042"$Rd32 = round($Rs32,#$Ii)",
3043tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3044let Inst{7-5} = 0b100;
3045let Inst{13-13} = 0b0;
3046let Inst{31-21} = 0b10001100111;
3047let hasNewValue = 1;
3048let opNewValue = 0;
3049let prefersSlot3 = 1;
3050}
3051def A4_round_ri_sat : HInst<
3052(outs IntRegs:$Rd32),
3053(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3054"$Rd32 = round($Rs32,#$Ii):sat",
3055tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3056let Inst{7-5} = 0b110;
3057let Inst{13-13} = 0b0;
3058let Inst{31-21} = 0b10001100111;
3059let hasNewValue = 1;
3060let opNewValue = 0;
3061let prefersSlot3 = 1;
3062let Defs = [USR_OVF];
3063}
3064def A4_round_rr : HInst<
3065(outs IntRegs:$Rd32),
3066(ins IntRegs:$Rs32, IntRegs:$Rt32),
3067"$Rd32 = round($Rs32,$Rt32)",
3068tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3069let Inst{7-5} = 0b100;
3070let Inst{13-13} = 0b0;
3071let Inst{31-21} = 0b11000110110;
3072let hasNewValue = 1;
3073let opNewValue = 0;
3074let prefersSlot3 = 1;
3075}
3076def A4_round_rr_sat : HInst<
3077(outs IntRegs:$Rd32),
3078(ins IntRegs:$Rs32, IntRegs:$Rt32),
3079"$Rd32 = round($Rs32,$Rt32):sat",
3080tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3081let Inst{7-5} = 0b110;
3082let Inst{13-13} = 0b0;
3083let Inst{31-21} = 0b11000110110;
3084let hasNewValue = 1;
3085let opNewValue = 0;
3086let prefersSlot3 = 1;
3087let Defs = [USR_OVF];
3088}
3089def A4_subp_c : HInst<
3090(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
3091(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
3092"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
3093tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
3094let Inst{7-7} = 0b0;
3095let Inst{13-13} = 0b0;
3096let Inst{31-21} = 0b11000010111;
3097let isPredicateLate = 1;
3098let Constraints = "$Px4 = $Px4in";
3099}
3100def A4_tfrcpp : HInst<
3101(outs DoubleRegs:$Rdd32),
3102(ins CtrRegs64:$Css32),
3103"$Rdd32 = $Css32",
3104tc_7476d766, TypeCR>, Enc_667b39 {
3105let Inst{13-5} = 0b000000000;
3106let Inst{31-21} = 0b01101000000;
3107}
3108def A4_tfrpcp : HInst<
3109(outs CtrRegs64:$Cdd32),
3110(ins DoubleRegs:$Rss32),
3111"$Cdd32 = $Rss32",
3112tc_49fdfd4b, TypeCR>, Enc_0ed752 {
3113let Inst{13-5} = 0b000000000;
3114let Inst{31-21} = 0b01100011001;
3115}
3116def A4_tlbmatch : HInst<
3117(outs PredRegs:$Pd4),
3118(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3119"$Pd4 = tlbmatch($Rss32,$Rt32)",
3120tc_d68dca5c, TypeALU64>, Enc_03833b {
3121let Inst{7-2} = 0b011000;
3122let Inst{13-13} = 0b1;
3123let Inst{31-21} = 0b11010010000;
3124let isPredicateLate = 1;
3125}
3126def A4_vcmpbeq_any : HInst<
3127(outs PredRegs:$Pd4),
3128(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3129"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
3130tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3131let Inst{7-2} = 0b000000;
3132let Inst{13-13} = 0b1;
3133let Inst{31-21} = 0b11010010000;
3134}
3135def A4_vcmpbeqi : HInst<
3136(outs PredRegs:$Pd4),
3137(ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
3138"$Pd4 = vcmpb.eq($Rss32,#$Ii)",
3139tc_a1297125, TypeALU64>, Enc_0d8adb {
3140let Inst{4-2} = 0b000;
3141let Inst{13-13} = 0b0;
3142let Inst{31-21} = 0b11011100000;
3143}
3144def A4_vcmpbgt : HInst<
3145(outs PredRegs:$Pd4),
3146(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3147"$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
3148tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3149let Inst{7-2} = 0b010000;
3150let Inst{13-13} = 0b1;
3151let Inst{31-21} = 0b11010010000;
3152}
3153def A4_vcmpbgti : HInst<
3154(outs PredRegs:$Pd4),
3155(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3156"$Pd4 = vcmpb.gt($Rss32,#$Ii)",
3157tc_a1297125, TypeALU64>, Enc_0d8adb {
3158let Inst{4-2} = 0b000;
3159let Inst{13-13} = 0b0;
3160let Inst{31-21} = 0b11011100001;
3161}
3162def A4_vcmpbgtui : HInst<
3163(outs PredRegs:$Pd4),
3164(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3165"$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
3166tc_a1297125, TypeALU64>, Enc_3680c2 {
3167let Inst{4-2} = 0b000;
3168let Inst{13-12} = 0b00;
3169let Inst{31-21} = 0b11011100010;
3170}
3171def A4_vcmpheqi : HInst<
3172(outs PredRegs:$Pd4),
3173(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3174"$Pd4 = vcmph.eq($Rss32,#$Ii)",
3175tc_a1297125, TypeALU64>, Enc_0d8adb {
3176let Inst{4-2} = 0b010;
3177let Inst{13-13} = 0b0;
3178let Inst{31-21} = 0b11011100000;
3179}
3180def A4_vcmphgti : HInst<
3181(outs PredRegs:$Pd4),
3182(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3183"$Pd4 = vcmph.gt($Rss32,#$Ii)",
3184tc_a1297125, TypeALU64>, Enc_0d8adb {
3185let Inst{4-2} = 0b010;
3186let Inst{13-13} = 0b0;
3187let Inst{31-21} = 0b11011100001;
3188}
3189def A4_vcmphgtui : HInst<
3190(outs PredRegs:$Pd4),
3191(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3192"$Pd4 = vcmph.gtu($Rss32,#$Ii)",
3193tc_a1297125, TypeALU64>, Enc_3680c2 {
3194let Inst{4-2} = 0b010;
3195let Inst{13-12} = 0b00;
3196let Inst{31-21} = 0b11011100010;
3197}
3198def A4_vcmpweqi : HInst<
3199(outs PredRegs:$Pd4),
3200(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3201"$Pd4 = vcmpw.eq($Rss32,#$Ii)",
3202tc_a1297125, TypeALU64>, Enc_0d8adb {
3203let Inst{4-2} = 0b100;
3204let Inst{13-13} = 0b0;
3205let Inst{31-21} = 0b11011100000;
3206}
3207def A4_vcmpwgti : HInst<
3208(outs PredRegs:$Pd4),
3209(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3210"$Pd4 = vcmpw.gt($Rss32,#$Ii)",
3211tc_a1297125, TypeALU64>, Enc_0d8adb {
3212let Inst{4-2} = 0b100;
3213let Inst{13-13} = 0b0;
3214let Inst{31-21} = 0b11011100001;
3215}
3216def A4_vcmpwgtui : HInst<
3217(outs PredRegs:$Pd4),
3218(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3219"$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
3220tc_a1297125, TypeALU64>, Enc_3680c2 {
3221let Inst{4-2} = 0b100;
3222let Inst{13-12} = 0b00;
3223let Inst{31-21} = 0b11011100010;
3224}
3225def A4_vrmaxh : HInst<
3226(outs DoubleRegs:$Rxx32),
3227(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3228"$Rxx32 = vrmaxh($Rss32,$Ru32)",
3229tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3230let Inst{7-5} = 0b001;
3231let Inst{13-13} = 0b0;
3232let Inst{31-21} = 0b11001011001;
3233let prefersSlot3 = 1;
3234let Constraints = "$Rxx32 = $Rxx32in";
3235}
3236def A4_vrmaxuh : HInst<
3237(outs DoubleRegs:$Rxx32),
3238(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3239"$Rxx32 = vrmaxuh($Rss32,$Ru32)",
3240tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3241let Inst{7-5} = 0b001;
3242let Inst{13-13} = 0b1;
3243let Inst{31-21} = 0b11001011001;
3244let prefersSlot3 = 1;
3245let Constraints = "$Rxx32 = $Rxx32in";
3246}
3247def A4_vrmaxuw : HInst<
3248(outs DoubleRegs:$Rxx32),
3249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3250"$Rxx32 = vrmaxuw($Rss32,$Ru32)",
3251tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3252let Inst{7-5} = 0b010;
3253let Inst{13-13} = 0b1;
3254let Inst{31-21} = 0b11001011001;
3255let prefersSlot3 = 1;
3256let Constraints = "$Rxx32 = $Rxx32in";
3257}
3258def A4_vrmaxw : HInst<
3259(outs DoubleRegs:$Rxx32),
3260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3261"$Rxx32 = vrmaxw($Rss32,$Ru32)",
3262tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3263let Inst{7-5} = 0b010;
3264let Inst{13-13} = 0b0;
3265let Inst{31-21} = 0b11001011001;
3266let prefersSlot3 = 1;
3267let Constraints = "$Rxx32 = $Rxx32in";
3268}
3269def A4_vrminh : HInst<
3270(outs DoubleRegs:$Rxx32),
3271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3272"$Rxx32 = vrminh($Rss32,$Ru32)",
3273tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3274let Inst{7-5} = 0b101;
3275let Inst{13-13} = 0b0;
3276let Inst{31-21} = 0b11001011001;
3277let prefersSlot3 = 1;
3278let Constraints = "$Rxx32 = $Rxx32in";
3279}
3280def A4_vrminuh : HInst<
3281(outs DoubleRegs:$Rxx32),
3282(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3283"$Rxx32 = vrminuh($Rss32,$Ru32)",
3284tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3285let Inst{7-5} = 0b101;
3286let Inst{13-13} = 0b1;
3287let Inst{31-21} = 0b11001011001;
3288let prefersSlot3 = 1;
3289let Constraints = "$Rxx32 = $Rxx32in";
3290}
3291def A4_vrminuw : HInst<
3292(outs DoubleRegs:$Rxx32),
3293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3294"$Rxx32 = vrminuw($Rss32,$Ru32)",
3295tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3296let Inst{7-5} = 0b110;
3297let Inst{13-13} = 0b1;
3298let Inst{31-21} = 0b11001011001;
3299let prefersSlot3 = 1;
3300let Constraints = "$Rxx32 = $Rxx32in";
3301}
3302def A4_vrminw : HInst<
3303(outs DoubleRegs:$Rxx32),
3304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3305"$Rxx32 = vrminw($Rss32,$Ru32)",
3306tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3307let Inst{7-5} = 0b110;
3308let Inst{13-13} = 0b0;
3309let Inst{31-21} = 0b11001011001;
3310let prefersSlot3 = 1;
3311let Constraints = "$Rxx32 = $Rxx32in";
3312}
3313def A5_ACS : HInst<
3314(outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
3315(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3316"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
3317tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> {
3318let Inst{7-7} = 0b0;
3319let Inst{13-13} = 0b0;
3320let Inst{31-21} = 0b11101010101;
3321let isPredicateLate = 1;
3322let prefersSlot3 = 1;
3323let Defs = [USR_OVF];
3324let Constraints = "$Rxx32 = $Rxx32in";
3325}
3326def A5_vaddhubs : HInst<
3327(outs IntRegs:$Rd32),
3328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3329"$Rd32 = vaddhub($Rss32,$Rtt32):sat",
3330tc_0dfac0a7, TypeS_3op>, Enc_d2216a {
3331let Inst{7-5} = 0b001;
3332let Inst{13-13} = 0b0;
3333let Inst{31-21} = 0b11000001010;
3334let hasNewValue = 1;
3335let opNewValue = 0;
3336let prefersSlot3 = 1;
3337let Defs = [USR_OVF];
3338}
3339def A6_vcmpbeq_notany : HInst<
3340(outs PredRegs:$Pd4),
3341(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3342"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
3343tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> {
3344let Inst{7-2} = 0b001000;
3345let Inst{13-13} = 0b1;
3346let Inst{31-21} = 0b11010010000;
3347}
3348def A6_vminub_RdP : HInst<
3349(outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
3350(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
3351"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
3352tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> {
3353let Inst{7-7} = 0b0;
3354let Inst{13-13} = 0b0;
3355let Inst{31-21} = 0b11101010111;
3356let isPredicateLate = 1;
3357let prefersSlot3 = 1;
3358}
3359def A7_clip : HInst<
3360(outs IntRegs:$Rd32),
3361(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3362"$Rd32 = clip($Rs32,#$Ii)",
3363tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> {
3364let Inst{7-5} = 0b101;
3365let Inst{13-13} = 0b0;
3366let Inst{31-21} = 0b10001000110;
3367let hasNewValue = 1;
3368let opNewValue = 0;
3369}
3370def A7_croundd_ri : HInst<
3371(outs DoubleRegs:$Rdd32),
3372(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
3373"$Rdd32 = cround($Rss32,#$Ii)",
3374tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> {
3375let Inst{7-5} = 0b010;
3376let Inst{31-21} = 0b10001100111;
3377let prefersSlot3 = 1;
3378}
3379def A7_croundd_rr : HInst<
3380(outs DoubleRegs:$Rdd32),
3381(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3382"$Rdd32 = cround($Rss32,$Rt32)",
3383tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> {
3384let Inst{7-5} = 0b010;
3385let Inst{13-13} = 0b0;
3386let Inst{31-21} = 0b11000110110;
3387let prefersSlot3 = 1;
3388}
3389def A7_vclip : HInst<
3390(outs DoubleRegs:$Rdd32),
3391(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
3392"$Rdd32 = vclip($Rss32,#$Ii)",
3393tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> {
3394let Inst{7-5} = 0b110;
3395let Inst{13-13} = 0b0;
3396let Inst{31-21} = 0b10001000110;
3397}
3398def C2_all8 : HInst<
3399(outs PredRegs:$Pd4),
3400(ins PredRegs:$Ps4),
3401"$Pd4 = all8($Ps4)",
3402tc_151bf368, TypeCR>, Enc_65d691 {
3403let Inst{13-2} = 0b000000000000;
3404let Inst{31-18} = 0b01101011101000;
3405}
3406def C2_and : HInst<
3407(outs PredRegs:$Pd4),
3408(ins PredRegs:$Pt4, PredRegs:$Ps4),
3409"$Pd4 = and($Pt4,$Ps4)",
3410tc_651cbe02, TypeCR>, Enc_454a26 {
3411let Inst{7-2} = 0b000000;
3412let Inst{13-10} = 0b0000;
3413let Inst{31-18} = 0b01101011000000;
3414}
3415def C2_andn : HInst<
3416(outs PredRegs:$Pd4),
3417(ins PredRegs:$Pt4, PredRegs:$Ps4),
3418"$Pd4 = and($Pt4,!$Ps4)",
3419tc_651cbe02, TypeCR>, Enc_454a26 {
3420let Inst{7-2} = 0b000000;
3421let Inst{13-10} = 0b0000;
3422let Inst{31-18} = 0b01101011011000;
3423}
3424def C2_any8 : HInst<
3425(outs PredRegs:$Pd4),
3426(ins PredRegs:$Ps4),
3427"$Pd4 = any8($Ps4)",
3428tc_151bf368, TypeCR>, Enc_65d691 {
3429let Inst{13-2} = 0b000000000000;
3430let Inst{31-18} = 0b01101011100000;
3431}
3432def C2_bitsclr : HInst<
3433(outs PredRegs:$Pd4),
3434(ins IntRegs:$Rs32, IntRegs:$Rt32),
3435"$Pd4 = bitsclr($Rs32,$Rt32)",
3436tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3437let Inst{7-2} = 0b000000;
3438let Inst{13-13} = 0b0;
3439let Inst{31-21} = 0b11000111100;
3440}
3441def C2_bitsclri : HInst<
3442(outs PredRegs:$Pd4),
3443(ins IntRegs:$Rs32, u6_0Imm:$Ii),
3444"$Pd4 = bitsclr($Rs32,#$Ii)",
3445tc_a1297125, TypeS_2op>, Enc_5d6c34 {
3446let Inst{7-2} = 0b000000;
3447let Inst{31-21} = 0b10000101100;
3448}
3449def C2_bitsset : HInst<
3450(outs PredRegs:$Pd4),
3451(ins IntRegs:$Rs32, IntRegs:$Rt32),
3452"$Pd4 = bitsset($Rs32,$Rt32)",
3453tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3454let Inst{7-2} = 0b000000;
3455let Inst{13-13} = 0b0;
3456let Inst{31-21} = 0b11000111010;
3457}
3458def C2_ccombinewf : HInst<
3459(outs DoubleRegs:$Rdd32),
3460(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3461"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3462tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3463let Inst{7-7} = 0b1;
3464let Inst{13-13} = 0b0;
3465let Inst{31-21} = 0b11111101000;
3466let isPredicated = 1;
3467let isPredicatedFalse = 1;
3468let BaseOpcode = "A2_combinew";
3469}
3470def C2_ccombinewnewf : HInst<
3471(outs DoubleRegs:$Rdd32),
3472(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3473"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3474tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3475let Inst{7-7} = 0b1;
3476let Inst{13-13} = 0b1;
3477let Inst{31-21} = 0b11111101000;
3478let isPredicated = 1;
3479let isPredicatedFalse = 1;
3480let isPredicatedNew = 1;
3481let BaseOpcode = "A2_combinew";
3482}
3483def C2_ccombinewnewt : HInst<
3484(outs DoubleRegs:$Rdd32),
3485(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3486"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3487tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3488let Inst{7-7} = 0b0;
3489let Inst{13-13} = 0b1;
3490let Inst{31-21} = 0b11111101000;
3491let isPredicated = 1;
3492let isPredicatedNew = 1;
3493let BaseOpcode = "A2_combinew";
3494}
3495def C2_ccombinewt : HInst<
3496(outs DoubleRegs:$Rdd32),
3497(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3498"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3499tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3500let Inst{7-7} = 0b0;
3501let Inst{13-13} = 0b0;
3502let Inst{31-21} = 0b11111101000;
3503let isPredicated = 1;
3504let BaseOpcode = "A2_combinew";
3505}
3506def C2_cmoveif : HInst<
3507(outs IntRegs:$Rd32),
3508(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3509"if (!$Pu4) $Rd32 = #$Ii",
3510tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3511let Inst{13-13} = 0b0;
3512let Inst{20-20} = 0b0;
3513let Inst{31-23} = 0b011111101;
3514let isPredicated = 1;
3515let isPredicatedFalse = 1;
3516let hasNewValue = 1;
3517let opNewValue = 0;
3518let BaseOpcode = "A2_tfrsi";
3519let CextOpcode = "A2_tfr";
3520let InputType = "imm";
3521let isMoveImm = 1;
3522let isExtendable = 1;
3523let opExtendable = 2;
3524let isExtentSigned = 1;
3525let opExtentBits = 12;
3526let opExtentAlign = 0;
3527}
3528def C2_cmoveit : HInst<
3529(outs IntRegs:$Rd32),
3530(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3531"if ($Pu4) $Rd32 = #$Ii",
3532tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3533let Inst{13-13} = 0b0;
3534let Inst{20-20} = 0b0;
3535let Inst{31-23} = 0b011111100;
3536let isPredicated = 1;
3537let hasNewValue = 1;
3538let opNewValue = 0;
3539let BaseOpcode = "A2_tfrsi";
3540let CextOpcode = "A2_tfr";
3541let InputType = "imm";
3542let isMoveImm = 1;
3543let isExtendable = 1;
3544let opExtendable = 2;
3545let isExtentSigned = 1;
3546let opExtentBits = 12;
3547let opExtentAlign = 0;
3548}
3549def C2_cmovenewif : HInst<
3550(outs IntRegs:$Rd32),
3551(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3552"if (!$Pu4.new) $Rd32 = #$Ii",
3553tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3554let Inst{13-13} = 0b1;
3555let Inst{20-20} = 0b0;
3556let Inst{31-23} = 0b011111101;
3557let isPredicated = 1;
3558let isPredicatedFalse = 1;
3559let hasNewValue = 1;
3560let opNewValue = 0;
3561let isPredicatedNew = 1;
3562let BaseOpcode = "A2_tfrsi";
3563let CextOpcode = "A2_tfr";
3564let InputType = "imm";
3565let isMoveImm = 1;
3566let isExtendable = 1;
3567let opExtendable = 2;
3568let isExtentSigned = 1;
3569let opExtentBits = 12;
3570let opExtentAlign = 0;
3571}
3572def C2_cmovenewit : HInst<
3573(outs IntRegs:$Rd32),
3574(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3575"if ($Pu4.new) $Rd32 = #$Ii",
3576tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3577let Inst{13-13} = 0b1;
3578let Inst{20-20} = 0b0;
3579let Inst{31-23} = 0b011111100;
3580let isPredicated = 1;
3581let hasNewValue = 1;
3582let opNewValue = 0;
3583let isPredicatedNew = 1;
3584let BaseOpcode = "A2_tfrsi";
3585let CextOpcode = "A2_tfr";
3586let InputType = "imm";
3587let isMoveImm = 1;
3588let isExtendable = 1;
3589let opExtendable = 2;
3590let isExtentSigned = 1;
3591let opExtentBits = 12;
3592let opExtentAlign = 0;
3593}
3594def C2_cmpeq : HInst<
3595(outs PredRegs:$Pd4),
3596(ins IntRegs:$Rs32, IntRegs:$Rt32),
3597"$Pd4 = cmp.eq($Rs32,$Rt32)",
3598tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3599let Inst{7-2} = 0b000000;
3600let Inst{13-13} = 0b0;
3601let Inst{31-21} = 0b11110010000;
3602let CextOpcode = "C2_cmpeq";
3603let InputType = "reg";
3604let isCommutable = 1;
3605let isCompare = 1;
3606}
3607def C2_cmpeqi : HInst<
3608(outs PredRegs:$Pd4),
3609(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3610"$Pd4 = cmp.eq($Rs32,#$Ii)",
3611tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3612let Inst{4-2} = 0b000;
3613let Inst{31-22} = 0b0111010100;
3614let CextOpcode = "C2_cmpeq";
3615let InputType = "imm";
3616let isCompare = 1;
3617let isExtendable = 1;
3618let opExtendable = 2;
3619let isExtentSigned = 1;
3620let opExtentBits = 10;
3621let opExtentAlign = 0;
3622}
3623def C2_cmpeqp : HInst<
3624(outs PredRegs:$Pd4),
3625(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3626"$Pd4 = cmp.eq($Rss32,$Rtt32)",
3627tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3628let Inst{7-2} = 0b000000;
3629let Inst{13-13} = 0b0;
3630let Inst{31-21} = 0b11010010100;
3631let isCommutable = 1;
3632let isCompare = 1;
3633}
3634def C2_cmpgei : HInst<
3635(outs PredRegs:$Pd4),
3636(ins IntRegs:$Rs32, s8_0Imm:$Ii),
3637"$Pd4 = cmp.ge($Rs32,#$Ii)",
3638tc_d33e5eee, TypeALU32_2op> {
3639let isCompare = 1;
3640let isPseudo = 1;
3641}
3642def C2_cmpgeui : HInst<
3643(outs PredRegs:$Pd4),
3644(ins IntRegs:$Rs32, u8_0Imm:$Ii),
3645"$Pd4 = cmp.geu($Rs32,#$Ii)",
3646tc_d33e5eee, TypeALU32_2op> {
3647let isCompare = 1;
3648let isPseudo = 1;
3649}
3650def C2_cmpgt : HInst<
3651(outs PredRegs:$Pd4),
3652(ins IntRegs:$Rs32, IntRegs:$Rt32),
3653"$Pd4 = cmp.gt($Rs32,$Rt32)",
3654tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3655let Inst{7-2} = 0b000000;
3656let Inst{13-13} = 0b0;
3657let Inst{31-21} = 0b11110010010;
3658let CextOpcode = "C2_cmpgt";
3659let InputType = "reg";
3660let isCompare = 1;
3661}
3662def C2_cmpgti : HInst<
3663(outs PredRegs:$Pd4),
3664(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3665"$Pd4 = cmp.gt($Rs32,#$Ii)",
3666tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3667let Inst{4-2} = 0b000;
3668let Inst{31-22} = 0b0111010101;
3669let CextOpcode = "C2_cmpgt";
3670let InputType = "imm";
3671let isCompare = 1;
3672let isExtendable = 1;
3673let opExtendable = 2;
3674let isExtentSigned = 1;
3675let opExtentBits = 10;
3676let opExtentAlign = 0;
3677}
3678def C2_cmpgtp : HInst<
3679(outs PredRegs:$Pd4),
3680(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3681"$Pd4 = cmp.gt($Rss32,$Rtt32)",
3682tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3683let Inst{7-2} = 0b010000;
3684let Inst{13-13} = 0b0;
3685let Inst{31-21} = 0b11010010100;
3686let isCompare = 1;
3687}
3688def C2_cmpgtu : HInst<
3689(outs PredRegs:$Pd4),
3690(ins IntRegs:$Rs32, IntRegs:$Rt32),
3691"$Pd4 = cmp.gtu($Rs32,$Rt32)",
3692tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3693let Inst{7-2} = 0b000000;
3694let Inst{13-13} = 0b0;
3695let Inst{31-21} = 0b11110010011;
3696let CextOpcode = "C2_cmpgtu";
3697let InputType = "reg";
3698let isCompare = 1;
3699}
3700def C2_cmpgtui : HInst<
3701(outs PredRegs:$Pd4),
3702(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3703"$Pd4 = cmp.gtu($Rs32,#$Ii)",
3704tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3705let Inst{4-2} = 0b000;
3706let Inst{31-21} = 0b01110101100;
3707let CextOpcode = "C2_cmpgtu";
3708let InputType = "imm";
3709let isCompare = 1;
3710let isExtendable = 1;
3711let opExtendable = 2;
3712let isExtentSigned = 0;
3713let opExtentBits = 9;
3714let opExtentAlign = 0;
3715}
3716def C2_cmpgtup : HInst<
3717(outs PredRegs:$Pd4),
3718(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3719"$Pd4 = cmp.gtu($Rss32,$Rtt32)",
3720tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3721let Inst{7-2} = 0b100000;
3722let Inst{13-13} = 0b0;
3723let Inst{31-21} = 0b11010010100;
3724let isCompare = 1;
3725}
3726def C2_cmplt : HInst<
3727(outs PredRegs:$Pd4),
3728(ins IntRegs:$Rs32, IntRegs:$Rt32),
3729"$Pd4 = cmp.lt($Rs32,$Rt32)",
3730tc_d33e5eee, TypeALU32_3op> {
3731let isCompare = 1;
3732let isPseudo = 1;
3733let isCodeGenOnly = 1;
3734}
3735def C2_cmpltu : HInst<
3736(outs PredRegs:$Pd4),
3737(ins IntRegs:$Rs32, IntRegs:$Rt32),
3738"$Pd4 = cmp.ltu($Rs32,$Rt32)",
3739tc_d33e5eee, TypeALU32_3op> {
3740let isCompare = 1;
3741let isPseudo = 1;
3742let isCodeGenOnly = 1;
3743}
3744def C2_mask : HInst<
3745(outs DoubleRegs:$Rdd32),
3746(ins PredRegs:$Pt4),
3747"$Rdd32 = mask($Pt4)",
3748tc_9f6cd987, TypeS_2op>, Enc_78e566 {
3749let Inst{7-5} = 0b000;
3750let Inst{13-10} = 0b0000;
3751let Inst{31-16} = 0b1000011000000000;
3752}
3753def C2_mux : HInst<
3754(outs IntRegs:$Rd32),
3755(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3756"$Rd32 = mux($Pu4,$Rs32,$Rt32)",
3757tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 {
3758let Inst{7-7} = 0b0;
3759let Inst{13-13} = 0b0;
3760let Inst{31-21} = 0b11110100000;
3761let hasNewValue = 1;
3762let opNewValue = 0;
3763let InputType = "reg";
3764}
3765def C2_muxii : HInst<
3766(outs IntRegs:$Rd32),
3767(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
3768"$Rd32 = mux($Pu4,#$Ii,#$II)",
3769tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d {
3770let Inst{31-25} = 0b0111101;
3771let hasNewValue = 1;
3772let opNewValue = 0;
3773let isExtendable = 1;
3774let opExtendable = 2;
3775let isExtentSigned = 1;
3776let opExtentBits = 8;
3777let opExtentAlign = 0;
3778}
3779def C2_muxir : HInst<
3780(outs IntRegs:$Rd32),
3781(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
3782"$Rd32 = mux($Pu4,$Rs32,#$Ii)",
3783tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3784let Inst{13-13} = 0b0;
3785let Inst{31-23} = 0b011100110;
3786let hasNewValue = 1;
3787let opNewValue = 0;
3788let InputType = "imm";
3789let isExtendable = 1;
3790let opExtendable = 3;
3791let isExtentSigned = 1;
3792let opExtentBits = 8;
3793let opExtentAlign = 0;
3794}
3795def C2_muxri : HInst<
3796(outs IntRegs:$Rd32),
3797(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
3798"$Rd32 = mux($Pu4,#$Ii,$Rs32)",
3799tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3800let Inst{13-13} = 0b0;
3801let Inst{31-23} = 0b011100111;
3802let hasNewValue = 1;
3803let opNewValue = 0;
3804let InputType = "imm";
3805let isExtendable = 1;
3806let opExtendable = 2;
3807let isExtentSigned = 1;
3808let opExtentBits = 8;
3809let opExtentAlign = 0;
3810}
3811def C2_not : HInst<
3812(outs PredRegs:$Pd4),
3813(ins PredRegs:$Ps4),
3814"$Pd4 = not($Ps4)",
3815tc_151bf368, TypeCR>, Enc_65d691 {
3816let Inst{13-2} = 0b000000000000;
3817let Inst{31-18} = 0b01101011110000;
3818}
3819def C2_or : HInst<
3820(outs PredRegs:$Pd4),
3821(ins PredRegs:$Pt4, PredRegs:$Ps4),
3822"$Pd4 = or($Pt4,$Ps4)",
3823tc_651cbe02, TypeCR>, Enc_454a26 {
3824let Inst{7-2} = 0b000000;
3825let Inst{13-10} = 0b0000;
3826let Inst{31-18} = 0b01101011001000;
3827}
3828def C2_orn : HInst<
3829(outs PredRegs:$Pd4),
3830(ins PredRegs:$Pt4, PredRegs:$Ps4),
3831"$Pd4 = or($Pt4,!$Ps4)",
3832tc_651cbe02, TypeCR>, Enc_454a26 {
3833let Inst{7-2} = 0b000000;
3834let Inst{13-10} = 0b0000;
3835let Inst{31-18} = 0b01101011111000;
3836}
3837def C2_pxfer_map : HInst<
3838(outs PredRegs:$Pd4),
3839(ins PredRegs:$Ps4),
3840"$Pd4 = $Ps4",
3841tc_651cbe02, TypeMAPPING> {
3842let isPseudo = 1;
3843let isCodeGenOnly = 1;
3844}
3845def C2_tfrpr : HInst<
3846(outs IntRegs:$Rd32),
3847(ins PredRegs:$Ps4),
3848"$Rd32 = $Ps4",
3849tc_9f6cd987, TypeS_2op>, Enc_f5e933 {
3850let Inst{13-5} = 0b000000000;
3851let Inst{31-18} = 0b10001001010000;
3852let hasNewValue = 1;
3853let opNewValue = 0;
3854}
3855def C2_tfrrp : HInst<
3856(outs PredRegs:$Pd4),
3857(ins IntRegs:$Rs32),
3858"$Pd4 = $Rs32",
3859tc_55b33fda, TypeS_2op>, Enc_48b75f {
3860let Inst{13-2} = 0b000000000000;
3861let Inst{31-21} = 0b10000101010;
3862}
3863def C2_vitpack : HInst<
3864(outs IntRegs:$Rd32),
3865(ins PredRegs:$Ps4, PredRegs:$Pt4),
3866"$Rd32 = vitpack($Ps4,$Pt4)",
3867tc_f34c1c21, TypeS_2op>, Enc_527412 {
3868let Inst{7-5} = 0b000;
3869let Inst{13-10} = 0b0000;
3870let Inst{31-18} = 0b10001001000000;
3871let hasNewValue = 1;
3872let opNewValue = 0;
3873let prefersSlot3 = 1;
3874}
3875def C2_vmux : HInst<
3876(outs DoubleRegs:$Rdd32),
3877(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3878"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
3879tc_6fc5dbea, TypeALU64>, Enc_329361 {
3880let Inst{7-7} = 0b0;
3881let Inst{13-13} = 0b0;
3882let Inst{31-21} = 0b11010001000;
3883}
3884def C2_xor : HInst<
3885(outs PredRegs:$Pd4),
3886(ins PredRegs:$Ps4, PredRegs:$Pt4),
3887"$Pd4 = xor($Ps4,$Pt4)",
3888tc_651cbe02, TypeCR>, Enc_284ebb {
3889let Inst{7-2} = 0b000000;
3890let Inst{13-10} = 0b0000;
3891let Inst{31-18} = 0b01101011010000;
3892}
3893def C4_addipc : HInst<
3894(outs IntRegs:$Rd32),
3895(ins u32_0Imm:$Ii),
3896"$Rd32 = add(pc,#$Ii)",
3897tc_3edca78f, TypeCR>, Enc_607661 {
3898let Inst{6-5} = 0b00;
3899let Inst{13-13} = 0b0;
3900let Inst{31-16} = 0b0110101001001001;
3901let hasNewValue = 1;
3902let opNewValue = 0;
3903let isExtendable = 1;
3904let opExtendable = 1;
3905let isExtentSigned = 0;
3906let opExtentBits = 6;
3907let opExtentAlign = 0;
3908}
3909def C4_and_and : HInst<
3910(outs PredRegs:$Pd4),
3911(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3912"$Pd4 = and($Ps4,and($Pt4,$Pu4))",
3913tc_a7a13fac, TypeCR>, Enc_9ac432 {
3914let Inst{5-2} = 0b0000;
3915let Inst{13-10} = 0b0000;
3916let Inst{31-18} = 0b01101011000100;
3917}
3918def C4_and_andn : HInst<
3919(outs PredRegs:$Pd4),
3920(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3921"$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
3922tc_a7a13fac, TypeCR>, Enc_9ac432 {
3923let Inst{5-2} = 0b0000;
3924let Inst{13-10} = 0b0000;
3925let Inst{31-18} = 0b01101011100100;
3926}
3927def C4_and_or : HInst<
3928(outs PredRegs:$Pd4),
3929(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3930"$Pd4 = and($Ps4,or($Pt4,$Pu4))",
3931tc_a7a13fac, TypeCR>, Enc_9ac432 {
3932let Inst{5-2} = 0b0000;
3933let Inst{13-10} = 0b0000;
3934let Inst{31-18} = 0b01101011001100;
3935}
3936def C4_and_orn : HInst<
3937(outs PredRegs:$Pd4),
3938(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3939"$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
3940tc_a7a13fac, TypeCR>, Enc_9ac432 {
3941let Inst{5-2} = 0b0000;
3942let Inst{13-10} = 0b0000;
3943let Inst{31-18} = 0b01101011101100;
3944}
3945def C4_cmplte : HInst<
3946(outs PredRegs:$Pd4),
3947(ins IntRegs:$Rs32, IntRegs:$Rt32),
3948"$Pd4 = !cmp.gt($Rs32,$Rt32)",
3949tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3950let Inst{7-2} = 0b000100;
3951let Inst{13-13} = 0b0;
3952let Inst{31-21} = 0b11110010010;
3953let CextOpcode = "C4_cmplte";
3954let InputType = "reg";
3955let isCompare = 1;
3956}
3957def C4_cmpltei : HInst<
3958(outs PredRegs:$Pd4),
3959(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3960"$Pd4 = !cmp.gt($Rs32,#$Ii)",
3961tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3962let Inst{4-2} = 0b100;
3963let Inst{31-22} = 0b0111010101;
3964let CextOpcode = "C4_cmplte";
3965let InputType = "imm";
3966let isCompare = 1;
3967let isExtendable = 1;
3968let opExtendable = 2;
3969let isExtentSigned = 1;
3970let opExtentBits = 10;
3971let opExtentAlign = 0;
3972}
3973def C4_cmplteu : HInst<
3974(outs PredRegs:$Pd4),
3975(ins IntRegs:$Rs32, IntRegs:$Rt32),
3976"$Pd4 = !cmp.gtu($Rs32,$Rt32)",
3977tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3978let Inst{7-2} = 0b000100;
3979let Inst{13-13} = 0b0;
3980let Inst{31-21} = 0b11110010011;
3981let CextOpcode = "C4_cmplteu";
3982let InputType = "reg";
3983let isCompare = 1;
3984}
3985def C4_cmplteui : HInst<
3986(outs PredRegs:$Pd4),
3987(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3988"$Pd4 = !cmp.gtu($Rs32,#$Ii)",
3989tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3990let Inst{4-2} = 0b100;
3991let Inst{31-21} = 0b01110101100;
3992let CextOpcode = "C4_cmplteu";
3993let InputType = "imm";
3994let isCompare = 1;
3995let isExtendable = 1;
3996let opExtendable = 2;
3997let isExtentSigned = 0;
3998let opExtentBits = 9;
3999let opExtentAlign = 0;
4000}
4001def C4_cmpneq : HInst<
4002(outs PredRegs:$Pd4),
4003(ins IntRegs:$Rs32, IntRegs:$Rt32),
4004"$Pd4 = !cmp.eq($Rs32,$Rt32)",
4005tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
4006let Inst{7-2} = 0b000100;
4007let Inst{13-13} = 0b0;
4008let Inst{31-21} = 0b11110010000;
4009let CextOpcode = "C4_cmpneq";
4010let InputType = "reg";
4011let isCommutable = 1;
4012let isCompare = 1;
4013}
4014def C4_cmpneqi : HInst<
4015(outs PredRegs:$Pd4),
4016(ins IntRegs:$Rs32, s32_0Imm:$Ii),
4017"$Pd4 = !cmp.eq($Rs32,#$Ii)",
4018tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
4019let Inst{4-2} = 0b100;
4020let Inst{31-22} = 0b0111010100;
4021let CextOpcode = "C4_cmpneq";
4022let InputType = "imm";
4023let isCompare = 1;
4024let isExtendable = 1;
4025let opExtendable = 2;
4026let isExtentSigned = 1;
4027let opExtentBits = 10;
4028let opExtentAlign = 0;
4029}
4030def C4_fastcorner9 : HInst<
4031(outs PredRegs:$Pd4),
4032(ins PredRegs:$Ps4, PredRegs:$Pt4),
4033"$Pd4 = fastcorner9($Ps4,$Pt4)",
4034tc_651cbe02, TypeCR>, Enc_284ebb {
4035let Inst{7-2} = 0b100100;
4036let Inst{13-10} = 0b1000;
4037let Inst{31-18} = 0b01101011000000;
4038}
4039def C4_fastcorner9_not : HInst<
4040(outs PredRegs:$Pd4),
4041(ins PredRegs:$Ps4, PredRegs:$Pt4),
4042"$Pd4 = !fastcorner9($Ps4,$Pt4)",
4043tc_651cbe02, TypeCR>, Enc_284ebb {
4044let Inst{7-2} = 0b100100;
4045let Inst{13-10} = 0b1000;
4046let Inst{31-18} = 0b01101011000100;
4047}
4048def C4_nbitsclr : HInst<
4049(outs PredRegs:$Pd4),
4050(ins IntRegs:$Rs32, IntRegs:$Rt32),
4051"$Pd4 = !bitsclr($Rs32,$Rt32)",
4052tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4053let Inst{7-2} = 0b000000;
4054let Inst{13-13} = 0b0;
4055let Inst{31-21} = 0b11000111101;
4056}
4057def C4_nbitsclri : HInst<
4058(outs PredRegs:$Pd4),
4059(ins IntRegs:$Rs32, u6_0Imm:$Ii),
4060"$Pd4 = !bitsclr($Rs32,#$Ii)",
4061tc_a1297125, TypeS_2op>, Enc_5d6c34 {
4062let Inst{7-2} = 0b000000;
4063let Inst{31-21} = 0b10000101101;
4064}
4065def C4_nbitsset : HInst<
4066(outs PredRegs:$Pd4),
4067(ins IntRegs:$Rs32, IntRegs:$Rt32),
4068"$Pd4 = !bitsset($Rs32,$Rt32)",
4069tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4070let Inst{7-2} = 0b000000;
4071let Inst{13-13} = 0b0;
4072let Inst{31-21} = 0b11000111011;
4073}
4074def C4_or_and : HInst<
4075(outs PredRegs:$Pd4),
4076(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4077"$Pd4 = or($Ps4,and($Pt4,$Pu4))",
4078tc_a7a13fac, TypeCR>, Enc_9ac432 {
4079let Inst{5-2} = 0b0000;
4080let Inst{13-10} = 0b0000;
4081let Inst{31-18} = 0b01101011010100;
4082}
4083def C4_or_andn : HInst<
4084(outs PredRegs:$Pd4),
4085(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4086"$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
4087tc_a7a13fac, TypeCR>, Enc_9ac432 {
4088let Inst{5-2} = 0b0000;
4089let Inst{13-10} = 0b0000;
4090let Inst{31-18} = 0b01101011110100;
4091}
4092def C4_or_or : HInst<
4093(outs PredRegs:$Pd4),
4094(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4095"$Pd4 = or($Ps4,or($Pt4,$Pu4))",
4096tc_a7a13fac, TypeCR>, Enc_9ac432 {
4097let Inst{5-2} = 0b0000;
4098let Inst{13-10} = 0b0000;
4099let Inst{31-18} = 0b01101011011100;
4100}
4101def C4_or_orn : HInst<
4102(outs PredRegs:$Pd4),
4103(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4104"$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
4105tc_a7a13fac, TypeCR>, Enc_9ac432 {
4106let Inst{5-2} = 0b0000;
4107let Inst{13-10} = 0b0000;
4108let Inst{31-18} = 0b01101011111100;
4109}
4110def F2_conv_d2df : HInst<
4111(outs DoubleRegs:$Rdd32),
4112(ins DoubleRegs:$Rss32),
4113"$Rdd32 = convert_d2df($Rss32)",
4114tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4115let Inst{13-5} = 0b000000011;
4116let Inst{31-21} = 0b10000000111;
4117let isFP = 1;
4118let Uses = [USR];
4119}
4120def F2_conv_d2sf : HInst<
4121(outs IntRegs:$Rd32),
4122(ins DoubleRegs:$Rss32),
4123"$Rd32 = convert_d2sf($Rss32)",
4124tc_9783714b, TypeS_2op>, Enc_90cd8b {
4125let Inst{13-5} = 0b000000001;
4126let Inst{31-21} = 0b10001000010;
4127let hasNewValue = 1;
4128let opNewValue = 0;
4129let isFP = 1;
4130let Uses = [USR];
4131}
4132def F2_conv_df2d : HInst<
4133(outs DoubleRegs:$Rdd32),
4134(ins DoubleRegs:$Rss32),
4135"$Rdd32 = convert_df2d($Rss32)",
4136tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4137let Inst{13-5} = 0b000000000;
4138let Inst{31-21} = 0b10000000111;
4139let isFP = 1;
4140let Uses = [USR];
4141}
4142def F2_conv_df2d_chop : HInst<
4143(outs DoubleRegs:$Rdd32),
4144(ins DoubleRegs:$Rss32),
4145"$Rdd32 = convert_df2d($Rss32):chop",
4146tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4147let Inst{13-5} = 0b000000110;
4148let Inst{31-21} = 0b10000000111;
4149let isFP = 1;
4150let Uses = [USR];
4151}
4152def F2_conv_df2sf : HInst<
4153(outs IntRegs:$Rd32),
4154(ins DoubleRegs:$Rss32),
4155"$Rd32 = convert_df2sf($Rss32)",
4156tc_9783714b, TypeS_2op>, Enc_90cd8b {
4157let Inst{13-5} = 0b000000001;
4158let Inst{31-21} = 0b10001000000;
4159let hasNewValue = 1;
4160let opNewValue = 0;
4161let isFP = 1;
4162let Uses = [USR];
4163}
4164def F2_conv_df2ud : HInst<
4165(outs DoubleRegs:$Rdd32),
4166(ins DoubleRegs:$Rss32),
4167"$Rdd32 = convert_df2ud($Rss32)",
4168tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4169let Inst{13-5} = 0b000000001;
4170let Inst{31-21} = 0b10000000111;
4171let isFP = 1;
4172let Uses = [USR];
4173}
4174def F2_conv_df2ud_chop : HInst<
4175(outs DoubleRegs:$Rdd32),
4176(ins DoubleRegs:$Rss32),
4177"$Rdd32 = convert_df2ud($Rss32):chop",
4178tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4179let Inst{13-5} = 0b000000111;
4180let Inst{31-21} = 0b10000000111;
4181let isFP = 1;
4182let Uses = [USR];
4183}
4184def F2_conv_df2uw : HInst<
4185(outs IntRegs:$Rd32),
4186(ins DoubleRegs:$Rss32),
4187"$Rd32 = convert_df2uw($Rss32)",
4188tc_9783714b, TypeS_2op>, Enc_90cd8b {
4189let Inst{13-5} = 0b000000001;
4190let Inst{31-21} = 0b10001000011;
4191let hasNewValue = 1;
4192let opNewValue = 0;
4193let isFP = 1;
4194let Uses = [USR];
4195}
4196def F2_conv_df2uw_chop : HInst<
4197(outs IntRegs:$Rd32),
4198(ins DoubleRegs:$Rss32),
4199"$Rd32 = convert_df2uw($Rss32):chop",
4200tc_9783714b, TypeS_2op>, Enc_90cd8b {
4201let Inst{13-5} = 0b000000001;
4202let Inst{31-21} = 0b10001000101;
4203let hasNewValue = 1;
4204let opNewValue = 0;
4205let isFP = 1;
4206let Uses = [USR];
4207}
4208def F2_conv_df2w : HInst<
4209(outs IntRegs:$Rd32),
4210(ins DoubleRegs:$Rss32),
4211"$Rd32 = convert_df2w($Rss32)",
4212tc_9783714b, TypeS_2op>, Enc_90cd8b {
4213let Inst{13-5} = 0b000000001;
4214let Inst{31-21} = 0b10001000100;
4215let hasNewValue = 1;
4216let opNewValue = 0;
4217let isFP = 1;
4218let Uses = [USR];
4219}
4220def F2_conv_df2w_chop : HInst<
4221(outs IntRegs:$Rd32),
4222(ins DoubleRegs:$Rss32),
4223"$Rd32 = convert_df2w($Rss32):chop",
4224tc_9783714b, TypeS_2op>, Enc_90cd8b {
4225let Inst{13-5} = 0b000000001;
4226let Inst{31-21} = 0b10001000111;
4227let hasNewValue = 1;
4228let opNewValue = 0;
4229let isFP = 1;
4230let Uses = [USR];
4231}
4232def F2_conv_sf2d : HInst<
4233(outs DoubleRegs:$Rdd32),
4234(ins IntRegs:$Rs32),
4235"$Rdd32 = convert_sf2d($Rs32)",
4236tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4237let Inst{13-5} = 0b000000100;
4238let Inst{31-21} = 0b10000100100;
4239let isFP = 1;
4240let Uses = [USR];
4241}
4242def F2_conv_sf2d_chop : HInst<
4243(outs DoubleRegs:$Rdd32),
4244(ins IntRegs:$Rs32),
4245"$Rdd32 = convert_sf2d($Rs32):chop",
4246tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4247let Inst{13-5} = 0b000000110;
4248let Inst{31-21} = 0b10000100100;
4249let isFP = 1;
4250let Uses = [USR];
4251}
4252def F2_conv_sf2df : HInst<
4253(outs DoubleRegs:$Rdd32),
4254(ins IntRegs:$Rs32),
4255"$Rdd32 = convert_sf2df($Rs32)",
4256tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4257let Inst{13-5} = 0b000000000;
4258let Inst{31-21} = 0b10000100100;
4259let isFP = 1;
4260let Uses = [USR];
4261}
4262def F2_conv_sf2ud : HInst<
4263(outs DoubleRegs:$Rdd32),
4264(ins IntRegs:$Rs32),
4265"$Rdd32 = convert_sf2ud($Rs32)",
4266tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4267let Inst{13-5} = 0b000000011;
4268let Inst{31-21} = 0b10000100100;
4269let isFP = 1;
4270let Uses = [USR];
4271}
4272def F2_conv_sf2ud_chop : HInst<
4273(outs DoubleRegs:$Rdd32),
4274(ins IntRegs:$Rs32),
4275"$Rdd32 = convert_sf2ud($Rs32):chop",
4276tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4277let Inst{13-5} = 0b000000101;
4278let Inst{31-21} = 0b10000100100;
4279let isFP = 1;
4280let Uses = [USR];
4281}
4282def F2_conv_sf2uw : HInst<
4283(outs IntRegs:$Rd32),
4284(ins IntRegs:$Rs32),
4285"$Rd32 = convert_sf2uw($Rs32)",
4286tc_9783714b, TypeS_2op>, Enc_5e2823 {
4287let Inst{13-5} = 0b000000000;
4288let Inst{31-21} = 0b10001011011;
4289let hasNewValue = 1;
4290let opNewValue = 0;
4291let isFP = 1;
4292let Uses = [USR];
4293}
4294def F2_conv_sf2uw_chop : HInst<
4295(outs IntRegs:$Rd32),
4296(ins IntRegs:$Rs32),
4297"$Rd32 = convert_sf2uw($Rs32):chop",
4298tc_9783714b, TypeS_2op>, Enc_5e2823 {
4299let Inst{13-5} = 0b000000001;
4300let Inst{31-21} = 0b10001011011;
4301let hasNewValue = 1;
4302let opNewValue = 0;
4303let isFP = 1;
4304let Uses = [USR];
4305}
4306def F2_conv_sf2w : HInst<
4307(outs IntRegs:$Rd32),
4308(ins IntRegs:$Rs32),
4309"$Rd32 = convert_sf2w($Rs32)",
4310tc_9783714b, TypeS_2op>, Enc_5e2823 {
4311let Inst{13-5} = 0b000000000;
4312let Inst{31-21} = 0b10001011100;
4313let hasNewValue = 1;
4314let opNewValue = 0;
4315let isFP = 1;
4316let Uses = [USR];
4317}
4318def F2_conv_sf2w_chop : HInst<
4319(outs IntRegs:$Rd32),
4320(ins IntRegs:$Rs32),
4321"$Rd32 = convert_sf2w($Rs32):chop",
4322tc_9783714b, TypeS_2op>, Enc_5e2823 {
4323let Inst{13-5} = 0b000000001;
4324let Inst{31-21} = 0b10001011100;
4325let hasNewValue = 1;
4326let opNewValue = 0;
4327let isFP = 1;
4328let Uses = [USR];
4329}
4330def F2_conv_ud2df : HInst<
4331(outs DoubleRegs:$Rdd32),
4332(ins DoubleRegs:$Rss32),
4333"$Rdd32 = convert_ud2df($Rss32)",
4334tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4335let Inst{13-5} = 0b000000010;
4336let Inst{31-21} = 0b10000000111;
4337let isFP = 1;
4338let Uses = [USR];
4339}
4340def F2_conv_ud2sf : HInst<
4341(outs IntRegs:$Rd32),
4342(ins DoubleRegs:$Rss32),
4343"$Rd32 = convert_ud2sf($Rss32)",
4344tc_9783714b, TypeS_2op>, Enc_90cd8b {
4345let Inst{13-5} = 0b000000001;
4346let Inst{31-21} = 0b10001000001;
4347let hasNewValue = 1;
4348let opNewValue = 0;
4349let isFP = 1;
4350let Uses = [USR];
4351}
4352def F2_conv_uw2df : HInst<
4353(outs DoubleRegs:$Rdd32),
4354(ins IntRegs:$Rs32),
4355"$Rdd32 = convert_uw2df($Rs32)",
4356tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4357let Inst{13-5} = 0b000000001;
4358let Inst{31-21} = 0b10000100100;
4359let isFP = 1;
4360let Uses = [USR];
4361}
4362def F2_conv_uw2sf : HInst<
4363(outs IntRegs:$Rd32),
4364(ins IntRegs:$Rs32),
4365"$Rd32 = convert_uw2sf($Rs32)",
4366tc_9783714b, TypeS_2op>, Enc_5e2823 {
4367let Inst{13-5} = 0b000000000;
4368let Inst{31-21} = 0b10001011001;
4369let hasNewValue = 1;
4370let opNewValue = 0;
4371let isFP = 1;
4372let Uses = [USR];
4373}
4374def F2_conv_w2df : HInst<
4375(outs DoubleRegs:$Rdd32),
4376(ins IntRegs:$Rs32),
4377"$Rdd32 = convert_w2df($Rs32)",
4378tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4379let Inst{13-5} = 0b000000010;
4380let Inst{31-21} = 0b10000100100;
4381let isFP = 1;
4382let Uses = [USR];
4383}
4384def F2_conv_w2sf : HInst<
4385(outs IntRegs:$Rd32),
4386(ins IntRegs:$Rs32),
4387"$Rd32 = convert_w2sf($Rs32)",
4388tc_9783714b, TypeS_2op>, Enc_5e2823 {
4389let Inst{13-5} = 0b000000000;
4390let Inst{31-21} = 0b10001011010;
4391let hasNewValue = 1;
4392let opNewValue = 0;
4393let isFP = 1;
4394let Uses = [USR];
4395}
4396def F2_dfadd : HInst<
4397(outs DoubleRegs:$Rdd32),
4398(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4399"$Rdd32 = dfadd($Rss32,$Rtt32)",
4400tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4401let Inst{7-5} = 0b011;
4402let Inst{13-13} = 0b0;
4403let Inst{31-21} = 0b11101000000;
4404let isFP = 1;
4405let Uses = [USR];
4406}
4407def F2_dfclass : HInst<
4408(outs PredRegs:$Pd4),
4409(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
4410"$Pd4 = dfclass($Rss32,#$Ii)",
4411tc_a1297125, TypeALU64>, Enc_1f19b5 {
4412let Inst{4-2} = 0b100;
4413let Inst{13-10} = 0b0000;
4414let Inst{31-21} = 0b11011100100;
4415let isFP = 1;
4416let Uses = [USR];
4417}
4418def F2_dfcmpeq : HInst<
4419(outs PredRegs:$Pd4),
4420(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4421"$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
4422tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4423let Inst{7-2} = 0b000000;
4424let Inst{13-13} = 0b0;
4425let Inst{31-21} = 0b11010010111;
4426let isFP = 1;
4427let Uses = [USR];
4428let isCompare = 1;
4429}
4430def F2_dfcmpge : HInst<
4431(outs PredRegs:$Pd4),
4432(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4433"$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
4434tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4435let Inst{7-2} = 0b010000;
4436let Inst{13-13} = 0b0;
4437let Inst{31-21} = 0b11010010111;
4438let isFP = 1;
4439let Uses = [USR];
4440let isCompare = 1;
4441}
4442def F2_dfcmpgt : HInst<
4443(outs PredRegs:$Pd4),
4444(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4445"$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
4446tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4447let Inst{7-2} = 0b001000;
4448let Inst{13-13} = 0b0;
4449let Inst{31-21} = 0b11010010111;
4450let isFP = 1;
4451let Uses = [USR];
4452let isCompare = 1;
4453}
4454def F2_dfcmpuo : HInst<
4455(outs PredRegs:$Pd4),
4456(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4457"$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
4458tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4459let Inst{7-2} = 0b011000;
4460let Inst{13-13} = 0b0;
4461let Inst{31-21} = 0b11010010111;
4462let isFP = 1;
4463let Uses = [USR];
4464let isCompare = 1;
4465}
4466def F2_dfimm_n : HInst<
4467(outs DoubleRegs:$Rdd32),
4468(ins u10_0Imm:$Ii),
4469"$Rdd32 = dfmake(#$Ii):neg",
4470tc_65279839, TypeALU64>, Enc_e6c957 {
4471let Inst{20-16} = 0b00000;
4472let Inst{31-22} = 0b1101100101;
4473let prefersSlot3 = 1;
4474}
4475def F2_dfimm_p : HInst<
4476(outs DoubleRegs:$Rdd32),
4477(ins u10_0Imm:$Ii),
4478"$Rdd32 = dfmake(#$Ii):pos",
4479tc_65279839, TypeALU64>, Enc_e6c957 {
4480let Inst{20-16} = 0b00000;
4481let Inst{31-22} = 0b1101100100;
4482let prefersSlot3 = 1;
4483}
4484def F2_dfmax : HInst<
4485(outs DoubleRegs:$Rdd32),
4486(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4487"$Rdd32 = dfmax($Rss32,$Rtt32)",
4488tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4489let Inst{7-5} = 0b011;
4490let Inst{13-13} = 0b0;
4491let Inst{31-21} = 0b11101000001;
4492let isFP = 1;
4493let prefersSlot3 = 1;
4494let Uses = [USR];
4495}
4496def F2_dfmin : HInst<
4497(outs DoubleRegs:$Rdd32),
4498(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4499"$Rdd32 = dfmin($Rss32,$Rtt32)",
4500tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4501let Inst{7-5} = 0b011;
4502let Inst{13-13} = 0b0;
4503let Inst{31-21} = 0b11101000110;
4504let isFP = 1;
4505let prefersSlot3 = 1;
4506let Uses = [USR];
4507}
4508def F2_dfmpyfix : HInst<
4509(outs DoubleRegs:$Rdd32),
4510(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4511"$Rdd32 = dfmpyfix($Rss32,$Rtt32)",
4512tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> {
4513let Inst{7-5} = 0b011;
4514let Inst{13-13} = 0b0;
4515let Inst{31-21} = 0b11101000010;
4516let isFP = 1;
4517let Uses = [USR];
4518}
4519def F2_dfmpyhh : HInst<
4520(outs DoubleRegs:$Rxx32),
4521(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4522"$Rxx32 += dfmpyhh($Rss32,$Rtt32)",
4523tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4524let Inst{7-5} = 0b011;
4525let Inst{13-13} = 0b0;
4526let Inst{31-21} = 0b11101010100;
4527let isFP = 1;
4528let Uses = [USR];
4529let Constraints = "$Rxx32 = $Rxx32in";
4530}
4531def F2_dfmpylh : HInst<
4532(outs DoubleRegs:$Rxx32),
4533(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4534"$Rxx32 += dfmpylh($Rss32,$Rtt32)",
4535tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4536let Inst{7-5} = 0b011;
4537let Inst{13-13} = 0b0;
4538let Inst{31-21} = 0b11101010000;
4539let prefersSlot3 = 1;
4540let Constraints = "$Rxx32 = $Rxx32in";
4541}
4542def F2_dfmpyll : HInst<
4543(outs DoubleRegs:$Rdd32),
4544(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4545"$Rdd32 = dfmpyll($Rss32,$Rtt32)",
4546tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> {
4547let Inst{7-5} = 0b011;
4548let Inst{13-13} = 0b0;
4549let Inst{31-21} = 0b11101000101;
4550let prefersSlot3 = 1;
4551}
4552def F2_dfsub : HInst<
4553(outs DoubleRegs:$Rdd32),
4554(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4555"$Rdd32 = dfsub($Rss32,$Rtt32)",
4556tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4557let Inst{7-5} = 0b011;
4558let Inst{13-13} = 0b0;
4559let Inst{31-21} = 0b11101000100;
4560let isFP = 1;
4561let Uses = [USR];
4562}
4563def F2_sfadd : HInst<
4564(outs IntRegs:$Rd32),
4565(ins IntRegs:$Rs32, IntRegs:$Rt32),
4566"$Rd32 = sfadd($Rs32,$Rt32)",
4567tc_02fe1c65, TypeM>, Enc_5ab2be {
4568let Inst{7-5} = 0b000;
4569let Inst{13-13} = 0b0;
4570let Inst{31-21} = 0b11101011000;
4571let hasNewValue = 1;
4572let opNewValue = 0;
4573let isFP = 1;
4574let Uses = [USR];
4575let isCommutable = 1;
4576}
4577def F2_sfclass : HInst<
4578(outs PredRegs:$Pd4),
4579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
4580"$Pd4 = sfclass($Rs32,#$Ii)",
4581tc_a1297125, TypeS_2op>, Enc_83ee64 {
4582let Inst{7-2} = 0b000000;
4583let Inst{13-13} = 0b0;
4584let Inst{31-21} = 0b10000101111;
4585let isFP = 1;
4586let Uses = [USR];
4587}
4588def F2_sfcmpeq : HInst<
4589(outs PredRegs:$Pd4),
4590(ins IntRegs:$Rs32, IntRegs:$Rt32),
4591"$Pd4 = sfcmp.eq($Rs32,$Rt32)",
4592tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4593let Inst{7-2} = 0b011000;
4594let Inst{13-13} = 0b0;
4595let Inst{31-21} = 0b11000111111;
4596let isFP = 1;
4597let Uses = [USR];
4598let isCompare = 1;
4599}
4600def F2_sfcmpge : HInst<
4601(outs PredRegs:$Pd4),
4602(ins IntRegs:$Rs32, IntRegs:$Rt32),
4603"$Pd4 = sfcmp.ge($Rs32,$Rt32)",
4604tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4605let Inst{7-2} = 0b000000;
4606let Inst{13-13} = 0b0;
4607let Inst{31-21} = 0b11000111111;
4608let isFP = 1;
4609let Uses = [USR];
4610let isCompare = 1;
4611}
4612def F2_sfcmpgt : HInst<
4613(outs PredRegs:$Pd4),
4614(ins IntRegs:$Rs32, IntRegs:$Rt32),
4615"$Pd4 = sfcmp.gt($Rs32,$Rt32)",
4616tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4617let Inst{7-2} = 0b100000;
4618let Inst{13-13} = 0b0;
4619let Inst{31-21} = 0b11000111111;
4620let isFP = 1;
4621let Uses = [USR];
4622let isCompare = 1;
4623}
4624def F2_sfcmpuo : HInst<
4625(outs PredRegs:$Pd4),
4626(ins IntRegs:$Rs32, IntRegs:$Rt32),
4627"$Pd4 = sfcmp.uo($Rs32,$Rt32)",
4628tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4629let Inst{7-2} = 0b001000;
4630let Inst{13-13} = 0b0;
4631let Inst{31-21} = 0b11000111111;
4632let isFP = 1;
4633let Uses = [USR];
4634let isCompare = 1;
4635}
4636def F2_sffixupd : HInst<
4637(outs IntRegs:$Rd32),
4638(ins IntRegs:$Rs32, IntRegs:$Rt32),
4639"$Rd32 = sffixupd($Rs32,$Rt32)",
4640tc_02fe1c65, TypeM>, Enc_5ab2be {
4641let Inst{7-5} = 0b001;
4642let Inst{13-13} = 0b0;
4643let Inst{31-21} = 0b11101011110;
4644let hasNewValue = 1;
4645let opNewValue = 0;
4646let isFP = 1;
4647}
4648def F2_sffixupn : HInst<
4649(outs IntRegs:$Rd32),
4650(ins IntRegs:$Rs32, IntRegs:$Rt32),
4651"$Rd32 = sffixupn($Rs32,$Rt32)",
4652tc_02fe1c65, TypeM>, Enc_5ab2be {
4653let Inst{7-5} = 0b000;
4654let Inst{13-13} = 0b0;
4655let Inst{31-21} = 0b11101011110;
4656let hasNewValue = 1;
4657let opNewValue = 0;
4658let isFP = 1;
4659}
4660def F2_sffixupr : HInst<
4661(outs IntRegs:$Rd32),
4662(ins IntRegs:$Rs32),
4663"$Rd32 = sffixupr($Rs32)",
4664tc_9783714b, TypeS_2op>, Enc_5e2823 {
4665let Inst{13-5} = 0b000000000;
4666let Inst{31-21} = 0b10001011101;
4667let hasNewValue = 1;
4668let opNewValue = 0;
4669let isFP = 1;
4670}
4671def F2_sffma : HInst<
4672(outs IntRegs:$Rx32),
4673(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4674"$Rx32 += sfmpy($Rs32,$Rt32)",
4675tc_9e72dc89, TypeM>, Enc_2ae154 {
4676let Inst{7-5} = 0b100;
4677let Inst{13-13} = 0b0;
4678let Inst{31-21} = 0b11101111000;
4679let hasNewValue = 1;
4680let opNewValue = 0;
4681let isFP = 1;
4682let Uses = [USR];
4683let Constraints = "$Rx32 = $Rx32in";
4684}
4685def F2_sffma_lib : HInst<
4686(outs IntRegs:$Rx32),
4687(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4688"$Rx32 += sfmpy($Rs32,$Rt32):lib",
4689tc_9e72dc89, TypeM>, Enc_2ae154 {
4690let Inst{7-5} = 0b110;
4691let Inst{13-13} = 0b0;
4692let Inst{31-21} = 0b11101111000;
4693let hasNewValue = 1;
4694let opNewValue = 0;
4695let isFP = 1;
4696let Uses = [USR];
4697let Constraints = "$Rx32 = $Rx32in";
4698}
4699def F2_sffma_sc : HInst<
4700(outs IntRegs:$Rx32),
4701(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
4702"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
4703tc_9edb7c77, TypeM>, Enc_437f33 {
4704let Inst{7-7} = 0b1;
4705let Inst{13-13} = 0b0;
4706let Inst{31-21} = 0b11101111011;
4707let hasNewValue = 1;
4708let opNewValue = 0;
4709let isFP = 1;
4710let Uses = [USR];
4711let Constraints = "$Rx32 = $Rx32in";
4712}
4713def F2_sffms : HInst<
4714(outs IntRegs:$Rx32),
4715(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4716"$Rx32 -= sfmpy($Rs32,$Rt32)",
4717tc_9e72dc89, TypeM>, Enc_2ae154 {
4718let Inst{7-5} = 0b101;
4719let Inst{13-13} = 0b0;
4720let Inst{31-21} = 0b11101111000;
4721let hasNewValue = 1;
4722let opNewValue = 0;
4723let isFP = 1;
4724let Uses = [USR];
4725let Constraints = "$Rx32 = $Rx32in";
4726}
4727def F2_sffms_lib : HInst<
4728(outs IntRegs:$Rx32),
4729(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4730"$Rx32 -= sfmpy($Rs32,$Rt32):lib",
4731tc_9e72dc89, TypeM>, Enc_2ae154 {
4732let Inst{7-5} = 0b111;
4733let Inst{13-13} = 0b0;
4734let Inst{31-21} = 0b11101111000;
4735let hasNewValue = 1;
4736let opNewValue = 0;
4737let isFP = 1;
4738let Uses = [USR];
4739let Constraints = "$Rx32 = $Rx32in";
4740}
4741def F2_sfimm_n : HInst<
4742(outs IntRegs:$Rd32),
4743(ins u10_0Imm:$Ii),
4744"$Rd32 = sfmake(#$Ii):neg",
4745tc_65279839, TypeALU64>, Enc_6c9440 {
4746let Inst{20-16} = 0b00000;
4747let Inst{31-22} = 0b1101011001;
4748let hasNewValue = 1;
4749let opNewValue = 0;
4750let prefersSlot3 = 1;
4751}
4752def F2_sfimm_p : HInst<
4753(outs IntRegs:$Rd32),
4754(ins u10_0Imm:$Ii),
4755"$Rd32 = sfmake(#$Ii):pos",
4756tc_65279839, TypeALU64>, Enc_6c9440 {
4757let Inst{20-16} = 0b00000;
4758let Inst{31-22} = 0b1101011000;
4759let hasNewValue = 1;
4760let opNewValue = 0;
4761let prefersSlot3 = 1;
4762}
4763def F2_sfinvsqrta : HInst<
4764(outs IntRegs:$Rd32, PredRegs:$Pe4),
4765(ins IntRegs:$Rs32),
4766"$Rd32,$Pe4 = sfinvsqrta($Rs32)",
4767tc_7f7f45f5, TypeS_2op>, Enc_890909 {
4768let Inst{13-7} = 0b0000000;
4769let Inst{31-21} = 0b10001011111;
4770let hasNewValue = 1;
4771let opNewValue = 0;
4772let isFP = 1;
4773let isPredicateLate = 1;
4774}
4775def F2_sfmax : HInst<
4776(outs IntRegs:$Rd32),
4777(ins IntRegs:$Rs32, IntRegs:$Rt32),
4778"$Rd32 = sfmax($Rs32,$Rt32)",
4779tc_c20701f0, TypeM>, Enc_5ab2be {
4780let Inst{7-5} = 0b000;
4781let Inst{13-13} = 0b0;
4782let Inst{31-21} = 0b11101011100;
4783let hasNewValue = 1;
4784let opNewValue = 0;
4785let isFP = 1;
4786let prefersSlot3 = 1;
4787let Uses = [USR];
4788}
4789def F2_sfmin : HInst<
4790(outs IntRegs:$Rd32),
4791(ins IntRegs:$Rs32, IntRegs:$Rt32),
4792"$Rd32 = sfmin($Rs32,$Rt32)",
4793tc_c20701f0, TypeM>, Enc_5ab2be {
4794let Inst{7-5} = 0b001;
4795let Inst{13-13} = 0b0;
4796let Inst{31-21} = 0b11101011100;
4797let hasNewValue = 1;
4798let opNewValue = 0;
4799let isFP = 1;
4800let prefersSlot3 = 1;
4801let Uses = [USR];
4802}
4803def F2_sfmpy : HInst<
4804(outs IntRegs:$Rd32),
4805(ins IntRegs:$Rs32, IntRegs:$Rt32),
4806"$Rd32 = sfmpy($Rs32,$Rt32)",
4807tc_02fe1c65, TypeM>, Enc_5ab2be {
4808let Inst{7-5} = 0b000;
4809let Inst{13-13} = 0b0;
4810let Inst{31-21} = 0b11101011010;
4811let hasNewValue = 1;
4812let opNewValue = 0;
4813let isFP = 1;
4814let Uses = [USR];
4815let isCommutable = 1;
4816}
4817def F2_sfrecipa : HInst<
4818(outs IntRegs:$Rd32, PredRegs:$Pe4),
4819(ins IntRegs:$Rs32, IntRegs:$Rt32),
4820"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
4821tc_f7569068, TypeM>, Enc_a94f3b {
4822let Inst{7-7} = 0b1;
4823let Inst{13-13} = 0b0;
4824let Inst{31-21} = 0b11101011111;
4825let hasNewValue = 1;
4826let opNewValue = 0;
4827let isFP = 1;
4828let isPredicateLate = 1;
4829}
4830def F2_sfsub : HInst<
4831(outs IntRegs:$Rd32),
4832(ins IntRegs:$Rs32, IntRegs:$Rt32),
4833"$Rd32 = sfsub($Rs32,$Rt32)",
4834tc_02fe1c65, TypeM>, Enc_5ab2be {
4835let Inst{7-5} = 0b001;
4836let Inst{13-13} = 0b0;
4837let Inst{31-21} = 0b11101011000;
4838let hasNewValue = 1;
4839let opNewValue = 0;
4840let isFP = 1;
4841let Uses = [USR];
4842}
4843def G4_tfrgcpp : HInst<
4844(outs DoubleRegs:$Rdd32),
4845(ins GuestRegs64:$Gss32),
4846"$Rdd32 = $Gss32",
4847tc_fae9dfa5, TypeCR>, Enc_0aa344 {
4848let Inst{13-5} = 0b000000000;
4849let Inst{31-21} = 0b01101000001;
4850}
4851def G4_tfrgcrr : HInst<
4852(outs IntRegs:$Rd32),
4853(ins GuestRegs:$Gs32),
4854"$Rd32 = $Gs32",
4855tc_fae9dfa5, TypeCR>, Enc_44271f {
4856let Inst{13-5} = 0b000000000;
4857let Inst{31-21} = 0b01101010001;
4858let hasNewValue = 1;
4859let opNewValue = 0;
4860}
4861def G4_tfrgpcp : HInst<
4862(outs GuestRegs64:$Gdd32),
4863(ins DoubleRegs:$Rss32),
4864"$Gdd32 = $Rss32",
4865tc_6ae3426b, TypeCR>, Enc_ed5027 {
4866let Inst{13-5} = 0b000000000;
4867let Inst{31-21} = 0b01100011000;
4868let hasNewValue = 1;
4869let opNewValue = 0;
4870}
4871def G4_tfrgrcr : HInst<
4872(outs GuestRegs:$Gd32),
4873(ins IntRegs:$Rs32),
4874"$Gd32 = $Rs32",
4875tc_6ae3426b, TypeCR>, Enc_621fba {
4876let Inst{13-5} = 0b000000000;
4877let Inst{31-21} = 0b01100010000;
4878let hasNewValue = 1;
4879let opNewValue = 0;
4880}
4881def J2_call : HInst<
4882(outs),
4883(ins a30_2Imm:$Ii),
4884"call $Ii",
4885tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel {
4886let Inst{0-0} = 0b0;
4887let Inst{31-25} = 0b0101101;
4888let isCall = 1;
4889let prefersSlot3 = 1;
4890let cofRelax2 = 1;
4891let cofMax1 = 1;
4892let Uses = [R29];
4893let Defs = [PC, R31];
4894let BaseOpcode = "J2_call";
4895let hasSideEffects = 1;
4896let isPredicable = 1;
4897let isExtendable = 1;
4898let opExtendable = 0;
4899let isExtentSigned = 1;
4900let opExtentBits = 24;
4901let opExtentAlign = 2;
4902}
4903def J2_callf : HInst<
4904(outs),
4905(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4906"if (!$Pu4) call $Ii",
4907tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4908let Inst{0-0} = 0b0;
4909let Inst{12-10} = 0b000;
4910let Inst{21-21} = 0b1;
4911let Inst{31-24} = 0b01011101;
4912let isPredicated = 1;
4913let isPredicatedFalse = 1;
4914let isCall = 1;
4915let prefersSlot3 = 1;
4916let cofRelax1 = 1;
4917let cofRelax2 = 1;
4918let cofMax1 = 1;
4919let Uses = [R29];
4920let Defs = [PC, R31];
4921let BaseOpcode = "J2_call";
4922let hasSideEffects = 1;
4923let isTaken = Inst{12};
4924let isExtendable = 1;
4925let opExtendable = 1;
4926let isExtentSigned = 1;
4927let opExtentBits = 17;
4928let opExtentAlign = 2;
4929}
4930def J2_callr : HInst<
4931(outs),
4932(ins IntRegs:$Rs32),
4933"callr $Rs32",
4934tc_362b0be2, TypeJ>, Enc_ecbcc8 {
4935let Inst{13-0} = 0b00000000000000;
4936let Inst{31-21} = 0b01010000101;
4937let isCall = 1;
4938let prefersSlot3 = 1;
4939let cofMax1 = 1;
4940let Uses = [R29];
4941let Defs = [PC, R31];
4942let hasSideEffects = 1;
4943}
4944def J2_callrf : HInst<
4945(outs),
4946(ins PredRegs:$Pu4, IntRegs:$Rs32),
4947"if (!$Pu4) callr $Rs32",
4948tc_dc51281d, TypeJ>, Enc_88d4d9 {
4949let Inst{7-0} = 0b00000000;
4950let Inst{13-10} = 0b0000;
4951let Inst{31-21} = 0b01010001001;
4952let isPredicated = 1;
4953let isPredicatedFalse = 1;
4954let isCall = 1;
4955let prefersSlot3 = 1;
4956let cofMax1 = 1;
4957let Uses = [R29];
4958let Defs = [PC, R31];
4959let hasSideEffects = 1;
4960let isTaken = Inst{12};
4961}
4962def J2_callrt : HInst<
4963(outs),
4964(ins PredRegs:$Pu4, IntRegs:$Rs32),
4965"if ($Pu4) callr $Rs32",
4966tc_dc51281d, TypeJ>, Enc_88d4d9 {
4967let Inst{7-0} = 0b00000000;
4968let Inst{13-10} = 0b0000;
4969let Inst{31-21} = 0b01010001000;
4970let isPredicated = 1;
4971let isCall = 1;
4972let prefersSlot3 = 1;
4973let cofMax1 = 1;
4974let Uses = [R29];
4975let Defs = [PC, R31];
4976let hasSideEffects = 1;
4977let isTaken = Inst{12};
4978}
4979def J2_callt : HInst<
4980(outs),
4981(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4982"if ($Pu4) call $Ii",
4983tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4984let Inst{0-0} = 0b0;
4985let Inst{12-10} = 0b000;
4986let Inst{21-21} = 0b0;
4987let Inst{31-24} = 0b01011101;
4988let isPredicated = 1;
4989let isCall = 1;
4990let prefersSlot3 = 1;
4991let cofRelax1 = 1;
4992let cofRelax2 = 1;
4993let cofMax1 = 1;
4994let Uses = [R29];
4995let Defs = [PC, R31];
4996let BaseOpcode = "J2_call";
4997let hasSideEffects = 1;
4998let isTaken = Inst{12};
4999let isExtendable = 1;
5000let opExtendable = 1;
5001let isExtentSigned = 1;
5002let opExtentBits = 17;
5003let opExtentAlign = 2;
5004}
5005def J2_endloop0 : HInst<
5006(outs),
5007(ins),
5008"endloop0",
5009tc_23708a21, TypeJ> {
5010let Uses = [LC0, SA0];
5011let Defs = [LC0, P3, PC, USR];
5012let isBranch = 1;
5013let isTerminator = 1;
5014let isPseudo = 1;
5015}
5016def J2_endloop01 : HInst<
5017(outs),
5018(ins),
5019"endloop01",
5020tc_23708a21, TypeJ> {
5021let Uses = [LC0, LC1, SA0, SA1];
5022let Defs = [LC0, LC1, P3, PC, USR];
5023let isPseudo = 1;
5024}
5025def J2_endloop1 : HInst<
5026(outs),
5027(ins),
5028"endloop1",
5029tc_23708a21, TypeJ> {
5030let Uses = [LC1, SA1];
5031let Defs = [LC1, PC];
5032let isBranch = 1;
5033let isTerminator = 1;
5034let isPseudo = 1;
5035}
5036def J2_jump : HInst<
5037(outs),
5038(ins b30_2Imm:$Ii),
5039"jump $Ii",
5040tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel {
5041let Inst{0-0} = 0b0;
5042let Inst{31-25} = 0b0101100;
5043let isTerminator = 1;
5044let isBranch = 1;
5045let cofRelax2 = 1;
5046let cofMax1 = 1;
5047let Defs = [PC];
5048let BaseOpcode = "J2_jump";
5049let InputType = "imm";
5050let isBarrier = 1;
5051let isPredicable = 1;
5052let isExtendable = 1;
5053let opExtendable = 0;
5054let isExtentSigned = 1;
5055let opExtentBits = 24;
5056let opExtentAlign = 2;
5057}
5058def J2_jumpf : HInst<
5059(outs),
5060(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5061"if (!$Pu4) jump:nt $Ii",
5062tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5063let Inst{0-0} = 0b0;
5064let Inst{12-10} = 0b000;
5065let Inst{21-21} = 0b1;
5066let Inst{31-24} = 0b01011100;
5067let isPredicated = 1;
5068let isPredicatedFalse = 1;
5069let isTerminator = 1;
5070let isBranch = 1;
5071let cofRelax1 = 1;
5072let cofRelax2 = 1;
5073let cofMax1 = 1;
5074let Defs = [PC];
5075let BaseOpcode = "J2_jump";
5076let InputType = "imm";
5077let isTaken = Inst{12};
5078let isExtendable = 1;
5079let opExtendable = 1;
5080let isExtentSigned = 1;
5081let opExtentBits = 17;
5082let opExtentAlign = 2;
5083}
5084def J2_jumpf_nopred_map : HInst<
5085(outs),
5086(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5087"if (!$Pu4) jump $Ii",
5088tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5089let isPseudo = 1;
5090let isCodeGenOnly = 1;
5091}
5092def J2_jumpfnew : HInst<
5093(outs),
5094(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5095"if (!$Pu4.new) jump:nt $Ii",
5096tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5097let Inst{0-0} = 0b0;
5098let Inst{12-10} = 0b010;
5099let Inst{21-21} = 0b1;
5100let Inst{31-24} = 0b01011100;
5101let isPredicated = 1;
5102let isPredicatedFalse = 1;
5103let isTerminator = 1;
5104let isBranch = 1;
5105let isPredicatedNew = 1;
5106let cofRelax1 = 1;
5107let cofRelax2 = 1;
5108let cofMax1 = 1;
5109let Defs = [PC];
5110let BaseOpcode = "J2_jump";
5111let InputType = "imm";
5112let isTaken = Inst{12};
5113let isExtendable = 1;
5114let opExtendable = 1;
5115let isExtentSigned = 1;
5116let opExtentBits = 17;
5117let opExtentAlign = 2;
5118}
5119def J2_jumpfnewpt : HInst<
5120(outs),
5121(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5122"if (!$Pu4.new) jump:t $Ii",
5123tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5124let Inst{0-0} = 0b0;
5125let Inst{12-10} = 0b110;
5126let Inst{21-21} = 0b1;
5127let Inst{31-24} = 0b01011100;
5128let isPredicated = 1;
5129let isPredicatedFalse = 1;
5130let isTerminator = 1;
5131let isBranch = 1;
5132let isPredicatedNew = 1;
5133let cofRelax1 = 1;
5134let cofRelax2 = 1;
5135let cofMax1 = 1;
5136let Defs = [PC];
5137let BaseOpcode = "J2_jump";
5138let InputType = "imm";
5139let isTaken = Inst{12};
5140let isExtendable = 1;
5141let opExtendable = 1;
5142let isExtentSigned = 1;
5143let opExtentBits = 17;
5144let opExtentAlign = 2;
5145}
5146def J2_jumpfpt : HInst<
5147(outs),
5148(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5149"if (!$Pu4) jump:t $Ii",
5150tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5151let Inst{0-0} = 0b0;
5152let Inst{12-10} = 0b100;
5153let Inst{21-21} = 0b1;
5154let Inst{31-24} = 0b01011100;
5155let isPredicated = 1;
5156let isPredicatedFalse = 1;
5157let isTerminator = 1;
5158let isBranch = 1;
5159let cofRelax1 = 1;
5160let cofRelax2 = 1;
5161let cofMax1 = 1;
5162let Defs = [PC];
5163let BaseOpcode = "J2_jump";
5164let InputType = "imm";
5165let isTaken = Inst{12};
5166let isExtendable = 1;
5167let opExtendable = 1;
5168let isExtentSigned = 1;
5169let opExtentBits = 17;
5170let opExtentAlign = 2;
5171}
5172def J2_jumpr : HInst<
5173(outs),
5174(ins IntRegs:$Rs32),
5175"jumpr $Rs32",
5176tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel {
5177let Inst{13-0} = 0b00000000000000;
5178let Inst{31-21} = 0b01010010100;
5179let isTerminator = 1;
5180let isIndirectBranch = 1;
5181let isBranch = 1;
5182let cofMax1 = 1;
5183let Defs = [PC];
5184let BaseOpcode = "J2_jumpr";
5185let InputType = "reg";
5186let isBarrier = 1;
5187let isPredicable = 1;
5188}
5189def J2_jumprf : HInst<
5190(outs),
5191(ins PredRegs:$Pu4, IntRegs:$Rs32),
5192"if (!$Pu4) jumpr:nt $Rs32",
5193tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5194let Inst{7-0} = 0b00000000;
5195let Inst{13-10} = 0b0000;
5196let Inst{31-21} = 0b01010011011;
5197let isPredicated = 1;
5198let isPredicatedFalse = 1;
5199let isTerminator = 1;
5200let isIndirectBranch = 1;
5201let isBranch = 1;
5202let cofMax1 = 1;
5203let Defs = [PC];
5204let BaseOpcode = "J2_jumpr";
5205let InputType = "reg";
5206let isTaken = Inst{12};
5207}
5208def J2_jumprf_nopred_map : HInst<
5209(outs),
5210(ins PredRegs:$Pu4, IntRegs:$Rs32),
5211"if (!$Pu4) jumpr $Rs32",
5212tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5213let isPseudo = 1;
5214let isCodeGenOnly = 1;
5215}
5216def J2_jumprfnew : HInst<
5217(outs),
5218(ins PredRegs:$Pu4, IntRegs:$Rs32),
5219"if (!$Pu4.new) jumpr:nt $Rs32",
5220tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5221let Inst{7-0} = 0b00000000;
5222let Inst{13-10} = 0b0010;
5223let Inst{31-21} = 0b01010011011;
5224let isPredicated = 1;
5225let isPredicatedFalse = 1;
5226let isTerminator = 1;
5227let isIndirectBranch = 1;
5228let isBranch = 1;
5229let isPredicatedNew = 1;
5230let cofMax1 = 1;
5231let Defs = [PC];
5232let BaseOpcode = "J2_jumpr";
5233let InputType = "reg";
5234let isTaken = Inst{12};
5235}
5236def J2_jumprfnewpt : HInst<
5237(outs),
5238(ins PredRegs:$Pu4, IntRegs:$Rs32),
5239"if (!$Pu4.new) jumpr:t $Rs32",
5240tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5241let Inst{7-0} = 0b00000000;
5242let Inst{13-10} = 0b0110;
5243let Inst{31-21} = 0b01010011011;
5244let isPredicated = 1;
5245let isPredicatedFalse = 1;
5246let isTerminator = 1;
5247let isIndirectBranch = 1;
5248let isBranch = 1;
5249let isPredicatedNew = 1;
5250let cofMax1 = 1;
5251let Defs = [PC];
5252let BaseOpcode = "J2_jumpr";
5253let InputType = "reg";
5254let isTaken = Inst{12};
5255}
5256def J2_jumprfpt : HInst<
5257(outs),
5258(ins PredRegs:$Pu4, IntRegs:$Rs32),
5259"if (!$Pu4) jumpr:t $Rs32",
5260tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5261let Inst{7-0} = 0b00000000;
5262let Inst{13-10} = 0b0100;
5263let Inst{31-21} = 0b01010011011;
5264let isPredicated = 1;
5265let isPredicatedFalse = 1;
5266let isTerminator = 1;
5267let isIndirectBranch = 1;
5268let isBranch = 1;
5269let cofMax1 = 1;
5270let Defs = [PC];
5271let BaseOpcode = "J2_jumpr";
5272let InputType = "reg";
5273let isTaken = Inst{12};
5274}
5275def J2_jumprgtez : HInst<
5276(outs),
5277(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5278"if ($Rs32>=#0) jump:nt $Ii",
5279tc_57a55b54, TypeCR>, Enc_0fa531 {
5280let Inst{0-0} = 0b0;
5281let Inst{12-12} = 0b0;
5282let Inst{31-22} = 0b0110000101;
5283let isPredicated = 1;
5284let isTerminator = 1;
5285let isBranch = 1;
5286let isPredicatedNew = 1;
5287let cofRelax1 = 1;
5288let cofRelax2 = 1;
5289let cofMax1 = 1;
5290let Defs = [PC];
5291let isTaken = Inst{12};
5292}
5293def J2_jumprgtezpt : HInst<
5294(outs),
5295(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5296"if ($Rs32>=#0) jump:t $Ii",
5297tc_57a55b54, TypeCR>, Enc_0fa531 {
5298let Inst{0-0} = 0b0;
5299let Inst{12-12} = 0b1;
5300let Inst{31-22} = 0b0110000101;
5301let isPredicated = 1;
5302let isTerminator = 1;
5303let isBranch = 1;
5304let isPredicatedNew = 1;
5305let cofRelax1 = 1;
5306let cofRelax2 = 1;
5307let cofMax1 = 1;
5308let Defs = [PC];
5309let isTaken = Inst{12};
5310}
5311def J2_jumprltez : HInst<
5312(outs),
5313(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5314"if ($Rs32<=#0) jump:nt $Ii",
5315tc_57a55b54, TypeCR>, Enc_0fa531 {
5316let Inst{0-0} = 0b0;
5317let Inst{12-12} = 0b0;
5318let Inst{31-22} = 0b0110000111;
5319let isPredicated = 1;
5320let isTerminator = 1;
5321let isBranch = 1;
5322let isPredicatedNew = 1;
5323let cofRelax1 = 1;
5324let cofRelax2 = 1;
5325let cofMax1 = 1;
5326let Defs = [PC];
5327let isTaken = Inst{12};
5328}
5329def J2_jumprltezpt : HInst<
5330(outs),
5331(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5332"if ($Rs32<=#0) jump:t $Ii",
5333tc_57a55b54, TypeCR>, Enc_0fa531 {
5334let Inst{0-0} = 0b0;
5335let Inst{12-12} = 0b1;
5336let Inst{31-22} = 0b0110000111;
5337let isPredicated = 1;
5338let isTerminator = 1;
5339let isBranch = 1;
5340let isPredicatedNew = 1;
5341let cofRelax1 = 1;
5342let cofRelax2 = 1;
5343let cofMax1 = 1;
5344let Defs = [PC];
5345let isTaken = Inst{12};
5346}
5347def J2_jumprnz : HInst<
5348(outs),
5349(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5350"if ($Rs32==#0) jump:nt $Ii",
5351tc_57a55b54, TypeCR>, Enc_0fa531 {
5352let Inst{0-0} = 0b0;
5353let Inst{12-12} = 0b0;
5354let Inst{31-22} = 0b0110000110;
5355let isPredicated = 1;
5356let isTerminator = 1;
5357let isBranch = 1;
5358let isPredicatedNew = 1;
5359let cofRelax1 = 1;
5360let cofRelax2 = 1;
5361let cofMax1 = 1;
5362let Defs = [PC];
5363let isTaken = Inst{12};
5364}
5365def J2_jumprnzpt : HInst<
5366(outs),
5367(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5368"if ($Rs32==#0) jump:t $Ii",
5369tc_57a55b54, TypeCR>, Enc_0fa531 {
5370let Inst{0-0} = 0b0;
5371let Inst{12-12} = 0b1;
5372let Inst{31-22} = 0b0110000110;
5373let isPredicated = 1;
5374let isTerminator = 1;
5375let isBranch = 1;
5376let isPredicatedNew = 1;
5377let cofRelax1 = 1;
5378let cofRelax2 = 1;
5379let cofMax1 = 1;
5380let Defs = [PC];
5381let isTaken = Inst{12};
5382}
5383def J2_jumprt : HInst<
5384(outs),
5385(ins PredRegs:$Pu4, IntRegs:$Rs32),
5386"if ($Pu4) jumpr:nt $Rs32",
5387tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5388let Inst{7-0} = 0b00000000;
5389let Inst{13-10} = 0b0000;
5390let Inst{31-21} = 0b01010011010;
5391let isPredicated = 1;
5392let isTerminator = 1;
5393let isIndirectBranch = 1;
5394let isBranch = 1;
5395let cofMax1 = 1;
5396let Defs = [PC];
5397let BaseOpcode = "J2_jumpr";
5398let InputType = "reg";
5399let isTaken = Inst{12};
5400}
5401def J2_jumprt_nopred_map : HInst<
5402(outs),
5403(ins PredRegs:$Pu4, IntRegs:$Rs32),
5404"if ($Pu4) jumpr $Rs32",
5405tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5406let isPseudo = 1;
5407let isCodeGenOnly = 1;
5408}
5409def J2_jumprtnew : HInst<
5410(outs),
5411(ins PredRegs:$Pu4, IntRegs:$Rs32),
5412"if ($Pu4.new) jumpr:nt $Rs32",
5413tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5414let Inst{7-0} = 0b00000000;
5415let Inst{13-10} = 0b0010;
5416let Inst{31-21} = 0b01010011010;
5417let isPredicated = 1;
5418let isTerminator = 1;
5419let isIndirectBranch = 1;
5420let isBranch = 1;
5421let isPredicatedNew = 1;
5422let cofMax1 = 1;
5423let Defs = [PC];
5424let BaseOpcode = "J2_jumpr";
5425let InputType = "reg";
5426let isTaken = Inst{12};
5427}
5428def J2_jumprtnewpt : HInst<
5429(outs),
5430(ins PredRegs:$Pu4, IntRegs:$Rs32),
5431"if ($Pu4.new) jumpr:t $Rs32",
5432tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5433let Inst{7-0} = 0b00000000;
5434let Inst{13-10} = 0b0110;
5435let Inst{31-21} = 0b01010011010;
5436let isPredicated = 1;
5437let isTerminator = 1;
5438let isIndirectBranch = 1;
5439let isBranch = 1;
5440let isPredicatedNew = 1;
5441let cofMax1 = 1;
5442let Defs = [PC];
5443let BaseOpcode = "J2_jumpr";
5444let InputType = "reg";
5445let isTaken = Inst{12};
5446}
5447def J2_jumprtpt : HInst<
5448(outs),
5449(ins PredRegs:$Pu4, IntRegs:$Rs32),
5450"if ($Pu4) jumpr:t $Rs32",
5451tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5452let Inst{7-0} = 0b00000000;
5453let Inst{13-10} = 0b0100;
5454let Inst{31-21} = 0b01010011010;
5455let isPredicated = 1;
5456let isTerminator = 1;
5457let isIndirectBranch = 1;
5458let isBranch = 1;
5459let cofMax1 = 1;
5460let Defs = [PC];
5461let BaseOpcode = "J2_jumpr";
5462let InputType = "reg";
5463let isTaken = Inst{12};
5464}
5465def J2_jumprz : HInst<
5466(outs),
5467(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5468"if ($Rs32!=#0) jump:nt $Ii",
5469tc_57a55b54, TypeCR>, Enc_0fa531 {
5470let Inst{0-0} = 0b0;
5471let Inst{12-12} = 0b0;
5472let Inst{31-22} = 0b0110000100;
5473let isPredicated = 1;
5474let isTerminator = 1;
5475let isBranch = 1;
5476let isPredicatedNew = 1;
5477let cofRelax1 = 1;
5478let cofRelax2 = 1;
5479let cofMax1 = 1;
5480let Defs = [PC];
5481let isTaken = Inst{12};
5482}
5483def J2_jumprzpt : HInst<
5484(outs),
5485(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5486"if ($Rs32!=#0) jump:t $Ii",
5487tc_57a55b54, TypeCR>, Enc_0fa531 {
5488let Inst{0-0} = 0b0;
5489let Inst{12-12} = 0b1;
5490let Inst{31-22} = 0b0110000100;
5491let isPredicated = 1;
5492let isTerminator = 1;
5493let isBranch = 1;
5494let isPredicatedNew = 1;
5495let cofRelax1 = 1;
5496let cofRelax2 = 1;
5497let cofMax1 = 1;
5498let Defs = [PC];
5499let isTaken = Inst{12};
5500}
5501def J2_jumpt : HInst<
5502(outs),
5503(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5504"if ($Pu4) jump:nt $Ii",
5505tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5506let Inst{0-0} = 0b0;
5507let Inst{12-10} = 0b000;
5508let Inst{21-21} = 0b0;
5509let Inst{31-24} = 0b01011100;
5510let isPredicated = 1;
5511let isTerminator = 1;
5512let isBranch = 1;
5513let cofRelax1 = 1;
5514let cofRelax2 = 1;
5515let cofMax1 = 1;
5516let Defs = [PC];
5517let BaseOpcode = "J2_jump";
5518let InputType = "imm";
5519let isTaken = Inst{12};
5520let isExtendable = 1;
5521let opExtendable = 1;
5522let isExtentSigned = 1;
5523let opExtentBits = 17;
5524let opExtentAlign = 2;
5525}
5526def J2_jumpt_nopred_map : HInst<
5527(outs),
5528(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5529"if ($Pu4) jump $Ii",
5530tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5531let isPseudo = 1;
5532let isCodeGenOnly = 1;
5533}
5534def J2_jumptnew : HInst<
5535(outs),
5536(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5537"if ($Pu4.new) jump:nt $Ii",
5538tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5539let Inst{0-0} = 0b0;
5540let Inst{12-10} = 0b010;
5541let Inst{21-21} = 0b0;
5542let Inst{31-24} = 0b01011100;
5543let isPredicated = 1;
5544let isTerminator = 1;
5545let isBranch = 1;
5546let isPredicatedNew = 1;
5547let cofRelax1 = 1;
5548let cofRelax2 = 1;
5549let cofMax1 = 1;
5550let Defs = [PC];
5551let BaseOpcode = "J2_jump";
5552let InputType = "imm";
5553let isTaken = Inst{12};
5554let isExtendable = 1;
5555let opExtendable = 1;
5556let isExtentSigned = 1;
5557let opExtentBits = 17;
5558let opExtentAlign = 2;
5559}
5560def J2_jumptnewpt : HInst<
5561(outs),
5562(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5563"if ($Pu4.new) jump:t $Ii",
5564tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5565let Inst{0-0} = 0b0;
5566let Inst{12-10} = 0b110;
5567let Inst{21-21} = 0b0;
5568let Inst{31-24} = 0b01011100;
5569let isPredicated = 1;
5570let isTerminator = 1;
5571let isBranch = 1;
5572let isPredicatedNew = 1;
5573let cofRelax1 = 1;
5574let cofRelax2 = 1;
5575let cofMax1 = 1;
5576let Defs = [PC];
5577let BaseOpcode = "J2_jump";
5578let InputType = "imm";
5579let isTaken = Inst{12};
5580let isExtendable = 1;
5581let opExtendable = 1;
5582let isExtentSigned = 1;
5583let opExtentBits = 17;
5584let opExtentAlign = 2;
5585}
5586def J2_jumptpt : HInst<
5587(outs),
5588(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5589"if ($Pu4) jump:t $Ii",
5590tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5591let Inst{0-0} = 0b0;
5592let Inst{12-10} = 0b100;
5593let Inst{21-21} = 0b0;
5594let Inst{31-24} = 0b01011100;
5595let isPredicated = 1;
5596let isTerminator = 1;
5597let isBranch = 1;
5598let cofRelax1 = 1;
5599let cofRelax2 = 1;
5600let cofMax1 = 1;
5601let Defs = [PC];
5602let BaseOpcode = "J2_jump";
5603let InputType = "imm";
5604let isTaken = Inst{12};
5605let isExtendable = 1;
5606let opExtendable = 1;
5607let isExtentSigned = 1;
5608let opExtentBits = 17;
5609let opExtentAlign = 2;
5610}
5611def J2_loop0i : HInst<
5612(outs),
5613(ins b30_2Imm:$Ii, u10_0Imm:$II),
5614"loop0($Ii,#$II)",
5615tc_1248597c, TypeCR>, Enc_4dc228 {
5616let Inst{2-2} = 0b0;
5617let Inst{13-13} = 0b0;
5618let Inst{31-21} = 0b01101001000;
5619let cofRelax1 = 1;
5620let cofRelax2 = 1;
5621let Defs = [LC0, SA0, USR];
5622let isExtendable = 1;
5623let opExtendable = 0;
5624let isExtentSigned = 1;
5625let opExtentBits = 9;
5626let opExtentAlign = 2;
5627}
5628def J2_loop0r : HInst<
5629(outs),
5630(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5631"loop0($Ii,$Rs32)",
5632tc_9406230a, TypeCR>, Enc_864a5a {
5633let Inst{2-0} = 0b000;
5634let Inst{7-5} = 0b000;
5635let Inst{13-13} = 0b0;
5636let Inst{31-21} = 0b01100000000;
5637let cofRelax1 = 1;
5638let cofRelax2 = 1;
5639let Defs = [LC0, SA0, USR];
5640let isExtendable = 1;
5641let opExtendable = 0;
5642let isExtentSigned = 1;
5643let opExtentBits = 9;
5644let opExtentAlign = 2;
5645}
5646def J2_loop1i : HInst<
5647(outs),
5648(ins b30_2Imm:$Ii, u10_0Imm:$II),
5649"loop1($Ii,#$II)",
5650tc_1248597c, TypeCR>, Enc_4dc228 {
5651let Inst{2-2} = 0b0;
5652let Inst{13-13} = 0b0;
5653let Inst{31-21} = 0b01101001001;
5654let cofRelax1 = 1;
5655let cofRelax2 = 1;
5656let Defs = [LC1, SA1];
5657let isExtendable = 1;
5658let opExtendable = 0;
5659let isExtentSigned = 1;
5660let opExtentBits = 9;
5661let opExtentAlign = 2;
5662}
5663def J2_loop1r : HInst<
5664(outs),
5665(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5666"loop1($Ii,$Rs32)",
5667tc_9406230a, TypeCR>, Enc_864a5a {
5668let Inst{2-0} = 0b000;
5669let Inst{7-5} = 0b000;
5670let Inst{13-13} = 0b0;
5671let Inst{31-21} = 0b01100000001;
5672let cofRelax1 = 1;
5673let cofRelax2 = 1;
5674let Defs = [LC1, SA1];
5675let isExtendable = 1;
5676let opExtendable = 0;
5677let isExtentSigned = 1;
5678let opExtentBits = 9;
5679let opExtentAlign = 2;
5680}
5681def J2_pause : HInst<
5682(outs),
5683(ins u8_0Imm:$Ii),
5684"pause(#$Ii)",
5685tc_d57d649c, TypeJ>, Enc_a51a9a {
5686let Inst{1-0} = 0b00;
5687let Inst{7-5} = 0b000;
5688let Inst{13-13} = 0b0;
5689let Inst{31-16} = 0b0101010001000000;
5690let isSolo = 1;
5691}
5692def J2_ploop1si : HInst<
5693(outs),
5694(ins b30_2Imm:$Ii, u10_0Imm:$II),
5695"p3 = sp1loop0($Ii,#$II)",
5696tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5697let Inst{2-2} = 0b0;
5698let Inst{13-13} = 0b0;
5699let Inst{31-21} = 0b01101001101;
5700let isPredicateLate = 1;
5701let cofRelax1 = 1;
5702let cofRelax2 = 1;
5703let Defs = [LC0, P3, SA0, USR];
5704let isExtendable = 1;
5705let opExtendable = 0;
5706let isExtentSigned = 1;
5707let opExtentBits = 9;
5708let opExtentAlign = 2;
5709}
5710def J2_ploop1sr : HInst<
5711(outs),
5712(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5713"p3 = sp1loop0($Ii,$Rs32)",
5714tc_6d861a95, TypeCR>, Enc_864a5a {
5715let Inst{2-0} = 0b000;
5716let Inst{7-5} = 0b000;
5717let Inst{13-13} = 0b0;
5718let Inst{31-21} = 0b01100000101;
5719let isPredicateLate = 1;
5720let cofRelax1 = 1;
5721let cofRelax2 = 1;
5722let Defs = [LC0, P3, SA0, USR];
5723let isExtendable = 1;
5724let opExtendable = 0;
5725let isExtentSigned = 1;
5726let opExtentBits = 9;
5727let opExtentAlign = 2;
5728}
5729def J2_ploop2si : HInst<
5730(outs),
5731(ins b30_2Imm:$Ii, u10_0Imm:$II),
5732"p3 = sp2loop0($Ii,#$II)",
5733tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5734let Inst{2-2} = 0b0;
5735let Inst{13-13} = 0b0;
5736let Inst{31-21} = 0b01101001110;
5737let isPredicateLate = 1;
5738let cofRelax1 = 1;
5739let cofRelax2 = 1;
5740let Defs = [LC0, P3, SA0, USR];
5741let isExtendable = 1;
5742let opExtendable = 0;
5743let isExtentSigned = 1;
5744let opExtentBits = 9;
5745let opExtentAlign = 2;
5746}
5747def J2_ploop2sr : HInst<
5748(outs),
5749(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5750"p3 = sp2loop0($Ii,$Rs32)",
5751tc_6d861a95, TypeCR>, Enc_864a5a {
5752let Inst{2-0} = 0b000;
5753let Inst{7-5} = 0b000;
5754let Inst{13-13} = 0b0;
5755let Inst{31-21} = 0b01100000110;
5756let isPredicateLate = 1;
5757let cofRelax1 = 1;
5758let cofRelax2 = 1;
5759let Defs = [LC0, P3, SA0, USR];
5760let isExtendable = 1;
5761let opExtendable = 0;
5762let isExtentSigned = 1;
5763let opExtentBits = 9;
5764let opExtentAlign = 2;
5765}
5766def J2_ploop3si : HInst<
5767(outs),
5768(ins b30_2Imm:$Ii, u10_0Imm:$II),
5769"p3 = sp3loop0($Ii,#$II)",
5770tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5771let Inst{2-2} = 0b0;
5772let Inst{13-13} = 0b0;
5773let Inst{31-21} = 0b01101001111;
5774let isPredicateLate = 1;
5775let cofRelax1 = 1;
5776let cofRelax2 = 1;
5777let Defs = [LC0, P3, SA0, USR];
5778let isExtendable = 1;
5779let opExtendable = 0;
5780let isExtentSigned = 1;
5781let opExtentBits = 9;
5782let opExtentAlign = 2;
5783}
5784def J2_ploop3sr : HInst<
5785(outs),
5786(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5787"p3 = sp3loop0($Ii,$Rs32)",
5788tc_6d861a95, TypeCR>, Enc_864a5a {
5789let Inst{2-0} = 0b000;
5790let Inst{7-5} = 0b000;
5791let Inst{13-13} = 0b0;
5792let Inst{31-21} = 0b01100000111;
5793let isPredicateLate = 1;
5794let cofRelax1 = 1;
5795let cofRelax2 = 1;
5796let Defs = [LC0, P3, SA0, USR];
5797let isExtendable = 1;
5798let opExtendable = 0;
5799let isExtentSigned = 1;
5800let opExtentBits = 9;
5801let opExtentAlign = 2;
5802}
5803def J2_trap0 : HInst<
5804(outs),
5805(ins u8_0Imm:$Ii),
5806"trap0(#$Ii)",
5807tc_45f9d1be, TypeJ>, Enc_a51a9a {
5808let Inst{1-0} = 0b00;
5809let Inst{7-5} = 0b000;
5810let Inst{13-13} = 0b0;
5811let Inst{31-16} = 0b0101010000000000;
5812let isSolo = 1;
5813let hasSideEffects = 1;
5814}
5815def J2_trap1 : HInst<
5816(outs IntRegs:$Rx32),
5817(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
5818"trap1($Rx32,#$Ii)",
5819tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> {
5820let Inst{1-0} = 0b00;
5821let Inst{7-5} = 0b000;
5822let Inst{13-13} = 0b0;
5823let Inst{31-21} = 0b01010100100;
5824let hasNewValue = 1;
5825let opNewValue = 0;
5826let isSolo = 1;
5827let Uses = [CCR, GOSP];
5828let Defs = [CCR, GOSP, PC];
5829let hasSideEffects = 1;
5830let Constraints = "$Rx32 = $Rx32in";
5831}
5832def J2_trap1_noregmap : HInst<
5833(outs),
5834(ins u8_0Imm:$Ii),
5835"trap1(#$Ii)",
5836tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> {
5837let hasSideEffects = 1;
5838let isPseudo = 1;
5839let isCodeGenOnly = 1;
5840}
5841def J4_cmpeq_f_jumpnv_nt : HInst<
5842(outs),
5843(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5844"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5845tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5846let Inst{0-0} = 0b0;
5847let Inst{13-13} = 0b0;
5848let Inst{19-19} = 0b0;
5849let Inst{31-22} = 0b0010000001;
5850let isPredicated = 1;
5851let isPredicatedFalse = 1;
5852let isTerminator = 1;
5853let isBranch = 1;
5854let isNewValue = 1;
5855let cofMax1 = 1;
5856let isRestrictNoSlot1Store = 1;
5857let Defs = [PC];
5858let BaseOpcode = "J4_cmpeqr";
5859let isTaken = Inst{13};
5860let isExtendable = 1;
5861let opExtendable = 2;
5862let isExtentSigned = 1;
5863let opExtentBits = 11;
5864let opExtentAlign = 2;
5865let opNewValue = 0;
5866}
5867def J4_cmpeq_f_jumpnv_t : HInst<
5868(outs),
5869(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5870"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5871tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5872let Inst{0-0} = 0b0;
5873let Inst{13-13} = 0b1;
5874let Inst{19-19} = 0b0;
5875let Inst{31-22} = 0b0010000001;
5876let isPredicated = 1;
5877let isPredicatedFalse = 1;
5878let isTerminator = 1;
5879let isBranch = 1;
5880let isNewValue = 1;
5881let cofMax1 = 1;
5882let isRestrictNoSlot1Store = 1;
5883let Defs = [PC];
5884let BaseOpcode = "J4_cmpeqr";
5885let isTaken = Inst{13};
5886let isExtendable = 1;
5887let opExtendable = 2;
5888let isExtentSigned = 1;
5889let opExtentBits = 11;
5890let opExtentAlign = 2;
5891let opNewValue = 0;
5892}
5893def J4_cmpeq_fp0_jump_nt : HInst<
5894(outs),
5895(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5896"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
5897tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5898let Inst{0-0} = 0b0;
5899let Inst{13-12} = 0b00;
5900let Inst{31-22} = 0b0001010001;
5901let isPredicated = 1;
5902let isPredicatedFalse = 1;
5903let isTerminator = 1;
5904let isBranch = 1;
5905let isPredicatedNew = 1;
5906let cofRelax1 = 1;
5907let cofRelax2 = 1;
5908let cofMax1 = 1;
5909let Uses = [P0];
5910let Defs = [P0, PC];
5911let BaseOpcode = "J4_cmpeqp0";
5912let isTaken = Inst{13};
5913let isExtendable = 1;
5914let opExtendable = 2;
5915let isExtentSigned = 1;
5916let opExtentBits = 11;
5917let opExtentAlign = 2;
5918}
5919def J4_cmpeq_fp0_jump_t : HInst<
5920(outs),
5921(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5922"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
5923tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5924let Inst{0-0} = 0b0;
5925let Inst{13-12} = 0b10;
5926let Inst{31-22} = 0b0001010001;
5927let isPredicated = 1;
5928let isPredicatedFalse = 1;
5929let isTerminator = 1;
5930let isBranch = 1;
5931let isPredicatedNew = 1;
5932let cofRelax1 = 1;
5933let cofRelax2 = 1;
5934let cofMax1 = 1;
5935let Uses = [P0];
5936let Defs = [P0, PC];
5937let BaseOpcode = "J4_cmpeqp0";
5938let isTaken = Inst{13};
5939let isExtendable = 1;
5940let opExtendable = 2;
5941let isExtentSigned = 1;
5942let opExtentBits = 11;
5943let opExtentAlign = 2;
5944}
5945def J4_cmpeq_fp1_jump_nt : HInst<
5946(outs),
5947(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5948"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
5949tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5950let Inst{0-0} = 0b0;
5951let Inst{13-12} = 0b01;
5952let Inst{31-22} = 0b0001010001;
5953let isPredicated = 1;
5954let isPredicatedFalse = 1;
5955let isTerminator = 1;
5956let isBranch = 1;
5957let isPredicatedNew = 1;
5958let cofRelax1 = 1;
5959let cofRelax2 = 1;
5960let cofMax1 = 1;
5961let Uses = [P1];
5962let Defs = [P1, PC];
5963let BaseOpcode = "J4_cmpeqp1";
5964let isTaken = Inst{13};
5965let isExtendable = 1;
5966let opExtendable = 2;
5967let isExtentSigned = 1;
5968let opExtentBits = 11;
5969let opExtentAlign = 2;
5970}
5971def J4_cmpeq_fp1_jump_t : HInst<
5972(outs),
5973(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5974"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
5975tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5976let Inst{0-0} = 0b0;
5977let Inst{13-12} = 0b11;
5978let Inst{31-22} = 0b0001010001;
5979let isPredicated = 1;
5980let isPredicatedFalse = 1;
5981let isTerminator = 1;
5982let isBranch = 1;
5983let isPredicatedNew = 1;
5984let cofRelax1 = 1;
5985let cofRelax2 = 1;
5986let cofMax1 = 1;
5987let Uses = [P1];
5988let Defs = [P1, PC];
5989let BaseOpcode = "J4_cmpeqp1";
5990let isTaken = Inst{13};
5991let isExtendable = 1;
5992let opExtendable = 2;
5993let isExtentSigned = 1;
5994let opExtentBits = 11;
5995let opExtentAlign = 2;
5996}
5997def J4_cmpeq_t_jumpnv_nt : HInst<
5998(outs),
5999(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6000"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
6001tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6002let Inst{0-0} = 0b0;
6003let Inst{13-13} = 0b0;
6004let Inst{19-19} = 0b0;
6005let Inst{31-22} = 0b0010000000;
6006let isPredicated = 1;
6007let isTerminator = 1;
6008let isBranch = 1;
6009let isNewValue = 1;
6010let cofMax1 = 1;
6011let isRestrictNoSlot1Store = 1;
6012let Defs = [PC];
6013let BaseOpcode = "J4_cmpeqr";
6014let isTaken = Inst{13};
6015let isExtendable = 1;
6016let opExtendable = 2;
6017let isExtentSigned = 1;
6018let opExtentBits = 11;
6019let opExtentAlign = 2;
6020let opNewValue = 0;
6021}
6022def J4_cmpeq_t_jumpnv_t : HInst<
6023(outs),
6024(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6025"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
6026tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6027let Inst{0-0} = 0b0;
6028let Inst{13-13} = 0b1;
6029let Inst{19-19} = 0b0;
6030let Inst{31-22} = 0b0010000000;
6031let isPredicated = 1;
6032let isTerminator = 1;
6033let isBranch = 1;
6034let isNewValue = 1;
6035let cofMax1 = 1;
6036let isRestrictNoSlot1Store = 1;
6037let Defs = [PC];
6038let BaseOpcode = "J4_cmpeqr";
6039let isTaken = Inst{13};
6040let isExtendable = 1;
6041let opExtendable = 2;
6042let isExtentSigned = 1;
6043let opExtentBits = 11;
6044let opExtentAlign = 2;
6045let opNewValue = 0;
6046}
6047def J4_cmpeq_tp0_jump_nt : HInst<
6048(outs),
6049(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6050"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6051tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6052let Inst{0-0} = 0b0;
6053let Inst{13-12} = 0b00;
6054let Inst{31-22} = 0b0001010000;
6055let isPredicated = 1;
6056let isTerminator = 1;
6057let isBranch = 1;
6058let isPredicatedNew = 1;
6059let cofRelax1 = 1;
6060let cofRelax2 = 1;
6061let cofMax1 = 1;
6062let Uses = [P0];
6063let Defs = [P0, PC];
6064let BaseOpcode = "J4_cmpeqp0";
6065let isTaken = Inst{13};
6066let isExtendable = 1;
6067let opExtendable = 2;
6068let isExtentSigned = 1;
6069let opExtentBits = 11;
6070let opExtentAlign = 2;
6071}
6072def J4_cmpeq_tp0_jump_t : HInst<
6073(outs),
6074(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6075"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6076tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6077let Inst{0-0} = 0b0;
6078let Inst{13-12} = 0b10;
6079let Inst{31-22} = 0b0001010000;
6080let isPredicated = 1;
6081let isTerminator = 1;
6082let isBranch = 1;
6083let isPredicatedNew = 1;
6084let cofRelax1 = 1;
6085let cofRelax2 = 1;
6086let cofMax1 = 1;
6087let Uses = [P0];
6088let Defs = [P0, PC];
6089let BaseOpcode = "J4_cmpeqp0";
6090let isTaken = Inst{13};
6091let isExtendable = 1;
6092let opExtendable = 2;
6093let isExtentSigned = 1;
6094let opExtentBits = 11;
6095let opExtentAlign = 2;
6096}
6097def J4_cmpeq_tp1_jump_nt : HInst<
6098(outs),
6099(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6100"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
6101tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6102let Inst{0-0} = 0b0;
6103let Inst{13-12} = 0b01;
6104let Inst{31-22} = 0b0001010000;
6105let isPredicated = 1;
6106let isTerminator = 1;
6107let isBranch = 1;
6108let isPredicatedNew = 1;
6109let cofRelax1 = 1;
6110let cofRelax2 = 1;
6111let cofMax1 = 1;
6112let Uses = [P1];
6113let Defs = [P1, PC];
6114let BaseOpcode = "J4_cmpeqp1";
6115let isTaken = Inst{13};
6116let isExtendable = 1;
6117let opExtendable = 2;
6118let isExtentSigned = 1;
6119let opExtentBits = 11;
6120let opExtentAlign = 2;
6121}
6122def J4_cmpeq_tp1_jump_t : HInst<
6123(outs),
6124(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6125"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6126tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6127let Inst{0-0} = 0b0;
6128let Inst{13-12} = 0b11;
6129let Inst{31-22} = 0b0001010000;
6130let isPredicated = 1;
6131let isTerminator = 1;
6132let isBranch = 1;
6133let isPredicatedNew = 1;
6134let cofRelax1 = 1;
6135let cofRelax2 = 1;
6136let cofMax1 = 1;
6137let Uses = [P1];
6138let Defs = [P1, PC];
6139let BaseOpcode = "J4_cmpeqp1";
6140let isTaken = Inst{13};
6141let isExtendable = 1;
6142let opExtendable = 2;
6143let isExtentSigned = 1;
6144let opExtentBits = 11;
6145let opExtentAlign = 2;
6146}
6147def J4_cmpeqi_f_jumpnv_nt : HInst<
6148(outs),
6149(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6150"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6151tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6152let Inst{0-0} = 0b0;
6153let Inst{13-13} = 0b0;
6154let Inst{19-19} = 0b0;
6155let Inst{31-22} = 0b0010010001;
6156let isPredicated = 1;
6157let isPredicatedFalse = 1;
6158let isTerminator = 1;
6159let isBranch = 1;
6160let isNewValue = 1;
6161let cofMax1 = 1;
6162let isRestrictNoSlot1Store = 1;
6163let Defs = [PC];
6164let BaseOpcode = "J4_cmpeqi";
6165let isTaken = Inst{13};
6166let isExtendable = 1;
6167let opExtendable = 2;
6168let isExtentSigned = 1;
6169let opExtentBits = 11;
6170let opExtentAlign = 2;
6171let opNewValue = 0;
6172}
6173def J4_cmpeqi_f_jumpnv_t : HInst<
6174(outs),
6175(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6176"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6177tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6178let Inst{0-0} = 0b0;
6179let Inst{13-13} = 0b1;
6180let Inst{19-19} = 0b0;
6181let Inst{31-22} = 0b0010010001;
6182let isPredicated = 1;
6183let isPredicatedFalse = 1;
6184let isTerminator = 1;
6185let isBranch = 1;
6186let isNewValue = 1;
6187let cofMax1 = 1;
6188let isRestrictNoSlot1Store = 1;
6189let Defs = [PC];
6190let BaseOpcode = "J4_cmpeqi";
6191let isTaken = Inst{13};
6192let isExtendable = 1;
6193let opExtendable = 2;
6194let isExtentSigned = 1;
6195let opExtentBits = 11;
6196let opExtentAlign = 2;
6197let opNewValue = 0;
6198}
6199def J4_cmpeqi_fp0_jump_nt : HInst<
6200(outs),
6201(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6202"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
6203tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6204let Inst{0-0} = 0b0;
6205let Inst{13-13} = 0b0;
6206let Inst{31-22} = 0b0001000001;
6207let isPredicated = 1;
6208let isPredicatedFalse = 1;
6209let isTerminator = 1;
6210let isBranch = 1;
6211let isPredicatedNew = 1;
6212let cofRelax1 = 1;
6213let cofRelax2 = 1;
6214let cofMax1 = 1;
6215let Uses = [P0];
6216let Defs = [P0, PC];
6217let BaseOpcode = "J4_cmpeqip0";
6218let isTaken = Inst{13};
6219let isExtendable = 1;
6220let opExtendable = 2;
6221let isExtentSigned = 1;
6222let opExtentBits = 11;
6223let opExtentAlign = 2;
6224}
6225def J4_cmpeqi_fp0_jump_t : HInst<
6226(outs),
6227(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6228"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
6229tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6230let Inst{0-0} = 0b0;
6231let Inst{13-13} = 0b1;
6232let Inst{31-22} = 0b0001000001;
6233let isPredicated = 1;
6234let isPredicatedFalse = 1;
6235let isTerminator = 1;
6236let isBranch = 1;
6237let isPredicatedNew = 1;
6238let cofRelax1 = 1;
6239let cofRelax2 = 1;
6240let cofMax1 = 1;
6241let Uses = [P0];
6242let Defs = [P0, PC];
6243let BaseOpcode = "J4_cmpeqip0";
6244let isTaken = Inst{13};
6245let isExtendable = 1;
6246let opExtendable = 2;
6247let isExtentSigned = 1;
6248let opExtentBits = 11;
6249let opExtentAlign = 2;
6250}
6251def J4_cmpeqi_fp1_jump_nt : HInst<
6252(outs),
6253(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6254"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6255tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6256let Inst{0-0} = 0b0;
6257let Inst{13-13} = 0b0;
6258let Inst{31-22} = 0b0001001001;
6259let isPredicated = 1;
6260let isPredicatedFalse = 1;
6261let isTerminator = 1;
6262let isBranch = 1;
6263let isPredicatedNew = 1;
6264let cofRelax1 = 1;
6265let cofRelax2 = 1;
6266let cofMax1 = 1;
6267let Uses = [P1];
6268let Defs = [P1, PC];
6269let BaseOpcode = "J4_cmpeqip1";
6270let isTaken = Inst{13};
6271let isExtendable = 1;
6272let opExtendable = 2;
6273let isExtentSigned = 1;
6274let opExtentBits = 11;
6275let opExtentAlign = 2;
6276}
6277def J4_cmpeqi_fp1_jump_t : HInst<
6278(outs),
6279(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6280"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
6281tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6282let Inst{0-0} = 0b0;
6283let Inst{13-13} = 0b1;
6284let Inst{31-22} = 0b0001001001;
6285let isPredicated = 1;
6286let isPredicatedFalse = 1;
6287let isTerminator = 1;
6288let isBranch = 1;
6289let isPredicatedNew = 1;
6290let cofRelax1 = 1;
6291let cofRelax2 = 1;
6292let cofMax1 = 1;
6293let Uses = [P1];
6294let Defs = [P1, PC];
6295let BaseOpcode = "J4_cmpeqip1";
6296let isTaken = Inst{13};
6297let isExtendable = 1;
6298let opExtendable = 2;
6299let isExtentSigned = 1;
6300let opExtentBits = 11;
6301let opExtentAlign = 2;
6302}
6303def J4_cmpeqi_t_jumpnv_nt : HInst<
6304(outs),
6305(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6306"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6307tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6308let Inst{0-0} = 0b0;
6309let Inst{13-13} = 0b0;
6310let Inst{19-19} = 0b0;
6311let Inst{31-22} = 0b0010010000;
6312let isPredicated = 1;
6313let isTerminator = 1;
6314let isBranch = 1;
6315let isNewValue = 1;
6316let cofMax1 = 1;
6317let isRestrictNoSlot1Store = 1;
6318let Defs = [PC];
6319let BaseOpcode = "J4_cmpeqi";
6320let isTaken = Inst{13};
6321let isExtendable = 1;
6322let opExtendable = 2;
6323let isExtentSigned = 1;
6324let opExtentBits = 11;
6325let opExtentAlign = 2;
6326let opNewValue = 0;
6327}
6328def J4_cmpeqi_t_jumpnv_t : HInst<
6329(outs),
6330(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6331"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6332tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6333let Inst{0-0} = 0b0;
6334let Inst{13-13} = 0b1;
6335let Inst{19-19} = 0b0;
6336let Inst{31-22} = 0b0010010000;
6337let isPredicated = 1;
6338let isTerminator = 1;
6339let isBranch = 1;
6340let isNewValue = 1;
6341let cofMax1 = 1;
6342let isRestrictNoSlot1Store = 1;
6343let Defs = [PC];
6344let BaseOpcode = "J4_cmpeqi";
6345let isTaken = Inst{13};
6346let isExtendable = 1;
6347let opExtendable = 2;
6348let isExtentSigned = 1;
6349let opExtentBits = 11;
6350let opExtentAlign = 2;
6351let opNewValue = 0;
6352}
6353def J4_cmpeqi_tp0_jump_nt : HInst<
6354(outs),
6355(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6356"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
6357tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6358let Inst{0-0} = 0b0;
6359let Inst{13-13} = 0b0;
6360let Inst{31-22} = 0b0001000000;
6361let isPredicated = 1;
6362let isTerminator = 1;
6363let isBranch = 1;
6364let isPredicatedNew = 1;
6365let cofRelax1 = 1;
6366let cofRelax2 = 1;
6367let cofMax1 = 1;
6368let Uses = [P0];
6369let Defs = [P0, PC];
6370let BaseOpcode = "J4_cmpeqip0";
6371let isTaken = Inst{13};
6372let isExtendable = 1;
6373let opExtendable = 2;
6374let isExtentSigned = 1;
6375let opExtentBits = 11;
6376let opExtentAlign = 2;
6377}
6378def J4_cmpeqi_tp0_jump_t : HInst<
6379(outs),
6380(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6381"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
6382tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6383let Inst{0-0} = 0b0;
6384let Inst{13-13} = 0b1;
6385let Inst{31-22} = 0b0001000000;
6386let isPredicated = 1;
6387let isTerminator = 1;
6388let isBranch = 1;
6389let isPredicatedNew = 1;
6390let cofRelax1 = 1;
6391let cofRelax2 = 1;
6392let cofMax1 = 1;
6393let Uses = [P0];
6394let Defs = [P0, PC];
6395let BaseOpcode = "J4_cmpeqip0";
6396let isTaken = Inst{13};
6397let isExtendable = 1;
6398let opExtendable = 2;
6399let isExtentSigned = 1;
6400let opExtentBits = 11;
6401let opExtentAlign = 2;
6402}
6403def J4_cmpeqi_tp1_jump_nt : HInst<
6404(outs),
6405(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6406"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
6407tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6408let Inst{0-0} = 0b0;
6409let Inst{13-13} = 0b0;
6410let Inst{31-22} = 0b0001001000;
6411let isPredicated = 1;
6412let isTerminator = 1;
6413let isBranch = 1;
6414let isPredicatedNew = 1;
6415let cofRelax1 = 1;
6416let cofRelax2 = 1;
6417let cofMax1 = 1;
6418let Uses = [P1];
6419let Defs = [P1, PC];
6420let BaseOpcode = "J4_cmpeqip1";
6421let isTaken = Inst{13};
6422let isExtendable = 1;
6423let opExtendable = 2;
6424let isExtentSigned = 1;
6425let opExtentBits = 11;
6426let opExtentAlign = 2;
6427}
6428def J4_cmpeqi_tp1_jump_t : HInst<
6429(outs),
6430(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6431"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
6432tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6433let Inst{0-0} = 0b0;
6434let Inst{13-13} = 0b1;
6435let Inst{31-22} = 0b0001001000;
6436let isPredicated = 1;
6437let isTerminator = 1;
6438let isBranch = 1;
6439let isPredicatedNew = 1;
6440let cofRelax1 = 1;
6441let cofRelax2 = 1;
6442let cofMax1 = 1;
6443let Uses = [P1];
6444let Defs = [P1, PC];
6445let BaseOpcode = "J4_cmpeqip1";
6446let isTaken = Inst{13};
6447let isExtendable = 1;
6448let opExtendable = 2;
6449let isExtentSigned = 1;
6450let opExtentBits = 11;
6451let opExtentAlign = 2;
6452}
6453def J4_cmpeqn1_f_jumpnv_nt : HInst<
6454(outs),
6455(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6456"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6457tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel {
6458let Inst{0-0} = 0b0;
6459let Inst{13-8} = 0b000000;
6460let Inst{19-19} = 0b0;
6461let Inst{31-22} = 0b0010011001;
6462let isPredicated = 1;
6463let isPredicatedFalse = 1;
6464let isTerminator = 1;
6465let isBranch = 1;
6466let isNewValue = 1;
6467let cofMax1 = 1;
6468let isRestrictNoSlot1Store = 1;
6469let Defs = [PC];
6470let BaseOpcode = "J4_cmpeqn1r";
6471let isTaken = Inst{13};
6472let isExtendable = 1;
6473let opExtendable = 2;
6474let isExtentSigned = 1;
6475let opExtentBits = 11;
6476let opExtentAlign = 2;
6477let opNewValue = 0;
6478}
6479def J4_cmpeqn1_f_jumpnv_t : HInst<
6480(outs),
6481(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6482"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6483tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel {
6484let Inst{0-0} = 0b0;
6485let Inst{13-8} = 0b100000;
6486let Inst{19-19} = 0b0;
6487let Inst{31-22} = 0b0010011001;
6488let isPredicated = 1;
6489let isPredicatedFalse = 1;
6490let isTerminator = 1;
6491let isBranch = 1;
6492let isNewValue = 1;
6493let cofMax1 = 1;
6494let isRestrictNoSlot1Store = 1;
6495let Defs = [PC];
6496let BaseOpcode = "J4_cmpeqn1r";
6497let isTaken = Inst{13};
6498let isExtendable = 1;
6499let opExtendable = 2;
6500let isExtentSigned = 1;
6501let opExtentBits = 11;
6502let opExtentAlign = 2;
6503let opNewValue = 0;
6504}
6505def J4_cmpeqn1_fp0_jump_nt : HInst<
6506(outs),
6507(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6508"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
6509tc_24f426ab, TypeCJ>, Enc_1de724, PredRel {
6510let Inst{0-0} = 0b0;
6511let Inst{13-8} = 0b000000;
6512let Inst{31-22} = 0b0001000111;
6513let isPredicated = 1;
6514let isPredicatedFalse = 1;
6515let isTerminator = 1;
6516let isBranch = 1;
6517let isPredicatedNew = 1;
6518let cofRelax1 = 1;
6519let cofRelax2 = 1;
6520let cofMax1 = 1;
6521let Uses = [P0];
6522let Defs = [P0, PC];
6523let BaseOpcode = "J4_cmpeqn1p0";
6524let isTaken = Inst{13};
6525let isExtendable = 1;
6526let opExtendable = 2;
6527let isExtentSigned = 1;
6528let opExtentBits = 11;
6529let opExtentAlign = 2;
6530}
6531def J4_cmpeqn1_fp0_jump_t : HInst<
6532(outs),
6533(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6534"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
6535tc_24f426ab, TypeCJ>, Enc_14640c, PredRel {
6536let Inst{0-0} = 0b0;
6537let Inst{13-8} = 0b100000;
6538let Inst{31-22} = 0b0001000111;
6539let isPredicated = 1;
6540let isPredicatedFalse = 1;
6541let isTerminator = 1;
6542let isBranch = 1;
6543let isPredicatedNew = 1;
6544let cofRelax1 = 1;
6545let cofRelax2 = 1;
6546let cofMax1 = 1;
6547let Uses = [P0];
6548let Defs = [P0, PC];
6549let BaseOpcode = "J4_cmpeqn1p0";
6550let isTaken = Inst{13};
6551let isExtendable = 1;
6552let opExtendable = 2;
6553let isExtentSigned = 1;
6554let opExtentBits = 11;
6555let opExtentAlign = 2;
6556}
6557def J4_cmpeqn1_fp1_jump_nt : HInst<
6558(outs),
6559(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6560"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
6561tc_24f426ab, TypeCJ>, Enc_668704, PredRel {
6562let Inst{0-0} = 0b0;
6563let Inst{13-8} = 0b000000;
6564let Inst{31-22} = 0b0001001111;
6565let isPredicated = 1;
6566let isPredicatedFalse = 1;
6567let isTerminator = 1;
6568let isBranch = 1;
6569let isPredicatedNew = 1;
6570let cofRelax1 = 1;
6571let cofRelax2 = 1;
6572let cofMax1 = 1;
6573let Uses = [P1];
6574let Defs = [P1, PC];
6575let BaseOpcode = "J4_cmpeqn1p1";
6576let isTaken = Inst{13};
6577let isExtendable = 1;
6578let opExtendable = 2;
6579let isExtentSigned = 1;
6580let opExtentBits = 11;
6581let opExtentAlign = 2;
6582}
6583def J4_cmpeqn1_fp1_jump_t : HInst<
6584(outs),
6585(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6586"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
6587tc_24f426ab, TypeCJ>, Enc_800e04, PredRel {
6588let Inst{0-0} = 0b0;
6589let Inst{13-8} = 0b100000;
6590let Inst{31-22} = 0b0001001111;
6591let isPredicated = 1;
6592let isPredicatedFalse = 1;
6593let isTerminator = 1;
6594let isBranch = 1;
6595let isPredicatedNew = 1;
6596let cofRelax1 = 1;
6597let cofRelax2 = 1;
6598let cofMax1 = 1;
6599let Uses = [P1];
6600let Defs = [P1, PC];
6601let BaseOpcode = "J4_cmpeqn1p1";
6602let isTaken = Inst{13};
6603let isExtendable = 1;
6604let opExtendable = 2;
6605let isExtentSigned = 1;
6606let opExtentBits = 11;
6607let opExtentAlign = 2;
6608}
6609def J4_cmpeqn1_t_jumpnv_nt : HInst<
6610(outs),
6611(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6612"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6613tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel {
6614let Inst{0-0} = 0b0;
6615let Inst{13-8} = 0b000000;
6616let Inst{19-19} = 0b0;
6617let Inst{31-22} = 0b0010011000;
6618let isPredicated = 1;
6619let isTerminator = 1;
6620let isBranch = 1;
6621let isNewValue = 1;
6622let cofMax1 = 1;
6623let isRestrictNoSlot1Store = 1;
6624let Defs = [PC];
6625let BaseOpcode = "J4_cmpeqn1r";
6626let isTaken = Inst{13};
6627let isExtendable = 1;
6628let opExtendable = 2;
6629let isExtentSigned = 1;
6630let opExtentBits = 11;
6631let opExtentAlign = 2;
6632let opNewValue = 0;
6633}
6634def J4_cmpeqn1_t_jumpnv_t : HInst<
6635(outs),
6636(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6637"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6638tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel {
6639let Inst{0-0} = 0b0;
6640let Inst{13-8} = 0b100000;
6641let Inst{19-19} = 0b0;
6642let Inst{31-22} = 0b0010011000;
6643let isPredicated = 1;
6644let isTerminator = 1;
6645let isBranch = 1;
6646let isNewValue = 1;
6647let cofMax1 = 1;
6648let isRestrictNoSlot1Store = 1;
6649let Defs = [PC];
6650let BaseOpcode = "J4_cmpeqn1r";
6651let isTaken = Inst{13};
6652let isExtendable = 1;
6653let opExtendable = 2;
6654let isExtentSigned = 1;
6655let opExtentBits = 11;
6656let opExtentAlign = 2;
6657let opNewValue = 0;
6658}
6659def J4_cmpeqn1_tp0_jump_nt : HInst<
6660(outs),
6661(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6662"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
6663tc_24f426ab, TypeCJ>, Enc_405228, PredRel {
6664let Inst{0-0} = 0b0;
6665let Inst{13-8} = 0b000000;
6666let Inst{31-22} = 0b0001000110;
6667let isPredicated = 1;
6668let isTerminator = 1;
6669let isBranch = 1;
6670let isPredicatedNew = 1;
6671let cofRelax1 = 1;
6672let cofRelax2 = 1;
6673let cofMax1 = 1;
6674let Uses = [P0];
6675let Defs = [P0, PC];
6676let BaseOpcode = "J4_cmpeqn1p0";
6677let isTaken = Inst{13};
6678let isExtendable = 1;
6679let opExtendable = 2;
6680let isExtentSigned = 1;
6681let opExtentBits = 11;
6682let opExtentAlign = 2;
6683}
6684def J4_cmpeqn1_tp0_jump_t : HInst<
6685(outs),
6686(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6687"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
6688tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel {
6689let Inst{0-0} = 0b0;
6690let Inst{13-8} = 0b100000;
6691let Inst{31-22} = 0b0001000110;
6692let isPredicated = 1;
6693let isTerminator = 1;
6694let isBranch = 1;
6695let isPredicatedNew = 1;
6696let cofRelax1 = 1;
6697let cofRelax2 = 1;
6698let cofMax1 = 1;
6699let Uses = [P0];
6700let Defs = [P0, PC];
6701let BaseOpcode = "J4_cmpeqn1p0";
6702let isTaken = Inst{13};
6703let isExtendable = 1;
6704let opExtendable = 2;
6705let isExtentSigned = 1;
6706let opExtentBits = 11;
6707let opExtentAlign = 2;
6708}
6709def J4_cmpeqn1_tp1_jump_nt : HInst<
6710(outs),
6711(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6712"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
6713tc_24f426ab, TypeCJ>, Enc_736575, PredRel {
6714let Inst{0-0} = 0b0;
6715let Inst{13-8} = 0b000000;
6716let Inst{31-22} = 0b0001001110;
6717let isPredicated = 1;
6718let isTerminator = 1;
6719let isBranch = 1;
6720let isPredicatedNew = 1;
6721let cofRelax1 = 1;
6722let cofRelax2 = 1;
6723let cofMax1 = 1;
6724let Uses = [P1];
6725let Defs = [P1, PC];
6726let BaseOpcode = "J4_cmpeqn1p1";
6727let isTaken = Inst{13};
6728let isExtendable = 1;
6729let opExtendable = 2;
6730let isExtentSigned = 1;
6731let opExtentBits = 11;
6732let opExtentAlign = 2;
6733}
6734def J4_cmpeqn1_tp1_jump_t : HInst<
6735(outs),
6736(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6737"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
6738tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel {
6739let Inst{0-0} = 0b0;
6740let Inst{13-8} = 0b100000;
6741let Inst{31-22} = 0b0001001110;
6742let isPredicated = 1;
6743let isTerminator = 1;
6744let isBranch = 1;
6745let isPredicatedNew = 1;
6746let cofRelax1 = 1;
6747let cofRelax2 = 1;
6748let cofMax1 = 1;
6749let Uses = [P1];
6750let Defs = [P1, PC];
6751let BaseOpcode = "J4_cmpeqn1p1";
6752let isTaken = Inst{13};
6753let isExtendable = 1;
6754let opExtendable = 2;
6755let isExtentSigned = 1;
6756let opExtentBits = 11;
6757let opExtentAlign = 2;
6758}
6759def J4_cmpgt_f_jumpnv_nt : HInst<
6760(outs),
6761(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6762"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6763tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6764let Inst{0-0} = 0b0;
6765let Inst{13-13} = 0b0;
6766let Inst{19-19} = 0b0;
6767let Inst{31-22} = 0b0010000011;
6768let isPredicated = 1;
6769let isPredicatedFalse = 1;
6770let isTerminator = 1;
6771let isBranch = 1;
6772let isNewValue = 1;
6773let cofMax1 = 1;
6774let isRestrictNoSlot1Store = 1;
6775let Defs = [PC];
6776let BaseOpcode = "J4_cmpgtr";
6777let isTaken = Inst{13};
6778let isExtendable = 1;
6779let opExtendable = 2;
6780let isExtentSigned = 1;
6781let opExtentBits = 11;
6782let opExtentAlign = 2;
6783let opNewValue = 0;
6784}
6785def J4_cmpgt_f_jumpnv_t : HInst<
6786(outs),
6787(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6788"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6789tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6790let Inst{0-0} = 0b0;
6791let Inst{13-13} = 0b1;
6792let Inst{19-19} = 0b0;
6793let Inst{31-22} = 0b0010000011;
6794let isPredicated = 1;
6795let isPredicatedFalse = 1;
6796let isTerminator = 1;
6797let isBranch = 1;
6798let isNewValue = 1;
6799let cofMax1 = 1;
6800let isRestrictNoSlot1Store = 1;
6801let Defs = [PC];
6802let BaseOpcode = "J4_cmpgtr";
6803let isTaken = Inst{13};
6804let isExtendable = 1;
6805let opExtendable = 2;
6806let isExtentSigned = 1;
6807let opExtentBits = 11;
6808let opExtentAlign = 2;
6809let opNewValue = 0;
6810}
6811def J4_cmpgt_fp0_jump_nt : HInst<
6812(outs),
6813(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6814"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
6815tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6816let Inst{0-0} = 0b0;
6817let Inst{13-12} = 0b00;
6818let Inst{31-22} = 0b0001010011;
6819let isPredicated = 1;
6820let isPredicatedFalse = 1;
6821let isTerminator = 1;
6822let isBranch = 1;
6823let isPredicatedNew = 1;
6824let cofRelax1 = 1;
6825let cofRelax2 = 1;
6826let cofMax1 = 1;
6827let Uses = [P0];
6828let Defs = [P0, PC];
6829let BaseOpcode = "J4_cmpgtp0";
6830let isTaken = Inst{13};
6831let isExtendable = 1;
6832let opExtendable = 2;
6833let isExtentSigned = 1;
6834let opExtentBits = 11;
6835let opExtentAlign = 2;
6836}
6837def J4_cmpgt_fp0_jump_t : HInst<
6838(outs),
6839(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6840"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
6841tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6842let Inst{0-0} = 0b0;
6843let Inst{13-12} = 0b10;
6844let Inst{31-22} = 0b0001010011;
6845let isPredicated = 1;
6846let isPredicatedFalse = 1;
6847let isTerminator = 1;
6848let isBranch = 1;
6849let isPredicatedNew = 1;
6850let cofRelax1 = 1;
6851let cofRelax2 = 1;
6852let cofMax1 = 1;
6853let Uses = [P0];
6854let Defs = [P0, PC];
6855let BaseOpcode = "J4_cmpgtp0";
6856let isTaken = Inst{13};
6857let isExtendable = 1;
6858let opExtendable = 2;
6859let isExtentSigned = 1;
6860let opExtentBits = 11;
6861let opExtentAlign = 2;
6862}
6863def J4_cmpgt_fp1_jump_nt : HInst<
6864(outs),
6865(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6866"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
6867tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6868let Inst{0-0} = 0b0;
6869let Inst{13-12} = 0b01;
6870let Inst{31-22} = 0b0001010011;
6871let isPredicated = 1;
6872let isPredicatedFalse = 1;
6873let isTerminator = 1;
6874let isBranch = 1;
6875let isPredicatedNew = 1;
6876let cofRelax1 = 1;
6877let cofRelax2 = 1;
6878let cofMax1 = 1;
6879let Uses = [P1];
6880let Defs = [P1, PC];
6881let BaseOpcode = "J4_cmpgtp1";
6882let isTaken = Inst{13};
6883let isExtendable = 1;
6884let opExtendable = 2;
6885let isExtentSigned = 1;
6886let opExtentBits = 11;
6887let opExtentAlign = 2;
6888}
6889def J4_cmpgt_fp1_jump_t : HInst<
6890(outs),
6891(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6892"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6893tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6894let Inst{0-0} = 0b0;
6895let Inst{13-12} = 0b11;
6896let Inst{31-22} = 0b0001010011;
6897let isPredicated = 1;
6898let isPredicatedFalse = 1;
6899let isTerminator = 1;
6900let isBranch = 1;
6901let isPredicatedNew = 1;
6902let cofRelax1 = 1;
6903let cofRelax2 = 1;
6904let cofMax1 = 1;
6905let Uses = [P1];
6906let Defs = [P1, PC];
6907let BaseOpcode = "J4_cmpgtp1";
6908let isTaken = Inst{13};
6909let isExtendable = 1;
6910let opExtendable = 2;
6911let isExtentSigned = 1;
6912let opExtentBits = 11;
6913let opExtentAlign = 2;
6914}
6915def J4_cmpgt_t_jumpnv_nt : HInst<
6916(outs),
6917(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6918"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6919tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6920let Inst{0-0} = 0b0;
6921let Inst{13-13} = 0b0;
6922let Inst{19-19} = 0b0;
6923let Inst{31-22} = 0b0010000010;
6924let isPredicated = 1;
6925let isTerminator = 1;
6926let isBranch = 1;
6927let isNewValue = 1;
6928let cofMax1 = 1;
6929let isRestrictNoSlot1Store = 1;
6930let Defs = [PC];
6931let BaseOpcode = "J4_cmpgtr";
6932let isTaken = Inst{13};
6933let isExtendable = 1;
6934let opExtendable = 2;
6935let isExtentSigned = 1;
6936let opExtentBits = 11;
6937let opExtentAlign = 2;
6938let opNewValue = 0;
6939}
6940def J4_cmpgt_t_jumpnv_t : HInst<
6941(outs),
6942(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6943"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6944tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6945let Inst{0-0} = 0b0;
6946let Inst{13-13} = 0b1;
6947let Inst{19-19} = 0b0;
6948let Inst{31-22} = 0b0010000010;
6949let isPredicated = 1;
6950let isTerminator = 1;
6951let isBranch = 1;
6952let isNewValue = 1;
6953let cofMax1 = 1;
6954let isRestrictNoSlot1Store = 1;
6955let Defs = [PC];
6956let BaseOpcode = "J4_cmpgtr";
6957let isTaken = Inst{13};
6958let isExtendable = 1;
6959let opExtendable = 2;
6960let isExtentSigned = 1;
6961let opExtentBits = 11;
6962let opExtentAlign = 2;
6963let opNewValue = 0;
6964}
6965def J4_cmpgt_tp0_jump_nt : HInst<
6966(outs),
6967(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6968"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6969tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6970let Inst{0-0} = 0b0;
6971let Inst{13-12} = 0b00;
6972let Inst{31-22} = 0b0001010010;
6973let isPredicated = 1;
6974let isTerminator = 1;
6975let isBranch = 1;
6976let isPredicatedNew = 1;
6977let cofRelax1 = 1;
6978let cofRelax2 = 1;
6979let cofMax1 = 1;
6980let Uses = [P0];
6981let Defs = [P0, PC];
6982let BaseOpcode = "J4_cmpgtp0";
6983let isTaken = Inst{13};
6984let isExtendable = 1;
6985let opExtendable = 2;
6986let isExtentSigned = 1;
6987let opExtentBits = 11;
6988let opExtentAlign = 2;
6989}
6990def J4_cmpgt_tp0_jump_t : HInst<
6991(outs),
6992(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6993"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6994tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6995let Inst{0-0} = 0b0;
6996let Inst{13-12} = 0b10;
6997let Inst{31-22} = 0b0001010010;
6998let isPredicated = 1;
6999let isTerminator = 1;
7000let isBranch = 1;
7001let isPredicatedNew = 1;
7002let cofRelax1 = 1;
7003let cofRelax2 = 1;
7004let cofMax1 = 1;
7005let Uses = [P0];
7006let Defs = [P0, PC];
7007let BaseOpcode = "J4_cmpgtp0";
7008let isTaken = Inst{13};
7009let isExtendable = 1;
7010let opExtendable = 2;
7011let isExtentSigned = 1;
7012let opExtentBits = 11;
7013let opExtentAlign = 2;
7014}
7015def J4_cmpgt_tp1_jump_nt : HInst<
7016(outs),
7017(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7018"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7019tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7020let Inst{0-0} = 0b0;
7021let Inst{13-12} = 0b01;
7022let Inst{31-22} = 0b0001010010;
7023let isPredicated = 1;
7024let isTerminator = 1;
7025let isBranch = 1;
7026let isPredicatedNew = 1;
7027let cofRelax1 = 1;
7028let cofRelax2 = 1;
7029let cofMax1 = 1;
7030let Uses = [P1];
7031let Defs = [P1, PC];
7032let BaseOpcode = "J4_cmpgtp1";
7033let isTaken = Inst{13};
7034let isExtendable = 1;
7035let opExtendable = 2;
7036let isExtentSigned = 1;
7037let opExtentBits = 11;
7038let opExtentAlign = 2;
7039}
7040def J4_cmpgt_tp1_jump_t : HInst<
7041(outs),
7042(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7043"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7044tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7045let Inst{0-0} = 0b0;
7046let Inst{13-12} = 0b11;
7047let Inst{31-22} = 0b0001010010;
7048let isPredicated = 1;
7049let isTerminator = 1;
7050let isBranch = 1;
7051let isPredicatedNew = 1;
7052let cofRelax1 = 1;
7053let cofRelax2 = 1;
7054let cofMax1 = 1;
7055let Uses = [P1];
7056let Defs = [P1, PC];
7057let BaseOpcode = "J4_cmpgtp1";
7058let isTaken = Inst{13};
7059let isExtendable = 1;
7060let opExtendable = 2;
7061let isExtentSigned = 1;
7062let opExtentBits = 11;
7063let opExtentAlign = 2;
7064}
7065def J4_cmpgti_f_jumpnv_nt : HInst<
7066(outs),
7067(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7068"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7069tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7070let Inst{0-0} = 0b0;
7071let Inst{13-13} = 0b0;
7072let Inst{19-19} = 0b0;
7073let Inst{31-22} = 0b0010010011;
7074let isPredicated = 1;
7075let isPredicatedFalse = 1;
7076let isTerminator = 1;
7077let isBranch = 1;
7078let isNewValue = 1;
7079let cofMax1 = 1;
7080let isRestrictNoSlot1Store = 1;
7081let Defs = [PC];
7082let BaseOpcode = "J4_cmpgtir";
7083let isTaken = Inst{13};
7084let isExtendable = 1;
7085let opExtendable = 2;
7086let isExtentSigned = 1;
7087let opExtentBits = 11;
7088let opExtentAlign = 2;
7089let opNewValue = 0;
7090}
7091def J4_cmpgti_f_jumpnv_t : HInst<
7092(outs),
7093(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7094"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7095tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7096let Inst{0-0} = 0b0;
7097let Inst{13-13} = 0b1;
7098let Inst{19-19} = 0b0;
7099let Inst{31-22} = 0b0010010011;
7100let isPredicated = 1;
7101let isPredicatedFalse = 1;
7102let isTerminator = 1;
7103let isBranch = 1;
7104let isNewValue = 1;
7105let cofMax1 = 1;
7106let isRestrictNoSlot1Store = 1;
7107let Defs = [PC];
7108let BaseOpcode = "J4_cmpgtir";
7109let isTaken = Inst{13};
7110let isExtendable = 1;
7111let opExtendable = 2;
7112let isExtentSigned = 1;
7113let opExtentBits = 11;
7114let opExtentAlign = 2;
7115let opNewValue = 0;
7116}
7117def J4_cmpgti_fp0_jump_nt : HInst<
7118(outs),
7119(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7120"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7121tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7122let Inst{0-0} = 0b0;
7123let Inst{13-13} = 0b0;
7124let Inst{31-22} = 0b0001000011;
7125let isPredicated = 1;
7126let isPredicatedFalse = 1;
7127let isTerminator = 1;
7128let isBranch = 1;
7129let isPredicatedNew = 1;
7130let cofRelax1 = 1;
7131let cofRelax2 = 1;
7132let cofMax1 = 1;
7133let Uses = [P0];
7134let Defs = [P0, PC];
7135let BaseOpcode = "J4_cmpgtip0";
7136let isTaken = Inst{13};
7137let isExtendable = 1;
7138let opExtendable = 2;
7139let isExtentSigned = 1;
7140let opExtentBits = 11;
7141let opExtentAlign = 2;
7142}
7143def J4_cmpgti_fp0_jump_t : HInst<
7144(outs),
7145(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7146"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
7147tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7148let Inst{0-0} = 0b0;
7149let Inst{13-13} = 0b1;
7150let Inst{31-22} = 0b0001000011;
7151let isPredicated = 1;
7152let isPredicatedFalse = 1;
7153let isTerminator = 1;
7154let isBranch = 1;
7155let isPredicatedNew = 1;
7156let cofRelax1 = 1;
7157let cofRelax2 = 1;
7158let cofMax1 = 1;
7159let Uses = [P0];
7160let Defs = [P0, PC];
7161let BaseOpcode = "J4_cmpgtip0";
7162let isTaken = Inst{13};
7163let isExtendable = 1;
7164let opExtendable = 2;
7165let isExtentSigned = 1;
7166let opExtentBits = 11;
7167let opExtentAlign = 2;
7168}
7169def J4_cmpgti_fp1_jump_nt : HInst<
7170(outs),
7171(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7172"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7173tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7174let Inst{0-0} = 0b0;
7175let Inst{13-13} = 0b0;
7176let Inst{31-22} = 0b0001001011;
7177let isPredicated = 1;
7178let isPredicatedFalse = 1;
7179let isTerminator = 1;
7180let isBranch = 1;
7181let isPredicatedNew = 1;
7182let cofRelax1 = 1;
7183let cofRelax2 = 1;
7184let cofMax1 = 1;
7185let Uses = [P1];
7186let Defs = [P1, PC];
7187let BaseOpcode = "J4_cmpgtip1";
7188let isTaken = Inst{13};
7189let isExtendable = 1;
7190let opExtendable = 2;
7191let isExtentSigned = 1;
7192let opExtentBits = 11;
7193let opExtentAlign = 2;
7194}
7195def J4_cmpgti_fp1_jump_t : HInst<
7196(outs),
7197(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7198"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
7199tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7200let Inst{0-0} = 0b0;
7201let Inst{13-13} = 0b1;
7202let Inst{31-22} = 0b0001001011;
7203let isPredicated = 1;
7204let isPredicatedFalse = 1;
7205let isTerminator = 1;
7206let isBranch = 1;
7207let isPredicatedNew = 1;
7208let cofRelax1 = 1;
7209let cofRelax2 = 1;
7210let cofMax1 = 1;
7211let Uses = [P1];
7212let Defs = [P1, PC];
7213let BaseOpcode = "J4_cmpgtip1";
7214let isTaken = Inst{13};
7215let isExtendable = 1;
7216let opExtendable = 2;
7217let isExtentSigned = 1;
7218let opExtentBits = 11;
7219let opExtentAlign = 2;
7220}
7221def J4_cmpgti_t_jumpnv_nt : HInst<
7222(outs),
7223(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7224"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7225tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7226let Inst{0-0} = 0b0;
7227let Inst{13-13} = 0b0;
7228let Inst{19-19} = 0b0;
7229let Inst{31-22} = 0b0010010010;
7230let isPredicated = 1;
7231let isTerminator = 1;
7232let isBranch = 1;
7233let isNewValue = 1;
7234let cofMax1 = 1;
7235let isRestrictNoSlot1Store = 1;
7236let Defs = [PC];
7237let BaseOpcode = "J4_cmpgtir";
7238let isTaken = Inst{13};
7239let isExtendable = 1;
7240let opExtendable = 2;
7241let isExtentSigned = 1;
7242let opExtentBits = 11;
7243let opExtentAlign = 2;
7244let opNewValue = 0;
7245}
7246def J4_cmpgti_t_jumpnv_t : HInst<
7247(outs),
7248(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7249"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7250tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7251let Inst{0-0} = 0b0;
7252let Inst{13-13} = 0b1;
7253let Inst{19-19} = 0b0;
7254let Inst{31-22} = 0b0010010010;
7255let isPredicated = 1;
7256let isTerminator = 1;
7257let isBranch = 1;
7258let isNewValue = 1;
7259let cofMax1 = 1;
7260let isRestrictNoSlot1Store = 1;
7261let Defs = [PC];
7262let BaseOpcode = "J4_cmpgtir";
7263let isTaken = Inst{13};
7264let isExtendable = 1;
7265let opExtendable = 2;
7266let isExtentSigned = 1;
7267let opExtentBits = 11;
7268let opExtentAlign = 2;
7269let opNewValue = 0;
7270}
7271def J4_cmpgti_tp0_jump_nt : HInst<
7272(outs),
7273(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7274"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
7275tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7276let Inst{0-0} = 0b0;
7277let Inst{13-13} = 0b0;
7278let Inst{31-22} = 0b0001000010;
7279let isPredicated = 1;
7280let isTerminator = 1;
7281let isBranch = 1;
7282let isPredicatedNew = 1;
7283let cofRelax1 = 1;
7284let cofRelax2 = 1;
7285let cofMax1 = 1;
7286let Uses = [P0];
7287let Defs = [P0, PC];
7288let BaseOpcode = "J4_cmpgtip0";
7289let isTaken = Inst{13};
7290let isExtendable = 1;
7291let opExtendable = 2;
7292let isExtentSigned = 1;
7293let opExtentBits = 11;
7294let opExtentAlign = 2;
7295}
7296def J4_cmpgti_tp0_jump_t : HInst<
7297(outs),
7298(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7299"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
7300tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7301let Inst{0-0} = 0b0;
7302let Inst{13-13} = 0b1;
7303let Inst{31-22} = 0b0001000010;
7304let isPredicated = 1;
7305let isTerminator = 1;
7306let isBranch = 1;
7307let isPredicatedNew = 1;
7308let cofRelax1 = 1;
7309let cofRelax2 = 1;
7310let cofMax1 = 1;
7311let Uses = [P0];
7312let Defs = [P0, PC];
7313let BaseOpcode = "J4_cmpgtip0";
7314let isTaken = Inst{13};
7315let isExtendable = 1;
7316let opExtendable = 2;
7317let isExtentSigned = 1;
7318let opExtentBits = 11;
7319let opExtentAlign = 2;
7320}
7321def J4_cmpgti_tp1_jump_nt : HInst<
7322(outs),
7323(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7324"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
7325tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7326let Inst{0-0} = 0b0;
7327let Inst{13-13} = 0b0;
7328let Inst{31-22} = 0b0001001010;
7329let isPredicated = 1;
7330let isTerminator = 1;
7331let isBranch = 1;
7332let isPredicatedNew = 1;
7333let cofRelax1 = 1;
7334let cofRelax2 = 1;
7335let cofMax1 = 1;
7336let Uses = [P1];
7337let Defs = [P1, PC];
7338let BaseOpcode = "J4_cmpgtip1";
7339let isTaken = Inst{13};
7340let isExtendable = 1;
7341let opExtendable = 2;
7342let isExtentSigned = 1;
7343let opExtentBits = 11;
7344let opExtentAlign = 2;
7345}
7346def J4_cmpgti_tp1_jump_t : HInst<
7347(outs),
7348(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7349"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
7350tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7351let Inst{0-0} = 0b0;
7352let Inst{13-13} = 0b1;
7353let Inst{31-22} = 0b0001001010;
7354let isPredicated = 1;
7355let isTerminator = 1;
7356let isBranch = 1;
7357let isPredicatedNew = 1;
7358let cofRelax1 = 1;
7359let cofRelax2 = 1;
7360let cofMax1 = 1;
7361let Uses = [P1];
7362let Defs = [P1, PC];
7363let BaseOpcode = "J4_cmpgtip1";
7364let isTaken = Inst{13};
7365let isExtendable = 1;
7366let opExtendable = 2;
7367let isExtentSigned = 1;
7368let opExtentBits = 11;
7369let opExtentAlign = 2;
7370}
7371def J4_cmpgtn1_f_jumpnv_nt : HInst<
7372(outs),
7373(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7374"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7375tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel {
7376let Inst{0-0} = 0b0;
7377let Inst{13-8} = 0b000000;
7378let Inst{19-19} = 0b0;
7379let Inst{31-22} = 0b0010011011;
7380let isPredicated = 1;
7381let isPredicatedFalse = 1;
7382let isTerminator = 1;
7383let isBranch = 1;
7384let isNewValue = 1;
7385let cofMax1 = 1;
7386let isRestrictNoSlot1Store = 1;
7387let Defs = [PC];
7388let BaseOpcode = "J4_cmpgtn1r";
7389let isTaken = Inst{13};
7390let isExtendable = 1;
7391let opExtendable = 2;
7392let isExtentSigned = 1;
7393let opExtentBits = 11;
7394let opExtentAlign = 2;
7395let opNewValue = 0;
7396}
7397def J4_cmpgtn1_f_jumpnv_t : HInst<
7398(outs),
7399(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7400"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7401tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel {
7402let Inst{0-0} = 0b0;
7403let Inst{13-8} = 0b100000;
7404let Inst{19-19} = 0b0;
7405let Inst{31-22} = 0b0010011011;
7406let isPredicated = 1;
7407let isPredicatedFalse = 1;
7408let isTerminator = 1;
7409let isBranch = 1;
7410let isNewValue = 1;
7411let cofMax1 = 1;
7412let isRestrictNoSlot1Store = 1;
7413let Defs = [PC];
7414let BaseOpcode = "J4_cmpgtn1r";
7415let isTaken = Inst{13};
7416let isExtendable = 1;
7417let opExtendable = 2;
7418let isExtentSigned = 1;
7419let opExtentBits = 11;
7420let opExtentAlign = 2;
7421let opNewValue = 0;
7422}
7423def J4_cmpgtn1_fp0_jump_nt : HInst<
7424(outs),
7425(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7426"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
7427tc_24f426ab, TypeCJ>, Enc_a42857, PredRel {
7428let Inst{0-0} = 0b0;
7429let Inst{13-8} = 0b000001;
7430let Inst{31-22} = 0b0001000111;
7431let isPredicated = 1;
7432let isPredicatedFalse = 1;
7433let isTerminator = 1;
7434let isBranch = 1;
7435let isPredicatedNew = 1;
7436let cofRelax1 = 1;
7437let cofRelax2 = 1;
7438let cofMax1 = 1;
7439let Uses = [P0];
7440let Defs = [P0, PC];
7441let BaseOpcode = "J4_cmpgtn1p0";
7442let isTaken = Inst{13};
7443let isExtendable = 1;
7444let opExtendable = 2;
7445let isExtentSigned = 1;
7446let opExtentBits = 11;
7447let opExtentAlign = 2;
7448}
7449def J4_cmpgtn1_fp0_jump_t : HInst<
7450(outs),
7451(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7452"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
7453tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel {
7454let Inst{0-0} = 0b0;
7455let Inst{13-8} = 0b100001;
7456let Inst{31-22} = 0b0001000111;
7457let isPredicated = 1;
7458let isPredicatedFalse = 1;
7459let isTerminator = 1;
7460let isBranch = 1;
7461let isPredicatedNew = 1;
7462let cofRelax1 = 1;
7463let cofRelax2 = 1;
7464let cofMax1 = 1;
7465let Uses = [P0];
7466let Defs = [P0, PC];
7467let BaseOpcode = "J4_cmpgtn1p0";
7468let isTaken = Inst{13};
7469let isExtendable = 1;
7470let opExtendable = 2;
7471let isExtentSigned = 1;
7472let opExtentBits = 11;
7473let opExtentAlign = 2;
7474}
7475def J4_cmpgtn1_fp1_jump_nt : HInst<
7476(outs),
7477(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7478"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
7479tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel {
7480let Inst{0-0} = 0b0;
7481let Inst{13-8} = 0b000001;
7482let Inst{31-22} = 0b0001001111;
7483let isPredicated = 1;
7484let isPredicatedFalse = 1;
7485let isTerminator = 1;
7486let isBranch = 1;
7487let isPredicatedNew = 1;
7488let cofRelax1 = 1;
7489let cofRelax2 = 1;
7490let cofMax1 = 1;
7491let Uses = [P1];
7492let Defs = [P1, PC];
7493let BaseOpcode = "J4_cmpgtn1p1";
7494let isTaken = Inst{13};
7495let isExtendable = 1;
7496let opExtendable = 2;
7497let isExtentSigned = 1;
7498let opExtentBits = 11;
7499let opExtentAlign = 2;
7500}
7501def J4_cmpgtn1_fp1_jump_t : HInst<
7502(outs),
7503(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7504"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
7505tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel {
7506let Inst{0-0} = 0b0;
7507let Inst{13-8} = 0b100001;
7508let Inst{31-22} = 0b0001001111;
7509let isPredicated = 1;
7510let isPredicatedFalse = 1;
7511let isTerminator = 1;
7512let isBranch = 1;
7513let isPredicatedNew = 1;
7514let cofRelax1 = 1;
7515let cofRelax2 = 1;
7516let cofMax1 = 1;
7517let Uses = [P1];
7518let Defs = [P1, PC];
7519let BaseOpcode = "J4_cmpgtn1p1";
7520let isTaken = Inst{13};
7521let isExtendable = 1;
7522let opExtendable = 2;
7523let isExtentSigned = 1;
7524let opExtentBits = 11;
7525let opExtentAlign = 2;
7526}
7527def J4_cmpgtn1_t_jumpnv_nt : HInst<
7528(outs),
7529(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7530"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7531tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel {
7532let Inst{0-0} = 0b0;
7533let Inst{13-8} = 0b000000;
7534let Inst{19-19} = 0b0;
7535let Inst{31-22} = 0b0010011010;
7536let isPredicated = 1;
7537let isTerminator = 1;
7538let isBranch = 1;
7539let isNewValue = 1;
7540let cofMax1 = 1;
7541let isRestrictNoSlot1Store = 1;
7542let Defs = [PC];
7543let BaseOpcode = "J4_cmpgtn1r";
7544let isTaken = Inst{13};
7545let isExtendable = 1;
7546let opExtendable = 2;
7547let isExtentSigned = 1;
7548let opExtentBits = 11;
7549let opExtentAlign = 2;
7550let opNewValue = 0;
7551}
7552def J4_cmpgtn1_t_jumpnv_t : HInst<
7553(outs),
7554(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7555"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7556tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel {
7557let Inst{0-0} = 0b0;
7558let Inst{13-8} = 0b100000;
7559let Inst{19-19} = 0b0;
7560let Inst{31-22} = 0b0010011010;
7561let isPredicated = 1;
7562let isTerminator = 1;
7563let isBranch = 1;
7564let isNewValue = 1;
7565let cofMax1 = 1;
7566let isRestrictNoSlot1Store = 1;
7567let Defs = [PC];
7568let BaseOpcode = "J4_cmpgtn1r";
7569let isTaken = Inst{13};
7570let isExtendable = 1;
7571let opExtendable = 2;
7572let isExtentSigned = 1;
7573let opExtentBits = 11;
7574let opExtentAlign = 2;
7575let opNewValue = 0;
7576}
7577def J4_cmpgtn1_tp0_jump_nt : HInst<
7578(outs),
7579(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7580"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
7581tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel {
7582let Inst{0-0} = 0b0;
7583let Inst{13-8} = 0b000001;
7584let Inst{31-22} = 0b0001000110;
7585let isPredicated = 1;
7586let isTerminator = 1;
7587let isBranch = 1;
7588let isPredicatedNew = 1;
7589let cofRelax1 = 1;
7590let cofRelax2 = 1;
7591let cofMax1 = 1;
7592let Uses = [P0];
7593let Defs = [P0, PC];
7594let BaseOpcode = "J4_cmpgtn1p0";
7595let isTaken = Inst{13};
7596let isExtendable = 1;
7597let opExtendable = 2;
7598let isExtentSigned = 1;
7599let opExtentBits = 11;
7600let opExtentAlign = 2;
7601}
7602def J4_cmpgtn1_tp0_jump_t : HInst<
7603(outs),
7604(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7605"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
7606tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel {
7607let Inst{0-0} = 0b0;
7608let Inst{13-8} = 0b100001;
7609let Inst{31-22} = 0b0001000110;
7610let isPredicated = 1;
7611let isTerminator = 1;
7612let isBranch = 1;
7613let isPredicatedNew = 1;
7614let cofRelax1 = 1;
7615let cofRelax2 = 1;
7616let cofMax1 = 1;
7617let Uses = [P0];
7618let Defs = [P0, PC];
7619let BaseOpcode = "J4_cmpgtn1p0";
7620let isTaken = Inst{13};
7621let isExtendable = 1;
7622let opExtendable = 2;
7623let isExtentSigned = 1;
7624let opExtentBits = 11;
7625let opExtentAlign = 2;
7626}
7627def J4_cmpgtn1_tp1_jump_nt : HInst<
7628(outs),
7629(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7630"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
7631tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel {
7632let Inst{0-0} = 0b0;
7633let Inst{13-8} = 0b000001;
7634let Inst{31-22} = 0b0001001110;
7635let isPredicated = 1;
7636let isTerminator = 1;
7637let isBranch = 1;
7638let isPredicatedNew = 1;
7639let cofRelax1 = 1;
7640let cofRelax2 = 1;
7641let cofMax1 = 1;
7642let Uses = [P1];
7643let Defs = [P1, PC];
7644let BaseOpcode = "J4_cmpgtn1p1";
7645let isTaken = Inst{13};
7646let isExtendable = 1;
7647let opExtendable = 2;
7648let isExtentSigned = 1;
7649let opExtentBits = 11;
7650let opExtentAlign = 2;
7651}
7652def J4_cmpgtn1_tp1_jump_t : HInst<
7653(outs),
7654(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7655"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
7656tc_24f426ab, TypeCJ>, Enc_178717, PredRel {
7657let Inst{0-0} = 0b0;
7658let Inst{13-8} = 0b100001;
7659let Inst{31-22} = 0b0001001110;
7660let isPredicated = 1;
7661let isTerminator = 1;
7662let isBranch = 1;
7663let isPredicatedNew = 1;
7664let cofRelax1 = 1;
7665let cofRelax2 = 1;
7666let cofMax1 = 1;
7667let Uses = [P1];
7668let Defs = [P1, PC];
7669let BaseOpcode = "J4_cmpgtn1p1";
7670let isTaken = Inst{13};
7671let isExtendable = 1;
7672let opExtendable = 2;
7673let isExtentSigned = 1;
7674let opExtentBits = 11;
7675let opExtentAlign = 2;
7676}
7677def J4_cmpgtu_f_jumpnv_nt : HInst<
7678(outs),
7679(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7680"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7681tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7682let Inst{0-0} = 0b0;
7683let Inst{13-13} = 0b0;
7684let Inst{19-19} = 0b0;
7685let Inst{31-22} = 0b0010000101;
7686let isPredicated = 1;
7687let isPredicatedFalse = 1;
7688let isTerminator = 1;
7689let isBranch = 1;
7690let isNewValue = 1;
7691let cofMax1 = 1;
7692let isRestrictNoSlot1Store = 1;
7693let Defs = [PC];
7694let BaseOpcode = "J4_cmpgtur";
7695let isTaken = Inst{13};
7696let isExtendable = 1;
7697let opExtendable = 2;
7698let isExtentSigned = 1;
7699let opExtentBits = 11;
7700let opExtentAlign = 2;
7701let opNewValue = 0;
7702}
7703def J4_cmpgtu_f_jumpnv_t : HInst<
7704(outs),
7705(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7706"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7707tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7708let Inst{0-0} = 0b0;
7709let Inst{13-13} = 0b1;
7710let Inst{19-19} = 0b0;
7711let Inst{31-22} = 0b0010000101;
7712let isPredicated = 1;
7713let isPredicatedFalse = 1;
7714let isTerminator = 1;
7715let isBranch = 1;
7716let isNewValue = 1;
7717let cofMax1 = 1;
7718let isRestrictNoSlot1Store = 1;
7719let Defs = [PC];
7720let BaseOpcode = "J4_cmpgtur";
7721let isTaken = Inst{13};
7722let isExtendable = 1;
7723let opExtendable = 2;
7724let isExtentSigned = 1;
7725let opExtentBits = 11;
7726let opExtentAlign = 2;
7727let opNewValue = 0;
7728}
7729def J4_cmpgtu_fp0_jump_nt : HInst<
7730(outs),
7731(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7732"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
7733tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7734let Inst{0-0} = 0b0;
7735let Inst{13-12} = 0b00;
7736let Inst{31-22} = 0b0001010101;
7737let isPredicated = 1;
7738let isPredicatedFalse = 1;
7739let isTerminator = 1;
7740let isBranch = 1;
7741let isPredicatedNew = 1;
7742let cofRelax1 = 1;
7743let cofRelax2 = 1;
7744let cofMax1 = 1;
7745let Uses = [P0];
7746let Defs = [P0, PC];
7747let BaseOpcode = "J4_cmpgtup0";
7748let isTaken = Inst{13};
7749let isExtendable = 1;
7750let opExtendable = 2;
7751let isExtentSigned = 1;
7752let opExtentBits = 11;
7753let opExtentAlign = 2;
7754}
7755def J4_cmpgtu_fp0_jump_t : HInst<
7756(outs),
7757(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7758"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
7759tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7760let Inst{0-0} = 0b0;
7761let Inst{13-12} = 0b10;
7762let Inst{31-22} = 0b0001010101;
7763let isPredicated = 1;
7764let isPredicatedFalse = 1;
7765let isTerminator = 1;
7766let isBranch = 1;
7767let isPredicatedNew = 1;
7768let cofRelax1 = 1;
7769let cofRelax2 = 1;
7770let cofMax1 = 1;
7771let Uses = [P0];
7772let Defs = [P0, PC];
7773let BaseOpcode = "J4_cmpgtup0";
7774let isTaken = Inst{13};
7775let isExtendable = 1;
7776let opExtendable = 2;
7777let isExtentSigned = 1;
7778let opExtentBits = 11;
7779let opExtentAlign = 2;
7780}
7781def J4_cmpgtu_fp1_jump_nt : HInst<
7782(outs),
7783(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7784"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
7785tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7786let Inst{0-0} = 0b0;
7787let Inst{13-12} = 0b01;
7788let Inst{31-22} = 0b0001010101;
7789let isPredicated = 1;
7790let isPredicatedFalse = 1;
7791let isTerminator = 1;
7792let isBranch = 1;
7793let isPredicatedNew = 1;
7794let cofRelax1 = 1;
7795let cofRelax2 = 1;
7796let cofMax1 = 1;
7797let Uses = [P1];
7798let Defs = [P1, PC];
7799let BaseOpcode = "J4_cmpgtup1";
7800let isTaken = Inst{13};
7801let isExtendable = 1;
7802let opExtendable = 2;
7803let isExtentSigned = 1;
7804let opExtentBits = 11;
7805let opExtentAlign = 2;
7806}
7807def J4_cmpgtu_fp1_jump_t : HInst<
7808(outs),
7809(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7810"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
7811tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7812let Inst{0-0} = 0b0;
7813let Inst{13-12} = 0b11;
7814let Inst{31-22} = 0b0001010101;
7815let isPredicated = 1;
7816let isPredicatedFalse = 1;
7817let isTerminator = 1;
7818let isBranch = 1;
7819let isPredicatedNew = 1;
7820let cofRelax1 = 1;
7821let cofRelax2 = 1;
7822let cofMax1 = 1;
7823let Uses = [P1];
7824let Defs = [P1, PC];
7825let BaseOpcode = "J4_cmpgtup1";
7826let isTaken = Inst{13};
7827let isExtendable = 1;
7828let opExtendable = 2;
7829let isExtentSigned = 1;
7830let opExtentBits = 11;
7831let opExtentAlign = 2;
7832}
7833def J4_cmpgtu_t_jumpnv_nt : HInst<
7834(outs),
7835(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7836"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7837tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7838let Inst{0-0} = 0b0;
7839let Inst{13-13} = 0b0;
7840let Inst{19-19} = 0b0;
7841let Inst{31-22} = 0b0010000100;
7842let isPredicated = 1;
7843let isTerminator = 1;
7844let isBranch = 1;
7845let isNewValue = 1;
7846let cofMax1 = 1;
7847let isRestrictNoSlot1Store = 1;
7848let Defs = [PC];
7849let BaseOpcode = "J4_cmpgtur";
7850let isTaken = Inst{13};
7851let isExtendable = 1;
7852let opExtendable = 2;
7853let isExtentSigned = 1;
7854let opExtentBits = 11;
7855let opExtentAlign = 2;
7856let opNewValue = 0;
7857}
7858def J4_cmpgtu_t_jumpnv_t : HInst<
7859(outs),
7860(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7861"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7862tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7863let Inst{0-0} = 0b0;
7864let Inst{13-13} = 0b1;
7865let Inst{19-19} = 0b0;
7866let Inst{31-22} = 0b0010000100;
7867let isPredicated = 1;
7868let isTerminator = 1;
7869let isBranch = 1;
7870let isNewValue = 1;
7871let cofMax1 = 1;
7872let isRestrictNoSlot1Store = 1;
7873let Defs = [PC];
7874let BaseOpcode = "J4_cmpgtur";
7875let isTaken = Inst{13};
7876let isExtendable = 1;
7877let opExtendable = 2;
7878let isExtentSigned = 1;
7879let opExtentBits = 11;
7880let opExtentAlign = 2;
7881let opNewValue = 0;
7882}
7883def J4_cmpgtu_tp0_jump_nt : HInst<
7884(outs),
7885(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7886"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7887tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7888let Inst{0-0} = 0b0;
7889let Inst{13-12} = 0b00;
7890let Inst{31-22} = 0b0001010100;
7891let isPredicated = 1;
7892let isTerminator = 1;
7893let isBranch = 1;
7894let isPredicatedNew = 1;
7895let cofRelax1 = 1;
7896let cofRelax2 = 1;
7897let cofMax1 = 1;
7898let Uses = [P0];
7899let Defs = [P0, PC];
7900let BaseOpcode = "J4_cmpgtup0";
7901let isTaken = Inst{13};
7902let isExtendable = 1;
7903let opExtendable = 2;
7904let isExtentSigned = 1;
7905let opExtentBits = 11;
7906let opExtentAlign = 2;
7907}
7908def J4_cmpgtu_tp0_jump_t : HInst<
7909(outs),
7910(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7911"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7912tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7913let Inst{0-0} = 0b0;
7914let Inst{13-12} = 0b10;
7915let Inst{31-22} = 0b0001010100;
7916let isPredicated = 1;
7917let isTerminator = 1;
7918let isBranch = 1;
7919let isPredicatedNew = 1;
7920let cofRelax1 = 1;
7921let cofRelax2 = 1;
7922let cofMax1 = 1;
7923let Uses = [P0];
7924let Defs = [P0, PC];
7925let BaseOpcode = "J4_cmpgtup0";
7926let isTaken = Inst{13};
7927let isExtendable = 1;
7928let opExtendable = 2;
7929let isExtentSigned = 1;
7930let opExtentBits = 11;
7931let opExtentAlign = 2;
7932}
7933def J4_cmpgtu_tp1_jump_nt : HInst<
7934(outs),
7935(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7936"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7937tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7938let Inst{0-0} = 0b0;
7939let Inst{13-12} = 0b01;
7940let Inst{31-22} = 0b0001010100;
7941let isPredicated = 1;
7942let isTerminator = 1;
7943let isBranch = 1;
7944let isPredicatedNew = 1;
7945let cofRelax1 = 1;
7946let cofRelax2 = 1;
7947let cofMax1 = 1;
7948let Uses = [P1];
7949let Defs = [P1, PC];
7950let BaseOpcode = "J4_cmpgtup1";
7951let isTaken = Inst{13};
7952let isExtendable = 1;
7953let opExtendable = 2;
7954let isExtentSigned = 1;
7955let opExtentBits = 11;
7956let opExtentAlign = 2;
7957}
7958def J4_cmpgtu_tp1_jump_t : HInst<
7959(outs),
7960(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7961"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7962tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7963let Inst{0-0} = 0b0;
7964let Inst{13-12} = 0b11;
7965let Inst{31-22} = 0b0001010100;
7966let isPredicated = 1;
7967let isTerminator = 1;
7968let isBranch = 1;
7969let isPredicatedNew = 1;
7970let cofRelax1 = 1;
7971let cofRelax2 = 1;
7972let cofMax1 = 1;
7973let Uses = [P1];
7974let Defs = [P1, PC];
7975let BaseOpcode = "J4_cmpgtup1";
7976let isTaken = Inst{13};
7977let isExtendable = 1;
7978let opExtendable = 2;
7979let isExtentSigned = 1;
7980let opExtentBits = 11;
7981let opExtentAlign = 2;
7982}
7983def J4_cmpgtui_f_jumpnv_nt : HInst<
7984(outs),
7985(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7986"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
7987tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7988let Inst{0-0} = 0b0;
7989let Inst{13-13} = 0b0;
7990let Inst{19-19} = 0b0;
7991let Inst{31-22} = 0b0010010101;
7992let isPredicated = 1;
7993let isPredicatedFalse = 1;
7994let isTerminator = 1;
7995let isBranch = 1;
7996let isNewValue = 1;
7997let cofMax1 = 1;
7998let isRestrictNoSlot1Store = 1;
7999let Defs = [PC];
8000let BaseOpcode = "J4_cmpgtuir";
8001let isTaken = Inst{13};
8002let isExtendable = 1;
8003let opExtendable = 2;
8004let isExtentSigned = 1;
8005let opExtentBits = 11;
8006let opExtentAlign = 2;
8007let opNewValue = 0;
8008}
8009def J4_cmpgtui_f_jumpnv_t : HInst<
8010(outs),
8011(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8012"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8013tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8014let Inst{0-0} = 0b0;
8015let Inst{13-13} = 0b1;
8016let Inst{19-19} = 0b0;
8017let Inst{31-22} = 0b0010010101;
8018let isPredicated = 1;
8019let isPredicatedFalse = 1;
8020let isTerminator = 1;
8021let isBranch = 1;
8022let isNewValue = 1;
8023let cofMax1 = 1;
8024let isRestrictNoSlot1Store = 1;
8025let Defs = [PC];
8026let BaseOpcode = "J4_cmpgtuir";
8027let isTaken = Inst{13};
8028let isExtendable = 1;
8029let opExtendable = 2;
8030let isExtentSigned = 1;
8031let opExtentBits = 11;
8032let opExtentAlign = 2;
8033let opNewValue = 0;
8034}
8035def J4_cmpgtui_fp0_jump_nt : HInst<
8036(outs),
8037(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8038"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
8039tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8040let Inst{0-0} = 0b0;
8041let Inst{13-13} = 0b0;
8042let Inst{31-22} = 0b0001000101;
8043let isPredicated = 1;
8044let isPredicatedFalse = 1;
8045let isTerminator = 1;
8046let isBranch = 1;
8047let isPredicatedNew = 1;
8048let cofRelax1 = 1;
8049let cofRelax2 = 1;
8050let cofMax1 = 1;
8051let Uses = [P0];
8052let Defs = [P0, PC];
8053let BaseOpcode = "J4_cmpgtuip0";
8054let isTaken = Inst{13};
8055let isExtendable = 1;
8056let opExtendable = 2;
8057let isExtentSigned = 1;
8058let opExtentBits = 11;
8059let opExtentAlign = 2;
8060}
8061def J4_cmpgtui_fp0_jump_t : HInst<
8062(outs),
8063(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8064"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
8065tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8066let Inst{0-0} = 0b0;
8067let Inst{13-13} = 0b1;
8068let Inst{31-22} = 0b0001000101;
8069let isPredicated = 1;
8070let isPredicatedFalse = 1;
8071let isTerminator = 1;
8072let isBranch = 1;
8073let isPredicatedNew = 1;
8074let cofRelax1 = 1;
8075let cofRelax2 = 1;
8076let cofMax1 = 1;
8077let Uses = [P0];
8078let Defs = [P0, PC];
8079let BaseOpcode = "J4_cmpgtuip0";
8080let isTaken = Inst{13};
8081let isExtendable = 1;
8082let opExtendable = 2;
8083let isExtentSigned = 1;
8084let opExtentBits = 11;
8085let opExtentAlign = 2;
8086}
8087def J4_cmpgtui_fp1_jump_nt : HInst<
8088(outs),
8089(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8090"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
8091tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8092let Inst{0-0} = 0b0;
8093let Inst{13-13} = 0b0;
8094let Inst{31-22} = 0b0001001101;
8095let isPredicated = 1;
8096let isPredicatedFalse = 1;
8097let isTerminator = 1;
8098let isBranch = 1;
8099let isPredicatedNew = 1;
8100let cofRelax1 = 1;
8101let cofRelax2 = 1;
8102let cofMax1 = 1;
8103let Uses = [P1];
8104let Defs = [P1, PC];
8105let BaseOpcode = "J4_cmpgtuip1";
8106let isTaken = Inst{13};
8107let isExtendable = 1;
8108let opExtendable = 2;
8109let isExtentSigned = 1;
8110let opExtentBits = 11;
8111let opExtentAlign = 2;
8112}
8113def J4_cmpgtui_fp1_jump_t : HInst<
8114(outs),
8115(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8116"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
8117tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8118let Inst{0-0} = 0b0;
8119let Inst{13-13} = 0b1;
8120let Inst{31-22} = 0b0001001101;
8121let isPredicated = 1;
8122let isPredicatedFalse = 1;
8123let isTerminator = 1;
8124let isBranch = 1;
8125let isPredicatedNew = 1;
8126let cofRelax1 = 1;
8127let cofRelax2 = 1;
8128let cofMax1 = 1;
8129let Uses = [P1];
8130let Defs = [P1, PC];
8131let BaseOpcode = "J4_cmpgtuip1";
8132let isTaken = Inst{13};
8133let isExtendable = 1;
8134let opExtendable = 2;
8135let isExtentSigned = 1;
8136let opExtentBits = 11;
8137let opExtentAlign = 2;
8138}
8139def J4_cmpgtui_t_jumpnv_nt : HInst<
8140(outs),
8141(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8142"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8143tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8144let Inst{0-0} = 0b0;
8145let Inst{13-13} = 0b0;
8146let Inst{19-19} = 0b0;
8147let Inst{31-22} = 0b0010010100;
8148let isPredicated = 1;
8149let isTerminator = 1;
8150let isBranch = 1;
8151let isNewValue = 1;
8152let cofMax1 = 1;
8153let isRestrictNoSlot1Store = 1;
8154let Defs = [PC];
8155let BaseOpcode = "J4_cmpgtuir";
8156let isTaken = Inst{13};
8157let isExtendable = 1;
8158let opExtendable = 2;
8159let isExtentSigned = 1;
8160let opExtentBits = 11;
8161let opExtentAlign = 2;
8162let opNewValue = 0;
8163}
8164def J4_cmpgtui_t_jumpnv_t : HInst<
8165(outs),
8166(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8167"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8168tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8169let Inst{0-0} = 0b0;
8170let Inst{13-13} = 0b1;
8171let Inst{19-19} = 0b0;
8172let Inst{31-22} = 0b0010010100;
8173let isPredicated = 1;
8174let isTerminator = 1;
8175let isBranch = 1;
8176let isNewValue = 1;
8177let cofMax1 = 1;
8178let isRestrictNoSlot1Store = 1;
8179let Defs = [PC];
8180let BaseOpcode = "J4_cmpgtuir";
8181let isTaken = Inst{13};
8182let isExtendable = 1;
8183let opExtendable = 2;
8184let isExtentSigned = 1;
8185let opExtentBits = 11;
8186let opExtentAlign = 2;
8187let opNewValue = 0;
8188}
8189def J4_cmpgtui_tp0_jump_nt : HInst<
8190(outs),
8191(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8192"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
8193tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8194let Inst{0-0} = 0b0;
8195let Inst{13-13} = 0b0;
8196let Inst{31-22} = 0b0001000100;
8197let isPredicated = 1;
8198let isTerminator = 1;
8199let isBranch = 1;
8200let isPredicatedNew = 1;
8201let cofRelax1 = 1;
8202let cofRelax2 = 1;
8203let cofMax1 = 1;
8204let Uses = [P0];
8205let Defs = [P0, PC];
8206let BaseOpcode = "J4_cmpgtuip0";
8207let isTaken = Inst{13};
8208let isExtendable = 1;
8209let opExtendable = 2;
8210let isExtentSigned = 1;
8211let opExtentBits = 11;
8212let opExtentAlign = 2;
8213}
8214def J4_cmpgtui_tp0_jump_t : HInst<
8215(outs),
8216(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8217"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
8218tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8219let Inst{0-0} = 0b0;
8220let Inst{13-13} = 0b1;
8221let Inst{31-22} = 0b0001000100;
8222let isPredicated = 1;
8223let isTerminator = 1;
8224let isBranch = 1;
8225let isPredicatedNew = 1;
8226let cofRelax1 = 1;
8227let cofRelax2 = 1;
8228let cofMax1 = 1;
8229let Uses = [P0];
8230let Defs = [P0, PC];
8231let BaseOpcode = "J4_cmpgtuip0";
8232let isTaken = Inst{13};
8233let isExtendable = 1;
8234let opExtendable = 2;
8235let isExtentSigned = 1;
8236let opExtentBits = 11;
8237let opExtentAlign = 2;
8238}
8239def J4_cmpgtui_tp1_jump_nt : HInst<
8240(outs),
8241(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8242"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
8243tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8244let Inst{0-0} = 0b0;
8245let Inst{13-13} = 0b0;
8246let Inst{31-22} = 0b0001001100;
8247let isPredicated = 1;
8248let isTerminator = 1;
8249let isBranch = 1;
8250let isPredicatedNew = 1;
8251let cofRelax1 = 1;
8252let cofRelax2 = 1;
8253let cofMax1 = 1;
8254let Uses = [P1];
8255let Defs = [P1, PC];
8256let BaseOpcode = "J4_cmpgtuip1";
8257let isTaken = Inst{13};
8258let isExtendable = 1;
8259let opExtendable = 2;
8260let isExtentSigned = 1;
8261let opExtentBits = 11;
8262let opExtentAlign = 2;
8263}
8264def J4_cmpgtui_tp1_jump_t : HInst<
8265(outs),
8266(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8267"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
8268tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8269let Inst{0-0} = 0b0;
8270let Inst{13-13} = 0b1;
8271let Inst{31-22} = 0b0001001100;
8272let isPredicated = 1;
8273let isTerminator = 1;
8274let isBranch = 1;
8275let isPredicatedNew = 1;
8276let cofRelax1 = 1;
8277let cofRelax2 = 1;
8278let cofMax1 = 1;
8279let Uses = [P1];
8280let Defs = [P1, PC];
8281let BaseOpcode = "J4_cmpgtuip1";
8282let isTaken = Inst{13};
8283let isExtendable = 1;
8284let opExtendable = 2;
8285let isExtentSigned = 1;
8286let opExtentBits = 11;
8287let opExtentAlign = 2;
8288}
8289def J4_cmplt_f_jumpnv_nt : HInst<
8290(outs),
8291(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8292"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8293tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8294let Inst{0-0} = 0b0;
8295let Inst{13-13} = 0b0;
8296let Inst{19-19} = 0b0;
8297let Inst{31-22} = 0b0010000111;
8298let isPredicated = 1;
8299let isPredicatedFalse = 1;
8300let isTerminator = 1;
8301let isBranch = 1;
8302let isNewValue = 1;
8303let cofMax1 = 1;
8304let isRestrictNoSlot1Store = 1;
8305let Defs = [PC];
8306let BaseOpcode = "J4_cmpltr";
8307let isTaken = Inst{13};
8308let isExtendable = 1;
8309let opExtendable = 2;
8310let isExtentSigned = 1;
8311let opExtentBits = 11;
8312let opExtentAlign = 2;
8313let opNewValue = 1;
8314}
8315def J4_cmplt_f_jumpnv_t : HInst<
8316(outs),
8317(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8318"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8319tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8320let Inst{0-0} = 0b0;
8321let Inst{13-13} = 0b1;
8322let Inst{19-19} = 0b0;
8323let Inst{31-22} = 0b0010000111;
8324let isPredicated = 1;
8325let isPredicatedFalse = 1;
8326let isTerminator = 1;
8327let isBranch = 1;
8328let isNewValue = 1;
8329let cofMax1 = 1;
8330let isRestrictNoSlot1Store = 1;
8331let Defs = [PC];
8332let BaseOpcode = "J4_cmpltr";
8333let isTaken = Inst{13};
8334let isExtendable = 1;
8335let opExtendable = 2;
8336let isExtentSigned = 1;
8337let opExtentBits = 11;
8338let opExtentAlign = 2;
8339let opNewValue = 1;
8340}
8341def J4_cmplt_t_jumpnv_nt : HInst<
8342(outs),
8343(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8344"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8345tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8346let Inst{0-0} = 0b0;
8347let Inst{13-13} = 0b0;
8348let Inst{19-19} = 0b0;
8349let Inst{31-22} = 0b0010000110;
8350let isPredicated = 1;
8351let isTerminator = 1;
8352let isBranch = 1;
8353let isNewValue = 1;
8354let cofMax1 = 1;
8355let isRestrictNoSlot1Store = 1;
8356let Defs = [PC];
8357let BaseOpcode = "J4_cmpltr";
8358let isTaken = Inst{13};
8359let isExtendable = 1;
8360let opExtendable = 2;
8361let isExtentSigned = 1;
8362let opExtentBits = 11;
8363let opExtentAlign = 2;
8364let opNewValue = 1;
8365}
8366def J4_cmplt_t_jumpnv_t : HInst<
8367(outs),
8368(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8369"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8370tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8371let Inst{0-0} = 0b0;
8372let Inst{13-13} = 0b1;
8373let Inst{19-19} = 0b0;
8374let Inst{31-22} = 0b0010000110;
8375let isPredicated = 1;
8376let isTerminator = 1;
8377let isBranch = 1;
8378let isNewValue = 1;
8379let cofMax1 = 1;
8380let isRestrictNoSlot1Store = 1;
8381let Defs = [PC];
8382let BaseOpcode = "J4_cmpltr";
8383let isTaken = Inst{13};
8384let isExtendable = 1;
8385let opExtendable = 2;
8386let isExtentSigned = 1;
8387let opExtentBits = 11;
8388let opExtentAlign = 2;
8389let opNewValue = 1;
8390}
8391def J4_cmpltu_f_jumpnv_nt : HInst<
8392(outs),
8393(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8394"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8395tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8396let Inst{0-0} = 0b0;
8397let Inst{13-13} = 0b0;
8398let Inst{19-19} = 0b0;
8399let Inst{31-22} = 0b0010001001;
8400let isPredicated = 1;
8401let isPredicatedFalse = 1;
8402let isTerminator = 1;
8403let isBranch = 1;
8404let isNewValue = 1;
8405let cofMax1 = 1;
8406let isRestrictNoSlot1Store = 1;
8407let Defs = [PC];
8408let BaseOpcode = "J4_cmpltur";
8409let isTaken = Inst{13};
8410let isExtendable = 1;
8411let opExtendable = 2;
8412let isExtentSigned = 1;
8413let opExtentBits = 11;
8414let opExtentAlign = 2;
8415let opNewValue = 1;
8416}
8417def J4_cmpltu_f_jumpnv_t : HInst<
8418(outs),
8419(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8420"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8421tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8422let Inst{0-0} = 0b0;
8423let Inst{13-13} = 0b1;
8424let Inst{19-19} = 0b0;
8425let Inst{31-22} = 0b0010001001;
8426let isPredicated = 1;
8427let isPredicatedFalse = 1;
8428let isTerminator = 1;
8429let isBranch = 1;
8430let isNewValue = 1;
8431let cofMax1 = 1;
8432let isRestrictNoSlot1Store = 1;
8433let Defs = [PC];
8434let BaseOpcode = "J4_cmpltur";
8435let isTaken = Inst{13};
8436let isExtendable = 1;
8437let opExtendable = 2;
8438let isExtentSigned = 1;
8439let opExtentBits = 11;
8440let opExtentAlign = 2;
8441let opNewValue = 1;
8442}
8443def J4_cmpltu_t_jumpnv_nt : HInst<
8444(outs),
8445(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8446"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8447tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8448let Inst{0-0} = 0b0;
8449let Inst{13-13} = 0b0;
8450let Inst{19-19} = 0b0;
8451let Inst{31-22} = 0b0010001000;
8452let isPredicated = 1;
8453let isTerminator = 1;
8454let isBranch = 1;
8455let isNewValue = 1;
8456let cofMax1 = 1;
8457let isRestrictNoSlot1Store = 1;
8458let Defs = [PC];
8459let BaseOpcode = "J4_cmpltur";
8460let isTaken = Inst{13};
8461let isExtendable = 1;
8462let opExtendable = 2;
8463let isExtentSigned = 1;
8464let opExtentBits = 11;
8465let opExtentAlign = 2;
8466let opNewValue = 1;
8467}
8468def J4_cmpltu_t_jumpnv_t : HInst<
8469(outs),
8470(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8471"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8472tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8473let Inst{0-0} = 0b0;
8474let Inst{13-13} = 0b1;
8475let Inst{19-19} = 0b0;
8476let Inst{31-22} = 0b0010001000;
8477let isPredicated = 1;
8478let isTerminator = 1;
8479let isBranch = 1;
8480let isNewValue = 1;
8481let cofMax1 = 1;
8482let isRestrictNoSlot1Store = 1;
8483let Defs = [PC];
8484let BaseOpcode = "J4_cmpltur";
8485let isTaken = Inst{13};
8486let isExtendable = 1;
8487let opExtendable = 2;
8488let isExtentSigned = 1;
8489let opExtentBits = 11;
8490let opExtentAlign = 2;
8491let opNewValue = 1;
8492}
8493def J4_hintjumpr : HInst<
8494(outs),
8495(ins IntRegs:$Rs32),
8496"hintjr($Rs32)",
8497tc_60e324ff, TypeJ>, Enc_ecbcc8 {
8498let Inst{13-0} = 0b00000000000000;
8499let Inst{31-21} = 0b01010010101;
8500let isTerminator = 1;
8501let isIndirectBranch = 1;
8502let isBranch = 1;
8503let cofRelax1 = 1;
8504let cofRelax2 = 1;
8505let cofMax1 = 1;
8506}
8507def J4_jumpseti : HInst<
8508(outs GeneralSubRegs:$Rd16),
8509(ins u6_0Imm:$II, b30_2Imm:$Ii),
8510"$Rd16 = #$II ; jump $Ii",
8511tc_5502c366, TypeCJ>, Enc_9e4c3f {
8512let Inst{0-0} = 0b0;
8513let Inst{31-22} = 0b0001011000;
8514let hasNewValue = 1;
8515let opNewValue = 0;
8516let isTerminator = 1;
8517let isBranch = 1;
8518let cofRelax2 = 1;
8519let cofMax1 = 1;
8520let Defs = [PC];
8521let isExtendable = 1;
8522let opExtendable = 2;
8523let isExtentSigned = 1;
8524let opExtentBits = 11;
8525let opExtentAlign = 2;
8526}
8527def J4_jumpsetr : HInst<
8528(outs GeneralSubRegs:$Rd16),
8529(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8530"$Rd16 = $Rs16 ; jump $Ii",
8531tc_5502c366, TypeCJ>, Enc_66bce1 {
8532let Inst{0-0} = 0b0;
8533let Inst{13-12} = 0b00;
8534let Inst{31-22} = 0b0001011100;
8535let hasNewValue = 1;
8536let opNewValue = 0;
8537let isTerminator = 1;
8538let isBranch = 1;
8539let cofRelax2 = 1;
8540let cofMax1 = 1;
8541let Defs = [PC];
8542let isExtendable = 1;
8543let opExtendable = 2;
8544let isExtentSigned = 1;
8545let opExtentBits = 11;
8546let opExtentAlign = 2;
8547}
8548def J4_tstbit0_f_jumpnv_nt : HInst<
8549(outs),
8550(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8551"if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
8552tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8553let Inst{0-0} = 0b0;
8554let Inst{13-8} = 0b000000;
8555let Inst{19-19} = 0b0;
8556let Inst{31-22} = 0b0010010111;
8557let isPredicated = 1;
8558let isPredicatedFalse = 1;
8559let isTerminator = 1;
8560let isBranch = 1;
8561let isNewValue = 1;
8562let cofMax1 = 1;
8563let isRestrictNoSlot1Store = 1;
8564let Defs = [PC];
8565let isTaken = Inst{13};
8566let isExtendable = 1;
8567let opExtendable = 1;
8568let isExtentSigned = 1;
8569let opExtentBits = 11;
8570let opExtentAlign = 2;
8571let opNewValue = 0;
8572}
8573def J4_tstbit0_f_jumpnv_t : HInst<
8574(outs),
8575(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8576"if (!tstbit($Ns8.new,#0)) jump:t $Ii",
8577tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8578let Inst{0-0} = 0b0;
8579let Inst{13-8} = 0b100000;
8580let Inst{19-19} = 0b0;
8581let Inst{31-22} = 0b0010010111;
8582let isPredicated = 1;
8583let isPredicatedFalse = 1;
8584let isTerminator = 1;
8585let isBranch = 1;
8586let isNewValue = 1;
8587let cofMax1 = 1;
8588let isRestrictNoSlot1Store = 1;
8589let Defs = [PC];
8590let isTaken = Inst{13};
8591let isExtendable = 1;
8592let opExtendable = 1;
8593let isExtentSigned = 1;
8594let opExtentBits = 11;
8595let opExtentAlign = 2;
8596let opNewValue = 0;
8597}
8598def J4_tstbit0_fp0_jump_nt : HInst<
8599(outs),
8600(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8601"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
8602tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8603let Inst{0-0} = 0b0;
8604let Inst{13-8} = 0b000011;
8605let Inst{31-22} = 0b0001000111;
8606let isPredicated = 1;
8607let isPredicatedFalse = 1;
8608let isTerminator = 1;
8609let isBranch = 1;
8610let isPredicatedNew = 1;
8611let cofRelax1 = 1;
8612let cofRelax2 = 1;
8613let cofMax1 = 1;
8614let Uses = [P0];
8615let Defs = [P0, PC];
8616let isTaken = Inst{13};
8617let isExtendable = 1;
8618let opExtendable = 1;
8619let isExtentSigned = 1;
8620let opExtentBits = 11;
8621let opExtentAlign = 2;
8622}
8623def J4_tstbit0_fp0_jump_t : HInst<
8624(outs),
8625(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8626"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
8627tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8628let Inst{0-0} = 0b0;
8629let Inst{13-8} = 0b100011;
8630let Inst{31-22} = 0b0001000111;
8631let isPredicated = 1;
8632let isPredicatedFalse = 1;
8633let isTerminator = 1;
8634let isBranch = 1;
8635let isPredicatedNew = 1;
8636let cofRelax1 = 1;
8637let cofRelax2 = 1;
8638let cofMax1 = 1;
8639let Uses = [P0];
8640let Defs = [P0, PC];
8641let isTaken = Inst{13};
8642let isExtendable = 1;
8643let opExtendable = 1;
8644let isExtentSigned = 1;
8645let opExtentBits = 11;
8646let opExtentAlign = 2;
8647}
8648def J4_tstbit0_fp1_jump_nt : HInst<
8649(outs),
8650(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8651"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
8652tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8653let Inst{0-0} = 0b0;
8654let Inst{13-8} = 0b000011;
8655let Inst{31-22} = 0b0001001111;
8656let isPredicated = 1;
8657let isPredicatedFalse = 1;
8658let isTerminator = 1;
8659let isBranch = 1;
8660let isPredicatedNew = 1;
8661let cofRelax1 = 1;
8662let cofRelax2 = 1;
8663let cofMax1 = 1;
8664let Uses = [P1];
8665let Defs = [P1, PC];
8666let isTaken = Inst{13};
8667let isExtendable = 1;
8668let opExtendable = 1;
8669let isExtentSigned = 1;
8670let opExtentBits = 11;
8671let opExtentAlign = 2;
8672}
8673def J4_tstbit0_fp1_jump_t : HInst<
8674(outs),
8675(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8676"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
8677tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8678let Inst{0-0} = 0b0;
8679let Inst{13-8} = 0b100011;
8680let Inst{31-22} = 0b0001001111;
8681let isPredicated = 1;
8682let isPredicatedFalse = 1;
8683let isTerminator = 1;
8684let isBranch = 1;
8685let isPredicatedNew = 1;
8686let cofRelax1 = 1;
8687let cofRelax2 = 1;
8688let cofMax1 = 1;
8689let Uses = [P1];
8690let Defs = [P1, PC];
8691let isTaken = Inst{13};
8692let isExtendable = 1;
8693let opExtendable = 1;
8694let isExtentSigned = 1;
8695let opExtentBits = 11;
8696let opExtentAlign = 2;
8697}
8698def J4_tstbit0_t_jumpnv_nt : HInst<
8699(outs),
8700(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8701"if (tstbit($Ns8.new,#0)) jump:nt $Ii",
8702tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8703let Inst{0-0} = 0b0;
8704let Inst{13-8} = 0b000000;
8705let Inst{19-19} = 0b0;
8706let Inst{31-22} = 0b0010010110;
8707let isPredicated = 1;
8708let isTerminator = 1;
8709let isBranch = 1;
8710let isNewValue = 1;
8711let cofMax1 = 1;
8712let isRestrictNoSlot1Store = 1;
8713let Defs = [PC];
8714let isTaken = Inst{13};
8715let isExtendable = 1;
8716let opExtendable = 1;
8717let isExtentSigned = 1;
8718let opExtentBits = 11;
8719let opExtentAlign = 2;
8720let opNewValue = 0;
8721}
8722def J4_tstbit0_t_jumpnv_t : HInst<
8723(outs),
8724(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8725"if (tstbit($Ns8.new,#0)) jump:t $Ii",
8726tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8727let Inst{0-0} = 0b0;
8728let Inst{13-8} = 0b100000;
8729let Inst{19-19} = 0b0;
8730let Inst{31-22} = 0b0010010110;
8731let isPredicated = 1;
8732let isTerminator = 1;
8733let isBranch = 1;
8734let isNewValue = 1;
8735let cofMax1 = 1;
8736let isRestrictNoSlot1Store = 1;
8737let Defs = [PC];
8738let isTaken = Inst{13};
8739let isExtendable = 1;
8740let opExtendable = 1;
8741let isExtentSigned = 1;
8742let opExtentBits = 11;
8743let opExtentAlign = 2;
8744let opNewValue = 0;
8745}
8746def J4_tstbit0_tp0_jump_nt : HInst<
8747(outs),
8748(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8749"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
8750tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8751let Inst{0-0} = 0b0;
8752let Inst{13-8} = 0b000011;
8753let Inst{31-22} = 0b0001000110;
8754let isPredicated = 1;
8755let isTerminator = 1;
8756let isBranch = 1;
8757let isPredicatedNew = 1;
8758let cofRelax1 = 1;
8759let cofRelax2 = 1;
8760let cofMax1 = 1;
8761let Uses = [P0];
8762let Defs = [P0, PC];
8763let isTaken = Inst{13};
8764let isExtendable = 1;
8765let opExtendable = 1;
8766let isExtentSigned = 1;
8767let opExtentBits = 11;
8768let opExtentAlign = 2;
8769}
8770def J4_tstbit0_tp0_jump_t : HInst<
8771(outs),
8772(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8773"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
8774tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8775let Inst{0-0} = 0b0;
8776let Inst{13-8} = 0b100011;
8777let Inst{31-22} = 0b0001000110;
8778let isPredicated = 1;
8779let isTerminator = 1;
8780let isBranch = 1;
8781let isPredicatedNew = 1;
8782let cofRelax1 = 1;
8783let cofRelax2 = 1;
8784let cofMax1 = 1;
8785let Uses = [P0];
8786let Defs = [P0, PC];
8787let isTaken = Inst{13};
8788let isExtendable = 1;
8789let opExtendable = 1;
8790let isExtentSigned = 1;
8791let opExtentBits = 11;
8792let opExtentAlign = 2;
8793}
8794def J4_tstbit0_tp1_jump_nt : HInst<
8795(outs),
8796(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8797"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
8798tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8799let Inst{0-0} = 0b0;
8800let Inst{13-8} = 0b000011;
8801let Inst{31-22} = 0b0001001110;
8802let isPredicated = 1;
8803let isTerminator = 1;
8804let isBranch = 1;
8805let isPredicatedNew = 1;
8806let cofRelax1 = 1;
8807let cofRelax2 = 1;
8808let cofMax1 = 1;
8809let Uses = [P1];
8810let Defs = [P1, PC];
8811let isTaken = Inst{13};
8812let isExtendable = 1;
8813let opExtendable = 1;
8814let isExtentSigned = 1;
8815let opExtentBits = 11;
8816let opExtentAlign = 2;
8817}
8818def J4_tstbit0_tp1_jump_t : HInst<
8819(outs),
8820(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8821"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
8822tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8823let Inst{0-0} = 0b0;
8824let Inst{13-8} = 0b100011;
8825let Inst{31-22} = 0b0001001110;
8826let isPredicated = 1;
8827let isTerminator = 1;
8828let isBranch = 1;
8829let isPredicatedNew = 1;
8830let cofRelax1 = 1;
8831let cofRelax2 = 1;
8832let cofMax1 = 1;
8833let Uses = [P1];
8834let Defs = [P1, PC];
8835let isTaken = Inst{13};
8836let isExtendable = 1;
8837let opExtendable = 1;
8838let isExtentSigned = 1;
8839let opExtentBits = 11;
8840let opExtentAlign = 2;
8841}
8842def L2_deallocframe : HInst<
8843(outs DoubleRegs:$Rdd32),
8844(ins IntRegs:$Rs32),
8845"$Rdd32 = deallocframe($Rs32):raw",
8846tc_e9170fb7, TypeLD>, Enc_3a3d62 {
8847let Inst{13-5} = 0b000000000;
8848let Inst{31-21} = 0b10010000000;
8849let accessSize = DoubleWordAccess;
8850let mayLoad = 1;
8851let Uses = [FRAMEKEY];
8852let Defs = [R29];
8853}
8854def L2_loadalignb_io : HInst<
8855(outs DoubleRegs:$Ryy32),
8856(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
8857"$Ryy32 = memb_fifo($Rs32+#$Ii)",
8858tc_fedb7e19, TypeLD>, Enc_a27588 {
8859let Inst{24-21} = 0b0100;
8860let Inst{31-27} = 0b10010;
8861let addrMode = BaseImmOffset;
8862let accessSize = ByteAccess;
8863let mayLoad = 1;
8864let isExtendable = 1;
8865let opExtendable = 3;
8866let isExtentSigned = 1;
8867let opExtentBits = 11;
8868let opExtentAlign = 0;
8869let Constraints = "$Ryy32 = $Ryy32in";
8870}
8871def L2_loadalignb_pbr : HInst<
8872(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8873(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8874"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
8875tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8876let Inst{12-5} = 0b00000000;
8877let Inst{31-21} = 0b10011110100;
8878let addrMode = PostInc;
8879let accessSize = ByteAccess;
8880let mayLoad = 1;
8881let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8882}
8883def L2_loadalignb_pci : HInst<
8884(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8885(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
8886"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
8887tc_76bb5435, TypeLD>, Enc_74aef2 {
8888let Inst{12-9} = 0b0000;
8889let Inst{31-21} = 0b10011000100;
8890let addrMode = PostInc;
8891let accessSize = ByteAccess;
8892let mayLoad = 1;
8893let Uses = [CS];
8894let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8895}
8896def L2_loadalignb_pcr : HInst<
8897(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8898(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8899"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
8900tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8901let Inst{12-5} = 0b00010000;
8902let Inst{31-21} = 0b10011000100;
8903let addrMode = PostInc;
8904let accessSize = ByteAccess;
8905let mayLoad = 1;
8906let Uses = [CS];
8907let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8908}
8909def L2_loadalignb_pi : HInst<
8910(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8911(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
8912"$Ryy32 = memb_fifo($Rx32++#$Ii)",
8913tc_1c7522a8, TypeLD>, Enc_6b197f {
8914let Inst{13-9} = 0b00000;
8915let Inst{31-21} = 0b10011010100;
8916let addrMode = PostInc;
8917let accessSize = ByteAccess;
8918let mayLoad = 1;
8919let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8920}
8921def L2_loadalignb_pr : HInst<
8922(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8923(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8924"$Ryy32 = memb_fifo($Rx32++$Mu2)",
8925tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8926let Inst{12-5} = 0b00000000;
8927let Inst{31-21} = 0b10011100100;
8928let addrMode = PostInc;
8929let accessSize = ByteAccess;
8930let mayLoad = 1;
8931let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8932}
8933def L2_loadalignb_zomap : HInst<
8934(outs DoubleRegs:$Ryy32),
8935(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8936"$Ryy32 = memb_fifo($Rs32)",
8937tc_fedb7e19, TypeMAPPING> {
8938let isPseudo = 1;
8939let isCodeGenOnly = 1;
8940let Constraints = "$Ryy32 = $Ryy32in";
8941}
8942def L2_loadalignh_io : HInst<
8943(outs DoubleRegs:$Ryy32),
8944(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
8945"$Ryy32 = memh_fifo($Rs32+#$Ii)",
8946tc_fedb7e19, TypeLD>, Enc_5cd7e9 {
8947let Inst{24-21} = 0b0010;
8948let Inst{31-27} = 0b10010;
8949let addrMode = BaseImmOffset;
8950let accessSize = HalfWordAccess;
8951let mayLoad = 1;
8952let isExtendable = 1;
8953let opExtendable = 3;
8954let isExtentSigned = 1;
8955let opExtentBits = 12;
8956let opExtentAlign = 1;
8957let Constraints = "$Ryy32 = $Ryy32in";
8958}
8959def L2_loadalignh_pbr : HInst<
8960(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8961(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8962"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
8963tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8964let Inst{12-5} = 0b00000000;
8965let Inst{31-21} = 0b10011110010;
8966let addrMode = PostInc;
8967let accessSize = HalfWordAccess;
8968let mayLoad = 1;
8969let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8970}
8971def L2_loadalignh_pci : HInst<
8972(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8973(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
8974"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
8975tc_76bb5435, TypeLD>, Enc_9e2e1c {
8976let Inst{12-9} = 0b0000;
8977let Inst{31-21} = 0b10011000010;
8978let addrMode = PostInc;
8979let accessSize = HalfWordAccess;
8980let mayLoad = 1;
8981let Uses = [CS];
8982let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8983}
8984def L2_loadalignh_pcr : HInst<
8985(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8986(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8987"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
8988tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8989let Inst{12-5} = 0b00010000;
8990let Inst{31-21} = 0b10011000010;
8991let addrMode = PostInc;
8992let accessSize = HalfWordAccess;
8993let mayLoad = 1;
8994let Uses = [CS];
8995let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8996}
8997def L2_loadalignh_pi : HInst<
8998(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8999(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
9000"$Ryy32 = memh_fifo($Rx32++#$Ii)",
9001tc_1c7522a8, TypeLD>, Enc_bd1cbc {
9002let Inst{13-9} = 0b00000;
9003let Inst{31-21} = 0b10011010010;
9004let addrMode = PostInc;
9005let accessSize = HalfWordAccess;
9006let mayLoad = 1;
9007let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9008}
9009def L2_loadalignh_pr : HInst<
9010(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9011(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9012"$Ryy32 = memh_fifo($Rx32++$Mu2)",
9013tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9014let Inst{12-5} = 0b00000000;
9015let Inst{31-21} = 0b10011100010;
9016let addrMode = PostInc;
9017let accessSize = HalfWordAccess;
9018let mayLoad = 1;
9019let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9020}
9021def L2_loadalignh_zomap : HInst<
9022(outs DoubleRegs:$Ryy32),
9023(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
9024"$Ryy32 = memh_fifo($Rs32)",
9025tc_fedb7e19, TypeMAPPING> {
9026let isPseudo = 1;
9027let isCodeGenOnly = 1;
9028let Constraints = "$Ryy32 = $Ryy32in";
9029}
9030def L2_loadbsw2_io : HInst<
9031(outs IntRegs:$Rd32),
9032(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9033"$Rd32 = membh($Rs32+#$Ii)",
9034tc_4222e6bf, TypeLD>, Enc_de0214 {
9035let Inst{24-21} = 0b0001;
9036let Inst{31-27} = 0b10010;
9037let hasNewValue = 1;
9038let opNewValue = 0;
9039let addrMode = BaseImmOffset;
9040let accessSize = HalfWordAccess;
9041let mayLoad = 1;
9042let isExtendable = 1;
9043let opExtendable = 2;
9044let isExtentSigned = 1;
9045let opExtentBits = 12;
9046let opExtentAlign = 1;
9047}
9048def L2_loadbsw2_pbr : HInst<
9049(outs IntRegs:$Rd32, IntRegs:$Rx32),
9050(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9051"$Rd32 = membh($Rx32++$Mu2:brev)",
9052tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9053let Inst{12-5} = 0b00000000;
9054let Inst{31-21} = 0b10011110001;
9055let hasNewValue = 1;
9056let opNewValue = 0;
9057let addrMode = PostInc;
9058let accessSize = HalfWordAccess;
9059let mayLoad = 1;
9060let Constraints = "$Rx32 = $Rx32in";
9061}
9062def L2_loadbsw2_pci : HInst<
9063(outs IntRegs:$Rd32, IntRegs:$Rx32),
9064(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9065"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
9066tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9067let Inst{12-9} = 0b0000;
9068let Inst{31-21} = 0b10011000001;
9069let hasNewValue = 1;
9070let opNewValue = 0;
9071let addrMode = PostInc;
9072let accessSize = HalfWordAccess;
9073let mayLoad = 1;
9074let Uses = [CS];
9075let Constraints = "$Rx32 = $Rx32in";
9076}
9077def L2_loadbsw2_pcr : HInst<
9078(outs IntRegs:$Rd32, IntRegs:$Rx32),
9079(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9080"$Rd32 = membh($Rx32++I:circ($Mu2))",
9081tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9082let Inst{12-5} = 0b00010000;
9083let Inst{31-21} = 0b10011000001;
9084let hasNewValue = 1;
9085let opNewValue = 0;
9086let addrMode = PostInc;
9087let accessSize = HalfWordAccess;
9088let mayLoad = 1;
9089let Uses = [CS];
9090let Constraints = "$Rx32 = $Rx32in";
9091}
9092def L2_loadbsw2_pi : HInst<
9093(outs IntRegs:$Rd32, IntRegs:$Rx32),
9094(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9095"$Rd32 = membh($Rx32++#$Ii)",
9096tc_075c8dd8, TypeLD>, Enc_152467 {
9097let Inst{13-9} = 0b00000;
9098let Inst{31-21} = 0b10011010001;
9099let hasNewValue = 1;
9100let opNewValue = 0;
9101let addrMode = PostInc;
9102let accessSize = HalfWordAccess;
9103let mayLoad = 1;
9104let Constraints = "$Rx32 = $Rx32in";
9105}
9106def L2_loadbsw2_pr : HInst<
9107(outs IntRegs:$Rd32, IntRegs:$Rx32),
9108(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9109"$Rd32 = membh($Rx32++$Mu2)",
9110tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9111let Inst{12-5} = 0b00000000;
9112let Inst{31-21} = 0b10011100001;
9113let hasNewValue = 1;
9114let opNewValue = 0;
9115let addrMode = PostInc;
9116let accessSize = HalfWordAccess;
9117let mayLoad = 1;
9118let Constraints = "$Rx32 = $Rx32in";
9119}
9120def L2_loadbsw2_zomap : HInst<
9121(outs IntRegs:$Rd32),
9122(ins IntRegs:$Rs32),
9123"$Rd32 = membh($Rs32)",
9124tc_4222e6bf, TypeMAPPING> {
9125let hasNewValue = 1;
9126let opNewValue = 0;
9127let isPseudo = 1;
9128let isCodeGenOnly = 1;
9129}
9130def L2_loadbsw4_io : HInst<
9131(outs DoubleRegs:$Rdd32),
9132(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9133"$Rdd32 = membh($Rs32+#$Ii)",
9134tc_4222e6bf, TypeLD>, Enc_2d7491 {
9135let Inst{24-21} = 0b0111;
9136let Inst{31-27} = 0b10010;
9137let addrMode = BaseImmOffset;
9138let accessSize = WordAccess;
9139let mayLoad = 1;
9140let isExtendable = 1;
9141let opExtendable = 2;
9142let isExtentSigned = 1;
9143let opExtentBits = 13;
9144let opExtentAlign = 2;
9145}
9146def L2_loadbsw4_pbr : HInst<
9147(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9148(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9149"$Rdd32 = membh($Rx32++$Mu2:brev)",
9150tc_075c8dd8, TypeLD>, Enc_7eee72 {
9151let Inst{12-5} = 0b00000000;
9152let Inst{31-21} = 0b10011110111;
9153let addrMode = PostInc;
9154let accessSize = WordAccess;
9155let mayLoad = 1;
9156let Constraints = "$Rx32 = $Rx32in";
9157}
9158def L2_loadbsw4_pci : HInst<
9159(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9160(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9161"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
9162tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9163let Inst{12-9} = 0b0000;
9164let Inst{31-21} = 0b10011000111;
9165let addrMode = PostInc;
9166let accessSize = WordAccess;
9167let mayLoad = 1;
9168let Uses = [CS];
9169let Constraints = "$Rx32 = $Rx32in";
9170}
9171def L2_loadbsw4_pcr : HInst<
9172(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9173(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9174"$Rdd32 = membh($Rx32++I:circ($Mu2))",
9175tc_075c8dd8, TypeLD>, Enc_7eee72 {
9176let Inst{12-5} = 0b00010000;
9177let Inst{31-21} = 0b10011000111;
9178let addrMode = PostInc;
9179let accessSize = WordAccess;
9180let mayLoad = 1;
9181let Uses = [CS];
9182let Constraints = "$Rx32 = $Rx32in";
9183}
9184def L2_loadbsw4_pi : HInst<
9185(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9186(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9187"$Rdd32 = membh($Rx32++#$Ii)",
9188tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9189let Inst{13-9} = 0b00000;
9190let Inst{31-21} = 0b10011010111;
9191let addrMode = PostInc;
9192let accessSize = WordAccess;
9193let mayLoad = 1;
9194let Constraints = "$Rx32 = $Rx32in";
9195}
9196def L2_loadbsw4_pr : HInst<
9197(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9198(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9199"$Rdd32 = membh($Rx32++$Mu2)",
9200tc_075c8dd8, TypeLD>, Enc_7eee72 {
9201let Inst{12-5} = 0b00000000;
9202let Inst{31-21} = 0b10011100111;
9203let addrMode = PostInc;
9204let accessSize = WordAccess;
9205let mayLoad = 1;
9206let Constraints = "$Rx32 = $Rx32in";
9207}
9208def L2_loadbsw4_zomap : HInst<
9209(outs DoubleRegs:$Rdd32),
9210(ins IntRegs:$Rs32),
9211"$Rdd32 = membh($Rs32)",
9212tc_4222e6bf, TypeMAPPING> {
9213let isPseudo = 1;
9214let isCodeGenOnly = 1;
9215}
9216def L2_loadbzw2_io : HInst<
9217(outs IntRegs:$Rd32),
9218(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9219"$Rd32 = memubh($Rs32+#$Ii)",
9220tc_4222e6bf, TypeLD>, Enc_de0214 {
9221let Inst{24-21} = 0b0011;
9222let Inst{31-27} = 0b10010;
9223let hasNewValue = 1;
9224let opNewValue = 0;
9225let addrMode = BaseImmOffset;
9226let accessSize = HalfWordAccess;
9227let mayLoad = 1;
9228let isExtendable = 1;
9229let opExtendable = 2;
9230let isExtentSigned = 1;
9231let opExtentBits = 12;
9232let opExtentAlign = 1;
9233}
9234def L2_loadbzw2_pbr : HInst<
9235(outs IntRegs:$Rd32, IntRegs:$Rx32),
9236(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9237"$Rd32 = memubh($Rx32++$Mu2:brev)",
9238tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9239let Inst{12-5} = 0b00000000;
9240let Inst{31-21} = 0b10011110011;
9241let hasNewValue = 1;
9242let opNewValue = 0;
9243let addrMode = PostInc;
9244let accessSize = HalfWordAccess;
9245let mayLoad = 1;
9246let Constraints = "$Rx32 = $Rx32in";
9247}
9248def L2_loadbzw2_pci : HInst<
9249(outs IntRegs:$Rd32, IntRegs:$Rx32),
9250(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9251"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9252tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9253let Inst{12-9} = 0b0000;
9254let Inst{31-21} = 0b10011000011;
9255let hasNewValue = 1;
9256let opNewValue = 0;
9257let addrMode = PostInc;
9258let accessSize = HalfWordAccess;
9259let mayLoad = 1;
9260let Uses = [CS];
9261let Constraints = "$Rx32 = $Rx32in";
9262}
9263def L2_loadbzw2_pcr : HInst<
9264(outs IntRegs:$Rd32, IntRegs:$Rx32),
9265(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9266"$Rd32 = memubh($Rx32++I:circ($Mu2))",
9267tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9268let Inst{12-5} = 0b00010000;
9269let Inst{31-21} = 0b10011000011;
9270let hasNewValue = 1;
9271let opNewValue = 0;
9272let addrMode = PostInc;
9273let accessSize = HalfWordAccess;
9274let mayLoad = 1;
9275let Uses = [CS];
9276let Constraints = "$Rx32 = $Rx32in";
9277}
9278def L2_loadbzw2_pi : HInst<
9279(outs IntRegs:$Rd32, IntRegs:$Rx32),
9280(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9281"$Rd32 = memubh($Rx32++#$Ii)",
9282tc_075c8dd8, TypeLD>, Enc_152467 {
9283let Inst{13-9} = 0b00000;
9284let Inst{31-21} = 0b10011010011;
9285let hasNewValue = 1;
9286let opNewValue = 0;
9287let addrMode = PostInc;
9288let accessSize = HalfWordAccess;
9289let mayLoad = 1;
9290let Constraints = "$Rx32 = $Rx32in";
9291}
9292def L2_loadbzw2_pr : HInst<
9293(outs IntRegs:$Rd32, IntRegs:$Rx32),
9294(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9295"$Rd32 = memubh($Rx32++$Mu2)",
9296tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9297let Inst{12-5} = 0b00000000;
9298let Inst{31-21} = 0b10011100011;
9299let hasNewValue = 1;
9300let opNewValue = 0;
9301let addrMode = PostInc;
9302let accessSize = HalfWordAccess;
9303let mayLoad = 1;
9304let Constraints = "$Rx32 = $Rx32in";
9305}
9306def L2_loadbzw2_zomap : HInst<
9307(outs IntRegs:$Rd32),
9308(ins IntRegs:$Rs32),
9309"$Rd32 = memubh($Rs32)",
9310tc_4222e6bf, TypeMAPPING> {
9311let hasNewValue = 1;
9312let opNewValue = 0;
9313let isPseudo = 1;
9314let isCodeGenOnly = 1;
9315}
9316def L2_loadbzw4_io : HInst<
9317(outs DoubleRegs:$Rdd32),
9318(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9319"$Rdd32 = memubh($Rs32+#$Ii)",
9320tc_4222e6bf, TypeLD>, Enc_2d7491 {
9321let Inst{24-21} = 0b0101;
9322let Inst{31-27} = 0b10010;
9323let addrMode = BaseImmOffset;
9324let accessSize = WordAccess;
9325let mayLoad = 1;
9326let isExtendable = 1;
9327let opExtendable = 2;
9328let isExtentSigned = 1;
9329let opExtentBits = 13;
9330let opExtentAlign = 2;
9331}
9332def L2_loadbzw4_pbr : HInst<
9333(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9334(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9335"$Rdd32 = memubh($Rx32++$Mu2:brev)",
9336tc_075c8dd8, TypeLD>, Enc_7eee72 {
9337let Inst{12-5} = 0b00000000;
9338let Inst{31-21} = 0b10011110101;
9339let addrMode = PostInc;
9340let accessSize = WordAccess;
9341let mayLoad = 1;
9342let Constraints = "$Rx32 = $Rx32in";
9343}
9344def L2_loadbzw4_pci : HInst<
9345(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9346(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9347"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9348tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9349let Inst{12-9} = 0b0000;
9350let Inst{31-21} = 0b10011000101;
9351let addrMode = PostInc;
9352let accessSize = WordAccess;
9353let mayLoad = 1;
9354let Uses = [CS];
9355let Constraints = "$Rx32 = $Rx32in";
9356}
9357def L2_loadbzw4_pcr : HInst<
9358(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9359(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9360"$Rdd32 = memubh($Rx32++I:circ($Mu2))",
9361tc_075c8dd8, TypeLD>, Enc_7eee72 {
9362let Inst{12-5} = 0b00010000;
9363let Inst{31-21} = 0b10011000101;
9364let addrMode = PostInc;
9365let accessSize = WordAccess;
9366let mayLoad = 1;
9367let Uses = [CS];
9368let Constraints = "$Rx32 = $Rx32in";
9369}
9370def L2_loadbzw4_pi : HInst<
9371(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9372(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9373"$Rdd32 = memubh($Rx32++#$Ii)",
9374tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9375let Inst{13-9} = 0b00000;
9376let Inst{31-21} = 0b10011010101;
9377let addrMode = PostInc;
9378let accessSize = WordAccess;
9379let mayLoad = 1;
9380let Constraints = "$Rx32 = $Rx32in";
9381}
9382def L2_loadbzw4_pr : HInst<
9383(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9384(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9385"$Rdd32 = memubh($Rx32++$Mu2)",
9386tc_075c8dd8, TypeLD>, Enc_7eee72 {
9387let Inst{12-5} = 0b00000000;
9388let Inst{31-21} = 0b10011100101;
9389let addrMode = PostInc;
9390let accessSize = WordAccess;
9391let mayLoad = 1;
9392let Constraints = "$Rx32 = $Rx32in";
9393}
9394def L2_loadbzw4_zomap : HInst<
9395(outs DoubleRegs:$Rdd32),
9396(ins IntRegs:$Rs32),
9397"$Rdd32 = memubh($Rs32)",
9398tc_4222e6bf, TypeMAPPING> {
9399let isPseudo = 1;
9400let isCodeGenOnly = 1;
9401}
9402def L2_loadrb_io : HInst<
9403(outs IntRegs:$Rd32),
9404(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9405"$Rd32 = memb($Rs32+#$Ii)",
9406tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9407let Inst{24-21} = 0b1000;
9408let Inst{31-27} = 0b10010;
9409let hasNewValue = 1;
9410let opNewValue = 0;
9411let addrMode = BaseImmOffset;
9412let accessSize = ByteAccess;
9413let mayLoad = 1;
9414let BaseOpcode = "L2_loadrb_io";
9415let CextOpcode = "L2_loadrb";
9416let isPredicable = 1;
9417let isExtendable = 1;
9418let opExtendable = 2;
9419let isExtentSigned = 1;
9420let opExtentBits = 11;
9421let opExtentAlign = 0;
9422}
9423def L2_loadrb_pbr : HInst<
9424(outs IntRegs:$Rd32, IntRegs:$Rx32),
9425(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9426"$Rd32 = memb($Rx32++$Mu2:brev)",
9427tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9428let Inst{12-5} = 0b00000000;
9429let Inst{31-21} = 0b10011111000;
9430let hasNewValue = 1;
9431let opNewValue = 0;
9432let addrMode = PostInc;
9433let accessSize = ByteAccess;
9434let mayLoad = 1;
9435let Constraints = "$Rx32 = $Rx32in";
9436}
9437def L2_loadrb_pci : HInst<
9438(outs IntRegs:$Rd32, IntRegs:$Rx32),
9439(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9440"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
9441tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9442let Inst{12-9} = 0b0000;
9443let Inst{31-21} = 0b10011001000;
9444let hasNewValue = 1;
9445let opNewValue = 0;
9446let addrMode = PostInc;
9447let accessSize = ByteAccess;
9448let mayLoad = 1;
9449let Uses = [CS];
9450let Constraints = "$Rx32 = $Rx32in";
9451}
9452def L2_loadrb_pcr : HInst<
9453(outs IntRegs:$Rd32, IntRegs:$Rx32),
9454(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9455"$Rd32 = memb($Rx32++I:circ($Mu2))",
9456tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9457let Inst{12-5} = 0b00010000;
9458let Inst{31-21} = 0b10011001000;
9459let hasNewValue = 1;
9460let opNewValue = 0;
9461let addrMode = PostInc;
9462let accessSize = ByteAccess;
9463let mayLoad = 1;
9464let Uses = [CS];
9465let Constraints = "$Rx32 = $Rx32in";
9466}
9467def L2_loadrb_pi : HInst<
9468(outs IntRegs:$Rd32, IntRegs:$Rx32),
9469(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9470"$Rd32 = memb($Rx32++#$Ii)",
9471tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9472let Inst{13-9} = 0b00000;
9473let Inst{31-21} = 0b10011011000;
9474let hasNewValue = 1;
9475let opNewValue = 0;
9476let addrMode = PostInc;
9477let accessSize = ByteAccess;
9478let mayLoad = 1;
9479let BaseOpcode = "L2_loadrb_pi";
9480let CextOpcode = "L2_loadrb";
9481let isPredicable = 1;
9482let Constraints = "$Rx32 = $Rx32in";
9483}
9484def L2_loadrb_pr : HInst<
9485(outs IntRegs:$Rd32, IntRegs:$Rx32),
9486(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9487"$Rd32 = memb($Rx32++$Mu2)",
9488tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9489let Inst{12-5} = 0b00000000;
9490let Inst{31-21} = 0b10011101000;
9491let hasNewValue = 1;
9492let opNewValue = 0;
9493let addrMode = PostInc;
9494let accessSize = ByteAccess;
9495let mayLoad = 1;
9496let Constraints = "$Rx32 = $Rx32in";
9497}
9498def L2_loadrb_zomap : HInst<
9499(outs IntRegs:$Rd32),
9500(ins IntRegs:$Rs32),
9501"$Rd32 = memb($Rs32)",
9502tc_4222e6bf, TypeMAPPING> {
9503let hasNewValue = 1;
9504let opNewValue = 0;
9505let isPseudo = 1;
9506let isCodeGenOnly = 1;
9507}
9508def L2_loadrbgp : HInst<
9509(outs IntRegs:$Rd32),
9510(ins u32_0Imm:$Ii),
9511"$Rd32 = memb(gp+#$Ii)",
9512tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9513let Inst{24-21} = 0b1000;
9514let Inst{31-27} = 0b01001;
9515let hasNewValue = 1;
9516let opNewValue = 0;
9517let accessSize = ByteAccess;
9518let mayLoad = 1;
9519let Uses = [GP];
9520let BaseOpcode = "L4_loadrb_abs";
9521let isPredicable = 1;
9522let opExtendable = 1;
9523let isExtentSigned = 0;
9524let opExtentBits = 16;
9525let opExtentAlign = 0;
9526}
9527def L2_loadrd_io : HInst<
9528(outs DoubleRegs:$Rdd32),
9529(ins IntRegs:$Rs32, s29_3Imm:$Ii),
9530"$Rdd32 = memd($Rs32+#$Ii)",
9531tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
9532let Inst{24-21} = 0b1110;
9533let Inst{31-27} = 0b10010;
9534let addrMode = BaseImmOffset;
9535let accessSize = DoubleWordAccess;
9536let mayLoad = 1;
9537let BaseOpcode = "L2_loadrd_io";
9538let CextOpcode = "L2_loadrd";
9539let isPredicable = 1;
9540let isExtendable = 1;
9541let opExtendable = 2;
9542let isExtentSigned = 1;
9543let opExtentBits = 14;
9544let opExtentAlign = 3;
9545}
9546def L2_loadrd_pbr : HInst<
9547(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9548(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9549"$Rdd32 = memd($Rx32++$Mu2:brev)",
9550tc_075c8dd8, TypeLD>, Enc_7eee72 {
9551let Inst{12-5} = 0b00000000;
9552let Inst{31-21} = 0b10011111110;
9553let addrMode = PostInc;
9554let accessSize = DoubleWordAccess;
9555let mayLoad = 1;
9556let Constraints = "$Rx32 = $Rx32in";
9557}
9558def L2_loadrd_pci : HInst<
9559(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9560(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
9561"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
9562tc_5ceb2f9e, TypeLD>, Enc_b05839 {
9563let Inst{12-9} = 0b0000;
9564let Inst{31-21} = 0b10011001110;
9565let addrMode = PostInc;
9566let accessSize = DoubleWordAccess;
9567let mayLoad = 1;
9568let Uses = [CS];
9569let Constraints = "$Rx32 = $Rx32in";
9570}
9571def L2_loadrd_pcr : HInst<
9572(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9573(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9574"$Rdd32 = memd($Rx32++I:circ($Mu2))",
9575tc_075c8dd8, TypeLD>, Enc_7eee72 {
9576let Inst{12-5} = 0b00010000;
9577let Inst{31-21} = 0b10011001110;
9578let addrMode = PostInc;
9579let accessSize = DoubleWordAccess;
9580let mayLoad = 1;
9581let Uses = [CS];
9582let Constraints = "$Rx32 = $Rx32in";
9583}
9584def L2_loadrd_pi : HInst<
9585(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9586(ins IntRegs:$Rx32in, s4_3Imm:$Ii),
9587"$Rdd32 = memd($Rx32++#$Ii)",
9588tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
9589let Inst{13-9} = 0b00000;
9590let Inst{31-21} = 0b10011011110;
9591let addrMode = PostInc;
9592let accessSize = DoubleWordAccess;
9593let mayLoad = 1;
9594let BaseOpcode = "L2_loadrd_pi";
9595let CextOpcode = "L2_loadrd";
9596let isPredicable = 1;
9597let Constraints = "$Rx32 = $Rx32in";
9598}
9599def L2_loadrd_pr : HInst<
9600(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9601(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9602"$Rdd32 = memd($Rx32++$Mu2)",
9603tc_075c8dd8, TypeLD>, Enc_7eee72 {
9604let Inst{12-5} = 0b00000000;
9605let Inst{31-21} = 0b10011101110;
9606let addrMode = PostInc;
9607let accessSize = DoubleWordAccess;
9608let mayLoad = 1;
9609let Constraints = "$Rx32 = $Rx32in";
9610}
9611def L2_loadrd_zomap : HInst<
9612(outs DoubleRegs:$Rdd32),
9613(ins IntRegs:$Rs32),
9614"$Rdd32 = memd($Rs32)",
9615tc_4222e6bf, TypeMAPPING> {
9616let isPseudo = 1;
9617let isCodeGenOnly = 1;
9618}
9619def L2_loadrdgp : HInst<
9620(outs DoubleRegs:$Rdd32),
9621(ins u29_3Imm:$Ii),
9622"$Rdd32 = memd(gp+#$Ii)",
9623tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
9624let Inst{24-21} = 0b1110;
9625let Inst{31-27} = 0b01001;
9626let accessSize = DoubleWordAccess;
9627let mayLoad = 1;
9628let Uses = [GP];
9629let BaseOpcode = "L4_loadrd_abs";
9630let isPredicable = 1;
9631let opExtendable = 1;
9632let isExtentSigned = 0;
9633let opExtentBits = 19;
9634let opExtentAlign = 3;
9635}
9636def L2_loadrh_io : HInst<
9637(outs IntRegs:$Rd32),
9638(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9639"$Rd32 = memh($Rs32+#$Ii)",
9640tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9641let Inst{24-21} = 0b1010;
9642let Inst{31-27} = 0b10010;
9643let hasNewValue = 1;
9644let opNewValue = 0;
9645let addrMode = BaseImmOffset;
9646let accessSize = HalfWordAccess;
9647let mayLoad = 1;
9648let BaseOpcode = "L2_loadrh_io";
9649let CextOpcode = "L2_loadrh";
9650let isPredicable = 1;
9651let isExtendable = 1;
9652let opExtendable = 2;
9653let isExtentSigned = 1;
9654let opExtentBits = 12;
9655let opExtentAlign = 1;
9656}
9657def L2_loadrh_pbr : HInst<
9658(outs IntRegs:$Rd32, IntRegs:$Rx32),
9659(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9660"$Rd32 = memh($Rx32++$Mu2:brev)",
9661tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9662let Inst{12-5} = 0b00000000;
9663let Inst{31-21} = 0b10011111010;
9664let hasNewValue = 1;
9665let opNewValue = 0;
9666let addrMode = PostInc;
9667let accessSize = HalfWordAccess;
9668let mayLoad = 1;
9669let Constraints = "$Rx32 = $Rx32in";
9670}
9671def L2_loadrh_pci : HInst<
9672(outs IntRegs:$Rd32, IntRegs:$Rx32),
9673(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9674"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
9675tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9676let Inst{12-9} = 0b0000;
9677let Inst{31-21} = 0b10011001010;
9678let hasNewValue = 1;
9679let opNewValue = 0;
9680let addrMode = PostInc;
9681let accessSize = HalfWordAccess;
9682let mayLoad = 1;
9683let Uses = [CS];
9684let Constraints = "$Rx32 = $Rx32in";
9685}
9686def L2_loadrh_pcr : HInst<
9687(outs IntRegs:$Rd32, IntRegs:$Rx32),
9688(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9689"$Rd32 = memh($Rx32++I:circ($Mu2))",
9690tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9691let Inst{12-5} = 0b00010000;
9692let Inst{31-21} = 0b10011001010;
9693let hasNewValue = 1;
9694let opNewValue = 0;
9695let addrMode = PostInc;
9696let accessSize = HalfWordAccess;
9697let mayLoad = 1;
9698let Uses = [CS];
9699let Constraints = "$Rx32 = $Rx32in";
9700}
9701def L2_loadrh_pi : HInst<
9702(outs IntRegs:$Rd32, IntRegs:$Rx32),
9703(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9704"$Rd32 = memh($Rx32++#$Ii)",
9705tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9706let Inst{13-9} = 0b00000;
9707let Inst{31-21} = 0b10011011010;
9708let hasNewValue = 1;
9709let opNewValue = 0;
9710let addrMode = PostInc;
9711let accessSize = HalfWordAccess;
9712let mayLoad = 1;
9713let BaseOpcode = "L2_loadrh_pi";
9714let CextOpcode = "L2_loadrh";
9715let isPredicable = 1;
9716let Constraints = "$Rx32 = $Rx32in";
9717}
9718def L2_loadrh_pr : HInst<
9719(outs IntRegs:$Rd32, IntRegs:$Rx32),
9720(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9721"$Rd32 = memh($Rx32++$Mu2)",
9722tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9723let Inst{12-5} = 0b00000000;
9724let Inst{31-21} = 0b10011101010;
9725let hasNewValue = 1;
9726let opNewValue = 0;
9727let addrMode = PostInc;
9728let accessSize = HalfWordAccess;
9729let mayLoad = 1;
9730let Constraints = "$Rx32 = $Rx32in";
9731}
9732def L2_loadrh_zomap : HInst<
9733(outs IntRegs:$Rd32),
9734(ins IntRegs:$Rs32),
9735"$Rd32 = memh($Rs32)",
9736tc_4222e6bf, TypeMAPPING> {
9737let hasNewValue = 1;
9738let opNewValue = 0;
9739let isPseudo = 1;
9740let isCodeGenOnly = 1;
9741}
9742def L2_loadrhgp : HInst<
9743(outs IntRegs:$Rd32),
9744(ins u31_1Imm:$Ii),
9745"$Rd32 = memh(gp+#$Ii)",
9746tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9747let Inst{24-21} = 0b1010;
9748let Inst{31-27} = 0b01001;
9749let hasNewValue = 1;
9750let opNewValue = 0;
9751let accessSize = HalfWordAccess;
9752let mayLoad = 1;
9753let Uses = [GP];
9754let BaseOpcode = "L4_loadrh_abs";
9755let isPredicable = 1;
9756let opExtendable = 1;
9757let isExtentSigned = 0;
9758let opExtentBits = 17;
9759let opExtentAlign = 1;
9760}
9761def L2_loadri_io : HInst<
9762(outs IntRegs:$Rd32),
9763(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9764"$Rd32 = memw($Rs32+#$Ii)",
9765tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
9766let Inst{24-21} = 0b1100;
9767let Inst{31-27} = 0b10010;
9768let hasNewValue = 1;
9769let opNewValue = 0;
9770let addrMode = BaseImmOffset;
9771let accessSize = WordAccess;
9772let mayLoad = 1;
9773let BaseOpcode = "L2_loadri_io";
9774let CextOpcode = "L2_loadri";
9775let isPredicable = 1;
9776let isExtendable = 1;
9777let opExtendable = 2;
9778let isExtentSigned = 1;
9779let opExtentBits = 13;
9780let opExtentAlign = 2;
9781}
9782def L2_loadri_pbr : HInst<
9783(outs IntRegs:$Rd32, IntRegs:$Rx32),
9784(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9785"$Rd32 = memw($Rx32++$Mu2:brev)",
9786tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9787let Inst{12-5} = 0b00000000;
9788let Inst{31-21} = 0b10011111100;
9789let hasNewValue = 1;
9790let opNewValue = 0;
9791let addrMode = PostInc;
9792let accessSize = WordAccess;
9793let mayLoad = 1;
9794let Constraints = "$Rx32 = $Rx32in";
9795}
9796def L2_loadri_pci : HInst<
9797(outs IntRegs:$Rd32, IntRegs:$Rx32),
9798(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9799"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
9800tc_5ceb2f9e, TypeLD>, Enc_27fd0e {
9801let Inst{12-9} = 0b0000;
9802let Inst{31-21} = 0b10011001100;
9803let hasNewValue = 1;
9804let opNewValue = 0;
9805let addrMode = PostInc;
9806let accessSize = WordAccess;
9807let mayLoad = 1;
9808let Uses = [CS];
9809let Constraints = "$Rx32 = $Rx32in";
9810}
9811def L2_loadri_pcr : HInst<
9812(outs IntRegs:$Rd32, IntRegs:$Rx32),
9813(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9814"$Rd32 = memw($Rx32++I:circ($Mu2))",
9815tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9816let Inst{12-5} = 0b00010000;
9817let Inst{31-21} = 0b10011001100;
9818let hasNewValue = 1;
9819let opNewValue = 0;
9820let addrMode = PostInc;
9821let accessSize = WordAccess;
9822let mayLoad = 1;
9823let Uses = [CS];
9824let Constraints = "$Rx32 = $Rx32in";
9825}
9826def L2_loadri_pi : HInst<
9827(outs IntRegs:$Rd32, IntRegs:$Rx32),
9828(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9829"$Rd32 = memw($Rx32++#$Ii)",
9830tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
9831let Inst{13-9} = 0b00000;
9832let Inst{31-21} = 0b10011011100;
9833let hasNewValue = 1;
9834let opNewValue = 0;
9835let addrMode = PostInc;
9836let accessSize = WordAccess;
9837let mayLoad = 1;
9838let BaseOpcode = "L2_loadri_pi";
9839let CextOpcode = "L2_loadri";
9840let isPredicable = 1;
9841let Constraints = "$Rx32 = $Rx32in";
9842}
9843def L2_loadri_pr : HInst<
9844(outs IntRegs:$Rd32, IntRegs:$Rx32),
9845(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9846"$Rd32 = memw($Rx32++$Mu2)",
9847tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9848let Inst{12-5} = 0b00000000;
9849let Inst{31-21} = 0b10011101100;
9850let hasNewValue = 1;
9851let opNewValue = 0;
9852let addrMode = PostInc;
9853let accessSize = WordAccess;
9854let mayLoad = 1;
9855let Constraints = "$Rx32 = $Rx32in";
9856}
9857def L2_loadri_zomap : HInst<
9858(outs IntRegs:$Rd32),
9859(ins IntRegs:$Rs32),
9860"$Rd32 = memw($Rs32)",
9861tc_4222e6bf, TypeMAPPING> {
9862let hasNewValue = 1;
9863let opNewValue = 0;
9864let isPseudo = 1;
9865let isCodeGenOnly = 1;
9866}
9867def L2_loadrigp : HInst<
9868(outs IntRegs:$Rd32),
9869(ins u30_2Imm:$Ii),
9870"$Rd32 = memw(gp+#$Ii)",
9871tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
9872let Inst{24-21} = 0b1100;
9873let Inst{31-27} = 0b01001;
9874let hasNewValue = 1;
9875let opNewValue = 0;
9876let accessSize = WordAccess;
9877let mayLoad = 1;
9878let Uses = [GP];
9879let BaseOpcode = "L4_loadri_abs";
9880let isPredicable = 1;
9881let opExtendable = 1;
9882let isExtentSigned = 0;
9883let opExtentBits = 18;
9884let opExtentAlign = 2;
9885}
9886def L2_loadrub_io : HInst<
9887(outs IntRegs:$Rd32),
9888(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9889"$Rd32 = memub($Rs32+#$Ii)",
9890tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9891let Inst{24-21} = 0b1001;
9892let Inst{31-27} = 0b10010;
9893let hasNewValue = 1;
9894let opNewValue = 0;
9895let addrMode = BaseImmOffset;
9896let accessSize = ByteAccess;
9897let mayLoad = 1;
9898let BaseOpcode = "L2_loadrub_io";
9899let CextOpcode = "L2_loadrub";
9900let isPredicable = 1;
9901let isExtendable = 1;
9902let opExtendable = 2;
9903let isExtentSigned = 1;
9904let opExtentBits = 11;
9905let opExtentAlign = 0;
9906}
9907def L2_loadrub_pbr : HInst<
9908(outs IntRegs:$Rd32, IntRegs:$Rx32),
9909(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9910"$Rd32 = memub($Rx32++$Mu2:brev)",
9911tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9912let Inst{12-5} = 0b00000000;
9913let Inst{31-21} = 0b10011111001;
9914let hasNewValue = 1;
9915let opNewValue = 0;
9916let addrMode = PostInc;
9917let accessSize = ByteAccess;
9918let mayLoad = 1;
9919let Constraints = "$Rx32 = $Rx32in";
9920}
9921def L2_loadrub_pci : HInst<
9922(outs IntRegs:$Rd32, IntRegs:$Rx32),
9923(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9924"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
9925tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9926let Inst{12-9} = 0b0000;
9927let Inst{31-21} = 0b10011001001;
9928let hasNewValue = 1;
9929let opNewValue = 0;
9930let addrMode = PostInc;
9931let accessSize = ByteAccess;
9932let mayLoad = 1;
9933let Uses = [CS];
9934let Constraints = "$Rx32 = $Rx32in";
9935}
9936def L2_loadrub_pcr : HInst<
9937(outs IntRegs:$Rd32, IntRegs:$Rx32),
9938(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9939"$Rd32 = memub($Rx32++I:circ($Mu2))",
9940tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9941let Inst{12-5} = 0b00010000;
9942let Inst{31-21} = 0b10011001001;
9943let hasNewValue = 1;
9944let opNewValue = 0;
9945let addrMode = PostInc;
9946let accessSize = ByteAccess;
9947let mayLoad = 1;
9948let Uses = [CS];
9949let Constraints = "$Rx32 = $Rx32in";
9950}
9951def L2_loadrub_pi : HInst<
9952(outs IntRegs:$Rd32, IntRegs:$Rx32),
9953(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9954"$Rd32 = memub($Rx32++#$Ii)",
9955tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9956let Inst{13-9} = 0b00000;
9957let Inst{31-21} = 0b10011011001;
9958let hasNewValue = 1;
9959let opNewValue = 0;
9960let addrMode = PostInc;
9961let accessSize = ByteAccess;
9962let mayLoad = 1;
9963let BaseOpcode = "L2_loadrub_pi";
9964let CextOpcode = "L2_loadrub";
9965let isPredicable = 1;
9966let Constraints = "$Rx32 = $Rx32in";
9967}
9968def L2_loadrub_pr : HInst<
9969(outs IntRegs:$Rd32, IntRegs:$Rx32),
9970(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9971"$Rd32 = memub($Rx32++$Mu2)",
9972tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9973let Inst{12-5} = 0b00000000;
9974let Inst{31-21} = 0b10011101001;
9975let hasNewValue = 1;
9976let opNewValue = 0;
9977let addrMode = PostInc;
9978let accessSize = ByteAccess;
9979let mayLoad = 1;
9980let Constraints = "$Rx32 = $Rx32in";
9981}
9982def L2_loadrub_zomap : HInst<
9983(outs IntRegs:$Rd32),
9984(ins IntRegs:$Rs32),
9985"$Rd32 = memub($Rs32)",
9986tc_4222e6bf, TypeMAPPING> {
9987let hasNewValue = 1;
9988let opNewValue = 0;
9989let isPseudo = 1;
9990let isCodeGenOnly = 1;
9991}
9992def L2_loadrubgp : HInst<
9993(outs IntRegs:$Rd32),
9994(ins u32_0Imm:$Ii),
9995"$Rd32 = memub(gp+#$Ii)",
9996tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9997let Inst{24-21} = 0b1001;
9998let Inst{31-27} = 0b01001;
9999let hasNewValue = 1;
10000let opNewValue = 0;
10001let accessSize = ByteAccess;
10002let mayLoad = 1;
10003let Uses = [GP];
10004let BaseOpcode = "L4_loadrub_abs";
10005let isPredicable = 1;
10006let opExtendable = 1;
10007let isExtentSigned = 0;
10008let opExtentBits = 16;
10009let opExtentAlign = 0;
10010}
10011def L2_loadruh_io : HInst<
10012(outs IntRegs:$Rd32),
10013(ins IntRegs:$Rs32, s31_1Imm:$Ii),
10014"$Rd32 = memuh($Rs32+#$Ii)",
10015tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
10016let Inst{24-21} = 0b1011;
10017let Inst{31-27} = 0b10010;
10018let hasNewValue = 1;
10019let opNewValue = 0;
10020let addrMode = BaseImmOffset;
10021let accessSize = HalfWordAccess;
10022let mayLoad = 1;
10023let BaseOpcode = "L2_loadruh_io";
10024let CextOpcode = "L2_loadruh";
10025let isPredicable = 1;
10026let isExtendable = 1;
10027let opExtendable = 2;
10028let isExtentSigned = 1;
10029let opExtentBits = 12;
10030let opExtentAlign = 1;
10031}
10032def L2_loadruh_pbr : HInst<
10033(outs IntRegs:$Rd32, IntRegs:$Rx32),
10034(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10035"$Rd32 = memuh($Rx32++$Mu2:brev)",
10036tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10037let Inst{12-5} = 0b00000000;
10038let Inst{31-21} = 0b10011111011;
10039let hasNewValue = 1;
10040let opNewValue = 0;
10041let addrMode = PostInc;
10042let accessSize = HalfWordAccess;
10043let mayLoad = 1;
10044let Constraints = "$Rx32 = $Rx32in";
10045}
10046def L2_loadruh_pci : HInst<
10047(outs IntRegs:$Rd32, IntRegs:$Rx32),
10048(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
10049"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
10050tc_5ceb2f9e, TypeLD>, Enc_e83554 {
10051let Inst{12-9} = 0b0000;
10052let Inst{31-21} = 0b10011001011;
10053let hasNewValue = 1;
10054let opNewValue = 0;
10055let addrMode = PostInc;
10056let accessSize = HalfWordAccess;
10057let mayLoad = 1;
10058let Uses = [CS];
10059let Constraints = "$Rx32 = $Rx32in";
10060}
10061def L2_loadruh_pcr : HInst<
10062(outs IntRegs:$Rd32, IntRegs:$Rx32),
10063(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10064"$Rd32 = memuh($Rx32++I:circ($Mu2))",
10065tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10066let Inst{12-5} = 0b00010000;
10067let Inst{31-21} = 0b10011001011;
10068let hasNewValue = 1;
10069let opNewValue = 0;
10070let addrMode = PostInc;
10071let accessSize = HalfWordAccess;
10072let mayLoad = 1;
10073let Uses = [CS];
10074let Constraints = "$Rx32 = $Rx32in";
10075}
10076def L2_loadruh_pi : HInst<
10077(outs IntRegs:$Rd32, IntRegs:$Rx32),
10078(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
10079"$Rd32 = memuh($Rx32++#$Ii)",
10080tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
10081let Inst{13-9} = 0b00000;
10082let Inst{31-21} = 0b10011011011;
10083let hasNewValue = 1;
10084let opNewValue = 0;
10085let addrMode = PostInc;
10086let accessSize = HalfWordAccess;
10087let mayLoad = 1;
10088let BaseOpcode = "L2_loadruh_pi";
10089let CextOpcode = "L2_loadruh";
10090let isPredicable = 1;
10091let Constraints = "$Rx32 = $Rx32in";
10092}
10093def L2_loadruh_pr : HInst<
10094(outs IntRegs:$Rd32, IntRegs:$Rx32),
10095(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10096"$Rd32 = memuh($Rx32++$Mu2)",
10097tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10098let Inst{12-5} = 0b00000000;
10099let Inst{31-21} = 0b10011101011;
10100let hasNewValue = 1;
10101let opNewValue = 0;
10102let addrMode = PostInc;
10103let accessSize = HalfWordAccess;
10104let mayLoad = 1;
10105let Constraints = "$Rx32 = $Rx32in";
10106}
10107def L2_loadruh_zomap : HInst<
10108(outs IntRegs:$Rd32),
10109(ins IntRegs:$Rs32),
10110"$Rd32 = memuh($Rs32)",
10111tc_4222e6bf, TypeMAPPING> {
10112let hasNewValue = 1;
10113let opNewValue = 0;
10114let isPseudo = 1;
10115let isCodeGenOnly = 1;
10116}
10117def L2_loadruhgp : HInst<
10118(outs IntRegs:$Rd32),
10119(ins u31_1Imm:$Ii),
10120"$Rd32 = memuh(gp+#$Ii)",
10121tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
10122let Inst{24-21} = 0b1011;
10123let Inst{31-27} = 0b01001;
10124let hasNewValue = 1;
10125let opNewValue = 0;
10126let accessSize = HalfWordAccess;
10127let mayLoad = 1;
10128let Uses = [GP];
10129let BaseOpcode = "L4_loadruh_abs";
10130let isPredicable = 1;
10131let opExtendable = 1;
10132let isExtentSigned = 0;
10133let opExtentBits = 17;
10134let opExtentAlign = 1;
10135}
10136def L2_loadw_aq : HInst<
10137(outs IntRegs:$Rd32),
10138(ins IntRegs:$Rs32),
10139"$Rd32 = memw_aq($Rs32)",
10140tc_2471c1c8, TypeLD>, Enc_5e2823, Requires<[HasV68]> {
10141let Inst{13-5} = 0b001000000;
10142let Inst{31-21} = 0b10010010000;
10143let hasNewValue = 1;
10144let opNewValue = 0;
10145let accessSize = WordAccess;
10146let mayLoad = 1;
10147}
10148def L2_loadw_locked : HInst<
10149(outs IntRegs:$Rd32),
10150(ins IntRegs:$Rs32),
10151"$Rd32 = memw_locked($Rs32)",
10152tc_64b00d8a, TypeLD>, Enc_5e2823 {
10153let Inst{13-5} = 0b000000000;
10154let Inst{31-21} = 0b10010010000;
10155let hasNewValue = 1;
10156let opNewValue = 0;
10157let accessSize = WordAccess;
10158let mayLoad = 1;
10159let isSoloAX = 1;
10160}
10161def L2_ploadrbf_io : HInst<
10162(outs IntRegs:$Rd32),
10163(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10164"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
10165tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10166let Inst{13-13} = 0b0;
10167let Inst{31-21} = 0b01000101000;
10168let isPredicated = 1;
10169let isPredicatedFalse = 1;
10170let hasNewValue = 1;
10171let opNewValue = 0;
10172let addrMode = BaseImmOffset;
10173let accessSize = ByteAccess;
10174let mayLoad = 1;
10175let BaseOpcode = "L2_loadrb_io";
10176let CextOpcode = "L2_loadrb";
10177let isExtendable = 1;
10178let opExtendable = 3;
10179let isExtentSigned = 0;
10180let opExtentBits = 6;
10181let opExtentAlign = 0;
10182}
10183def L2_ploadrbf_pi : HInst<
10184(outs IntRegs:$Rd32, IntRegs:$Rx32),
10185(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10186"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
10187tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10188let Inst{13-11} = 0b101;
10189let Inst{31-21} = 0b10011011000;
10190let isPredicated = 1;
10191let isPredicatedFalse = 1;
10192let hasNewValue = 1;
10193let opNewValue = 0;
10194let addrMode = PostInc;
10195let accessSize = ByteAccess;
10196let mayLoad = 1;
10197let BaseOpcode = "L2_loadrb_pi";
10198let Constraints = "$Rx32 = $Rx32in";
10199}
10200def L2_ploadrbf_zomap : HInst<
10201(outs IntRegs:$Rd32),
10202(ins PredRegs:$Pt4, IntRegs:$Rs32),
10203"if (!$Pt4) $Rd32 = memb($Rs32)",
10204tc_fedb7e19, TypeMAPPING> {
10205let hasNewValue = 1;
10206let opNewValue = 0;
10207let isPseudo = 1;
10208let isCodeGenOnly = 1;
10209}
10210def L2_ploadrbfnew_io : HInst<
10211(outs IntRegs:$Rd32),
10212(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10213"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10214tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10215let Inst{13-13} = 0b0;
10216let Inst{31-21} = 0b01000111000;
10217let isPredicated = 1;
10218let isPredicatedFalse = 1;
10219let hasNewValue = 1;
10220let opNewValue = 0;
10221let addrMode = BaseImmOffset;
10222let accessSize = ByteAccess;
10223let isPredicatedNew = 1;
10224let mayLoad = 1;
10225let BaseOpcode = "L2_loadrb_io";
10226let CextOpcode = "L2_loadrb";
10227let isExtendable = 1;
10228let opExtendable = 3;
10229let isExtentSigned = 0;
10230let opExtentBits = 6;
10231let opExtentAlign = 0;
10232}
10233def L2_ploadrbfnew_pi : HInst<
10234(outs IntRegs:$Rd32, IntRegs:$Rx32),
10235(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10236"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10237tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10238let Inst{13-11} = 0b111;
10239let Inst{31-21} = 0b10011011000;
10240let isPredicated = 1;
10241let isPredicatedFalse = 1;
10242let hasNewValue = 1;
10243let opNewValue = 0;
10244let addrMode = PostInc;
10245let accessSize = ByteAccess;
10246let isPredicatedNew = 1;
10247let mayLoad = 1;
10248let BaseOpcode = "L2_loadrb_pi";
10249let Constraints = "$Rx32 = $Rx32in";
10250}
10251def L2_ploadrbfnew_zomap : HInst<
10252(outs IntRegs:$Rd32),
10253(ins PredRegs:$Pt4, IntRegs:$Rs32),
10254"if (!$Pt4.new) $Rd32 = memb($Rs32)",
10255tc_075c8dd8, TypeMAPPING> {
10256let hasNewValue = 1;
10257let opNewValue = 0;
10258let isPseudo = 1;
10259let isCodeGenOnly = 1;
10260}
10261def L2_ploadrbt_io : HInst<
10262(outs IntRegs:$Rd32),
10263(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10264"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
10265tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10266let Inst{13-13} = 0b0;
10267let Inst{31-21} = 0b01000001000;
10268let isPredicated = 1;
10269let hasNewValue = 1;
10270let opNewValue = 0;
10271let addrMode = BaseImmOffset;
10272let accessSize = ByteAccess;
10273let mayLoad = 1;
10274let BaseOpcode = "L2_loadrb_io";
10275let CextOpcode = "L2_loadrb";
10276let isExtendable = 1;
10277let opExtendable = 3;
10278let isExtentSigned = 0;
10279let opExtentBits = 6;
10280let opExtentAlign = 0;
10281}
10282def L2_ploadrbt_pi : HInst<
10283(outs IntRegs:$Rd32, IntRegs:$Rx32),
10284(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10285"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
10286tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10287let Inst{13-11} = 0b100;
10288let Inst{31-21} = 0b10011011000;
10289let isPredicated = 1;
10290let hasNewValue = 1;
10291let opNewValue = 0;
10292let addrMode = PostInc;
10293let accessSize = ByteAccess;
10294let mayLoad = 1;
10295let BaseOpcode = "L2_loadrb_pi";
10296let Constraints = "$Rx32 = $Rx32in";
10297}
10298def L2_ploadrbt_zomap : HInst<
10299(outs IntRegs:$Rd32),
10300(ins PredRegs:$Pt4, IntRegs:$Rs32),
10301"if ($Pt4) $Rd32 = memb($Rs32)",
10302tc_fedb7e19, TypeMAPPING> {
10303let hasNewValue = 1;
10304let opNewValue = 0;
10305let isPseudo = 1;
10306let isCodeGenOnly = 1;
10307}
10308def L2_ploadrbtnew_io : HInst<
10309(outs IntRegs:$Rd32),
10310(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10311"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10312tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10313let Inst{13-13} = 0b0;
10314let Inst{31-21} = 0b01000011000;
10315let isPredicated = 1;
10316let hasNewValue = 1;
10317let opNewValue = 0;
10318let addrMode = BaseImmOffset;
10319let accessSize = ByteAccess;
10320let isPredicatedNew = 1;
10321let mayLoad = 1;
10322let BaseOpcode = "L2_loadrb_io";
10323let CextOpcode = "L2_loadrb";
10324let isExtendable = 1;
10325let opExtendable = 3;
10326let isExtentSigned = 0;
10327let opExtentBits = 6;
10328let opExtentAlign = 0;
10329}
10330def L2_ploadrbtnew_pi : HInst<
10331(outs IntRegs:$Rd32, IntRegs:$Rx32),
10332(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10333"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10334tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10335let Inst{13-11} = 0b110;
10336let Inst{31-21} = 0b10011011000;
10337let isPredicated = 1;
10338let hasNewValue = 1;
10339let opNewValue = 0;
10340let addrMode = PostInc;
10341let accessSize = ByteAccess;
10342let isPredicatedNew = 1;
10343let mayLoad = 1;
10344let BaseOpcode = "L2_loadrb_pi";
10345let Constraints = "$Rx32 = $Rx32in";
10346}
10347def L2_ploadrbtnew_zomap : HInst<
10348(outs IntRegs:$Rd32),
10349(ins PredRegs:$Pt4, IntRegs:$Rs32),
10350"if ($Pt4.new) $Rd32 = memb($Rs32)",
10351tc_075c8dd8, TypeMAPPING> {
10352let hasNewValue = 1;
10353let opNewValue = 0;
10354let isPseudo = 1;
10355let isCodeGenOnly = 1;
10356}
10357def L2_ploadrdf_io : HInst<
10358(outs DoubleRegs:$Rdd32),
10359(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10360"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10361tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10362let Inst{13-13} = 0b0;
10363let Inst{31-21} = 0b01000101110;
10364let isPredicated = 1;
10365let isPredicatedFalse = 1;
10366let addrMode = BaseImmOffset;
10367let accessSize = DoubleWordAccess;
10368let mayLoad = 1;
10369let BaseOpcode = "L2_loadrd_io";
10370let CextOpcode = "L2_loadrd";
10371let isExtendable = 1;
10372let opExtendable = 3;
10373let isExtentSigned = 0;
10374let opExtentBits = 9;
10375let opExtentAlign = 3;
10376}
10377def L2_ploadrdf_pi : HInst<
10378(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10379(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10380"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10381tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10382let Inst{13-11} = 0b101;
10383let Inst{31-21} = 0b10011011110;
10384let isPredicated = 1;
10385let isPredicatedFalse = 1;
10386let addrMode = PostInc;
10387let accessSize = DoubleWordAccess;
10388let mayLoad = 1;
10389let BaseOpcode = "L2_loadrd_pi";
10390let Constraints = "$Rx32 = $Rx32in";
10391}
10392def L2_ploadrdf_zomap : HInst<
10393(outs DoubleRegs:$Rdd32),
10394(ins PredRegs:$Pt4, IntRegs:$Rs32),
10395"if (!$Pt4) $Rdd32 = memd($Rs32)",
10396tc_fedb7e19, TypeMAPPING> {
10397let isPseudo = 1;
10398let isCodeGenOnly = 1;
10399}
10400def L2_ploadrdfnew_io : HInst<
10401(outs DoubleRegs:$Rdd32),
10402(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10403"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10404tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10405let Inst{13-13} = 0b0;
10406let Inst{31-21} = 0b01000111110;
10407let isPredicated = 1;
10408let isPredicatedFalse = 1;
10409let addrMode = BaseImmOffset;
10410let accessSize = DoubleWordAccess;
10411let isPredicatedNew = 1;
10412let mayLoad = 1;
10413let BaseOpcode = "L2_loadrd_io";
10414let CextOpcode = "L2_loadrd";
10415let isExtendable = 1;
10416let opExtendable = 3;
10417let isExtentSigned = 0;
10418let opExtentBits = 9;
10419let opExtentAlign = 3;
10420}
10421def L2_ploadrdfnew_pi : HInst<
10422(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10423(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10424"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10425tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10426let Inst{13-11} = 0b111;
10427let Inst{31-21} = 0b10011011110;
10428let isPredicated = 1;
10429let isPredicatedFalse = 1;
10430let addrMode = PostInc;
10431let accessSize = DoubleWordAccess;
10432let isPredicatedNew = 1;
10433let mayLoad = 1;
10434let BaseOpcode = "L2_loadrd_pi";
10435let Constraints = "$Rx32 = $Rx32in";
10436}
10437def L2_ploadrdfnew_zomap : HInst<
10438(outs DoubleRegs:$Rdd32),
10439(ins PredRegs:$Pt4, IntRegs:$Rs32),
10440"if (!$Pt4.new) $Rdd32 = memd($Rs32)",
10441tc_075c8dd8, TypeMAPPING> {
10442let isPseudo = 1;
10443let isCodeGenOnly = 1;
10444}
10445def L2_ploadrdt_io : HInst<
10446(outs DoubleRegs:$Rdd32),
10447(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10448"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10449tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10450let Inst{13-13} = 0b0;
10451let Inst{31-21} = 0b01000001110;
10452let isPredicated = 1;
10453let addrMode = BaseImmOffset;
10454let accessSize = DoubleWordAccess;
10455let mayLoad = 1;
10456let BaseOpcode = "L2_loadrd_io";
10457let CextOpcode = "L2_loadrd";
10458let isExtendable = 1;
10459let opExtendable = 3;
10460let isExtentSigned = 0;
10461let opExtentBits = 9;
10462let opExtentAlign = 3;
10463}
10464def L2_ploadrdt_pi : HInst<
10465(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10466(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10467"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10468tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10469let Inst{13-11} = 0b100;
10470let Inst{31-21} = 0b10011011110;
10471let isPredicated = 1;
10472let addrMode = PostInc;
10473let accessSize = DoubleWordAccess;
10474let mayLoad = 1;
10475let BaseOpcode = "L2_loadrd_pi";
10476let Constraints = "$Rx32 = $Rx32in";
10477}
10478def L2_ploadrdt_zomap : HInst<
10479(outs DoubleRegs:$Rdd32),
10480(ins PredRegs:$Pt4, IntRegs:$Rs32),
10481"if ($Pt4) $Rdd32 = memd($Rs32)",
10482tc_fedb7e19, TypeMAPPING> {
10483let isPseudo = 1;
10484let isCodeGenOnly = 1;
10485}
10486def L2_ploadrdtnew_io : HInst<
10487(outs DoubleRegs:$Rdd32),
10488(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10489"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10490tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10491let Inst{13-13} = 0b0;
10492let Inst{31-21} = 0b01000011110;
10493let isPredicated = 1;
10494let addrMode = BaseImmOffset;
10495let accessSize = DoubleWordAccess;
10496let isPredicatedNew = 1;
10497let mayLoad = 1;
10498let BaseOpcode = "L2_loadrd_io";
10499let CextOpcode = "L2_loadrd";
10500let isExtendable = 1;
10501let opExtendable = 3;
10502let isExtentSigned = 0;
10503let opExtentBits = 9;
10504let opExtentAlign = 3;
10505}
10506def L2_ploadrdtnew_pi : HInst<
10507(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10508(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10509"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10510tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10511let Inst{13-11} = 0b110;
10512let Inst{31-21} = 0b10011011110;
10513let isPredicated = 1;
10514let addrMode = PostInc;
10515let accessSize = DoubleWordAccess;
10516let isPredicatedNew = 1;
10517let mayLoad = 1;
10518let BaseOpcode = "L2_loadrd_pi";
10519let Constraints = "$Rx32 = $Rx32in";
10520}
10521def L2_ploadrdtnew_zomap : HInst<
10522(outs DoubleRegs:$Rdd32),
10523(ins PredRegs:$Pt4, IntRegs:$Rs32),
10524"if ($Pt4.new) $Rdd32 = memd($Rs32)",
10525tc_075c8dd8, TypeMAPPING> {
10526let isPseudo = 1;
10527let isCodeGenOnly = 1;
10528}
10529def L2_ploadrhf_io : HInst<
10530(outs IntRegs:$Rd32),
10531(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10532"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
10533tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10534let Inst{13-13} = 0b0;
10535let Inst{31-21} = 0b01000101010;
10536let isPredicated = 1;
10537let isPredicatedFalse = 1;
10538let hasNewValue = 1;
10539let opNewValue = 0;
10540let addrMode = BaseImmOffset;
10541let accessSize = HalfWordAccess;
10542let mayLoad = 1;
10543let BaseOpcode = "L2_loadrh_io";
10544let CextOpcode = "L2_loadrh";
10545let isExtendable = 1;
10546let opExtendable = 3;
10547let isExtentSigned = 0;
10548let opExtentBits = 7;
10549let opExtentAlign = 1;
10550}
10551def L2_ploadrhf_pi : HInst<
10552(outs IntRegs:$Rd32, IntRegs:$Rx32),
10553(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10554"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
10555tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10556let Inst{13-11} = 0b101;
10557let Inst{31-21} = 0b10011011010;
10558let isPredicated = 1;
10559let isPredicatedFalse = 1;
10560let hasNewValue = 1;
10561let opNewValue = 0;
10562let addrMode = PostInc;
10563let accessSize = HalfWordAccess;
10564let mayLoad = 1;
10565let BaseOpcode = "L2_loadrh_pi";
10566let Constraints = "$Rx32 = $Rx32in";
10567}
10568def L2_ploadrhf_zomap : HInst<
10569(outs IntRegs:$Rd32),
10570(ins PredRegs:$Pt4, IntRegs:$Rs32),
10571"if (!$Pt4) $Rd32 = memh($Rs32)",
10572tc_fedb7e19, TypeMAPPING> {
10573let hasNewValue = 1;
10574let opNewValue = 0;
10575let isPseudo = 1;
10576let isCodeGenOnly = 1;
10577}
10578def L2_ploadrhfnew_io : HInst<
10579(outs IntRegs:$Rd32),
10580(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10581"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10582tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10583let Inst{13-13} = 0b0;
10584let Inst{31-21} = 0b01000111010;
10585let isPredicated = 1;
10586let isPredicatedFalse = 1;
10587let hasNewValue = 1;
10588let opNewValue = 0;
10589let addrMode = BaseImmOffset;
10590let accessSize = HalfWordAccess;
10591let isPredicatedNew = 1;
10592let mayLoad = 1;
10593let BaseOpcode = "L2_loadrh_io";
10594let CextOpcode = "L2_loadrh";
10595let isExtendable = 1;
10596let opExtendable = 3;
10597let isExtentSigned = 0;
10598let opExtentBits = 7;
10599let opExtentAlign = 1;
10600}
10601def L2_ploadrhfnew_pi : HInst<
10602(outs IntRegs:$Rd32, IntRegs:$Rx32),
10603(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10604"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10605tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10606let Inst{13-11} = 0b111;
10607let Inst{31-21} = 0b10011011010;
10608let isPredicated = 1;
10609let isPredicatedFalse = 1;
10610let hasNewValue = 1;
10611let opNewValue = 0;
10612let addrMode = PostInc;
10613let accessSize = HalfWordAccess;
10614let isPredicatedNew = 1;
10615let mayLoad = 1;
10616let BaseOpcode = "L2_loadrh_pi";
10617let Constraints = "$Rx32 = $Rx32in";
10618}
10619def L2_ploadrhfnew_zomap : HInst<
10620(outs IntRegs:$Rd32),
10621(ins PredRegs:$Pt4, IntRegs:$Rs32),
10622"if (!$Pt4.new) $Rd32 = memh($Rs32)",
10623tc_075c8dd8, TypeMAPPING> {
10624let hasNewValue = 1;
10625let opNewValue = 0;
10626let isPseudo = 1;
10627let isCodeGenOnly = 1;
10628}
10629def L2_ploadrht_io : HInst<
10630(outs IntRegs:$Rd32),
10631(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10632"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
10633tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10634let Inst{13-13} = 0b0;
10635let Inst{31-21} = 0b01000001010;
10636let isPredicated = 1;
10637let hasNewValue = 1;
10638let opNewValue = 0;
10639let addrMode = BaseImmOffset;
10640let accessSize = HalfWordAccess;
10641let mayLoad = 1;
10642let BaseOpcode = "L2_loadrh_io";
10643let CextOpcode = "L2_loadrh";
10644let isExtendable = 1;
10645let opExtendable = 3;
10646let isExtentSigned = 0;
10647let opExtentBits = 7;
10648let opExtentAlign = 1;
10649}
10650def L2_ploadrht_pi : HInst<
10651(outs IntRegs:$Rd32, IntRegs:$Rx32),
10652(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10653"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
10654tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10655let Inst{13-11} = 0b100;
10656let Inst{31-21} = 0b10011011010;
10657let isPredicated = 1;
10658let hasNewValue = 1;
10659let opNewValue = 0;
10660let addrMode = PostInc;
10661let accessSize = HalfWordAccess;
10662let mayLoad = 1;
10663let BaseOpcode = "L2_loadrh_pi";
10664let Constraints = "$Rx32 = $Rx32in";
10665}
10666def L2_ploadrht_zomap : HInst<
10667(outs IntRegs:$Rd32),
10668(ins PredRegs:$Pt4, IntRegs:$Rs32),
10669"if ($Pt4) $Rd32 = memh($Rs32)",
10670tc_fedb7e19, TypeMAPPING> {
10671let hasNewValue = 1;
10672let opNewValue = 0;
10673let isPseudo = 1;
10674let isCodeGenOnly = 1;
10675}
10676def L2_ploadrhtnew_io : HInst<
10677(outs IntRegs:$Rd32),
10678(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10679"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10680tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10681let Inst{13-13} = 0b0;
10682let Inst{31-21} = 0b01000011010;
10683let isPredicated = 1;
10684let hasNewValue = 1;
10685let opNewValue = 0;
10686let addrMode = BaseImmOffset;
10687let accessSize = HalfWordAccess;
10688let isPredicatedNew = 1;
10689let mayLoad = 1;
10690let BaseOpcode = "L2_loadrh_io";
10691let CextOpcode = "L2_loadrh";
10692let isExtendable = 1;
10693let opExtendable = 3;
10694let isExtentSigned = 0;
10695let opExtentBits = 7;
10696let opExtentAlign = 1;
10697}
10698def L2_ploadrhtnew_pi : HInst<
10699(outs IntRegs:$Rd32, IntRegs:$Rx32),
10700(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10701"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10702tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10703let Inst{13-11} = 0b110;
10704let Inst{31-21} = 0b10011011010;
10705let isPredicated = 1;
10706let hasNewValue = 1;
10707let opNewValue = 0;
10708let addrMode = PostInc;
10709let accessSize = HalfWordAccess;
10710let isPredicatedNew = 1;
10711let mayLoad = 1;
10712let BaseOpcode = "L2_loadrh_pi";
10713let Constraints = "$Rx32 = $Rx32in";
10714}
10715def L2_ploadrhtnew_zomap : HInst<
10716(outs IntRegs:$Rd32),
10717(ins PredRegs:$Pt4, IntRegs:$Rs32),
10718"if ($Pt4.new) $Rd32 = memh($Rs32)",
10719tc_075c8dd8, TypeMAPPING> {
10720let hasNewValue = 1;
10721let opNewValue = 0;
10722let isPseudo = 1;
10723let isCodeGenOnly = 1;
10724}
10725def L2_ploadrif_io : HInst<
10726(outs IntRegs:$Rd32),
10727(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10728"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
10729tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10730let Inst{13-13} = 0b0;
10731let Inst{31-21} = 0b01000101100;
10732let isPredicated = 1;
10733let isPredicatedFalse = 1;
10734let hasNewValue = 1;
10735let opNewValue = 0;
10736let addrMode = BaseImmOffset;
10737let accessSize = WordAccess;
10738let mayLoad = 1;
10739let BaseOpcode = "L2_loadri_io";
10740let CextOpcode = "L2_loadri";
10741let isExtendable = 1;
10742let opExtendable = 3;
10743let isExtentSigned = 0;
10744let opExtentBits = 8;
10745let opExtentAlign = 2;
10746}
10747def L2_ploadrif_pi : HInst<
10748(outs IntRegs:$Rd32, IntRegs:$Rx32),
10749(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10750"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
10751tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10752let Inst{13-11} = 0b101;
10753let Inst{31-21} = 0b10011011100;
10754let isPredicated = 1;
10755let isPredicatedFalse = 1;
10756let hasNewValue = 1;
10757let opNewValue = 0;
10758let addrMode = PostInc;
10759let accessSize = WordAccess;
10760let mayLoad = 1;
10761let BaseOpcode = "L2_loadri_pi";
10762let Constraints = "$Rx32 = $Rx32in";
10763}
10764def L2_ploadrif_zomap : HInst<
10765(outs IntRegs:$Rd32),
10766(ins PredRegs:$Pt4, IntRegs:$Rs32),
10767"if (!$Pt4) $Rd32 = memw($Rs32)",
10768tc_fedb7e19, TypeMAPPING> {
10769let hasNewValue = 1;
10770let opNewValue = 0;
10771let isPseudo = 1;
10772let isCodeGenOnly = 1;
10773}
10774def L2_ploadrifnew_io : HInst<
10775(outs IntRegs:$Rd32),
10776(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10777"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10778tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10779let Inst{13-13} = 0b0;
10780let Inst{31-21} = 0b01000111100;
10781let isPredicated = 1;
10782let isPredicatedFalse = 1;
10783let hasNewValue = 1;
10784let opNewValue = 0;
10785let addrMode = BaseImmOffset;
10786let accessSize = WordAccess;
10787let isPredicatedNew = 1;
10788let mayLoad = 1;
10789let BaseOpcode = "L2_loadri_io";
10790let CextOpcode = "L2_loadri";
10791let isExtendable = 1;
10792let opExtendable = 3;
10793let isExtentSigned = 0;
10794let opExtentBits = 8;
10795let opExtentAlign = 2;
10796}
10797def L2_ploadrifnew_pi : HInst<
10798(outs IntRegs:$Rd32, IntRegs:$Rx32),
10799(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10800"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10801tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10802let Inst{13-11} = 0b111;
10803let Inst{31-21} = 0b10011011100;
10804let isPredicated = 1;
10805let isPredicatedFalse = 1;
10806let hasNewValue = 1;
10807let opNewValue = 0;
10808let addrMode = PostInc;
10809let accessSize = WordAccess;
10810let isPredicatedNew = 1;
10811let mayLoad = 1;
10812let BaseOpcode = "L2_loadri_pi";
10813let Constraints = "$Rx32 = $Rx32in";
10814}
10815def L2_ploadrifnew_zomap : HInst<
10816(outs IntRegs:$Rd32),
10817(ins PredRegs:$Pt4, IntRegs:$Rs32),
10818"if (!$Pt4.new) $Rd32 = memw($Rs32)",
10819tc_075c8dd8, TypeMAPPING> {
10820let hasNewValue = 1;
10821let opNewValue = 0;
10822let isPseudo = 1;
10823let isCodeGenOnly = 1;
10824}
10825def L2_ploadrit_io : HInst<
10826(outs IntRegs:$Rd32),
10827(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10828"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
10829tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10830let Inst{13-13} = 0b0;
10831let Inst{31-21} = 0b01000001100;
10832let isPredicated = 1;
10833let hasNewValue = 1;
10834let opNewValue = 0;
10835let addrMode = BaseImmOffset;
10836let accessSize = WordAccess;
10837let mayLoad = 1;
10838let BaseOpcode = "L2_loadri_io";
10839let CextOpcode = "L2_loadri";
10840let isExtendable = 1;
10841let opExtendable = 3;
10842let isExtentSigned = 0;
10843let opExtentBits = 8;
10844let opExtentAlign = 2;
10845}
10846def L2_ploadrit_pi : HInst<
10847(outs IntRegs:$Rd32, IntRegs:$Rx32),
10848(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10849"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
10850tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10851let Inst{13-11} = 0b100;
10852let Inst{31-21} = 0b10011011100;
10853let isPredicated = 1;
10854let hasNewValue = 1;
10855let opNewValue = 0;
10856let addrMode = PostInc;
10857let accessSize = WordAccess;
10858let mayLoad = 1;
10859let BaseOpcode = "L2_loadri_pi";
10860let Constraints = "$Rx32 = $Rx32in";
10861}
10862def L2_ploadrit_zomap : HInst<
10863(outs IntRegs:$Rd32),
10864(ins PredRegs:$Pt4, IntRegs:$Rs32),
10865"if ($Pt4) $Rd32 = memw($Rs32)",
10866tc_fedb7e19, TypeMAPPING> {
10867let hasNewValue = 1;
10868let opNewValue = 0;
10869let isPseudo = 1;
10870let isCodeGenOnly = 1;
10871}
10872def L2_ploadritnew_io : HInst<
10873(outs IntRegs:$Rd32),
10874(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10875"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10876tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10877let Inst{13-13} = 0b0;
10878let Inst{31-21} = 0b01000011100;
10879let isPredicated = 1;
10880let hasNewValue = 1;
10881let opNewValue = 0;
10882let addrMode = BaseImmOffset;
10883let accessSize = WordAccess;
10884let isPredicatedNew = 1;
10885let mayLoad = 1;
10886let BaseOpcode = "L2_loadri_io";
10887let CextOpcode = "L2_loadri";
10888let isExtendable = 1;
10889let opExtendable = 3;
10890let isExtentSigned = 0;
10891let opExtentBits = 8;
10892let opExtentAlign = 2;
10893}
10894def L2_ploadritnew_pi : HInst<
10895(outs IntRegs:$Rd32, IntRegs:$Rx32),
10896(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10897"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10898tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10899let Inst{13-11} = 0b110;
10900let Inst{31-21} = 0b10011011100;
10901let isPredicated = 1;
10902let hasNewValue = 1;
10903let opNewValue = 0;
10904let addrMode = PostInc;
10905let accessSize = WordAccess;
10906let isPredicatedNew = 1;
10907let mayLoad = 1;
10908let BaseOpcode = "L2_loadri_pi";
10909let Constraints = "$Rx32 = $Rx32in";
10910}
10911def L2_ploadritnew_zomap : HInst<
10912(outs IntRegs:$Rd32),
10913(ins PredRegs:$Pt4, IntRegs:$Rs32),
10914"if ($Pt4.new) $Rd32 = memw($Rs32)",
10915tc_075c8dd8, TypeMAPPING> {
10916let hasNewValue = 1;
10917let opNewValue = 0;
10918let isPseudo = 1;
10919let isCodeGenOnly = 1;
10920}
10921def L2_ploadrubf_io : HInst<
10922(outs IntRegs:$Rd32),
10923(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10924"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
10925tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10926let Inst{13-13} = 0b0;
10927let Inst{31-21} = 0b01000101001;
10928let isPredicated = 1;
10929let isPredicatedFalse = 1;
10930let hasNewValue = 1;
10931let opNewValue = 0;
10932let addrMode = BaseImmOffset;
10933let accessSize = ByteAccess;
10934let mayLoad = 1;
10935let BaseOpcode = "L2_loadrub_io";
10936let CextOpcode = "L2_loadrub";
10937let isExtendable = 1;
10938let opExtendable = 3;
10939let isExtentSigned = 0;
10940let opExtentBits = 6;
10941let opExtentAlign = 0;
10942}
10943def L2_ploadrubf_pi : HInst<
10944(outs IntRegs:$Rd32, IntRegs:$Rx32),
10945(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10946"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
10947tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10948let Inst{13-11} = 0b101;
10949let Inst{31-21} = 0b10011011001;
10950let isPredicated = 1;
10951let isPredicatedFalse = 1;
10952let hasNewValue = 1;
10953let opNewValue = 0;
10954let addrMode = PostInc;
10955let accessSize = ByteAccess;
10956let mayLoad = 1;
10957let BaseOpcode = "L2_loadrub_pi";
10958let Constraints = "$Rx32 = $Rx32in";
10959}
10960def L2_ploadrubf_zomap : HInst<
10961(outs IntRegs:$Rd32),
10962(ins PredRegs:$Pt4, IntRegs:$Rs32),
10963"if (!$Pt4) $Rd32 = memub($Rs32)",
10964tc_fedb7e19, TypeMAPPING> {
10965let hasNewValue = 1;
10966let opNewValue = 0;
10967let isPseudo = 1;
10968let isCodeGenOnly = 1;
10969}
10970def L2_ploadrubfnew_io : HInst<
10971(outs IntRegs:$Rd32),
10972(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10973"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
10974tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10975let Inst{13-13} = 0b0;
10976let Inst{31-21} = 0b01000111001;
10977let isPredicated = 1;
10978let isPredicatedFalse = 1;
10979let hasNewValue = 1;
10980let opNewValue = 0;
10981let addrMode = BaseImmOffset;
10982let accessSize = ByteAccess;
10983let isPredicatedNew = 1;
10984let mayLoad = 1;
10985let BaseOpcode = "L2_loadrub_io";
10986let CextOpcode = "L2_loadrub";
10987let isExtendable = 1;
10988let opExtendable = 3;
10989let isExtentSigned = 0;
10990let opExtentBits = 6;
10991let opExtentAlign = 0;
10992}
10993def L2_ploadrubfnew_pi : HInst<
10994(outs IntRegs:$Rd32, IntRegs:$Rx32),
10995(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10996"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
10997tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10998let Inst{13-11} = 0b111;
10999let Inst{31-21} = 0b10011011001;
11000let isPredicated = 1;
11001let isPredicatedFalse = 1;
11002let hasNewValue = 1;
11003let opNewValue = 0;
11004let addrMode = PostInc;
11005let accessSize = ByteAccess;
11006let isPredicatedNew = 1;
11007let mayLoad = 1;
11008let BaseOpcode = "L2_loadrub_pi";
11009let Constraints = "$Rx32 = $Rx32in";
11010}
11011def L2_ploadrubfnew_zomap : HInst<
11012(outs IntRegs:$Rd32),
11013(ins PredRegs:$Pt4, IntRegs:$Rs32),
11014"if (!$Pt4.new) $Rd32 = memub($Rs32)",
11015tc_075c8dd8, TypeMAPPING> {
11016let hasNewValue = 1;
11017let opNewValue = 0;
11018let isPseudo = 1;
11019let isCodeGenOnly = 1;
11020}
11021def L2_ploadrubt_io : HInst<
11022(outs IntRegs:$Rd32),
11023(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11024"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
11025tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11026let Inst{13-13} = 0b0;
11027let Inst{31-21} = 0b01000001001;
11028let isPredicated = 1;
11029let hasNewValue = 1;
11030let opNewValue = 0;
11031let addrMode = BaseImmOffset;
11032let accessSize = ByteAccess;
11033let mayLoad = 1;
11034let BaseOpcode = "L2_loadrub_io";
11035let CextOpcode = "L2_loadrub";
11036let isExtendable = 1;
11037let opExtendable = 3;
11038let isExtentSigned = 0;
11039let opExtentBits = 6;
11040let opExtentAlign = 0;
11041}
11042def L2_ploadrubt_pi : HInst<
11043(outs IntRegs:$Rd32, IntRegs:$Rx32),
11044(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11045"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
11046tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
11047let Inst{13-11} = 0b100;
11048let Inst{31-21} = 0b10011011001;
11049let isPredicated = 1;
11050let hasNewValue = 1;
11051let opNewValue = 0;
11052let addrMode = PostInc;
11053let accessSize = ByteAccess;
11054let mayLoad = 1;
11055let BaseOpcode = "L2_loadrub_pi";
11056let Constraints = "$Rx32 = $Rx32in";
11057}
11058def L2_ploadrubt_zomap : HInst<
11059(outs IntRegs:$Rd32),
11060(ins PredRegs:$Pt4, IntRegs:$Rs32),
11061"if ($Pt4) $Rd32 = memub($Rs32)",
11062tc_fedb7e19, TypeMAPPING> {
11063let hasNewValue = 1;
11064let opNewValue = 0;
11065let isPseudo = 1;
11066let isCodeGenOnly = 1;
11067}
11068def L2_ploadrubtnew_io : HInst<
11069(outs IntRegs:$Rd32),
11070(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11071"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
11072tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11073let Inst{13-13} = 0b0;
11074let Inst{31-21} = 0b01000011001;
11075let isPredicated = 1;
11076let hasNewValue = 1;
11077let opNewValue = 0;
11078let addrMode = BaseImmOffset;
11079let accessSize = ByteAccess;
11080let isPredicatedNew = 1;
11081let mayLoad = 1;
11082let BaseOpcode = "L2_loadrub_io";
11083let CextOpcode = "L2_loadrub";
11084let isExtendable = 1;
11085let opExtendable = 3;
11086let isExtentSigned = 0;
11087let opExtentBits = 6;
11088let opExtentAlign = 0;
11089}
11090def L2_ploadrubtnew_pi : HInst<
11091(outs IntRegs:$Rd32, IntRegs:$Rx32),
11092(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11093"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
11094tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
11095let Inst{13-11} = 0b110;
11096let Inst{31-21} = 0b10011011001;
11097let isPredicated = 1;
11098let hasNewValue = 1;
11099let opNewValue = 0;
11100let addrMode = PostInc;
11101let accessSize = ByteAccess;
11102let isPredicatedNew = 1;
11103let mayLoad = 1;
11104let BaseOpcode = "L2_loadrub_pi";
11105let Constraints = "$Rx32 = $Rx32in";
11106}
11107def L2_ploadrubtnew_zomap : HInst<
11108(outs IntRegs:$Rd32),
11109(ins PredRegs:$Pt4, IntRegs:$Rs32),
11110"if ($Pt4.new) $Rd32 = memub($Rs32)",
11111tc_075c8dd8, TypeMAPPING> {
11112let hasNewValue = 1;
11113let opNewValue = 0;
11114let isPseudo = 1;
11115let isCodeGenOnly = 1;
11116}
11117def L2_ploadruhf_io : HInst<
11118(outs IntRegs:$Rd32),
11119(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11120"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11121tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11122let Inst{13-13} = 0b0;
11123let Inst{31-21} = 0b01000101011;
11124let isPredicated = 1;
11125let isPredicatedFalse = 1;
11126let hasNewValue = 1;
11127let opNewValue = 0;
11128let addrMode = BaseImmOffset;
11129let accessSize = HalfWordAccess;
11130let mayLoad = 1;
11131let BaseOpcode = "L2_loadruh_io";
11132let CextOpcode = "L2_loadruh";
11133let isExtendable = 1;
11134let opExtendable = 3;
11135let isExtentSigned = 0;
11136let opExtentBits = 7;
11137let opExtentAlign = 1;
11138}
11139def L2_ploadruhf_pi : HInst<
11140(outs IntRegs:$Rd32, IntRegs:$Rx32),
11141(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11142"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11143tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11144let Inst{13-11} = 0b101;
11145let Inst{31-21} = 0b10011011011;
11146let isPredicated = 1;
11147let isPredicatedFalse = 1;
11148let hasNewValue = 1;
11149let opNewValue = 0;
11150let addrMode = PostInc;
11151let accessSize = HalfWordAccess;
11152let mayLoad = 1;
11153let BaseOpcode = "L2_loadruh_pi";
11154let Constraints = "$Rx32 = $Rx32in";
11155}
11156def L2_ploadruhf_zomap : HInst<
11157(outs IntRegs:$Rd32),
11158(ins PredRegs:$Pt4, IntRegs:$Rs32),
11159"if (!$Pt4) $Rd32 = memuh($Rs32)",
11160tc_fedb7e19, TypeMAPPING> {
11161let hasNewValue = 1;
11162let opNewValue = 0;
11163let isPseudo = 1;
11164let isCodeGenOnly = 1;
11165}
11166def L2_ploadruhfnew_io : HInst<
11167(outs IntRegs:$Rd32),
11168(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11169"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11170tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11171let Inst{13-13} = 0b0;
11172let Inst{31-21} = 0b01000111011;
11173let isPredicated = 1;
11174let isPredicatedFalse = 1;
11175let hasNewValue = 1;
11176let opNewValue = 0;
11177let addrMode = BaseImmOffset;
11178let accessSize = HalfWordAccess;
11179let isPredicatedNew = 1;
11180let mayLoad = 1;
11181let BaseOpcode = "L2_loadruh_io";
11182let CextOpcode = "L2_loadruh";
11183let isExtendable = 1;
11184let opExtendable = 3;
11185let isExtentSigned = 0;
11186let opExtentBits = 7;
11187let opExtentAlign = 1;
11188}
11189def L2_ploadruhfnew_pi : HInst<
11190(outs IntRegs:$Rd32, IntRegs:$Rx32),
11191(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11192"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11193tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11194let Inst{13-11} = 0b111;
11195let Inst{31-21} = 0b10011011011;
11196let isPredicated = 1;
11197let isPredicatedFalse = 1;
11198let hasNewValue = 1;
11199let opNewValue = 0;
11200let addrMode = PostInc;
11201let accessSize = HalfWordAccess;
11202let isPredicatedNew = 1;
11203let mayLoad = 1;
11204let BaseOpcode = "L2_loadruh_pi";
11205let Constraints = "$Rx32 = $Rx32in";
11206}
11207def L2_ploadruhfnew_zomap : HInst<
11208(outs IntRegs:$Rd32),
11209(ins PredRegs:$Pt4, IntRegs:$Rs32),
11210"if (!$Pt4.new) $Rd32 = memuh($Rs32)",
11211tc_075c8dd8, TypeMAPPING> {
11212let hasNewValue = 1;
11213let opNewValue = 0;
11214let isPseudo = 1;
11215let isCodeGenOnly = 1;
11216}
11217def L2_ploadruht_io : HInst<
11218(outs IntRegs:$Rd32),
11219(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11220"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11221tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11222let Inst{13-13} = 0b0;
11223let Inst{31-21} = 0b01000001011;
11224let isPredicated = 1;
11225let hasNewValue = 1;
11226let opNewValue = 0;
11227let addrMode = BaseImmOffset;
11228let accessSize = HalfWordAccess;
11229let mayLoad = 1;
11230let BaseOpcode = "L2_loadruh_io";
11231let CextOpcode = "L2_loadruh";
11232let isExtendable = 1;
11233let opExtendable = 3;
11234let isExtentSigned = 0;
11235let opExtentBits = 7;
11236let opExtentAlign = 1;
11237}
11238def L2_ploadruht_pi : HInst<
11239(outs IntRegs:$Rd32, IntRegs:$Rx32),
11240(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11241"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11242tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11243let Inst{13-11} = 0b100;
11244let Inst{31-21} = 0b10011011011;
11245let isPredicated = 1;
11246let hasNewValue = 1;
11247let opNewValue = 0;
11248let addrMode = PostInc;
11249let accessSize = HalfWordAccess;
11250let mayLoad = 1;
11251let BaseOpcode = "L2_loadruh_pi";
11252let Constraints = "$Rx32 = $Rx32in";
11253}
11254def L2_ploadruht_zomap : HInst<
11255(outs IntRegs:$Rd32),
11256(ins PredRegs:$Pt4, IntRegs:$Rs32),
11257"if ($Pt4) $Rd32 = memuh($Rs32)",
11258tc_fedb7e19, TypeMAPPING> {
11259let hasNewValue = 1;
11260let opNewValue = 0;
11261let isPseudo = 1;
11262let isCodeGenOnly = 1;
11263}
11264def L2_ploadruhtnew_io : HInst<
11265(outs IntRegs:$Rd32),
11266(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11267"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11268tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11269let Inst{13-13} = 0b0;
11270let Inst{31-21} = 0b01000011011;
11271let isPredicated = 1;
11272let hasNewValue = 1;
11273let opNewValue = 0;
11274let addrMode = BaseImmOffset;
11275let accessSize = HalfWordAccess;
11276let isPredicatedNew = 1;
11277let mayLoad = 1;
11278let BaseOpcode = "L2_loadruh_io";
11279let CextOpcode = "L2_loadruh";
11280let isExtendable = 1;
11281let opExtendable = 3;
11282let isExtentSigned = 0;
11283let opExtentBits = 7;
11284let opExtentAlign = 1;
11285}
11286def L2_ploadruhtnew_pi : HInst<
11287(outs IntRegs:$Rd32, IntRegs:$Rx32),
11288(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11289"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11290tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11291let Inst{13-11} = 0b110;
11292let Inst{31-21} = 0b10011011011;
11293let isPredicated = 1;
11294let hasNewValue = 1;
11295let opNewValue = 0;
11296let addrMode = PostInc;
11297let accessSize = HalfWordAccess;
11298let isPredicatedNew = 1;
11299let mayLoad = 1;
11300let BaseOpcode = "L2_loadruh_pi";
11301let Constraints = "$Rx32 = $Rx32in";
11302}
11303def L2_ploadruhtnew_zomap : HInst<
11304(outs IntRegs:$Rd32),
11305(ins PredRegs:$Pt4, IntRegs:$Rs32),
11306"if ($Pt4.new) $Rd32 = memuh($Rs32)",
11307tc_075c8dd8, TypeMAPPING> {
11308let hasNewValue = 1;
11309let opNewValue = 0;
11310let isPseudo = 1;
11311let isCodeGenOnly = 1;
11312}
11313def L4_add_memopb_io : HInst<
11314(outs),
11315(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11316"memb($Rs32+#$Ii) += $Rt32",
11317tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11318let Inst{6-5} = 0b00;
11319let Inst{13-13} = 0b0;
11320let Inst{31-21} = 0b00111110000;
11321let addrMode = BaseImmOffset;
11322let accessSize = ByteAccess;
11323let mayLoad = 1;
11324let isRestrictNoSlot1Store = 1;
11325let mayStore = 1;
11326let isExtendable = 1;
11327let opExtendable = 1;
11328let isExtentSigned = 0;
11329let opExtentBits = 6;
11330let opExtentAlign = 0;
11331}
11332def L4_add_memopb_zomap : HInst<
11333(outs),
11334(ins IntRegs:$Rs32, IntRegs:$Rt32),
11335"memb($Rs32) += $Rt32",
11336tc_9bcfb2ee, TypeMAPPING> {
11337let isPseudo = 1;
11338let isCodeGenOnly = 1;
11339}
11340def L4_add_memoph_io : HInst<
11341(outs),
11342(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11343"memh($Rs32+#$Ii) += $Rt32",
11344tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11345let Inst{6-5} = 0b00;
11346let Inst{13-13} = 0b0;
11347let Inst{31-21} = 0b00111110001;
11348let addrMode = BaseImmOffset;
11349let accessSize = HalfWordAccess;
11350let mayLoad = 1;
11351let isRestrictNoSlot1Store = 1;
11352let mayStore = 1;
11353let isExtendable = 1;
11354let opExtendable = 1;
11355let isExtentSigned = 0;
11356let opExtentBits = 7;
11357let opExtentAlign = 1;
11358}
11359def L4_add_memoph_zomap : HInst<
11360(outs),
11361(ins IntRegs:$Rs32, IntRegs:$Rt32),
11362"memh($Rs32) += $Rt32",
11363tc_9bcfb2ee, TypeMAPPING> {
11364let isPseudo = 1;
11365let isCodeGenOnly = 1;
11366}
11367def L4_add_memopw_io : HInst<
11368(outs),
11369(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11370"memw($Rs32+#$Ii) += $Rt32",
11371tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11372let Inst{6-5} = 0b00;
11373let Inst{13-13} = 0b0;
11374let Inst{31-21} = 0b00111110010;
11375let addrMode = BaseImmOffset;
11376let accessSize = WordAccess;
11377let mayLoad = 1;
11378let isRestrictNoSlot1Store = 1;
11379let mayStore = 1;
11380let isExtendable = 1;
11381let opExtendable = 1;
11382let isExtentSigned = 0;
11383let opExtentBits = 8;
11384let opExtentAlign = 2;
11385}
11386def L4_add_memopw_zomap : HInst<
11387(outs),
11388(ins IntRegs:$Rs32, IntRegs:$Rt32),
11389"memw($Rs32) += $Rt32",
11390tc_9bcfb2ee, TypeMAPPING> {
11391let isPseudo = 1;
11392let isCodeGenOnly = 1;
11393}
11394def L4_and_memopb_io : HInst<
11395(outs),
11396(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11397"memb($Rs32+#$Ii) &= $Rt32",
11398tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11399let Inst{6-5} = 0b10;
11400let Inst{13-13} = 0b0;
11401let Inst{31-21} = 0b00111110000;
11402let addrMode = BaseImmOffset;
11403let accessSize = ByteAccess;
11404let mayLoad = 1;
11405let isRestrictNoSlot1Store = 1;
11406let mayStore = 1;
11407let isExtendable = 1;
11408let opExtendable = 1;
11409let isExtentSigned = 0;
11410let opExtentBits = 6;
11411let opExtentAlign = 0;
11412}
11413def L4_and_memopb_zomap : HInst<
11414(outs),
11415(ins IntRegs:$Rs32, IntRegs:$Rt32),
11416"memb($Rs32) &= $Rt32",
11417tc_9bcfb2ee, TypeMAPPING> {
11418let isPseudo = 1;
11419let isCodeGenOnly = 1;
11420}
11421def L4_and_memoph_io : HInst<
11422(outs),
11423(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11424"memh($Rs32+#$Ii) &= $Rt32",
11425tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11426let Inst{6-5} = 0b10;
11427let Inst{13-13} = 0b0;
11428let Inst{31-21} = 0b00111110001;
11429let addrMode = BaseImmOffset;
11430let accessSize = HalfWordAccess;
11431let mayLoad = 1;
11432let isRestrictNoSlot1Store = 1;
11433let mayStore = 1;
11434let isExtendable = 1;
11435let opExtendable = 1;
11436let isExtentSigned = 0;
11437let opExtentBits = 7;
11438let opExtentAlign = 1;
11439}
11440def L4_and_memoph_zomap : HInst<
11441(outs),
11442(ins IntRegs:$Rs32, IntRegs:$Rt32),
11443"memh($Rs32) &= $Rt32",
11444tc_9bcfb2ee, TypeMAPPING> {
11445let isPseudo = 1;
11446let isCodeGenOnly = 1;
11447}
11448def L4_and_memopw_io : HInst<
11449(outs),
11450(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11451"memw($Rs32+#$Ii) &= $Rt32",
11452tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11453let Inst{6-5} = 0b10;
11454let Inst{13-13} = 0b0;
11455let Inst{31-21} = 0b00111110010;
11456let addrMode = BaseImmOffset;
11457let accessSize = WordAccess;
11458let mayLoad = 1;
11459let isRestrictNoSlot1Store = 1;
11460let mayStore = 1;
11461let isExtendable = 1;
11462let opExtendable = 1;
11463let isExtentSigned = 0;
11464let opExtentBits = 8;
11465let opExtentAlign = 2;
11466}
11467def L4_and_memopw_zomap : HInst<
11468(outs),
11469(ins IntRegs:$Rs32, IntRegs:$Rt32),
11470"memw($Rs32) &= $Rt32",
11471tc_9bcfb2ee, TypeMAPPING> {
11472let isPseudo = 1;
11473let isCodeGenOnly = 1;
11474}
11475def L4_iadd_memopb_io : HInst<
11476(outs),
11477(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11478"memb($Rs32+#$Ii) += #$II",
11479tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11480let Inst{6-5} = 0b00;
11481let Inst{13-13} = 0b0;
11482let Inst{31-21} = 0b00111111000;
11483let addrMode = BaseImmOffset;
11484let accessSize = ByteAccess;
11485let mayLoad = 1;
11486let isRestrictNoSlot1Store = 1;
11487let mayStore = 1;
11488let isExtendable = 1;
11489let opExtendable = 1;
11490let isExtentSigned = 0;
11491let opExtentBits = 6;
11492let opExtentAlign = 0;
11493}
11494def L4_iadd_memopb_zomap : HInst<
11495(outs),
11496(ins IntRegs:$Rs32, u5_0Imm:$II),
11497"memb($Rs32) += #$II",
11498tc_158aa3f7, TypeMAPPING> {
11499let isPseudo = 1;
11500let isCodeGenOnly = 1;
11501}
11502def L4_iadd_memoph_io : HInst<
11503(outs),
11504(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11505"memh($Rs32+#$Ii) += #$II",
11506tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11507let Inst{6-5} = 0b00;
11508let Inst{13-13} = 0b0;
11509let Inst{31-21} = 0b00111111001;
11510let addrMode = BaseImmOffset;
11511let accessSize = HalfWordAccess;
11512let mayLoad = 1;
11513let isRestrictNoSlot1Store = 1;
11514let mayStore = 1;
11515let isExtendable = 1;
11516let opExtendable = 1;
11517let isExtentSigned = 0;
11518let opExtentBits = 7;
11519let opExtentAlign = 1;
11520}
11521def L4_iadd_memoph_zomap : HInst<
11522(outs),
11523(ins IntRegs:$Rs32, u5_0Imm:$II),
11524"memh($Rs32) += #$II",
11525tc_158aa3f7, TypeMAPPING> {
11526let isPseudo = 1;
11527let isCodeGenOnly = 1;
11528}
11529def L4_iadd_memopw_io : HInst<
11530(outs),
11531(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11532"memw($Rs32+#$Ii) += #$II",
11533tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11534let Inst{6-5} = 0b00;
11535let Inst{13-13} = 0b0;
11536let Inst{31-21} = 0b00111111010;
11537let addrMode = BaseImmOffset;
11538let accessSize = WordAccess;
11539let mayLoad = 1;
11540let isRestrictNoSlot1Store = 1;
11541let mayStore = 1;
11542let isExtendable = 1;
11543let opExtendable = 1;
11544let isExtentSigned = 0;
11545let opExtentBits = 8;
11546let opExtentAlign = 2;
11547}
11548def L4_iadd_memopw_zomap : HInst<
11549(outs),
11550(ins IntRegs:$Rs32, u5_0Imm:$II),
11551"memw($Rs32) += #$II",
11552tc_158aa3f7, TypeMAPPING> {
11553let isPseudo = 1;
11554let isCodeGenOnly = 1;
11555}
11556def L4_iand_memopb_io : HInst<
11557(outs),
11558(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11559"memb($Rs32+#$Ii) = clrbit(#$II)",
11560tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11561let Inst{6-5} = 0b10;
11562let Inst{13-13} = 0b0;
11563let Inst{31-21} = 0b00111111000;
11564let addrMode = BaseImmOffset;
11565let accessSize = ByteAccess;
11566let mayLoad = 1;
11567let isRestrictNoSlot1Store = 1;
11568let mayStore = 1;
11569let isExtendable = 1;
11570let opExtendable = 1;
11571let isExtentSigned = 0;
11572let opExtentBits = 6;
11573let opExtentAlign = 0;
11574}
11575def L4_iand_memopb_zomap : HInst<
11576(outs),
11577(ins IntRegs:$Rs32, u5_0Imm:$II),
11578"memb($Rs32) = clrbit(#$II)",
11579tc_158aa3f7, TypeMAPPING> {
11580let isPseudo = 1;
11581let isCodeGenOnly = 1;
11582}
11583def L4_iand_memoph_io : HInst<
11584(outs),
11585(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11586"memh($Rs32+#$Ii) = clrbit(#$II)",
11587tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11588let Inst{6-5} = 0b10;
11589let Inst{13-13} = 0b0;
11590let Inst{31-21} = 0b00111111001;
11591let addrMode = BaseImmOffset;
11592let accessSize = HalfWordAccess;
11593let mayLoad = 1;
11594let isRestrictNoSlot1Store = 1;
11595let mayStore = 1;
11596let isExtendable = 1;
11597let opExtendable = 1;
11598let isExtentSigned = 0;
11599let opExtentBits = 7;
11600let opExtentAlign = 1;
11601}
11602def L4_iand_memoph_zomap : HInst<
11603(outs),
11604(ins IntRegs:$Rs32, u5_0Imm:$II),
11605"memh($Rs32) = clrbit(#$II)",
11606tc_158aa3f7, TypeMAPPING> {
11607let isPseudo = 1;
11608let isCodeGenOnly = 1;
11609}
11610def L4_iand_memopw_io : HInst<
11611(outs),
11612(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11613"memw($Rs32+#$Ii) = clrbit(#$II)",
11614tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11615let Inst{6-5} = 0b10;
11616let Inst{13-13} = 0b0;
11617let Inst{31-21} = 0b00111111010;
11618let addrMode = BaseImmOffset;
11619let accessSize = WordAccess;
11620let mayLoad = 1;
11621let isRestrictNoSlot1Store = 1;
11622let mayStore = 1;
11623let isExtendable = 1;
11624let opExtendable = 1;
11625let isExtentSigned = 0;
11626let opExtentBits = 8;
11627let opExtentAlign = 2;
11628}
11629def L4_iand_memopw_zomap : HInst<
11630(outs),
11631(ins IntRegs:$Rs32, u5_0Imm:$II),
11632"memw($Rs32) = clrbit(#$II)",
11633tc_158aa3f7, TypeMAPPING> {
11634let isPseudo = 1;
11635let isCodeGenOnly = 1;
11636}
11637def L4_ior_memopb_io : HInst<
11638(outs),
11639(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11640"memb($Rs32+#$Ii) = setbit(#$II)",
11641tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11642let Inst{6-5} = 0b11;
11643let Inst{13-13} = 0b0;
11644let Inst{31-21} = 0b00111111000;
11645let addrMode = BaseImmOffset;
11646let accessSize = ByteAccess;
11647let mayLoad = 1;
11648let isRestrictNoSlot1Store = 1;
11649let mayStore = 1;
11650let isExtendable = 1;
11651let opExtendable = 1;
11652let isExtentSigned = 0;
11653let opExtentBits = 6;
11654let opExtentAlign = 0;
11655}
11656def L4_ior_memopb_zomap : HInst<
11657(outs),
11658(ins IntRegs:$Rs32, u5_0Imm:$II),
11659"memb($Rs32) = setbit(#$II)",
11660tc_158aa3f7, TypeMAPPING> {
11661let isPseudo = 1;
11662let isCodeGenOnly = 1;
11663}
11664def L4_ior_memoph_io : HInst<
11665(outs),
11666(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11667"memh($Rs32+#$Ii) = setbit(#$II)",
11668tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11669let Inst{6-5} = 0b11;
11670let Inst{13-13} = 0b0;
11671let Inst{31-21} = 0b00111111001;
11672let addrMode = BaseImmOffset;
11673let accessSize = HalfWordAccess;
11674let mayLoad = 1;
11675let isRestrictNoSlot1Store = 1;
11676let mayStore = 1;
11677let isExtendable = 1;
11678let opExtendable = 1;
11679let isExtentSigned = 0;
11680let opExtentBits = 7;
11681let opExtentAlign = 1;
11682}
11683def L4_ior_memoph_zomap : HInst<
11684(outs),
11685(ins IntRegs:$Rs32, u5_0Imm:$II),
11686"memh($Rs32) = setbit(#$II)",
11687tc_158aa3f7, TypeMAPPING> {
11688let isPseudo = 1;
11689let isCodeGenOnly = 1;
11690}
11691def L4_ior_memopw_io : HInst<
11692(outs),
11693(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11694"memw($Rs32+#$Ii) = setbit(#$II)",
11695tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11696let Inst{6-5} = 0b11;
11697let Inst{13-13} = 0b0;
11698let Inst{31-21} = 0b00111111010;
11699let addrMode = BaseImmOffset;
11700let accessSize = WordAccess;
11701let mayLoad = 1;
11702let isRestrictNoSlot1Store = 1;
11703let mayStore = 1;
11704let isExtendable = 1;
11705let opExtendable = 1;
11706let isExtentSigned = 0;
11707let opExtentBits = 8;
11708let opExtentAlign = 2;
11709}
11710def L4_ior_memopw_zomap : HInst<
11711(outs),
11712(ins IntRegs:$Rs32, u5_0Imm:$II),
11713"memw($Rs32) = setbit(#$II)",
11714tc_158aa3f7, TypeMAPPING> {
11715let isPseudo = 1;
11716let isCodeGenOnly = 1;
11717}
11718def L4_isub_memopb_io : HInst<
11719(outs),
11720(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11721"memb($Rs32+#$Ii) -= #$II",
11722tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11723let Inst{6-5} = 0b01;
11724let Inst{13-13} = 0b0;
11725let Inst{31-21} = 0b00111111000;
11726let addrMode = BaseImmOffset;
11727let accessSize = ByteAccess;
11728let mayLoad = 1;
11729let isRestrictNoSlot1Store = 1;
11730let mayStore = 1;
11731let isExtendable = 1;
11732let opExtendable = 1;
11733let isExtentSigned = 0;
11734let opExtentBits = 6;
11735let opExtentAlign = 0;
11736}
11737def L4_isub_memopb_zomap : HInst<
11738(outs),
11739(ins IntRegs:$Rs32, u5_0Imm:$II),
11740"memb($Rs32) -= #$II",
11741tc_158aa3f7, TypeMAPPING> {
11742let isPseudo = 1;
11743let isCodeGenOnly = 1;
11744}
11745def L4_isub_memoph_io : HInst<
11746(outs),
11747(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11748"memh($Rs32+#$Ii) -= #$II",
11749tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11750let Inst{6-5} = 0b01;
11751let Inst{13-13} = 0b0;
11752let Inst{31-21} = 0b00111111001;
11753let addrMode = BaseImmOffset;
11754let accessSize = HalfWordAccess;
11755let mayLoad = 1;
11756let isRestrictNoSlot1Store = 1;
11757let mayStore = 1;
11758let isExtendable = 1;
11759let opExtendable = 1;
11760let isExtentSigned = 0;
11761let opExtentBits = 7;
11762let opExtentAlign = 1;
11763}
11764def L4_isub_memoph_zomap : HInst<
11765(outs),
11766(ins IntRegs:$Rs32, u5_0Imm:$II),
11767"memh($Rs32) -= #$II",
11768tc_158aa3f7, TypeMAPPING> {
11769let isPseudo = 1;
11770let isCodeGenOnly = 1;
11771}
11772def L4_isub_memopw_io : HInst<
11773(outs),
11774(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11775"memw($Rs32+#$Ii) -= #$II",
11776tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11777let Inst{6-5} = 0b01;
11778let Inst{13-13} = 0b0;
11779let Inst{31-21} = 0b00111111010;
11780let addrMode = BaseImmOffset;
11781let accessSize = WordAccess;
11782let mayLoad = 1;
11783let isRestrictNoSlot1Store = 1;
11784let mayStore = 1;
11785let isExtendable = 1;
11786let opExtendable = 1;
11787let isExtentSigned = 0;
11788let opExtentBits = 8;
11789let opExtentAlign = 2;
11790}
11791def L4_isub_memopw_zomap : HInst<
11792(outs),
11793(ins IntRegs:$Rs32, u5_0Imm:$II),
11794"memw($Rs32) -= #$II",
11795tc_158aa3f7, TypeMAPPING> {
11796let isPseudo = 1;
11797let isCodeGenOnly = 1;
11798}
11799def L4_loadalignb_ap : HInst<
11800(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11801(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11802"$Ryy32 = memb_fifo($Re32=#$II)",
11803tc_ac65613f, TypeLD>, Enc_f394d3 {
11804let Inst{7-7} = 0b0;
11805let Inst{13-12} = 0b01;
11806let Inst{31-21} = 0b10011010100;
11807let addrMode = AbsoluteSet;
11808let accessSize = ByteAccess;
11809let mayLoad = 1;
11810let isExtended = 1;
11811let DecoderNamespace = "MustExtend";
11812let isExtendable = 1;
11813let opExtendable = 3;
11814let isExtentSigned = 0;
11815let opExtentBits = 6;
11816let opExtentAlign = 0;
11817let Constraints = "$Ryy32 = $Ryy32in";
11818}
11819def L4_loadalignb_ur : HInst<
11820(outs DoubleRegs:$Ryy32),
11821(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11822"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
11823tc_a32e03e7, TypeLD>, Enc_04c959 {
11824let Inst{12-12} = 0b1;
11825let Inst{31-21} = 0b10011100100;
11826let addrMode = BaseLongOffset;
11827let accessSize = ByteAccess;
11828let mayLoad = 1;
11829let isExtended = 1;
11830let InputType = "imm";
11831let DecoderNamespace = "MustExtend";
11832let isExtendable = 1;
11833let opExtendable = 4;
11834let isExtentSigned = 0;
11835let opExtentBits = 6;
11836let opExtentAlign = 0;
11837let Constraints = "$Ryy32 = $Ryy32in";
11838}
11839def L4_loadalignh_ap : HInst<
11840(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11841(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11842"$Ryy32 = memh_fifo($Re32=#$II)",
11843tc_ac65613f, TypeLD>, Enc_f394d3 {
11844let Inst{7-7} = 0b0;
11845let Inst{13-12} = 0b01;
11846let Inst{31-21} = 0b10011010010;
11847let addrMode = AbsoluteSet;
11848let accessSize = HalfWordAccess;
11849let mayLoad = 1;
11850let isExtended = 1;
11851let DecoderNamespace = "MustExtend";
11852let isExtendable = 1;
11853let opExtendable = 3;
11854let isExtentSigned = 0;
11855let opExtentBits = 6;
11856let opExtentAlign = 0;
11857let Constraints = "$Ryy32 = $Ryy32in";
11858}
11859def L4_loadalignh_ur : HInst<
11860(outs DoubleRegs:$Ryy32),
11861(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11862"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
11863tc_a32e03e7, TypeLD>, Enc_04c959 {
11864let Inst{12-12} = 0b1;
11865let Inst{31-21} = 0b10011100010;
11866let addrMode = BaseLongOffset;
11867let accessSize = HalfWordAccess;
11868let mayLoad = 1;
11869let isExtended = 1;
11870let InputType = "imm";
11871let DecoderNamespace = "MustExtend";
11872let isExtendable = 1;
11873let opExtendable = 4;
11874let isExtentSigned = 0;
11875let opExtentBits = 6;
11876let opExtentAlign = 0;
11877let Constraints = "$Ryy32 = $Ryy32in";
11878}
11879def L4_loadbsw2_ap : HInst<
11880(outs IntRegs:$Rd32, IntRegs:$Re32),
11881(ins u32_0Imm:$II),
11882"$Rd32 = membh($Re32=#$II)",
11883tc_822c3c68, TypeLD>, Enc_323f2d {
11884let Inst{7-7} = 0b0;
11885let Inst{13-12} = 0b01;
11886let Inst{31-21} = 0b10011010001;
11887let hasNewValue = 1;
11888let opNewValue = 0;
11889let addrMode = AbsoluteSet;
11890let accessSize = HalfWordAccess;
11891let mayLoad = 1;
11892let isExtended = 1;
11893let DecoderNamespace = "MustExtend";
11894let isExtendable = 1;
11895let opExtendable = 2;
11896let isExtentSigned = 0;
11897let opExtentBits = 6;
11898let opExtentAlign = 0;
11899}
11900def L4_loadbsw2_ur : HInst<
11901(outs IntRegs:$Rd32),
11902(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11903"$Rd32 = membh($Rt32<<#$Ii+#$II)",
11904tc_abfd9a6d, TypeLD>, Enc_4f677b {
11905let Inst{12-12} = 0b1;
11906let Inst{31-21} = 0b10011100001;
11907let hasNewValue = 1;
11908let opNewValue = 0;
11909let addrMode = BaseLongOffset;
11910let accessSize = HalfWordAccess;
11911let mayLoad = 1;
11912let isExtended = 1;
11913let InputType = "imm";
11914let DecoderNamespace = "MustExtend";
11915let isExtendable = 1;
11916let opExtendable = 3;
11917let isExtentSigned = 0;
11918let opExtentBits = 6;
11919let opExtentAlign = 0;
11920}
11921def L4_loadbsw4_ap : HInst<
11922(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11923(ins u32_0Imm:$II),
11924"$Rdd32 = membh($Re32=#$II)",
11925tc_822c3c68, TypeLD>, Enc_7fa7f6 {
11926let Inst{7-7} = 0b0;
11927let Inst{13-12} = 0b01;
11928let Inst{31-21} = 0b10011010111;
11929let addrMode = AbsoluteSet;
11930let accessSize = WordAccess;
11931let mayLoad = 1;
11932let isExtended = 1;
11933let DecoderNamespace = "MustExtend";
11934let isExtendable = 1;
11935let opExtendable = 2;
11936let isExtentSigned = 0;
11937let opExtentBits = 6;
11938let opExtentAlign = 0;
11939}
11940def L4_loadbsw4_ur : HInst<
11941(outs DoubleRegs:$Rdd32),
11942(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11943"$Rdd32 = membh($Rt32<<#$Ii+#$II)",
11944tc_abfd9a6d, TypeLD>, Enc_6185fe {
11945let Inst{12-12} = 0b1;
11946let Inst{31-21} = 0b10011100111;
11947let addrMode = BaseLongOffset;
11948let accessSize = WordAccess;
11949let mayLoad = 1;
11950let isExtended = 1;
11951let InputType = "imm";
11952let DecoderNamespace = "MustExtend";
11953let isExtendable = 1;
11954let opExtendable = 3;
11955let isExtentSigned = 0;
11956let opExtentBits = 6;
11957let opExtentAlign = 0;
11958}
11959def L4_loadbzw2_ap : HInst<
11960(outs IntRegs:$Rd32, IntRegs:$Re32),
11961(ins u32_0Imm:$II),
11962"$Rd32 = memubh($Re32=#$II)",
11963tc_822c3c68, TypeLD>, Enc_323f2d {
11964let Inst{7-7} = 0b0;
11965let Inst{13-12} = 0b01;
11966let Inst{31-21} = 0b10011010011;
11967let hasNewValue = 1;
11968let opNewValue = 0;
11969let addrMode = AbsoluteSet;
11970let accessSize = HalfWordAccess;
11971let mayLoad = 1;
11972let isExtended = 1;
11973let DecoderNamespace = "MustExtend";
11974let isExtendable = 1;
11975let opExtendable = 2;
11976let isExtentSigned = 0;
11977let opExtentBits = 6;
11978let opExtentAlign = 0;
11979}
11980def L4_loadbzw2_ur : HInst<
11981(outs IntRegs:$Rd32),
11982(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11983"$Rd32 = memubh($Rt32<<#$Ii+#$II)",
11984tc_abfd9a6d, TypeLD>, Enc_4f677b {
11985let Inst{12-12} = 0b1;
11986let Inst{31-21} = 0b10011100011;
11987let hasNewValue = 1;
11988let opNewValue = 0;
11989let addrMode = BaseLongOffset;
11990let accessSize = HalfWordAccess;
11991let mayLoad = 1;
11992let isExtended = 1;
11993let InputType = "imm";
11994let DecoderNamespace = "MustExtend";
11995let isExtendable = 1;
11996let opExtendable = 3;
11997let isExtentSigned = 0;
11998let opExtentBits = 6;
11999let opExtentAlign = 0;
12000}
12001def L4_loadbzw4_ap : HInst<
12002(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12003(ins u32_0Imm:$II),
12004"$Rdd32 = memubh($Re32=#$II)",
12005tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12006let Inst{7-7} = 0b0;
12007let Inst{13-12} = 0b01;
12008let Inst{31-21} = 0b10011010101;
12009let addrMode = AbsoluteSet;
12010let accessSize = WordAccess;
12011let mayLoad = 1;
12012let isExtended = 1;
12013let DecoderNamespace = "MustExtend";
12014let isExtendable = 1;
12015let opExtendable = 2;
12016let isExtentSigned = 0;
12017let opExtentBits = 6;
12018let opExtentAlign = 0;
12019}
12020def L4_loadbzw4_ur : HInst<
12021(outs DoubleRegs:$Rdd32),
12022(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12023"$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
12024tc_abfd9a6d, TypeLD>, Enc_6185fe {
12025let Inst{12-12} = 0b1;
12026let Inst{31-21} = 0b10011100101;
12027let addrMode = BaseLongOffset;
12028let accessSize = WordAccess;
12029let mayLoad = 1;
12030let isExtended = 1;
12031let InputType = "imm";
12032let DecoderNamespace = "MustExtend";
12033let isExtendable = 1;
12034let opExtendable = 3;
12035let isExtentSigned = 0;
12036let opExtentBits = 6;
12037let opExtentAlign = 0;
12038}
12039def L4_loadd_aq : HInst<
12040(outs DoubleRegs:$Rdd32),
12041(ins IntRegs:$Rs32),
12042"$Rdd32 = memd_aq($Rs32)",
12043tc_2471c1c8, TypeLD>, Enc_3a3d62, Requires<[HasV68]> {
12044let Inst{13-5} = 0b011000000;
12045let Inst{31-21} = 0b10010010000;
12046let accessSize = DoubleWordAccess;
12047let mayLoad = 1;
12048}
12049def L4_loadd_locked : HInst<
12050(outs DoubleRegs:$Rdd32),
12051(ins IntRegs:$Rs32),
12052"$Rdd32 = memd_locked($Rs32)",
12053tc_64b00d8a, TypeLD>, Enc_3a3d62 {
12054let Inst{13-5} = 0b010000000;
12055let Inst{31-21} = 0b10010010000;
12056let accessSize = DoubleWordAccess;
12057let mayLoad = 1;
12058let isSoloAX = 1;
12059}
12060def L4_loadrb_ap : HInst<
12061(outs IntRegs:$Rd32, IntRegs:$Re32),
12062(ins u32_0Imm:$II),
12063"$Rd32 = memb($Re32=#$II)",
12064tc_822c3c68, TypeLD>, Enc_323f2d {
12065let Inst{7-7} = 0b0;
12066let Inst{13-12} = 0b01;
12067let Inst{31-21} = 0b10011011000;
12068let hasNewValue = 1;
12069let opNewValue = 0;
12070let addrMode = AbsoluteSet;
12071let accessSize = ByteAccess;
12072let mayLoad = 1;
12073let isExtended = 1;
12074let DecoderNamespace = "MustExtend";
12075let isExtendable = 1;
12076let opExtendable = 2;
12077let isExtentSigned = 0;
12078let opExtentBits = 6;
12079let opExtentAlign = 0;
12080}
12081def L4_loadrb_rr : HInst<
12082(outs IntRegs:$Rd32),
12083(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12084"$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12085tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12086let Inst{6-5} = 0b00;
12087let Inst{31-21} = 0b00111010000;
12088let hasNewValue = 1;
12089let opNewValue = 0;
12090let addrMode = BaseRegOffset;
12091let accessSize = ByteAccess;
12092let mayLoad = 1;
12093let BaseOpcode = "L4_loadrb_rr";
12094let CextOpcode = "L2_loadrb";
12095let InputType = "reg";
12096let isPredicable = 1;
12097}
12098def L4_loadrb_ur : HInst<
12099(outs IntRegs:$Rd32),
12100(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12101"$Rd32 = memb($Rt32<<#$Ii+#$II)",
12102tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12103let Inst{12-12} = 0b1;
12104let Inst{31-21} = 0b10011101000;
12105let hasNewValue = 1;
12106let opNewValue = 0;
12107let addrMode = BaseLongOffset;
12108let accessSize = ByteAccess;
12109let mayLoad = 1;
12110let isExtended = 1;
12111let CextOpcode = "L2_loadrb";
12112let InputType = "imm";
12113let DecoderNamespace = "MustExtend";
12114let isExtendable = 1;
12115let opExtendable = 3;
12116let isExtentSigned = 0;
12117let opExtentBits = 6;
12118let opExtentAlign = 0;
12119}
12120def L4_loadrd_ap : HInst<
12121(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12122(ins u32_0Imm:$II),
12123"$Rdd32 = memd($Re32=#$II)",
12124tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12125let Inst{7-7} = 0b0;
12126let Inst{13-12} = 0b01;
12127let Inst{31-21} = 0b10011011110;
12128let addrMode = AbsoluteSet;
12129let accessSize = DoubleWordAccess;
12130let mayLoad = 1;
12131let isExtended = 1;
12132let DecoderNamespace = "MustExtend";
12133let isExtendable = 1;
12134let opExtendable = 2;
12135let isExtentSigned = 0;
12136let opExtentBits = 6;
12137let opExtentAlign = 0;
12138}
12139def L4_loadrd_rr : HInst<
12140(outs DoubleRegs:$Rdd32),
12141(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12142"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12143tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
12144let Inst{6-5} = 0b00;
12145let Inst{31-21} = 0b00111010110;
12146let addrMode = BaseRegOffset;
12147let accessSize = DoubleWordAccess;
12148let mayLoad = 1;
12149let BaseOpcode = "L4_loadrd_rr";
12150let CextOpcode = "L2_loadrd";
12151let InputType = "reg";
12152let isPredicable = 1;
12153}
12154def L4_loadrd_ur : HInst<
12155(outs DoubleRegs:$Rdd32),
12156(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12157"$Rdd32 = memd($Rt32<<#$Ii+#$II)",
12158tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
12159let Inst{12-12} = 0b1;
12160let Inst{31-21} = 0b10011101110;
12161let addrMode = BaseLongOffset;
12162let accessSize = DoubleWordAccess;
12163let mayLoad = 1;
12164let isExtended = 1;
12165let CextOpcode = "L2_loadrd";
12166let InputType = "imm";
12167let DecoderNamespace = "MustExtend";
12168let isExtendable = 1;
12169let opExtendable = 3;
12170let isExtentSigned = 0;
12171let opExtentBits = 6;
12172let opExtentAlign = 0;
12173}
12174def L4_loadrh_ap : HInst<
12175(outs IntRegs:$Rd32, IntRegs:$Re32),
12176(ins u32_0Imm:$II),
12177"$Rd32 = memh($Re32=#$II)",
12178tc_822c3c68, TypeLD>, Enc_323f2d {
12179let Inst{7-7} = 0b0;
12180let Inst{13-12} = 0b01;
12181let Inst{31-21} = 0b10011011010;
12182let hasNewValue = 1;
12183let opNewValue = 0;
12184let addrMode = AbsoluteSet;
12185let accessSize = HalfWordAccess;
12186let mayLoad = 1;
12187let isExtended = 1;
12188let DecoderNamespace = "MustExtend";
12189let isExtendable = 1;
12190let opExtendable = 2;
12191let isExtentSigned = 0;
12192let opExtentBits = 6;
12193let opExtentAlign = 0;
12194}
12195def L4_loadrh_rr : HInst<
12196(outs IntRegs:$Rd32),
12197(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12198"$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12199tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12200let Inst{6-5} = 0b00;
12201let Inst{31-21} = 0b00111010010;
12202let hasNewValue = 1;
12203let opNewValue = 0;
12204let addrMode = BaseRegOffset;
12205let accessSize = HalfWordAccess;
12206let mayLoad = 1;
12207let BaseOpcode = "L4_loadrh_rr";
12208let CextOpcode = "L2_loadrh";
12209let InputType = "reg";
12210let isPredicable = 1;
12211}
12212def L4_loadrh_ur : HInst<
12213(outs IntRegs:$Rd32),
12214(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12215"$Rd32 = memh($Rt32<<#$Ii+#$II)",
12216tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12217let Inst{12-12} = 0b1;
12218let Inst{31-21} = 0b10011101010;
12219let hasNewValue = 1;
12220let opNewValue = 0;
12221let addrMode = BaseLongOffset;
12222let accessSize = HalfWordAccess;
12223let mayLoad = 1;
12224let isExtended = 1;
12225let CextOpcode = "L2_loadrh";
12226let InputType = "imm";
12227let DecoderNamespace = "MustExtend";
12228let isExtendable = 1;
12229let opExtendable = 3;
12230let isExtentSigned = 0;
12231let opExtentBits = 6;
12232let opExtentAlign = 0;
12233}
12234def L4_loadri_ap : HInst<
12235(outs IntRegs:$Rd32, IntRegs:$Re32),
12236(ins u32_0Imm:$II),
12237"$Rd32 = memw($Re32=#$II)",
12238tc_822c3c68, TypeLD>, Enc_323f2d {
12239let Inst{7-7} = 0b0;
12240let Inst{13-12} = 0b01;
12241let Inst{31-21} = 0b10011011100;
12242let hasNewValue = 1;
12243let opNewValue = 0;
12244let addrMode = AbsoluteSet;
12245let accessSize = WordAccess;
12246let mayLoad = 1;
12247let isExtended = 1;
12248let DecoderNamespace = "MustExtend";
12249let isExtendable = 1;
12250let opExtendable = 2;
12251let isExtentSigned = 0;
12252let opExtentBits = 6;
12253let opExtentAlign = 0;
12254}
12255def L4_loadri_rr : HInst<
12256(outs IntRegs:$Rd32),
12257(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12258"$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12259tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12260let Inst{6-5} = 0b00;
12261let Inst{31-21} = 0b00111010100;
12262let hasNewValue = 1;
12263let opNewValue = 0;
12264let addrMode = BaseRegOffset;
12265let accessSize = WordAccess;
12266let mayLoad = 1;
12267let BaseOpcode = "L4_loadri_rr";
12268let CextOpcode = "L2_loadri";
12269let InputType = "reg";
12270let isPredicable = 1;
12271}
12272def L4_loadri_ur : HInst<
12273(outs IntRegs:$Rd32),
12274(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12275"$Rd32 = memw($Rt32<<#$Ii+#$II)",
12276tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12277let Inst{12-12} = 0b1;
12278let Inst{31-21} = 0b10011101100;
12279let hasNewValue = 1;
12280let opNewValue = 0;
12281let addrMode = BaseLongOffset;
12282let accessSize = WordAccess;
12283let mayLoad = 1;
12284let isExtended = 1;
12285let CextOpcode = "L2_loadri";
12286let InputType = "imm";
12287let DecoderNamespace = "MustExtend";
12288let isExtendable = 1;
12289let opExtendable = 3;
12290let isExtentSigned = 0;
12291let opExtentBits = 6;
12292let opExtentAlign = 0;
12293}
12294def L4_loadrub_ap : HInst<
12295(outs IntRegs:$Rd32, IntRegs:$Re32),
12296(ins u32_0Imm:$II),
12297"$Rd32 = memub($Re32=#$II)",
12298tc_822c3c68, TypeLD>, Enc_323f2d {
12299let Inst{7-7} = 0b0;
12300let Inst{13-12} = 0b01;
12301let Inst{31-21} = 0b10011011001;
12302let hasNewValue = 1;
12303let opNewValue = 0;
12304let addrMode = AbsoluteSet;
12305let accessSize = ByteAccess;
12306let mayLoad = 1;
12307let isExtended = 1;
12308let DecoderNamespace = "MustExtend";
12309let isExtendable = 1;
12310let opExtendable = 2;
12311let isExtentSigned = 0;
12312let opExtentBits = 6;
12313let opExtentAlign = 0;
12314}
12315def L4_loadrub_rr : HInst<
12316(outs IntRegs:$Rd32),
12317(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12318"$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12319tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12320let Inst{6-5} = 0b00;
12321let Inst{31-21} = 0b00111010001;
12322let hasNewValue = 1;
12323let opNewValue = 0;
12324let addrMode = BaseRegOffset;
12325let accessSize = ByteAccess;
12326let mayLoad = 1;
12327let BaseOpcode = "L4_loadrub_rr";
12328let CextOpcode = "L2_loadrub";
12329let InputType = "reg";
12330let isPredicable = 1;
12331}
12332def L4_loadrub_ur : HInst<
12333(outs IntRegs:$Rd32),
12334(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12335"$Rd32 = memub($Rt32<<#$Ii+#$II)",
12336tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12337let Inst{12-12} = 0b1;
12338let Inst{31-21} = 0b10011101001;
12339let hasNewValue = 1;
12340let opNewValue = 0;
12341let addrMode = BaseLongOffset;
12342let accessSize = ByteAccess;
12343let mayLoad = 1;
12344let isExtended = 1;
12345let CextOpcode = "L2_loadrub";
12346let InputType = "imm";
12347let DecoderNamespace = "MustExtend";
12348let isExtendable = 1;
12349let opExtendable = 3;
12350let isExtentSigned = 0;
12351let opExtentBits = 6;
12352let opExtentAlign = 0;
12353}
12354def L4_loadruh_ap : HInst<
12355(outs IntRegs:$Rd32, IntRegs:$Re32),
12356(ins u32_0Imm:$II),
12357"$Rd32 = memuh($Re32=#$II)",
12358tc_822c3c68, TypeLD>, Enc_323f2d {
12359let Inst{7-7} = 0b0;
12360let Inst{13-12} = 0b01;
12361let Inst{31-21} = 0b10011011011;
12362let hasNewValue = 1;
12363let opNewValue = 0;
12364let addrMode = AbsoluteSet;
12365let accessSize = HalfWordAccess;
12366let mayLoad = 1;
12367let isExtended = 1;
12368let DecoderNamespace = "MustExtend";
12369let isExtendable = 1;
12370let opExtendable = 2;
12371let isExtentSigned = 0;
12372let opExtentBits = 6;
12373let opExtentAlign = 0;
12374}
12375def L4_loadruh_rr : HInst<
12376(outs IntRegs:$Rd32),
12377(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12378"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
12379tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12380let Inst{6-5} = 0b00;
12381let Inst{31-21} = 0b00111010011;
12382let hasNewValue = 1;
12383let opNewValue = 0;
12384let addrMode = BaseRegOffset;
12385let accessSize = HalfWordAccess;
12386let mayLoad = 1;
12387let BaseOpcode = "L4_loadruh_rr";
12388let CextOpcode = "L2_loadruh";
12389let InputType = "reg";
12390let isPredicable = 1;
12391}
12392def L4_loadruh_ur : HInst<
12393(outs IntRegs:$Rd32),
12394(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12395"$Rd32 = memuh($Rt32<<#$Ii+#$II)",
12396tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12397let Inst{12-12} = 0b1;
12398let Inst{31-21} = 0b10011101011;
12399let hasNewValue = 1;
12400let opNewValue = 0;
12401let addrMode = BaseLongOffset;
12402let accessSize = HalfWordAccess;
12403let mayLoad = 1;
12404let isExtended = 1;
12405let CextOpcode = "L2_loadruh";
12406let InputType = "imm";
12407let DecoderNamespace = "MustExtend";
12408let isExtendable = 1;
12409let opExtendable = 3;
12410let isExtentSigned = 0;
12411let opExtentBits = 6;
12412let opExtentAlign = 0;
12413}
12414def L4_or_memopb_io : HInst<
12415(outs),
12416(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
12417"memb($Rs32+#$Ii) |= $Rt32",
12418tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
12419let Inst{6-5} = 0b11;
12420let Inst{13-13} = 0b0;
12421let Inst{31-21} = 0b00111110000;
12422let addrMode = BaseImmOffset;
12423let accessSize = ByteAccess;
12424let mayLoad = 1;
12425let isRestrictNoSlot1Store = 1;
12426let mayStore = 1;
12427let isExtendable = 1;
12428let opExtendable = 1;
12429let isExtentSigned = 0;
12430let opExtentBits = 6;
12431let opExtentAlign = 0;
12432}
12433def L4_or_memopb_zomap : HInst<
12434(outs),
12435(ins IntRegs:$Rs32, IntRegs:$Rt32),
12436"memb($Rs32) |= $Rt32",
12437tc_9bcfb2ee, TypeMAPPING> {
12438let isPseudo = 1;
12439let isCodeGenOnly = 1;
12440}
12441def L4_or_memoph_io : HInst<
12442(outs),
12443(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
12444"memh($Rs32+#$Ii) |= $Rt32",
12445tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
12446let Inst{6-5} = 0b11;
12447let Inst{13-13} = 0b0;
12448let Inst{31-21} = 0b00111110001;
12449let addrMode = BaseImmOffset;
12450let accessSize = HalfWordAccess;
12451let mayLoad = 1;
12452let isRestrictNoSlot1Store = 1;
12453let mayStore = 1;
12454let isExtendable = 1;
12455let opExtendable = 1;
12456let isExtentSigned = 0;
12457let opExtentBits = 7;
12458let opExtentAlign = 1;
12459}
12460def L4_or_memoph_zomap : HInst<
12461(outs),
12462(ins IntRegs:$Rs32, IntRegs:$Rt32),
12463"memh($Rs32) |= $Rt32",
12464tc_9bcfb2ee, TypeMAPPING> {
12465let isPseudo = 1;
12466let isCodeGenOnly = 1;
12467}
12468def L4_or_memopw_io : HInst<
12469(outs),
12470(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
12471"memw($Rs32+#$Ii) |= $Rt32",
12472tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
12473let Inst{6-5} = 0b11;
12474let Inst{13-13} = 0b0;
12475let Inst{31-21} = 0b00111110010;
12476let addrMode = BaseImmOffset;
12477let accessSize = WordAccess;
12478let mayLoad = 1;
12479let isRestrictNoSlot1Store = 1;
12480let mayStore = 1;
12481let isExtendable = 1;
12482let opExtendable = 1;
12483let isExtentSigned = 0;
12484let opExtentBits = 8;
12485let opExtentAlign = 2;
12486}
12487def L4_or_memopw_zomap : HInst<
12488(outs),
12489(ins IntRegs:$Rs32, IntRegs:$Rt32),
12490"memw($Rs32) |= $Rt32",
12491tc_9bcfb2ee, TypeMAPPING> {
12492let isPseudo = 1;
12493let isCodeGenOnly = 1;
12494}
12495def L4_ploadrbf_abs : HInst<
12496(outs IntRegs:$Rd32),
12497(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12498"if (!$Pt4) $Rd32 = memb(#$Ii)",
12499tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12500let Inst{7-5} = 0b100;
12501let Inst{13-11} = 0b101;
12502let Inst{31-21} = 0b10011111000;
12503let isPredicated = 1;
12504let isPredicatedFalse = 1;
12505let hasNewValue = 1;
12506let opNewValue = 0;
12507let addrMode = Absolute;
12508let accessSize = ByteAccess;
12509let mayLoad = 1;
12510let isExtended = 1;
12511let BaseOpcode = "L4_loadrb_abs";
12512let CextOpcode = "L2_loadrb";
12513let DecoderNamespace = "MustExtend";
12514let isExtendable = 1;
12515let opExtendable = 2;
12516let isExtentSigned = 0;
12517let opExtentBits = 6;
12518let opExtentAlign = 0;
12519}
12520def L4_ploadrbf_rr : HInst<
12521(outs IntRegs:$Rd32),
12522(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12523"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12524tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12525let Inst{31-21} = 0b00110001000;
12526let isPredicated = 1;
12527let isPredicatedFalse = 1;
12528let hasNewValue = 1;
12529let opNewValue = 0;
12530let addrMode = BaseRegOffset;
12531let accessSize = ByteAccess;
12532let mayLoad = 1;
12533let BaseOpcode = "L4_loadrb_rr";
12534let CextOpcode = "L2_loadrb";
12535let InputType = "reg";
12536}
12537def L4_ploadrbfnew_abs : HInst<
12538(outs IntRegs:$Rd32),
12539(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12540"if (!$Pt4.new) $Rd32 = memb(#$Ii)",
12541tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12542let Inst{7-5} = 0b100;
12543let Inst{13-11} = 0b111;
12544let Inst{31-21} = 0b10011111000;
12545let isPredicated = 1;
12546let isPredicatedFalse = 1;
12547let hasNewValue = 1;
12548let opNewValue = 0;
12549let addrMode = Absolute;
12550let accessSize = ByteAccess;
12551let isPredicatedNew = 1;
12552let mayLoad = 1;
12553let isExtended = 1;
12554let BaseOpcode = "L4_loadrb_abs";
12555let CextOpcode = "L2_loadrb";
12556let DecoderNamespace = "MustExtend";
12557let isExtendable = 1;
12558let opExtendable = 2;
12559let isExtentSigned = 0;
12560let opExtentBits = 6;
12561let opExtentAlign = 0;
12562}
12563def L4_ploadrbfnew_rr : HInst<
12564(outs IntRegs:$Rd32),
12565(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12566"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12567tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12568let Inst{31-21} = 0b00110011000;
12569let isPredicated = 1;
12570let isPredicatedFalse = 1;
12571let hasNewValue = 1;
12572let opNewValue = 0;
12573let addrMode = BaseRegOffset;
12574let accessSize = ByteAccess;
12575let isPredicatedNew = 1;
12576let mayLoad = 1;
12577let BaseOpcode = "L4_loadrb_rr";
12578let CextOpcode = "L2_loadrb";
12579let InputType = "reg";
12580}
12581def L4_ploadrbt_abs : HInst<
12582(outs IntRegs:$Rd32),
12583(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12584"if ($Pt4) $Rd32 = memb(#$Ii)",
12585tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12586let Inst{7-5} = 0b100;
12587let Inst{13-11} = 0b100;
12588let Inst{31-21} = 0b10011111000;
12589let isPredicated = 1;
12590let hasNewValue = 1;
12591let opNewValue = 0;
12592let addrMode = Absolute;
12593let accessSize = ByteAccess;
12594let mayLoad = 1;
12595let isExtended = 1;
12596let BaseOpcode = "L4_loadrb_abs";
12597let CextOpcode = "L2_loadrb";
12598let DecoderNamespace = "MustExtend";
12599let isExtendable = 1;
12600let opExtendable = 2;
12601let isExtentSigned = 0;
12602let opExtentBits = 6;
12603let opExtentAlign = 0;
12604}
12605def L4_ploadrbt_rr : HInst<
12606(outs IntRegs:$Rd32),
12607(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12608"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12609tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12610let Inst{31-21} = 0b00110000000;
12611let isPredicated = 1;
12612let hasNewValue = 1;
12613let opNewValue = 0;
12614let addrMode = BaseRegOffset;
12615let accessSize = ByteAccess;
12616let mayLoad = 1;
12617let BaseOpcode = "L4_loadrb_rr";
12618let CextOpcode = "L2_loadrb";
12619let InputType = "reg";
12620}
12621def L4_ploadrbtnew_abs : HInst<
12622(outs IntRegs:$Rd32),
12623(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12624"if ($Pt4.new) $Rd32 = memb(#$Ii)",
12625tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12626let Inst{7-5} = 0b100;
12627let Inst{13-11} = 0b110;
12628let Inst{31-21} = 0b10011111000;
12629let isPredicated = 1;
12630let hasNewValue = 1;
12631let opNewValue = 0;
12632let addrMode = Absolute;
12633let accessSize = ByteAccess;
12634let isPredicatedNew = 1;
12635let mayLoad = 1;
12636let isExtended = 1;
12637let BaseOpcode = "L4_loadrb_abs";
12638let CextOpcode = "L2_loadrb";
12639let DecoderNamespace = "MustExtend";
12640let isExtendable = 1;
12641let opExtendable = 2;
12642let isExtentSigned = 0;
12643let opExtentBits = 6;
12644let opExtentAlign = 0;
12645}
12646def L4_ploadrbtnew_rr : HInst<
12647(outs IntRegs:$Rd32),
12648(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12649"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12650tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12651let Inst{31-21} = 0b00110010000;
12652let isPredicated = 1;
12653let hasNewValue = 1;
12654let opNewValue = 0;
12655let addrMode = BaseRegOffset;
12656let accessSize = ByteAccess;
12657let isPredicatedNew = 1;
12658let mayLoad = 1;
12659let BaseOpcode = "L4_loadrb_rr";
12660let CextOpcode = "L2_loadrb";
12661let InputType = "reg";
12662}
12663def L4_ploadrdf_abs : HInst<
12664(outs DoubleRegs:$Rdd32),
12665(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12666"if (!$Pt4) $Rdd32 = memd(#$Ii)",
12667tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12668let Inst{7-5} = 0b100;
12669let Inst{13-11} = 0b101;
12670let Inst{31-21} = 0b10011111110;
12671let isPredicated = 1;
12672let isPredicatedFalse = 1;
12673let addrMode = Absolute;
12674let accessSize = DoubleWordAccess;
12675let mayLoad = 1;
12676let isExtended = 1;
12677let BaseOpcode = "L4_loadrd_abs";
12678let CextOpcode = "L2_loadrd";
12679let DecoderNamespace = "MustExtend";
12680let isExtendable = 1;
12681let opExtendable = 2;
12682let isExtentSigned = 0;
12683let opExtentBits = 6;
12684let opExtentAlign = 0;
12685}
12686def L4_ploadrdf_rr : HInst<
12687(outs DoubleRegs:$Rdd32),
12688(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12689"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12690tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12691let Inst{31-21} = 0b00110001110;
12692let isPredicated = 1;
12693let isPredicatedFalse = 1;
12694let addrMode = BaseRegOffset;
12695let accessSize = DoubleWordAccess;
12696let mayLoad = 1;
12697let BaseOpcode = "L4_loadrd_rr";
12698let CextOpcode = "L2_loadrd";
12699let InputType = "reg";
12700}
12701def L4_ploadrdfnew_abs : HInst<
12702(outs DoubleRegs:$Rdd32),
12703(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12704"if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
12705tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12706let Inst{7-5} = 0b100;
12707let Inst{13-11} = 0b111;
12708let Inst{31-21} = 0b10011111110;
12709let isPredicated = 1;
12710let isPredicatedFalse = 1;
12711let addrMode = Absolute;
12712let accessSize = DoubleWordAccess;
12713let isPredicatedNew = 1;
12714let mayLoad = 1;
12715let isExtended = 1;
12716let BaseOpcode = "L4_loadrd_abs";
12717let CextOpcode = "L2_loadrd";
12718let DecoderNamespace = "MustExtend";
12719let isExtendable = 1;
12720let opExtendable = 2;
12721let isExtentSigned = 0;
12722let opExtentBits = 6;
12723let opExtentAlign = 0;
12724}
12725def L4_ploadrdfnew_rr : HInst<
12726(outs DoubleRegs:$Rdd32),
12727(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12728"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12729tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12730let Inst{31-21} = 0b00110011110;
12731let isPredicated = 1;
12732let isPredicatedFalse = 1;
12733let addrMode = BaseRegOffset;
12734let accessSize = DoubleWordAccess;
12735let isPredicatedNew = 1;
12736let mayLoad = 1;
12737let BaseOpcode = "L4_loadrd_rr";
12738let CextOpcode = "L2_loadrd";
12739let InputType = "reg";
12740}
12741def L4_ploadrdt_abs : HInst<
12742(outs DoubleRegs:$Rdd32),
12743(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12744"if ($Pt4) $Rdd32 = memd(#$Ii)",
12745tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12746let Inst{7-5} = 0b100;
12747let Inst{13-11} = 0b100;
12748let Inst{31-21} = 0b10011111110;
12749let isPredicated = 1;
12750let addrMode = Absolute;
12751let accessSize = DoubleWordAccess;
12752let mayLoad = 1;
12753let isExtended = 1;
12754let BaseOpcode = "L4_loadrd_abs";
12755let CextOpcode = "L2_loadrd";
12756let DecoderNamespace = "MustExtend";
12757let isExtendable = 1;
12758let opExtendable = 2;
12759let isExtentSigned = 0;
12760let opExtentBits = 6;
12761let opExtentAlign = 0;
12762}
12763def L4_ploadrdt_rr : HInst<
12764(outs DoubleRegs:$Rdd32),
12765(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12766"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12767tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12768let Inst{31-21} = 0b00110000110;
12769let isPredicated = 1;
12770let addrMode = BaseRegOffset;
12771let accessSize = DoubleWordAccess;
12772let mayLoad = 1;
12773let BaseOpcode = "L4_loadrd_rr";
12774let CextOpcode = "L2_loadrd";
12775let InputType = "reg";
12776}
12777def L4_ploadrdtnew_abs : HInst<
12778(outs DoubleRegs:$Rdd32),
12779(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12780"if ($Pt4.new) $Rdd32 = memd(#$Ii)",
12781tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12782let Inst{7-5} = 0b100;
12783let Inst{13-11} = 0b110;
12784let Inst{31-21} = 0b10011111110;
12785let isPredicated = 1;
12786let addrMode = Absolute;
12787let accessSize = DoubleWordAccess;
12788let isPredicatedNew = 1;
12789let mayLoad = 1;
12790let isExtended = 1;
12791let BaseOpcode = "L4_loadrd_abs";
12792let CextOpcode = "L2_loadrd";
12793let DecoderNamespace = "MustExtend";
12794let isExtendable = 1;
12795let opExtendable = 2;
12796let isExtentSigned = 0;
12797let opExtentBits = 6;
12798let opExtentAlign = 0;
12799}
12800def L4_ploadrdtnew_rr : HInst<
12801(outs DoubleRegs:$Rdd32),
12802(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12803"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12804tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12805let Inst{31-21} = 0b00110010110;
12806let isPredicated = 1;
12807let addrMode = BaseRegOffset;
12808let accessSize = DoubleWordAccess;
12809let isPredicatedNew = 1;
12810let mayLoad = 1;
12811let BaseOpcode = "L4_loadrd_rr";
12812let CextOpcode = "L2_loadrd";
12813let InputType = "reg";
12814}
12815def L4_ploadrhf_abs : HInst<
12816(outs IntRegs:$Rd32),
12817(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12818"if (!$Pt4) $Rd32 = memh(#$Ii)",
12819tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12820let Inst{7-5} = 0b100;
12821let Inst{13-11} = 0b101;
12822let Inst{31-21} = 0b10011111010;
12823let isPredicated = 1;
12824let isPredicatedFalse = 1;
12825let hasNewValue = 1;
12826let opNewValue = 0;
12827let addrMode = Absolute;
12828let accessSize = HalfWordAccess;
12829let mayLoad = 1;
12830let isExtended = 1;
12831let BaseOpcode = "L4_loadrh_abs";
12832let CextOpcode = "L2_loadrh";
12833let DecoderNamespace = "MustExtend";
12834let isExtendable = 1;
12835let opExtendable = 2;
12836let isExtentSigned = 0;
12837let opExtentBits = 6;
12838let opExtentAlign = 0;
12839}
12840def L4_ploadrhf_rr : HInst<
12841(outs IntRegs:$Rd32),
12842(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12843"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12844tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12845let Inst{31-21} = 0b00110001010;
12846let isPredicated = 1;
12847let isPredicatedFalse = 1;
12848let hasNewValue = 1;
12849let opNewValue = 0;
12850let addrMode = BaseRegOffset;
12851let accessSize = HalfWordAccess;
12852let mayLoad = 1;
12853let BaseOpcode = "L4_loadrh_rr";
12854let CextOpcode = "L2_loadrh";
12855let InputType = "reg";
12856}
12857def L4_ploadrhfnew_abs : HInst<
12858(outs IntRegs:$Rd32),
12859(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12860"if (!$Pt4.new) $Rd32 = memh(#$Ii)",
12861tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12862let Inst{7-5} = 0b100;
12863let Inst{13-11} = 0b111;
12864let Inst{31-21} = 0b10011111010;
12865let isPredicated = 1;
12866let isPredicatedFalse = 1;
12867let hasNewValue = 1;
12868let opNewValue = 0;
12869let addrMode = Absolute;
12870let accessSize = HalfWordAccess;
12871let isPredicatedNew = 1;
12872let mayLoad = 1;
12873let isExtended = 1;
12874let BaseOpcode = "L4_loadrh_abs";
12875let CextOpcode = "L2_loadrh";
12876let DecoderNamespace = "MustExtend";
12877let isExtendable = 1;
12878let opExtendable = 2;
12879let isExtentSigned = 0;
12880let opExtentBits = 6;
12881let opExtentAlign = 0;
12882}
12883def L4_ploadrhfnew_rr : HInst<
12884(outs IntRegs:$Rd32),
12885(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12886"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12887tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12888let Inst{31-21} = 0b00110011010;
12889let isPredicated = 1;
12890let isPredicatedFalse = 1;
12891let hasNewValue = 1;
12892let opNewValue = 0;
12893let addrMode = BaseRegOffset;
12894let accessSize = HalfWordAccess;
12895let isPredicatedNew = 1;
12896let mayLoad = 1;
12897let BaseOpcode = "L4_loadrh_rr";
12898let CextOpcode = "L2_loadrh";
12899let InputType = "reg";
12900}
12901def L4_ploadrht_abs : HInst<
12902(outs IntRegs:$Rd32),
12903(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12904"if ($Pt4) $Rd32 = memh(#$Ii)",
12905tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12906let Inst{7-5} = 0b100;
12907let Inst{13-11} = 0b100;
12908let Inst{31-21} = 0b10011111010;
12909let isPredicated = 1;
12910let hasNewValue = 1;
12911let opNewValue = 0;
12912let addrMode = Absolute;
12913let accessSize = HalfWordAccess;
12914let mayLoad = 1;
12915let isExtended = 1;
12916let BaseOpcode = "L4_loadrh_abs";
12917let CextOpcode = "L2_loadrh";
12918let DecoderNamespace = "MustExtend";
12919let isExtendable = 1;
12920let opExtendable = 2;
12921let isExtentSigned = 0;
12922let opExtentBits = 6;
12923let opExtentAlign = 0;
12924}
12925def L4_ploadrht_rr : HInst<
12926(outs IntRegs:$Rd32),
12927(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12928"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12929tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12930let Inst{31-21} = 0b00110000010;
12931let isPredicated = 1;
12932let hasNewValue = 1;
12933let opNewValue = 0;
12934let addrMode = BaseRegOffset;
12935let accessSize = HalfWordAccess;
12936let mayLoad = 1;
12937let BaseOpcode = "L4_loadrh_rr";
12938let CextOpcode = "L2_loadrh";
12939let InputType = "reg";
12940}
12941def L4_ploadrhtnew_abs : HInst<
12942(outs IntRegs:$Rd32),
12943(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12944"if ($Pt4.new) $Rd32 = memh(#$Ii)",
12945tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12946let Inst{7-5} = 0b100;
12947let Inst{13-11} = 0b110;
12948let Inst{31-21} = 0b10011111010;
12949let isPredicated = 1;
12950let hasNewValue = 1;
12951let opNewValue = 0;
12952let addrMode = Absolute;
12953let accessSize = HalfWordAccess;
12954let isPredicatedNew = 1;
12955let mayLoad = 1;
12956let isExtended = 1;
12957let BaseOpcode = "L4_loadrh_abs";
12958let CextOpcode = "L2_loadrh";
12959let DecoderNamespace = "MustExtend";
12960let isExtendable = 1;
12961let opExtendable = 2;
12962let isExtentSigned = 0;
12963let opExtentBits = 6;
12964let opExtentAlign = 0;
12965}
12966def L4_ploadrhtnew_rr : HInst<
12967(outs IntRegs:$Rd32),
12968(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12969"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12970tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12971let Inst{31-21} = 0b00110010010;
12972let isPredicated = 1;
12973let hasNewValue = 1;
12974let opNewValue = 0;
12975let addrMode = BaseRegOffset;
12976let accessSize = HalfWordAccess;
12977let isPredicatedNew = 1;
12978let mayLoad = 1;
12979let BaseOpcode = "L4_loadrh_rr";
12980let CextOpcode = "L2_loadrh";
12981let InputType = "reg";
12982}
12983def L4_ploadrif_abs : HInst<
12984(outs IntRegs:$Rd32),
12985(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12986"if (!$Pt4) $Rd32 = memw(#$Ii)",
12987tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12988let Inst{7-5} = 0b100;
12989let Inst{13-11} = 0b101;
12990let Inst{31-21} = 0b10011111100;
12991let isPredicated = 1;
12992let isPredicatedFalse = 1;
12993let hasNewValue = 1;
12994let opNewValue = 0;
12995let addrMode = Absolute;
12996let accessSize = WordAccess;
12997let mayLoad = 1;
12998let isExtended = 1;
12999let BaseOpcode = "L4_loadri_abs";
13000let CextOpcode = "L2_loadri";
13001let DecoderNamespace = "MustExtend";
13002let isExtendable = 1;
13003let opExtendable = 2;
13004let isExtentSigned = 0;
13005let opExtentBits = 6;
13006let opExtentAlign = 0;
13007}
13008def L4_ploadrif_rr : HInst<
13009(outs IntRegs:$Rd32),
13010(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13011"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13012tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13013let Inst{31-21} = 0b00110001100;
13014let isPredicated = 1;
13015let isPredicatedFalse = 1;
13016let hasNewValue = 1;
13017let opNewValue = 0;
13018let addrMode = BaseRegOffset;
13019let accessSize = WordAccess;
13020let mayLoad = 1;
13021let BaseOpcode = "L4_loadri_rr";
13022let CextOpcode = "L2_loadri";
13023let InputType = "reg";
13024}
13025def L4_ploadrifnew_abs : HInst<
13026(outs IntRegs:$Rd32),
13027(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13028"if (!$Pt4.new) $Rd32 = memw(#$Ii)",
13029tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13030let Inst{7-5} = 0b100;
13031let Inst{13-11} = 0b111;
13032let Inst{31-21} = 0b10011111100;
13033let isPredicated = 1;
13034let isPredicatedFalse = 1;
13035let hasNewValue = 1;
13036let opNewValue = 0;
13037let addrMode = Absolute;
13038let accessSize = WordAccess;
13039let isPredicatedNew = 1;
13040let mayLoad = 1;
13041let isExtended = 1;
13042let BaseOpcode = "L4_loadri_abs";
13043let CextOpcode = "L2_loadri";
13044let DecoderNamespace = "MustExtend";
13045let isExtendable = 1;
13046let opExtendable = 2;
13047let isExtentSigned = 0;
13048let opExtentBits = 6;
13049let opExtentAlign = 0;
13050}
13051def L4_ploadrifnew_rr : HInst<
13052(outs IntRegs:$Rd32),
13053(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13054"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13055tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13056let Inst{31-21} = 0b00110011100;
13057let isPredicated = 1;
13058let isPredicatedFalse = 1;
13059let hasNewValue = 1;
13060let opNewValue = 0;
13061let addrMode = BaseRegOffset;
13062let accessSize = WordAccess;
13063let isPredicatedNew = 1;
13064let mayLoad = 1;
13065let BaseOpcode = "L4_loadri_rr";
13066let CextOpcode = "L2_loadri";
13067let InputType = "reg";
13068}
13069def L4_ploadrit_abs : HInst<
13070(outs IntRegs:$Rd32),
13071(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13072"if ($Pt4) $Rd32 = memw(#$Ii)",
13073tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13074let Inst{7-5} = 0b100;
13075let Inst{13-11} = 0b100;
13076let Inst{31-21} = 0b10011111100;
13077let isPredicated = 1;
13078let hasNewValue = 1;
13079let opNewValue = 0;
13080let addrMode = Absolute;
13081let accessSize = WordAccess;
13082let mayLoad = 1;
13083let isExtended = 1;
13084let BaseOpcode = "L4_loadri_abs";
13085let CextOpcode = "L2_loadri";
13086let DecoderNamespace = "MustExtend";
13087let isExtendable = 1;
13088let opExtendable = 2;
13089let isExtentSigned = 0;
13090let opExtentBits = 6;
13091let opExtentAlign = 0;
13092}
13093def L4_ploadrit_rr : HInst<
13094(outs IntRegs:$Rd32),
13095(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13096"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13097tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13098let Inst{31-21} = 0b00110000100;
13099let isPredicated = 1;
13100let hasNewValue = 1;
13101let opNewValue = 0;
13102let addrMode = BaseRegOffset;
13103let accessSize = WordAccess;
13104let mayLoad = 1;
13105let BaseOpcode = "L4_loadri_rr";
13106let CextOpcode = "L2_loadri";
13107let InputType = "reg";
13108}
13109def L4_ploadritnew_abs : HInst<
13110(outs IntRegs:$Rd32),
13111(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13112"if ($Pt4.new) $Rd32 = memw(#$Ii)",
13113tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13114let Inst{7-5} = 0b100;
13115let Inst{13-11} = 0b110;
13116let Inst{31-21} = 0b10011111100;
13117let isPredicated = 1;
13118let hasNewValue = 1;
13119let opNewValue = 0;
13120let addrMode = Absolute;
13121let accessSize = WordAccess;
13122let isPredicatedNew = 1;
13123let mayLoad = 1;
13124let isExtended = 1;
13125let BaseOpcode = "L4_loadri_abs";
13126let CextOpcode = "L2_loadri";
13127let DecoderNamespace = "MustExtend";
13128let isExtendable = 1;
13129let opExtendable = 2;
13130let isExtentSigned = 0;
13131let opExtentBits = 6;
13132let opExtentAlign = 0;
13133}
13134def L4_ploadritnew_rr : HInst<
13135(outs IntRegs:$Rd32),
13136(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13137"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13138tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13139let Inst{31-21} = 0b00110010100;
13140let isPredicated = 1;
13141let hasNewValue = 1;
13142let opNewValue = 0;
13143let addrMode = BaseRegOffset;
13144let accessSize = WordAccess;
13145let isPredicatedNew = 1;
13146let mayLoad = 1;
13147let BaseOpcode = "L4_loadri_rr";
13148let CextOpcode = "L2_loadri";
13149let InputType = "reg";
13150}
13151def L4_ploadrubf_abs : HInst<
13152(outs IntRegs:$Rd32),
13153(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13154"if (!$Pt4) $Rd32 = memub(#$Ii)",
13155tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13156let Inst{7-5} = 0b100;
13157let Inst{13-11} = 0b101;
13158let Inst{31-21} = 0b10011111001;
13159let isPredicated = 1;
13160let isPredicatedFalse = 1;
13161let hasNewValue = 1;
13162let opNewValue = 0;
13163let addrMode = Absolute;
13164let accessSize = ByteAccess;
13165let mayLoad = 1;
13166let isExtended = 1;
13167let BaseOpcode = "L4_loadrub_abs";
13168let CextOpcode = "L2_loadrub";
13169let DecoderNamespace = "MustExtend";
13170let isExtendable = 1;
13171let opExtendable = 2;
13172let isExtentSigned = 0;
13173let opExtentBits = 6;
13174let opExtentAlign = 0;
13175}
13176def L4_ploadrubf_rr : HInst<
13177(outs IntRegs:$Rd32),
13178(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13179"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13180tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13181let Inst{31-21} = 0b00110001001;
13182let isPredicated = 1;
13183let isPredicatedFalse = 1;
13184let hasNewValue = 1;
13185let opNewValue = 0;
13186let addrMode = BaseRegOffset;
13187let accessSize = ByteAccess;
13188let mayLoad = 1;
13189let BaseOpcode = "L4_loadrub_rr";
13190let CextOpcode = "L2_loadrub";
13191let InputType = "reg";
13192}
13193def L4_ploadrubfnew_abs : HInst<
13194(outs IntRegs:$Rd32),
13195(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13196"if (!$Pt4.new) $Rd32 = memub(#$Ii)",
13197tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13198let Inst{7-5} = 0b100;
13199let Inst{13-11} = 0b111;
13200let Inst{31-21} = 0b10011111001;
13201let isPredicated = 1;
13202let isPredicatedFalse = 1;
13203let hasNewValue = 1;
13204let opNewValue = 0;
13205let addrMode = Absolute;
13206let accessSize = ByteAccess;
13207let isPredicatedNew = 1;
13208let mayLoad = 1;
13209let isExtended = 1;
13210let BaseOpcode = "L4_loadrub_abs";
13211let CextOpcode = "L2_loadrub";
13212let DecoderNamespace = "MustExtend";
13213let isExtendable = 1;
13214let opExtendable = 2;
13215let isExtentSigned = 0;
13216let opExtentBits = 6;
13217let opExtentAlign = 0;
13218}
13219def L4_ploadrubfnew_rr : HInst<
13220(outs IntRegs:$Rd32),
13221(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13222"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13223tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13224let Inst{31-21} = 0b00110011001;
13225let isPredicated = 1;
13226let isPredicatedFalse = 1;
13227let hasNewValue = 1;
13228let opNewValue = 0;
13229let addrMode = BaseRegOffset;
13230let accessSize = ByteAccess;
13231let isPredicatedNew = 1;
13232let mayLoad = 1;
13233let BaseOpcode = "L4_loadrub_rr";
13234let CextOpcode = "L2_loadrub";
13235let InputType = "reg";
13236}
13237def L4_ploadrubt_abs : HInst<
13238(outs IntRegs:$Rd32),
13239(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13240"if ($Pt4) $Rd32 = memub(#$Ii)",
13241tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13242let Inst{7-5} = 0b100;
13243let Inst{13-11} = 0b100;
13244let Inst{31-21} = 0b10011111001;
13245let isPredicated = 1;
13246let hasNewValue = 1;
13247let opNewValue = 0;
13248let addrMode = Absolute;
13249let accessSize = ByteAccess;
13250let mayLoad = 1;
13251let isExtended = 1;
13252let BaseOpcode = "L4_loadrub_abs";
13253let CextOpcode = "L2_loadrub";
13254let DecoderNamespace = "MustExtend";
13255let isExtendable = 1;
13256let opExtendable = 2;
13257let isExtentSigned = 0;
13258let opExtentBits = 6;
13259let opExtentAlign = 0;
13260}
13261def L4_ploadrubt_rr : HInst<
13262(outs IntRegs:$Rd32),
13263(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13264"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13265tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13266let Inst{31-21} = 0b00110000001;
13267let isPredicated = 1;
13268let hasNewValue = 1;
13269let opNewValue = 0;
13270let addrMode = BaseRegOffset;
13271let accessSize = ByteAccess;
13272let mayLoad = 1;
13273let BaseOpcode = "L4_loadrub_rr";
13274let CextOpcode = "L2_loadrub";
13275let InputType = "reg";
13276}
13277def L4_ploadrubtnew_abs : HInst<
13278(outs IntRegs:$Rd32),
13279(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13280"if ($Pt4.new) $Rd32 = memub(#$Ii)",
13281tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13282let Inst{7-5} = 0b100;
13283let Inst{13-11} = 0b110;
13284let Inst{31-21} = 0b10011111001;
13285let isPredicated = 1;
13286let hasNewValue = 1;
13287let opNewValue = 0;
13288let addrMode = Absolute;
13289let accessSize = ByteAccess;
13290let isPredicatedNew = 1;
13291let mayLoad = 1;
13292let isExtended = 1;
13293let BaseOpcode = "L4_loadrub_abs";
13294let CextOpcode = "L2_loadrub";
13295let DecoderNamespace = "MustExtend";
13296let isExtendable = 1;
13297let opExtendable = 2;
13298let isExtentSigned = 0;
13299let opExtentBits = 6;
13300let opExtentAlign = 0;
13301}
13302def L4_ploadrubtnew_rr : HInst<
13303(outs IntRegs:$Rd32),
13304(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13305"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13306tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13307let Inst{31-21} = 0b00110010001;
13308let isPredicated = 1;
13309let hasNewValue = 1;
13310let opNewValue = 0;
13311let addrMode = BaseRegOffset;
13312let accessSize = ByteAccess;
13313let isPredicatedNew = 1;
13314let mayLoad = 1;
13315let BaseOpcode = "L4_loadrub_rr";
13316let CextOpcode = "L2_loadrub";
13317let InputType = "reg";
13318}
13319def L4_ploadruhf_abs : HInst<
13320(outs IntRegs:$Rd32),
13321(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13322"if (!$Pt4) $Rd32 = memuh(#$Ii)",
13323tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13324let Inst{7-5} = 0b100;
13325let Inst{13-11} = 0b101;
13326let Inst{31-21} = 0b10011111011;
13327let isPredicated = 1;
13328let isPredicatedFalse = 1;
13329let hasNewValue = 1;
13330let opNewValue = 0;
13331let addrMode = Absolute;
13332let accessSize = HalfWordAccess;
13333let mayLoad = 1;
13334let isExtended = 1;
13335let BaseOpcode = "L4_loadruh_abs";
13336let CextOpcode = "L2_loadruh";
13337let DecoderNamespace = "MustExtend";
13338let isExtendable = 1;
13339let opExtendable = 2;
13340let isExtentSigned = 0;
13341let opExtentBits = 6;
13342let opExtentAlign = 0;
13343}
13344def L4_ploadruhf_rr : HInst<
13345(outs IntRegs:$Rd32),
13346(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13347"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13348tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13349let Inst{31-21} = 0b00110001011;
13350let isPredicated = 1;
13351let isPredicatedFalse = 1;
13352let hasNewValue = 1;
13353let opNewValue = 0;
13354let addrMode = BaseRegOffset;
13355let accessSize = HalfWordAccess;
13356let mayLoad = 1;
13357let BaseOpcode = "L4_loadruh_rr";
13358let CextOpcode = "L2_loadruh";
13359let InputType = "reg";
13360}
13361def L4_ploadruhfnew_abs : HInst<
13362(outs IntRegs:$Rd32),
13363(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13364"if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
13365tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13366let Inst{7-5} = 0b100;
13367let Inst{13-11} = 0b111;
13368let Inst{31-21} = 0b10011111011;
13369let isPredicated = 1;
13370let isPredicatedFalse = 1;
13371let hasNewValue = 1;
13372let opNewValue = 0;
13373let addrMode = Absolute;
13374let accessSize = HalfWordAccess;
13375let isPredicatedNew = 1;
13376let mayLoad = 1;
13377let isExtended = 1;
13378let BaseOpcode = "L4_loadruh_abs";
13379let CextOpcode = "L2_loadruh";
13380let DecoderNamespace = "MustExtend";
13381let isExtendable = 1;
13382let opExtendable = 2;
13383let isExtentSigned = 0;
13384let opExtentBits = 6;
13385let opExtentAlign = 0;
13386}
13387def L4_ploadruhfnew_rr : HInst<
13388(outs IntRegs:$Rd32),
13389(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13390"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13391tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13392let Inst{31-21} = 0b00110011011;
13393let isPredicated = 1;
13394let isPredicatedFalse = 1;
13395let hasNewValue = 1;
13396let opNewValue = 0;
13397let addrMode = BaseRegOffset;
13398let accessSize = HalfWordAccess;
13399let isPredicatedNew = 1;
13400let mayLoad = 1;
13401let BaseOpcode = "L4_loadruh_rr";
13402let CextOpcode = "L2_loadruh";
13403let InputType = "reg";
13404}
13405def L4_ploadruht_abs : HInst<
13406(outs IntRegs:$Rd32),
13407(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13408"if ($Pt4) $Rd32 = memuh(#$Ii)",
13409tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13410let Inst{7-5} = 0b100;
13411let Inst{13-11} = 0b100;
13412let Inst{31-21} = 0b10011111011;
13413let isPredicated = 1;
13414let hasNewValue = 1;
13415let opNewValue = 0;
13416let addrMode = Absolute;
13417let accessSize = HalfWordAccess;
13418let mayLoad = 1;
13419let isExtended = 1;
13420let BaseOpcode = "L4_loadruh_abs";
13421let CextOpcode = "L2_loadruh";
13422let DecoderNamespace = "MustExtend";
13423let isExtendable = 1;
13424let opExtendable = 2;
13425let isExtentSigned = 0;
13426let opExtentBits = 6;
13427let opExtentAlign = 0;
13428}
13429def L4_ploadruht_rr : HInst<
13430(outs IntRegs:$Rd32),
13431(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13432"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13433tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13434let Inst{31-21} = 0b00110000011;
13435let isPredicated = 1;
13436let hasNewValue = 1;
13437let opNewValue = 0;
13438let addrMode = BaseRegOffset;
13439let accessSize = HalfWordAccess;
13440let mayLoad = 1;
13441let BaseOpcode = "L4_loadruh_rr";
13442let CextOpcode = "L2_loadruh";
13443let InputType = "reg";
13444}
13445def L4_ploadruhtnew_abs : HInst<
13446(outs IntRegs:$Rd32),
13447(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13448"if ($Pt4.new) $Rd32 = memuh(#$Ii)",
13449tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13450let Inst{7-5} = 0b100;
13451let Inst{13-11} = 0b110;
13452let Inst{31-21} = 0b10011111011;
13453let isPredicated = 1;
13454let hasNewValue = 1;
13455let opNewValue = 0;
13456let addrMode = Absolute;
13457let accessSize = HalfWordAccess;
13458let isPredicatedNew = 1;
13459let mayLoad = 1;
13460let isExtended = 1;
13461let BaseOpcode = "L4_loadruh_abs";
13462let CextOpcode = "L2_loadruh";
13463let DecoderNamespace = "MustExtend";
13464let isExtendable = 1;
13465let opExtendable = 2;
13466let isExtentSigned = 0;
13467let opExtentBits = 6;
13468let opExtentAlign = 0;
13469}
13470def L4_ploadruhtnew_rr : HInst<
13471(outs IntRegs:$Rd32),
13472(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13473"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13474tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13475let Inst{31-21} = 0b00110010011;
13476let isPredicated = 1;
13477let hasNewValue = 1;
13478let opNewValue = 0;
13479let addrMode = BaseRegOffset;
13480let accessSize = HalfWordAccess;
13481let isPredicatedNew = 1;
13482let mayLoad = 1;
13483let BaseOpcode = "L4_loadruh_rr";
13484let CextOpcode = "L2_loadruh";
13485let InputType = "reg";
13486}
13487def L4_return : HInst<
13488(outs DoubleRegs:$Rdd32),
13489(ins IntRegs:$Rs32),
13490"$Rdd32 = dealloc_return($Rs32):raw",
13491tc_40d64c94, TypeLD>, Enc_3a3d62, PredNewRel {
13492let Inst{13-5} = 0b000000000;
13493let Inst{31-21} = 0b10010110000;
13494let isTerminator = 1;
13495let isIndirectBranch = 1;
13496let accessSize = DoubleWordAccess;
13497let mayLoad = 1;
13498let cofMax1 = 1;
13499let isRestrictNoSlot1Store = 1;
13500let isReturn = 1;
13501let Uses = [FRAMEKEY];
13502let Defs = [PC, R29];
13503let BaseOpcode = "L4_return";
13504let isBarrier = 1;
13505let isPredicable = 1;
13506let isTaken = 1;
13507}
13508def L4_return_f : HInst<
13509(outs DoubleRegs:$Rdd32),
13510(ins PredRegs:$Pv4, IntRegs:$Rs32),
13511"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13512tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13513let Inst{7-5} = 0b000;
13514let Inst{13-10} = 0b1100;
13515let Inst{31-21} = 0b10010110000;
13516let isPredicated = 1;
13517let isPredicatedFalse = 1;
13518let isTerminator = 1;
13519let isIndirectBranch = 1;
13520let accessSize = DoubleWordAccess;
13521let mayLoad = 1;
13522let cofMax1 = 1;
13523let isRestrictNoSlot1Store = 1;
13524let isReturn = 1;
13525let Uses = [FRAMEKEY];
13526let Defs = [PC, R29];
13527let BaseOpcode = "L4_return";
13528let isTaken = Inst{12};
13529}
13530def L4_return_fnew_pnt : HInst<
13531(outs DoubleRegs:$Rdd32),
13532(ins PredRegs:$Pv4, IntRegs:$Rs32),
13533"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13534tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13535let Inst{7-5} = 0b000;
13536let Inst{13-10} = 0b1010;
13537let Inst{31-21} = 0b10010110000;
13538let isPredicated = 1;
13539let isPredicatedFalse = 1;
13540let isTerminator = 1;
13541let isIndirectBranch = 1;
13542let accessSize = DoubleWordAccess;
13543let isPredicatedNew = 1;
13544let mayLoad = 1;
13545let cofMax1 = 1;
13546let isRestrictNoSlot1Store = 1;
13547let isReturn = 1;
13548let Uses = [FRAMEKEY];
13549let Defs = [PC, R29];
13550let BaseOpcode = "L4_return";
13551let isTaken = Inst{12};
13552}
13553def L4_return_fnew_pt : HInst<
13554(outs DoubleRegs:$Rdd32),
13555(ins PredRegs:$Pv4, IntRegs:$Rs32),
13556"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13557tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13558let Inst{7-5} = 0b000;
13559let Inst{13-10} = 0b1110;
13560let Inst{31-21} = 0b10010110000;
13561let isPredicated = 1;
13562let isPredicatedFalse = 1;
13563let isTerminator = 1;
13564let isIndirectBranch = 1;
13565let accessSize = DoubleWordAccess;
13566let isPredicatedNew = 1;
13567let mayLoad = 1;
13568let cofMax1 = 1;
13569let isRestrictNoSlot1Store = 1;
13570let isReturn = 1;
13571let Uses = [FRAMEKEY];
13572let Defs = [PC, R29];
13573let BaseOpcode = "L4_return";
13574let isTaken = Inst{12};
13575}
13576def L4_return_map_to_raw_f : HInst<
13577(outs),
13578(ins PredRegs:$Pv4),
13579"if (!$Pv4) dealloc_return",
13580tc_df5d53f9, TypeMAPPING>, Requires<[HasV65]> {
13581let isPseudo = 1;
13582let isCodeGenOnly = 1;
13583}
13584def L4_return_map_to_raw_fnew_pnt : HInst<
13585(outs),
13586(ins PredRegs:$Pv4),
13587"if (!$Pv4.new) dealloc_return:nt",
13588tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13589let isPseudo = 1;
13590let isCodeGenOnly = 1;
13591}
13592def L4_return_map_to_raw_fnew_pt : HInst<
13593(outs),
13594(ins PredRegs:$Pv4),
13595"if (!$Pv4.new) dealloc_return:t",
13596tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13597let isPseudo = 1;
13598let isCodeGenOnly = 1;
13599}
13600def L4_return_map_to_raw_t : HInst<
13601(outs),
13602(ins PredRegs:$Pv4),
13603"if ($Pv4) dealloc_return",
13604tc_f38f92e1, TypeMAPPING>, Requires<[HasV65]> {
13605let isPseudo = 1;
13606let isCodeGenOnly = 1;
13607}
13608def L4_return_map_to_raw_tnew_pnt : HInst<
13609(outs),
13610(ins PredRegs:$Pv4),
13611"if ($Pv4.new) dealloc_return:nt",
13612tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13613let isPseudo = 1;
13614let isCodeGenOnly = 1;
13615}
13616def L4_return_map_to_raw_tnew_pt : HInst<
13617(outs),
13618(ins PredRegs:$Pv4),
13619"if ($Pv4.new) dealloc_return:t",
13620tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13621let isPseudo = 1;
13622let isCodeGenOnly = 1;
13623}
13624def L4_return_t : HInst<
13625(outs DoubleRegs:$Rdd32),
13626(ins PredRegs:$Pv4, IntRegs:$Rs32),
13627"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13628tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13629let Inst{7-5} = 0b000;
13630let Inst{13-10} = 0b0100;
13631let Inst{31-21} = 0b10010110000;
13632let isPredicated = 1;
13633let isTerminator = 1;
13634let isIndirectBranch = 1;
13635let accessSize = DoubleWordAccess;
13636let mayLoad = 1;
13637let cofMax1 = 1;
13638let isRestrictNoSlot1Store = 1;
13639let isReturn = 1;
13640let Uses = [FRAMEKEY];
13641let Defs = [PC, R29];
13642let BaseOpcode = "L4_return";
13643let isTaken = Inst{12};
13644}
13645def L4_return_tnew_pnt : HInst<
13646(outs DoubleRegs:$Rdd32),
13647(ins PredRegs:$Pv4, IntRegs:$Rs32),
13648"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13649tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13650let Inst{7-5} = 0b000;
13651let Inst{13-10} = 0b0010;
13652let Inst{31-21} = 0b10010110000;
13653let isPredicated = 1;
13654let isTerminator = 1;
13655let isIndirectBranch = 1;
13656let accessSize = DoubleWordAccess;
13657let isPredicatedNew = 1;
13658let mayLoad = 1;
13659let cofMax1 = 1;
13660let isRestrictNoSlot1Store = 1;
13661let isReturn = 1;
13662let Uses = [FRAMEKEY];
13663let Defs = [PC, R29];
13664let BaseOpcode = "L4_return";
13665let isTaken = Inst{12};
13666}
13667def L4_return_tnew_pt : HInst<
13668(outs DoubleRegs:$Rdd32),
13669(ins PredRegs:$Pv4, IntRegs:$Rs32),
13670"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13671tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13672let Inst{7-5} = 0b000;
13673let Inst{13-10} = 0b0110;
13674let Inst{31-21} = 0b10010110000;
13675let isPredicated = 1;
13676let isTerminator = 1;
13677let isIndirectBranch = 1;
13678let accessSize = DoubleWordAccess;
13679let isPredicatedNew = 1;
13680let mayLoad = 1;
13681let cofMax1 = 1;
13682let isRestrictNoSlot1Store = 1;
13683let isReturn = 1;
13684let Uses = [FRAMEKEY];
13685let Defs = [PC, R29];
13686let BaseOpcode = "L4_return";
13687let isTaken = Inst{12};
13688}
13689def L4_sub_memopb_io : HInst<
13690(outs),
13691(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
13692"memb($Rs32+#$Ii) -= $Rt32",
13693tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
13694let Inst{6-5} = 0b01;
13695let Inst{13-13} = 0b0;
13696let Inst{31-21} = 0b00111110000;
13697let addrMode = BaseImmOffset;
13698let accessSize = ByteAccess;
13699let mayLoad = 1;
13700let isRestrictNoSlot1Store = 1;
13701let mayStore = 1;
13702let isExtendable = 1;
13703let opExtendable = 1;
13704let isExtentSigned = 0;
13705let opExtentBits = 6;
13706let opExtentAlign = 0;
13707}
13708def L4_sub_memopb_zomap : HInst<
13709(outs),
13710(ins IntRegs:$Rs32, IntRegs:$Rt32),
13711"memb($Rs32) -= $Rt32",
13712tc_9bcfb2ee, TypeMAPPING> {
13713let isPseudo = 1;
13714let isCodeGenOnly = 1;
13715}
13716def L4_sub_memoph_io : HInst<
13717(outs),
13718(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
13719"memh($Rs32+#$Ii) -= $Rt32",
13720tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
13721let Inst{6-5} = 0b01;
13722let Inst{13-13} = 0b0;
13723let Inst{31-21} = 0b00111110001;
13724let addrMode = BaseImmOffset;
13725let accessSize = HalfWordAccess;
13726let mayLoad = 1;
13727let isRestrictNoSlot1Store = 1;
13728let mayStore = 1;
13729let isExtendable = 1;
13730let opExtendable = 1;
13731let isExtentSigned = 0;
13732let opExtentBits = 7;
13733let opExtentAlign = 1;
13734}
13735def L4_sub_memoph_zomap : HInst<
13736(outs),
13737(ins IntRegs:$Rs32, IntRegs:$Rt32),
13738"memh($Rs32) -= $Rt32",
13739tc_9bcfb2ee, TypeMAPPING> {
13740let isPseudo = 1;
13741let isCodeGenOnly = 1;
13742}
13743def L4_sub_memopw_io : HInst<
13744(outs),
13745(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
13746"memw($Rs32+#$Ii) -= $Rt32",
13747tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
13748let Inst{6-5} = 0b01;
13749let Inst{13-13} = 0b0;
13750let Inst{31-21} = 0b00111110010;
13751let addrMode = BaseImmOffset;
13752let accessSize = WordAccess;
13753let mayLoad = 1;
13754let isRestrictNoSlot1Store = 1;
13755let mayStore = 1;
13756let isExtendable = 1;
13757let opExtendable = 1;
13758let isExtentSigned = 0;
13759let opExtentBits = 8;
13760let opExtentAlign = 2;
13761}
13762def L4_sub_memopw_zomap : HInst<
13763(outs),
13764(ins IntRegs:$Rs32, IntRegs:$Rt32),
13765"memw($Rs32) -= $Rt32",
13766tc_9bcfb2ee, TypeMAPPING> {
13767let isPseudo = 1;
13768let isCodeGenOnly = 1;
13769}
13770def L6_deallocframe_map_to_raw : HInst<
13771(outs),
13772(ins),
13773"deallocframe",
13774tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> {
13775let isPseudo = 1;
13776let isCodeGenOnly = 1;
13777}
13778def L6_memcpy : HInst<
13779(outs),
13780(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
13781"memcpy($Rs32,$Rt32,$Mu2)",
13782tc_5944960d, TypeLD>, Enc_a75aa6, Requires<[HasV66]> {
13783let Inst{7-0} = 0b01000000;
13784let Inst{31-21} = 0b10010010000;
13785let mayLoad = 1;
13786let isSolo = 1;
13787let mayStore = 1;
13788}
13789def L6_return_map_to_raw : HInst<
13790(outs),
13791(ins),
13792"dealloc_return",
13793tc_40d64c94, TypeMAPPING>, Requires<[HasV65]> {
13794let isPseudo = 1;
13795let isCodeGenOnly = 1;
13796}
13797def M2_acci : HInst<
13798(outs IntRegs:$Rx32),
13799(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13800"$Rx32 += add($Rs32,$Rt32)",
13801tc_2c13e7f5, TypeM>, Enc_2ae154, ImmRegRel {
13802let Inst{7-5} = 0b001;
13803let Inst{13-13} = 0b0;
13804let Inst{31-21} = 0b11101111000;
13805let hasNewValue = 1;
13806let opNewValue = 0;
13807let prefersSlot3 = 1;
13808let CextOpcode = "M2_acci";
13809let InputType = "reg";
13810let Constraints = "$Rx32 = $Rx32in";
13811}
13812def M2_accii : HInst<
13813(outs IntRegs:$Rx32),
13814(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
13815"$Rx32 += add($Rs32,#$Ii)",
13816tc_2c13e7f5, TypeM>, Enc_c90aca, ImmRegRel {
13817let Inst{13-13} = 0b0;
13818let Inst{31-21} = 0b11100010000;
13819let hasNewValue = 1;
13820let opNewValue = 0;
13821let prefersSlot3 = 1;
13822let CextOpcode = "M2_acci";
13823let InputType = "imm";
13824let isExtendable = 1;
13825let opExtendable = 3;
13826let isExtentSigned = 1;
13827let opExtentBits = 8;
13828let opExtentAlign = 0;
13829let Constraints = "$Rx32 = $Rx32in";
13830}
13831def M2_cmaci_s0 : HInst<
13832(outs DoubleRegs:$Rxx32),
13833(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13834"$Rxx32 += cmpyi($Rs32,$Rt32)",
13835tc_7f8ae742, TypeM>, Enc_61f0b0 {
13836let Inst{7-5} = 0b001;
13837let Inst{13-13} = 0b0;
13838let Inst{31-21} = 0b11100111000;
13839let prefersSlot3 = 1;
13840let Constraints = "$Rxx32 = $Rxx32in";
13841}
13842def M2_cmacr_s0 : HInst<
13843(outs DoubleRegs:$Rxx32),
13844(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13845"$Rxx32 += cmpyr($Rs32,$Rt32)",
13846tc_7f8ae742, TypeM>, Enc_61f0b0 {
13847let Inst{7-5} = 0b010;
13848let Inst{13-13} = 0b0;
13849let Inst{31-21} = 0b11100111000;
13850let prefersSlot3 = 1;
13851let Constraints = "$Rxx32 = $Rxx32in";
13852}
13853def M2_cmacs_s0 : HInst<
13854(outs DoubleRegs:$Rxx32),
13855(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13856"$Rxx32 += cmpy($Rs32,$Rt32):sat",
13857tc_7f8ae742, TypeM>, Enc_61f0b0 {
13858let Inst{7-5} = 0b110;
13859let Inst{13-13} = 0b0;
13860let Inst{31-21} = 0b11100111000;
13861let prefersSlot3 = 1;
13862let Defs = [USR_OVF];
13863let Constraints = "$Rxx32 = $Rxx32in";
13864}
13865def M2_cmacs_s1 : HInst<
13866(outs DoubleRegs:$Rxx32),
13867(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13868"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
13869tc_7f8ae742, TypeM>, Enc_61f0b0 {
13870let Inst{7-5} = 0b110;
13871let Inst{13-13} = 0b0;
13872let Inst{31-21} = 0b11100111100;
13873let prefersSlot3 = 1;
13874let Defs = [USR_OVF];
13875let Constraints = "$Rxx32 = $Rxx32in";
13876}
13877def M2_cmacsc_s0 : HInst<
13878(outs DoubleRegs:$Rxx32),
13879(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13880"$Rxx32 += cmpy($Rs32,$Rt32*):sat",
13881tc_7f8ae742, TypeM>, Enc_61f0b0 {
13882let Inst{7-5} = 0b110;
13883let Inst{13-13} = 0b0;
13884let Inst{31-21} = 0b11100111010;
13885let prefersSlot3 = 1;
13886let Defs = [USR_OVF];
13887let Constraints = "$Rxx32 = $Rxx32in";
13888}
13889def M2_cmacsc_s1 : HInst<
13890(outs DoubleRegs:$Rxx32),
13891(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13892"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
13893tc_7f8ae742, TypeM>, Enc_61f0b0 {
13894let Inst{7-5} = 0b110;
13895let Inst{13-13} = 0b0;
13896let Inst{31-21} = 0b11100111110;
13897let prefersSlot3 = 1;
13898let Defs = [USR_OVF];
13899let Constraints = "$Rxx32 = $Rxx32in";
13900}
13901def M2_cmpyi_s0 : HInst<
13902(outs DoubleRegs:$Rdd32),
13903(ins IntRegs:$Rs32, IntRegs:$Rt32),
13904"$Rdd32 = cmpyi($Rs32,$Rt32)",
13905tc_c21d7447, TypeM>, Enc_be32a5 {
13906let Inst{7-5} = 0b001;
13907let Inst{13-13} = 0b0;
13908let Inst{31-21} = 0b11100101000;
13909let prefersSlot3 = 1;
13910}
13911def M2_cmpyr_s0 : HInst<
13912(outs DoubleRegs:$Rdd32),
13913(ins IntRegs:$Rs32, IntRegs:$Rt32),
13914"$Rdd32 = cmpyr($Rs32,$Rt32)",
13915tc_c21d7447, TypeM>, Enc_be32a5 {
13916let Inst{7-5} = 0b010;
13917let Inst{13-13} = 0b0;
13918let Inst{31-21} = 0b11100101000;
13919let prefersSlot3 = 1;
13920}
13921def M2_cmpyrs_s0 : HInst<
13922(outs IntRegs:$Rd32),
13923(ins IntRegs:$Rs32, IntRegs:$Rt32),
13924"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
13925tc_c21d7447, TypeM>, Enc_5ab2be {
13926let Inst{7-5} = 0b110;
13927let Inst{13-13} = 0b0;
13928let Inst{31-21} = 0b11101101001;
13929let hasNewValue = 1;
13930let opNewValue = 0;
13931let prefersSlot3 = 1;
13932let Defs = [USR_OVF];
13933}
13934def M2_cmpyrs_s1 : HInst<
13935(outs IntRegs:$Rd32),
13936(ins IntRegs:$Rs32, IntRegs:$Rt32),
13937"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
13938tc_c21d7447, TypeM>, Enc_5ab2be {
13939let Inst{7-5} = 0b110;
13940let Inst{13-13} = 0b0;
13941let Inst{31-21} = 0b11101101101;
13942let hasNewValue = 1;
13943let opNewValue = 0;
13944let prefersSlot3 = 1;
13945let Defs = [USR_OVF];
13946}
13947def M2_cmpyrsc_s0 : HInst<
13948(outs IntRegs:$Rd32),
13949(ins IntRegs:$Rs32, IntRegs:$Rt32),
13950"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
13951tc_c21d7447, TypeM>, Enc_5ab2be {
13952let Inst{7-5} = 0b110;
13953let Inst{13-13} = 0b0;
13954let Inst{31-21} = 0b11101101011;
13955let hasNewValue = 1;
13956let opNewValue = 0;
13957let prefersSlot3 = 1;
13958let Defs = [USR_OVF];
13959}
13960def M2_cmpyrsc_s1 : HInst<
13961(outs IntRegs:$Rd32),
13962(ins IntRegs:$Rs32, IntRegs:$Rt32),
13963"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
13964tc_c21d7447, TypeM>, Enc_5ab2be {
13965let Inst{7-5} = 0b110;
13966let Inst{13-13} = 0b0;
13967let Inst{31-21} = 0b11101101111;
13968let hasNewValue = 1;
13969let opNewValue = 0;
13970let prefersSlot3 = 1;
13971let Defs = [USR_OVF];
13972}
13973def M2_cmpys_s0 : HInst<
13974(outs DoubleRegs:$Rdd32),
13975(ins IntRegs:$Rs32, IntRegs:$Rt32),
13976"$Rdd32 = cmpy($Rs32,$Rt32):sat",
13977tc_c21d7447, TypeM>, Enc_be32a5 {
13978let Inst{7-5} = 0b110;
13979let Inst{13-13} = 0b0;
13980let Inst{31-21} = 0b11100101000;
13981let prefersSlot3 = 1;
13982let Defs = [USR_OVF];
13983}
13984def M2_cmpys_s1 : HInst<
13985(outs DoubleRegs:$Rdd32),
13986(ins IntRegs:$Rs32, IntRegs:$Rt32),
13987"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
13988tc_c21d7447, TypeM>, Enc_be32a5 {
13989let Inst{7-5} = 0b110;
13990let Inst{13-13} = 0b0;
13991let Inst{31-21} = 0b11100101100;
13992let prefersSlot3 = 1;
13993let Defs = [USR_OVF];
13994}
13995def M2_cmpysc_s0 : HInst<
13996(outs DoubleRegs:$Rdd32),
13997(ins IntRegs:$Rs32, IntRegs:$Rt32),
13998"$Rdd32 = cmpy($Rs32,$Rt32*):sat",
13999tc_c21d7447, TypeM>, Enc_be32a5 {
14000let Inst{7-5} = 0b110;
14001let Inst{13-13} = 0b0;
14002let Inst{31-21} = 0b11100101010;
14003let prefersSlot3 = 1;
14004let Defs = [USR_OVF];
14005}
14006def M2_cmpysc_s1 : HInst<
14007(outs DoubleRegs:$Rdd32),
14008(ins IntRegs:$Rs32, IntRegs:$Rt32),
14009"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
14010tc_c21d7447, TypeM>, Enc_be32a5 {
14011let Inst{7-5} = 0b110;
14012let Inst{13-13} = 0b0;
14013let Inst{31-21} = 0b11100101110;
14014let prefersSlot3 = 1;
14015let Defs = [USR_OVF];
14016}
14017def M2_cnacs_s0 : HInst<
14018(outs DoubleRegs:$Rxx32),
14019(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14020"$Rxx32 -= cmpy($Rs32,$Rt32):sat",
14021tc_7f8ae742, TypeM>, Enc_61f0b0 {
14022let Inst{7-5} = 0b111;
14023let Inst{13-13} = 0b0;
14024let Inst{31-21} = 0b11100111000;
14025let prefersSlot3 = 1;
14026let Defs = [USR_OVF];
14027let Constraints = "$Rxx32 = $Rxx32in";
14028}
14029def M2_cnacs_s1 : HInst<
14030(outs DoubleRegs:$Rxx32),
14031(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14032"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
14033tc_7f8ae742, TypeM>, Enc_61f0b0 {
14034let Inst{7-5} = 0b111;
14035let Inst{13-13} = 0b0;
14036let Inst{31-21} = 0b11100111100;
14037let prefersSlot3 = 1;
14038let Defs = [USR_OVF];
14039let Constraints = "$Rxx32 = $Rxx32in";
14040}
14041def M2_cnacsc_s0 : HInst<
14042(outs DoubleRegs:$Rxx32),
14043(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14044"$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
14045tc_7f8ae742, TypeM>, Enc_61f0b0 {
14046let Inst{7-5} = 0b111;
14047let Inst{13-13} = 0b0;
14048let Inst{31-21} = 0b11100111010;
14049let prefersSlot3 = 1;
14050let Defs = [USR_OVF];
14051let Constraints = "$Rxx32 = $Rxx32in";
14052}
14053def M2_cnacsc_s1 : HInst<
14054(outs DoubleRegs:$Rxx32),
14055(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14056"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
14057tc_7f8ae742, TypeM>, Enc_61f0b0 {
14058let Inst{7-5} = 0b111;
14059let Inst{13-13} = 0b0;
14060let Inst{31-21} = 0b11100111110;
14061let prefersSlot3 = 1;
14062let Defs = [USR_OVF];
14063let Constraints = "$Rxx32 = $Rxx32in";
14064}
14065def M2_dpmpyss_acc_s0 : HInst<
14066(outs DoubleRegs:$Rxx32),
14067(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14068"$Rxx32 += mpy($Rs32,$Rt32)",
14069tc_7f8ae742, TypeM>, Enc_61f0b0 {
14070let Inst{7-5} = 0b000;
14071let Inst{13-13} = 0b0;
14072let Inst{31-21} = 0b11100111000;
14073let prefersSlot3 = 1;
14074let Constraints = "$Rxx32 = $Rxx32in";
14075}
14076def M2_dpmpyss_nac_s0 : HInst<
14077(outs DoubleRegs:$Rxx32),
14078(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14079"$Rxx32 -= mpy($Rs32,$Rt32)",
14080tc_7f8ae742, TypeM>, Enc_61f0b0 {
14081let Inst{7-5} = 0b000;
14082let Inst{13-13} = 0b0;
14083let Inst{31-21} = 0b11100111001;
14084let prefersSlot3 = 1;
14085let Constraints = "$Rxx32 = $Rxx32in";
14086}
14087def M2_dpmpyss_rnd_s0 : HInst<
14088(outs IntRegs:$Rd32),
14089(ins IntRegs:$Rs32, IntRegs:$Rt32),
14090"$Rd32 = mpy($Rs32,$Rt32):rnd",
14091tc_c21d7447, TypeM>, Enc_5ab2be {
14092let Inst{7-5} = 0b001;
14093let Inst{13-13} = 0b0;
14094let Inst{31-21} = 0b11101101001;
14095let hasNewValue = 1;
14096let opNewValue = 0;
14097let prefersSlot3 = 1;
14098}
14099def M2_dpmpyss_s0 : HInst<
14100(outs DoubleRegs:$Rdd32),
14101(ins IntRegs:$Rs32, IntRegs:$Rt32),
14102"$Rdd32 = mpy($Rs32,$Rt32)",
14103tc_c21d7447, TypeM>, Enc_be32a5 {
14104let Inst{7-5} = 0b000;
14105let Inst{13-13} = 0b0;
14106let Inst{31-21} = 0b11100101000;
14107let prefersSlot3 = 1;
14108}
14109def M2_dpmpyuu_acc_s0 : HInst<
14110(outs DoubleRegs:$Rxx32),
14111(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14112"$Rxx32 += mpyu($Rs32,$Rt32)",
14113tc_7f8ae742, TypeM>, Enc_61f0b0 {
14114let Inst{7-5} = 0b000;
14115let Inst{13-13} = 0b0;
14116let Inst{31-21} = 0b11100111010;
14117let prefersSlot3 = 1;
14118let Constraints = "$Rxx32 = $Rxx32in";
14119}
14120def M2_dpmpyuu_nac_s0 : HInst<
14121(outs DoubleRegs:$Rxx32),
14122(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14123"$Rxx32 -= mpyu($Rs32,$Rt32)",
14124tc_7f8ae742, TypeM>, Enc_61f0b0 {
14125let Inst{7-5} = 0b000;
14126let Inst{13-13} = 0b0;
14127let Inst{31-21} = 0b11100111011;
14128let prefersSlot3 = 1;
14129let Constraints = "$Rxx32 = $Rxx32in";
14130}
14131def M2_dpmpyuu_s0 : HInst<
14132(outs DoubleRegs:$Rdd32),
14133(ins IntRegs:$Rs32, IntRegs:$Rt32),
14134"$Rdd32 = mpyu($Rs32,$Rt32)",
14135tc_c21d7447, TypeM>, Enc_be32a5 {
14136let Inst{7-5} = 0b000;
14137let Inst{13-13} = 0b0;
14138let Inst{31-21} = 0b11100101010;
14139let prefersSlot3 = 1;
14140}
14141def M2_hmmpyh_rs1 : HInst<
14142(outs IntRegs:$Rd32),
14143(ins IntRegs:$Rs32, IntRegs:$Rt32),
14144"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
14145tc_c21d7447, TypeM>, Enc_5ab2be {
14146let Inst{7-5} = 0b100;
14147let Inst{13-13} = 0b0;
14148let Inst{31-21} = 0b11101101101;
14149let hasNewValue = 1;
14150let opNewValue = 0;
14151let prefersSlot3 = 1;
14152let Defs = [USR_OVF];
14153}
14154def M2_hmmpyh_s1 : HInst<
14155(outs IntRegs:$Rd32),
14156(ins IntRegs:$Rs32, IntRegs:$Rt32),
14157"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
14158tc_c21d7447, TypeM>, Enc_5ab2be {
14159let Inst{7-5} = 0b000;
14160let Inst{13-13} = 0b0;
14161let Inst{31-21} = 0b11101101101;
14162let hasNewValue = 1;
14163let opNewValue = 0;
14164let prefersSlot3 = 1;
14165let Defs = [USR_OVF];
14166}
14167def M2_hmmpyl_rs1 : HInst<
14168(outs IntRegs:$Rd32),
14169(ins IntRegs:$Rs32, IntRegs:$Rt32),
14170"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
14171tc_c21d7447, TypeM>, Enc_5ab2be {
14172let Inst{7-5} = 0b100;
14173let Inst{13-13} = 0b0;
14174let Inst{31-21} = 0b11101101111;
14175let hasNewValue = 1;
14176let opNewValue = 0;
14177let prefersSlot3 = 1;
14178let Defs = [USR_OVF];
14179}
14180def M2_hmmpyl_s1 : HInst<
14181(outs IntRegs:$Rd32),
14182(ins IntRegs:$Rs32, IntRegs:$Rt32),
14183"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
14184tc_c21d7447, TypeM>, Enc_5ab2be {
14185let Inst{7-5} = 0b001;
14186let Inst{13-13} = 0b0;
14187let Inst{31-21} = 0b11101101101;
14188let hasNewValue = 1;
14189let opNewValue = 0;
14190let prefersSlot3 = 1;
14191let Defs = [USR_OVF];
14192}
14193def M2_maci : HInst<
14194(outs IntRegs:$Rx32),
14195(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14196"$Rx32 += mpyi($Rs32,$Rt32)",
14197tc_7f8ae742, TypeM>, Enc_2ae154, ImmRegRel {
14198let Inst{7-5} = 0b000;
14199let Inst{13-13} = 0b0;
14200let Inst{31-21} = 0b11101111000;
14201let hasNewValue = 1;
14202let opNewValue = 0;
14203let prefersSlot3 = 1;
14204let CextOpcode = "M2_maci";
14205let InputType = "reg";
14206let Constraints = "$Rx32 = $Rx32in";
14207}
14208def M2_macsin : HInst<
14209(outs IntRegs:$Rx32),
14210(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14211"$Rx32 -= mpyi($Rs32,#$Ii)",
14212tc_a154b476, TypeM>, Enc_c90aca {
14213let Inst{13-13} = 0b0;
14214let Inst{31-21} = 0b11100001100;
14215let hasNewValue = 1;
14216let opNewValue = 0;
14217let prefersSlot3 = 1;
14218let InputType = "imm";
14219let isExtendable = 1;
14220let opExtendable = 3;
14221let isExtentSigned = 0;
14222let opExtentBits = 8;
14223let opExtentAlign = 0;
14224let Constraints = "$Rx32 = $Rx32in";
14225}
14226def M2_macsip : HInst<
14227(outs IntRegs:$Rx32),
14228(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14229"$Rx32 += mpyi($Rs32,#$Ii)",
14230tc_a154b476, TypeM>, Enc_c90aca, ImmRegRel {
14231let Inst{13-13} = 0b0;
14232let Inst{31-21} = 0b11100001000;
14233let hasNewValue = 1;
14234let opNewValue = 0;
14235let prefersSlot3 = 1;
14236let CextOpcode = "M2_maci";
14237let InputType = "imm";
14238let isExtendable = 1;
14239let opExtendable = 3;
14240let isExtentSigned = 0;
14241let opExtentBits = 8;
14242let opExtentAlign = 0;
14243let Constraints = "$Rx32 = $Rx32in";
14244}
14245def M2_mmachs_rs0 : HInst<
14246(outs DoubleRegs:$Rxx32),
14247(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14248"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
14249tc_7f8ae742, TypeM>, Enc_88c16c {
14250let Inst{7-5} = 0b111;
14251let Inst{13-13} = 0b0;
14252let Inst{31-21} = 0b11101010001;
14253let prefersSlot3 = 1;
14254let Defs = [USR_OVF];
14255let Constraints = "$Rxx32 = $Rxx32in";
14256}
14257def M2_mmachs_rs1 : HInst<
14258(outs DoubleRegs:$Rxx32),
14259(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14260"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14261tc_7f8ae742, TypeM>, Enc_88c16c {
14262let Inst{7-5} = 0b111;
14263let Inst{13-13} = 0b0;
14264let Inst{31-21} = 0b11101010101;
14265let prefersSlot3 = 1;
14266let Defs = [USR_OVF];
14267let Constraints = "$Rxx32 = $Rxx32in";
14268}
14269def M2_mmachs_s0 : HInst<
14270(outs DoubleRegs:$Rxx32),
14271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14272"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
14273tc_7f8ae742, TypeM>, Enc_88c16c {
14274let Inst{7-5} = 0b111;
14275let Inst{13-13} = 0b0;
14276let Inst{31-21} = 0b11101010000;
14277let prefersSlot3 = 1;
14278let Defs = [USR_OVF];
14279let Constraints = "$Rxx32 = $Rxx32in";
14280}
14281def M2_mmachs_s1 : HInst<
14282(outs DoubleRegs:$Rxx32),
14283(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14284"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
14285tc_7f8ae742, TypeM>, Enc_88c16c {
14286let Inst{7-5} = 0b111;
14287let Inst{13-13} = 0b0;
14288let Inst{31-21} = 0b11101010100;
14289let prefersSlot3 = 1;
14290let Defs = [USR_OVF];
14291let Constraints = "$Rxx32 = $Rxx32in";
14292}
14293def M2_mmacls_rs0 : HInst<
14294(outs DoubleRegs:$Rxx32),
14295(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14296"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
14297tc_7f8ae742, TypeM>, Enc_88c16c {
14298let Inst{7-5} = 0b101;
14299let Inst{13-13} = 0b0;
14300let Inst{31-21} = 0b11101010001;
14301let prefersSlot3 = 1;
14302let Defs = [USR_OVF];
14303let Constraints = "$Rxx32 = $Rxx32in";
14304}
14305def M2_mmacls_rs1 : HInst<
14306(outs DoubleRegs:$Rxx32),
14307(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14308"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14309tc_7f8ae742, TypeM>, Enc_88c16c {
14310let Inst{7-5} = 0b101;
14311let Inst{13-13} = 0b0;
14312let Inst{31-21} = 0b11101010101;
14313let prefersSlot3 = 1;
14314let Defs = [USR_OVF];
14315let Constraints = "$Rxx32 = $Rxx32in";
14316}
14317def M2_mmacls_s0 : HInst<
14318(outs DoubleRegs:$Rxx32),
14319(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14320"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
14321tc_7f8ae742, TypeM>, Enc_88c16c {
14322let Inst{7-5} = 0b101;
14323let Inst{13-13} = 0b0;
14324let Inst{31-21} = 0b11101010000;
14325let prefersSlot3 = 1;
14326let Defs = [USR_OVF];
14327let Constraints = "$Rxx32 = $Rxx32in";
14328}
14329def M2_mmacls_s1 : HInst<
14330(outs DoubleRegs:$Rxx32),
14331(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14332"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
14333tc_7f8ae742, TypeM>, Enc_88c16c {
14334let Inst{7-5} = 0b101;
14335let Inst{13-13} = 0b0;
14336let Inst{31-21} = 0b11101010100;
14337let prefersSlot3 = 1;
14338let Defs = [USR_OVF];
14339let Constraints = "$Rxx32 = $Rxx32in";
14340}
14341def M2_mmacuhs_rs0 : HInst<
14342(outs DoubleRegs:$Rxx32),
14343(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14344"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
14345tc_7f8ae742, TypeM>, Enc_88c16c {
14346let Inst{7-5} = 0b111;
14347let Inst{13-13} = 0b0;
14348let Inst{31-21} = 0b11101010011;
14349let prefersSlot3 = 1;
14350let Defs = [USR_OVF];
14351let Constraints = "$Rxx32 = $Rxx32in";
14352}
14353def M2_mmacuhs_rs1 : HInst<
14354(outs DoubleRegs:$Rxx32),
14355(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14356"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14357tc_7f8ae742, TypeM>, Enc_88c16c {
14358let Inst{7-5} = 0b111;
14359let Inst{13-13} = 0b0;
14360let Inst{31-21} = 0b11101010111;
14361let prefersSlot3 = 1;
14362let Defs = [USR_OVF];
14363let Constraints = "$Rxx32 = $Rxx32in";
14364}
14365def M2_mmacuhs_s0 : HInst<
14366(outs DoubleRegs:$Rxx32),
14367(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14368"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
14369tc_7f8ae742, TypeM>, Enc_88c16c {
14370let Inst{7-5} = 0b111;
14371let Inst{13-13} = 0b0;
14372let Inst{31-21} = 0b11101010010;
14373let prefersSlot3 = 1;
14374let Defs = [USR_OVF];
14375let Constraints = "$Rxx32 = $Rxx32in";
14376}
14377def M2_mmacuhs_s1 : HInst<
14378(outs DoubleRegs:$Rxx32),
14379(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14380"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
14381tc_7f8ae742, TypeM>, Enc_88c16c {
14382let Inst{7-5} = 0b111;
14383let Inst{13-13} = 0b0;
14384let Inst{31-21} = 0b11101010110;
14385let prefersSlot3 = 1;
14386let Defs = [USR_OVF];
14387let Constraints = "$Rxx32 = $Rxx32in";
14388}
14389def M2_mmaculs_rs0 : HInst<
14390(outs DoubleRegs:$Rxx32),
14391(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14392"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
14393tc_7f8ae742, TypeM>, Enc_88c16c {
14394let Inst{7-5} = 0b101;
14395let Inst{13-13} = 0b0;
14396let Inst{31-21} = 0b11101010011;
14397let prefersSlot3 = 1;
14398let Defs = [USR_OVF];
14399let Constraints = "$Rxx32 = $Rxx32in";
14400}
14401def M2_mmaculs_rs1 : HInst<
14402(outs DoubleRegs:$Rxx32),
14403(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14404"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14405tc_7f8ae742, TypeM>, Enc_88c16c {
14406let Inst{7-5} = 0b101;
14407let Inst{13-13} = 0b0;
14408let Inst{31-21} = 0b11101010111;
14409let prefersSlot3 = 1;
14410let Defs = [USR_OVF];
14411let Constraints = "$Rxx32 = $Rxx32in";
14412}
14413def M2_mmaculs_s0 : HInst<
14414(outs DoubleRegs:$Rxx32),
14415(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14416"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
14417tc_7f8ae742, TypeM>, Enc_88c16c {
14418let Inst{7-5} = 0b101;
14419let Inst{13-13} = 0b0;
14420let Inst{31-21} = 0b11101010010;
14421let prefersSlot3 = 1;
14422let Defs = [USR_OVF];
14423let Constraints = "$Rxx32 = $Rxx32in";
14424}
14425def M2_mmaculs_s1 : HInst<
14426(outs DoubleRegs:$Rxx32),
14427(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14428"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
14429tc_7f8ae742, TypeM>, Enc_88c16c {
14430let Inst{7-5} = 0b101;
14431let Inst{13-13} = 0b0;
14432let Inst{31-21} = 0b11101010110;
14433let prefersSlot3 = 1;
14434let Defs = [USR_OVF];
14435let Constraints = "$Rxx32 = $Rxx32in";
14436}
14437def M2_mmpyh_rs0 : HInst<
14438(outs DoubleRegs:$Rdd32),
14439(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14440"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
14441tc_c21d7447, TypeM>, Enc_a56825 {
14442let Inst{7-5} = 0b111;
14443let Inst{13-13} = 0b0;
14444let Inst{31-21} = 0b11101000001;
14445let prefersSlot3 = 1;
14446let Defs = [USR_OVF];
14447}
14448def M2_mmpyh_rs1 : HInst<
14449(outs DoubleRegs:$Rdd32),
14450(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14451"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14452tc_c21d7447, TypeM>, Enc_a56825 {
14453let Inst{7-5} = 0b111;
14454let Inst{13-13} = 0b0;
14455let Inst{31-21} = 0b11101000101;
14456let prefersSlot3 = 1;
14457let Defs = [USR_OVF];
14458}
14459def M2_mmpyh_s0 : HInst<
14460(outs DoubleRegs:$Rdd32),
14461(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14462"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
14463tc_c21d7447, TypeM>, Enc_a56825 {
14464let Inst{7-5} = 0b111;
14465let Inst{13-13} = 0b0;
14466let Inst{31-21} = 0b11101000000;
14467let prefersSlot3 = 1;
14468let Defs = [USR_OVF];
14469}
14470def M2_mmpyh_s1 : HInst<
14471(outs DoubleRegs:$Rdd32),
14472(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14473"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
14474tc_c21d7447, TypeM>, Enc_a56825 {
14475let Inst{7-5} = 0b111;
14476let Inst{13-13} = 0b0;
14477let Inst{31-21} = 0b11101000100;
14478let prefersSlot3 = 1;
14479let Defs = [USR_OVF];
14480}
14481def M2_mmpyl_rs0 : HInst<
14482(outs DoubleRegs:$Rdd32),
14483(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14484"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
14485tc_c21d7447, TypeM>, Enc_a56825 {
14486let Inst{7-5} = 0b101;
14487let Inst{13-13} = 0b0;
14488let Inst{31-21} = 0b11101000001;
14489let prefersSlot3 = 1;
14490let Defs = [USR_OVF];
14491}
14492def M2_mmpyl_rs1 : HInst<
14493(outs DoubleRegs:$Rdd32),
14494(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14495"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14496tc_c21d7447, TypeM>, Enc_a56825 {
14497let Inst{7-5} = 0b101;
14498let Inst{13-13} = 0b0;
14499let Inst{31-21} = 0b11101000101;
14500let prefersSlot3 = 1;
14501let Defs = [USR_OVF];
14502}
14503def M2_mmpyl_s0 : HInst<
14504(outs DoubleRegs:$Rdd32),
14505(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14506"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
14507tc_c21d7447, TypeM>, Enc_a56825 {
14508let Inst{7-5} = 0b101;
14509let Inst{13-13} = 0b0;
14510let Inst{31-21} = 0b11101000000;
14511let prefersSlot3 = 1;
14512let Defs = [USR_OVF];
14513}
14514def M2_mmpyl_s1 : HInst<
14515(outs DoubleRegs:$Rdd32),
14516(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14517"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
14518tc_c21d7447, TypeM>, Enc_a56825 {
14519let Inst{7-5} = 0b101;
14520let Inst{13-13} = 0b0;
14521let Inst{31-21} = 0b11101000100;
14522let prefersSlot3 = 1;
14523let Defs = [USR_OVF];
14524}
14525def M2_mmpyuh_rs0 : HInst<
14526(outs DoubleRegs:$Rdd32),
14527(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14528"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
14529tc_c21d7447, TypeM>, Enc_a56825 {
14530let Inst{7-5} = 0b111;
14531let Inst{13-13} = 0b0;
14532let Inst{31-21} = 0b11101000011;
14533let prefersSlot3 = 1;
14534let Defs = [USR_OVF];
14535}
14536def M2_mmpyuh_rs1 : HInst<
14537(outs DoubleRegs:$Rdd32),
14538(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14539"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14540tc_c21d7447, TypeM>, Enc_a56825 {
14541let Inst{7-5} = 0b111;
14542let Inst{13-13} = 0b0;
14543let Inst{31-21} = 0b11101000111;
14544let prefersSlot3 = 1;
14545let Defs = [USR_OVF];
14546}
14547def M2_mmpyuh_s0 : HInst<
14548(outs DoubleRegs:$Rdd32),
14549(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14550"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
14551tc_c21d7447, TypeM>, Enc_a56825 {
14552let Inst{7-5} = 0b111;
14553let Inst{13-13} = 0b0;
14554let Inst{31-21} = 0b11101000010;
14555let prefersSlot3 = 1;
14556let Defs = [USR_OVF];
14557}
14558def M2_mmpyuh_s1 : HInst<
14559(outs DoubleRegs:$Rdd32),
14560(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14561"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
14562tc_c21d7447, TypeM>, Enc_a56825 {
14563let Inst{7-5} = 0b111;
14564let Inst{13-13} = 0b0;
14565let Inst{31-21} = 0b11101000110;
14566let prefersSlot3 = 1;
14567let Defs = [USR_OVF];
14568}
14569def M2_mmpyul_rs0 : HInst<
14570(outs DoubleRegs:$Rdd32),
14571(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14572"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
14573tc_c21d7447, TypeM>, Enc_a56825 {
14574let Inst{7-5} = 0b101;
14575let Inst{13-13} = 0b0;
14576let Inst{31-21} = 0b11101000011;
14577let prefersSlot3 = 1;
14578let Defs = [USR_OVF];
14579}
14580def M2_mmpyul_rs1 : HInst<
14581(outs DoubleRegs:$Rdd32),
14582(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14583"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14584tc_c21d7447, TypeM>, Enc_a56825 {
14585let Inst{7-5} = 0b101;
14586let Inst{13-13} = 0b0;
14587let Inst{31-21} = 0b11101000111;
14588let prefersSlot3 = 1;
14589let Defs = [USR_OVF];
14590}
14591def M2_mmpyul_s0 : HInst<
14592(outs DoubleRegs:$Rdd32),
14593(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14594"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
14595tc_c21d7447, TypeM>, Enc_a56825 {
14596let Inst{7-5} = 0b101;
14597let Inst{13-13} = 0b0;
14598let Inst{31-21} = 0b11101000010;
14599let prefersSlot3 = 1;
14600let Defs = [USR_OVF];
14601}
14602def M2_mmpyul_s1 : HInst<
14603(outs DoubleRegs:$Rdd32),
14604(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14605"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
14606tc_c21d7447, TypeM>, Enc_a56825 {
14607let Inst{7-5} = 0b101;
14608let Inst{13-13} = 0b0;
14609let Inst{31-21} = 0b11101000110;
14610let prefersSlot3 = 1;
14611let Defs = [USR_OVF];
14612}
14613def M2_mnaci : HInst<
14614(outs IntRegs:$Rx32),
14615(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14616"$Rx32 -= mpyi($Rs32,$Rt32)",
14617tc_01e1be3b, TypeM>, Enc_2ae154, Requires<[HasV66]> {
14618let Inst{7-5} = 0b000;
14619let Inst{13-13} = 0b0;
14620let Inst{31-21} = 0b11101111100;
14621let hasNewValue = 1;
14622let opNewValue = 0;
14623let prefersSlot3 = 1;
14624let Constraints = "$Rx32 = $Rx32in";
14625}
14626def M2_mpy_acc_hh_s0 : HInst<
14627(outs IntRegs:$Rx32),
14628(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14629"$Rx32 += mpy($Rs32.h,$Rt32.h)",
14630tc_7f8ae742, TypeM>, Enc_2ae154 {
14631let Inst{7-5} = 0b011;
14632let Inst{13-13} = 0b0;
14633let Inst{31-21} = 0b11101110000;
14634let hasNewValue = 1;
14635let opNewValue = 0;
14636let prefersSlot3 = 1;
14637let Constraints = "$Rx32 = $Rx32in";
14638}
14639def M2_mpy_acc_hh_s1 : HInst<
14640(outs IntRegs:$Rx32),
14641(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14642"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
14643tc_7f8ae742, TypeM>, Enc_2ae154 {
14644let Inst{7-5} = 0b011;
14645let Inst{13-13} = 0b0;
14646let Inst{31-21} = 0b11101110100;
14647let hasNewValue = 1;
14648let opNewValue = 0;
14649let prefersSlot3 = 1;
14650let Constraints = "$Rx32 = $Rx32in";
14651}
14652def M2_mpy_acc_hl_s0 : HInst<
14653(outs IntRegs:$Rx32),
14654(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14655"$Rx32 += mpy($Rs32.h,$Rt32.l)",
14656tc_7f8ae742, TypeM>, Enc_2ae154 {
14657let Inst{7-5} = 0b010;
14658let Inst{13-13} = 0b0;
14659let Inst{31-21} = 0b11101110000;
14660let hasNewValue = 1;
14661let opNewValue = 0;
14662let prefersSlot3 = 1;
14663let Constraints = "$Rx32 = $Rx32in";
14664}
14665def M2_mpy_acc_hl_s1 : HInst<
14666(outs IntRegs:$Rx32),
14667(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14668"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
14669tc_7f8ae742, TypeM>, Enc_2ae154 {
14670let Inst{7-5} = 0b010;
14671let Inst{13-13} = 0b0;
14672let Inst{31-21} = 0b11101110100;
14673let hasNewValue = 1;
14674let opNewValue = 0;
14675let prefersSlot3 = 1;
14676let Constraints = "$Rx32 = $Rx32in";
14677}
14678def M2_mpy_acc_lh_s0 : HInst<
14679(outs IntRegs:$Rx32),
14680(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14681"$Rx32 += mpy($Rs32.l,$Rt32.h)",
14682tc_7f8ae742, TypeM>, Enc_2ae154 {
14683let Inst{7-5} = 0b001;
14684let Inst{13-13} = 0b0;
14685let Inst{31-21} = 0b11101110000;
14686let hasNewValue = 1;
14687let opNewValue = 0;
14688let prefersSlot3 = 1;
14689let Constraints = "$Rx32 = $Rx32in";
14690}
14691def M2_mpy_acc_lh_s1 : HInst<
14692(outs IntRegs:$Rx32),
14693(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14694"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
14695tc_7f8ae742, TypeM>, Enc_2ae154 {
14696let Inst{7-5} = 0b001;
14697let Inst{13-13} = 0b0;
14698let Inst{31-21} = 0b11101110100;
14699let hasNewValue = 1;
14700let opNewValue = 0;
14701let prefersSlot3 = 1;
14702let Constraints = "$Rx32 = $Rx32in";
14703}
14704def M2_mpy_acc_ll_s0 : HInst<
14705(outs IntRegs:$Rx32),
14706(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14707"$Rx32 += mpy($Rs32.l,$Rt32.l)",
14708tc_7f8ae742, TypeM>, Enc_2ae154 {
14709let Inst{7-5} = 0b000;
14710let Inst{13-13} = 0b0;
14711let Inst{31-21} = 0b11101110000;
14712let hasNewValue = 1;
14713let opNewValue = 0;
14714let prefersSlot3 = 1;
14715let Constraints = "$Rx32 = $Rx32in";
14716}
14717def M2_mpy_acc_ll_s1 : HInst<
14718(outs IntRegs:$Rx32),
14719(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14720"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
14721tc_7f8ae742, TypeM>, Enc_2ae154 {
14722let Inst{7-5} = 0b000;
14723let Inst{13-13} = 0b0;
14724let Inst{31-21} = 0b11101110100;
14725let hasNewValue = 1;
14726let opNewValue = 0;
14727let prefersSlot3 = 1;
14728let Constraints = "$Rx32 = $Rx32in";
14729}
14730def M2_mpy_acc_sat_hh_s0 : HInst<
14731(outs IntRegs:$Rx32),
14732(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14733"$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
14734tc_7f8ae742, TypeM>, Enc_2ae154 {
14735let Inst{7-5} = 0b111;
14736let Inst{13-13} = 0b0;
14737let Inst{31-21} = 0b11101110000;
14738let hasNewValue = 1;
14739let opNewValue = 0;
14740let prefersSlot3 = 1;
14741let Defs = [USR_OVF];
14742let Constraints = "$Rx32 = $Rx32in";
14743}
14744def M2_mpy_acc_sat_hh_s1 : HInst<
14745(outs IntRegs:$Rx32),
14746(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14747"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
14748tc_7f8ae742, TypeM>, Enc_2ae154 {
14749let Inst{7-5} = 0b111;
14750let Inst{13-13} = 0b0;
14751let Inst{31-21} = 0b11101110100;
14752let hasNewValue = 1;
14753let opNewValue = 0;
14754let prefersSlot3 = 1;
14755let Defs = [USR_OVF];
14756let Constraints = "$Rx32 = $Rx32in";
14757}
14758def M2_mpy_acc_sat_hl_s0 : HInst<
14759(outs IntRegs:$Rx32),
14760(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14761"$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
14762tc_7f8ae742, TypeM>, Enc_2ae154 {
14763let Inst{7-5} = 0b110;
14764let Inst{13-13} = 0b0;
14765let Inst{31-21} = 0b11101110000;
14766let hasNewValue = 1;
14767let opNewValue = 0;
14768let prefersSlot3 = 1;
14769let Defs = [USR_OVF];
14770let Constraints = "$Rx32 = $Rx32in";
14771}
14772def M2_mpy_acc_sat_hl_s1 : HInst<
14773(outs IntRegs:$Rx32),
14774(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14775"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
14776tc_7f8ae742, TypeM>, Enc_2ae154 {
14777let Inst{7-5} = 0b110;
14778let Inst{13-13} = 0b0;
14779let Inst{31-21} = 0b11101110100;
14780let hasNewValue = 1;
14781let opNewValue = 0;
14782let prefersSlot3 = 1;
14783let Defs = [USR_OVF];
14784let Constraints = "$Rx32 = $Rx32in";
14785}
14786def M2_mpy_acc_sat_lh_s0 : HInst<
14787(outs IntRegs:$Rx32),
14788(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14789"$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
14790tc_7f8ae742, TypeM>, Enc_2ae154 {
14791let Inst{7-5} = 0b101;
14792let Inst{13-13} = 0b0;
14793let Inst{31-21} = 0b11101110000;
14794let hasNewValue = 1;
14795let opNewValue = 0;
14796let prefersSlot3 = 1;
14797let Defs = [USR_OVF];
14798let Constraints = "$Rx32 = $Rx32in";
14799}
14800def M2_mpy_acc_sat_lh_s1 : HInst<
14801(outs IntRegs:$Rx32),
14802(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14803"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
14804tc_7f8ae742, TypeM>, Enc_2ae154 {
14805let Inst{7-5} = 0b101;
14806let Inst{13-13} = 0b0;
14807let Inst{31-21} = 0b11101110100;
14808let hasNewValue = 1;
14809let opNewValue = 0;
14810let prefersSlot3 = 1;
14811let Defs = [USR_OVF];
14812let Constraints = "$Rx32 = $Rx32in";
14813}
14814def M2_mpy_acc_sat_ll_s0 : HInst<
14815(outs IntRegs:$Rx32),
14816(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14817"$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
14818tc_7f8ae742, TypeM>, Enc_2ae154 {
14819let Inst{7-5} = 0b100;
14820let Inst{13-13} = 0b0;
14821let Inst{31-21} = 0b11101110000;
14822let hasNewValue = 1;
14823let opNewValue = 0;
14824let prefersSlot3 = 1;
14825let Defs = [USR_OVF];
14826let Constraints = "$Rx32 = $Rx32in";
14827}
14828def M2_mpy_acc_sat_ll_s1 : HInst<
14829(outs IntRegs:$Rx32),
14830(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14831"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
14832tc_7f8ae742, TypeM>, Enc_2ae154 {
14833let Inst{7-5} = 0b100;
14834let Inst{13-13} = 0b0;
14835let Inst{31-21} = 0b11101110100;
14836let hasNewValue = 1;
14837let opNewValue = 0;
14838let prefersSlot3 = 1;
14839let Defs = [USR_OVF];
14840let Constraints = "$Rx32 = $Rx32in";
14841}
14842def M2_mpy_hh_s0 : HInst<
14843(outs IntRegs:$Rd32),
14844(ins IntRegs:$Rs32, IntRegs:$Rt32),
14845"$Rd32 = mpy($Rs32.h,$Rt32.h)",
14846tc_c21d7447, TypeM>, Enc_5ab2be {
14847let Inst{7-5} = 0b011;
14848let Inst{13-13} = 0b0;
14849let Inst{31-21} = 0b11101100000;
14850let hasNewValue = 1;
14851let opNewValue = 0;
14852let prefersSlot3 = 1;
14853}
14854def M2_mpy_hh_s1 : HInst<
14855(outs IntRegs:$Rd32),
14856(ins IntRegs:$Rs32, IntRegs:$Rt32),
14857"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
14858tc_c21d7447, TypeM>, Enc_5ab2be {
14859let Inst{7-5} = 0b011;
14860let Inst{13-13} = 0b0;
14861let Inst{31-21} = 0b11101100100;
14862let hasNewValue = 1;
14863let opNewValue = 0;
14864let prefersSlot3 = 1;
14865}
14866def M2_mpy_hl_s0 : HInst<
14867(outs IntRegs:$Rd32),
14868(ins IntRegs:$Rs32, IntRegs:$Rt32),
14869"$Rd32 = mpy($Rs32.h,$Rt32.l)",
14870tc_c21d7447, TypeM>, Enc_5ab2be {
14871let Inst{7-5} = 0b010;
14872let Inst{13-13} = 0b0;
14873let Inst{31-21} = 0b11101100000;
14874let hasNewValue = 1;
14875let opNewValue = 0;
14876let prefersSlot3 = 1;
14877}
14878def M2_mpy_hl_s1 : HInst<
14879(outs IntRegs:$Rd32),
14880(ins IntRegs:$Rs32, IntRegs:$Rt32),
14881"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
14882tc_c21d7447, TypeM>, Enc_5ab2be {
14883let Inst{7-5} = 0b010;
14884let Inst{13-13} = 0b0;
14885let Inst{31-21} = 0b11101100100;
14886let hasNewValue = 1;
14887let opNewValue = 0;
14888let prefersSlot3 = 1;
14889}
14890def M2_mpy_lh_s0 : HInst<
14891(outs IntRegs:$Rd32),
14892(ins IntRegs:$Rs32, IntRegs:$Rt32),
14893"$Rd32 = mpy($Rs32.l,$Rt32.h)",
14894tc_c21d7447, TypeM>, Enc_5ab2be {
14895let Inst{7-5} = 0b001;
14896let Inst{13-13} = 0b0;
14897let Inst{31-21} = 0b11101100000;
14898let hasNewValue = 1;
14899let opNewValue = 0;
14900let prefersSlot3 = 1;
14901}
14902def M2_mpy_lh_s1 : HInst<
14903(outs IntRegs:$Rd32),
14904(ins IntRegs:$Rs32, IntRegs:$Rt32),
14905"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
14906tc_c21d7447, TypeM>, Enc_5ab2be {
14907let Inst{7-5} = 0b001;
14908let Inst{13-13} = 0b0;
14909let Inst{31-21} = 0b11101100100;
14910let hasNewValue = 1;
14911let opNewValue = 0;
14912let prefersSlot3 = 1;
14913}
14914def M2_mpy_ll_s0 : HInst<
14915(outs IntRegs:$Rd32),
14916(ins IntRegs:$Rs32, IntRegs:$Rt32),
14917"$Rd32 = mpy($Rs32.l,$Rt32.l)",
14918tc_c21d7447, TypeM>, Enc_5ab2be {
14919let Inst{7-5} = 0b000;
14920let Inst{13-13} = 0b0;
14921let Inst{31-21} = 0b11101100000;
14922let hasNewValue = 1;
14923let opNewValue = 0;
14924let prefersSlot3 = 1;
14925}
14926def M2_mpy_ll_s1 : HInst<
14927(outs IntRegs:$Rd32),
14928(ins IntRegs:$Rs32, IntRegs:$Rt32),
14929"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
14930tc_c21d7447, TypeM>, Enc_5ab2be {
14931let Inst{7-5} = 0b000;
14932let Inst{13-13} = 0b0;
14933let Inst{31-21} = 0b11101100100;
14934let hasNewValue = 1;
14935let opNewValue = 0;
14936let prefersSlot3 = 1;
14937}
14938def M2_mpy_nac_hh_s0 : HInst<
14939(outs IntRegs:$Rx32),
14940(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14941"$Rx32 -= mpy($Rs32.h,$Rt32.h)",
14942tc_7f8ae742, TypeM>, Enc_2ae154 {
14943let Inst{7-5} = 0b011;
14944let Inst{13-13} = 0b0;
14945let Inst{31-21} = 0b11101110001;
14946let hasNewValue = 1;
14947let opNewValue = 0;
14948let prefersSlot3 = 1;
14949let Constraints = "$Rx32 = $Rx32in";
14950}
14951def M2_mpy_nac_hh_s1 : HInst<
14952(outs IntRegs:$Rx32),
14953(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14954"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
14955tc_7f8ae742, TypeM>, Enc_2ae154 {
14956let Inst{7-5} = 0b011;
14957let Inst{13-13} = 0b0;
14958let Inst{31-21} = 0b11101110101;
14959let hasNewValue = 1;
14960let opNewValue = 0;
14961let prefersSlot3 = 1;
14962let Constraints = "$Rx32 = $Rx32in";
14963}
14964def M2_mpy_nac_hl_s0 : HInst<
14965(outs IntRegs:$Rx32),
14966(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14967"$Rx32 -= mpy($Rs32.h,$Rt32.l)",
14968tc_7f8ae742, TypeM>, Enc_2ae154 {
14969let Inst{7-5} = 0b010;
14970let Inst{13-13} = 0b0;
14971let Inst{31-21} = 0b11101110001;
14972let hasNewValue = 1;
14973let opNewValue = 0;
14974let prefersSlot3 = 1;
14975let Constraints = "$Rx32 = $Rx32in";
14976}
14977def M2_mpy_nac_hl_s1 : HInst<
14978(outs IntRegs:$Rx32),
14979(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14980"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
14981tc_7f8ae742, TypeM>, Enc_2ae154 {
14982let Inst{7-5} = 0b010;
14983let Inst{13-13} = 0b0;
14984let Inst{31-21} = 0b11101110101;
14985let hasNewValue = 1;
14986let opNewValue = 0;
14987let prefersSlot3 = 1;
14988let Constraints = "$Rx32 = $Rx32in";
14989}
14990def M2_mpy_nac_lh_s0 : HInst<
14991(outs IntRegs:$Rx32),
14992(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14993"$Rx32 -= mpy($Rs32.l,$Rt32.h)",
14994tc_7f8ae742, TypeM>, Enc_2ae154 {
14995let Inst{7-5} = 0b001;
14996let Inst{13-13} = 0b0;
14997let Inst{31-21} = 0b11101110001;
14998let hasNewValue = 1;
14999let opNewValue = 0;
15000let prefersSlot3 = 1;
15001let Constraints = "$Rx32 = $Rx32in";
15002}
15003def M2_mpy_nac_lh_s1 : HInst<
15004(outs IntRegs:$Rx32),
15005(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15006"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15007tc_7f8ae742, TypeM>, Enc_2ae154 {
15008let Inst{7-5} = 0b001;
15009let Inst{13-13} = 0b0;
15010let Inst{31-21} = 0b11101110101;
15011let hasNewValue = 1;
15012let opNewValue = 0;
15013let prefersSlot3 = 1;
15014let Constraints = "$Rx32 = $Rx32in";
15015}
15016def M2_mpy_nac_ll_s0 : HInst<
15017(outs IntRegs:$Rx32),
15018(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15019"$Rx32 -= mpy($Rs32.l,$Rt32.l)",
15020tc_7f8ae742, TypeM>, Enc_2ae154 {
15021let Inst{7-5} = 0b000;
15022let Inst{13-13} = 0b0;
15023let Inst{31-21} = 0b11101110001;
15024let hasNewValue = 1;
15025let opNewValue = 0;
15026let prefersSlot3 = 1;
15027let Constraints = "$Rx32 = $Rx32in";
15028}
15029def M2_mpy_nac_ll_s1 : HInst<
15030(outs IntRegs:$Rx32),
15031(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15032"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15033tc_7f8ae742, TypeM>, Enc_2ae154 {
15034let Inst{7-5} = 0b000;
15035let Inst{13-13} = 0b0;
15036let Inst{31-21} = 0b11101110101;
15037let hasNewValue = 1;
15038let opNewValue = 0;
15039let prefersSlot3 = 1;
15040let Constraints = "$Rx32 = $Rx32in";
15041}
15042def M2_mpy_nac_sat_hh_s0 : HInst<
15043(outs IntRegs:$Rx32),
15044(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15045"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
15046tc_7f8ae742, TypeM>, Enc_2ae154 {
15047let Inst{7-5} = 0b111;
15048let Inst{13-13} = 0b0;
15049let Inst{31-21} = 0b11101110001;
15050let hasNewValue = 1;
15051let opNewValue = 0;
15052let prefersSlot3 = 1;
15053let Defs = [USR_OVF];
15054let Constraints = "$Rx32 = $Rx32in";
15055}
15056def M2_mpy_nac_sat_hh_s1 : HInst<
15057(outs IntRegs:$Rx32),
15058(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15059"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
15060tc_7f8ae742, TypeM>, Enc_2ae154 {
15061let Inst{7-5} = 0b111;
15062let Inst{13-13} = 0b0;
15063let Inst{31-21} = 0b11101110101;
15064let hasNewValue = 1;
15065let opNewValue = 0;
15066let prefersSlot3 = 1;
15067let Defs = [USR_OVF];
15068let Constraints = "$Rx32 = $Rx32in";
15069}
15070def M2_mpy_nac_sat_hl_s0 : HInst<
15071(outs IntRegs:$Rx32),
15072(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15073"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
15074tc_7f8ae742, TypeM>, Enc_2ae154 {
15075let Inst{7-5} = 0b110;
15076let Inst{13-13} = 0b0;
15077let Inst{31-21} = 0b11101110001;
15078let hasNewValue = 1;
15079let opNewValue = 0;
15080let prefersSlot3 = 1;
15081let Defs = [USR_OVF];
15082let Constraints = "$Rx32 = $Rx32in";
15083}
15084def M2_mpy_nac_sat_hl_s1 : HInst<
15085(outs IntRegs:$Rx32),
15086(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15087"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
15088tc_7f8ae742, TypeM>, Enc_2ae154 {
15089let Inst{7-5} = 0b110;
15090let Inst{13-13} = 0b0;
15091let Inst{31-21} = 0b11101110101;
15092let hasNewValue = 1;
15093let opNewValue = 0;
15094let prefersSlot3 = 1;
15095let Defs = [USR_OVF];
15096let Constraints = "$Rx32 = $Rx32in";
15097}
15098def M2_mpy_nac_sat_lh_s0 : HInst<
15099(outs IntRegs:$Rx32),
15100(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15101"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
15102tc_7f8ae742, TypeM>, Enc_2ae154 {
15103let Inst{7-5} = 0b101;
15104let Inst{13-13} = 0b0;
15105let Inst{31-21} = 0b11101110001;
15106let hasNewValue = 1;
15107let opNewValue = 0;
15108let prefersSlot3 = 1;
15109let Defs = [USR_OVF];
15110let Constraints = "$Rx32 = $Rx32in";
15111}
15112def M2_mpy_nac_sat_lh_s1 : HInst<
15113(outs IntRegs:$Rx32),
15114(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15115"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
15116tc_7f8ae742, TypeM>, Enc_2ae154 {
15117let Inst{7-5} = 0b101;
15118let Inst{13-13} = 0b0;
15119let Inst{31-21} = 0b11101110101;
15120let hasNewValue = 1;
15121let opNewValue = 0;
15122let prefersSlot3 = 1;
15123let Defs = [USR_OVF];
15124let Constraints = "$Rx32 = $Rx32in";
15125}
15126def M2_mpy_nac_sat_ll_s0 : HInst<
15127(outs IntRegs:$Rx32),
15128(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15129"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
15130tc_7f8ae742, TypeM>, Enc_2ae154 {
15131let Inst{7-5} = 0b100;
15132let Inst{13-13} = 0b0;
15133let Inst{31-21} = 0b11101110001;
15134let hasNewValue = 1;
15135let opNewValue = 0;
15136let prefersSlot3 = 1;
15137let Defs = [USR_OVF];
15138let Constraints = "$Rx32 = $Rx32in";
15139}
15140def M2_mpy_nac_sat_ll_s1 : HInst<
15141(outs IntRegs:$Rx32),
15142(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15143"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
15144tc_7f8ae742, TypeM>, Enc_2ae154 {
15145let Inst{7-5} = 0b100;
15146let Inst{13-13} = 0b0;
15147let Inst{31-21} = 0b11101110101;
15148let hasNewValue = 1;
15149let opNewValue = 0;
15150let prefersSlot3 = 1;
15151let Defs = [USR_OVF];
15152let Constraints = "$Rx32 = $Rx32in";
15153}
15154def M2_mpy_rnd_hh_s0 : HInst<
15155(outs IntRegs:$Rd32),
15156(ins IntRegs:$Rs32, IntRegs:$Rt32),
15157"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
15158tc_c21d7447, TypeM>, Enc_5ab2be {
15159let Inst{7-5} = 0b011;
15160let Inst{13-13} = 0b0;
15161let Inst{31-21} = 0b11101100001;
15162let hasNewValue = 1;
15163let opNewValue = 0;
15164let prefersSlot3 = 1;
15165}
15166def M2_mpy_rnd_hh_s1 : HInst<
15167(outs IntRegs:$Rd32),
15168(ins IntRegs:$Rs32, IntRegs:$Rt32),
15169"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15170tc_c21d7447, TypeM>, Enc_5ab2be {
15171let Inst{7-5} = 0b011;
15172let Inst{13-13} = 0b0;
15173let Inst{31-21} = 0b11101100101;
15174let hasNewValue = 1;
15175let opNewValue = 0;
15176let prefersSlot3 = 1;
15177}
15178def M2_mpy_rnd_hl_s0 : HInst<
15179(outs IntRegs:$Rd32),
15180(ins IntRegs:$Rs32, IntRegs:$Rt32),
15181"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
15182tc_c21d7447, TypeM>, Enc_5ab2be {
15183let Inst{7-5} = 0b010;
15184let Inst{13-13} = 0b0;
15185let Inst{31-21} = 0b11101100001;
15186let hasNewValue = 1;
15187let opNewValue = 0;
15188let prefersSlot3 = 1;
15189}
15190def M2_mpy_rnd_hl_s1 : HInst<
15191(outs IntRegs:$Rd32),
15192(ins IntRegs:$Rs32, IntRegs:$Rt32),
15193"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15194tc_c21d7447, TypeM>, Enc_5ab2be {
15195let Inst{7-5} = 0b010;
15196let Inst{13-13} = 0b0;
15197let Inst{31-21} = 0b11101100101;
15198let hasNewValue = 1;
15199let opNewValue = 0;
15200let prefersSlot3 = 1;
15201}
15202def M2_mpy_rnd_lh_s0 : HInst<
15203(outs IntRegs:$Rd32),
15204(ins IntRegs:$Rs32, IntRegs:$Rt32),
15205"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
15206tc_c21d7447, TypeM>, Enc_5ab2be {
15207let Inst{7-5} = 0b001;
15208let Inst{13-13} = 0b0;
15209let Inst{31-21} = 0b11101100001;
15210let hasNewValue = 1;
15211let opNewValue = 0;
15212let prefersSlot3 = 1;
15213}
15214def M2_mpy_rnd_lh_s1 : HInst<
15215(outs IntRegs:$Rd32),
15216(ins IntRegs:$Rs32, IntRegs:$Rt32),
15217"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15218tc_c21d7447, TypeM>, Enc_5ab2be {
15219let Inst{7-5} = 0b001;
15220let Inst{13-13} = 0b0;
15221let Inst{31-21} = 0b11101100101;
15222let hasNewValue = 1;
15223let opNewValue = 0;
15224let prefersSlot3 = 1;
15225}
15226def M2_mpy_rnd_ll_s0 : HInst<
15227(outs IntRegs:$Rd32),
15228(ins IntRegs:$Rs32, IntRegs:$Rt32),
15229"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
15230tc_c21d7447, TypeM>, Enc_5ab2be {
15231let Inst{7-5} = 0b000;
15232let Inst{13-13} = 0b0;
15233let Inst{31-21} = 0b11101100001;
15234let hasNewValue = 1;
15235let opNewValue = 0;
15236let prefersSlot3 = 1;
15237}
15238def M2_mpy_rnd_ll_s1 : HInst<
15239(outs IntRegs:$Rd32),
15240(ins IntRegs:$Rs32, IntRegs:$Rt32),
15241"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15242tc_c21d7447, TypeM>, Enc_5ab2be {
15243let Inst{7-5} = 0b000;
15244let Inst{13-13} = 0b0;
15245let Inst{31-21} = 0b11101100101;
15246let hasNewValue = 1;
15247let opNewValue = 0;
15248let prefersSlot3 = 1;
15249}
15250def M2_mpy_sat_hh_s0 : HInst<
15251(outs IntRegs:$Rd32),
15252(ins IntRegs:$Rs32, IntRegs:$Rt32),
15253"$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
15254tc_c21d7447, TypeM>, Enc_5ab2be {
15255let Inst{7-5} = 0b111;
15256let Inst{13-13} = 0b0;
15257let Inst{31-21} = 0b11101100000;
15258let hasNewValue = 1;
15259let opNewValue = 0;
15260let prefersSlot3 = 1;
15261let Defs = [USR_OVF];
15262}
15263def M2_mpy_sat_hh_s1 : HInst<
15264(outs IntRegs:$Rd32),
15265(ins IntRegs:$Rs32, IntRegs:$Rt32),
15266"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
15267tc_c21d7447, TypeM>, Enc_5ab2be {
15268let Inst{7-5} = 0b111;
15269let Inst{13-13} = 0b0;
15270let Inst{31-21} = 0b11101100100;
15271let hasNewValue = 1;
15272let opNewValue = 0;
15273let prefersSlot3 = 1;
15274let Defs = [USR_OVF];
15275}
15276def M2_mpy_sat_hl_s0 : HInst<
15277(outs IntRegs:$Rd32),
15278(ins IntRegs:$Rs32, IntRegs:$Rt32),
15279"$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
15280tc_c21d7447, TypeM>, Enc_5ab2be {
15281let Inst{7-5} = 0b110;
15282let Inst{13-13} = 0b0;
15283let Inst{31-21} = 0b11101100000;
15284let hasNewValue = 1;
15285let opNewValue = 0;
15286let prefersSlot3 = 1;
15287let Defs = [USR_OVF];
15288}
15289def M2_mpy_sat_hl_s1 : HInst<
15290(outs IntRegs:$Rd32),
15291(ins IntRegs:$Rs32, IntRegs:$Rt32),
15292"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
15293tc_c21d7447, TypeM>, Enc_5ab2be {
15294let Inst{7-5} = 0b110;
15295let Inst{13-13} = 0b0;
15296let Inst{31-21} = 0b11101100100;
15297let hasNewValue = 1;
15298let opNewValue = 0;
15299let prefersSlot3 = 1;
15300let Defs = [USR_OVF];
15301}
15302def M2_mpy_sat_lh_s0 : HInst<
15303(outs IntRegs:$Rd32),
15304(ins IntRegs:$Rs32, IntRegs:$Rt32),
15305"$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
15306tc_c21d7447, TypeM>, Enc_5ab2be {
15307let Inst{7-5} = 0b101;
15308let Inst{13-13} = 0b0;
15309let Inst{31-21} = 0b11101100000;
15310let hasNewValue = 1;
15311let opNewValue = 0;
15312let prefersSlot3 = 1;
15313let Defs = [USR_OVF];
15314}
15315def M2_mpy_sat_lh_s1 : HInst<
15316(outs IntRegs:$Rd32),
15317(ins IntRegs:$Rs32, IntRegs:$Rt32),
15318"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
15319tc_c21d7447, TypeM>, Enc_5ab2be {
15320let Inst{7-5} = 0b101;
15321let Inst{13-13} = 0b0;
15322let Inst{31-21} = 0b11101100100;
15323let hasNewValue = 1;
15324let opNewValue = 0;
15325let prefersSlot3 = 1;
15326let Defs = [USR_OVF];
15327}
15328def M2_mpy_sat_ll_s0 : HInst<
15329(outs IntRegs:$Rd32),
15330(ins IntRegs:$Rs32, IntRegs:$Rt32),
15331"$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
15332tc_c21d7447, TypeM>, Enc_5ab2be {
15333let Inst{7-5} = 0b100;
15334let Inst{13-13} = 0b0;
15335let Inst{31-21} = 0b11101100000;
15336let hasNewValue = 1;
15337let opNewValue = 0;
15338let prefersSlot3 = 1;
15339let Defs = [USR_OVF];
15340}
15341def M2_mpy_sat_ll_s1 : HInst<
15342(outs IntRegs:$Rd32),
15343(ins IntRegs:$Rs32, IntRegs:$Rt32),
15344"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
15345tc_c21d7447, TypeM>, Enc_5ab2be {
15346let Inst{7-5} = 0b100;
15347let Inst{13-13} = 0b0;
15348let Inst{31-21} = 0b11101100100;
15349let hasNewValue = 1;
15350let opNewValue = 0;
15351let prefersSlot3 = 1;
15352let Defs = [USR_OVF];
15353}
15354def M2_mpy_sat_rnd_hh_s0 : HInst<
15355(outs IntRegs:$Rd32),
15356(ins IntRegs:$Rs32, IntRegs:$Rt32),
15357"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
15358tc_c21d7447, TypeM>, Enc_5ab2be {
15359let Inst{7-5} = 0b111;
15360let Inst{13-13} = 0b0;
15361let Inst{31-21} = 0b11101100001;
15362let hasNewValue = 1;
15363let opNewValue = 0;
15364let prefersSlot3 = 1;
15365let Defs = [USR_OVF];
15366}
15367def M2_mpy_sat_rnd_hh_s1 : HInst<
15368(outs IntRegs:$Rd32),
15369(ins IntRegs:$Rs32, IntRegs:$Rt32),
15370"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
15371tc_c21d7447, TypeM>, Enc_5ab2be {
15372let Inst{7-5} = 0b111;
15373let Inst{13-13} = 0b0;
15374let Inst{31-21} = 0b11101100101;
15375let hasNewValue = 1;
15376let opNewValue = 0;
15377let prefersSlot3 = 1;
15378let Defs = [USR_OVF];
15379}
15380def M2_mpy_sat_rnd_hl_s0 : HInst<
15381(outs IntRegs:$Rd32),
15382(ins IntRegs:$Rs32, IntRegs:$Rt32),
15383"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
15384tc_c21d7447, TypeM>, Enc_5ab2be {
15385let Inst{7-5} = 0b110;
15386let Inst{13-13} = 0b0;
15387let Inst{31-21} = 0b11101100001;
15388let hasNewValue = 1;
15389let opNewValue = 0;
15390let prefersSlot3 = 1;
15391let Defs = [USR_OVF];
15392}
15393def M2_mpy_sat_rnd_hl_s1 : HInst<
15394(outs IntRegs:$Rd32),
15395(ins IntRegs:$Rs32, IntRegs:$Rt32),
15396"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
15397tc_c21d7447, TypeM>, Enc_5ab2be {
15398let Inst{7-5} = 0b110;
15399let Inst{13-13} = 0b0;
15400let Inst{31-21} = 0b11101100101;
15401let hasNewValue = 1;
15402let opNewValue = 0;
15403let prefersSlot3 = 1;
15404let Defs = [USR_OVF];
15405}
15406def M2_mpy_sat_rnd_lh_s0 : HInst<
15407(outs IntRegs:$Rd32),
15408(ins IntRegs:$Rs32, IntRegs:$Rt32),
15409"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
15410tc_c21d7447, TypeM>, Enc_5ab2be {
15411let Inst{7-5} = 0b101;
15412let Inst{13-13} = 0b0;
15413let Inst{31-21} = 0b11101100001;
15414let hasNewValue = 1;
15415let opNewValue = 0;
15416let prefersSlot3 = 1;
15417let Defs = [USR_OVF];
15418}
15419def M2_mpy_sat_rnd_lh_s1 : HInst<
15420(outs IntRegs:$Rd32),
15421(ins IntRegs:$Rs32, IntRegs:$Rt32),
15422"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
15423tc_c21d7447, TypeM>, Enc_5ab2be {
15424let Inst{7-5} = 0b101;
15425let Inst{13-13} = 0b0;
15426let Inst{31-21} = 0b11101100101;
15427let hasNewValue = 1;
15428let opNewValue = 0;
15429let prefersSlot3 = 1;
15430let Defs = [USR_OVF];
15431}
15432def M2_mpy_sat_rnd_ll_s0 : HInst<
15433(outs IntRegs:$Rd32),
15434(ins IntRegs:$Rs32, IntRegs:$Rt32),
15435"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
15436tc_c21d7447, TypeM>, Enc_5ab2be {
15437let Inst{7-5} = 0b100;
15438let Inst{13-13} = 0b0;
15439let Inst{31-21} = 0b11101100001;
15440let hasNewValue = 1;
15441let opNewValue = 0;
15442let prefersSlot3 = 1;
15443let Defs = [USR_OVF];
15444}
15445def M2_mpy_sat_rnd_ll_s1 : HInst<
15446(outs IntRegs:$Rd32),
15447(ins IntRegs:$Rs32, IntRegs:$Rt32),
15448"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
15449tc_c21d7447, TypeM>, Enc_5ab2be {
15450let Inst{7-5} = 0b100;
15451let Inst{13-13} = 0b0;
15452let Inst{31-21} = 0b11101100101;
15453let hasNewValue = 1;
15454let opNewValue = 0;
15455let prefersSlot3 = 1;
15456let Defs = [USR_OVF];
15457}
15458def M2_mpy_up : HInst<
15459(outs IntRegs:$Rd32),
15460(ins IntRegs:$Rs32, IntRegs:$Rt32),
15461"$Rd32 = mpy($Rs32,$Rt32)",
15462tc_c21d7447, TypeM>, Enc_5ab2be {
15463let Inst{7-5} = 0b001;
15464let Inst{13-13} = 0b0;
15465let Inst{31-21} = 0b11101101000;
15466let hasNewValue = 1;
15467let opNewValue = 0;
15468let prefersSlot3 = 1;
15469}
15470def M2_mpy_up_s1 : HInst<
15471(outs IntRegs:$Rd32),
15472(ins IntRegs:$Rs32, IntRegs:$Rt32),
15473"$Rd32 = mpy($Rs32,$Rt32):<<1",
15474tc_c21d7447, TypeM>, Enc_5ab2be {
15475let Inst{7-5} = 0b010;
15476let Inst{13-13} = 0b0;
15477let Inst{31-21} = 0b11101101101;
15478let hasNewValue = 1;
15479let opNewValue = 0;
15480let prefersSlot3 = 1;
15481}
15482def M2_mpy_up_s1_sat : HInst<
15483(outs IntRegs:$Rd32),
15484(ins IntRegs:$Rs32, IntRegs:$Rt32),
15485"$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
15486tc_c21d7447, TypeM>, Enc_5ab2be {
15487let Inst{7-5} = 0b000;
15488let Inst{13-13} = 0b0;
15489let Inst{31-21} = 0b11101101111;
15490let hasNewValue = 1;
15491let opNewValue = 0;
15492let prefersSlot3 = 1;
15493let Defs = [USR_OVF];
15494}
15495def M2_mpyd_acc_hh_s0 : HInst<
15496(outs DoubleRegs:$Rxx32),
15497(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15498"$Rxx32 += mpy($Rs32.h,$Rt32.h)",
15499tc_7f8ae742, TypeM>, Enc_61f0b0 {
15500let Inst{7-5} = 0b011;
15501let Inst{13-13} = 0b0;
15502let Inst{31-21} = 0b11100110000;
15503let prefersSlot3 = 1;
15504let Constraints = "$Rxx32 = $Rxx32in";
15505}
15506def M2_mpyd_acc_hh_s1 : HInst<
15507(outs DoubleRegs:$Rxx32),
15508(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15509"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
15510tc_7f8ae742, TypeM>, Enc_61f0b0 {
15511let Inst{7-5} = 0b011;
15512let Inst{13-13} = 0b0;
15513let Inst{31-21} = 0b11100110100;
15514let prefersSlot3 = 1;
15515let Constraints = "$Rxx32 = $Rxx32in";
15516}
15517def M2_mpyd_acc_hl_s0 : HInst<
15518(outs DoubleRegs:$Rxx32),
15519(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15520"$Rxx32 += mpy($Rs32.h,$Rt32.l)",
15521tc_7f8ae742, TypeM>, Enc_61f0b0 {
15522let Inst{7-5} = 0b010;
15523let Inst{13-13} = 0b0;
15524let Inst{31-21} = 0b11100110000;
15525let prefersSlot3 = 1;
15526let Constraints = "$Rxx32 = $Rxx32in";
15527}
15528def M2_mpyd_acc_hl_s1 : HInst<
15529(outs DoubleRegs:$Rxx32),
15530(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15531"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
15532tc_7f8ae742, TypeM>, Enc_61f0b0 {
15533let Inst{7-5} = 0b010;
15534let Inst{13-13} = 0b0;
15535let Inst{31-21} = 0b11100110100;
15536let prefersSlot3 = 1;
15537let Constraints = "$Rxx32 = $Rxx32in";
15538}
15539def M2_mpyd_acc_lh_s0 : HInst<
15540(outs DoubleRegs:$Rxx32),
15541(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15542"$Rxx32 += mpy($Rs32.l,$Rt32.h)",
15543tc_7f8ae742, TypeM>, Enc_61f0b0 {
15544let Inst{7-5} = 0b001;
15545let Inst{13-13} = 0b0;
15546let Inst{31-21} = 0b11100110000;
15547let prefersSlot3 = 1;
15548let Constraints = "$Rxx32 = $Rxx32in";
15549}
15550def M2_mpyd_acc_lh_s1 : HInst<
15551(outs DoubleRegs:$Rxx32),
15552(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15553"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
15554tc_7f8ae742, TypeM>, Enc_61f0b0 {
15555let Inst{7-5} = 0b001;
15556let Inst{13-13} = 0b0;
15557let Inst{31-21} = 0b11100110100;
15558let prefersSlot3 = 1;
15559let Constraints = "$Rxx32 = $Rxx32in";
15560}
15561def M2_mpyd_acc_ll_s0 : HInst<
15562(outs DoubleRegs:$Rxx32),
15563(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15564"$Rxx32 += mpy($Rs32.l,$Rt32.l)",
15565tc_7f8ae742, TypeM>, Enc_61f0b0 {
15566let Inst{7-5} = 0b000;
15567let Inst{13-13} = 0b0;
15568let Inst{31-21} = 0b11100110000;
15569let prefersSlot3 = 1;
15570let Constraints = "$Rxx32 = $Rxx32in";
15571}
15572def M2_mpyd_acc_ll_s1 : HInst<
15573(outs DoubleRegs:$Rxx32),
15574(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15575"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
15576tc_7f8ae742, TypeM>, Enc_61f0b0 {
15577let Inst{7-5} = 0b000;
15578let Inst{13-13} = 0b0;
15579let Inst{31-21} = 0b11100110100;
15580let prefersSlot3 = 1;
15581let Constraints = "$Rxx32 = $Rxx32in";
15582}
15583def M2_mpyd_hh_s0 : HInst<
15584(outs DoubleRegs:$Rdd32),
15585(ins IntRegs:$Rs32, IntRegs:$Rt32),
15586"$Rdd32 = mpy($Rs32.h,$Rt32.h)",
15587tc_c21d7447, TypeM>, Enc_be32a5 {
15588let Inst{7-5} = 0b011;
15589let Inst{13-13} = 0b0;
15590let Inst{31-21} = 0b11100100000;
15591let prefersSlot3 = 1;
15592}
15593def M2_mpyd_hh_s1 : HInst<
15594(outs DoubleRegs:$Rdd32),
15595(ins IntRegs:$Rs32, IntRegs:$Rt32),
15596"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
15597tc_c21d7447, TypeM>, Enc_be32a5 {
15598let Inst{7-5} = 0b011;
15599let Inst{13-13} = 0b0;
15600let Inst{31-21} = 0b11100100100;
15601let prefersSlot3 = 1;
15602}
15603def M2_mpyd_hl_s0 : HInst<
15604(outs DoubleRegs:$Rdd32),
15605(ins IntRegs:$Rs32, IntRegs:$Rt32),
15606"$Rdd32 = mpy($Rs32.h,$Rt32.l)",
15607tc_c21d7447, TypeM>, Enc_be32a5 {
15608let Inst{7-5} = 0b010;
15609let Inst{13-13} = 0b0;
15610let Inst{31-21} = 0b11100100000;
15611let prefersSlot3 = 1;
15612}
15613def M2_mpyd_hl_s1 : HInst<
15614(outs DoubleRegs:$Rdd32),
15615(ins IntRegs:$Rs32, IntRegs:$Rt32),
15616"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
15617tc_c21d7447, TypeM>, Enc_be32a5 {
15618let Inst{7-5} = 0b010;
15619let Inst{13-13} = 0b0;
15620let Inst{31-21} = 0b11100100100;
15621let prefersSlot3 = 1;
15622}
15623def M2_mpyd_lh_s0 : HInst<
15624(outs DoubleRegs:$Rdd32),
15625(ins IntRegs:$Rs32, IntRegs:$Rt32),
15626"$Rdd32 = mpy($Rs32.l,$Rt32.h)",
15627tc_c21d7447, TypeM>, Enc_be32a5 {
15628let Inst{7-5} = 0b001;
15629let Inst{13-13} = 0b0;
15630let Inst{31-21} = 0b11100100000;
15631let prefersSlot3 = 1;
15632}
15633def M2_mpyd_lh_s1 : HInst<
15634(outs DoubleRegs:$Rdd32),
15635(ins IntRegs:$Rs32, IntRegs:$Rt32),
15636"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
15637tc_c21d7447, TypeM>, Enc_be32a5 {
15638let Inst{7-5} = 0b001;
15639let Inst{13-13} = 0b0;
15640let Inst{31-21} = 0b11100100100;
15641let prefersSlot3 = 1;
15642}
15643def M2_mpyd_ll_s0 : HInst<
15644(outs DoubleRegs:$Rdd32),
15645(ins IntRegs:$Rs32, IntRegs:$Rt32),
15646"$Rdd32 = mpy($Rs32.l,$Rt32.l)",
15647tc_c21d7447, TypeM>, Enc_be32a5 {
15648let Inst{7-5} = 0b000;
15649let Inst{13-13} = 0b0;
15650let Inst{31-21} = 0b11100100000;
15651let prefersSlot3 = 1;
15652}
15653def M2_mpyd_ll_s1 : HInst<
15654(outs DoubleRegs:$Rdd32),
15655(ins IntRegs:$Rs32, IntRegs:$Rt32),
15656"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
15657tc_c21d7447, TypeM>, Enc_be32a5 {
15658let Inst{7-5} = 0b000;
15659let Inst{13-13} = 0b0;
15660let Inst{31-21} = 0b11100100100;
15661let prefersSlot3 = 1;
15662}
15663def M2_mpyd_nac_hh_s0 : HInst<
15664(outs DoubleRegs:$Rxx32),
15665(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15666"$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
15667tc_7f8ae742, TypeM>, Enc_61f0b0 {
15668let Inst{7-5} = 0b011;
15669let Inst{13-13} = 0b0;
15670let Inst{31-21} = 0b11100110001;
15671let prefersSlot3 = 1;
15672let Constraints = "$Rxx32 = $Rxx32in";
15673}
15674def M2_mpyd_nac_hh_s1 : HInst<
15675(outs DoubleRegs:$Rxx32),
15676(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15677"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15678tc_7f8ae742, TypeM>, Enc_61f0b0 {
15679let Inst{7-5} = 0b011;
15680let Inst{13-13} = 0b0;
15681let Inst{31-21} = 0b11100110101;
15682let prefersSlot3 = 1;
15683let Constraints = "$Rxx32 = $Rxx32in";
15684}
15685def M2_mpyd_nac_hl_s0 : HInst<
15686(outs DoubleRegs:$Rxx32),
15687(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15688"$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
15689tc_7f8ae742, TypeM>, Enc_61f0b0 {
15690let Inst{7-5} = 0b010;
15691let Inst{13-13} = 0b0;
15692let Inst{31-21} = 0b11100110001;
15693let prefersSlot3 = 1;
15694let Constraints = "$Rxx32 = $Rxx32in";
15695}
15696def M2_mpyd_nac_hl_s1 : HInst<
15697(outs DoubleRegs:$Rxx32),
15698(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15699"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15700tc_7f8ae742, TypeM>, Enc_61f0b0 {
15701let Inst{7-5} = 0b010;
15702let Inst{13-13} = 0b0;
15703let Inst{31-21} = 0b11100110101;
15704let prefersSlot3 = 1;
15705let Constraints = "$Rxx32 = $Rxx32in";
15706}
15707def M2_mpyd_nac_lh_s0 : HInst<
15708(outs DoubleRegs:$Rxx32),
15709(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15710"$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
15711tc_7f8ae742, TypeM>, Enc_61f0b0 {
15712let Inst{7-5} = 0b001;
15713let Inst{13-13} = 0b0;
15714let Inst{31-21} = 0b11100110001;
15715let prefersSlot3 = 1;
15716let Constraints = "$Rxx32 = $Rxx32in";
15717}
15718def M2_mpyd_nac_lh_s1 : HInst<
15719(outs DoubleRegs:$Rxx32),
15720(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15721"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15722tc_7f8ae742, TypeM>, Enc_61f0b0 {
15723let Inst{7-5} = 0b001;
15724let Inst{13-13} = 0b0;
15725let Inst{31-21} = 0b11100110101;
15726let prefersSlot3 = 1;
15727let Constraints = "$Rxx32 = $Rxx32in";
15728}
15729def M2_mpyd_nac_ll_s0 : HInst<
15730(outs DoubleRegs:$Rxx32),
15731(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15732"$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
15733tc_7f8ae742, TypeM>, Enc_61f0b0 {
15734let Inst{7-5} = 0b000;
15735let Inst{13-13} = 0b0;
15736let Inst{31-21} = 0b11100110001;
15737let prefersSlot3 = 1;
15738let Constraints = "$Rxx32 = $Rxx32in";
15739}
15740def M2_mpyd_nac_ll_s1 : HInst<
15741(outs DoubleRegs:$Rxx32),
15742(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15743"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15744tc_7f8ae742, TypeM>, Enc_61f0b0 {
15745let Inst{7-5} = 0b000;
15746let Inst{13-13} = 0b0;
15747let Inst{31-21} = 0b11100110101;
15748let prefersSlot3 = 1;
15749let Constraints = "$Rxx32 = $Rxx32in";
15750}
15751def M2_mpyd_rnd_hh_s0 : HInst<
15752(outs DoubleRegs:$Rdd32),
15753(ins IntRegs:$Rs32, IntRegs:$Rt32),
15754"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
15755tc_c21d7447, TypeM>, Enc_be32a5 {
15756let Inst{7-5} = 0b011;
15757let Inst{13-13} = 0b0;
15758let Inst{31-21} = 0b11100100001;
15759let prefersSlot3 = 1;
15760}
15761def M2_mpyd_rnd_hh_s1 : HInst<
15762(outs DoubleRegs:$Rdd32),
15763(ins IntRegs:$Rs32, IntRegs:$Rt32),
15764"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15765tc_c21d7447, TypeM>, Enc_be32a5 {
15766let Inst{7-5} = 0b011;
15767let Inst{13-13} = 0b0;
15768let Inst{31-21} = 0b11100100101;
15769let prefersSlot3 = 1;
15770}
15771def M2_mpyd_rnd_hl_s0 : HInst<
15772(outs DoubleRegs:$Rdd32),
15773(ins IntRegs:$Rs32, IntRegs:$Rt32),
15774"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
15775tc_c21d7447, TypeM>, Enc_be32a5 {
15776let Inst{7-5} = 0b010;
15777let Inst{13-13} = 0b0;
15778let Inst{31-21} = 0b11100100001;
15779let prefersSlot3 = 1;
15780}
15781def M2_mpyd_rnd_hl_s1 : HInst<
15782(outs DoubleRegs:$Rdd32),
15783(ins IntRegs:$Rs32, IntRegs:$Rt32),
15784"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15785tc_c21d7447, TypeM>, Enc_be32a5 {
15786let Inst{7-5} = 0b010;
15787let Inst{13-13} = 0b0;
15788let Inst{31-21} = 0b11100100101;
15789let prefersSlot3 = 1;
15790}
15791def M2_mpyd_rnd_lh_s0 : HInst<
15792(outs DoubleRegs:$Rdd32),
15793(ins IntRegs:$Rs32, IntRegs:$Rt32),
15794"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
15795tc_c21d7447, TypeM>, Enc_be32a5 {
15796let Inst{7-5} = 0b001;
15797let Inst{13-13} = 0b0;
15798let Inst{31-21} = 0b11100100001;
15799let prefersSlot3 = 1;
15800}
15801def M2_mpyd_rnd_lh_s1 : HInst<
15802(outs DoubleRegs:$Rdd32),
15803(ins IntRegs:$Rs32, IntRegs:$Rt32),
15804"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15805tc_c21d7447, TypeM>, Enc_be32a5 {
15806let Inst{7-5} = 0b001;
15807let Inst{13-13} = 0b0;
15808let Inst{31-21} = 0b11100100101;
15809let prefersSlot3 = 1;
15810}
15811def M2_mpyd_rnd_ll_s0 : HInst<
15812(outs DoubleRegs:$Rdd32),
15813(ins IntRegs:$Rs32, IntRegs:$Rt32),
15814"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
15815tc_c21d7447, TypeM>, Enc_be32a5 {
15816let Inst{7-5} = 0b000;
15817let Inst{13-13} = 0b0;
15818let Inst{31-21} = 0b11100100001;
15819let prefersSlot3 = 1;
15820}
15821def M2_mpyd_rnd_ll_s1 : HInst<
15822(outs DoubleRegs:$Rdd32),
15823(ins IntRegs:$Rs32, IntRegs:$Rt32),
15824"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15825tc_c21d7447, TypeM>, Enc_be32a5 {
15826let Inst{7-5} = 0b000;
15827let Inst{13-13} = 0b0;
15828let Inst{31-21} = 0b11100100101;
15829let prefersSlot3 = 1;
15830}
15831def M2_mpyi : HInst<
15832(outs IntRegs:$Rd32),
15833(ins IntRegs:$Rs32, IntRegs:$Rt32),
15834"$Rd32 = mpyi($Rs32,$Rt32)",
15835tc_c21d7447, TypeM>, Enc_5ab2be, ImmRegRel {
15836let Inst{7-5} = 0b000;
15837let Inst{13-13} = 0b0;
15838let Inst{31-21} = 0b11101101000;
15839let hasNewValue = 1;
15840let opNewValue = 0;
15841let prefersSlot3 = 1;
15842let CextOpcode = "M2_mpyi";
15843let InputType = "reg";
15844}
15845def M2_mpysin : HInst<
15846(outs IntRegs:$Rd32),
15847(ins IntRegs:$Rs32, u8_0Imm:$Ii),
15848"$Rd32 = -mpyi($Rs32,#$Ii)",
15849tc_38382228, TypeM>, Enc_b8c967 {
15850let Inst{13-13} = 0b0;
15851let Inst{31-21} = 0b11100000100;
15852let hasNewValue = 1;
15853let opNewValue = 0;
15854let prefersSlot3 = 1;
15855}
15856def M2_mpysip : HInst<
15857(outs IntRegs:$Rd32),
15858(ins IntRegs:$Rs32, u32_0Imm:$Ii),
15859"$Rd32 = +mpyi($Rs32,#$Ii)",
15860tc_38382228, TypeM>, Enc_b8c967 {
15861let Inst{13-13} = 0b0;
15862let Inst{31-21} = 0b11100000000;
15863let hasNewValue = 1;
15864let opNewValue = 0;
15865let prefersSlot3 = 1;
15866let isExtendable = 1;
15867let opExtendable = 2;
15868let isExtentSigned = 0;
15869let opExtentBits = 8;
15870let opExtentAlign = 0;
15871}
15872def M2_mpysmi : HInst<
15873(outs IntRegs:$Rd32),
15874(ins IntRegs:$Rs32, m32_0Imm:$Ii),
15875"$Rd32 = mpyi($Rs32,#$Ii)",
15876tc_38382228, TypeM>, ImmRegRel {
15877let hasNewValue = 1;
15878let opNewValue = 0;
15879let CextOpcode = "M2_mpyi";
15880let InputType = "imm";
15881let isPseudo = 1;
15882let isExtendable = 1;
15883let opExtendable = 2;
15884let isExtentSigned = 1;
15885let opExtentBits = 9;
15886let opExtentAlign = 0;
15887}
15888def M2_mpysu_up : HInst<
15889(outs IntRegs:$Rd32),
15890(ins IntRegs:$Rs32, IntRegs:$Rt32),
15891"$Rd32 = mpysu($Rs32,$Rt32)",
15892tc_c21d7447, TypeM>, Enc_5ab2be {
15893let Inst{7-5} = 0b001;
15894let Inst{13-13} = 0b0;
15895let Inst{31-21} = 0b11101101011;
15896let hasNewValue = 1;
15897let opNewValue = 0;
15898let prefersSlot3 = 1;
15899}
15900def M2_mpyu_acc_hh_s0 : HInst<
15901(outs IntRegs:$Rx32),
15902(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15903"$Rx32 += mpyu($Rs32.h,$Rt32.h)",
15904tc_7f8ae742, TypeM>, Enc_2ae154 {
15905let Inst{7-5} = 0b011;
15906let Inst{13-13} = 0b0;
15907let Inst{31-21} = 0b11101110010;
15908let hasNewValue = 1;
15909let opNewValue = 0;
15910let prefersSlot3 = 1;
15911let Constraints = "$Rx32 = $Rx32in";
15912}
15913def M2_mpyu_acc_hh_s1 : HInst<
15914(outs IntRegs:$Rx32),
15915(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15916"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15917tc_7f8ae742, TypeM>, Enc_2ae154 {
15918let Inst{7-5} = 0b011;
15919let Inst{13-13} = 0b0;
15920let Inst{31-21} = 0b11101110110;
15921let hasNewValue = 1;
15922let opNewValue = 0;
15923let prefersSlot3 = 1;
15924let Constraints = "$Rx32 = $Rx32in";
15925}
15926def M2_mpyu_acc_hl_s0 : HInst<
15927(outs IntRegs:$Rx32),
15928(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15929"$Rx32 += mpyu($Rs32.h,$Rt32.l)",
15930tc_7f8ae742, TypeM>, Enc_2ae154 {
15931let Inst{7-5} = 0b010;
15932let Inst{13-13} = 0b0;
15933let Inst{31-21} = 0b11101110010;
15934let hasNewValue = 1;
15935let opNewValue = 0;
15936let prefersSlot3 = 1;
15937let Constraints = "$Rx32 = $Rx32in";
15938}
15939def M2_mpyu_acc_hl_s1 : HInst<
15940(outs IntRegs:$Rx32),
15941(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15942"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
15943tc_7f8ae742, TypeM>, Enc_2ae154 {
15944let Inst{7-5} = 0b010;
15945let Inst{13-13} = 0b0;
15946let Inst{31-21} = 0b11101110110;
15947let hasNewValue = 1;
15948let opNewValue = 0;
15949let prefersSlot3 = 1;
15950let Constraints = "$Rx32 = $Rx32in";
15951}
15952def M2_mpyu_acc_lh_s0 : HInst<
15953(outs IntRegs:$Rx32),
15954(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15955"$Rx32 += mpyu($Rs32.l,$Rt32.h)",
15956tc_7f8ae742, TypeM>, Enc_2ae154 {
15957let Inst{7-5} = 0b001;
15958let Inst{13-13} = 0b0;
15959let Inst{31-21} = 0b11101110010;
15960let hasNewValue = 1;
15961let opNewValue = 0;
15962let prefersSlot3 = 1;
15963let Constraints = "$Rx32 = $Rx32in";
15964}
15965def M2_mpyu_acc_lh_s1 : HInst<
15966(outs IntRegs:$Rx32),
15967(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15968"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
15969tc_7f8ae742, TypeM>, Enc_2ae154 {
15970let Inst{7-5} = 0b001;
15971let Inst{13-13} = 0b0;
15972let Inst{31-21} = 0b11101110110;
15973let hasNewValue = 1;
15974let opNewValue = 0;
15975let prefersSlot3 = 1;
15976let Constraints = "$Rx32 = $Rx32in";
15977}
15978def M2_mpyu_acc_ll_s0 : HInst<
15979(outs IntRegs:$Rx32),
15980(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15981"$Rx32 += mpyu($Rs32.l,$Rt32.l)",
15982tc_7f8ae742, TypeM>, Enc_2ae154 {
15983let Inst{7-5} = 0b000;
15984let Inst{13-13} = 0b0;
15985let Inst{31-21} = 0b11101110010;
15986let hasNewValue = 1;
15987let opNewValue = 0;
15988let prefersSlot3 = 1;
15989let Constraints = "$Rx32 = $Rx32in";
15990}
15991def M2_mpyu_acc_ll_s1 : HInst<
15992(outs IntRegs:$Rx32),
15993(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15994"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
15995tc_7f8ae742, TypeM>, Enc_2ae154 {
15996let Inst{7-5} = 0b000;
15997let Inst{13-13} = 0b0;
15998let Inst{31-21} = 0b11101110110;
15999let hasNewValue = 1;
16000let opNewValue = 0;
16001let prefersSlot3 = 1;
16002let Constraints = "$Rx32 = $Rx32in";
16003}
16004def M2_mpyu_hh_s0 : HInst<
16005(outs IntRegs:$Rd32),
16006(ins IntRegs:$Rs32, IntRegs:$Rt32),
16007"$Rd32 = mpyu($Rs32.h,$Rt32.h)",
16008tc_c21d7447, TypeM>, Enc_5ab2be {
16009let Inst{7-5} = 0b011;
16010let Inst{13-13} = 0b0;
16011let Inst{31-21} = 0b11101100010;
16012let hasNewValue = 1;
16013let opNewValue = 0;
16014let prefersSlot3 = 1;
16015}
16016def M2_mpyu_hh_s1 : HInst<
16017(outs IntRegs:$Rd32),
16018(ins IntRegs:$Rs32, IntRegs:$Rt32),
16019"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16020tc_c21d7447, TypeM>, Enc_5ab2be {
16021let Inst{7-5} = 0b011;
16022let Inst{13-13} = 0b0;
16023let Inst{31-21} = 0b11101100110;
16024let hasNewValue = 1;
16025let opNewValue = 0;
16026let prefersSlot3 = 1;
16027}
16028def M2_mpyu_hl_s0 : HInst<
16029(outs IntRegs:$Rd32),
16030(ins IntRegs:$Rs32, IntRegs:$Rt32),
16031"$Rd32 = mpyu($Rs32.h,$Rt32.l)",
16032tc_c21d7447, TypeM>, Enc_5ab2be {
16033let Inst{7-5} = 0b010;
16034let Inst{13-13} = 0b0;
16035let Inst{31-21} = 0b11101100010;
16036let hasNewValue = 1;
16037let opNewValue = 0;
16038let prefersSlot3 = 1;
16039}
16040def M2_mpyu_hl_s1 : HInst<
16041(outs IntRegs:$Rd32),
16042(ins IntRegs:$Rs32, IntRegs:$Rt32),
16043"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16044tc_c21d7447, TypeM>, Enc_5ab2be {
16045let Inst{7-5} = 0b010;
16046let Inst{13-13} = 0b0;
16047let Inst{31-21} = 0b11101100110;
16048let hasNewValue = 1;
16049let opNewValue = 0;
16050let prefersSlot3 = 1;
16051}
16052def M2_mpyu_lh_s0 : HInst<
16053(outs IntRegs:$Rd32),
16054(ins IntRegs:$Rs32, IntRegs:$Rt32),
16055"$Rd32 = mpyu($Rs32.l,$Rt32.h)",
16056tc_c21d7447, TypeM>, Enc_5ab2be {
16057let Inst{7-5} = 0b001;
16058let Inst{13-13} = 0b0;
16059let Inst{31-21} = 0b11101100010;
16060let hasNewValue = 1;
16061let opNewValue = 0;
16062let prefersSlot3 = 1;
16063}
16064def M2_mpyu_lh_s1 : HInst<
16065(outs IntRegs:$Rd32),
16066(ins IntRegs:$Rs32, IntRegs:$Rt32),
16067"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16068tc_c21d7447, TypeM>, Enc_5ab2be {
16069let Inst{7-5} = 0b001;
16070let Inst{13-13} = 0b0;
16071let Inst{31-21} = 0b11101100110;
16072let hasNewValue = 1;
16073let opNewValue = 0;
16074let prefersSlot3 = 1;
16075}
16076def M2_mpyu_ll_s0 : HInst<
16077(outs IntRegs:$Rd32),
16078(ins IntRegs:$Rs32, IntRegs:$Rt32),
16079"$Rd32 = mpyu($Rs32.l,$Rt32.l)",
16080tc_c21d7447, TypeM>, Enc_5ab2be {
16081let Inst{7-5} = 0b000;
16082let Inst{13-13} = 0b0;
16083let Inst{31-21} = 0b11101100010;
16084let hasNewValue = 1;
16085let opNewValue = 0;
16086let prefersSlot3 = 1;
16087}
16088def M2_mpyu_ll_s1 : HInst<
16089(outs IntRegs:$Rd32),
16090(ins IntRegs:$Rs32, IntRegs:$Rt32),
16091"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16092tc_c21d7447, TypeM>, Enc_5ab2be {
16093let Inst{7-5} = 0b000;
16094let Inst{13-13} = 0b0;
16095let Inst{31-21} = 0b11101100110;
16096let hasNewValue = 1;
16097let opNewValue = 0;
16098let prefersSlot3 = 1;
16099}
16100def M2_mpyu_nac_hh_s0 : HInst<
16101(outs IntRegs:$Rx32),
16102(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16103"$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
16104tc_7f8ae742, TypeM>, Enc_2ae154 {
16105let Inst{7-5} = 0b011;
16106let Inst{13-13} = 0b0;
16107let Inst{31-21} = 0b11101110011;
16108let hasNewValue = 1;
16109let opNewValue = 0;
16110let prefersSlot3 = 1;
16111let Constraints = "$Rx32 = $Rx32in";
16112}
16113def M2_mpyu_nac_hh_s1 : HInst<
16114(outs IntRegs:$Rx32),
16115(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16116"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16117tc_7f8ae742, TypeM>, Enc_2ae154 {
16118let Inst{7-5} = 0b011;
16119let Inst{13-13} = 0b0;
16120let Inst{31-21} = 0b11101110111;
16121let hasNewValue = 1;
16122let opNewValue = 0;
16123let prefersSlot3 = 1;
16124let Constraints = "$Rx32 = $Rx32in";
16125}
16126def M2_mpyu_nac_hl_s0 : HInst<
16127(outs IntRegs:$Rx32),
16128(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16129"$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
16130tc_7f8ae742, TypeM>, Enc_2ae154 {
16131let Inst{7-5} = 0b010;
16132let Inst{13-13} = 0b0;
16133let Inst{31-21} = 0b11101110011;
16134let hasNewValue = 1;
16135let opNewValue = 0;
16136let prefersSlot3 = 1;
16137let Constraints = "$Rx32 = $Rx32in";
16138}
16139def M2_mpyu_nac_hl_s1 : HInst<
16140(outs IntRegs:$Rx32),
16141(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16142"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16143tc_7f8ae742, TypeM>, Enc_2ae154 {
16144let Inst{7-5} = 0b010;
16145let Inst{13-13} = 0b0;
16146let Inst{31-21} = 0b11101110111;
16147let hasNewValue = 1;
16148let opNewValue = 0;
16149let prefersSlot3 = 1;
16150let Constraints = "$Rx32 = $Rx32in";
16151}
16152def M2_mpyu_nac_lh_s0 : HInst<
16153(outs IntRegs:$Rx32),
16154(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16155"$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
16156tc_7f8ae742, TypeM>, Enc_2ae154 {
16157let Inst{7-5} = 0b001;
16158let Inst{13-13} = 0b0;
16159let Inst{31-21} = 0b11101110011;
16160let hasNewValue = 1;
16161let opNewValue = 0;
16162let prefersSlot3 = 1;
16163let Constraints = "$Rx32 = $Rx32in";
16164}
16165def M2_mpyu_nac_lh_s1 : HInst<
16166(outs IntRegs:$Rx32),
16167(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16168"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16169tc_7f8ae742, TypeM>, Enc_2ae154 {
16170let Inst{7-5} = 0b001;
16171let Inst{13-13} = 0b0;
16172let Inst{31-21} = 0b11101110111;
16173let hasNewValue = 1;
16174let opNewValue = 0;
16175let prefersSlot3 = 1;
16176let Constraints = "$Rx32 = $Rx32in";
16177}
16178def M2_mpyu_nac_ll_s0 : HInst<
16179(outs IntRegs:$Rx32),
16180(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16181"$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
16182tc_7f8ae742, TypeM>, Enc_2ae154 {
16183let Inst{7-5} = 0b000;
16184let Inst{13-13} = 0b0;
16185let Inst{31-21} = 0b11101110011;
16186let hasNewValue = 1;
16187let opNewValue = 0;
16188let prefersSlot3 = 1;
16189let Constraints = "$Rx32 = $Rx32in";
16190}
16191def M2_mpyu_nac_ll_s1 : HInst<
16192(outs IntRegs:$Rx32),
16193(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16194"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16195tc_7f8ae742, TypeM>, Enc_2ae154 {
16196let Inst{7-5} = 0b000;
16197let Inst{13-13} = 0b0;
16198let Inst{31-21} = 0b11101110111;
16199let hasNewValue = 1;
16200let opNewValue = 0;
16201let prefersSlot3 = 1;
16202let Constraints = "$Rx32 = $Rx32in";
16203}
16204def M2_mpyu_up : HInst<
16205(outs IntRegs:$Rd32),
16206(ins IntRegs:$Rs32, IntRegs:$Rt32),
16207"$Rd32 = mpyu($Rs32,$Rt32)",
16208tc_c21d7447, TypeM>, Enc_5ab2be {
16209let Inst{7-5} = 0b001;
16210let Inst{13-13} = 0b0;
16211let Inst{31-21} = 0b11101101010;
16212let hasNewValue = 1;
16213let opNewValue = 0;
16214let prefersSlot3 = 1;
16215}
16216def M2_mpyud_acc_hh_s0 : HInst<
16217(outs DoubleRegs:$Rxx32),
16218(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16219"$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
16220tc_7f8ae742, TypeM>, Enc_61f0b0 {
16221let Inst{7-5} = 0b011;
16222let Inst{13-13} = 0b0;
16223let Inst{31-21} = 0b11100110010;
16224let prefersSlot3 = 1;
16225let Constraints = "$Rxx32 = $Rxx32in";
16226}
16227def M2_mpyud_acc_hh_s1 : HInst<
16228(outs DoubleRegs:$Rxx32),
16229(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16230"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
16231tc_7f8ae742, TypeM>, Enc_61f0b0 {
16232let Inst{7-5} = 0b011;
16233let Inst{13-13} = 0b0;
16234let Inst{31-21} = 0b11100110110;
16235let prefersSlot3 = 1;
16236let Constraints = "$Rxx32 = $Rxx32in";
16237}
16238def M2_mpyud_acc_hl_s0 : HInst<
16239(outs DoubleRegs:$Rxx32),
16240(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16241"$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
16242tc_7f8ae742, TypeM>, Enc_61f0b0 {
16243let Inst{7-5} = 0b010;
16244let Inst{13-13} = 0b0;
16245let Inst{31-21} = 0b11100110010;
16246let prefersSlot3 = 1;
16247let Constraints = "$Rxx32 = $Rxx32in";
16248}
16249def M2_mpyud_acc_hl_s1 : HInst<
16250(outs DoubleRegs:$Rxx32),
16251(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16252"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
16253tc_7f8ae742, TypeM>, Enc_61f0b0 {
16254let Inst{7-5} = 0b010;
16255let Inst{13-13} = 0b0;
16256let Inst{31-21} = 0b11100110110;
16257let prefersSlot3 = 1;
16258let Constraints = "$Rxx32 = $Rxx32in";
16259}
16260def M2_mpyud_acc_lh_s0 : HInst<
16261(outs DoubleRegs:$Rxx32),
16262(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16263"$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
16264tc_7f8ae742, TypeM>, Enc_61f0b0 {
16265let Inst{7-5} = 0b001;
16266let Inst{13-13} = 0b0;
16267let Inst{31-21} = 0b11100110010;
16268let prefersSlot3 = 1;
16269let Constraints = "$Rxx32 = $Rxx32in";
16270}
16271def M2_mpyud_acc_lh_s1 : HInst<
16272(outs DoubleRegs:$Rxx32),
16273(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16274"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16275tc_7f8ae742, TypeM>, Enc_61f0b0 {
16276let Inst{7-5} = 0b001;
16277let Inst{13-13} = 0b0;
16278let Inst{31-21} = 0b11100110110;
16279let prefersSlot3 = 1;
16280let Constraints = "$Rxx32 = $Rxx32in";
16281}
16282def M2_mpyud_acc_ll_s0 : HInst<
16283(outs DoubleRegs:$Rxx32),
16284(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16285"$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
16286tc_7f8ae742, TypeM>, Enc_61f0b0 {
16287let Inst{7-5} = 0b000;
16288let Inst{13-13} = 0b0;
16289let Inst{31-21} = 0b11100110010;
16290let prefersSlot3 = 1;
16291let Constraints = "$Rxx32 = $Rxx32in";
16292}
16293def M2_mpyud_acc_ll_s1 : HInst<
16294(outs DoubleRegs:$Rxx32),
16295(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16296"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16297tc_7f8ae742, TypeM>, Enc_61f0b0 {
16298let Inst{7-5} = 0b000;
16299let Inst{13-13} = 0b0;
16300let Inst{31-21} = 0b11100110110;
16301let prefersSlot3 = 1;
16302let Constraints = "$Rxx32 = $Rxx32in";
16303}
16304def M2_mpyud_hh_s0 : HInst<
16305(outs DoubleRegs:$Rdd32),
16306(ins IntRegs:$Rs32, IntRegs:$Rt32),
16307"$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
16308tc_c21d7447, TypeM>, Enc_be32a5 {
16309let Inst{7-5} = 0b011;
16310let Inst{13-13} = 0b0;
16311let Inst{31-21} = 0b11100100010;
16312let prefersSlot3 = 1;
16313}
16314def M2_mpyud_hh_s1 : HInst<
16315(outs DoubleRegs:$Rdd32),
16316(ins IntRegs:$Rs32, IntRegs:$Rt32),
16317"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16318tc_c21d7447, TypeM>, Enc_be32a5 {
16319let Inst{7-5} = 0b011;
16320let Inst{13-13} = 0b0;
16321let Inst{31-21} = 0b11100100110;
16322let prefersSlot3 = 1;
16323}
16324def M2_mpyud_hl_s0 : HInst<
16325(outs DoubleRegs:$Rdd32),
16326(ins IntRegs:$Rs32, IntRegs:$Rt32),
16327"$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
16328tc_c21d7447, TypeM>, Enc_be32a5 {
16329let Inst{7-5} = 0b010;
16330let Inst{13-13} = 0b0;
16331let Inst{31-21} = 0b11100100010;
16332let prefersSlot3 = 1;
16333}
16334def M2_mpyud_hl_s1 : HInst<
16335(outs DoubleRegs:$Rdd32),
16336(ins IntRegs:$Rs32, IntRegs:$Rt32),
16337"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16338tc_c21d7447, TypeM>, Enc_be32a5 {
16339let Inst{7-5} = 0b010;
16340let Inst{13-13} = 0b0;
16341let Inst{31-21} = 0b11100100110;
16342let prefersSlot3 = 1;
16343}
16344def M2_mpyud_lh_s0 : HInst<
16345(outs DoubleRegs:$Rdd32),
16346(ins IntRegs:$Rs32, IntRegs:$Rt32),
16347"$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
16348tc_c21d7447, TypeM>, Enc_be32a5 {
16349let Inst{7-5} = 0b001;
16350let Inst{13-13} = 0b0;
16351let Inst{31-21} = 0b11100100010;
16352let prefersSlot3 = 1;
16353}
16354def M2_mpyud_lh_s1 : HInst<
16355(outs DoubleRegs:$Rdd32),
16356(ins IntRegs:$Rs32, IntRegs:$Rt32),
16357"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16358tc_c21d7447, TypeM>, Enc_be32a5 {
16359let Inst{7-5} = 0b001;
16360let Inst{13-13} = 0b0;
16361let Inst{31-21} = 0b11100100110;
16362let prefersSlot3 = 1;
16363}
16364def M2_mpyud_ll_s0 : HInst<
16365(outs DoubleRegs:$Rdd32),
16366(ins IntRegs:$Rs32, IntRegs:$Rt32),
16367"$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
16368tc_c21d7447, TypeM>, Enc_be32a5 {
16369let Inst{7-5} = 0b000;
16370let Inst{13-13} = 0b0;
16371let Inst{31-21} = 0b11100100010;
16372let prefersSlot3 = 1;
16373}
16374def M2_mpyud_ll_s1 : HInst<
16375(outs DoubleRegs:$Rdd32),
16376(ins IntRegs:$Rs32, IntRegs:$Rt32),
16377"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16378tc_c21d7447, TypeM>, Enc_be32a5 {
16379let Inst{7-5} = 0b000;
16380let Inst{13-13} = 0b0;
16381let Inst{31-21} = 0b11100100110;
16382let prefersSlot3 = 1;
16383}
16384def M2_mpyud_nac_hh_s0 : HInst<
16385(outs DoubleRegs:$Rxx32),
16386(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16387"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
16388tc_7f8ae742, TypeM>, Enc_61f0b0 {
16389let Inst{7-5} = 0b011;
16390let Inst{13-13} = 0b0;
16391let Inst{31-21} = 0b11100110011;
16392let prefersSlot3 = 1;
16393let Constraints = "$Rxx32 = $Rxx32in";
16394}
16395def M2_mpyud_nac_hh_s1 : HInst<
16396(outs DoubleRegs:$Rxx32),
16397(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16398"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16399tc_7f8ae742, TypeM>, Enc_61f0b0 {
16400let Inst{7-5} = 0b011;
16401let Inst{13-13} = 0b0;
16402let Inst{31-21} = 0b11100110111;
16403let prefersSlot3 = 1;
16404let Constraints = "$Rxx32 = $Rxx32in";
16405}
16406def M2_mpyud_nac_hl_s0 : HInst<
16407(outs DoubleRegs:$Rxx32),
16408(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16409"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
16410tc_7f8ae742, TypeM>, Enc_61f0b0 {
16411let Inst{7-5} = 0b010;
16412let Inst{13-13} = 0b0;
16413let Inst{31-21} = 0b11100110011;
16414let prefersSlot3 = 1;
16415let Constraints = "$Rxx32 = $Rxx32in";
16416}
16417def M2_mpyud_nac_hl_s1 : HInst<
16418(outs DoubleRegs:$Rxx32),
16419(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16420"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16421tc_7f8ae742, TypeM>, Enc_61f0b0 {
16422let Inst{7-5} = 0b010;
16423let Inst{13-13} = 0b0;
16424let Inst{31-21} = 0b11100110111;
16425let prefersSlot3 = 1;
16426let Constraints = "$Rxx32 = $Rxx32in";
16427}
16428def M2_mpyud_nac_lh_s0 : HInst<
16429(outs DoubleRegs:$Rxx32),
16430(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16431"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
16432tc_7f8ae742, TypeM>, Enc_61f0b0 {
16433let Inst{7-5} = 0b001;
16434let Inst{13-13} = 0b0;
16435let Inst{31-21} = 0b11100110011;
16436let prefersSlot3 = 1;
16437let Constraints = "$Rxx32 = $Rxx32in";
16438}
16439def M2_mpyud_nac_lh_s1 : HInst<
16440(outs DoubleRegs:$Rxx32),
16441(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16442"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16443tc_7f8ae742, TypeM>, Enc_61f0b0 {
16444let Inst{7-5} = 0b001;
16445let Inst{13-13} = 0b0;
16446let Inst{31-21} = 0b11100110111;
16447let prefersSlot3 = 1;
16448let Constraints = "$Rxx32 = $Rxx32in";
16449}
16450def M2_mpyud_nac_ll_s0 : HInst<
16451(outs DoubleRegs:$Rxx32),
16452(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16453"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
16454tc_7f8ae742, TypeM>, Enc_61f0b0 {
16455let Inst{7-5} = 0b000;
16456let Inst{13-13} = 0b0;
16457let Inst{31-21} = 0b11100110011;
16458let prefersSlot3 = 1;
16459let Constraints = "$Rxx32 = $Rxx32in";
16460}
16461def M2_mpyud_nac_ll_s1 : HInst<
16462(outs DoubleRegs:$Rxx32),
16463(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16464"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16465tc_7f8ae742, TypeM>, Enc_61f0b0 {
16466let Inst{7-5} = 0b000;
16467let Inst{13-13} = 0b0;
16468let Inst{31-21} = 0b11100110111;
16469let prefersSlot3 = 1;
16470let Constraints = "$Rxx32 = $Rxx32in";
16471}
16472def M2_mpyui : HInst<
16473(outs IntRegs:$Rd32),
16474(ins IntRegs:$Rs32, IntRegs:$Rt32),
16475"$Rd32 = mpyui($Rs32,$Rt32)",
16476tc_c21d7447, TypeM> {
16477let hasNewValue = 1;
16478let opNewValue = 0;
16479let isPseudo = 1;
16480let isCodeGenOnly = 1;
16481}
16482def M2_nacci : HInst<
16483(outs IntRegs:$Rx32),
16484(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16485"$Rx32 -= add($Rs32,$Rt32)",
16486tc_2c13e7f5, TypeM>, Enc_2ae154 {
16487let Inst{7-5} = 0b001;
16488let Inst{13-13} = 0b0;
16489let Inst{31-21} = 0b11101111100;
16490let hasNewValue = 1;
16491let opNewValue = 0;
16492let prefersSlot3 = 1;
16493let InputType = "reg";
16494let Constraints = "$Rx32 = $Rx32in";
16495}
16496def M2_naccii : HInst<
16497(outs IntRegs:$Rx32),
16498(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
16499"$Rx32 -= add($Rs32,#$Ii)",
16500tc_2c13e7f5, TypeM>, Enc_c90aca {
16501let Inst{13-13} = 0b0;
16502let Inst{31-21} = 0b11100010100;
16503let hasNewValue = 1;
16504let opNewValue = 0;
16505let prefersSlot3 = 1;
16506let InputType = "imm";
16507let isExtendable = 1;
16508let opExtendable = 3;
16509let isExtentSigned = 1;
16510let opExtentBits = 8;
16511let opExtentAlign = 0;
16512let Constraints = "$Rx32 = $Rx32in";
16513}
16514def M2_subacc : HInst<
16515(outs IntRegs:$Rx32),
16516(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
16517"$Rx32 += sub($Rt32,$Rs32)",
16518tc_2c13e7f5, TypeM>, Enc_a568d4 {
16519let Inst{7-5} = 0b011;
16520let Inst{13-13} = 0b0;
16521let Inst{31-21} = 0b11101111000;
16522let hasNewValue = 1;
16523let opNewValue = 0;
16524let prefersSlot3 = 1;
16525let InputType = "reg";
16526let Constraints = "$Rx32 = $Rx32in";
16527}
16528def M2_vabsdiffh : HInst<
16529(outs DoubleRegs:$Rdd32),
16530(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16531"$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
16532tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16533let Inst{7-5} = 0b000;
16534let Inst{13-13} = 0b0;
16535let Inst{31-21} = 0b11101000011;
16536let prefersSlot3 = 1;
16537}
16538def M2_vabsdiffw : HInst<
16539(outs DoubleRegs:$Rdd32),
16540(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16541"$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
16542tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16543let Inst{7-5} = 0b000;
16544let Inst{13-13} = 0b0;
16545let Inst{31-21} = 0b11101000001;
16546let prefersSlot3 = 1;
16547}
16548def M2_vcmac_s0_sat_i : HInst<
16549(outs DoubleRegs:$Rxx32),
16550(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16551"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
16552tc_7f8ae742, TypeM>, Enc_88c16c {
16553let Inst{7-5} = 0b100;
16554let Inst{13-13} = 0b0;
16555let Inst{31-21} = 0b11101010010;
16556let prefersSlot3 = 1;
16557let Defs = [USR_OVF];
16558let Constraints = "$Rxx32 = $Rxx32in";
16559}
16560def M2_vcmac_s0_sat_r : HInst<
16561(outs DoubleRegs:$Rxx32),
16562(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16563"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
16564tc_7f8ae742, TypeM>, Enc_88c16c {
16565let Inst{7-5} = 0b100;
16566let Inst{13-13} = 0b0;
16567let Inst{31-21} = 0b11101010001;
16568let prefersSlot3 = 1;
16569let Defs = [USR_OVF];
16570let Constraints = "$Rxx32 = $Rxx32in";
16571}
16572def M2_vcmpy_s0_sat_i : HInst<
16573(outs DoubleRegs:$Rdd32),
16574(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16575"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
16576tc_c21d7447, TypeM>, Enc_a56825 {
16577let Inst{7-5} = 0b110;
16578let Inst{13-13} = 0b0;
16579let Inst{31-21} = 0b11101000010;
16580let prefersSlot3 = 1;
16581let Defs = [USR_OVF];
16582}
16583def M2_vcmpy_s0_sat_r : HInst<
16584(outs DoubleRegs:$Rdd32),
16585(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16586"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
16587tc_c21d7447, TypeM>, Enc_a56825 {
16588let Inst{7-5} = 0b110;
16589let Inst{13-13} = 0b0;
16590let Inst{31-21} = 0b11101000001;
16591let prefersSlot3 = 1;
16592let Defs = [USR_OVF];
16593}
16594def M2_vcmpy_s1_sat_i : HInst<
16595(outs DoubleRegs:$Rdd32),
16596(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16597"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
16598tc_c21d7447, TypeM>, Enc_a56825 {
16599let Inst{7-5} = 0b110;
16600let Inst{13-13} = 0b0;
16601let Inst{31-21} = 0b11101000110;
16602let prefersSlot3 = 1;
16603let Defs = [USR_OVF];
16604}
16605def M2_vcmpy_s1_sat_r : HInst<
16606(outs DoubleRegs:$Rdd32),
16607(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16608"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
16609tc_c21d7447, TypeM>, Enc_a56825 {
16610let Inst{7-5} = 0b110;
16611let Inst{13-13} = 0b0;
16612let Inst{31-21} = 0b11101000101;
16613let prefersSlot3 = 1;
16614let Defs = [USR_OVF];
16615}
16616def M2_vdmacs_s0 : HInst<
16617(outs DoubleRegs:$Rxx32),
16618(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16619"$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
16620tc_7f8ae742, TypeM>, Enc_88c16c {
16621let Inst{7-5} = 0b100;
16622let Inst{13-13} = 0b0;
16623let Inst{31-21} = 0b11101010000;
16624let prefersSlot3 = 1;
16625let Defs = [USR_OVF];
16626let Constraints = "$Rxx32 = $Rxx32in";
16627}
16628def M2_vdmacs_s1 : HInst<
16629(outs DoubleRegs:$Rxx32),
16630(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16631"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
16632tc_7f8ae742, TypeM>, Enc_88c16c {
16633let Inst{7-5} = 0b100;
16634let Inst{13-13} = 0b0;
16635let Inst{31-21} = 0b11101010100;
16636let prefersSlot3 = 1;
16637let Defs = [USR_OVF];
16638let Constraints = "$Rxx32 = $Rxx32in";
16639}
16640def M2_vdmpyrs_s0 : HInst<
16641(outs IntRegs:$Rd32),
16642(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16643"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
16644tc_c21d7447, TypeM>, Enc_d2216a {
16645let Inst{7-5} = 0b000;
16646let Inst{13-13} = 0b0;
16647let Inst{31-21} = 0b11101001000;
16648let hasNewValue = 1;
16649let opNewValue = 0;
16650let prefersSlot3 = 1;
16651let Defs = [USR_OVF];
16652}
16653def M2_vdmpyrs_s1 : HInst<
16654(outs IntRegs:$Rd32),
16655(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16656"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
16657tc_c21d7447, TypeM>, Enc_d2216a {
16658let Inst{7-5} = 0b000;
16659let Inst{13-13} = 0b0;
16660let Inst{31-21} = 0b11101001100;
16661let hasNewValue = 1;
16662let opNewValue = 0;
16663let prefersSlot3 = 1;
16664let Defs = [USR_OVF];
16665}
16666def M2_vdmpys_s0 : HInst<
16667(outs DoubleRegs:$Rdd32),
16668(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16669"$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
16670tc_c21d7447, TypeM>, Enc_a56825 {
16671let Inst{7-5} = 0b100;
16672let Inst{13-13} = 0b0;
16673let Inst{31-21} = 0b11101000000;
16674let prefersSlot3 = 1;
16675let Defs = [USR_OVF];
16676}
16677def M2_vdmpys_s1 : HInst<
16678(outs DoubleRegs:$Rdd32),
16679(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16680"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
16681tc_c21d7447, TypeM>, Enc_a56825 {
16682let Inst{7-5} = 0b100;
16683let Inst{13-13} = 0b0;
16684let Inst{31-21} = 0b11101000100;
16685let prefersSlot3 = 1;
16686let Defs = [USR_OVF];
16687}
16688def M2_vmac2 : HInst<
16689(outs DoubleRegs:$Rxx32),
16690(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16691"$Rxx32 += vmpyh($Rs32,$Rt32)",
16692tc_7f8ae742, TypeM>, Enc_61f0b0 {
16693let Inst{7-5} = 0b001;
16694let Inst{13-13} = 0b0;
16695let Inst{31-21} = 0b11100111001;
16696let prefersSlot3 = 1;
16697let Constraints = "$Rxx32 = $Rxx32in";
16698}
16699def M2_vmac2es : HInst<
16700(outs DoubleRegs:$Rxx32),
16701(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16702"$Rxx32 += vmpyeh($Rss32,$Rtt32)",
16703tc_7f8ae742, TypeM>, Enc_88c16c {
16704let Inst{7-5} = 0b010;
16705let Inst{13-13} = 0b0;
16706let Inst{31-21} = 0b11101010001;
16707let prefersSlot3 = 1;
16708let Constraints = "$Rxx32 = $Rxx32in";
16709}
16710def M2_vmac2es_s0 : HInst<
16711(outs DoubleRegs:$Rxx32),
16712(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16713"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
16714tc_7f8ae742, TypeM>, Enc_88c16c {
16715let Inst{7-5} = 0b110;
16716let Inst{13-13} = 0b0;
16717let Inst{31-21} = 0b11101010000;
16718let prefersSlot3 = 1;
16719let Defs = [USR_OVF];
16720let Constraints = "$Rxx32 = $Rxx32in";
16721}
16722def M2_vmac2es_s1 : HInst<
16723(outs DoubleRegs:$Rxx32),
16724(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16725"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
16726tc_7f8ae742, TypeM>, Enc_88c16c {
16727let Inst{7-5} = 0b110;
16728let Inst{13-13} = 0b0;
16729let Inst{31-21} = 0b11101010100;
16730let prefersSlot3 = 1;
16731let Defs = [USR_OVF];
16732let Constraints = "$Rxx32 = $Rxx32in";
16733}
16734def M2_vmac2s_s0 : HInst<
16735(outs DoubleRegs:$Rxx32),
16736(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16737"$Rxx32 += vmpyh($Rs32,$Rt32):sat",
16738tc_7f8ae742, TypeM>, Enc_61f0b0 {
16739let Inst{7-5} = 0b101;
16740let Inst{13-13} = 0b0;
16741let Inst{31-21} = 0b11100111000;
16742let prefersSlot3 = 1;
16743let Defs = [USR_OVF];
16744let Constraints = "$Rxx32 = $Rxx32in";
16745}
16746def M2_vmac2s_s1 : HInst<
16747(outs DoubleRegs:$Rxx32),
16748(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16749"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
16750tc_7f8ae742, TypeM>, Enc_61f0b0 {
16751let Inst{7-5} = 0b101;
16752let Inst{13-13} = 0b0;
16753let Inst{31-21} = 0b11100111100;
16754let prefersSlot3 = 1;
16755let Defs = [USR_OVF];
16756let Constraints = "$Rxx32 = $Rxx32in";
16757}
16758def M2_vmac2su_s0 : HInst<
16759(outs DoubleRegs:$Rxx32),
16760(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16761"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
16762tc_7f8ae742, TypeM>, Enc_61f0b0 {
16763let Inst{7-5} = 0b101;
16764let Inst{13-13} = 0b0;
16765let Inst{31-21} = 0b11100111011;
16766let prefersSlot3 = 1;
16767let Defs = [USR_OVF];
16768let Constraints = "$Rxx32 = $Rxx32in";
16769}
16770def M2_vmac2su_s1 : HInst<
16771(outs DoubleRegs:$Rxx32),
16772(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16773"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
16774tc_7f8ae742, TypeM>, Enc_61f0b0 {
16775let Inst{7-5} = 0b101;
16776let Inst{13-13} = 0b0;
16777let Inst{31-21} = 0b11100111111;
16778let prefersSlot3 = 1;
16779let Defs = [USR_OVF];
16780let Constraints = "$Rxx32 = $Rxx32in";
16781}
16782def M2_vmpy2es_s0 : HInst<
16783(outs DoubleRegs:$Rdd32),
16784(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16785"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
16786tc_c21d7447, TypeM>, Enc_a56825 {
16787let Inst{7-5} = 0b110;
16788let Inst{13-13} = 0b0;
16789let Inst{31-21} = 0b11101000000;
16790let prefersSlot3 = 1;
16791let Defs = [USR_OVF];
16792}
16793def M2_vmpy2es_s1 : HInst<
16794(outs DoubleRegs:$Rdd32),
16795(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16796"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
16797tc_c21d7447, TypeM>, Enc_a56825 {
16798let Inst{7-5} = 0b110;
16799let Inst{13-13} = 0b0;
16800let Inst{31-21} = 0b11101000100;
16801let prefersSlot3 = 1;
16802let Defs = [USR_OVF];
16803}
16804def M2_vmpy2s_s0 : HInst<
16805(outs DoubleRegs:$Rdd32),
16806(ins IntRegs:$Rs32, IntRegs:$Rt32),
16807"$Rdd32 = vmpyh($Rs32,$Rt32):sat",
16808tc_c21d7447, TypeM>, Enc_be32a5 {
16809let Inst{7-5} = 0b101;
16810let Inst{13-13} = 0b0;
16811let Inst{31-21} = 0b11100101000;
16812let prefersSlot3 = 1;
16813let Defs = [USR_OVF];
16814}
16815def M2_vmpy2s_s0pack : HInst<
16816(outs IntRegs:$Rd32),
16817(ins IntRegs:$Rs32, IntRegs:$Rt32),
16818"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
16819tc_c21d7447, TypeM>, Enc_5ab2be {
16820let Inst{7-5} = 0b111;
16821let Inst{13-13} = 0b0;
16822let Inst{31-21} = 0b11101101001;
16823let hasNewValue = 1;
16824let opNewValue = 0;
16825let prefersSlot3 = 1;
16826let Defs = [USR_OVF];
16827}
16828def M2_vmpy2s_s1 : HInst<
16829(outs DoubleRegs:$Rdd32),
16830(ins IntRegs:$Rs32, IntRegs:$Rt32),
16831"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
16832tc_c21d7447, TypeM>, Enc_be32a5 {
16833let Inst{7-5} = 0b101;
16834let Inst{13-13} = 0b0;
16835let Inst{31-21} = 0b11100101100;
16836let prefersSlot3 = 1;
16837let Defs = [USR_OVF];
16838}
16839def M2_vmpy2s_s1pack : HInst<
16840(outs IntRegs:$Rd32),
16841(ins IntRegs:$Rs32, IntRegs:$Rt32),
16842"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
16843tc_c21d7447, TypeM>, Enc_5ab2be {
16844let Inst{7-5} = 0b111;
16845let Inst{13-13} = 0b0;
16846let Inst{31-21} = 0b11101101101;
16847let hasNewValue = 1;
16848let opNewValue = 0;
16849let prefersSlot3 = 1;
16850let Defs = [USR_OVF];
16851}
16852def M2_vmpy2su_s0 : HInst<
16853(outs DoubleRegs:$Rdd32),
16854(ins IntRegs:$Rs32, IntRegs:$Rt32),
16855"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
16856tc_c21d7447, TypeM>, Enc_be32a5 {
16857let Inst{7-5} = 0b111;
16858let Inst{13-13} = 0b0;
16859let Inst{31-21} = 0b11100101000;
16860let prefersSlot3 = 1;
16861let Defs = [USR_OVF];
16862}
16863def M2_vmpy2su_s1 : HInst<
16864(outs DoubleRegs:$Rdd32),
16865(ins IntRegs:$Rs32, IntRegs:$Rt32),
16866"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
16867tc_c21d7447, TypeM>, Enc_be32a5 {
16868let Inst{7-5} = 0b111;
16869let Inst{13-13} = 0b0;
16870let Inst{31-21} = 0b11100101100;
16871let prefersSlot3 = 1;
16872let Defs = [USR_OVF];
16873}
16874def M2_vraddh : HInst<
16875(outs IntRegs:$Rd32),
16876(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16877"$Rd32 = vraddh($Rss32,$Rtt32)",
16878tc_c21d7447, TypeM>, Enc_d2216a {
16879let Inst{7-5} = 0b111;
16880let Inst{13-13} = 0b0;
16881let Inst{31-21} = 0b11101001001;
16882let hasNewValue = 1;
16883let opNewValue = 0;
16884let prefersSlot3 = 1;
16885}
16886def M2_vradduh : HInst<
16887(outs IntRegs:$Rd32),
16888(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16889"$Rd32 = vradduh($Rss32,$Rtt32)",
16890tc_c21d7447, TypeM>, Enc_d2216a {
16891let Inst{7-5} = 0b001;
16892let Inst{13-13} = 0b0;
16893let Inst{31-21} = 0b11101001000;
16894let hasNewValue = 1;
16895let opNewValue = 0;
16896let prefersSlot3 = 1;
16897}
16898def M2_vrcmaci_s0 : HInst<
16899(outs DoubleRegs:$Rxx32),
16900(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16901"$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
16902tc_7f8ae742, TypeM>, Enc_88c16c {
16903let Inst{7-5} = 0b000;
16904let Inst{13-13} = 0b0;
16905let Inst{31-21} = 0b11101010000;
16906let prefersSlot3 = 1;
16907let Constraints = "$Rxx32 = $Rxx32in";
16908}
16909def M2_vrcmaci_s0c : HInst<
16910(outs DoubleRegs:$Rxx32),
16911(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16912"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
16913tc_7f8ae742, TypeM>, Enc_88c16c {
16914let Inst{7-5} = 0b000;
16915let Inst{13-13} = 0b0;
16916let Inst{31-21} = 0b11101010010;
16917let prefersSlot3 = 1;
16918let Constraints = "$Rxx32 = $Rxx32in";
16919}
16920def M2_vrcmacr_s0 : HInst<
16921(outs DoubleRegs:$Rxx32),
16922(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16923"$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
16924tc_7f8ae742, TypeM>, Enc_88c16c {
16925let Inst{7-5} = 0b001;
16926let Inst{13-13} = 0b0;
16927let Inst{31-21} = 0b11101010000;
16928let prefersSlot3 = 1;
16929let Constraints = "$Rxx32 = $Rxx32in";
16930}
16931def M2_vrcmacr_s0c : HInst<
16932(outs DoubleRegs:$Rxx32),
16933(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16934"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
16935tc_7f8ae742, TypeM>, Enc_88c16c {
16936let Inst{7-5} = 0b001;
16937let Inst{13-13} = 0b0;
16938let Inst{31-21} = 0b11101010011;
16939let prefersSlot3 = 1;
16940let Constraints = "$Rxx32 = $Rxx32in";
16941}
16942def M2_vrcmpyi_s0 : HInst<
16943(outs DoubleRegs:$Rdd32),
16944(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16945"$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
16946tc_c21d7447, TypeM>, Enc_a56825 {
16947let Inst{7-5} = 0b000;
16948let Inst{13-13} = 0b0;
16949let Inst{31-21} = 0b11101000000;
16950let prefersSlot3 = 1;
16951}
16952def M2_vrcmpyi_s0c : HInst<
16953(outs DoubleRegs:$Rdd32),
16954(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16955"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
16956tc_c21d7447, TypeM>, Enc_a56825 {
16957let Inst{7-5} = 0b000;
16958let Inst{13-13} = 0b0;
16959let Inst{31-21} = 0b11101000010;
16960let prefersSlot3 = 1;
16961}
16962def M2_vrcmpyr_s0 : HInst<
16963(outs DoubleRegs:$Rdd32),
16964(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16965"$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
16966tc_c21d7447, TypeM>, Enc_a56825 {
16967let Inst{7-5} = 0b001;
16968let Inst{13-13} = 0b0;
16969let Inst{31-21} = 0b11101000000;
16970let prefersSlot3 = 1;
16971}
16972def M2_vrcmpyr_s0c : HInst<
16973(outs DoubleRegs:$Rdd32),
16974(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16975"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
16976tc_c21d7447, TypeM>, Enc_a56825 {
16977let Inst{7-5} = 0b001;
16978let Inst{13-13} = 0b0;
16979let Inst{31-21} = 0b11101000011;
16980let prefersSlot3 = 1;
16981}
16982def M2_vrcmpys_acc_s1 : HInst<
16983(outs DoubleRegs:$Rxx32),
16984(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
16985"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
16986tc_7f8ae742, TypeM> {
16987let isPseudo = 1;
16988let Constraints = "$Rxx32 = $Rxx32in";
16989}
16990def M2_vrcmpys_acc_s1_h : HInst<
16991(outs DoubleRegs:$Rxx32),
16992(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16993"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
16994tc_7f8ae742, TypeM>, Enc_88c16c {
16995let Inst{7-5} = 0b100;
16996let Inst{13-13} = 0b0;
16997let Inst{31-21} = 0b11101010101;
16998let prefersSlot3 = 1;
16999let Defs = [USR_OVF];
17000let Constraints = "$Rxx32 = $Rxx32in";
17001}
17002def M2_vrcmpys_acc_s1_l : HInst<
17003(outs DoubleRegs:$Rxx32),
17004(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17005"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17006tc_7f8ae742, TypeM>, Enc_88c16c {
17007let Inst{7-5} = 0b100;
17008let Inst{13-13} = 0b0;
17009let Inst{31-21} = 0b11101010111;
17010let prefersSlot3 = 1;
17011let Defs = [USR_OVF];
17012let Constraints = "$Rxx32 = $Rxx32in";
17013}
17014def M2_vrcmpys_s1 : HInst<
17015(outs DoubleRegs:$Rdd32),
17016(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17017"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
17018tc_c21d7447, TypeM> {
17019let isPseudo = 1;
17020}
17021def M2_vrcmpys_s1_h : HInst<
17022(outs DoubleRegs:$Rdd32),
17023(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17024"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
17025tc_c21d7447, TypeM>, Enc_a56825 {
17026let Inst{7-5} = 0b100;
17027let Inst{13-13} = 0b0;
17028let Inst{31-21} = 0b11101000101;
17029let prefersSlot3 = 1;
17030let Defs = [USR_OVF];
17031}
17032def M2_vrcmpys_s1_l : HInst<
17033(outs DoubleRegs:$Rdd32),
17034(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17035"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17036tc_c21d7447, TypeM>, Enc_a56825 {
17037let Inst{7-5} = 0b100;
17038let Inst{13-13} = 0b0;
17039let Inst{31-21} = 0b11101000111;
17040let prefersSlot3 = 1;
17041let Defs = [USR_OVF];
17042}
17043def M2_vrcmpys_s1rp : HInst<
17044(outs IntRegs:$Rd32),
17045(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17046"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
17047tc_c21d7447, TypeM> {
17048let hasNewValue = 1;
17049let opNewValue = 0;
17050let isPseudo = 1;
17051}
17052def M2_vrcmpys_s1rp_h : HInst<
17053(outs IntRegs:$Rd32),
17054(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17055"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
17056tc_c21d7447, TypeM>, Enc_d2216a {
17057let Inst{7-5} = 0b110;
17058let Inst{13-13} = 0b0;
17059let Inst{31-21} = 0b11101001101;
17060let hasNewValue = 1;
17061let opNewValue = 0;
17062let prefersSlot3 = 1;
17063let Defs = [USR_OVF];
17064}
17065def M2_vrcmpys_s1rp_l : HInst<
17066(outs IntRegs:$Rd32),
17067(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17068"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
17069tc_c21d7447, TypeM>, Enc_d2216a {
17070let Inst{7-5} = 0b111;
17071let Inst{13-13} = 0b0;
17072let Inst{31-21} = 0b11101001101;
17073let hasNewValue = 1;
17074let opNewValue = 0;
17075let prefersSlot3 = 1;
17076let Defs = [USR_OVF];
17077}
17078def M2_vrmac_s0 : HInst<
17079(outs DoubleRegs:$Rxx32),
17080(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17081"$Rxx32 += vrmpyh($Rss32,$Rtt32)",
17082tc_7f8ae742, TypeM>, Enc_88c16c {
17083let Inst{7-5} = 0b010;
17084let Inst{13-13} = 0b0;
17085let Inst{31-21} = 0b11101010000;
17086let prefersSlot3 = 1;
17087let Constraints = "$Rxx32 = $Rxx32in";
17088}
17089def M2_vrmpy_s0 : HInst<
17090(outs DoubleRegs:$Rdd32),
17091(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17092"$Rdd32 = vrmpyh($Rss32,$Rtt32)",
17093tc_c21d7447, TypeM>, Enc_a56825 {
17094let Inst{7-5} = 0b010;
17095let Inst{13-13} = 0b0;
17096let Inst{31-21} = 0b11101000000;
17097let prefersSlot3 = 1;
17098}
17099def M2_xor_xacc : HInst<
17100(outs IntRegs:$Rx32),
17101(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17102"$Rx32 ^= xor($Rs32,$Rt32)",
17103tc_a4e22bbd, TypeM>, Enc_2ae154 {
17104let Inst{7-5} = 0b011;
17105let Inst{13-13} = 0b0;
17106let Inst{31-21} = 0b11101111100;
17107let hasNewValue = 1;
17108let opNewValue = 0;
17109let prefersSlot3 = 1;
17110let InputType = "reg";
17111let Constraints = "$Rx32 = $Rx32in";
17112}
17113def M4_and_and : HInst<
17114(outs IntRegs:$Rx32),
17115(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17116"$Rx32 &= and($Rs32,$Rt32)",
17117tc_a4e22bbd, TypeM>, Enc_2ae154 {
17118let Inst{7-5} = 0b000;
17119let Inst{13-13} = 0b0;
17120let Inst{31-21} = 0b11101111010;
17121let hasNewValue = 1;
17122let opNewValue = 0;
17123let prefersSlot3 = 1;
17124let InputType = "reg";
17125let Constraints = "$Rx32 = $Rx32in";
17126}
17127def M4_and_andn : HInst<
17128(outs IntRegs:$Rx32),
17129(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17130"$Rx32 &= and($Rs32,~$Rt32)",
17131tc_a4e22bbd, TypeM>, Enc_2ae154 {
17132let Inst{7-5} = 0b001;
17133let Inst{13-13} = 0b0;
17134let Inst{31-21} = 0b11101111001;
17135let hasNewValue = 1;
17136let opNewValue = 0;
17137let prefersSlot3 = 1;
17138let InputType = "reg";
17139let Constraints = "$Rx32 = $Rx32in";
17140}
17141def M4_and_or : HInst<
17142(outs IntRegs:$Rx32),
17143(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17144"$Rx32 &= or($Rs32,$Rt32)",
17145tc_a4e22bbd, TypeM>, Enc_2ae154 {
17146let Inst{7-5} = 0b001;
17147let Inst{13-13} = 0b0;
17148let Inst{31-21} = 0b11101111010;
17149let hasNewValue = 1;
17150let opNewValue = 0;
17151let prefersSlot3 = 1;
17152let InputType = "reg";
17153let Constraints = "$Rx32 = $Rx32in";
17154}
17155def M4_and_xor : HInst<
17156(outs IntRegs:$Rx32),
17157(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17158"$Rx32 &= xor($Rs32,$Rt32)",
17159tc_a4e22bbd, TypeM>, Enc_2ae154 {
17160let Inst{7-5} = 0b010;
17161let Inst{13-13} = 0b0;
17162let Inst{31-21} = 0b11101111010;
17163let hasNewValue = 1;
17164let opNewValue = 0;
17165let prefersSlot3 = 1;
17166let InputType = "reg";
17167let Constraints = "$Rx32 = $Rx32in";
17168}
17169def M4_cmpyi_wh : HInst<
17170(outs IntRegs:$Rd32),
17171(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17172"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
17173tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17174let Inst{7-5} = 0b100;
17175let Inst{13-13} = 0b0;
17176let Inst{31-21} = 0b11000101000;
17177let hasNewValue = 1;
17178let opNewValue = 0;
17179let prefersSlot3 = 1;
17180let Defs = [USR_OVF];
17181}
17182def M4_cmpyi_whc : HInst<
17183(outs IntRegs:$Rd32),
17184(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17185"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
17186tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17187let Inst{7-5} = 0b101;
17188let Inst{13-13} = 0b0;
17189let Inst{31-21} = 0b11000101000;
17190let hasNewValue = 1;
17191let opNewValue = 0;
17192let prefersSlot3 = 1;
17193let Defs = [USR_OVF];
17194}
17195def M4_cmpyr_wh : HInst<
17196(outs IntRegs:$Rd32),
17197(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17198"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
17199tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17200let Inst{7-5} = 0b110;
17201let Inst{13-13} = 0b0;
17202let Inst{31-21} = 0b11000101000;
17203let hasNewValue = 1;
17204let opNewValue = 0;
17205let prefersSlot3 = 1;
17206let Defs = [USR_OVF];
17207}
17208def M4_cmpyr_whc : HInst<
17209(outs IntRegs:$Rd32),
17210(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17211"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
17212tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17213let Inst{7-5} = 0b111;
17214let Inst{13-13} = 0b0;
17215let Inst{31-21} = 0b11000101000;
17216let hasNewValue = 1;
17217let opNewValue = 0;
17218let prefersSlot3 = 1;
17219let Defs = [USR_OVF];
17220}
17221def M4_mac_up_s1_sat : HInst<
17222(outs IntRegs:$Rx32),
17223(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17224"$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
17225tc_7f8ae742, TypeM>, Enc_2ae154 {
17226let Inst{7-5} = 0b000;
17227let Inst{13-13} = 0b0;
17228let Inst{31-21} = 0b11101111011;
17229let hasNewValue = 1;
17230let opNewValue = 0;
17231let prefersSlot3 = 1;
17232let Defs = [USR_OVF];
17233let InputType = "reg";
17234let Constraints = "$Rx32 = $Rx32in";
17235}
17236def M4_mpyri_addi : HInst<
17237(outs IntRegs:$Rd32),
17238(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
17239"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
17240tc_a154b476, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel {
17241let Inst{31-24} = 0b11011000;
17242let hasNewValue = 1;
17243let opNewValue = 0;
17244let prefersSlot3 = 1;
17245let CextOpcode = "M4_mpyri_addr";
17246let isExtendable = 1;
17247let opExtendable = 1;
17248let isExtentSigned = 0;
17249let opExtentBits = 6;
17250let opExtentAlign = 0;
17251}
17252def M4_mpyri_addr : HInst<
17253(outs IntRegs:$Rd32),
17254(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
17255"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
17256tc_a154b476, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel {
17257let Inst{31-23} = 0b110111111;
17258let hasNewValue = 1;
17259let opNewValue = 0;
17260let prefersSlot3 = 1;
17261let CextOpcode = "M4_mpyri_addr";
17262let InputType = "imm";
17263let isExtendable = 1;
17264let opExtendable = 3;
17265let isExtentSigned = 0;
17266let opExtentBits = 6;
17267let opExtentAlign = 0;
17268}
17269def M4_mpyri_addr_u2 : HInst<
17270(outs IntRegs:$Rd32),
17271(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
17272"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17273tc_503ce0f3, TypeALU64>, Enc_277737, Requires<[UseCompound]> {
17274let Inst{31-23} = 0b110111110;
17275let hasNewValue = 1;
17276let opNewValue = 0;
17277let prefersSlot3 = 1;
17278}
17279def M4_mpyrr_addi : HInst<
17280(outs IntRegs:$Rd32),
17281(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
17282"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17283tc_7f8ae742, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel {
17284let Inst{31-23} = 0b110101110;
17285let hasNewValue = 1;
17286let opNewValue = 0;
17287let prefersSlot3 = 1;
17288let CextOpcode = "M4_mpyrr_addr";
17289let InputType = "imm";
17290let isExtendable = 1;
17291let opExtendable = 1;
17292let isExtentSigned = 0;
17293let opExtentBits = 6;
17294let opExtentAlign = 0;
17295}
17296def M4_mpyrr_addr : HInst<
17297(outs IntRegs:$Ry32),
17298(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
17299"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17300tc_7f8ae742, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel {
17301let Inst{7-5} = 0b000;
17302let Inst{13-13} = 0b0;
17303let Inst{31-21} = 0b11100011000;
17304let hasNewValue = 1;
17305let opNewValue = 0;
17306let prefersSlot3 = 1;
17307let CextOpcode = "M4_mpyrr_addr";
17308let InputType = "reg";
17309let Constraints = "$Ry32 = $Ry32in";
17310}
17311def M4_nac_up_s1_sat : HInst<
17312(outs IntRegs:$Rx32),
17313(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17314"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
17315tc_7f8ae742, TypeM>, Enc_2ae154 {
17316let Inst{7-5} = 0b001;
17317let Inst{13-13} = 0b0;
17318let Inst{31-21} = 0b11101111011;
17319let hasNewValue = 1;
17320let opNewValue = 0;
17321let prefersSlot3 = 1;
17322let Defs = [USR_OVF];
17323let InputType = "reg";
17324let Constraints = "$Rx32 = $Rx32in";
17325}
17326def M4_or_and : HInst<
17327(outs IntRegs:$Rx32),
17328(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17329"$Rx32 |= and($Rs32,$Rt32)",
17330tc_a4e22bbd, TypeM>, Enc_2ae154 {
17331let Inst{7-5} = 0b011;
17332let Inst{13-13} = 0b0;
17333let Inst{31-21} = 0b11101111010;
17334let hasNewValue = 1;
17335let opNewValue = 0;
17336let prefersSlot3 = 1;
17337let InputType = "reg";
17338let Constraints = "$Rx32 = $Rx32in";
17339}
17340def M4_or_andn : HInst<
17341(outs IntRegs:$Rx32),
17342(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17343"$Rx32 |= and($Rs32,~$Rt32)",
17344tc_a4e22bbd, TypeM>, Enc_2ae154 {
17345let Inst{7-5} = 0b000;
17346let Inst{13-13} = 0b0;
17347let Inst{31-21} = 0b11101111001;
17348let hasNewValue = 1;
17349let opNewValue = 0;
17350let prefersSlot3 = 1;
17351let InputType = "reg";
17352let Constraints = "$Rx32 = $Rx32in";
17353}
17354def M4_or_or : HInst<
17355(outs IntRegs:$Rx32),
17356(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17357"$Rx32 |= or($Rs32,$Rt32)",
17358tc_a4e22bbd, TypeM>, Enc_2ae154 {
17359let Inst{7-5} = 0b000;
17360let Inst{13-13} = 0b0;
17361let Inst{31-21} = 0b11101111110;
17362let hasNewValue = 1;
17363let opNewValue = 0;
17364let prefersSlot3 = 1;
17365let InputType = "reg";
17366let Constraints = "$Rx32 = $Rx32in";
17367}
17368def M4_or_xor : HInst<
17369(outs IntRegs:$Rx32),
17370(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17371"$Rx32 |= xor($Rs32,$Rt32)",
17372tc_a4e22bbd, TypeM>, Enc_2ae154 {
17373let Inst{7-5} = 0b001;
17374let Inst{13-13} = 0b0;
17375let Inst{31-21} = 0b11101111110;
17376let hasNewValue = 1;
17377let opNewValue = 0;
17378let prefersSlot3 = 1;
17379let InputType = "reg";
17380let Constraints = "$Rx32 = $Rx32in";
17381}
17382def M4_pmpyw : HInst<
17383(outs DoubleRegs:$Rdd32),
17384(ins IntRegs:$Rs32, IntRegs:$Rt32),
17385"$Rdd32 = pmpyw($Rs32,$Rt32)",
17386tc_c21d7447, TypeM>, Enc_be32a5 {
17387let Inst{7-5} = 0b111;
17388let Inst{13-13} = 0b0;
17389let Inst{31-21} = 0b11100101010;
17390let prefersSlot3 = 1;
17391}
17392def M4_pmpyw_acc : HInst<
17393(outs DoubleRegs:$Rxx32),
17394(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17395"$Rxx32 ^= pmpyw($Rs32,$Rt32)",
17396tc_7f8ae742, TypeM>, Enc_61f0b0 {
17397let Inst{7-5} = 0b111;
17398let Inst{13-13} = 0b0;
17399let Inst{31-21} = 0b11100111001;
17400let prefersSlot3 = 1;
17401let Constraints = "$Rxx32 = $Rxx32in";
17402}
17403def M4_vpmpyh : HInst<
17404(outs DoubleRegs:$Rdd32),
17405(ins IntRegs:$Rs32, IntRegs:$Rt32),
17406"$Rdd32 = vpmpyh($Rs32,$Rt32)",
17407tc_c21d7447, TypeM>, Enc_be32a5 {
17408let Inst{7-5} = 0b111;
17409let Inst{13-13} = 0b0;
17410let Inst{31-21} = 0b11100101110;
17411let prefersSlot3 = 1;
17412}
17413def M4_vpmpyh_acc : HInst<
17414(outs DoubleRegs:$Rxx32),
17415(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17416"$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
17417tc_7f8ae742, TypeM>, Enc_61f0b0 {
17418let Inst{7-5} = 0b111;
17419let Inst{13-13} = 0b0;
17420let Inst{31-21} = 0b11100111101;
17421let prefersSlot3 = 1;
17422let Constraints = "$Rxx32 = $Rxx32in";
17423}
17424def M4_vrmpyeh_acc_s0 : HInst<
17425(outs DoubleRegs:$Rxx32),
17426(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17427"$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
17428tc_7f8ae742, TypeM>, Enc_88c16c {
17429let Inst{7-5} = 0b110;
17430let Inst{13-13} = 0b0;
17431let Inst{31-21} = 0b11101010001;
17432let prefersSlot3 = 1;
17433let Constraints = "$Rxx32 = $Rxx32in";
17434}
17435def M4_vrmpyeh_acc_s1 : HInst<
17436(outs DoubleRegs:$Rxx32),
17437(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17438"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
17439tc_7f8ae742, TypeM>, Enc_88c16c {
17440let Inst{7-5} = 0b110;
17441let Inst{13-13} = 0b0;
17442let Inst{31-21} = 0b11101010101;
17443let prefersSlot3 = 1;
17444let Constraints = "$Rxx32 = $Rxx32in";
17445}
17446def M4_vrmpyeh_s0 : HInst<
17447(outs DoubleRegs:$Rdd32),
17448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17449"$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
17450tc_c21d7447, TypeM>, Enc_a56825 {
17451let Inst{7-5} = 0b100;
17452let Inst{13-13} = 0b0;
17453let Inst{31-21} = 0b11101000010;
17454let prefersSlot3 = 1;
17455}
17456def M4_vrmpyeh_s1 : HInst<
17457(outs DoubleRegs:$Rdd32),
17458(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17459"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
17460tc_c21d7447, TypeM>, Enc_a56825 {
17461let Inst{7-5} = 0b100;
17462let Inst{13-13} = 0b0;
17463let Inst{31-21} = 0b11101000110;
17464let prefersSlot3 = 1;
17465}
17466def M4_vrmpyoh_acc_s0 : HInst<
17467(outs DoubleRegs:$Rxx32),
17468(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17469"$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
17470tc_7f8ae742, TypeM>, Enc_88c16c {
17471let Inst{7-5} = 0b110;
17472let Inst{13-13} = 0b0;
17473let Inst{31-21} = 0b11101010011;
17474let prefersSlot3 = 1;
17475let Constraints = "$Rxx32 = $Rxx32in";
17476}
17477def M4_vrmpyoh_acc_s1 : HInst<
17478(outs DoubleRegs:$Rxx32),
17479(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17480"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
17481tc_7f8ae742, TypeM>, Enc_88c16c {
17482let Inst{7-5} = 0b110;
17483let Inst{13-13} = 0b0;
17484let Inst{31-21} = 0b11101010111;
17485let prefersSlot3 = 1;
17486let Constraints = "$Rxx32 = $Rxx32in";
17487}
17488def M4_vrmpyoh_s0 : HInst<
17489(outs DoubleRegs:$Rdd32),
17490(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17491"$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
17492tc_c21d7447, TypeM>, Enc_a56825 {
17493let Inst{7-5} = 0b010;
17494let Inst{13-13} = 0b0;
17495let Inst{31-21} = 0b11101000001;
17496let prefersSlot3 = 1;
17497}
17498def M4_vrmpyoh_s1 : HInst<
17499(outs DoubleRegs:$Rdd32),
17500(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17501"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
17502tc_c21d7447, TypeM>, Enc_a56825 {
17503let Inst{7-5} = 0b010;
17504let Inst{13-13} = 0b0;
17505let Inst{31-21} = 0b11101000101;
17506let prefersSlot3 = 1;
17507}
17508def M4_xor_and : HInst<
17509(outs IntRegs:$Rx32),
17510(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17511"$Rx32 ^= and($Rs32,$Rt32)",
17512tc_a4e22bbd, TypeM>, Enc_2ae154 {
17513let Inst{7-5} = 0b010;
17514let Inst{13-13} = 0b0;
17515let Inst{31-21} = 0b11101111110;
17516let hasNewValue = 1;
17517let opNewValue = 0;
17518let prefersSlot3 = 1;
17519let InputType = "reg";
17520let Constraints = "$Rx32 = $Rx32in";
17521}
17522def M4_xor_andn : HInst<
17523(outs IntRegs:$Rx32),
17524(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17525"$Rx32 ^= and($Rs32,~$Rt32)",
17526tc_a4e22bbd, TypeM>, Enc_2ae154 {
17527let Inst{7-5} = 0b010;
17528let Inst{13-13} = 0b0;
17529let Inst{31-21} = 0b11101111001;
17530let hasNewValue = 1;
17531let opNewValue = 0;
17532let prefersSlot3 = 1;
17533let InputType = "reg";
17534let Constraints = "$Rx32 = $Rx32in";
17535}
17536def M4_xor_or : HInst<
17537(outs IntRegs:$Rx32),
17538(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17539"$Rx32 ^= or($Rs32,$Rt32)",
17540tc_a4e22bbd, TypeM>, Enc_2ae154 {
17541let Inst{7-5} = 0b011;
17542let Inst{13-13} = 0b0;
17543let Inst{31-21} = 0b11101111110;
17544let hasNewValue = 1;
17545let opNewValue = 0;
17546let prefersSlot3 = 1;
17547let InputType = "reg";
17548let Constraints = "$Rx32 = $Rx32in";
17549}
17550def M4_xor_xacc : HInst<
17551(outs DoubleRegs:$Rxx32),
17552(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17553"$Rxx32 ^= xor($Rss32,$Rtt32)",
17554tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
17555let Inst{7-5} = 0b000;
17556let Inst{13-13} = 0b0;
17557let Inst{31-21} = 0b11001010100;
17558let prefersSlot3 = 1;
17559let Constraints = "$Rxx32 = $Rxx32in";
17560}
17561def M5_vdmacbsu : HInst<
17562(outs DoubleRegs:$Rxx32),
17563(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17564"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
17565tc_7f8ae742, TypeM>, Enc_88c16c {
17566let Inst{7-5} = 0b001;
17567let Inst{13-13} = 0b0;
17568let Inst{31-21} = 0b11101010001;
17569let prefersSlot3 = 1;
17570let Defs = [USR_OVF];
17571let Constraints = "$Rxx32 = $Rxx32in";
17572}
17573def M5_vdmpybsu : HInst<
17574(outs DoubleRegs:$Rdd32),
17575(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17576"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
17577tc_c21d7447, TypeM>, Enc_a56825 {
17578let Inst{7-5} = 0b001;
17579let Inst{13-13} = 0b0;
17580let Inst{31-21} = 0b11101000101;
17581let prefersSlot3 = 1;
17582let Defs = [USR_OVF];
17583}
17584def M5_vmacbsu : HInst<
17585(outs DoubleRegs:$Rxx32),
17586(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17587"$Rxx32 += vmpybsu($Rs32,$Rt32)",
17588tc_7f8ae742, TypeM>, Enc_61f0b0 {
17589let Inst{7-5} = 0b001;
17590let Inst{13-13} = 0b0;
17591let Inst{31-21} = 0b11100111110;
17592let prefersSlot3 = 1;
17593let Constraints = "$Rxx32 = $Rxx32in";
17594}
17595def M5_vmacbuu : HInst<
17596(outs DoubleRegs:$Rxx32),
17597(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17598"$Rxx32 += vmpybu($Rs32,$Rt32)",
17599tc_7f8ae742, TypeM>, Enc_61f0b0 {
17600let Inst{7-5} = 0b001;
17601let Inst{13-13} = 0b0;
17602let Inst{31-21} = 0b11100111100;
17603let prefersSlot3 = 1;
17604let Constraints = "$Rxx32 = $Rxx32in";
17605}
17606def M5_vmpybsu : HInst<
17607(outs DoubleRegs:$Rdd32),
17608(ins IntRegs:$Rs32, IntRegs:$Rt32),
17609"$Rdd32 = vmpybsu($Rs32,$Rt32)",
17610tc_c21d7447, TypeM>, Enc_be32a5 {
17611let Inst{7-5} = 0b001;
17612let Inst{13-13} = 0b0;
17613let Inst{31-21} = 0b11100101010;
17614let prefersSlot3 = 1;
17615}
17616def M5_vmpybuu : HInst<
17617(outs DoubleRegs:$Rdd32),
17618(ins IntRegs:$Rs32, IntRegs:$Rt32),
17619"$Rdd32 = vmpybu($Rs32,$Rt32)",
17620tc_c21d7447, TypeM>, Enc_be32a5 {
17621let Inst{7-5} = 0b001;
17622let Inst{13-13} = 0b0;
17623let Inst{31-21} = 0b11100101100;
17624let prefersSlot3 = 1;
17625}
17626def M5_vrmacbsu : HInst<
17627(outs DoubleRegs:$Rxx32),
17628(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17629"$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
17630tc_7f8ae742, TypeM>, Enc_88c16c {
17631let Inst{7-5} = 0b001;
17632let Inst{13-13} = 0b0;
17633let Inst{31-21} = 0b11101010110;
17634let prefersSlot3 = 1;
17635let Constraints = "$Rxx32 = $Rxx32in";
17636}
17637def M5_vrmacbuu : HInst<
17638(outs DoubleRegs:$Rxx32),
17639(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17640"$Rxx32 += vrmpybu($Rss32,$Rtt32)",
17641tc_7f8ae742, TypeM>, Enc_88c16c {
17642let Inst{7-5} = 0b001;
17643let Inst{13-13} = 0b0;
17644let Inst{31-21} = 0b11101010100;
17645let prefersSlot3 = 1;
17646let Constraints = "$Rxx32 = $Rxx32in";
17647}
17648def M5_vrmpybsu : HInst<
17649(outs DoubleRegs:$Rdd32),
17650(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17651"$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
17652tc_c21d7447, TypeM>, Enc_a56825 {
17653let Inst{7-5} = 0b001;
17654let Inst{13-13} = 0b0;
17655let Inst{31-21} = 0b11101000110;
17656let prefersSlot3 = 1;
17657}
17658def M5_vrmpybuu : HInst<
17659(outs DoubleRegs:$Rdd32),
17660(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17661"$Rdd32 = vrmpybu($Rss32,$Rtt32)",
17662tc_c21d7447, TypeM>, Enc_a56825 {
17663let Inst{7-5} = 0b001;
17664let Inst{13-13} = 0b0;
17665let Inst{31-21} = 0b11101000100;
17666let prefersSlot3 = 1;
17667}
17668def M6_vabsdiffb : HInst<
17669(outs DoubleRegs:$Rdd32),
17670(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17671"$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
17672tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17673let Inst{7-5} = 0b000;
17674let Inst{13-13} = 0b0;
17675let Inst{31-21} = 0b11101000111;
17676let prefersSlot3 = 1;
17677}
17678def M6_vabsdiffub : HInst<
17679(outs DoubleRegs:$Rdd32),
17680(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17681"$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
17682tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17683let Inst{7-5} = 0b000;
17684let Inst{13-13} = 0b0;
17685let Inst{31-21} = 0b11101000101;
17686let prefersSlot3 = 1;
17687}
17688def M7_dcmpyiw : HInst<
17689(outs DoubleRegs:$Rdd32),
17690(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17691"$Rdd32 = cmpyiw($Rss32,$Rtt32)",
17692tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17693let Inst{7-5} = 0b010;
17694let Inst{13-13} = 0b0;
17695let Inst{31-21} = 0b11101000011;
17696let prefersSlot3 = 1;
17697}
17698def M7_dcmpyiw_acc : HInst<
17699(outs DoubleRegs:$Rxx32),
17700(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17701"$Rxx32 += cmpyiw($Rss32,$Rtt32)",
17702tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17703let Inst{7-5} = 0b010;
17704let Inst{13-13} = 0b0;
17705let Inst{31-21} = 0b11101010011;
17706let prefersSlot3 = 1;
17707let Constraints = "$Rxx32 = $Rxx32in";
17708}
17709def M7_dcmpyiwc : HInst<
17710(outs DoubleRegs:$Rdd32),
17711(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17712"$Rdd32 = cmpyiw($Rss32,$Rtt32*)",
17713tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17714let Inst{7-5} = 0b010;
17715let Inst{13-13} = 0b0;
17716let Inst{31-21} = 0b11101000111;
17717let prefersSlot3 = 1;
17718}
17719def M7_dcmpyiwc_acc : HInst<
17720(outs DoubleRegs:$Rxx32),
17721(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17722"$Rxx32 += cmpyiw($Rss32,$Rtt32*)",
17723tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17724let Inst{7-5} = 0b110;
17725let Inst{13-13} = 0b0;
17726let Inst{31-21} = 0b11101010010;
17727let prefersSlot3 = 1;
17728let Constraints = "$Rxx32 = $Rxx32in";
17729}
17730def M7_dcmpyrw : HInst<
17731(outs DoubleRegs:$Rdd32),
17732(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17733"$Rdd32 = cmpyrw($Rss32,$Rtt32)",
17734tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17735let Inst{7-5} = 0b010;
17736let Inst{13-13} = 0b0;
17737let Inst{31-21} = 0b11101000100;
17738let prefersSlot3 = 1;
17739}
17740def M7_dcmpyrw_acc : HInst<
17741(outs DoubleRegs:$Rxx32),
17742(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17743"$Rxx32 += cmpyrw($Rss32,$Rtt32)",
17744tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17745let Inst{7-5} = 0b010;
17746let Inst{13-13} = 0b0;
17747let Inst{31-21} = 0b11101010100;
17748let prefersSlot3 = 1;
17749let Constraints = "$Rxx32 = $Rxx32in";
17750}
17751def M7_dcmpyrwc : HInst<
17752(outs DoubleRegs:$Rdd32),
17753(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17754"$Rdd32 = cmpyrw($Rss32,$Rtt32*)",
17755tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17756let Inst{7-5} = 0b010;
17757let Inst{13-13} = 0b0;
17758let Inst{31-21} = 0b11101000110;
17759let prefersSlot3 = 1;
17760}
17761def M7_dcmpyrwc_acc : HInst<
17762(outs DoubleRegs:$Rxx32),
17763(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17764"$Rxx32 += cmpyrw($Rss32,$Rtt32*)",
17765tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17766let Inst{7-5} = 0b010;
17767let Inst{13-13} = 0b0;
17768let Inst{31-21} = 0b11101010110;
17769let prefersSlot3 = 1;
17770let Constraints = "$Rxx32 = $Rxx32in";
17771}
17772def M7_vdmpy : HInst<
17773(outs DoubleRegs:$Rdd32),
17774(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17775"$Rdd32 = vdmpyw($Rss32,$Rtt32)",
17776tc_5a4b5e58, TypeM>, Requires<[HasV67]> {
17777let isPseudo = 1;
17778let isCodeGenOnly = 1;
17779}
17780def M7_vdmpy_acc : HInst<
17781(outs DoubleRegs:$Rxx32),
17782(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17783"$Rxx32 += vdmpyw($Rss32,$Rtt32)",
17784tc_197dce51, TypeM>, Requires<[HasV67]> {
17785let isPseudo = 1;
17786let isCodeGenOnly = 1;
17787let Constraints = "$Rxx32 = $Rxx32in";
17788}
17789def M7_wcmpyiw : HInst<
17790(outs IntRegs:$Rd32),
17791(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17792"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:sat",
17793tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17794let Inst{7-5} = 0b000;
17795let Inst{13-13} = 0b0;
17796let Inst{31-21} = 0b11101001001;
17797let hasNewValue = 1;
17798let opNewValue = 0;
17799let prefersSlot3 = 1;
17800let Defs = [USR_OVF];
17801}
17802def M7_wcmpyiw_rnd : HInst<
17803(outs IntRegs:$Rd32),
17804(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17805"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:rnd:sat",
17806tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17807let Inst{7-5} = 0b000;
17808let Inst{13-13} = 0b0;
17809let Inst{31-21} = 0b11101001101;
17810let hasNewValue = 1;
17811let opNewValue = 0;
17812let prefersSlot3 = 1;
17813let Defs = [USR_OVF];
17814}
17815def M7_wcmpyiwc : HInst<
17816(outs IntRegs:$Rd32),
17817(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17818"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:sat",
17819tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17820let Inst{7-5} = 0b100;
17821let Inst{13-13} = 0b0;
17822let Inst{31-21} = 0b11101001000;
17823let hasNewValue = 1;
17824let opNewValue = 0;
17825let prefersSlot3 = 1;
17826let Defs = [USR_OVF];
17827}
17828def M7_wcmpyiwc_rnd : HInst<
17829(outs IntRegs:$Rd32),
17830(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17831"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:rnd:sat",
17832tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17833let Inst{7-5} = 0b100;
17834let Inst{13-13} = 0b0;
17835let Inst{31-21} = 0b11101001100;
17836let hasNewValue = 1;
17837let opNewValue = 0;
17838let prefersSlot3 = 1;
17839let Defs = [USR_OVF];
17840}
17841def M7_wcmpyrw : HInst<
17842(outs IntRegs:$Rd32),
17843(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17844"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:sat",
17845tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17846let Inst{7-5} = 0b000;
17847let Inst{13-13} = 0b0;
17848let Inst{31-21} = 0b11101001010;
17849let hasNewValue = 1;
17850let opNewValue = 0;
17851let prefersSlot3 = 1;
17852let Defs = [USR_OVF];
17853}
17854def M7_wcmpyrw_rnd : HInst<
17855(outs IntRegs:$Rd32),
17856(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17857"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:rnd:sat",
17858tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17859let Inst{7-5} = 0b000;
17860let Inst{13-13} = 0b0;
17861let Inst{31-21} = 0b11101001110;
17862let hasNewValue = 1;
17863let opNewValue = 0;
17864let prefersSlot3 = 1;
17865let Defs = [USR_OVF];
17866}
17867def M7_wcmpyrwc : HInst<
17868(outs IntRegs:$Rd32),
17869(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17870"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:sat",
17871tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17872let Inst{7-5} = 0b000;
17873let Inst{13-13} = 0b0;
17874let Inst{31-21} = 0b11101001011;
17875let hasNewValue = 1;
17876let opNewValue = 0;
17877let prefersSlot3 = 1;
17878let Defs = [USR_OVF];
17879}
17880def M7_wcmpyrwc_rnd : HInst<
17881(outs IntRegs:$Rd32),
17882(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17883"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:rnd:sat",
17884tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17885let Inst{7-5} = 0b000;
17886let Inst{13-13} = 0b0;
17887let Inst{31-21} = 0b11101001111;
17888let hasNewValue = 1;
17889let opNewValue = 0;
17890let prefersSlot3 = 1;
17891let Defs = [USR_OVF];
17892}
17893def PS_loadrbabs : HInst<
17894(outs IntRegs:$Rd32),
17895(ins u32_0Imm:$Ii),
17896"$Rd32 = memb(#$Ii)",
17897tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17898let Inst{24-21} = 0b1000;
17899let Inst{31-27} = 0b01001;
17900let hasNewValue = 1;
17901let opNewValue = 0;
17902let addrMode = Absolute;
17903let accessSize = ByteAccess;
17904let mayLoad = 1;
17905let isExtended = 1;
17906let BaseOpcode = "L4_loadrb_abs";
17907let CextOpcode = "L2_loadrb";
17908let isPredicable = 1;
17909let DecoderNamespace = "MustExtend";
17910let isExtended = 1;
17911let opExtendable = 1;
17912let isExtentSigned = 0;
17913let opExtentBits = 16;
17914let opExtentAlign = 0;
17915}
17916def PS_loadrdabs : HInst<
17917(outs DoubleRegs:$Rdd32),
17918(ins u29_3Imm:$Ii),
17919"$Rdd32 = memd(#$Ii)",
17920tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
17921let Inst{24-21} = 0b1110;
17922let Inst{31-27} = 0b01001;
17923let addrMode = Absolute;
17924let accessSize = DoubleWordAccess;
17925let mayLoad = 1;
17926let isExtended = 1;
17927let BaseOpcode = "L4_loadrd_abs";
17928let CextOpcode = "L2_loadrd";
17929let isPredicable = 1;
17930let DecoderNamespace = "MustExtend";
17931let isExtended = 1;
17932let opExtendable = 1;
17933let isExtentSigned = 0;
17934let opExtentBits = 19;
17935let opExtentAlign = 3;
17936}
17937def PS_loadrhabs : HInst<
17938(outs IntRegs:$Rd32),
17939(ins u31_1Imm:$Ii),
17940"$Rd32 = memh(#$Ii)",
17941tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17942let Inst{24-21} = 0b1010;
17943let Inst{31-27} = 0b01001;
17944let hasNewValue = 1;
17945let opNewValue = 0;
17946let addrMode = Absolute;
17947let accessSize = HalfWordAccess;
17948let mayLoad = 1;
17949let isExtended = 1;
17950let BaseOpcode = "L4_loadrh_abs";
17951let CextOpcode = "L2_loadrh";
17952let isPredicable = 1;
17953let DecoderNamespace = "MustExtend";
17954let isExtended = 1;
17955let opExtendable = 1;
17956let isExtentSigned = 0;
17957let opExtentBits = 17;
17958let opExtentAlign = 1;
17959}
17960def PS_loadriabs : HInst<
17961(outs IntRegs:$Rd32),
17962(ins u30_2Imm:$Ii),
17963"$Rd32 = memw(#$Ii)",
17964tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
17965let Inst{24-21} = 0b1100;
17966let Inst{31-27} = 0b01001;
17967let hasNewValue = 1;
17968let opNewValue = 0;
17969let addrMode = Absolute;
17970let accessSize = WordAccess;
17971let mayLoad = 1;
17972let isExtended = 1;
17973let BaseOpcode = "L4_loadri_abs";
17974let CextOpcode = "L2_loadri";
17975let isPredicable = 1;
17976let DecoderNamespace = "MustExtend";
17977let isExtended = 1;
17978let opExtendable = 1;
17979let isExtentSigned = 0;
17980let opExtentBits = 18;
17981let opExtentAlign = 2;
17982}
17983def PS_loadrubabs : HInst<
17984(outs IntRegs:$Rd32),
17985(ins u32_0Imm:$Ii),
17986"$Rd32 = memub(#$Ii)",
17987tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17988let Inst{24-21} = 0b1001;
17989let Inst{31-27} = 0b01001;
17990let hasNewValue = 1;
17991let opNewValue = 0;
17992let addrMode = Absolute;
17993let accessSize = ByteAccess;
17994let mayLoad = 1;
17995let isExtended = 1;
17996let BaseOpcode = "L4_loadrub_abs";
17997let CextOpcode = "L2_loadrub";
17998let isPredicable = 1;
17999let DecoderNamespace = "MustExtend";
18000let isExtended = 1;
18001let opExtendable = 1;
18002let isExtentSigned = 0;
18003let opExtentBits = 16;
18004let opExtentAlign = 0;
18005}
18006def PS_loadruhabs : HInst<
18007(outs IntRegs:$Rd32),
18008(ins u31_1Imm:$Ii),
18009"$Rd32 = memuh(#$Ii)",
18010tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
18011let Inst{24-21} = 0b1011;
18012let Inst{31-27} = 0b01001;
18013let hasNewValue = 1;
18014let opNewValue = 0;
18015let addrMode = Absolute;
18016let accessSize = HalfWordAccess;
18017let mayLoad = 1;
18018let isExtended = 1;
18019let BaseOpcode = "L4_loadruh_abs";
18020let CextOpcode = "L2_loadruh";
18021let isPredicable = 1;
18022let DecoderNamespace = "MustExtend";
18023let isExtended = 1;
18024let opExtendable = 1;
18025let isExtentSigned = 0;
18026let opExtentBits = 17;
18027let opExtentAlign = 1;
18028}
18029def PS_storerbabs : HInst<
18030(outs),
18031(ins u32_0Imm:$Ii, IntRegs:$Rt32),
18032"memb(#$Ii) = $Rt32",
18033tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
18034let Inst{24-21} = 0b0000;
18035let Inst{31-27} = 0b01001;
18036let addrMode = Absolute;
18037let accessSize = ByteAccess;
18038let isExtended = 1;
18039let mayStore = 1;
18040let BaseOpcode = "S2_storerbabs";
18041let CextOpcode = "S2_storerb";
18042let isNVStorable = 1;
18043let isPredicable = 1;
18044let DecoderNamespace = "MustExtend";
18045let isExtended = 1;
18046let opExtendable = 0;
18047let isExtentSigned = 0;
18048let opExtentBits = 16;
18049let opExtentAlign = 0;
18050}
18051def PS_storerbnewabs : HInst<
18052(outs),
18053(ins u32_0Imm:$Ii, IntRegs:$Nt8),
18054"memb(#$Ii) = $Nt8.new",
18055tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
18056let Inst{12-11} = 0b00;
18057let Inst{24-21} = 0b0101;
18058let Inst{31-27} = 0b01001;
18059let addrMode = Absolute;
18060let accessSize = ByteAccess;
18061let isNVStore = 1;
18062let isNewValue = 1;
18063let isExtended = 1;
18064let isRestrictNoSlot1Store = 1;
18065let mayStore = 1;
18066let BaseOpcode = "S2_storerbabs";
18067let CextOpcode = "S2_storerb";
18068let isPredicable = 1;
18069let DecoderNamespace = "MustExtend";
18070let isExtended = 1;
18071let opExtendable = 0;
18072let isExtentSigned = 0;
18073let opExtentBits = 16;
18074let opExtentAlign = 0;
18075let opNewValue = 1;
18076}
18077def PS_storerdabs : HInst<
18078(outs),
18079(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
18080"memd(#$Ii) = $Rtt32",
18081tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
18082let Inst{24-21} = 0b0110;
18083let Inst{31-27} = 0b01001;
18084let addrMode = Absolute;
18085let accessSize = DoubleWordAccess;
18086let isExtended = 1;
18087let mayStore = 1;
18088let BaseOpcode = "S2_storerdabs";
18089let CextOpcode = "S2_storerd";
18090let isPredicable = 1;
18091let DecoderNamespace = "MustExtend";
18092let isExtended = 1;
18093let opExtendable = 0;
18094let isExtentSigned = 0;
18095let opExtentBits = 19;
18096let opExtentAlign = 3;
18097}
18098def PS_storerfabs : HInst<
18099(outs),
18100(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18101"memh(#$Ii) = $Rt32.h",
18102tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18103let Inst{24-21} = 0b0011;
18104let Inst{31-27} = 0b01001;
18105let addrMode = Absolute;
18106let accessSize = HalfWordAccess;
18107let isExtended = 1;
18108let mayStore = 1;
18109let BaseOpcode = "S2_storerfabs";
18110let CextOpcode = "S2_storerf";
18111let isPredicable = 1;
18112let DecoderNamespace = "MustExtend";
18113let isExtended = 1;
18114let opExtendable = 0;
18115let isExtentSigned = 0;
18116let opExtentBits = 17;
18117let opExtentAlign = 1;
18118}
18119def PS_storerhabs : HInst<
18120(outs),
18121(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18122"memh(#$Ii) = $Rt32",
18123tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18124let Inst{24-21} = 0b0010;
18125let Inst{31-27} = 0b01001;
18126let addrMode = Absolute;
18127let accessSize = HalfWordAccess;
18128let isExtended = 1;
18129let mayStore = 1;
18130let BaseOpcode = "S2_storerhabs";
18131let CextOpcode = "S2_storerh";
18132let isNVStorable = 1;
18133let isPredicable = 1;
18134let DecoderNamespace = "MustExtend";
18135let isExtended = 1;
18136let opExtendable = 0;
18137let isExtentSigned = 0;
18138let opExtentBits = 17;
18139let opExtentAlign = 1;
18140}
18141def PS_storerhnewabs : HInst<
18142(outs),
18143(ins u31_1Imm:$Ii, IntRegs:$Nt8),
18144"memh(#$Ii) = $Nt8.new",
18145tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
18146let Inst{12-11} = 0b01;
18147let Inst{24-21} = 0b0101;
18148let Inst{31-27} = 0b01001;
18149let addrMode = Absolute;
18150let accessSize = HalfWordAccess;
18151let isNVStore = 1;
18152let isNewValue = 1;
18153let isExtended = 1;
18154let isRestrictNoSlot1Store = 1;
18155let mayStore = 1;
18156let BaseOpcode = "S2_storerhabs";
18157let CextOpcode = "S2_storerh";
18158let isPredicable = 1;
18159let DecoderNamespace = "MustExtend";
18160let isExtended = 1;
18161let opExtendable = 0;
18162let isExtentSigned = 0;
18163let opExtentBits = 17;
18164let opExtentAlign = 1;
18165let opNewValue = 1;
18166}
18167def PS_storeriabs : HInst<
18168(outs),
18169(ins u30_2Imm:$Ii, IntRegs:$Rt32),
18170"memw(#$Ii) = $Rt32",
18171tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
18172let Inst{24-21} = 0b0100;
18173let Inst{31-27} = 0b01001;
18174let addrMode = Absolute;
18175let accessSize = WordAccess;
18176let isExtended = 1;
18177let mayStore = 1;
18178let BaseOpcode = "S2_storeriabs";
18179let CextOpcode = "S2_storeri";
18180let isNVStorable = 1;
18181let isPredicable = 1;
18182let DecoderNamespace = "MustExtend";
18183let isExtended = 1;
18184let opExtendable = 0;
18185let isExtentSigned = 0;
18186let opExtentBits = 18;
18187let opExtentAlign = 2;
18188}
18189def PS_storerinewabs : HInst<
18190(outs),
18191(ins u30_2Imm:$Ii, IntRegs:$Nt8),
18192"memw(#$Ii) = $Nt8.new",
18193tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
18194let Inst{12-11} = 0b10;
18195let Inst{24-21} = 0b0101;
18196let Inst{31-27} = 0b01001;
18197let addrMode = Absolute;
18198let accessSize = WordAccess;
18199let isNVStore = 1;
18200let isNewValue = 1;
18201let isExtended = 1;
18202let isRestrictNoSlot1Store = 1;
18203let mayStore = 1;
18204let BaseOpcode = "S2_storeriabs";
18205let CextOpcode = "S2_storeri";
18206let isPredicable = 1;
18207let DecoderNamespace = "MustExtend";
18208let isExtended = 1;
18209let opExtendable = 0;
18210let isExtentSigned = 0;
18211let opExtentBits = 18;
18212let opExtentAlign = 2;
18213let opNewValue = 1;
18214}
18215def R6_release_at_vi : HInst<
18216(outs),
18217(ins IntRegs:$Rs32),
18218"release($Rs32):at",
18219tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18220let Inst{7-2} = 0b000011;
18221let Inst{13-13} = 0b0;
18222let Inst{31-21} = 0b10100000111;
18223let isSolo = 1;
18224let mayStore = 1;
18225}
18226def R6_release_st_vi : HInst<
18227(outs),
18228(ins IntRegs:$Rs32),
18229"release($Rs32):st",
18230tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18231let Inst{7-2} = 0b001011;
18232let Inst{13-13} = 0b0;
18233let Inst{31-21} = 0b10100000111;
18234let isSolo = 1;
18235let mayStore = 1;
18236}
18237def S2_addasl_rrri : HInst<
18238(outs IntRegs:$Rd32),
18239(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
18240"$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
18241tc_2c13e7f5, TypeS_3op>, Enc_47ef61 {
18242let Inst{13-13} = 0b0;
18243let Inst{31-21} = 0b11000100000;
18244let hasNewValue = 1;
18245let opNewValue = 0;
18246let prefersSlot3 = 1;
18247}
18248def S2_allocframe : HInst<
18249(outs IntRegs:$Rx32),
18250(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
18251"allocframe($Rx32,#$Ii):raw",
18252tc_934753bb, TypeST>, Enc_22c845 {
18253let Inst{13-11} = 0b000;
18254let Inst{31-21} = 0b10100000100;
18255let hasNewValue = 1;
18256let opNewValue = 0;
18257let addrMode = BaseImmOffset;
18258let accessSize = DoubleWordAccess;
18259let mayStore = 1;
18260let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
18261let Defs = [R30];
18262let Constraints = "$Rx32 = $Rx32in";
18263}
18264def S2_asl_i_p : HInst<
18265(outs DoubleRegs:$Rdd32),
18266(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18267"$Rdd32 = asl($Rss32,#$Ii)",
18268tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18269let Inst{7-5} = 0b010;
18270let Inst{31-21} = 0b10000000000;
18271}
18272def S2_asl_i_p_acc : HInst<
18273(outs DoubleRegs:$Rxx32),
18274(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18275"$Rxx32 += asl($Rss32,#$Ii)",
18276tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18277let Inst{7-5} = 0b110;
18278let Inst{31-21} = 0b10000010000;
18279let prefersSlot3 = 1;
18280let Constraints = "$Rxx32 = $Rxx32in";
18281}
18282def S2_asl_i_p_and : HInst<
18283(outs DoubleRegs:$Rxx32),
18284(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18285"$Rxx32 &= asl($Rss32,#$Ii)",
18286tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18287let Inst{7-5} = 0b010;
18288let Inst{31-21} = 0b10000010010;
18289let prefersSlot3 = 1;
18290let Constraints = "$Rxx32 = $Rxx32in";
18291}
18292def S2_asl_i_p_nac : HInst<
18293(outs DoubleRegs:$Rxx32),
18294(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18295"$Rxx32 -= asl($Rss32,#$Ii)",
18296tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18297let Inst{7-5} = 0b010;
18298let Inst{31-21} = 0b10000010000;
18299let prefersSlot3 = 1;
18300let Constraints = "$Rxx32 = $Rxx32in";
18301}
18302def S2_asl_i_p_or : HInst<
18303(outs DoubleRegs:$Rxx32),
18304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18305"$Rxx32 |= asl($Rss32,#$Ii)",
18306tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18307let Inst{7-5} = 0b110;
18308let Inst{31-21} = 0b10000010010;
18309let prefersSlot3 = 1;
18310let Constraints = "$Rxx32 = $Rxx32in";
18311}
18312def S2_asl_i_p_xacc : HInst<
18313(outs DoubleRegs:$Rxx32),
18314(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18315"$Rxx32 ^= asl($Rss32,#$Ii)",
18316tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18317let Inst{7-5} = 0b010;
18318let Inst{31-21} = 0b10000010100;
18319let prefersSlot3 = 1;
18320let Constraints = "$Rxx32 = $Rxx32in";
18321}
18322def S2_asl_i_r : HInst<
18323(outs IntRegs:$Rd32),
18324(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18325"$Rd32 = asl($Rs32,#$Ii)",
18326tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18327let Inst{7-5} = 0b010;
18328let Inst{13-13} = 0b0;
18329let Inst{31-21} = 0b10001100000;
18330let hasNewValue = 1;
18331let opNewValue = 0;
18332}
18333def S2_asl_i_r_acc : HInst<
18334(outs IntRegs:$Rx32),
18335(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18336"$Rx32 += asl($Rs32,#$Ii)",
18337tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18338let Inst{7-5} = 0b110;
18339let Inst{13-13} = 0b0;
18340let Inst{31-21} = 0b10001110000;
18341let hasNewValue = 1;
18342let opNewValue = 0;
18343let prefersSlot3 = 1;
18344let Constraints = "$Rx32 = $Rx32in";
18345}
18346def S2_asl_i_r_and : HInst<
18347(outs IntRegs:$Rx32),
18348(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18349"$Rx32 &= asl($Rs32,#$Ii)",
18350tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18351let Inst{7-5} = 0b010;
18352let Inst{13-13} = 0b0;
18353let Inst{31-21} = 0b10001110010;
18354let hasNewValue = 1;
18355let opNewValue = 0;
18356let prefersSlot3 = 1;
18357let Constraints = "$Rx32 = $Rx32in";
18358}
18359def S2_asl_i_r_nac : HInst<
18360(outs IntRegs:$Rx32),
18361(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18362"$Rx32 -= asl($Rs32,#$Ii)",
18363tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18364let Inst{7-5} = 0b010;
18365let Inst{13-13} = 0b0;
18366let Inst{31-21} = 0b10001110000;
18367let hasNewValue = 1;
18368let opNewValue = 0;
18369let prefersSlot3 = 1;
18370let Constraints = "$Rx32 = $Rx32in";
18371}
18372def S2_asl_i_r_or : HInst<
18373(outs IntRegs:$Rx32),
18374(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18375"$Rx32 |= asl($Rs32,#$Ii)",
18376tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18377let Inst{7-5} = 0b110;
18378let Inst{13-13} = 0b0;
18379let Inst{31-21} = 0b10001110010;
18380let hasNewValue = 1;
18381let opNewValue = 0;
18382let prefersSlot3 = 1;
18383let Constraints = "$Rx32 = $Rx32in";
18384}
18385def S2_asl_i_r_sat : HInst<
18386(outs IntRegs:$Rd32),
18387(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18388"$Rd32 = asl($Rs32,#$Ii):sat",
18389tc_8a825db2, TypeS_2op>, Enc_a05677 {
18390let Inst{7-5} = 0b010;
18391let Inst{13-13} = 0b0;
18392let Inst{31-21} = 0b10001100010;
18393let hasNewValue = 1;
18394let opNewValue = 0;
18395let prefersSlot3 = 1;
18396let Defs = [USR_OVF];
18397}
18398def S2_asl_i_r_xacc : HInst<
18399(outs IntRegs:$Rx32),
18400(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18401"$Rx32 ^= asl($Rs32,#$Ii)",
18402tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18403let Inst{7-5} = 0b010;
18404let Inst{13-13} = 0b0;
18405let Inst{31-21} = 0b10001110100;
18406let hasNewValue = 1;
18407let opNewValue = 0;
18408let prefersSlot3 = 1;
18409let Constraints = "$Rx32 = $Rx32in";
18410}
18411def S2_asl_i_vh : HInst<
18412(outs DoubleRegs:$Rdd32),
18413(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18414"$Rdd32 = vaslh($Rss32,#$Ii)",
18415tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18416let Inst{7-5} = 0b010;
18417let Inst{13-12} = 0b00;
18418let Inst{31-21} = 0b10000000100;
18419}
18420def S2_asl_i_vw : HInst<
18421(outs DoubleRegs:$Rdd32),
18422(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18423"$Rdd32 = vaslw($Rss32,#$Ii)",
18424tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18425let Inst{7-5} = 0b010;
18426let Inst{13-13} = 0b0;
18427let Inst{31-21} = 0b10000000010;
18428}
18429def S2_asl_r_p : HInst<
18430(outs DoubleRegs:$Rdd32),
18431(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18432"$Rdd32 = asl($Rss32,$Rt32)",
18433tc_5da50c4b, TypeS_3op>, Enc_927852 {
18434let Inst{7-5} = 0b100;
18435let Inst{13-13} = 0b0;
18436let Inst{31-21} = 0b11000011100;
18437}
18438def S2_asl_r_p_acc : HInst<
18439(outs DoubleRegs:$Rxx32),
18440(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18441"$Rxx32 += asl($Rss32,$Rt32)",
18442tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18443let Inst{7-5} = 0b100;
18444let Inst{13-13} = 0b0;
18445let Inst{31-21} = 0b11001011110;
18446let prefersSlot3 = 1;
18447let Constraints = "$Rxx32 = $Rxx32in";
18448}
18449def S2_asl_r_p_and : HInst<
18450(outs DoubleRegs:$Rxx32),
18451(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18452"$Rxx32 &= asl($Rss32,$Rt32)",
18453tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18454let Inst{7-5} = 0b100;
18455let Inst{13-13} = 0b0;
18456let Inst{31-21} = 0b11001011010;
18457let prefersSlot3 = 1;
18458let Constraints = "$Rxx32 = $Rxx32in";
18459}
18460def S2_asl_r_p_nac : HInst<
18461(outs DoubleRegs:$Rxx32),
18462(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18463"$Rxx32 -= asl($Rss32,$Rt32)",
18464tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18465let Inst{7-5} = 0b100;
18466let Inst{13-13} = 0b0;
18467let Inst{31-21} = 0b11001011100;
18468let prefersSlot3 = 1;
18469let Constraints = "$Rxx32 = $Rxx32in";
18470}
18471def S2_asl_r_p_or : HInst<
18472(outs DoubleRegs:$Rxx32),
18473(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18474"$Rxx32 |= asl($Rss32,$Rt32)",
18475tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18476let Inst{7-5} = 0b100;
18477let Inst{13-13} = 0b0;
18478let Inst{31-21} = 0b11001011000;
18479let prefersSlot3 = 1;
18480let Constraints = "$Rxx32 = $Rxx32in";
18481}
18482def S2_asl_r_p_xor : HInst<
18483(outs DoubleRegs:$Rxx32),
18484(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18485"$Rxx32 ^= asl($Rss32,$Rt32)",
18486tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18487let Inst{7-5} = 0b100;
18488let Inst{13-13} = 0b0;
18489let Inst{31-21} = 0b11001011011;
18490let prefersSlot3 = 1;
18491let Constraints = "$Rxx32 = $Rxx32in";
18492}
18493def S2_asl_r_r : HInst<
18494(outs IntRegs:$Rd32),
18495(ins IntRegs:$Rs32, IntRegs:$Rt32),
18496"$Rd32 = asl($Rs32,$Rt32)",
18497tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18498let Inst{7-5} = 0b100;
18499let Inst{13-13} = 0b0;
18500let Inst{31-21} = 0b11000110010;
18501let hasNewValue = 1;
18502let opNewValue = 0;
18503}
18504def S2_asl_r_r_acc : HInst<
18505(outs IntRegs:$Rx32),
18506(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18507"$Rx32 += asl($Rs32,$Rt32)",
18508tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18509let Inst{7-5} = 0b100;
18510let Inst{13-13} = 0b0;
18511let Inst{31-21} = 0b11001100110;
18512let hasNewValue = 1;
18513let opNewValue = 0;
18514let prefersSlot3 = 1;
18515let Constraints = "$Rx32 = $Rx32in";
18516}
18517def S2_asl_r_r_and : HInst<
18518(outs IntRegs:$Rx32),
18519(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18520"$Rx32 &= asl($Rs32,$Rt32)",
18521tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18522let Inst{7-5} = 0b100;
18523let Inst{13-13} = 0b0;
18524let Inst{31-21} = 0b11001100010;
18525let hasNewValue = 1;
18526let opNewValue = 0;
18527let prefersSlot3 = 1;
18528let Constraints = "$Rx32 = $Rx32in";
18529}
18530def S2_asl_r_r_nac : HInst<
18531(outs IntRegs:$Rx32),
18532(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18533"$Rx32 -= asl($Rs32,$Rt32)",
18534tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18535let Inst{7-5} = 0b100;
18536let Inst{13-13} = 0b0;
18537let Inst{31-21} = 0b11001100100;
18538let hasNewValue = 1;
18539let opNewValue = 0;
18540let prefersSlot3 = 1;
18541let Constraints = "$Rx32 = $Rx32in";
18542}
18543def S2_asl_r_r_or : HInst<
18544(outs IntRegs:$Rx32),
18545(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18546"$Rx32 |= asl($Rs32,$Rt32)",
18547tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18548let Inst{7-5} = 0b100;
18549let Inst{13-13} = 0b0;
18550let Inst{31-21} = 0b11001100000;
18551let hasNewValue = 1;
18552let opNewValue = 0;
18553let prefersSlot3 = 1;
18554let Constraints = "$Rx32 = $Rx32in";
18555}
18556def S2_asl_r_r_sat : HInst<
18557(outs IntRegs:$Rd32),
18558(ins IntRegs:$Rs32, IntRegs:$Rt32),
18559"$Rd32 = asl($Rs32,$Rt32):sat",
18560tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18561let Inst{7-5} = 0b100;
18562let Inst{13-13} = 0b0;
18563let Inst{31-21} = 0b11000110000;
18564let hasNewValue = 1;
18565let opNewValue = 0;
18566let prefersSlot3 = 1;
18567let Defs = [USR_OVF];
18568}
18569def S2_asl_r_vh : HInst<
18570(outs DoubleRegs:$Rdd32),
18571(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18572"$Rdd32 = vaslh($Rss32,$Rt32)",
18573tc_5da50c4b, TypeS_3op>, Enc_927852 {
18574let Inst{7-5} = 0b100;
18575let Inst{13-13} = 0b0;
18576let Inst{31-21} = 0b11000011010;
18577}
18578def S2_asl_r_vw : HInst<
18579(outs DoubleRegs:$Rdd32),
18580(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18581"$Rdd32 = vaslw($Rss32,$Rt32)",
18582tc_5da50c4b, TypeS_3op>, Enc_927852 {
18583let Inst{7-5} = 0b100;
18584let Inst{13-13} = 0b0;
18585let Inst{31-21} = 0b11000011000;
18586}
18587def S2_asr_i_p : HInst<
18588(outs DoubleRegs:$Rdd32),
18589(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18590"$Rdd32 = asr($Rss32,#$Ii)",
18591tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18592let Inst{7-5} = 0b000;
18593let Inst{31-21} = 0b10000000000;
18594}
18595def S2_asr_i_p_acc : HInst<
18596(outs DoubleRegs:$Rxx32),
18597(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18598"$Rxx32 += asr($Rss32,#$Ii)",
18599tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18600let Inst{7-5} = 0b100;
18601let Inst{31-21} = 0b10000010000;
18602let prefersSlot3 = 1;
18603let Constraints = "$Rxx32 = $Rxx32in";
18604}
18605def S2_asr_i_p_and : HInst<
18606(outs DoubleRegs:$Rxx32),
18607(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18608"$Rxx32 &= asr($Rss32,#$Ii)",
18609tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18610let Inst{7-5} = 0b000;
18611let Inst{31-21} = 0b10000010010;
18612let prefersSlot3 = 1;
18613let Constraints = "$Rxx32 = $Rxx32in";
18614}
18615def S2_asr_i_p_nac : HInst<
18616(outs DoubleRegs:$Rxx32),
18617(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18618"$Rxx32 -= asr($Rss32,#$Ii)",
18619tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18620let Inst{7-5} = 0b000;
18621let Inst{31-21} = 0b10000010000;
18622let prefersSlot3 = 1;
18623let Constraints = "$Rxx32 = $Rxx32in";
18624}
18625def S2_asr_i_p_or : HInst<
18626(outs DoubleRegs:$Rxx32),
18627(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18628"$Rxx32 |= asr($Rss32,#$Ii)",
18629tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18630let Inst{7-5} = 0b100;
18631let Inst{31-21} = 0b10000010010;
18632let prefersSlot3 = 1;
18633let Constraints = "$Rxx32 = $Rxx32in";
18634}
18635def S2_asr_i_p_rnd : HInst<
18636(outs DoubleRegs:$Rdd32),
18637(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18638"$Rdd32 = asr($Rss32,#$Ii):rnd",
18639tc_0dfac0a7, TypeS_2op>, Enc_5eac98 {
18640let Inst{7-5} = 0b111;
18641let Inst{31-21} = 0b10000000110;
18642let prefersSlot3 = 1;
18643}
18644def S2_asr_i_p_rnd_goodsyntax : HInst<
18645(outs DoubleRegs:$Rdd32),
18646(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18647"$Rdd32 = asrrnd($Rss32,#$Ii)",
18648tc_0dfac0a7, TypeS_2op> {
18649let isPseudo = 1;
18650}
18651def S2_asr_i_r : HInst<
18652(outs IntRegs:$Rd32),
18653(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18654"$Rd32 = asr($Rs32,#$Ii)",
18655tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18656let Inst{7-5} = 0b000;
18657let Inst{13-13} = 0b0;
18658let Inst{31-21} = 0b10001100000;
18659let hasNewValue = 1;
18660let opNewValue = 0;
18661}
18662def S2_asr_i_r_acc : HInst<
18663(outs IntRegs:$Rx32),
18664(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18665"$Rx32 += asr($Rs32,#$Ii)",
18666tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18667let Inst{7-5} = 0b100;
18668let Inst{13-13} = 0b0;
18669let Inst{31-21} = 0b10001110000;
18670let hasNewValue = 1;
18671let opNewValue = 0;
18672let prefersSlot3 = 1;
18673let Constraints = "$Rx32 = $Rx32in";
18674}
18675def S2_asr_i_r_and : HInst<
18676(outs IntRegs:$Rx32),
18677(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18678"$Rx32 &= asr($Rs32,#$Ii)",
18679tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18680let Inst{7-5} = 0b000;
18681let Inst{13-13} = 0b0;
18682let Inst{31-21} = 0b10001110010;
18683let hasNewValue = 1;
18684let opNewValue = 0;
18685let prefersSlot3 = 1;
18686let Constraints = "$Rx32 = $Rx32in";
18687}
18688def S2_asr_i_r_nac : HInst<
18689(outs IntRegs:$Rx32),
18690(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18691"$Rx32 -= asr($Rs32,#$Ii)",
18692tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18693let Inst{7-5} = 0b000;
18694let Inst{13-13} = 0b0;
18695let Inst{31-21} = 0b10001110000;
18696let hasNewValue = 1;
18697let opNewValue = 0;
18698let prefersSlot3 = 1;
18699let Constraints = "$Rx32 = $Rx32in";
18700}
18701def S2_asr_i_r_or : HInst<
18702(outs IntRegs:$Rx32),
18703(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18704"$Rx32 |= asr($Rs32,#$Ii)",
18705tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18706let Inst{7-5} = 0b100;
18707let Inst{13-13} = 0b0;
18708let Inst{31-21} = 0b10001110010;
18709let hasNewValue = 1;
18710let opNewValue = 0;
18711let prefersSlot3 = 1;
18712let Constraints = "$Rx32 = $Rx32in";
18713}
18714def S2_asr_i_r_rnd : HInst<
18715(outs IntRegs:$Rd32),
18716(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18717"$Rd32 = asr($Rs32,#$Ii):rnd",
18718tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
18719let Inst{7-5} = 0b000;
18720let Inst{13-13} = 0b0;
18721let Inst{31-21} = 0b10001100010;
18722let hasNewValue = 1;
18723let opNewValue = 0;
18724let prefersSlot3 = 1;
18725}
18726def S2_asr_i_r_rnd_goodsyntax : HInst<
18727(outs IntRegs:$Rd32),
18728(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18729"$Rd32 = asrrnd($Rs32,#$Ii)",
18730tc_0dfac0a7, TypeS_2op> {
18731let hasNewValue = 1;
18732let opNewValue = 0;
18733let isPseudo = 1;
18734}
18735def S2_asr_i_svw_trun : HInst<
18736(outs IntRegs:$Rd32),
18737(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18738"$Rd32 = vasrw($Rss32,#$Ii)",
18739tc_f34c1c21, TypeS_2op>, Enc_8dec2e {
18740let Inst{7-5} = 0b010;
18741let Inst{13-13} = 0b0;
18742let Inst{31-21} = 0b10001000110;
18743let hasNewValue = 1;
18744let opNewValue = 0;
18745let prefersSlot3 = 1;
18746}
18747def S2_asr_i_vh : HInst<
18748(outs DoubleRegs:$Rdd32),
18749(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18750"$Rdd32 = vasrh($Rss32,#$Ii)",
18751tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18752let Inst{7-5} = 0b000;
18753let Inst{13-12} = 0b00;
18754let Inst{31-21} = 0b10000000100;
18755}
18756def S2_asr_i_vw : HInst<
18757(outs DoubleRegs:$Rdd32),
18758(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18759"$Rdd32 = vasrw($Rss32,#$Ii)",
18760tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18761let Inst{7-5} = 0b000;
18762let Inst{13-13} = 0b0;
18763let Inst{31-21} = 0b10000000010;
18764}
18765def S2_asr_r_p : HInst<
18766(outs DoubleRegs:$Rdd32),
18767(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18768"$Rdd32 = asr($Rss32,$Rt32)",
18769tc_5da50c4b, TypeS_3op>, Enc_927852 {
18770let Inst{7-5} = 0b000;
18771let Inst{13-13} = 0b0;
18772let Inst{31-21} = 0b11000011100;
18773}
18774def S2_asr_r_p_acc : HInst<
18775(outs DoubleRegs:$Rxx32),
18776(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18777"$Rxx32 += asr($Rss32,$Rt32)",
18778tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18779let Inst{7-5} = 0b000;
18780let Inst{13-13} = 0b0;
18781let Inst{31-21} = 0b11001011110;
18782let prefersSlot3 = 1;
18783let Constraints = "$Rxx32 = $Rxx32in";
18784}
18785def S2_asr_r_p_and : HInst<
18786(outs DoubleRegs:$Rxx32),
18787(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18788"$Rxx32 &= asr($Rss32,$Rt32)",
18789tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18790let Inst{7-5} = 0b000;
18791let Inst{13-13} = 0b0;
18792let Inst{31-21} = 0b11001011010;
18793let prefersSlot3 = 1;
18794let Constraints = "$Rxx32 = $Rxx32in";
18795}
18796def S2_asr_r_p_nac : HInst<
18797(outs DoubleRegs:$Rxx32),
18798(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18799"$Rxx32 -= asr($Rss32,$Rt32)",
18800tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18801let Inst{7-5} = 0b000;
18802let Inst{13-13} = 0b0;
18803let Inst{31-21} = 0b11001011100;
18804let prefersSlot3 = 1;
18805let Constraints = "$Rxx32 = $Rxx32in";
18806}
18807def S2_asr_r_p_or : HInst<
18808(outs DoubleRegs:$Rxx32),
18809(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18810"$Rxx32 |= asr($Rss32,$Rt32)",
18811tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18812let Inst{7-5} = 0b000;
18813let Inst{13-13} = 0b0;
18814let Inst{31-21} = 0b11001011000;
18815let prefersSlot3 = 1;
18816let Constraints = "$Rxx32 = $Rxx32in";
18817}
18818def S2_asr_r_p_xor : HInst<
18819(outs DoubleRegs:$Rxx32),
18820(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18821"$Rxx32 ^= asr($Rss32,$Rt32)",
18822tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18823let Inst{7-5} = 0b000;
18824let Inst{13-13} = 0b0;
18825let Inst{31-21} = 0b11001011011;
18826let prefersSlot3 = 1;
18827let Constraints = "$Rxx32 = $Rxx32in";
18828}
18829def S2_asr_r_r : HInst<
18830(outs IntRegs:$Rd32),
18831(ins IntRegs:$Rs32, IntRegs:$Rt32),
18832"$Rd32 = asr($Rs32,$Rt32)",
18833tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18834let Inst{7-5} = 0b000;
18835let Inst{13-13} = 0b0;
18836let Inst{31-21} = 0b11000110010;
18837let hasNewValue = 1;
18838let opNewValue = 0;
18839}
18840def S2_asr_r_r_acc : HInst<
18841(outs IntRegs:$Rx32),
18842(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18843"$Rx32 += asr($Rs32,$Rt32)",
18844tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18845let Inst{7-5} = 0b000;
18846let Inst{13-13} = 0b0;
18847let Inst{31-21} = 0b11001100110;
18848let hasNewValue = 1;
18849let opNewValue = 0;
18850let prefersSlot3 = 1;
18851let Constraints = "$Rx32 = $Rx32in";
18852}
18853def S2_asr_r_r_and : HInst<
18854(outs IntRegs:$Rx32),
18855(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18856"$Rx32 &= asr($Rs32,$Rt32)",
18857tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18858let Inst{7-5} = 0b000;
18859let Inst{13-13} = 0b0;
18860let Inst{31-21} = 0b11001100010;
18861let hasNewValue = 1;
18862let opNewValue = 0;
18863let prefersSlot3 = 1;
18864let Constraints = "$Rx32 = $Rx32in";
18865}
18866def S2_asr_r_r_nac : HInst<
18867(outs IntRegs:$Rx32),
18868(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18869"$Rx32 -= asr($Rs32,$Rt32)",
18870tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18871let Inst{7-5} = 0b000;
18872let Inst{13-13} = 0b0;
18873let Inst{31-21} = 0b11001100100;
18874let hasNewValue = 1;
18875let opNewValue = 0;
18876let prefersSlot3 = 1;
18877let Constraints = "$Rx32 = $Rx32in";
18878}
18879def S2_asr_r_r_or : HInst<
18880(outs IntRegs:$Rx32),
18881(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18882"$Rx32 |= asr($Rs32,$Rt32)",
18883tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18884let Inst{7-5} = 0b000;
18885let Inst{13-13} = 0b0;
18886let Inst{31-21} = 0b11001100000;
18887let hasNewValue = 1;
18888let opNewValue = 0;
18889let prefersSlot3 = 1;
18890let Constraints = "$Rx32 = $Rx32in";
18891}
18892def S2_asr_r_r_sat : HInst<
18893(outs IntRegs:$Rd32),
18894(ins IntRegs:$Rs32, IntRegs:$Rt32),
18895"$Rd32 = asr($Rs32,$Rt32):sat",
18896tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18897let Inst{7-5} = 0b000;
18898let Inst{13-13} = 0b0;
18899let Inst{31-21} = 0b11000110000;
18900let hasNewValue = 1;
18901let opNewValue = 0;
18902let prefersSlot3 = 1;
18903let Defs = [USR_OVF];
18904}
18905def S2_asr_r_svw_trun : HInst<
18906(outs IntRegs:$Rd32),
18907(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18908"$Rd32 = vasrw($Rss32,$Rt32)",
18909tc_f34c1c21, TypeS_3op>, Enc_3d5b28 {
18910let Inst{7-5} = 0b010;
18911let Inst{13-13} = 0b0;
18912let Inst{31-21} = 0b11000101000;
18913let hasNewValue = 1;
18914let opNewValue = 0;
18915let prefersSlot3 = 1;
18916}
18917def S2_asr_r_vh : HInst<
18918(outs DoubleRegs:$Rdd32),
18919(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18920"$Rdd32 = vasrh($Rss32,$Rt32)",
18921tc_5da50c4b, TypeS_3op>, Enc_927852 {
18922let Inst{7-5} = 0b000;
18923let Inst{13-13} = 0b0;
18924let Inst{31-21} = 0b11000011010;
18925}
18926def S2_asr_r_vw : HInst<
18927(outs DoubleRegs:$Rdd32),
18928(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18929"$Rdd32 = vasrw($Rss32,$Rt32)",
18930tc_5da50c4b, TypeS_3op>, Enc_927852 {
18931let Inst{7-5} = 0b000;
18932let Inst{13-13} = 0b0;
18933let Inst{31-21} = 0b11000011000;
18934}
18935def S2_brev : HInst<
18936(outs IntRegs:$Rd32),
18937(ins IntRegs:$Rs32),
18938"$Rd32 = brev($Rs32)",
18939tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18940let Inst{13-5} = 0b000000110;
18941let Inst{31-21} = 0b10001100010;
18942let hasNewValue = 1;
18943let opNewValue = 0;
18944let prefersSlot3 = 1;
18945}
18946def S2_brevp : HInst<
18947(outs DoubleRegs:$Rdd32),
18948(ins DoubleRegs:$Rss32),
18949"$Rdd32 = brev($Rss32)",
18950tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
18951let Inst{13-5} = 0b000000110;
18952let Inst{31-21} = 0b10000000110;
18953let prefersSlot3 = 1;
18954}
18955def S2_cabacdecbin : HInst<
18956(outs DoubleRegs:$Rdd32),
18957(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18958"$Rdd32 = decbin($Rss32,$Rtt32)",
18959tc_db596beb, TypeS_3op>, Enc_a56825, Requires<[UseCabac]> {
18960let Inst{7-5} = 0b110;
18961let Inst{13-13} = 0b0;
18962let Inst{31-21} = 0b11000001110;
18963let isPredicateLate = 1;
18964let prefersSlot3 = 1;
18965let Defs = [P0];
18966}
18967def S2_cl0 : HInst<
18968(outs IntRegs:$Rd32),
18969(ins IntRegs:$Rs32),
18970"$Rd32 = cl0($Rs32)",
18971tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18972let Inst{13-5} = 0b000000101;
18973let Inst{31-21} = 0b10001100000;
18974let hasNewValue = 1;
18975let opNewValue = 0;
18976let prefersSlot3 = 1;
18977}
18978def S2_cl0p : HInst<
18979(outs IntRegs:$Rd32),
18980(ins DoubleRegs:$Rss32),
18981"$Rd32 = cl0($Rss32)",
18982tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
18983let Inst{13-5} = 0b000000010;
18984let Inst{31-21} = 0b10001000010;
18985let hasNewValue = 1;
18986let opNewValue = 0;
18987let prefersSlot3 = 1;
18988}
18989def S2_cl1 : HInst<
18990(outs IntRegs:$Rd32),
18991(ins IntRegs:$Rs32),
18992"$Rd32 = cl1($Rs32)",
18993tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18994let Inst{13-5} = 0b000000110;
18995let Inst{31-21} = 0b10001100000;
18996let hasNewValue = 1;
18997let opNewValue = 0;
18998let prefersSlot3 = 1;
18999}
19000def S2_cl1p : HInst<
19001(outs IntRegs:$Rd32),
19002(ins DoubleRegs:$Rss32),
19003"$Rd32 = cl1($Rss32)",
19004tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19005let Inst{13-5} = 0b000000100;
19006let Inst{31-21} = 0b10001000010;
19007let hasNewValue = 1;
19008let opNewValue = 0;
19009let prefersSlot3 = 1;
19010}
19011def S2_clb : HInst<
19012(outs IntRegs:$Rd32),
19013(ins IntRegs:$Rs32),
19014"$Rd32 = clb($Rs32)",
19015tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19016let Inst{13-5} = 0b000000100;
19017let Inst{31-21} = 0b10001100000;
19018let hasNewValue = 1;
19019let opNewValue = 0;
19020let prefersSlot3 = 1;
19021}
19022def S2_clbnorm : HInst<
19023(outs IntRegs:$Rd32),
19024(ins IntRegs:$Rs32),
19025"$Rd32 = normamt($Rs32)",
19026tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19027let Inst{13-5} = 0b000000111;
19028let Inst{31-21} = 0b10001100000;
19029let hasNewValue = 1;
19030let opNewValue = 0;
19031let prefersSlot3 = 1;
19032}
19033def S2_clbp : HInst<
19034(outs IntRegs:$Rd32),
19035(ins DoubleRegs:$Rss32),
19036"$Rd32 = clb($Rss32)",
19037tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19038let Inst{13-5} = 0b000000000;
19039let Inst{31-21} = 0b10001000010;
19040let hasNewValue = 1;
19041let opNewValue = 0;
19042let prefersSlot3 = 1;
19043}
19044def S2_clrbit_i : HInst<
19045(outs IntRegs:$Rd32),
19046(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19047"$Rd32 = clrbit($Rs32,#$Ii)",
19048tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19049let Inst{7-5} = 0b001;
19050let Inst{13-13} = 0b0;
19051let Inst{31-21} = 0b10001100110;
19052let hasNewValue = 1;
19053let opNewValue = 0;
19054}
19055def S2_clrbit_r : HInst<
19056(outs IntRegs:$Rd32),
19057(ins IntRegs:$Rs32, IntRegs:$Rt32),
19058"$Rd32 = clrbit($Rs32,$Rt32)",
19059tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19060let Inst{7-5} = 0b010;
19061let Inst{13-13} = 0b0;
19062let Inst{31-21} = 0b11000110100;
19063let hasNewValue = 1;
19064let opNewValue = 0;
19065}
19066def S2_ct0 : HInst<
19067(outs IntRegs:$Rd32),
19068(ins IntRegs:$Rs32),
19069"$Rd32 = ct0($Rs32)",
19070tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19071let Inst{13-5} = 0b000000100;
19072let Inst{31-21} = 0b10001100010;
19073let hasNewValue = 1;
19074let opNewValue = 0;
19075let prefersSlot3 = 1;
19076}
19077def S2_ct0p : HInst<
19078(outs IntRegs:$Rd32),
19079(ins DoubleRegs:$Rss32),
19080"$Rd32 = ct0($Rss32)",
19081tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19082let Inst{13-5} = 0b000000010;
19083let Inst{31-21} = 0b10001000111;
19084let hasNewValue = 1;
19085let opNewValue = 0;
19086let prefersSlot3 = 1;
19087}
19088def S2_ct1 : HInst<
19089(outs IntRegs:$Rd32),
19090(ins IntRegs:$Rs32),
19091"$Rd32 = ct1($Rs32)",
19092tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19093let Inst{13-5} = 0b000000101;
19094let Inst{31-21} = 0b10001100010;
19095let hasNewValue = 1;
19096let opNewValue = 0;
19097let prefersSlot3 = 1;
19098}
19099def S2_ct1p : HInst<
19100(outs IntRegs:$Rd32),
19101(ins DoubleRegs:$Rss32),
19102"$Rd32 = ct1($Rss32)",
19103tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19104let Inst{13-5} = 0b000000100;
19105let Inst{31-21} = 0b10001000111;
19106let hasNewValue = 1;
19107let opNewValue = 0;
19108let prefersSlot3 = 1;
19109}
19110def S2_deinterleave : HInst<
19111(outs DoubleRegs:$Rdd32),
19112(ins DoubleRegs:$Rss32),
19113"$Rdd32 = deinterleave($Rss32)",
19114tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19115let Inst{13-5} = 0b000000100;
19116let Inst{31-21} = 0b10000000110;
19117let prefersSlot3 = 1;
19118}
19119def S2_extractu : HInst<
19120(outs IntRegs:$Rd32),
19121(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19122"$Rd32 = extractu($Rs32,#$Ii,#$II)",
19123tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
19124let Inst{13-13} = 0b0;
19125let Inst{31-23} = 0b100011010;
19126let hasNewValue = 1;
19127let opNewValue = 0;
19128let prefersSlot3 = 1;
19129}
19130def S2_extractu_rp : HInst<
19131(outs IntRegs:$Rd32),
19132(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
19133"$Rd32 = extractu($Rs32,$Rtt32)",
19134tc_a08b630b, TypeS_3op>, Enc_e07374 {
19135let Inst{7-5} = 0b000;
19136let Inst{13-13} = 0b0;
19137let Inst{31-21} = 0b11001001000;
19138let hasNewValue = 1;
19139let opNewValue = 0;
19140let prefersSlot3 = 1;
19141}
19142def S2_extractup : HInst<
19143(outs DoubleRegs:$Rdd32),
19144(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19145"$Rdd32 = extractu($Rss32,#$Ii,#$II)",
19146tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
19147let Inst{31-24} = 0b10000001;
19148let prefersSlot3 = 1;
19149}
19150def S2_extractup_rp : HInst<
19151(outs DoubleRegs:$Rdd32),
19152(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19153"$Rdd32 = extractu($Rss32,$Rtt32)",
19154tc_a08b630b, TypeS_3op>, Enc_a56825 {
19155let Inst{7-5} = 0b000;
19156let Inst{13-13} = 0b0;
19157let Inst{31-21} = 0b11000001000;
19158let prefersSlot3 = 1;
19159}
19160def S2_insert : HInst<
19161(outs IntRegs:$Rx32),
19162(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19163"$Rx32 = insert($Rs32,#$Ii,#$II)",
19164tc_bb831a7c, TypeS_2op>, Enc_a1e29d {
19165let Inst{13-13} = 0b0;
19166let Inst{31-23} = 0b100011110;
19167let hasNewValue = 1;
19168let opNewValue = 0;
19169let prefersSlot3 = 1;
19170let Constraints = "$Rx32 = $Rx32in";
19171}
19172def S2_insert_rp : HInst<
19173(outs IntRegs:$Rx32),
19174(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19175"$Rx32 = insert($Rs32,$Rtt32)",
19176tc_a4e22bbd, TypeS_3op>, Enc_179b35 {
19177let Inst{7-5} = 0b000;
19178let Inst{13-13} = 0b0;
19179let Inst{31-21} = 0b11001000000;
19180let hasNewValue = 1;
19181let opNewValue = 0;
19182let prefersSlot3 = 1;
19183let Constraints = "$Rx32 = $Rx32in";
19184}
19185def S2_insertp : HInst<
19186(outs DoubleRegs:$Rxx32),
19187(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19188"$Rxx32 = insert($Rss32,#$Ii,#$II)",
19189tc_bb831a7c, TypeS_2op>, Enc_143a3c {
19190let Inst{31-24} = 0b10000011;
19191let prefersSlot3 = 1;
19192let Constraints = "$Rxx32 = $Rxx32in";
19193}
19194def S2_insertp_rp : HInst<
19195(outs DoubleRegs:$Rxx32),
19196(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19197"$Rxx32 = insert($Rss32,$Rtt32)",
19198tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
19199let Inst{7-5} = 0b000;
19200let Inst{13-13} = 0b0;
19201let Inst{31-21} = 0b11001010000;
19202let prefersSlot3 = 1;
19203let Constraints = "$Rxx32 = $Rxx32in";
19204}
19205def S2_interleave : HInst<
19206(outs DoubleRegs:$Rdd32),
19207(ins DoubleRegs:$Rss32),
19208"$Rdd32 = interleave($Rss32)",
19209tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19210let Inst{13-5} = 0b000000101;
19211let Inst{31-21} = 0b10000000110;
19212let prefersSlot3 = 1;
19213}
19214def S2_lfsp : HInst<
19215(outs DoubleRegs:$Rdd32),
19216(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19217"$Rdd32 = lfs($Rss32,$Rtt32)",
19218tc_a08b630b, TypeS_3op>, Enc_a56825 {
19219let Inst{7-5} = 0b110;
19220let Inst{13-13} = 0b0;
19221let Inst{31-21} = 0b11000001100;
19222let prefersSlot3 = 1;
19223}
19224def S2_lsl_r_p : HInst<
19225(outs DoubleRegs:$Rdd32),
19226(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19227"$Rdd32 = lsl($Rss32,$Rt32)",
19228tc_5da50c4b, TypeS_3op>, Enc_927852 {
19229let Inst{7-5} = 0b110;
19230let Inst{13-13} = 0b0;
19231let Inst{31-21} = 0b11000011100;
19232}
19233def S2_lsl_r_p_acc : HInst<
19234(outs DoubleRegs:$Rxx32),
19235(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19236"$Rxx32 += lsl($Rss32,$Rt32)",
19237tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19238let Inst{7-5} = 0b110;
19239let Inst{13-13} = 0b0;
19240let Inst{31-21} = 0b11001011110;
19241let prefersSlot3 = 1;
19242let Constraints = "$Rxx32 = $Rxx32in";
19243}
19244def S2_lsl_r_p_and : HInst<
19245(outs DoubleRegs:$Rxx32),
19246(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19247"$Rxx32 &= lsl($Rss32,$Rt32)",
19248tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19249let Inst{7-5} = 0b110;
19250let Inst{13-13} = 0b0;
19251let Inst{31-21} = 0b11001011010;
19252let prefersSlot3 = 1;
19253let Constraints = "$Rxx32 = $Rxx32in";
19254}
19255def S2_lsl_r_p_nac : HInst<
19256(outs DoubleRegs:$Rxx32),
19257(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19258"$Rxx32 -= lsl($Rss32,$Rt32)",
19259tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19260let Inst{7-5} = 0b110;
19261let Inst{13-13} = 0b0;
19262let Inst{31-21} = 0b11001011100;
19263let prefersSlot3 = 1;
19264let Constraints = "$Rxx32 = $Rxx32in";
19265}
19266def S2_lsl_r_p_or : HInst<
19267(outs DoubleRegs:$Rxx32),
19268(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19269"$Rxx32 |= lsl($Rss32,$Rt32)",
19270tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19271let Inst{7-5} = 0b110;
19272let Inst{13-13} = 0b0;
19273let Inst{31-21} = 0b11001011000;
19274let prefersSlot3 = 1;
19275let Constraints = "$Rxx32 = $Rxx32in";
19276}
19277def S2_lsl_r_p_xor : HInst<
19278(outs DoubleRegs:$Rxx32),
19279(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19280"$Rxx32 ^= lsl($Rss32,$Rt32)",
19281tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19282let Inst{7-5} = 0b110;
19283let Inst{13-13} = 0b0;
19284let Inst{31-21} = 0b11001011011;
19285let prefersSlot3 = 1;
19286let Constraints = "$Rxx32 = $Rxx32in";
19287}
19288def S2_lsl_r_r : HInst<
19289(outs IntRegs:$Rd32),
19290(ins IntRegs:$Rs32, IntRegs:$Rt32),
19291"$Rd32 = lsl($Rs32,$Rt32)",
19292tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19293let Inst{7-5} = 0b110;
19294let Inst{13-13} = 0b0;
19295let Inst{31-21} = 0b11000110010;
19296let hasNewValue = 1;
19297let opNewValue = 0;
19298}
19299def S2_lsl_r_r_acc : HInst<
19300(outs IntRegs:$Rx32),
19301(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19302"$Rx32 += lsl($Rs32,$Rt32)",
19303tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19304let Inst{7-5} = 0b110;
19305let Inst{13-13} = 0b0;
19306let Inst{31-21} = 0b11001100110;
19307let hasNewValue = 1;
19308let opNewValue = 0;
19309let prefersSlot3 = 1;
19310let Constraints = "$Rx32 = $Rx32in";
19311}
19312def S2_lsl_r_r_and : HInst<
19313(outs IntRegs:$Rx32),
19314(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19315"$Rx32 &= lsl($Rs32,$Rt32)",
19316tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19317let Inst{7-5} = 0b110;
19318let Inst{13-13} = 0b0;
19319let Inst{31-21} = 0b11001100010;
19320let hasNewValue = 1;
19321let opNewValue = 0;
19322let prefersSlot3 = 1;
19323let Constraints = "$Rx32 = $Rx32in";
19324}
19325def S2_lsl_r_r_nac : HInst<
19326(outs IntRegs:$Rx32),
19327(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19328"$Rx32 -= lsl($Rs32,$Rt32)",
19329tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19330let Inst{7-5} = 0b110;
19331let Inst{13-13} = 0b0;
19332let Inst{31-21} = 0b11001100100;
19333let hasNewValue = 1;
19334let opNewValue = 0;
19335let prefersSlot3 = 1;
19336let Constraints = "$Rx32 = $Rx32in";
19337}
19338def S2_lsl_r_r_or : HInst<
19339(outs IntRegs:$Rx32),
19340(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19341"$Rx32 |= lsl($Rs32,$Rt32)",
19342tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19343let Inst{7-5} = 0b110;
19344let Inst{13-13} = 0b0;
19345let Inst{31-21} = 0b11001100000;
19346let hasNewValue = 1;
19347let opNewValue = 0;
19348let prefersSlot3 = 1;
19349let Constraints = "$Rx32 = $Rx32in";
19350}
19351def S2_lsl_r_vh : HInst<
19352(outs DoubleRegs:$Rdd32),
19353(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19354"$Rdd32 = vlslh($Rss32,$Rt32)",
19355tc_5da50c4b, TypeS_3op>, Enc_927852 {
19356let Inst{7-5} = 0b110;
19357let Inst{13-13} = 0b0;
19358let Inst{31-21} = 0b11000011010;
19359}
19360def S2_lsl_r_vw : HInst<
19361(outs DoubleRegs:$Rdd32),
19362(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19363"$Rdd32 = vlslw($Rss32,$Rt32)",
19364tc_5da50c4b, TypeS_3op>, Enc_927852 {
19365let Inst{7-5} = 0b110;
19366let Inst{13-13} = 0b0;
19367let Inst{31-21} = 0b11000011000;
19368}
19369def S2_lsr_i_p : HInst<
19370(outs DoubleRegs:$Rdd32),
19371(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
19372"$Rdd32 = lsr($Rss32,#$Ii)",
19373tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
19374let Inst{7-5} = 0b001;
19375let Inst{31-21} = 0b10000000000;
19376}
19377def S2_lsr_i_p_acc : HInst<
19378(outs DoubleRegs:$Rxx32),
19379(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19380"$Rxx32 += lsr($Rss32,#$Ii)",
19381tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19382let Inst{7-5} = 0b101;
19383let Inst{31-21} = 0b10000010000;
19384let prefersSlot3 = 1;
19385let Constraints = "$Rxx32 = $Rxx32in";
19386}
19387def S2_lsr_i_p_and : HInst<
19388(outs DoubleRegs:$Rxx32),
19389(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19390"$Rxx32 &= lsr($Rss32,#$Ii)",
19391tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19392let Inst{7-5} = 0b001;
19393let Inst{31-21} = 0b10000010010;
19394let prefersSlot3 = 1;
19395let Constraints = "$Rxx32 = $Rxx32in";
19396}
19397def S2_lsr_i_p_nac : HInst<
19398(outs DoubleRegs:$Rxx32),
19399(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19400"$Rxx32 -= lsr($Rss32,#$Ii)",
19401tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19402let Inst{7-5} = 0b001;
19403let Inst{31-21} = 0b10000010000;
19404let prefersSlot3 = 1;
19405let Constraints = "$Rxx32 = $Rxx32in";
19406}
19407def S2_lsr_i_p_or : HInst<
19408(outs DoubleRegs:$Rxx32),
19409(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19410"$Rxx32 |= lsr($Rss32,#$Ii)",
19411tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19412let Inst{7-5} = 0b101;
19413let Inst{31-21} = 0b10000010010;
19414let prefersSlot3 = 1;
19415let Constraints = "$Rxx32 = $Rxx32in";
19416}
19417def S2_lsr_i_p_xacc : HInst<
19418(outs DoubleRegs:$Rxx32),
19419(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19420"$Rxx32 ^= lsr($Rss32,#$Ii)",
19421tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19422let Inst{7-5} = 0b001;
19423let Inst{31-21} = 0b10000010100;
19424let prefersSlot3 = 1;
19425let Constraints = "$Rxx32 = $Rxx32in";
19426}
19427def S2_lsr_i_r : HInst<
19428(outs IntRegs:$Rd32),
19429(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19430"$Rd32 = lsr($Rs32,#$Ii)",
19431tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19432let Inst{7-5} = 0b001;
19433let Inst{13-13} = 0b0;
19434let Inst{31-21} = 0b10001100000;
19435let hasNewValue = 1;
19436let opNewValue = 0;
19437}
19438def S2_lsr_i_r_acc : HInst<
19439(outs IntRegs:$Rx32),
19440(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19441"$Rx32 += lsr($Rs32,#$Ii)",
19442tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19443let Inst{7-5} = 0b101;
19444let Inst{13-13} = 0b0;
19445let Inst{31-21} = 0b10001110000;
19446let hasNewValue = 1;
19447let opNewValue = 0;
19448let prefersSlot3 = 1;
19449let Constraints = "$Rx32 = $Rx32in";
19450}
19451def S2_lsr_i_r_and : HInst<
19452(outs IntRegs:$Rx32),
19453(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19454"$Rx32 &= lsr($Rs32,#$Ii)",
19455tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19456let Inst{7-5} = 0b001;
19457let Inst{13-13} = 0b0;
19458let Inst{31-21} = 0b10001110010;
19459let hasNewValue = 1;
19460let opNewValue = 0;
19461let prefersSlot3 = 1;
19462let Constraints = "$Rx32 = $Rx32in";
19463}
19464def S2_lsr_i_r_nac : HInst<
19465(outs IntRegs:$Rx32),
19466(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19467"$Rx32 -= lsr($Rs32,#$Ii)",
19468tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19469let Inst{7-5} = 0b001;
19470let Inst{13-13} = 0b0;
19471let Inst{31-21} = 0b10001110000;
19472let hasNewValue = 1;
19473let opNewValue = 0;
19474let prefersSlot3 = 1;
19475let Constraints = "$Rx32 = $Rx32in";
19476}
19477def S2_lsr_i_r_or : HInst<
19478(outs IntRegs:$Rx32),
19479(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19480"$Rx32 |= lsr($Rs32,#$Ii)",
19481tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19482let Inst{7-5} = 0b101;
19483let Inst{13-13} = 0b0;
19484let Inst{31-21} = 0b10001110010;
19485let hasNewValue = 1;
19486let opNewValue = 0;
19487let prefersSlot3 = 1;
19488let Constraints = "$Rx32 = $Rx32in";
19489}
19490def S2_lsr_i_r_xacc : HInst<
19491(outs IntRegs:$Rx32),
19492(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19493"$Rx32 ^= lsr($Rs32,#$Ii)",
19494tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19495let Inst{7-5} = 0b001;
19496let Inst{13-13} = 0b0;
19497let Inst{31-21} = 0b10001110100;
19498let hasNewValue = 1;
19499let opNewValue = 0;
19500let prefersSlot3 = 1;
19501let Constraints = "$Rx32 = $Rx32in";
19502}
19503def S2_lsr_i_vh : HInst<
19504(outs DoubleRegs:$Rdd32),
19505(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
19506"$Rdd32 = vlsrh($Rss32,#$Ii)",
19507tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
19508let Inst{7-5} = 0b001;
19509let Inst{13-12} = 0b00;
19510let Inst{31-21} = 0b10000000100;
19511}
19512def S2_lsr_i_vw : HInst<
19513(outs DoubleRegs:$Rdd32),
19514(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
19515"$Rdd32 = vlsrw($Rss32,#$Ii)",
19516tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
19517let Inst{7-5} = 0b001;
19518let Inst{13-13} = 0b0;
19519let Inst{31-21} = 0b10000000010;
19520}
19521def S2_lsr_r_p : HInst<
19522(outs DoubleRegs:$Rdd32),
19523(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19524"$Rdd32 = lsr($Rss32,$Rt32)",
19525tc_5da50c4b, TypeS_3op>, Enc_927852 {
19526let Inst{7-5} = 0b010;
19527let Inst{13-13} = 0b0;
19528let Inst{31-21} = 0b11000011100;
19529}
19530def S2_lsr_r_p_acc : HInst<
19531(outs DoubleRegs:$Rxx32),
19532(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19533"$Rxx32 += lsr($Rss32,$Rt32)",
19534tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19535let Inst{7-5} = 0b010;
19536let Inst{13-13} = 0b0;
19537let Inst{31-21} = 0b11001011110;
19538let prefersSlot3 = 1;
19539let Constraints = "$Rxx32 = $Rxx32in";
19540}
19541def S2_lsr_r_p_and : HInst<
19542(outs DoubleRegs:$Rxx32),
19543(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19544"$Rxx32 &= lsr($Rss32,$Rt32)",
19545tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19546let Inst{7-5} = 0b010;
19547let Inst{13-13} = 0b0;
19548let Inst{31-21} = 0b11001011010;
19549let prefersSlot3 = 1;
19550let Constraints = "$Rxx32 = $Rxx32in";
19551}
19552def S2_lsr_r_p_nac : HInst<
19553(outs DoubleRegs:$Rxx32),
19554(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19555"$Rxx32 -= lsr($Rss32,$Rt32)",
19556tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19557let Inst{7-5} = 0b010;
19558let Inst{13-13} = 0b0;
19559let Inst{31-21} = 0b11001011100;
19560let prefersSlot3 = 1;
19561let Constraints = "$Rxx32 = $Rxx32in";
19562}
19563def S2_lsr_r_p_or : HInst<
19564(outs DoubleRegs:$Rxx32),
19565(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19566"$Rxx32 |= lsr($Rss32,$Rt32)",
19567tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19568let Inst{7-5} = 0b010;
19569let Inst{13-13} = 0b0;
19570let Inst{31-21} = 0b11001011000;
19571let prefersSlot3 = 1;
19572let Constraints = "$Rxx32 = $Rxx32in";
19573}
19574def S2_lsr_r_p_xor : HInst<
19575(outs DoubleRegs:$Rxx32),
19576(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19577"$Rxx32 ^= lsr($Rss32,$Rt32)",
19578tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19579let Inst{7-5} = 0b010;
19580let Inst{13-13} = 0b0;
19581let Inst{31-21} = 0b11001011011;
19582let prefersSlot3 = 1;
19583let Constraints = "$Rxx32 = $Rxx32in";
19584}
19585def S2_lsr_r_r : HInst<
19586(outs IntRegs:$Rd32),
19587(ins IntRegs:$Rs32, IntRegs:$Rt32),
19588"$Rd32 = lsr($Rs32,$Rt32)",
19589tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19590let Inst{7-5} = 0b010;
19591let Inst{13-13} = 0b0;
19592let Inst{31-21} = 0b11000110010;
19593let hasNewValue = 1;
19594let opNewValue = 0;
19595}
19596def S2_lsr_r_r_acc : HInst<
19597(outs IntRegs:$Rx32),
19598(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19599"$Rx32 += lsr($Rs32,$Rt32)",
19600tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19601let Inst{7-5} = 0b010;
19602let Inst{13-13} = 0b0;
19603let Inst{31-21} = 0b11001100110;
19604let hasNewValue = 1;
19605let opNewValue = 0;
19606let prefersSlot3 = 1;
19607let Constraints = "$Rx32 = $Rx32in";
19608}
19609def S2_lsr_r_r_and : HInst<
19610(outs IntRegs:$Rx32),
19611(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19612"$Rx32 &= lsr($Rs32,$Rt32)",
19613tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19614let Inst{7-5} = 0b010;
19615let Inst{13-13} = 0b0;
19616let Inst{31-21} = 0b11001100010;
19617let hasNewValue = 1;
19618let opNewValue = 0;
19619let prefersSlot3 = 1;
19620let Constraints = "$Rx32 = $Rx32in";
19621}
19622def S2_lsr_r_r_nac : HInst<
19623(outs IntRegs:$Rx32),
19624(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19625"$Rx32 -= lsr($Rs32,$Rt32)",
19626tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19627let Inst{7-5} = 0b010;
19628let Inst{13-13} = 0b0;
19629let Inst{31-21} = 0b11001100100;
19630let hasNewValue = 1;
19631let opNewValue = 0;
19632let prefersSlot3 = 1;
19633let Constraints = "$Rx32 = $Rx32in";
19634}
19635def S2_lsr_r_r_or : HInst<
19636(outs IntRegs:$Rx32),
19637(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19638"$Rx32 |= lsr($Rs32,$Rt32)",
19639tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19640let Inst{7-5} = 0b010;
19641let Inst{13-13} = 0b0;
19642let Inst{31-21} = 0b11001100000;
19643let hasNewValue = 1;
19644let opNewValue = 0;
19645let prefersSlot3 = 1;
19646let Constraints = "$Rx32 = $Rx32in";
19647}
19648def S2_lsr_r_vh : HInst<
19649(outs DoubleRegs:$Rdd32),
19650(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19651"$Rdd32 = vlsrh($Rss32,$Rt32)",
19652tc_5da50c4b, TypeS_3op>, Enc_927852 {
19653let Inst{7-5} = 0b010;
19654let Inst{13-13} = 0b0;
19655let Inst{31-21} = 0b11000011010;
19656}
19657def S2_lsr_r_vw : HInst<
19658(outs DoubleRegs:$Rdd32),
19659(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19660"$Rdd32 = vlsrw($Rss32,$Rt32)",
19661tc_5da50c4b, TypeS_3op>, Enc_927852 {
19662let Inst{7-5} = 0b010;
19663let Inst{13-13} = 0b0;
19664let Inst{31-21} = 0b11000011000;
19665}
19666def S2_mask : HInst<
19667(outs IntRegs:$Rd32),
19668(ins u5_0Imm:$Ii, u5_0Imm:$II),
19669"$Rd32 = mask(#$Ii,#$II)",
19670tc_1fcb8495, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> {
19671let Inst{13-13} = 0b1;
19672let Inst{20-16} = 0b00000;
19673let Inst{31-23} = 0b100011010;
19674let hasNewValue = 1;
19675let opNewValue = 0;
19676let prefersSlot3 = 1;
19677}
19678def S2_packhl : HInst<
19679(outs DoubleRegs:$Rdd32),
19680(ins IntRegs:$Rs32, IntRegs:$Rt32),
19681"$Rdd32 = packhl($Rs32,$Rt32)",
19682tc_713b66bf, TypeALU32_3op>, Enc_be32a5 {
19683let Inst{7-5} = 0b000;
19684let Inst{13-13} = 0b0;
19685let Inst{31-21} = 0b11110101100;
19686let InputType = "reg";
19687}
19688def S2_parityp : HInst<
19689(outs IntRegs:$Rd32),
19690(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19691"$Rd32 = parity($Rss32,$Rtt32)",
19692tc_a08b630b, TypeALU64>, Enc_d2216a {
19693let Inst{7-5} = 0b000;
19694let Inst{13-13} = 0b0;
19695let Inst{31-21} = 0b11010000000;
19696let hasNewValue = 1;
19697let opNewValue = 0;
19698let prefersSlot3 = 1;
19699}
19700def S2_pstorerbf_io : HInst<
19701(outs),
19702(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19703"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
19704tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19705let Inst{2-2} = 0b0;
19706let Inst{31-21} = 0b01000100000;
19707let isPredicated = 1;
19708let isPredicatedFalse = 1;
19709let addrMode = BaseImmOffset;
19710let accessSize = ByteAccess;
19711let mayStore = 1;
19712let BaseOpcode = "S2_storerb_io";
19713let CextOpcode = "S2_storerb";
19714let InputType = "imm";
19715let isNVStorable = 1;
19716let isExtendable = 1;
19717let opExtendable = 2;
19718let isExtentSigned = 0;
19719let opExtentBits = 6;
19720let opExtentAlign = 0;
19721}
19722def S2_pstorerbf_pi : HInst<
19723(outs IntRegs:$Rx32),
19724(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19725"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
19726tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19727let Inst{2-2} = 0b1;
19728let Inst{7-7} = 0b0;
19729let Inst{13-13} = 0b1;
19730let Inst{31-21} = 0b10101011000;
19731let isPredicated = 1;
19732let isPredicatedFalse = 1;
19733let addrMode = PostInc;
19734let accessSize = ByteAccess;
19735let mayStore = 1;
19736let BaseOpcode = "S2_storerb_pi";
19737let isNVStorable = 1;
19738let Constraints = "$Rx32 = $Rx32in";
19739}
19740def S2_pstorerbf_zomap : HInst<
19741(outs),
19742(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19743"if (!$Pv4) memb($Rs32) = $Rt32",
19744tc_8035e91f, TypeMAPPING> {
19745let isPseudo = 1;
19746let isCodeGenOnly = 1;
19747}
19748def S2_pstorerbfnew_pi : HInst<
19749(outs IntRegs:$Rx32),
19750(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19751"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19752tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19753let Inst{2-2} = 0b1;
19754let Inst{7-7} = 0b1;
19755let Inst{13-13} = 0b1;
19756let Inst{31-21} = 0b10101011000;
19757let isPredicated = 1;
19758let isPredicatedFalse = 1;
19759let addrMode = PostInc;
19760let accessSize = ByteAccess;
19761let isPredicatedNew = 1;
19762let mayStore = 1;
19763let BaseOpcode = "S2_storerb_pi";
19764let isNVStorable = 1;
19765let Constraints = "$Rx32 = $Rx32in";
19766}
19767def S2_pstorerbnewf_io : HInst<
19768(outs),
19769(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19770"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19771tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19772let Inst{2-2} = 0b0;
19773let Inst{12-11} = 0b00;
19774let Inst{31-21} = 0b01000100101;
19775let isPredicated = 1;
19776let isPredicatedFalse = 1;
19777let addrMode = BaseImmOffset;
19778let accessSize = ByteAccess;
19779let isNVStore = 1;
19780let isNewValue = 1;
19781let isRestrictNoSlot1Store = 1;
19782let mayStore = 1;
19783let BaseOpcode = "S2_storerb_io";
19784let CextOpcode = "S2_storerb";
19785let InputType = "imm";
19786let isExtendable = 1;
19787let opExtendable = 2;
19788let isExtentSigned = 0;
19789let opExtentBits = 6;
19790let opExtentAlign = 0;
19791let opNewValue = 3;
19792}
19793def S2_pstorerbnewf_pi : HInst<
19794(outs IntRegs:$Rx32),
19795(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19796"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19797tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19798let Inst{2-2} = 0b1;
19799let Inst{7-7} = 0b0;
19800let Inst{13-11} = 0b100;
19801let Inst{31-21} = 0b10101011101;
19802let isPredicated = 1;
19803let isPredicatedFalse = 1;
19804let addrMode = PostInc;
19805let accessSize = ByteAccess;
19806let isNVStore = 1;
19807let isNewValue = 1;
19808let isRestrictNoSlot1Store = 1;
19809let mayStore = 1;
19810let BaseOpcode = "S2_storerb_pi";
19811let CextOpcode = "S2_storerb";
19812let opNewValue = 4;
19813let Constraints = "$Rx32 = $Rx32in";
19814}
19815def S2_pstorerbnewf_zomap : HInst<
19816(outs),
19817(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19818"if (!$Pv4) memb($Rs32) = $Nt8.new",
19819tc_011e0e9d, TypeMAPPING> {
19820let isPseudo = 1;
19821let isCodeGenOnly = 1;
19822let opNewValue = 2;
19823}
19824def S2_pstorerbnewfnew_pi : HInst<
19825(outs IntRegs:$Rx32),
19826(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19827"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19828tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19829let Inst{2-2} = 0b1;
19830let Inst{7-7} = 0b1;
19831let Inst{13-11} = 0b100;
19832let Inst{31-21} = 0b10101011101;
19833let isPredicated = 1;
19834let isPredicatedFalse = 1;
19835let addrMode = PostInc;
19836let accessSize = ByteAccess;
19837let isNVStore = 1;
19838let isPredicatedNew = 1;
19839let isNewValue = 1;
19840let isRestrictNoSlot1Store = 1;
19841let mayStore = 1;
19842let BaseOpcode = "S2_storerb_pi";
19843let CextOpcode = "S2_storerb";
19844let opNewValue = 4;
19845let Constraints = "$Rx32 = $Rx32in";
19846}
19847def S2_pstorerbnewt_io : HInst<
19848(outs),
19849(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19850"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19851tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19852let Inst{2-2} = 0b0;
19853let Inst{12-11} = 0b00;
19854let Inst{31-21} = 0b01000000101;
19855let isPredicated = 1;
19856let addrMode = BaseImmOffset;
19857let accessSize = ByteAccess;
19858let isNVStore = 1;
19859let isNewValue = 1;
19860let isRestrictNoSlot1Store = 1;
19861let mayStore = 1;
19862let BaseOpcode = "S2_storerb_io";
19863let CextOpcode = "S2_storerb";
19864let InputType = "imm";
19865let isExtendable = 1;
19866let opExtendable = 2;
19867let isExtentSigned = 0;
19868let opExtentBits = 6;
19869let opExtentAlign = 0;
19870let opNewValue = 3;
19871}
19872def S2_pstorerbnewt_pi : HInst<
19873(outs IntRegs:$Rx32),
19874(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19875"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19876tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19877let Inst{2-2} = 0b0;
19878let Inst{7-7} = 0b0;
19879let Inst{13-11} = 0b100;
19880let Inst{31-21} = 0b10101011101;
19881let isPredicated = 1;
19882let addrMode = PostInc;
19883let accessSize = ByteAccess;
19884let isNVStore = 1;
19885let isNewValue = 1;
19886let isRestrictNoSlot1Store = 1;
19887let mayStore = 1;
19888let BaseOpcode = "S2_storerb_pi";
19889let CextOpcode = "S2_storerb";
19890let opNewValue = 4;
19891let Constraints = "$Rx32 = $Rx32in";
19892}
19893def S2_pstorerbnewt_zomap : HInst<
19894(outs),
19895(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19896"if ($Pv4) memb($Rs32) = $Nt8.new",
19897tc_011e0e9d, TypeMAPPING> {
19898let isPseudo = 1;
19899let isCodeGenOnly = 1;
19900let opNewValue = 2;
19901}
19902def S2_pstorerbnewtnew_pi : HInst<
19903(outs IntRegs:$Rx32),
19904(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19905"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19906tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19907let Inst{2-2} = 0b0;
19908let Inst{7-7} = 0b1;
19909let Inst{13-11} = 0b100;
19910let Inst{31-21} = 0b10101011101;
19911let isPredicated = 1;
19912let addrMode = PostInc;
19913let accessSize = ByteAccess;
19914let isNVStore = 1;
19915let isPredicatedNew = 1;
19916let isNewValue = 1;
19917let isRestrictNoSlot1Store = 1;
19918let mayStore = 1;
19919let BaseOpcode = "S2_storerb_pi";
19920let CextOpcode = "S2_storerb";
19921let opNewValue = 4;
19922let Constraints = "$Rx32 = $Rx32in";
19923}
19924def S2_pstorerbt_io : HInst<
19925(outs),
19926(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19927"if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
19928tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19929let Inst{2-2} = 0b0;
19930let Inst{31-21} = 0b01000000000;
19931let isPredicated = 1;
19932let addrMode = BaseImmOffset;
19933let accessSize = ByteAccess;
19934let mayStore = 1;
19935let BaseOpcode = "S2_storerb_io";
19936let CextOpcode = "S2_storerb";
19937let InputType = "imm";
19938let isNVStorable = 1;
19939let isExtendable = 1;
19940let opExtendable = 2;
19941let isExtentSigned = 0;
19942let opExtentBits = 6;
19943let opExtentAlign = 0;
19944}
19945def S2_pstorerbt_pi : HInst<
19946(outs IntRegs:$Rx32),
19947(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19948"if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
19949tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19950let Inst{2-2} = 0b0;
19951let Inst{7-7} = 0b0;
19952let Inst{13-13} = 0b1;
19953let Inst{31-21} = 0b10101011000;
19954let isPredicated = 1;
19955let addrMode = PostInc;
19956let accessSize = ByteAccess;
19957let mayStore = 1;
19958let BaseOpcode = "S2_storerb_pi";
19959let isNVStorable = 1;
19960let Constraints = "$Rx32 = $Rx32in";
19961}
19962def S2_pstorerbt_zomap : HInst<
19963(outs),
19964(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19965"if ($Pv4) memb($Rs32) = $Rt32",
19966tc_8035e91f, TypeMAPPING> {
19967let isPseudo = 1;
19968let isCodeGenOnly = 1;
19969}
19970def S2_pstorerbtnew_pi : HInst<
19971(outs IntRegs:$Rx32),
19972(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19973"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19974tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19975let Inst{2-2} = 0b0;
19976let Inst{7-7} = 0b1;
19977let Inst{13-13} = 0b1;
19978let Inst{31-21} = 0b10101011000;
19979let isPredicated = 1;
19980let addrMode = PostInc;
19981let accessSize = ByteAccess;
19982let isPredicatedNew = 1;
19983let mayStore = 1;
19984let BaseOpcode = "S2_storerb_pi";
19985let isNVStorable = 1;
19986let Constraints = "$Rx32 = $Rx32in";
19987}
19988def S2_pstorerdf_io : HInst<
19989(outs),
19990(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
19991"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
19992tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
19993let Inst{2-2} = 0b0;
19994let Inst{31-21} = 0b01000100110;
19995let isPredicated = 1;
19996let isPredicatedFalse = 1;
19997let addrMode = BaseImmOffset;
19998let accessSize = DoubleWordAccess;
19999let mayStore = 1;
20000let BaseOpcode = "S2_storerd_io";
20001let CextOpcode = "S2_storerd";
20002let InputType = "imm";
20003let isExtendable = 1;
20004let opExtendable = 2;
20005let isExtentSigned = 0;
20006let opExtentBits = 9;
20007let opExtentAlign = 3;
20008}
20009def S2_pstorerdf_pi : HInst<
20010(outs IntRegs:$Rx32),
20011(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20012"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
20013tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20014let Inst{2-2} = 0b1;
20015let Inst{7-7} = 0b0;
20016let Inst{13-13} = 0b1;
20017let Inst{31-21} = 0b10101011110;
20018let isPredicated = 1;
20019let isPredicatedFalse = 1;
20020let addrMode = PostInc;
20021let accessSize = DoubleWordAccess;
20022let mayStore = 1;
20023let BaseOpcode = "S2_storerd_pi";
20024let CextOpcode = "S2_storerd";
20025let Constraints = "$Rx32 = $Rx32in";
20026}
20027def S2_pstorerdf_zomap : HInst<
20028(outs),
20029(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20030"if (!$Pv4) memd($Rs32) = $Rtt32",
20031tc_8035e91f, TypeMAPPING> {
20032let isPseudo = 1;
20033let isCodeGenOnly = 1;
20034}
20035def S2_pstorerdfnew_pi : HInst<
20036(outs IntRegs:$Rx32),
20037(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20038"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20039tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20040let Inst{2-2} = 0b1;
20041let Inst{7-7} = 0b1;
20042let Inst{13-13} = 0b1;
20043let Inst{31-21} = 0b10101011110;
20044let isPredicated = 1;
20045let isPredicatedFalse = 1;
20046let addrMode = PostInc;
20047let accessSize = DoubleWordAccess;
20048let isPredicatedNew = 1;
20049let mayStore = 1;
20050let BaseOpcode = "S2_storerd_pi";
20051let CextOpcode = "S2_storerd";
20052let Constraints = "$Rx32 = $Rx32in";
20053}
20054def S2_pstorerdt_io : HInst<
20055(outs),
20056(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20057"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
20058tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20059let Inst{2-2} = 0b0;
20060let Inst{31-21} = 0b01000000110;
20061let isPredicated = 1;
20062let addrMode = BaseImmOffset;
20063let accessSize = DoubleWordAccess;
20064let mayStore = 1;
20065let BaseOpcode = "S2_storerd_io";
20066let CextOpcode = "S2_storerd";
20067let InputType = "imm";
20068let isExtendable = 1;
20069let opExtendable = 2;
20070let isExtentSigned = 0;
20071let opExtentBits = 9;
20072let opExtentAlign = 3;
20073}
20074def S2_pstorerdt_pi : HInst<
20075(outs IntRegs:$Rx32),
20076(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20077"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
20078tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20079let Inst{2-2} = 0b0;
20080let Inst{7-7} = 0b0;
20081let Inst{13-13} = 0b1;
20082let Inst{31-21} = 0b10101011110;
20083let isPredicated = 1;
20084let addrMode = PostInc;
20085let accessSize = DoubleWordAccess;
20086let mayStore = 1;
20087let BaseOpcode = "S2_storerd_pi";
20088let CextOpcode = "S2_storerd";
20089let Constraints = "$Rx32 = $Rx32in";
20090}
20091def S2_pstorerdt_zomap : HInst<
20092(outs),
20093(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20094"if ($Pv4) memd($Rs32) = $Rtt32",
20095tc_8035e91f, TypeMAPPING> {
20096let isPseudo = 1;
20097let isCodeGenOnly = 1;
20098}
20099def S2_pstorerdtnew_pi : HInst<
20100(outs IntRegs:$Rx32),
20101(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20102"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20103tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20104let Inst{2-2} = 0b0;
20105let Inst{7-7} = 0b1;
20106let Inst{13-13} = 0b1;
20107let Inst{31-21} = 0b10101011110;
20108let isPredicated = 1;
20109let addrMode = PostInc;
20110let accessSize = DoubleWordAccess;
20111let isPredicatedNew = 1;
20112let mayStore = 1;
20113let BaseOpcode = "S2_storerd_pi";
20114let CextOpcode = "S2_storerd";
20115let Constraints = "$Rx32 = $Rx32in";
20116}
20117def S2_pstorerff_io : HInst<
20118(outs),
20119(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20120"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20121tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20122let Inst{2-2} = 0b0;
20123let Inst{31-21} = 0b01000100011;
20124let isPredicated = 1;
20125let isPredicatedFalse = 1;
20126let addrMode = BaseImmOffset;
20127let accessSize = HalfWordAccess;
20128let mayStore = 1;
20129let BaseOpcode = "S2_storerf_io";
20130let CextOpcode = "S2_storerf";
20131let InputType = "imm";
20132let isExtendable = 1;
20133let opExtendable = 2;
20134let isExtentSigned = 0;
20135let opExtentBits = 7;
20136let opExtentAlign = 1;
20137}
20138def S2_pstorerff_pi : HInst<
20139(outs IntRegs:$Rx32),
20140(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20141"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20142tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20143let Inst{2-2} = 0b1;
20144let Inst{7-7} = 0b0;
20145let Inst{13-13} = 0b1;
20146let Inst{31-21} = 0b10101011011;
20147let isPredicated = 1;
20148let isPredicatedFalse = 1;
20149let addrMode = PostInc;
20150let accessSize = HalfWordAccess;
20151let mayStore = 1;
20152let BaseOpcode = "S2_storerf_pi";
20153let CextOpcode = "S2_storerf";
20154let Constraints = "$Rx32 = $Rx32in";
20155}
20156def S2_pstorerff_zomap : HInst<
20157(outs),
20158(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20159"if (!$Pv4) memh($Rs32) = $Rt32.h",
20160tc_8035e91f, TypeMAPPING> {
20161let isPseudo = 1;
20162let isCodeGenOnly = 1;
20163}
20164def S2_pstorerffnew_pi : HInst<
20165(outs IntRegs:$Rx32),
20166(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20167"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20168tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20169let Inst{2-2} = 0b1;
20170let Inst{7-7} = 0b1;
20171let Inst{13-13} = 0b1;
20172let Inst{31-21} = 0b10101011011;
20173let isPredicated = 1;
20174let isPredicatedFalse = 1;
20175let addrMode = PostInc;
20176let accessSize = HalfWordAccess;
20177let isPredicatedNew = 1;
20178let mayStore = 1;
20179let BaseOpcode = "S2_storerf_pi";
20180let CextOpcode = "S2_storerf";
20181let Constraints = "$Rx32 = $Rx32in";
20182}
20183def S2_pstorerft_io : HInst<
20184(outs),
20185(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20186"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20187tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20188let Inst{2-2} = 0b0;
20189let Inst{31-21} = 0b01000000011;
20190let isPredicated = 1;
20191let addrMode = BaseImmOffset;
20192let accessSize = HalfWordAccess;
20193let mayStore = 1;
20194let BaseOpcode = "S2_storerf_io";
20195let CextOpcode = "S2_storerf";
20196let InputType = "imm";
20197let isExtendable = 1;
20198let opExtendable = 2;
20199let isExtentSigned = 0;
20200let opExtentBits = 7;
20201let opExtentAlign = 1;
20202}
20203def S2_pstorerft_pi : HInst<
20204(outs IntRegs:$Rx32),
20205(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20206"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20207tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20208let Inst{2-2} = 0b0;
20209let Inst{7-7} = 0b0;
20210let Inst{13-13} = 0b1;
20211let Inst{31-21} = 0b10101011011;
20212let isPredicated = 1;
20213let addrMode = PostInc;
20214let accessSize = HalfWordAccess;
20215let mayStore = 1;
20216let BaseOpcode = "S2_storerf_pi";
20217let CextOpcode = "S2_storerf";
20218let Constraints = "$Rx32 = $Rx32in";
20219}
20220def S2_pstorerft_zomap : HInst<
20221(outs),
20222(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20223"if ($Pv4) memh($Rs32) = $Rt32.h",
20224tc_8035e91f, TypeMAPPING> {
20225let isPseudo = 1;
20226let isCodeGenOnly = 1;
20227}
20228def S2_pstorerftnew_pi : HInst<
20229(outs IntRegs:$Rx32),
20230(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20231"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20232tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20233let Inst{2-2} = 0b0;
20234let Inst{7-7} = 0b1;
20235let Inst{13-13} = 0b1;
20236let Inst{31-21} = 0b10101011011;
20237let isPredicated = 1;
20238let addrMode = PostInc;
20239let accessSize = HalfWordAccess;
20240let isPredicatedNew = 1;
20241let mayStore = 1;
20242let BaseOpcode = "S2_storerf_pi";
20243let CextOpcode = "S2_storerf";
20244let Constraints = "$Rx32 = $Rx32in";
20245}
20246def S2_pstorerhf_io : HInst<
20247(outs),
20248(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20249"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
20250tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20251let Inst{2-2} = 0b0;
20252let Inst{31-21} = 0b01000100010;
20253let isPredicated = 1;
20254let isPredicatedFalse = 1;
20255let addrMode = BaseImmOffset;
20256let accessSize = HalfWordAccess;
20257let mayStore = 1;
20258let BaseOpcode = "S2_storerh_io";
20259let CextOpcode = "S2_storerh";
20260let InputType = "imm";
20261let isNVStorable = 1;
20262let isExtendable = 1;
20263let opExtendable = 2;
20264let isExtentSigned = 0;
20265let opExtentBits = 7;
20266let opExtentAlign = 1;
20267}
20268def S2_pstorerhf_pi : HInst<
20269(outs IntRegs:$Rx32),
20270(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20271"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
20272tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20273let Inst{2-2} = 0b1;
20274let Inst{7-7} = 0b0;
20275let Inst{13-13} = 0b1;
20276let Inst{31-21} = 0b10101011010;
20277let isPredicated = 1;
20278let isPredicatedFalse = 1;
20279let addrMode = PostInc;
20280let accessSize = HalfWordAccess;
20281let mayStore = 1;
20282let BaseOpcode = "S2_storerh_pi";
20283let isNVStorable = 1;
20284let Constraints = "$Rx32 = $Rx32in";
20285}
20286def S2_pstorerhf_zomap : HInst<
20287(outs),
20288(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20289"if (!$Pv4) memh($Rs32) = $Rt32",
20290tc_8035e91f, TypeMAPPING> {
20291let isPseudo = 1;
20292let isCodeGenOnly = 1;
20293}
20294def S2_pstorerhfnew_pi : HInst<
20295(outs IntRegs:$Rx32),
20296(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20297"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20298tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20299let Inst{2-2} = 0b1;
20300let Inst{7-7} = 0b1;
20301let Inst{13-13} = 0b1;
20302let Inst{31-21} = 0b10101011010;
20303let isPredicated = 1;
20304let isPredicatedFalse = 1;
20305let addrMode = PostInc;
20306let accessSize = HalfWordAccess;
20307let isPredicatedNew = 1;
20308let mayStore = 1;
20309let BaseOpcode = "S2_storerh_pi";
20310let isNVStorable = 1;
20311let Constraints = "$Rx32 = $Rx32in";
20312}
20313def S2_pstorerhnewf_io : HInst<
20314(outs),
20315(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20316"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20317tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20318let Inst{2-2} = 0b0;
20319let Inst{12-11} = 0b01;
20320let Inst{31-21} = 0b01000100101;
20321let isPredicated = 1;
20322let isPredicatedFalse = 1;
20323let addrMode = BaseImmOffset;
20324let accessSize = HalfWordAccess;
20325let isNVStore = 1;
20326let isNewValue = 1;
20327let isRestrictNoSlot1Store = 1;
20328let mayStore = 1;
20329let BaseOpcode = "S2_storerh_io";
20330let CextOpcode = "S2_storerh";
20331let InputType = "imm";
20332let isExtendable = 1;
20333let opExtendable = 2;
20334let isExtentSigned = 0;
20335let opExtentBits = 7;
20336let opExtentAlign = 1;
20337let opNewValue = 3;
20338}
20339def S2_pstorerhnewf_pi : HInst<
20340(outs IntRegs:$Rx32),
20341(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20342"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20343tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20344let Inst{2-2} = 0b1;
20345let Inst{7-7} = 0b0;
20346let Inst{13-11} = 0b101;
20347let Inst{31-21} = 0b10101011101;
20348let isPredicated = 1;
20349let isPredicatedFalse = 1;
20350let addrMode = PostInc;
20351let accessSize = HalfWordAccess;
20352let isNVStore = 1;
20353let isNewValue = 1;
20354let isRestrictNoSlot1Store = 1;
20355let mayStore = 1;
20356let BaseOpcode = "S2_storerh_pi";
20357let CextOpcode = "S2_storerh";
20358let opNewValue = 4;
20359let Constraints = "$Rx32 = $Rx32in";
20360}
20361def S2_pstorerhnewf_zomap : HInst<
20362(outs),
20363(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20364"if (!$Pv4) memh($Rs32) = $Nt8.new",
20365tc_011e0e9d, TypeMAPPING> {
20366let isPseudo = 1;
20367let isCodeGenOnly = 1;
20368let opNewValue = 2;
20369}
20370def S2_pstorerhnewfnew_pi : HInst<
20371(outs IntRegs:$Rx32),
20372(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20373"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20374tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20375let Inst{2-2} = 0b1;
20376let Inst{7-7} = 0b1;
20377let Inst{13-11} = 0b101;
20378let Inst{31-21} = 0b10101011101;
20379let isPredicated = 1;
20380let isPredicatedFalse = 1;
20381let addrMode = PostInc;
20382let accessSize = HalfWordAccess;
20383let isNVStore = 1;
20384let isPredicatedNew = 1;
20385let isNewValue = 1;
20386let isRestrictNoSlot1Store = 1;
20387let mayStore = 1;
20388let BaseOpcode = "S2_storerh_pi";
20389let CextOpcode = "S2_storerh";
20390let opNewValue = 4;
20391let Constraints = "$Rx32 = $Rx32in";
20392}
20393def S2_pstorerhnewt_io : HInst<
20394(outs),
20395(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20396"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20397tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20398let Inst{2-2} = 0b0;
20399let Inst{12-11} = 0b01;
20400let Inst{31-21} = 0b01000000101;
20401let isPredicated = 1;
20402let addrMode = BaseImmOffset;
20403let accessSize = HalfWordAccess;
20404let isNVStore = 1;
20405let isNewValue = 1;
20406let isRestrictNoSlot1Store = 1;
20407let mayStore = 1;
20408let BaseOpcode = "S2_storerh_io";
20409let CextOpcode = "S2_storerh";
20410let InputType = "imm";
20411let isExtendable = 1;
20412let opExtendable = 2;
20413let isExtentSigned = 0;
20414let opExtentBits = 7;
20415let opExtentAlign = 1;
20416let opNewValue = 3;
20417}
20418def S2_pstorerhnewt_pi : HInst<
20419(outs IntRegs:$Rx32),
20420(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20421"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20422tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20423let Inst{2-2} = 0b0;
20424let Inst{7-7} = 0b0;
20425let Inst{13-11} = 0b101;
20426let Inst{31-21} = 0b10101011101;
20427let isPredicated = 1;
20428let addrMode = PostInc;
20429let accessSize = HalfWordAccess;
20430let isNVStore = 1;
20431let isNewValue = 1;
20432let isRestrictNoSlot1Store = 1;
20433let mayStore = 1;
20434let BaseOpcode = "S2_storerh_pi";
20435let CextOpcode = "S2_storerh";
20436let opNewValue = 4;
20437let Constraints = "$Rx32 = $Rx32in";
20438}
20439def S2_pstorerhnewt_zomap : HInst<
20440(outs),
20441(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20442"if ($Pv4) memh($Rs32) = $Nt8.new",
20443tc_011e0e9d, TypeMAPPING> {
20444let isPseudo = 1;
20445let isCodeGenOnly = 1;
20446let opNewValue = 2;
20447}
20448def S2_pstorerhnewtnew_pi : HInst<
20449(outs IntRegs:$Rx32),
20450(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20451"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20452tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20453let Inst{2-2} = 0b0;
20454let Inst{7-7} = 0b1;
20455let Inst{13-11} = 0b101;
20456let Inst{31-21} = 0b10101011101;
20457let isPredicated = 1;
20458let addrMode = PostInc;
20459let accessSize = HalfWordAccess;
20460let isNVStore = 1;
20461let isPredicatedNew = 1;
20462let isNewValue = 1;
20463let isRestrictNoSlot1Store = 1;
20464let mayStore = 1;
20465let BaseOpcode = "S2_storerh_pi";
20466let CextOpcode = "S2_storerh";
20467let opNewValue = 4;
20468let Constraints = "$Rx32 = $Rx32in";
20469}
20470def S2_pstorerht_io : HInst<
20471(outs),
20472(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20473"if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
20474tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20475let Inst{2-2} = 0b0;
20476let Inst{31-21} = 0b01000000010;
20477let isPredicated = 1;
20478let addrMode = BaseImmOffset;
20479let accessSize = HalfWordAccess;
20480let mayStore = 1;
20481let BaseOpcode = "S2_storerh_io";
20482let CextOpcode = "S2_storerh";
20483let InputType = "imm";
20484let isNVStorable = 1;
20485let isExtendable = 1;
20486let opExtendable = 2;
20487let isExtentSigned = 0;
20488let opExtentBits = 7;
20489let opExtentAlign = 1;
20490}
20491def S2_pstorerht_pi : HInst<
20492(outs IntRegs:$Rx32),
20493(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20494"if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
20495tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20496let Inst{2-2} = 0b0;
20497let Inst{7-7} = 0b0;
20498let Inst{13-13} = 0b1;
20499let Inst{31-21} = 0b10101011010;
20500let isPredicated = 1;
20501let addrMode = PostInc;
20502let accessSize = HalfWordAccess;
20503let mayStore = 1;
20504let BaseOpcode = "S2_storerh_pi";
20505let isNVStorable = 1;
20506let Constraints = "$Rx32 = $Rx32in";
20507}
20508def S2_pstorerht_zomap : HInst<
20509(outs),
20510(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20511"if ($Pv4) memh($Rs32) = $Rt32",
20512tc_8035e91f, TypeMAPPING> {
20513let isPseudo = 1;
20514let isCodeGenOnly = 1;
20515}
20516def S2_pstorerhtnew_pi : HInst<
20517(outs IntRegs:$Rx32),
20518(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20519"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20520tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20521let Inst{2-2} = 0b0;
20522let Inst{7-7} = 0b1;
20523let Inst{13-13} = 0b1;
20524let Inst{31-21} = 0b10101011010;
20525let isPredicated = 1;
20526let addrMode = PostInc;
20527let accessSize = HalfWordAccess;
20528let isPredicatedNew = 1;
20529let mayStore = 1;
20530let BaseOpcode = "S2_storerh_pi";
20531let isNVStorable = 1;
20532let Constraints = "$Rx32 = $Rx32in";
20533}
20534def S2_pstorerif_io : HInst<
20535(outs),
20536(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20537"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
20538tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20539let Inst{2-2} = 0b0;
20540let Inst{31-21} = 0b01000100100;
20541let isPredicated = 1;
20542let isPredicatedFalse = 1;
20543let addrMode = BaseImmOffset;
20544let accessSize = WordAccess;
20545let mayStore = 1;
20546let BaseOpcode = "S2_storeri_io";
20547let CextOpcode = "S2_storeri";
20548let InputType = "imm";
20549let isNVStorable = 1;
20550let isExtendable = 1;
20551let opExtendable = 2;
20552let isExtentSigned = 0;
20553let opExtentBits = 8;
20554let opExtentAlign = 2;
20555}
20556def S2_pstorerif_pi : HInst<
20557(outs IntRegs:$Rx32),
20558(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20559"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
20560tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20561let Inst{2-2} = 0b1;
20562let Inst{7-7} = 0b0;
20563let Inst{13-13} = 0b1;
20564let Inst{31-21} = 0b10101011100;
20565let isPredicated = 1;
20566let isPredicatedFalse = 1;
20567let addrMode = PostInc;
20568let accessSize = WordAccess;
20569let mayStore = 1;
20570let BaseOpcode = "S2_storeri_pi";
20571let isNVStorable = 1;
20572let Constraints = "$Rx32 = $Rx32in";
20573}
20574def S2_pstorerif_zomap : HInst<
20575(outs),
20576(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20577"if (!$Pv4) memw($Rs32) = $Rt32",
20578tc_8035e91f, TypeMAPPING> {
20579let isPseudo = 1;
20580let isCodeGenOnly = 1;
20581}
20582def S2_pstorerifnew_pi : HInst<
20583(outs IntRegs:$Rx32),
20584(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20585"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20586tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20587let Inst{2-2} = 0b1;
20588let Inst{7-7} = 0b1;
20589let Inst{13-13} = 0b1;
20590let Inst{31-21} = 0b10101011100;
20591let isPredicated = 1;
20592let isPredicatedFalse = 1;
20593let addrMode = PostInc;
20594let accessSize = WordAccess;
20595let isPredicatedNew = 1;
20596let mayStore = 1;
20597let BaseOpcode = "S2_storeri_pi";
20598let CextOpcode = "S2_storeri";
20599let isNVStorable = 1;
20600let Constraints = "$Rx32 = $Rx32in";
20601}
20602def S2_pstorerinewf_io : HInst<
20603(outs),
20604(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20605"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20606tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20607let Inst{2-2} = 0b0;
20608let Inst{12-11} = 0b10;
20609let Inst{31-21} = 0b01000100101;
20610let isPredicated = 1;
20611let isPredicatedFalse = 1;
20612let addrMode = BaseImmOffset;
20613let accessSize = WordAccess;
20614let isNVStore = 1;
20615let isNewValue = 1;
20616let isRestrictNoSlot1Store = 1;
20617let mayStore = 1;
20618let BaseOpcode = "S2_storeri_io";
20619let CextOpcode = "S2_storeri";
20620let InputType = "imm";
20621let isExtendable = 1;
20622let opExtendable = 2;
20623let isExtentSigned = 0;
20624let opExtentBits = 8;
20625let opExtentAlign = 2;
20626let opNewValue = 3;
20627}
20628def S2_pstorerinewf_pi : HInst<
20629(outs IntRegs:$Rx32),
20630(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20631"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20632tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20633let Inst{2-2} = 0b1;
20634let Inst{7-7} = 0b0;
20635let Inst{13-11} = 0b110;
20636let Inst{31-21} = 0b10101011101;
20637let isPredicated = 1;
20638let isPredicatedFalse = 1;
20639let addrMode = PostInc;
20640let accessSize = WordAccess;
20641let isNVStore = 1;
20642let isNewValue = 1;
20643let isRestrictNoSlot1Store = 1;
20644let mayStore = 1;
20645let BaseOpcode = "S2_storeri_pi";
20646let CextOpcode = "S2_storeri";
20647let opNewValue = 4;
20648let Constraints = "$Rx32 = $Rx32in";
20649}
20650def S2_pstorerinewf_zomap : HInst<
20651(outs),
20652(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20653"if (!$Pv4) memw($Rs32) = $Nt8.new",
20654tc_011e0e9d, TypeMAPPING> {
20655let isPseudo = 1;
20656let isCodeGenOnly = 1;
20657let opNewValue = 2;
20658}
20659def S2_pstorerinewfnew_pi : HInst<
20660(outs IntRegs:$Rx32),
20661(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20662"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20663tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20664let Inst{2-2} = 0b1;
20665let Inst{7-7} = 0b1;
20666let Inst{13-11} = 0b110;
20667let Inst{31-21} = 0b10101011101;
20668let isPredicated = 1;
20669let isPredicatedFalse = 1;
20670let addrMode = PostInc;
20671let accessSize = WordAccess;
20672let isNVStore = 1;
20673let isPredicatedNew = 1;
20674let isNewValue = 1;
20675let isRestrictNoSlot1Store = 1;
20676let mayStore = 1;
20677let BaseOpcode = "S2_storeri_pi";
20678let CextOpcode = "S2_storeri";
20679let opNewValue = 4;
20680let Constraints = "$Rx32 = $Rx32in";
20681}
20682def S2_pstorerinewt_io : HInst<
20683(outs),
20684(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20685"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20686tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20687let Inst{2-2} = 0b0;
20688let Inst{12-11} = 0b10;
20689let Inst{31-21} = 0b01000000101;
20690let isPredicated = 1;
20691let addrMode = BaseImmOffset;
20692let accessSize = WordAccess;
20693let isNVStore = 1;
20694let isNewValue = 1;
20695let isRestrictNoSlot1Store = 1;
20696let mayStore = 1;
20697let BaseOpcode = "S2_storeri_io";
20698let CextOpcode = "S2_storeri";
20699let InputType = "imm";
20700let isExtendable = 1;
20701let opExtendable = 2;
20702let isExtentSigned = 0;
20703let opExtentBits = 8;
20704let opExtentAlign = 2;
20705let opNewValue = 3;
20706}
20707def S2_pstorerinewt_pi : HInst<
20708(outs IntRegs:$Rx32),
20709(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20710"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20711tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20712let Inst{2-2} = 0b0;
20713let Inst{7-7} = 0b0;
20714let Inst{13-11} = 0b110;
20715let Inst{31-21} = 0b10101011101;
20716let isPredicated = 1;
20717let addrMode = PostInc;
20718let accessSize = WordAccess;
20719let isNVStore = 1;
20720let isNewValue = 1;
20721let isRestrictNoSlot1Store = 1;
20722let mayStore = 1;
20723let BaseOpcode = "S2_storeri_pi";
20724let CextOpcode = "S2_storeri";
20725let opNewValue = 4;
20726let Constraints = "$Rx32 = $Rx32in";
20727}
20728def S2_pstorerinewt_zomap : HInst<
20729(outs),
20730(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20731"if ($Pv4) memw($Rs32) = $Nt8.new",
20732tc_011e0e9d, TypeMAPPING> {
20733let isPseudo = 1;
20734let isCodeGenOnly = 1;
20735let opNewValue = 2;
20736}
20737def S2_pstorerinewtnew_pi : HInst<
20738(outs IntRegs:$Rx32),
20739(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20740"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20741tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20742let Inst{2-2} = 0b0;
20743let Inst{7-7} = 0b1;
20744let Inst{13-11} = 0b110;
20745let Inst{31-21} = 0b10101011101;
20746let isPredicated = 1;
20747let addrMode = PostInc;
20748let accessSize = WordAccess;
20749let isNVStore = 1;
20750let isPredicatedNew = 1;
20751let isNewValue = 1;
20752let isRestrictNoSlot1Store = 1;
20753let mayStore = 1;
20754let BaseOpcode = "S2_storeri_pi";
20755let CextOpcode = "S2_storeri";
20756let opNewValue = 4;
20757let Constraints = "$Rx32 = $Rx32in";
20758}
20759def S2_pstorerit_io : HInst<
20760(outs),
20761(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20762"if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
20763tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20764let Inst{2-2} = 0b0;
20765let Inst{31-21} = 0b01000000100;
20766let isPredicated = 1;
20767let addrMode = BaseImmOffset;
20768let accessSize = WordAccess;
20769let mayStore = 1;
20770let BaseOpcode = "S2_storeri_io";
20771let CextOpcode = "S2_storeri";
20772let InputType = "imm";
20773let isNVStorable = 1;
20774let isExtendable = 1;
20775let opExtendable = 2;
20776let isExtentSigned = 0;
20777let opExtentBits = 8;
20778let opExtentAlign = 2;
20779}
20780def S2_pstorerit_pi : HInst<
20781(outs IntRegs:$Rx32),
20782(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20783"if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
20784tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20785let Inst{2-2} = 0b0;
20786let Inst{7-7} = 0b0;
20787let Inst{13-13} = 0b1;
20788let Inst{31-21} = 0b10101011100;
20789let isPredicated = 1;
20790let addrMode = PostInc;
20791let accessSize = WordAccess;
20792let mayStore = 1;
20793let BaseOpcode = "S2_storeri_pi";
20794let isNVStorable = 1;
20795let Constraints = "$Rx32 = $Rx32in";
20796}
20797def S2_pstorerit_zomap : HInst<
20798(outs),
20799(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20800"if ($Pv4) memw($Rs32) = $Rt32",
20801tc_8035e91f, TypeMAPPING> {
20802let isPseudo = 1;
20803let isCodeGenOnly = 1;
20804}
20805def S2_pstoreritnew_pi : HInst<
20806(outs IntRegs:$Rx32),
20807(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20808"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20809tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20810let Inst{2-2} = 0b0;
20811let Inst{7-7} = 0b1;
20812let Inst{13-13} = 0b1;
20813let Inst{31-21} = 0b10101011100;
20814let isPredicated = 1;
20815let addrMode = PostInc;
20816let accessSize = WordAccess;
20817let isPredicatedNew = 1;
20818let mayStore = 1;
20819let BaseOpcode = "S2_storeri_pi";
20820let isNVStorable = 1;
20821let Constraints = "$Rx32 = $Rx32in";
20822}
20823def S2_setbit_i : HInst<
20824(outs IntRegs:$Rd32),
20825(ins IntRegs:$Rs32, u5_0Imm:$Ii),
20826"$Rd32 = setbit($Rs32,#$Ii)",
20827tc_5da50c4b, TypeS_2op>, Enc_a05677 {
20828let Inst{7-5} = 0b000;
20829let Inst{13-13} = 0b0;
20830let Inst{31-21} = 0b10001100110;
20831let hasNewValue = 1;
20832let opNewValue = 0;
20833}
20834def S2_setbit_r : HInst<
20835(outs IntRegs:$Rd32),
20836(ins IntRegs:$Rs32, IntRegs:$Rt32),
20837"$Rd32 = setbit($Rs32,$Rt32)",
20838tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
20839let Inst{7-5} = 0b000;
20840let Inst{13-13} = 0b0;
20841let Inst{31-21} = 0b11000110100;
20842let hasNewValue = 1;
20843let opNewValue = 0;
20844}
20845def S2_shuffeb : HInst<
20846(outs DoubleRegs:$Rdd32),
20847(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20848"$Rdd32 = shuffeb($Rss32,$Rtt32)",
20849tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20850let Inst{7-5} = 0b010;
20851let Inst{13-13} = 0b0;
20852let Inst{31-21} = 0b11000001000;
20853}
20854def S2_shuffeh : HInst<
20855(outs DoubleRegs:$Rdd32),
20856(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20857"$Rdd32 = shuffeh($Rss32,$Rtt32)",
20858tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20859let Inst{7-5} = 0b110;
20860let Inst{13-13} = 0b0;
20861let Inst{31-21} = 0b11000001000;
20862}
20863def S2_shuffob : HInst<
20864(outs DoubleRegs:$Rdd32),
20865(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20866"$Rdd32 = shuffob($Rtt32,$Rss32)",
20867tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20868let Inst{7-5} = 0b100;
20869let Inst{13-13} = 0b0;
20870let Inst{31-21} = 0b11000001000;
20871}
20872def S2_shuffoh : HInst<
20873(outs DoubleRegs:$Rdd32),
20874(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20875"$Rdd32 = shuffoh($Rtt32,$Rss32)",
20876tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20877let Inst{7-5} = 0b000;
20878let Inst{13-13} = 0b0;
20879let Inst{31-21} = 0b11000001100;
20880}
20881def S2_storerb_io : HInst<
20882(outs),
20883(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
20884"memb($Rs32+#$Ii) = $Rt32",
20885tc_ae5babd7, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
20886let Inst{24-21} = 0b1000;
20887let Inst{31-27} = 0b10100;
20888let addrMode = BaseImmOffset;
20889let accessSize = ByteAccess;
20890let mayStore = 1;
20891let BaseOpcode = "S2_storerb_io";
20892let CextOpcode = "S2_storerb";
20893let InputType = "imm";
20894let isNVStorable = 1;
20895let isPredicable = 1;
20896let isExtendable = 1;
20897let opExtendable = 1;
20898let isExtentSigned = 1;
20899let opExtentBits = 11;
20900let opExtentAlign = 0;
20901}
20902def S2_storerb_pbr : HInst<
20903(outs IntRegs:$Rx32),
20904(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20905"memb($Rx32++$Mu2:brev) = $Rt32",
20906tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20907let Inst{7-0} = 0b00000000;
20908let Inst{31-21} = 0b10101111000;
20909let addrMode = PostInc;
20910let accessSize = ByteAccess;
20911let mayStore = 1;
20912let BaseOpcode = "S2_storerb_pbr";
20913let isNVStorable = 1;
20914let Constraints = "$Rx32 = $Rx32in";
20915}
20916def S2_storerb_pci : HInst<
20917(outs IntRegs:$Rx32),
20918(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20919"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20920tc_b4dc7630, TypeST>, Enc_b15941, AddrModeRel {
20921let Inst{2-0} = 0b000;
20922let Inst{7-7} = 0b0;
20923let Inst{31-21} = 0b10101001000;
20924let addrMode = PostInc;
20925let accessSize = ByteAccess;
20926let mayStore = 1;
20927let Uses = [CS];
20928let BaseOpcode = "S2_storerb_pci";
20929let isNVStorable = 1;
20930let Constraints = "$Rx32 = $Rx32in";
20931}
20932def S2_storerb_pcr : HInst<
20933(outs IntRegs:$Rx32),
20934(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20935"memb($Rx32++I:circ($Mu2)) = $Rt32",
20936tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20937let Inst{7-0} = 0b00000010;
20938let Inst{31-21} = 0b10101001000;
20939let addrMode = PostInc;
20940let accessSize = ByteAccess;
20941let mayStore = 1;
20942let Uses = [CS];
20943let BaseOpcode = "S2_storerb_pcr";
20944let isNVStorable = 1;
20945let Constraints = "$Rx32 = $Rx32in";
20946}
20947def S2_storerb_pi : HInst<
20948(outs IntRegs:$Rx32),
20949(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20950"memb($Rx32++#$Ii) = $Rt32",
20951tc_a2b365d2, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
20952let Inst{2-0} = 0b000;
20953let Inst{7-7} = 0b0;
20954let Inst{13-13} = 0b0;
20955let Inst{31-21} = 0b10101011000;
20956let addrMode = PostInc;
20957let accessSize = ByteAccess;
20958let mayStore = 1;
20959let BaseOpcode = "S2_storerb_pi";
20960let CextOpcode = "S2_storerb";
20961let isNVStorable = 1;
20962let isPredicable = 1;
20963let Constraints = "$Rx32 = $Rx32in";
20964}
20965def S2_storerb_pr : HInst<
20966(outs IntRegs:$Rx32),
20967(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20968"memb($Rx32++$Mu2) = $Rt32",
20969tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20970let Inst{7-0} = 0b00000000;
20971let Inst{31-21} = 0b10101101000;
20972let addrMode = PostInc;
20973let accessSize = ByteAccess;
20974let mayStore = 1;
20975let BaseOpcode = "S2_storerb_pr";
20976let isNVStorable = 1;
20977let Constraints = "$Rx32 = $Rx32in";
20978}
20979def S2_storerb_zomap : HInst<
20980(outs),
20981(ins IntRegs:$Rs32, IntRegs:$Rt32),
20982"memb($Rs32) = $Rt32",
20983tc_ae5babd7, TypeMAPPING> {
20984let isPseudo = 1;
20985let isCodeGenOnly = 1;
20986}
20987def S2_storerbgp : HInst<
20988(outs),
20989(ins u32_0Imm:$Ii, IntRegs:$Rt32),
20990"memb(gp+#$Ii) = $Rt32",
20991tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
20992let Inst{24-21} = 0b0000;
20993let Inst{31-27} = 0b01001;
20994let accessSize = ByteAccess;
20995let mayStore = 1;
20996let Uses = [GP];
20997let BaseOpcode = "S2_storerbabs";
20998let isNVStorable = 1;
20999let isPredicable = 1;
21000let opExtendable = 0;
21001let isExtentSigned = 0;
21002let opExtentBits = 16;
21003let opExtentAlign = 0;
21004}
21005def S2_storerbnew_io : HInst<
21006(outs),
21007(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
21008"memb($Rs32+#$Ii) = $Nt8.new",
21009tc_5deb5e47, TypeST>, Enc_4df4e9, AddrModeRel {
21010let Inst{12-11} = 0b00;
21011let Inst{24-21} = 0b1101;
21012let Inst{31-27} = 0b10100;
21013let addrMode = BaseImmOffset;
21014let accessSize = ByteAccess;
21015let isNVStore = 1;
21016let isNewValue = 1;
21017let isRestrictNoSlot1Store = 1;
21018let mayStore = 1;
21019let BaseOpcode = "S2_storerb_io";
21020let CextOpcode = "S2_storerb";
21021let InputType = "imm";
21022let isPredicable = 1;
21023let isExtendable = 1;
21024let opExtendable = 1;
21025let isExtentSigned = 1;
21026let opExtentBits = 11;
21027let opExtentAlign = 0;
21028let opNewValue = 2;
21029}
21030def S2_storerbnew_pbr : HInst<
21031(outs IntRegs:$Rx32),
21032(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21033"memb($Rx32++$Mu2:brev) = $Nt8.new",
21034tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21035let Inst{7-0} = 0b00000000;
21036let Inst{12-11} = 0b00;
21037let Inst{31-21} = 0b10101111101;
21038let addrMode = PostInc;
21039let accessSize = ByteAccess;
21040let isNVStore = 1;
21041let isNewValue = 1;
21042let isRestrictNoSlot1Store = 1;
21043let mayStore = 1;
21044let BaseOpcode = "S2_storerb_pbr";
21045let opNewValue = 3;
21046let Constraints = "$Rx32 = $Rx32in";
21047}
21048def S2_storerbnew_pci : HInst<
21049(outs IntRegs:$Rx32),
21050(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21051"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21052tc_addc37a8, TypeST>, Enc_96ce4f, AddrModeRel {
21053let Inst{2-0} = 0b000;
21054let Inst{7-7} = 0b0;
21055let Inst{12-11} = 0b00;
21056let Inst{31-21} = 0b10101001101;
21057let addrMode = PostInc;
21058let accessSize = ByteAccess;
21059let isNVStore = 1;
21060let isNewValue = 1;
21061let isRestrictNoSlot1Store = 1;
21062let mayStore = 1;
21063let Uses = [CS];
21064let BaseOpcode = "S2_storerb_pci";
21065let opNewValue = 4;
21066let Constraints = "$Rx32 = $Rx32in";
21067}
21068def S2_storerbnew_pcr : HInst<
21069(outs IntRegs:$Rx32),
21070(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21071"memb($Rx32++I:circ($Mu2)) = $Nt8.new",
21072tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21073let Inst{7-0} = 0b00000010;
21074let Inst{12-11} = 0b00;
21075let Inst{31-21} = 0b10101001101;
21076let addrMode = PostInc;
21077let accessSize = ByteAccess;
21078let isNVStore = 1;
21079let isNewValue = 1;
21080let isRestrictNoSlot1Store = 1;
21081let mayStore = 1;
21082let Uses = [CS];
21083let BaseOpcode = "S2_storerb_pcr";
21084let opNewValue = 3;
21085let Constraints = "$Rx32 = $Rx32in";
21086}
21087def S2_storerbnew_pi : HInst<
21088(outs IntRegs:$Rx32),
21089(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
21090"memb($Rx32++#$Ii) = $Nt8.new",
21091tc_92240447, TypeST>, Enc_c7cd90, AddrModeRel {
21092let Inst{2-0} = 0b000;
21093let Inst{7-7} = 0b0;
21094let Inst{13-11} = 0b000;
21095let Inst{31-21} = 0b10101011101;
21096let addrMode = PostInc;
21097let accessSize = ByteAccess;
21098let isNVStore = 1;
21099let isNewValue = 1;
21100let isRestrictNoSlot1Store = 1;
21101let mayStore = 1;
21102let BaseOpcode = "S2_storerb_pi";
21103let isNVStorable = 1;
21104let isPredicable = 1;
21105let opNewValue = 3;
21106let Constraints = "$Rx32 = $Rx32in";
21107}
21108def S2_storerbnew_pr : HInst<
21109(outs IntRegs:$Rx32),
21110(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21111"memb($Rx32++$Mu2) = $Nt8.new",
21112tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21113let Inst{7-0} = 0b00000000;
21114let Inst{12-11} = 0b00;
21115let Inst{31-21} = 0b10101101101;
21116let addrMode = PostInc;
21117let accessSize = ByteAccess;
21118let isNVStore = 1;
21119let isNewValue = 1;
21120let isRestrictNoSlot1Store = 1;
21121let mayStore = 1;
21122let BaseOpcode = "S2_storerb_pr";
21123let opNewValue = 3;
21124let Constraints = "$Rx32 = $Rx32in";
21125}
21126def S2_storerbnew_zomap : HInst<
21127(outs),
21128(ins IntRegs:$Rs32, IntRegs:$Nt8),
21129"memb($Rs32) = $Nt8.new",
21130tc_5deb5e47, TypeMAPPING> {
21131let isPseudo = 1;
21132let isCodeGenOnly = 1;
21133let opNewValue = 1;
21134}
21135def S2_storerbnewgp : HInst<
21136(outs),
21137(ins u32_0Imm:$Ii, IntRegs:$Nt8),
21138"memb(gp+#$Ii) = $Nt8.new",
21139tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
21140let Inst{12-11} = 0b00;
21141let Inst{24-21} = 0b0101;
21142let Inst{31-27} = 0b01001;
21143let accessSize = ByteAccess;
21144let isNVStore = 1;
21145let isNewValue = 1;
21146let isRestrictNoSlot1Store = 1;
21147let mayStore = 1;
21148let Uses = [GP];
21149let BaseOpcode = "S2_storerbabs";
21150let isPredicable = 1;
21151let opExtendable = 0;
21152let isExtentSigned = 0;
21153let opExtentBits = 16;
21154let opExtentAlign = 0;
21155let opNewValue = 1;
21156}
21157def S2_storerd_io : HInst<
21158(outs),
21159(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
21160"memd($Rs32+#$Ii) = $Rtt32",
21161tc_ae5babd7, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
21162let Inst{24-21} = 0b1110;
21163let Inst{31-27} = 0b10100;
21164let addrMode = BaseImmOffset;
21165let accessSize = DoubleWordAccess;
21166let mayStore = 1;
21167let BaseOpcode = "S2_storerd_io";
21168let CextOpcode = "S2_storerd";
21169let InputType = "imm";
21170let isPredicable = 1;
21171let isExtendable = 1;
21172let opExtendable = 1;
21173let isExtentSigned = 1;
21174let opExtentBits = 14;
21175let opExtentAlign = 3;
21176}
21177def S2_storerd_pbr : HInst<
21178(outs IntRegs:$Rx32),
21179(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21180"memd($Rx32++$Mu2:brev) = $Rtt32",
21181tc_a2b365d2, TypeST>, Enc_928ca1 {
21182let Inst{7-0} = 0b00000000;
21183let Inst{31-21} = 0b10101111110;
21184let addrMode = PostInc;
21185let accessSize = DoubleWordAccess;
21186let mayStore = 1;
21187let Constraints = "$Rx32 = $Rx32in";
21188}
21189def S2_storerd_pci : HInst<
21190(outs IntRegs:$Rx32),
21191(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21192"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
21193tc_b4dc7630, TypeST>, Enc_395cc4 {
21194let Inst{2-0} = 0b000;
21195let Inst{7-7} = 0b0;
21196let Inst{31-21} = 0b10101001110;
21197let addrMode = PostInc;
21198let accessSize = DoubleWordAccess;
21199let mayStore = 1;
21200let Uses = [CS];
21201let Constraints = "$Rx32 = $Rx32in";
21202}
21203def S2_storerd_pcr : HInst<
21204(outs IntRegs:$Rx32),
21205(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21206"memd($Rx32++I:circ($Mu2)) = $Rtt32",
21207tc_a2b365d2, TypeST>, Enc_928ca1 {
21208let Inst{7-0} = 0b00000010;
21209let Inst{31-21} = 0b10101001110;
21210let addrMode = PostInc;
21211let accessSize = DoubleWordAccess;
21212let mayStore = 1;
21213let Uses = [CS];
21214let Constraints = "$Rx32 = $Rx32in";
21215}
21216def S2_storerd_pi : HInst<
21217(outs IntRegs:$Rx32),
21218(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
21219"memd($Rx32++#$Ii) = $Rtt32",
21220tc_a2b365d2, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
21221let Inst{2-0} = 0b000;
21222let Inst{7-7} = 0b0;
21223let Inst{13-13} = 0b0;
21224let Inst{31-21} = 0b10101011110;
21225let addrMode = PostInc;
21226let accessSize = DoubleWordAccess;
21227let mayStore = 1;
21228let BaseOpcode = "S2_storerd_pi";
21229let CextOpcode = "S2_storerd";
21230let isPredicable = 1;
21231let Constraints = "$Rx32 = $Rx32in";
21232}
21233def S2_storerd_pr : HInst<
21234(outs IntRegs:$Rx32),
21235(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21236"memd($Rx32++$Mu2) = $Rtt32",
21237tc_a2b365d2, TypeST>, Enc_928ca1 {
21238let Inst{7-0} = 0b00000000;
21239let Inst{31-21} = 0b10101101110;
21240let addrMode = PostInc;
21241let accessSize = DoubleWordAccess;
21242let mayStore = 1;
21243let Constraints = "$Rx32 = $Rx32in";
21244}
21245def S2_storerd_zomap : HInst<
21246(outs),
21247(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
21248"memd($Rs32) = $Rtt32",
21249tc_ae5babd7, TypeMAPPING> {
21250let isPseudo = 1;
21251let isCodeGenOnly = 1;
21252}
21253def S2_storerdgp : HInst<
21254(outs),
21255(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
21256"memd(gp+#$Ii) = $Rtt32",
21257tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
21258let Inst{24-21} = 0b0110;
21259let Inst{31-27} = 0b01001;
21260let accessSize = DoubleWordAccess;
21261let mayStore = 1;
21262let Uses = [GP];
21263let BaseOpcode = "S2_storerdabs";
21264let isPredicable = 1;
21265let opExtendable = 0;
21266let isExtentSigned = 0;
21267let opExtentBits = 19;
21268let opExtentAlign = 3;
21269}
21270def S2_storerf_io : HInst<
21271(outs),
21272(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21273"memh($Rs32+#$Ii) = $Rt32.h",
21274tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21275let Inst{24-21} = 0b1011;
21276let Inst{31-27} = 0b10100;
21277let addrMode = BaseImmOffset;
21278let accessSize = HalfWordAccess;
21279let mayStore = 1;
21280let BaseOpcode = "S2_storerf_io";
21281let CextOpcode = "S2_storerf";
21282let InputType = "imm";
21283let isPredicable = 1;
21284let isExtendable = 1;
21285let opExtendable = 1;
21286let isExtentSigned = 1;
21287let opExtentBits = 12;
21288let opExtentAlign = 1;
21289}
21290def S2_storerf_pbr : HInst<
21291(outs IntRegs:$Rx32),
21292(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21293"memh($Rx32++$Mu2:brev) = $Rt32.h",
21294tc_a2b365d2, TypeST>, Enc_d5c73f {
21295let Inst{7-0} = 0b00000000;
21296let Inst{31-21} = 0b10101111011;
21297let addrMode = PostInc;
21298let accessSize = HalfWordAccess;
21299let mayStore = 1;
21300let Constraints = "$Rx32 = $Rx32in";
21301}
21302def S2_storerf_pci : HInst<
21303(outs IntRegs:$Rx32),
21304(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21305"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
21306tc_b4dc7630, TypeST>, Enc_935d9b {
21307let Inst{2-0} = 0b000;
21308let Inst{7-7} = 0b0;
21309let Inst{31-21} = 0b10101001011;
21310let addrMode = PostInc;
21311let accessSize = HalfWordAccess;
21312let mayStore = 1;
21313let Uses = [CS];
21314let Constraints = "$Rx32 = $Rx32in";
21315}
21316def S2_storerf_pcr : HInst<
21317(outs IntRegs:$Rx32),
21318(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21319"memh($Rx32++I:circ($Mu2)) = $Rt32.h",
21320tc_a2b365d2, TypeST>, Enc_d5c73f {
21321let Inst{7-0} = 0b00000010;
21322let Inst{31-21} = 0b10101001011;
21323let addrMode = PostInc;
21324let accessSize = HalfWordAccess;
21325let mayStore = 1;
21326let Uses = [CS];
21327let Constraints = "$Rx32 = $Rx32in";
21328}
21329def S2_storerf_pi : HInst<
21330(outs IntRegs:$Rx32),
21331(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21332"memh($Rx32++#$Ii) = $Rt32.h",
21333tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21334let Inst{2-0} = 0b000;
21335let Inst{7-7} = 0b0;
21336let Inst{13-13} = 0b0;
21337let Inst{31-21} = 0b10101011011;
21338let addrMode = PostInc;
21339let accessSize = HalfWordAccess;
21340let mayStore = 1;
21341let BaseOpcode = "S2_storerf_pi";
21342let CextOpcode = "S2_storerf";
21343let isPredicable = 1;
21344let Constraints = "$Rx32 = $Rx32in";
21345}
21346def S2_storerf_pr : HInst<
21347(outs IntRegs:$Rx32),
21348(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21349"memh($Rx32++$Mu2) = $Rt32.h",
21350tc_a2b365d2, TypeST>, Enc_d5c73f {
21351let Inst{7-0} = 0b00000000;
21352let Inst{31-21} = 0b10101101011;
21353let addrMode = PostInc;
21354let accessSize = HalfWordAccess;
21355let mayStore = 1;
21356let Constraints = "$Rx32 = $Rx32in";
21357}
21358def S2_storerf_zomap : HInst<
21359(outs),
21360(ins IntRegs:$Rs32, IntRegs:$Rt32),
21361"memh($Rs32) = $Rt32.h",
21362tc_ae5babd7, TypeMAPPING> {
21363let isPseudo = 1;
21364let isCodeGenOnly = 1;
21365}
21366def S2_storerfgp : HInst<
21367(outs),
21368(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21369"memh(gp+#$Ii) = $Rt32.h",
21370tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21371let Inst{24-21} = 0b0011;
21372let Inst{31-27} = 0b01001;
21373let accessSize = HalfWordAccess;
21374let mayStore = 1;
21375let Uses = [GP];
21376let BaseOpcode = "S2_storerfabs";
21377let isPredicable = 1;
21378let opExtendable = 0;
21379let isExtentSigned = 0;
21380let opExtentBits = 17;
21381let opExtentAlign = 1;
21382}
21383def S2_storerh_io : HInst<
21384(outs),
21385(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21386"memh($Rs32+#$Ii) = $Rt32",
21387tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21388let Inst{24-21} = 0b1010;
21389let Inst{31-27} = 0b10100;
21390let addrMode = BaseImmOffset;
21391let accessSize = HalfWordAccess;
21392let mayStore = 1;
21393let BaseOpcode = "S2_storerh_io";
21394let CextOpcode = "S2_storerh";
21395let InputType = "imm";
21396let isNVStorable = 1;
21397let isPredicable = 1;
21398let isExtendable = 1;
21399let opExtendable = 1;
21400let isExtentSigned = 1;
21401let opExtentBits = 12;
21402let opExtentAlign = 1;
21403}
21404def S2_storerh_pbr : HInst<
21405(outs IntRegs:$Rx32),
21406(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21407"memh($Rx32++$Mu2:brev) = $Rt32",
21408tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21409let Inst{7-0} = 0b00000000;
21410let Inst{31-21} = 0b10101111010;
21411let addrMode = PostInc;
21412let accessSize = HalfWordAccess;
21413let mayStore = 1;
21414let BaseOpcode = "S2_storerh_pbr";
21415let isNVStorable = 1;
21416let Constraints = "$Rx32 = $Rx32in";
21417}
21418def S2_storerh_pci : HInst<
21419(outs IntRegs:$Rx32),
21420(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21421"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21422tc_b4dc7630, TypeST>, Enc_935d9b, AddrModeRel {
21423let Inst{2-0} = 0b000;
21424let Inst{7-7} = 0b0;
21425let Inst{31-21} = 0b10101001010;
21426let addrMode = PostInc;
21427let accessSize = HalfWordAccess;
21428let mayStore = 1;
21429let Uses = [CS];
21430let BaseOpcode = "S2_storerh_pci";
21431let isNVStorable = 1;
21432let Constraints = "$Rx32 = $Rx32in";
21433}
21434def S2_storerh_pcr : HInst<
21435(outs IntRegs:$Rx32),
21436(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21437"memh($Rx32++I:circ($Mu2)) = $Rt32",
21438tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21439let Inst{7-0} = 0b00000010;
21440let Inst{31-21} = 0b10101001010;
21441let addrMode = PostInc;
21442let accessSize = HalfWordAccess;
21443let mayStore = 1;
21444let Uses = [CS];
21445let BaseOpcode = "S2_storerh_pcr";
21446let isNVStorable = 1;
21447let Constraints = "$Rx32 = $Rx32in";
21448}
21449def S2_storerh_pi : HInst<
21450(outs IntRegs:$Rx32),
21451(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21452"memh($Rx32++#$Ii) = $Rt32",
21453tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21454let Inst{2-0} = 0b000;
21455let Inst{7-7} = 0b0;
21456let Inst{13-13} = 0b0;
21457let Inst{31-21} = 0b10101011010;
21458let addrMode = PostInc;
21459let accessSize = HalfWordAccess;
21460let mayStore = 1;
21461let BaseOpcode = "S2_storerh_pi";
21462let CextOpcode = "S2_storerh";
21463let isNVStorable = 1;
21464let isPredicable = 1;
21465let Constraints = "$Rx32 = $Rx32in";
21466}
21467def S2_storerh_pr : HInst<
21468(outs IntRegs:$Rx32),
21469(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21470"memh($Rx32++$Mu2) = $Rt32",
21471tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21472let Inst{7-0} = 0b00000000;
21473let Inst{31-21} = 0b10101101010;
21474let addrMode = PostInc;
21475let accessSize = HalfWordAccess;
21476let mayStore = 1;
21477let BaseOpcode = "S2_storerh_pr";
21478let isNVStorable = 1;
21479let Constraints = "$Rx32 = $Rx32in";
21480}
21481def S2_storerh_zomap : HInst<
21482(outs),
21483(ins IntRegs:$Rs32, IntRegs:$Rt32),
21484"memh($Rs32) = $Rt32",
21485tc_ae5babd7, TypeMAPPING> {
21486let isPseudo = 1;
21487let isCodeGenOnly = 1;
21488}
21489def S2_storerhgp : HInst<
21490(outs),
21491(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21492"memh(gp+#$Ii) = $Rt32",
21493tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21494let Inst{24-21} = 0b0010;
21495let Inst{31-27} = 0b01001;
21496let accessSize = HalfWordAccess;
21497let mayStore = 1;
21498let Uses = [GP];
21499let BaseOpcode = "S2_storerhabs";
21500let isNVStorable = 1;
21501let isPredicable = 1;
21502let opExtendable = 0;
21503let isExtentSigned = 0;
21504let opExtentBits = 17;
21505let opExtentAlign = 1;
21506}
21507def S2_storerhnew_io : HInst<
21508(outs),
21509(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
21510"memh($Rs32+#$Ii) = $Nt8.new",
21511tc_5deb5e47, TypeST>, Enc_0d8870, AddrModeRel {
21512let Inst{12-11} = 0b01;
21513let Inst{24-21} = 0b1101;
21514let Inst{31-27} = 0b10100;
21515let addrMode = BaseImmOffset;
21516let accessSize = HalfWordAccess;
21517let isNVStore = 1;
21518let isNewValue = 1;
21519let isRestrictNoSlot1Store = 1;
21520let mayStore = 1;
21521let BaseOpcode = "S2_storerh_io";
21522let CextOpcode = "S2_storerh";
21523let InputType = "imm";
21524let isPredicable = 1;
21525let isExtendable = 1;
21526let opExtendable = 1;
21527let isExtentSigned = 1;
21528let opExtentBits = 12;
21529let opExtentAlign = 1;
21530let opNewValue = 2;
21531}
21532def S2_storerhnew_pbr : HInst<
21533(outs IntRegs:$Rx32),
21534(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21535"memh($Rx32++$Mu2:brev) = $Nt8.new",
21536tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21537let Inst{7-0} = 0b00000000;
21538let Inst{12-11} = 0b01;
21539let Inst{31-21} = 0b10101111101;
21540let addrMode = PostInc;
21541let accessSize = HalfWordAccess;
21542let isNVStore = 1;
21543let isNewValue = 1;
21544let isRestrictNoSlot1Store = 1;
21545let mayStore = 1;
21546let BaseOpcode = "S2_storerh_pbr";
21547let opNewValue = 3;
21548let Constraints = "$Rx32 = $Rx32in";
21549}
21550def S2_storerhnew_pci : HInst<
21551(outs IntRegs:$Rx32),
21552(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21553"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21554tc_addc37a8, TypeST>, Enc_91b9fe, AddrModeRel {
21555let Inst{2-0} = 0b000;
21556let Inst{7-7} = 0b0;
21557let Inst{12-11} = 0b01;
21558let Inst{31-21} = 0b10101001101;
21559let addrMode = PostInc;
21560let accessSize = HalfWordAccess;
21561let isNVStore = 1;
21562let isNewValue = 1;
21563let isRestrictNoSlot1Store = 1;
21564let mayStore = 1;
21565let Uses = [CS];
21566let BaseOpcode = "S2_storerh_pci";
21567let opNewValue = 4;
21568let Constraints = "$Rx32 = $Rx32in";
21569}
21570def S2_storerhnew_pcr : HInst<
21571(outs IntRegs:$Rx32),
21572(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21573"memh($Rx32++I:circ($Mu2)) = $Nt8.new",
21574tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21575let Inst{7-0} = 0b00000010;
21576let Inst{12-11} = 0b01;
21577let Inst{31-21} = 0b10101001101;
21578let addrMode = PostInc;
21579let accessSize = HalfWordAccess;
21580let isNVStore = 1;
21581let isNewValue = 1;
21582let isRestrictNoSlot1Store = 1;
21583let mayStore = 1;
21584let Uses = [CS];
21585let BaseOpcode = "S2_storerh_pcr";
21586let opNewValue = 3;
21587let Constraints = "$Rx32 = $Rx32in";
21588}
21589def S2_storerhnew_pi : HInst<
21590(outs IntRegs:$Rx32),
21591(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
21592"memh($Rx32++#$Ii) = $Nt8.new",
21593tc_92240447, TypeST>, Enc_e26546, AddrModeRel {
21594let Inst{2-0} = 0b000;
21595let Inst{7-7} = 0b0;
21596let Inst{13-11} = 0b001;
21597let Inst{31-21} = 0b10101011101;
21598let addrMode = PostInc;
21599let accessSize = HalfWordAccess;
21600let isNVStore = 1;
21601let isNewValue = 1;
21602let isRestrictNoSlot1Store = 1;
21603let mayStore = 1;
21604let BaseOpcode = "S2_storerh_pi";
21605let isNVStorable = 1;
21606let isPredicable = 1;
21607let opNewValue = 3;
21608let Constraints = "$Rx32 = $Rx32in";
21609}
21610def S2_storerhnew_pr : HInst<
21611(outs IntRegs:$Rx32),
21612(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21613"memh($Rx32++$Mu2) = $Nt8.new",
21614tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21615let Inst{7-0} = 0b00000000;
21616let Inst{12-11} = 0b01;
21617let Inst{31-21} = 0b10101101101;
21618let addrMode = PostInc;
21619let accessSize = HalfWordAccess;
21620let isNVStore = 1;
21621let isNewValue = 1;
21622let isRestrictNoSlot1Store = 1;
21623let mayStore = 1;
21624let BaseOpcode = "S2_storerh_pr";
21625let opNewValue = 3;
21626let Constraints = "$Rx32 = $Rx32in";
21627}
21628def S2_storerhnew_zomap : HInst<
21629(outs),
21630(ins IntRegs:$Rs32, IntRegs:$Nt8),
21631"memh($Rs32) = $Nt8.new",
21632tc_5deb5e47, TypeMAPPING> {
21633let isPseudo = 1;
21634let isCodeGenOnly = 1;
21635let opNewValue = 1;
21636}
21637def S2_storerhnewgp : HInst<
21638(outs),
21639(ins u31_1Imm:$Ii, IntRegs:$Nt8),
21640"memh(gp+#$Ii) = $Nt8.new",
21641tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
21642let Inst{12-11} = 0b01;
21643let Inst{24-21} = 0b0101;
21644let Inst{31-27} = 0b01001;
21645let accessSize = HalfWordAccess;
21646let isNVStore = 1;
21647let isNewValue = 1;
21648let isRestrictNoSlot1Store = 1;
21649let mayStore = 1;
21650let Uses = [GP];
21651let BaseOpcode = "S2_storerhabs";
21652let isPredicable = 1;
21653let opExtendable = 0;
21654let isExtentSigned = 0;
21655let opExtentBits = 17;
21656let opExtentAlign = 1;
21657let opNewValue = 1;
21658}
21659def S2_storeri_io : HInst<
21660(outs),
21661(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
21662"memw($Rs32+#$Ii) = $Rt32",
21663tc_ae5babd7, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
21664let Inst{24-21} = 0b1100;
21665let Inst{31-27} = 0b10100;
21666let addrMode = BaseImmOffset;
21667let accessSize = WordAccess;
21668let mayStore = 1;
21669let BaseOpcode = "S2_storeri_io";
21670let CextOpcode = "S2_storeri";
21671let InputType = "imm";
21672let isNVStorable = 1;
21673let isPredicable = 1;
21674let isExtendable = 1;
21675let opExtendable = 1;
21676let isExtentSigned = 1;
21677let opExtentBits = 13;
21678let opExtentAlign = 2;
21679}
21680def S2_storeri_pbr : HInst<
21681(outs IntRegs:$Rx32),
21682(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21683"memw($Rx32++$Mu2:brev) = $Rt32",
21684tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21685let Inst{7-0} = 0b00000000;
21686let Inst{31-21} = 0b10101111100;
21687let addrMode = PostInc;
21688let accessSize = WordAccess;
21689let mayStore = 1;
21690let BaseOpcode = "S2_storeri_pbr";
21691let isNVStorable = 1;
21692let Constraints = "$Rx32 = $Rx32in";
21693}
21694def S2_storeri_pci : HInst<
21695(outs IntRegs:$Rx32),
21696(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21697"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21698tc_b4dc7630, TypeST>, Enc_79b8c8, AddrModeRel {
21699let Inst{2-0} = 0b000;
21700let Inst{7-7} = 0b0;
21701let Inst{31-21} = 0b10101001100;
21702let addrMode = PostInc;
21703let accessSize = WordAccess;
21704let mayStore = 1;
21705let Uses = [CS];
21706let BaseOpcode = "S2_storeri_pci";
21707let isNVStorable = 1;
21708let Constraints = "$Rx32 = $Rx32in";
21709}
21710def S2_storeri_pcr : HInst<
21711(outs IntRegs:$Rx32),
21712(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21713"memw($Rx32++I:circ($Mu2)) = $Rt32",
21714tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21715let Inst{7-0} = 0b00000010;
21716let Inst{31-21} = 0b10101001100;
21717let addrMode = PostInc;
21718let accessSize = WordAccess;
21719let mayStore = 1;
21720let Uses = [CS];
21721let BaseOpcode = "S2_storeri_pcr";
21722let isNVStorable = 1;
21723let Constraints = "$Rx32 = $Rx32in";
21724}
21725def S2_storeri_pi : HInst<
21726(outs IntRegs:$Rx32),
21727(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
21728"memw($Rx32++#$Ii) = $Rt32",
21729tc_a2b365d2, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
21730let Inst{2-0} = 0b000;
21731let Inst{7-7} = 0b0;
21732let Inst{13-13} = 0b0;
21733let Inst{31-21} = 0b10101011100;
21734let addrMode = PostInc;
21735let accessSize = WordAccess;
21736let mayStore = 1;
21737let BaseOpcode = "S2_storeri_pi";
21738let CextOpcode = "S2_storeri";
21739let isNVStorable = 1;
21740let isPredicable = 1;
21741let Constraints = "$Rx32 = $Rx32in";
21742}
21743def S2_storeri_pr : HInst<
21744(outs IntRegs:$Rx32),
21745(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21746"memw($Rx32++$Mu2) = $Rt32",
21747tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21748let Inst{7-0} = 0b00000000;
21749let Inst{31-21} = 0b10101101100;
21750let addrMode = PostInc;
21751let accessSize = WordAccess;
21752let mayStore = 1;
21753let BaseOpcode = "S2_storeri_pr";
21754let isNVStorable = 1;
21755let Constraints = "$Rx32 = $Rx32in";
21756}
21757def S2_storeri_zomap : HInst<
21758(outs),
21759(ins IntRegs:$Rs32, IntRegs:$Rt32),
21760"memw($Rs32) = $Rt32",
21761tc_ae5babd7, TypeMAPPING> {
21762let isPseudo = 1;
21763let isCodeGenOnly = 1;
21764}
21765def S2_storerigp : HInst<
21766(outs),
21767(ins u30_2Imm:$Ii, IntRegs:$Rt32),
21768"memw(gp+#$Ii) = $Rt32",
21769tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
21770let Inst{24-21} = 0b0100;
21771let Inst{31-27} = 0b01001;
21772let accessSize = WordAccess;
21773let mayStore = 1;
21774let Uses = [GP];
21775let BaseOpcode = "S2_storeriabs";
21776let isNVStorable = 1;
21777let isPredicable = 1;
21778let opExtendable = 0;
21779let isExtentSigned = 0;
21780let opExtentBits = 18;
21781let opExtentAlign = 2;
21782}
21783def S2_storerinew_io : HInst<
21784(outs),
21785(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
21786"memw($Rs32+#$Ii) = $Nt8.new",
21787tc_5deb5e47, TypeST>, Enc_690862, AddrModeRel {
21788let Inst{12-11} = 0b10;
21789let Inst{24-21} = 0b1101;
21790let Inst{31-27} = 0b10100;
21791let addrMode = BaseImmOffset;
21792let accessSize = WordAccess;
21793let isNVStore = 1;
21794let isNewValue = 1;
21795let isRestrictNoSlot1Store = 1;
21796let mayStore = 1;
21797let BaseOpcode = "S2_storeri_io";
21798let CextOpcode = "S2_storeri";
21799let InputType = "imm";
21800let isPredicable = 1;
21801let isExtendable = 1;
21802let opExtendable = 1;
21803let isExtentSigned = 1;
21804let opExtentBits = 13;
21805let opExtentAlign = 2;
21806let opNewValue = 2;
21807}
21808def S2_storerinew_pbr : HInst<
21809(outs IntRegs:$Rx32),
21810(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21811"memw($Rx32++$Mu2:brev) = $Nt8.new",
21812tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21813let Inst{7-0} = 0b00000000;
21814let Inst{12-11} = 0b10;
21815let Inst{31-21} = 0b10101111101;
21816let addrMode = PostInc;
21817let accessSize = WordAccess;
21818let isNVStore = 1;
21819let isNewValue = 1;
21820let isRestrictNoSlot1Store = 1;
21821let mayStore = 1;
21822let BaseOpcode = "S2_storeri_pbr";
21823let opNewValue = 3;
21824let Constraints = "$Rx32 = $Rx32in";
21825}
21826def S2_storerinew_pci : HInst<
21827(outs IntRegs:$Rx32),
21828(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21829"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21830tc_addc37a8, TypeST>, Enc_3f97c8, AddrModeRel {
21831let Inst{2-0} = 0b000;
21832let Inst{7-7} = 0b0;
21833let Inst{12-11} = 0b10;
21834let Inst{31-21} = 0b10101001101;
21835let addrMode = PostInc;
21836let accessSize = WordAccess;
21837let isNVStore = 1;
21838let isNewValue = 1;
21839let isRestrictNoSlot1Store = 1;
21840let mayStore = 1;
21841let Uses = [CS];
21842let BaseOpcode = "S2_storeri_pci";
21843let opNewValue = 4;
21844let Constraints = "$Rx32 = $Rx32in";
21845}
21846def S2_storerinew_pcr : HInst<
21847(outs IntRegs:$Rx32),
21848(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21849"memw($Rx32++I:circ($Mu2)) = $Nt8.new",
21850tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21851let Inst{7-0} = 0b00000010;
21852let Inst{12-11} = 0b10;
21853let Inst{31-21} = 0b10101001101;
21854let addrMode = PostInc;
21855let accessSize = WordAccess;
21856let isNVStore = 1;
21857let isNewValue = 1;
21858let isRestrictNoSlot1Store = 1;
21859let mayStore = 1;
21860let Uses = [CS];
21861let BaseOpcode = "S2_storeri_pcr";
21862let opNewValue = 3;
21863let Constraints = "$Rx32 = $Rx32in";
21864}
21865def S2_storerinew_pi : HInst<
21866(outs IntRegs:$Rx32),
21867(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
21868"memw($Rx32++#$Ii) = $Nt8.new",
21869tc_92240447, TypeST>, Enc_223005, AddrModeRel {
21870let Inst{2-0} = 0b000;
21871let Inst{7-7} = 0b0;
21872let Inst{13-11} = 0b010;
21873let Inst{31-21} = 0b10101011101;
21874let addrMode = PostInc;
21875let accessSize = WordAccess;
21876let isNVStore = 1;
21877let isNewValue = 1;
21878let isRestrictNoSlot1Store = 1;
21879let mayStore = 1;
21880let BaseOpcode = "S2_storeri_pi";
21881let isPredicable = 1;
21882let opNewValue = 3;
21883let Constraints = "$Rx32 = $Rx32in";
21884}
21885def S2_storerinew_pr : HInst<
21886(outs IntRegs:$Rx32),
21887(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21888"memw($Rx32++$Mu2) = $Nt8.new",
21889tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21890let Inst{7-0} = 0b00000000;
21891let Inst{12-11} = 0b10;
21892let Inst{31-21} = 0b10101101101;
21893let addrMode = PostInc;
21894let accessSize = WordAccess;
21895let isNVStore = 1;
21896let isNewValue = 1;
21897let isRestrictNoSlot1Store = 1;
21898let mayStore = 1;
21899let BaseOpcode = "S2_storeri_pr";
21900let opNewValue = 3;
21901let Constraints = "$Rx32 = $Rx32in";
21902}
21903def S2_storerinew_zomap : HInst<
21904(outs),
21905(ins IntRegs:$Rs32, IntRegs:$Nt8),
21906"memw($Rs32) = $Nt8.new",
21907tc_5deb5e47, TypeMAPPING> {
21908let isPseudo = 1;
21909let isCodeGenOnly = 1;
21910let opNewValue = 1;
21911}
21912def S2_storerinewgp : HInst<
21913(outs),
21914(ins u30_2Imm:$Ii, IntRegs:$Nt8),
21915"memw(gp+#$Ii) = $Nt8.new",
21916tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
21917let Inst{12-11} = 0b10;
21918let Inst{24-21} = 0b0101;
21919let Inst{31-27} = 0b01001;
21920let accessSize = WordAccess;
21921let isNVStore = 1;
21922let isNewValue = 1;
21923let isRestrictNoSlot1Store = 1;
21924let mayStore = 1;
21925let Uses = [GP];
21926let BaseOpcode = "S2_storeriabs";
21927let isPredicable = 1;
21928let opExtendable = 0;
21929let isExtentSigned = 0;
21930let opExtentBits = 18;
21931let opExtentAlign = 2;
21932let opNewValue = 1;
21933}
21934def S2_storew_locked : HInst<
21935(outs PredRegs:$Pd4),
21936(ins IntRegs:$Rs32, IntRegs:$Rt32),
21937"memw_locked($Rs32,$Pd4) = $Rt32",
21938tc_6f42bc60, TypeST>, Enc_c2b48e {
21939let Inst{7-2} = 0b000000;
21940let Inst{13-13} = 0b0;
21941let Inst{31-21} = 0b10100000101;
21942let accessSize = WordAccess;
21943let isPredicateLate = 1;
21944let isSoloAX = 1;
21945let mayStore = 1;
21946}
21947def S2_storew_rl_at_vi : HInst<
21948(outs),
21949(ins IntRegs:$Rs32, IntRegs:$Rt32),
21950"memw_rl($Rs32):at = $Rt32",
21951tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
21952let Inst{7-2} = 0b000010;
21953let Inst{13-13} = 0b0;
21954let Inst{31-21} = 0b10100000101;
21955let accessSize = WordAccess;
21956let isSolo = 1;
21957let mayStore = 1;
21958}
21959def S2_storew_rl_st_vi : HInst<
21960(outs),
21961(ins IntRegs:$Rs32, IntRegs:$Rt32),
21962"memw_rl($Rs32):st = $Rt32",
21963tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
21964let Inst{7-2} = 0b001010;
21965let Inst{13-13} = 0b0;
21966let Inst{31-21} = 0b10100000101;
21967let accessSize = WordAccess;
21968let isSolo = 1;
21969let mayStore = 1;
21970}
21971def S2_svsathb : HInst<
21972(outs IntRegs:$Rd32),
21973(ins IntRegs:$Rs32),
21974"$Rd32 = vsathb($Rs32)",
21975tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
21976let Inst{13-5} = 0b000000000;
21977let Inst{31-21} = 0b10001100100;
21978let hasNewValue = 1;
21979let opNewValue = 0;
21980let Defs = [USR_OVF];
21981}
21982def S2_svsathub : HInst<
21983(outs IntRegs:$Rd32),
21984(ins IntRegs:$Rs32),
21985"$Rd32 = vsathub($Rs32)",
21986tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
21987let Inst{13-5} = 0b000000010;
21988let Inst{31-21} = 0b10001100100;
21989let hasNewValue = 1;
21990let opNewValue = 0;
21991let Defs = [USR_OVF];
21992}
21993def S2_tableidxb : HInst<
21994(outs IntRegs:$Rx32),
21995(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21996"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
21997tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
21998let Inst{31-22} = 0b1000011100;
21999let hasNewValue = 1;
22000let opNewValue = 0;
22001let prefersSlot3 = 1;
22002let Constraints = "$Rx32 = $Rx32in";
22003}
22004def S2_tableidxb_goodsyntax : HInst<
22005(outs IntRegs:$Rx32),
22006(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22007"$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
22008tc_bb831a7c, TypeS_2op> {
22009let hasNewValue = 1;
22010let opNewValue = 0;
22011let isPseudo = 1;
22012let isCodeGenOnly = 1;
22013let Constraints = "$Rx32 = $Rx32in";
22014}
22015def S2_tableidxd : HInst<
22016(outs IntRegs:$Rx32),
22017(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22018"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
22019tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22020let Inst{31-22} = 0b1000011111;
22021let hasNewValue = 1;
22022let opNewValue = 0;
22023let prefersSlot3 = 1;
22024let Constraints = "$Rx32 = $Rx32in";
22025}
22026def S2_tableidxd_goodsyntax : HInst<
22027(outs IntRegs:$Rx32),
22028(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22029"$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
22030tc_bb831a7c, TypeS_2op> {
22031let hasNewValue = 1;
22032let opNewValue = 0;
22033let isPseudo = 1;
22034let Constraints = "$Rx32 = $Rx32in";
22035}
22036def S2_tableidxh : HInst<
22037(outs IntRegs:$Rx32),
22038(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22039"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
22040tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22041let Inst{31-22} = 0b1000011101;
22042let hasNewValue = 1;
22043let opNewValue = 0;
22044let prefersSlot3 = 1;
22045let Constraints = "$Rx32 = $Rx32in";
22046}
22047def S2_tableidxh_goodsyntax : HInst<
22048(outs IntRegs:$Rx32),
22049(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22050"$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
22051tc_bb831a7c, TypeS_2op> {
22052let hasNewValue = 1;
22053let opNewValue = 0;
22054let isPseudo = 1;
22055let Constraints = "$Rx32 = $Rx32in";
22056}
22057def S2_tableidxw : HInst<
22058(outs IntRegs:$Rx32),
22059(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22060"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
22061tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22062let Inst{31-22} = 0b1000011110;
22063let hasNewValue = 1;
22064let opNewValue = 0;
22065let prefersSlot3 = 1;
22066let Constraints = "$Rx32 = $Rx32in";
22067}
22068def S2_tableidxw_goodsyntax : HInst<
22069(outs IntRegs:$Rx32),
22070(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22071"$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
22072tc_bb831a7c, TypeS_2op> {
22073let hasNewValue = 1;
22074let opNewValue = 0;
22075let isPseudo = 1;
22076let Constraints = "$Rx32 = $Rx32in";
22077}
22078def S2_togglebit_i : HInst<
22079(outs IntRegs:$Rd32),
22080(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22081"$Rd32 = togglebit($Rs32,#$Ii)",
22082tc_5da50c4b, TypeS_2op>, Enc_a05677 {
22083let Inst{7-5} = 0b010;
22084let Inst{13-13} = 0b0;
22085let Inst{31-21} = 0b10001100110;
22086let hasNewValue = 1;
22087let opNewValue = 0;
22088}
22089def S2_togglebit_r : HInst<
22090(outs IntRegs:$Rd32),
22091(ins IntRegs:$Rs32, IntRegs:$Rt32),
22092"$Rd32 = togglebit($Rs32,$Rt32)",
22093tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
22094let Inst{7-5} = 0b100;
22095let Inst{13-13} = 0b0;
22096let Inst{31-21} = 0b11000110100;
22097let hasNewValue = 1;
22098let opNewValue = 0;
22099}
22100def S2_tstbit_i : HInst<
22101(outs PredRegs:$Pd4),
22102(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22103"$Pd4 = tstbit($Rs32,#$Ii)",
22104tc_a1297125, TypeS_2op>, Enc_83ee64 {
22105let Inst{7-2} = 0b000000;
22106let Inst{13-13} = 0b0;
22107let Inst{31-21} = 0b10000101000;
22108}
22109def S2_tstbit_r : HInst<
22110(outs PredRegs:$Pd4),
22111(ins IntRegs:$Rs32, IntRegs:$Rt32),
22112"$Pd4 = tstbit($Rs32,$Rt32)",
22113tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22114let Inst{7-2} = 0b000000;
22115let Inst{13-13} = 0b0;
22116let Inst{31-21} = 0b11000111000;
22117}
22118def S2_valignib : HInst<
22119(outs DoubleRegs:$Rdd32),
22120(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
22121"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
22122tc_6fc5dbea, TypeS_3op>, Enc_729ff7 {
22123let Inst{13-13} = 0b0;
22124let Inst{31-21} = 0b11000000000;
22125}
22126def S2_valignrb : HInst<
22127(outs DoubleRegs:$Rdd32),
22128(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
22129"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
22130tc_6fc5dbea, TypeS_3op>, Enc_8c6530 {
22131let Inst{7-7} = 0b0;
22132let Inst{13-13} = 0b0;
22133let Inst{31-21} = 0b11000010000;
22134}
22135def S2_vcnegh : HInst<
22136(outs DoubleRegs:$Rdd32),
22137(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22138"$Rdd32 = vcnegh($Rss32,$Rt32)",
22139tc_8a825db2, TypeS_3op>, Enc_927852 {
22140let Inst{7-5} = 0b010;
22141let Inst{13-13} = 0b0;
22142let Inst{31-21} = 0b11000011110;
22143let prefersSlot3 = 1;
22144let Defs = [USR_OVF];
22145}
22146def S2_vcrotate : HInst<
22147(outs DoubleRegs:$Rdd32),
22148(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22149"$Rdd32 = vcrotate($Rss32,$Rt32)",
22150tc_0dfac0a7, TypeS_3op>, Enc_927852 {
22151let Inst{7-5} = 0b000;
22152let Inst{13-13} = 0b0;
22153let Inst{31-21} = 0b11000011110;
22154let prefersSlot3 = 1;
22155let Defs = [USR_OVF];
22156}
22157def S2_vrcnegh : HInst<
22158(outs DoubleRegs:$Rxx32),
22159(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
22160"$Rxx32 += vrcnegh($Rss32,$Rt32)",
22161tc_7f8ae742, TypeS_3op>, Enc_1aa186 {
22162let Inst{7-5} = 0b111;
22163let Inst{13-13} = 0b1;
22164let Inst{31-21} = 0b11001011001;
22165let prefersSlot3 = 1;
22166let Constraints = "$Rxx32 = $Rxx32in";
22167}
22168def S2_vrndpackwh : HInst<
22169(outs IntRegs:$Rd32),
22170(ins DoubleRegs:$Rss32),
22171"$Rd32 = vrndwh($Rss32)",
22172tc_e3d699e3, TypeS_2op>, Enc_90cd8b {
22173let Inst{13-5} = 0b000000100;
22174let Inst{31-21} = 0b10001000100;
22175let hasNewValue = 1;
22176let opNewValue = 0;
22177let prefersSlot3 = 1;
22178}
22179def S2_vrndpackwhs : HInst<
22180(outs IntRegs:$Rd32),
22181(ins DoubleRegs:$Rss32),
22182"$Rd32 = vrndwh($Rss32):sat",
22183tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
22184let Inst{13-5} = 0b000000110;
22185let Inst{31-21} = 0b10001000100;
22186let hasNewValue = 1;
22187let opNewValue = 0;
22188let prefersSlot3 = 1;
22189let Defs = [USR_OVF];
22190}
22191def S2_vsathb : HInst<
22192(outs IntRegs:$Rd32),
22193(ins DoubleRegs:$Rss32),
22194"$Rd32 = vsathb($Rss32)",
22195tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22196let Inst{13-5} = 0b000000110;
22197let Inst{31-21} = 0b10001000000;
22198let hasNewValue = 1;
22199let opNewValue = 0;
22200let Defs = [USR_OVF];
22201}
22202def S2_vsathb_nopack : HInst<
22203(outs DoubleRegs:$Rdd32),
22204(ins DoubleRegs:$Rss32),
22205"$Rdd32 = vsathb($Rss32)",
22206tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22207let Inst{13-5} = 0b000000111;
22208let Inst{31-21} = 0b10000000000;
22209let Defs = [USR_OVF];
22210}
22211def S2_vsathub : HInst<
22212(outs IntRegs:$Rd32),
22213(ins DoubleRegs:$Rss32),
22214"$Rd32 = vsathub($Rss32)",
22215tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22216let Inst{13-5} = 0b000000000;
22217let Inst{31-21} = 0b10001000000;
22218let hasNewValue = 1;
22219let opNewValue = 0;
22220let Defs = [USR_OVF];
22221}
22222def S2_vsathub_nopack : HInst<
22223(outs DoubleRegs:$Rdd32),
22224(ins DoubleRegs:$Rss32),
22225"$Rdd32 = vsathub($Rss32)",
22226tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22227let Inst{13-5} = 0b000000100;
22228let Inst{31-21} = 0b10000000000;
22229let Defs = [USR_OVF];
22230}
22231def S2_vsatwh : HInst<
22232(outs IntRegs:$Rd32),
22233(ins DoubleRegs:$Rss32),
22234"$Rd32 = vsatwh($Rss32)",
22235tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22236let Inst{13-5} = 0b000000010;
22237let Inst{31-21} = 0b10001000000;
22238let hasNewValue = 1;
22239let opNewValue = 0;
22240let Defs = [USR_OVF];
22241}
22242def S2_vsatwh_nopack : HInst<
22243(outs DoubleRegs:$Rdd32),
22244(ins DoubleRegs:$Rss32),
22245"$Rdd32 = vsatwh($Rss32)",
22246tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22247let Inst{13-5} = 0b000000110;
22248let Inst{31-21} = 0b10000000000;
22249let Defs = [USR_OVF];
22250}
22251def S2_vsatwuh : HInst<
22252(outs IntRegs:$Rd32),
22253(ins DoubleRegs:$Rss32),
22254"$Rd32 = vsatwuh($Rss32)",
22255tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22256let Inst{13-5} = 0b000000100;
22257let Inst{31-21} = 0b10001000000;
22258let hasNewValue = 1;
22259let opNewValue = 0;
22260let Defs = [USR_OVF];
22261}
22262def S2_vsatwuh_nopack : HInst<
22263(outs DoubleRegs:$Rdd32),
22264(ins DoubleRegs:$Rss32),
22265"$Rdd32 = vsatwuh($Rss32)",
22266tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22267let Inst{13-5} = 0b000000101;
22268let Inst{31-21} = 0b10000000000;
22269let Defs = [USR_OVF];
22270}
22271def S2_vsplatrb : HInst<
22272(outs IntRegs:$Rd32),
22273(ins IntRegs:$Rs32),
22274"$Rd32 = vsplatb($Rs32)",
22275tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22276let Inst{13-5} = 0b000000111;
22277let Inst{31-21} = 0b10001100010;
22278let hasNewValue = 1;
22279let opNewValue = 0;
22280let isAsCheapAsAMove = 1;
22281let isReMaterializable = 1;
22282}
22283def S2_vsplatrh : HInst<
22284(outs DoubleRegs:$Rdd32),
22285(ins IntRegs:$Rs32),
22286"$Rdd32 = vsplath($Rs32)",
22287tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22288let Inst{13-5} = 0b000000010;
22289let Inst{31-21} = 0b10000100010;
22290let isAsCheapAsAMove = 1;
22291let isReMaterializable = 1;
22292}
22293def S2_vspliceib : HInst<
22294(outs DoubleRegs:$Rdd32),
22295(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
22296"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
22297tc_6fc5dbea, TypeS_3op>, Enc_d50cd3 {
22298let Inst{13-13} = 0b0;
22299let Inst{31-21} = 0b11000000100;
22300}
22301def S2_vsplicerb : HInst<
22302(outs DoubleRegs:$Rdd32),
22303(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
22304"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
22305tc_6fc5dbea, TypeS_3op>, Enc_dbd70c {
22306let Inst{7-7} = 0b0;
22307let Inst{13-13} = 0b0;
22308let Inst{31-21} = 0b11000010100;
22309}
22310def S2_vsxtbh : HInst<
22311(outs DoubleRegs:$Rdd32),
22312(ins IntRegs:$Rs32),
22313"$Rdd32 = vsxtbh($Rs32)",
22314tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22315let Inst{13-5} = 0b000000000;
22316let Inst{31-21} = 0b10000100000;
22317let isAsCheapAsAMove = 1;
22318let isReMaterializable = 1;
22319}
22320def S2_vsxthw : HInst<
22321(outs DoubleRegs:$Rdd32),
22322(ins IntRegs:$Rs32),
22323"$Rdd32 = vsxthw($Rs32)",
22324tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22325let Inst{13-5} = 0b000000100;
22326let Inst{31-21} = 0b10000100000;
22327let isAsCheapAsAMove = 1;
22328let isReMaterializable = 1;
22329}
22330def S2_vtrunehb : HInst<
22331(outs IntRegs:$Rd32),
22332(ins DoubleRegs:$Rss32),
22333"$Rd32 = vtrunehb($Rss32)",
22334tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22335let Inst{13-5} = 0b000000010;
22336let Inst{31-21} = 0b10001000100;
22337let hasNewValue = 1;
22338let opNewValue = 0;
22339}
22340def S2_vtrunewh : HInst<
22341(outs DoubleRegs:$Rdd32),
22342(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22343"$Rdd32 = vtrunewh($Rss32,$Rtt32)",
22344tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22345let Inst{7-5} = 0b010;
22346let Inst{13-13} = 0b0;
22347let Inst{31-21} = 0b11000001100;
22348}
22349def S2_vtrunohb : HInst<
22350(outs IntRegs:$Rd32),
22351(ins DoubleRegs:$Rss32),
22352"$Rd32 = vtrunohb($Rss32)",
22353tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22354let Inst{13-5} = 0b000000000;
22355let Inst{31-21} = 0b10001000100;
22356let hasNewValue = 1;
22357let opNewValue = 0;
22358}
22359def S2_vtrunowh : HInst<
22360(outs DoubleRegs:$Rdd32),
22361(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22362"$Rdd32 = vtrunowh($Rss32,$Rtt32)",
22363tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22364let Inst{7-5} = 0b100;
22365let Inst{13-13} = 0b0;
22366let Inst{31-21} = 0b11000001100;
22367}
22368def S2_vzxtbh : HInst<
22369(outs DoubleRegs:$Rdd32),
22370(ins IntRegs:$Rs32),
22371"$Rdd32 = vzxtbh($Rs32)",
22372tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22373let Inst{13-5} = 0b000000010;
22374let Inst{31-21} = 0b10000100000;
22375let isAsCheapAsAMove = 1;
22376let isReMaterializable = 1;
22377}
22378def S2_vzxthw : HInst<
22379(outs DoubleRegs:$Rdd32),
22380(ins IntRegs:$Rs32),
22381"$Rdd32 = vzxthw($Rs32)",
22382tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22383let Inst{13-5} = 0b000000110;
22384let Inst{31-21} = 0b10000100000;
22385let isAsCheapAsAMove = 1;
22386let isReMaterializable = 1;
22387}
22388def S4_addaddi : HInst<
22389(outs IntRegs:$Rd32),
22390(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
22391"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
22392tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
22393let Inst{31-23} = 0b110110110;
22394let hasNewValue = 1;
22395let opNewValue = 0;
22396let prefersSlot3 = 1;
22397let isExtendable = 1;
22398let opExtendable = 3;
22399let isExtentSigned = 1;
22400let opExtentBits = 6;
22401let opExtentAlign = 0;
22402}
22403def S4_addi_asl_ri : HInst<
22404(outs IntRegs:$Rx32),
22405(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22406"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
22407tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22408let Inst{2-0} = 0b100;
22409let Inst{4-4} = 0b0;
22410let Inst{31-24} = 0b11011110;
22411let hasNewValue = 1;
22412let opNewValue = 0;
22413let prefersSlot3 = 1;
22414let isExtendable = 1;
22415let opExtendable = 1;
22416let isExtentSigned = 0;
22417let opExtentBits = 8;
22418let opExtentAlign = 0;
22419let Constraints = "$Rx32 = $Rx32in";
22420}
22421def S4_addi_lsr_ri : HInst<
22422(outs IntRegs:$Rx32),
22423(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22424"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
22425tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22426let Inst{2-0} = 0b100;
22427let Inst{4-4} = 0b1;
22428let Inst{31-24} = 0b11011110;
22429let hasNewValue = 1;
22430let opNewValue = 0;
22431let prefersSlot3 = 1;
22432let isExtendable = 1;
22433let opExtendable = 1;
22434let isExtentSigned = 0;
22435let opExtentBits = 8;
22436let opExtentAlign = 0;
22437let Constraints = "$Rx32 = $Rx32in";
22438}
22439def S4_andi_asl_ri : HInst<
22440(outs IntRegs:$Rx32),
22441(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22442"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
22443tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22444let Inst{2-0} = 0b000;
22445let Inst{4-4} = 0b0;
22446let Inst{31-24} = 0b11011110;
22447let hasNewValue = 1;
22448let opNewValue = 0;
22449let prefersSlot3 = 1;
22450let isExtendable = 1;
22451let opExtendable = 1;
22452let isExtentSigned = 0;
22453let opExtentBits = 8;
22454let opExtentAlign = 0;
22455let Constraints = "$Rx32 = $Rx32in";
22456}
22457def S4_andi_lsr_ri : HInst<
22458(outs IntRegs:$Rx32),
22459(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22460"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
22461tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22462let Inst{2-0} = 0b000;
22463let Inst{4-4} = 0b1;
22464let Inst{31-24} = 0b11011110;
22465let hasNewValue = 1;
22466let opNewValue = 0;
22467let prefersSlot3 = 1;
22468let isExtendable = 1;
22469let opExtendable = 1;
22470let isExtentSigned = 0;
22471let opExtentBits = 8;
22472let opExtentAlign = 0;
22473let Constraints = "$Rx32 = $Rx32in";
22474}
22475def S4_clbaddi : HInst<
22476(outs IntRegs:$Rd32),
22477(ins IntRegs:$Rs32, s6_0Imm:$Ii),
22478"$Rd32 = add(clb($Rs32),#$Ii)",
22479tc_a08b630b, TypeS_2op>, Enc_9fae8a {
22480let Inst{7-5} = 0b000;
22481let Inst{31-21} = 0b10001100001;
22482let hasNewValue = 1;
22483let opNewValue = 0;
22484let prefersSlot3 = 1;
22485}
22486def S4_clbpaddi : HInst<
22487(outs IntRegs:$Rd32),
22488(ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
22489"$Rd32 = add(clb($Rss32),#$Ii)",
22490tc_a08b630b, TypeS_2op>, Enc_a1640c {
22491let Inst{7-5} = 0b010;
22492let Inst{31-21} = 0b10001000011;
22493let hasNewValue = 1;
22494let opNewValue = 0;
22495let prefersSlot3 = 1;
22496}
22497def S4_clbpnorm : HInst<
22498(outs IntRegs:$Rd32),
22499(ins DoubleRegs:$Rss32),
22500"$Rd32 = normamt($Rss32)",
22501tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
22502let Inst{13-5} = 0b000000000;
22503let Inst{31-21} = 0b10001000011;
22504let hasNewValue = 1;
22505let opNewValue = 0;
22506let prefersSlot3 = 1;
22507}
22508def S4_extract : HInst<
22509(outs IntRegs:$Rd32),
22510(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
22511"$Rd32 = extract($Rs32,#$Ii,#$II)",
22512tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
22513let Inst{13-13} = 0b0;
22514let Inst{31-23} = 0b100011011;
22515let hasNewValue = 1;
22516let opNewValue = 0;
22517let prefersSlot3 = 1;
22518}
22519def S4_extract_rp : HInst<
22520(outs IntRegs:$Rd32),
22521(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
22522"$Rd32 = extract($Rs32,$Rtt32)",
22523tc_a08b630b, TypeS_3op>, Enc_e07374 {
22524let Inst{7-5} = 0b010;
22525let Inst{13-13} = 0b0;
22526let Inst{31-21} = 0b11001001000;
22527let hasNewValue = 1;
22528let opNewValue = 0;
22529let prefersSlot3 = 1;
22530}
22531def S4_extractp : HInst<
22532(outs DoubleRegs:$Rdd32),
22533(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
22534"$Rdd32 = extract($Rss32,#$Ii,#$II)",
22535tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
22536let Inst{31-24} = 0b10001010;
22537let prefersSlot3 = 1;
22538}
22539def S4_extractp_rp : HInst<
22540(outs DoubleRegs:$Rdd32),
22541(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22542"$Rdd32 = extract($Rss32,$Rtt32)",
22543tc_a08b630b, TypeS_3op>, Enc_a56825 {
22544let Inst{7-5} = 0b100;
22545let Inst{13-13} = 0b0;
22546let Inst{31-21} = 0b11000001110;
22547let prefersSlot3 = 1;
22548}
22549def S4_lsli : HInst<
22550(outs IntRegs:$Rd32),
22551(ins s6_0Imm:$Ii, IntRegs:$Rt32),
22552"$Rd32 = lsl(#$Ii,$Rt32)",
22553tc_5da50c4b, TypeS_3op>, Enc_fef969 {
22554let Inst{7-6} = 0b11;
22555let Inst{13-13} = 0b0;
22556let Inst{31-21} = 0b11000110100;
22557let hasNewValue = 1;
22558let opNewValue = 0;
22559}
22560def S4_ntstbit_i : HInst<
22561(outs PredRegs:$Pd4),
22562(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22563"$Pd4 = !tstbit($Rs32,#$Ii)",
22564tc_a1297125, TypeS_2op>, Enc_83ee64 {
22565let Inst{7-2} = 0b000000;
22566let Inst{13-13} = 0b0;
22567let Inst{31-21} = 0b10000101001;
22568}
22569def S4_ntstbit_r : HInst<
22570(outs PredRegs:$Pd4),
22571(ins IntRegs:$Rs32, IntRegs:$Rt32),
22572"$Pd4 = !tstbit($Rs32,$Rt32)",
22573tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22574let Inst{7-2} = 0b000000;
22575let Inst{13-13} = 0b0;
22576let Inst{31-21} = 0b11000111001;
22577}
22578def S4_or_andi : HInst<
22579(outs IntRegs:$Rx32),
22580(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22581"$Rx32 |= and($Rs32,#$Ii)",
22582tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22583let Inst{31-22} = 0b1101101000;
22584let hasNewValue = 1;
22585let opNewValue = 0;
22586let prefersSlot3 = 1;
22587let InputType = "imm";
22588let isExtendable = 1;
22589let opExtendable = 3;
22590let isExtentSigned = 1;
22591let opExtentBits = 10;
22592let opExtentAlign = 0;
22593let Constraints = "$Rx32 = $Rx32in";
22594}
22595def S4_or_andix : HInst<
22596(outs IntRegs:$Rx32),
22597(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
22598"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22599tc_a4e22bbd, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> {
22600let Inst{31-22} = 0b1101101001;
22601let hasNewValue = 1;
22602let opNewValue = 0;
22603let prefersSlot3 = 1;
22604let isExtendable = 1;
22605let opExtendable = 3;
22606let isExtentSigned = 1;
22607let opExtentBits = 10;
22608let opExtentAlign = 0;
22609let Constraints = "$Rx32 = $Rx32in";
22610}
22611def S4_or_ori : HInst<
22612(outs IntRegs:$Rx32),
22613(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22614"$Rx32 |= or($Rs32,#$Ii)",
22615tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22616let Inst{31-22} = 0b1101101010;
22617let hasNewValue = 1;
22618let opNewValue = 0;
22619let prefersSlot3 = 1;
22620let InputType = "imm";
22621let isExtendable = 1;
22622let opExtendable = 3;
22623let isExtentSigned = 1;
22624let opExtentBits = 10;
22625let opExtentAlign = 0;
22626let Constraints = "$Rx32 = $Rx32in";
22627}
22628def S4_ori_asl_ri : HInst<
22629(outs IntRegs:$Rx32),
22630(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22631"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22632tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22633let Inst{2-0} = 0b010;
22634let Inst{4-4} = 0b0;
22635let Inst{31-24} = 0b11011110;
22636let hasNewValue = 1;
22637let opNewValue = 0;
22638let prefersSlot3 = 1;
22639let isExtendable = 1;
22640let opExtendable = 1;
22641let isExtentSigned = 0;
22642let opExtentBits = 8;
22643let opExtentAlign = 0;
22644let Constraints = "$Rx32 = $Rx32in";
22645}
22646def S4_ori_lsr_ri : HInst<
22647(outs IntRegs:$Rx32),
22648(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22649"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22650tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22651let Inst{2-0} = 0b010;
22652let Inst{4-4} = 0b1;
22653let Inst{31-24} = 0b11011110;
22654let hasNewValue = 1;
22655let opNewValue = 0;
22656let prefersSlot3 = 1;
22657let isExtendable = 1;
22658let opExtendable = 1;
22659let isExtentSigned = 0;
22660let opExtentBits = 8;
22661let opExtentAlign = 0;
22662let Constraints = "$Rx32 = $Rx32in";
22663}
22664def S4_parity : HInst<
22665(outs IntRegs:$Rd32),
22666(ins IntRegs:$Rs32, IntRegs:$Rt32),
22667"$Rd32 = parity($Rs32,$Rt32)",
22668tc_a08b630b, TypeALU64>, Enc_5ab2be {
22669let Inst{7-5} = 0b000;
22670let Inst{13-13} = 0b0;
22671let Inst{31-21} = 0b11010101111;
22672let hasNewValue = 1;
22673let opNewValue = 0;
22674let prefersSlot3 = 1;
22675}
22676def S4_pstorerbf_abs : HInst<
22677(outs),
22678(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22679"if (!$Pv4) memb(#$Ii) = $Rt32",
22680tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
22681let Inst{2-2} = 0b1;
22682let Inst{7-7} = 0b1;
22683let Inst{13-13} = 0b0;
22684let Inst{31-18} = 0b10101111000000;
22685let isPredicated = 1;
22686let isPredicatedFalse = 1;
22687let addrMode = Absolute;
22688let accessSize = ByteAccess;
22689let isExtended = 1;
22690let mayStore = 1;
22691let BaseOpcode = "S2_storerbabs";
22692let CextOpcode = "S2_storerb";
22693let isNVStorable = 1;
22694let DecoderNamespace = "MustExtend";
22695let isExtendable = 1;
22696let opExtendable = 1;
22697let isExtentSigned = 0;
22698let opExtentBits = 6;
22699let opExtentAlign = 0;
22700}
22701def S4_pstorerbf_rr : HInst<
22702(outs),
22703(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22704"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22705tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
22706let Inst{31-21} = 0b00110101000;
22707let isPredicated = 1;
22708let isPredicatedFalse = 1;
22709let addrMode = BaseRegOffset;
22710let accessSize = ByteAccess;
22711let mayStore = 1;
22712let BaseOpcode = "S4_storerb_rr";
22713let CextOpcode = "S2_storerb";
22714let InputType = "reg";
22715let isNVStorable = 1;
22716}
22717def S4_pstorerbfnew_abs : HInst<
22718(outs),
22719(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22720"if (!$Pv4.new) memb(#$Ii) = $Rt32",
22721tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
22722let Inst{2-2} = 0b1;
22723let Inst{7-7} = 0b1;
22724let Inst{13-13} = 0b1;
22725let Inst{31-18} = 0b10101111000000;
22726let isPredicated = 1;
22727let isPredicatedFalse = 1;
22728let addrMode = Absolute;
22729let accessSize = ByteAccess;
22730let isPredicatedNew = 1;
22731let isExtended = 1;
22732let mayStore = 1;
22733let BaseOpcode = "S2_storerbabs";
22734let CextOpcode = "S2_storerb";
22735let isNVStorable = 1;
22736let DecoderNamespace = "MustExtend";
22737let isExtendable = 1;
22738let opExtendable = 1;
22739let isExtentSigned = 0;
22740let opExtentBits = 6;
22741let opExtentAlign = 0;
22742}
22743def S4_pstorerbfnew_io : HInst<
22744(outs),
22745(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22746"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22747tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22748let Inst{2-2} = 0b0;
22749let Inst{31-21} = 0b01000110000;
22750let isPredicated = 1;
22751let isPredicatedFalse = 1;
22752let addrMode = BaseImmOffset;
22753let accessSize = ByteAccess;
22754let isPredicatedNew = 1;
22755let mayStore = 1;
22756let BaseOpcode = "S2_storerb_io";
22757let CextOpcode = "S2_storerb";
22758let InputType = "imm";
22759let isNVStorable = 1;
22760let isExtendable = 1;
22761let opExtendable = 2;
22762let isExtentSigned = 0;
22763let opExtentBits = 6;
22764let opExtentAlign = 0;
22765}
22766def S4_pstorerbfnew_rr : HInst<
22767(outs),
22768(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22769"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22770tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
22771let Inst{31-21} = 0b00110111000;
22772let isPredicated = 1;
22773let isPredicatedFalse = 1;
22774let addrMode = BaseRegOffset;
22775let accessSize = ByteAccess;
22776let isPredicatedNew = 1;
22777let mayStore = 1;
22778let BaseOpcode = "S4_storerb_rr";
22779let CextOpcode = "S2_storerb";
22780let InputType = "reg";
22781let isNVStorable = 1;
22782}
22783def S4_pstorerbfnew_zomap : HInst<
22784(outs),
22785(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22786"if (!$Pv4.new) memb($Rs32) = $Rt32",
22787tc_a2b365d2, TypeMAPPING> {
22788let isPseudo = 1;
22789let isCodeGenOnly = 1;
22790}
22791def S4_pstorerbnewf_abs : HInst<
22792(outs),
22793(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22794"if (!$Pv4) memb(#$Ii) = $Nt8.new",
22795tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22796let Inst{2-2} = 0b1;
22797let Inst{7-7} = 0b1;
22798let Inst{13-11} = 0b000;
22799let Inst{31-18} = 0b10101111101000;
22800let isPredicated = 1;
22801let isPredicatedFalse = 1;
22802let addrMode = Absolute;
22803let accessSize = ByteAccess;
22804let isNVStore = 1;
22805let isNewValue = 1;
22806let isExtended = 1;
22807let isRestrictNoSlot1Store = 1;
22808let mayStore = 1;
22809let BaseOpcode = "S2_storerbabs";
22810let CextOpcode = "S2_storerb";
22811let DecoderNamespace = "MustExtend";
22812let isExtendable = 1;
22813let opExtendable = 1;
22814let isExtentSigned = 0;
22815let opExtentBits = 6;
22816let opExtentAlign = 0;
22817let opNewValue = 2;
22818}
22819def S4_pstorerbnewf_rr : HInst<
22820(outs),
22821(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22822"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22823tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22824let Inst{4-3} = 0b00;
22825let Inst{31-21} = 0b00110101101;
22826let isPredicated = 1;
22827let isPredicatedFalse = 1;
22828let addrMode = BaseRegOffset;
22829let accessSize = ByteAccess;
22830let isNVStore = 1;
22831let isNewValue = 1;
22832let isRestrictNoSlot1Store = 1;
22833let mayStore = 1;
22834let BaseOpcode = "S4_storerb_rr";
22835let CextOpcode = "S2_storerb";
22836let InputType = "reg";
22837let opNewValue = 4;
22838}
22839def S4_pstorerbnewfnew_abs : HInst<
22840(outs),
22841(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22842"if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
22843tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22844let Inst{2-2} = 0b1;
22845let Inst{7-7} = 0b1;
22846let Inst{13-11} = 0b100;
22847let Inst{31-18} = 0b10101111101000;
22848let isPredicated = 1;
22849let isPredicatedFalse = 1;
22850let addrMode = Absolute;
22851let accessSize = ByteAccess;
22852let isNVStore = 1;
22853let isPredicatedNew = 1;
22854let isNewValue = 1;
22855let isExtended = 1;
22856let isRestrictNoSlot1Store = 1;
22857let mayStore = 1;
22858let BaseOpcode = "S2_storerbabs";
22859let CextOpcode = "S2_storerb";
22860let DecoderNamespace = "MustExtend";
22861let isExtendable = 1;
22862let opExtendable = 1;
22863let isExtentSigned = 0;
22864let opExtentBits = 6;
22865let opExtentAlign = 0;
22866let opNewValue = 2;
22867}
22868def S4_pstorerbnewfnew_io : HInst<
22869(outs),
22870(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22871"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22872tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
22873let Inst{2-2} = 0b0;
22874let Inst{12-11} = 0b00;
22875let Inst{31-21} = 0b01000110101;
22876let isPredicated = 1;
22877let isPredicatedFalse = 1;
22878let addrMode = BaseImmOffset;
22879let accessSize = ByteAccess;
22880let isNVStore = 1;
22881let isPredicatedNew = 1;
22882let isNewValue = 1;
22883let isRestrictNoSlot1Store = 1;
22884let mayStore = 1;
22885let BaseOpcode = "S2_storerb_io";
22886let CextOpcode = "S2_storerb";
22887let InputType = "imm";
22888let isExtendable = 1;
22889let opExtendable = 2;
22890let isExtentSigned = 0;
22891let opExtentBits = 6;
22892let opExtentAlign = 0;
22893let opNewValue = 3;
22894}
22895def S4_pstorerbnewfnew_rr : HInst<
22896(outs),
22897(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22898"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22899tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
22900let Inst{4-3} = 0b00;
22901let Inst{31-21} = 0b00110111101;
22902let isPredicated = 1;
22903let isPredicatedFalse = 1;
22904let addrMode = BaseRegOffset;
22905let accessSize = ByteAccess;
22906let isNVStore = 1;
22907let isPredicatedNew = 1;
22908let isNewValue = 1;
22909let isRestrictNoSlot1Store = 1;
22910let mayStore = 1;
22911let BaseOpcode = "S4_storerb_rr";
22912let CextOpcode = "S2_storerb";
22913let InputType = "reg";
22914let opNewValue = 4;
22915}
22916def S4_pstorerbnewfnew_zomap : HInst<
22917(outs),
22918(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22919"if (!$Pv4.new) memb($Rs32) = $Nt8.new",
22920tc_92240447, TypeMAPPING> {
22921let isPseudo = 1;
22922let isCodeGenOnly = 1;
22923let opNewValue = 2;
22924}
22925def S4_pstorerbnewt_abs : HInst<
22926(outs),
22927(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22928"if ($Pv4) memb(#$Ii) = $Nt8.new",
22929tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22930let Inst{2-2} = 0b0;
22931let Inst{7-7} = 0b1;
22932let Inst{13-11} = 0b000;
22933let Inst{31-18} = 0b10101111101000;
22934let isPredicated = 1;
22935let addrMode = Absolute;
22936let accessSize = ByteAccess;
22937let isNVStore = 1;
22938let isNewValue = 1;
22939let isExtended = 1;
22940let isRestrictNoSlot1Store = 1;
22941let mayStore = 1;
22942let BaseOpcode = "S2_storerbabs";
22943let CextOpcode = "S2_storerb";
22944let DecoderNamespace = "MustExtend";
22945let isExtendable = 1;
22946let opExtendable = 1;
22947let isExtentSigned = 0;
22948let opExtentBits = 6;
22949let opExtentAlign = 0;
22950let opNewValue = 2;
22951}
22952def S4_pstorerbnewt_rr : HInst<
22953(outs),
22954(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22955"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22956tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22957let Inst{4-3} = 0b00;
22958let Inst{31-21} = 0b00110100101;
22959let isPredicated = 1;
22960let addrMode = BaseRegOffset;
22961let accessSize = ByteAccess;
22962let isNVStore = 1;
22963let isNewValue = 1;
22964let isRestrictNoSlot1Store = 1;
22965let mayStore = 1;
22966let BaseOpcode = "S4_storerb_rr";
22967let CextOpcode = "S2_storerb";
22968let InputType = "reg";
22969let opNewValue = 4;
22970}
22971def S4_pstorerbnewtnew_abs : HInst<
22972(outs),
22973(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22974"if ($Pv4.new) memb(#$Ii) = $Nt8.new",
22975tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22976let Inst{2-2} = 0b0;
22977let Inst{7-7} = 0b1;
22978let Inst{13-11} = 0b100;
22979let Inst{31-18} = 0b10101111101000;
22980let isPredicated = 1;
22981let addrMode = Absolute;
22982let accessSize = ByteAccess;
22983let isNVStore = 1;
22984let isPredicatedNew = 1;
22985let isNewValue = 1;
22986let isExtended = 1;
22987let isRestrictNoSlot1Store = 1;
22988let mayStore = 1;
22989let BaseOpcode = "S2_storerbabs";
22990let CextOpcode = "S2_storerb";
22991let DecoderNamespace = "MustExtend";
22992let isExtendable = 1;
22993let opExtendable = 1;
22994let isExtentSigned = 0;
22995let opExtentBits = 6;
22996let opExtentAlign = 0;
22997let opNewValue = 2;
22998}
22999def S4_pstorerbnewtnew_io : HInst<
23000(outs),
23001(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
23002"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
23003tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
23004let Inst{2-2} = 0b0;
23005let Inst{12-11} = 0b00;
23006let Inst{31-21} = 0b01000010101;
23007let isPredicated = 1;
23008let addrMode = BaseImmOffset;
23009let accessSize = ByteAccess;
23010let isNVStore = 1;
23011let isPredicatedNew = 1;
23012let isNewValue = 1;
23013let isRestrictNoSlot1Store = 1;
23014let mayStore = 1;
23015let BaseOpcode = "S2_storerb_io";
23016let CextOpcode = "S2_storerb";
23017let InputType = "imm";
23018let isExtendable = 1;
23019let opExtendable = 2;
23020let isExtentSigned = 0;
23021let opExtentBits = 6;
23022let opExtentAlign = 0;
23023let opNewValue = 3;
23024}
23025def S4_pstorerbnewtnew_rr : HInst<
23026(outs),
23027(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23028"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23029tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23030let Inst{4-3} = 0b00;
23031let Inst{31-21} = 0b00110110101;
23032let isPredicated = 1;
23033let addrMode = BaseRegOffset;
23034let accessSize = ByteAccess;
23035let isNVStore = 1;
23036let isPredicatedNew = 1;
23037let isNewValue = 1;
23038let isRestrictNoSlot1Store = 1;
23039let mayStore = 1;
23040let BaseOpcode = "S4_storerb_rr";
23041let CextOpcode = "S2_storerb";
23042let InputType = "reg";
23043let opNewValue = 4;
23044}
23045def S4_pstorerbnewtnew_zomap : HInst<
23046(outs),
23047(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23048"if ($Pv4.new) memb($Rs32) = $Nt8.new",
23049tc_92240447, TypeMAPPING> {
23050let isPseudo = 1;
23051let isCodeGenOnly = 1;
23052let opNewValue = 2;
23053}
23054def S4_pstorerbt_abs : HInst<
23055(outs),
23056(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23057"if ($Pv4) memb(#$Ii) = $Rt32",
23058tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23059let Inst{2-2} = 0b0;
23060let Inst{7-7} = 0b1;
23061let Inst{13-13} = 0b0;
23062let Inst{31-18} = 0b10101111000000;
23063let isPredicated = 1;
23064let addrMode = Absolute;
23065let accessSize = ByteAccess;
23066let isExtended = 1;
23067let mayStore = 1;
23068let BaseOpcode = "S2_storerbabs";
23069let CextOpcode = "S2_storerb";
23070let isNVStorable = 1;
23071let DecoderNamespace = "MustExtend";
23072let isExtendable = 1;
23073let opExtendable = 1;
23074let isExtentSigned = 0;
23075let opExtentBits = 6;
23076let opExtentAlign = 0;
23077}
23078def S4_pstorerbt_rr : HInst<
23079(outs),
23080(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23081"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23082tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23083let Inst{31-21} = 0b00110100000;
23084let isPredicated = 1;
23085let addrMode = BaseRegOffset;
23086let accessSize = ByteAccess;
23087let mayStore = 1;
23088let BaseOpcode = "S4_storerb_rr";
23089let CextOpcode = "S2_storerb";
23090let InputType = "reg";
23091let isNVStorable = 1;
23092}
23093def S4_pstorerbtnew_abs : HInst<
23094(outs),
23095(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23096"if ($Pv4.new) memb(#$Ii) = $Rt32",
23097tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23098let Inst{2-2} = 0b0;
23099let Inst{7-7} = 0b1;
23100let Inst{13-13} = 0b1;
23101let Inst{31-18} = 0b10101111000000;
23102let isPredicated = 1;
23103let addrMode = Absolute;
23104let accessSize = ByteAccess;
23105let isPredicatedNew = 1;
23106let isExtended = 1;
23107let mayStore = 1;
23108let BaseOpcode = "S2_storerbabs";
23109let CextOpcode = "S2_storerb";
23110let isNVStorable = 1;
23111let DecoderNamespace = "MustExtend";
23112let isExtendable = 1;
23113let opExtendable = 1;
23114let isExtentSigned = 0;
23115let opExtentBits = 6;
23116let opExtentAlign = 0;
23117}
23118def S4_pstorerbtnew_io : HInst<
23119(outs),
23120(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
23121"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
23122tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
23123let Inst{2-2} = 0b0;
23124let Inst{31-21} = 0b01000010000;
23125let isPredicated = 1;
23126let addrMode = BaseImmOffset;
23127let accessSize = ByteAccess;
23128let isPredicatedNew = 1;
23129let mayStore = 1;
23130let BaseOpcode = "S2_storerb_io";
23131let CextOpcode = "S2_storerb";
23132let InputType = "imm";
23133let isNVStorable = 1;
23134let isExtendable = 1;
23135let opExtendable = 2;
23136let isExtentSigned = 0;
23137let opExtentBits = 6;
23138let opExtentAlign = 0;
23139}
23140def S4_pstorerbtnew_rr : HInst<
23141(outs),
23142(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23143"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23144tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23145let Inst{31-21} = 0b00110110000;
23146let isPredicated = 1;
23147let addrMode = BaseRegOffset;
23148let accessSize = ByteAccess;
23149let isPredicatedNew = 1;
23150let mayStore = 1;
23151let BaseOpcode = "S4_storerb_rr";
23152let CextOpcode = "S2_storerb";
23153let InputType = "reg";
23154let isNVStorable = 1;
23155}
23156def S4_pstorerbtnew_zomap : HInst<
23157(outs),
23158(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23159"if ($Pv4.new) memb($Rs32) = $Rt32",
23160tc_a2b365d2, TypeMAPPING> {
23161let isPseudo = 1;
23162let isCodeGenOnly = 1;
23163}
23164def S4_pstorerdf_abs : HInst<
23165(outs),
23166(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23167"if (!$Pv4) memd(#$Ii) = $Rtt32",
23168tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23169let Inst{2-2} = 0b1;
23170let Inst{7-7} = 0b1;
23171let Inst{13-13} = 0b0;
23172let Inst{31-18} = 0b10101111110000;
23173let isPredicated = 1;
23174let isPredicatedFalse = 1;
23175let addrMode = Absolute;
23176let accessSize = DoubleWordAccess;
23177let isExtended = 1;
23178let mayStore = 1;
23179let BaseOpcode = "S2_storerdabs";
23180let CextOpcode = "S2_storerd";
23181let DecoderNamespace = "MustExtend";
23182let isExtendable = 1;
23183let opExtendable = 1;
23184let isExtentSigned = 0;
23185let opExtentBits = 6;
23186let opExtentAlign = 0;
23187}
23188def S4_pstorerdf_rr : HInst<
23189(outs),
23190(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23191"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23192tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23193let Inst{31-21} = 0b00110101110;
23194let isPredicated = 1;
23195let isPredicatedFalse = 1;
23196let addrMode = BaseRegOffset;
23197let accessSize = DoubleWordAccess;
23198let mayStore = 1;
23199let BaseOpcode = "S2_storerd_rr";
23200let CextOpcode = "S2_storerd";
23201let InputType = "reg";
23202}
23203def S4_pstorerdfnew_abs : HInst<
23204(outs),
23205(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23206"if (!$Pv4.new) memd(#$Ii) = $Rtt32",
23207tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23208let Inst{2-2} = 0b1;
23209let Inst{7-7} = 0b1;
23210let Inst{13-13} = 0b1;
23211let Inst{31-18} = 0b10101111110000;
23212let isPredicated = 1;
23213let isPredicatedFalse = 1;
23214let addrMode = Absolute;
23215let accessSize = DoubleWordAccess;
23216let isPredicatedNew = 1;
23217let isExtended = 1;
23218let mayStore = 1;
23219let BaseOpcode = "S2_storerdabs";
23220let CextOpcode = "S2_storerd";
23221let DecoderNamespace = "MustExtend";
23222let isExtendable = 1;
23223let opExtendable = 1;
23224let isExtentSigned = 0;
23225let opExtentBits = 6;
23226let opExtentAlign = 0;
23227}
23228def S4_pstorerdfnew_io : HInst<
23229(outs),
23230(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23231"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23232tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23233let Inst{2-2} = 0b0;
23234let Inst{31-21} = 0b01000110110;
23235let isPredicated = 1;
23236let isPredicatedFalse = 1;
23237let addrMode = BaseImmOffset;
23238let accessSize = DoubleWordAccess;
23239let isPredicatedNew = 1;
23240let mayStore = 1;
23241let BaseOpcode = "S2_storerd_io";
23242let CextOpcode = "S2_storerd";
23243let InputType = "imm";
23244let isExtendable = 1;
23245let opExtendable = 2;
23246let isExtentSigned = 0;
23247let opExtentBits = 9;
23248let opExtentAlign = 3;
23249}
23250def S4_pstorerdfnew_rr : HInst<
23251(outs),
23252(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23253"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23254tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23255let Inst{31-21} = 0b00110111110;
23256let isPredicated = 1;
23257let isPredicatedFalse = 1;
23258let addrMode = BaseRegOffset;
23259let accessSize = DoubleWordAccess;
23260let isPredicatedNew = 1;
23261let mayStore = 1;
23262let BaseOpcode = "S2_storerd_rr";
23263let CextOpcode = "S2_storerd";
23264let InputType = "reg";
23265}
23266def S4_pstorerdfnew_zomap : HInst<
23267(outs),
23268(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23269"if (!$Pv4.new) memd($Rs32) = $Rtt32",
23270tc_a2b365d2, TypeMAPPING> {
23271let isPseudo = 1;
23272let isCodeGenOnly = 1;
23273}
23274def S4_pstorerdt_abs : HInst<
23275(outs),
23276(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23277"if ($Pv4) memd(#$Ii) = $Rtt32",
23278tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23279let Inst{2-2} = 0b0;
23280let Inst{7-7} = 0b1;
23281let Inst{13-13} = 0b0;
23282let Inst{31-18} = 0b10101111110000;
23283let isPredicated = 1;
23284let addrMode = Absolute;
23285let accessSize = DoubleWordAccess;
23286let isExtended = 1;
23287let mayStore = 1;
23288let BaseOpcode = "S2_storerdabs";
23289let CextOpcode = "S2_storerd";
23290let DecoderNamespace = "MustExtend";
23291let isExtendable = 1;
23292let opExtendable = 1;
23293let isExtentSigned = 0;
23294let opExtentBits = 6;
23295let opExtentAlign = 0;
23296}
23297def S4_pstorerdt_rr : HInst<
23298(outs),
23299(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23300"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23301tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23302let Inst{31-21} = 0b00110100110;
23303let isPredicated = 1;
23304let addrMode = BaseRegOffset;
23305let accessSize = DoubleWordAccess;
23306let mayStore = 1;
23307let BaseOpcode = "S2_storerd_rr";
23308let CextOpcode = "S2_storerd";
23309let InputType = "reg";
23310}
23311def S4_pstorerdtnew_abs : HInst<
23312(outs),
23313(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23314"if ($Pv4.new) memd(#$Ii) = $Rtt32",
23315tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23316let Inst{2-2} = 0b0;
23317let Inst{7-7} = 0b1;
23318let Inst{13-13} = 0b1;
23319let Inst{31-18} = 0b10101111110000;
23320let isPredicated = 1;
23321let addrMode = Absolute;
23322let accessSize = DoubleWordAccess;
23323let isPredicatedNew = 1;
23324let isExtended = 1;
23325let mayStore = 1;
23326let BaseOpcode = "S2_storerdabs";
23327let CextOpcode = "S2_storerd";
23328let DecoderNamespace = "MustExtend";
23329let isExtendable = 1;
23330let opExtendable = 1;
23331let isExtentSigned = 0;
23332let opExtentBits = 6;
23333let opExtentAlign = 0;
23334}
23335def S4_pstorerdtnew_io : HInst<
23336(outs),
23337(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23338"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23339tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23340let Inst{2-2} = 0b0;
23341let Inst{31-21} = 0b01000010110;
23342let isPredicated = 1;
23343let addrMode = BaseImmOffset;
23344let accessSize = DoubleWordAccess;
23345let isPredicatedNew = 1;
23346let mayStore = 1;
23347let BaseOpcode = "S2_storerd_io";
23348let CextOpcode = "S2_storerd";
23349let InputType = "imm";
23350let isExtendable = 1;
23351let opExtendable = 2;
23352let isExtentSigned = 0;
23353let opExtentBits = 9;
23354let opExtentAlign = 3;
23355}
23356def S4_pstorerdtnew_rr : HInst<
23357(outs),
23358(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23359"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23360tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23361let Inst{31-21} = 0b00110110110;
23362let isPredicated = 1;
23363let addrMode = BaseRegOffset;
23364let accessSize = DoubleWordAccess;
23365let isPredicatedNew = 1;
23366let mayStore = 1;
23367let BaseOpcode = "S2_storerd_rr";
23368let CextOpcode = "S2_storerd";
23369let InputType = "reg";
23370}
23371def S4_pstorerdtnew_zomap : HInst<
23372(outs),
23373(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23374"if ($Pv4.new) memd($Rs32) = $Rtt32",
23375tc_a2b365d2, TypeMAPPING> {
23376let isPseudo = 1;
23377let isCodeGenOnly = 1;
23378}
23379def S4_pstorerff_abs : HInst<
23380(outs),
23381(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23382"if (!$Pv4) memh(#$Ii) = $Rt32.h",
23383tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23384let Inst{2-2} = 0b1;
23385let Inst{7-7} = 0b1;
23386let Inst{13-13} = 0b0;
23387let Inst{31-18} = 0b10101111011000;
23388let isPredicated = 1;
23389let isPredicatedFalse = 1;
23390let addrMode = Absolute;
23391let accessSize = HalfWordAccess;
23392let isExtended = 1;
23393let mayStore = 1;
23394let BaseOpcode = "S2_storerfabs";
23395let CextOpcode = "S2_storerf";
23396let DecoderNamespace = "MustExtend";
23397let isExtendable = 1;
23398let opExtendable = 1;
23399let isExtentSigned = 0;
23400let opExtentBits = 6;
23401let opExtentAlign = 0;
23402}
23403def S4_pstorerff_rr : HInst<
23404(outs),
23405(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23406"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23407tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23408let Inst{31-21} = 0b00110101011;
23409let isPredicated = 1;
23410let isPredicatedFalse = 1;
23411let addrMode = BaseRegOffset;
23412let accessSize = HalfWordAccess;
23413let mayStore = 1;
23414let BaseOpcode = "S4_storerf_rr";
23415let CextOpcode = "S2_storerf";
23416let InputType = "reg";
23417}
23418def S4_pstorerffnew_abs : HInst<
23419(outs),
23420(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23421"if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
23422tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23423let Inst{2-2} = 0b1;
23424let Inst{7-7} = 0b1;
23425let Inst{13-13} = 0b1;
23426let Inst{31-18} = 0b10101111011000;
23427let isPredicated = 1;
23428let isPredicatedFalse = 1;
23429let addrMode = Absolute;
23430let accessSize = HalfWordAccess;
23431let isPredicatedNew = 1;
23432let isExtended = 1;
23433let mayStore = 1;
23434let BaseOpcode = "S2_storerfabs";
23435let CextOpcode = "S2_storerf";
23436let DecoderNamespace = "MustExtend";
23437let isExtendable = 1;
23438let opExtendable = 1;
23439let isExtentSigned = 0;
23440let opExtentBits = 6;
23441let opExtentAlign = 0;
23442}
23443def S4_pstorerffnew_io : HInst<
23444(outs),
23445(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23446"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23447tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23448let Inst{2-2} = 0b0;
23449let Inst{31-21} = 0b01000110011;
23450let isPredicated = 1;
23451let isPredicatedFalse = 1;
23452let addrMode = BaseImmOffset;
23453let accessSize = HalfWordAccess;
23454let isPredicatedNew = 1;
23455let mayStore = 1;
23456let BaseOpcode = "S2_storerf_io";
23457let CextOpcode = "S2_storerf";
23458let InputType = "imm";
23459let isExtendable = 1;
23460let opExtendable = 2;
23461let isExtentSigned = 0;
23462let opExtentBits = 7;
23463let opExtentAlign = 1;
23464}
23465def S4_pstorerffnew_rr : HInst<
23466(outs),
23467(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23468"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23469tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23470let Inst{31-21} = 0b00110111011;
23471let isPredicated = 1;
23472let isPredicatedFalse = 1;
23473let addrMode = BaseRegOffset;
23474let accessSize = HalfWordAccess;
23475let isPredicatedNew = 1;
23476let mayStore = 1;
23477let BaseOpcode = "S4_storerf_rr";
23478let CextOpcode = "S2_storerf";
23479let InputType = "reg";
23480}
23481def S4_pstorerffnew_zomap : HInst<
23482(outs),
23483(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23484"if (!$Pv4.new) memh($Rs32) = $Rt32.h",
23485tc_a2b365d2, TypeMAPPING> {
23486let isPseudo = 1;
23487let isCodeGenOnly = 1;
23488}
23489def S4_pstorerft_abs : HInst<
23490(outs),
23491(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23492"if ($Pv4) memh(#$Ii) = $Rt32.h",
23493tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23494let Inst{2-2} = 0b0;
23495let Inst{7-7} = 0b1;
23496let Inst{13-13} = 0b0;
23497let Inst{31-18} = 0b10101111011000;
23498let isPredicated = 1;
23499let addrMode = Absolute;
23500let accessSize = HalfWordAccess;
23501let isExtended = 1;
23502let mayStore = 1;
23503let BaseOpcode = "S2_storerfabs";
23504let CextOpcode = "S2_storerf";
23505let DecoderNamespace = "MustExtend";
23506let isExtendable = 1;
23507let opExtendable = 1;
23508let isExtentSigned = 0;
23509let opExtentBits = 6;
23510let opExtentAlign = 0;
23511}
23512def S4_pstorerft_rr : HInst<
23513(outs),
23514(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23515"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23516tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23517let Inst{31-21} = 0b00110100011;
23518let isPredicated = 1;
23519let addrMode = BaseRegOffset;
23520let accessSize = HalfWordAccess;
23521let mayStore = 1;
23522let BaseOpcode = "S4_storerf_rr";
23523let CextOpcode = "S2_storerf";
23524let InputType = "reg";
23525}
23526def S4_pstorerftnew_abs : HInst<
23527(outs),
23528(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23529"if ($Pv4.new) memh(#$Ii) = $Rt32.h",
23530tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23531let Inst{2-2} = 0b0;
23532let Inst{7-7} = 0b1;
23533let Inst{13-13} = 0b1;
23534let Inst{31-18} = 0b10101111011000;
23535let isPredicated = 1;
23536let addrMode = Absolute;
23537let accessSize = HalfWordAccess;
23538let isPredicatedNew = 1;
23539let isExtended = 1;
23540let mayStore = 1;
23541let BaseOpcode = "S2_storerfabs";
23542let CextOpcode = "S2_storerf";
23543let DecoderNamespace = "MustExtend";
23544let isExtendable = 1;
23545let opExtendable = 1;
23546let isExtentSigned = 0;
23547let opExtentBits = 6;
23548let opExtentAlign = 0;
23549}
23550def S4_pstorerftnew_io : HInst<
23551(outs),
23552(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23553"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23554tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23555let Inst{2-2} = 0b0;
23556let Inst{31-21} = 0b01000010011;
23557let isPredicated = 1;
23558let addrMode = BaseImmOffset;
23559let accessSize = HalfWordAccess;
23560let isPredicatedNew = 1;
23561let mayStore = 1;
23562let BaseOpcode = "S2_storerf_io";
23563let CextOpcode = "S2_storerf";
23564let InputType = "imm";
23565let isExtendable = 1;
23566let opExtendable = 2;
23567let isExtentSigned = 0;
23568let opExtentBits = 7;
23569let opExtentAlign = 1;
23570}
23571def S4_pstorerftnew_rr : HInst<
23572(outs),
23573(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23574"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23575tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23576let Inst{31-21} = 0b00110110011;
23577let isPredicated = 1;
23578let addrMode = BaseRegOffset;
23579let accessSize = HalfWordAccess;
23580let isPredicatedNew = 1;
23581let mayStore = 1;
23582let BaseOpcode = "S4_storerf_rr";
23583let CextOpcode = "S2_storerf";
23584let InputType = "reg";
23585}
23586def S4_pstorerftnew_zomap : HInst<
23587(outs),
23588(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23589"if ($Pv4.new) memh($Rs32) = $Rt32.h",
23590tc_a2b365d2, TypeMAPPING> {
23591let isPseudo = 1;
23592let isCodeGenOnly = 1;
23593}
23594def S4_pstorerhf_abs : HInst<
23595(outs),
23596(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23597"if (!$Pv4) memh(#$Ii) = $Rt32",
23598tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23599let Inst{2-2} = 0b1;
23600let Inst{7-7} = 0b1;
23601let Inst{13-13} = 0b0;
23602let Inst{31-18} = 0b10101111010000;
23603let isPredicated = 1;
23604let isPredicatedFalse = 1;
23605let addrMode = Absolute;
23606let accessSize = HalfWordAccess;
23607let isExtended = 1;
23608let mayStore = 1;
23609let BaseOpcode = "S2_storerhabs";
23610let CextOpcode = "S2_storerh";
23611let isNVStorable = 1;
23612let DecoderNamespace = "MustExtend";
23613let isExtendable = 1;
23614let opExtendable = 1;
23615let isExtentSigned = 0;
23616let opExtentBits = 6;
23617let opExtentAlign = 0;
23618}
23619def S4_pstorerhf_rr : HInst<
23620(outs),
23621(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23622"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23623tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23624let Inst{31-21} = 0b00110101010;
23625let isPredicated = 1;
23626let isPredicatedFalse = 1;
23627let addrMode = BaseRegOffset;
23628let accessSize = HalfWordAccess;
23629let mayStore = 1;
23630let BaseOpcode = "S2_storerh_rr";
23631let CextOpcode = "S2_storerh";
23632let InputType = "reg";
23633let isNVStorable = 1;
23634}
23635def S4_pstorerhfnew_abs : HInst<
23636(outs),
23637(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23638"if (!$Pv4.new) memh(#$Ii) = $Rt32",
23639tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23640let Inst{2-2} = 0b1;
23641let Inst{7-7} = 0b1;
23642let Inst{13-13} = 0b1;
23643let Inst{31-18} = 0b10101111010000;
23644let isPredicated = 1;
23645let isPredicatedFalse = 1;
23646let addrMode = Absolute;
23647let accessSize = HalfWordAccess;
23648let isPredicatedNew = 1;
23649let isExtended = 1;
23650let mayStore = 1;
23651let BaseOpcode = "S2_storerhabs";
23652let CextOpcode = "S2_storerh";
23653let isNVStorable = 1;
23654let DecoderNamespace = "MustExtend";
23655let isExtendable = 1;
23656let opExtendable = 1;
23657let isExtentSigned = 0;
23658let opExtentBits = 6;
23659let opExtentAlign = 0;
23660}
23661def S4_pstorerhfnew_io : HInst<
23662(outs),
23663(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23664"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23665tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23666let Inst{2-2} = 0b0;
23667let Inst{31-21} = 0b01000110010;
23668let isPredicated = 1;
23669let isPredicatedFalse = 1;
23670let addrMode = BaseImmOffset;
23671let accessSize = HalfWordAccess;
23672let isPredicatedNew = 1;
23673let mayStore = 1;
23674let BaseOpcode = "S2_storerh_io";
23675let CextOpcode = "S2_storerh";
23676let InputType = "imm";
23677let isNVStorable = 1;
23678let isExtendable = 1;
23679let opExtendable = 2;
23680let isExtentSigned = 0;
23681let opExtentBits = 7;
23682let opExtentAlign = 1;
23683}
23684def S4_pstorerhfnew_rr : HInst<
23685(outs),
23686(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23687"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23688tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23689let Inst{31-21} = 0b00110111010;
23690let isPredicated = 1;
23691let isPredicatedFalse = 1;
23692let addrMode = BaseRegOffset;
23693let accessSize = HalfWordAccess;
23694let isPredicatedNew = 1;
23695let mayStore = 1;
23696let BaseOpcode = "S2_storerh_rr";
23697let CextOpcode = "S2_storerh";
23698let InputType = "reg";
23699let isNVStorable = 1;
23700}
23701def S4_pstorerhfnew_zomap : HInst<
23702(outs),
23703(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23704"if (!$Pv4.new) memh($Rs32) = $Rt32",
23705tc_a2b365d2, TypeMAPPING> {
23706let isPseudo = 1;
23707let isCodeGenOnly = 1;
23708}
23709def S4_pstorerhnewf_abs : HInst<
23710(outs),
23711(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23712"if (!$Pv4) memh(#$Ii) = $Nt8.new",
23713tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23714let Inst{2-2} = 0b1;
23715let Inst{7-7} = 0b1;
23716let Inst{13-11} = 0b001;
23717let Inst{31-18} = 0b10101111101000;
23718let isPredicated = 1;
23719let isPredicatedFalse = 1;
23720let addrMode = Absolute;
23721let accessSize = HalfWordAccess;
23722let isNVStore = 1;
23723let isNewValue = 1;
23724let isExtended = 1;
23725let isRestrictNoSlot1Store = 1;
23726let mayStore = 1;
23727let BaseOpcode = "S2_storerhabs";
23728let CextOpcode = "S2_storerh";
23729let DecoderNamespace = "MustExtend";
23730let isExtendable = 1;
23731let opExtendable = 1;
23732let isExtentSigned = 0;
23733let opExtentBits = 6;
23734let opExtentAlign = 0;
23735let opNewValue = 2;
23736}
23737def S4_pstorerhnewf_rr : HInst<
23738(outs),
23739(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23740"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23741tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23742let Inst{4-3} = 0b01;
23743let Inst{31-21} = 0b00110101101;
23744let isPredicated = 1;
23745let isPredicatedFalse = 1;
23746let addrMode = BaseRegOffset;
23747let accessSize = HalfWordAccess;
23748let isNVStore = 1;
23749let isNewValue = 1;
23750let isRestrictNoSlot1Store = 1;
23751let mayStore = 1;
23752let BaseOpcode = "S2_storerh_rr";
23753let CextOpcode = "S2_storerh";
23754let InputType = "reg";
23755let opNewValue = 4;
23756}
23757def S4_pstorerhnewfnew_abs : HInst<
23758(outs),
23759(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23760"if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
23761tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23762let Inst{2-2} = 0b1;
23763let Inst{7-7} = 0b1;
23764let Inst{13-11} = 0b101;
23765let Inst{31-18} = 0b10101111101000;
23766let isPredicated = 1;
23767let isPredicatedFalse = 1;
23768let addrMode = Absolute;
23769let accessSize = HalfWordAccess;
23770let isNVStore = 1;
23771let isPredicatedNew = 1;
23772let isNewValue = 1;
23773let isExtended = 1;
23774let isRestrictNoSlot1Store = 1;
23775let mayStore = 1;
23776let BaseOpcode = "S2_storerhabs";
23777let CextOpcode = "S2_storerh";
23778let DecoderNamespace = "MustExtend";
23779let isExtendable = 1;
23780let opExtendable = 1;
23781let isExtentSigned = 0;
23782let opExtentBits = 6;
23783let opExtentAlign = 0;
23784let opNewValue = 2;
23785}
23786def S4_pstorerhnewfnew_io : HInst<
23787(outs),
23788(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23789"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23790tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23791let Inst{2-2} = 0b0;
23792let Inst{12-11} = 0b01;
23793let Inst{31-21} = 0b01000110101;
23794let isPredicated = 1;
23795let isPredicatedFalse = 1;
23796let addrMode = BaseImmOffset;
23797let accessSize = HalfWordAccess;
23798let isNVStore = 1;
23799let isPredicatedNew = 1;
23800let isNewValue = 1;
23801let isRestrictNoSlot1Store = 1;
23802let mayStore = 1;
23803let BaseOpcode = "S2_storerh_io";
23804let CextOpcode = "S2_storerh";
23805let InputType = "imm";
23806let isExtendable = 1;
23807let opExtendable = 2;
23808let isExtentSigned = 0;
23809let opExtentBits = 7;
23810let opExtentAlign = 1;
23811let opNewValue = 3;
23812}
23813def S4_pstorerhnewfnew_rr : HInst<
23814(outs),
23815(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23816"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23817tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23818let Inst{4-3} = 0b01;
23819let Inst{31-21} = 0b00110111101;
23820let isPredicated = 1;
23821let isPredicatedFalse = 1;
23822let addrMode = BaseRegOffset;
23823let accessSize = HalfWordAccess;
23824let isNVStore = 1;
23825let isPredicatedNew = 1;
23826let isNewValue = 1;
23827let isRestrictNoSlot1Store = 1;
23828let mayStore = 1;
23829let BaseOpcode = "S2_storerh_rr";
23830let CextOpcode = "S2_storerh";
23831let InputType = "reg";
23832let opNewValue = 4;
23833}
23834def S4_pstorerhnewfnew_zomap : HInst<
23835(outs),
23836(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23837"if (!$Pv4.new) memh($Rs32) = $Nt8.new",
23838tc_92240447, TypeMAPPING> {
23839let isPseudo = 1;
23840let isCodeGenOnly = 1;
23841let opNewValue = 2;
23842}
23843def S4_pstorerhnewt_abs : HInst<
23844(outs),
23845(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23846"if ($Pv4) memh(#$Ii) = $Nt8.new",
23847tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23848let Inst{2-2} = 0b0;
23849let Inst{7-7} = 0b1;
23850let Inst{13-11} = 0b001;
23851let Inst{31-18} = 0b10101111101000;
23852let isPredicated = 1;
23853let addrMode = Absolute;
23854let accessSize = HalfWordAccess;
23855let isNVStore = 1;
23856let isNewValue = 1;
23857let isExtended = 1;
23858let isRestrictNoSlot1Store = 1;
23859let mayStore = 1;
23860let BaseOpcode = "S2_storerhabs";
23861let CextOpcode = "S2_storerh";
23862let DecoderNamespace = "MustExtend";
23863let isExtendable = 1;
23864let opExtendable = 1;
23865let isExtentSigned = 0;
23866let opExtentBits = 6;
23867let opExtentAlign = 0;
23868let opNewValue = 2;
23869}
23870def S4_pstorerhnewt_rr : HInst<
23871(outs),
23872(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23873"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23874tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23875let Inst{4-3} = 0b01;
23876let Inst{31-21} = 0b00110100101;
23877let isPredicated = 1;
23878let addrMode = BaseRegOffset;
23879let accessSize = HalfWordAccess;
23880let isNVStore = 1;
23881let isNewValue = 1;
23882let isRestrictNoSlot1Store = 1;
23883let mayStore = 1;
23884let BaseOpcode = "S2_storerh_rr";
23885let CextOpcode = "S2_storerh";
23886let InputType = "reg";
23887let opNewValue = 4;
23888}
23889def S4_pstorerhnewtnew_abs : HInst<
23890(outs),
23891(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23892"if ($Pv4.new) memh(#$Ii) = $Nt8.new",
23893tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23894let Inst{2-2} = 0b0;
23895let Inst{7-7} = 0b1;
23896let Inst{13-11} = 0b101;
23897let Inst{31-18} = 0b10101111101000;
23898let isPredicated = 1;
23899let addrMode = Absolute;
23900let accessSize = HalfWordAccess;
23901let isNVStore = 1;
23902let isPredicatedNew = 1;
23903let isNewValue = 1;
23904let isExtended = 1;
23905let isRestrictNoSlot1Store = 1;
23906let mayStore = 1;
23907let BaseOpcode = "S2_storerhabs";
23908let CextOpcode = "S2_storerh";
23909let DecoderNamespace = "MustExtend";
23910let isExtendable = 1;
23911let opExtendable = 1;
23912let isExtentSigned = 0;
23913let opExtentBits = 6;
23914let opExtentAlign = 0;
23915let opNewValue = 2;
23916}
23917def S4_pstorerhnewtnew_io : HInst<
23918(outs),
23919(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23920"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23921tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23922let Inst{2-2} = 0b0;
23923let Inst{12-11} = 0b01;
23924let Inst{31-21} = 0b01000010101;
23925let isPredicated = 1;
23926let addrMode = BaseImmOffset;
23927let accessSize = HalfWordAccess;
23928let isNVStore = 1;
23929let isPredicatedNew = 1;
23930let isNewValue = 1;
23931let isRestrictNoSlot1Store = 1;
23932let mayStore = 1;
23933let BaseOpcode = "S2_storerh_io";
23934let CextOpcode = "S2_storerh";
23935let InputType = "imm";
23936let isExtendable = 1;
23937let opExtendable = 2;
23938let isExtentSigned = 0;
23939let opExtentBits = 7;
23940let opExtentAlign = 1;
23941let opNewValue = 3;
23942}
23943def S4_pstorerhnewtnew_rr : HInst<
23944(outs),
23945(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23946"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23947tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23948let Inst{4-3} = 0b01;
23949let Inst{31-21} = 0b00110110101;
23950let isPredicated = 1;
23951let addrMode = BaseRegOffset;
23952let accessSize = HalfWordAccess;
23953let isNVStore = 1;
23954let isPredicatedNew = 1;
23955let isNewValue = 1;
23956let isRestrictNoSlot1Store = 1;
23957let mayStore = 1;
23958let BaseOpcode = "S2_storerh_rr";
23959let CextOpcode = "S2_storerh";
23960let InputType = "reg";
23961let opNewValue = 4;
23962}
23963def S4_pstorerhnewtnew_zomap : HInst<
23964(outs),
23965(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23966"if ($Pv4.new) memh($Rs32) = $Nt8.new",
23967tc_92240447, TypeMAPPING> {
23968let isPseudo = 1;
23969let isCodeGenOnly = 1;
23970let opNewValue = 2;
23971}
23972def S4_pstorerht_abs : HInst<
23973(outs),
23974(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23975"if ($Pv4) memh(#$Ii) = $Rt32",
23976tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23977let Inst{2-2} = 0b0;
23978let Inst{7-7} = 0b1;
23979let Inst{13-13} = 0b0;
23980let Inst{31-18} = 0b10101111010000;
23981let isPredicated = 1;
23982let addrMode = Absolute;
23983let accessSize = HalfWordAccess;
23984let isExtended = 1;
23985let mayStore = 1;
23986let BaseOpcode = "S2_storerhabs";
23987let CextOpcode = "S2_storerh";
23988let isNVStorable = 1;
23989let DecoderNamespace = "MustExtend";
23990let isExtendable = 1;
23991let opExtendable = 1;
23992let isExtentSigned = 0;
23993let opExtentBits = 6;
23994let opExtentAlign = 0;
23995}
23996def S4_pstorerht_rr : HInst<
23997(outs),
23998(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23999"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24000tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24001let Inst{31-21} = 0b00110100010;
24002let isPredicated = 1;
24003let addrMode = BaseRegOffset;
24004let accessSize = HalfWordAccess;
24005let mayStore = 1;
24006let BaseOpcode = "S2_storerh_rr";
24007let CextOpcode = "S2_storerh";
24008let InputType = "reg";
24009let isNVStorable = 1;
24010}
24011def S4_pstorerhtnew_abs : HInst<
24012(outs),
24013(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24014"if ($Pv4.new) memh(#$Ii) = $Rt32",
24015tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24016let Inst{2-2} = 0b0;
24017let Inst{7-7} = 0b1;
24018let Inst{13-13} = 0b1;
24019let Inst{31-18} = 0b10101111010000;
24020let isPredicated = 1;
24021let addrMode = Absolute;
24022let accessSize = HalfWordAccess;
24023let isPredicatedNew = 1;
24024let isExtended = 1;
24025let mayStore = 1;
24026let BaseOpcode = "S2_storerhabs";
24027let CextOpcode = "S2_storerh";
24028let isNVStorable = 1;
24029let DecoderNamespace = "MustExtend";
24030let isExtendable = 1;
24031let opExtendable = 1;
24032let isExtentSigned = 0;
24033let opExtentBits = 6;
24034let opExtentAlign = 0;
24035}
24036def S4_pstorerhtnew_io : HInst<
24037(outs),
24038(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
24039"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
24040tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
24041let Inst{2-2} = 0b0;
24042let Inst{31-21} = 0b01000010010;
24043let isPredicated = 1;
24044let addrMode = BaseImmOffset;
24045let accessSize = HalfWordAccess;
24046let isPredicatedNew = 1;
24047let mayStore = 1;
24048let BaseOpcode = "S2_storerh_io";
24049let CextOpcode = "S2_storerh";
24050let InputType = "imm";
24051let isNVStorable = 1;
24052let isExtendable = 1;
24053let opExtendable = 2;
24054let isExtentSigned = 0;
24055let opExtentBits = 7;
24056let opExtentAlign = 1;
24057}
24058def S4_pstorerhtnew_rr : HInst<
24059(outs),
24060(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24061"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24062tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24063let Inst{31-21} = 0b00110110010;
24064let isPredicated = 1;
24065let addrMode = BaseRegOffset;
24066let accessSize = HalfWordAccess;
24067let isPredicatedNew = 1;
24068let mayStore = 1;
24069let BaseOpcode = "S2_storerh_rr";
24070let CextOpcode = "S2_storerh";
24071let InputType = "reg";
24072let isNVStorable = 1;
24073}
24074def S4_pstorerhtnew_zomap : HInst<
24075(outs),
24076(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24077"if ($Pv4.new) memh($Rs32) = $Rt32",
24078tc_a2b365d2, TypeMAPPING> {
24079let isPseudo = 1;
24080let isCodeGenOnly = 1;
24081}
24082def S4_pstorerif_abs : HInst<
24083(outs),
24084(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24085"if (!$Pv4) memw(#$Ii) = $Rt32",
24086tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24087let Inst{2-2} = 0b1;
24088let Inst{7-7} = 0b1;
24089let Inst{13-13} = 0b0;
24090let Inst{31-18} = 0b10101111100000;
24091let isPredicated = 1;
24092let isPredicatedFalse = 1;
24093let addrMode = Absolute;
24094let accessSize = WordAccess;
24095let isExtended = 1;
24096let mayStore = 1;
24097let BaseOpcode = "S2_storeriabs";
24098let CextOpcode = "S2_storeri";
24099let isNVStorable = 1;
24100let DecoderNamespace = "MustExtend";
24101let isExtendable = 1;
24102let opExtendable = 1;
24103let isExtentSigned = 0;
24104let opExtentBits = 6;
24105let opExtentAlign = 0;
24106}
24107def S4_pstorerif_rr : HInst<
24108(outs),
24109(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24110"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24111tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24112let Inst{31-21} = 0b00110101100;
24113let isPredicated = 1;
24114let isPredicatedFalse = 1;
24115let addrMode = BaseRegOffset;
24116let accessSize = WordAccess;
24117let mayStore = 1;
24118let BaseOpcode = "S2_storeri_rr";
24119let CextOpcode = "S2_storeri";
24120let InputType = "reg";
24121let isNVStorable = 1;
24122}
24123def S4_pstorerifnew_abs : HInst<
24124(outs),
24125(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24126"if (!$Pv4.new) memw(#$Ii) = $Rt32",
24127tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24128let Inst{2-2} = 0b1;
24129let Inst{7-7} = 0b1;
24130let Inst{13-13} = 0b1;
24131let Inst{31-18} = 0b10101111100000;
24132let isPredicated = 1;
24133let isPredicatedFalse = 1;
24134let addrMode = Absolute;
24135let accessSize = WordAccess;
24136let isPredicatedNew = 1;
24137let isExtended = 1;
24138let mayStore = 1;
24139let BaseOpcode = "S2_storeriabs";
24140let CextOpcode = "S2_storeri";
24141let isNVStorable = 1;
24142let DecoderNamespace = "MustExtend";
24143let isExtendable = 1;
24144let opExtendable = 1;
24145let isExtentSigned = 0;
24146let opExtentBits = 6;
24147let opExtentAlign = 0;
24148}
24149def S4_pstorerifnew_io : HInst<
24150(outs),
24151(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24152"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24153tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24154let Inst{2-2} = 0b0;
24155let Inst{31-21} = 0b01000110100;
24156let isPredicated = 1;
24157let isPredicatedFalse = 1;
24158let addrMode = BaseImmOffset;
24159let accessSize = WordAccess;
24160let isPredicatedNew = 1;
24161let mayStore = 1;
24162let BaseOpcode = "S2_storeri_io";
24163let CextOpcode = "S2_storeri";
24164let InputType = "imm";
24165let isNVStorable = 1;
24166let isExtendable = 1;
24167let opExtendable = 2;
24168let isExtentSigned = 0;
24169let opExtentBits = 8;
24170let opExtentAlign = 2;
24171}
24172def S4_pstorerifnew_rr : HInst<
24173(outs),
24174(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24175"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24176tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24177let Inst{31-21} = 0b00110111100;
24178let isPredicated = 1;
24179let isPredicatedFalse = 1;
24180let addrMode = BaseRegOffset;
24181let accessSize = WordAccess;
24182let isPredicatedNew = 1;
24183let mayStore = 1;
24184let BaseOpcode = "S2_storeri_rr";
24185let CextOpcode = "S2_storeri";
24186let InputType = "reg";
24187let isNVStorable = 1;
24188}
24189def S4_pstorerifnew_zomap : HInst<
24190(outs),
24191(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24192"if (!$Pv4.new) memw($Rs32) = $Rt32",
24193tc_a2b365d2, TypeMAPPING> {
24194let isPseudo = 1;
24195let isCodeGenOnly = 1;
24196}
24197def S4_pstorerinewf_abs : HInst<
24198(outs),
24199(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24200"if (!$Pv4) memw(#$Ii) = $Nt8.new",
24201tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24202let Inst{2-2} = 0b1;
24203let Inst{7-7} = 0b1;
24204let Inst{13-11} = 0b010;
24205let Inst{31-18} = 0b10101111101000;
24206let isPredicated = 1;
24207let isPredicatedFalse = 1;
24208let addrMode = Absolute;
24209let accessSize = WordAccess;
24210let isNVStore = 1;
24211let isNewValue = 1;
24212let isExtended = 1;
24213let isRestrictNoSlot1Store = 1;
24214let mayStore = 1;
24215let BaseOpcode = "S2_storeriabs";
24216let CextOpcode = "S2_storeri";
24217let DecoderNamespace = "MustExtend";
24218let isExtendable = 1;
24219let opExtendable = 1;
24220let isExtentSigned = 0;
24221let opExtentBits = 6;
24222let opExtentAlign = 0;
24223let opNewValue = 2;
24224}
24225def S4_pstorerinewf_rr : HInst<
24226(outs),
24227(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24228"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24229tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24230let Inst{4-3} = 0b10;
24231let Inst{31-21} = 0b00110101101;
24232let isPredicated = 1;
24233let isPredicatedFalse = 1;
24234let addrMode = BaseRegOffset;
24235let accessSize = WordAccess;
24236let isNVStore = 1;
24237let isNewValue = 1;
24238let isRestrictNoSlot1Store = 1;
24239let mayStore = 1;
24240let BaseOpcode = "S2_storeri_rr";
24241let CextOpcode = "S2_storeri";
24242let InputType = "reg";
24243let opNewValue = 4;
24244}
24245def S4_pstorerinewfnew_abs : HInst<
24246(outs),
24247(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24248"if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
24249tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24250let Inst{2-2} = 0b1;
24251let Inst{7-7} = 0b1;
24252let Inst{13-11} = 0b110;
24253let Inst{31-18} = 0b10101111101000;
24254let isPredicated = 1;
24255let isPredicatedFalse = 1;
24256let addrMode = Absolute;
24257let accessSize = WordAccess;
24258let isNVStore = 1;
24259let isPredicatedNew = 1;
24260let isNewValue = 1;
24261let isExtended = 1;
24262let isRestrictNoSlot1Store = 1;
24263let mayStore = 1;
24264let BaseOpcode = "S2_storeriabs";
24265let CextOpcode = "S2_storeri";
24266let DecoderNamespace = "MustExtend";
24267let isExtendable = 1;
24268let opExtendable = 1;
24269let isExtentSigned = 0;
24270let opExtentBits = 6;
24271let opExtentAlign = 0;
24272let opNewValue = 2;
24273}
24274def S4_pstorerinewfnew_io : HInst<
24275(outs),
24276(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24277"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24278tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24279let Inst{2-2} = 0b0;
24280let Inst{12-11} = 0b10;
24281let Inst{31-21} = 0b01000110101;
24282let isPredicated = 1;
24283let isPredicatedFalse = 1;
24284let addrMode = BaseImmOffset;
24285let accessSize = WordAccess;
24286let isNVStore = 1;
24287let isPredicatedNew = 1;
24288let isNewValue = 1;
24289let isRestrictNoSlot1Store = 1;
24290let mayStore = 1;
24291let BaseOpcode = "S2_storeri_io";
24292let CextOpcode = "S2_storeri";
24293let InputType = "imm";
24294let isExtendable = 1;
24295let opExtendable = 2;
24296let isExtentSigned = 0;
24297let opExtentBits = 8;
24298let opExtentAlign = 2;
24299let opNewValue = 3;
24300}
24301def S4_pstorerinewfnew_rr : HInst<
24302(outs),
24303(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24304"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24305tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24306let Inst{4-3} = 0b10;
24307let Inst{31-21} = 0b00110111101;
24308let isPredicated = 1;
24309let isPredicatedFalse = 1;
24310let addrMode = BaseRegOffset;
24311let accessSize = WordAccess;
24312let isNVStore = 1;
24313let isPredicatedNew = 1;
24314let isNewValue = 1;
24315let isRestrictNoSlot1Store = 1;
24316let mayStore = 1;
24317let BaseOpcode = "S2_storeri_rr";
24318let CextOpcode = "S2_storeri";
24319let InputType = "reg";
24320let opNewValue = 4;
24321}
24322def S4_pstorerinewfnew_zomap : HInst<
24323(outs),
24324(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24325"if (!$Pv4.new) memw($Rs32) = $Nt8.new",
24326tc_92240447, TypeMAPPING> {
24327let isPseudo = 1;
24328let isCodeGenOnly = 1;
24329let opNewValue = 2;
24330}
24331def S4_pstorerinewt_abs : HInst<
24332(outs),
24333(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24334"if ($Pv4) memw(#$Ii) = $Nt8.new",
24335tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24336let Inst{2-2} = 0b0;
24337let Inst{7-7} = 0b1;
24338let Inst{13-11} = 0b010;
24339let Inst{31-18} = 0b10101111101000;
24340let isPredicated = 1;
24341let addrMode = Absolute;
24342let accessSize = WordAccess;
24343let isNVStore = 1;
24344let isNewValue = 1;
24345let isExtended = 1;
24346let isRestrictNoSlot1Store = 1;
24347let mayStore = 1;
24348let BaseOpcode = "S2_storeriabs";
24349let CextOpcode = "S2_storeri";
24350let DecoderNamespace = "MustExtend";
24351let isExtendable = 1;
24352let opExtendable = 1;
24353let isExtentSigned = 0;
24354let opExtentBits = 6;
24355let opExtentAlign = 0;
24356let opNewValue = 2;
24357}
24358def S4_pstorerinewt_rr : HInst<
24359(outs),
24360(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24361"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24362tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24363let Inst{4-3} = 0b10;
24364let Inst{31-21} = 0b00110100101;
24365let isPredicated = 1;
24366let addrMode = BaseRegOffset;
24367let accessSize = WordAccess;
24368let isNVStore = 1;
24369let isNewValue = 1;
24370let isRestrictNoSlot1Store = 1;
24371let mayStore = 1;
24372let BaseOpcode = "S2_storeri_rr";
24373let CextOpcode = "S2_storeri";
24374let InputType = "reg";
24375let opNewValue = 4;
24376}
24377def S4_pstorerinewtnew_abs : HInst<
24378(outs),
24379(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24380"if ($Pv4.new) memw(#$Ii) = $Nt8.new",
24381tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24382let Inst{2-2} = 0b0;
24383let Inst{7-7} = 0b1;
24384let Inst{13-11} = 0b110;
24385let Inst{31-18} = 0b10101111101000;
24386let isPredicated = 1;
24387let addrMode = Absolute;
24388let accessSize = WordAccess;
24389let isNVStore = 1;
24390let isPredicatedNew = 1;
24391let isNewValue = 1;
24392let isExtended = 1;
24393let isRestrictNoSlot1Store = 1;
24394let mayStore = 1;
24395let BaseOpcode = "S2_storeriabs";
24396let CextOpcode = "S2_storeri";
24397let DecoderNamespace = "MustExtend";
24398let isExtendable = 1;
24399let opExtendable = 1;
24400let isExtentSigned = 0;
24401let opExtentBits = 6;
24402let opExtentAlign = 0;
24403let opNewValue = 2;
24404}
24405def S4_pstorerinewtnew_io : HInst<
24406(outs),
24407(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24408"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24409tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24410let Inst{2-2} = 0b0;
24411let Inst{12-11} = 0b10;
24412let Inst{31-21} = 0b01000010101;
24413let isPredicated = 1;
24414let addrMode = BaseImmOffset;
24415let accessSize = WordAccess;
24416let isNVStore = 1;
24417let isPredicatedNew = 1;
24418let isNewValue = 1;
24419let isRestrictNoSlot1Store = 1;
24420let mayStore = 1;
24421let BaseOpcode = "S2_storeri_io";
24422let CextOpcode = "S2_storeri";
24423let InputType = "imm";
24424let isExtendable = 1;
24425let opExtendable = 2;
24426let isExtentSigned = 0;
24427let opExtentBits = 8;
24428let opExtentAlign = 2;
24429let opNewValue = 3;
24430}
24431def S4_pstorerinewtnew_rr : HInst<
24432(outs),
24433(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24434"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24435tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24436let Inst{4-3} = 0b10;
24437let Inst{31-21} = 0b00110110101;
24438let isPredicated = 1;
24439let addrMode = BaseRegOffset;
24440let accessSize = WordAccess;
24441let isNVStore = 1;
24442let isPredicatedNew = 1;
24443let isNewValue = 1;
24444let isRestrictNoSlot1Store = 1;
24445let mayStore = 1;
24446let BaseOpcode = "S2_storeri_rr";
24447let CextOpcode = "S2_storeri";
24448let InputType = "reg";
24449let opNewValue = 4;
24450}
24451def S4_pstorerinewtnew_zomap : HInst<
24452(outs),
24453(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24454"if ($Pv4.new) memw($Rs32) = $Nt8.new",
24455tc_92240447, TypeMAPPING> {
24456let isPseudo = 1;
24457let isCodeGenOnly = 1;
24458let opNewValue = 2;
24459}
24460def S4_pstorerit_abs : HInst<
24461(outs),
24462(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24463"if ($Pv4) memw(#$Ii) = $Rt32",
24464tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24465let Inst{2-2} = 0b0;
24466let Inst{7-7} = 0b1;
24467let Inst{13-13} = 0b0;
24468let Inst{31-18} = 0b10101111100000;
24469let isPredicated = 1;
24470let addrMode = Absolute;
24471let accessSize = WordAccess;
24472let isExtended = 1;
24473let mayStore = 1;
24474let BaseOpcode = "S2_storeriabs";
24475let CextOpcode = "S2_storeri";
24476let isNVStorable = 1;
24477let DecoderNamespace = "MustExtend";
24478let isExtendable = 1;
24479let opExtendable = 1;
24480let isExtentSigned = 0;
24481let opExtentBits = 6;
24482let opExtentAlign = 0;
24483}
24484def S4_pstorerit_rr : HInst<
24485(outs),
24486(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24487"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24488tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24489let Inst{31-21} = 0b00110100100;
24490let isPredicated = 1;
24491let addrMode = BaseRegOffset;
24492let accessSize = WordAccess;
24493let mayStore = 1;
24494let BaseOpcode = "S2_storeri_rr";
24495let CextOpcode = "S2_storeri";
24496let InputType = "reg";
24497let isNVStorable = 1;
24498}
24499def S4_pstoreritnew_abs : HInst<
24500(outs),
24501(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24502"if ($Pv4.new) memw(#$Ii) = $Rt32",
24503tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24504let Inst{2-2} = 0b0;
24505let Inst{7-7} = 0b1;
24506let Inst{13-13} = 0b1;
24507let Inst{31-18} = 0b10101111100000;
24508let isPredicated = 1;
24509let addrMode = Absolute;
24510let accessSize = WordAccess;
24511let isPredicatedNew = 1;
24512let isExtended = 1;
24513let mayStore = 1;
24514let BaseOpcode = "S2_storeriabs";
24515let CextOpcode = "S2_storeri";
24516let isNVStorable = 1;
24517let DecoderNamespace = "MustExtend";
24518let isExtendable = 1;
24519let opExtendable = 1;
24520let isExtentSigned = 0;
24521let opExtentBits = 6;
24522let opExtentAlign = 0;
24523}
24524def S4_pstoreritnew_io : HInst<
24525(outs),
24526(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24527"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24528tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24529let Inst{2-2} = 0b0;
24530let Inst{31-21} = 0b01000010100;
24531let isPredicated = 1;
24532let addrMode = BaseImmOffset;
24533let accessSize = WordAccess;
24534let isPredicatedNew = 1;
24535let mayStore = 1;
24536let BaseOpcode = "S2_storeri_io";
24537let CextOpcode = "S2_storeri";
24538let InputType = "imm";
24539let isNVStorable = 1;
24540let isExtendable = 1;
24541let opExtendable = 2;
24542let isExtentSigned = 0;
24543let opExtentBits = 8;
24544let opExtentAlign = 2;
24545}
24546def S4_pstoreritnew_rr : HInst<
24547(outs),
24548(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24549"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24550tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24551let Inst{31-21} = 0b00110110100;
24552let isPredicated = 1;
24553let addrMode = BaseRegOffset;
24554let accessSize = WordAccess;
24555let isPredicatedNew = 1;
24556let mayStore = 1;
24557let BaseOpcode = "S2_storeri_rr";
24558let CextOpcode = "S2_storeri";
24559let InputType = "reg";
24560let isNVStorable = 1;
24561}
24562def S4_pstoreritnew_zomap : HInst<
24563(outs),
24564(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24565"if ($Pv4.new) memw($Rs32) = $Rt32",
24566tc_a2b365d2, TypeMAPPING> {
24567let isPseudo = 1;
24568let isCodeGenOnly = 1;
24569}
24570def S4_stored_locked : HInst<
24571(outs PredRegs:$Pd4),
24572(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24573"memd_locked($Rs32,$Pd4) = $Rtt32",
24574tc_6f42bc60, TypeST>, Enc_d7dc10 {
24575let Inst{7-2} = 0b000000;
24576let Inst{13-13} = 0b0;
24577let Inst{31-21} = 0b10100000111;
24578let accessSize = DoubleWordAccess;
24579let isPredicateLate = 1;
24580let isSoloAX = 1;
24581let mayStore = 1;
24582}
24583def S4_stored_rl_at_vi : HInst<
24584(outs),
24585(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24586"memd_rl($Rs32):at = $Rtt32",
24587tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24588let Inst{7-2} = 0b000010;
24589let Inst{13-13} = 0b0;
24590let Inst{31-21} = 0b10100000111;
24591let accessSize = DoubleWordAccess;
24592let isSolo = 1;
24593let mayStore = 1;
24594}
24595def S4_stored_rl_st_vi : HInst<
24596(outs),
24597(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24598"memd_rl($Rs32):st = $Rtt32",
24599tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24600let Inst{7-2} = 0b001010;
24601let Inst{13-13} = 0b0;
24602let Inst{31-21} = 0b10100000111;
24603let accessSize = DoubleWordAccess;
24604let isSolo = 1;
24605let mayStore = 1;
24606}
24607def S4_storeirb_io : HInst<
24608(outs),
24609(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24610"memb($Rs32+#$Ii) = #$II",
24611tc_7c31e19a, TypeST>, Enc_8203bb, PredNewRel {
24612let Inst{31-21} = 0b00111100000;
24613let addrMode = BaseImmOffset;
24614let accessSize = ByteAccess;
24615let mayStore = 1;
24616let BaseOpcode = "S4_storeirb_io";
24617let CextOpcode = "S2_storerb";
24618let InputType = "imm";
24619let isPredicable = 1;
24620let isExtendable = 1;
24621let opExtendable = 2;
24622let isExtentSigned = 1;
24623let opExtentBits = 8;
24624let opExtentAlign = 0;
24625}
24626def S4_storeirb_zomap : HInst<
24627(outs),
24628(ins IntRegs:$Rs32, s8_0Imm:$II),
24629"memb($Rs32) = #$II",
24630tc_7c31e19a, TypeMAPPING> {
24631let isPseudo = 1;
24632let isCodeGenOnly = 1;
24633}
24634def S4_storeirbf_io : HInst<
24635(outs),
24636(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24637"if (!$Pv4) memb($Rs32+#$Ii) = #$II",
24638tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24639let Inst{31-21} = 0b00111000100;
24640let isPredicated = 1;
24641let isPredicatedFalse = 1;
24642let addrMode = BaseImmOffset;
24643let accessSize = ByteAccess;
24644let mayStore = 1;
24645let BaseOpcode = "S4_storeirb_io";
24646let CextOpcode = "S2_storerb";
24647let InputType = "imm";
24648let isExtendable = 1;
24649let opExtendable = 3;
24650let isExtentSigned = 1;
24651let opExtentBits = 6;
24652let opExtentAlign = 0;
24653}
24654def S4_storeirbf_zomap : HInst<
24655(outs),
24656(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24657"if (!$Pv4) memb($Rs32) = #$II",
24658tc_d03278fd, TypeMAPPING> {
24659let isPseudo = 1;
24660let isCodeGenOnly = 1;
24661}
24662def S4_storeirbfnew_io : HInst<
24663(outs),
24664(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24665"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
24666tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24667let Inst{31-21} = 0b00111001100;
24668let isPredicated = 1;
24669let isPredicatedFalse = 1;
24670let addrMode = BaseImmOffset;
24671let accessSize = ByteAccess;
24672let isPredicatedNew = 1;
24673let mayStore = 1;
24674let BaseOpcode = "S4_storeirb_io";
24675let CextOpcode = "S2_storerb";
24676let InputType = "imm";
24677let isExtendable = 1;
24678let opExtendable = 3;
24679let isExtentSigned = 1;
24680let opExtentBits = 6;
24681let opExtentAlign = 0;
24682}
24683def S4_storeirbfnew_zomap : HInst<
24684(outs),
24685(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24686"if (!$Pv4.new) memb($Rs32) = #$II",
24687tc_65cbd974, TypeMAPPING> {
24688let isPseudo = 1;
24689let isCodeGenOnly = 1;
24690}
24691def S4_storeirbt_io : HInst<
24692(outs),
24693(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24694"if ($Pv4) memb($Rs32+#$Ii) = #$II",
24695tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24696let Inst{31-21} = 0b00111000000;
24697let isPredicated = 1;
24698let addrMode = BaseImmOffset;
24699let accessSize = ByteAccess;
24700let mayStore = 1;
24701let BaseOpcode = "S4_storeirb_io";
24702let CextOpcode = "S2_storerb";
24703let InputType = "imm";
24704let isExtendable = 1;
24705let opExtendable = 3;
24706let isExtentSigned = 1;
24707let opExtentBits = 6;
24708let opExtentAlign = 0;
24709}
24710def S4_storeirbt_zomap : HInst<
24711(outs),
24712(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24713"if ($Pv4) memb($Rs32) = #$II",
24714tc_d03278fd, TypeMAPPING> {
24715let isPseudo = 1;
24716let isCodeGenOnly = 1;
24717}
24718def S4_storeirbtnew_io : HInst<
24719(outs),
24720(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24721"if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
24722tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24723let Inst{31-21} = 0b00111001000;
24724let isPredicated = 1;
24725let addrMode = BaseImmOffset;
24726let accessSize = ByteAccess;
24727let isPredicatedNew = 1;
24728let mayStore = 1;
24729let BaseOpcode = "S4_storeirb_io";
24730let CextOpcode = "S2_storerb";
24731let InputType = "imm";
24732let isExtendable = 1;
24733let opExtendable = 3;
24734let isExtentSigned = 1;
24735let opExtentBits = 6;
24736let opExtentAlign = 0;
24737}
24738def S4_storeirbtnew_zomap : HInst<
24739(outs),
24740(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24741"if ($Pv4.new) memb($Rs32) = #$II",
24742tc_65cbd974, TypeMAPPING> {
24743let isPseudo = 1;
24744let isCodeGenOnly = 1;
24745}
24746def S4_storeirh_io : HInst<
24747(outs),
24748(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24749"memh($Rs32+#$Ii) = #$II",
24750tc_7c31e19a, TypeST>, Enc_a803e0, PredNewRel {
24751let Inst{31-21} = 0b00111100001;
24752let addrMode = BaseImmOffset;
24753let accessSize = HalfWordAccess;
24754let mayStore = 1;
24755let BaseOpcode = "S4_storeirh_io";
24756let CextOpcode = "S2_storerh";
24757let InputType = "imm";
24758let isPredicable = 1;
24759let isExtendable = 1;
24760let opExtendable = 2;
24761let isExtentSigned = 1;
24762let opExtentBits = 8;
24763let opExtentAlign = 0;
24764}
24765def S4_storeirh_zomap : HInst<
24766(outs),
24767(ins IntRegs:$Rs32, s8_0Imm:$II),
24768"memh($Rs32) = #$II",
24769tc_7c31e19a, TypeMAPPING> {
24770let isPseudo = 1;
24771let isCodeGenOnly = 1;
24772}
24773def S4_storeirhf_io : HInst<
24774(outs),
24775(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24776"if (!$Pv4) memh($Rs32+#$Ii) = #$II",
24777tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24778let Inst{31-21} = 0b00111000101;
24779let isPredicated = 1;
24780let isPredicatedFalse = 1;
24781let addrMode = BaseImmOffset;
24782let accessSize = HalfWordAccess;
24783let mayStore = 1;
24784let BaseOpcode = "S4_storeirh_io";
24785let CextOpcode = "S2_storerh";
24786let InputType = "imm";
24787let isExtendable = 1;
24788let opExtendable = 3;
24789let isExtentSigned = 1;
24790let opExtentBits = 6;
24791let opExtentAlign = 0;
24792}
24793def S4_storeirhf_zomap : HInst<
24794(outs),
24795(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24796"if (!$Pv4) memh($Rs32) = #$II",
24797tc_d03278fd, TypeMAPPING> {
24798let isPseudo = 1;
24799let isCodeGenOnly = 1;
24800}
24801def S4_storeirhfnew_io : HInst<
24802(outs),
24803(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24804"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
24805tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24806let Inst{31-21} = 0b00111001101;
24807let isPredicated = 1;
24808let isPredicatedFalse = 1;
24809let addrMode = BaseImmOffset;
24810let accessSize = HalfWordAccess;
24811let isPredicatedNew = 1;
24812let mayStore = 1;
24813let BaseOpcode = "S4_storeirh_io";
24814let CextOpcode = "S2_storerh";
24815let InputType = "imm";
24816let isExtendable = 1;
24817let opExtendable = 3;
24818let isExtentSigned = 1;
24819let opExtentBits = 6;
24820let opExtentAlign = 0;
24821}
24822def S4_storeirhfnew_zomap : HInst<
24823(outs),
24824(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24825"if (!$Pv4.new) memh($Rs32) = #$II",
24826tc_65cbd974, TypeMAPPING> {
24827let isPseudo = 1;
24828let isCodeGenOnly = 1;
24829}
24830def S4_storeirht_io : HInst<
24831(outs),
24832(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24833"if ($Pv4) memh($Rs32+#$Ii) = #$II",
24834tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24835let Inst{31-21} = 0b00111000001;
24836let isPredicated = 1;
24837let addrMode = BaseImmOffset;
24838let accessSize = HalfWordAccess;
24839let mayStore = 1;
24840let BaseOpcode = "S4_storeirh_io";
24841let CextOpcode = "S2_storerh";
24842let InputType = "imm";
24843let isExtendable = 1;
24844let opExtendable = 3;
24845let isExtentSigned = 1;
24846let opExtentBits = 6;
24847let opExtentAlign = 0;
24848}
24849def S4_storeirht_zomap : HInst<
24850(outs),
24851(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24852"if ($Pv4) memh($Rs32) = #$II",
24853tc_d03278fd, TypeMAPPING> {
24854let isPseudo = 1;
24855let isCodeGenOnly = 1;
24856}
24857def S4_storeirhtnew_io : HInst<
24858(outs),
24859(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24860"if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
24861tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24862let Inst{31-21} = 0b00111001001;
24863let isPredicated = 1;
24864let addrMode = BaseImmOffset;
24865let accessSize = HalfWordAccess;
24866let isPredicatedNew = 1;
24867let mayStore = 1;
24868let BaseOpcode = "S4_storeirh_io";
24869let CextOpcode = "S2_storerh";
24870let InputType = "imm";
24871let isExtendable = 1;
24872let opExtendable = 3;
24873let isExtentSigned = 1;
24874let opExtentBits = 6;
24875let opExtentAlign = 0;
24876}
24877def S4_storeirhtnew_zomap : HInst<
24878(outs),
24879(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24880"if ($Pv4.new) memh($Rs32) = #$II",
24881tc_65cbd974, TypeMAPPING> {
24882let isPseudo = 1;
24883let isCodeGenOnly = 1;
24884}
24885def S4_storeiri_io : HInst<
24886(outs),
24887(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24888"memw($Rs32+#$Ii) = #$II",
24889tc_7c31e19a, TypeST>, Enc_f37377, PredNewRel {
24890let Inst{31-21} = 0b00111100010;
24891let addrMode = BaseImmOffset;
24892let accessSize = WordAccess;
24893let mayStore = 1;
24894let BaseOpcode = "S4_storeiri_io";
24895let CextOpcode = "S2_storeri";
24896let InputType = "imm";
24897let isPredicable = 1;
24898let isExtendable = 1;
24899let opExtendable = 2;
24900let isExtentSigned = 1;
24901let opExtentBits = 8;
24902let opExtentAlign = 0;
24903}
24904def S4_storeiri_zomap : HInst<
24905(outs),
24906(ins IntRegs:$Rs32, s8_0Imm:$II),
24907"memw($Rs32) = #$II",
24908tc_7c31e19a, TypeMAPPING> {
24909let isPseudo = 1;
24910let isCodeGenOnly = 1;
24911}
24912def S4_storeirif_io : HInst<
24913(outs),
24914(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24915"if (!$Pv4) memw($Rs32+#$Ii) = #$II",
24916tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24917let Inst{31-21} = 0b00111000110;
24918let isPredicated = 1;
24919let isPredicatedFalse = 1;
24920let addrMode = BaseImmOffset;
24921let accessSize = WordAccess;
24922let mayStore = 1;
24923let BaseOpcode = "S4_storeiri_io";
24924let CextOpcode = "S2_storeri";
24925let InputType = "imm";
24926let isExtendable = 1;
24927let opExtendable = 3;
24928let isExtentSigned = 1;
24929let opExtentBits = 6;
24930let opExtentAlign = 0;
24931}
24932def S4_storeirif_zomap : HInst<
24933(outs),
24934(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24935"if (!$Pv4) memw($Rs32) = #$II",
24936tc_d03278fd, TypeMAPPING> {
24937let isPseudo = 1;
24938let isCodeGenOnly = 1;
24939}
24940def S4_storeirifnew_io : HInst<
24941(outs),
24942(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24943"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
24944tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
24945let Inst{31-21} = 0b00111001110;
24946let isPredicated = 1;
24947let isPredicatedFalse = 1;
24948let addrMode = BaseImmOffset;
24949let accessSize = WordAccess;
24950let isPredicatedNew = 1;
24951let mayStore = 1;
24952let BaseOpcode = "S4_storeiri_io";
24953let CextOpcode = "S2_storeri";
24954let InputType = "imm";
24955let isExtendable = 1;
24956let opExtendable = 3;
24957let isExtentSigned = 1;
24958let opExtentBits = 6;
24959let opExtentAlign = 0;
24960}
24961def S4_storeirifnew_zomap : HInst<
24962(outs),
24963(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24964"if (!$Pv4.new) memw($Rs32) = #$II",
24965tc_65cbd974, TypeMAPPING> {
24966let isPseudo = 1;
24967let isCodeGenOnly = 1;
24968}
24969def S4_storeirit_io : HInst<
24970(outs),
24971(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24972"if ($Pv4) memw($Rs32+#$Ii) = #$II",
24973tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24974let Inst{31-21} = 0b00111000010;
24975let isPredicated = 1;
24976let addrMode = BaseImmOffset;
24977let accessSize = WordAccess;
24978let mayStore = 1;
24979let BaseOpcode = "S4_storeiri_io";
24980let CextOpcode = "S2_storeri";
24981let InputType = "imm";
24982let isExtendable = 1;
24983let opExtendable = 3;
24984let isExtentSigned = 1;
24985let opExtentBits = 6;
24986let opExtentAlign = 0;
24987}
24988def S4_storeirit_zomap : HInst<
24989(outs),
24990(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24991"if ($Pv4) memw($Rs32) = #$II",
24992tc_d03278fd, TypeMAPPING> {
24993let isPseudo = 1;
24994let isCodeGenOnly = 1;
24995}
24996def S4_storeiritnew_io : HInst<
24997(outs),
24998(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24999"if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
25000tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
25001let Inst{31-21} = 0b00111001010;
25002let isPredicated = 1;
25003let addrMode = BaseImmOffset;
25004let accessSize = WordAccess;
25005let isPredicatedNew = 1;
25006let mayStore = 1;
25007let BaseOpcode = "S4_storeiri_io";
25008let CextOpcode = "S2_storeri";
25009let InputType = "imm";
25010let isExtendable = 1;
25011let opExtendable = 3;
25012let isExtentSigned = 1;
25013let opExtentBits = 6;
25014let opExtentAlign = 0;
25015}
25016def S4_storeiritnew_zomap : HInst<
25017(outs),
25018(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
25019"if ($Pv4.new) memw($Rs32) = #$II",
25020tc_65cbd974, TypeMAPPING> {
25021let isPseudo = 1;
25022let isCodeGenOnly = 1;
25023}
25024def S4_storerb_ap : HInst<
25025(outs IntRegs:$Re32),
25026(ins u32_0Imm:$II, IntRegs:$Rt32),
25027"memb($Re32=#$II) = $Rt32",
25028tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25029let Inst{7-6} = 0b10;
25030let Inst{13-13} = 0b0;
25031let Inst{31-21} = 0b10101011000;
25032let addrMode = AbsoluteSet;
25033let accessSize = ByteAccess;
25034let isExtended = 1;
25035let mayStore = 1;
25036let BaseOpcode = "S2_storerb_ap";
25037let isNVStorable = 1;
25038let DecoderNamespace = "MustExtend";
25039let isExtendable = 1;
25040let opExtendable = 1;
25041let isExtentSigned = 0;
25042let opExtentBits = 6;
25043let opExtentAlign = 0;
25044}
25045def S4_storerb_rr : HInst<
25046(outs),
25047(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25048"memb($Rs32+$Ru32<<#$Ii) = $Rt32",
25049tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25050let Inst{6-5} = 0b00;
25051let Inst{31-21} = 0b00111011000;
25052let addrMode = BaseRegOffset;
25053let accessSize = ByteAccess;
25054let mayStore = 1;
25055let BaseOpcode = "S4_storerb_rr";
25056let CextOpcode = "S2_storerb";
25057let InputType = "reg";
25058let isNVStorable = 1;
25059let isPredicable = 1;
25060}
25061def S4_storerb_ur : HInst<
25062(outs),
25063(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25064"memb($Ru32<<#$Ii+#$II) = $Rt32",
25065tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25066let Inst{7-7} = 0b1;
25067let Inst{31-21} = 0b10101101000;
25068let addrMode = BaseLongOffset;
25069let accessSize = ByteAccess;
25070let isExtended = 1;
25071let mayStore = 1;
25072let BaseOpcode = "S4_storerb_ur";
25073let CextOpcode = "S2_storerb";
25074let InputType = "imm";
25075let isNVStorable = 1;
25076let DecoderNamespace = "MustExtend";
25077let isExtendable = 1;
25078let opExtendable = 2;
25079let isExtentSigned = 0;
25080let opExtentBits = 6;
25081let opExtentAlign = 0;
25082}
25083def S4_storerbnew_ap : HInst<
25084(outs IntRegs:$Re32),
25085(ins u32_0Imm:$II, IntRegs:$Nt8),
25086"memb($Re32=#$II) = $Nt8.new",
25087tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25088let Inst{7-6} = 0b10;
25089let Inst{13-11} = 0b000;
25090let Inst{31-21} = 0b10101011101;
25091let addrMode = AbsoluteSet;
25092let accessSize = ByteAccess;
25093let isNVStore = 1;
25094let isNewValue = 1;
25095let isExtended = 1;
25096let isRestrictNoSlot1Store = 1;
25097let mayStore = 1;
25098let BaseOpcode = "S2_storerb_ap";
25099let DecoderNamespace = "MustExtend";
25100let isExtendable = 1;
25101let opExtendable = 1;
25102let isExtentSigned = 0;
25103let opExtentBits = 6;
25104let opExtentAlign = 0;
25105let opNewValue = 2;
25106}
25107def S4_storerbnew_rr : HInst<
25108(outs),
25109(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25110"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25111tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25112let Inst{6-3} = 0b0000;
25113let Inst{31-21} = 0b00111011101;
25114let addrMode = BaseRegOffset;
25115let accessSize = ByteAccess;
25116let isNVStore = 1;
25117let isNewValue = 1;
25118let isRestrictNoSlot1Store = 1;
25119let mayStore = 1;
25120let BaseOpcode = "S4_storerb_rr";
25121let CextOpcode = "S2_storerb";
25122let InputType = "reg";
25123let isPredicable = 1;
25124let opNewValue = 3;
25125}
25126def S4_storerbnew_ur : HInst<
25127(outs),
25128(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25129"memb($Ru32<<#$Ii+#$II) = $Nt8.new",
25130tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25131let Inst{7-7} = 0b1;
25132let Inst{12-11} = 0b00;
25133let Inst{31-21} = 0b10101101101;
25134let addrMode = BaseLongOffset;
25135let accessSize = ByteAccess;
25136let isNVStore = 1;
25137let isNewValue = 1;
25138let isExtended = 1;
25139let isRestrictNoSlot1Store = 1;
25140let mayStore = 1;
25141let BaseOpcode = "S4_storerb_ur";
25142let CextOpcode = "S2_storerb";
25143let DecoderNamespace = "MustExtend";
25144let isExtendable = 1;
25145let opExtendable = 2;
25146let isExtentSigned = 0;
25147let opExtentBits = 6;
25148let opExtentAlign = 0;
25149let opNewValue = 3;
25150}
25151def S4_storerd_ap : HInst<
25152(outs IntRegs:$Re32),
25153(ins u32_0Imm:$II, DoubleRegs:$Rtt32),
25154"memd($Re32=#$II) = $Rtt32",
25155tc_bb07f2c5, TypeST>, Enc_c7a204 {
25156let Inst{7-6} = 0b10;
25157let Inst{13-13} = 0b0;
25158let Inst{31-21} = 0b10101011110;
25159let addrMode = AbsoluteSet;
25160let accessSize = DoubleWordAccess;
25161let isExtended = 1;
25162let mayStore = 1;
25163let BaseOpcode = "S4_storerd_ap";
25164let DecoderNamespace = "MustExtend";
25165let isExtendable = 1;
25166let opExtendable = 1;
25167let isExtentSigned = 0;
25168let opExtentBits = 6;
25169let opExtentAlign = 0;
25170}
25171def S4_storerd_rr : HInst<
25172(outs),
25173(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
25174"memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
25175tc_280f7fe1, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
25176let Inst{6-5} = 0b00;
25177let Inst{31-21} = 0b00111011110;
25178let addrMode = BaseRegOffset;
25179let accessSize = DoubleWordAccess;
25180let mayStore = 1;
25181let BaseOpcode = "S2_storerd_rr";
25182let CextOpcode = "S2_storerd";
25183let InputType = "reg";
25184let isPredicable = 1;
25185}
25186def S4_storerd_ur : HInst<
25187(outs),
25188(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
25189"memd($Ru32<<#$Ii+#$II) = $Rtt32",
25190tc_887d1bb7, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
25191let Inst{7-7} = 0b1;
25192let Inst{31-21} = 0b10101101110;
25193let addrMode = BaseLongOffset;
25194let accessSize = DoubleWordAccess;
25195let isExtended = 1;
25196let mayStore = 1;
25197let BaseOpcode = "S2_storerd_ur";
25198let CextOpcode = "S2_storerd";
25199let InputType = "imm";
25200let DecoderNamespace = "MustExtend";
25201let isExtendable = 1;
25202let opExtendable = 2;
25203let isExtentSigned = 0;
25204let opExtentBits = 6;
25205let opExtentAlign = 0;
25206}
25207def S4_storerf_ap : HInst<
25208(outs IntRegs:$Re32),
25209(ins u32_0Imm:$II, IntRegs:$Rt32),
25210"memh($Re32=#$II) = $Rt32.h",
25211tc_bb07f2c5, TypeST>, Enc_8bcba4 {
25212let Inst{7-6} = 0b10;
25213let Inst{13-13} = 0b0;
25214let Inst{31-21} = 0b10101011011;
25215let addrMode = AbsoluteSet;
25216let accessSize = HalfWordAccess;
25217let isExtended = 1;
25218let mayStore = 1;
25219let BaseOpcode = "S4_storerf_ap";
25220let DecoderNamespace = "MustExtend";
25221let isExtendable = 1;
25222let opExtendable = 1;
25223let isExtentSigned = 0;
25224let opExtentBits = 6;
25225let opExtentAlign = 0;
25226}
25227def S4_storerf_rr : HInst<
25228(outs),
25229(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25230"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
25231tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25232let Inst{6-5} = 0b00;
25233let Inst{31-21} = 0b00111011011;
25234let addrMode = BaseRegOffset;
25235let accessSize = HalfWordAccess;
25236let mayStore = 1;
25237let BaseOpcode = "S4_storerf_rr";
25238let CextOpcode = "S2_storerf";
25239let InputType = "reg";
25240let isPredicable = 1;
25241}
25242def S4_storerf_ur : HInst<
25243(outs),
25244(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25245"memh($Ru32<<#$Ii+#$II) = $Rt32.h",
25246tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25247let Inst{7-7} = 0b1;
25248let Inst{31-21} = 0b10101101011;
25249let addrMode = BaseLongOffset;
25250let accessSize = HalfWordAccess;
25251let isExtended = 1;
25252let mayStore = 1;
25253let BaseOpcode = "S4_storerf_rr";
25254let CextOpcode = "S2_storerf";
25255let InputType = "imm";
25256let DecoderNamespace = "MustExtend";
25257let isExtendable = 1;
25258let opExtendable = 2;
25259let isExtentSigned = 0;
25260let opExtentBits = 6;
25261let opExtentAlign = 0;
25262}
25263def S4_storerh_ap : HInst<
25264(outs IntRegs:$Re32),
25265(ins u32_0Imm:$II, IntRegs:$Rt32),
25266"memh($Re32=#$II) = $Rt32",
25267tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25268let Inst{7-6} = 0b10;
25269let Inst{13-13} = 0b0;
25270let Inst{31-21} = 0b10101011010;
25271let addrMode = AbsoluteSet;
25272let accessSize = HalfWordAccess;
25273let isExtended = 1;
25274let mayStore = 1;
25275let BaseOpcode = "S2_storerh_ap";
25276let isNVStorable = 1;
25277let DecoderNamespace = "MustExtend";
25278let isExtendable = 1;
25279let opExtendable = 1;
25280let isExtentSigned = 0;
25281let opExtentBits = 6;
25282let opExtentAlign = 0;
25283}
25284def S4_storerh_rr : HInst<
25285(outs),
25286(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25287"memh($Rs32+$Ru32<<#$Ii) = $Rt32",
25288tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25289let Inst{6-5} = 0b00;
25290let Inst{31-21} = 0b00111011010;
25291let addrMode = BaseRegOffset;
25292let accessSize = HalfWordAccess;
25293let mayStore = 1;
25294let BaseOpcode = "S2_storerh_rr";
25295let CextOpcode = "S2_storerh";
25296let InputType = "reg";
25297let isNVStorable = 1;
25298let isPredicable = 1;
25299}
25300def S4_storerh_ur : HInst<
25301(outs),
25302(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25303"memh($Ru32<<#$Ii+#$II) = $Rt32",
25304tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25305let Inst{7-7} = 0b1;
25306let Inst{31-21} = 0b10101101010;
25307let addrMode = BaseLongOffset;
25308let accessSize = HalfWordAccess;
25309let isExtended = 1;
25310let mayStore = 1;
25311let BaseOpcode = "S2_storerh_ur";
25312let CextOpcode = "S2_storerh";
25313let InputType = "imm";
25314let isNVStorable = 1;
25315let DecoderNamespace = "MustExtend";
25316let isExtendable = 1;
25317let opExtendable = 2;
25318let isExtentSigned = 0;
25319let opExtentBits = 6;
25320let opExtentAlign = 0;
25321}
25322def S4_storerhnew_ap : HInst<
25323(outs IntRegs:$Re32),
25324(ins u32_0Imm:$II, IntRegs:$Nt8),
25325"memh($Re32=#$II) = $Nt8.new",
25326tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25327let Inst{7-6} = 0b10;
25328let Inst{13-11} = 0b001;
25329let Inst{31-21} = 0b10101011101;
25330let addrMode = AbsoluteSet;
25331let accessSize = HalfWordAccess;
25332let isNVStore = 1;
25333let isNewValue = 1;
25334let isExtended = 1;
25335let isRestrictNoSlot1Store = 1;
25336let mayStore = 1;
25337let BaseOpcode = "S2_storerh_ap";
25338let DecoderNamespace = "MustExtend";
25339let isExtendable = 1;
25340let opExtendable = 1;
25341let isExtentSigned = 0;
25342let opExtentBits = 6;
25343let opExtentAlign = 0;
25344let opNewValue = 2;
25345}
25346def S4_storerhnew_rr : HInst<
25347(outs),
25348(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25349"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25350tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25351let Inst{6-3} = 0b0001;
25352let Inst{31-21} = 0b00111011101;
25353let addrMode = BaseRegOffset;
25354let accessSize = HalfWordAccess;
25355let isNVStore = 1;
25356let isNewValue = 1;
25357let isRestrictNoSlot1Store = 1;
25358let mayStore = 1;
25359let BaseOpcode = "S2_storerh_rr";
25360let CextOpcode = "S2_storerh";
25361let InputType = "reg";
25362let isPredicable = 1;
25363let opNewValue = 3;
25364}
25365def S4_storerhnew_ur : HInst<
25366(outs),
25367(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25368"memh($Ru32<<#$Ii+#$II) = $Nt8.new",
25369tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25370let Inst{7-7} = 0b1;
25371let Inst{12-11} = 0b01;
25372let Inst{31-21} = 0b10101101101;
25373let addrMode = BaseLongOffset;
25374let accessSize = HalfWordAccess;
25375let isNVStore = 1;
25376let isNewValue = 1;
25377let isExtended = 1;
25378let isRestrictNoSlot1Store = 1;
25379let mayStore = 1;
25380let BaseOpcode = "S2_storerh_ur";
25381let CextOpcode = "S2_storerh";
25382let DecoderNamespace = "MustExtend";
25383let isExtendable = 1;
25384let opExtendable = 2;
25385let isExtentSigned = 0;
25386let opExtentBits = 6;
25387let opExtentAlign = 0;
25388let opNewValue = 3;
25389}
25390def S4_storeri_ap : HInst<
25391(outs IntRegs:$Re32),
25392(ins u32_0Imm:$II, IntRegs:$Rt32),
25393"memw($Re32=#$II) = $Rt32",
25394tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25395let Inst{7-6} = 0b10;
25396let Inst{13-13} = 0b0;
25397let Inst{31-21} = 0b10101011100;
25398let addrMode = AbsoluteSet;
25399let accessSize = WordAccess;
25400let isExtended = 1;
25401let mayStore = 1;
25402let BaseOpcode = "S2_storeri_ap";
25403let isNVStorable = 1;
25404let DecoderNamespace = "MustExtend";
25405let isExtendable = 1;
25406let opExtendable = 1;
25407let isExtentSigned = 0;
25408let opExtentBits = 6;
25409let opExtentAlign = 0;
25410}
25411def S4_storeri_rr : HInst<
25412(outs),
25413(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25414"memw($Rs32+$Ru32<<#$Ii) = $Rt32",
25415tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25416let Inst{6-5} = 0b00;
25417let Inst{31-21} = 0b00111011100;
25418let addrMode = BaseRegOffset;
25419let accessSize = WordAccess;
25420let mayStore = 1;
25421let BaseOpcode = "S2_storeri_rr";
25422let CextOpcode = "S2_storeri";
25423let InputType = "reg";
25424let isNVStorable = 1;
25425let isPredicable = 1;
25426}
25427def S4_storeri_ur : HInst<
25428(outs),
25429(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25430"memw($Ru32<<#$Ii+#$II) = $Rt32",
25431tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25432let Inst{7-7} = 0b1;
25433let Inst{31-21} = 0b10101101100;
25434let addrMode = BaseLongOffset;
25435let accessSize = WordAccess;
25436let isExtended = 1;
25437let mayStore = 1;
25438let BaseOpcode = "S2_storeri_ur";
25439let CextOpcode = "S2_storeri";
25440let InputType = "imm";
25441let isNVStorable = 1;
25442let DecoderNamespace = "MustExtend";
25443let isExtendable = 1;
25444let opExtendable = 2;
25445let isExtentSigned = 0;
25446let opExtentBits = 6;
25447let opExtentAlign = 0;
25448}
25449def S4_storerinew_ap : HInst<
25450(outs IntRegs:$Re32),
25451(ins u32_0Imm:$II, IntRegs:$Nt8),
25452"memw($Re32=#$II) = $Nt8.new",
25453tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25454let Inst{7-6} = 0b10;
25455let Inst{13-11} = 0b010;
25456let Inst{31-21} = 0b10101011101;
25457let addrMode = AbsoluteSet;
25458let accessSize = WordAccess;
25459let isNVStore = 1;
25460let isNewValue = 1;
25461let isExtended = 1;
25462let isRestrictNoSlot1Store = 1;
25463let mayStore = 1;
25464let BaseOpcode = "S2_storeri_ap";
25465let DecoderNamespace = "MustExtend";
25466let isExtendable = 1;
25467let opExtendable = 1;
25468let isExtentSigned = 0;
25469let opExtentBits = 6;
25470let opExtentAlign = 0;
25471let opNewValue = 2;
25472}
25473def S4_storerinew_rr : HInst<
25474(outs),
25475(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25476"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25477tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25478let Inst{6-3} = 0b0010;
25479let Inst{31-21} = 0b00111011101;
25480let addrMode = BaseRegOffset;
25481let accessSize = WordAccess;
25482let isNVStore = 1;
25483let isNewValue = 1;
25484let isRestrictNoSlot1Store = 1;
25485let mayStore = 1;
25486let BaseOpcode = "S2_storeri_rr";
25487let CextOpcode = "S2_storeri";
25488let InputType = "reg";
25489let isPredicable = 1;
25490let opNewValue = 3;
25491}
25492def S4_storerinew_ur : HInst<
25493(outs),
25494(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25495"memw($Ru32<<#$Ii+#$II) = $Nt8.new",
25496tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25497let Inst{7-7} = 0b1;
25498let Inst{12-11} = 0b10;
25499let Inst{31-21} = 0b10101101101;
25500let addrMode = BaseLongOffset;
25501let accessSize = WordAccess;
25502let isNVStore = 1;
25503let isNewValue = 1;
25504let isExtended = 1;
25505let isRestrictNoSlot1Store = 1;
25506let mayStore = 1;
25507let BaseOpcode = "S2_storeri_ur";
25508let CextOpcode = "S2_storeri";
25509let DecoderNamespace = "MustExtend";
25510let isExtendable = 1;
25511let opExtendable = 2;
25512let isExtentSigned = 0;
25513let opExtentBits = 6;
25514let opExtentAlign = 0;
25515let opNewValue = 3;
25516}
25517def S4_subaddi : HInst<
25518(outs IntRegs:$Rd32),
25519(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
25520"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
25521tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
25522let Inst{31-23} = 0b110110111;
25523let hasNewValue = 1;
25524let opNewValue = 0;
25525let prefersSlot3 = 1;
25526let isExtendable = 1;
25527let opExtendable = 2;
25528let isExtentSigned = 1;
25529let opExtentBits = 6;
25530let opExtentAlign = 0;
25531}
25532def S4_subi_asl_ri : HInst<
25533(outs IntRegs:$Rx32),
25534(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25535"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
25536tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25537let Inst{2-0} = 0b110;
25538let Inst{4-4} = 0b0;
25539let Inst{31-24} = 0b11011110;
25540let hasNewValue = 1;
25541let opNewValue = 0;
25542let prefersSlot3 = 1;
25543let isExtendable = 1;
25544let opExtendable = 1;
25545let isExtentSigned = 0;
25546let opExtentBits = 8;
25547let opExtentAlign = 0;
25548let Constraints = "$Rx32 = $Rx32in";
25549}
25550def S4_subi_lsr_ri : HInst<
25551(outs IntRegs:$Rx32),
25552(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25553"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
25554tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25555let Inst{2-0} = 0b110;
25556let Inst{4-4} = 0b1;
25557let Inst{31-24} = 0b11011110;
25558let hasNewValue = 1;
25559let opNewValue = 0;
25560let prefersSlot3 = 1;
25561let isExtendable = 1;
25562let opExtendable = 1;
25563let isExtentSigned = 0;
25564let opExtentBits = 8;
25565let opExtentAlign = 0;
25566let Constraints = "$Rx32 = $Rx32in";
25567}
25568def S4_vrcrotate : HInst<
25569(outs DoubleRegs:$Rdd32),
25570(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25571"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
25572tc_f0cdeccf, TypeS_3op>, Enc_645d54 {
25573let Inst{7-6} = 0b11;
25574let Inst{31-21} = 0b11000011110;
25575let prefersSlot3 = 1;
25576}
25577def S4_vrcrotate_acc : HInst<
25578(outs DoubleRegs:$Rxx32),
25579(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25580"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
25581tc_a38c45dc, TypeS_3op>, Enc_b72622 {
25582let Inst{7-6} = 0b00;
25583let Inst{31-21} = 0b11001011101;
25584let prefersSlot3 = 1;
25585let Constraints = "$Rxx32 = $Rxx32in";
25586}
25587def S4_vxaddsubh : HInst<
25588(outs DoubleRegs:$Rdd32),
25589(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25590"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
25591tc_8a825db2, TypeS_3op>, Enc_a56825 {
25592let Inst{7-5} = 0b100;
25593let Inst{13-13} = 0b0;
25594let Inst{31-21} = 0b11000001010;
25595let prefersSlot3 = 1;
25596let Defs = [USR_OVF];
25597}
25598def S4_vxaddsubhr : HInst<
25599(outs DoubleRegs:$Rdd32),
25600(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25601"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
25602tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25603let Inst{7-5} = 0b000;
25604let Inst{13-13} = 0b0;
25605let Inst{31-21} = 0b11000001110;
25606let prefersSlot3 = 1;
25607let Defs = [USR_OVF];
25608}
25609def S4_vxaddsubw : HInst<
25610(outs DoubleRegs:$Rdd32),
25611(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25612"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
25613tc_8a825db2, TypeS_3op>, Enc_a56825 {
25614let Inst{7-5} = 0b000;
25615let Inst{13-13} = 0b0;
25616let Inst{31-21} = 0b11000001010;
25617let prefersSlot3 = 1;
25618let Defs = [USR_OVF];
25619}
25620def S4_vxsubaddh : HInst<
25621(outs DoubleRegs:$Rdd32),
25622(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25623"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
25624tc_8a825db2, TypeS_3op>, Enc_a56825 {
25625let Inst{7-5} = 0b110;
25626let Inst{13-13} = 0b0;
25627let Inst{31-21} = 0b11000001010;
25628let prefersSlot3 = 1;
25629let Defs = [USR_OVF];
25630}
25631def S4_vxsubaddhr : HInst<
25632(outs DoubleRegs:$Rdd32),
25633(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25634"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
25635tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25636let Inst{7-5} = 0b010;
25637let Inst{13-13} = 0b0;
25638let Inst{31-21} = 0b11000001110;
25639let prefersSlot3 = 1;
25640let Defs = [USR_OVF];
25641}
25642def S4_vxsubaddw : HInst<
25643(outs DoubleRegs:$Rdd32),
25644(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25645"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
25646tc_8a825db2, TypeS_3op>, Enc_a56825 {
25647let Inst{7-5} = 0b010;
25648let Inst{13-13} = 0b0;
25649let Inst{31-21} = 0b11000001010;
25650let prefersSlot3 = 1;
25651let Defs = [USR_OVF];
25652}
25653def S5_asrhub_rnd_sat : HInst<
25654(outs IntRegs:$Rd32),
25655(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25656"$Rd32 = vasrhub($Rss32,#$Ii):raw",
25657tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25658let Inst{7-5} = 0b100;
25659let Inst{13-12} = 0b00;
25660let Inst{31-21} = 0b10001000011;
25661let hasNewValue = 1;
25662let opNewValue = 0;
25663let prefersSlot3 = 1;
25664let Defs = [USR_OVF];
25665}
25666def S5_asrhub_rnd_sat_goodsyntax : HInst<
25667(outs IntRegs:$Rd32),
25668(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25669"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
25670tc_0dfac0a7, TypeS_2op> {
25671let hasNewValue = 1;
25672let opNewValue = 0;
25673let isPseudo = 1;
25674}
25675def S5_asrhub_sat : HInst<
25676(outs IntRegs:$Rd32),
25677(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25678"$Rd32 = vasrhub($Rss32,#$Ii):sat",
25679tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25680let Inst{7-5} = 0b101;
25681let Inst{13-12} = 0b00;
25682let Inst{31-21} = 0b10001000011;
25683let hasNewValue = 1;
25684let opNewValue = 0;
25685let prefersSlot3 = 1;
25686let Defs = [USR_OVF];
25687}
25688def S5_popcountp : HInst<
25689(outs IntRegs:$Rd32),
25690(ins DoubleRegs:$Rss32),
25691"$Rd32 = popcount($Rss32)",
25692tc_d3632d88, TypeS_2op>, Enc_90cd8b {
25693let Inst{13-5} = 0b000000011;
25694let Inst{31-21} = 0b10001000011;
25695let hasNewValue = 1;
25696let opNewValue = 0;
25697let prefersSlot3 = 1;
25698}
25699def S5_vasrhrnd : HInst<
25700(outs DoubleRegs:$Rdd32),
25701(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25702"$Rdd32 = vasrh($Rss32,#$Ii):raw",
25703tc_0dfac0a7, TypeS_2op>, Enc_12b6e9 {
25704let Inst{7-5} = 0b000;
25705let Inst{13-12} = 0b00;
25706let Inst{31-21} = 0b10000000001;
25707let prefersSlot3 = 1;
25708}
25709def S5_vasrhrnd_goodsyntax : HInst<
25710(outs DoubleRegs:$Rdd32),
25711(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25712"$Rdd32 = vasrh($Rss32,#$Ii):rnd",
25713tc_0dfac0a7, TypeS_2op> {
25714let isPseudo = 1;
25715}
25716def S6_allocframe_to_raw : HInst<
25717(outs),
25718(ins u11_3Imm:$Ii),
25719"allocframe(#$Ii)",
25720tc_934753bb, TypeMAPPING>, Requires<[HasV65]> {
25721let isPseudo = 1;
25722let isCodeGenOnly = 1;
25723}
25724def S6_rol_i_p : HInst<
25725(outs DoubleRegs:$Rdd32),
25726(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
25727"$Rdd32 = rol($Rss32,#$Ii)",
25728tc_407e96f9, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> {
25729let Inst{7-5} = 0b011;
25730let Inst{31-21} = 0b10000000000;
25731}
25732def S6_rol_i_p_acc : HInst<
25733(outs DoubleRegs:$Rxx32),
25734(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25735"$Rxx32 += rol($Rss32,#$Ii)",
25736tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25737let Inst{7-5} = 0b111;
25738let Inst{31-21} = 0b10000010000;
25739let prefersSlot3 = 1;
25740let Constraints = "$Rxx32 = $Rxx32in";
25741}
25742def S6_rol_i_p_and : HInst<
25743(outs DoubleRegs:$Rxx32),
25744(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25745"$Rxx32 &= rol($Rss32,#$Ii)",
25746tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25747let Inst{7-5} = 0b011;
25748let Inst{31-21} = 0b10000010010;
25749let prefersSlot3 = 1;
25750let Constraints = "$Rxx32 = $Rxx32in";
25751}
25752def S6_rol_i_p_nac : HInst<
25753(outs DoubleRegs:$Rxx32),
25754(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25755"$Rxx32 -= rol($Rss32,#$Ii)",
25756tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25757let Inst{7-5} = 0b011;
25758let Inst{31-21} = 0b10000010000;
25759let prefersSlot3 = 1;
25760let Constraints = "$Rxx32 = $Rxx32in";
25761}
25762def S6_rol_i_p_or : HInst<
25763(outs DoubleRegs:$Rxx32),
25764(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25765"$Rxx32 |= rol($Rss32,#$Ii)",
25766tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25767let Inst{7-5} = 0b111;
25768let Inst{31-21} = 0b10000010010;
25769let prefersSlot3 = 1;
25770let Constraints = "$Rxx32 = $Rxx32in";
25771}
25772def S6_rol_i_p_xacc : HInst<
25773(outs DoubleRegs:$Rxx32),
25774(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25775"$Rxx32 ^= rol($Rss32,#$Ii)",
25776tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25777let Inst{7-5} = 0b011;
25778let Inst{31-21} = 0b10000010100;
25779let prefersSlot3 = 1;
25780let Constraints = "$Rxx32 = $Rxx32in";
25781}
25782def S6_rol_i_r : HInst<
25783(outs IntRegs:$Rd32),
25784(ins IntRegs:$Rs32, u5_0Imm:$Ii),
25785"$Rd32 = rol($Rs32,#$Ii)",
25786tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV60]> {
25787let Inst{7-5} = 0b011;
25788let Inst{13-13} = 0b0;
25789let Inst{31-21} = 0b10001100000;
25790let hasNewValue = 1;
25791let opNewValue = 0;
25792}
25793def S6_rol_i_r_acc : HInst<
25794(outs IntRegs:$Rx32),
25795(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25796"$Rx32 += rol($Rs32,#$Ii)",
25797tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25798let Inst{7-5} = 0b111;
25799let Inst{13-13} = 0b0;
25800let Inst{31-21} = 0b10001110000;
25801let hasNewValue = 1;
25802let opNewValue = 0;
25803let prefersSlot3 = 1;
25804let Constraints = "$Rx32 = $Rx32in";
25805}
25806def S6_rol_i_r_and : HInst<
25807(outs IntRegs:$Rx32),
25808(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25809"$Rx32 &= rol($Rs32,#$Ii)",
25810tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25811let Inst{7-5} = 0b011;
25812let Inst{13-13} = 0b0;
25813let Inst{31-21} = 0b10001110010;
25814let hasNewValue = 1;
25815let opNewValue = 0;
25816let prefersSlot3 = 1;
25817let Constraints = "$Rx32 = $Rx32in";
25818}
25819def S6_rol_i_r_nac : HInst<
25820(outs IntRegs:$Rx32),
25821(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25822"$Rx32 -= rol($Rs32,#$Ii)",
25823tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25824let Inst{7-5} = 0b011;
25825let Inst{13-13} = 0b0;
25826let Inst{31-21} = 0b10001110000;
25827let hasNewValue = 1;
25828let opNewValue = 0;
25829let prefersSlot3 = 1;
25830let Constraints = "$Rx32 = $Rx32in";
25831}
25832def S6_rol_i_r_or : HInst<
25833(outs IntRegs:$Rx32),
25834(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25835"$Rx32 |= rol($Rs32,#$Ii)",
25836tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25837let Inst{7-5} = 0b111;
25838let Inst{13-13} = 0b0;
25839let Inst{31-21} = 0b10001110010;
25840let hasNewValue = 1;
25841let opNewValue = 0;
25842let prefersSlot3 = 1;
25843let Constraints = "$Rx32 = $Rx32in";
25844}
25845def S6_rol_i_r_xacc : HInst<
25846(outs IntRegs:$Rx32),
25847(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25848"$Rx32 ^= rol($Rs32,#$Ii)",
25849tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25850let Inst{7-5} = 0b011;
25851let Inst{13-13} = 0b0;
25852let Inst{31-21} = 0b10001110100;
25853let hasNewValue = 1;
25854let opNewValue = 0;
25855let prefersSlot3 = 1;
25856let Constraints = "$Rx32 = $Rx32in";
25857}
25858def S6_vsplatrbp : HInst<
25859(outs DoubleRegs:$Rdd32),
25860(ins IntRegs:$Rs32),
25861"$Rdd32 = vsplatb($Rs32)",
25862tc_ef921005, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> {
25863let Inst{13-5} = 0b000000100;
25864let Inst{31-21} = 0b10000100010;
25865}
25866def S6_vtrunehb_ppp : HInst<
25867(outs DoubleRegs:$Rdd32),
25868(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25869"$Rdd32 = vtrunehb($Rss32,$Rtt32)",
25870tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25871let Inst{7-5} = 0b011;
25872let Inst{13-13} = 0b0;
25873let Inst{31-21} = 0b11000001100;
25874}
25875def S6_vtrunohb_ppp : HInst<
25876(outs DoubleRegs:$Rdd32),
25877(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25878"$Rdd32 = vtrunohb($Rss32,$Rtt32)",
25879tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25880let Inst{7-5} = 0b101;
25881let Inst{13-13} = 0b0;
25882let Inst{31-21} = 0b11000001100;
25883}
25884def SA1_addi : HInst<
25885(outs GeneralSubRegs:$Rx16),
25886(ins GeneralSubRegs:$Rx16in, s32_0Imm:$Ii),
25887"$Rx16 = add($Rx16in,#$Ii)",
25888tc_5b347363, TypeSUBINSN>, Enc_93af4c {
25889let Inst{12-11} = 0b00;
25890let hasNewValue = 1;
25891let opNewValue = 0;
25892let AsmVariantName = "NonParsable";
25893let DecoderNamespace = "SUBINSN_A";
25894let isExtendable = 1;
25895let opExtendable = 2;
25896let isExtentSigned = 1;
25897let opExtentBits = 7;
25898let opExtentAlign = 0;
25899let Constraints = "$Rx16 = $Rx16in";
25900}
25901def SA1_addrx : HInst<
25902(outs GeneralSubRegs:$Rx16),
25903(ins GeneralSubRegs:$Rx16in, GeneralSubRegs:$Rs16),
25904"$Rx16 = add($Rx16in,$Rs16)",
25905tc_5b347363, TypeSUBINSN>, Enc_0527db {
25906let Inst{12-8} = 0b11000;
25907let hasNewValue = 1;
25908let opNewValue = 0;
25909let AsmVariantName = "NonParsable";
25910let DecoderNamespace = "SUBINSN_A";
25911let Constraints = "$Rx16 = $Rx16in";
25912}
25913def SA1_addsp : HInst<
25914(outs GeneralSubRegs:$Rd16),
25915(ins u6_2Imm:$Ii),
25916"$Rd16 = add(r29,#$Ii)",
25917tc_3d14a17b, TypeSUBINSN>, Enc_2df31d {
25918let Inst{12-10} = 0b011;
25919let hasNewValue = 1;
25920let opNewValue = 0;
25921let AsmVariantName = "NonParsable";
25922let Uses = [R29];
25923let DecoderNamespace = "SUBINSN_A";
25924}
25925def SA1_and1 : HInst<
25926(outs GeneralSubRegs:$Rd16),
25927(ins GeneralSubRegs:$Rs16),
25928"$Rd16 = and($Rs16,#1)",
25929tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
25930let Inst{12-8} = 0b10010;
25931let hasNewValue = 1;
25932let opNewValue = 0;
25933let AsmVariantName = "NonParsable";
25934let DecoderNamespace = "SUBINSN_A";
25935}
25936def SA1_clrf : HInst<
25937(outs GeneralSubRegs:$Rd16),
25938(ins),
25939"if (!p0) $Rd16 = #0",
25940tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25941let Inst{12-4} = 0b110100111;
25942let isPredicated = 1;
25943let isPredicatedFalse = 1;
25944let hasNewValue = 1;
25945let opNewValue = 0;
25946let AsmVariantName = "NonParsable";
25947let Uses = [P0];
25948let DecoderNamespace = "SUBINSN_A";
25949}
25950def SA1_clrfnew : HInst<
25951(outs GeneralSubRegs:$Rd16),
25952(ins),
25953"if (!p0.new) $Rd16 = #0",
25954tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
25955let Inst{12-4} = 0b110100101;
25956let isPredicated = 1;
25957let isPredicatedFalse = 1;
25958let hasNewValue = 1;
25959let opNewValue = 0;
25960let AsmVariantName = "NonParsable";
25961let isPredicatedNew = 1;
25962let Uses = [P0];
25963let DecoderNamespace = "SUBINSN_A";
25964}
25965def SA1_clrt : HInst<
25966(outs GeneralSubRegs:$Rd16),
25967(ins),
25968"if (p0) $Rd16 = #0",
25969tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25970let Inst{12-4} = 0b110100110;
25971let isPredicated = 1;
25972let hasNewValue = 1;
25973let opNewValue = 0;
25974let AsmVariantName = "NonParsable";
25975let Uses = [P0];
25976let DecoderNamespace = "SUBINSN_A";
25977}
25978def SA1_clrtnew : HInst<
25979(outs GeneralSubRegs:$Rd16),
25980(ins),
25981"if (p0.new) $Rd16 = #0",
25982tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
25983let Inst{12-4} = 0b110100100;
25984let isPredicated = 1;
25985let hasNewValue = 1;
25986let opNewValue = 0;
25987let AsmVariantName = "NonParsable";
25988let isPredicatedNew = 1;
25989let Uses = [P0];
25990let DecoderNamespace = "SUBINSN_A";
25991}
25992def SA1_cmpeqi : HInst<
25993(outs),
25994(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
25995"p0 = cmp.eq($Rs16,#$Ii)",
25996tc_59a7822c, TypeSUBINSN>, Enc_63eaeb {
25997let Inst{3-2} = 0b00;
25998let Inst{12-8} = 0b11001;
25999let AsmVariantName = "NonParsable";
26000let Defs = [P0];
26001let DecoderNamespace = "SUBINSN_A";
26002}
26003def SA1_combine0i : HInst<
26004(outs GeneralDoubleLow8Regs:$Rdd8),
26005(ins u2_0Imm:$Ii),
26006"$Rdd8 = combine(#0,#$Ii)",
26007tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26008let Inst{4-3} = 0b00;
26009let Inst{12-7} = 0b111000;
26010let hasNewValue = 1;
26011let opNewValue = 0;
26012let AsmVariantName = "NonParsable";
26013let DecoderNamespace = "SUBINSN_A";
26014}
26015def SA1_combine1i : HInst<
26016(outs GeneralDoubleLow8Regs:$Rdd8),
26017(ins u2_0Imm:$Ii),
26018"$Rdd8 = combine(#1,#$Ii)",
26019tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26020let Inst{4-3} = 0b01;
26021let Inst{12-7} = 0b111000;
26022let hasNewValue = 1;
26023let opNewValue = 0;
26024let AsmVariantName = "NonParsable";
26025let DecoderNamespace = "SUBINSN_A";
26026}
26027def SA1_combine2i : HInst<
26028(outs GeneralDoubleLow8Regs:$Rdd8),
26029(ins u2_0Imm:$Ii),
26030"$Rdd8 = combine(#2,#$Ii)",
26031tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26032let Inst{4-3} = 0b10;
26033let Inst{12-7} = 0b111000;
26034let hasNewValue = 1;
26035let opNewValue = 0;
26036let AsmVariantName = "NonParsable";
26037let DecoderNamespace = "SUBINSN_A";
26038}
26039def SA1_combine3i : HInst<
26040(outs GeneralDoubleLow8Regs:$Rdd8),
26041(ins u2_0Imm:$Ii),
26042"$Rdd8 = combine(#3,#$Ii)",
26043tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26044let Inst{4-3} = 0b11;
26045let Inst{12-7} = 0b111000;
26046let hasNewValue = 1;
26047let opNewValue = 0;
26048let AsmVariantName = "NonParsable";
26049let DecoderNamespace = "SUBINSN_A";
26050}
26051def SA1_combinerz : HInst<
26052(outs GeneralDoubleLow8Regs:$Rdd8),
26053(ins GeneralSubRegs:$Rs16),
26054"$Rdd8 = combine($Rs16,#0)",
26055tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26056let Inst{3-3} = 0b1;
26057let Inst{12-8} = 0b11101;
26058let hasNewValue = 1;
26059let opNewValue = 0;
26060let AsmVariantName = "NonParsable";
26061let DecoderNamespace = "SUBINSN_A";
26062}
26063def SA1_combinezr : HInst<
26064(outs GeneralDoubleLow8Regs:$Rdd8),
26065(ins GeneralSubRegs:$Rs16),
26066"$Rdd8 = combine(#0,$Rs16)",
26067tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26068let Inst{3-3} = 0b0;
26069let Inst{12-8} = 0b11101;
26070let hasNewValue = 1;
26071let opNewValue = 0;
26072let AsmVariantName = "NonParsable";
26073let DecoderNamespace = "SUBINSN_A";
26074}
26075def SA1_dec : HInst<
26076(outs GeneralSubRegs:$Rd16),
26077(ins GeneralSubRegs:$Rs16, n1Const:$n1),
26078"$Rd16 = add($Rs16,#$n1)",
26079tc_5b347363, TypeSUBINSN>, Enc_ee5ed0 {
26080let Inst{12-8} = 0b10011;
26081let hasNewValue = 1;
26082let opNewValue = 0;
26083let AsmVariantName = "NonParsable";
26084let DecoderNamespace = "SUBINSN_A";
26085}
26086def SA1_inc : HInst<
26087(outs GeneralSubRegs:$Rd16),
26088(ins GeneralSubRegs:$Rs16),
26089"$Rd16 = add($Rs16,#1)",
26090tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26091let Inst{12-8} = 0b10001;
26092let hasNewValue = 1;
26093let opNewValue = 0;
26094let AsmVariantName = "NonParsable";
26095let DecoderNamespace = "SUBINSN_A";
26096}
26097def SA1_seti : HInst<
26098(outs GeneralSubRegs:$Rd16),
26099(ins u32_0Imm:$Ii),
26100"$Rd16 = #$Ii",
26101tc_3d14a17b, TypeSUBINSN>, Enc_e39bb2 {
26102let Inst{12-10} = 0b010;
26103let hasNewValue = 1;
26104let opNewValue = 0;
26105let AsmVariantName = "NonParsable";
26106let DecoderNamespace = "SUBINSN_A";
26107let isExtendable = 1;
26108let opExtendable = 1;
26109let isExtentSigned = 0;
26110let opExtentBits = 6;
26111let opExtentAlign = 0;
26112}
26113def SA1_setin1 : HInst<
26114(outs GeneralSubRegs:$Rd16),
26115(ins n1Const:$n1),
26116"$Rd16 = #$n1",
26117tc_3d14a17b, TypeSUBINSN>, Enc_7a0ea6 {
26118let Inst{12-4} = 0b110100000;
26119let hasNewValue = 1;
26120let opNewValue = 0;
26121let AsmVariantName = "NonParsable";
26122let DecoderNamespace = "SUBINSN_A";
26123}
26124def SA1_sxtb : HInst<
26125(outs GeneralSubRegs:$Rd16),
26126(ins GeneralSubRegs:$Rs16),
26127"$Rd16 = sxtb($Rs16)",
26128tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26129let Inst{12-8} = 0b10101;
26130let hasNewValue = 1;
26131let opNewValue = 0;
26132let AsmVariantName = "NonParsable";
26133let DecoderNamespace = "SUBINSN_A";
26134}
26135def SA1_sxth : HInst<
26136(outs GeneralSubRegs:$Rd16),
26137(ins GeneralSubRegs:$Rs16),
26138"$Rd16 = sxth($Rs16)",
26139tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26140let Inst{12-8} = 0b10100;
26141let hasNewValue = 1;
26142let opNewValue = 0;
26143let AsmVariantName = "NonParsable";
26144let DecoderNamespace = "SUBINSN_A";
26145}
26146def SA1_tfr : HInst<
26147(outs GeneralSubRegs:$Rd16),
26148(ins GeneralSubRegs:$Rs16),
26149"$Rd16 = $Rs16",
26150tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26151let Inst{12-8} = 0b10000;
26152let hasNewValue = 1;
26153let opNewValue = 0;
26154let AsmVariantName = "NonParsable";
26155let DecoderNamespace = "SUBINSN_A";
26156}
26157def SA1_zxtb : HInst<
26158(outs GeneralSubRegs:$Rd16),
26159(ins GeneralSubRegs:$Rs16),
26160"$Rd16 = and($Rs16,#255)",
26161tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26162let Inst{12-8} = 0b10111;
26163let hasNewValue = 1;
26164let opNewValue = 0;
26165let AsmVariantName = "NonParsable";
26166let DecoderNamespace = "SUBINSN_A";
26167}
26168def SA1_zxth : HInst<
26169(outs GeneralSubRegs:$Rd16),
26170(ins GeneralSubRegs:$Rs16),
26171"$Rd16 = zxth($Rs16)",
26172tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26173let Inst{12-8} = 0b10110;
26174let hasNewValue = 1;
26175let opNewValue = 0;
26176let AsmVariantName = "NonParsable";
26177let DecoderNamespace = "SUBINSN_A";
26178}
26179def SL1_loadri_io : HInst<
26180(outs GeneralSubRegs:$Rd16),
26181(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26182"$Rd16 = memw($Rs16+#$Ii)",
26183tc_4222e6bf, TypeSUBINSN>, Enc_53dca9 {
26184let Inst{12-12} = 0b0;
26185let hasNewValue = 1;
26186let opNewValue = 0;
26187let addrMode = BaseImmOffset;
26188let accessSize = WordAccess;
26189let AsmVariantName = "NonParsable";
26190let mayLoad = 1;
26191let DecoderNamespace = "SUBINSN_L1";
26192}
26193def SL1_loadrub_io : HInst<
26194(outs GeneralSubRegs:$Rd16),
26195(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26196"$Rd16 = memub($Rs16+#$Ii)",
26197tc_4222e6bf, TypeSUBINSN>, Enc_c175d0 {
26198let Inst{12-12} = 0b1;
26199let hasNewValue = 1;
26200let opNewValue = 0;
26201let addrMode = BaseImmOffset;
26202let accessSize = ByteAccess;
26203let AsmVariantName = "NonParsable";
26204let mayLoad = 1;
26205let DecoderNamespace = "SUBINSN_L1";
26206}
26207def SL2_deallocframe : HInst<
26208(outs),
26209(ins),
26210"deallocframe",
26211tc_937dd41c, TypeSUBINSN>, Enc_e3b0c4 {
26212let Inst{12-0} = 0b1111100000000;
26213let accessSize = DoubleWordAccess;
26214let AsmVariantName = "NonParsable";
26215let mayLoad = 1;
26216let Uses = [FRAMEKEY, R30];
26217let Defs = [R29, R30, R31];
26218let DecoderNamespace = "SUBINSN_L2";
26219}
26220def SL2_jumpr31 : HInst<
26221(outs),
26222(ins),
26223"jumpr r31",
26224tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26225let Inst{12-0} = 0b1111111000000;
26226let isTerminator = 1;
26227let isIndirectBranch = 1;
26228let AsmVariantName = "NonParsable";
26229let cofMax1 = 1;
26230let isReturn = 1;
26231let Uses = [R31];
26232let Defs = [PC];
26233let DecoderNamespace = "SUBINSN_L2";
26234}
26235def SL2_jumpr31_f : HInst<
26236(outs),
26237(ins),
26238"if (!p0) jumpr r31",
26239tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26240let Inst{12-0} = 0b1111111000101;
26241let isPredicated = 1;
26242let isPredicatedFalse = 1;
26243let isTerminator = 1;
26244let isIndirectBranch = 1;
26245let AsmVariantName = "NonParsable";
26246let cofMax1 = 1;
26247let isReturn = 1;
26248let Uses = [P0, R31];
26249let Defs = [PC];
26250let isTaken = Inst{4};
26251let DecoderNamespace = "SUBINSN_L2";
26252}
26253def SL2_jumpr31_fnew : HInst<
26254(outs),
26255(ins),
26256"if (!p0.new) jumpr:nt r31",
26257tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26258let Inst{12-0} = 0b1111111000111;
26259let isPredicated = 1;
26260let isPredicatedFalse = 1;
26261let isTerminator = 1;
26262let isIndirectBranch = 1;
26263let AsmVariantName = "NonParsable";
26264let isPredicatedNew = 1;
26265let cofMax1 = 1;
26266let isReturn = 1;
26267let Uses = [P0, R31];
26268let Defs = [PC];
26269let isTaken = Inst{4};
26270let DecoderNamespace = "SUBINSN_L2";
26271}
26272def SL2_jumpr31_t : HInst<
26273(outs),
26274(ins),
26275"if (p0) jumpr r31",
26276tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26277let Inst{12-0} = 0b1111111000100;
26278let isPredicated = 1;
26279let isTerminator = 1;
26280let isIndirectBranch = 1;
26281let AsmVariantName = "NonParsable";
26282let cofMax1 = 1;
26283let isReturn = 1;
26284let Uses = [P0, R31];
26285let Defs = [PC];
26286let isTaken = Inst{4};
26287let DecoderNamespace = "SUBINSN_L2";
26288}
26289def SL2_jumpr31_tnew : HInst<
26290(outs),
26291(ins),
26292"if (p0.new) jumpr:nt r31",
26293tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26294let Inst{12-0} = 0b1111111000110;
26295let isPredicated = 1;
26296let isTerminator = 1;
26297let isIndirectBranch = 1;
26298let AsmVariantName = "NonParsable";
26299let isPredicatedNew = 1;
26300let cofMax1 = 1;
26301let isReturn = 1;
26302let Uses = [P0, R31];
26303let Defs = [PC];
26304let isTaken = Inst{4};
26305let DecoderNamespace = "SUBINSN_L2";
26306}
26307def SL2_loadrb_io : HInst<
26308(outs GeneralSubRegs:$Rd16),
26309(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
26310"$Rd16 = memb($Rs16+#$Ii)",
26311tc_4222e6bf, TypeSUBINSN>, Enc_2fbf3c {
26312let Inst{12-11} = 0b10;
26313let hasNewValue = 1;
26314let opNewValue = 0;
26315let addrMode = BaseImmOffset;
26316let accessSize = ByteAccess;
26317let AsmVariantName = "NonParsable";
26318let mayLoad = 1;
26319let DecoderNamespace = "SUBINSN_L2";
26320}
26321def SL2_loadrd_sp : HInst<
26322(outs GeneralDoubleLow8Regs:$Rdd8),
26323(ins u5_3Imm:$Ii),
26324"$Rdd8 = memd(r29+#$Ii)",
26325tc_8a6d0d94, TypeSUBINSN>, Enc_86a14b {
26326let Inst{12-8} = 0b11110;
26327let hasNewValue = 1;
26328let opNewValue = 0;
26329let addrMode = BaseImmOffset;
26330let accessSize = DoubleWordAccess;
26331let AsmVariantName = "NonParsable";
26332let mayLoad = 1;
26333let Uses = [R29];
26334let DecoderNamespace = "SUBINSN_L2";
26335}
26336def SL2_loadrh_io : HInst<
26337(outs GeneralSubRegs:$Rd16),
26338(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26339"$Rd16 = memh($Rs16+#$Ii)",
26340tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26341let Inst{12-11} = 0b00;
26342let hasNewValue = 1;
26343let opNewValue = 0;
26344let addrMode = BaseImmOffset;
26345let accessSize = HalfWordAccess;
26346let AsmVariantName = "NonParsable";
26347let mayLoad = 1;
26348let DecoderNamespace = "SUBINSN_L2";
26349}
26350def SL2_loadri_sp : HInst<
26351(outs GeneralSubRegs:$Rd16),
26352(ins u5_2Imm:$Ii),
26353"$Rd16 = memw(r29+#$Ii)",
26354tc_8a6d0d94, TypeSUBINSN>, Enc_51635c {
26355let Inst{12-9} = 0b1110;
26356let hasNewValue = 1;
26357let opNewValue = 0;
26358let addrMode = BaseImmOffset;
26359let accessSize = WordAccess;
26360let AsmVariantName = "NonParsable";
26361let mayLoad = 1;
26362let Uses = [R29];
26363let DecoderNamespace = "SUBINSN_L2";
26364}
26365def SL2_loadruh_io : HInst<
26366(outs GeneralSubRegs:$Rd16),
26367(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26368"$Rd16 = memuh($Rs16+#$Ii)",
26369tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26370let Inst{12-11} = 0b01;
26371let hasNewValue = 1;
26372let opNewValue = 0;
26373let addrMode = BaseImmOffset;
26374let accessSize = HalfWordAccess;
26375let AsmVariantName = "NonParsable";
26376let mayLoad = 1;
26377let DecoderNamespace = "SUBINSN_L2";
26378}
26379def SL2_return : HInst<
26380(outs),
26381(ins),
26382"dealloc_return",
26383tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26384let Inst{12-0} = 0b1111101000000;
26385let isTerminator = 1;
26386let isIndirectBranch = 1;
26387let accessSize = DoubleWordAccess;
26388let AsmVariantName = "NonParsable";
26389let mayLoad = 1;
26390let cofMax1 = 1;
26391let isRestrictNoSlot1Store = 1;
26392let isReturn = 1;
26393let Uses = [FRAMEKEY, R30];
26394let Defs = [PC, R29, R30, R31];
26395let DecoderNamespace = "SUBINSN_L2";
26396}
26397def SL2_return_f : HInst<
26398(outs),
26399(ins),
26400"if (!p0) dealloc_return",
26401tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26402let Inst{12-0} = 0b1111101000101;
26403let isPredicated = 1;
26404let isPredicatedFalse = 1;
26405let isTerminator = 1;
26406let isIndirectBranch = 1;
26407let accessSize = DoubleWordAccess;
26408let AsmVariantName = "NonParsable";
26409let mayLoad = 1;
26410let cofMax1 = 1;
26411let isRestrictNoSlot1Store = 1;
26412let isReturn = 1;
26413let Uses = [FRAMEKEY, P0, R30];
26414let Defs = [PC, R29, R30, R31];
26415let isTaken = Inst{4};
26416let DecoderNamespace = "SUBINSN_L2";
26417}
26418def SL2_return_fnew : HInst<
26419(outs),
26420(ins),
26421"if (!p0.new) dealloc_return:nt",
26422tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26423let Inst{12-0} = 0b1111101000111;
26424let isPredicated = 1;
26425let isPredicatedFalse = 1;
26426let isTerminator = 1;
26427let isIndirectBranch = 1;
26428let accessSize = DoubleWordAccess;
26429let AsmVariantName = "NonParsable";
26430let isPredicatedNew = 1;
26431let mayLoad = 1;
26432let cofMax1 = 1;
26433let isRestrictNoSlot1Store = 1;
26434let isReturn = 1;
26435let Uses = [FRAMEKEY, P0, R30];
26436let Defs = [PC, R29, R30, R31];
26437let isTaken = Inst{4};
26438let DecoderNamespace = "SUBINSN_L2";
26439}
26440def SL2_return_t : HInst<
26441(outs),
26442(ins),
26443"if (p0) dealloc_return",
26444tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26445let Inst{12-0} = 0b1111101000100;
26446let isPredicated = 1;
26447let isTerminator = 1;
26448let isIndirectBranch = 1;
26449let accessSize = DoubleWordAccess;
26450let AsmVariantName = "NonParsable";
26451let mayLoad = 1;
26452let cofMax1 = 1;
26453let isRestrictNoSlot1Store = 1;
26454let isReturn = 1;
26455let Uses = [FRAMEKEY, P0, R30];
26456let Defs = [PC, R29, R30, R31];
26457let isTaken = Inst{4};
26458let DecoderNamespace = "SUBINSN_L2";
26459}
26460def SL2_return_tnew : HInst<
26461(outs),
26462(ins),
26463"if (p0.new) dealloc_return:nt",
26464tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26465let Inst{12-0} = 0b1111101000110;
26466let isPredicated = 1;
26467let isTerminator = 1;
26468let isIndirectBranch = 1;
26469let accessSize = DoubleWordAccess;
26470let AsmVariantName = "NonParsable";
26471let isPredicatedNew = 1;
26472let mayLoad = 1;
26473let cofMax1 = 1;
26474let isRestrictNoSlot1Store = 1;
26475let isReturn = 1;
26476let Uses = [FRAMEKEY, P0, R30];
26477let Defs = [PC, R29, R30, R31];
26478let isTaken = Inst{4};
26479let DecoderNamespace = "SUBINSN_L2";
26480}
26481def SS1_storeb_io : HInst<
26482(outs),
26483(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
26484"memb($Rs16+#$Ii) = $Rt16",
26485tc_ae5babd7, TypeSUBINSN>, Enc_b38ffc {
26486let Inst{12-12} = 0b1;
26487let addrMode = BaseImmOffset;
26488let accessSize = ByteAccess;
26489let AsmVariantName = "NonParsable";
26490let mayStore = 1;
26491let DecoderNamespace = "SUBINSN_S1";
26492}
26493def SS1_storew_io : HInst<
26494(outs),
26495(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
26496"memw($Rs16+#$Ii) = $Rt16",
26497tc_ae5babd7, TypeSUBINSN>, Enc_f55a0c {
26498let Inst{12-12} = 0b0;
26499let addrMode = BaseImmOffset;
26500let accessSize = WordAccess;
26501let AsmVariantName = "NonParsable";
26502let mayStore = 1;
26503let DecoderNamespace = "SUBINSN_S1";
26504}
26505def SS2_allocframe : HInst<
26506(outs),
26507(ins u5_3Imm:$Ii),
26508"allocframe(#$Ii)",
26509tc_1242dc2a, TypeSUBINSN>, Enc_6f70ca {
26510let Inst{3-0} = 0b0000;
26511let Inst{12-9} = 0b1110;
26512let addrMode = BaseImmOffset;
26513let accessSize = DoubleWordAccess;
26514let AsmVariantName = "NonParsable";
26515let mayStore = 1;
26516let Uses = [FRAMEKEY, FRAMELIMIT, R29, R30, R31];
26517let Defs = [R29, R30];
26518let DecoderNamespace = "SUBINSN_S2";
26519}
26520def SS2_storebi0 : HInst<
26521(outs),
26522(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26523"memb($Rs16+#$Ii) = #0",
26524tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26525let Inst{12-8} = 0b10010;
26526let addrMode = BaseImmOffset;
26527let accessSize = ByteAccess;
26528let AsmVariantName = "NonParsable";
26529let mayStore = 1;
26530let DecoderNamespace = "SUBINSN_S2";
26531}
26532def SS2_storebi1 : HInst<
26533(outs),
26534(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26535"memb($Rs16+#$Ii) = #1",
26536tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26537let Inst{12-8} = 0b10011;
26538let addrMode = BaseImmOffset;
26539let accessSize = ByteAccess;
26540let AsmVariantName = "NonParsable";
26541let mayStore = 1;
26542let DecoderNamespace = "SUBINSN_S2";
26543}
26544def SS2_stored_sp : HInst<
26545(outs),
26546(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
26547"memd(r29+#$Ii) = $Rtt8",
26548tc_0655b949, TypeSUBINSN>, Enc_b8309d {
26549let Inst{12-9} = 0b0101;
26550let addrMode = BaseImmOffset;
26551let accessSize = DoubleWordAccess;
26552let AsmVariantName = "NonParsable";
26553let mayStore = 1;
26554let Uses = [R29];
26555let DecoderNamespace = "SUBINSN_S2";
26556}
26557def SS2_storeh_io : HInst<
26558(outs),
26559(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
26560"memh($Rs16+#$Ii) = $Rt16",
26561tc_ae5babd7, TypeSUBINSN>, Enc_625deb {
26562let Inst{12-11} = 0b00;
26563let addrMode = BaseImmOffset;
26564let accessSize = HalfWordAccess;
26565let AsmVariantName = "NonParsable";
26566let mayStore = 1;
26567let DecoderNamespace = "SUBINSN_S2";
26568}
26569def SS2_storew_sp : HInst<
26570(outs),
26571(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
26572"memw(r29+#$Ii) = $Rt16",
26573tc_0655b949, TypeSUBINSN>, Enc_87c142 {
26574let Inst{12-9} = 0b0100;
26575let addrMode = BaseImmOffset;
26576let accessSize = WordAccess;
26577let AsmVariantName = "NonParsable";
26578let mayStore = 1;
26579let Uses = [R29];
26580let DecoderNamespace = "SUBINSN_S2";
26581}
26582def SS2_storewi0 : HInst<
26583(outs),
26584(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26585"memw($Rs16+#$Ii) = #0",
26586tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26587let Inst{12-8} = 0b10000;
26588let addrMode = BaseImmOffset;
26589let accessSize = WordAccess;
26590let AsmVariantName = "NonParsable";
26591let mayStore = 1;
26592let DecoderNamespace = "SUBINSN_S2";
26593}
26594def SS2_storewi1 : HInst<
26595(outs),
26596(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26597"memw($Rs16+#$Ii) = #1",
26598tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26599let Inst{12-8} = 0b10001;
26600let addrMode = BaseImmOffset;
26601let accessSize = WordAccess;
26602let AsmVariantName = "NonParsable";
26603let mayStore = 1;
26604let DecoderNamespace = "SUBINSN_S2";
26605}
26606def V6_MAP_equb : HInst<
26607(outs HvxQR:$Qd4),
26608(ins HvxVR:$Vu32, HvxVR:$Vv32),
26609"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
26610PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26611let hasNewValue = 1;
26612let opNewValue = 0;
26613let isCVI = 1;
26614let isPseudo = 1;
26615let isCodeGenOnly = 1;
26616let DecoderNamespace = "EXT_mmvec";
26617}
26618def V6_MAP_equb_and : HInst<
26619(outs HvxQR:$Qx4),
26620(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26621"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
26622PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26623let isCVI = 1;
26624let isPseudo = 1;
26625let isCodeGenOnly = 1;
26626let DecoderNamespace = "EXT_mmvec";
26627let Constraints = "$Qx4 = $Qx4in";
26628}
26629def V6_MAP_equb_ior : HInst<
26630(outs HvxQR:$Qx4),
26631(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26632"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
26633PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26634let isAccumulator = 1;
26635let isCVI = 1;
26636let isPseudo = 1;
26637let isCodeGenOnly = 1;
26638let DecoderNamespace = "EXT_mmvec";
26639let Constraints = "$Qx4 = $Qx4in";
26640}
26641def V6_MAP_equb_xor : HInst<
26642(outs HvxQR:$Qx4),
26643(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26644"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
26645PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26646let isCVI = 1;
26647let isPseudo = 1;
26648let isCodeGenOnly = 1;
26649let DecoderNamespace = "EXT_mmvec";
26650let Constraints = "$Qx4 = $Qx4in";
26651}
26652def V6_MAP_equh : HInst<
26653(outs HvxQR:$Qd4),
26654(ins HvxVR:$Vu32, HvxVR:$Vv32),
26655"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
26656PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26657let hasNewValue = 1;
26658let opNewValue = 0;
26659let isCVI = 1;
26660let isPseudo = 1;
26661let isCodeGenOnly = 1;
26662let DecoderNamespace = "EXT_mmvec";
26663}
26664def V6_MAP_equh_and : HInst<
26665(outs HvxQR:$Qx4),
26666(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26667"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
26668PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26669let isCVI = 1;
26670let isPseudo = 1;
26671let isCodeGenOnly = 1;
26672let DecoderNamespace = "EXT_mmvec";
26673let Constraints = "$Qx4 = $Qx4in";
26674}
26675def V6_MAP_equh_ior : HInst<
26676(outs HvxQR:$Qx4),
26677(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26678"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
26679PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26680let isAccumulator = 1;
26681let isCVI = 1;
26682let isPseudo = 1;
26683let isCodeGenOnly = 1;
26684let DecoderNamespace = "EXT_mmvec";
26685let Constraints = "$Qx4 = $Qx4in";
26686}
26687def V6_MAP_equh_xor : HInst<
26688(outs HvxQR:$Qx4),
26689(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26690"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
26691PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26692let isCVI = 1;
26693let isPseudo = 1;
26694let isCodeGenOnly = 1;
26695let DecoderNamespace = "EXT_mmvec";
26696let Constraints = "$Qx4 = $Qx4in";
26697}
26698def V6_MAP_equw : HInst<
26699(outs HvxQR:$Qd4),
26700(ins HvxVR:$Vu32, HvxVR:$Vv32),
26701"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
26702PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26703let hasNewValue = 1;
26704let opNewValue = 0;
26705let isCVI = 1;
26706let isPseudo = 1;
26707let isCodeGenOnly = 1;
26708let DecoderNamespace = "EXT_mmvec";
26709}
26710def V6_MAP_equw_and : HInst<
26711(outs HvxQR:$Qx4),
26712(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26713"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
26714PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26715let isCVI = 1;
26716let isPseudo = 1;
26717let isCodeGenOnly = 1;
26718let DecoderNamespace = "EXT_mmvec";
26719let Constraints = "$Qx4 = $Qx4in";
26720}
26721def V6_MAP_equw_ior : HInst<
26722(outs HvxQR:$Qx4),
26723(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26724"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
26725PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26726let isAccumulator = 1;
26727let isCVI = 1;
26728let isPseudo = 1;
26729let isCodeGenOnly = 1;
26730let DecoderNamespace = "EXT_mmvec";
26731let Constraints = "$Qx4 = $Qx4in";
26732}
26733def V6_MAP_equw_xor : HInst<
26734(outs HvxQR:$Qx4),
26735(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26736"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
26737PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26738let isCVI = 1;
26739let isPseudo = 1;
26740let isCodeGenOnly = 1;
26741let DecoderNamespace = "EXT_mmvec";
26742let Constraints = "$Qx4 = $Qx4in";
26743}
26744def V6_extractw : HInst<
26745(outs IntRegs:$Rd32),
26746(ins HvxVR:$Vu32, IntRegs:$Rs32),
26747"$Rd32 = vextract($Vu32,$Rs32)",
26748tc_540c3da3, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
26749let Inst{7-5} = 0b001;
26750let Inst{13-13} = 0b0;
26751let Inst{31-21} = 0b10010010000;
26752let hasNewValue = 1;
26753let opNewValue = 0;
26754let isCVI = 1;
26755let isSolo = 1;
26756let mayLoad = 1;
26757let DecoderNamespace = "EXT_mmvec";
26758}
26759def V6_extractw_alt : HInst<
26760(outs IntRegs:$Rd32),
26761(ins HvxVR:$Vu32, IntRegs:$Rs32),
26762"$Rd32.w = vextract($Vu32,$Rs32)",
26763PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26764let hasNewValue = 1;
26765let opNewValue = 0;
26766let isCVI = 1;
26767let isPseudo = 1;
26768let isCodeGenOnly = 1;
26769let DecoderNamespace = "EXT_mmvec";
26770}
26771def V6_hi : HInst<
26772(outs HvxVR:$Vd32),
26773(ins HvxWR:$Vss32),
26774"$Vd32 = hi($Vss32)",
26775CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26776let hasNewValue = 1;
26777let opNewValue = 0;
26778let isCVI = 1;
26779let isPseudo = 1;
26780let DecoderNamespace = "EXT_mmvec";
26781}
26782def V6_ld0 : HInst<
26783(outs HvxVR:$Vd32),
26784(ins IntRegs:$Rt32),
26785"$Vd32 = vmem($Rt32)",
26786PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26787let hasNewValue = 1;
26788let opNewValue = 0;
26789let isCVI = 1;
26790let isPseudo = 1;
26791let isCodeGenOnly = 1;
26792let DecoderNamespace = "EXT_mmvec";
26793}
26794def V6_ldcnp0 : HInst<
26795(outs HvxVR:$Vd32),
26796(ins PredRegs:$Pv4, IntRegs:$Rt32),
26797"if (!$Pv4) $Vd32.cur = vmem($Rt32)",
26798PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26799let hasNewValue = 1;
26800let opNewValue = 0;
26801let isCVI = 1;
26802let isPseudo = 1;
26803let isCodeGenOnly = 1;
26804let DecoderNamespace = "EXT_mmvec";
26805}
26806def V6_ldcnpnt0 : HInst<
26807(outs HvxVR:$Vd32),
26808(ins PredRegs:$Pv4, IntRegs:$Rt32),
26809"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
26810PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26811let hasNewValue = 1;
26812let opNewValue = 0;
26813let isCVI = 1;
26814let isPseudo = 1;
26815let isCodeGenOnly = 1;
26816let DecoderNamespace = "EXT_mmvec";
26817}
26818def V6_ldcp0 : HInst<
26819(outs HvxVR:$Vd32),
26820(ins PredRegs:$Pv4, IntRegs:$Rt32),
26821"if ($Pv4) $Vd32.cur = vmem($Rt32)",
26822PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26823let hasNewValue = 1;
26824let opNewValue = 0;
26825let isCVI = 1;
26826let isPseudo = 1;
26827let isCodeGenOnly = 1;
26828let DecoderNamespace = "EXT_mmvec";
26829}
26830def V6_ldcpnt0 : HInst<
26831(outs HvxVR:$Vd32),
26832(ins PredRegs:$Pv4, IntRegs:$Rt32),
26833"if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
26834PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26835let hasNewValue = 1;
26836let opNewValue = 0;
26837let isCVI = 1;
26838let isPseudo = 1;
26839let isCodeGenOnly = 1;
26840let DecoderNamespace = "EXT_mmvec";
26841}
26842def V6_ldnp0 : HInst<
26843(outs HvxVR:$Vd32),
26844(ins PredRegs:$Pv4, IntRegs:$Rt32),
26845"if (!$Pv4) $Vd32 = vmem($Rt32)",
26846PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26847let hasNewValue = 1;
26848let opNewValue = 0;
26849let isCVI = 1;
26850let isPseudo = 1;
26851let isCodeGenOnly = 1;
26852let DecoderNamespace = "EXT_mmvec";
26853}
26854def V6_ldnpnt0 : HInst<
26855(outs HvxVR:$Vd32),
26856(ins PredRegs:$Pv4, IntRegs:$Rt32),
26857"if (!$Pv4) $Vd32 = vmem($Rt32):nt",
26858PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26859let hasNewValue = 1;
26860let opNewValue = 0;
26861let isCVI = 1;
26862let isPseudo = 1;
26863let isCodeGenOnly = 1;
26864let DecoderNamespace = "EXT_mmvec";
26865}
26866def V6_ldnt0 : HInst<
26867(outs HvxVR:$Vd32),
26868(ins IntRegs:$Rt32),
26869"$Vd32 = vmem($Rt32):nt",
26870PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26871let hasNewValue = 1;
26872let opNewValue = 0;
26873let isCVI = 1;
26874let isPseudo = 1;
26875let isCodeGenOnly = 1;
26876let DecoderNamespace = "EXT_mmvec";
26877}
26878def V6_ldp0 : HInst<
26879(outs HvxVR:$Vd32),
26880(ins PredRegs:$Pv4, IntRegs:$Rt32),
26881"if ($Pv4) $Vd32 = vmem($Rt32)",
26882PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26883let hasNewValue = 1;
26884let opNewValue = 0;
26885let isCVI = 1;
26886let isPseudo = 1;
26887let isCodeGenOnly = 1;
26888let DecoderNamespace = "EXT_mmvec";
26889}
26890def V6_ldpnt0 : HInst<
26891(outs HvxVR:$Vd32),
26892(ins PredRegs:$Pv4, IntRegs:$Rt32),
26893"if ($Pv4) $Vd32 = vmem($Rt32):nt",
26894PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26895let hasNewValue = 1;
26896let opNewValue = 0;
26897let isCVI = 1;
26898let isPseudo = 1;
26899let isCodeGenOnly = 1;
26900let DecoderNamespace = "EXT_mmvec";
26901}
26902def V6_ldtnp0 : HInst<
26903(outs HvxVR:$Vd32),
26904(ins PredRegs:$Pv4, IntRegs:$Rt32),
26905"if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
26906PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26907let hasNewValue = 1;
26908let opNewValue = 0;
26909let isCVI = 1;
26910let isPseudo = 1;
26911let isCodeGenOnly = 1;
26912let DecoderNamespace = "EXT_mmvec";
26913}
26914def V6_ldtnpnt0 : HInst<
26915(outs HvxVR:$Vd32),
26916(ins PredRegs:$Pv4, IntRegs:$Rt32),
26917"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
26918PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26919let hasNewValue = 1;
26920let opNewValue = 0;
26921let isCVI = 1;
26922let isPseudo = 1;
26923let isCodeGenOnly = 1;
26924let DecoderNamespace = "EXT_mmvec";
26925}
26926def V6_ldtp0 : HInst<
26927(outs HvxVR:$Vd32),
26928(ins PredRegs:$Pv4, IntRegs:$Rt32),
26929"if ($Pv4) $Vd32.tmp = vmem($Rt32)",
26930PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26931let hasNewValue = 1;
26932let opNewValue = 0;
26933let isCVI = 1;
26934let isPseudo = 1;
26935let isCodeGenOnly = 1;
26936let DecoderNamespace = "EXT_mmvec";
26937}
26938def V6_ldtpnt0 : HInst<
26939(outs HvxVR:$Vd32),
26940(ins PredRegs:$Pv4, IntRegs:$Rt32),
26941"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
26942PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26943let hasNewValue = 1;
26944let opNewValue = 0;
26945let isCVI = 1;
26946let isPseudo = 1;
26947let isCodeGenOnly = 1;
26948let DecoderNamespace = "EXT_mmvec";
26949}
26950def V6_ldu0 : HInst<
26951(outs HvxVR:$Vd32),
26952(ins IntRegs:$Rt32),
26953"$Vd32 = vmemu($Rt32)",
26954PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26955let hasNewValue = 1;
26956let opNewValue = 0;
26957let isCVI = 1;
26958let isPseudo = 1;
26959let isCodeGenOnly = 1;
26960let DecoderNamespace = "EXT_mmvec";
26961}
26962def V6_lo : HInst<
26963(outs HvxVR:$Vd32),
26964(ins HvxWR:$Vss32),
26965"$Vd32 = lo($Vss32)",
26966CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26967let hasNewValue = 1;
26968let opNewValue = 0;
26969let isCVI = 1;
26970let isPseudo = 1;
26971let DecoderNamespace = "EXT_mmvec";
26972}
26973def V6_lvsplatb : HInst<
26974(outs HvxVR:$Vd32),
26975(ins IntRegs:$Rt32),
26976"$Vd32.b = vsplat($Rt32)",
26977tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26978let Inst{13-5} = 0b000000010;
26979let Inst{31-21} = 0b00011001110;
26980let hasNewValue = 1;
26981let opNewValue = 0;
26982let isCVI = 1;
26983let DecoderNamespace = "EXT_mmvec";
26984}
26985def V6_lvsplath : HInst<
26986(outs HvxVR:$Vd32),
26987(ins IntRegs:$Rt32),
26988"$Vd32.h = vsplat($Rt32)",
26989tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26990let Inst{13-5} = 0b000000001;
26991let Inst{31-21} = 0b00011001110;
26992let hasNewValue = 1;
26993let opNewValue = 0;
26994let isCVI = 1;
26995let DecoderNamespace = "EXT_mmvec";
26996}
26997def V6_lvsplatw : HInst<
26998(outs HvxVR:$Vd32),
26999(ins IntRegs:$Rt32),
27000"$Vd32 = vsplat($Rt32)",
27001tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
27002let Inst{13-5} = 0b000000001;
27003let Inst{31-21} = 0b00011001101;
27004let hasNewValue = 1;
27005let opNewValue = 0;
27006let isCVI = 1;
27007let DecoderNamespace = "EXT_mmvec";
27008}
27009def V6_pred_and : HInst<
27010(outs HvxQR:$Qd4),
27011(ins HvxQR:$Qs4, HvxQR:$Qt4),
27012"$Qd4 = and($Qs4,$Qt4)",
27013tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27014let Inst{7-2} = 0b000000;
27015let Inst{13-10} = 0b0000;
27016let Inst{21-16} = 0b000011;
27017let Inst{31-24} = 0b00011110;
27018let hasNewValue = 1;
27019let opNewValue = 0;
27020let isCVI = 1;
27021let DecoderNamespace = "EXT_mmvec";
27022}
27023def V6_pred_and_n : HInst<
27024(outs HvxQR:$Qd4),
27025(ins HvxQR:$Qs4, HvxQR:$Qt4),
27026"$Qd4 = and($Qs4,!$Qt4)",
27027tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27028let Inst{7-2} = 0b000101;
27029let Inst{13-10} = 0b0000;
27030let Inst{21-16} = 0b000011;
27031let Inst{31-24} = 0b00011110;
27032let hasNewValue = 1;
27033let opNewValue = 0;
27034let isCVI = 1;
27035let DecoderNamespace = "EXT_mmvec";
27036}
27037def V6_pred_not : HInst<
27038(outs HvxQR:$Qd4),
27039(ins HvxQR:$Qs4),
27040"$Qd4 = not($Qs4)",
27041tc_0ec46cf9, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
27042let Inst{7-2} = 0b000010;
27043let Inst{13-10} = 0b0000;
27044let Inst{31-16} = 0b0001111000000011;
27045let hasNewValue = 1;
27046let opNewValue = 0;
27047let isCVI = 1;
27048let DecoderNamespace = "EXT_mmvec";
27049}
27050def V6_pred_or : HInst<
27051(outs HvxQR:$Qd4),
27052(ins HvxQR:$Qs4, HvxQR:$Qt4),
27053"$Qd4 = or($Qs4,$Qt4)",
27054tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27055let Inst{7-2} = 0b000001;
27056let Inst{13-10} = 0b0000;
27057let Inst{21-16} = 0b000011;
27058let Inst{31-24} = 0b00011110;
27059let hasNewValue = 1;
27060let opNewValue = 0;
27061let isCVI = 1;
27062let DecoderNamespace = "EXT_mmvec";
27063}
27064def V6_pred_or_n : HInst<
27065(outs HvxQR:$Qd4),
27066(ins HvxQR:$Qs4, HvxQR:$Qt4),
27067"$Qd4 = or($Qs4,!$Qt4)",
27068tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27069let Inst{7-2} = 0b000100;
27070let Inst{13-10} = 0b0000;
27071let Inst{21-16} = 0b000011;
27072let Inst{31-24} = 0b00011110;
27073let hasNewValue = 1;
27074let opNewValue = 0;
27075let isCVI = 1;
27076let DecoderNamespace = "EXT_mmvec";
27077}
27078def V6_pred_scalar2 : HInst<
27079(outs HvxQR:$Qd4),
27080(ins IntRegs:$Rt32),
27081"$Qd4 = vsetq($Rt32)",
27082tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
27083let Inst{13-2} = 0b000000010001;
27084let Inst{31-21} = 0b00011001101;
27085let hasNewValue = 1;
27086let opNewValue = 0;
27087let isCVI = 1;
27088let DecoderNamespace = "EXT_mmvec";
27089}
27090def V6_pred_scalar2v2 : HInst<
27091(outs HvxQR:$Qd4),
27092(ins IntRegs:$Rt32),
27093"$Qd4 = vsetq2($Rt32)",
27094tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
27095let Inst{13-2} = 0b000000010011;
27096let Inst{31-21} = 0b00011001101;
27097let hasNewValue = 1;
27098let opNewValue = 0;
27099let isCVI = 1;
27100let DecoderNamespace = "EXT_mmvec";
27101}
27102def V6_pred_xor : HInst<
27103(outs HvxQR:$Qd4),
27104(ins HvxQR:$Qs4, HvxQR:$Qt4),
27105"$Qd4 = xor($Qs4,$Qt4)",
27106tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27107let Inst{7-2} = 0b000011;
27108let Inst{13-10} = 0b0000;
27109let Inst{21-16} = 0b000011;
27110let Inst{31-24} = 0b00011110;
27111let hasNewValue = 1;
27112let opNewValue = 0;
27113let isCVI = 1;
27114let DecoderNamespace = "EXT_mmvec";
27115}
27116def V6_shuffeqh : HInst<
27117(outs HvxQR:$Qd4),
27118(ins HvxQR:$Qs4, HvxQR:$Qt4),
27119"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
27120tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27121let Inst{7-2} = 0b000110;
27122let Inst{13-10} = 0b0000;
27123let Inst{21-16} = 0b000011;
27124let Inst{31-24} = 0b00011110;
27125let hasNewValue = 1;
27126let opNewValue = 0;
27127let isCVI = 1;
27128let DecoderNamespace = "EXT_mmvec";
27129}
27130def V6_shuffeqw : HInst<
27131(outs HvxQR:$Qd4),
27132(ins HvxQR:$Qs4, HvxQR:$Qt4),
27133"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
27134tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27135let Inst{7-2} = 0b000111;
27136let Inst{13-10} = 0b0000;
27137let Inst{21-16} = 0b000011;
27138let Inst{31-24} = 0b00011110;
27139let hasNewValue = 1;
27140let opNewValue = 0;
27141let isCVI = 1;
27142let DecoderNamespace = "EXT_mmvec";
27143}
27144def V6_st0 : HInst<
27145(outs),
27146(ins IntRegs:$Rt32, HvxVR:$Vs32),
27147"vmem($Rt32) = $Vs32",
27148PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27149let isCVI = 1;
27150let isPseudo = 1;
27151let isCodeGenOnly = 1;
27152let DecoderNamespace = "EXT_mmvec";
27153}
27154def V6_stn0 : HInst<
27155(outs),
27156(ins IntRegs:$Rt32, HvxVR:$Os8),
27157"vmem($Rt32) = $Os8.new",
27158PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27159let isCVI = 1;
27160let isPseudo = 1;
27161let isCodeGenOnly = 1;
27162let DecoderNamespace = "EXT_mmvec";
27163let opNewValue = 1;
27164}
27165def V6_stnnt0 : HInst<
27166(outs),
27167(ins IntRegs:$Rt32, HvxVR:$Os8),
27168"vmem($Rt32):nt = $Os8.new",
27169PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27170let isCVI = 1;
27171let isPseudo = 1;
27172let isCodeGenOnly = 1;
27173let DecoderNamespace = "EXT_mmvec";
27174let opNewValue = 1;
27175}
27176def V6_stnp0 : HInst<
27177(outs),
27178(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27179"if (!$Pv4) vmem($Rt32) = $Vs32",
27180PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27181let isCVI = 1;
27182let isPseudo = 1;
27183let isCodeGenOnly = 1;
27184let DecoderNamespace = "EXT_mmvec";
27185}
27186def V6_stnpnt0 : HInst<
27187(outs),
27188(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27189"if (!$Pv4) vmem($Rt32):nt = $Vs32",
27190PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27191let isCVI = 1;
27192let isPseudo = 1;
27193let isCodeGenOnly = 1;
27194let DecoderNamespace = "EXT_mmvec";
27195}
27196def V6_stnq0 : HInst<
27197(outs),
27198(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27199"if (!$Qv4) vmem($Rt32) = $Vs32",
27200PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27201let isCVI = 1;
27202let isPseudo = 1;
27203let isCodeGenOnly = 1;
27204let DecoderNamespace = "EXT_mmvec";
27205}
27206def V6_stnqnt0 : HInst<
27207(outs),
27208(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27209"if (!$Qv4) vmem($Rt32):nt = $Vs32",
27210PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27211let isCVI = 1;
27212let isPseudo = 1;
27213let isCodeGenOnly = 1;
27214let DecoderNamespace = "EXT_mmvec";
27215}
27216def V6_stnt0 : HInst<
27217(outs),
27218(ins IntRegs:$Rt32, HvxVR:$Vs32),
27219"vmem($Rt32):nt = $Vs32",
27220PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27221let isCVI = 1;
27222let isPseudo = 1;
27223let isCodeGenOnly = 1;
27224let DecoderNamespace = "EXT_mmvec";
27225}
27226def V6_stp0 : HInst<
27227(outs),
27228(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27229"if ($Pv4) vmem($Rt32) = $Vs32",
27230PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27231let isCVI = 1;
27232let isPseudo = 1;
27233let isCodeGenOnly = 1;
27234let DecoderNamespace = "EXT_mmvec";
27235}
27236def V6_stpnt0 : HInst<
27237(outs),
27238(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27239"if ($Pv4) vmem($Rt32):nt = $Vs32",
27240PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27241let isCVI = 1;
27242let isPseudo = 1;
27243let isCodeGenOnly = 1;
27244let DecoderNamespace = "EXT_mmvec";
27245}
27246def V6_stq0 : HInst<
27247(outs),
27248(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27249"if ($Qv4) vmem($Rt32) = $Vs32",
27250PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27251let isCVI = 1;
27252let isPseudo = 1;
27253let isCodeGenOnly = 1;
27254let DecoderNamespace = "EXT_mmvec";
27255}
27256def V6_stqnt0 : HInst<
27257(outs),
27258(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27259"if ($Qv4) vmem($Rt32):nt = $Vs32",
27260PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27261let isCVI = 1;
27262let isPseudo = 1;
27263let isCodeGenOnly = 1;
27264let DecoderNamespace = "EXT_mmvec";
27265}
27266def V6_stu0 : HInst<
27267(outs),
27268(ins IntRegs:$Rt32, HvxVR:$Vs32),
27269"vmemu($Rt32) = $Vs32",
27270PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27271let isCVI = 1;
27272let isPseudo = 1;
27273let isCodeGenOnly = 1;
27274let DecoderNamespace = "EXT_mmvec";
27275}
27276def V6_stunp0 : HInst<
27277(outs),
27278(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27279"if (!$Pv4) vmemu($Rt32) = $Vs32",
27280PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27281let isCVI = 1;
27282let isPseudo = 1;
27283let isCodeGenOnly = 1;
27284let DecoderNamespace = "EXT_mmvec";
27285}
27286def V6_stup0 : HInst<
27287(outs),
27288(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27289"if ($Pv4) vmemu($Rt32) = $Vs32",
27290PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27291let isCVI = 1;
27292let isPseudo = 1;
27293let isCodeGenOnly = 1;
27294let DecoderNamespace = "EXT_mmvec";
27295}
27296def V6_v10mpyubs10 : HInst<
27297(outs HvxWR:$Vdd32),
27298(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u1_0Imm:$Ii),
27299"$Vdd32.w = v10mpy($Vuu32.ub,$Vvv32.b,#$Ii)",
27300tc_f175e046, TypeCVI_VX>, Requires<[UseHVXV69]> {
27301let hasNewValue = 1;
27302let opNewValue = 0;
27303let isCVI = 1;
27304let isPseudo = 1;
27305let DecoderNamespace = "EXT_mmvec";
27306}
27307def V6_v10mpyubs10_vxx : HInst<
27308(outs HvxWR:$Vxx32),
27309(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u1_0Imm:$Ii),
27310"$Vxx32.w += v10mpy($Vuu32.ub,$Vvv32.b,#$Ii)",
27311tc_4942646a, TypeCVI_VX>, Requires<[UseHVXV69]> {
27312let hasNewValue = 1;
27313let opNewValue = 0;
27314let isAccumulator = 1;
27315let isCVI = 1;
27316let isPseudo = 1;
27317let DecoderNamespace = "EXT_mmvec";
27318let Constraints = "$Vxx32 = $Vxx32in";
27319}
27320def V6_v6mpyhubs10 : HInst<
27321(outs HvxWR:$Vdd32),
27322(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27323"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27324tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27325let Inst{7-7} = 0b1;
27326let Inst{13-13} = 0b1;
27327let Inst{31-21} = 0b00011111010;
27328let hasNewValue = 1;
27329let opNewValue = 0;
27330let isCVI = 1;
27331let DecoderNamespace = "EXT_mmvec";
27332}
27333def V6_v6mpyhubs10_alt : HInst<
27334(outs HvxWR:$Vdd32),
27335(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27336"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):h",
27337PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27338let hasNewValue = 1;
27339let opNewValue = 0;
27340let isCVI = 1;
27341let isPseudo = 1;
27342let isCodeGenOnly = 1;
27343let DecoderNamespace = "EXT_mmvec";
27344}
27345def V6_v6mpyhubs10_vxx : HInst<
27346(outs HvxWR:$Vxx32),
27347(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27348"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27349tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27350let Inst{7-7} = 0b1;
27351let Inst{13-13} = 0b1;
27352let Inst{31-21} = 0b00011111001;
27353let hasNewValue = 1;
27354let opNewValue = 0;
27355let isAccumulator = 1;
27356let isCVI = 1;
27357let DecoderNamespace = "EXT_mmvec";
27358let Constraints = "$Vxx32 = $Vxx32in";
27359}
27360def V6_v6mpyvubs10 : HInst<
27361(outs HvxWR:$Vdd32),
27362(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27363"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27364tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27365let Inst{7-7} = 0b0;
27366let Inst{13-13} = 0b1;
27367let Inst{31-21} = 0b00011111010;
27368let hasNewValue = 1;
27369let opNewValue = 0;
27370let isCVI = 1;
27371let DecoderNamespace = "EXT_mmvec";
27372}
27373def V6_v6mpyvubs10_alt : HInst<
27374(outs HvxWR:$Vdd32),
27375(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27376"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):v",
27377PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27378let hasNewValue = 1;
27379let opNewValue = 0;
27380let isCVI = 1;
27381let isPseudo = 1;
27382let isCodeGenOnly = 1;
27383let DecoderNamespace = "EXT_mmvec";
27384}
27385def V6_v6mpyvubs10_vxx : HInst<
27386(outs HvxWR:$Vxx32),
27387(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27388"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27389tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27390let Inst{7-7} = 0b0;
27391let Inst{13-13} = 0b1;
27392let Inst{31-21} = 0b00011111001;
27393let hasNewValue = 1;
27394let opNewValue = 0;
27395let isAccumulator = 1;
27396let isCVI = 1;
27397let DecoderNamespace = "EXT_mmvec";
27398let Constraints = "$Vxx32 = $Vxx32in";
27399}
27400def V6_vL32Ub_ai : HInst<
27401(outs HvxVR:$Vd32),
27402(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27403"$Vd32 = vmemu($Rt32+#$Ii)",
27404tc_a7e6707d, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]>, PostInc_BaseImm {
27405let Inst{7-5} = 0b111;
27406let Inst{12-11} = 0b00;
27407let Inst{31-21} = 0b00101000000;
27408let hasNewValue = 1;
27409let opNewValue = 0;
27410let addrMode = BaseImmOffset;
27411let accessSize = HVXVectorAccess;
27412let isCVLoad = 1;
27413let isCVI = 1;
27414let mayLoad = 1;
27415let isRestrictNoSlot1Store = 1;
27416let BaseOpcode = "V6_vL32Ub_ai";
27417let CextOpcode = "V6_vL32Ub";
27418let DecoderNamespace = "EXT_mmvec";
27419}
27420def V6_vL32Ub_pi : HInst<
27421(outs HvxVR:$Vd32, IntRegs:$Rx32),
27422(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27423"$Vd32 = vmemu($Rx32++#$Ii)",
27424tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]>, PostInc_BaseImm {
27425let Inst{7-5} = 0b111;
27426let Inst{13-11} = 0b000;
27427let Inst{31-21} = 0b00101001000;
27428let hasNewValue = 1;
27429let opNewValue = 0;
27430let addrMode = PostInc;
27431let accessSize = HVXVectorAccess;
27432let isCVLoad = 1;
27433let isCVI = 1;
27434let mayLoad = 1;
27435let isRestrictNoSlot1Store = 1;
27436let BaseOpcode = "V6_vL32b_pi";
27437let CextOpcode = "V6_vL32Ub";
27438let DecoderNamespace = "EXT_mmvec";
27439let Constraints = "$Rx32 = $Rx32in";
27440}
27441def V6_vL32Ub_ppu : HInst<
27442(outs HvxVR:$Vd32, IntRegs:$Rx32),
27443(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27444"$Vd32 = vmemu($Rx32++$Mu2)",
27445tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
27446let Inst{12-5} = 0b00000111;
27447let Inst{31-21} = 0b00101011000;
27448let hasNewValue = 1;
27449let opNewValue = 0;
27450let addrMode = PostInc;
27451let accessSize = HVXVectorAccess;
27452let isCVLoad = 1;
27453let isCVI = 1;
27454let mayLoad = 1;
27455let isRestrictNoSlot1Store = 1;
27456let DecoderNamespace = "EXT_mmvec";
27457let Constraints = "$Rx32 = $Rx32in";
27458}
27459def V6_vL32b_ai : HInst<
27460(outs HvxVR:$Vd32),
27461(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27462"$Vd32 = vmem($Rt32+#$Ii)",
27463tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27464let Inst{7-5} = 0b000;
27465let Inst{12-11} = 0b00;
27466let Inst{31-21} = 0b00101000000;
27467let hasNewValue = 1;
27468let opNewValue = 0;
27469let addrMode = BaseImmOffset;
27470let accessSize = HVXVectorAccess;
27471let isCVLoad = 1;
27472let isCVI = 1;
27473let mayLoad = 1;
27474let isRestrictNoSlot1Store = 1;
27475let BaseOpcode = "V6_vL32b_ai";
27476let CextOpcode = "V6_vL32b";
27477let isCVLoadable = 1;
27478let isPredicable = 1;
27479let DecoderNamespace = "EXT_mmvec";
27480}
27481def V6_vL32b_cur_ai : HInst<
27482(outs HvxVR:$Vd32),
27483(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27484"$Vd32.cur = vmem($Rt32+#$Ii)",
27485tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27486let Inst{7-5} = 0b001;
27487let Inst{12-11} = 0b00;
27488let Inst{31-21} = 0b00101000000;
27489let hasNewValue = 1;
27490let opNewValue = 0;
27491let addrMode = BaseImmOffset;
27492let accessSize = HVXVectorAccess;
27493let isCVLoad = 1;
27494let isCVI = 1;
27495let CVINew = 1;
27496let mayLoad = 1;
27497let isRestrictNoSlot1Store = 1;
27498let BaseOpcode = "V6_vL32b_cur_ai";
27499let CextOpcode = "V6_vL32b_cur";
27500let isPredicable = 1;
27501let DecoderNamespace = "EXT_mmvec";
27502}
27503def V6_vL32b_cur_npred_ai : HInst<
27504(outs HvxVR:$Vd32),
27505(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27506"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27507tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27508let Inst{7-5} = 0b101;
27509let Inst{31-21} = 0b00101000100;
27510let isPredicated = 1;
27511let isPredicatedFalse = 1;
27512let hasNewValue = 1;
27513let opNewValue = 0;
27514let addrMode = BaseImmOffset;
27515let accessSize = HVXVectorAccess;
27516let isCVLoad = 1;
27517let isCVI = 1;
27518let CVINew = 1;
27519let mayLoad = 1;
27520let isRestrictNoSlot1Store = 1;
27521let BaseOpcode = "V6_vL32b_cur_ai";
27522let DecoderNamespace = "EXT_mmvec";
27523}
27524def V6_vL32b_cur_npred_pi : HInst<
27525(outs HvxVR:$Vd32, IntRegs:$Rx32),
27526(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27527"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27528tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27529let Inst{7-5} = 0b101;
27530let Inst{13-13} = 0b0;
27531let Inst{31-21} = 0b00101001100;
27532let isPredicated = 1;
27533let isPredicatedFalse = 1;
27534let hasNewValue = 1;
27535let opNewValue = 0;
27536let addrMode = PostInc;
27537let accessSize = HVXVectorAccess;
27538let isCVLoad = 1;
27539let isCVI = 1;
27540let CVINew = 1;
27541let mayLoad = 1;
27542let isRestrictNoSlot1Store = 1;
27543let BaseOpcode = "V6_vL32b_cur_pi";
27544let DecoderNamespace = "EXT_mmvec";
27545let Constraints = "$Rx32 = $Rx32in";
27546}
27547def V6_vL32b_cur_npred_ppu : HInst<
27548(outs HvxVR:$Vd32, IntRegs:$Rx32),
27549(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27550"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27551tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27552let Inst{10-5} = 0b000101;
27553let Inst{31-21} = 0b00101011100;
27554let isPredicated = 1;
27555let isPredicatedFalse = 1;
27556let hasNewValue = 1;
27557let opNewValue = 0;
27558let addrMode = PostInc;
27559let accessSize = HVXVectorAccess;
27560let isCVLoad = 1;
27561let isCVI = 1;
27562let CVINew = 1;
27563let mayLoad = 1;
27564let isRestrictNoSlot1Store = 1;
27565let BaseOpcode = "V6_vL32b_cur_ppu";
27566let DecoderNamespace = "EXT_mmvec";
27567let Constraints = "$Rx32 = $Rx32in";
27568}
27569def V6_vL32b_cur_pi : HInst<
27570(outs HvxVR:$Vd32, IntRegs:$Rx32),
27571(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27572"$Vd32.cur = vmem($Rx32++#$Ii)",
27573tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27574let Inst{7-5} = 0b001;
27575let Inst{13-11} = 0b000;
27576let Inst{31-21} = 0b00101001000;
27577let hasNewValue = 1;
27578let opNewValue = 0;
27579let addrMode = PostInc;
27580let accessSize = HVXVectorAccess;
27581let isCVLoad = 1;
27582let isCVI = 1;
27583let CVINew = 1;
27584let mayLoad = 1;
27585let isRestrictNoSlot1Store = 1;
27586let BaseOpcode = "V6_vL32b_cur_pi";
27587let CextOpcode = "V6_vL32b_cur";
27588let isPredicable = 1;
27589let DecoderNamespace = "EXT_mmvec";
27590let Constraints = "$Rx32 = $Rx32in";
27591}
27592def V6_vL32b_cur_ppu : HInst<
27593(outs HvxVR:$Vd32, IntRegs:$Rx32),
27594(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27595"$Vd32.cur = vmem($Rx32++$Mu2)",
27596tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27597let Inst{12-5} = 0b00000001;
27598let Inst{31-21} = 0b00101011000;
27599let hasNewValue = 1;
27600let opNewValue = 0;
27601let addrMode = PostInc;
27602let accessSize = HVXVectorAccess;
27603let isCVLoad = 1;
27604let isCVI = 1;
27605let CVINew = 1;
27606let mayLoad = 1;
27607let isRestrictNoSlot1Store = 1;
27608let BaseOpcode = "V6_vL32b_cur_ppu";
27609let isPredicable = 1;
27610let DecoderNamespace = "EXT_mmvec";
27611let Constraints = "$Rx32 = $Rx32in";
27612}
27613def V6_vL32b_cur_pred_ai : HInst<
27614(outs HvxVR:$Vd32),
27615(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27616"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27617tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27618let Inst{7-5} = 0b100;
27619let Inst{31-21} = 0b00101000100;
27620let isPredicated = 1;
27621let hasNewValue = 1;
27622let opNewValue = 0;
27623let addrMode = BaseImmOffset;
27624let accessSize = HVXVectorAccess;
27625let isCVLoad = 1;
27626let isCVI = 1;
27627let CVINew = 1;
27628let mayLoad = 1;
27629let isRestrictNoSlot1Store = 1;
27630let BaseOpcode = "V6_vL32b_cur_ai";
27631let DecoderNamespace = "EXT_mmvec";
27632}
27633def V6_vL32b_cur_pred_pi : HInst<
27634(outs HvxVR:$Vd32, IntRegs:$Rx32),
27635(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27636"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27637tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27638let Inst{7-5} = 0b100;
27639let Inst{13-13} = 0b0;
27640let Inst{31-21} = 0b00101001100;
27641let isPredicated = 1;
27642let hasNewValue = 1;
27643let opNewValue = 0;
27644let addrMode = PostInc;
27645let accessSize = HVXVectorAccess;
27646let isCVLoad = 1;
27647let isCVI = 1;
27648let CVINew = 1;
27649let mayLoad = 1;
27650let isRestrictNoSlot1Store = 1;
27651let BaseOpcode = "V6_vL32b_cur_pi";
27652let DecoderNamespace = "EXT_mmvec";
27653let Constraints = "$Rx32 = $Rx32in";
27654}
27655def V6_vL32b_cur_pred_ppu : HInst<
27656(outs HvxVR:$Vd32, IntRegs:$Rx32),
27657(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27658"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27659tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27660let Inst{10-5} = 0b000100;
27661let Inst{31-21} = 0b00101011100;
27662let isPredicated = 1;
27663let hasNewValue = 1;
27664let opNewValue = 0;
27665let addrMode = PostInc;
27666let accessSize = HVXVectorAccess;
27667let isCVLoad = 1;
27668let isCVI = 1;
27669let CVINew = 1;
27670let mayLoad = 1;
27671let isRestrictNoSlot1Store = 1;
27672let BaseOpcode = "V6_vL32b_cur_ppu";
27673let DecoderNamespace = "EXT_mmvec";
27674let Constraints = "$Rx32 = $Rx32in";
27675}
27676def V6_vL32b_npred_ai : HInst<
27677(outs HvxVR:$Vd32),
27678(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27679"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27680tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27681let Inst{7-5} = 0b011;
27682let Inst{31-21} = 0b00101000100;
27683let isPredicated = 1;
27684let isPredicatedFalse = 1;
27685let hasNewValue = 1;
27686let opNewValue = 0;
27687let addrMode = BaseImmOffset;
27688let accessSize = HVXVectorAccess;
27689let isCVLoad = 1;
27690let isCVI = 1;
27691let mayLoad = 1;
27692let isRestrictNoSlot1Store = 1;
27693let BaseOpcode = "V6_vL32b_ai";
27694let DecoderNamespace = "EXT_mmvec";
27695}
27696def V6_vL32b_npred_pi : HInst<
27697(outs HvxVR:$Vd32, IntRegs:$Rx32),
27698(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27699"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27700tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27701let Inst{7-5} = 0b011;
27702let Inst{13-13} = 0b0;
27703let Inst{31-21} = 0b00101001100;
27704let isPredicated = 1;
27705let isPredicatedFalse = 1;
27706let hasNewValue = 1;
27707let opNewValue = 0;
27708let addrMode = PostInc;
27709let accessSize = HVXVectorAccess;
27710let isCVLoad = 1;
27711let isCVI = 1;
27712let mayLoad = 1;
27713let isRestrictNoSlot1Store = 1;
27714let BaseOpcode = "V6_vL32b_pi";
27715let DecoderNamespace = "EXT_mmvec";
27716let Constraints = "$Rx32 = $Rx32in";
27717}
27718def V6_vL32b_npred_ppu : HInst<
27719(outs HvxVR:$Vd32, IntRegs:$Rx32),
27720(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27721"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27722tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27723let Inst{10-5} = 0b000011;
27724let Inst{31-21} = 0b00101011100;
27725let isPredicated = 1;
27726let isPredicatedFalse = 1;
27727let hasNewValue = 1;
27728let opNewValue = 0;
27729let addrMode = PostInc;
27730let accessSize = HVXVectorAccess;
27731let isCVLoad = 1;
27732let isCVI = 1;
27733let mayLoad = 1;
27734let isRestrictNoSlot1Store = 1;
27735let BaseOpcode = "V6_vL32b_ppu";
27736let DecoderNamespace = "EXT_mmvec";
27737let Constraints = "$Rx32 = $Rx32in";
27738}
27739def V6_vL32b_nt_ai : HInst<
27740(outs HvxVR:$Vd32),
27741(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27742"$Vd32 = vmem($Rt32+#$Ii):nt",
27743tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27744let Inst{7-5} = 0b000;
27745let Inst{12-11} = 0b00;
27746let Inst{31-21} = 0b00101000010;
27747let hasNewValue = 1;
27748let opNewValue = 0;
27749let addrMode = BaseImmOffset;
27750let accessSize = HVXVectorAccess;
27751let isCVLoad = 1;
27752let isCVI = 1;
27753let mayLoad = 1;
27754let isNonTemporal = 1;
27755let isRestrictNoSlot1Store = 1;
27756let BaseOpcode = "V6_vL32b_nt_ai";
27757let CextOpcode = "V6_vL32b_nt";
27758let isCVLoadable = 1;
27759let isPredicable = 1;
27760let DecoderNamespace = "EXT_mmvec";
27761}
27762def V6_vL32b_nt_cur_ai : HInst<
27763(outs HvxVR:$Vd32),
27764(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27765"$Vd32.cur = vmem($Rt32+#$Ii):nt",
27766tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27767let Inst{7-5} = 0b001;
27768let Inst{12-11} = 0b00;
27769let Inst{31-21} = 0b00101000010;
27770let hasNewValue = 1;
27771let opNewValue = 0;
27772let addrMode = BaseImmOffset;
27773let accessSize = HVXVectorAccess;
27774let isCVLoad = 1;
27775let isCVI = 1;
27776let CVINew = 1;
27777let mayLoad = 1;
27778let isNonTemporal = 1;
27779let isRestrictNoSlot1Store = 1;
27780let BaseOpcode = "V6_vL32b_nt_cur_ai";
27781let CextOpcode = "V6_vL32b_nt_cur";
27782let isPredicable = 1;
27783let DecoderNamespace = "EXT_mmvec";
27784}
27785def V6_vL32b_nt_cur_npred_ai : HInst<
27786(outs HvxVR:$Vd32),
27787(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27788"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27789tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27790let Inst{7-5} = 0b101;
27791let Inst{31-21} = 0b00101000110;
27792let isPredicated = 1;
27793let isPredicatedFalse = 1;
27794let hasNewValue = 1;
27795let opNewValue = 0;
27796let addrMode = BaseImmOffset;
27797let accessSize = HVXVectorAccess;
27798let isCVLoad = 1;
27799let isCVI = 1;
27800let CVINew = 1;
27801let mayLoad = 1;
27802let isNonTemporal = 1;
27803let isRestrictNoSlot1Store = 1;
27804let BaseOpcode = "V6_vL32b_nt_cur_ai";
27805let DecoderNamespace = "EXT_mmvec";
27806}
27807def V6_vL32b_nt_cur_npred_pi : HInst<
27808(outs HvxVR:$Vd32, IntRegs:$Rx32),
27809(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27810"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27811tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27812let Inst{7-5} = 0b101;
27813let Inst{13-13} = 0b0;
27814let Inst{31-21} = 0b00101001110;
27815let isPredicated = 1;
27816let isPredicatedFalse = 1;
27817let hasNewValue = 1;
27818let opNewValue = 0;
27819let addrMode = PostInc;
27820let accessSize = HVXVectorAccess;
27821let isCVLoad = 1;
27822let isCVI = 1;
27823let CVINew = 1;
27824let mayLoad = 1;
27825let isNonTemporal = 1;
27826let isRestrictNoSlot1Store = 1;
27827let BaseOpcode = "V6_vL32b_nt_cur_pi";
27828let DecoderNamespace = "EXT_mmvec";
27829let Constraints = "$Rx32 = $Rx32in";
27830}
27831def V6_vL32b_nt_cur_npred_ppu : HInst<
27832(outs HvxVR:$Vd32, IntRegs:$Rx32),
27833(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27834"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27835tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27836let Inst{10-5} = 0b000101;
27837let Inst{31-21} = 0b00101011110;
27838let isPredicated = 1;
27839let isPredicatedFalse = 1;
27840let hasNewValue = 1;
27841let opNewValue = 0;
27842let addrMode = PostInc;
27843let accessSize = HVXVectorAccess;
27844let isCVLoad = 1;
27845let isCVI = 1;
27846let CVINew = 1;
27847let mayLoad = 1;
27848let isNonTemporal = 1;
27849let isRestrictNoSlot1Store = 1;
27850let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27851let DecoderNamespace = "EXT_mmvec";
27852let Constraints = "$Rx32 = $Rx32in";
27853}
27854def V6_vL32b_nt_cur_pi : HInst<
27855(outs HvxVR:$Vd32, IntRegs:$Rx32),
27856(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27857"$Vd32.cur = vmem($Rx32++#$Ii):nt",
27858tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27859let Inst{7-5} = 0b001;
27860let Inst{13-11} = 0b000;
27861let Inst{31-21} = 0b00101001010;
27862let hasNewValue = 1;
27863let opNewValue = 0;
27864let addrMode = PostInc;
27865let accessSize = HVXVectorAccess;
27866let isCVLoad = 1;
27867let isCVI = 1;
27868let CVINew = 1;
27869let mayLoad = 1;
27870let isNonTemporal = 1;
27871let isRestrictNoSlot1Store = 1;
27872let BaseOpcode = "V6_vL32b_nt_cur_pi";
27873let CextOpcode = "V6_vL32b_nt_cur";
27874let isPredicable = 1;
27875let DecoderNamespace = "EXT_mmvec";
27876let Constraints = "$Rx32 = $Rx32in";
27877}
27878def V6_vL32b_nt_cur_ppu : HInst<
27879(outs HvxVR:$Vd32, IntRegs:$Rx32),
27880(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27881"$Vd32.cur = vmem($Rx32++$Mu2):nt",
27882tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27883let Inst{12-5} = 0b00000001;
27884let Inst{31-21} = 0b00101011010;
27885let hasNewValue = 1;
27886let opNewValue = 0;
27887let addrMode = PostInc;
27888let accessSize = HVXVectorAccess;
27889let isCVLoad = 1;
27890let isCVI = 1;
27891let CVINew = 1;
27892let mayLoad = 1;
27893let isNonTemporal = 1;
27894let isRestrictNoSlot1Store = 1;
27895let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27896let isPredicable = 1;
27897let DecoderNamespace = "EXT_mmvec";
27898let Constraints = "$Rx32 = $Rx32in";
27899}
27900def V6_vL32b_nt_cur_pred_ai : HInst<
27901(outs HvxVR:$Vd32),
27902(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27903"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27904tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27905let Inst{7-5} = 0b100;
27906let Inst{31-21} = 0b00101000110;
27907let isPredicated = 1;
27908let hasNewValue = 1;
27909let opNewValue = 0;
27910let addrMode = BaseImmOffset;
27911let accessSize = HVXVectorAccess;
27912let isCVLoad = 1;
27913let isCVI = 1;
27914let CVINew = 1;
27915let mayLoad = 1;
27916let isNonTemporal = 1;
27917let isRestrictNoSlot1Store = 1;
27918let BaseOpcode = "V6_vL32b_nt_cur_ai";
27919let DecoderNamespace = "EXT_mmvec";
27920}
27921def V6_vL32b_nt_cur_pred_pi : HInst<
27922(outs HvxVR:$Vd32, IntRegs:$Rx32),
27923(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27924"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27925tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27926let Inst{7-5} = 0b100;
27927let Inst{13-13} = 0b0;
27928let Inst{31-21} = 0b00101001110;
27929let isPredicated = 1;
27930let hasNewValue = 1;
27931let opNewValue = 0;
27932let addrMode = PostInc;
27933let accessSize = HVXVectorAccess;
27934let isCVLoad = 1;
27935let isCVI = 1;
27936let CVINew = 1;
27937let mayLoad = 1;
27938let isNonTemporal = 1;
27939let isRestrictNoSlot1Store = 1;
27940let BaseOpcode = "V6_vL32b_nt_cur_pi";
27941let DecoderNamespace = "EXT_mmvec";
27942let Constraints = "$Rx32 = $Rx32in";
27943}
27944def V6_vL32b_nt_cur_pred_ppu : HInst<
27945(outs HvxVR:$Vd32, IntRegs:$Rx32),
27946(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27947"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27948tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27949let Inst{10-5} = 0b000100;
27950let Inst{31-21} = 0b00101011110;
27951let isPredicated = 1;
27952let hasNewValue = 1;
27953let opNewValue = 0;
27954let addrMode = PostInc;
27955let accessSize = HVXVectorAccess;
27956let isCVLoad = 1;
27957let isCVI = 1;
27958let CVINew = 1;
27959let mayLoad = 1;
27960let isNonTemporal = 1;
27961let isRestrictNoSlot1Store = 1;
27962let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27963let DecoderNamespace = "EXT_mmvec";
27964let Constraints = "$Rx32 = $Rx32in";
27965}
27966def V6_vL32b_nt_npred_ai : HInst<
27967(outs HvxVR:$Vd32),
27968(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27969"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27970tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27971let Inst{7-5} = 0b011;
27972let Inst{31-21} = 0b00101000110;
27973let isPredicated = 1;
27974let isPredicatedFalse = 1;
27975let hasNewValue = 1;
27976let opNewValue = 0;
27977let addrMode = BaseImmOffset;
27978let accessSize = HVXVectorAccess;
27979let isCVLoad = 1;
27980let isCVI = 1;
27981let mayLoad = 1;
27982let isNonTemporal = 1;
27983let isRestrictNoSlot1Store = 1;
27984let BaseOpcode = "V6_vL32b_nt_ai";
27985let DecoderNamespace = "EXT_mmvec";
27986}
27987def V6_vL32b_nt_npred_pi : HInst<
27988(outs HvxVR:$Vd32, IntRegs:$Rx32),
27989(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27990"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27991tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27992let Inst{7-5} = 0b011;
27993let Inst{13-13} = 0b0;
27994let Inst{31-21} = 0b00101001110;
27995let isPredicated = 1;
27996let isPredicatedFalse = 1;
27997let hasNewValue = 1;
27998let opNewValue = 0;
27999let addrMode = PostInc;
28000let accessSize = HVXVectorAccess;
28001let isCVLoad = 1;
28002let isCVI = 1;
28003let mayLoad = 1;
28004let isNonTemporal = 1;
28005let isRestrictNoSlot1Store = 1;
28006let BaseOpcode = "V6_vL32b_nt_pi";
28007let DecoderNamespace = "EXT_mmvec";
28008let Constraints = "$Rx32 = $Rx32in";
28009}
28010def V6_vL32b_nt_npred_ppu : HInst<
28011(outs HvxVR:$Vd32, IntRegs:$Rx32),
28012(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28013"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28014tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28015let Inst{10-5} = 0b000011;
28016let Inst{31-21} = 0b00101011110;
28017let isPredicated = 1;
28018let isPredicatedFalse = 1;
28019let hasNewValue = 1;
28020let opNewValue = 0;
28021let addrMode = PostInc;
28022let accessSize = HVXVectorAccess;
28023let isCVLoad = 1;
28024let isCVI = 1;
28025let mayLoad = 1;
28026let isNonTemporal = 1;
28027let isRestrictNoSlot1Store = 1;
28028let BaseOpcode = "V6_vL32b_nt_ppu";
28029let DecoderNamespace = "EXT_mmvec";
28030let Constraints = "$Rx32 = $Rx32in";
28031}
28032def V6_vL32b_nt_pi : HInst<
28033(outs HvxVR:$Vd32, IntRegs:$Rx32),
28034(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28035"$Vd32 = vmem($Rx32++#$Ii):nt",
28036tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28037let Inst{7-5} = 0b000;
28038let Inst{13-11} = 0b000;
28039let Inst{31-21} = 0b00101001010;
28040let hasNewValue = 1;
28041let opNewValue = 0;
28042let addrMode = PostInc;
28043let accessSize = HVXVectorAccess;
28044let isCVLoad = 1;
28045let isCVI = 1;
28046let mayLoad = 1;
28047let isNonTemporal = 1;
28048let isRestrictNoSlot1Store = 1;
28049let BaseOpcode = "V6_vL32b_nt_pi";
28050let CextOpcode = "V6_vL32b_nt";
28051let isCVLoadable = 1;
28052let isPredicable = 1;
28053let DecoderNamespace = "EXT_mmvec";
28054let Constraints = "$Rx32 = $Rx32in";
28055}
28056def V6_vL32b_nt_ppu : HInst<
28057(outs HvxVR:$Vd32, IntRegs:$Rx32),
28058(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28059"$Vd32 = vmem($Rx32++$Mu2):nt",
28060tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28061let Inst{12-5} = 0b00000000;
28062let Inst{31-21} = 0b00101011010;
28063let hasNewValue = 1;
28064let opNewValue = 0;
28065let addrMode = PostInc;
28066let accessSize = HVXVectorAccess;
28067let isCVLoad = 1;
28068let isCVI = 1;
28069let mayLoad = 1;
28070let isNonTemporal = 1;
28071let isRestrictNoSlot1Store = 1;
28072let BaseOpcode = "V6_vL32b_nt_ppu";
28073let isCVLoadable = 1;
28074let isPredicable = 1;
28075let DecoderNamespace = "EXT_mmvec";
28076let Constraints = "$Rx32 = $Rx32in";
28077}
28078def V6_vL32b_nt_pred_ai : HInst<
28079(outs HvxVR:$Vd32),
28080(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28081"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
28082tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28083let Inst{7-5} = 0b010;
28084let Inst{31-21} = 0b00101000110;
28085let isPredicated = 1;
28086let hasNewValue = 1;
28087let opNewValue = 0;
28088let addrMode = BaseImmOffset;
28089let accessSize = HVXVectorAccess;
28090let isCVLoad = 1;
28091let isCVI = 1;
28092let mayLoad = 1;
28093let isNonTemporal = 1;
28094let isRestrictNoSlot1Store = 1;
28095let BaseOpcode = "V6_vL32b_nt_ai";
28096let DecoderNamespace = "EXT_mmvec";
28097}
28098def V6_vL32b_nt_pred_pi : HInst<
28099(outs HvxVR:$Vd32, IntRegs:$Rx32),
28100(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28101"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
28102tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28103let Inst{7-5} = 0b010;
28104let Inst{13-13} = 0b0;
28105let Inst{31-21} = 0b00101001110;
28106let isPredicated = 1;
28107let hasNewValue = 1;
28108let opNewValue = 0;
28109let addrMode = PostInc;
28110let accessSize = HVXVectorAccess;
28111let isCVLoad = 1;
28112let isCVI = 1;
28113let mayLoad = 1;
28114let isNonTemporal = 1;
28115let isRestrictNoSlot1Store = 1;
28116let BaseOpcode = "V6_vL32b_nt_pi";
28117let DecoderNamespace = "EXT_mmvec";
28118let Constraints = "$Rx32 = $Rx32in";
28119}
28120def V6_vL32b_nt_pred_ppu : HInst<
28121(outs HvxVR:$Vd32, IntRegs:$Rx32),
28122(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28123"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28124tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28125let Inst{10-5} = 0b000010;
28126let Inst{31-21} = 0b00101011110;
28127let isPredicated = 1;
28128let hasNewValue = 1;
28129let opNewValue = 0;
28130let addrMode = PostInc;
28131let accessSize = HVXVectorAccess;
28132let isCVLoad = 1;
28133let isCVI = 1;
28134let mayLoad = 1;
28135let isNonTemporal = 1;
28136let isRestrictNoSlot1Store = 1;
28137let BaseOpcode = "V6_vL32b_nt_ppu";
28138let DecoderNamespace = "EXT_mmvec";
28139let Constraints = "$Rx32 = $Rx32in";
28140}
28141def V6_vL32b_nt_tmp_ai : HInst<
28142(outs HvxVR:$Vd32),
28143(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28144"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
28145tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28146let Inst{7-5} = 0b010;
28147let Inst{12-11} = 0b00;
28148let Inst{31-21} = 0b00101000010;
28149let hasNewValue = 1;
28150let opNewValue = 0;
28151let addrMode = BaseImmOffset;
28152let accessSize = HVXVectorAccess;
28153let isCVLoad = 1;
28154let isCVI = 1;
28155let hasHvxTmp = 1;
28156let mayLoad = 1;
28157let isNonTemporal = 1;
28158let isRestrictNoSlot1Store = 1;
28159let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28160let CextOpcode = "V6_vL32b_nt_tmp";
28161let isPredicable = 1;
28162let DecoderNamespace = "EXT_mmvec";
28163}
28164def V6_vL32b_nt_tmp_npred_ai : HInst<
28165(outs HvxVR:$Vd32),
28166(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28167"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28168tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28169let Inst{7-5} = 0b111;
28170let Inst{31-21} = 0b00101000110;
28171let isPredicated = 1;
28172let isPredicatedFalse = 1;
28173let hasNewValue = 1;
28174let opNewValue = 0;
28175let addrMode = BaseImmOffset;
28176let accessSize = HVXVectorAccess;
28177let isCVLoad = 1;
28178let isCVI = 1;
28179let hasHvxTmp = 1;
28180let mayLoad = 1;
28181let isNonTemporal = 1;
28182let isRestrictNoSlot1Store = 1;
28183let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28184let DecoderNamespace = "EXT_mmvec";
28185}
28186def V6_vL32b_nt_tmp_npred_pi : HInst<
28187(outs HvxVR:$Vd32, IntRegs:$Rx32),
28188(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28189"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28190tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28191let Inst{7-5} = 0b111;
28192let Inst{13-13} = 0b0;
28193let Inst{31-21} = 0b00101001110;
28194let isPredicated = 1;
28195let isPredicatedFalse = 1;
28196let hasNewValue = 1;
28197let opNewValue = 0;
28198let addrMode = PostInc;
28199let accessSize = HVXVectorAccess;
28200let isCVLoad = 1;
28201let isCVI = 1;
28202let hasHvxTmp = 1;
28203let mayLoad = 1;
28204let isNonTemporal = 1;
28205let isRestrictNoSlot1Store = 1;
28206let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28207let DecoderNamespace = "EXT_mmvec";
28208let Constraints = "$Rx32 = $Rx32in";
28209}
28210def V6_vL32b_nt_tmp_npred_ppu : HInst<
28211(outs HvxVR:$Vd32, IntRegs:$Rx32),
28212(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28213"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28214tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28215let Inst{10-5} = 0b000111;
28216let Inst{31-21} = 0b00101011110;
28217let isPredicated = 1;
28218let isPredicatedFalse = 1;
28219let hasNewValue = 1;
28220let opNewValue = 0;
28221let addrMode = PostInc;
28222let accessSize = HVXVectorAccess;
28223let isCVLoad = 1;
28224let isCVI = 1;
28225let hasHvxTmp = 1;
28226let mayLoad = 1;
28227let isNonTemporal = 1;
28228let isRestrictNoSlot1Store = 1;
28229let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28230let DecoderNamespace = "EXT_mmvec";
28231let Constraints = "$Rx32 = $Rx32in";
28232}
28233def V6_vL32b_nt_tmp_pi : HInst<
28234(outs HvxVR:$Vd32, IntRegs:$Rx32),
28235(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28236"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
28237tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28238let Inst{7-5} = 0b010;
28239let Inst{13-11} = 0b000;
28240let Inst{31-21} = 0b00101001010;
28241let hasNewValue = 1;
28242let opNewValue = 0;
28243let addrMode = PostInc;
28244let accessSize = HVXVectorAccess;
28245let isCVLoad = 1;
28246let isCVI = 1;
28247let hasHvxTmp = 1;
28248let mayLoad = 1;
28249let isNonTemporal = 1;
28250let isRestrictNoSlot1Store = 1;
28251let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28252let CextOpcode = "V6_vL32b_nt_tmp";
28253let isPredicable = 1;
28254let DecoderNamespace = "EXT_mmvec";
28255let Constraints = "$Rx32 = $Rx32in";
28256}
28257def V6_vL32b_nt_tmp_ppu : HInst<
28258(outs HvxVR:$Vd32, IntRegs:$Rx32),
28259(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28260"$Vd32.tmp = vmem($Rx32++$Mu2):nt",
28261tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28262let Inst{12-5} = 0b00000010;
28263let Inst{31-21} = 0b00101011010;
28264let hasNewValue = 1;
28265let opNewValue = 0;
28266let addrMode = PostInc;
28267let accessSize = HVXVectorAccess;
28268let isCVLoad = 1;
28269let isCVI = 1;
28270let hasHvxTmp = 1;
28271let mayLoad = 1;
28272let isNonTemporal = 1;
28273let isRestrictNoSlot1Store = 1;
28274let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28275let isPredicable = 1;
28276let DecoderNamespace = "EXT_mmvec";
28277let Constraints = "$Rx32 = $Rx32in";
28278}
28279def V6_vL32b_nt_tmp_pred_ai : HInst<
28280(outs HvxVR:$Vd32),
28281(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28282"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28283tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28284let Inst{7-5} = 0b110;
28285let Inst{31-21} = 0b00101000110;
28286let isPredicated = 1;
28287let hasNewValue = 1;
28288let opNewValue = 0;
28289let addrMode = BaseImmOffset;
28290let accessSize = HVXVectorAccess;
28291let isCVLoad = 1;
28292let isCVI = 1;
28293let hasHvxTmp = 1;
28294let mayLoad = 1;
28295let isNonTemporal = 1;
28296let isRestrictNoSlot1Store = 1;
28297let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28298let DecoderNamespace = "EXT_mmvec";
28299}
28300def V6_vL32b_nt_tmp_pred_pi : HInst<
28301(outs HvxVR:$Vd32, IntRegs:$Rx32),
28302(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28303"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28304tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28305let Inst{7-5} = 0b110;
28306let Inst{13-13} = 0b0;
28307let Inst{31-21} = 0b00101001110;
28308let isPredicated = 1;
28309let hasNewValue = 1;
28310let opNewValue = 0;
28311let addrMode = PostInc;
28312let accessSize = HVXVectorAccess;
28313let isCVLoad = 1;
28314let isCVI = 1;
28315let hasHvxTmp = 1;
28316let mayLoad = 1;
28317let isNonTemporal = 1;
28318let isRestrictNoSlot1Store = 1;
28319let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28320let DecoderNamespace = "EXT_mmvec";
28321let Constraints = "$Rx32 = $Rx32in";
28322}
28323def V6_vL32b_nt_tmp_pred_ppu : HInst<
28324(outs HvxVR:$Vd32, IntRegs:$Rx32),
28325(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28326"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28327tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28328let Inst{10-5} = 0b000110;
28329let Inst{31-21} = 0b00101011110;
28330let isPredicated = 1;
28331let hasNewValue = 1;
28332let opNewValue = 0;
28333let addrMode = PostInc;
28334let accessSize = HVXVectorAccess;
28335let isCVLoad = 1;
28336let isCVI = 1;
28337let hasHvxTmp = 1;
28338let mayLoad = 1;
28339let isNonTemporal = 1;
28340let isRestrictNoSlot1Store = 1;
28341let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28342let DecoderNamespace = "EXT_mmvec";
28343let Constraints = "$Rx32 = $Rx32in";
28344}
28345def V6_vL32b_pi : HInst<
28346(outs HvxVR:$Vd32, IntRegs:$Rx32),
28347(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28348"$Vd32 = vmem($Rx32++#$Ii)",
28349tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28350let Inst{7-5} = 0b000;
28351let Inst{13-11} = 0b000;
28352let Inst{31-21} = 0b00101001000;
28353let hasNewValue = 1;
28354let opNewValue = 0;
28355let addrMode = PostInc;
28356let accessSize = HVXVectorAccess;
28357let isCVLoad = 1;
28358let isCVI = 1;
28359let mayLoad = 1;
28360let isRestrictNoSlot1Store = 1;
28361let BaseOpcode = "V6_vL32b_pi";
28362let CextOpcode = "V6_vL32b";
28363let isCVLoadable = 1;
28364let isPredicable = 1;
28365let DecoderNamespace = "EXT_mmvec";
28366let Constraints = "$Rx32 = $Rx32in";
28367}
28368def V6_vL32b_ppu : HInst<
28369(outs HvxVR:$Vd32, IntRegs:$Rx32),
28370(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28371"$Vd32 = vmem($Rx32++$Mu2)",
28372tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28373let Inst{12-5} = 0b00000000;
28374let Inst{31-21} = 0b00101011000;
28375let hasNewValue = 1;
28376let opNewValue = 0;
28377let addrMode = PostInc;
28378let accessSize = HVXVectorAccess;
28379let isCVLoad = 1;
28380let isCVI = 1;
28381let mayLoad = 1;
28382let isRestrictNoSlot1Store = 1;
28383let BaseOpcode = "V6_vL32b_ppu";
28384let isCVLoadable = 1;
28385let isPredicable = 1;
28386let DecoderNamespace = "EXT_mmvec";
28387let Constraints = "$Rx32 = $Rx32in";
28388}
28389def V6_vL32b_pred_ai : HInst<
28390(outs HvxVR:$Vd32),
28391(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28392"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
28393tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28394let Inst{7-5} = 0b010;
28395let Inst{31-21} = 0b00101000100;
28396let isPredicated = 1;
28397let hasNewValue = 1;
28398let opNewValue = 0;
28399let addrMode = BaseImmOffset;
28400let accessSize = HVXVectorAccess;
28401let isCVLoad = 1;
28402let isCVI = 1;
28403let mayLoad = 1;
28404let isRestrictNoSlot1Store = 1;
28405let BaseOpcode = "V6_vL32b_ai";
28406let DecoderNamespace = "EXT_mmvec";
28407}
28408def V6_vL32b_pred_pi : HInst<
28409(outs HvxVR:$Vd32, IntRegs:$Rx32),
28410(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28411"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
28412tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28413let Inst{7-5} = 0b010;
28414let Inst{13-13} = 0b0;
28415let Inst{31-21} = 0b00101001100;
28416let isPredicated = 1;
28417let hasNewValue = 1;
28418let opNewValue = 0;
28419let addrMode = PostInc;
28420let accessSize = HVXVectorAccess;
28421let isCVLoad = 1;
28422let isCVI = 1;
28423let mayLoad = 1;
28424let isRestrictNoSlot1Store = 1;
28425let BaseOpcode = "V6_vL32b_pi";
28426let DecoderNamespace = "EXT_mmvec";
28427let Constraints = "$Rx32 = $Rx32in";
28428}
28429def V6_vL32b_pred_ppu : HInst<
28430(outs HvxVR:$Vd32, IntRegs:$Rx32),
28431(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28432"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
28433tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28434let Inst{10-5} = 0b000010;
28435let Inst{31-21} = 0b00101011100;
28436let isPredicated = 1;
28437let hasNewValue = 1;
28438let opNewValue = 0;
28439let addrMode = PostInc;
28440let accessSize = HVXVectorAccess;
28441let isCVLoad = 1;
28442let isCVI = 1;
28443let mayLoad = 1;
28444let isRestrictNoSlot1Store = 1;
28445let BaseOpcode = "V6_vL32b_ppu";
28446let DecoderNamespace = "EXT_mmvec";
28447let Constraints = "$Rx32 = $Rx32in";
28448}
28449def V6_vL32b_tmp_ai : HInst<
28450(outs HvxVR:$Vd32),
28451(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28452"$Vd32.tmp = vmem($Rt32+#$Ii)",
28453tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28454let Inst{7-5} = 0b010;
28455let Inst{12-11} = 0b00;
28456let Inst{31-21} = 0b00101000000;
28457let hasNewValue = 1;
28458let opNewValue = 0;
28459let addrMode = BaseImmOffset;
28460let accessSize = HVXVectorAccess;
28461let isCVLoad = 1;
28462let isCVI = 1;
28463let hasHvxTmp = 1;
28464let mayLoad = 1;
28465let isRestrictNoSlot1Store = 1;
28466let BaseOpcode = "V6_vL32b_tmp_ai";
28467let CextOpcode = "V6_vL32b_tmp";
28468let isPredicable = 1;
28469let DecoderNamespace = "EXT_mmvec";
28470}
28471def V6_vL32b_tmp_npred_ai : HInst<
28472(outs HvxVR:$Vd32),
28473(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28474"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28475tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28476let Inst{7-5} = 0b111;
28477let Inst{31-21} = 0b00101000100;
28478let isPredicated = 1;
28479let isPredicatedFalse = 1;
28480let hasNewValue = 1;
28481let opNewValue = 0;
28482let addrMode = BaseImmOffset;
28483let accessSize = HVXVectorAccess;
28484let isCVLoad = 1;
28485let isCVI = 1;
28486let hasHvxTmp = 1;
28487let mayLoad = 1;
28488let isRestrictNoSlot1Store = 1;
28489let BaseOpcode = "V6_vL32b_tmp_ai";
28490let DecoderNamespace = "EXT_mmvec";
28491}
28492def V6_vL32b_tmp_npred_pi : HInst<
28493(outs HvxVR:$Vd32, IntRegs:$Rx32),
28494(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28495"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28496tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28497let Inst{7-5} = 0b111;
28498let Inst{13-13} = 0b0;
28499let Inst{31-21} = 0b00101001100;
28500let isPredicated = 1;
28501let isPredicatedFalse = 1;
28502let hasNewValue = 1;
28503let opNewValue = 0;
28504let addrMode = PostInc;
28505let accessSize = HVXVectorAccess;
28506let isCVLoad = 1;
28507let isCVI = 1;
28508let hasHvxTmp = 1;
28509let mayLoad = 1;
28510let isRestrictNoSlot1Store = 1;
28511let BaseOpcode = "V6_vL32b_tmp_pi";
28512let DecoderNamespace = "EXT_mmvec";
28513let Constraints = "$Rx32 = $Rx32in";
28514}
28515def V6_vL32b_tmp_npred_ppu : HInst<
28516(outs HvxVR:$Vd32, IntRegs:$Rx32),
28517(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28518"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28519tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28520let Inst{10-5} = 0b000111;
28521let Inst{31-21} = 0b00101011100;
28522let isPredicated = 1;
28523let isPredicatedFalse = 1;
28524let hasNewValue = 1;
28525let opNewValue = 0;
28526let addrMode = PostInc;
28527let accessSize = HVXVectorAccess;
28528let isCVLoad = 1;
28529let isCVI = 1;
28530let hasHvxTmp = 1;
28531let mayLoad = 1;
28532let isRestrictNoSlot1Store = 1;
28533let BaseOpcode = "V6_vL32b_tmp_ppu";
28534let DecoderNamespace = "EXT_mmvec";
28535let Constraints = "$Rx32 = $Rx32in";
28536}
28537def V6_vL32b_tmp_pi : HInst<
28538(outs HvxVR:$Vd32, IntRegs:$Rx32),
28539(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28540"$Vd32.tmp = vmem($Rx32++#$Ii)",
28541tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28542let Inst{7-5} = 0b010;
28543let Inst{13-11} = 0b000;
28544let Inst{31-21} = 0b00101001000;
28545let hasNewValue = 1;
28546let opNewValue = 0;
28547let addrMode = PostInc;
28548let accessSize = HVXVectorAccess;
28549let isCVLoad = 1;
28550let isCVI = 1;
28551let hasHvxTmp = 1;
28552let mayLoad = 1;
28553let isRestrictNoSlot1Store = 1;
28554let BaseOpcode = "V6_vL32b_tmp_pi";
28555let CextOpcode = "V6_vL32b_tmp";
28556let isPredicable = 1;
28557let DecoderNamespace = "EXT_mmvec";
28558let Constraints = "$Rx32 = $Rx32in";
28559}
28560def V6_vL32b_tmp_ppu : HInst<
28561(outs HvxVR:$Vd32, IntRegs:$Rx32),
28562(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28563"$Vd32.tmp = vmem($Rx32++$Mu2)",
28564tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28565let Inst{12-5} = 0b00000010;
28566let Inst{31-21} = 0b00101011000;
28567let hasNewValue = 1;
28568let opNewValue = 0;
28569let addrMode = PostInc;
28570let accessSize = HVXVectorAccess;
28571let isCVLoad = 1;
28572let isCVI = 1;
28573let hasHvxTmp = 1;
28574let mayLoad = 1;
28575let isRestrictNoSlot1Store = 1;
28576let BaseOpcode = "V6_vL32b_tmp_ppu";
28577let isPredicable = 1;
28578let DecoderNamespace = "EXT_mmvec";
28579let Constraints = "$Rx32 = $Rx32in";
28580}
28581def V6_vL32b_tmp_pred_ai : HInst<
28582(outs HvxVR:$Vd32),
28583(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28584"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28585tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28586let Inst{7-5} = 0b110;
28587let Inst{31-21} = 0b00101000100;
28588let isPredicated = 1;
28589let hasNewValue = 1;
28590let opNewValue = 0;
28591let addrMode = BaseImmOffset;
28592let accessSize = HVXVectorAccess;
28593let isCVLoad = 1;
28594let isCVI = 1;
28595let hasHvxTmp = 1;
28596let mayLoad = 1;
28597let isRestrictNoSlot1Store = 1;
28598let BaseOpcode = "V6_vL32b_tmp_ai";
28599let DecoderNamespace = "EXT_mmvec";
28600}
28601def V6_vL32b_tmp_pred_pi : HInst<
28602(outs HvxVR:$Vd32, IntRegs:$Rx32),
28603(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28604"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28605tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28606let Inst{7-5} = 0b110;
28607let Inst{13-13} = 0b0;
28608let Inst{31-21} = 0b00101001100;
28609let isPredicated = 1;
28610let hasNewValue = 1;
28611let opNewValue = 0;
28612let addrMode = PostInc;
28613let accessSize = HVXVectorAccess;
28614let isCVLoad = 1;
28615let isCVI = 1;
28616let hasHvxTmp = 1;
28617let mayLoad = 1;
28618let isRestrictNoSlot1Store = 1;
28619let BaseOpcode = "V6_vL32b_tmp_pi";
28620let DecoderNamespace = "EXT_mmvec";
28621let Constraints = "$Rx32 = $Rx32in";
28622}
28623def V6_vL32b_tmp_pred_ppu : HInst<
28624(outs HvxVR:$Vd32, IntRegs:$Rx32),
28625(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28626"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28627tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28628let Inst{10-5} = 0b000110;
28629let Inst{31-21} = 0b00101011100;
28630let isPredicated = 1;
28631let hasNewValue = 1;
28632let opNewValue = 0;
28633let addrMode = PostInc;
28634let accessSize = HVXVectorAccess;
28635let isCVLoad = 1;
28636let isCVI = 1;
28637let hasHvxTmp = 1;
28638let mayLoad = 1;
28639let isRestrictNoSlot1Store = 1;
28640let BaseOpcode = "V6_vL32b_tmp_ppu";
28641let DecoderNamespace = "EXT_mmvec";
28642let Constraints = "$Rx32 = $Rx32in";
28643}
28644def V6_vS32Ub_ai : HInst<
28645(outs),
28646(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28647"vmemu($Rt32+#$Ii) = $Vs32",
28648tc_f21e8abb, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28649let Inst{7-5} = 0b111;
28650let Inst{12-11} = 0b00;
28651let Inst{31-21} = 0b00101000001;
28652let addrMode = BaseImmOffset;
28653let accessSize = HVXVectorAccess;
28654let isCVI = 1;
28655let mayStore = 1;
28656let BaseOpcode = "V6_vS32Ub_ai";
28657let CextOpcode = "V6_vS32Ub";
28658let isPredicable = 1;
28659let DecoderNamespace = "EXT_mmvec";
28660}
28661def V6_vS32Ub_npred_ai : HInst<
28662(outs),
28663(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28664"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28665tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28666let Inst{7-5} = 0b111;
28667let Inst{31-21} = 0b00101000101;
28668let isPredicated = 1;
28669let isPredicatedFalse = 1;
28670let addrMode = BaseImmOffset;
28671let accessSize = HVXVectorAccess;
28672let isCVI = 1;
28673let mayStore = 1;
28674let BaseOpcode = "V6_vS32Ub_ai";
28675let DecoderNamespace = "EXT_mmvec";
28676}
28677def V6_vS32Ub_npred_pi : HInst<
28678(outs IntRegs:$Rx32),
28679(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28680"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28681tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28682let Inst{7-5} = 0b111;
28683let Inst{13-13} = 0b0;
28684let Inst{31-21} = 0b00101001101;
28685let isPredicated = 1;
28686let isPredicatedFalse = 1;
28687let addrMode = PostInc;
28688let accessSize = HVXVectorAccess;
28689let isCVI = 1;
28690let mayStore = 1;
28691let BaseOpcode = "V6_vS32Ub_pi";
28692let DecoderNamespace = "EXT_mmvec";
28693let Constraints = "$Rx32 = $Rx32in";
28694}
28695def V6_vS32Ub_npred_ppu : HInst<
28696(outs IntRegs:$Rx32),
28697(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28698"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28699tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28700let Inst{10-5} = 0b000111;
28701let Inst{31-21} = 0b00101011101;
28702let isPredicated = 1;
28703let isPredicatedFalse = 1;
28704let addrMode = PostInc;
28705let accessSize = HVXVectorAccess;
28706let isCVI = 1;
28707let mayStore = 1;
28708let BaseOpcode = "V6_vS32Ub_ppu";
28709let DecoderNamespace = "EXT_mmvec";
28710let Constraints = "$Rx32 = $Rx32in";
28711}
28712def V6_vS32Ub_pi : HInst<
28713(outs IntRegs:$Rx32),
28714(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28715"vmemu($Rx32++#$Ii) = $Vs32",
28716tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28717let Inst{7-5} = 0b111;
28718let Inst{13-11} = 0b000;
28719let Inst{31-21} = 0b00101001001;
28720let addrMode = PostInc;
28721let accessSize = HVXVectorAccess;
28722let isCVI = 1;
28723let mayStore = 1;
28724let BaseOpcode = "V6_vS32Ub_pi";
28725let CextOpcode = "V6_vS32Ub";
28726let isPredicable = 1;
28727let DecoderNamespace = "EXT_mmvec";
28728let Constraints = "$Rx32 = $Rx32in";
28729}
28730def V6_vS32Ub_ppu : HInst<
28731(outs IntRegs:$Rx32),
28732(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28733"vmemu($Rx32++$Mu2) = $Vs32",
28734tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28735let Inst{12-5} = 0b00000111;
28736let Inst{31-21} = 0b00101011001;
28737let addrMode = PostInc;
28738let accessSize = HVXVectorAccess;
28739let isCVI = 1;
28740let mayStore = 1;
28741let BaseOpcode = "V6_vS32Ub_ppu";
28742let isPredicable = 1;
28743let DecoderNamespace = "EXT_mmvec";
28744let Constraints = "$Rx32 = $Rx32in";
28745}
28746def V6_vS32Ub_pred_ai : HInst<
28747(outs),
28748(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28749"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28750tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28751let Inst{7-5} = 0b110;
28752let Inst{31-21} = 0b00101000101;
28753let isPredicated = 1;
28754let addrMode = BaseImmOffset;
28755let accessSize = HVXVectorAccess;
28756let isCVI = 1;
28757let mayStore = 1;
28758let BaseOpcode = "V6_vS32Ub_ai";
28759let DecoderNamespace = "EXT_mmvec";
28760}
28761def V6_vS32Ub_pred_pi : HInst<
28762(outs IntRegs:$Rx32),
28763(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28764"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28765tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28766let Inst{7-5} = 0b110;
28767let Inst{13-13} = 0b0;
28768let Inst{31-21} = 0b00101001101;
28769let isPredicated = 1;
28770let addrMode = PostInc;
28771let accessSize = HVXVectorAccess;
28772let isCVI = 1;
28773let mayStore = 1;
28774let BaseOpcode = "V6_vS32Ub_pi";
28775let DecoderNamespace = "EXT_mmvec";
28776let Constraints = "$Rx32 = $Rx32in";
28777}
28778def V6_vS32Ub_pred_ppu : HInst<
28779(outs IntRegs:$Rx32),
28780(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28781"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28782tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28783let Inst{10-5} = 0b000110;
28784let Inst{31-21} = 0b00101011101;
28785let isPredicated = 1;
28786let addrMode = PostInc;
28787let accessSize = HVXVectorAccess;
28788let isCVI = 1;
28789let mayStore = 1;
28790let BaseOpcode = "V6_vS32Ub_ppu";
28791let DecoderNamespace = "EXT_mmvec";
28792let Constraints = "$Rx32 = $Rx32in";
28793}
28794def V6_vS32b_ai : HInst<
28795(outs),
28796(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28797"vmem($Rt32+#$Ii) = $Vs32",
28798tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28799let Inst{7-5} = 0b000;
28800let Inst{12-11} = 0b00;
28801let Inst{31-21} = 0b00101000001;
28802let addrMode = BaseImmOffset;
28803let accessSize = HVXVectorAccess;
28804let isCVI = 1;
28805let mayStore = 1;
28806let BaseOpcode = "V6_vS32b_ai";
28807let CextOpcode = "V6_vS32b";
28808let isNVStorable = 1;
28809let isPredicable = 1;
28810let DecoderNamespace = "EXT_mmvec";
28811}
28812def V6_vS32b_new_ai : HInst<
28813(outs),
28814(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28815"vmem($Rt32+#$Ii) = $Os8.new",
28816tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28817let Inst{7-3} = 0b00100;
28818let Inst{12-11} = 0b00;
28819let Inst{31-21} = 0b00101000001;
28820let addrMode = BaseImmOffset;
28821let accessSize = HVXVectorAccess;
28822let isNVStore = 1;
28823let isCVI = 1;
28824let CVINew = 1;
28825let isNewValue = 1;
28826let mayStore = 1;
28827let BaseOpcode = "V6_vS32b_ai";
28828let CextOpcode = "V6_vS32b_new";
28829let isPredicable = 1;
28830let DecoderNamespace = "EXT_mmvec";
28831let opNewValue = 2;
28832}
28833def V6_vS32b_new_npred_ai : HInst<
28834(outs),
28835(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28836"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28837tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28838let Inst{7-3} = 0b01101;
28839let Inst{31-21} = 0b00101000101;
28840let isPredicated = 1;
28841let isPredicatedFalse = 1;
28842let addrMode = BaseImmOffset;
28843let accessSize = HVXVectorAccess;
28844let isNVStore = 1;
28845let isCVI = 1;
28846let CVINew = 1;
28847let isNewValue = 1;
28848let mayStore = 1;
28849let BaseOpcode = "V6_vS32b_ai";
28850let DecoderNamespace = "EXT_mmvec";
28851let opNewValue = 3;
28852}
28853def V6_vS32b_new_npred_pi : HInst<
28854(outs IntRegs:$Rx32),
28855(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28856"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28857tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28858let Inst{7-3} = 0b01101;
28859let Inst{13-13} = 0b0;
28860let Inst{31-21} = 0b00101001101;
28861let isPredicated = 1;
28862let isPredicatedFalse = 1;
28863let addrMode = PostInc;
28864let accessSize = HVXVectorAccess;
28865let isNVStore = 1;
28866let isCVI = 1;
28867let CVINew = 1;
28868let isNewValue = 1;
28869let mayStore = 1;
28870let BaseOpcode = "V6_vS32b_pi";
28871let DecoderNamespace = "EXT_mmvec";
28872let opNewValue = 4;
28873let Constraints = "$Rx32 = $Rx32in";
28874}
28875def V6_vS32b_new_npred_ppu : HInst<
28876(outs IntRegs:$Rx32),
28877(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28878"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28879tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28880let Inst{10-3} = 0b00001101;
28881let Inst{31-21} = 0b00101011101;
28882let isPredicated = 1;
28883let isPredicatedFalse = 1;
28884let addrMode = PostInc;
28885let accessSize = HVXVectorAccess;
28886let isNVStore = 1;
28887let isCVI = 1;
28888let CVINew = 1;
28889let isNewValue = 1;
28890let mayStore = 1;
28891let BaseOpcode = "V6_vS32b_ppu";
28892let DecoderNamespace = "EXT_mmvec";
28893let opNewValue = 4;
28894let Constraints = "$Rx32 = $Rx32in";
28895}
28896def V6_vS32b_new_pi : HInst<
28897(outs IntRegs:$Rx32),
28898(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28899"vmem($Rx32++#$Ii) = $Os8.new",
28900tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28901let Inst{7-3} = 0b00100;
28902let Inst{13-11} = 0b000;
28903let Inst{31-21} = 0b00101001001;
28904let addrMode = PostInc;
28905let accessSize = HVXVectorAccess;
28906let isNVStore = 1;
28907let isCVI = 1;
28908let CVINew = 1;
28909let isNewValue = 1;
28910let mayStore = 1;
28911let BaseOpcode = "V6_vS32b_pi";
28912let CextOpcode = "V6_vS32b_new";
28913let isPredicable = 1;
28914let DecoderNamespace = "EXT_mmvec";
28915let opNewValue = 3;
28916let Constraints = "$Rx32 = $Rx32in";
28917}
28918def V6_vS32b_new_ppu : HInst<
28919(outs IntRegs:$Rx32),
28920(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28921"vmem($Rx32++$Mu2) = $Os8.new",
28922tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
28923let Inst{12-3} = 0b0000000100;
28924let Inst{31-21} = 0b00101011001;
28925let addrMode = PostInc;
28926let accessSize = HVXVectorAccess;
28927let isNVStore = 1;
28928let isCVI = 1;
28929let CVINew = 1;
28930let isNewValue = 1;
28931let mayStore = 1;
28932let BaseOpcode = "V6_vS32b_ppu";
28933let isPredicable = 1;
28934let DecoderNamespace = "EXT_mmvec";
28935let opNewValue = 3;
28936let Constraints = "$Rx32 = $Rx32in";
28937}
28938def V6_vS32b_new_pred_ai : HInst<
28939(outs),
28940(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28941"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28942tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28943let Inst{7-3} = 0b01000;
28944let Inst{31-21} = 0b00101000101;
28945let isPredicated = 1;
28946let addrMode = BaseImmOffset;
28947let accessSize = HVXVectorAccess;
28948let isNVStore = 1;
28949let isCVI = 1;
28950let CVINew = 1;
28951let isNewValue = 1;
28952let mayStore = 1;
28953let BaseOpcode = "V6_vS32b_ai";
28954let DecoderNamespace = "EXT_mmvec";
28955let opNewValue = 3;
28956}
28957def V6_vS32b_new_pred_pi : HInst<
28958(outs IntRegs:$Rx32),
28959(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28960"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28961tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28962let Inst{7-3} = 0b01000;
28963let Inst{13-13} = 0b0;
28964let Inst{31-21} = 0b00101001101;
28965let isPredicated = 1;
28966let addrMode = PostInc;
28967let accessSize = HVXVectorAccess;
28968let isNVStore = 1;
28969let isCVI = 1;
28970let CVINew = 1;
28971let isNewValue = 1;
28972let mayStore = 1;
28973let BaseOpcode = "V6_vS32b_pi";
28974let DecoderNamespace = "EXT_mmvec";
28975let opNewValue = 4;
28976let Constraints = "$Rx32 = $Rx32in";
28977}
28978def V6_vS32b_new_pred_ppu : HInst<
28979(outs IntRegs:$Rx32),
28980(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28981"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28982tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28983let Inst{10-3} = 0b00001000;
28984let Inst{31-21} = 0b00101011101;
28985let isPredicated = 1;
28986let addrMode = PostInc;
28987let accessSize = HVXVectorAccess;
28988let isNVStore = 1;
28989let isCVI = 1;
28990let CVINew = 1;
28991let isNewValue = 1;
28992let mayStore = 1;
28993let BaseOpcode = "V6_vS32b_ppu";
28994let DecoderNamespace = "EXT_mmvec";
28995let opNewValue = 4;
28996let Constraints = "$Rx32 = $Rx32in";
28997}
28998def V6_vS32b_npred_ai : HInst<
28999(outs),
29000(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29001"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
29002tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29003let Inst{7-5} = 0b001;
29004let Inst{31-21} = 0b00101000101;
29005let isPredicated = 1;
29006let isPredicatedFalse = 1;
29007let addrMode = BaseImmOffset;
29008let accessSize = HVXVectorAccess;
29009let isCVI = 1;
29010let mayStore = 1;
29011let BaseOpcode = "V6_vS32b_ai";
29012let isNVStorable = 1;
29013let DecoderNamespace = "EXT_mmvec";
29014}
29015def V6_vS32b_npred_pi : HInst<
29016(outs IntRegs:$Rx32),
29017(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29018"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
29019tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29020let Inst{7-5} = 0b001;
29021let Inst{13-13} = 0b0;
29022let Inst{31-21} = 0b00101001101;
29023let isPredicated = 1;
29024let isPredicatedFalse = 1;
29025let addrMode = PostInc;
29026let accessSize = HVXVectorAccess;
29027let isCVI = 1;
29028let mayStore = 1;
29029let BaseOpcode = "V6_vS32b_pi";
29030let isNVStorable = 1;
29031let DecoderNamespace = "EXT_mmvec";
29032let Constraints = "$Rx32 = $Rx32in";
29033}
29034def V6_vS32b_npred_ppu : HInst<
29035(outs IntRegs:$Rx32),
29036(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29037"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
29038tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29039let Inst{10-5} = 0b000001;
29040let Inst{31-21} = 0b00101011101;
29041let isPredicated = 1;
29042let isPredicatedFalse = 1;
29043let addrMode = PostInc;
29044let accessSize = HVXVectorAccess;
29045let isCVI = 1;
29046let mayStore = 1;
29047let BaseOpcode = "V6_vS32b_ppu";
29048let isNVStorable = 1;
29049let DecoderNamespace = "EXT_mmvec";
29050let Constraints = "$Rx32 = $Rx32in";
29051}
29052def V6_vS32b_nqpred_ai : HInst<
29053(outs),
29054(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29055"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
29056tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29057let Inst{7-5} = 0b001;
29058let Inst{31-21} = 0b00101000100;
29059let addrMode = BaseImmOffset;
29060let accessSize = HVXVectorAccess;
29061let isCVI = 1;
29062let mayStore = 1;
29063let DecoderNamespace = "EXT_mmvec";
29064}
29065def V6_vS32b_nqpred_pi : HInst<
29066(outs IntRegs:$Rx32),
29067(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29068"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
29069tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29070let Inst{7-5} = 0b001;
29071let Inst{13-13} = 0b0;
29072let Inst{31-21} = 0b00101001100;
29073let addrMode = PostInc;
29074let accessSize = HVXVectorAccess;
29075let isCVI = 1;
29076let mayStore = 1;
29077let DecoderNamespace = "EXT_mmvec";
29078let Constraints = "$Rx32 = $Rx32in";
29079}
29080def V6_vS32b_nqpred_ppu : HInst<
29081(outs IntRegs:$Rx32),
29082(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29083"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
29084tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29085let Inst{10-5} = 0b000001;
29086let Inst{31-21} = 0b00101011100;
29087let addrMode = PostInc;
29088let accessSize = HVXVectorAccess;
29089let isCVI = 1;
29090let mayStore = 1;
29091let DecoderNamespace = "EXT_mmvec";
29092let Constraints = "$Rx32 = $Rx32in";
29093}
29094def V6_vS32b_nt_ai : HInst<
29095(outs),
29096(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29097"vmem($Rt32+#$Ii):nt = $Vs32",
29098tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29099let Inst{7-5} = 0b000;
29100let Inst{12-11} = 0b00;
29101let Inst{31-21} = 0b00101000011;
29102let addrMode = BaseImmOffset;
29103let accessSize = HVXVectorAccess;
29104let isCVI = 1;
29105let isNonTemporal = 1;
29106let mayStore = 1;
29107let BaseOpcode = "V6_vS32b_ai";
29108let CextOpcode = "V6_vS32b_nt";
29109let isNVStorable = 1;
29110let isPredicable = 1;
29111let DecoderNamespace = "EXT_mmvec";
29112}
29113def V6_vS32b_nt_new_ai : HInst<
29114(outs),
29115(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29116"vmem($Rt32+#$Ii):nt = $Os8.new",
29117tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29118let Inst{7-3} = 0b00100;
29119let Inst{12-11} = 0b00;
29120let Inst{31-21} = 0b00101000011;
29121let addrMode = BaseImmOffset;
29122let accessSize = HVXVectorAccess;
29123let isNVStore = 1;
29124let isCVI = 1;
29125let CVINew = 1;
29126let isNewValue = 1;
29127let isNonTemporal = 1;
29128let mayStore = 1;
29129let BaseOpcode = "V6_vS32b_ai";
29130let CextOpcode = "V6_vS32b_nt_new";
29131let isPredicable = 1;
29132let DecoderNamespace = "EXT_mmvec";
29133let opNewValue = 2;
29134}
29135def V6_vS32b_nt_new_npred_ai : HInst<
29136(outs),
29137(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29138"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29139tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29140let Inst{7-3} = 0b01111;
29141let Inst{31-21} = 0b00101000111;
29142let isPredicated = 1;
29143let isPredicatedFalse = 1;
29144let addrMode = BaseImmOffset;
29145let accessSize = HVXVectorAccess;
29146let isNVStore = 1;
29147let isCVI = 1;
29148let CVINew = 1;
29149let isNewValue = 1;
29150let isNonTemporal = 1;
29151let mayStore = 1;
29152let BaseOpcode = "V6_vS32b_ai";
29153let DecoderNamespace = "EXT_mmvec";
29154let opNewValue = 3;
29155}
29156def V6_vS32b_nt_new_npred_pi : HInst<
29157(outs IntRegs:$Rx32),
29158(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29159"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29160tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29161let Inst{7-3} = 0b01111;
29162let Inst{13-13} = 0b0;
29163let Inst{31-21} = 0b00101001111;
29164let isPredicated = 1;
29165let isPredicatedFalse = 1;
29166let addrMode = PostInc;
29167let accessSize = HVXVectorAccess;
29168let isNVStore = 1;
29169let isCVI = 1;
29170let CVINew = 1;
29171let isNewValue = 1;
29172let isNonTemporal = 1;
29173let mayStore = 1;
29174let BaseOpcode = "V6_vS32b_pi";
29175let DecoderNamespace = "EXT_mmvec";
29176let opNewValue = 4;
29177let Constraints = "$Rx32 = $Rx32in";
29178}
29179def V6_vS32b_nt_new_npred_ppu : HInst<
29180(outs IntRegs:$Rx32),
29181(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29182"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29183tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29184let Inst{10-3} = 0b00001111;
29185let Inst{31-21} = 0b00101011111;
29186let isPredicated = 1;
29187let isPredicatedFalse = 1;
29188let addrMode = PostInc;
29189let accessSize = HVXVectorAccess;
29190let isNVStore = 1;
29191let isCVI = 1;
29192let CVINew = 1;
29193let isNewValue = 1;
29194let isNonTemporal = 1;
29195let mayStore = 1;
29196let BaseOpcode = "V6_vS32b_ppu";
29197let DecoderNamespace = "EXT_mmvec";
29198let opNewValue = 4;
29199let Constraints = "$Rx32 = $Rx32in";
29200}
29201def V6_vS32b_nt_new_pi : HInst<
29202(outs IntRegs:$Rx32),
29203(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29204"vmem($Rx32++#$Ii):nt = $Os8.new",
29205tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29206let Inst{7-3} = 0b00100;
29207let Inst{13-11} = 0b000;
29208let Inst{31-21} = 0b00101001011;
29209let addrMode = PostInc;
29210let accessSize = HVXVectorAccess;
29211let isNVStore = 1;
29212let isCVI = 1;
29213let CVINew = 1;
29214let isNewValue = 1;
29215let isNonTemporal = 1;
29216let mayStore = 1;
29217let BaseOpcode = "V6_vS32b_pi";
29218let CextOpcode = "V6_vS32b_nt_new";
29219let isPredicable = 1;
29220let DecoderNamespace = "EXT_mmvec";
29221let opNewValue = 3;
29222let Constraints = "$Rx32 = $Rx32in";
29223}
29224def V6_vS32b_nt_new_ppu : HInst<
29225(outs IntRegs:$Rx32),
29226(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29227"vmem($Rx32++$Mu2):nt = $Os8.new",
29228tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
29229let Inst{12-3} = 0b0000000100;
29230let Inst{31-21} = 0b00101011011;
29231let addrMode = PostInc;
29232let accessSize = HVXVectorAccess;
29233let isNVStore = 1;
29234let isCVI = 1;
29235let CVINew = 1;
29236let isNewValue = 1;
29237let isNonTemporal = 1;
29238let mayStore = 1;
29239let BaseOpcode = "V6_vS32b_ppu";
29240let isPredicable = 1;
29241let DecoderNamespace = "EXT_mmvec";
29242let opNewValue = 3;
29243let Constraints = "$Rx32 = $Rx32in";
29244}
29245def V6_vS32b_nt_new_pred_ai : HInst<
29246(outs),
29247(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29248"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29249tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29250let Inst{7-3} = 0b01010;
29251let Inst{31-21} = 0b00101000111;
29252let isPredicated = 1;
29253let addrMode = BaseImmOffset;
29254let accessSize = HVXVectorAccess;
29255let isNVStore = 1;
29256let isCVI = 1;
29257let CVINew = 1;
29258let isNewValue = 1;
29259let isNonTemporal = 1;
29260let mayStore = 1;
29261let BaseOpcode = "V6_vS32b_ai";
29262let DecoderNamespace = "EXT_mmvec";
29263let opNewValue = 3;
29264}
29265def V6_vS32b_nt_new_pred_pi : HInst<
29266(outs IntRegs:$Rx32),
29267(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29268"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29269tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29270let Inst{7-3} = 0b01010;
29271let Inst{13-13} = 0b0;
29272let Inst{31-21} = 0b00101001111;
29273let isPredicated = 1;
29274let addrMode = PostInc;
29275let accessSize = HVXVectorAccess;
29276let isNVStore = 1;
29277let isCVI = 1;
29278let CVINew = 1;
29279let isNewValue = 1;
29280let isNonTemporal = 1;
29281let mayStore = 1;
29282let BaseOpcode = "V6_vS32b_pi";
29283let DecoderNamespace = "EXT_mmvec";
29284let opNewValue = 4;
29285let Constraints = "$Rx32 = $Rx32in";
29286}
29287def V6_vS32b_nt_new_pred_ppu : HInst<
29288(outs IntRegs:$Rx32),
29289(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29290"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29291tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29292let Inst{10-3} = 0b00001010;
29293let Inst{31-21} = 0b00101011111;
29294let isPredicated = 1;
29295let addrMode = PostInc;
29296let accessSize = HVXVectorAccess;
29297let isNVStore = 1;
29298let isCVI = 1;
29299let CVINew = 1;
29300let isNewValue = 1;
29301let isNonTemporal = 1;
29302let mayStore = 1;
29303let BaseOpcode = "V6_vS32b_ppu";
29304let DecoderNamespace = "EXT_mmvec";
29305let opNewValue = 4;
29306let Constraints = "$Rx32 = $Rx32in";
29307}
29308def V6_vS32b_nt_npred_ai : HInst<
29309(outs),
29310(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29311"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29312tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29313let Inst{7-5} = 0b001;
29314let Inst{31-21} = 0b00101000111;
29315let isPredicated = 1;
29316let isPredicatedFalse = 1;
29317let addrMode = BaseImmOffset;
29318let accessSize = HVXVectorAccess;
29319let isCVI = 1;
29320let isNonTemporal = 1;
29321let mayStore = 1;
29322let BaseOpcode = "V6_vS32b_ai";
29323let isNVStorable = 1;
29324let DecoderNamespace = "EXT_mmvec";
29325}
29326def V6_vS32b_nt_npred_pi : HInst<
29327(outs IntRegs:$Rx32),
29328(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29329"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29330tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29331let Inst{7-5} = 0b001;
29332let Inst{13-13} = 0b0;
29333let Inst{31-21} = 0b00101001111;
29334let isPredicated = 1;
29335let isPredicatedFalse = 1;
29336let addrMode = PostInc;
29337let accessSize = HVXVectorAccess;
29338let isCVI = 1;
29339let isNonTemporal = 1;
29340let mayStore = 1;
29341let BaseOpcode = "V6_vS32b_pi";
29342let isNVStorable = 1;
29343let DecoderNamespace = "EXT_mmvec";
29344let Constraints = "$Rx32 = $Rx32in";
29345}
29346def V6_vS32b_nt_npred_ppu : HInst<
29347(outs IntRegs:$Rx32),
29348(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29349"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29350tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29351let Inst{10-5} = 0b000001;
29352let Inst{31-21} = 0b00101011111;
29353let isPredicated = 1;
29354let isPredicatedFalse = 1;
29355let addrMode = PostInc;
29356let accessSize = HVXVectorAccess;
29357let isCVI = 1;
29358let isNonTemporal = 1;
29359let mayStore = 1;
29360let BaseOpcode = "V6_vS32b_ppu";
29361let isNVStorable = 1;
29362let DecoderNamespace = "EXT_mmvec";
29363let Constraints = "$Rx32 = $Rx32in";
29364}
29365def V6_vS32b_nt_nqpred_ai : HInst<
29366(outs),
29367(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29368"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29369tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29370let Inst{7-5} = 0b001;
29371let Inst{31-21} = 0b00101000110;
29372let addrMode = BaseImmOffset;
29373let accessSize = HVXVectorAccess;
29374let isCVI = 1;
29375let isNonTemporal = 1;
29376let mayStore = 1;
29377let DecoderNamespace = "EXT_mmvec";
29378}
29379def V6_vS32b_nt_nqpred_pi : HInst<
29380(outs IntRegs:$Rx32),
29381(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29382"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29383tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29384let Inst{7-5} = 0b001;
29385let Inst{13-13} = 0b0;
29386let Inst{31-21} = 0b00101001110;
29387let addrMode = PostInc;
29388let accessSize = HVXVectorAccess;
29389let isCVI = 1;
29390let isNonTemporal = 1;
29391let mayStore = 1;
29392let DecoderNamespace = "EXT_mmvec";
29393let Constraints = "$Rx32 = $Rx32in";
29394}
29395def V6_vS32b_nt_nqpred_ppu : HInst<
29396(outs IntRegs:$Rx32),
29397(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29398"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29399tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29400let Inst{10-5} = 0b000001;
29401let Inst{31-21} = 0b00101011110;
29402let addrMode = PostInc;
29403let accessSize = HVXVectorAccess;
29404let isCVI = 1;
29405let isNonTemporal = 1;
29406let mayStore = 1;
29407let DecoderNamespace = "EXT_mmvec";
29408let Constraints = "$Rx32 = $Rx32in";
29409}
29410def V6_vS32b_nt_pi : HInst<
29411(outs IntRegs:$Rx32),
29412(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29413"vmem($Rx32++#$Ii):nt = $Vs32",
29414tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29415let Inst{7-5} = 0b000;
29416let Inst{13-11} = 0b000;
29417let Inst{31-21} = 0b00101001011;
29418let addrMode = PostInc;
29419let accessSize = HVXVectorAccess;
29420let isCVI = 1;
29421let isNonTemporal = 1;
29422let mayStore = 1;
29423let BaseOpcode = "V6_vS32b_pi";
29424let CextOpcode = "V6_vS32b_nt";
29425let isNVStorable = 1;
29426let isPredicable = 1;
29427let DecoderNamespace = "EXT_mmvec";
29428let Constraints = "$Rx32 = $Rx32in";
29429}
29430def V6_vS32b_nt_ppu : HInst<
29431(outs IntRegs:$Rx32),
29432(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29433"vmem($Rx32++$Mu2):nt = $Vs32",
29434tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29435let Inst{12-5} = 0b00000000;
29436let Inst{31-21} = 0b00101011011;
29437let addrMode = PostInc;
29438let accessSize = HVXVectorAccess;
29439let isCVI = 1;
29440let isNonTemporal = 1;
29441let mayStore = 1;
29442let BaseOpcode = "V6_vS32b_ppu";
29443let isNVStorable = 1;
29444let isPredicable = 1;
29445let DecoderNamespace = "EXT_mmvec";
29446let Constraints = "$Rx32 = $Rx32in";
29447}
29448def V6_vS32b_nt_pred_ai : HInst<
29449(outs),
29450(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29451"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29452tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29453let Inst{7-5} = 0b000;
29454let Inst{31-21} = 0b00101000111;
29455let isPredicated = 1;
29456let addrMode = BaseImmOffset;
29457let accessSize = HVXVectorAccess;
29458let isCVI = 1;
29459let isNonTemporal = 1;
29460let mayStore = 1;
29461let BaseOpcode = "V6_vS32b_ai";
29462let isNVStorable = 1;
29463let DecoderNamespace = "EXT_mmvec";
29464}
29465def V6_vS32b_nt_pred_pi : HInst<
29466(outs IntRegs:$Rx32),
29467(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29468"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29469tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29470let Inst{7-5} = 0b000;
29471let Inst{13-13} = 0b0;
29472let Inst{31-21} = 0b00101001111;
29473let isPredicated = 1;
29474let addrMode = PostInc;
29475let accessSize = HVXVectorAccess;
29476let isCVI = 1;
29477let isNonTemporal = 1;
29478let mayStore = 1;
29479let BaseOpcode = "V6_vS32b_pi";
29480let isNVStorable = 1;
29481let DecoderNamespace = "EXT_mmvec";
29482let Constraints = "$Rx32 = $Rx32in";
29483}
29484def V6_vS32b_nt_pred_ppu : HInst<
29485(outs IntRegs:$Rx32),
29486(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29487"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29488tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29489let Inst{10-5} = 0b000000;
29490let Inst{31-21} = 0b00101011111;
29491let isPredicated = 1;
29492let addrMode = PostInc;
29493let accessSize = HVXVectorAccess;
29494let isCVI = 1;
29495let isNonTemporal = 1;
29496let mayStore = 1;
29497let BaseOpcode = "V6_vS32b_ppu";
29498let isNVStorable = 1;
29499let DecoderNamespace = "EXT_mmvec";
29500let Constraints = "$Rx32 = $Rx32in";
29501}
29502def V6_vS32b_nt_qpred_ai : HInst<
29503(outs),
29504(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29505"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29506tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29507let Inst{7-5} = 0b000;
29508let Inst{31-21} = 0b00101000110;
29509let addrMode = BaseImmOffset;
29510let accessSize = HVXVectorAccess;
29511let isCVI = 1;
29512let isNonTemporal = 1;
29513let mayStore = 1;
29514let DecoderNamespace = "EXT_mmvec";
29515}
29516def V6_vS32b_nt_qpred_pi : HInst<
29517(outs IntRegs:$Rx32),
29518(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29519"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29520tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29521let Inst{7-5} = 0b000;
29522let Inst{13-13} = 0b0;
29523let Inst{31-21} = 0b00101001110;
29524let addrMode = PostInc;
29525let accessSize = HVXVectorAccess;
29526let isCVI = 1;
29527let isNonTemporal = 1;
29528let mayStore = 1;
29529let DecoderNamespace = "EXT_mmvec";
29530let Constraints = "$Rx32 = $Rx32in";
29531}
29532def V6_vS32b_nt_qpred_ppu : HInst<
29533(outs IntRegs:$Rx32),
29534(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29535"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29536tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29537let Inst{10-5} = 0b000000;
29538let Inst{31-21} = 0b00101011110;
29539let addrMode = PostInc;
29540let accessSize = HVXVectorAccess;
29541let isCVI = 1;
29542let isNonTemporal = 1;
29543let mayStore = 1;
29544let DecoderNamespace = "EXT_mmvec";
29545let Constraints = "$Rx32 = $Rx32in";
29546}
29547def V6_vS32b_pi : HInst<
29548(outs IntRegs:$Rx32),
29549(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29550"vmem($Rx32++#$Ii) = $Vs32",
29551tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29552let Inst{7-5} = 0b000;
29553let Inst{13-11} = 0b000;
29554let Inst{31-21} = 0b00101001001;
29555let addrMode = PostInc;
29556let accessSize = HVXVectorAccess;
29557let isCVI = 1;
29558let mayStore = 1;
29559let BaseOpcode = "V6_vS32b_pi";
29560let CextOpcode = "V6_vS32b";
29561let isNVStorable = 1;
29562let isPredicable = 1;
29563let DecoderNamespace = "EXT_mmvec";
29564let Constraints = "$Rx32 = $Rx32in";
29565}
29566def V6_vS32b_ppu : HInst<
29567(outs IntRegs:$Rx32),
29568(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29569"vmem($Rx32++$Mu2) = $Vs32",
29570tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29571let Inst{12-5} = 0b00000000;
29572let Inst{31-21} = 0b00101011001;
29573let addrMode = PostInc;
29574let accessSize = HVXVectorAccess;
29575let isCVI = 1;
29576let mayStore = 1;
29577let BaseOpcode = "V6_vS32b_ppu";
29578let isNVStorable = 1;
29579let isPredicable = 1;
29580let DecoderNamespace = "EXT_mmvec";
29581let Constraints = "$Rx32 = $Rx32in";
29582}
29583def V6_vS32b_pred_ai : HInst<
29584(outs),
29585(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29586"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
29587tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29588let Inst{7-5} = 0b000;
29589let Inst{31-21} = 0b00101000101;
29590let isPredicated = 1;
29591let addrMode = BaseImmOffset;
29592let accessSize = HVXVectorAccess;
29593let isCVI = 1;
29594let mayStore = 1;
29595let BaseOpcode = "V6_vS32b_ai";
29596let isNVStorable = 1;
29597let DecoderNamespace = "EXT_mmvec";
29598}
29599def V6_vS32b_pred_pi : HInst<
29600(outs IntRegs:$Rx32),
29601(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29602"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
29603tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29604let Inst{7-5} = 0b000;
29605let Inst{13-13} = 0b0;
29606let Inst{31-21} = 0b00101001101;
29607let isPredicated = 1;
29608let addrMode = PostInc;
29609let accessSize = HVXVectorAccess;
29610let isCVI = 1;
29611let mayStore = 1;
29612let BaseOpcode = "V6_vS32b_pi";
29613let isNVStorable = 1;
29614let DecoderNamespace = "EXT_mmvec";
29615let Constraints = "$Rx32 = $Rx32in";
29616}
29617def V6_vS32b_pred_ppu : HInst<
29618(outs IntRegs:$Rx32),
29619(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29620"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
29621tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29622let Inst{10-5} = 0b000000;
29623let Inst{31-21} = 0b00101011101;
29624let isPredicated = 1;
29625let addrMode = PostInc;
29626let accessSize = HVXVectorAccess;
29627let isCVI = 1;
29628let mayStore = 1;
29629let BaseOpcode = "V6_vS32b_ppu";
29630let isNVStorable = 1;
29631let DecoderNamespace = "EXT_mmvec";
29632let Constraints = "$Rx32 = $Rx32in";
29633}
29634def V6_vS32b_qpred_ai : HInst<
29635(outs),
29636(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29637"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
29638tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29639let Inst{7-5} = 0b000;
29640let Inst{31-21} = 0b00101000100;
29641let addrMode = BaseImmOffset;
29642let accessSize = HVXVectorAccess;
29643let isCVI = 1;
29644let mayStore = 1;
29645let DecoderNamespace = "EXT_mmvec";
29646}
29647def V6_vS32b_qpred_pi : HInst<
29648(outs IntRegs:$Rx32),
29649(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29650"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
29651tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29652let Inst{7-5} = 0b000;
29653let Inst{13-13} = 0b0;
29654let Inst{31-21} = 0b00101001100;
29655let addrMode = PostInc;
29656let accessSize = HVXVectorAccess;
29657let isCVI = 1;
29658let mayStore = 1;
29659let DecoderNamespace = "EXT_mmvec";
29660let Constraints = "$Rx32 = $Rx32in";
29661}
29662def V6_vS32b_qpred_ppu : HInst<
29663(outs IntRegs:$Rx32),
29664(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29665"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
29666tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29667let Inst{10-5} = 0b000000;
29668let Inst{31-21} = 0b00101011100;
29669let addrMode = PostInc;
29670let accessSize = HVXVectorAccess;
29671let isCVI = 1;
29672let mayStore = 1;
29673let DecoderNamespace = "EXT_mmvec";
29674let Constraints = "$Rx32 = $Rx32in";
29675}
29676def V6_vS32b_srls_ai : HInst<
29677(outs),
29678(ins IntRegs:$Rt32, s4_0Imm:$Ii),
29679"vmem($Rt32+#$Ii):scatter_release",
29680tc_3ce09744, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
29681let Inst{7-0} = 0b00101000;
29682let Inst{12-11} = 0b00;
29683let Inst{31-21} = 0b00101000001;
29684let addrMode = BaseImmOffset;
29685let accessSize = HVXVectorAccess;
29686let isCVI = 1;
29687let CVINew = 1;
29688let mayStore = 1;
29689let DecoderNamespace = "EXT_mmvec";
29690}
29691def V6_vS32b_srls_pi : HInst<
29692(outs IntRegs:$Rx32),
29693(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
29694"vmem($Rx32++#$Ii):scatter_release",
29695tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
29696let Inst{7-0} = 0b00101000;
29697let Inst{13-11} = 0b000;
29698let Inst{31-21} = 0b00101001001;
29699let addrMode = PostInc;
29700let accessSize = HVXVectorAccess;
29701let isCVI = 1;
29702let CVINew = 1;
29703let mayStore = 1;
29704let DecoderNamespace = "EXT_mmvec";
29705let Constraints = "$Rx32 = $Rx32in";
29706}
29707def V6_vS32b_srls_ppu : HInst<
29708(outs IntRegs:$Rx32),
29709(ins IntRegs:$Rx32in, ModRegs:$Mu2),
29710"vmem($Rx32++$Mu2):scatter_release",
29711tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
29712let Inst{12-0} = 0b0000000101000;
29713let Inst{31-21} = 0b00101011001;
29714let addrMode = PostInc;
29715let accessSize = HVXVectorAccess;
29716let isCVI = 1;
29717let CVINew = 1;
29718let mayStore = 1;
29719let DecoderNamespace = "EXT_mmvec";
29720let Constraints = "$Rx32 = $Rx32in";
29721}
29722def V6_vabs_hf : HInst<
29723(outs HvxVR:$Vd32),
29724(ins HvxVR:$Vu32),
29725"$Vd32.hf = vabs($Vu32.hf)",
29726tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
29727let Inst{7-5} = 0b100;
29728let Inst{13-13} = 0b1;
29729let Inst{31-16} = 0b0001111000000110;
29730let hasNewValue = 1;
29731let opNewValue = 0;
29732let isCVI = 1;
29733let DecoderNamespace = "EXT_mmvec";
29734}
29735def V6_vabs_sf : HInst<
29736(outs HvxVR:$Vd32),
29737(ins HvxVR:$Vu32),
29738"$Vd32.sf = vabs($Vu32.sf)",
29739tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
29740let Inst{7-5} = 0b101;
29741let Inst{13-13} = 0b1;
29742let Inst{31-16} = 0b0001111000000110;
29743let hasNewValue = 1;
29744let opNewValue = 0;
29745let isCVI = 1;
29746let DecoderNamespace = "EXT_mmvec";
29747}
29748def V6_vabsb : HInst<
29749(outs HvxVR:$Vd32),
29750(ins HvxVR:$Vu32),
29751"$Vd32.b = vabs($Vu32.b)",
29752tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29753let Inst{7-5} = 0b100;
29754let Inst{13-13} = 0b0;
29755let Inst{31-16} = 0b0001111000000001;
29756let hasNewValue = 1;
29757let opNewValue = 0;
29758let isCVI = 1;
29759let DecoderNamespace = "EXT_mmvec";
29760}
29761def V6_vabsb_alt : HInst<
29762(outs HvxVR:$Vd32),
29763(ins HvxVR:$Vu32),
29764"$Vd32 = vabsb($Vu32)",
29765PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29766let hasNewValue = 1;
29767let opNewValue = 0;
29768let isCVI = 1;
29769let isPseudo = 1;
29770let isCodeGenOnly = 1;
29771let DecoderNamespace = "EXT_mmvec";
29772}
29773def V6_vabsb_sat : HInst<
29774(outs HvxVR:$Vd32),
29775(ins HvxVR:$Vu32),
29776"$Vd32.b = vabs($Vu32.b):sat",
29777tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29778let Inst{7-5} = 0b101;
29779let Inst{13-13} = 0b0;
29780let Inst{31-16} = 0b0001111000000001;
29781let hasNewValue = 1;
29782let opNewValue = 0;
29783let isCVI = 1;
29784let DecoderNamespace = "EXT_mmvec";
29785}
29786def V6_vabsb_sat_alt : HInst<
29787(outs HvxVR:$Vd32),
29788(ins HvxVR:$Vu32),
29789"$Vd32 = vabsb($Vu32):sat",
29790PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29791let hasNewValue = 1;
29792let opNewValue = 0;
29793let isCVI = 1;
29794let isPseudo = 1;
29795let isCodeGenOnly = 1;
29796let DecoderNamespace = "EXT_mmvec";
29797}
29798def V6_vabsdiffh : HInst<
29799(outs HvxVR:$Vd32),
29800(ins HvxVR:$Vu32, HvxVR:$Vv32),
29801"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
29802tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29803let Inst{7-5} = 0b001;
29804let Inst{13-13} = 0b0;
29805let Inst{31-21} = 0b00011100110;
29806let hasNewValue = 1;
29807let opNewValue = 0;
29808let isCVI = 1;
29809let DecoderNamespace = "EXT_mmvec";
29810}
29811def V6_vabsdiffh_alt : HInst<
29812(outs HvxVR:$Vd32),
29813(ins HvxVR:$Vu32, HvxVR:$Vv32),
29814"$Vd32 = vabsdiffh($Vu32,$Vv32)",
29815PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29816let hasNewValue = 1;
29817let opNewValue = 0;
29818let isCVI = 1;
29819let isPseudo = 1;
29820let isCodeGenOnly = 1;
29821let DecoderNamespace = "EXT_mmvec";
29822}
29823def V6_vabsdiffub : HInst<
29824(outs HvxVR:$Vd32),
29825(ins HvxVR:$Vu32, HvxVR:$Vv32),
29826"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
29827tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29828let Inst{7-5} = 0b000;
29829let Inst{13-13} = 0b0;
29830let Inst{31-21} = 0b00011100110;
29831let hasNewValue = 1;
29832let opNewValue = 0;
29833let isCVI = 1;
29834let DecoderNamespace = "EXT_mmvec";
29835}
29836def V6_vabsdiffub_alt : HInst<
29837(outs HvxVR:$Vd32),
29838(ins HvxVR:$Vu32, HvxVR:$Vv32),
29839"$Vd32 = vabsdiffub($Vu32,$Vv32)",
29840PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29841let hasNewValue = 1;
29842let opNewValue = 0;
29843let isCVI = 1;
29844let isPseudo = 1;
29845let isCodeGenOnly = 1;
29846let DecoderNamespace = "EXT_mmvec";
29847}
29848def V6_vabsdiffuh : HInst<
29849(outs HvxVR:$Vd32),
29850(ins HvxVR:$Vu32, HvxVR:$Vv32),
29851"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
29852tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29853let Inst{7-5} = 0b010;
29854let Inst{13-13} = 0b0;
29855let Inst{31-21} = 0b00011100110;
29856let hasNewValue = 1;
29857let opNewValue = 0;
29858let isCVI = 1;
29859let DecoderNamespace = "EXT_mmvec";
29860}
29861def V6_vabsdiffuh_alt : HInst<
29862(outs HvxVR:$Vd32),
29863(ins HvxVR:$Vu32, HvxVR:$Vv32),
29864"$Vd32 = vabsdiffuh($Vu32,$Vv32)",
29865PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29866let hasNewValue = 1;
29867let opNewValue = 0;
29868let isCVI = 1;
29869let isPseudo = 1;
29870let isCodeGenOnly = 1;
29871let DecoderNamespace = "EXT_mmvec";
29872}
29873def V6_vabsdiffw : HInst<
29874(outs HvxVR:$Vd32),
29875(ins HvxVR:$Vu32, HvxVR:$Vv32),
29876"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
29877tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29878let Inst{7-5} = 0b011;
29879let Inst{13-13} = 0b0;
29880let Inst{31-21} = 0b00011100110;
29881let hasNewValue = 1;
29882let opNewValue = 0;
29883let isCVI = 1;
29884let DecoderNamespace = "EXT_mmvec";
29885}
29886def V6_vabsdiffw_alt : HInst<
29887(outs HvxVR:$Vd32),
29888(ins HvxVR:$Vu32, HvxVR:$Vv32),
29889"$Vd32 = vabsdiffw($Vu32,$Vv32)",
29890PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29891let hasNewValue = 1;
29892let opNewValue = 0;
29893let isCVI = 1;
29894let isPseudo = 1;
29895let isCodeGenOnly = 1;
29896let DecoderNamespace = "EXT_mmvec";
29897}
29898def V6_vabsh : HInst<
29899(outs HvxVR:$Vd32),
29900(ins HvxVR:$Vu32),
29901"$Vd32.h = vabs($Vu32.h)",
29902tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29903let Inst{7-5} = 0b000;
29904let Inst{13-13} = 0b0;
29905let Inst{31-16} = 0b0001111000000000;
29906let hasNewValue = 1;
29907let opNewValue = 0;
29908let isCVI = 1;
29909let DecoderNamespace = "EXT_mmvec";
29910}
29911def V6_vabsh_alt : HInst<
29912(outs HvxVR:$Vd32),
29913(ins HvxVR:$Vu32),
29914"$Vd32 = vabsh($Vu32)",
29915PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29916let hasNewValue = 1;
29917let opNewValue = 0;
29918let isCVI = 1;
29919let isPseudo = 1;
29920let isCodeGenOnly = 1;
29921let DecoderNamespace = "EXT_mmvec";
29922}
29923def V6_vabsh_sat : HInst<
29924(outs HvxVR:$Vd32),
29925(ins HvxVR:$Vu32),
29926"$Vd32.h = vabs($Vu32.h):sat",
29927tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29928let Inst{7-5} = 0b001;
29929let Inst{13-13} = 0b0;
29930let Inst{31-16} = 0b0001111000000000;
29931let hasNewValue = 1;
29932let opNewValue = 0;
29933let isCVI = 1;
29934let DecoderNamespace = "EXT_mmvec";
29935}
29936def V6_vabsh_sat_alt : HInst<
29937(outs HvxVR:$Vd32),
29938(ins HvxVR:$Vu32),
29939"$Vd32 = vabsh($Vu32):sat",
29940PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29941let hasNewValue = 1;
29942let opNewValue = 0;
29943let isCVI = 1;
29944let isPseudo = 1;
29945let isCodeGenOnly = 1;
29946let DecoderNamespace = "EXT_mmvec";
29947}
29948def V6_vabsub_alt : HInst<
29949(outs HvxVR:$Vd32),
29950(ins HvxVR:$Vu32),
29951"$Vd32.ub = vabs($Vu32.b)",
29952tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29953let hasNewValue = 1;
29954let opNewValue = 0;
29955let isCVI = 1;
29956let isPseudo = 1;
29957let isCodeGenOnly = 1;
29958let DecoderNamespace = "EXT_mmvec";
29959}
29960def V6_vabsuh_alt : HInst<
29961(outs HvxVR:$Vd32),
29962(ins HvxVR:$Vu32),
29963"$Vd32.uh = vabs($Vu32.h)",
29964tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29965let hasNewValue = 1;
29966let opNewValue = 0;
29967let isCVI = 1;
29968let isPseudo = 1;
29969let isCodeGenOnly = 1;
29970let DecoderNamespace = "EXT_mmvec";
29971}
29972def V6_vabsuw_alt : HInst<
29973(outs HvxVR:$Vd32),
29974(ins HvxVR:$Vu32),
29975"$Vd32.uw = vabs($Vu32.w)",
29976tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29977let hasNewValue = 1;
29978let opNewValue = 0;
29979let isCVI = 1;
29980let isPseudo = 1;
29981let isCodeGenOnly = 1;
29982let DecoderNamespace = "EXT_mmvec";
29983}
29984def V6_vabsw : HInst<
29985(outs HvxVR:$Vd32),
29986(ins HvxVR:$Vu32),
29987"$Vd32.w = vabs($Vu32.w)",
29988tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29989let Inst{7-5} = 0b010;
29990let Inst{13-13} = 0b0;
29991let Inst{31-16} = 0b0001111000000000;
29992let hasNewValue = 1;
29993let opNewValue = 0;
29994let isCVI = 1;
29995let DecoderNamespace = "EXT_mmvec";
29996}
29997def V6_vabsw_alt : HInst<
29998(outs HvxVR:$Vd32),
29999(ins HvxVR:$Vu32),
30000"$Vd32 = vabsw($Vu32)",
30001PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30002let hasNewValue = 1;
30003let opNewValue = 0;
30004let isCVI = 1;
30005let isPseudo = 1;
30006let isCodeGenOnly = 1;
30007let DecoderNamespace = "EXT_mmvec";
30008}
30009def V6_vabsw_sat : HInst<
30010(outs HvxVR:$Vd32),
30011(ins HvxVR:$Vu32),
30012"$Vd32.w = vabs($Vu32.w):sat",
30013tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30014let Inst{7-5} = 0b011;
30015let Inst{13-13} = 0b0;
30016let Inst{31-16} = 0b0001111000000000;
30017let hasNewValue = 1;
30018let opNewValue = 0;
30019let isCVI = 1;
30020let DecoderNamespace = "EXT_mmvec";
30021}
30022def V6_vabsw_sat_alt : HInst<
30023(outs HvxVR:$Vd32),
30024(ins HvxVR:$Vu32),
30025"$Vd32 = vabsw($Vu32):sat",
30026PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30027let hasNewValue = 1;
30028let opNewValue = 0;
30029let isCVI = 1;
30030let isPseudo = 1;
30031let isCodeGenOnly = 1;
30032let DecoderNamespace = "EXT_mmvec";
30033}
30034def V6_vadd_hf : HInst<
30035(outs HvxVR:$Vd32),
30036(ins HvxVR:$Vu32, HvxVR:$Vv32),
30037"$Vd32.qf16 = vadd($Vu32.hf,$Vv32.hf)",
30038tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30039let Inst{7-5} = 0b011;
30040let Inst{13-13} = 0b1;
30041let Inst{31-21} = 0b00011111011;
30042let hasNewValue = 1;
30043let opNewValue = 0;
30044let isCVI = 1;
30045let DecoderNamespace = "EXT_mmvec";
30046}
30047def V6_vadd_hf_hf : HInst<
30048(outs HvxVR:$Vd32),
30049(ins HvxVR:$Vu32, HvxVR:$Vv32),
30050"$Vd32.hf = vadd($Vu32.hf,$Vv32.hf)",
30051tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30052let Inst{7-5} = 0b111;
30053let Inst{13-13} = 0b1;
30054let Inst{31-21} = 0b00011111101;
30055let hasNewValue = 1;
30056let opNewValue = 0;
30057let isCVI = 1;
30058let DecoderNamespace = "EXT_mmvec";
30059}
30060def V6_vadd_qf16 : HInst<
30061(outs HvxVR:$Vd32),
30062(ins HvxVR:$Vu32, HvxVR:$Vv32),
30063"$Vd32.qf16 = vadd($Vu32.qf16,$Vv32.qf16)",
30064tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30065let Inst{7-5} = 0b010;
30066let Inst{13-13} = 0b1;
30067let Inst{31-21} = 0b00011111011;
30068let hasNewValue = 1;
30069let opNewValue = 0;
30070let isCVI = 1;
30071let DecoderNamespace = "EXT_mmvec";
30072}
30073def V6_vadd_qf16_mix : HInst<
30074(outs HvxVR:$Vd32),
30075(ins HvxVR:$Vu32, HvxVR:$Vv32),
30076"$Vd32.qf16 = vadd($Vu32.qf16,$Vv32.hf)",
30077tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30078let Inst{7-5} = 0b100;
30079let Inst{13-13} = 0b1;
30080let Inst{31-21} = 0b00011111011;
30081let hasNewValue = 1;
30082let opNewValue = 0;
30083let isCVI = 1;
30084let DecoderNamespace = "EXT_mmvec";
30085}
30086def V6_vadd_qf32 : HInst<
30087(outs HvxVR:$Vd32),
30088(ins HvxVR:$Vu32, HvxVR:$Vv32),
30089"$Vd32.qf32 = vadd($Vu32.qf32,$Vv32.qf32)",
30090tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30091let Inst{7-5} = 0b000;
30092let Inst{13-13} = 0b1;
30093let Inst{31-21} = 0b00011111101;
30094let hasNewValue = 1;
30095let opNewValue = 0;
30096let isCVI = 1;
30097let DecoderNamespace = "EXT_mmvec";
30098}
30099def V6_vadd_qf32_mix : HInst<
30100(outs HvxVR:$Vd32),
30101(ins HvxVR:$Vu32, HvxVR:$Vv32),
30102"$Vd32.qf32 = vadd($Vu32.qf32,$Vv32.sf)",
30103tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30104let Inst{7-5} = 0b010;
30105let Inst{13-13} = 0b1;
30106let Inst{31-21} = 0b00011111101;
30107let hasNewValue = 1;
30108let opNewValue = 0;
30109let isCVI = 1;
30110let DecoderNamespace = "EXT_mmvec";
30111}
30112def V6_vadd_sf : HInst<
30113(outs HvxVR:$Vd32),
30114(ins HvxVR:$Vu32, HvxVR:$Vv32),
30115"$Vd32.qf32 = vadd($Vu32.sf,$Vv32.sf)",
30116tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30117let Inst{7-5} = 0b001;
30118let Inst{13-13} = 0b1;
30119let Inst{31-21} = 0b00011111101;
30120let hasNewValue = 1;
30121let opNewValue = 0;
30122let isCVI = 1;
30123let DecoderNamespace = "EXT_mmvec";
30124}
30125def V6_vadd_sf_hf : HInst<
30126(outs HvxWR:$Vdd32),
30127(ins HvxVR:$Vu32, HvxVR:$Vv32),
30128"$Vdd32.sf = vadd($Vu32.hf,$Vv32.hf)",
30129tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30130let Inst{7-5} = 0b100;
30131let Inst{13-13} = 0b1;
30132let Inst{31-21} = 0b00011111100;
30133let hasNewValue = 1;
30134let opNewValue = 0;
30135let isCVI = 1;
30136let DecoderNamespace = "EXT_mmvec";
30137}
30138def V6_vadd_sf_sf : HInst<
30139(outs HvxVR:$Vd32),
30140(ins HvxVR:$Vu32, HvxVR:$Vv32),
30141"$Vd32.sf = vadd($Vu32.sf,$Vv32.sf)",
30142tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30143let Inst{7-5} = 0b110;
30144let Inst{13-13} = 0b1;
30145let Inst{31-21} = 0b00011111100;
30146let hasNewValue = 1;
30147let opNewValue = 0;
30148let isCVI = 1;
30149let DecoderNamespace = "EXT_mmvec";
30150}
30151def V6_vaddb : HInst<
30152(outs HvxVR:$Vd32),
30153(ins HvxVR:$Vu32, HvxVR:$Vv32),
30154"$Vd32.b = vadd($Vu32.b,$Vv32.b)",
30155tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30156let Inst{7-5} = 0b110;
30157let Inst{13-13} = 0b0;
30158let Inst{31-21} = 0b00011111101;
30159let hasNewValue = 1;
30160let opNewValue = 0;
30161let isCVI = 1;
30162let DecoderNamespace = "EXT_mmvec";
30163}
30164def V6_vaddb_alt : HInst<
30165(outs HvxVR:$Vd32),
30166(ins HvxVR:$Vu32, HvxVR:$Vv32),
30167"$Vd32 = vaddb($Vu32,$Vv32)",
30168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30169let hasNewValue = 1;
30170let opNewValue = 0;
30171let isCVI = 1;
30172let isPseudo = 1;
30173let isCodeGenOnly = 1;
30174let DecoderNamespace = "EXT_mmvec";
30175}
30176def V6_vaddb_dv : HInst<
30177(outs HvxWR:$Vdd32),
30178(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30179"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
30180tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30181let Inst{7-5} = 0b100;
30182let Inst{13-13} = 0b0;
30183let Inst{31-21} = 0b00011100011;
30184let hasNewValue = 1;
30185let opNewValue = 0;
30186let isCVI = 1;
30187let DecoderNamespace = "EXT_mmvec";
30188}
30189def V6_vaddb_dv_alt : HInst<
30190(outs HvxWR:$Vdd32),
30191(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30192"$Vdd32 = vaddb($Vuu32,$Vvv32)",
30193PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30194let hasNewValue = 1;
30195let opNewValue = 0;
30196let isCVI = 1;
30197let isPseudo = 1;
30198let isCodeGenOnly = 1;
30199let DecoderNamespace = "EXT_mmvec";
30200}
30201def V6_vaddbnq : HInst<
30202(outs HvxVR:$Vx32),
30203(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30204"if (!$Qv4) $Vx32.b += $Vu32.b",
30205tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30206let Inst{7-5} = 0b011;
30207let Inst{13-13} = 0b1;
30208let Inst{21-16} = 0b000001;
30209let Inst{31-24} = 0b00011110;
30210let hasNewValue = 1;
30211let opNewValue = 0;
30212let isAccumulator = 1;
30213let isCVI = 1;
30214let DecoderNamespace = "EXT_mmvec";
30215let Constraints = "$Vx32 = $Vx32in";
30216}
30217def V6_vaddbnq_alt : HInst<
30218(outs HvxVR:$Vx32),
30219(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30220"if (!$Qv4.b) $Vx32.b += $Vu32.b",
30221PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30222let hasNewValue = 1;
30223let opNewValue = 0;
30224let isAccumulator = 1;
30225let isCVI = 1;
30226let isPseudo = 1;
30227let isCodeGenOnly = 1;
30228let DecoderNamespace = "EXT_mmvec";
30229let Constraints = "$Vx32 = $Vx32in";
30230}
30231def V6_vaddbq : HInst<
30232(outs HvxVR:$Vx32),
30233(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30234"if ($Qv4) $Vx32.b += $Vu32.b",
30235tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30236let Inst{7-5} = 0b000;
30237let Inst{13-13} = 0b1;
30238let Inst{21-16} = 0b000001;
30239let Inst{31-24} = 0b00011110;
30240let hasNewValue = 1;
30241let opNewValue = 0;
30242let isAccumulator = 1;
30243let isCVI = 1;
30244let DecoderNamespace = "EXT_mmvec";
30245let Constraints = "$Vx32 = $Vx32in";
30246}
30247def V6_vaddbq_alt : HInst<
30248(outs HvxVR:$Vx32),
30249(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30250"if ($Qv4.b) $Vx32.b += $Vu32.b",
30251PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30252let hasNewValue = 1;
30253let opNewValue = 0;
30254let isAccumulator = 1;
30255let isCVI = 1;
30256let isPseudo = 1;
30257let isCodeGenOnly = 1;
30258let DecoderNamespace = "EXT_mmvec";
30259let Constraints = "$Vx32 = $Vx32in";
30260}
30261def V6_vaddbsat : HInst<
30262(outs HvxVR:$Vd32),
30263(ins HvxVR:$Vu32, HvxVR:$Vv32),
30264"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
30265tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30266let Inst{7-5} = 0b000;
30267let Inst{13-13} = 0b0;
30268let Inst{31-21} = 0b00011111000;
30269let hasNewValue = 1;
30270let opNewValue = 0;
30271let isCVI = 1;
30272let DecoderNamespace = "EXT_mmvec";
30273}
30274def V6_vaddbsat_alt : HInst<
30275(outs HvxVR:$Vd32),
30276(ins HvxVR:$Vu32, HvxVR:$Vv32),
30277"$Vd32 = vaddb($Vu32,$Vv32):sat",
30278PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30279let hasNewValue = 1;
30280let opNewValue = 0;
30281let isCVI = 1;
30282let isPseudo = 1;
30283let isCodeGenOnly = 1;
30284let DecoderNamespace = "EXT_mmvec";
30285}
30286def V6_vaddbsat_dv : HInst<
30287(outs HvxWR:$Vdd32),
30288(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30289"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
30290tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
30291let Inst{7-5} = 0b000;
30292let Inst{13-13} = 0b0;
30293let Inst{31-21} = 0b00011110101;
30294let hasNewValue = 1;
30295let opNewValue = 0;
30296let isCVI = 1;
30297let DecoderNamespace = "EXT_mmvec";
30298}
30299def V6_vaddbsat_dv_alt : HInst<
30300(outs HvxWR:$Vdd32),
30301(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30302"$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
30303PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30304let hasNewValue = 1;
30305let opNewValue = 0;
30306let isCVI = 1;
30307let isPseudo = 1;
30308let isCodeGenOnly = 1;
30309let DecoderNamespace = "EXT_mmvec";
30310}
30311def V6_vaddcarry : HInst<
30312(outs HvxVR:$Vd32, HvxQR:$Qx4),
30313(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
30314"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
30315tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
30316let Inst{7-7} = 0b0;
30317let Inst{13-13} = 0b1;
30318let Inst{31-21} = 0b00011100101;
30319let hasNewValue = 1;
30320let opNewValue = 0;
30321let isCVI = 1;
30322let DecoderNamespace = "EXT_mmvec";
30323let Constraints = "$Qx4 = $Qx4in";
30324}
30325def V6_vaddcarryo : HInst<
30326(outs HvxVR:$Vd32, HvxQR:$Qe4),
30327(ins HvxVR:$Vu32, HvxVR:$Vv32),
30328"$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry",
30329tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
30330let Inst{7-7} = 0b0;
30331let Inst{13-13} = 0b1;
30332let Inst{31-21} = 0b00011101101;
30333let hasNewValue = 1;
30334let opNewValue = 0;
30335let hasNewValue2 = 1;
30336let opNewValue2 = 1;
30337let isCVI = 1;
30338let DecoderNamespace = "EXT_mmvec";
30339}
30340def V6_vaddcarrysat : HInst<
30341(outs HvxVR:$Vd32),
30342(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qs4),
30343"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qs4):carry:sat",
30344tc_257f6f7c, TypeCVI_VA>, Enc_e0820b, Requires<[UseHVXV66]> {
30345let Inst{7-7} = 0b0;
30346let Inst{13-13} = 0b1;
30347let Inst{31-21} = 0b00011101100;
30348let hasNewValue = 1;
30349let opNewValue = 0;
30350let isCVI = 1;
30351let DecoderNamespace = "EXT_mmvec";
30352}
30353def V6_vaddclbh : HInst<
30354(outs HvxVR:$Vd32),
30355(ins HvxVR:$Vu32, HvxVR:$Vv32),
30356"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
30357tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30358let Inst{7-5} = 0b000;
30359let Inst{13-13} = 0b1;
30360let Inst{31-21} = 0b00011111000;
30361let hasNewValue = 1;
30362let opNewValue = 0;
30363let isCVI = 1;
30364let DecoderNamespace = "EXT_mmvec";
30365}
30366def V6_vaddclbw : HInst<
30367(outs HvxVR:$Vd32),
30368(ins HvxVR:$Vu32, HvxVR:$Vv32),
30369"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
30370tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30371let Inst{7-5} = 0b001;
30372let Inst{13-13} = 0b1;
30373let Inst{31-21} = 0b00011111000;
30374let hasNewValue = 1;
30375let opNewValue = 0;
30376let isCVI = 1;
30377let DecoderNamespace = "EXT_mmvec";
30378}
30379def V6_vaddh : HInst<
30380(outs HvxVR:$Vd32),
30381(ins HvxVR:$Vu32, HvxVR:$Vv32),
30382"$Vd32.h = vadd($Vu32.h,$Vv32.h)",
30383tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30384let Inst{7-5} = 0b111;
30385let Inst{13-13} = 0b0;
30386let Inst{31-21} = 0b00011111101;
30387let hasNewValue = 1;
30388let opNewValue = 0;
30389let isCVI = 1;
30390let DecoderNamespace = "EXT_mmvec";
30391}
30392def V6_vaddh_alt : HInst<
30393(outs HvxVR:$Vd32),
30394(ins HvxVR:$Vu32, HvxVR:$Vv32),
30395"$Vd32 = vaddh($Vu32,$Vv32)",
30396PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30397let hasNewValue = 1;
30398let opNewValue = 0;
30399let isCVI = 1;
30400let isPseudo = 1;
30401let isCodeGenOnly = 1;
30402let DecoderNamespace = "EXT_mmvec";
30403}
30404def V6_vaddh_dv : HInst<
30405(outs HvxWR:$Vdd32),
30406(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30407"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
30408tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30409let Inst{7-5} = 0b101;
30410let Inst{13-13} = 0b0;
30411let Inst{31-21} = 0b00011100011;
30412let hasNewValue = 1;
30413let opNewValue = 0;
30414let isCVI = 1;
30415let DecoderNamespace = "EXT_mmvec";
30416}
30417def V6_vaddh_dv_alt : HInst<
30418(outs HvxWR:$Vdd32),
30419(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30420"$Vdd32 = vaddh($Vuu32,$Vvv32)",
30421PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30422let hasNewValue = 1;
30423let opNewValue = 0;
30424let isCVI = 1;
30425let isPseudo = 1;
30426let isCodeGenOnly = 1;
30427let DecoderNamespace = "EXT_mmvec";
30428}
30429def V6_vaddhnq : HInst<
30430(outs HvxVR:$Vx32),
30431(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30432"if (!$Qv4) $Vx32.h += $Vu32.h",
30433tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30434let Inst{7-5} = 0b100;
30435let Inst{13-13} = 0b1;
30436let Inst{21-16} = 0b000001;
30437let Inst{31-24} = 0b00011110;
30438let hasNewValue = 1;
30439let opNewValue = 0;
30440let isAccumulator = 1;
30441let isCVI = 1;
30442let DecoderNamespace = "EXT_mmvec";
30443let Constraints = "$Vx32 = $Vx32in";
30444}
30445def V6_vaddhnq_alt : HInst<
30446(outs HvxVR:$Vx32),
30447(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30448"if (!$Qv4.h) $Vx32.h += $Vu32.h",
30449PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30450let hasNewValue = 1;
30451let opNewValue = 0;
30452let isAccumulator = 1;
30453let isCVI = 1;
30454let isPseudo = 1;
30455let isCodeGenOnly = 1;
30456let DecoderNamespace = "EXT_mmvec";
30457let Constraints = "$Vx32 = $Vx32in";
30458}
30459def V6_vaddhq : HInst<
30460(outs HvxVR:$Vx32),
30461(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30462"if ($Qv4) $Vx32.h += $Vu32.h",
30463tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30464let Inst{7-5} = 0b001;
30465let Inst{13-13} = 0b1;
30466let Inst{21-16} = 0b000001;
30467let Inst{31-24} = 0b00011110;
30468let hasNewValue = 1;
30469let opNewValue = 0;
30470let isAccumulator = 1;
30471let isCVI = 1;
30472let DecoderNamespace = "EXT_mmvec";
30473let Constraints = "$Vx32 = $Vx32in";
30474}
30475def V6_vaddhq_alt : HInst<
30476(outs HvxVR:$Vx32),
30477(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30478"if ($Qv4.h) $Vx32.h += $Vu32.h",
30479PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30480let hasNewValue = 1;
30481let opNewValue = 0;
30482let isAccumulator = 1;
30483let isCVI = 1;
30484let isPseudo = 1;
30485let isCodeGenOnly = 1;
30486let DecoderNamespace = "EXT_mmvec";
30487let Constraints = "$Vx32 = $Vx32in";
30488}
30489def V6_vaddhsat : HInst<
30490(outs HvxVR:$Vd32),
30491(ins HvxVR:$Vu32, HvxVR:$Vv32),
30492"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
30493tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30494let Inst{7-5} = 0b011;
30495let Inst{13-13} = 0b0;
30496let Inst{31-21} = 0b00011100010;
30497let hasNewValue = 1;
30498let opNewValue = 0;
30499let isCVI = 1;
30500let DecoderNamespace = "EXT_mmvec";
30501}
30502def V6_vaddhsat_alt : HInst<
30503(outs HvxVR:$Vd32),
30504(ins HvxVR:$Vu32, HvxVR:$Vv32),
30505"$Vd32 = vaddh($Vu32,$Vv32):sat",
30506PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30507let hasNewValue = 1;
30508let opNewValue = 0;
30509let isCVI = 1;
30510let isPseudo = 1;
30511let isCodeGenOnly = 1;
30512let DecoderNamespace = "EXT_mmvec";
30513}
30514def V6_vaddhsat_dv : HInst<
30515(outs HvxWR:$Vdd32),
30516(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30517"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
30518tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30519let Inst{7-5} = 0b001;
30520let Inst{13-13} = 0b0;
30521let Inst{31-21} = 0b00011100100;
30522let hasNewValue = 1;
30523let opNewValue = 0;
30524let isCVI = 1;
30525let DecoderNamespace = "EXT_mmvec";
30526}
30527def V6_vaddhsat_dv_alt : HInst<
30528(outs HvxWR:$Vdd32),
30529(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30530"$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
30531PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30532let hasNewValue = 1;
30533let opNewValue = 0;
30534let isCVI = 1;
30535let isPseudo = 1;
30536let isCodeGenOnly = 1;
30537let DecoderNamespace = "EXT_mmvec";
30538}
30539def V6_vaddhw : HInst<
30540(outs HvxWR:$Vdd32),
30541(ins HvxVR:$Vu32, HvxVR:$Vv32),
30542"$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
30543tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30544let Inst{7-5} = 0b100;
30545let Inst{13-13} = 0b0;
30546let Inst{31-21} = 0b00011100101;
30547let hasNewValue = 1;
30548let opNewValue = 0;
30549let isCVI = 1;
30550let DecoderNamespace = "EXT_mmvec";
30551}
30552def V6_vaddhw_acc : HInst<
30553(outs HvxWR:$Vxx32),
30554(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30555"$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
30556tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30557let Inst{7-5} = 0b010;
30558let Inst{13-13} = 0b1;
30559let Inst{31-21} = 0b00011100001;
30560let hasNewValue = 1;
30561let opNewValue = 0;
30562let isAccumulator = 1;
30563let isCVI = 1;
30564let DecoderNamespace = "EXT_mmvec";
30565let Constraints = "$Vxx32 = $Vxx32in";
30566}
30567def V6_vaddhw_acc_alt : HInst<
30568(outs HvxWR:$Vxx32),
30569(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30570"$Vxx32 += vaddh($Vu32,$Vv32)",
30571PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30572let hasNewValue = 1;
30573let opNewValue = 0;
30574let isAccumulator = 1;
30575let isCVI = 1;
30576let isPseudo = 1;
30577let isCodeGenOnly = 1;
30578let DecoderNamespace = "EXT_mmvec";
30579let Constraints = "$Vxx32 = $Vxx32in";
30580}
30581def V6_vaddhw_alt : HInst<
30582(outs HvxWR:$Vdd32),
30583(ins HvxVR:$Vu32, HvxVR:$Vv32),
30584"$Vdd32 = vaddh($Vu32,$Vv32)",
30585PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30586let hasNewValue = 1;
30587let opNewValue = 0;
30588let isCVI = 1;
30589let isPseudo = 1;
30590let isCodeGenOnly = 1;
30591let DecoderNamespace = "EXT_mmvec";
30592}
30593def V6_vaddubh : HInst<
30594(outs HvxWR:$Vdd32),
30595(ins HvxVR:$Vu32, HvxVR:$Vv32),
30596"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
30597tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30598let Inst{7-5} = 0b010;
30599let Inst{13-13} = 0b0;
30600let Inst{31-21} = 0b00011100101;
30601let hasNewValue = 1;
30602let opNewValue = 0;
30603let isCVI = 1;
30604let DecoderNamespace = "EXT_mmvec";
30605}
30606def V6_vaddubh_acc : HInst<
30607(outs HvxWR:$Vxx32),
30608(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30609"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
30610tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30611let Inst{7-5} = 0b101;
30612let Inst{13-13} = 0b1;
30613let Inst{31-21} = 0b00011100010;
30614let hasNewValue = 1;
30615let opNewValue = 0;
30616let isAccumulator = 1;
30617let isCVI = 1;
30618let DecoderNamespace = "EXT_mmvec";
30619let Constraints = "$Vxx32 = $Vxx32in";
30620}
30621def V6_vaddubh_acc_alt : HInst<
30622(outs HvxWR:$Vxx32),
30623(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30624"$Vxx32 += vaddub($Vu32,$Vv32)",
30625PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30626let hasNewValue = 1;
30627let opNewValue = 0;
30628let isAccumulator = 1;
30629let isCVI = 1;
30630let isPseudo = 1;
30631let isCodeGenOnly = 1;
30632let DecoderNamespace = "EXT_mmvec";
30633let Constraints = "$Vxx32 = $Vxx32in";
30634}
30635def V6_vaddubh_alt : HInst<
30636(outs HvxWR:$Vdd32),
30637(ins HvxVR:$Vu32, HvxVR:$Vv32),
30638"$Vdd32 = vaddub($Vu32,$Vv32)",
30639PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30640let hasNewValue = 1;
30641let opNewValue = 0;
30642let isCVI = 1;
30643let isPseudo = 1;
30644let isCodeGenOnly = 1;
30645let DecoderNamespace = "EXT_mmvec";
30646}
30647def V6_vaddubsat : HInst<
30648(outs HvxVR:$Vd32),
30649(ins HvxVR:$Vu32, HvxVR:$Vv32),
30650"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
30651tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30652let Inst{7-5} = 0b001;
30653let Inst{13-13} = 0b0;
30654let Inst{31-21} = 0b00011100010;
30655let hasNewValue = 1;
30656let opNewValue = 0;
30657let isCVI = 1;
30658let DecoderNamespace = "EXT_mmvec";
30659}
30660def V6_vaddubsat_alt : HInst<
30661(outs HvxVR:$Vd32),
30662(ins HvxVR:$Vu32, HvxVR:$Vv32),
30663"$Vd32 = vaddub($Vu32,$Vv32):sat",
30664PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30665let hasNewValue = 1;
30666let opNewValue = 0;
30667let isCVI = 1;
30668let isPseudo = 1;
30669let isCodeGenOnly = 1;
30670let DecoderNamespace = "EXT_mmvec";
30671}
30672def V6_vaddubsat_dv : HInst<
30673(outs HvxWR:$Vdd32),
30674(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30675"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
30676tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30677let Inst{7-5} = 0b111;
30678let Inst{13-13} = 0b0;
30679let Inst{31-21} = 0b00011100011;
30680let hasNewValue = 1;
30681let opNewValue = 0;
30682let isCVI = 1;
30683let DecoderNamespace = "EXT_mmvec";
30684}
30685def V6_vaddubsat_dv_alt : HInst<
30686(outs HvxWR:$Vdd32),
30687(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30688"$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
30689PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30690let hasNewValue = 1;
30691let opNewValue = 0;
30692let isCVI = 1;
30693let isPseudo = 1;
30694let isCodeGenOnly = 1;
30695let DecoderNamespace = "EXT_mmvec";
30696}
30697def V6_vaddububb_sat : HInst<
30698(outs HvxVR:$Vd32),
30699(ins HvxVR:$Vu32, HvxVR:$Vv32),
30700"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
30701tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30702let Inst{7-5} = 0b100;
30703let Inst{13-13} = 0b0;
30704let Inst{31-21} = 0b00011110101;
30705let hasNewValue = 1;
30706let opNewValue = 0;
30707let isCVI = 1;
30708let DecoderNamespace = "EXT_mmvec";
30709}
30710def V6_vadduhsat : HInst<
30711(outs HvxVR:$Vd32),
30712(ins HvxVR:$Vu32, HvxVR:$Vv32),
30713"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
30714tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30715let Inst{7-5} = 0b010;
30716let Inst{13-13} = 0b0;
30717let Inst{31-21} = 0b00011100010;
30718let hasNewValue = 1;
30719let opNewValue = 0;
30720let isCVI = 1;
30721let DecoderNamespace = "EXT_mmvec";
30722}
30723def V6_vadduhsat_alt : HInst<
30724(outs HvxVR:$Vd32),
30725(ins HvxVR:$Vu32, HvxVR:$Vv32),
30726"$Vd32 = vadduh($Vu32,$Vv32):sat",
30727PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30728let hasNewValue = 1;
30729let opNewValue = 0;
30730let isCVI = 1;
30731let isPseudo = 1;
30732let isCodeGenOnly = 1;
30733let DecoderNamespace = "EXT_mmvec";
30734}
30735def V6_vadduhsat_dv : HInst<
30736(outs HvxWR:$Vdd32),
30737(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30738"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
30739tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30740let Inst{7-5} = 0b000;
30741let Inst{13-13} = 0b0;
30742let Inst{31-21} = 0b00011100100;
30743let hasNewValue = 1;
30744let opNewValue = 0;
30745let isCVI = 1;
30746let DecoderNamespace = "EXT_mmvec";
30747}
30748def V6_vadduhsat_dv_alt : HInst<
30749(outs HvxWR:$Vdd32),
30750(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30751"$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
30752PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30753let hasNewValue = 1;
30754let opNewValue = 0;
30755let isCVI = 1;
30756let isPseudo = 1;
30757let isCodeGenOnly = 1;
30758let DecoderNamespace = "EXT_mmvec";
30759}
30760def V6_vadduhw : HInst<
30761(outs HvxWR:$Vdd32),
30762(ins HvxVR:$Vu32, HvxVR:$Vv32),
30763"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
30764tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30765let Inst{7-5} = 0b011;
30766let Inst{13-13} = 0b0;
30767let Inst{31-21} = 0b00011100101;
30768let hasNewValue = 1;
30769let opNewValue = 0;
30770let isCVI = 1;
30771let DecoderNamespace = "EXT_mmvec";
30772}
30773def V6_vadduhw_acc : HInst<
30774(outs HvxWR:$Vxx32),
30775(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30776"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
30777tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30778let Inst{7-5} = 0b100;
30779let Inst{13-13} = 0b1;
30780let Inst{31-21} = 0b00011100010;
30781let hasNewValue = 1;
30782let opNewValue = 0;
30783let isAccumulator = 1;
30784let isCVI = 1;
30785let DecoderNamespace = "EXT_mmvec";
30786let Constraints = "$Vxx32 = $Vxx32in";
30787}
30788def V6_vadduhw_acc_alt : HInst<
30789(outs HvxWR:$Vxx32),
30790(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30791"$Vxx32 += vadduh($Vu32,$Vv32)",
30792PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30793let hasNewValue = 1;
30794let opNewValue = 0;
30795let isAccumulator = 1;
30796let isCVI = 1;
30797let isPseudo = 1;
30798let isCodeGenOnly = 1;
30799let DecoderNamespace = "EXT_mmvec";
30800let Constraints = "$Vxx32 = $Vxx32in";
30801}
30802def V6_vadduhw_alt : HInst<
30803(outs HvxWR:$Vdd32),
30804(ins HvxVR:$Vu32, HvxVR:$Vv32),
30805"$Vdd32 = vadduh($Vu32,$Vv32)",
30806PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30807let hasNewValue = 1;
30808let opNewValue = 0;
30809let isCVI = 1;
30810let isPseudo = 1;
30811let isCodeGenOnly = 1;
30812let DecoderNamespace = "EXT_mmvec";
30813}
30814def V6_vadduwsat : HInst<
30815(outs HvxVR:$Vd32),
30816(ins HvxVR:$Vu32, HvxVR:$Vv32),
30817"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
30818tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30819let Inst{7-5} = 0b001;
30820let Inst{13-13} = 0b0;
30821let Inst{31-21} = 0b00011111011;
30822let hasNewValue = 1;
30823let opNewValue = 0;
30824let isCVI = 1;
30825let DecoderNamespace = "EXT_mmvec";
30826}
30827def V6_vadduwsat_alt : HInst<
30828(outs HvxVR:$Vd32),
30829(ins HvxVR:$Vu32, HvxVR:$Vv32),
30830"$Vd32 = vadduw($Vu32,$Vv32):sat",
30831PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30832let hasNewValue = 1;
30833let opNewValue = 0;
30834let isCVI = 1;
30835let isPseudo = 1;
30836let isCodeGenOnly = 1;
30837let DecoderNamespace = "EXT_mmvec";
30838}
30839def V6_vadduwsat_dv : HInst<
30840(outs HvxWR:$Vdd32),
30841(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30842"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
30843tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
30844let Inst{7-5} = 0b010;
30845let Inst{13-13} = 0b0;
30846let Inst{31-21} = 0b00011110101;
30847let hasNewValue = 1;
30848let opNewValue = 0;
30849let isCVI = 1;
30850let DecoderNamespace = "EXT_mmvec";
30851}
30852def V6_vadduwsat_dv_alt : HInst<
30853(outs HvxWR:$Vdd32),
30854(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30855"$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
30856PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30857let hasNewValue = 1;
30858let opNewValue = 0;
30859let isCVI = 1;
30860let isPseudo = 1;
30861let isCodeGenOnly = 1;
30862let DecoderNamespace = "EXT_mmvec";
30863}
30864def V6_vaddw : HInst<
30865(outs HvxVR:$Vd32),
30866(ins HvxVR:$Vu32, HvxVR:$Vv32),
30867"$Vd32.w = vadd($Vu32.w,$Vv32.w)",
30868tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30869let Inst{7-5} = 0b000;
30870let Inst{13-13} = 0b0;
30871let Inst{31-21} = 0b00011100010;
30872let hasNewValue = 1;
30873let opNewValue = 0;
30874let isCVI = 1;
30875let DecoderNamespace = "EXT_mmvec";
30876}
30877def V6_vaddw_alt : HInst<
30878(outs HvxVR:$Vd32),
30879(ins HvxVR:$Vu32, HvxVR:$Vv32),
30880"$Vd32 = vaddw($Vu32,$Vv32)",
30881PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30882let hasNewValue = 1;
30883let opNewValue = 0;
30884let isCVI = 1;
30885let isPseudo = 1;
30886let isCodeGenOnly = 1;
30887let DecoderNamespace = "EXT_mmvec";
30888}
30889def V6_vaddw_dv : HInst<
30890(outs HvxWR:$Vdd32),
30891(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30892"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
30893tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30894let Inst{7-5} = 0b110;
30895let Inst{13-13} = 0b0;
30896let Inst{31-21} = 0b00011100011;
30897let hasNewValue = 1;
30898let opNewValue = 0;
30899let isCVI = 1;
30900let DecoderNamespace = "EXT_mmvec";
30901}
30902def V6_vaddw_dv_alt : HInst<
30903(outs HvxWR:$Vdd32),
30904(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30905"$Vdd32 = vaddw($Vuu32,$Vvv32)",
30906PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30907let hasNewValue = 1;
30908let opNewValue = 0;
30909let isCVI = 1;
30910let isPseudo = 1;
30911let isCodeGenOnly = 1;
30912let DecoderNamespace = "EXT_mmvec";
30913}
30914def V6_vaddwnq : HInst<
30915(outs HvxVR:$Vx32),
30916(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30917"if (!$Qv4) $Vx32.w += $Vu32.w",
30918tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30919let Inst{7-5} = 0b101;
30920let Inst{13-13} = 0b1;
30921let Inst{21-16} = 0b000001;
30922let Inst{31-24} = 0b00011110;
30923let hasNewValue = 1;
30924let opNewValue = 0;
30925let isAccumulator = 1;
30926let isCVI = 1;
30927let DecoderNamespace = "EXT_mmvec";
30928let Constraints = "$Vx32 = $Vx32in";
30929}
30930def V6_vaddwnq_alt : HInst<
30931(outs HvxVR:$Vx32),
30932(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30933"if (!$Qv4.w) $Vx32.w += $Vu32.w",
30934PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30935let hasNewValue = 1;
30936let opNewValue = 0;
30937let isAccumulator = 1;
30938let isCVI = 1;
30939let isPseudo = 1;
30940let isCodeGenOnly = 1;
30941let DecoderNamespace = "EXT_mmvec";
30942let Constraints = "$Vx32 = $Vx32in";
30943}
30944def V6_vaddwq : HInst<
30945(outs HvxVR:$Vx32),
30946(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30947"if ($Qv4) $Vx32.w += $Vu32.w",
30948tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30949let Inst{7-5} = 0b010;
30950let Inst{13-13} = 0b1;
30951let Inst{21-16} = 0b000001;
30952let Inst{31-24} = 0b00011110;
30953let hasNewValue = 1;
30954let opNewValue = 0;
30955let isAccumulator = 1;
30956let isCVI = 1;
30957let DecoderNamespace = "EXT_mmvec";
30958let Constraints = "$Vx32 = $Vx32in";
30959}
30960def V6_vaddwq_alt : HInst<
30961(outs HvxVR:$Vx32),
30962(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30963"if ($Qv4.w) $Vx32.w += $Vu32.w",
30964PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30965let hasNewValue = 1;
30966let opNewValue = 0;
30967let isAccumulator = 1;
30968let isCVI = 1;
30969let isPseudo = 1;
30970let isCodeGenOnly = 1;
30971let DecoderNamespace = "EXT_mmvec";
30972let Constraints = "$Vx32 = $Vx32in";
30973}
30974def V6_vaddwsat : HInst<
30975(outs HvxVR:$Vd32),
30976(ins HvxVR:$Vu32, HvxVR:$Vv32),
30977"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
30978tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30979let Inst{7-5} = 0b100;
30980let Inst{13-13} = 0b0;
30981let Inst{31-21} = 0b00011100010;
30982let hasNewValue = 1;
30983let opNewValue = 0;
30984let isCVI = 1;
30985let DecoderNamespace = "EXT_mmvec";
30986}
30987def V6_vaddwsat_alt : HInst<
30988(outs HvxVR:$Vd32),
30989(ins HvxVR:$Vu32, HvxVR:$Vv32),
30990"$Vd32 = vaddw($Vu32,$Vv32):sat",
30991PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30992let hasNewValue = 1;
30993let opNewValue = 0;
30994let isCVI = 1;
30995let isPseudo = 1;
30996let isCodeGenOnly = 1;
30997let DecoderNamespace = "EXT_mmvec";
30998}
30999def V6_vaddwsat_dv : HInst<
31000(outs HvxWR:$Vdd32),
31001(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31002"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
31003tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
31004let Inst{7-5} = 0b010;
31005let Inst{13-13} = 0b0;
31006let Inst{31-21} = 0b00011100100;
31007let hasNewValue = 1;
31008let opNewValue = 0;
31009let isCVI = 1;
31010let DecoderNamespace = "EXT_mmvec";
31011}
31012def V6_vaddwsat_dv_alt : HInst<
31013(outs HvxWR:$Vdd32),
31014(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31015"$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
31016PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31017let hasNewValue = 1;
31018let opNewValue = 0;
31019let isCVI = 1;
31020let isPseudo = 1;
31021let isCodeGenOnly = 1;
31022let DecoderNamespace = "EXT_mmvec";
31023}
31024def V6_valignb : HInst<
31025(outs HvxVR:$Vd32),
31026(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31027"$Vd32 = valign($Vu32,$Vv32,$Rt8)",
31028tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
31029let Inst{7-5} = 0b000;
31030let Inst{13-13} = 0b0;
31031let Inst{31-24} = 0b00011011;
31032let hasNewValue = 1;
31033let opNewValue = 0;
31034let isCVI = 1;
31035let DecoderNamespace = "EXT_mmvec";
31036}
31037def V6_valignbi : HInst<
31038(outs HvxVR:$Vd32),
31039(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
31040"$Vd32 = valign($Vu32,$Vv32,#$Ii)",
31041tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
31042let Inst{13-13} = 0b1;
31043let Inst{31-21} = 0b00011110001;
31044let hasNewValue = 1;
31045let opNewValue = 0;
31046let isCVI = 1;
31047let DecoderNamespace = "EXT_mmvec";
31048}
31049def V6_vand : HInst<
31050(outs HvxVR:$Vd32),
31051(ins HvxVR:$Vu32, HvxVR:$Vv32),
31052"$Vd32 = vand($Vu32,$Vv32)",
31053tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31054let Inst{7-5} = 0b101;
31055let Inst{13-13} = 0b0;
31056let Inst{31-21} = 0b00011100001;
31057let hasNewValue = 1;
31058let opNewValue = 0;
31059let isCVI = 1;
31060let DecoderNamespace = "EXT_mmvec";
31061}
31062def V6_vandnqrt : HInst<
31063(outs HvxVR:$Vd32),
31064(ins HvxQR:$Qu4, IntRegs:$Rt32),
31065"$Vd32 = vand(!$Qu4,$Rt32)",
31066tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV62]> {
31067let Inst{7-5} = 0b101;
31068let Inst{13-10} = 0b0001;
31069let Inst{31-21} = 0b00011001101;
31070let hasNewValue = 1;
31071let opNewValue = 0;
31072let isCVI = 1;
31073let DecoderNamespace = "EXT_mmvec";
31074}
31075def V6_vandnqrt_acc : HInst<
31076(outs HvxVR:$Vx32),
31077(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31078"$Vx32 |= vand(!$Qu4,$Rt32)",
31079tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV62]> {
31080let Inst{7-5} = 0b011;
31081let Inst{13-10} = 0b1001;
31082let Inst{31-21} = 0b00011001011;
31083let hasNewValue = 1;
31084let opNewValue = 0;
31085let isAccumulator = 1;
31086let isCVI = 1;
31087let DecoderNamespace = "EXT_mmvec";
31088let Constraints = "$Vx32 = $Vx32in";
31089}
31090def V6_vandnqrt_acc_alt : HInst<
31091(outs HvxVR:$Vx32),
31092(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31093"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
31094PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31095let hasNewValue = 1;
31096let opNewValue = 0;
31097let isAccumulator = 1;
31098let isCVI = 1;
31099let isPseudo = 1;
31100let isCodeGenOnly = 1;
31101let DecoderNamespace = "EXT_mmvec";
31102let Constraints = "$Vx32 = $Vx32in";
31103}
31104def V6_vandnqrt_alt : HInst<
31105(outs HvxVR:$Vd32),
31106(ins HvxQR:$Qu4, IntRegs:$Rt32),
31107"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
31108PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31109let hasNewValue = 1;
31110let opNewValue = 0;
31111let isCVI = 1;
31112let isPseudo = 1;
31113let isCodeGenOnly = 1;
31114let DecoderNamespace = "EXT_mmvec";
31115}
31116def V6_vandqrt : HInst<
31117(outs HvxVR:$Vd32),
31118(ins HvxQR:$Qu4, IntRegs:$Rt32),
31119"$Vd32 = vand($Qu4,$Rt32)",
31120tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
31121let Inst{7-5} = 0b101;
31122let Inst{13-10} = 0b0000;
31123let Inst{31-21} = 0b00011001101;
31124let hasNewValue = 1;
31125let opNewValue = 0;
31126let isCVI = 1;
31127let DecoderNamespace = "EXT_mmvec";
31128}
31129def V6_vandqrt_acc : HInst<
31130(outs HvxVR:$Vx32),
31131(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31132"$Vx32 |= vand($Qu4,$Rt32)",
31133tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
31134let Inst{7-5} = 0b011;
31135let Inst{13-10} = 0b1000;
31136let Inst{31-21} = 0b00011001011;
31137let hasNewValue = 1;
31138let opNewValue = 0;
31139let isAccumulator = 1;
31140let isCVI = 1;
31141let DecoderNamespace = "EXT_mmvec";
31142let Constraints = "$Vx32 = $Vx32in";
31143}
31144def V6_vandqrt_acc_alt : HInst<
31145(outs HvxVR:$Vx32),
31146(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31147"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
31148PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31149let hasNewValue = 1;
31150let opNewValue = 0;
31151let isAccumulator = 1;
31152let isCVI = 1;
31153let isPseudo = 1;
31154let isCodeGenOnly = 1;
31155let DecoderNamespace = "EXT_mmvec";
31156let Constraints = "$Vx32 = $Vx32in";
31157}
31158def V6_vandqrt_alt : HInst<
31159(outs HvxVR:$Vd32),
31160(ins HvxQR:$Qu4, IntRegs:$Rt32),
31161"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
31162PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31163let hasNewValue = 1;
31164let opNewValue = 0;
31165let isCVI = 1;
31166let isPseudo = 1;
31167let isCodeGenOnly = 1;
31168let DecoderNamespace = "EXT_mmvec";
31169}
31170def V6_vandvnqv : HInst<
31171(outs HvxVR:$Vd32),
31172(ins HvxQR:$Qv4, HvxVR:$Vu32),
31173"$Vd32 = vand(!$Qv4,$Vu32)",
31174tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31175let Inst{7-5} = 0b001;
31176let Inst{13-13} = 0b1;
31177let Inst{21-16} = 0b000011;
31178let Inst{31-24} = 0b00011110;
31179let hasNewValue = 1;
31180let opNewValue = 0;
31181let isCVI = 1;
31182let DecoderNamespace = "EXT_mmvec";
31183}
31184def V6_vandvqv : HInst<
31185(outs HvxVR:$Vd32),
31186(ins HvxQR:$Qv4, HvxVR:$Vu32),
31187"$Vd32 = vand($Qv4,$Vu32)",
31188tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31189let Inst{7-5} = 0b000;
31190let Inst{13-13} = 0b1;
31191let Inst{21-16} = 0b000011;
31192let Inst{31-24} = 0b00011110;
31193let hasNewValue = 1;
31194let opNewValue = 0;
31195let isCVI = 1;
31196let DecoderNamespace = "EXT_mmvec";
31197}
31198def V6_vandvrt : HInst<
31199(outs HvxQR:$Qd4),
31200(ins HvxVR:$Vu32, IntRegs:$Rt32),
31201"$Qd4 = vand($Vu32,$Rt32)",
31202tc_ac4046bc, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
31203let Inst{7-2} = 0b010010;
31204let Inst{13-13} = 0b0;
31205let Inst{31-21} = 0b00011001101;
31206let hasNewValue = 1;
31207let opNewValue = 0;
31208let isCVI = 1;
31209let DecoderNamespace = "EXT_mmvec";
31210}
31211def V6_vandvrt_acc : HInst<
31212(outs HvxQR:$Qx4),
31213(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31214"$Qx4 |= vand($Vu32,$Rt32)",
31215tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
31216let Inst{7-2} = 0b100000;
31217let Inst{13-13} = 0b1;
31218let Inst{31-21} = 0b00011001011;
31219let isAccumulator = 1;
31220let isCVI = 1;
31221let DecoderNamespace = "EXT_mmvec";
31222let Constraints = "$Qx4 = $Qx4in";
31223}
31224def V6_vandvrt_acc_alt : HInst<
31225(outs HvxQR:$Qx4),
31226(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31227"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
31228PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31229let isAccumulator = 1;
31230let isCVI = 1;
31231let isPseudo = 1;
31232let isCodeGenOnly = 1;
31233let DecoderNamespace = "EXT_mmvec";
31234let Constraints = "$Qx4 = $Qx4in";
31235}
31236def V6_vandvrt_alt : HInst<
31237(outs HvxQR:$Qd4),
31238(ins HvxVR:$Vu32, IntRegs:$Rt32),
31239"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
31240PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31241let hasNewValue = 1;
31242let opNewValue = 0;
31243let isCVI = 1;
31244let isPseudo = 1;
31245let isCodeGenOnly = 1;
31246let DecoderNamespace = "EXT_mmvec";
31247}
31248def V6_vaslh : HInst<
31249(outs HvxVR:$Vd32),
31250(ins HvxVR:$Vu32, IntRegs:$Rt32),
31251"$Vd32.h = vasl($Vu32.h,$Rt32)",
31252tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31253let Inst{7-5} = 0b000;
31254let Inst{13-13} = 0b0;
31255let Inst{31-21} = 0b00011001100;
31256let hasNewValue = 1;
31257let opNewValue = 0;
31258let isCVI = 1;
31259let DecoderNamespace = "EXT_mmvec";
31260}
31261def V6_vaslh_acc : HInst<
31262(outs HvxVR:$Vx32),
31263(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31264"$Vx32.h += vasl($Vu32.h,$Rt32)",
31265tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31266let Inst{7-5} = 0b101;
31267let Inst{13-13} = 0b1;
31268let Inst{31-21} = 0b00011001101;
31269let hasNewValue = 1;
31270let opNewValue = 0;
31271let isAccumulator = 1;
31272let isCVI = 1;
31273let DecoderNamespace = "EXT_mmvec";
31274let Constraints = "$Vx32 = $Vx32in";
31275}
31276def V6_vaslh_acc_alt : HInst<
31277(outs HvxVR:$Vx32),
31278(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31279"$Vx32 += vaslh($Vu32,$Rt32)",
31280PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31281let hasNewValue = 1;
31282let opNewValue = 0;
31283let isAccumulator = 1;
31284let isCVI = 1;
31285let isPseudo = 1;
31286let isCodeGenOnly = 1;
31287let DecoderNamespace = "EXT_mmvec";
31288let Constraints = "$Vx32 = $Vx32in";
31289}
31290def V6_vaslh_alt : HInst<
31291(outs HvxVR:$Vd32),
31292(ins HvxVR:$Vu32, IntRegs:$Rt32),
31293"$Vd32 = vaslh($Vu32,$Rt32)",
31294PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31295let hasNewValue = 1;
31296let opNewValue = 0;
31297let isCVI = 1;
31298let isPseudo = 1;
31299let isCodeGenOnly = 1;
31300let DecoderNamespace = "EXT_mmvec";
31301}
31302def V6_vaslhv : HInst<
31303(outs HvxVR:$Vd32),
31304(ins HvxVR:$Vu32, HvxVR:$Vv32),
31305"$Vd32.h = vasl($Vu32.h,$Vv32.h)",
31306tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31307let Inst{7-5} = 0b101;
31308let Inst{13-13} = 0b0;
31309let Inst{31-21} = 0b00011111101;
31310let hasNewValue = 1;
31311let opNewValue = 0;
31312let isCVI = 1;
31313let DecoderNamespace = "EXT_mmvec";
31314}
31315def V6_vaslhv_alt : HInst<
31316(outs HvxVR:$Vd32),
31317(ins HvxVR:$Vu32, HvxVR:$Vv32),
31318"$Vd32 = vaslh($Vu32,$Vv32)",
31319PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31320let hasNewValue = 1;
31321let opNewValue = 0;
31322let isCVI = 1;
31323let isPseudo = 1;
31324let isCodeGenOnly = 1;
31325let DecoderNamespace = "EXT_mmvec";
31326}
31327def V6_vaslw : HInst<
31328(outs HvxVR:$Vd32),
31329(ins HvxVR:$Vu32, IntRegs:$Rt32),
31330"$Vd32.w = vasl($Vu32.w,$Rt32)",
31331tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31332let Inst{7-5} = 0b111;
31333let Inst{13-13} = 0b0;
31334let Inst{31-21} = 0b00011001011;
31335let hasNewValue = 1;
31336let opNewValue = 0;
31337let isCVI = 1;
31338let DecoderNamespace = "EXT_mmvec";
31339}
31340def V6_vaslw_acc : HInst<
31341(outs HvxVR:$Vx32),
31342(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31343"$Vx32.w += vasl($Vu32.w,$Rt32)",
31344tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31345let Inst{7-5} = 0b010;
31346let Inst{13-13} = 0b1;
31347let Inst{31-21} = 0b00011001011;
31348let hasNewValue = 1;
31349let opNewValue = 0;
31350let isAccumulator = 1;
31351let isCVI = 1;
31352let DecoderNamespace = "EXT_mmvec";
31353let Constraints = "$Vx32 = $Vx32in";
31354}
31355def V6_vaslw_acc_alt : HInst<
31356(outs HvxVR:$Vx32),
31357(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31358"$Vx32 += vaslw($Vu32,$Rt32)",
31359PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31360let hasNewValue = 1;
31361let opNewValue = 0;
31362let isAccumulator = 1;
31363let isCVI = 1;
31364let isPseudo = 1;
31365let isCodeGenOnly = 1;
31366let DecoderNamespace = "EXT_mmvec";
31367let Constraints = "$Vx32 = $Vx32in";
31368}
31369def V6_vaslw_alt : HInst<
31370(outs HvxVR:$Vd32),
31371(ins HvxVR:$Vu32, IntRegs:$Rt32),
31372"$Vd32 = vaslw($Vu32,$Rt32)",
31373PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31374let hasNewValue = 1;
31375let opNewValue = 0;
31376let isCVI = 1;
31377let isPseudo = 1;
31378let isCodeGenOnly = 1;
31379let DecoderNamespace = "EXT_mmvec";
31380}
31381def V6_vaslwv : HInst<
31382(outs HvxVR:$Vd32),
31383(ins HvxVR:$Vu32, HvxVR:$Vv32),
31384"$Vd32.w = vasl($Vu32.w,$Vv32.w)",
31385tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31386let Inst{7-5} = 0b100;
31387let Inst{13-13} = 0b0;
31388let Inst{31-21} = 0b00011111101;
31389let hasNewValue = 1;
31390let opNewValue = 0;
31391let isCVI = 1;
31392let DecoderNamespace = "EXT_mmvec";
31393}
31394def V6_vaslwv_alt : HInst<
31395(outs HvxVR:$Vd32),
31396(ins HvxVR:$Vu32, HvxVR:$Vv32),
31397"$Vd32 = vaslw($Vu32,$Vv32)",
31398PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31399let hasNewValue = 1;
31400let opNewValue = 0;
31401let isCVI = 1;
31402let isPseudo = 1;
31403let isCodeGenOnly = 1;
31404let DecoderNamespace = "EXT_mmvec";
31405}
31406def V6_vasr_into : HInst<
31407(outs HvxWR:$Vxx32),
31408(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31409"$Vxx32.w = vasrinto($Vu32.w,$Vv32.w)",
31410tc_df80eeb0, TypeCVI_VP_VS>, Enc_3fc427, Requires<[UseHVXV66]> {
31411let Inst{7-5} = 0b111;
31412let Inst{13-13} = 0b1;
31413let Inst{31-21} = 0b00011010101;
31414let hasNewValue = 1;
31415let opNewValue = 0;
31416let isCVI = 1;
31417let DecoderNamespace = "EXT_mmvec";
31418let Constraints = "$Vxx32 = $Vxx32in";
31419}
31420def V6_vasr_into_alt : HInst<
31421(outs HvxWR:$Vxx32),
31422(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31423"$Vxx32 = vasrinto($Vu32,$Vv32)",
31424PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
31425let hasNewValue = 1;
31426let opNewValue = 0;
31427let isCVI = 1;
31428let isPseudo = 1;
31429let isCodeGenOnly = 1;
31430let DecoderNamespace = "EXT_mmvec";
31431let Constraints = "$Vxx32 = $Vxx32in";
31432}
31433def V6_vasrh : HInst<
31434(outs HvxVR:$Vd32),
31435(ins HvxVR:$Vu32, IntRegs:$Rt32),
31436"$Vd32.h = vasr($Vu32.h,$Rt32)",
31437tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31438let Inst{7-5} = 0b110;
31439let Inst{13-13} = 0b0;
31440let Inst{31-21} = 0b00011001011;
31441let hasNewValue = 1;
31442let opNewValue = 0;
31443let isCVI = 1;
31444let DecoderNamespace = "EXT_mmvec";
31445}
31446def V6_vasrh_acc : HInst<
31447(outs HvxVR:$Vx32),
31448(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31449"$Vx32.h += vasr($Vu32.h,$Rt32)",
31450tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31451let Inst{7-5} = 0b111;
31452let Inst{13-13} = 0b1;
31453let Inst{31-21} = 0b00011001100;
31454let hasNewValue = 1;
31455let opNewValue = 0;
31456let isAccumulator = 1;
31457let isCVI = 1;
31458let DecoderNamespace = "EXT_mmvec";
31459let Constraints = "$Vx32 = $Vx32in";
31460}
31461def V6_vasrh_acc_alt : HInst<
31462(outs HvxVR:$Vx32),
31463(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31464"$Vx32 += vasrh($Vu32,$Rt32)",
31465PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31466let hasNewValue = 1;
31467let opNewValue = 0;
31468let isAccumulator = 1;
31469let isCVI = 1;
31470let isPseudo = 1;
31471let isCodeGenOnly = 1;
31472let DecoderNamespace = "EXT_mmvec";
31473let Constraints = "$Vx32 = $Vx32in";
31474}
31475def V6_vasrh_alt : HInst<
31476(outs HvxVR:$Vd32),
31477(ins HvxVR:$Vu32, IntRegs:$Rt32),
31478"$Vd32 = vasrh($Vu32,$Rt32)",
31479PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31480let hasNewValue = 1;
31481let opNewValue = 0;
31482let isCVI = 1;
31483let isPseudo = 1;
31484let isCodeGenOnly = 1;
31485let DecoderNamespace = "EXT_mmvec";
31486}
31487def V6_vasrhbrndsat : HInst<
31488(outs HvxVR:$Vd32),
31489(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31490"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31491tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31492let Inst{7-5} = 0b000;
31493let Inst{13-13} = 0b1;
31494let Inst{31-24} = 0b00011011;
31495let hasNewValue = 1;
31496let opNewValue = 0;
31497let isCVI = 1;
31498let DecoderNamespace = "EXT_mmvec";
31499}
31500def V6_vasrhbsat : HInst<
31501(outs HvxVR:$Vd32),
31502(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31503"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31504tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31505let Inst{7-5} = 0b000;
31506let Inst{13-13} = 0b0;
31507let Inst{31-24} = 0b00011000;
31508let hasNewValue = 1;
31509let opNewValue = 0;
31510let isCVI = 1;
31511let DecoderNamespace = "EXT_mmvec";
31512}
31513def V6_vasrhubrndsat : HInst<
31514(outs HvxVR:$Vd32),
31515(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31516"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31517tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31518let Inst{7-5} = 0b111;
31519let Inst{13-13} = 0b0;
31520let Inst{31-24} = 0b00011011;
31521let hasNewValue = 1;
31522let opNewValue = 0;
31523let isCVI = 1;
31524let DecoderNamespace = "EXT_mmvec";
31525}
31526def V6_vasrhubsat : HInst<
31527(outs HvxVR:$Vd32),
31528(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31529"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31530tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31531let Inst{7-5} = 0b110;
31532let Inst{13-13} = 0b0;
31533let Inst{31-24} = 0b00011011;
31534let hasNewValue = 1;
31535let opNewValue = 0;
31536let isCVI = 1;
31537let DecoderNamespace = "EXT_mmvec";
31538}
31539def V6_vasrhv : HInst<
31540(outs HvxVR:$Vd32),
31541(ins HvxVR:$Vu32, HvxVR:$Vv32),
31542"$Vd32.h = vasr($Vu32.h,$Vv32.h)",
31543tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31544let Inst{7-5} = 0b011;
31545let Inst{13-13} = 0b0;
31546let Inst{31-21} = 0b00011111101;
31547let hasNewValue = 1;
31548let opNewValue = 0;
31549let isCVI = 1;
31550let DecoderNamespace = "EXT_mmvec";
31551}
31552def V6_vasrhv_alt : HInst<
31553(outs HvxVR:$Vd32),
31554(ins HvxVR:$Vu32, HvxVR:$Vv32),
31555"$Vd32 = vasrh($Vu32,$Vv32)",
31556PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31557let hasNewValue = 1;
31558let opNewValue = 0;
31559let isCVI = 1;
31560let isPseudo = 1;
31561let isCodeGenOnly = 1;
31562let DecoderNamespace = "EXT_mmvec";
31563}
31564def V6_vasruhubrndsat : HInst<
31565(outs HvxVR:$Vd32),
31566(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31567"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
31568tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31569let Inst{7-5} = 0b111;
31570let Inst{13-13} = 0b0;
31571let Inst{31-24} = 0b00011000;
31572let hasNewValue = 1;
31573let opNewValue = 0;
31574let isCVI = 1;
31575let DecoderNamespace = "EXT_mmvec";
31576}
31577def V6_vasruhubsat : HInst<
31578(outs HvxVR:$Vd32),
31579(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31580"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
31581tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31582let Inst{7-5} = 0b101;
31583let Inst{13-13} = 0b1;
31584let Inst{31-24} = 0b00011000;
31585let hasNewValue = 1;
31586let opNewValue = 0;
31587let isCVI = 1;
31588let DecoderNamespace = "EXT_mmvec";
31589}
31590def V6_vasruwuhrndsat : HInst<
31591(outs HvxVR:$Vd32),
31592(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31593"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
31594tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31595let Inst{7-5} = 0b001;
31596let Inst{13-13} = 0b0;
31597let Inst{31-24} = 0b00011000;
31598let hasNewValue = 1;
31599let opNewValue = 0;
31600let isCVI = 1;
31601let DecoderNamespace = "EXT_mmvec";
31602}
31603def V6_vasruwuhsat : HInst<
31604(outs HvxVR:$Vd32),
31605(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31606"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
31607tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31608let Inst{7-5} = 0b100;
31609let Inst{13-13} = 0b1;
31610let Inst{31-24} = 0b00011000;
31611let hasNewValue = 1;
31612let opNewValue = 0;
31613let isCVI = 1;
31614let DecoderNamespace = "EXT_mmvec";
31615}
31616def V6_vasrvuhubrndsat : HInst<
31617(outs HvxVR:$Vd32),
31618(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31619"$Vd32.ub = vasr($Vuu32.uh,$Vv32.ub):rnd:sat",
31620tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31621let Inst{7-5} = 0b011;
31622let Inst{13-13} = 0b0;
31623let Inst{31-21} = 0b00011101000;
31624let hasNewValue = 1;
31625let opNewValue = 0;
31626let isCVI = 1;
31627let DecoderNamespace = "EXT_mmvec";
31628}
31629def V6_vasrvuhubsat : HInst<
31630(outs HvxVR:$Vd32),
31631(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31632"$Vd32.ub = vasr($Vuu32.uh,$Vv32.ub):sat",
31633tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31634let Inst{7-5} = 0b010;
31635let Inst{13-13} = 0b0;
31636let Inst{31-21} = 0b00011101000;
31637let hasNewValue = 1;
31638let opNewValue = 0;
31639let isCVI = 1;
31640let DecoderNamespace = "EXT_mmvec";
31641}
31642def V6_vasrvwuhrndsat : HInst<
31643(outs HvxVR:$Vd32),
31644(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31645"$Vd32.uh = vasr($Vuu32.w,$Vv32.uh):rnd:sat",
31646tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31647let Inst{7-5} = 0b001;
31648let Inst{13-13} = 0b0;
31649let Inst{31-21} = 0b00011101000;
31650let hasNewValue = 1;
31651let opNewValue = 0;
31652let isCVI = 1;
31653let DecoderNamespace = "EXT_mmvec";
31654}
31655def V6_vasrvwuhsat : HInst<
31656(outs HvxVR:$Vd32),
31657(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31658"$Vd32.uh = vasr($Vuu32.w,$Vv32.uh):sat",
31659tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31660let Inst{7-5} = 0b000;
31661let Inst{13-13} = 0b0;
31662let Inst{31-21} = 0b00011101000;
31663let hasNewValue = 1;
31664let opNewValue = 0;
31665let isCVI = 1;
31666let DecoderNamespace = "EXT_mmvec";
31667}
31668def V6_vasrw : HInst<
31669(outs HvxVR:$Vd32),
31670(ins HvxVR:$Vu32, IntRegs:$Rt32),
31671"$Vd32.w = vasr($Vu32.w,$Rt32)",
31672tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31673let Inst{7-5} = 0b101;
31674let Inst{13-13} = 0b0;
31675let Inst{31-21} = 0b00011001011;
31676let hasNewValue = 1;
31677let opNewValue = 0;
31678let isCVI = 1;
31679let DecoderNamespace = "EXT_mmvec";
31680}
31681def V6_vasrw_acc : HInst<
31682(outs HvxVR:$Vx32),
31683(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31684"$Vx32.w += vasr($Vu32.w,$Rt32)",
31685tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31686let Inst{7-5} = 0b101;
31687let Inst{13-13} = 0b1;
31688let Inst{31-21} = 0b00011001011;
31689let hasNewValue = 1;
31690let opNewValue = 0;
31691let isAccumulator = 1;
31692let isCVI = 1;
31693let DecoderNamespace = "EXT_mmvec";
31694let Constraints = "$Vx32 = $Vx32in";
31695}
31696def V6_vasrw_acc_alt : HInst<
31697(outs HvxVR:$Vx32),
31698(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31699"$Vx32 += vasrw($Vu32,$Rt32)",
31700PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31701let hasNewValue = 1;
31702let opNewValue = 0;
31703let isAccumulator = 1;
31704let isCVI = 1;
31705let isPseudo = 1;
31706let isCodeGenOnly = 1;
31707let DecoderNamespace = "EXT_mmvec";
31708let Constraints = "$Vx32 = $Vx32in";
31709}
31710def V6_vasrw_alt : HInst<
31711(outs HvxVR:$Vd32),
31712(ins HvxVR:$Vu32, IntRegs:$Rt32),
31713"$Vd32 = vasrw($Vu32,$Rt32)",
31714PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31715let hasNewValue = 1;
31716let opNewValue = 0;
31717let isCVI = 1;
31718let isPseudo = 1;
31719let isCodeGenOnly = 1;
31720let DecoderNamespace = "EXT_mmvec";
31721}
31722def V6_vasrwh : HInst<
31723(outs HvxVR:$Vd32),
31724(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31725"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
31726tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31727let Inst{7-5} = 0b010;
31728let Inst{13-13} = 0b0;
31729let Inst{31-24} = 0b00011011;
31730let hasNewValue = 1;
31731let opNewValue = 0;
31732let isCVI = 1;
31733let DecoderNamespace = "EXT_mmvec";
31734}
31735def V6_vasrwhrndsat : HInst<
31736(outs HvxVR:$Vd32),
31737(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31738"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31739tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31740let Inst{7-5} = 0b100;
31741let Inst{13-13} = 0b0;
31742let Inst{31-24} = 0b00011011;
31743let hasNewValue = 1;
31744let opNewValue = 0;
31745let isCVI = 1;
31746let DecoderNamespace = "EXT_mmvec";
31747}
31748def V6_vasrwhsat : HInst<
31749(outs HvxVR:$Vd32),
31750(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31751"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31752tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31753let Inst{7-5} = 0b011;
31754let Inst{13-13} = 0b0;
31755let Inst{31-24} = 0b00011011;
31756let hasNewValue = 1;
31757let opNewValue = 0;
31758let isCVI = 1;
31759let DecoderNamespace = "EXT_mmvec";
31760}
31761def V6_vasrwuhrndsat : HInst<
31762(outs HvxVR:$Vd32),
31763(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31764"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31765tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31766let Inst{7-5} = 0b010;
31767let Inst{13-13} = 0b0;
31768let Inst{31-24} = 0b00011000;
31769let hasNewValue = 1;
31770let opNewValue = 0;
31771let isCVI = 1;
31772let DecoderNamespace = "EXT_mmvec";
31773}
31774def V6_vasrwuhsat : HInst<
31775(outs HvxVR:$Vd32),
31776(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31777"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31778tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31779let Inst{7-5} = 0b101;
31780let Inst{13-13} = 0b0;
31781let Inst{31-24} = 0b00011011;
31782let hasNewValue = 1;
31783let opNewValue = 0;
31784let isCVI = 1;
31785let DecoderNamespace = "EXT_mmvec";
31786}
31787def V6_vasrwv : HInst<
31788(outs HvxVR:$Vd32),
31789(ins HvxVR:$Vu32, HvxVR:$Vv32),
31790"$Vd32.w = vasr($Vu32.w,$Vv32.w)",
31791tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31792let Inst{7-5} = 0b000;
31793let Inst{13-13} = 0b0;
31794let Inst{31-21} = 0b00011111101;
31795let hasNewValue = 1;
31796let opNewValue = 0;
31797let isCVI = 1;
31798let DecoderNamespace = "EXT_mmvec";
31799}
31800def V6_vasrwv_alt : HInst<
31801(outs HvxVR:$Vd32),
31802(ins HvxVR:$Vu32, HvxVR:$Vv32),
31803"$Vd32 = vasrw($Vu32,$Vv32)",
31804PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31805let hasNewValue = 1;
31806let opNewValue = 0;
31807let isCVI = 1;
31808let isPseudo = 1;
31809let isCodeGenOnly = 1;
31810let DecoderNamespace = "EXT_mmvec";
31811}
31812def V6_vassign : HInst<
31813(outs HvxVR:$Vd32),
31814(ins HvxVR:$Vu32),
31815"$Vd32 = $Vu32",
31816tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
31817let Inst{7-5} = 0b111;
31818let Inst{13-13} = 0b1;
31819let Inst{31-16} = 0b0001111000000011;
31820let hasNewValue = 1;
31821let opNewValue = 0;
31822let isCVI = 1;
31823let DecoderNamespace = "EXT_mmvec";
31824}
31825def V6_vassign_fp : HInst<
31826(outs HvxVR:$Vd32),
31827(ins HvxVR:$Vu32),
31828"$Vd32.w = vfmv($Vu32.w)",
31829tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
31830let Inst{7-5} = 0b001;
31831let Inst{13-13} = 0b1;
31832let Inst{31-16} = 0b0001111000000110;
31833let hasNewValue = 1;
31834let opNewValue = 0;
31835let isCVI = 1;
31836let DecoderNamespace = "EXT_mmvec";
31837}
31838def V6_vassign_tmp : HInst<
31839(outs HvxVR:$Vd32),
31840(ins HvxVR:$Vu32),
31841"$Vd32.tmp = $Vu32",
31842tc_2120355e, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV69]> {
31843let Inst{7-5} = 0b110;
31844let Inst{13-13} = 0b0;
31845let Inst{31-16} = 0b0001111000000001;
31846let hasNewValue = 1;
31847let opNewValue = 0;
31848let isCVI = 1;
31849let hasHvxTmp = 1;
31850let DecoderNamespace = "EXT_mmvec";
31851}
31852def V6_vassignp : HInst<
31853(outs HvxWR:$Vdd32),
31854(ins HvxWR:$Vuu32),
31855"$Vdd32 = $Vuu32",
31856CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
31857let hasNewValue = 1;
31858let opNewValue = 0;
31859let isCVI = 1;
31860let isPseudo = 1;
31861let DecoderNamespace = "EXT_mmvec";
31862}
31863def V6_vavgb : HInst<
31864(outs HvxVR:$Vd32),
31865(ins HvxVR:$Vu32, HvxVR:$Vv32),
31866"$Vd32.b = vavg($Vu32.b,$Vv32.b)",
31867tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31868let Inst{7-5} = 0b100;
31869let Inst{13-13} = 0b1;
31870let Inst{31-21} = 0b00011111000;
31871let hasNewValue = 1;
31872let opNewValue = 0;
31873let isCVI = 1;
31874let DecoderNamespace = "EXT_mmvec";
31875}
31876def V6_vavgb_alt : HInst<
31877(outs HvxVR:$Vd32),
31878(ins HvxVR:$Vu32, HvxVR:$Vv32),
31879"$Vd32 = vavgb($Vu32,$Vv32)",
31880PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31881let hasNewValue = 1;
31882let opNewValue = 0;
31883let isCVI = 1;
31884let isPseudo = 1;
31885let isCodeGenOnly = 1;
31886let DecoderNamespace = "EXT_mmvec";
31887}
31888def V6_vavgbrnd : HInst<
31889(outs HvxVR:$Vd32),
31890(ins HvxVR:$Vu32, HvxVR:$Vv32),
31891"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
31892tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31893let Inst{7-5} = 0b101;
31894let Inst{13-13} = 0b1;
31895let Inst{31-21} = 0b00011111000;
31896let hasNewValue = 1;
31897let opNewValue = 0;
31898let isCVI = 1;
31899let DecoderNamespace = "EXT_mmvec";
31900}
31901def V6_vavgbrnd_alt : HInst<
31902(outs HvxVR:$Vd32),
31903(ins HvxVR:$Vu32, HvxVR:$Vv32),
31904"$Vd32 = vavgb($Vu32,$Vv32):rnd",
31905PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31906let hasNewValue = 1;
31907let opNewValue = 0;
31908let isCVI = 1;
31909let isPseudo = 1;
31910let isCodeGenOnly = 1;
31911let DecoderNamespace = "EXT_mmvec";
31912}
31913def V6_vavgh : HInst<
31914(outs HvxVR:$Vd32),
31915(ins HvxVR:$Vu32, HvxVR:$Vv32),
31916"$Vd32.h = vavg($Vu32.h,$Vv32.h)",
31917tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31918let Inst{7-5} = 0b110;
31919let Inst{13-13} = 0b0;
31920let Inst{31-21} = 0b00011100110;
31921let hasNewValue = 1;
31922let opNewValue = 0;
31923let isCVI = 1;
31924let DecoderNamespace = "EXT_mmvec";
31925}
31926def V6_vavgh_alt : HInst<
31927(outs HvxVR:$Vd32),
31928(ins HvxVR:$Vu32, HvxVR:$Vv32),
31929"$Vd32 = vavgh($Vu32,$Vv32)",
31930PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31931let hasNewValue = 1;
31932let opNewValue = 0;
31933let isCVI = 1;
31934let isPseudo = 1;
31935let isCodeGenOnly = 1;
31936let DecoderNamespace = "EXT_mmvec";
31937}
31938def V6_vavghrnd : HInst<
31939(outs HvxVR:$Vd32),
31940(ins HvxVR:$Vu32, HvxVR:$Vv32),
31941"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
31942tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31943let Inst{7-5} = 0b101;
31944let Inst{13-13} = 0b0;
31945let Inst{31-21} = 0b00011100111;
31946let hasNewValue = 1;
31947let opNewValue = 0;
31948let isCVI = 1;
31949let DecoderNamespace = "EXT_mmvec";
31950}
31951def V6_vavghrnd_alt : HInst<
31952(outs HvxVR:$Vd32),
31953(ins HvxVR:$Vu32, HvxVR:$Vv32),
31954"$Vd32 = vavgh($Vu32,$Vv32):rnd",
31955PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31956let hasNewValue = 1;
31957let opNewValue = 0;
31958let isCVI = 1;
31959let isPseudo = 1;
31960let isCodeGenOnly = 1;
31961let DecoderNamespace = "EXT_mmvec";
31962}
31963def V6_vavgub : HInst<
31964(outs HvxVR:$Vd32),
31965(ins HvxVR:$Vu32, HvxVR:$Vv32),
31966"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
31967tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31968let Inst{7-5} = 0b100;
31969let Inst{13-13} = 0b0;
31970let Inst{31-21} = 0b00011100110;
31971let hasNewValue = 1;
31972let opNewValue = 0;
31973let isCVI = 1;
31974let DecoderNamespace = "EXT_mmvec";
31975}
31976def V6_vavgub_alt : HInst<
31977(outs HvxVR:$Vd32),
31978(ins HvxVR:$Vu32, HvxVR:$Vv32),
31979"$Vd32 = vavgub($Vu32,$Vv32)",
31980PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31981let hasNewValue = 1;
31982let opNewValue = 0;
31983let isCVI = 1;
31984let isPseudo = 1;
31985let isCodeGenOnly = 1;
31986let DecoderNamespace = "EXT_mmvec";
31987}
31988def V6_vavgubrnd : HInst<
31989(outs HvxVR:$Vd32),
31990(ins HvxVR:$Vu32, HvxVR:$Vv32),
31991"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
31992tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31993let Inst{7-5} = 0b011;
31994let Inst{13-13} = 0b0;
31995let Inst{31-21} = 0b00011100111;
31996let hasNewValue = 1;
31997let opNewValue = 0;
31998let isCVI = 1;
31999let DecoderNamespace = "EXT_mmvec";
32000}
32001def V6_vavgubrnd_alt : HInst<
32002(outs HvxVR:$Vd32),
32003(ins HvxVR:$Vu32, HvxVR:$Vv32),
32004"$Vd32 = vavgub($Vu32,$Vv32):rnd",
32005PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32006let hasNewValue = 1;
32007let opNewValue = 0;
32008let isCVI = 1;
32009let isPseudo = 1;
32010let isCodeGenOnly = 1;
32011let DecoderNamespace = "EXT_mmvec";
32012}
32013def V6_vavguh : HInst<
32014(outs HvxVR:$Vd32),
32015(ins HvxVR:$Vu32, HvxVR:$Vv32),
32016"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
32017tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32018let Inst{7-5} = 0b101;
32019let Inst{13-13} = 0b0;
32020let Inst{31-21} = 0b00011100110;
32021let hasNewValue = 1;
32022let opNewValue = 0;
32023let isCVI = 1;
32024let DecoderNamespace = "EXT_mmvec";
32025}
32026def V6_vavguh_alt : HInst<
32027(outs HvxVR:$Vd32),
32028(ins HvxVR:$Vu32, HvxVR:$Vv32),
32029"$Vd32 = vavguh($Vu32,$Vv32)",
32030PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32031let hasNewValue = 1;
32032let opNewValue = 0;
32033let isCVI = 1;
32034let isPseudo = 1;
32035let isCodeGenOnly = 1;
32036let DecoderNamespace = "EXT_mmvec";
32037}
32038def V6_vavguhrnd : HInst<
32039(outs HvxVR:$Vd32),
32040(ins HvxVR:$Vu32, HvxVR:$Vv32),
32041"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
32042tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32043let Inst{7-5} = 0b100;
32044let Inst{13-13} = 0b0;
32045let Inst{31-21} = 0b00011100111;
32046let hasNewValue = 1;
32047let opNewValue = 0;
32048let isCVI = 1;
32049let DecoderNamespace = "EXT_mmvec";
32050}
32051def V6_vavguhrnd_alt : HInst<
32052(outs HvxVR:$Vd32),
32053(ins HvxVR:$Vu32, HvxVR:$Vv32),
32054"$Vd32 = vavguh($Vu32,$Vv32):rnd",
32055PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32056let hasNewValue = 1;
32057let opNewValue = 0;
32058let isCVI = 1;
32059let isPseudo = 1;
32060let isCodeGenOnly = 1;
32061let DecoderNamespace = "EXT_mmvec";
32062}
32063def V6_vavguw : HInst<
32064(outs HvxVR:$Vd32),
32065(ins HvxVR:$Vu32, HvxVR:$Vv32),
32066"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
32067tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32068let Inst{7-5} = 0b010;
32069let Inst{13-13} = 0b1;
32070let Inst{31-21} = 0b00011111000;
32071let hasNewValue = 1;
32072let opNewValue = 0;
32073let isCVI = 1;
32074let DecoderNamespace = "EXT_mmvec";
32075}
32076def V6_vavguw_alt : HInst<
32077(outs HvxVR:$Vd32),
32078(ins HvxVR:$Vu32, HvxVR:$Vv32),
32079"$Vd32 = vavguw($Vu32,$Vv32)",
32080PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32081let hasNewValue = 1;
32082let opNewValue = 0;
32083let isCVI = 1;
32084let isPseudo = 1;
32085let isCodeGenOnly = 1;
32086let DecoderNamespace = "EXT_mmvec";
32087}
32088def V6_vavguwrnd : HInst<
32089(outs HvxVR:$Vd32),
32090(ins HvxVR:$Vu32, HvxVR:$Vv32),
32091"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
32092tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32093let Inst{7-5} = 0b011;
32094let Inst{13-13} = 0b1;
32095let Inst{31-21} = 0b00011111000;
32096let hasNewValue = 1;
32097let opNewValue = 0;
32098let isCVI = 1;
32099let DecoderNamespace = "EXT_mmvec";
32100}
32101def V6_vavguwrnd_alt : HInst<
32102(outs HvxVR:$Vd32),
32103(ins HvxVR:$Vu32, HvxVR:$Vv32),
32104"$Vd32 = vavguw($Vu32,$Vv32):rnd",
32105PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32106let hasNewValue = 1;
32107let opNewValue = 0;
32108let isCVI = 1;
32109let isPseudo = 1;
32110let isCodeGenOnly = 1;
32111let DecoderNamespace = "EXT_mmvec";
32112}
32113def V6_vavgw : HInst<
32114(outs HvxVR:$Vd32),
32115(ins HvxVR:$Vu32, HvxVR:$Vv32),
32116"$Vd32.w = vavg($Vu32.w,$Vv32.w)",
32117tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32118let Inst{7-5} = 0b111;
32119let Inst{13-13} = 0b0;
32120let Inst{31-21} = 0b00011100110;
32121let hasNewValue = 1;
32122let opNewValue = 0;
32123let isCVI = 1;
32124let DecoderNamespace = "EXT_mmvec";
32125}
32126def V6_vavgw_alt : HInst<
32127(outs HvxVR:$Vd32),
32128(ins HvxVR:$Vu32, HvxVR:$Vv32),
32129"$Vd32 = vavgw($Vu32,$Vv32)",
32130PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32131let hasNewValue = 1;
32132let opNewValue = 0;
32133let isCVI = 1;
32134let isPseudo = 1;
32135let isCodeGenOnly = 1;
32136let DecoderNamespace = "EXT_mmvec";
32137}
32138def V6_vavgwrnd : HInst<
32139(outs HvxVR:$Vd32),
32140(ins HvxVR:$Vu32, HvxVR:$Vv32),
32141"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
32142tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32143let Inst{7-5} = 0b110;
32144let Inst{13-13} = 0b0;
32145let Inst{31-21} = 0b00011100111;
32146let hasNewValue = 1;
32147let opNewValue = 0;
32148let isCVI = 1;
32149let DecoderNamespace = "EXT_mmvec";
32150}
32151def V6_vavgwrnd_alt : HInst<
32152(outs HvxVR:$Vd32),
32153(ins HvxVR:$Vu32, HvxVR:$Vv32),
32154"$Vd32 = vavgw($Vu32,$Vv32):rnd",
32155PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32156let hasNewValue = 1;
32157let opNewValue = 0;
32158let isCVI = 1;
32159let isPseudo = 1;
32160let isCodeGenOnly = 1;
32161let DecoderNamespace = "EXT_mmvec";
32162}
32163def V6_vccombine : HInst<
32164(outs HvxWR:$Vdd32),
32165(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
32166"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
32167tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
32168let Inst{7-7} = 0b0;
32169let Inst{13-13} = 0b0;
32170let Inst{31-21} = 0b00011010011;
32171let isPredicated = 1;
32172let hasNewValue = 1;
32173let opNewValue = 0;
32174let isCVI = 1;
32175let DecoderNamespace = "EXT_mmvec";
32176}
32177def V6_vcl0h : HInst<
32178(outs HvxVR:$Vd32),
32179(ins HvxVR:$Vu32),
32180"$Vd32.uh = vcl0($Vu32.uh)",
32181tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
32182let Inst{7-5} = 0b111;
32183let Inst{13-13} = 0b0;
32184let Inst{31-16} = 0b0001111000000010;
32185let hasNewValue = 1;
32186let opNewValue = 0;
32187let isCVI = 1;
32188let DecoderNamespace = "EXT_mmvec";
32189}
32190def V6_vcl0h_alt : HInst<
32191(outs HvxVR:$Vd32),
32192(ins HvxVR:$Vu32),
32193"$Vd32 = vcl0h($Vu32)",
32194PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32195let hasNewValue = 1;
32196let opNewValue = 0;
32197let isCVI = 1;
32198let isPseudo = 1;
32199let isCodeGenOnly = 1;
32200let DecoderNamespace = "EXT_mmvec";
32201}
32202def V6_vcl0w : HInst<
32203(outs HvxVR:$Vd32),
32204(ins HvxVR:$Vu32),
32205"$Vd32.uw = vcl0($Vu32.uw)",
32206tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
32207let Inst{7-5} = 0b101;
32208let Inst{13-13} = 0b0;
32209let Inst{31-16} = 0b0001111000000010;
32210let hasNewValue = 1;
32211let opNewValue = 0;
32212let isCVI = 1;
32213let DecoderNamespace = "EXT_mmvec";
32214}
32215def V6_vcl0w_alt : HInst<
32216(outs HvxVR:$Vd32),
32217(ins HvxVR:$Vu32),
32218"$Vd32 = vcl0w($Vu32)",
32219PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32220let hasNewValue = 1;
32221let opNewValue = 0;
32222let isCVI = 1;
32223let isPseudo = 1;
32224let isCodeGenOnly = 1;
32225let DecoderNamespace = "EXT_mmvec";
32226}
32227def V6_vcmov : HInst<
32228(outs HvxVR:$Vd32),
32229(ins PredRegs:$Ps4, HvxVR:$Vu32),
32230"if ($Ps4) $Vd32 = $Vu32",
32231tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
32232let Inst{7-7} = 0b0;
32233let Inst{13-13} = 0b0;
32234let Inst{31-16} = 0b0001101000000000;
32235let isPredicated = 1;
32236let hasNewValue = 1;
32237let opNewValue = 0;
32238let isCVI = 1;
32239let DecoderNamespace = "EXT_mmvec";
32240}
32241def V6_vcombine : HInst<
32242(outs HvxWR:$Vdd32),
32243(ins HvxVR:$Vu32, HvxVR:$Vv32),
32244"$Vdd32 = vcombine($Vu32,$Vv32)",
32245tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
32246let Inst{7-5} = 0b111;
32247let Inst{13-13} = 0b0;
32248let Inst{31-21} = 0b00011111010;
32249let hasNewValue = 1;
32250let opNewValue = 0;
32251let isCVI = 1;
32252let isRegSequence = 1;
32253let DecoderNamespace = "EXT_mmvec";
32254}
32255def V6_vcombine_tmp : HInst<
32256(outs HvxWR:$Vdd32),
32257(ins HvxVR:$Vu32, HvxVR:$Vv32),
32258"$Vdd32.tmp = vcombine($Vu32,$Vv32)",
32259tc_aa047364, TypeCVI_VX>, Enc_71bb9b, Requires<[UseHVXV69]> {
32260let Inst{7-5} = 0b111;
32261let Inst{13-13} = 0b0;
32262let Inst{31-21} = 0b00011110101;
32263let hasNewValue = 1;
32264let opNewValue = 0;
32265let isCVI = 1;
32266let hasHvxTmp = 1;
32267let DecoderNamespace = "EXT_mmvec";
32268}
32269def V6_vconv_hf_qf16 : HInst<
32270(outs HvxVR:$Vd32),
32271(ins HvxVR:$Vu32),
32272"$Vd32.hf = $Vu32.qf16",
32273tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV68,UseHVXQFloat]> {
32274let Inst{7-5} = 0b011;
32275let Inst{13-13} = 0b1;
32276let Inst{31-16} = 0b0001111000000100;
32277let hasNewValue = 1;
32278let opNewValue = 0;
32279let isCVI = 1;
32280let DecoderNamespace = "EXT_mmvec";
32281}
32282def V6_vconv_hf_qf32 : HInst<
32283(outs HvxVR:$Vd32),
32284(ins HvxWR:$Vuu32),
32285"$Vd32.hf = $Vuu32.qf32",
32286tc_51d0ecc3, TypeCVI_VS>, Enc_a33d04, Requires<[UseHVXV68,UseHVXQFloat]> {
32287let Inst{7-5} = 0b110;
32288let Inst{13-13} = 0b1;
32289let Inst{31-16} = 0b0001111000000100;
32290let hasNewValue = 1;
32291let opNewValue = 0;
32292let isCVI = 1;
32293let DecoderNamespace = "EXT_mmvec";
32294}
32295def V6_vconv_sf_qf32 : HInst<
32296(outs HvxVR:$Vd32),
32297(ins HvxVR:$Vu32),
32298"$Vd32.sf = $Vu32.qf32",
32299tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV68,UseHVXQFloat]> {
32300let Inst{7-5} = 0b000;
32301let Inst{13-13} = 0b1;
32302let Inst{31-16} = 0b0001111000000100;
32303let hasNewValue = 1;
32304let opNewValue = 0;
32305let isCVI = 1;
32306let DecoderNamespace = "EXT_mmvec";
32307}
32308def V6_vcvt_b_hf : HInst<
32309(outs HvxVR:$Vd32),
32310(ins HvxVR:$Vu32, HvxVR:$Vv32),
32311"$Vd32.b = vcvt($Vu32.hf,$Vv32.hf)",
32312tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32313let Inst{7-5} = 0b110;
32314let Inst{13-13} = 0b1;
32315let Inst{31-21} = 0b00011111110;
32316let hasNewValue = 1;
32317let opNewValue = 0;
32318let isCVI = 1;
32319let DecoderNamespace = "EXT_mmvec";
32320}
32321def V6_vcvt_h_hf : HInst<
32322(outs HvxVR:$Vd32),
32323(ins HvxVR:$Vu32),
32324"$Vd32.h = vcvt($Vu32.hf)",
32325tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32326let Inst{7-5} = 0b000;
32327let Inst{13-13} = 0b1;
32328let Inst{31-16} = 0b0001111000000110;
32329let hasNewValue = 1;
32330let opNewValue = 0;
32331let isCVI = 1;
32332let DecoderNamespace = "EXT_mmvec";
32333}
32334def V6_vcvt_hf_b : HInst<
32335(outs HvxWR:$Vdd32),
32336(ins HvxVR:$Vu32),
32337"$Vdd32.hf = vcvt($Vu32.b)",
32338tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32339let Inst{7-5} = 0b010;
32340let Inst{13-13} = 0b1;
32341let Inst{31-16} = 0b0001111000000100;
32342let hasNewValue = 1;
32343let opNewValue = 0;
32344let isCVI = 1;
32345let DecoderNamespace = "EXT_mmvec";
32346}
32347def V6_vcvt_hf_h : HInst<
32348(outs HvxVR:$Vd32),
32349(ins HvxVR:$Vu32),
32350"$Vd32.hf = vcvt($Vu32.h)",
32351tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32352let Inst{7-5} = 0b111;
32353let Inst{13-13} = 0b1;
32354let Inst{31-16} = 0b0001111000000100;
32355let hasNewValue = 1;
32356let opNewValue = 0;
32357let isCVI = 1;
32358let DecoderNamespace = "EXT_mmvec";
32359}
32360def V6_vcvt_hf_sf : HInst<
32361(outs HvxVR:$Vd32),
32362(ins HvxVR:$Vu32, HvxVR:$Vv32),
32363"$Vd32.hf = vcvt($Vu32.sf,$Vv32.sf)",
32364tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32365let Inst{7-5} = 0b001;
32366let Inst{13-13} = 0b1;
32367let Inst{31-21} = 0b00011111011;
32368let hasNewValue = 1;
32369let opNewValue = 0;
32370let isCVI = 1;
32371let DecoderNamespace = "EXT_mmvec";
32372}
32373def V6_vcvt_hf_ub : HInst<
32374(outs HvxWR:$Vdd32),
32375(ins HvxVR:$Vu32),
32376"$Vdd32.hf = vcvt($Vu32.ub)",
32377tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32378let Inst{7-5} = 0b001;
32379let Inst{13-13} = 0b1;
32380let Inst{31-16} = 0b0001111000000100;
32381let hasNewValue = 1;
32382let opNewValue = 0;
32383let isCVI = 1;
32384let DecoderNamespace = "EXT_mmvec";
32385}
32386def V6_vcvt_hf_uh : HInst<
32387(outs HvxVR:$Vd32),
32388(ins HvxVR:$Vu32),
32389"$Vd32.hf = vcvt($Vu32.uh)",
32390tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32391let Inst{7-5} = 0b101;
32392let Inst{13-13} = 0b1;
32393let Inst{31-16} = 0b0001111000000100;
32394let hasNewValue = 1;
32395let opNewValue = 0;
32396let isCVI = 1;
32397let DecoderNamespace = "EXT_mmvec";
32398}
32399def V6_vcvt_sf_hf : HInst<
32400(outs HvxWR:$Vdd32),
32401(ins HvxVR:$Vu32),
32402"$Vdd32.sf = vcvt($Vu32.hf)",
32403tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32404let Inst{7-5} = 0b100;
32405let Inst{13-13} = 0b1;
32406let Inst{31-16} = 0b0001111000000100;
32407let hasNewValue = 1;
32408let opNewValue = 0;
32409let isCVI = 1;
32410let DecoderNamespace = "EXT_mmvec";
32411}
32412def V6_vcvt_ub_hf : HInst<
32413(outs HvxVR:$Vd32),
32414(ins HvxVR:$Vu32, HvxVR:$Vv32),
32415"$Vd32.ub = vcvt($Vu32.hf,$Vv32.hf)",
32416tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32417let Inst{7-5} = 0b101;
32418let Inst{13-13} = 0b1;
32419let Inst{31-21} = 0b00011111110;
32420let hasNewValue = 1;
32421let opNewValue = 0;
32422let isCVI = 1;
32423let DecoderNamespace = "EXT_mmvec";
32424}
32425def V6_vcvt_uh_hf : HInst<
32426(outs HvxVR:$Vd32),
32427(ins HvxVR:$Vu32),
32428"$Vd32.uh = vcvt($Vu32.hf)",
32429tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32430let Inst{7-5} = 0b000;
32431let Inst{13-13} = 0b1;
32432let Inst{31-16} = 0b0001111000000101;
32433let hasNewValue = 1;
32434let opNewValue = 0;
32435let isCVI = 1;
32436let DecoderNamespace = "EXT_mmvec";
32437}
32438def V6_vd0 : HInst<
32439(outs HvxVR:$Vd32),
32440(ins),
32441"$Vd32 = #0",
32442CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
32443let hasNewValue = 1;
32444let opNewValue = 0;
32445let isCVI = 1;
32446let isPseudo = 1;
32447let isCodeGenOnly = 1;
32448let DecoderNamespace = "EXT_mmvec";
32449}
32450def V6_vdd0 : HInst<
32451(outs HvxWR:$Vdd32),
32452(ins),
32453"$Vdd32 = #0",
32454tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> {
32455let hasNewValue = 1;
32456let opNewValue = 0;
32457let isCVI = 1;
32458let isPseudo = 1;
32459let isCodeGenOnly = 1;
32460let DecoderNamespace = "EXT_mmvec";
32461}
32462def V6_vdeal : HInst<
32463(outs HvxVR:$Vy32, HvxVR:$Vx32),
32464(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
32465"vdeal($Vy32,$Vx32,$Rt32)",
32466tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
32467let Inst{7-5} = 0b010;
32468let Inst{13-13} = 0b1;
32469let Inst{31-21} = 0b00011001111;
32470let hasNewValue = 1;
32471let opNewValue = 0;
32472let hasNewValue2 = 1;
32473let opNewValue2 = 1;
32474let isCVI = 1;
32475let DecoderNamespace = "EXT_mmvec";
32476let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
32477}
32478def V6_vdealb : HInst<
32479(outs HvxVR:$Vd32),
32480(ins HvxVR:$Vu32),
32481"$Vd32.b = vdeal($Vu32.b)",
32482tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32483let Inst{7-5} = 0b111;
32484let Inst{13-13} = 0b0;
32485let Inst{31-16} = 0b0001111000000000;
32486let hasNewValue = 1;
32487let opNewValue = 0;
32488let isCVI = 1;
32489let DecoderNamespace = "EXT_mmvec";
32490}
32491def V6_vdealb4w : HInst<
32492(outs HvxVR:$Vd32),
32493(ins HvxVR:$Vu32, HvxVR:$Vv32),
32494"$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
32495tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32496let Inst{7-5} = 0b111;
32497let Inst{13-13} = 0b0;
32498let Inst{31-21} = 0b00011111001;
32499let hasNewValue = 1;
32500let opNewValue = 0;
32501let isCVI = 1;
32502let DecoderNamespace = "EXT_mmvec";
32503}
32504def V6_vdealb4w_alt : HInst<
32505(outs HvxVR:$Vd32),
32506(ins HvxVR:$Vu32, HvxVR:$Vv32),
32507"$Vd32 = vdealb4w($Vu32,$Vv32)",
32508PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32509let hasNewValue = 1;
32510let opNewValue = 0;
32511let isCVI = 1;
32512let isPseudo = 1;
32513let isCodeGenOnly = 1;
32514let DecoderNamespace = "EXT_mmvec";
32515}
32516def V6_vdealb_alt : HInst<
32517(outs HvxVR:$Vd32),
32518(ins HvxVR:$Vu32),
32519"$Vd32 = vdealb($Vu32)",
32520PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32521let hasNewValue = 1;
32522let opNewValue = 0;
32523let isCVI = 1;
32524let isPseudo = 1;
32525let isCodeGenOnly = 1;
32526let DecoderNamespace = "EXT_mmvec";
32527}
32528def V6_vdealh : HInst<
32529(outs HvxVR:$Vd32),
32530(ins HvxVR:$Vu32),
32531"$Vd32.h = vdeal($Vu32.h)",
32532tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32533let Inst{7-5} = 0b110;
32534let Inst{13-13} = 0b0;
32535let Inst{31-16} = 0b0001111000000000;
32536let hasNewValue = 1;
32537let opNewValue = 0;
32538let isCVI = 1;
32539let DecoderNamespace = "EXT_mmvec";
32540}
32541def V6_vdealh_alt : HInst<
32542(outs HvxVR:$Vd32),
32543(ins HvxVR:$Vu32),
32544"$Vd32 = vdealh($Vu32)",
32545PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32546let hasNewValue = 1;
32547let opNewValue = 0;
32548let isCVI = 1;
32549let isPseudo = 1;
32550let isCodeGenOnly = 1;
32551let DecoderNamespace = "EXT_mmvec";
32552}
32553def V6_vdealvdd : HInst<
32554(outs HvxWR:$Vdd32),
32555(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32556"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
32557tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
32558let Inst{7-5} = 0b100;
32559let Inst{13-13} = 0b1;
32560let Inst{31-24} = 0b00011011;
32561let hasNewValue = 1;
32562let opNewValue = 0;
32563let isCVI = 1;
32564let DecoderNamespace = "EXT_mmvec";
32565}
32566def V6_vdelta : HInst<
32567(outs HvxVR:$Vd32),
32568(ins HvxVR:$Vu32, HvxVR:$Vv32),
32569"$Vd32 = vdelta($Vu32,$Vv32)",
32570tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32571let Inst{7-5} = 0b001;
32572let Inst{13-13} = 0b0;
32573let Inst{31-21} = 0b00011111001;
32574let hasNewValue = 1;
32575let opNewValue = 0;
32576let isCVI = 1;
32577let DecoderNamespace = "EXT_mmvec";
32578}
32579def V6_vdmpy_sf_hf : HInst<
32580(outs HvxVR:$Vd32),
32581(ins HvxVR:$Vu32, HvxVR:$Vv32),
32582"$Vd32.sf = vdmpy($Vu32.hf,$Vv32.hf)",
32583tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32584let Inst{7-5} = 0b110;
32585let Inst{13-13} = 0b1;
32586let Inst{31-21} = 0b00011111101;
32587let hasNewValue = 1;
32588let opNewValue = 0;
32589let isCVI = 1;
32590let DecoderNamespace = "EXT_mmvec";
32591}
32592def V6_vdmpy_sf_hf_acc : HInst<
32593(outs HvxVR:$Vx32),
32594(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
32595"$Vx32.sf += vdmpy($Vu32.hf,$Vv32.hf)",
32596tc_a19b9305, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32597let Inst{7-5} = 0b011;
32598let Inst{13-13} = 0b1;
32599let Inst{31-21} = 0b00011100010;
32600let hasNewValue = 1;
32601let opNewValue = 0;
32602let isAccumulator = 1;
32603let isCVI = 1;
32604let DecoderNamespace = "EXT_mmvec";
32605let Constraints = "$Vx32 = $Vx32in";
32606}
32607def V6_vdmpybus : HInst<
32608(outs HvxVR:$Vd32),
32609(ins HvxVR:$Vu32, IntRegs:$Rt32),
32610"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
32611tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32612let Inst{7-5} = 0b110;
32613let Inst{13-13} = 0b0;
32614let Inst{31-21} = 0b00011001000;
32615let hasNewValue = 1;
32616let opNewValue = 0;
32617let isCVI = 1;
32618let DecoderNamespace = "EXT_mmvec";
32619}
32620def V6_vdmpybus_acc : HInst<
32621(outs HvxVR:$Vx32),
32622(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32623"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
32624tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32625let Inst{7-5} = 0b110;
32626let Inst{13-13} = 0b1;
32627let Inst{31-21} = 0b00011001000;
32628let hasNewValue = 1;
32629let opNewValue = 0;
32630let isAccumulator = 1;
32631let isCVI = 1;
32632let DecoderNamespace = "EXT_mmvec";
32633let Constraints = "$Vx32 = $Vx32in";
32634}
32635def V6_vdmpybus_acc_alt : HInst<
32636(outs HvxVR:$Vx32),
32637(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32638"$Vx32 += vdmpybus($Vu32,$Rt32)",
32639PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32640let hasNewValue = 1;
32641let opNewValue = 0;
32642let isAccumulator = 1;
32643let isCVI = 1;
32644let isPseudo = 1;
32645let isCodeGenOnly = 1;
32646let DecoderNamespace = "EXT_mmvec";
32647let Constraints = "$Vx32 = $Vx32in";
32648}
32649def V6_vdmpybus_alt : HInst<
32650(outs HvxVR:$Vd32),
32651(ins HvxVR:$Vu32, IntRegs:$Rt32),
32652"$Vd32 = vdmpybus($Vu32,$Rt32)",
32653PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32654let hasNewValue = 1;
32655let opNewValue = 0;
32656let isCVI = 1;
32657let isPseudo = 1;
32658let isCodeGenOnly = 1;
32659let DecoderNamespace = "EXT_mmvec";
32660}
32661def V6_vdmpybus_dv : HInst<
32662(outs HvxWR:$Vdd32),
32663(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32664"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
32665tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32666let Inst{7-5} = 0b111;
32667let Inst{13-13} = 0b0;
32668let Inst{31-21} = 0b00011001000;
32669let hasNewValue = 1;
32670let opNewValue = 0;
32671let isCVI = 1;
32672let DecoderNamespace = "EXT_mmvec";
32673}
32674def V6_vdmpybus_dv_acc : HInst<
32675(outs HvxWR:$Vxx32),
32676(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32677"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
32678tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32679let Inst{7-5} = 0b111;
32680let Inst{13-13} = 0b1;
32681let Inst{31-21} = 0b00011001000;
32682let hasNewValue = 1;
32683let opNewValue = 0;
32684let isAccumulator = 1;
32685let isCVI = 1;
32686let DecoderNamespace = "EXT_mmvec";
32687let Constraints = "$Vxx32 = $Vxx32in";
32688}
32689def V6_vdmpybus_dv_acc_alt : HInst<
32690(outs HvxWR:$Vxx32),
32691(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32692"$Vxx32 += vdmpybus($Vuu32,$Rt32)",
32693PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32694let hasNewValue = 1;
32695let opNewValue = 0;
32696let isAccumulator = 1;
32697let isCVI = 1;
32698let isPseudo = 1;
32699let isCodeGenOnly = 1;
32700let DecoderNamespace = "EXT_mmvec";
32701let Constraints = "$Vxx32 = $Vxx32in";
32702}
32703def V6_vdmpybus_dv_alt : HInst<
32704(outs HvxWR:$Vdd32),
32705(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32706"$Vdd32 = vdmpybus($Vuu32,$Rt32)",
32707PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32708let hasNewValue = 1;
32709let opNewValue = 0;
32710let isCVI = 1;
32711let isPseudo = 1;
32712let isCodeGenOnly = 1;
32713let DecoderNamespace = "EXT_mmvec";
32714}
32715def V6_vdmpyhb : HInst<
32716(outs HvxVR:$Vd32),
32717(ins HvxVR:$Vu32, IntRegs:$Rt32),
32718"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
32719tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32720let Inst{7-5} = 0b010;
32721let Inst{13-13} = 0b0;
32722let Inst{31-21} = 0b00011001000;
32723let hasNewValue = 1;
32724let opNewValue = 0;
32725let isCVI = 1;
32726let DecoderNamespace = "EXT_mmvec";
32727}
32728def V6_vdmpyhb_acc : HInst<
32729(outs HvxVR:$Vx32),
32730(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32731"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
32732tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32733let Inst{7-5} = 0b011;
32734let Inst{13-13} = 0b1;
32735let Inst{31-21} = 0b00011001000;
32736let hasNewValue = 1;
32737let opNewValue = 0;
32738let isAccumulator = 1;
32739let isCVI = 1;
32740let DecoderNamespace = "EXT_mmvec";
32741let Constraints = "$Vx32 = $Vx32in";
32742}
32743def V6_vdmpyhb_acc_alt : HInst<
32744(outs HvxVR:$Vx32),
32745(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32746"$Vx32 += vdmpyhb($Vu32,$Rt32)",
32747PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32748let hasNewValue = 1;
32749let opNewValue = 0;
32750let isAccumulator = 1;
32751let isCVI = 1;
32752let isPseudo = 1;
32753let isCodeGenOnly = 1;
32754let DecoderNamespace = "EXT_mmvec";
32755let Constraints = "$Vx32 = $Vx32in";
32756}
32757def V6_vdmpyhb_alt : HInst<
32758(outs HvxVR:$Vd32),
32759(ins HvxVR:$Vu32, IntRegs:$Rt32),
32760"$Vd32 = vdmpyhb($Vu32,$Rt32)",
32761PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32762let hasNewValue = 1;
32763let opNewValue = 0;
32764let isCVI = 1;
32765let isPseudo = 1;
32766let isCodeGenOnly = 1;
32767let DecoderNamespace = "EXT_mmvec";
32768}
32769def V6_vdmpyhb_dv : HInst<
32770(outs HvxWR:$Vdd32),
32771(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32772"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
32773tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32774let Inst{7-5} = 0b100;
32775let Inst{13-13} = 0b0;
32776let Inst{31-21} = 0b00011001001;
32777let hasNewValue = 1;
32778let opNewValue = 0;
32779let isCVI = 1;
32780let DecoderNamespace = "EXT_mmvec";
32781}
32782def V6_vdmpyhb_dv_acc : HInst<
32783(outs HvxWR:$Vxx32),
32784(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32785"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
32786tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32787let Inst{7-5} = 0b100;
32788let Inst{13-13} = 0b1;
32789let Inst{31-21} = 0b00011001001;
32790let hasNewValue = 1;
32791let opNewValue = 0;
32792let isAccumulator = 1;
32793let isCVI = 1;
32794let DecoderNamespace = "EXT_mmvec";
32795let Constraints = "$Vxx32 = $Vxx32in";
32796}
32797def V6_vdmpyhb_dv_acc_alt : HInst<
32798(outs HvxWR:$Vxx32),
32799(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32800"$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
32801PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32802let hasNewValue = 1;
32803let opNewValue = 0;
32804let isAccumulator = 1;
32805let isCVI = 1;
32806let isPseudo = 1;
32807let isCodeGenOnly = 1;
32808let DecoderNamespace = "EXT_mmvec";
32809let Constraints = "$Vxx32 = $Vxx32in";
32810}
32811def V6_vdmpyhb_dv_alt : HInst<
32812(outs HvxWR:$Vdd32),
32813(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32814"$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
32815PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32816let hasNewValue = 1;
32817let opNewValue = 0;
32818let isCVI = 1;
32819let isPseudo = 1;
32820let isCodeGenOnly = 1;
32821let DecoderNamespace = "EXT_mmvec";
32822}
32823def V6_vdmpyhisat : HInst<
32824(outs HvxVR:$Vd32),
32825(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32826"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
32827tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
32828let Inst{7-5} = 0b011;
32829let Inst{13-13} = 0b0;
32830let Inst{31-21} = 0b00011001001;
32831let hasNewValue = 1;
32832let opNewValue = 0;
32833let isCVI = 1;
32834let DecoderNamespace = "EXT_mmvec";
32835}
32836def V6_vdmpyhisat_acc : HInst<
32837(outs HvxVR:$Vx32),
32838(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32839"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
32840tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
32841let Inst{7-5} = 0b010;
32842let Inst{13-13} = 0b1;
32843let Inst{31-21} = 0b00011001001;
32844let hasNewValue = 1;
32845let opNewValue = 0;
32846let isAccumulator = 1;
32847let isCVI = 1;
32848let DecoderNamespace = "EXT_mmvec";
32849let Constraints = "$Vx32 = $Vx32in";
32850}
32851def V6_vdmpyhisat_acc_alt : HInst<
32852(outs HvxVR:$Vx32),
32853(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32854"$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
32855PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32856let hasNewValue = 1;
32857let opNewValue = 0;
32858let isAccumulator = 1;
32859let isCVI = 1;
32860let isPseudo = 1;
32861let isCodeGenOnly = 1;
32862let DecoderNamespace = "EXT_mmvec";
32863let Constraints = "$Vx32 = $Vx32in";
32864}
32865def V6_vdmpyhisat_alt : HInst<
32866(outs HvxVR:$Vd32),
32867(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32868"$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
32869PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32870let hasNewValue = 1;
32871let opNewValue = 0;
32872let isCVI = 1;
32873let isPseudo = 1;
32874let isCodeGenOnly = 1;
32875let DecoderNamespace = "EXT_mmvec";
32876}
32877def V6_vdmpyhsat : HInst<
32878(outs HvxVR:$Vd32),
32879(ins HvxVR:$Vu32, IntRegs:$Rt32),
32880"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
32881tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32882let Inst{7-5} = 0b010;
32883let Inst{13-13} = 0b0;
32884let Inst{31-21} = 0b00011001001;
32885let hasNewValue = 1;
32886let opNewValue = 0;
32887let isCVI = 1;
32888let DecoderNamespace = "EXT_mmvec";
32889}
32890def V6_vdmpyhsat_acc : HInst<
32891(outs HvxVR:$Vx32),
32892(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32893"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
32894tc_72e2b393, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32895let Inst{7-5} = 0b011;
32896let Inst{13-13} = 0b1;
32897let Inst{31-21} = 0b00011001001;
32898let hasNewValue = 1;
32899let opNewValue = 0;
32900let isAccumulator = 1;
32901let isCVI = 1;
32902let DecoderNamespace = "EXT_mmvec";
32903let Constraints = "$Vx32 = $Vx32in";
32904}
32905def V6_vdmpyhsat_acc_alt : HInst<
32906(outs HvxVR:$Vx32),
32907(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32908"$Vx32 += vdmpyh($Vu32,$Rt32):sat",
32909PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32910let hasNewValue = 1;
32911let opNewValue = 0;
32912let isAccumulator = 1;
32913let isCVI = 1;
32914let isPseudo = 1;
32915let isCodeGenOnly = 1;
32916let DecoderNamespace = "EXT_mmvec";
32917let Constraints = "$Vx32 = $Vx32in";
32918}
32919def V6_vdmpyhsat_alt : HInst<
32920(outs HvxVR:$Vd32),
32921(ins HvxVR:$Vu32, IntRegs:$Rt32),
32922"$Vd32 = vdmpyh($Vu32,$Rt32):sat",
32923PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32924let hasNewValue = 1;
32925let opNewValue = 0;
32926let isCVI = 1;
32927let isPseudo = 1;
32928let isCodeGenOnly = 1;
32929let DecoderNamespace = "EXT_mmvec";
32930}
32931def V6_vdmpyhsuisat : HInst<
32932(outs HvxVR:$Vd32),
32933(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32934"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
32935tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
32936let Inst{7-5} = 0b001;
32937let Inst{13-13} = 0b0;
32938let Inst{31-21} = 0b00011001001;
32939let hasNewValue = 1;
32940let opNewValue = 0;
32941let isCVI = 1;
32942let DecoderNamespace = "EXT_mmvec";
32943}
32944def V6_vdmpyhsuisat_acc : HInst<
32945(outs HvxVR:$Vx32),
32946(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32947"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
32948tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
32949let Inst{7-5} = 0b001;
32950let Inst{13-13} = 0b1;
32951let Inst{31-21} = 0b00011001001;
32952let hasNewValue = 1;
32953let opNewValue = 0;
32954let isAccumulator = 1;
32955let isCVI = 1;
32956let DecoderNamespace = "EXT_mmvec";
32957let Constraints = "$Vx32 = $Vx32in";
32958}
32959def V6_vdmpyhsuisat_acc_alt : HInst<
32960(outs HvxVR:$Vx32),
32961(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32962"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
32963PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32964let hasNewValue = 1;
32965let opNewValue = 0;
32966let isAccumulator = 1;
32967let isCVI = 1;
32968let isPseudo = 1;
32969let isCodeGenOnly = 1;
32970let DecoderNamespace = "EXT_mmvec";
32971let Constraints = "$Vx32 = $Vx32in";
32972}
32973def V6_vdmpyhsuisat_alt : HInst<
32974(outs HvxVR:$Vd32),
32975(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32976"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
32977PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32978let hasNewValue = 1;
32979let opNewValue = 0;
32980let isCVI = 1;
32981let isPseudo = 1;
32982let isCodeGenOnly = 1;
32983let DecoderNamespace = "EXT_mmvec";
32984}
32985def V6_vdmpyhsusat : HInst<
32986(outs HvxVR:$Vd32),
32987(ins HvxVR:$Vu32, IntRegs:$Rt32),
32988"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
32989tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32990let Inst{7-5} = 0b000;
32991let Inst{13-13} = 0b0;
32992let Inst{31-21} = 0b00011001001;
32993let hasNewValue = 1;
32994let opNewValue = 0;
32995let isCVI = 1;
32996let DecoderNamespace = "EXT_mmvec";
32997}
32998def V6_vdmpyhsusat_acc : HInst<
32999(outs HvxVR:$Vx32),
33000(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33001"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
33002tc_72e2b393, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33003let Inst{7-5} = 0b000;
33004let Inst{13-13} = 0b1;
33005let Inst{31-21} = 0b00011001001;
33006let hasNewValue = 1;
33007let opNewValue = 0;
33008let isAccumulator = 1;
33009let isCVI = 1;
33010let DecoderNamespace = "EXT_mmvec";
33011let Constraints = "$Vx32 = $Vx32in";
33012}
33013def V6_vdmpyhsusat_acc_alt : HInst<
33014(outs HvxVR:$Vx32),
33015(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33016"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
33017PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33018let hasNewValue = 1;
33019let opNewValue = 0;
33020let isAccumulator = 1;
33021let isCVI = 1;
33022let isPseudo = 1;
33023let isCodeGenOnly = 1;
33024let DecoderNamespace = "EXT_mmvec";
33025let Constraints = "$Vx32 = $Vx32in";
33026}
33027def V6_vdmpyhsusat_alt : HInst<
33028(outs HvxVR:$Vd32),
33029(ins HvxVR:$Vu32, IntRegs:$Rt32),
33030"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
33031PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33032let hasNewValue = 1;
33033let opNewValue = 0;
33034let isCVI = 1;
33035let isPseudo = 1;
33036let isCodeGenOnly = 1;
33037let DecoderNamespace = "EXT_mmvec";
33038}
33039def V6_vdmpyhvsat : HInst<
33040(outs HvxVR:$Vd32),
33041(ins HvxVR:$Vu32, HvxVR:$Vv32),
33042"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
33043tc_73efe966, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
33044let Inst{7-5} = 0b011;
33045let Inst{13-13} = 0b0;
33046let Inst{31-21} = 0b00011100000;
33047let hasNewValue = 1;
33048let opNewValue = 0;
33049let isCVI = 1;
33050let DecoderNamespace = "EXT_mmvec";
33051}
33052def V6_vdmpyhvsat_acc : HInst<
33053(outs HvxVR:$Vx32),
33054(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33055"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
33056tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33057let Inst{7-5} = 0b011;
33058let Inst{13-13} = 0b1;
33059let Inst{31-21} = 0b00011100000;
33060let hasNewValue = 1;
33061let opNewValue = 0;
33062let isAccumulator = 1;
33063let isCVI = 1;
33064let DecoderNamespace = "EXT_mmvec";
33065let Constraints = "$Vx32 = $Vx32in";
33066}
33067def V6_vdmpyhvsat_acc_alt : HInst<
33068(outs HvxVR:$Vx32),
33069(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33070"$Vx32 += vdmpyh($Vu32,$Vv32):sat",
33071PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33072let hasNewValue = 1;
33073let opNewValue = 0;
33074let isAccumulator = 1;
33075let isCVI = 1;
33076let isPseudo = 1;
33077let isCodeGenOnly = 1;
33078let DecoderNamespace = "EXT_mmvec";
33079let Constraints = "$Vx32 = $Vx32in";
33080}
33081def V6_vdmpyhvsat_alt : HInst<
33082(outs HvxVR:$Vd32),
33083(ins HvxVR:$Vu32, HvxVR:$Vv32),
33084"$Vd32 = vdmpyh($Vu32,$Vv32):sat",
33085PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33086let hasNewValue = 1;
33087let opNewValue = 0;
33088let isCVI = 1;
33089let isPseudo = 1;
33090let isCodeGenOnly = 1;
33091let DecoderNamespace = "EXT_mmvec";
33092}
33093def V6_vdsaduh : HInst<
33094(outs HvxWR:$Vdd32),
33095(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33096"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
33097tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33098let Inst{7-5} = 0b101;
33099let Inst{13-13} = 0b0;
33100let Inst{31-21} = 0b00011001000;
33101let hasNewValue = 1;
33102let opNewValue = 0;
33103let isCVI = 1;
33104let DecoderNamespace = "EXT_mmvec";
33105}
33106def V6_vdsaduh_acc : HInst<
33107(outs HvxWR:$Vxx32),
33108(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33109"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
33110tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33111let Inst{7-5} = 0b000;
33112let Inst{13-13} = 0b1;
33113let Inst{31-21} = 0b00011001011;
33114let hasNewValue = 1;
33115let opNewValue = 0;
33116let isAccumulator = 1;
33117let isCVI = 1;
33118let DecoderNamespace = "EXT_mmvec";
33119let Constraints = "$Vxx32 = $Vxx32in";
33120}
33121def V6_vdsaduh_acc_alt : HInst<
33122(outs HvxWR:$Vxx32),
33123(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33124"$Vxx32 += vdsaduh($Vuu32,$Rt32)",
33125PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33126let hasNewValue = 1;
33127let opNewValue = 0;
33128let isAccumulator = 1;
33129let isCVI = 1;
33130let isPseudo = 1;
33131let isCodeGenOnly = 1;
33132let DecoderNamespace = "EXT_mmvec";
33133let Constraints = "$Vxx32 = $Vxx32in";
33134}
33135def V6_vdsaduh_alt : HInst<
33136(outs HvxWR:$Vdd32),
33137(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33138"$Vdd32 = vdsaduh($Vuu32,$Rt32)",
33139PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33140let hasNewValue = 1;
33141let opNewValue = 0;
33142let isCVI = 1;
33143let isPseudo = 1;
33144let isCodeGenOnly = 1;
33145let DecoderNamespace = "EXT_mmvec";
33146}
33147def V6_veqb : HInst<
33148(outs HvxQR:$Qd4),
33149(ins HvxVR:$Vu32, HvxVR:$Vv32),
33150"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
33151tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33152let Inst{7-2} = 0b000000;
33153let Inst{13-13} = 0b0;
33154let Inst{31-21} = 0b00011111100;
33155let hasNewValue = 1;
33156let opNewValue = 0;
33157let isCVI = 1;
33158let DecoderNamespace = "EXT_mmvec";
33159}
33160def V6_veqb_and : HInst<
33161(outs HvxQR:$Qx4),
33162(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33163"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
33164tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33165let Inst{7-2} = 0b000000;
33166let Inst{13-13} = 0b1;
33167let Inst{31-21} = 0b00011100100;
33168let isCVI = 1;
33169let DecoderNamespace = "EXT_mmvec";
33170let Constraints = "$Qx4 = $Qx4in";
33171}
33172def V6_veqb_or : HInst<
33173(outs HvxQR:$Qx4),
33174(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33175"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
33176tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33177let Inst{7-2} = 0b010000;
33178let Inst{13-13} = 0b1;
33179let Inst{31-21} = 0b00011100100;
33180let isAccumulator = 1;
33181let isCVI = 1;
33182let DecoderNamespace = "EXT_mmvec";
33183let Constraints = "$Qx4 = $Qx4in";
33184}
33185def V6_veqb_xor : HInst<
33186(outs HvxQR:$Qx4),
33187(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33188"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
33189tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33190let Inst{7-2} = 0b100000;
33191let Inst{13-13} = 0b1;
33192let Inst{31-21} = 0b00011100100;
33193let isCVI = 1;
33194let DecoderNamespace = "EXT_mmvec";
33195let Constraints = "$Qx4 = $Qx4in";
33196}
33197def V6_veqh : HInst<
33198(outs HvxQR:$Qd4),
33199(ins HvxVR:$Vu32, HvxVR:$Vv32),
33200"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
33201tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33202let Inst{7-2} = 0b000001;
33203let Inst{13-13} = 0b0;
33204let Inst{31-21} = 0b00011111100;
33205let hasNewValue = 1;
33206let opNewValue = 0;
33207let isCVI = 1;
33208let DecoderNamespace = "EXT_mmvec";
33209}
33210def V6_veqh_and : HInst<
33211(outs HvxQR:$Qx4),
33212(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33213"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
33214tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33215let Inst{7-2} = 0b000001;
33216let Inst{13-13} = 0b1;
33217let Inst{31-21} = 0b00011100100;
33218let isCVI = 1;
33219let DecoderNamespace = "EXT_mmvec";
33220let Constraints = "$Qx4 = $Qx4in";
33221}
33222def V6_veqh_or : HInst<
33223(outs HvxQR:$Qx4),
33224(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33225"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
33226tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33227let Inst{7-2} = 0b010001;
33228let Inst{13-13} = 0b1;
33229let Inst{31-21} = 0b00011100100;
33230let isAccumulator = 1;
33231let isCVI = 1;
33232let DecoderNamespace = "EXT_mmvec";
33233let Constraints = "$Qx4 = $Qx4in";
33234}
33235def V6_veqh_xor : HInst<
33236(outs HvxQR:$Qx4),
33237(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33238"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
33239tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33240let Inst{7-2} = 0b100001;
33241let Inst{13-13} = 0b1;
33242let Inst{31-21} = 0b00011100100;
33243let isCVI = 1;
33244let DecoderNamespace = "EXT_mmvec";
33245let Constraints = "$Qx4 = $Qx4in";
33246}
33247def V6_veqw : HInst<
33248(outs HvxQR:$Qd4),
33249(ins HvxVR:$Vu32, HvxVR:$Vv32),
33250"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
33251tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33252let Inst{7-2} = 0b000010;
33253let Inst{13-13} = 0b0;
33254let Inst{31-21} = 0b00011111100;
33255let hasNewValue = 1;
33256let opNewValue = 0;
33257let isCVI = 1;
33258let DecoderNamespace = "EXT_mmvec";
33259}
33260def V6_veqw_and : HInst<
33261(outs HvxQR:$Qx4),
33262(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33263"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
33264tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33265let Inst{7-2} = 0b000010;
33266let Inst{13-13} = 0b1;
33267let Inst{31-21} = 0b00011100100;
33268let isCVI = 1;
33269let DecoderNamespace = "EXT_mmvec";
33270let Constraints = "$Qx4 = $Qx4in";
33271}
33272def V6_veqw_or : HInst<
33273(outs HvxQR:$Qx4),
33274(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33275"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
33276tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33277let Inst{7-2} = 0b010010;
33278let Inst{13-13} = 0b1;
33279let Inst{31-21} = 0b00011100100;
33280let isAccumulator = 1;
33281let isCVI = 1;
33282let DecoderNamespace = "EXT_mmvec";
33283let Constraints = "$Qx4 = $Qx4in";
33284}
33285def V6_veqw_xor : HInst<
33286(outs HvxQR:$Qx4),
33287(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33288"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
33289tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33290let Inst{7-2} = 0b100010;
33291let Inst{13-13} = 0b1;
33292let Inst{31-21} = 0b00011100100;
33293let isCVI = 1;
33294let DecoderNamespace = "EXT_mmvec";
33295let Constraints = "$Qx4 = $Qx4in";
33296}
33297def V6_vfmax_hf : HInst<
33298(outs HvxVR:$Vd32),
33299(ins HvxVR:$Vu32, HvxVR:$Vv32),
33300"$Vd32.hf = vfmax($Vu32.hf,$Vv32.hf)",
33301tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33302let Inst{7-5} = 0b010;
33303let Inst{13-13} = 0b1;
33304let Inst{31-21} = 0b00011100011;
33305let hasNewValue = 1;
33306let opNewValue = 0;
33307let isCVI = 1;
33308let DecoderNamespace = "EXT_mmvec";
33309}
33310def V6_vfmax_sf : HInst<
33311(outs HvxVR:$Vd32),
33312(ins HvxVR:$Vu32, HvxVR:$Vv32),
33313"$Vd32.sf = vfmax($Vu32.sf,$Vv32.sf)",
33314tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33315let Inst{7-5} = 0b011;
33316let Inst{13-13} = 0b1;
33317let Inst{31-21} = 0b00011100011;
33318let hasNewValue = 1;
33319let opNewValue = 0;
33320let isCVI = 1;
33321let DecoderNamespace = "EXT_mmvec";
33322}
33323def V6_vfmin_hf : HInst<
33324(outs HvxVR:$Vd32),
33325(ins HvxVR:$Vu32, HvxVR:$Vv32),
33326"$Vd32.hf = vfmin($Vu32.hf,$Vv32.hf)",
33327tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33328let Inst{7-5} = 0b000;
33329let Inst{13-13} = 0b1;
33330let Inst{31-21} = 0b00011100011;
33331let hasNewValue = 1;
33332let opNewValue = 0;
33333let isCVI = 1;
33334let DecoderNamespace = "EXT_mmvec";
33335}
33336def V6_vfmin_sf : HInst<
33337(outs HvxVR:$Vd32),
33338(ins HvxVR:$Vu32, HvxVR:$Vv32),
33339"$Vd32.sf = vfmin($Vu32.sf,$Vv32.sf)",
33340tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33341let Inst{7-5} = 0b001;
33342let Inst{13-13} = 0b1;
33343let Inst{31-21} = 0b00011100011;
33344let hasNewValue = 1;
33345let opNewValue = 0;
33346let isCVI = 1;
33347let DecoderNamespace = "EXT_mmvec";
33348}
33349def V6_vfneg_hf : HInst<
33350(outs HvxVR:$Vd32),
33351(ins HvxVR:$Vu32),
33352"$Vd32.hf = vfneg($Vu32.hf)",
33353tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33354let Inst{7-5} = 0b010;
33355let Inst{13-13} = 0b1;
33356let Inst{31-16} = 0b0001111000000110;
33357let hasNewValue = 1;
33358let opNewValue = 0;
33359let isCVI = 1;
33360let DecoderNamespace = "EXT_mmvec";
33361}
33362def V6_vfneg_sf : HInst<
33363(outs HvxVR:$Vd32),
33364(ins HvxVR:$Vu32),
33365"$Vd32.sf = vfneg($Vu32.sf)",
33366tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33367let Inst{7-5} = 0b011;
33368let Inst{13-13} = 0b1;
33369let Inst{31-16} = 0b0001111000000110;
33370let hasNewValue = 1;
33371let opNewValue = 0;
33372let isCVI = 1;
33373let DecoderNamespace = "EXT_mmvec";
33374}
33375def V6_vgathermh : HInst<
33376(outs),
33377(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33378"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33379tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
33380let Inst{12-5} = 0b00001000;
33381let Inst{31-21} = 0b00101111000;
33382let hasNewValue = 1;
33383let opNewValue = 0;
33384let accessSize = HalfWordAccess;
33385let isCVLoad = 1;
33386let isCVI = 1;
33387let mayLoad = 1;
33388let Defs = [VTMP];
33389let DecoderNamespace = "EXT_mmvec";
33390}
33391def V6_vgathermhq : HInst<
33392(outs),
33393(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33394"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33395tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
33396let Inst{12-7} = 0b001010;
33397let Inst{31-21} = 0b00101111000;
33398let hasNewValue = 1;
33399let opNewValue = 0;
33400let accessSize = HalfWordAccess;
33401let isCVLoad = 1;
33402let isCVI = 1;
33403let mayLoad = 1;
33404let Defs = [VTMP];
33405let DecoderNamespace = "EXT_mmvec";
33406}
33407def V6_vgathermhw : HInst<
33408(outs),
33409(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
33410"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33411tc_7095ecba, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> {
33412let Inst{12-5} = 0b00010000;
33413let Inst{31-21} = 0b00101111000;
33414let hasNewValue = 1;
33415let opNewValue = 0;
33416let accessSize = HalfWordAccess;
33417let isCVLoad = 1;
33418let isCVI = 1;
33419let mayLoad = 1;
33420let Defs = [VTMP];
33421let DecoderNamespace = "EXT_mmvec";
33422}
33423def V6_vgathermhwq : HInst<
33424(outs),
33425(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
33426"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33427tc_a69eeee1, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> {
33428let Inst{12-7} = 0b001100;
33429let Inst{31-21} = 0b00101111000;
33430let hasNewValue = 1;
33431let opNewValue = 0;
33432let accessSize = HalfWordAccess;
33433let isCVLoad = 1;
33434let isCVI = 1;
33435let mayLoad = 1;
33436let Defs = [VTMP];
33437let DecoderNamespace = "EXT_mmvec";
33438}
33439def V6_vgathermw : HInst<
33440(outs),
33441(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33442"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
33443tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
33444let Inst{12-5} = 0b00000000;
33445let Inst{31-21} = 0b00101111000;
33446let hasNewValue = 1;
33447let opNewValue = 0;
33448let accessSize = WordAccess;
33449let isCVLoad = 1;
33450let isCVI = 1;
33451let mayLoad = 1;
33452let Defs = [VTMP];
33453let DecoderNamespace = "EXT_mmvec";
33454}
33455def V6_vgathermwq : HInst<
33456(outs),
33457(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33458"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
33459tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
33460let Inst{12-7} = 0b001000;
33461let Inst{31-21} = 0b00101111000;
33462let hasNewValue = 1;
33463let opNewValue = 0;
33464let accessSize = WordAccess;
33465let isCVLoad = 1;
33466let isCVI = 1;
33467let mayLoad = 1;
33468let Defs = [VTMP];
33469let DecoderNamespace = "EXT_mmvec";
33470}
33471def V6_vgtb : HInst<
33472(outs HvxQR:$Qd4),
33473(ins HvxVR:$Vu32, HvxVR:$Vv32),
33474"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
33475tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33476let Inst{7-2} = 0b000100;
33477let Inst{13-13} = 0b0;
33478let Inst{31-21} = 0b00011111100;
33479let hasNewValue = 1;
33480let opNewValue = 0;
33481let isCVI = 1;
33482let DecoderNamespace = "EXT_mmvec";
33483}
33484def V6_vgtb_and : HInst<
33485(outs HvxQR:$Qx4),
33486(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33487"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
33488tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33489let Inst{7-2} = 0b000100;
33490let Inst{13-13} = 0b1;
33491let Inst{31-21} = 0b00011100100;
33492let isCVI = 1;
33493let DecoderNamespace = "EXT_mmvec";
33494let Constraints = "$Qx4 = $Qx4in";
33495}
33496def V6_vgtb_or : HInst<
33497(outs HvxQR:$Qx4),
33498(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33499"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
33500tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33501let Inst{7-2} = 0b010100;
33502let Inst{13-13} = 0b1;
33503let Inst{31-21} = 0b00011100100;
33504let isAccumulator = 1;
33505let isCVI = 1;
33506let DecoderNamespace = "EXT_mmvec";
33507let Constraints = "$Qx4 = $Qx4in";
33508}
33509def V6_vgtb_xor : HInst<
33510(outs HvxQR:$Qx4),
33511(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33512"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
33513tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33514let Inst{7-2} = 0b100100;
33515let Inst{13-13} = 0b1;
33516let Inst{31-21} = 0b00011100100;
33517let isCVI = 1;
33518let DecoderNamespace = "EXT_mmvec";
33519let Constraints = "$Qx4 = $Qx4in";
33520}
33521def V6_vgth : HInst<
33522(outs HvxQR:$Qd4),
33523(ins HvxVR:$Vu32, HvxVR:$Vv32),
33524"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
33525tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33526let Inst{7-2} = 0b000101;
33527let Inst{13-13} = 0b0;
33528let Inst{31-21} = 0b00011111100;
33529let hasNewValue = 1;
33530let opNewValue = 0;
33531let isCVI = 1;
33532let DecoderNamespace = "EXT_mmvec";
33533}
33534def V6_vgth_and : HInst<
33535(outs HvxQR:$Qx4),
33536(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33537"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
33538tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33539let Inst{7-2} = 0b000101;
33540let Inst{13-13} = 0b1;
33541let Inst{31-21} = 0b00011100100;
33542let isCVI = 1;
33543let DecoderNamespace = "EXT_mmvec";
33544let Constraints = "$Qx4 = $Qx4in";
33545}
33546def V6_vgth_or : HInst<
33547(outs HvxQR:$Qx4),
33548(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33549"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
33550tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33551let Inst{7-2} = 0b010101;
33552let Inst{13-13} = 0b1;
33553let Inst{31-21} = 0b00011100100;
33554let isAccumulator = 1;
33555let isCVI = 1;
33556let DecoderNamespace = "EXT_mmvec";
33557let Constraints = "$Qx4 = $Qx4in";
33558}
33559def V6_vgth_xor : HInst<
33560(outs HvxQR:$Qx4),
33561(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33562"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
33563tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33564let Inst{7-2} = 0b100101;
33565let Inst{13-13} = 0b1;
33566let Inst{31-21} = 0b00011100100;
33567let isCVI = 1;
33568let DecoderNamespace = "EXT_mmvec";
33569let Constraints = "$Qx4 = $Qx4in";
33570}
33571def V6_vgthf : HInst<
33572(outs HvxQR:$Qd4),
33573(ins HvxVR:$Vu32, HvxVR:$Vv32),
33574"$Qd4 = vcmp.gt($Vu32.hf,$Vv32.hf)",
33575tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33576let Inst{7-2} = 0b011101;
33577let Inst{13-13} = 0b1;
33578let Inst{31-21} = 0b00011100100;
33579let hasNewValue = 1;
33580let opNewValue = 0;
33581let isCVI = 1;
33582let DecoderNamespace = "EXT_mmvec";
33583}
33584def V6_vgthf_and : HInst<
33585(outs HvxQR:$Qx4),
33586(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33587"$Qx4 &= vcmp.gt($Vu32.hf,$Vv32.hf)",
33588tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33589let Inst{7-2} = 0b110011;
33590let Inst{13-13} = 0b1;
33591let Inst{31-21} = 0b00011100100;
33592let isCVI = 1;
33593let DecoderNamespace = "EXT_mmvec";
33594let Constraints = "$Qx4 = $Qx4in";
33595}
33596def V6_vgthf_or : HInst<
33597(outs HvxQR:$Qx4),
33598(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33599"$Qx4 |= vcmp.gt($Vu32.hf,$Vv32.hf)",
33600tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33601let Inst{7-2} = 0b001101;
33602let Inst{13-13} = 0b1;
33603let Inst{31-21} = 0b00011100100;
33604let isAccumulator = 1;
33605let isCVI = 1;
33606let DecoderNamespace = "EXT_mmvec";
33607let Constraints = "$Qx4 = $Qx4in";
33608}
33609def V6_vgthf_xor : HInst<
33610(outs HvxQR:$Qx4),
33611(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33612"$Qx4 ^= vcmp.gt($Vu32.hf,$Vv32.hf)",
33613tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33614let Inst{7-2} = 0b111011;
33615let Inst{13-13} = 0b1;
33616let Inst{31-21} = 0b00011100100;
33617let isCVI = 1;
33618let DecoderNamespace = "EXT_mmvec";
33619let Constraints = "$Qx4 = $Qx4in";
33620}
33621def V6_vgtsf : HInst<
33622(outs HvxQR:$Qd4),
33623(ins HvxVR:$Vu32, HvxVR:$Vv32),
33624"$Qd4 = vcmp.gt($Vu32.sf,$Vv32.sf)",
33625tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33626let Inst{7-2} = 0b011100;
33627let Inst{13-13} = 0b1;
33628let Inst{31-21} = 0b00011100100;
33629let hasNewValue = 1;
33630let opNewValue = 0;
33631let isCVI = 1;
33632let DecoderNamespace = "EXT_mmvec";
33633}
33634def V6_vgtsf_and : HInst<
33635(outs HvxQR:$Qx4),
33636(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33637"$Qx4 &= vcmp.gt($Vu32.sf,$Vv32.sf)",
33638tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33639let Inst{7-2} = 0b110010;
33640let Inst{13-13} = 0b1;
33641let Inst{31-21} = 0b00011100100;
33642let isCVI = 1;
33643let DecoderNamespace = "EXT_mmvec";
33644let Constraints = "$Qx4 = $Qx4in";
33645}
33646def V6_vgtsf_or : HInst<
33647(outs HvxQR:$Qx4),
33648(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33649"$Qx4 |= vcmp.gt($Vu32.sf,$Vv32.sf)",
33650tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33651let Inst{7-2} = 0b001100;
33652let Inst{13-13} = 0b1;
33653let Inst{31-21} = 0b00011100100;
33654let isAccumulator = 1;
33655let isCVI = 1;
33656let DecoderNamespace = "EXT_mmvec";
33657let Constraints = "$Qx4 = $Qx4in";
33658}
33659def V6_vgtsf_xor : HInst<
33660(outs HvxQR:$Qx4),
33661(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33662"$Qx4 ^= vcmp.gt($Vu32.sf,$Vv32.sf)",
33663tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33664let Inst{7-2} = 0b111010;
33665let Inst{13-13} = 0b1;
33666let Inst{31-21} = 0b00011100100;
33667let isCVI = 1;
33668let DecoderNamespace = "EXT_mmvec";
33669let Constraints = "$Qx4 = $Qx4in";
33670}
33671def V6_vgtub : HInst<
33672(outs HvxQR:$Qd4),
33673(ins HvxVR:$Vu32, HvxVR:$Vv32),
33674"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
33675tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33676let Inst{7-2} = 0b001000;
33677let Inst{13-13} = 0b0;
33678let Inst{31-21} = 0b00011111100;
33679let hasNewValue = 1;
33680let opNewValue = 0;
33681let isCVI = 1;
33682let DecoderNamespace = "EXT_mmvec";
33683}
33684def V6_vgtub_and : HInst<
33685(outs HvxQR:$Qx4),
33686(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33687"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
33688tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33689let Inst{7-2} = 0b001000;
33690let Inst{13-13} = 0b1;
33691let Inst{31-21} = 0b00011100100;
33692let isCVI = 1;
33693let DecoderNamespace = "EXT_mmvec";
33694let Constraints = "$Qx4 = $Qx4in";
33695}
33696def V6_vgtub_or : HInst<
33697(outs HvxQR:$Qx4),
33698(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33699"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
33700tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33701let Inst{7-2} = 0b011000;
33702let Inst{13-13} = 0b1;
33703let Inst{31-21} = 0b00011100100;
33704let isAccumulator = 1;
33705let isCVI = 1;
33706let DecoderNamespace = "EXT_mmvec";
33707let Constraints = "$Qx4 = $Qx4in";
33708}
33709def V6_vgtub_xor : HInst<
33710(outs HvxQR:$Qx4),
33711(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33712"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
33713tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33714let Inst{7-2} = 0b101000;
33715let Inst{13-13} = 0b1;
33716let Inst{31-21} = 0b00011100100;
33717let isCVI = 1;
33718let DecoderNamespace = "EXT_mmvec";
33719let Constraints = "$Qx4 = $Qx4in";
33720}
33721def V6_vgtuh : HInst<
33722(outs HvxQR:$Qd4),
33723(ins HvxVR:$Vu32, HvxVR:$Vv32),
33724"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
33725tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33726let Inst{7-2} = 0b001001;
33727let Inst{13-13} = 0b0;
33728let Inst{31-21} = 0b00011111100;
33729let hasNewValue = 1;
33730let opNewValue = 0;
33731let isCVI = 1;
33732let DecoderNamespace = "EXT_mmvec";
33733}
33734def V6_vgtuh_and : HInst<
33735(outs HvxQR:$Qx4),
33736(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33737"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
33738tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33739let Inst{7-2} = 0b001001;
33740let Inst{13-13} = 0b1;
33741let Inst{31-21} = 0b00011100100;
33742let isCVI = 1;
33743let DecoderNamespace = "EXT_mmvec";
33744let Constraints = "$Qx4 = $Qx4in";
33745}
33746def V6_vgtuh_or : HInst<
33747(outs HvxQR:$Qx4),
33748(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33749"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
33750tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33751let Inst{7-2} = 0b011001;
33752let Inst{13-13} = 0b1;
33753let Inst{31-21} = 0b00011100100;
33754let isAccumulator = 1;
33755let isCVI = 1;
33756let DecoderNamespace = "EXT_mmvec";
33757let Constraints = "$Qx4 = $Qx4in";
33758}
33759def V6_vgtuh_xor : HInst<
33760(outs HvxQR:$Qx4),
33761(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33762"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
33763tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33764let Inst{7-2} = 0b101001;
33765let Inst{13-13} = 0b1;
33766let Inst{31-21} = 0b00011100100;
33767let isCVI = 1;
33768let DecoderNamespace = "EXT_mmvec";
33769let Constraints = "$Qx4 = $Qx4in";
33770}
33771def V6_vgtuw : HInst<
33772(outs HvxQR:$Qd4),
33773(ins HvxVR:$Vu32, HvxVR:$Vv32),
33774"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
33775tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33776let Inst{7-2} = 0b001010;
33777let Inst{13-13} = 0b0;
33778let Inst{31-21} = 0b00011111100;
33779let hasNewValue = 1;
33780let opNewValue = 0;
33781let isCVI = 1;
33782let DecoderNamespace = "EXT_mmvec";
33783}
33784def V6_vgtuw_and : HInst<
33785(outs HvxQR:$Qx4),
33786(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33787"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
33788tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33789let Inst{7-2} = 0b001010;
33790let Inst{13-13} = 0b1;
33791let Inst{31-21} = 0b00011100100;
33792let isCVI = 1;
33793let DecoderNamespace = "EXT_mmvec";
33794let Constraints = "$Qx4 = $Qx4in";
33795}
33796def V6_vgtuw_or : HInst<
33797(outs HvxQR:$Qx4),
33798(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33799"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
33800tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33801let Inst{7-2} = 0b011010;
33802let Inst{13-13} = 0b1;
33803let Inst{31-21} = 0b00011100100;
33804let isAccumulator = 1;
33805let isCVI = 1;
33806let DecoderNamespace = "EXT_mmvec";
33807let Constraints = "$Qx4 = $Qx4in";
33808}
33809def V6_vgtuw_xor : HInst<
33810(outs HvxQR:$Qx4),
33811(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33812"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
33813tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33814let Inst{7-2} = 0b101010;
33815let Inst{13-13} = 0b1;
33816let Inst{31-21} = 0b00011100100;
33817let isCVI = 1;
33818let DecoderNamespace = "EXT_mmvec";
33819let Constraints = "$Qx4 = $Qx4in";
33820}
33821def V6_vgtw : HInst<
33822(outs HvxQR:$Qd4),
33823(ins HvxVR:$Vu32, HvxVR:$Vv32),
33824"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
33825tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33826let Inst{7-2} = 0b000110;
33827let Inst{13-13} = 0b0;
33828let Inst{31-21} = 0b00011111100;
33829let hasNewValue = 1;
33830let opNewValue = 0;
33831let isCVI = 1;
33832let DecoderNamespace = "EXT_mmvec";
33833}
33834def V6_vgtw_and : HInst<
33835(outs HvxQR:$Qx4),
33836(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33837"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
33838tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33839let Inst{7-2} = 0b000110;
33840let Inst{13-13} = 0b1;
33841let Inst{31-21} = 0b00011100100;
33842let isCVI = 1;
33843let DecoderNamespace = "EXT_mmvec";
33844let Constraints = "$Qx4 = $Qx4in";
33845}
33846def V6_vgtw_or : HInst<
33847(outs HvxQR:$Qx4),
33848(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33849"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
33850tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33851let Inst{7-2} = 0b010110;
33852let Inst{13-13} = 0b1;
33853let Inst{31-21} = 0b00011100100;
33854let isAccumulator = 1;
33855let isCVI = 1;
33856let DecoderNamespace = "EXT_mmvec";
33857let Constraints = "$Qx4 = $Qx4in";
33858}
33859def V6_vgtw_xor : HInst<
33860(outs HvxQR:$Qx4),
33861(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33862"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
33863tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33864let Inst{7-2} = 0b100110;
33865let Inst{13-13} = 0b1;
33866let Inst{31-21} = 0b00011100100;
33867let isCVI = 1;
33868let DecoderNamespace = "EXT_mmvec";
33869let Constraints = "$Qx4 = $Qx4in";
33870}
33871def V6_vhist : HInst<
33872(outs),
33873(ins),
33874"vhist",
33875tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
33876let Inst{13-0} = 0b10000010000000;
33877let Inst{31-16} = 0b0001111000000000;
33878let isCVI = 1;
33879let DecoderNamespace = "EXT_mmvec";
33880}
33881def V6_vhistq : HInst<
33882(outs),
33883(ins HvxQR:$Qv4),
33884"vhist($Qv4)",
33885tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
33886let Inst{13-0} = 0b10000010000000;
33887let Inst{21-16} = 0b000010;
33888let Inst{31-24} = 0b00011110;
33889let isCVI = 1;
33890let DecoderNamespace = "EXT_mmvec";
33891}
33892def V6_vinsertwr : HInst<
33893(outs HvxVR:$Vx32),
33894(ins HvxVR:$Vx32in, IntRegs:$Rt32),
33895"$Vx32.w = vinsert($Rt32)",
33896tc_ac4046bc, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
33897let Inst{13-5} = 0b100000001;
33898let Inst{31-21} = 0b00011001101;
33899let hasNewValue = 1;
33900let opNewValue = 0;
33901let isCVI = 1;
33902let DecoderNamespace = "EXT_mmvec";
33903let Constraints = "$Vx32 = $Vx32in";
33904}
33905def V6_vlalignb : HInst<
33906(outs HvxVR:$Vd32),
33907(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33908"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
33909tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
33910let Inst{7-5} = 0b001;
33911let Inst{13-13} = 0b0;
33912let Inst{31-24} = 0b00011011;
33913let hasNewValue = 1;
33914let opNewValue = 0;
33915let isCVI = 1;
33916let DecoderNamespace = "EXT_mmvec";
33917}
33918def V6_vlalignbi : HInst<
33919(outs HvxVR:$Vd32),
33920(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33921"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
33922tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
33923let Inst{13-13} = 0b1;
33924let Inst{31-21} = 0b00011110011;
33925let hasNewValue = 1;
33926let opNewValue = 0;
33927let isCVI = 1;
33928let DecoderNamespace = "EXT_mmvec";
33929}
33930def V6_vlsrb : HInst<
33931(outs HvxVR:$Vd32),
33932(ins HvxVR:$Vu32, IntRegs:$Rt32),
33933"$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
33934tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
33935let Inst{7-5} = 0b011;
33936let Inst{13-13} = 0b0;
33937let Inst{31-21} = 0b00011001100;
33938let hasNewValue = 1;
33939let opNewValue = 0;
33940let isCVI = 1;
33941let DecoderNamespace = "EXT_mmvec";
33942}
33943def V6_vlsrh : HInst<
33944(outs HvxVR:$Vd32),
33945(ins HvxVR:$Vu32, IntRegs:$Rt32),
33946"$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
33947tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
33948let Inst{7-5} = 0b010;
33949let Inst{13-13} = 0b0;
33950let Inst{31-21} = 0b00011001100;
33951let hasNewValue = 1;
33952let opNewValue = 0;
33953let isCVI = 1;
33954let DecoderNamespace = "EXT_mmvec";
33955}
33956def V6_vlsrh_alt : HInst<
33957(outs HvxVR:$Vd32),
33958(ins HvxVR:$Vu32, IntRegs:$Rt32),
33959"$Vd32 = vlsrh($Vu32,$Rt32)",
33960PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33961let hasNewValue = 1;
33962let opNewValue = 0;
33963let isCVI = 1;
33964let isPseudo = 1;
33965let isCodeGenOnly = 1;
33966let DecoderNamespace = "EXT_mmvec";
33967}
33968def V6_vlsrhv : HInst<
33969(outs HvxVR:$Vd32),
33970(ins HvxVR:$Vu32, HvxVR:$Vv32),
33971"$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
33972tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
33973let Inst{7-5} = 0b010;
33974let Inst{13-13} = 0b0;
33975let Inst{31-21} = 0b00011111101;
33976let hasNewValue = 1;
33977let opNewValue = 0;
33978let isCVI = 1;
33979let DecoderNamespace = "EXT_mmvec";
33980}
33981def V6_vlsrhv_alt : HInst<
33982(outs HvxVR:$Vd32),
33983(ins HvxVR:$Vu32, HvxVR:$Vv32),
33984"$Vd32 = vlsrh($Vu32,$Vv32)",
33985PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33986let hasNewValue = 1;
33987let opNewValue = 0;
33988let isCVI = 1;
33989let isPseudo = 1;
33990let isCodeGenOnly = 1;
33991let DecoderNamespace = "EXT_mmvec";
33992}
33993def V6_vlsrw : HInst<
33994(outs HvxVR:$Vd32),
33995(ins HvxVR:$Vu32, IntRegs:$Rt32),
33996"$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
33997tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
33998let Inst{7-5} = 0b001;
33999let Inst{13-13} = 0b0;
34000let Inst{31-21} = 0b00011001100;
34001let hasNewValue = 1;
34002let opNewValue = 0;
34003let isCVI = 1;
34004let DecoderNamespace = "EXT_mmvec";
34005}
34006def V6_vlsrw_alt : HInst<
34007(outs HvxVR:$Vd32),
34008(ins HvxVR:$Vu32, IntRegs:$Rt32),
34009"$Vd32 = vlsrw($Vu32,$Rt32)",
34010PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34011let hasNewValue = 1;
34012let opNewValue = 0;
34013let isCVI = 1;
34014let isPseudo = 1;
34015let isCodeGenOnly = 1;
34016let DecoderNamespace = "EXT_mmvec";
34017}
34018def V6_vlsrwv : HInst<
34019(outs HvxVR:$Vd32),
34020(ins HvxVR:$Vu32, HvxVR:$Vv32),
34021"$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
34022tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
34023let Inst{7-5} = 0b001;
34024let Inst{13-13} = 0b0;
34025let Inst{31-21} = 0b00011111101;
34026let hasNewValue = 1;
34027let opNewValue = 0;
34028let isCVI = 1;
34029let DecoderNamespace = "EXT_mmvec";
34030}
34031def V6_vlsrwv_alt : HInst<
34032(outs HvxVR:$Vd32),
34033(ins HvxVR:$Vu32, HvxVR:$Vv32),
34034"$Vd32 = vlsrw($Vu32,$Vv32)",
34035PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34036let hasNewValue = 1;
34037let opNewValue = 0;
34038let isCVI = 1;
34039let isPseudo = 1;
34040let isCodeGenOnly = 1;
34041let DecoderNamespace = "EXT_mmvec";
34042}
34043def V6_vlut4 : HInst<
34044(outs HvxVR:$Vd32),
34045(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34046"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
34047tc_f1de44ef, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
34048let Inst{7-5} = 0b100;
34049let Inst{13-13} = 0b0;
34050let Inst{31-21} = 0b00011001011;
34051let hasNewValue = 1;
34052let opNewValue = 0;
34053let isCVI = 1;
34054let DecoderNamespace = "EXT_mmvec";
34055}
34056def V6_vlutvvb : HInst<
34057(outs HvxVR:$Vd32),
34058(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34059"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
34060tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
34061let Inst{7-5} = 0b001;
34062let Inst{13-13} = 0b1;
34063let Inst{31-24} = 0b00011011;
34064let hasNewValue = 1;
34065let opNewValue = 0;
34066let isCVI = 1;
34067let DecoderNamespace = "EXT_mmvec";
34068}
34069def V6_vlutvvb_nm : HInst<
34070(outs HvxVR:$Vd32),
34071(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34072"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
34073tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
34074let Inst{7-5} = 0b011;
34075let Inst{13-13} = 0b0;
34076let Inst{31-24} = 0b00011000;
34077let hasNewValue = 1;
34078let opNewValue = 0;
34079let isCVI = 1;
34080let DecoderNamespace = "EXT_mmvec";
34081}
34082def V6_vlutvvb_oracc : HInst<
34083(outs HvxVR:$Vx32),
34084(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34085"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
34086tc_9d1dc972, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
34087let Inst{7-5} = 0b101;
34088let Inst{13-13} = 0b1;
34089let Inst{31-24} = 0b00011011;
34090let hasNewValue = 1;
34091let opNewValue = 0;
34092let isAccumulator = 1;
34093let isCVI = 1;
34094let DecoderNamespace = "EXT_mmvec";
34095let Constraints = "$Vx32 = $Vx32in";
34096}
34097def V6_vlutvvb_oracci : HInst<
34098(outs HvxVR:$Vx32),
34099(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34100"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
34101tc_9d1dc972, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
34102let Inst{13-13} = 0b1;
34103let Inst{31-21} = 0b00011100110;
34104let hasNewValue = 1;
34105let opNewValue = 0;
34106let isAccumulator = 1;
34107let isCVI = 1;
34108let DecoderNamespace = "EXT_mmvec";
34109let Constraints = "$Vx32 = $Vx32in";
34110}
34111def V6_vlutvvbi : HInst<
34112(outs HvxVR:$Vd32),
34113(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34114"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
34115tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
34116let Inst{13-13} = 0b0;
34117let Inst{31-21} = 0b00011110001;
34118let hasNewValue = 1;
34119let opNewValue = 0;
34120let isCVI = 1;
34121let DecoderNamespace = "EXT_mmvec";
34122}
34123def V6_vlutvwh : HInst<
34124(outs HvxWR:$Vdd32),
34125(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34126"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
34127tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
34128let Inst{7-5} = 0b110;
34129let Inst{13-13} = 0b1;
34130let Inst{31-24} = 0b00011011;
34131let hasNewValue = 1;
34132let opNewValue = 0;
34133let isCVI = 1;
34134let DecoderNamespace = "EXT_mmvec";
34135}
34136def V6_vlutvwh_nm : HInst<
34137(outs HvxWR:$Vdd32),
34138(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34139"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
34140tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
34141let Inst{7-5} = 0b100;
34142let Inst{13-13} = 0b0;
34143let Inst{31-24} = 0b00011000;
34144let hasNewValue = 1;
34145let opNewValue = 0;
34146let isCVI = 1;
34147let DecoderNamespace = "EXT_mmvec";
34148}
34149def V6_vlutvwh_oracc : HInst<
34150(outs HvxWR:$Vxx32),
34151(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34152"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
34153tc_9d1dc972, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
34154let Inst{7-5} = 0b111;
34155let Inst{13-13} = 0b1;
34156let Inst{31-24} = 0b00011011;
34157let hasNewValue = 1;
34158let opNewValue = 0;
34159let isAccumulator = 1;
34160let isCVI = 1;
34161let DecoderNamespace = "EXT_mmvec";
34162let Constraints = "$Vxx32 = $Vxx32in";
34163}
34164def V6_vlutvwh_oracci : HInst<
34165(outs HvxWR:$Vxx32),
34166(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34167"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
34168tc_9d1dc972, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
34169let Inst{13-13} = 0b1;
34170let Inst{31-21} = 0b00011100111;
34171let hasNewValue = 1;
34172let opNewValue = 0;
34173let isAccumulator = 1;
34174let isCVI = 1;
34175let DecoderNamespace = "EXT_mmvec";
34176let Constraints = "$Vxx32 = $Vxx32in";
34177}
34178def V6_vlutvwhi : HInst<
34179(outs HvxWR:$Vdd32),
34180(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34181"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
34182tc_87adc037, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
34183let Inst{13-13} = 0b0;
34184let Inst{31-21} = 0b00011110011;
34185let hasNewValue = 1;
34186let opNewValue = 0;
34187let isCVI = 1;
34188let DecoderNamespace = "EXT_mmvec";
34189}
34190def V6_vmax_hf : HInst<
34191(outs HvxVR:$Vd32),
34192(ins HvxVR:$Vu32, HvxVR:$Vv32),
34193"$Vd32.hf = vmax($Vu32.hf,$Vv32.hf)",
34194tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34195let Inst{7-5} = 0b011;
34196let Inst{13-13} = 0b1;
34197let Inst{31-21} = 0b00011111110;
34198let hasNewValue = 1;
34199let opNewValue = 0;
34200let isCVI = 1;
34201let DecoderNamespace = "EXT_mmvec";
34202}
34203def V6_vmax_sf : HInst<
34204(outs HvxVR:$Vd32),
34205(ins HvxVR:$Vu32, HvxVR:$Vv32),
34206"$Vd32.sf = vmax($Vu32.sf,$Vv32.sf)",
34207tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34208let Inst{7-5} = 0b001;
34209let Inst{13-13} = 0b1;
34210let Inst{31-21} = 0b00011111110;
34211let hasNewValue = 1;
34212let opNewValue = 0;
34213let isCVI = 1;
34214let DecoderNamespace = "EXT_mmvec";
34215}
34216def V6_vmaxb : HInst<
34217(outs HvxVR:$Vd32),
34218(ins HvxVR:$Vu32, HvxVR:$Vv32),
34219"$Vd32.b = vmax($Vu32.b,$Vv32.b)",
34220tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
34221let Inst{7-5} = 0b101;
34222let Inst{13-13} = 0b0;
34223let Inst{31-21} = 0b00011111001;
34224let hasNewValue = 1;
34225let opNewValue = 0;
34226let isCVI = 1;
34227let DecoderNamespace = "EXT_mmvec";
34228}
34229def V6_vmaxb_alt : HInst<
34230(outs HvxVR:$Vd32),
34231(ins HvxVR:$Vu32, HvxVR:$Vv32),
34232"$Vd32 = vmaxb($Vu32,$Vv32)",
34233PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34234let hasNewValue = 1;
34235let opNewValue = 0;
34236let isCVI = 1;
34237let isPseudo = 1;
34238let isCodeGenOnly = 1;
34239let DecoderNamespace = "EXT_mmvec";
34240}
34241def V6_vmaxh : HInst<
34242(outs HvxVR:$Vd32),
34243(ins HvxVR:$Vu32, HvxVR:$Vv32),
34244"$Vd32.h = vmax($Vu32.h,$Vv32.h)",
34245tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34246let Inst{7-5} = 0b111;
34247let Inst{13-13} = 0b0;
34248let Inst{31-21} = 0b00011111000;
34249let hasNewValue = 1;
34250let opNewValue = 0;
34251let isCVI = 1;
34252let DecoderNamespace = "EXT_mmvec";
34253}
34254def V6_vmaxh_alt : HInst<
34255(outs HvxVR:$Vd32),
34256(ins HvxVR:$Vu32, HvxVR:$Vv32),
34257"$Vd32 = vmaxh($Vu32,$Vv32)",
34258PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34259let hasNewValue = 1;
34260let opNewValue = 0;
34261let isCVI = 1;
34262let isPseudo = 1;
34263let isCodeGenOnly = 1;
34264let DecoderNamespace = "EXT_mmvec";
34265}
34266def V6_vmaxub : HInst<
34267(outs HvxVR:$Vd32),
34268(ins HvxVR:$Vu32, HvxVR:$Vv32),
34269"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
34270tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34271let Inst{7-5} = 0b101;
34272let Inst{13-13} = 0b0;
34273let Inst{31-21} = 0b00011111000;
34274let hasNewValue = 1;
34275let opNewValue = 0;
34276let isCVI = 1;
34277let DecoderNamespace = "EXT_mmvec";
34278}
34279def V6_vmaxub_alt : HInst<
34280(outs HvxVR:$Vd32),
34281(ins HvxVR:$Vu32, HvxVR:$Vv32),
34282"$Vd32 = vmaxub($Vu32,$Vv32)",
34283PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34284let hasNewValue = 1;
34285let opNewValue = 0;
34286let isCVI = 1;
34287let isPseudo = 1;
34288let isCodeGenOnly = 1;
34289let DecoderNamespace = "EXT_mmvec";
34290}
34291def V6_vmaxuh : HInst<
34292(outs HvxVR:$Vd32),
34293(ins HvxVR:$Vu32, HvxVR:$Vv32),
34294"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
34295tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34296let Inst{7-5} = 0b110;
34297let Inst{13-13} = 0b0;
34298let Inst{31-21} = 0b00011111000;
34299let hasNewValue = 1;
34300let opNewValue = 0;
34301let isCVI = 1;
34302let DecoderNamespace = "EXT_mmvec";
34303}
34304def V6_vmaxuh_alt : HInst<
34305(outs HvxVR:$Vd32),
34306(ins HvxVR:$Vu32, HvxVR:$Vv32),
34307"$Vd32 = vmaxuh($Vu32,$Vv32)",
34308PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34309let hasNewValue = 1;
34310let opNewValue = 0;
34311let isCVI = 1;
34312let isPseudo = 1;
34313let isCodeGenOnly = 1;
34314let DecoderNamespace = "EXT_mmvec";
34315}
34316def V6_vmaxw : HInst<
34317(outs HvxVR:$Vd32),
34318(ins HvxVR:$Vu32, HvxVR:$Vv32),
34319"$Vd32.w = vmax($Vu32.w,$Vv32.w)",
34320tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34321let Inst{7-5} = 0b000;
34322let Inst{13-13} = 0b0;
34323let Inst{31-21} = 0b00011111001;
34324let hasNewValue = 1;
34325let opNewValue = 0;
34326let isCVI = 1;
34327let DecoderNamespace = "EXT_mmvec";
34328}
34329def V6_vmaxw_alt : HInst<
34330(outs HvxVR:$Vd32),
34331(ins HvxVR:$Vu32, HvxVR:$Vv32),
34332"$Vd32 = vmaxw($Vu32,$Vv32)",
34333PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34334let hasNewValue = 1;
34335let opNewValue = 0;
34336let isCVI = 1;
34337let isPseudo = 1;
34338let isCodeGenOnly = 1;
34339let DecoderNamespace = "EXT_mmvec";
34340}
34341def V6_vmin_hf : HInst<
34342(outs HvxVR:$Vd32),
34343(ins HvxVR:$Vu32, HvxVR:$Vv32),
34344"$Vd32.hf = vmin($Vu32.hf,$Vv32.hf)",
34345tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34346let Inst{7-5} = 0b100;
34347let Inst{13-13} = 0b1;
34348let Inst{31-21} = 0b00011111110;
34349let hasNewValue = 1;
34350let opNewValue = 0;
34351let isCVI = 1;
34352let DecoderNamespace = "EXT_mmvec";
34353}
34354def V6_vmin_sf : HInst<
34355(outs HvxVR:$Vd32),
34356(ins HvxVR:$Vu32, HvxVR:$Vv32),
34357"$Vd32.sf = vmin($Vu32.sf,$Vv32.sf)",
34358tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34359let Inst{7-5} = 0b010;
34360let Inst{13-13} = 0b1;
34361let Inst{31-21} = 0b00011111110;
34362let hasNewValue = 1;
34363let opNewValue = 0;
34364let isCVI = 1;
34365let DecoderNamespace = "EXT_mmvec";
34366}
34367def V6_vminb : HInst<
34368(outs HvxVR:$Vd32),
34369(ins HvxVR:$Vu32, HvxVR:$Vv32),
34370"$Vd32.b = vmin($Vu32.b,$Vv32.b)",
34371tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
34372let Inst{7-5} = 0b100;
34373let Inst{13-13} = 0b0;
34374let Inst{31-21} = 0b00011111001;
34375let hasNewValue = 1;
34376let opNewValue = 0;
34377let isCVI = 1;
34378let DecoderNamespace = "EXT_mmvec";
34379}
34380def V6_vminb_alt : HInst<
34381(outs HvxVR:$Vd32),
34382(ins HvxVR:$Vu32, HvxVR:$Vv32),
34383"$Vd32 = vminb($Vu32,$Vv32)",
34384PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34385let hasNewValue = 1;
34386let opNewValue = 0;
34387let isCVI = 1;
34388let isPseudo = 1;
34389let isCodeGenOnly = 1;
34390let DecoderNamespace = "EXT_mmvec";
34391}
34392def V6_vminh : HInst<
34393(outs HvxVR:$Vd32),
34394(ins HvxVR:$Vu32, HvxVR:$Vv32),
34395"$Vd32.h = vmin($Vu32.h,$Vv32.h)",
34396tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34397let Inst{7-5} = 0b011;
34398let Inst{13-13} = 0b0;
34399let Inst{31-21} = 0b00011111000;
34400let hasNewValue = 1;
34401let opNewValue = 0;
34402let isCVI = 1;
34403let DecoderNamespace = "EXT_mmvec";
34404}
34405def V6_vminh_alt : HInst<
34406(outs HvxVR:$Vd32),
34407(ins HvxVR:$Vu32, HvxVR:$Vv32),
34408"$Vd32 = vminh($Vu32,$Vv32)",
34409PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34410let hasNewValue = 1;
34411let opNewValue = 0;
34412let isCVI = 1;
34413let isPseudo = 1;
34414let isCodeGenOnly = 1;
34415let DecoderNamespace = "EXT_mmvec";
34416}
34417def V6_vminub : HInst<
34418(outs HvxVR:$Vd32),
34419(ins HvxVR:$Vu32, HvxVR:$Vv32),
34420"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
34421tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34422let Inst{7-5} = 0b001;
34423let Inst{13-13} = 0b0;
34424let Inst{31-21} = 0b00011111000;
34425let hasNewValue = 1;
34426let opNewValue = 0;
34427let isCVI = 1;
34428let DecoderNamespace = "EXT_mmvec";
34429}
34430def V6_vminub_alt : HInst<
34431(outs HvxVR:$Vd32),
34432(ins HvxVR:$Vu32, HvxVR:$Vv32),
34433"$Vd32 = vminub($Vu32,$Vv32)",
34434PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34435let hasNewValue = 1;
34436let opNewValue = 0;
34437let isCVI = 1;
34438let isPseudo = 1;
34439let isCodeGenOnly = 1;
34440let DecoderNamespace = "EXT_mmvec";
34441}
34442def V6_vminuh : HInst<
34443(outs HvxVR:$Vd32),
34444(ins HvxVR:$Vu32, HvxVR:$Vv32),
34445"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
34446tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34447let Inst{7-5} = 0b010;
34448let Inst{13-13} = 0b0;
34449let Inst{31-21} = 0b00011111000;
34450let hasNewValue = 1;
34451let opNewValue = 0;
34452let isCVI = 1;
34453let DecoderNamespace = "EXT_mmvec";
34454}
34455def V6_vminuh_alt : HInst<
34456(outs HvxVR:$Vd32),
34457(ins HvxVR:$Vu32, HvxVR:$Vv32),
34458"$Vd32 = vminuh($Vu32,$Vv32)",
34459PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34460let hasNewValue = 1;
34461let opNewValue = 0;
34462let isCVI = 1;
34463let isPseudo = 1;
34464let isCodeGenOnly = 1;
34465let DecoderNamespace = "EXT_mmvec";
34466}
34467def V6_vminw : HInst<
34468(outs HvxVR:$Vd32),
34469(ins HvxVR:$Vu32, HvxVR:$Vv32),
34470"$Vd32.w = vmin($Vu32.w,$Vv32.w)",
34471tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34472let Inst{7-5} = 0b100;
34473let Inst{13-13} = 0b0;
34474let Inst{31-21} = 0b00011111000;
34475let hasNewValue = 1;
34476let opNewValue = 0;
34477let isCVI = 1;
34478let DecoderNamespace = "EXT_mmvec";
34479}
34480def V6_vminw_alt : HInst<
34481(outs HvxVR:$Vd32),
34482(ins HvxVR:$Vu32, HvxVR:$Vv32),
34483"$Vd32 = vminw($Vu32,$Vv32)",
34484PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34485let hasNewValue = 1;
34486let opNewValue = 0;
34487let isCVI = 1;
34488let isPseudo = 1;
34489let isCodeGenOnly = 1;
34490let DecoderNamespace = "EXT_mmvec";
34491}
34492def V6_vmpabus : HInst<
34493(outs HvxWR:$Vdd32),
34494(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34495"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
34496tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
34497let Inst{7-5} = 0b110;
34498let Inst{13-13} = 0b0;
34499let Inst{31-21} = 0b00011001001;
34500let hasNewValue = 1;
34501let opNewValue = 0;
34502let isCVI = 1;
34503let DecoderNamespace = "EXT_mmvec";
34504}
34505def V6_vmpabus_acc : HInst<
34506(outs HvxWR:$Vxx32),
34507(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34508"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
34509tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
34510let Inst{7-5} = 0b110;
34511let Inst{13-13} = 0b1;
34512let Inst{31-21} = 0b00011001001;
34513let hasNewValue = 1;
34514let opNewValue = 0;
34515let isAccumulator = 1;
34516let isCVI = 1;
34517let DecoderNamespace = "EXT_mmvec";
34518let Constraints = "$Vxx32 = $Vxx32in";
34519}
34520def V6_vmpabus_acc_alt : HInst<
34521(outs HvxWR:$Vxx32),
34522(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34523"$Vxx32 += vmpabus($Vuu32,$Rt32)",
34524PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34525let hasNewValue = 1;
34526let opNewValue = 0;
34527let isAccumulator = 1;
34528let isCVI = 1;
34529let isPseudo = 1;
34530let isCodeGenOnly = 1;
34531let DecoderNamespace = "EXT_mmvec";
34532let Constraints = "$Vxx32 = $Vxx32in";
34533}
34534def V6_vmpabus_alt : HInst<
34535(outs HvxWR:$Vdd32),
34536(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34537"$Vdd32 = vmpabus($Vuu32,$Rt32)",
34538PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34539let hasNewValue = 1;
34540let opNewValue = 0;
34541let isCVI = 1;
34542let isPseudo = 1;
34543let isCodeGenOnly = 1;
34544let DecoderNamespace = "EXT_mmvec";
34545}
34546def V6_vmpabusv : HInst<
34547(outs HvxWR:$Vdd32),
34548(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
34549"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
34550tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
34551let Inst{7-5} = 0b011;
34552let Inst{13-13} = 0b0;
34553let Inst{31-21} = 0b00011100001;
34554let hasNewValue = 1;
34555let opNewValue = 0;
34556let isCVI = 1;
34557let DecoderNamespace = "EXT_mmvec";
34558}
34559def V6_vmpabusv_alt : HInst<
34560(outs HvxWR:$Vdd32),
34561(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
34562"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
34563PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34564let hasNewValue = 1;
34565let opNewValue = 0;
34566let isCVI = 1;
34567let isPseudo = 1;
34568let isCodeGenOnly = 1;
34569let DecoderNamespace = "EXT_mmvec";
34570}
34571def V6_vmpabuu : HInst<
34572(outs HvxWR:$Vdd32),
34573(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34574"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
34575tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
34576let Inst{7-5} = 0b011;
34577let Inst{13-13} = 0b0;
34578let Inst{31-21} = 0b00011001011;
34579let hasNewValue = 1;
34580let opNewValue = 0;
34581let isCVI = 1;
34582let DecoderNamespace = "EXT_mmvec";
34583}
34584def V6_vmpabuu_acc : HInst<
34585(outs HvxWR:$Vxx32),
34586(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34587"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
34588tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
34589let Inst{7-5} = 0b100;
34590let Inst{13-13} = 0b1;
34591let Inst{31-21} = 0b00011001101;
34592let hasNewValue = 1;
34593let opNewValue = 0;
34594let isAccumulator = 1;
34595let isCVI = 1;
34596let DecoderNamespace = "EXT_mmvec";
34597let Constraints = "$Vxx32 = $Vxx32in";
34598}
34599def V6_vmpabuu_acc_alt : HInst<
34600(outs HvxWR:$Vxx32),
34601(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34602"$Vxx32 += vmpabuu($Vuu32,$Rt32)",
34603PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34604let hasNewValue = 1;
34605let opNewValue = 0;
34606let isAccumulator = 1;
34607let isCVI = 1;
34608let isPseudo = 1;
34609let isCodeGenOnly = 1;
34610let DecoderNamespace = "EXT_mmvec";
34611let Constraints = "$Vxx32 = $Vxx32in";
34612}
34613def V6_vmpabuu_alt : HInst<
34614(outs HvxWR:$Vdd32),
34615(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34616"$Vdd32 = vmpabuu($Vuu32,$Rt32)",
34617PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34618let hasNewValue = 1;
34619let opNewValue = 0;
34620let isCVI = 1;
34621let isPseudo = 1;
34622let isCodeGenOnly = 1;
34623let DecoderNamespace = "EXT_mmvec";
34624}
34625def V6_vmpabuuv : HInst<
34626(outs HvxWR:$Vdd32),
34627(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
34628"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
34629tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
34630let Inst{7-5} = 0b111;
34631let Inst{13-13} = 0b0;
34632let Inst{31-21} = 0b00011100111;
34633let hasNewValue = 1;
34634let opNewValue = 0;
34635let isCVI = 1;
34636let DecoderNamespace = "EXT_mmvec";
34637}
34638def V6_vmpabuuv_alt : HInst<
34639(outs HvxWR:$Vdd32),
34640(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
34641"$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
34642PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34643let hasNewValue = 1;
34644let opNewValue = 0;
34645let isCVI = 1;
34646let isPseudo = 1;
34647let isCodeGenOnly = 1;
34648let DecoderNamespace = "EXT_mmvec";
34649}
34650def V6_vmpahb : HInst<
34651(outs HvxWR:$Vdd32),
34652(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34653"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
34654tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
34655let Inst{7-5} = 0b111;
34656let Inst{13-13} = 0b0;
34657let Inst{31-21} = 0b00011001001;
34658let hasNewValue = 1;
34659let opNewValue = 0;
34660let isCVI = 1;
34661let DecoderNamespace = "EXT_mmvec";
34662}
34663def V6_vmpahb_acc : HInst<
34664(outs HvxWR:$Vxx32),
34665(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34666"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
34667tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
34668let Inst{7-5} = 0b111;
34669let Inst{13-13} = 0b1;
34670let Inst{31-21} = 0b00011001001;
34671let hasNewValue = 1;
34672let opNewValue = 0;
34673let isAccumulator = 1;
34674let isCVI = 1;
34675let DecoderNamespace = "EXT_mmvec";
34676let Constraints = "$Vxx32 = $Vxx32in";
34677}
34678def V6_vmpahb_acc_alt : HInst<
34679(outs HvxWR:$Vxx32),
34680(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34681"$Vxx32 += vmpahb($Vuu32,$Rt32)",
34682PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34683let hasNewValue = 1;
34684let opNewValue = 0;
34685let isAccumulator = 1;
34686let isCVI = 1;
34687let isPseudo = 1;
34688let isCodeGenOnly = 1;
34689let DecoderNamespace = "EXT_mmvec";
34690let Constraints = "$Vxx32 = $Vxx32in";
34691}
34692def V6_vmpahb_alt : HInst<
34693(outs HvxWR:$Vdd32),
34694(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34695"$Vdd32 = vmpahb($Vuu32,$Rt32)",
34696PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34697let hasNewValue = 1;
34698let opNewValue = 0;
34699let isCVI = 1;
34700let isPseudo = 1;
34701let isCodeGenOnly = 1;
34702let DecoderNamespace = "EXT_mmvec";
34703}
34704def V6_vmpahhsat : HInst<
34705(outs HvxVR:$Vx32),
34706(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34707"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
34708tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
34709let Inst{7-5} = 0b100;
34710let Inst{13-13} = 0b1;
34711let Inst{31-21} = 0b00011001100;
34712let hasNewValue = 1;
34713let opNewValue = 0;
34714let isCVI = 1;
34715let DecoderNamespace = "EXT_mmvec";
34716let Constraints = "$Vx32 = $Vx32in";
34717}
34718def V6_vmpauhb : HInst<
34719(outs HvxWR:$Vdd32),
34720(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34721"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
34722tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
34723let Inst{7-5} = 0b101;
34724let Inst{13-13} = 0b0;
34725let Inst{31-21} = 0b00011001100;
34726let hasNewValue = 1;
34727let opNewValue = 0;
34728let isCVI = 1;
34729let DecoderNamespace = "EXT_mmvec";
34730}
34731def V6_vmpauhb_acc : HInst<
34732(outs HvxWR:$Vxx32),
34733(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34734"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
34735tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
34736let Inst{7-5} = 0b010;
34737let Inst{13-13} = 0b1;
34738let Inst{31-21} = 0b00011001100;
34739let hasNewValue = 1;
34740let opNewValue = 0;
34741let isAccumulator = 1;
34742let isCVI = 1;
34743let DecoderNamespace = "EXT_mmvec";
34744let Constraints = "$Vxx32 = $Vxx32in";
34745}
34746def V6_vmpauhb_acc_alt : HInst<
34747(outs HvxWR:$Vxx32),
34748(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34749"$Vxx32 += vmpauhb($Vuu32,$Rt32)",
34750PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34751let hasNewValue = 1;
34752let opNewValue = 0;
34753let isAccumulator = 1;
34754let isCVI = 1;
34755let isPseudo = 1;
34756let isCodeGenOnly = 1;
34757let DecoderNamespace = "EXT_mmvec";
34758let Constraints = "$Vxx32 = $Vxx32in";
34759}
34760def V6_vmpauhb_alt : HInst<
34761(outs HvxWR:$Vdd32),
34762(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34763"$Vdd32 = vmpauhb($Vuu32,$Rt32)",
34764PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34765let hasNewValue = 1;
34766let opNewValue = 0;
34767let isCVI = 1;
34768let isPseudo = 1;
34769let isCodeGenOnly = 1;
34770let DecoderNamespace = "EXT_mmvec";
34771}
34772def V6_vmpauhuhsat : HInst<
34773(outs HvxVR:$Vx32),
34774(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34775"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
34776tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
34777let Inst{7-5} = 0b101;
34778let Inst{13-13} = 0b1;
34779let Inst{31-21} = 0b00011001100;
34780let hasNewValue = 1;
34781let opNewValue = 0;
34782let isCVI = 1;
34783let DecoderNamespace = "EXT_mmvec";
34784let Constraints = "$Vx32 = $Vx32in";
34785}
34786def V6_vmpsuhuhsat : HInst<
34787(outs HvxVR:$Vx32),
34788(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34789"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
34790tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
34791let Inst{7-5} = 0b110;
34792let Inst{13-13} = 0b1;
34793let Inst{31-21} = 0b00011001100;
34794let hasNewValue = 1;
34795let opNewValue = 0;
34796let isCVI = 1;
34797let DecoderNamespace = "EXT_mmvec";
34798let Constraints = "$Vx32 = $Vx32in";
34799}
34800def V6_vmpy_hf_hf : HInst<
34801(outs HvxVR:$Vd32),
34802(ins HvxVR:$Vu32, HvxVR:$Vv32),
34803"$Vd32.hf = vmpy($Vu32.hf,$Vv32.hf)",
34804tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
34805let Inst{7-5} = 0b011;
34806let Inst{13-13} = 0b1;
34807let Inst{31-21} = 0b00011111100;
34808let hasNewValue = 1;
34809let opNewValue = 0;
34810let isCVI = 1;
34811let DecoderNamespace = "EXT_mmvec";
34812}
34813def V6_vmpy_hf_hf_acc : HInst<
34814(outs HvxVR:$Vx32),
34815(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34816"$Vx32.hf += vmpy($Vu32.hf,$Vv32.hf)",
34817tc_a19b9305, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
34818let Inst{7-5} = 0b010;
34819let Inst{13-13} = 0b1;
34820let Inst{31-21} = 0b00011100010;
34821let hasNewValue = 1;
34822let opNewValue = 0;
34823let isAccumulator = 1;
34824let isCVI = 1;
34825let DecoderNamespace = "EXT_mmvec";
34826let Constraints = "$Vx32 = $Vx32in";
34827}
34828def V6_vmpy_qf16 : HInst<
34829(outs HvxVR:$Vd32),
34830(ins HvxVR:$Vu32, HvxVR:$Vv32),
34831"$Vd32.qf16 = vmpy($Vu32.qf16,$Vv32.qf16)",
34832tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34833let Inst{7-5} = 0b011;
34834let Inst{13-13} = 0b1;
34835let Inst{31-21} = 0b00011111111;
34836let hasNewValue = 1;
34837let opNewValue = 0;
34838let isCVI = 1;
34839let DecoderNamespace = "EXT_mmvec";
34840}
34841def V6_vmpy_qf16_hf : HInst<
34842(outs HvxVR:$Vd32),
34843(ins HvxVR:$Vu32, HvxVR:$Vv32),
34844"$Vd32.qf16 = vmpy($Vu32.hf,$Vv32.hf)",
34845tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34846let Inst{7-5} = 0b100;
34847let Inst{13-13} = 0b1;
34848let Inst{31-21} = 0b00011111111;
34849let hasNewValue = 1;
34850let opNewValue = 0;
34851let isCVI = 1;
34852let DecoderNamespace = "EXT_mmvec";
34853}
34854def V6_vmpy_qf16_mix_hf : HInst<
34855(outs HvxVR:$Vd32),
34856(ins HvxVR:$Vu32, HvxVR:$Vv32),
34857"$Vd32.qf16 = vmpy($Vu32.qf16,$Vv32.hf)",
34858tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34859let Inst{7-5} = 0b101;
34860let Inst{13-13} = 0b1;
34861let Inst{31-21} = 0b00011111111;
34862let hasNewValue = 1;
34863let opNewValue = 0;
34864let isCVI = 1;
34865let DecoderNamespace = "EXT_mmvec";
34866}
34867def V6_vmpy_qf32 : HInst<
34868(outs HvxVR:$Vd32),
34869(ins HvxVR:$Vu32, HvxVR:$Vv32),
34870"$Vd32.qf32 = vmpy($Vu32.qf32,$Vv32.qf32)",
34871tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34872let Inst{7-5} = 0b000;
34873let Inst{13-13} = 0b1;
34874let Inst{31-21} = 0b00011111111;
34875let hasNewValue = 1;
34876let opNewValue = 0;
34877let isCVI = 1;
34878let DecoderNamespace = "EXT_mmvec";
34879}
34880def V6_vmpy_qf32_hf : HInst<
34881(outs HvxWR:$Vdd32),
34882(ins HvxVR:$Vu32, HvxVR:$Vv32),
34883"$Vdd32.qf32 = vmpy($Vu32.hf,$Vv32.hf)",
34884tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
34885let Inst{7-5} = 0b111;
34886let Inst{13-13} = 0b1;
34887let Inst{31-21} = 0b00011111111;
34888let hasNewValue = 1;
34889let opNewValue = 0;
34890let isCVI = 1;
34891let DecoderNamespace = "EXT_mmvec";
34892}
34893def V6_vmpy_qf32_mix_hf : HInst<
34894(outs HvxWR:$Vdd32),
34895(ins HvxVR:$Vu32, HvxVR:$Vv32),
34896"$Vdd32.qf32 = vmpy($Vu32.qf16,$Vv32.hf)",
34897tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
34898let Inst{7-5} = 0b000;
34899let Inst{13-13} = 0b1;
34900let Inst{31-21} = 0b00011111100;
34901let hasNewValue = 1;
34902let opNewValue = 0;
34903let isCVI = 1;
34904let DecoderNamespace = "EXT_mmvec";
34905}
34906def V6_vmpy_qf32_qf16 : HInst<
34907(outs HvxWR:$Vdd32),
34908(ins HvxVR:$Vu32, HvxVR:$Vv32),
34909"$Vdd32.qf32 = vmpy($Vu32.qf16,$Vv32.qf16)",
34910tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
34911let Inst{7-5} = 0b110;
34912let Inst{13-13} = 0b1;
34913let Inst{31-21} = 0b00011111111;
34914let hasNewValue = 1;
34915let opNewValue = 0;
34916let isCVI = 1;
34917let DecoderNamespace = "EXT_mmvec";
34918}
34919def V6_vmpy_qf32_sf : HInst<
34920(outs HvxVR:$Vd32),
34921(ins HvxVR:$Vu32, HvxVR:$Vv32),
34922"$Vd32.qf32 = vmpy($Vu32.sf,$Vv32.sf)",
34923tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34924let Inst{7-5} = 0b001;
34925let Inst{13-13} = 0b1;
34926let Inst{31-21} = 0b00011111111;
34927let hasNewValue = 1;
34928let opNewValue = 0;
34929let isCVI = 1;
34930let DecoderNamespace = "EXT_mmvec";
34931}
34932def V6_vmpy_sf_hf : HInst<
34933(outs HvxWR:$Vdd32),
34934(ins HvxVR:$Vu32, HvxVR:$Vv32),
34935"$Vdd32.sf = vmpy($Vu32.hf,$Vv32.hf)",
34936tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
34937let Inst{7-5} = 0b010;
34938let Inst{13-13} = 0b1;
34939let Inst{31-21} = 0b00011111100;
34940let hasNewValue = 1;
34941let opNewValue = 0;
34942let isCVI = 1;
34943let DecoderNamespace = "EXT_mmvec";
34944}
34945def V6_vmpy_sf_hf_acc : HInst<
34946(outs HvxWR:$Vxx32),
34947(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34948"$Vxx32.sf += vmpy($Vu32.hf,$Vv32.hf)",
34949tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV68,UseHVXIEEEFP]> {
34950let Inst{7-5} = 0b001;
34951let Inst{13-13} = 0b1;
34952let Inst{31-21} = 0b00011100010;
34953let hasNewValue = 1;
34954let opNewValue = 0;
34955let isAccumulator = 1;
34956let isCVI = 1;
34957let DecoderNamespace = "EXT_mmvec";
34958let Constraints = "$Vxx32 = $Vxx32in";
34959}
34960def V6_vmpy_sf_sf : HInst<
34961(outs HvxVR:$Vd32),
34962(ins HvxVR:$Vu32, HvxVR:$Vv32),
34963"$Vd32.sf = vmpy($Vu32.sf,$Vv32.sf)",
34964tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
34965let Inst{7-5} = 0b001;
34966let Inst{13-13} = 0b1;
34967let Inst{31-21} = 0b00011111100;
34968let hasNewValue = 1;
34969let opNewValue = 0;
34970let isCVI = 1;
34971let DecoderNamespace = "EXT_mmvec";
34972}
34973def V6_vmpybus : HInst<
34974(outs HvxWR:$Vdd32),
34975(ins HvxVR:$Vu32, IntRegs:$Rt32),
34976"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
34977tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
34978let Inst{7-5} = 0b101;
34979let Inst{13-13} = 0b0;
34980let Inst{31-21} = 0b00011001001;
34981let hasNewValue = 1;
34982let opNewValue = 0;
34983let isCVI = 1;
34984let DecoderNamespace = "EXT_mmvec";
34985}
34986def V6_vmpybus_acc : HInst<
34987(outs HvxWR:$Vxx32),
34988(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34989"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
34990tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
34991let Inst{7-5} = 0b101;
34992let Inst{13-13} = 0b1;
34993let Inst{31-21} = 0b00011001001;
34994let hasNewValue = 1;
34995let opNewValue = 0;
34996let isAccumulator = 1;
34997let isCVI = 1;
34998let DecoderNamespace = "EXT_mmvec";
34999let Constraints = "$Vxx32 = $Vxx32in";
35000}
35001def V6_vmpybus_acc_alt : HInst<
35002(outs HvxWR:$Vxx32),
35003(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35004"$Vxx32 += vmpybus($Vu32,$Rt32)",
35005PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35006let hasNewValue = 1;
35007let opNewValue = 0;
35008let isAccumulator = 1;
35009let isCVI = 1;
35010let isPseudo = 1;
35011let isCodeGenOnly = 1;
35012let DecoderNamespace = "EXT_mmvec";
35013let Constraints = "$Vxx32 = $Vxx32in";
35014}
35015def V6_vmpybus_alt : HInst<
35016(outs HvxWR:$Vdd32),
35017(ins HvxVR:$Vu32, IntRegs:$Rt32),
35018"$Vdd32 = vmpybus($Vu32,$Rt32)",
35019PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35020let hasNewValue = 1;
35021let opNewValue = 0;
35022let isCVI = 1;
35023let isPseudo = 1;
35024let isCodeGenOnly = 1;
35025let DecoderNamespace = "EXT_mmvec";
35026}
35027def V6_vmpybusv : HInst<
35028(outs HvxWR:$Vdd32),
35029(ins HvxVR:$Vu32, HvxVR:$Vv32),
35030"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
35031tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35032let Inst{7-5} = 0b110;
35033let Inst{13-13} = 0b0;
35034let Inst{31-21} = 0b00011100000;
35035let hasNewValue = 1;
35036let opNewValue = 0;
35037let isCVI = 1;
35038let DecoderNamespace = "EXT_mmvec";
35039}
35040def V6_vmpybusv_acc : HInst<
35041(outs HvxWR:$Vxx32),
35042(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35043"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
35044tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35045let Inst{7-5} = 0b110;
35046let Inst{13-13} = 0b1;
35047let Inst{31-21} = 0b00011100000;
35048let hasNewValue = 1;
35049let opNewValue = 0;
35050let isAccumulator = 1;
35051let isCVI = 1;
35052let DecoderNamespace = "EXT_mmvec";
35053let Constraints = "$Vxx32 = $Vxx32in";
35054}
35055def V6_vmpybusv_acc_alt : HInst<
35056(outs HvxWR:$Vxx32),
35057(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35058"$Vxx32 += vmpybus($Vu32,$Vv32)",
35059PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35060let hasNewValue = 1;
35061let opNewValue = 0;
35062let isAccumulator = 1;
35063let isCVI = 1;
35064let isPseudo = 1;
35065let isCodeGenOnly = 1;
35066let DecoderNamespace = "EXT_mmvec";
35067let Constraints = "$Vxx32 = $Vxx32in";
35068}
35069def V6_vmpybusv_alt : HInst<
35070(outs HvxWR:$Vdd32),
35071(ins HvxVR:$Vu32, HvxVR:$Vv32),
35072"$Vdd32 = vmpybus($Vu32,$Vv32)",
35073PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35074let hasNewValue = 1;
35075let opNewValue = 0;
35076let isCVI = 1;
35077let isPseudo = 1;
35078let isCodeGenOnly = 1;
35079let DecoderNamespace = "EXT_mmvec";
35080}
35081def V6_vmpybv : HInst<
35082(outs HvxWR:$Vdd32),
35083(ins HvxVR:$Vu32, HvxVR:$Vv32),
35084"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
35085tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35086let Inst{7-5} = 0b100;
35087let Inst{13-13} = 0b0;
35088let Inst{31-21} = 0b00011100000;
35089let hasNewValue = 1;
35090let opNewValue = 0;
35091let isCVI = 1;
35092let DecoderNamespace = "EXT_mmvec";
35093}
35094def V6_vmpybv_acc : HInst<
35095(outs HvxWR:$Vxx32),
35096(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35097"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
35098tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35099let Inst{7-5} = 0b100;
35100let Inst{13-13} = 0b1;
35101let Inst{31-21} = 0b00011100000;
35102let hasNewValue = 1;
35103let opNewValue = 0;
35104let isAccumulator = 1;
35105let isCVI = 1;
35106let DecoderNamespace = "EXT_mmvec";
35107let Constraints = "$Vxx32 = $Vxx32in";
35108}
35109def V6_vmpybv_acc_alt : HInst<
35110(outs HvxWR:$Vxx32),
35111(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35112"$Vxx32 += vmpyb($Vu32,$Vv32)",
35113PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35114let hasNewValue = 1;
35115let opNewValue = 0;
35116let isAccumulator = 1;
35117let isCVI = 1;
35118let isPseudo = 1;
35119let isCodeGenOnly = 1;
35120let DecoderNamespace = "EXT_mmvec";
35121let Constraints = "$Vxx32 = $Vxx32in";
35122}
35123def V6_vmpybv_alt : HInst<
35124(outs HvxWR:$Vdd32),
35125(ins HvxVR:$Vu32, HvxVR:$Vv32),
35126"$Vdd32 = vmpyb($Vu32,$Vv32)",
35127PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35128let hasNewValue = 1;
35129let opNewValue = 0;
35130let isCVI = 1;
35131let isPseudo = 1;
35132let isCodeGenOnly = 1;
35133let DecoderNamespace = "EXT_mmvec";
35134}
35135def V6_vmpyewuh : HInst<
35136(outs HvxVR:$Vd32),
35137(ins HvxVR:$Vu32, HvxVR:$Vv32),
35138"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
35139tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35140let Inst{7-5} = 0b101;
35141let Inst{13-13} = 0b0;
35142let Inst{31-21} = 0b00011111111;
35143let hasNewValue = 1;
35144let opNewValue = 0;
35145let isCVI = 1;
35146let DecoderNamespace = "EXT_mmvec";
35147}
35148def V6_vmpyewuh_64 : HInst<
35149(outs HvxWR:$Vdd32),
35150(ins HvxVR:$Vu32, HvxVR:$Vv32),
35151"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
35152tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
35153let Inst{7-5} = 0b110;
35154let Inst{13-13} = 0b0;
35155let Inst{31-21} = 0b00011110101;
35156let hasNewValue = 1;
35157let opNewValue = 0;
35158let isCVI = 1;
35159let DecoderNamespace = "EXT_mmvec";
35160}
35161def V6_vmpyewuh_alt : HInst<
35162(outs HvxVR:$Vd32),
35163(ins HvxVR:$Vu32, HvxVR:$Vv32),
35164"$Vd32 = vmpyewuh($Vu32,$Vv32)",
35165PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35166let hasNewValue = 1;
35167let opNewValue = 0;
35168let isCVI = 1;
35169let isPseudo = 1;
35170let isCodeGenOnly = 1;
35171let DecoderNamespace = "EXT_mmvec";
35172}
35173def V6_vmpyh : HInst<
35174(outs HvxWR:$Vdd32),
35175(ins HvxVR:$Vu32, IntRegs:$Rt32),
35176"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
35177tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35178let Inst{7-5} = 0b000;
35179let Inst{13-13} = 0b0;
35180let Inst{31-21} = 0b00011001010;
35181let hasNewValue = 1;
35182let opNewValue = 0;
35183let isCVI = 1;
35184let DecoderNamespace = "EXT_mmvec";
35185}
35186def V6_vmpyh_acc : HInst<
35187(outs HvxWR:$Vxx32),
35188(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35189"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
35190tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
35191let Inst{7-5} = 0b110;
35192let Inst{13-13} = 0b1;
35193let Inst{31-21} = 0b00011001101;
35194let hasNewValue = 1;
35195let opNewValue = 0;
35196let isAccumulator = 1;
35197let isCVI = 1;
35198let DecoderNamespace = "EXT_mmvec";
35199let Constraints = "$Vxx32 = $Vxx32in";
35200}
35201def V6_vmpyh_acc_alt : HInst<
35202(outs HvxWR:$Vxx32),
35203(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35204"$Vxx32 += vmpyh($Vu32,$Rt32)",
35205PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35206let hasNewValue = 1;
35207let opNewValue = 0;
35208let isAccumulator = 1;
35209let isCVI = 1;
35210let isPseudo = 1;
35211let isCodeGenOnly = 1;
35212let DecoderNamespace = "EXT_mmvec";
35213let Constraints = "$Vxx32 = $Vxx32in";
35214}
35215def V6_vmpyh_alt : HInst<
35216(outs HvxWR:$Vdd32),
35217(ins HvxVR:$Vu32, IntRegs:$Rt32),
35218"$Vdd32 = vmpyh($Vu32,$Rt32)",
35219PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35220let hasNewValue = 1;
35221let opNewValue = 0;
35222let isCVI = 1;
35223let isPseudo = 1;
35224let isCodeGenOnly = 1;
35225let DecoderNamespace = "EXT_mmvec";
35226}
35227def V6_vmpyhsat_acc : HInst<
35228(outs HvxWR:$Vxx32),
35229(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35230"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
35231tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35232let Inst{7-5} = 0b000;
35233let Inst{13-13} = 0b1;
35234let Inst{31-21} = 0b00011001010;
35235let hasNewValue = 1;
35236let opNewValue = 0;
35237let isAccumulator = 1;
35238let isCVI = 1;
35239let DecoderNamespace = "EXT_mmvec";
35240let Constraints = "$Vxx32 = $Vxx32in";
35241}
35242def V6_vmpyhsat_acc_alt : HInst<
35243(outs HvxWR:$Vxx32),
35244(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35245"$Vxx32 += vmpyh($Vu32,$Rt32):sat",
35246PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35247let hasNewValue = 1;
35248let opNewValue = 0;
35249let isAccumulator = 1;
35250let isCVI = 1;
35251let isPseudo = 1;
35252let isCodeGenOnly = 1;
35253let DecoderNamespace = "EXT_mmvec";
35254let Constraints = "$Vxx32 = $Vxx32in";
35255}
35256def V6_vmpyhsrs : HInst<
35257(outs HvxVR:$Vd32),
35258(ins HvxVR:$Vu32, IntRegs:$Rt32),
35259"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
35260tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35261let Inst{7-5} = 0b010;
35262let Inst{13-13} = 0b0;
35263let Inst{31-21} = 0b00011001010;
35264let hasNewValue = 1;
35265let opNewValue = 0;
35266let isCVI = 1;
35267let DecoderNamespace = "EXT_mmvec";
35268}
35269def V6_vmpyhsrs_alt : HInst<
35270(outs HvxVR:$Vd32),
35271(ins HvxVR:$Vu32, IntRegs:$Rt32),
35272"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
35273PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35274let hasNewValue = 1;
35275let opNewValue = 0;
35276let isCVI = 1;
35277let isPseudo = 1;
35278let isCodeGenOnly = 1;
35279let DecoderNamespace = "EXT_mmvec";
35280}
35281def V6_vmpyhss : HInst<
35282(outs HvxVR:$Vd32),
35283(ins HvxVR:$Vu32, IntRegs:$Rt32),
35284"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
35285tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35286let Inst{7-5} = 0b001;
35287let Inst{13-13} = 0b0;
35288let Inst{31-21} = 0b00011001010;
35289let hasNewValue = 1;
35290let opNewValue = 0;
35291let isCVI = 1;
35292let DecoderNamespace = "EXT_mmvec";
35293}
35294def V6_vmpyhss_alt : HInst<
35295(outs HvxVR:$Vd32),
35296(ins HvxVR:$Vu32, IntRegs:$Rt32),
35297"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
35298PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35299let hasNewValue = 1;
35300let opNewValue = 0;
35301let isCVI = 1;
35302let isPseudo = 1;
35303let isCodeGenOnly = 1;
35304let DecoderNamespace = "EXT_mmvec";
35305}
35306def V6_vmpyhus : HInst<
35307(outs HvxWR:$Vdd32),
35308(ins HvxVR:$Vu32, HvxVR:$Vv32),
35309"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
35310tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35311let Inst{7-5} = 0b010;
35312let Inst{13-13} = 0b0;
35313let Inst{31-21} = 0b00011100001;
35314let hasNewValue = 1;
35315let opNewValue = 0;
35316let isCVI = 1;
35317let DecoderNamespace = "EXT_mmvec";
35318}
35319def V6_vmpyhus_acc : HInst<
35320(outs HvxWR:$Vxx32),
35321(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35322"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
35323tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35324let Inst{7-5} = 0b001;
35325let Inst{13-13} = 0b1;
35326let Inst{31-21} = 0b00011100001;
35327let hasNewValue = 1;
35328let opNewValue = 0;
35329let isAccumulator = 1;
35330let isCVI = 1;
35331let DecoderNamespace = "EXT_mmvec";
35332let Constraints = "$Vxx32 = $Vxx32in";
35333}
35334def V6_vmpyhus_acc_alt : HInst<
35335(outs HvxWR:$Vxx32),
35336(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35337"$Vxx32 += vmpyhus($Vu32,$Vv32)",
35338PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35339let hasNewValue = 1;
35340let opNewValue = 0;
35341let isAccumulator = 1;
35342let isCVI = 1;
35343let isPseudo = 1;
35344let isCodeGenOnly = 1;
35345let DecoderNamespace = "EXT_mmvec";
35346let Constraints = "$Vxx32 = $Vxx32in";
35347}
35348def V6_vmpyhus_alt : HInst<
35349(outs HvxWR:$Vdd32),
35350(ins HvxVR:$Vu32, HvxVR:$Vv32),
35351"$Vdd32 = vmpyhus($Vu32,$Vv32)",
35352PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35353let hasNewValue = 1;
35354let opNewValue = 0;
35355let isCVI = 1;
35356let isPseudo = 1;
35357let isCodeGenOnly = 1;
35358let DecoderNamespace = "EXT_mmvec";
35359}
35360def V6_vmpyhv : HInst<
35361(outs HvxWR:$Vdd32),
35362(ins HvxVR:$Vu32, HvxVR:$Vv32),
35363"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
35364tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35365let Inst{7-5} = 0b111;
35366let Inst{13-13} = 0b0;
35367let Inst{31-21} = 0b00011100000;
35368let hasNewValue = 1;
35369let opNewValue = 0;
35370let isCVI = 1;
35371let DecoderNamespace = "EXT_mmvec";
35372}
35373def V6_vmpyhv_acc : HInst<
35374(outs HvxWR:$Vxx32),
35375(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35376"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
35377tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35378let Inst{7-5} = 0b111;
35379let Inst{13-13} = 0b1;
35380let Inst{31-21} = 0b00011100000;
35381let hasNewValue = 1;
35382let opNewValue = 0;
35383let isAccumulator = 1;
35384let isCVI = 1;
35385let DecoderNamespace = "EXT_mmvec";
35386let Constraints = "$Vxx32 = $Vxx32in";
35387}
35388def V6_vmpyhv_acc_alt : HInst<
35389(outs HvxWR:$Vxx32),
35390(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35391"$Vxx32 += vmpyh($Vu32,$Vv32)",
35392PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35393let hasNewValue = 1;
35394let opNewValue = 0;
35395let isAccumulator = 1;
35396let isCVI = 1;
35397let isPseudo = 1;
35398let isCodeGenOnly = 1;
35399let DecoderNamespace = "EXT_mmvec";
35400let Constraints = "$Vxx32 = $Vxx32in";
35401}
35402def V6_vmpyhv_alt : HInst<
35403(outs HvxWR:$Vdd32),
35404(ins HvxVR:$Vu32, HvxVR:$Vv32),
35405"$Vdd32 = vmpyh($Vu32,$Vv32)",
35406PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35407let hasNewValue = 1;
35408let opNewValue = 0;
35409let isCVI = 1;
35410let isPseudo = 1;
35411let isCodeGenOnly = 1;
35412let DecoderNamespace = "EXT_mmvec";
35413}
35414def V6_vmpyhvsrs : HInst<
35415(outs HvxVR:$Vd32),
35416(ins HvxVR:$Vu32, HvxVR:$Vv32),
35417"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
35418tc_73efe966, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35419let Inst{7-5} = 0b001;
35420let Inst{13-13} = 0b0;
35421let Inst{31-21} = 0b00011100001;
35422let hasNewValue = 1;
35423let opNewValue = 0;
35424let isCVI = 1;
35425let DecoderNamespace = "EXT_mmvec";
35426}
35427def V6_vmpyhvsrs_alt : HInst<
35428(outs HvxVR:$Vd32),
35429(ins HvxVR:$Vu32, HvxVR:$Vv32),
35430"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
35431PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35432let hasNewValue = 1;
35433let opNewValue = 0;
35434let isCVI = 1;
35435let isPseudo = 1;
35436let isCodeGenOnly = 1;
35437let DecoderNamespace = "EXT_mmvec";
35438}
35439def V6_vmpyieoh : HInst<
35440(outs HvxVR:$Vd32),
35441(ins HvxVR:$Vu32, HvxVR:$Vv32),
35442"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
35443tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35444let Inst{7-5} = 0b000;
35445let Inst{13-13} = 0b0;
35446let Inst{31-21} = 0b00011111011;
35447let hasNewValue = 1;
35448let opNewValue = 0;
35449let isCVI = 1;
35450let DecoderNamespace = "EXT_mmvec";
35451}
35452def V6_vmpyiewh_acc : HInst<
35453(outs HvxVR:$Vx32),
35454(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35455"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
35456tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35457let Inst{7-5} = 0b000;
35458let Inst{13-13} = 0b1;
35459let Inst{31-21} = 0b00011100010;
35460let hasNewValue = 1;
35461let opNewValue = 0;
35462let isAccumulator = 1;
35463let isCVI = 1;
35464let DecoderNamespace = "EXT_mmvec";
35465let Constraints = "$Vx32 = $Vx32in";
35466}
35467def V6_vmpyiewh_acc_alt : HInst<
35468(outs HvxVR:$Vx32),
35469(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35470"$Vx32 += vmpyiewh($Vu32,$Vv32)",
35471PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35472let hasNewValue = 1;
35473let opNewValue = 0;
35474let isAccumulator = 1;
35475let isCVI = 1;
35476let isPseudo = 1;
35477let isCodeGenOnly = 1;
35478let DecoderNamespace = "EXT_mmvec";
35479let Constraints = "$Vx32 = $Vx32in";
35480}
35481def V6_vmpyiewuh : HInst<
35482(outs HvxVR:$Vd32),
35483(ins HvxVR:$Vu32, HvxVR:$Vv32),
35484"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
35485tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35486let Inst{7-5} = 0b000;
35487let Inst{13-13} = 0b0;
35488let Inst{31-21} = 0b00011111110;
35489let hasNewValue = 1;
35490let opNewValue = 0;
35491let isCVI = 1;
35492let DecoderNamespace = "EXT_mmvec";
35493}
35494def V6_vmpyiewuh_acc : HInst<
35495(outs HvxVR:$Vx32),
35496(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35497"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
35498tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35499let Inst{7-5} = 0b101;
35500let Inst{13-13} = 0b1;
35501let Inst{31-21} = 0b00011100001;
35502let hasNewValue = 1;
35503let opNewValue = 0;
35504let isAccumulator = 1;
35505let isCVI = 1;
35506let DecoderNamespace = "EXT_mmvec";
35507let Constraints = "$Vx32 = $Vx32in";
35508}
35509def V6_vmpyiewuh_acc_alt : HInst<
35510(outs HvxVR:$Vx32),
35511(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35512"$Vx32 += vmpyiewuh($Vu32,$Vv32)",
35513PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35514let hasNewValue = 1;
35515let opNewValue = 0;
35516let isAccumulator = 1;
35517let isCVI = 1;
35518let isPseudo = 1;
35519let isCodeGenOnly = 1;
35520let DecoderNamespace = "EXT_mmvec";
35521let Constraints = "$Vx32 = $Vx32in";
35522}
35523def V6_vmpyiewuh_alt : HInst<
35524(outs HvxVR:$Vd32),
35525(ins HvxVR:$Vu32, HvxVR:$Vv32),
35526"$Vd32 = vmpyiewuh($Vu32,$Vv32)",
35527PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35528let hasNewValue = 1;
35529let opNewValue = 0;
35530let isCVI = 1;
35531let isPseudo = 1;
35532let isCodeGenOnly = 1;
35533let DecoderNamespace = "EXT_mmvec";
35534}
35535def V6_vmpyih : HInst<
35536(outs HvxVR:$Vd32),
35537(ins HvxVR:$Vu32, HvxVR:$Vv32),
35538"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
35539tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35540let Inst{7-5} = 0b100;
35541let Inst{13-13} = 0b0;
35542let Inst{31-21} = 0b00011100001;
35543let hasNewValue = 1;
35544let opNewValue = 0;
35545let isCVI = 1;
35546let DecoderNamespace = "EXT_mmvec";
35547}
35548def V6_vmpyih_acc : HInst<
35549(outs HvxVR:$Vx32),
35550(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35551"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
35552tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35553let Inst{7-5} = 0b100;
35554let Inst{13-13} = 0b1;
35555let Inst{31-21} = 0b00011100001;
35556let hasNewValue = 1;
35557let opNewValue = 0;
35558let isAccumulator = 1;
35559let isCVI = 1;
35560let DecoderNamespace = "EXT_mmvec";
35561let Constraints = "$Vx32 = $Vx32in";
35562}
35563def V6_vmpyih_acc_alt : HInst<
35564(outs HvxVR:$Vx32),
35565(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35566"$Vx32 += vmpyih($Vu32,$Vv32)",
35567PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35568let hasNewValue = 1;
35569let opNewValue = 0;
35570let isAccumulator = 1;
35571let isCVI = 1;
35572let isPseudo = 1;
35573let isCodeGenOnly = 1;
35574let DecoderNamespace = "EXT_mmvec";
35575let Constraints = "$Vx32 = $Vx32in";
35576}
35577def V6_vmpyih_alt : HInst<
35578(outs HvxVR:$Vd32),
35579(ins HvxVR:$Vu32, HvxVR:$Vv32),
35580"$Vd32 = vmpyih($Vu32,$Vv32)",
35581PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35582let hasNewValue = 1;
35583let opNewValue = 0;
35584let isCVI = 1;
35585let isPseudo = 1;
35586let isCodeGenOnly = 1;
35587let DecoderNamespace = "EXT_mmvec";
35588}
35589def V6_vmpyihb : HInst<
35590(outs HvxVR:$Vd32),
35591(ins HvxVR:$Vu32, IntRegs:$Rt32),
35592"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
35593tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35594let Inst{7-5} = 0b000;
35595let Inst{13-13} = 0b0;
35596let Inst{31-21} = 0b00011001011;
35597let hasNewValue = 1;
35598let opNewValue = 0;
35599let isCVI = 1;
35600let DecoderNamespace = "EXT_mmvec";
35601}
35602def V6_vmpyihb_acc : HInst<
35603(outs HvxVR:$Vx32),
35604(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35605"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
35606tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
35607let Inst{7-5} = 0b001;
35608let Inst{13-13} = 0b1;
35609let Inst{31-21} = 0b00011001011;
35610let hasNewValue = 1;
35611let opNewValue = 0;
35612let isAccumulator = 1;
35613let isCVI = 1;
35614let DecoderNamespace = "EXT_mmvec";
35615let Constraints = "$Vx32 = $Vx32in";
35616}
35617def V6_vmpyihb_acc_alt : HInst<
35618(outs HvxVR:$Vx32),
35619(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35620"$Vx32 += vmpyihb($Vu32,$Rt32)",
35621PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35622let hasNewValue = 1;
35623let opNewValue = 0;
35624let isAccumulator = 1;
35625let isCVI = 1;
35626let isPseudo = 1;
35627let isCodeGenOnly = 1;
35628let DecoderNamespace = "EXT_mmvec";
35629let Constraints = "$Vx32 = $Vx32in";
35630}
35631def V6_vmpyihb_alt : HInst<
35632(outs HvxVR:$Vd32),
35633(ins HvxVR:$Vu32, IntRegs:$Rt32),
35634"$Vd32 = vmpyihb($Vu32,$Rt32)",
35635PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35636let hasNewValue = 1;
35637let opNewValue = 0;
35638let isCVI = 1;
35639let isPseudo = 1;
35640let isCodeGenOnly = 1;
35641let DecoderNamespace = "EXT_mmvec";
35642}
35643def V6_vmpyiowh : HInst<
35644(outs HvxVR:$Vd32),
35645(ins HvxVR:$Vu32, HvxVR:$Vv32),
35646"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
35647tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35648let Inst{7-5} = 0b001;
35649let Inst{13-13} = 0b0;
35650let Inst{31-21} = 0b00011111110;
35651let hasNewValue = 1;
35652let opNewValue = 0;
35653let isCVI = 1;
35654let DecoderNamespace = "EXT_mmvec";
35655}
35656def V6_vmpyiowh_alt : HInst<
35657(outs HvxVR:$Vd32),
35658(ins HvxVR:$Vu32, HvxVR:$Vv32),
35659"$Vd32 = vmpyiowh($Vu32,$Vv32)",
35660PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35661let hasNewValue = 1;
35662let opNewValue = 0;
35663let isCVI = 1;
35664let isPseudo = 1;
35665let isCodeGenOnly = 1;
35666let DecoderNamespace = "EXT_mmvec";
35667}
35668def V6_vmpyiwb : HInst<
35669(outs HvxVR:$Vd32),
35670(ins HvxVR:$Vu32, IntRegs:$Rt32),
35671"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
35672tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35673let Inst{7-5} = 0b000;
35674let Inst{13-13} = 0b0;
35675let Inst{31-21} = 0b00011001101;
35676let hasNewValue = 1;
35677let opNewValue = 0;
35678let isCVI = 1;
35679let DecoderNamespace = "EXT_mmvec";
35680}
35681def V6_vmpyiwb_acc : HInst<
35682(outs HvxVR:$Vx32),
35683(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35684"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
35685tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
35686let Inst{7-5} = 0b010;
35687let Inst{13-13} = 0b1;
35688let Inst{31-21} = 0b00011001010;
35689let hasNewValue = 1;
35690let opNewValue = 0;
35691let isAccumulator = 1;
35692let isCVI = 1;
35693let DecoderNamespace = "EXT_mmvec";
35694let Constraints = "$Vx32 = $Vx32in";
35695}
35696def V6_vmpyiwb_acc_alt : HInst<
35697(outs HvxVR:$Vx32),
35698(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35699"$Vx32 += vmpyiwb($Vu32,$Rt32)",
35700PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35701let hasNewValue = 1;
35702let opNewValue = 0;
35703let isAccumulator = 1;
35704let isCVI = 1;
35705let isPseudo = 1;
35706let isCodeGenOnly = 1;
35707let DecoderNamespace = "EXT_mmvec";
35708let Constraints = "$Vx32 = $Vx32in";
35709}
35710def V6_vmpyiwb_alt : HInst<
35711(outs HvxVR:$Vd32),
35712(ins HvxVR:$Vu32, IntRegs:$Rt32),
35713"$Vd32 = vmpyiwb($Vu32,$Rt32)",
35714PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35715let hasNewValue = 1;
35716let opNewValue = 0;
35717let isCVI = 1;
35718let isPseudo = 1;
35719let isCodeGenOnly = 1;
35720let DecoderNamespace = "EXT_mmvec";
35721}
35722def V6_vmpyiwh : HInst<
35723(outs HvxVR:$Vd32),
35724(ins HvxVR:$Vu32, IntRegs:$Rt32),
35725"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
35726tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
35727let Inst{7-5} = 0b111;
35728let Inst{13-13} = 0b0;
35729let Inst{31-21} = 0b00011001100;
35730let hasNewValue = 1;
35731let opNewValue = 0;
35732let isCVI = 1;
35733let DecoderNamespace = "EXT_mmvec";
35734}
35735def V6_vmpyiwh_acc : HInst<
35736(outs HvxVR:$Vx32),
35737(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35738"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
35739tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
35740let Inst{7-5} = 0b011;
35741let Inst{13-13} = 0b1;
35742let Inst{31-21} = 0b00011001010;
35743let hasNewValue = 1;
35744let opNewValue = 0;
35745let isAccumulator = 1;
35746let isCVI = 1;
35747let DecoderNamespace = "EXT_mmvec";
35748let Constraints = "$Vx32 = $Vx32in";
35749}
35750def V6_vmpyiwh_acc_alt : HInst<
35751(outs HvxVR:$Vx32),
35752(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35753"$Vx32 += vmpyiwh($Vu32,$Rt32)",
35754PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35755let hasNewValue = 1;
35756let opNewValue = 0;
35757let isAccumulator = 1;
35758let isCVI = 1;
35759let isPseudo = 1;
35760let isCodeGenOnly = 1;
35761let DecoderNamespace = "EXT_mmvec";
35762let Constraints = "$Vx32 = $Vx32in";
35763}
35764def V6_vmpyiwh_alt : HInst<
35765(outs HvxVR:$Vd32),
35766(ins HvxVR:$Vu32, IntRegs:$Rt32),
35767"$Vd32 = vmpyiwh($Vu32,$Rt32)",
35768PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35769let hasNewValue = 1;
35770let opNewValue = 0;
35771let isCVI = 1;
35772let isPseudo = 1;
35773let isCodeGenOnly = 1;
35774let DecoderNamespace = "EXT_mmvec";
35775}
35776def V6_vmpyiwub : HInst<
35777(outs HvxVR:$Vd32),
35778(ins HvxVR:$Vu32, IntRegs:$Rt32),
35779"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
35780tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
35781let Inst{7-5} = 0b110;
35782let Inst{13-13} = 0b0;
35783let Inst{31-21} = 0b00011001100;
35784let hasNewValue = 1;
35785let opNewValue = 0;
35786let isCVI = 1;
35787let DecoderNamespace = "EXT_mmvec";
35788}
35789def V6_vmpyiwub_acc : HInst<
35790(outs HvxVR:$Vx32),
35791(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35792"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
35793tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
35794let Inst{7-5} = 0b001;
35795let Inst{13-13} = 0b1;
35796let Inst{31-21} = 0b00011001100;
35797let hasNewValue = 1;
35798let opNewValue = 0;
35799let isAccumulator = 1;
35800let isCVI = 1;
35801let DecoderNamespace = "EXT_mmvec";
35802let Constraints = "$Vx32 = $Vx32in";
35803}
35804def V6_vmpyiwub_acc_alt : HInst<
35805(outs HvxVR:$Vx32),
35806(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35807"$Vx32 += vmpyiwub($Vu32,$Rt32)",
35808PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35809let hasNewValue = 1;
35810let opNewValue = 0;
35811let isAccumulator = 1;
35812let isCVI = 1;
35813let isPseudo = 1;
35814let isCodeGenOnly = 1;
35815let DecoderNamespace = "EXT_mmvec";
35816let Constraints = "$Vx32 = $Vx32in";
35817}
35818def V6_vmpyiwub_alt : HInst<
35819(outs HvxVR:$Vd32),
35820(ins HvxVR:$Vu32, IntRegs:$Rt32),
35821"$Vd32 = vmpyiwub($Vu32,$Rt32)",
35822PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35823let hasNewValue = 1;
35824let opNewValue = 0;
35825let isCVI = 1;
35826let isPseudo = 1;
35827let isCodeGenOnly = 1;
35828let DecoderNamespace = "EXT_mmvec";
35829}
35830def V6_vmpyowh : HInst<
35831(outs HvxVR:$Vd32),
35832(ins HvxVR:$Vu32, HvxVR:$Vv32),
35833"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
35834tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35835let Inst{7-5} = 0b111;
35836let Inst{13-13} = 0b0;
35837let Inst{31-21} = 0b00011111111;
35838let hasNewValue = 1;
35839let opNewValue = 0;
35840let isCVI = 1;
35841let DecoderNamespace = "EXT_mmvec";
35842}
35843def V6_vmpyowh_64_acc : HInst<
35844(outs HvxWR:$Vxx32),
35845(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35846"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
35847tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
35848let Inst{7-5} = 0b011;
35849let Inst{13-13} = 0b1;
35850let Inst{31-21} = 0b00011100001;
35851let hasNewValue = 1;
35852let opNewValue = 0;
35853let isAccumulator = 1;
35854let isCVI = 1;
35855let DecoderNamespace = "EXT_mmvec";
35856let Constraints = "$Vxx32 = $Vxx32in";
35857}
35858def V6_vmpyowh_alt : HInst<
35859(outs HvxVR:$Vd32),
35860(ins HvxVR:$Vu32, HvxVR:$Vv32),
35861"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
35862PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35863let hasNewValue = 1;
35864let opNewValue = 0;
35865let isCVI = 1;
35866let isPseudo = 1;
35867let isCodeGenOnly = 1;
35868let DecoderNamespace = "EXT_mmvec";
35869}
35870def V6_vmpyowh_rnd : HInst<
35871(outs HvxVR:$Vd32),
35872(ins HvxVR:$Vu32, HvxVR:$Vv32),
35873"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
35874tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35875let Inst{7-5} = 0b000;
35876let Inst{13-13} = 0b0;
35877let Inst{31-21} = 0b00011111010;
35878let hasNewValue = 1;
35879let opNewValue = 0;
35880let isCVI = 1;
35881let DecoderNamespace = "EXT_mmvec";
35882}
35883def V6_vmpyowh_rnd_alt : HInst<
35884(outs HvxVR:$Vd32),
35885(ins HvxVR:$Vu32, HvxVR:$Vv32),
35886"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
35887PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35888let hasNewValue = 1;
35889let opNewValue = 0;
35890let isCVI = 1;
35891let isPseudo = 1;
35892let isCodeGenOnly = 1;
35893let DecoderNamespace = "EXT_mmvec";
35894}
35895def V6_vmpyowh_rnd_sacc : HInst<
35896(outs HvxVR:$Vx32),
35897(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35898"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
35899tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35900let Inst{7-5} = 0b111;
35901let Inst{13-13} = 0b1;
35902let Inst{31-21} = 0b00011100001;
35903let hasNewValue = 1;
35904let opNewValue = 0;
35905let isAccumulator = 1;
35906let isCVI = 1;
35907let DecoderNamespace = "EXT_mmvec";
35908let Constraints = "$Vx32 = $Vx32in";
35909}
35910def V6_vmpyowh_rnd_sacc_alt : HInst<
35911(outs HvxVR:$Vx32),
35912(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35913"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
35914PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35915let hasNewValue = 1;
35916let opNewValue = 0;
35917let isAccumulator = 1;
35918let isCVI = 1;
35919let isPseudo = 1;
35920let DecoderNamespace = "EXT_mmvec";
35921let Constraints = "$Vx32 = $Vx32in";
35922}
35923def V6_vmpyowh_sacc : HInst<
35924(outs HvxVR:$Vx32),
35925(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35926"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
35927tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35928let Inst{7-5} = 0b110;
35929let Inst{13-13} = 0b1;
35930let Inst{31-21} = 0b00011100001;
35931let hasNewValue = 1;
35932let opNewValue = 0;
35933let isAccumulator = 1;
35934let isCVI = 1;
35935let DecoderNamespace = "EXT_mmvec";
35936let Constraints = "$Vx32 = $Vx32in";
35937}
35938def V6_vmpyowh_sacc_alt : HInst<
35939(outs HvxVR:$Vx32),
35940(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35941"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
35942PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35943let hasNewValue = 1;
35944let opNewValue = 0;
35945let isAccumulator = 1;
35946let isCVI = 1;
35947let isPseudo = 1;
35948let DecoderNamespace = "EXT_mmvec";
35949let Constraints = "$Vx32 = $Vx32in";
35950}
35951def V6_vmpyub : HInst<
35952(outs HvxWR:$Vdd32),
35953(ins HvxVR:$Vu32, IntRegs:$Rt32),
35954"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
35955tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35956let Inst{7-5} = 0b000;
35957let Inst{13-13} = 0b0;
35958let Inst{31-21} = 0b00011001110;
35959let hasNewValue = 1;
35960let opNewValue = 0;
35961let isCVI = 1;
35962let DecoderNamespace = "EXT_mmvec";
35963}
35964def V6_vmpyub_acc : HInst<
35965(outs HvxWR:$Vxx32),
35966(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35967"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
35968tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35969let Inst{7-5} = 0b000;
35970let Inst{13-13} = 0b1;
35971let Inst{31-21} = 0b00011001100;
35972let hasNewValue = 1;
35973let opNewValue = 0;
35974let isAccumulator = 1;
35975let isCVI = 1;
35976let DecoderNamespace = "EXT_mmvec";
35977let Constraints = "$Vxx32 = $Vxx32in";
35978}
35979def V6_vmpyub_acc_alt : HInst<
35980(outs HvxWR:$Vxx32),
35981(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35982"$Vxx32 += vmpyub($Vu32,$Rt32)",
35983PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35984let hasNewValue = 1;
35985let opNewValue = 0;
35986let isAccumulator = 1;
35987let isCVI = 1;
35988let isPseudo = 1;
35989let isCodeGenOnly = 1;
35990let DecoderNamespace = "EXT_mmvec";
35991let Constraints = "$Vxx32 = $Vxx32in";
35992}
35993def V6_vmpyub_alt : HInst<
35994(outs HvxWR:$Vdd32),
35995(ins HvxVR:$Vu32, IntRegs:$Rt32),
35996"$Vdd32 = vmpyub($Vu32,$Rt32)",
35997PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35998let hasNewValue = 1;
35999let opNewValue = 0;
36000let isCVI = 1;
36001let isPseudo = 1;
36002let isCodeGenOnly = 1;
36003let DecoderNamespace = "EXT_mmvec";
36004}
36005def V6_vmpyubv : HInst<
36006(outs HvxWR:$Vdd32),
36007(ins HvxVR:$Vu32, HvxVR:$Vv32),
36008"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
36009tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36010let Inst{7-5} = 0b101;
36011let Inst{13-13} = 0b0;
36012let Inst{31-21} = 0b00011100000;
36013let hasNewValue = 1;
36014let opNewValue = 0;
36015let isCVI = 1;
36016let DecoderNamespace = "EXT_mmvec";
36017}
36018def V6_vmpyubv_acc : HInst<
36019(outs HvxWR:$Vxx32),
36020(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36021"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
36022tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
36023let Inst{7-5} = 0b101;
36024let Inst{13-13} = 0b1;
36025let Inst{31-21} = 0b00011100000;
36026let hasNewValue = 1;
36027let opNewValue = 0;
36028let isAccumulator = 1;
36029let isCVI = 1;
36030let DecoderNamespace = "EXT_mmvec";
36031let Constraints = "$Vxx32 = $Vxx32in";
36032}
36033def V6_vmpyubv_acc_alt : HInst<
36034(outs HvxWR:$Vxx32),
36035(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36036"$Vxx32 += vmpyub($Vu32,$Vv32)",
36037PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36038let hasNewValue = 1;
36039let opNewValue = 0;
36040let isAccumulator = 1;
36041let isCVI = 1;
36042let isPseudo = 1;
36043let isCodeGenOnly = 1;
36044let DecoderNamespace = "EXT_mmvec";
36045let Constraints = "$Vxx32 = $Vxx32in";
36046}
36047def V6_vmpyubv_alt : HInst<
36048(outs HvxWR:$Vdd32),
36049(ins HvxVR:$Vu32, HvxVR:$Vv32),
36050"$Vdd32 = vmpyub($Vu32,$Vv32)",
36051PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36052let hasNewValue = 1;
36053let opNewValue = 0;
36054let isCVI = 1;
36055let isPseudo = 1;
36056let isCodeGenOnly = 1;
36057let DecoderNamespace = "EXT_mmvec";
36058}
36059def V6_vmpyuh : HInst<
36060(outs HvxWR:$Vdd32),
36061(ins HvxVR:$Vu32, IntRegs:$Rt32),
36062"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
36063tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
36064let Inst{7-5} = 0b011;
36065let Inst{13-13} = 0b0;
36066let Inst{31-21} = 0b00011001010;
36067let hasNewValue = 1;
36068let opNewValue = 0;
36069let isCVI = 1;
36070let DecoderNamespace = "EXT_mmvec";
36071}
36072def V6_vmpyuh_acc : HInst<
36073(outs HvxWR:$Vxx32),
36074(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36075"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
36076tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
36077let Inst{7-5} = 0b001;
36078let Inst{13-13} = 0b1;
36079let Inst{31-21} = 0b00011001010;
36080let hasNewValue = 1;
36081let opNewValue = 0;
36082let isAccumulator = 1;
36083let isCVI = 1;
36084let DecoderNamespace = "EXT_mmvec";
36085let Constraints = "$Vxx32 = $Vxx32in";
36086}
36087def V6_vmpyuh_acc_alt : HInst<
36088(outs HvxWR:$Vxx32),
36089(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36090"$Vxx32 += vmpyuh($Vu32,$Rt32)",
36091PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36092let hasNewValue = 1;
36093let opNewValue = 0;
36094let isAccumulator = 1;
36095let isCVI = 1;
36096let isPseudo = 1;
36097let isCodeGenOnly = 1;
36098let DecoderNamespace = "EXT_mmvec";
36099let Constraints = "$Vxx32 = $Vxx32in";
36100}
36101def V6_vmpyuh_alt : HInst<
36102(outs HvxWR:$Vdd32),
36103(ins HvxVR:$Vu32, IntRegs:$Rt32),
36104"$Vdd32 = vmpyuh($Vu32,$Rt32)",
36105PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36106let hasNewValue = 1;
36107let opNewValue = 0;
36108let isCVI = 1;
36109let isPseudo = 1;
36110let isCodeGenOnly = 1;
36111let DecoderNamespace = "EXT_mmvec";
36112}
36113def V6_vmpyuhe : HInst<
36114(outs HvxVR:$Vd32),
36115(ins HvxVR:$Vu32, IntRegs:$Rt32),
36116"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
36117tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
36118let Inst{7-5} = 0b010;
36119let Inst{13-13} = 0b0;
36120let Inst{31-21} = 0b00011001011;
36121let hasNewValue = 1;
36122let opNewValue = 0;
36123let isCVI = 1;
36124let DecoderNamespace = "EXT_mmvec";
36125}
36126def V6_vmpyuhe_acc : HInst<
36127(outs HvxVR:$Vx32),
36128(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36129"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
36130tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
36131let Inst{7-5} = 0b011;
36132let Inst{13-13} = 0b1;
36133let Inst{31-21} = 0b00011001100;
36134let hasNewValue = 1;
36135let opNewValue = 0;
36136let isAccumulator = 1;
36137let isCVI = 1;
36138let DecoderNamespace = "EXT_mmvec";
36139let Constraints = "$Vx32 = $Vx32in";
36140}
36141def V6_vmpyuhv : HInst<
36142(outs HvxWR:$Vdd32),
36143(ins HvxVR:$Vu32, HvxVR:$Vv32),
36144"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
36145tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36146let Inst{7-5} = 0b000;
36147let Inst{13-13} = 0b0;
36148let Inst{31-21} = 0b00011100001;
36149let hasNewValue = 1;
36150let opNewValue = 0;
36151let isCVI = 1;
36152let DecoderNamespace = "EXT_mmvec";
36153}
36154def V6_vmpyuhv_acc : HInst<
36155(outs HvxWR:$Vxx32),
36156(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36157"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
36158tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
36159let Inst{7-5} = 0b000;
36160let Inst{13-13} = 0b1;
36161let Inst{31-21} = 0b00011100001;
36162let hasNewValue = 1;
36163let opNewValue = 0;
36164let isAccumulator = 1;
36165let isCVI = 1;
36166let DecoderNamespace = "EXT_mmvec";
36167let Constraints = "$Vxx32 = $Vxx32in";
36168}
36169def V6_vmpyuhv_acc_alt : HInst<
36170(outs HvxWR:$Vxx32),
36171(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36172"$Vxx32 += vmpyuh($Vu32,$Vv32)",
36173PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36174let hasNewValue = 1;
36175let opNewValue = 0;
36176let isAccumulator = 1;
36177let isCVI = 1;
36178let isPseudo = 1;
36179let isCodeGenOnly = 1;
36180let DecoderNamespace = "EXT_mmvec";
36181let Constraints = "$Vxx32 = $Vxx32in";
36182}
36183def V6_vmpyuhv_alt : HInst<
36184(outs HvxWR:$Vdd32),
36185(ins HvxVR:$Vu32, HvxVR:$Vv32),
36186"$Vdd32 = vmpyuh($Vu32,$Vv32)",
36187PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36188let hasNewValue = 1;
36189let opNewValue = 0;
36190let isCVI = 1;
36191let isPseudo = 1;
36192let isCodeGenOnly = 1;
36193let DecoderNamespace = "EXT_mmvec";
36194}
36195def V6_vmpyuhvs : HInst<
36196(outs HvxVR:$Vd32),
36197(ins HvxVR:$Vu32, HvxVR:$Vv32),
36198"$Vd32.uh = vmpy($Vu32.uh,$Vv32.uh):>>16",
36199tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV69]> {
36200let Inst{7-5} = 0b111;
36201let Inst{13-13} = 0b1;
36202let Inst{31-21} = 0b00011111110;
36203let hasNewValue = 1;
36204let opNewValue = 0;
36205let isCVI = 1;
36206let DecoderNamespace = "EXT_mmvec";
36207}
36208def V6_vmux : HInst<
36209(outs HvxVR:$Vd32),
36210(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
36211"$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
36212tc_257f6f7c, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
36213let Inst{7-7} = 0b0;
36214let Inst{13-13} = 0b1;
36215let Inst{31-21} = 0b00011110111;
36216let hasNewValue = 1;
36217let opNewValue = 0;
36218let isCVI = 1;
36219let DecoderNamespace = "EXT_mmvec";
36220}
36221def V6_vnavgb : HInst<
36222(outs HvxVR:$Vd32),
36223(ins HvxVR:$Vu32, HvxVR:$Vv32),
36224"$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
36225tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
36226let Inst{7-5} = 0b110;
36227let Inst{13-13} = 0b1;
36228let Inst{31-21} = 0b00011111000;
36229let hasNewValue = 1;
36230let opNewValue = 0;
36231let isCVI = 1;
36232let DecoderNamespace = "EXT_mmvec";
36233}
36234def V6_vnavgb_alt : HInst<
36235(outs HvxVR:$Vd32),
36236(ins HvxVR:$Vu32, HvxVR:$Vv32),
36237"$Vd32 = vnavgb($Vu32,$Vv32)",
36238PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36239let hasNewValue = 1;
36240let opNewValue = 0;
36241let isCVI = 1;
36242let isPseudo = 1;
36243let isCodeGenOnly = 1;
36244let DecoderNamespace = "EXT_mmvec";
36245}
36246def V6_vnavgh : HInst<
36247(outs HvxVR:$Vd32),
36248(ins HvxVR:$Vu32, HvxVR:$Vv32),
36249"$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
36250tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36251let Inst{7-5} = 0b001;
36252let Inst{13-13} = 0b0;
36253let Inst{31-21} = 0b00011100111;
36254let hasNewValue = 1;
36255let opNewValue = 0;
36256let isCVI = 1;
36257let DecoderNamespace = "EXT_mmvec";
36258}
36259def V6_vnavgh_alt : HInst<
36260(outs HvxVR:$Vd32),
36261(ins HvxVR:$Vu32, HvxVR:$Vv32),
36262"$Vd32 = vnavgh($Vu32,$Vv32)",
36263PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36264let hasNewValue = 1;
36265let opNewValue = 0;
36266let isCVI = 1;
36267let isPseudo = 1;
36268let isCodeGenOnly = 1;
36269let DecoderNamespace = "EXT_mmvec";
36270}
36271def V6_vnavgub : HInst<
36272(outs HvxVR:$Vd32),
36273(ins HvxVR:$Vu32, HvxVR:$Vv32),
36274"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
36275tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36276let Inst{7-5} = 0b000;
36277let Inst{13-13} = 0b0;
36278let Inst{31-21} = 0b00011100111;
36279let hasNewValue = 1;
36280let opNewValue = 0;
36281let isCVI = 1;
36282let DecoderNamespace = "EXT_mmvec";
36283}
36284def V6_vnavgub_alt : HInst<
36285(outs HvxVR:$Vd32),
36286(ins HvxVR:$Vu32, HvxVR:$Vv32),
36287"$Vd32 = vnavgub($Vu32,$Vv32)",
36288PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36289let hasNewValue = 1;
36290let opNewValue = 0;
36291let isCVI = 1;
36292let isPseudo = 1;
36293let isCodeGenOnly = 1;
36294let DecoderNamespace = "EXT_mmvec";
36295}
36296def V6_vnavgw : HInst<
36297(outs HvxVR:$Vd32),
36298(ins HvxVR:$Vu32, HvxVR:$Vv32),
36299"$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
36300tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36301let Inst{7-5} = 0b010;
36302let Inst{13-13} = 0b0;
36303let Inst{31-21} = 0b00011100111;
36304let hasNewValue = 1;
36305let opNewValue = 0;
36306let isCVI = 1;
36307let DecoderNamespace = "EXT_mmvec";
36308}
36309def V6_vnavgw_alt : HInst<
36310(outs HvxVR:$Vd32),
36311(ins HvxVR:$Vu32, HvxVR:$Vv32),
36312"$Vd32 = vnavgw($Vu32,$Vv32)",
36313PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36314let hasNewValue = 1;
36315let opNewValue = 0;
36316let isCVI = 1;
36317let isPseudo = 1;
36318let isCodeGenOnly = 1;
36319let DecoderNamespace = "EXT_mmvec";
36320}
36321def V6_vnccombine : HInst<
36322(outs HvxWR:$Vdd32),
36323(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
36324"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
36325tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
36326let Inst{7-7} = 0b0;
36327let Inst{13-13} = 0b0;
36328let Inst{31-21} = 0b00011010010;
36329let isPredicated = 1;
36330let isPredicatedFalse = 1;
36331let hasNewValue = 1;
36332let opNewValue = 0;
36333let isCVI = 1;
36334let DecoderNamespace = "EXT_mmvec";
36335}
36336def V6_vncmov : HInst<
36337(outs HvxVR:$Vd32),
36338(ins PredRegs:$Ps4, HvxVR:$Vu32),
36339"if (!$Ps4) $Vd32 = $Vu32",
36340tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
36341let Inst{7-7} = 0b0;
36342let Inst{13-13} = 0b0;
36343let Inst{31-16} = 0b0001101000100000;
36344let isPredicated = 1;
36345let isPredicatedFalse = 1;
36346let hasNewValue = 1;
36347let opNewValue = 0;
36348let isCVI = 1;
36349let DecoderNamespace = "EXT_mmvec";
36350}
36351def V6_vnormamth : HInst<
36352(outs HvxVR:$Vd32),
36353(ins HvxVR:$Vu32),
36354"$Vd32.h = vnormamt($Vu32.h)",
36355tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
36356let Inst{7-5} = 0b101;
36357let Inst{13-13} = 0b0;
36358let Inst{31-16} = 0b0001111000000011;
36359let hasNewValue = 1;
36360let opNewValue = 0;
36361let isCVI = 1;
36362let DecoderNamespace = "EXT_mmvec";
36363}
36364def V6_vnormamth_alt : HInst<
36365(outs HvxVR:$Vd32),
36366(ins HvxVR:$Vu32),
36367"$Vd32 = vnormamth($Vu32)",
36368PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36369let hasNewValue = 1;
36370let opNewValue = 0;
36371let isCVI = 1;
36372let isPseudo = 1;
36373let isCodeGenOnly = 1;
36374let DecoderNamespace = "EXT_mmvec";
36375}
36376def V6_vnormamtw : HInst<
36377(outs HvxVR:$Vd32),
36378(ins HvxVR:$Vu32),
36379"$Vd32.w = vnormamt($Vu32.w)",
36380tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
36381let Inst{7-5} = 0b100;
36382let Inst{13-13} = 0b0;
36383let Inst{31-16} = 0b0001111000000011;
36384let hasNewValue = 1;
36385let opNewValue = 0;
36386let isCVI = 1;
36387let DecoderNamespace = "EXT_mmvec";
36388}
36389def V6_vnormamtw_alt : HInst<
36390(outs HvxVR:$Vd32),
36391(ins HvxVR:$Vu32),
36392"$Vd32 = vnormamtw($Vu32)",
36393PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36394let hasNewValue = 1;
36395let opNewValue = 0;
36396let isCVI = 1;
36397let isPseudo = 1;
36398let isCodeGenOnly = 1;
36399let DecoderNamespace = "EXT_mmvec";
36400}
36401def V6_vnot : HInst<
36402(outs HvxVR:$Vd32),
36403(ins HvxVR:$Vu32),
36404"$Vd32 = vnot($Vu32)",
36405tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
36406let Inst{7-5} = 0b100;
36407let Inst{13-13} = 0b0;
36408let Inst{31-16} = 0b0001111000000000;
36409let hasNewValue = 1;
36410let opNewValue = 0;
36411let isCVI = 1;
36412let DecoderNamespace = "EXT_mmvec";
36413}
36414def V6_vor : HInst<
36415(outs HvxVR:$Vd32),
36416(ins HvxVR:$Vu32, HvxVR:$Vv32),
36417"$Vd32 = vor($Vu32,$Vv32)",
36418tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36419let Inst{7-5} = 0b110;
36420let Inst{13-13} = 0b0;
36421let Inst{31-21} = 0b00011100001;
36422let hasNewValue = 1;
36423let opNewValue = 0;
36424let isCVI = 1;
36425let DecoderNamespace = "EXT_mmvec";
36426}
36427def V6_vpackeb : HInst<
36428(outs HvxVR:$Vd32),
36429(ins HvxVR:$Vu32, HvxVR:$Vv32),
36430"$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
36431tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36432let Inst{7-5} = 0b010;
36433let Inst{13-13} = 0b0;
36434let Inst{31-21} = 0b00011111110;
36435let hasNewValue = 1;
36436let opNewValue = 0;
36437let isCVI = 1;
36438let DecoderNamespace = "EXT_mmvec";
36439}
36440def V6_vpackeb_alt : HInst<
36441(outs HvxVR:$Vd32),
36442(ins HvxVR:$Vu32, HvxVR:$Vv32),
36443"$Vd32 = vpackeb($Vu32,$Vv32)",
36444PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36445let hasNewValue = 1;
36446let opNewValue = 0;
36447let isCVI = 1;
36448let isPseudo = 1;
36449let isCodeGenOnly = 1;
36450let DecoderNamespace = "EXT_mmvec";
36451}
36452def V6_vpackeh : HInst<
36453(outs HvxVR:$Vd32),
36454(ins HvxVR:$Vu32, HvxVR:$Vv32),
36455"$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
36456tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36457let Inst{7-5} = 0b011;
36458let Inst{13-13} = 0b0;
36459let Inst{31-21} = 0b00011111110;
36460let hasNewValue = 1;
36461let opNewValue = 0;
36462let isCVI = 1;
36463let DecoderNamespace = "EXT_mmvec";
36464}
36465def V6_vpackeh_alt : HInst<
36466(outs HvxVR:$Vd32),
36467(ins HvxVR:$Vu32, HvxVR:$Vv32),
36468"$Vd32 = vpackeh($Vu32,$Vv32)",
36469PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36470let hasNewValue = 1;
36471let opNewValue = 0;
36472let isCVI = 1;
36473let isPseudo = 1;
36474let isCodeGenOnly = 1;
36475let DecoderNamespace = "EXT_mmvec";
36476}
36477def V6_vpackhb_sat : HInst<
36478(outs HvxVR:$Vd32),
36479(ins HvxVR:$Vu32, HvxVR:$Vv32),
36480"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
36481tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36482let Inst{7-5} = 0b110;
36483let Inst{13-13} = 0b0;
36484let Inst{31-21} = 0b00011111110;
36485let hasNewValue = 1;
36486let opNewValue = 0;
36487let isCVI = 1;
36488let DecoderNamespace = "EXT_mmvec";
36489}
36490def V6_vpackhb_sat_alt : HInst<
36491(outs HvxVR:$Vd32),
36492(ins HvxVR:$Vu32, HvxVR:$Vv32),
36493"$Vd32 = vpackhb($Vu32,$Vv32):sat",
36494PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36495let hasNewValue = 1;
36496let opNewValue = 0;
36497let isCVI = 1;
36498let isPseudo = 1;
36499let isCodeGenOnly = 1;
36500let DecoderNamespace = "EXT_mmvec";
36501}
36502def V6_vpackhub_sat : HInst<
36503(outs HvxVR:$Vd32),
36504(ins HvxVR:$Vu32, HvxVR:$Vv32),
36505"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
36506tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36507let Inst{7-5} = 0b101;
36508let Inst{13-13} = 0b0;
36509let Inst{31-21} = 0b00011111110;
36510let hasNewValue = 1;
36511let opNewValue = 0;
36512let isCVI = 1;
36513let DecoderNamespace = "EXT_mmvec";
36514}
36515def V6_vpackhub_sat_alt : HInst<
36516(outs HvxVR:$Vd32),
36517(ins HvxVR:$Vu32, HvxVR:$Vv32),
36518"$Vd32 = vpackhub($Vu32,$Vv32):sat",
36519PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36520let hasNewValue = 1;
36521let opNewValue = 0;
36522let isCVI = 1;
36523let isPseudo = 1;
36524let isCodeGenOnly = 1;
36525let DecoderNamespace = "EXT_mmvec";
36526}
36527def V6_vpackob : HInst<
36528(outs HvxVR:$Vd32),
36529(ins HvxVR:$Vu32, HvxVR:$Vv32),
36530"$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
36531tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36532let Inst{7-5} = 0b001;
36533let Inst{13-13} = 0b0;
36534let Inst{31-21} = 0b00011111111;
36535let hasNewValue = 1;
36536let opNewValue = 0;
36537let isCVI = 1;
36538let DecoderNamespace = "EXT_mmvec";
36539}
36540def V6_vpackob_alt : HInst<
36541(outs HvxVR:$Vd32),
36542(ins HvxVR:$Vu32, HvxVR:$Vv32),
36543"$Vd32 = vpackob($Vu32,$Vv32)",
36544PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36545let hasNewValue = 1;
36546let opNewValue = 0;
36547let isCVI = 1;
36548let isPseudo = 1;
36549let isCodeGenOnly = 1;
36550let DecoderNamespace = "EXT_mmvec";
36551}
36552def V6_vpackoh : HInst<
36553(outs HvxVR:$Vd32),
36554(ins HvxVR:$Vu32, HvxVR:$Vv32),
36555"$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
36556tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36557let Inst{7-5} = 0b010;
36558let Inst{13-13} = 0b0;
36559let Inst{31-21} = 0b00011111111;
36560let hasNewValue = 1;
36561let opNewValue = 0;
36562let isCVI = 1;
36563let DecoderNamespace = "EXT_mmvec";
36564}
36565def V6_vpackoh_alt : HInst<
36566(outs HvxVR:$Vd32),
36567(ins HvxVR:$Vu32, HvxVR:$Vv32),
36568"$Vd32 = vpackoh($Vu32,$Vv32)",
36569PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36570let hasNewValue = 1;
36571let opNewValue = 0;
36572let isCVI = 1;
36573let isPseudo = 1;
36574let isCodeGenOnly = 1;
36575let DecoderNamespace = "EXT_mmvec";
36576}
36577def V6_vpackwh_sat : HInst<
36578(outs HvxVR:$Vd32),
36579(ins HvxVR:$Vu32, HvxVR:$Vv32),
36580"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
36581tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36582let Inst{7-5} = 0b000;
36583let Inst{13-13} = 0b0;
36584let Inst{31-21} = 0b00011111111;
36585let hasNewValue = 1;
36586let opNewValue = 0;
36587let isCVI = 1;
36588let DecoderNamespace = "EXT_mmvec";
36589}
36590def V6_vpackwh_sat_alt : HInst<
36591(outs HvxVR:$Vd32),
36592(ins HvxVR:$Vu32, HvxVR:$Vv32),
36593"$Vd32 = vpackwh($Vu32,$Vv32):sat",
36594PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36595let hasNewValue = 1;
36596let opNewValue = 0;
36597let isCVI = 1;
36598let isPseudo = 1;
36599let isCodeGenOnly = 1;
36600let DecoderNamespace = "EXT_mmvec";
36601}
36602def V6_vpackwuh_sat : HInst<
36603(outs HvxVR:$Vd32),
36604(ins HvxVR:$Vu32, HvxVR:$Vv32),
36605"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
36606tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36607let Inst{7-5} = 0b111;
36608let Inst{13-13} = 0b0;
36609let Inst{31-21} = 0b00011111110;
36610let hasNewValue = 1;
36611let opNewValue = 0;
36612let isCVI = 1;
36613let DecoderNamespace = "EXT_mmvec";
36614}
36615def V6_vpackwuh_sat_alt : HInst<
36616(outs HvxVR:$Vd32),
36617(ins HvxVR:$Vu32, HvxVR:$Vv32),
36618"$Vd32 = vpackwuh($Vu32,$Vv32):sat",
36619PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36620let hasNewValue = 1;
36621let opNewValue = 0;
36622let isCVI = 1;
36623let isPseudo = 1;
36624let isCodeGenOnly = 1;
36625let DecoderNamespace = "EXT_mmvec";
36626}
36627def V6_vpopcounth : HInst<
36628(outs HvxVR:$Vd32),
36629(ins HvxVR:$Vu32),
36630"$Vd32.h = vpopcount($Vu32.h)",
36631tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
36632let Inst{7-5} = 0b110;
36633let Inst{13-13} = 0b0;
36634let Inst{31-16} = 0b0001111000000010;
36635let hasNewValue = 1;
36636let opNewValue = 0;
36637let isCVI = 1;
36638let DecoderNamespace = "EXT_mmvec";
36639}
36640def V6_vpopcounth_alt : HInst<
36641(outs HvxVR:$Vd32),
36642(ins HvxVR:$Vu32),
36643"$Vd32 = vpopcounth($Vu32)",
36644PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36645let hasNewValue = 1;
36646let opNewValue = 0;
36647let isCVI = 1;
36648let isPseudo = 1;
36649let isCodeGenOnly = 1;
36650let DecoderNamespace = "EXT_mmvec";
36651}
36652def V6_vprefixqb : HInst<
36653(outs HvxVR:$Vd32),
36654(ins HvxQR:$Qv4),
36655"$Vd32.b = prefixsum($Qv4)",
36656tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
36657let Inst{13-5} = 0b100000010;
36658let Inst{21-16} = 0b000011;
36659let Inst{31-24} = 0b00011110;
36660let hasNewValue = 1;
36661let opNewValue = 0;
36662let isCVI = 1;
36663let DecoderNamespace = "EXT_mmvec";
36664}
36665def V6_vprefixqh : HInst<
36666(outs HvxVR:$Vd32),
36667(ins HvxQR:$Qv4),
36668"$Vd32.h = prefixsum($Qv4)",
36669tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
36670let Inst{13-5} = 0b100001010;
36671let Inst{21-16} = 0b000011;
36672let Inst{31-24} = 0b00011110;
36673let hasNewValue = 1;
36674let opNewValue = 0;
36675let isCVI = 1;
36676let DecoderNamespace = "EXT_mmvec";
36677}
36678def V6_vprefixqw : HInst<
36679(outs HvxVR:$Vd32),
36680(ins HvxQR:$Qv4),
36681"$Vd32.w = prefixsum($Qv4)",
36682tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
36683let Inst{13-5} = 0b100010010;
36684let Inst{21-16} = 0b000011;
36685let Inst{31-24} = 0b00011110;
36686let hasNewValue = 1;
36687let opNewValue = 0;
36688let isCVI = 1;
36689let DecoderNamespace = "EXT_mmvec";
36690}
36691def V6_vrdelta : HInst<
36692(outs HvxVR:$Vd32),
36693(ins HvxVR:$Vu32, HvxVR:$Vv32),
36694"$Vd32 = vrdelta($Vu32,$Vv32)",
36695tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36696let Inst{7-5} = 0b011;
36697let Inst{13-13} = 0b0;
36698let Inst{31-21} = 0b00011111001;
36699let hasNewValue = 1;
36700let opNewValue = 0;
36701let isCVI = 1;
36702let DecoderNamespace = "EXT_mmvec";
36703}
36704def V6_vrmpybub_rtt : HInst<
36705(outs HvxWR:$Vdd32),
36706(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
36707"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
36708tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
36709let Inst{7-5} = 0b101;
36710let Inst{13-13} = 0b0;
36711let Inst{31-21} = 0b00011001110;
36712let hasNewValue = 1;
36713let opNewValue = 0;
36714let isCVI = 1;
36715let DecoderNamespace = "EXT_mmvec";
36716}
36717def V6_vrmpybub_rtt_acc : HInst<
36718(outs HvxWR:$Vxx32),
36719(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
36720"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
36721tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
36722let Inst{7-5} = 0b000;
36723let Inst{13-13} = 0b1;
36724let Inst{31-21} = 0b00011001101;
36725let hasNewValue = 1;
36726let opNewValue = 0;
36727let isAccumulator = 1;
36728let isCVI = 1;
36729let DecoderNamespace = "EXT_mmvec";
36730let Constraints = "$Vxx32 = $Vxx32in";
36731}
36732def V6_vrmpybub_rtt_acc_alt : HInst<
36733(outs HvxWR:$Vxx32),
36734(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
36735"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
36736PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36737let hasNewValue = 1;
36738let opNewValue = 0;
36739let isAccumulator = 1;
36740let isCVI = 1;
36741let isPseudo = 1;
36742let isCodeGenOnly = 1;
36743let DecoderNamespace = "EXT_mmvec";
36744let Constraints = "$Vxx32 = $Vxx32in";
36745}
36746def V6_vrmpybub_rtt_alt : HInst<
36747(outs HvxWR:$Vdd32),
36748(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
36749"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
36750PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36751let hasNewValue = 1;
36752let opNewValue = 0;
36753let isCVI = 1;
36754let isPseudo = 1;
36755let isCodeGenOnly = 1;
36756let DecoderNamespace = "EXT_mmvec";
36757}
36758def V6_vrmpybus : HInst<
36759(outs HvxVR:$Vd32),
36760(ins HvxVR:$Vu32, IntRegs:$Rt32),
36761"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
36762tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
36763let Inst{7-5} = 0b100;
36764let Inst{13-13} = 0b0;
36765let Inst{31-21} = 0b00011001000;
36766let hasNewValue = 1;
36767let opNewValue = 0;
36768let isCVI = 1;
36769let DecoderNamespace = "EXT_mmvec";
36770}
36771def V6_vrmpybus_acc : HInst<
36772(outs HvxVR:$Vx32),
36773(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36774"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
36775tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
36776let Inst{7-5} = 0b101;
36777let Inst{13-13} = 0b1;
36778let Inst{31-21} = 0b00011001000;
36779let hasNewValue = 1;
36780let opNewValue = 0;
36781let isAccumulator = 1;
36782let isCVI = 1;
36783let DecoderNamespace = "EXT_mmvec";
36784let Constraints = "$Vx32 = $Vx32in";
36785}
36786def V6_vrmpybus_acc_alt : HInst<
36787(outs HvxVR:$Vx32),
36788(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36789"$Vx32 += vrmpybus($Vu32,$Rt32)",
36790PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36791let hasNewValue = 1;
36792let opNewValue = 0;
36793let isAccumulator = 1;
36794let isCVI = 1;
36795let isPseudo = 1;
36796let isCodeGenOnly = 1;
36797let DecoderNamespace = "EXT_mmvec";
36798let Constraints = "$Vx32 = $Vx32in";
36799}
36800def V6_vrmpybus_alt : HInst<
36801(outs HvxVR:$Vd32),
36802(ins HvxVR:$Vu32, IntRegs:$Rt32),
36803"$Vd32 = vrmpybus($Vu32,$Rt32)",
36804PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36805let hasNewValue = 1;
36806let opNewValue = 0;
36807let isCVI = 1;
36808let isPseudo = 1;
36809let isCodeGenOnly = 1;
36810let DecoderNamespace = "EXT_mmvec";
36811}
36812def V6_vrmpybusi : HInst<
36813(outs HvxWR:$Vdd32),
36814(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36815"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
36816tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
36817let Inst{7-6} = 0b10;
36818let Inst{13-13} = 0b0;
36819let Inst{31-21} = 0b00011001010;
36820let hasNewValue = 1;
36821let opNewValue = 0;
36822let isCVI = 1;
36823let DecoderNamespace = "EXT_mmvec";
36824}
36825def V6_vrmpybusi_acc : HInst<
36826(outs HvxWR:$Vxx32),
36827(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36828"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
36829tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
36830let Inst{7-6} = 0b10;
36831let Inst{13-13} = 0b1;
36832let Inst{31-21} = 0b00011001010;
36833let hasNewValue = 1;
36834let opNewValue = 0;
36835let isAccumulator = 1;
36836let isCVI = 1;
36837let DecoderNamespace = "EXT_mmvec";
36838let Constraints = "$Vxx32 = $Vxx32in";
36839}
36840def V6_vrmpybusi_acc_alt : HInst<
36841(outs HvxWR:$Vxx32),
36842(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36843"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
36844PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36845let hasNewValue = 1;
36846let opNewValue = 0;
36847let isAccumulator = 1;
36848let isCVI = 1;
36849let isPseudo = 1;
36850let isCodeGenOnly = 1;
36851let DecoderNamespace = "EXT_mmvec";
36852let Constraints = "$Vxx32 = $Vxx32in";
36853}
36854def V6_vrmpybusi_alt : HInst<
36855(outs HvxWR:$Vdd32),
36856(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36857"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
36858PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36859let hasNewValue = 1;
36860let opNewValue = 0;
36861let isCVI = 1;
36862let isPseudo = 1;
36863let isCodeGenOnly = 1;
36864let DecoderNamespace = "EXT_mmvec";
36865}
36866def V6_vrmpybusv : HInst<
36867(outs HvxVR:$Vd32),
36868(ins HvxVR:$Vu32, HvxVR:$Vv32),
36869"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
36870tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
36871let Inst{7-5} = 0b010;
36872let Inst{13-13} = 0b0;
36873let Inst{31-21} = 0b00011100000;
36874let hasNewValue = 1;
36875let opNewValue = 0;
36876let isCVI = 1;
36877let DecoderNamespace = "EXT_mmvec";
36878}
36879def V6_vrmpybusv_acc : HInst<
36880(outs HvxVR:$Vx32),
36881(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36882"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
36883tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
36884let Inst{7-5} = 0b010;
36885let Inst{13-13} = 0b1;
36886let Inst{31-21} = 0b00011100000;
36887let hasNewValue = 1;
36888let opNewValue = 0;
36889let isAccumulator = 1;
36890let isCVI = 1;
36891let DecoderNamespace = "EXT_mmvec";
36892let Constraints = "$Vx32 = $Vx32in";
36893}
36894def V6_vrmpybusv_acc_alt : HInst<
36895(outs HvxVR:$Vx32),
36896(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36897"$Vx32 += vrmpybus($Vu32,$Vv32)",
36898PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36899let hasNewValue = 1;
36900let opNewValue = 0;
36901let isAccumulator = 1;
36902let isCVI = 1;
36903let isPseudo = 1;
36904let isCodeGenOnly = 1;
36905let DecoderNamespace = "EXT_mmvec";
36906let Constraints = "$Vx32 = $Vx32in";
36907}
36908def V6_vrmpybusv_alt : HInst<
36909(outs HvxVR:$Vd32),
36910(ins HvxVR:$Vu32, HvxVR:$Vv32),
36911"$Vd32 = vrmpybus($Vu32,$Vv32)",
36912PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36913let hasNewValue = 1;
36914let opNewValue = 0;
36915let isCVI = 1;
36916let isPseudo = 1;
36917let isCodeGenOnly = 1;
36918let DecoderNamespace = "EXT_mmvec";
36919}
36920def V6_vrmpybv : HInst<
36921(outs HvxVR:$Vd32),
36922(ins HvxVR:$Vu32, HvxVR:$Vv32),
36923"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
36924tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
36925let Inst{7-5} = 0b001;
36926let Inst{13-13} = 0b0;
36927let Inst{31-21} = 0b00011100000;
36928let hasNewValue = 1;
36929let opNewValue = 0;
36930let isCVI = 1;
36931let DecoderNamespace = "EXT_mmvec";
36932}
36933def V6_vrmpybv_acc : HInst<
36934(outs HvxVR:$Vx32),
36935(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36936"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
36937tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
36938let Inst{7-5} = 0b001;
36939let Inst{13-13} = 0b1;
36940let Inst{31-21} = 0b00011100000;
36941let hasNewValue = 1;
36942let opNewValue = 0;
36943let isAccumulator = 1;
36944let isCVI = 1;
36945let DecoderNamespace = "EXT_mmvec";
36946let Constraints = "$Vx32 = $Vx32in";
36947}
36948def V6_vrmpybv_acc_alt : HInst<
36949(outs HvxVR:$Vx32),
36950(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36951"$Vx32 += vrmpyb($Vu32,$Vv32)",
36952PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36953let hasNewValue = 1;
36954let opNewValue = 0;
36955let isAccumulator = 1;
36956let isCVI = 1;
36957let isPseudo = 1;
36958let isCodeGenOnly = 1;
36959let DecoderNamespace = "EXT_mmvec";
36960let Constraints = "$Vx32 = $Vx32in";
36961}
36962def V6_vrmpybv_alt : HInst<
36963(outs HvxVR:$Vd32),
36964(ins HvxVR:$Vu32, HvxVR:$Vv32),
36965"$Vd32 = vrmpyb($Vu32,$Vv32)",
36966PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36967let hasNewValue = 1;
36968let opNewValue = 0;
36969let isCVI = 1;
36970let isPseudo = 1;
36971let isCodeGenOnly = 1;
36972let DecoderNamespace = "EXT_mmvec";
36973}
36974def V6_vrmpyub : HInst<
36975(outs HvxVR:$Vd32),
36976(ins HvxVR:$Vu32, IntRegs:$Rt32),
36977"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
36978tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
36979let Inst{7-5} = 0b011;
36980let Inst{13-13} = 0b0;
36981let Inst{31-21} = 0b00011001000;
36982let hasNewValue = 1;
36983let opNewValue = 0;
36984let isCVI = 1;
36985let DecoderNamespace = "EXT_mmvec";
36986}
36987def V6_vrmpyub_acc : HInst<
36988(outs HvxVR:$Vx32),
36989(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36990"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
36991tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
36992let Inst{7-5} = 0b100;
36993let Inst{13-13} = 0b1;
36994let Inst{31-21} = 0b00011001000;
36995let hasNewValue = 1;
36996let opNewValue = 0;
36997let isAccumulator = 1;
36998let isCVI = 1;
36999let DecoderNamespace = "EXT_mmvec";
37000let Constraints = "$Vx32 = $Vx32in";
37001}
37002def V6_vrmpyub_acc_alt : HInst<
37003(outs HvxVR:$Vx32),
37004(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37005"$Vx32 += vrmpyub($Vu32,$Rt32)",
37006PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37007let hasNewValue = 1;
37008let opNewValue = 0;
37009let isAccumulator = 1;
37010let isCVI = 1;
37011let isPseudo = 1;
37012let isCodeGenOnly = 1;
37013let DecoderNamespace = "EXT_mmvec";
37014let Constraints = "$Vx32 = $Vx32in";
37015}
37016def V6_vrmpyub_alt : HInst<
37017(outs HvxVR:$Vd32),
37018(ins HvxVR:$Vu32, IntRegs:$Rt32),
37019"$Vd32 = vrmpyub($Vu32,$Rt32)",
37020PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37021let hasNewValue = 1;
37022let opNewValue = 0;
37023let isCVI = 1;
37024let isPseudo = 1;
37025let isCodeGenOnly = 1;
37026let DecoderNamespace = "EXT_mmvec";
37027}
37028def V6_vrmpyub_rtt : HInst<
37029(outs HvxWR:$Vdd32),
37030(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37031"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
37032tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
37033let Inst{7-5} = 0b100;
37034let Inst{13-13} = 0b0;
37035let Inst{31-21} = 0b00011001110;
37036let hasNewValue = 1;
37037let opNewValue = 0;
37038let isCVI = 1;
37039let DecoderNamespace = "EXT_mmvec";
37040}
37041def V6_vrmpyub_rtt_acc : HInst<
37042(outs HvxWR:$Vxx32),
37043(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37044"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
37045tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
37046let Inst{7-5} = 0b111;
37047let Inst{13-13} = 0b1;
37048let Inst{31-21} = 0b00011001101;
37049let hasNewValue = 1;
37050let opNewValue = 0;
37051let isAccumulator = 1;
37052let isCVI = 1;
37053let DecoderNamespace = "EXT_mmvec";
37054let Constraints = "$Vxx32 = $Vxx32in";
37055}
37056def V6_vrmpyub_rtt_acc_alt : HInst<
37057(outs HvxWR:$Vxx32),
37058(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37059"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
37060PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37061let hasNewValue = 1;
37062let opNewValue = 0;
37063let isAccumulator = 1;
37064let isCVI = 1;
37065let isPseudo = 1;
37066let isCodeGenOnly = 1;
37067let DecoderNamespace = "EXT_mmvec";
37068let Constraints = "$Vxx32 = $Vxx32in";
37069}
37070def V6_vrmpyub_rtt_alt : HInst<
37071(outs HvxWR:$Vdd32),
37072(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37073"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
37074PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37075let hasNewValue = 1;
37076let opNewValue = 0;
37077let isCVI = 1;
37078let isPseudo = 1;
37079let isCodeGenOnly = 1;
37080let DecoderNamespace = "EXT_mmvec";
37081}
37082def V6_vrmpyubi : HInst<
37083(outs HvxWR:$Vdd32),
37084(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37085"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
37086tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
37087let Inst{7-6} = 0b11;
37088let Inst{13-13} = 0b0;
37089let Inst{31-21} = 0b00011001101;
37090let hasNewValue = 1;
37091let opNewValue = 0;
37092let isCVI = 1;
37093let DecoderNamespace = "EXT_mmvec";
37094}
37095def V6_vrmpyubi_acc : HInst<
37096(outs HvxWR:$Vxx32),
37097(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37098"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
37099tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
37100let Inst{7-6} = 0b11;
37101let Inst{13-13} = 0b1;
37102let Inst{31-21} = 0b00011001011;
37103let hasNewValue = 1;
37104let opNewValue = 0;
37105let isAccumulator = 1;
37106let isCVI = 1;
37107let DecoderNamespace = "EXT_mmvec";
37108let Constraints = "$Vxx32 = $Vxx32in";
37109}
37110def V6_vrmpyubi_acc_alt : HInst<
37111(outs HvxWR:$Vxx32),
37112(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37113"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
37114PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37115let hasNewValue = 1;
37116let opNewValue = 0;
37117let isAccumulator = 1;
37118let isCVI = 1;
37119let isPseudo = 1;
37120let isCodeGenOnly = 1;
37121let DecoderNamespace = "EXT_mmvec";
37122let Constraints = "$Vxx32 = $Vxx32in";
37123}
37124def V6_vrmpyubi_alt : HInst<
37125(outs HvxWR:$Vdd32),
37126(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37127"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
37128PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37129let hasNewValue = 1;
37130let opNewValue = 0;
37131let isCVI = 1;
37132let isPseudo = 1;
37133let isCodeGenOnly = 1;
37134let DecoderNamespace = "EXT_mmvec";
37135}
37136def V6_vrmpyubv : HInst<
37137(outs HvxVR:$Vd32),
37138(ins HvxVR:$Vu32, HvxVR:$Vv32),
37139"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
37140tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
37141let Inst{7-5} = 0b000;
37142let Inst{13-13} = 0b0;
37143let Inst{31-21} = 0b00011100000;
37144let hasNewValue = 1;
37145let opNewValue = 0;
37146let isCVI = 1;
37147let DecoderNamespace = "EXT_mmvec";
37148}
37149def V6_vrmpyubv_acc : HInst<
37150(outs HvxVR:$Vx32),
37151(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37152"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
37153tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
37154let Inst{7-5} = 0b000;
37155let Inst{13-13} = 0b1;
37156let Inst{31-21} = 0b00011100000;
37157let hasNewValue = 1;
37158let opNewValue = 0;
37159let isAccumulator = 1;
37160let isCVI = 1;
37161let DecoderNamespace = "EXT_mmvec";
37162let Constraints = "$Vx32 = $Vx32in";
37163}
37164def V6_vrmpyubv_acc_alt : HInst<
37165(outs HvxVR:$Vx32),
37166(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37167"$Vx32 += vrmpyub($Vu32,$Vv32)",
37168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37169let hasNewValue = 1;
37170let opNewValue = 0;
37171let isAccumulator = 1;
37172let isCVI = 1;
37173let isPseudo = 1;
37174let isCodeGenOnly = 1;
37175let DecoderNamespace = "EXT_mmvec";
37176let Constraints = "$Vx32 = $Vx32in";
37177}
37178def V6_vrmpyubv_alt : HInst<
37179(outs HvxVR:$Vd32),
37180(ins HvxVR:$Vu32, HvxVR:$Vv32),
37181"$Vd32 = vrmpyub($Vu32,$Vv32)",
37182PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37183let hasNewValue = 1;
37184let opNewValue = 0;
37185let isCVI = 1;
37186let isPseudo = 1;
37187let isCodeGenOnly = 1;
37188let DecoderNamespace = "EXT_mmvec";
37189}
37190def V6_vrmpyzbb_rt : HInst<
37191(outs HvxVQR:$Vdddd32),
37192(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37193"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.b)",
37194tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37195let Inst{7-5} = 0b000;
37196let Inst{13-13} = 0b0;
37197let Inst{31-19} = 0b0001100111101;
37198let hasNewValue = 1;
37199let opNewValue = 0;
37200let isCVI = 1;
37201let DecoderNamespace = "EXT_mmvec";
37202}
37203def V6_vrmpyzbb_rt_acc : HInst<
37204(outs HvxVQR:$Vyyyy32),
37205(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37206"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.b)",
37207tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37208let Inst{7-5} = 0b010;
37209let Inst{13-13} = 0b1;
37210let Inst{31-19} = 0b0001100111000;
37211let hasNewValue = 1;
37212let opNewValue = 0;
37213let isAccumulator = 1;
37214let isCVI = 1;
37215let DecoderNamespace = "EXT_mmvec";
37216let Constraints = "$Vyyyy32 = $Vyyyy32in";
37217}
37218def V6_vrmpyzbb_rx : HInst<
37219(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37220(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37221"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)",
37222tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37223let Inst{7-5} = 0b000;
37224let Inst{13-13} = 0b0;
37225let Inst{31-19} = 0b0001100111100;
37226let hasNewValue = 1;
37227let opNewValue = 0;
37228let isCVI = 1;
37229let DecoderNamespace = "EXT_mmvec";
37230let Constraints = "$Rx8 = $Rx8in";
37231}
37232def V6_vrmpyzbb_rx_acc : HInst<
37233(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37234(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37235"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)",
37236tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37237let Inst{7-5} = 0b010;
37238let Inst{13-13} = 0b1;
37239let Inst{31-19} = 0b0001100111001;
37240let hasNewValue = 1;
37241let opNewValue = 0;
37242let isAccumulator = 1;
37243let isCVI = 1;
37244let DecoderNamespace = "EXT_mmvec";
37245let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37246}
37247def V6_vrmpyzbub_rt : HInst<
37248(outs HvxVQR:$Vdddd32),
37249(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37250"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.ub)",
37251tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37252let Inst{7-5} = 0b010;
37253let Inst{13-13} = 0b0;
37254let Inst{31-19} = 0b0001100111111;
37255let hasNewValue = 1;
37256let opNewValue = 0;
37257let isCVI = 1;
37258let DecoderNamespace = "EXT_mmvec";
37259}
37260def V6_vrmpyzbub_rt_acc : HInst<
37261(outs HvxVQR:$Vyyyy32),
37262(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37263"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.ub)",
37264tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37265let Inst{7-5} = 0b001;
37266let Inst{13-13} = 0b1;
37267let Inst{31-19} = 0b0001100111010;
37268let hasNewValue = 1;
37269let opNewValue = 0;
37270let isAccumulator = 1;
37271let isCVI = 1;
37272let DecoderNamespace = "EXT_mmvec";
37273let Constraints = "$Vyyyy32 = $Vyyyy32in";
37274}
37275def V6_vrmpyzbub_rx : HInst<
37276(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37277(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37278"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)",
37279tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37280let Inst{7-5} = 0b010;
37281let Inst{13-13} = 0b0;
37282let Inst{31-19} = 0b0001100111110;
37283let hasNewValue = 1;
37284let opNewValue = 0;
37285let isCVI = 1;
37286let DecoderNamespace = "EXT_mmvec";
37287let Constraints = "$Rx8 = $Rx8in";
37288}
37289def V6_vrmpyzbub_rx_acc : HInst<
37290(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37291(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37292"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)",
37293tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37294let Inst{7-5} = 0b001;
37295let Inst{13-13} = 0b1;
37296let Inst{31-19} = 0b0001100111011;
37297let hasNewValue = 1;
37298let opNewValue = 0;
37299let isAccumulator = 1;
37300let isCVI = 1;
37301let DecoderNamespace = "EXT_mmvec";
37302let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37303}
37304def V6_vrmpyzcb_rt : HInst<
37305(outs HvxVQR:$Vdddd32),
37306(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37307"$Vdddd32.w = vr16mpyz($Vu32.c,$Rt8.b)",
37308tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37309let Inst{7-5} = 0b001;
37310let Inst{13-13} = 0b0;
37311let Inst{31-19} = 0b0001100111101;
37312let hasNewValue = 1;
37313let opNewValue = 0;
37314let isCVI = 1;
37315let DecoderNamespace = "EXT_mmvec";
37316}
37317def V6_vrmpyzcb_rt_acc : HInst<
37318(outs HvxVQR:$Vyyyy32),
37319(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37320"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rt8.b)",
37321tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37322let Inst{7-5} = 0b011;
37323let Inst{13-13} = 0b1;
37324let Inst{31-19} = 0b0001100111000;
37325let hasNewValue = 1;
37326let opNewValue = 0;
37327let isAccumulator = 1;
37328let isCVI = 1;
37329let DecoderNamespace = "EXT_mmvec";
37330let Constraints = "$Vyyyy32 = $Vyyyy32in";
37331}
37332def V6_vrmpyzcb_rx : HInst<
37333(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37334(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37335"$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)",
37336tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37337let Inst{7-5} = 0b001;
37338let Inst{13-13} = 0b0;
37339let Inst{31-19} = 0b0001100111100;
37340let hasNewValue = 1;
37341let opNewValue = 0;
37342let isCVI = 1;
37343let DecoderNamespace = "EXT_mmvec";
37344let Constraints = "$Rx8 = $Rx8in";
37345}
37346def V6_vrmpyzcb_rx_acc : HInst<
37347(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37348(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37349"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)",
37350tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37351let Inst{7-5} = 0b011;
37352let Inst{13-13} = 0b1;
37353let Inst{31-19} = 0b0001100111001;
37354let hasNewValue = 1;
37355let opNewValue = 0;
37356let isAccumulator = 1;
37357let isCVI = 1;
37358let DecoderNamespace = "EXT_mmvec";
37359let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37360}
37361def V6_vrmpyzcbs_rt : HInst<
37362(outs HvxVQR:$Vdddd32),
37363(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37364"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rt8.b)",
37365tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37366let Inst{7-5} = 0b010;
37367let Inst{13-13} = 0b0;
37368let Inst{31-19} = 0b0001100111101;
37369let hasNewValue = 1;
37370let opNewValue = 0;
37371let isCVI = 1;
37372let DecoderNamespace = "EXT_mmvec";
37373}
37374def V6_vrmpyzcbs_rt_acc : HInst<
37375(outs HvxVQR:$Vyyyy32),
37376(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37377"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rt8.b)",
37378tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37379let Inst{7-5} = 0b001;
37380let Inst{13-13} = 0b1;
37381let Inst{31-19} = 0b0001100111000;
37382let hasNewValue = 1;
37383let opNewValue = 0;
37384let isAccumulator = 1;
37385let isCVI = 1;
37386let DecoderNamespace = "EXT_mmvec";
37387let Constraints = "$Vyyyy32 = $Vyyyy32in";
37388}
37389def V6_vrmpyzcbs_rx : HInst<
37390(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37391(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37392"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)",
37393tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37394let Inst{7-5} = 0b010;
37395let Inst{13-13} = 0b0;
37396let Inst{31-19} = 0b0001100111100;
37397let hasNewValue = 1;
37398let opNewValue = 0;
37399let isCVI = 1;
37400let DecoderNamespace = "EXT_mmvec";
37401let Constraints = "$Rx8 = $Rx8in";
37402}
37403def V6_vrmpyzcbs_rx_acc : HInst<
37404(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37405(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37406"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)",
37407tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37408let Inst{7-5} = 0b001;
37409let Inst{13-13} = 0b1;
37410let Inst{31-19} = 0b0001100111001;
37411let hasNewValue = 1;
37412let opNewValue = 0;
37413let isAccumulator = 1;
37414let isCVI = 1;
37415let DecoderNamespace = "EXT_mmvec";
37416let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37417}
37418def V6_vrmpyznb_rt : HInst<
37419(outs HvxVQR:$Vdddd32),
37420(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37421"$Vdddd32.w = vr8mpyz($Vu32.n,$Rt8.b)",
37422tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37423let Inst{7-5} = 0b000;
37424let Inst{13-13} = 0b0;
37425let Inst{31-19} = 0b0001100111111;
37426let hasNewValue = 1;
37427let opNewValue = 0;
37428let isCVI = 1;
37429let DecoderNamespace = "EXT_mmvec";
37430}
37431def V6_vrmpyznb_rt_acc : HInst<
37432(outs HvxVQR:$Vyyyy32),
37433(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37434"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rt8.b)",
37435tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37436let Inst{7-5} = 0b010;
37437let Inst{13-13} = 0b1;
37438let Inst{31-19} = 0b0001100111010;
37439let hasNewValue = 1;
37440let opNewValue = 0;
37441let isAccumulator = 1;
37442let isCVI = 1;
37443let DecoderNamespace = "EXT_mmvec";
37444let Constraints = "$Vyyyy32 = $Vyyyy32in";
37445}
37446def V6_vrmpyznb_rx : HInst<
37447(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37448(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37449"$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)",
37450tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37451let Inst{7-5} = 0b000;
37452let Inst{13-13} = 0b0;
37453let Inst{31-19} = 0b0001100111110;
37454let hasNewValue = 1;
37455let opNewValue = 0;
37456let isCVI = 1;
37457let DecoderNamespace = "EXT_mmvec";
37458let Constraints = "$Rx8 = $Rx8in";
37459}
37460def V6_vrmpyznb_rx_acc : HInst<
37461(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37462(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37463"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)",
37464tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37465let Inst{7-5} = 0b010;
37466let Inst{13-13} = 0b1;
37467let Inst{31-19} = 0b0001100111011;
37468let hasNewValue = 1;
37469let opNewValue = 0;
37470let isAccumulator = 1;
37471let isCVI = 1;
37472let DecoderNamespace = "EXT_mmvec";
37473let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37474}
37475def V6_vror : HInst<
37476(outs HvxVR:$Vd32),
37477(ins HvxVR:$Vu32, IntRegs:$Rt32),
37478"$Vd32 = vror($Vu32,$Rt32)",
37479tc_6e7fa133, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
37480let Inst{7-5} = 0b001;
37481let Inst{13-13} = 0b0;
37482let Inst{31-21} = 0b00011001011;
37483let hasNewValue = 1;
37484let opNewValue = 0;
37485let isCVI = 1;
37486let DecoderNamespace = "EXT_mmvec";
37487}
37488def V6_vrotr : HInst<
37489(outs HvxVR:$Vd32),
37490(ins HvxVR:$Vu32, HvxVR:$Vv32),
37491"$Vd32.uw = vrotr($Vu32.uw,$Vv32.uw)",
37492tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV66]> {
37493let Inst{7-5} = 0b111;
37494let Inst{13-13} = 0b1;
37495let Inst{31-21} = 0b00011010100;
37496let hasNewValue = 1;
37497let opNewValue = 0;
37498let isCVI = 1;
37499let DecoderNamespace = "EXT_mmvec";
37500}
37501def V6_vrotr_alt : HInst<
37502(outs HvxVR:$Vd32),
37503(ins HvxVR:$Vu32, HvxVR:$Vv32),
37504"$Vd32 = vrotr($Vu32,$Vv32)",
37505PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
37506let hasNewValue = 1;
37507let opNewValue = 0;
37508let isCVI = 1;
37509let isPseudo = 1;
37510let isCodeGenOnly = 1;
37511let DecoderNamespace = "EXT_mmvec";
37512}
37513def V6_vroundhb : HInst<
37514(outs HvxVR:$Vd32),
37515(ins HvxVR:$Vu32, HvxVR:$Vv32),
37516"$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
37517tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
37518let Inst{7-5} = 0b110;
37519let Inst{13-13} = 0b0;
37520let Inst{31-21} = 0b00011111011;
37521let hasNewValue = 1;
37522let opNewValue = 0;
37523let isCVI = 1;
37524let DecoderNamespace = "EXT_mmvec";
37525}
37526def V6_vroundhb_alt : HInst<
37527(outs HvxVR:$Vd32),
37528(ins HvxVR:$Vu32, HvxVR:$Vv32),
37529"$Vd32 = vroundhb($Vu32,$Vv32):sat",
37530PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37531let hasNewValue = 1;
37532let opNewValue = 0;
37533let isCVI = 1;
37534let isPseudo = 1;
37535let isCodeGenOnly = 1;
37536let DecoderNamespace = "EXT_mmvec";
37537}
37538def V6_vroundhub : HInst<
37539(outs HvxVR:$Vd32),
37540(ins HvxVR:$Vu32, HvxVR:$Vv32),
37541"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
37542tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
37543let Inst{7-5} = 0b111;
37544let Inst{13-13} = 0b0;
37545let Inst{31-21} = 0b00011111011;
37546let hasNewValue = 1;
37547let opNewValue = 0;
37548let isCVI = 1;
37549let DecoderNamespace = "EXT_mmvec";
37550}
37551def V6_vroundhub_alt : HInst<
37552(outs HvxVR:$Vd32),
37553(ins HvxVR:$Vu32, HvxVR:$Vv32),
37554"$Vd32 = vroundhub($Vu32,$Vv32):sat",
37555PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37556let hasNewValue = 1;
37557let opNewValue = 0;
37558let isCVI = 1;
37559let isPseudo = 1;
37560let isCodeGenOnly = 1;
37561let DecoderNamespace = "EXT_mmvec";
37562}
37563def V6_vrounduhub : HInst<
37564(outs HvxVR:$Vd32),
37565(ins HvxVR:$Vu32, HvxVR:$Vv32),
37566"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
37567tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
37568let Inst{7-5} = 0b011;
37569let Inst{13-13} = 0b0;
37570let Inst{31-21} = 0b00011111111;
37571let hasNewValue = 1;
37572let opNewValue = 0;
37573let isCVI = 1;
37574let DecoderNamespace = "EXT_mmvec";
37575}
37576def V6_vrounduhub_alt : HInst<
37577(outs HvxVR:$Vd32),
37578(ins HvxVR:$Vu32, HvxVR:$Vv32),
37579"$Vd32 = vrounduhub($Vu32,$Vv32):sat",
37580PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37581let hasNewValue = 1;
37582let opNewValue = 0;
37583let isCVI = 1;
37584let isPseudo = 1;
37585let isCodeGenOnly = 1;
37586let DecoderNamespace = "EXT_mmvec";
37587}
37588def V6_vrounduwuh : HInst<
37589(outs HvxVR:$Vd32),
37590(ins HvxVR:$Vu32, HvxVR:$Vv32),
37591"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
37592tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
37593let Inst{7-5} = 0b100;
37594let Inst{13-13} = 0b0;
37595let Inst{31-21} = 0b00011111111;
37596let hasNewValue = 1;
37597let opNewValue = 0;
37598let isCVI = 1;
37599let DecoderNamespace = "EXT_mmvec";
37600}
37601def V6_vrounduwuh_alt : HInst<
37602(outs HvxVR:$Vd32),
37603(ins HvxVR:$Vu32, HvxVR:$Vv32),
37604"$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
37605PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37606let hasNewValue = 1;
37607let opNewValue = 0;
37608let isCVI = 1;
37609let isPseudo = 1;
37610let isCodeGenOnly = 1;
37611let DecoderNamespace = "EXT_mmvec";
37612}
37613def V6_vroundwh : HInst<
37614(outs HvxVR:$Vd32),
37615(ins HvxVR:$Vu32, HvxVR:$Vv32),
37616"$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
37617tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
37618let Inst{7-5} = 0b100;
37619let Inst{13-13} = 0b0;
37620let Inst{31-21} = 0b00011111011;
37621let hasNewValue = 1;
37622let opNewValue = 0;
37623let isCVI = 1;
37624let DecoderNamespace = "EXT_mmvec";
37625}
37626def V6_vroundwh_alt : HInst<
37627(outs HvxVR:$Vd32),
37628(ins HvxVR:$Vu32, HvxVR:$Vv32),
37629"$Vd32 = vroundwh($Vu32,$Vv32):sat",
37630PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37631let hasNewValue = 1;
37632let opNewValue = 0;
37633let isCVI = 1;
37634let isPseudo = 1;
37635let isCodeGenOnly = 1;
37636let DecoderNamespace = "EXT_mmvec";
37637}
37638def V6_vroundwuh : HInst<
37639(outs HvxVR:$Vd32),
37640(ins HvxVR:$Vu32, HvxVR:$Vv32),
37641"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
37642tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
37643let Inst{7-5} = 0b101;
37644let Inst{13-13} = 0b0;
37645let Inst{31-21} = 0b00011111011;
37646let hasNewValue = 1;
37647let opNewValue = 0;
37648let isCVI = 1;
37649let DecoderNamespace = "EXT_mmvec";
37650}
37651def V6_vroundwuh_alt : HInst<
37652(outs HvxVR:$Vd32),
37653(ins HvxVR:$Vu32, HvxVR:$Vv32),
37654"$Vd32 = vroundwuh($Vu32,$Vv32):sat",
37655PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37656let hasNewValue = 1;
37657let opNewValue = 0;
37658let isCVI = 1;
37659let isPseudo = 1;
37660let isCodeGenOnly = 1;
37661let DecoderNamespace = "EXT_mmvec";
37662}
37663def V6_vrsadubi : HInst<
37664(outs HvxWR:$Vdd32),
37665(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37666"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
37667tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
37668let Inst{7-6} = 0b11;
37669let Inst{13-13} = 0b0;
37670let Inst{31-21} = 0b00011001010;
37671let hasNewValue = 1;
37672let opNewValue = 0;
37673let isCVI = 1;
37674let DecoderNamespace = "EXT_mmvec";
37675}
37676def V6_vrsadubi_acc : HInst<
37677(outs HvxWR:$Vxx32),
37678(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37679"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
37680tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
37681let Inst{7-6} = 0b11;
37682let Inst{13-13} = 0b1;
37683let Inst{31-21} = 0b00011001010;
37684let hasNewValue = 1;
37685let opNewValue = 0;
37686let isAccumulator = 1;
37687let isCVI = 1;
37688let DecoderNamespace = "EXT_mmvec";
37689let Constraints = "$Vxx32 = $Vxx32in";
37690}
37691def V6_vrsadubi_acc_alt : HInst<
37692(outs HvxWR:$Vxx32),
37693(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37694"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
37695PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37696let hasNewValue = 1;
37697let opNewValue = 0;
37698let isAccumulator = 1;
37699let isCVI = 1;
37700let isPseudo = 1;
37701let isCodeGenOnly = 1;
37702let DecoderNamespace = "EXT_mmvec";
37703let Constraints = "$Vxx32 = $Vxx32in";
37704}
37705def V6_vrsadubi_alt : HInst<
37706(outs HvxWR:$Vdd32),
37707(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37708"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
37709PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37710let hasNewValue = 1;
37711let opNewValue = 0;
37712let isCVI = 1;
37713let isPseudo = 1;
37714let isCodeGenOnly = 1;
37715let DecoderNamespace = "EXT_mmvec";
37716}
37717def V6_vsatdw : HInst<
37718(outs HvxVR:$Vd32),
37719(ins HvxVR:$Vu32, HvxVR:$Vv32),
37720"$Vd32.w = vsatdw($Vu32.w,$Vv32.w)",
37721tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV66]> {
37722let Inst{7-5} = 0b111;
37723let Inst{13-13} = 0b1;
37724let Inst{31-21} = 0b00011101100;
37725let hasNewValue = 1;
37726let opNewValue = 0;
37727let isCVI = 1;
37728let DecoderNamespace = "EXT_mmvec";
37729}
37730def V6_vsathub : HInst<
37731(outs HvxVR:$Vd32),
37732(ins HvxVR:$Vu32, HvxVR:$Vv32),
37733"$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
37734tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37735let Inst{7-5} = 0b010;
37736let Inst{13-13} = 0b0;
37737let Inst{31-21} = 0b00011111011;
37738let hasNewValue = 1;
37739let opNewValue = 0;
37740let isCVI = 1;
37741let DecoderNamespace = "EXT_mmvec";
37742}
37743def V6_vsathub_alt : HInst<
37744(outs HvxVR:$Vd32),
37745(ins HvxVR:$Vu32, HvxVR:$Vv32),
37746"$Vd32 = vsathub($Vu32,$Vv32)",
37747PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37748let hasNewValue = 1;
37749let opNewValue = 0;
37750let isCVI = 1;
37751let isPseudo = 1;
37752let isCodeGenOnly = 1;
37753let DecoderNamespace = "EXT_mmvec";
37754}
37755def V6_vsatuwuh : HInst<
37756(outs HvxVR:$Vd32),
37757(ins HvxVR:$Vu32, HvxVR:$Vv32),
37758"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
37759tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
37760let Inst{7-5} = 0b110;
37761let Inst{13-13} = 0b0;
37762let Inst{31-21} = 0b00011111001;
37763let hasNewValue = 1;
37764let opNewValue = 0;
37765let isCVI = 1;
37766let DecoderNamespace = "EXT_mmvec";
37767}
37768def V6_vsatuwuh_alt : HInst<
37769(outs HvxVR:$Vd32),
37770(ins HvxVR:$Vu32, HvxVR:$Vv32),
37771"$Vd32 = vsatuwuh($Vu32,$Vv32)",
37772PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37773let hasNewValue = 1;
37774let opNewValue = 0;
37775let isCVI = 1;
37776let isPseudo = 1;
37777let isCodeGenOnly = 1;
37778let DecoderNamespace = "EXT_mmvec";
37779}
37780def V6_vsatwh : HInst<
37781(outs HvxVR:$Vd32),
37782(ins HvxVR:$Vu32, HvxVR:$Vv32),
37783"$Vd32.h = vsat($Vu32.w,$Vv32.w)",
37784tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37785let Inst{7-5} = 0b011;
37786let Inst{13-13} = 0b0;
37787let Inst{31-21} = 0b00011111011;
37788let hasNewValue = 1;
37789let opNewValue = 0;
37790let isCVI = 1;
37791let DecoderNamespace = "EXT_mmvec";
37792}
37793def V6_vsatwh_alt : HInst<
37794(outs HvxVR:$Vd32),
37795(ins HvxVR:$Vu32, HvxVR:$Vv32),
37796"$Vd32 = vsatwh($Vu32,$Vv32)",
37797PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37798let hasNewValue = 1;
37799let opNewValue = 0;
37800let isCVI = 1;
37801let isPseudo = 1;
37802let isCodeGenOnly = 1;
37803let DecoderNamespace = "EXT_mmvec";
37804}
37805def V6_vsb : HInst<
37806(outs HvxWR:$Vdd32),
37807(ins HvxVR:$Vu32),
37808"$Vdd32.h = vsxt($Vu32.b)",
37809tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
37810let Inst{7-5} = 0b011;
37811let Inst{13-13} = 0b0;
37812let Inst{31-16} = 0b0001111000000010;
37813let hasNewValue = 1;
37814let opNewValue = 0;
37815let isCVI = 1;
37816let DecoderNamespace = "EXT_mmvec";
37817}
37818def V6_vsb_alt : HInst<
37819(outs HvxWR:$Vdd32),
37820(ins HvxVR:$Vu32),
37821"$Vdd32 = vsxtb($Vu32)",
37822PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37823let hasNewValue = 1;
37824let opNewValue = 0;
37825let isCVI = 1;
37826let isPseudo = 1;
37827let isCodeGenOnly = 1;
37828let DecoderNamespace = "EXT_mmvec";
37829}
37830def V6_vscattermh : HInst<
37831(outs),
37832(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37833"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
37834tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
37835let Inst{7-5} = 0b001;
37836let Inst{31-21} = 0b00101111001;
37837let accessSize = HalfWordAccess;
37838let isCVI = 1;
37839let mayStore = 1;
37840let DecoderNamespace = "EXT_mmvec";
37841}
37842def V6_vscattermh_add : HInst<
37843(outs),
37844(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37845"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
37846tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
37847let Inst{7-5} = 0b101;
37848let Inst{31-21} = 0b00101111001;
37849let accessSize = HalfWordAccess;
37850let isAccumulator = 1;
37851let isCVI = 1;
37852let mayStore = 1;
37853let DecoderNamespace = "EXT_mmvec";
37854}
37855def V6_vscattermh_add_alt : HInst<
37856(outs),
37857(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37858"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
37859PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37860let isAccumulator = 1;
37861let isCVI = 1;
37862let isPseudo = 1;
37863let isCodeGenOnly = 1;
37864let DecoderNamespace = "EXT_mmvec";
37865}
37866def V6_vscattermh_alt : HInst<
37867(outs),
37868(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37869"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
37870PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37871let isCVI = 1;
37872let isPseudo = 1;
37873let isCodeGenOnly = 1;
37874let DecoderNamespace = "EXT_mmvec";
37875}
37876def V6_vscattermhq : HInst<
37877(outs),
37878(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37879"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
37880tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
37881let Inst{7-7} = 0b1;
37882let Inst{31-21} = 0b00101111100;
37883let accessSize = HalfWordAccess;
37884let isCVI = 1;
37885let mayStore = 1;
37886let DecoderNamespace = "EXT_mmvec";
37887}
37888def V6_vscattermhq_alt : HInst<
37889(outs),
37890(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37891"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
37892PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37893let isCVI = 1;
37894let isPseudo = 1;
37895let isCodeGenOnly = 1;
37896let DecoderNamespace = "EXT_mmvec";
37897}
37898def V6_vscattermhw : HInst<
37899(outs),
37900(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37901"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
37902tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
37903let Inst{7-5} = 0b010;
37904let Inst{31-21} = 0b00101111001;
37905let accessSize = HalfWordAccess;
37906let isCVI = 1;
37907let mayStore = 1;
37908let DecoderNamespace = "EXT_mmvec";
37909}
37910def V6_vscattermhw_add : HInst<
37911(outs),
37912(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37913"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
37914tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
37915let Inst{7-5} = 0b110;
37916let Inst{31-21} = 0b00101111001;
37917let accessSize = HalfWordAccess;
37918let isAccumulator = 1;
37919let isCVI = 1;
37920let mayStore = 1;
37921let DecoderNamespace = "EXT_mmvec";
37922}
37923def V6_vscattermhwq : HInst<
37924(outs),
37925(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37926"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
37927tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
37928let Inst{7-7} = 0b0;
37929let Inst{31-21} = 0b00101111101;
37930let accessSize = HalfWordAccess;
37931let isCVI = 1;
37932let mayStore = 1;
37933let DecoderNamespace = "EXT_mmvec";
37934}
37935def V6_vscattermw : HInst<
37936(outs),
37937(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37938"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
37939tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
37940let Inst{7-5} = 0b000;
37941let Inst{31-21} = 0b00101111001;
37942let accessSize = WordAccess;
37943let isCVI = 1;
37944let mayStore = 1;
37945let DecoderNamespace = "EXT_mmvec";
37946}
37947def V6_vscattermw_add : HInst<
37948(outs),
37949(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37950"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
37951tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
37952let Inst{7-5} = 0b100;
37953let Inst{31-21} = 0b00101111001;
37954let accessSize = WordAccess;
37955let isAccumulator = 1;
37956let isCVI = 1;
37957let mayStore = 1;
37958let DecoderNamespace = "EXT_mmvec";
37959}
37960def V6_vscattermw_add_alt : HInst<
37961(outs),
37962(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37963"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
37964PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37965let isAccumulator = 1;
37966let isCVI = 1;
37967let isPseudo = 1;
37968let isCodeGenOnly = 1;
37969let DecoderNamespace = "EXT_mmvec";
37970}
37971def V6_vscattermw_alt : HInst<
37972(outs),
37973(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37974"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
37975PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37976let isCVI = 1;
37977let isPseudo = 1;
37978let isCodeGenOnly = 1;
37979let DecoderNamespace = "EXT_mmvec";
37980}
37981def V6_vscattermwh_add_alt : HInst<
37982(outs),
37983(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37984"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
37985PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37986let isAccumulator = 1;
37987let isCVI = 1;
37988let isPseudo = 1;
37989let isCodeGenOnly = 1;
37990let DecoderNamespace = "EXT_mmvec";
37991}
37992def V6_vscattermwh_alt : HInst<
37993(outs),
37994(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37995"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
37996PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37997let isCVI = 1;
37998let isPseudo = 1;
37999let isCodeGenOnly = 1;
38000let DecoderNamespace = "EXT_mmvec";
38001}
38002def V6_vscattermwhq_alt : HInst<
38003(outs),
38004(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38005"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
38006PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38007let isCVI = 1;
38008let isPseudo = 1;
38009let isCodeGenOnly = 1;
38010let DecoderNamespace = "EXT_mmvec";
38011}
38012def V6_vscattermwq : HInst<
38013(outs),
38014(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38015"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
38016tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
38017let Inst{7-7} = 0b0;
38018let Inst{31-21} = 0b00101111100;
38019let accessSize = WordAccess;
38020let isCVI = 1;
38021let mayStore = 1;
38022let DecoderNamespace = "EXT_mmvec";
38023}
38024def V6_vscattermwq_alt : HInst<
38025(outs),
38026(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38027"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
38028PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38029let isCVI = 1;
38030let isPseudo = 1;
38031let isCodeGenOnly = 1;
38032let DecoderNamespace = "EXT_mmvec";
38033}
38034def V6_vsh : HInst<
38035(outs HvxWR:$Vdd32),
38036(ins HvxVR:$Vu32),
38037"$Vdd32.w = vsxt($Vu32.h)",
38038tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38039let Inst{7-5} = 0b100;
38040let Inst{13-13} = 0b0;
38041let Inst{31-16} = 0b0001111000000010;
38042let hasNewValue = 1;
38043let opNewValue = 0;
38044let isCVI = 1;
38045let DecoderNamespace = "EXT_mmvec";
38046}
38047def V6_vsh_alt : HInst<
38048(outs HvxWR:$Vdd32),
38049(ins HvxVR:$Vu32),
38050"$Vdd32 = vsxth($Vu32)",
38051PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38052let hasNewValue = 1;
38053let opNewValue = 0;
38054let isCVI = 1;
38055let isPseudo = 1;
38056let isCodeGenOnly = 1;
38057let DecoderNamespace = "EXT_mmvec";
38058}
38059def V6_vshufeh : HInst<
38060(outs HvxVR:$Vd32),
38061(ins HvxVR:$Vu32, HvxVR:$Vv32),
38062"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
38063tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38064let Inst{7-5} = 0b011;
38065let Inst{13-13} = 0b0;
38066let Inst{31-21} = 0b00011111010;
38067let hasNewValue = 1;
38068let opNewValue = 0;
38069let isCVI = 1;
38070let DecoderNamespace = "EXT_mmvec";
38071}
38072def V6_vshufeh_alt : HInst<
38073(outs HvxVR:$Vd32),
38074(ins HvxVR:$Vu32, HvxVR:$Vv32),
38075"$Vd32 = vshuffeh($Vu32,$Vv32)",
38076PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38077let hasNewValue = 1;
38078let opNewValue = 0;
38079let isCVI = 1;
38080let isPseudo = 1;
38081let isCodeGenOnly = 1;
38082let DecoderNamespace = "EXT_mmvec";
38083}
38084def V6_vshuff : HInst<
38085(outs HvxVR:$Vy32, HvxVR:$Vx32),
38086(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
38087"vshuff($Vy32,$Vx32,$Rt32)",
38088tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
38089let Inst{7-5} = 0b001;
38090let Inst{13-13} = 0b1;
38091let Inst{31-21} = 0b00011001111;
38092let hasNewValue = 1;
38093let opNewValue = 0;
38094let hasNewValue2 = 1;
38095let opNewValue2 = 1;
38096let isCVI = 1;
38097let DecoderNamespace = "EXT_mmvec";
38098let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
38099}
38100def V6_vshuffb : HInst<
38101(outs HvxVR:$Vd32),
38102(ins HvxVR:$Vu32),
38103"$Vd32.b = vshuff($Vu32.b)",
38104tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
38105let Inst{7-5} = 0b000;
38106let Inst{13-13} = 0b0;
38107let Inst{31-16} = 0b0001111000000010;
38108let hasNewValue = 1;
38109let opNewValue = 0;
38110let isCVI = 1;
38111let DecoderNamespace = "EXT_mmvec";
38112}
38113def V6_vshuffb_alt : HInst<
38114(outs HvxVR:$Vd32),
38115(ins HvxVR:$Vu32),
38116"$Vd32 = vshuffb($Vu32)",
38117PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38118let hasNewValue = 1;
38119let opNewValue = 0;
38120let isCVI = 1;
38121let isPseudo = 1;
38122let isCodeGenOnly = 1;
38123let DecoderNamespace = "EXT_mmvec";
38124}
38125def V6_vshuffeb : HInst<
38126(outs HvxVR:$Vd32),
38127(ins HvxVR:$Vu32, HvxVR:$Vv32),
38128"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
38129tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38130let Inst{7-5} = 0b001;
38131let Inst{13-13} = 0b0;
38132let Inst{31-21} = 0b00011111010;
38133let hasNewValue = 1;
38134let opNewValue = 0;
38135let isCVI = 1;
38136let DecoderNamespace = "EXT_mmvec";
38137}
38138def V6_vshuffeb_alt : HInst<
38139(outs HvxVR:$Vd32),
38140(ins HvxVR:$Vu32, HvxVR:$Vv32),
38141"$Vd32 = vshuffeb($Vu32,$Vv32)",
38142PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38143let hasNewValue = 1;
38144let opNewValue = 0;
38145let isCVI = 1;
38146let isPseudo = 1;
38147let isCodeGenOnly = 1;
38148let DecoderNamespace = "EXT_mmvec";
38149}
38150def V6_vshuffh : HInst<
38151(outs HvxVR:$Vd32),
38152(ins HvxVR:$Vu32),
38153"$Vd32.h = vshuff($Vu32.h)",
38154tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
38155let Inst{7-5} = 0b111;
38156let Inst{13-13} = 0b0;
38157let Inst{31-16} = 0b0001111000000001;
38158let hasNewValue = 1;
38159let opNewValue = 0;
38160let isCVI = 1;
38161let DecoderNamespace = "EXT_mmvec";
38162}
38163def V6_vshuffh_alt : HInst<
38164(outs HvxVR:$Vd32),
38165(ins HvxVR:$Vu32),
38166"$Vd32 = vshuffh($Vu32)",
38167PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38168let hasNewValue = 1;
38169let opNewValue = 0;
38170let isCVI = 1;
38171let isPseudo = 1;
38172let isCodeGenOnly = 1;
38173let DecoderNamespace = "EXT_mmvec";
38174}
38175def V6_vshuffob : HInst<
38176(outs HvxVR:$Vd32),
38177(ins HvxVR:$Vu32, HvxVR:$Vv32),
38178"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
38179tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38180let Inst{7-5} = 0b010;
38181let Inst{13-13} = 0b0;
38182let Inst{31-21} = 0b00011111010;
38183let hasNewValue = 1;
38184let opNewValue = 0;
38185let isCVI = 1;
38186let DecoderNamespace = "EXT_mmvec";
38187}
38188def V6_vshuffob_alt : HInst<
38189(outs HvxVR:$Vd32),
38190(ins HvxVR:$Vu32, HvxVR:$Vv32),
38191"$Vd32 = vshuffob($Vu32,$Vv32)",
38192PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38193let hasNewValue = 1;
38194let opNewValue = 0;
38195let isCVI = 1;
38196let isPseudo = 1;
38197let isCodeGenOnly = 1;
38198let DecoderNamespace = "EXT_mmvec";
38199}
38200def V6_vshuffvdd : HInst<
38201(outs HvxWR:$Vdd32),
38202(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
38203"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
38204tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
38205let Inst{7-5} = 0b011;
38206let Inst{13-13} = 0b1;
38207let Inst{31-24} = 0b00011011;
38208let hasNewValue = 1;
38209let opNewValue = 0;
38210let isCVI = 1;
38211let DecoderNamespace = "EXT_mmvec";
38212}
38213def V6_vshufoeb : HInst<
38214(outs HvxWR:$Vdd32),
38215(ins HvxVR:$Vu32, HvxVR:$Vv32),
38216"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
38217tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38218let Inst{7-5} = 0b110;
38219let Inst{13-13} = 0b0;
38220let Inst{31-21} = 0b00011111010;
38221let hasNewValue = 1;
38222let opNewValue = 0;
38223let isCVI = 1;
38224let DecoderNamespace = "EXT_mmvec";
38225}
38226def V6_vshufoeb_alt : HInst<
38227(outs HvxWR:$Vdd32),
38228(ins HvxVR:$Vu32, HvxVR:$Vv32),
38229"$Vdd32 = vshuffoeb($Vu32,$Vv32)",
38230PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38231let hasNewValue = 1;
38232let opNewValue = 0;
38233let isCVI = 1;
38234let isPseudo = 1;
38235let isCodeGenOnly = 1;
38236let DecoderNamespace = "EXT_mmvec";
38237}
38238def V6_vshufoeh : HInst<
38239(outs HvxWR:$Vdd32),
38240(ins HvxVR:$Vu32, HvxVR:$Vv32),
38241"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
38242tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38243let Inst{7-5} = 0b101;
38244let Inst{13-13} = 0b0;
38245let Inst{31-21} = 0b00011111010;
38246let hasNewValue = 1;
38247let opNewValue = 0;
38248let isCVI = 1;
38249let DecoderNamespace = "EXT_mmvec";
38250}
38251def V6_vshufoeh_alt : HInst<
38252(outs HvxWR:$Vdd32),
38253(ins HvxVR:$Vu32, HvxVR:$Vv32),
38254"$Vdd32 = vshuffoeh($Vu32,$Vv32)",
38255PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38256let hasNewValue = 1;
38257let opNewValue = 0;
38258let isCVI = 1;
38259let isPseudo = 1;
38260let isCodeGenOnly = 1;
38261let DecoderNamespace = "EXT_mmvec";
38262}
38263def V6_vshufoh : HInst<
38264(outs HvxVR:$Vd32),
38265(ins HvxVR:$Vu32, HvxVR:$Vv32),
38266"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
38267tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38268let Inst{7-5} = 0b100;
38269let Inst{13-13} = 0b0;
38270let Inst{31-21} = 0b00011111010;
38271let hasNewValue = 1;
38272let opNewValue = 0;
38273let isCVI = 1;
38274let DecoderNamespace = "EXT_mmvec";
38275}
38276def V6_vshufoh_alt : HInst<
38277(outs HvxVR:$Vd32),
38278(ins HvxVR:$Vu32, HvxVR:$Vv32),
38279"$Vd32 = vshuffoh($Vu32,$Vv32)",
38280PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38281let hasNewValue = 1;
38282let opNewValue = 0;
38283let isCVI = 1;
38284let isPseudo = 1;
38285let isCodeGenOnly = 1;
38286let DecoderNamespace = "EXT_mmvec";
38287}
38288def V6_vsub_hf : HInst<
38289(outs HvxVR:$Vd32),
38290(ins HvxVR:$Vu32, HvxVR:$Vv32),
38291"$Vd32.qf16 = vsub($Vu32.hf,$Vv32.hf)",
38292tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38293let Inst{7-5} = 0b110;
38294let Inst{13-13} = 0b1;
38295let Inst{31-21} = 0b00011111011;
38296let hasNewValue = 1;
38297let opNewValue = 0;
38298let isCVI = 1;
38299let DecoderNamespace = "EXT_mmvec";
38300}
38301def V6_vsub_hf_hf : HInst<
38302(outs HvxVR:$Vd32),
38303(ins HvxVR:$Vu32, HvxVR:$Vv32),
38304"$Vd32.hf = vsub($Vu32.hf,$Vv32.hf)",
38305tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38306let Inst{7-5} = 0b000;
38307let Inst{13-13} = 0b1;
38308let Inst{31-21} = 0b00011111011;
38309let hasNewValue = 1;
38310let opNewValue = 0;
38311let isCVI = 1;
38312let DecoderNamespace = "EXT_mmvec";
38313}
38314def V6_vsub_qf16 : HInst<
38315(outs HvxVR:$Vd32),
38316(ins HvxVR:$Vu32, HvxVR:$Vv32),
38317"$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.qf16)",
38318tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38319let Inst{7-5} = 0b101;
38320let Inst{13-13} = 0b1;
38321let Inst{31-21} = 0b00011111011;
38322let hasNewValue = 1;
38323let opNewValue = 0;
38324let isCVI = 1;
38325let DecoderNamespace = "EXT_mmvec";
38326}
38327def V6_vsub_qf16_mix : HInst<
38328(outs HvxVR:$Vd32),
38329(ins HvxVR:$Vu32, HvxVR:$Vv32),
38330"$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.hf)",
38331tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38332let Inst{7-5} = 0b111;
38333let Inst{13-13} = 0b1;
38334let Inst{31-21} = 0b00011111011;
38335let hasNewValue = 1;
38336let opNewValue = 0;
38337let isCVI = 1;
38338let DecoderNamespace = "EXT_mmvec";
38339}
38340def V6_vsub_qf32 : HInst<
38341(outs HvxVR:$Vd32),
38342(ins HvxVR:$Vu32, HvxVR:$Vv32),
38343"$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.qf32)",
38344tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38345let Inst{7-5} = 0b011;
38346let Inst{13-13} = 0b1;
38347let Inst{31-21} = 0b00011111101;
38348let hasNewValue = 1;
38349let opNewValue = 0;
38350let isCVI = 1;
38351let DecoderNamespace = "EXT_mmvec";
38352}
38353def V6_vsub_qf32_mix : HInst<
38354(outs HvxVR:$Vd32),
38355(ins HvxVR:$Vu32, HvxVR:$Vv32),
38356"$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.sf)",
38357tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38358let Inst{7-5} = 0b101;
38359let Inst{13-13} = 0b1;
38360let Inst{31-21} = 0b00011111101;
38361let hasNewValue = 1;
38362let opNewValue = 0;
38363let isCVI = 1;
38364let DecoderNamespace = "EXT_mmvec";
38365}
38366def V6_vsub_sf : HInst<
38367(outs HvxVR:$Vd32),
38368(ins HvxVR:$Vu32, HvxVR:$Vv32),
38369"$Vd32.qf32 = vsub($Vu32.sf,$Vv32.sf)",
38370tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38371let Inst{7-5} = 0b100;
38372let Inst{13-13} = 0b1;
38373let Inst{31-21} = 0b00011111101;
38374let hasNewValue = 1;
38375let opNewValue = 0;
38376let isCVI = 1;
38377let DecoderNamespace = "EXT_mmvec";
38378}
38379def V6_vsub_sf_hf : HInst<
38380(outs HvxWR:$Vdd32),
38381(ins HvxVR:$Vu32, HvxVR:$Vv32),
38382"$Vdd32.sf = vsub($Vu32.hf,$Vv32.hf)",
38383tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38384let Inst{7-5} = 0b101;
38385let Inst{13-13} = 0b1;
38386let Inst{31-21} = 0b00011111100;
38387let hasNewValue = 1;
38388let opNewValue = 0;
38389let isCVI = 1;
38390let DecoderNamespace = "EXT_mmvec";
38391}
38392def V6_vsub_sf_sf : HInst<
38393(outs HvxVR:$Vd32),
38394(ins HvxVR:$Vu32, HvxVR:$Vv32),
38395"$Vd32.sf = vsub($Vu32.sf,$Vv32.sf)",
38396tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38397let Inst{7-5} = 0b111;
38398let Inst{13-13} = 0b1;
38399let Inst{31-21} = 0b00011111100;
38400let hasNewValue = 1;
38401let opNewValue = 0;
38402let isCVI = 1;
38403let DecoderNamespace = "EXT_mmvec";
38404}
38405def V6_vsubb : HInst<
38406(outs HvxVR:$Vd32),
38407(ins HvxVR:$Vu32, HvxVR:$Vv32),
38408"$Vd32.b = vsub($Vu32.b,$Vv32.b)",
38409tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38410let Inst{7-5} = 0b101;
38411let Inst{13-13} = 0b0;
38412let Inst{31-21} = 0b00011100010;
38413let hasNewValue = 1;
38414let opNewValue = 0;
38415let isCVI = 1;
38416let DecoderNamespace = "EXT_mmvec";
38417}
38418def V6_vsubb_alt : HInst<
38419(outs HvxVR:$Vd32),
38420(ins HvxVR:$Vu32, HvxVR:$Vv32),
38421"$Vd32 = vsubb($Vu32,$Vv32)",
38422PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38423let hasNewValue = 1;
38424let opNewValue = 0;
38425let isCVI = 1;
38426let isPseudo = 1;
38427let isCodeGenOnly = 1;
38428let DecoderNamespace = "EXT_mmvec";
38429}
38430def V6_vsubb_dv : HInst<
38431(outs HvxWR:$Vdd32),
38432(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38433"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
38434tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
38435let Inst{7-5} = 0b011;
38436let Inst{13-13} = 0b0;
38437let Inst{31-21} = 0b00011100100;
38438let hasNewValue = 1;
38439let opNewValue = 0;
38440let isCVI = 1;
38441let DecoderNamespace = "EXT_mmvec";
38442}
38443def V6_vsubb_dv_alt : HInst<
38444(outs HvxWR:$Vdd32),
38445(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38446"$Vdd32 = vsubb($Vuu32,$Vvv32)",
38447PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38448let hasNewValue = 1;
38449let opNewValue = 0;
38450let isCVI = 1;
38451let isPseudo = 1;
38452let isCodeGenOnly = 1;
38453let DecoderNamespace = "EXT_mmvec";
38454}
38455def V6_vsubbnq : HInst<
38456(outs HvxVR:$Vx32),
38457(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38458"if (!$Qv4) $Vx32.b -= $Vu32.b",
38459tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
38460let Inst{7-5} = 0b001;
38461let Inst{13-13} = 0b1;
38462let Inst{21-16} = 0b000010;
38463let Inst{31-24} = 0b00011110;
38464let hasNewValue = 1;
38465let opNewValue = 0;
38466let isCVI = 1;
38467let DecoderNamespace = "EXT_mmvec";
38468let Constraints = "$Vx32 = $Vx32in";
38469}
38470def V6_vsubbnq_alt : HInst<
38471(outs HvxVR:$Vx32),
38472(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38473"if (!$Qv4.b) $Vx32.b -= $Vu32.b",
38474PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38475let hasNewValue = 1;
38476let opNewValue = 0;
38477let isCVI = 1;
38478let isPseudo = 1;
38479let isCodeGenOnly = 1;
38480let DecoderNamespace = "EXT_mmvec";
38481let Constraints = "$Vx32 = $Vx32in";
38482}
38483def V6_vsubbq : HInst<
38484(outs HvxVR:$Vx32),
38485(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38486"if ($Qv4) $Vx32.b -= $Vu32.b",
38487tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
38488let Inst{7-5} = 0b110;
38489let Inst{13-13} = 0b1;
38490let Inst{21-16} = 0b000001;
38491let Inst{31-24} = 0b00011110;
38492let hasNewValue = 1;
38493let opNewValue = 0;
38494let isCVI = 1;
38495let DecoderNamespace = "EXT_mmvec";
38496let Constraints = "$Vx32 = $Vx32in";
38497}
38498def V6_vsubbq_alt : HInst<
38499(outs HvxVR:$Vx32),
38500(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38501"if ($Qv4.b) $Vx32.b -= $Vu32.b",
38502PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38503let hasNewValue = 1;
38504let opNewValue = 0;
38505let isCVI = 1;
38506let isPseudo = 1;
38507let isCodeGenOnly = 1;
38508let DecoderNamespace = "EXT_mmvec";
38509let Constraints = "$Vx32 = $Vx32in";
38510}
38511def V6_vsubbsat : HInst<
38512(outs HvxVR:$Vd32),
38513(ins HvxVR:$Vu32, HvxVR:$Vv32),
38514"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
38515tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
38516let Inst{7-5} = 0b010;
38517let Inst{13-13} = 0b0;
38518let Inst{31-21} = 0b00011111001;
38519let hasNewValue = 1;
38520let opNewValue = 0;
38521let isCVI = 1;
38522let DecoderNamespace = "EXT_mmvec";
38523}
38524def V6_vsubbsat_alt : HInst<
38525(outs HvxVR:$Vd32),
38526(ins HvxVR:$Vu32, HvxVR:$Vv32),
38527"$Vd32 = vsubb($Vu32,$Vv32):sat",
38528PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38529let hasNewValue = 1;
38530let opNewValue = 0;
38531let isCVI = 1;
38532let isPseudo = 1;
38533let isCodeGenOnly = 1;
38534let DecoderNamespace = "EXT_mmvec";
38535}
38536def V6_vsubbsat_dv : HInst<
38537(outs HvxWR:$Vdd32),
38538(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38539"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
38540tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
38541let Inst{7-5} = 0b001;
38542let Inst{13-13} = 0b0;
38543let Inst{31-21} = 0b00011110101;
38544let hasNewValue = 1;
38545let opNewValue = 0;
38546let isCVI = 1;
38547let DecoderNamespace = "EXT_mmvec";
38548}
38549def V6_vsubbsat_dv_alt : HInst<
38550(outs HvxWR:$Vdd32),
38551(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38552"$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
38553PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38554let hasNewValue = 1;
38555let opNewValue = 0;
38556let isCVI = 1;
38557let isPseudo = 1;
38558let isCodeGenOnly = 1;
38559let DecoderNamespace = "EXT_mmvec";
38560}
38561def V6_vsubcarry : HInst<
38562(outs HvxVR:$Vd32, HvxQR:$Qx4),
38563(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
38564"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
38565tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
38566let Inst{7-7} = 0b1;
38567let Inst{13-13} = 0b1;
38568let Inst{31-21} = 0b00011100101;
38569let hasNewValue = 1;
38570let opNewValue = 0;
38571let isCVI = 1;
38572let DecoderNamespace = "EXT_mmvec";
38573let Constraints = "$Qx4 = $Qx4in";
38574}
38575def V6_vsubcarryo : HInst<
38576(outs HvxVR:$Vd32, HvxQR:$Qe4),
38577(ins HvxVR:$Vu32, HvxVR:$Vv32),
38578"$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry",
38579tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
38580let Inst{7-7} = 0b1;
38581let Inst{13-13} = 0b1;
38582let Inst{31-21} = 0b00011101101;
38583let hasNewValue = 1;
38584let opNewValue = 0;
38585let hasNewValue2 = 1;
38586let opNewValue2 = 1;
38587let isCVI = 1;
38588let DecoderNamespace = "EXT_mmvec";
38589}
38590def V6_vsubh : HInst<
38591(outs HvxVR:$Vd32),
38592(ins HvxVR:$Vu32, HvxVR:$Vv32),
38593"$Vd32.h = vsub($Vu32.h,$Vv32.h)",
38594tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38595let Inst{7-5} = 0b110;
38596let Inst{13-13} = 0b0;
38597let Inst{31-21} = 0b00011100010;
38598let hasNewValue = 1;
38599let opNewValue = 0;
38600let isCVI = 1;
38601let DecoderNamespace = "EXT_mmvec";
38602}
38603def V6_vsubh_alt : HInst<
38604(outs HvxVR:$Vd32),
38605(ins HvxVR:$Vu32, HvxVR:$Vv32),
38606"$Vd32 = vsubh($Vu32,$Vv32)",
38607PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38608let hasNewValue = 1;
38609let opNewValue = 0;
38610let isCVI = 1;
38611let isPseudo = 1;
38612let isCodeGenOnly = 1;
38613let DecoderNamespace = "EXT_mmvec";
38614}
38615def V6_vsubh_dv : HInst<
38616(outs HvxWR:$Vdd32),
38617(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38618"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
38619tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
38620let Inst{7-5} = 0b100;
38621let Inst{13-13} = 0b0;
38622let Inst{31-21} = 0b00011100100;
38623let hasNewValue = 1;
38624let opNewValue = 0;
38625let isCVI = 1;
38626let DecoderNamespace = "EXT_mmvec";
38627}
38628def V6_vsubh_dv_alt : HInst<
38629(outs HvxWR:$Vdd32),
38630(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38631"$Vdd32 = vsubh($Vuu32,$Vvv32)",
38632PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38633let hasNewValue = 1;
38634let opNewValue = 0;
38635let isCVI = 1;
38636let isPseudo = 1;
38637let isCodeGenOnly = 1;
38638let DecoderNamespace = "EXT_mmvec";
38639}
38640def V6_vsubhnq : HInst<
38641(outs HvxVR:$Vx32),
38642(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38643"if (!$Qv4) $Vx32.h -= $Vu32.h",
38644tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
38645let Inst{7-5} = 0b010;
38646let Inst{13-13} = 0b1;
38647let Inst{21-16} = 0b000010;
38648let Inst{31-24} = 0b00011110;
38649let hasNewValue = 1;
38650let opNewValue = 0;
38651let isCVI = 1;
38652let DecoderNamespace = "EXT_mmvec";
38653let Constraints = "$Vx32 = $Vx32in";
38654}
38655def V6_vsubhnq_alt : HInst<
38656(outs HvxVR:$Vx32),
38657(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38658"if (!$Qv4.h) $Vx32.h -= $Vu32.h",
38659PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38660let hasNewValue = 1;
38661let opNewValue = 0;
38662let isCVI = 1;
38663let isPseudo = 1;
38664let isCodeGenOnly = 1;
38665let DecoderNamespace = "EXT_mmvec";
38666let Constraints = "$Vx32 = $Vx32in";
38667}
38668def V6_vsubhq : HInst<
38669(outs HvxVR:$Vx32),
38670(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38671"if ($Qv4) $Vx32.h -= $Vu32.h",
38672tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
38673let Inst{7-5} = 0b111;
38674let Inst{13-13} = 0b1;
38675let Inst{21-16} = 0b000001;
38676let Inst{31-24} = 0b00011110;
38677let hasNewValue = 1;
38678let opNewValue = 0;
38679let isCVI = 1;
38680let DecoderNamespace = "EXT_mmvec";
38681let Constraints = "$Vx32 = $Vx32in";
38682}
38683def V6_vsubhq_alt : HInst<
38684(outs HvxVR:$Vx32),
38685(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38686"if ($Qv4.h) $Vx32.h -= $Vu32.h",
38687PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38688let hasNewValue = 1;
38689let opNewValue = 0;
38690let isCVI = 1;
38691let isPseudo = 1;
38692let isCodeGenOnly = 1;
38693let DecoderNamespace = "EXT_mmvec";
38694let Constraints = "$Vx32 = $Vx32in";
38695}
38696def V6_vsubhsat : HInst<
38697(outs HvxVR:$Vd32),
38698(ins HvxVR:$Vu32, HvxVR:$Vv32),
38699"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
38700tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38701let Inst{7-5} = 0b010;
38702let Inst{13-13} = 0b0;
38703let Inst{31-21} = 0b00011100011;
38704let hasNewValue = 1;
38705let opNewValue = 0;
38706let isCVI = 1;
38707let DecoderNamespace = "EXT_mmvec";
38708}
38709def V6_vsubhsat_alt : HInst<
38710(outs HvxVR:$Vd32),
38711(ins HvxVR:$Vu32, HvxVR:$Vv32),
38712"$Vd32 = vsubh($Vu32,$Vv32):sat",
38713PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38714let hasNewValue = 1;
38715let opNewValue = 0;
38716let isCVI = 1;
38717let isPseudo = 1;
38718let isCodeGenOnly = 1;
38719let DecoderNamespace = "EXT_mmvec";
38720}
38721def V6_vsubhsat_dv : HInst<
38722(outs HvxWR:$Vdd32),
38723(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38724"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
38725tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
38726let Inst{7-5} = 0b000;
38727let Inst{13-13} = 0b0;
38728let Inst{31-21} = 0b00011100101;
38729let hasNewValue = 1;
38730let opNewValue = 0;
38731let isCVI = 1;
38732let DecoderNamespace = "EXT_mmvec";
38733}
38734def V6_vsubhsat_dv_alt : HInst<
38735(outs HvxWR:$Vdd32),
38736(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38737"$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
38738PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38739let hasNewValue = 1;
38740let opNewValue = 0;
38741let isCVI = 1;
38742let isPseudo = 1;
38743let isCodeGenOnly = 1;
38744let DecoderNamespace = "EXT_mmvec";
38745}
38746def V6_vsubhw : HInst<
38747(outs HvxWR:$Vdd32),
38748(ins HvxVR:$Vu32, HvxVR:$Vv32),
38749"$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
38750tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38751let Inst{7-5} = 0b111;
38752let Inst{13-13} = 0b0;
38753let Inst{31-21} = 0b00011100101;
38754let hasNewValue = 1;
38755let opNewValue = 0;
38756let isCVI = 1;
38757let DecoderNamespace = "EXT_mmvec";
38758}
38759def V6_vsubhw_alt : HInst<
38760(outs HvxWR:$Vdd32),
38761(ins HvxVR:$Vu32, HvxVR:$Vv32),
38762"$Vdd32 = vsubh($Vu32,$Vv32)",
38763PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38764let hasNewValue = 1;
38765let opNewValue = 0;
38766let isCVI = 1;
38767let isPseudo = 1;
38768let isCodeGenOnly = 1;
38769let DecoderNamespace = "EXT_mmvec";
38770}
38771def V6_vsububh : HInst<
38772(outs HvxWR:$Vdd32),
38773(ins HvxVR:$Vu32, HvxVR:$Vv32),
38774"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
38775tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38776let Inst{7-5} = 0b101;
38777let Inst{13-13} = 0b0;
38778let Inst{31-21} = 0b00011100101;
38779let hasNewValue = 1;
38780let opNewValue = 0;
38781let isCVI = 1;
38782let DecoderNamespace = "EXT_mmvec";
38783}
38784def V6_vsububh_alt : HInst<
38785(outs HvxWR:$Vdd32),
38786(ins HvxVR:$Vu32, HvxVR:$Vv32),
38787"$Vdd32 = vsubub($Vu32,$Vv32)",
38788PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38789let hasNewValue = 1;
38790let opNewValue = 0;
38791let isCVI = 1;
38792let isPseudo = 1;
38793let isCodeGenOnly = 1;
38794let DecoderNamespace = "EXT_mmvec";
38795}
38796def V6_vsububsat : HInst<
38797(outs HvxVR:$Vd32),
38798(ins HvxVR:$Vu32, HvxVR:$Vv32),
38799"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
38800tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38801let Inst{7-5} = 0b000;
38802let Inst{13-13} = 0b0;
38803let Inst{31-21} = 0b00011100011;
38804let hasNewValue = 1;
38805let opNewValue = 0;
38806let isCVI = 1;
38807let DecoderNamespace = "EXT_mmvec";
38808}
38809def V6_vsububsat_alt : HInst<
38810(outs HvxVR:$Vd32),
38811(ins HvxVR:$Vu32, HvxVR:$Vv32),
38812"$Vd32 = vsubub($Vu32,$Vv32):sat",
38813PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38814let hasNewValue = 1;
38815let opNewValue = 0;
38816let isCVI = 1;
38817let isPseudo = 1;
38818let isCodeGenOnly = 1;
38819let DecoderNamespace = "EXT_mmvec";
38820}
38821def V6_vsububsat_dv : HInst<
38822(outs HvxWR:$Vdd32),
38823(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38824"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
38825tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
38826let Inst{7-5} = 0b110;
38827let Inst{13-13} = 0b0;
38828let Inst{31-21} = 0b00011100100;
38829let hasNewValue = 1;
38830let opNewValue = 0;
38831let isCVI = 1;
38832let DecoderNamespace = "EXT_mmvec";
38833}
38834def V6_vsububsat_dv_alt : HInst<
38835(outs HvxWR:$Vdd32),
38836(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38837"$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
38838PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38839let hasNewValue = 1;
38840let opNewValue = 0;
38841let isCVI = 1;
38842let isPseudo = 1;
38843let isCodeGenOnly = 1;
38844let DecoderNamespace = "EXT_mmvec";
38845}
38846def V6_vsubububb_sat : HInst<
38847(outs HvxVR:$Vd32),
38848(ins HvxVR:$Vu32, HvxVR:$Vv32),
38849"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
38850tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
38851let Inst{7-5} = 0b101;
38852let Inst{13-13} = 0b0;
38853let Inst{31-21} = 0b00011110101;
38854let hasNewValue = 1;
38855let opNewValue = 0;
38856let isCVI = 1;
38857let DecoderNamespace = "EXT_mmvec";
38858}
38859def V6_vsubuhsat : HInst<
38860(outs HvxVR:$Vd32),
38861(ins HvxVR:$Vu32, HvxVR:$Vv32),
38862"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
38863tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38864let Inst{7-5} = 0b001;
38865let Inst{13-13} = 0b0;
38866let Inst{31-21} = 0b00011100011;
38867let hasNewValue = 1;
38868let opNewValue = 0;
38869let isCVI = 1;
38870let DecoderNamespace = "EXT_mmvec";
38871}
38872def V6_vsubuhsat_alt : HInst<
38873(outs HvxVR:$Vd32),
38874(ins HvxVR:$Vu32, HvxVR:$Vv32),
38875"$Vd32 = vsubuh($Vu32,$Vv32):sat",
38876PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38877let hasNewValue = 1;
38878let opNewValue = 0;
38879let isCVI = 1;
38880let isPseudo = 1;
38881let isCodeGenOnly = 1;
38882let DecoderNamespace = "EXT_mmvec";
38883}
38884def V6_vsubuhsat_dv : HInst<
38885(outs HvxWR:$Vdd32),
38886(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38887"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
38888tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
38889let Inst{7-5} = 0b111;
38890let Inst{13-13} = 0b0;
38891let Inst{31-21} = 0b00011100100;
38892let hasNewValue = 1;
38893let opNewValue = 0;
38894let isCVI = 1;
38895let DecoderNamespace = "EXT_mmvec";
38896}
38897def V6_vsubuhsat_dv_alt : HInst<
38898(outs HvxWR:$Vdd32),
38899(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38900"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
38901PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38902let hasNewValue = 1;
38903let opNewValue = 0;
38904let isCVI = 1;
38905let isPseudo = 1;
38906let isCodeGenOnly = 1;
38907let DecoderNamespace = "EXT_mmvec";
38908}
38909def V6_vsubuhw : HInst<
38910(outs HvxWR:$Vdd32),
38911(ins HvxVR:$Vu32, HvxVR:$Vv32),
38912"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
38913tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38914let Inst{7-5} = 0b110;
38915let Inst{13-13} = 0b0;
38916let Inst{31-21} = 0b00011100101;
38917let hasNewValue = 1;
38918let opNewValue = 0;
38919let isCVI = 1;
38920let DecoderNamespace = "EXT_mmvec";
38921}
38922def V6_vsubuhw_alt : HInst<
38923(outs HvxWR:$Vdd32),
38924(ins HvxVR:$Vu32, HvxVR:$Vv32),
38925"$Vdd32 = vsubuh($Vu32,$Vv32)",
38926PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38927let hasNewValue = 1;
38928let opNewValue = 0;
38929let isCVI = 1;
38930let isPseudo = 1;
38931let isCodeGenOnly = 1;
38932let DecoderNamespace = "EXT_mmvec";
38933}
38934def V6_vsubuwsat : HInst<
38935(outs HvxVR:$Vd32),
38936(ins HvxVR:$Vu32, HvxVR:$Vv32),
38937"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
38938tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
38939let Inst{7-5} = 0b100;
38940let Inst{13-13} = 0b0;
38941let Inst{31-21} = 0b00011111110;
38942let hasNewValue = 1;
38943let opNewValue = 0;
38944let isCVI = 1;
38945let DecoderNamespace = "EXT_mmvec";
38946}
38947def V6_vsubuwsat_alt : HInst<
38948(outs HvxVR:$Vd32),
38949(ins HvxVR:$Vu32, HvxVR:$Vv32),
38950"$Vd32 = vsubuw($Vu32,$Vv32):sat",
38951PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38952let hasNewValue = 1;
38953let opNewValue = 0;
38954let isCVI = 1;
38955let isPseudo = 1;
38956let isCodeGenOnly = 1;
38957let DecoderNamespace = "EXT_mmvec";
38958}
38959def V6_vsubuwsat_dv : HInst<
38960(outs HvxWR:$Vdd32),
38961(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38962"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
38963tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
38964let Inst{7-5} = 0b011;
38965let Inst{13-13} = 0b0;
38966let Inst{31-21} = 0b00011110101;
38967let hasNewValue = 1;
38968let opNewValue = 0;
38969let isCVI = 1;
38970let DecoderNamespace = "EXT_mmvec";
38971}
38972def V6_vsubuwsat_dv_alt : HInst<
38973(outs HvxWR:$Vdd32),
38974(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38975"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
38976PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38977let hasNewValue = 1;
38978let opNewValue = 0;
38979let isCVI = 1;
38980let isPseudo = 1;
38981let isCodeGenOnly = 1;
38982let DecoderNamespace = "EXT_mmvec";
38983}
38984def V6_vsubw : HInst<
38985(outs HvxVR:$Vd32),
38986(ins HvxVR:$Vu32, HvxVR:$Vv32),
38987"$Vd32.w = vsub($Vu32.w,$Vv32.w)",
38988tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38989let Inst{7-5} = 0b111;
38990let Inst{13-13} = 0b0;
38991let Inst{31-21} = 0b00011100010;
38992let hasNewValue = 1;
38993let opNewValue = 0;
38994let isCVI = 1;
38995let DecoderNamespace = "EXT_mmvec";
38996}
38997def V6_vsubw_alt : HInst<
38998(outs HvxVR:$Vd32),
38999(ins HvxVR:$Vu32, HvxVR:$Vv32),
39000"$Vd32 = vsubw($Vu32,$Vv32)",
39001PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39002let hasNewValue = 1;
39003let opNewValue = 0;
39004let isCVI = 1;
39005let isPseudo = 1;
39006let isCodeGenOnly = 1;
39007let DecoderNamespace = "EXT_mmvec";
39008}
39009def V6_vsubw_dv : HInst<
39010(outs HvxWR:$Vdd32),
39011(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39012"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
39013tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39014let Inst{7-5} = 0b101;
39015let Inst{13-13} = 0b0;
39016let Inst{31-21} = 0b00011100100;
39017let hasNewValue = 1;
39018let opNewValue = 0;
39019let isCVI = 1;
39020let DecoderNamespace = "EXT_mmvec";
39021}
39022def V6_vsubw_dv_alt : HInst<
39023(outs HvxWR:$Vdd32),
39024(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39025"$Vdd32 = vsubw($Vuu32,$Vvv32)",
39026PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39027let hasNewValue = 1;
39028let opNewValue = 0;
39029let isCVI = 1;
39030let isPseudo = 1;
39031let isCodeGenOnly = 1;
39032let DecoderNamespace = "EXT_mmvec";
39033}
39034def V6_vsubwnq : HInst<
39035(outs HvxVR:$Vx32),
39036(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39037"if (!$Qv4) $Vx32.w -= $Vu32.w",
39038tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39039let Inst{7-5} = 0b011;
39040let Inst{13-13} = 0b1;
39041let Inst{21-16} = 0b000010;
39042let Inst{31-24} = 0b00011110;
39043let hasNewValue = 1;
39044let opNewValue = 0;
39045let isCVI = 1;
39046let DecoderNamespace = "EXT_mmvec";
39047let Constraints = "$Vx32 = $Vx32in";
39048}
39049def V6_vsubwnq_alt : HInst<
39050(outs HvxVR:$Vx32),
39051(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39052"if (!$Qv4.w) $Vx32.w -= $Vu32.w",
39053PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39054let hasNewValue = 1;
39055let opNewValue = 0;
39056let isCVI = 1;
39057let isPseudo = 1;
39058let isCodeGenOnly = 1;
39059let DecoderNamespace = "EXT_mmvec";
39060let Constraints = "$Vx32 = $Vx32in";
39061}
39062def V6_vsubwq : HInst<
39063(outs HvxVR:$Vx32),
39064(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39065"if ($Qv4) $Vx32.w -= $Vu32.w",
39066tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39067let Inst{7-5} = 0b000;
39068let Inst{13-13} = 0b1;
39069let Inst{21-16} = 0b000010;
39070let Inst{31-24} = 0b00011110;
39071let hasNewValue = 1;
39072let opNewValue = 0;
39073let isCVI = 1;
39074let DecoderNamespace = "EXT_mmvec";
39075let Constraints = "$Vx32 = $Vx32in";
39076}
39077def V6_vsubwq_alt : HInst<
39078(outs HvxVR:$Vx32),
39079(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39080"if ($Qv4.w) $Vx32.w -= $Vu32.w",
39081PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39082let hasNewValue = 1;
39083let opNewValue = 0;
39084let isCVI = 1;
39085let isPseudo = 1;
39086let isCodeGenOnly = 1;
39087let DecoderNamespace = "EXT_mmvec";
39088let Constraints = "$Vx32 = $Vx32in";
39089}
39090def V6_vsubwsat : HInst<
39091(outs HvxVR:$Vd32),
39092(ins HvxVR:$Vu32, HvxVR:$Vv32),
39093"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
39094tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39095let Inst{7-5} = 0b011;
39096let Inst{13-13} = 0b0;
39097let Inst{31-21} = 0b00011100011;
39098let hasNewValue = 1;
39099let opNewValue = 0;
39100let isCVI = 1;
39101let DecoderNamespace = "EXT_mmvec";
39102}
39103def V6_vsubwsat_alt : HInst<
39104(outs HvxVR:$Vd32),
39105(ins HvxVR:$Vu32, HvxVR:$Vv32),
39106"$Vd32 = vsubw($Vu32,$Vv32):sat",
39107PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39108let hasNewValue = 1;
39109let opNewValue = 0;
39110let isCVI = 1;
39111let isPseudo = 1;
39112let isCodeGenOnly = 1;
39113let DecoderNamespace = "EXT_mmvec";
39114}
39115def V6_vsubwsat_dv : HInst<
39116(outs HvxWR:$Vdd32),
39117(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39118"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
39119tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39120let Inst{7-5} = 0b001;
39121let Inst{13-13} = 0b0;
39122let Inst{31-21} = 0b00011100101;
39123let hasNewValue = 1;
39124let opNewValue = 0;
39125let isCVI = 1;
39126let DecoderNamespace = "EXT_mmvec";
39127}
39128def V6_vsubwsat_dv_alt : HInst<
39129(outs HvxWR:$Vdd32),
39130(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39131"$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
39132PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39133let hasNewValue = 1;
39134let opNewValue = 0;
39135let isCVI = 1;
39136let isPseudo = 1;
39137let isCodeGenOnly = 1;
39138let DecoderNamespace = "EXT_mmvec";
39139}
39140def V6_vswap : HInst<
39141(outs HvxWR:$Vdd32),
39142(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
39143"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
39144tc_71646d06, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
39145let Inst{7-7} = 0b0;
39146let Inst{13-13} = 0b1;
39147let Inst{31-21} = 0b00011110101;
39148let hasNewValue = 1;
39149let opNewValue = 0;
39150let isCVI = 1;
39151let DecoderNamespace = "EXT_mmvec";
39152}
39153def V6_vtmpyb : HInst<
39154(outs HvxWR:$Vdd32),
39155(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39156"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
39157tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39158let Inst{7-5} = 0b000;
39159let Inst{13-13} = 0b0;
39160let Inst{31-21} = 0b00011001000;
39161let hasNewValue = 1;
39162let opNewValue = 0;
39163let isCVI = 1;
39164let DecoderNamespace = "EXT_mmvec";
39165}
39166def V6_vtmpyb_acc : HInst<
39167(outs HvxWR:$Vxx32),
39168(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39169"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
39170tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39171let Inst{7-5} = 0b000;
39172let Inst{13-13} = 0b1;
39173let Inst{31-21} = 0b00011001000;
39174let hasNewValue = 1;
39175let opNewValue = 0;
39176let isAccumulator = 1;
39177let isCVI = 1;
39178let DecoderNamespace = "EXT_mmvec";
39179let Constraints = "$Vxx32 = $Vxx32in";
39180}
39181def V6_vtmpyb_acc_alt : HInst<
39182(outs HvxWR:$Vxx32),
39183(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39184"$Vxx32 += vtmpyb($Vuu32,$Rt32)",
39185PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39186let hasNewValue = 1;
39187let opNewValue = 0;
39188let isAccumulator = 1;
39189let isCVI = 1;
39190let isPseudo = 1;
39191let isCodeGenOnly = 1;
39192let DecoderNamespace = "EXT_mmvec";
39193let Constraints = "$Vxx32 = $Vxx32in";
39194}
39195def V6_vtmpyb_alt : HInst<
39196(outs HvxWR:$Vdd32),
39197(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39198"$Vdd32 = vtmpyb($Vuu32,$Rt32)",
39199PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39200let hasNewValue = 1;
39201let opNewValue = 0;
39202let isCVI = 1;
39203let isPseudo = 1;
39204let isCodeGenOnly = 1;
39205let DecoderNamespace = "EXT_mmvec";
39206}
39207def V6_vtmpybus : HInst<
39208(outs HvxWR:$Vdd32),
39209(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39210"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
39211tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39212let Inst{7-5} = 0b001;
39213let Inst{13-13} = 0b0;
39214let Inst{31-21} = 0b00011001000;
39215let hasNewValue = 1;
39216let opNewValue = 0;
39217let isCVI = 1;
39218let DecoderNamespace = "EXT_mmvec";
39219}
39220def V6_vtmpybus_acc : HInst<
39221(outs HvxWR:$Vxx32),
39222(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39223"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
39224tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39225let Inst{7-5} = 0b001;
39226let Inst{13-13} = 0b1;
39227let Inst{31-21} = 0b00011001000;
39228let hasNewValue = 1;
39229let opNewValue = 0;
39230let isAccumulator = 1;
39231let isCVI = 1;
39232let DecoderNamespace = "EXT_mmvec";
39233let Constraints = "$Vxx32 = $Vxx32in";
39234}
39235def V6_vtmpybus_acc_alt : HInst<
39236(outs HvxWR:$Vxx32),
39237(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39238"$Vxx32 += vtmpybus($Vuu32,$Rt32)",
39239PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39240let hasNewValue = 1;
39241let opNewValue = 0;
39242let isAccumulator = 1;
39243let isCVI = 1;
39244let isPseudo = 1;
39245let isCodeGenOnly = 1;
39246let DecoderNamespace = "EXT_mmvec";
39247let Constraints = "$Vxx32 = $Vxx32in";
39248}
39249def V6_vtmpybus_alt : HInst<
39250(outs HvxWR:$Vdd32),
39251(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39252"$Vdd32 = vtmpybus($Vuu32,$Rt32)",
39253PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39254let hasNewValue = 1;
39255let opNewValue = 0;
39256let isCVI = 1;
39257let isPseudo = 1;
39258let isCodeGenOnly = 1;
39259let DecoderNamespace = "EXT_mmvec";
39260}
39261def V6_vtmpyhb : HInst<
39262(outs HvxWR:$Vdd32),
39263(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39264"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
39265tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39266let Inst{7-5} = 0b100;
39267let Inst{13-13} = 0b0;
39268let Inst{31-21} = 0b00011001101;
39269let hasNewValue = 1;
39270let opNewValue = 0;
39271let isCVI = 1;
39272let DecoderNamespace = "EXT_mmvec";
39273}
39274def V6_vtmpyhb_acc : HInst<
39275(outs HvxWR:$Vxx32),
39276(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39277"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
39278tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39279let Inst{7-5} = 0b010;
39280let Inst{13-13} = 0b1;
39281let Inst{31-21} = 0b00011001000;
39282let hasNewValue = 1;
39283let opNewValue = 0;
39284let isAccumulator = 1;
39285let isCVI = 1;
39286let DecoderNamespace = "EXT_mmvec";
39287let Constraints = "$Vxx32 = $Vxx32in";
39288}
39289def V6_vtmpyhb_acc_alt : HInst<
39290(outs HvxWR:$Vxx32),
39291(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39292"$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
39293PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39294let hasNewValue = 1;
39295let opNewValue = 0;
39296let isAccumulator = 1;
39297let isCVI = 1;
39298let isPseudo = 1;
39299let isCodeGenOnly = 1;
39300let DecoderNamespace = "EXT_mmvec";
39301let Constraints = "$Vxx32 = $Vxx32in";
39302}
39303def V6_vtmpyhb_alt : HInst<
39304(outs HvxWR:$Vdd32),
39305(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39306"$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
39307PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39308let hasNewValue = 1;
39309let opNewValue = 0;
39310let isCVI = 1;
39311let isPseudo = 1;
39312let isCodeGenOnly = 1;
39313let DecoderNamespace = "EXT_mmvec";
39314}
39315def V6_vtran2x2_map : HInst<
39316(outs HvxVR:$Vy32, HvxVR:$Vx32),
39317(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
39318"vtrans2x2($Vy32,$Vx32,$Rt32)",
39319PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39320let hasNewValue = 1;
39321let opNewValue = 0;
39322let hasNewValue2 = 1;
39323let opNewValue2 = 1;
39324let isCVI = 1;
39325let isPseudo = 1;
39326let isCodeGenOnly = 1;
39327let DecoderNamespace = "EXT_mmvec";
39328let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
39329}
39330def V6_vunpackb : HInst<
39331(outs HvxWR:$Vdd32),
39332(ins HvxVR:$Vu32),
39333"$Vdd32.h = vunpack($Vu32.b)",
39334tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39335let Inst{7-5} = 0b010;
39336let Inst{13-13} = 0b0;
39337let Inst{31-16} = 0b0001111000000001;
39338let hasNewValue = 1;
39339let opNewValue = 0;
39340let isCVI = 1;
39341let DecoderNamespace = "EXT_mmvec";
39342}
39343def V6_vunpackb_alt : HInst<
39344(outs HvxWR:$Vdd32),
39345(ins HvxVR:$Vu32),
39346"$Vdd32 = vunpackb($Vu32)",
39347PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39348let hasNewValue = 1;
39349let opNewValue = 0;
39350let isCVI = 1;
39351let isPseudo = 1;
39352let isCodeGenOnly = 1;
39353let DecoderNamespace = "EXT_mmvec";
39354}
39355def V6_vunpackh : HInst<
39356(outs HvxWR:$Vdd32),
39357(ins HvxVR:$Vu32),
39358"$Vdd32.w = vunpack($Vu32.h)",
39359tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39360let Inst{7-5} = 0b011;
39361let Inst{13-13} = 0b0;
39362let Inst{31-16} = 0b0001111000000001;
39363let hasNewValue = 1;
39364let opNewValue = 0;
39365let isCVI = 1;
39366let DecoderNamespace = "EXT_mmvec";
39367}
39368def V6_vunpackh_alt : HInst<
39369(outs HvxWR:$Vdd32),
39370(ins HvxVR:$Vu32),
39371"$Vdd32 = vunpackh($Vu32)",
39372PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39373let hasNewValue = 1;
39374let opNewValue = 0;
39375let isCVI = 1;
39376let isPseudo = 1;
39377let isCodeGenOnly = 1;
39378let DecoderNamespace = "EXT_mmvec";
39379}
39380def V6_vunpackob : HInst<
39381(outs HvxWR:$Vxx32),
39382(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
39383"$Vxx32.h |= vunpacko($Vu32.b)",
39384tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
39385let Inst{7-5} = 0b000;
39386let Inst{13-13} = 0b1;
39387let Inst{31-16} = 0b0001111000000000;
39388let hasNewValue = 1;
39389let opNewValue = 0;
39390let isAccumulator = 1;
39391let isCVI = 1;
39392let DecoderNamespace = "EXT_mmvec";
39393let Constraints = "$Vxx32 = $Vxx32in";
39394}
39395def V6_vunpackob_alt : HInst<
39396(outs HvxWR:$Vxx32),
39397(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
39398"$Vxx32 |= vunpackob($Vu32)",
39399PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39400let hasNewValue = 1;
39401let opNewValue = 0;
39402let isAccumulator = 1;
39403let isCVI = 1;
39404let isPseudo = 1;
39405let DecoderNamespace = "EXT_mmvec";
39406let Constraints = "$Vxx32 = $Vxx32in";
39407}
39408def V6_vunpackoh : HInst<
39409(outs HvxWR:$Vxx32),
39410(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
39411"$Vxx32.w |= vunpacko($Vu32.h)",
39412tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
39413let Inst{7-5} = 0b001;
39414let Inst{13-13} = 0b1;
39415let Inst{31-16} = 0b0001111000000000;
39416let hasNewValue = 1;
39417let opNewValue = 0;
39418let isAccumulator = 1;
39419let isCVI = 1;
39420let DecoderNamespace = "EXT_mmvec";
39421let Constraints = "$Vxx32 = $Vxx32in";
39422}
39423def V6_vunpackoh_alt : HInst<
39424(outs HvxWR:$Vxx32),
39425(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
39426"$Vxx32 |= vunpackoh($Vu32)",
39427PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39428let hasNewValue = 1;
39429let opNewValue = 0;
39430let isAccumulator = 1;
39431let isCVI = 1;
39432let isPseudo = 1;
39433let isCodeGenOnly = 1;
39434let DecoderNamespace = "EXT_mmvec";
39435let Constraints = "$Vxx32 = $Vxx32in";
39436}
39437def V6_vunpackub : HInst<
39438(outs HvxWR:$Vdd32),
39439(ins HvxVR:$Vu32),
39440"$Vdd32.uh = vunpack($Vu32.ub)",
39441tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39442let Inst{7-5} = 0b000;
39443let Inst{13-13} = 0b0;
39444let Inst{31-16} = 0b0001111000000001;
39445let hasNewValue = 1;
39446let opNewValue = 0;
39447let isCVI = 1;
39448let DecoderNamespace = "EXT_mmvec";
39449}
39450def V6_vunpackub_alt : HInst<
39451(outs HvxWR:$Vdd32),
39452(ins HvxVR:$Vu32),
39453"$Vdd32 = vunpackub($Vu32)",
39454PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39455let hasNewValue = 1;
39456let opNewValue = 0;
39457let isCVI = 1;
39458let isPseudo = 1;
39459let isCodeGenOnly = 1;
39460let DecoderNamespace = "EXT_mmvec";
39461}
39462def V6_vunpackuh : HInst<
39463(outs HvxWR:$Vdd32),
39464(ins HvxVR:$Vu32),
39465"$Vdd32.uw = vunpack($Vu32.uh)",
39466tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39467let Inst{7-5} = 0b001;
39468let Inst{13-13} = 0b0;
39469let Inst{31-16} = 0b0001111000000001;
39470let hasNewValue = 1;
39471let opNewValue = 0;
39472let isCVI = 1;
39473let DecoderNamespace = "EXT_mmvec";
39474}
39475def V6_vunpackuh_alt : HInst<
39476(outs HvxWR:$Vdd32),
39477(ins HvxVR:$Vu32),
39478"$Vdd32 = vunpackuh($Vu32)",
39479PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39480let hasNewValue = 1;
39481let opNewValue = 0;
39482let isCVI = 1;
39483let isPseudo = 1;
39484let isCodeGenOnly = 1;
39485let DecoderNamespace = "EXT_mmvec";
39486}
39487def V6_vwhist128 : HInst<
39488(outs),
39489(ins),
39490"vwhist128",
39491tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
39492let Inst{13-0} = 0b10010010000000;
39493let Inst{31-16} = 0b0001111000000000;
39494let isCVI = 1;
39495let DecoderNamespace = "EXT_mmvec";
39496}
39497def V6_vwhist128m : HInst<
39498(outs),
39499(ins u1_0Imm:$Ii),
39500"vwhist128(#$Ii)",
39501tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
39502let Inst{7-0} = 0b10000000;
39503let Inst{13-9} = 0b10011;
39504let Inst{31-16} = 0b0001111000000000;
39505let isCVI = 1;
39506let DecoderNamespace = "EXT_mmvec";
39507}
39508def V6_vwhist128q : HInst<
39509(outs),
39510(ins HvxQR:$Qv4),
39511"vwhist128($Qv4)",
39512tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
39513let Inst{13-0} = 0b10010010000000;
39514let Inst{21-16} = 0b000010;
39515let Inst{31-24} = 0b00011110;
39516let isCVI = 1;
39517let DecoderNamespace = "EXT_mmvec";
39518}
39519def V6_vwhist128qm : HInst<
39520(outs),
39521(ins HvxQR:$Qv4, u1_0Imm:$Ii),
39522"vwhist128($Qv4,#$Ii)",
39523tc_767c4e9d, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
39524let Inst{7-0} = 0b10000000;
39525let Inst{13-9} = 0b10011;
39526let Inst{21-16} = 0b000010;
39527let Inst{31-24} = 0b00011110;
39528let isCVI = 1;
39529let DecoderNamespace = "EXT_mmvec";
39530}
39531def V6_vwhist256 : HInst<
39532(outs),
39533(ins),
39534"vwhist256",
39535tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
39536let Inst{13-0} = 0b10001010000000;
39537let Inst{31-16} = 0b0001111000000000;
39538let isCVI = 1;
39539let DecoderNamespace = "EXT_mmvec";
39540}
39541def V6_vwhist256_sat : HInst<
39542(outs),
39543(ins),
39544"vwhist256:sat",
39545tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
39546let Inst{13-0} = 0b10001110000000;
39547let Inst{31-16} = 0b0001111000000000;
39548let isCVI = 1;
39549let DecoderNamespace = "EXT_mmvec";
39550}
39551def V6_vwhist256q : HInst<
39552(outs),
39553(ins HvxQR:$Qv4),
39554"vwhist256($Qv4)",
39555tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
39556let Inst{13-0} = 0b10001010000000;
39557let Inst{21-16} = 0b000010;
39558let Inst{31-24} = 0b00011110;
39559let isCVI = 1;
39560let DecoderNamespace = "EXT_mmvec";
39561}
39562def V6_vwhist256q_sat : HInst<
39563(outs),
39564(ins HvxQR:$Qv4),
39565"vwhist256($Qv4):sat",
39566tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
39567let Inst{13-0} = 0b10001110000000;
39568let Inst{21-16} = 0b000010;
39569let Inst{31-24} = 0b00011110;
39570let isCVI = 1;
39571let DecoderNamespace = "EXT_mmvec";
39572}
39573def V6_vxor : HInst<
39574(outs HvxVR:$Vd32),
39575(ins HvxVR:$Vu32, HvxVR:$Vv32),
39576"$Vd32 = vxor($Vu32,$Vv32)",
39577tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39578let Inst{7-5} = 0b111;
39579let Inst{13-13} = 0b0;
39580let Inst{31-21} = 0b00011100001;
39581let hasNewValue = 1;
39582let opNewValue = 0;
39583let isCVI = 1;
39584let DecoderNamespace = "EXT_mmvec";
39585}
39586def V6_vzb : HInst<
39587(outs HvxWR:$Vdd32),
39588(ins HvxVR:$Vu32),
39589"$Vdd32.uh = vzxt($Vu32.ub)",
39590tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
39591let Inst{7-5} = 0b001;
39592let Inst{13-13} = 0b0;
39593let Inst{31-16} = 0b0001111000000010;
39594let hasNewValue = 1;
39595let opNewValue = 0;
39596let isCVI = 1;
39597let DecoderNamespace = "EXT_mmvec";
39598}
39599def V6_vzb_alt : HInst<
39600(outs HvxWR:$Vdd32),
39601(ins HvxVR:$Vu32),
39602"$Vdd32 = vzxtb($Vu32)",
39603PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39604let hasNewValue = 1;
39605let opNewValue = 0;
39606let isCVI = 1;
39607let isPseudo = 1;
39608let isCodeGenOnly = 1;
39609let DecoderNamespace = "EXT_mmvec";
39610}
39611def V6_vzh : HInst<
39612(outs HvxWR:$Vdd32),
39613(ins HvxVR:$Vu32),
39614"$Vdd32.uw = vzxt($Vu32.uh)",
39615tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
39616let Inst{7-5} = 0b010;
39617let Inst{13-13} = 0b0;
39618let Inst{31-16} = 0b0001111000000010;
39619let hasNewValue = 1;
39620let opNewValue = 0;
39621let isCVI = 1;
39622let DecoderNamespace = "EXT_mmvec";
39623}
39624def V6_vzh_alt : HInst<
39625(outs HvxWR:$Vdd32),
39626(ins HvxVR:$Vu32),
39627"$Vdd32 = vzxth($Vu32)",
39628PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39629let hasNewValue = 1;
39630let opNewValue = 0;
39631let isCVI = 1;
39632let isPseudo = 1;
39633let isCodeGenOnly = 1;
39634let DecoderNamespace = "EXT_mmvec";
39635}
39636def V6_zLd_ai : HInst<
39637(outs),
39638(ins IntRegs:$Rt32, s4_0Imm:$Ii),
39639"z = vmem($Rt32+#$Ii)",
39640tc_e699ae41, TypeCVI_ZW>, Enc_ff3442, Requires<[UseHVXV66,UseZReg]>, PostInc_BaseImm {
39641let Inst{7-0} = 0b00000000;
39642let Inst{12-11} = 0b00;
39643let Inst{31-21} = 0b00101100000;
39644let addrMode = BaseImmOffset;
39645let isCVI = 1;
39646let mayLoad = 1;
39647let isRestrictNoSlot1Store = 1;
39648let CextOpcode = "V6_zLd";
39649let DecoderNamespace = "EXT_mmvec";
39650}
39651def V6_zLd_pi : HInst<
39652(outs IntRegs:$Rx32),
39653(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
39654"z = vmem($Rx32++#$Ii)",
39655tc_a0dbea28, TypeCVI_ZW>, Enc_6c9ee0, Requires<[UseHVXV66,UseZReg]>, PostInc_BaseImm {
39656let Inst{7-0} = 0b00000000;
39657let Inst{13-11} = 0b000;
39658let Inst{31-21} = 0b00101101000;
39659let addrMode = PostInc;
39660let isCVI = 1;
39661let mayLoad = 1;
39662let isRestrictNoSlot1Store = 1;
39663let CextOpcode = "V6_zLd";
39664let DecoderNamespace = "EXT_mmvec";
39665let Constraints = "$Rx32 = $Rx32in";
39666}
39667def V6_zLd_ppu : HInst<
39668(outs IntRegs:$Rx32),
39669(ins IntRegs:$Rx32in, ModRegs:$Mu2),
39670"z = vmem($Rx32++$Mu2)",
39671tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> {
39672let Inst{12-0} = 0b0000000000001;
39673let Inst{31-21} = 0b00101101000;
39674let addrMode = PostInc;
39675let isCVI = 1;
39676let mayLoad = 1;
39677let isRestrictNoSlot1Store = 1;
39678let DecoderNamespace = "EXT_mmvec";
39679let Constraints = "$Rx32 = $Rx32in";
39680}
39681def V6_zLd_pred_ai : HInst<
39682(outs),
39683(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
39684"if ($Pv4) z = vmem($Rt32+#$Ii)",
39685tc_dd5b0695, TypeCVI_ZW>, Enc_ef601b, Requires<[UseHVXV66,UseZReg]> {
39686let Inst{7-0} = 0b00000000;
39687let Inst{31-21} = 0b00101100100;
39688let isPredicated = 1;
39689let addrMode = BaseImmOffset;
39690let isCVI = 1;
39691let mayLoad = 1;
39692let isRestrictNoSlot1Store = 1;
39693let DecoderNamespace = "EXT_mmvec";
39694}
39695def V6_zLd_pred_pi : HInst<
39696(outs IntRegs:$Rx32),
39697(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
39698"if ($Pv4) z = vmem($Rx32++#$Ii)",
39699tc_3ad719fb, TypeCVI_ZW>, Enc_6baed4, Requires<[UseHVXV66,UseZReg]> {
39700let Inst{7-0} = 0b00000000;
39701let Inst{13-13} = 0b0;
39702let Inst{31-21} = 0b00101101100;
39703let isPredicated = 1;
39704let addrMode = PostInc;
39705let isCVI = 1;
39706let mayLoad = 1;
39707let isRestrictNoSlot1Store = 1;
39708let DecoderNamespace = "EXT_mmvec";
39709let Constraints = "$Rx32 = $Rx32in";
39710}
39711def V6_zLd_pred_ppu : HInst<
39712(outs IntRegs:$Rx32),
39713(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
39714"if ($Pv4) z = vmem($Rx32++$Mu2)",
39715tc_3ad719fb, TypeCVI_ZW>, Enc_691712, Requires<[UseHVXV66,UseZReg]> {
39716let Inst{10-0} = 0b00000000001;
39717let Inst{31-21} = 0b00101101100;
39718let isPredicated = 1;
39719let addrMode = PostInc;
39720let isCVI = 1;
39721let mayLoad = 1;
39722let isRestrictNoSlot1Store = 1;
39723let DecoderNamespace = "EXT_mmvec";
39724let Constraints = "$Rx32 = $Rx32in";
39725}
39726def V6_zextract : HInst<
39727(outs HvxVR:$Vd32),
39728(ins IntRegs:$Rt32),
39729"$Vd32 = zextract($Rt32)",
39730tc_5bf8afbb, TypeCVI_VP>, Enc_a5ed8a, Requires<[UseHVXV66,UseZReg]> {
39731let Inst{13-5} = 0b000001001;
39732let Inst{31-21} = 0b00011001101;
39733let hasNewValue = 1;
39734let opNewValue = 0;
39735let isCVI = 1;
39736let DecoderNamespace = "EXT_mmvec";
39737}
39738def V6_zld0 : HInst<
39739(outs),
39740(ins IntRegs:$Rt32),
39741"z = vmem($Rt32)",
39742PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
39743let isCVI = 1;
39744let isPseudo = 1;
39745let isCodeGenOnly = 1;
39746let DecoderNamespace = "EXT_mmvec";
39747}
39748def V6_zldp0 : HInst<
39749(outs),
39750(ins PredRegs:$Pv4, IntRegs:$Rt32),
39751"if ($Pv4) z = vmem($Rt32)",
39752PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
39753let isCVI = 1;
39754let isPseudo = 1;
39755let isCodeGenOnly = 1;
39756let DecoderNamespace = "EXT_mmvec";
39757}
39758def Y2_barrier : HInst<
39759(outs),
39760(ins),
39761"barrier",
39762tc_77f94a5e, TypeST>, Enc_e3b0c4 {
39763let Inst{13-0} = 0b00000000000000;
39764let Inst{31-16} = 0b1010100000000000;
39765let isSoloAX = 1;
39766let hasSideEffects = 1;
39767}
39768def Y2_break : HInst<
39769(outs),
39770(ins),
39771"brkpt",
39772tc_55255f2b, TypeCR>, Enc_e3b0c4 {
39773let Inst{13-0} = 0b00000000000000;
39774let Inst{31-16} = 0b0110110000100000;
39775let isSolo = 1;
39776}
39777def Y2_crswap_old : HInst<
39778(outs IntRegs:$Rx32),
39779(ins IntRegs:$Rx32in),
39780"crswap($Rx32,sgp)",
39781PSEUDO, TypeMAPPING> {
39782let hasNewValue = 1;
39783let opNewValue = 0;
39784let isPseudo = 1;
39785let isCodeGenOnly = 1;
39786let Constraints = "$Rx32 = $Rx32in";
39787}
39788def Y2_dccleana : HInst<
39789(outs),
39790(ins IntRegs:$Rs32),
39791"dccleana($Rs32)",
39792tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
39793let Inst{13-0} = 0b00000000000000;
39794let Inst{31-21} = 0b10100000000;
39795let isRestrictSlot1AOK = 1;
39796let hasSideEffects = 1;
39797}
39798def Y2_dccleaninva : HInst<
39799(outs),
39800(ins IntRegs:$Rs32),
39801"dccleaninva($Rs32)",
39802tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
39803let Inst{13-0} = 0b00000000000000;
39804let Inst{31-21} = 0b10100000010;
39805let isRestrictSlot1AOK = 1;
39806let hasSideEffects = 1;
39807}
39808def Y2_dcfetch : HInst<
39809(outs),
39810(ins IntRegs:$Rs32),
39811"dcfetch($Rs32)",
39812tc_d45ba9cd, TypeMAPPING> {
39813let hasSideEffects = 1;
39814let isPseudo = 1;
39815let isCodeGenOnly = 1;
39816}
39817def Y2_dcfetchbo : HInst<
39818(outs),
39819(ins IntRegs:$Rs32, u11_3Imm:$Ii),
39820"dcfetch($Rs32+#$Ii)",
39821tc_2237d952, TypeLD>, Enc_2d829e {
39822let Inst{13-11} = 0b000;
39823let Inst{31-21} = 0b10010100000;
39824let addrMode = BaseImmOffset;
39825let isRestrictNoSlot1Store = 1;
39826let hasSideEffects = 1;
39827}
39828def Y2_dcinva : HInst<
39829(outs),
39830(ins IntRegs:$Rs32),
39831"dcinva($Rs32)",
39832tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
39833let Inst{13-0} = 0b00000000000000;
39834let Inst{31-21} = 0b10100000001;
39835let isRestrictSlot1AOK = 1;
39836let hasSideEffects = 1;
39837}
39838def Y2_dczeroa : HInst<
39839(outs),
39840(ins IntRegs:$Rs32),
39841"dczeroa($Rs32)",
39842tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
39843let Inst{13-0} = 0b00000000000000;
39844let Inst{31-21} = 0b10100000110;
39845let isRestrictSlot1AOK = 1;
39846let mayStore = 1;
39847let hasSideEffects = 1;
39848}
39849def Y2_icinva : HInst<
39850(outs),
39851(ins IntRegs:$Rs32),
39852"icinva($Rs32)",
39853tc_0ba0d5da, TypeJ>, Enc_ecbcc8 {
39854let Inst{13-0} = 0b00000000000000;
39855let Inst{31-21} = 0b01010110110;
39856let isSolo = 1;
39857}
39858def Y2_isync : HInst<
39859(outs),
39860(ins),
39861"isync",
39862tc_9b34f5e0, TypeJ>, Enc_e3b0c4 {
39863let Inst{13-0} = 0b00000000000010;
39864let Inst{31-16} = 0b0101011111000000;
39865let isSolo = 1;
39866}
39867def Y2_k1lock_map : HInst<
39868(outs),
39869(ins),
39870"k1lock",
39871PSEUDO, TypeMAPPING>, Requires<[HasV65]> {
39872let isPseudo = 1;
39873let isCodeGenOnly = 1;
39874}
39875def Y2_k1unlock_map : HInst<
39876(outs),
39877(ins),
39878"k1unlock",
39879PSEUDO, TypeMAPPING>, Requires<[HasV65]> {
39880let isPseudo = 1;
39881let isCodeGenOnly = 1;
39882}
39883def Y2_syncht : HInst<
39884(outs),
39885(ins),
39886"syncht",
39887tc_77f94a5e, TypeST>, Enc_e3b0c4 {
39888let Inst{13-0} = 0b00000000000000;
39889let Inst{31-16} = 0b1010100001000000;
39890let isSolo = 1;
39891}
39892def Y2_tfrscrr : HInst<
39893(outs IntRegs:$Rd32),
39894(ins SysRegs:$Ss128),
39895"$Rd32 = $Ss128",
39896tc_fae9dfa5, TypeCR>, Enc_7d1542 {
39897let Inst{13-5} = 0b000000000;
39898let Inst{31-23} = 0b011011101;
39899let hasNewValue = 1;
39900let opNewValue = 0;
39901}
39902def Y2_tfrsrcr : HInst<
39903(outs SysRegs:$Sd128),
39904(ins IntRegs:$Rs32),
39905"$Sd128 = $Rs32",
39906tc_6ae3426b, TypeCR>, Enc_8f7633 {
39907let Inst{13-7} = 0b0000000;
39908let Inst{31-21} = 0b01100111000;
39909let hasNewValue = 1;
39910let opNewValue = 0;
39911}
39912def Y2_wait : HInst<
39913(outs),
39914(ins IntRegs:$Rs32),
39915"wait($Rs32)",
39916tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> {
39917let Inst{13-0} = 0b00000000000000;
39918let Inst{31-21} = 0b01100100010;
39919let isSolo = 1;
39920}
39921def Y4_l2fetch : HInst<
39922(outs),
39923(ins IntRegs:$Rs32, IntRegs:$Rt32),
39924"l2fetch($Rs32,$Rt32)",
39925tc_a3070909, TypeST>, Enc_ca3887 {
39926let Inst{7-0} = 0b00000000;
39927let Inst{13-13} = 0b0;
39928let Inst{31-21} = 0b10100110000;
39929let isSoloAX = 1;
39930let hasSideEffects = 1;
39931let mayStore = 1;
39932}
39933def Y4_tfrscpp : HInst<
39934(outs DoubleRegs:$Rdd32),
39935(ins SysRegs64:$Sss128),
39936"$Rdd32 = $Sss128",
39937tc_fae9dfa5, TypeCR>, Enc_e32517 {
39938let Inst{13-5} = 0b000000000;
39939let Inst{31-23} = 0b011011110;
39940}
39941def Y4_tfrspcp : HInst<
39942(outs SysRegs64:$Sdd128),
39943(ins DoubleRegs:$Rss32),
39944"$Sdd128 = $Rss32",
39945tc_6ae3426b, TypeCR>, Enc_a705fc {
39946let Inst{13-7} = 0b0000000;
39947let Inst{31-21} = 0b01101101000;
39948let hasNewValue = 1;
39949let opNewValue = 0;
39950}
39951def Y4_trace : HInst<
39952(outs),
39953(ins IntRegs:$Rs32),
39954"trace($Rs32)",
39955tc_d7718fbe, TypeCR>, Enc_ecbcc8 {
39956let Inst{13-0} = 0b00000000000000;
39957let Inst{31-21} = 0b01100010010;
39958let isSoloAX = 1;
39959}
39960def Y5_l2fetch : HInst<
39961(outs),
39962(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
39963"l2fetch($Rs32,$Rtt32)",
39964tc_a3070909, TypeST>, Enc_e6abcf {
39965let Inst{7-0} = 0b00000000;
39966let Inst{13-13} = 0b0;
39967let Inst{31-21} = 0b10100110100;
39968let isSoloAX = 1;
39969let hasSideEffects = 1;
39970let mayStore = 1;
39971}
39972def Y6_diag : HInst<
39973(outs),
39974(ins IntRegs:$Rs32),
39975"diag($Rs32)",
39976tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV67]> {
39977let Inst{13-0} = 0b00000000100000;
39978let Inst{31-21} = 0b01100010010;
39979}
39980def Y6_diag0 : HInst<
39981(outs),
39982(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
39983"diag0($Rss32,$Rtt32)",
39984tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
39985let Inst{7-0} = 0b01000000;
39986let Inst{13-13} = 0b0;
39987let Inst{31-21} = 0b01100010010;
39988}
39989def Y6_diag1 : HInst<
39990(outs),
39991(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
39992"diag1($Rss32,$Rtt32)",
39993tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
39994let Inst{7-0} = 0b01100000;
39995let Inst{13-13} = 0b0;
39996let Inst{31-21} = 0b01100010010;
39997}
39998def Y6_dmlink : HInst<
39999(outs),
40000(ins IntRegs:$Rs32, IntRegs:$Rt32),
40001"dmlink($Rs32,$Rt32)",
40002tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
40003let Inst{7-0} = 0b01000000;
40004let Inst{13-13} = 0b0;
40005let Inst{31-21} = 0b10100110000;
40006let hasSideEffects = 1;
40007let isSolo = 1;
40008let mayStore = 1;
40009}
40010def Y6_dmpause : HInst<
40011(outs IntRegs:$Rd32),
40012(ins),
40013"$Rd32 = dmpause",
40014tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
40015let Inst{13-5} = 0b000000011;
40016let Inst{31-16} = 0b1010100000000000;
40017let hasNewValue = 1;
40018let opNewValue = 0;
40019let hasSideEffects = 1;
40020let isSolo = 1;
40021}
40022def Y6_dmpoll : HInst<
40023(outs IntRegs:$Rd32),
40024(ins),
40025"$Rd32 = dmpoll",
40026tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
40027let Inst{13-5} = 0b000000010;
40028let Inst{31-16} = 0b1010100000000000;
40029let hasNewValue = 1;
40030let opNewValue = 0;
40031let hasSideEffects = 1;
40032let isSolo = 1;
40033}
40034def Y6_dmresume : HInst<
40035(outs),
40036(ins IntRegs:$Rs32),
40037"dmresume($Rs32)",
40038tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
40039let Inst{13-0} = 0b00000010000000;
40040let Inst{31-21} = 0b10100110000;
40041let hasSideEffects = 1;
40042let isSolo = 1;
40043}
40044def Y6_dmstart : HInst<
40045(outs),
40046(ins IntRegs:$Rs32),
40047"dmstart($Rs32)",
40048tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
40049let Inst{13-0} = 0b00000000100000;
40050let Inst{31-21} = 0b10100110000;
40051let hasSideEffects = 1;
40052let isSolo = 1;
40053}
40054def Y6_dmwait : HInst<
40055(outs IntRegs:$Rd32),
40056(ins),
40057"$Rd32 = dmwait",
40058tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
40059let Inst{13-5} = 0b000000001;
40060let Inst{31-16} = 0b1010100000000000;
40061let hasNewValue = 1;
40062let opNewValue = 0;
40063let hasSideEffects = 1;
40064let isSolo = 1;
40065}
40066def dep_A2_addsat : HInst<
40067(outs IntRegs:$Rd32),
40068(ins IntRegs:$Rs32, IntRegs:$Rt32),
40069"$Rd32 = add($Rs32,$Rt32):sat:deprecated",
40070tc_8a825db2, TypeALU64>, Enc_5ab2be {
40071let Inst{7-5} = 0b000;
40072let Inst{13-13} = 0b0;
40073let Inst{31-21} = 0b11010101100;
40074let hasNewValue = 1;
40075let opNewValue = 0;
40076let prefersSlot3 = 1;
40077let Defs = [USR_OVF];
40078}
40079def dep_A2_subsat : HInst<
40080(outs IntRegs:$Rd32),
40081(ins IntRegs:$Rt32, IntRegs:$Rs32),
40082"$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
40083tc_8a825db2, TypeALU64>, Enc_bd6011 {
40084let Inst{7-5} = 0b100;
40085let Inst{13-13} = 0b0;
40086let Inst{31-21} = 0b11010101100;
40087let hasNewValue = 1;
40088let opNewValue = 0;
40089let prefersSlot3 = 1;
40090let Defs = [USR_OVF];
40091}
40092def dep_S2_packhl : HInst<
40093(outs DoubleRegs:$Rdd32),
40094(ins IntRegs:$Rs32, IntRegs:$Rt32),
40095"$Rdd32 = packhl($Rs32,$Rt32):deprecated",
40096tc_5da50c4b, TypeALU64>, Enc_be32a5 {
40097let Inst{7-5} = 0b000;
40098let Inst{13-13} = 0b0;
40099let Inst{31-21} = 0b11010100000;
40100}
40101def dup_A2_add : HInst<
40102(outs IntRegs:$Rd32),
40103(ins IntRegs:$Rs32, IntRegs:$Rt32),
40104"$Rd32 = add($Rs32,$Rt32)",
40105tc_388f9897, TypeALU32_3op>, Requires<[HasV69]> {
40106let hasNewValue = 1;
40107let opNewValue = 0;
40108let AsmVariantName = "NonParsable";
40109let isPseudo = 1;
40110}
40111def dup_A2_addi : HInst<
40112(outs IntRegs:$Rd32),
40113(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40114"$Rd32 = add($Rs32,#$Ii)",
40115tc_388f9897, TypeALU32_ADDI>, Requires<[HasV69]> {
40116let hasNewValue = 1;
40117let opNewValue = 0;
40118let AsmVariantName = "NonParsable";
40119let isPseudo = 1;
40120let isExtendable = 1;
40121let opExtendable = 2;
40122let isExtentSigned = 1;
40123let opExtentBits = 16;
40124let opExtentAlign = 0;
40125}
40126def dup_A2_andir : HInst<
40127(outs IntRegs:$Rd32),
40128(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40129"$Rd32 = and($Rs32,#$Ii)",
40130tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40131let hasNewValue = 1;
40132let opNewValue = 0;
40133let AsmVariantName = "NonParsable";
40134let isPseudo = 1;
40135let isExtendable = 1;
40136let opExtendable = 2;
40137let isExtentSigned = 1;
40138let opExtentBits = 10;
40139let opExtentAlign = 0;
40140}
40141def dup_A2_combineii : HInst<
40142(outs DoubleRegs:$Rdd32),
40143(ins s32_0Imm:$Ii, s8_0Imm:$II),
40144"$Rdd32 = combine(#$Ii,#$II)",
40145tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40146let AsmVariantName = "NonParsable";
40147let isPseudo = 1;
40148let isExtendable = 1;
40149let opExtendable = 1;
40150let isExtentSigned = 1;
40151let opExtentBits = 8;
40152let opExtentAlign = 0;
40153}
40154def dup_A2_sxtb : HInst<
40155(outs IntRegs:$Rd32),
40156(ins IntRegs:$Rs32),
40157"$Rd32 = sxtb($Rs32)",
40158tc_9124c04f, TypeALU32_2op>, Requires<[HasV69]> {
40159let hasNewValue = 1;
40160let opNewValue = 0;
40161let AsmVariantName = "NonParsable";
40162let isPseudo = 1;
40163}
40164def dup_A2_sxth : HInst<
40165(outs IntRegs:$Rd32),
40166(ins IntRegs:$Rs32),
40167"$Rd32 = sxth($Rs32)",
40168tc_9124c04f, TypeALU32_2op>, Requires<[HasV69]> {
40169let hasNewValue = 1;
40170let opNewValue = 0;
40171let AsmVariantName = "NonParsable";
40172let isPseudo = 1;
40173}
40174def dup_A2_tfr : HInst<
40175(outs IntRegs:$Rd32),
40176(ins IntRegs:$Rs32),
40177"$Rd32 = $Rs32",
40178tc_9124c04f, TypeALU32_2op>, Requires<[HasV69]> {
40179let hasNewValue = 1;
40180let opNewValue = 0;
40181let AsmVariantName = "NonParsable";
40182let isPseudo = 1;
40183}
40184def dup_A2_tfrsi : HInst<
40185(outs IntRegs:$Rd32),
40186(ins s32_0Imm:$Ii),
40187"$Rd32 = #$Ii",
40188tc_9124c04f, TypeALU32_2op>, Requires<[HasV69]> {
40189let hasNewValue = 1;
40190let opNewValue = 0;
40191let AsmVariantName = "NonParsable";
40192let isPseudo = 1;
40193let isExtendable = 1;
40194let opExtendable = 1;
40195let isExtentSigned = 1;
40196let opExtentBits = 16;
40197let opExtentAlign = 0;
40198}
40199def dup_A2_zxtb : HInst<
40200(outs IntRegs:$Rd32),
40201(ins IntRegs:$Rs32),
40202"$Rd32 = zxtb($Rs32)",
40203PSEUDO, TypeMAPPING>, Requires<[HasV69]> {
40204let hasNewValue = 1;
40205let opNewValue = 0;
40206let AsmVariantName = "NonParsable";
40207let isPseudo = 1;
40208}
40209def dup_A2_zxth : HInst<
40210(outs IntRegs:$Rd32),
40211(ins IntRegs:$Rs32),
40212"$Rd32 = zxth($Rs32)",
40213tc_9124c04f, TypeALU32_2op>, Requires<[HasV69]> {
40214let hasNewValue = 1;
40215let opNewValue = 0;
40216let AsmVariantName = "NonParsable";
40217let isPseudo = 1;
40218}
40219def dup_A4_combineii : HInst<
40220(outs DoubleRegs:$Rdd32),
40221(ins s8_0Imm:$Ii, u32_0Imm:$II),
40222"$Rdd32 = combine(#$Ii,#$II)",
40223tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40224let AsmVariantName = "NonParsable";
40225let isPseudo = 1;
40226let isExtendable = 1;
40227let opExtendable = 2;
40228let isExtentSigned = 0;
40229let opExtentBits = 6;
40230let opExtentAlign = 0;
40231}
40232def dup_A4_combineir : HInst<
40233(outs DoubleRegs:$Rdd32),
40234(ins s32_0Imm:$Ii, IntRegs:$Rs32),
40235"$Rdd32 = combine(#$Ii,$Rs32)",
40236tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40237let AsmVariantName = "NonParsable";
40238let isPseudo = 1;
40239let isExtendable = 1;
40240let opExtendable = 1;
40241let isExtentSigned = 1;
40242let opExtentBits = 8;
40243let opExtentAlign = 0;
40244}
40245def dup_A4_combineri : HInst<
40246(outs DoubleRegs:$Rdd32),
40247(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40248"$Rdd32 = combine($Rs32,#$Ii)",
40249tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40250let AsmVariantName = "NonParsable";
40251let isPseudo = 1;
40252let isExtendable = 1;
40253let opExtendable = 2;
40254let isExtentSigned = 1;
40255let opExtentBits = 8;
40256let opExtentAlign = 0;
40257}
40258def dup_C2_cmoveif : HInst<
40259(outs IntRegs:$Rd32),
40260(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40261"if (!$Pu4) $Rd32 = #$Ii",
40262tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40263let isPredicated = 1;
40264let isPredicatedFalse = 1;
40265let hasNewValue = 1;
40266let opNewValue = 0;
40267let AsmVariantName = "NonParsable";
40268let isPseudo = 1;
40269let isExtendable = 1;
40270let opExtendable = 2;
40271let isExtentSigned = 1;
40272let opExtentBits = 12;
40273let opExtentAlign = 0;
40274}
40275def dup_C2_cmoveit : HInst<
40276(outs IntRegs:$Rd32),
40277(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40278"if ($Pu4) $Rd32 = #$Ii",
40279tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40280let isPredicated = 1;
40281let hasNewValue = 1;
40282let opNewValue = 0;
40283let AsmVariantName = "NonParsable";
40284let isPseudo = 1;
40285let isExtendable = 1;
40286let opExtendable = 2;
40287let isExtentSigned = 1;
40288let opExtentBits = 12;
40289let opExtentAlign = 0;
40290}
40291def dup_C2_cmovenewif : HInst<
40292(outs IntRegs:$Rd32),
40293(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40294"if (!$Pu4.new) $Rd32 = #$Ii",
40295tc_4ac61d92, TypeALU32_2op>, Requires<[HasV69]> {
40296let isPredicated = 1;
40297let isPredicatedFalse = 1;
40298let hasNewValue = 1;
40299let opNewValue = 0;
40300let AsmVariantName = "NonParsable";
40301let isPredicatedNew = 1;
40302let isPseudo = 1;
40303let isExtendable = 1;
40304let opExtendable = 2;
40305let isExtentSigned = 1;
40306let opExtentBits = 12;
40307let opExtentAlign = 0;
40308}
40309def dup_C2_cmovenewit : HInst<
40310(outs IntRegs:$Rd32),
40311(ins PredRegs:$Pu4, s32_0Imm:$Ii),
40312"if ($Pu4.new) $Rd32 = #$Ii",
40313tc_4ac61d92, TypeALU32_2op>, Requires<[HasV69]> {
40314let isPredicated = 1;
40315let hasNewValue = 1;
40316let opNewValue = 0;
40317let AsmVariantName = "NonParsable";
40318let isPredicatedNew = 1;
40319let isPseudo = 1;
40320let isExtendable = 1;
40321let opExtendable = 2;
40322let isExtentSigned = 1;
40323let opExtentBits = 12;
40324let opExtentAlign = 0;
40325}
40326def dup_C2_cmpeqi : HInst<
40327(outs PredRegs:$Pd4),
40328(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40329"$Pd4 = cmp.eq($Rs32,#$Ii)",
40330tc_388f9897, TypeALU32_2op>, Requires<[HasV69]> {
40331let AsmVariantName = "NonParsable";
40332let isPseudo = 1;
40333let isExtendable = 1;
40334let opExtendable = 2;
40335let isExtentSigned = 1;
40336let opExtentBits = 10;
40337let opExtentAlign = 0;
40338}
40339def dup_L2_deallocframe : HInst<
40340(outs DoubleRegs:$Rdd32),
40341(ins IntRegs:$Rs32),
40342"$Rdd32 = deallocframe($Rs32):raw",
40343tc_aee6250c, TypeLD>, Requires<[HasV69]> {
40344let accessSize = DoubleWordAccess;
40345let AsmVariantName = "NonParsable";
40346let mayLoad = 1;
40347let Uses = [FRAMEKEY];
40348let Defs = [R29];
40349let isPseudo = 1;
40350}
40351def dup_L2_loadrb_io : HInst<
40352(outs IntRegs:$Rd32),
40353(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40354"$Rd32 = memb($Rs32+#$Ii)",
40355tc_eed07714, TypeLD>, Requires<[HasV69]> {
40356let hasNewValue = 1;
40357let opNewValue = 0;
40358let addrMode = BaseImmOffset;
40359let accessSize = ByteAccess;
40360let AsmVariantName = "NonParsable";
40361let mayLoad = 1;
40362let isPseudo = 1;
40363let isExtendable = 1;
40364let opExtendable = 2;
40365let isExtentSigned = 1;
40366let opExtentBits = 11;
40367let opExtentAlign = 0;
40368}
40369def dup_L2_loadrd_io : HInst<
40370(outs DoubleRegs:$Rdd32),
40371(ins IntRegs:$Rs32, s29_3Imm:$Ii),
40372"$Rdd32 = memd($Rs32+#$Ii)",
40373tc_eed07714, TypeLD>, Requires<[HasV69]> {
40374let addrMode = BaseImmOffset;
40375let accessSize = DoubleWordAccess;
40376let AsmVariantName = "NonParsable";
40377let mayLoad = 1;
40378let isPseudo = 1;
40379let isExtendable = 1;
40380let opExtendable = 2;
40381let isExtentSigned = 1;
40382let opExtentBits = 14;
40383let opExtentAlign = 3;
40384}
40385def dup_L2_loadrh_io : HInst<
40386(outs IntRegs:$Rd32),
40387(ins IntRegs:$Rs32, s31_1Imm:$Ii),
40388"$Rd32 = memh($Rs32+#$Ii)",
40389tc_eed07714, TypeLD>, Requires<[HasV69]> {
40390let hasNewValue = 1;
40391let opNewValue = 0;
40392let addrMode = BaseImmOffset;
40393let accessSize = HalfWordAccess;
40394let AsmVariantName = "NonParsable";
40395let mayLoad = 1;
40396let isPseudo = 1;
40397let isExtendable = 1;
40398let opExtendable = 2;
40399let isExtentSigned = 1;
40400let opExtentBits = 12;
40401let opExtentAlign = 1;
40402}
40403def dup_L2_loadri_io : HInst<
40404(outs IntRegs:$Rd32),
40405(ins IntRegs:$Rs32, s30_2Imm:$Ii),
40406"$Rd32 = memw($Rs32+#$Ii)",
40407tc_eed07714, TypeLD>, Requires<[HasV69]> {
40408let hasNewValue = 1;
40409let opNewValue = 0;
40410let addrMode = BaseImmOffset;
40411let accessSize = WordAccess;
40412let AsmVariantName = "NonParsable";
40413let mayLoad = 1;
40414let isPseudo = 1;
40415let isExtendable = 1;
40416let opExtendable = 2;
40417let isExtentSigned = 1;
40418let opExtentBits = 13;
40419let opExtentAlign = 2;
40420}
40421def dup_L2_loadrub_io : HInst<
40422(outs IntRegs:$Rd32),
40423(ins IntRegs:$Rs32, s32_0Imm:$Ii),
40424"$Rd32 = memub($Rs32+#$Ii)",
40425tc_eed07714, TypeLD>, Requires<[HasV69]> {
40426let hasNewValue = 1;
40427let opNewValue = 0;
40428let addrMode = BaseImmOffset;
40429let accessSize = ByteAccess;
40430let AsmVariantName = "NonParsable";
40431let mayLoad = 1;
40432let isPseudo = 1;
40433let isExtendable = 1;
40434let opExtendable = 2;
40435let isExtentSigned = 1;
40436let opExtentBits = 11;
40437let opExtentAlign = 0;
40438}
40439def dup_L2_loadruh_io : HInst<
40440(outs IntRegs:$Rd32),
40441(ins IntRegs:$Rs32, s31_1Imm:$Ii),
40442"$Rd32 = memuh($Rs32+#$Ii)",
40443tc_eed07714, TypeLD>, Requires<[HasV69]> {
40444let hasNewValue = 1;
40445let opNewValue = 0;
40446let addrMode = BaseImmOffset;
40447let accessSize = HalfWordAccess;
40448let AsmVariantName = "NonParsable";
40449let mayLoad = 1;
40450let isPseudo = 1;
40451let isExtendable = 1;
40452let opExtendable = 2;
40453let isExtentSigned = 1;
40454let opExtentBits = 12;
40455let opExtentAlign = 1;
40456}
40457def dup_S2_allocframe : HInst<
40458(outs IntRegs:$Rx32),
40459(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
40460"allocframe($Rx32,#$Ii):raw",
40461tc_74a42bda, TypeST>, Requires<[HasV69]> {
40462let hasNewValue = 1;
40463let opNewValue = 0;
40464let addrMode = BaseImmOffset;
40465let accessSize = DoubleWordAccess;
40466let AsmVariantName = "NonParsable";
40467let mayStore = 1;
40468let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
40469let Defs = [R30];
40470let isPseudo = 1;
40471let Constraints = "$Rx32 = $Rx32in";
40472}
40473def dup_S2_storerb_io : HInst<
40474(outs),
40475(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
40476"memb($Rs32+#$Ii) = $Rt32",
40477tc_a9edeffa, TypeST>, Requires<[HasV69]> {
40478let addrMode = BaseImmOffset;
40479let accessSize = ByteAccess;
40480let AsmVariantName = "NonParsable";
40481let mayStore = 1;
40482let isPseudo = 1;
40483let isExtendable = 1;
40484let opExtendable = 1;
40485let isExtentSigned = 1;
40486let opExtentBits = 11;
40487let opExtentAlign = 0;
40488}
40489def dup_S2_storerd_io : HInst<
40490(outs),
40491(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
40492"memd($Rs32+#$Ii) = $Rtt32",
40493tc_a9edeffa, TypeST>, Requires<[HasV69]> {
40494let addrMode = BaseImmOffset;
40495let accessSize = DoubleWordAccess;
40496let AsmVariantName = "NonParsable";
40497let mayStore = 1;
40498let isPseudo = 1;
40499let isExtendable = 1;
40500let opExtendable = 1;
40501let isExtentSigned = 1;
40502let opExtentBits = 14;
40503let opExtentAlign = 3;
40504}
40505def dup_S2_storerh_io : HInst<
40506(outs),
40507(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
40508"memh($Rs32+#$Ii) = $Rt32",
40509tc_a9edeffa, TypeST>, Requires<[HasV69]> {
40510let addrMode = BaseImmOffset;
40511let accessSize = HalfWordAccess;
40512let AsmVariantName = "NonParsable";
40513let mayStore = 1;
40514let isPseudo = 1;
40515let isExtendable = 1;
40516let opExtendable = 1;
40517let isExtentSigned = 1;
40518let opExtentBits = 12;
40519let opExtentAlign = 1;
40520}
40521def dup_S2_storeri_io : HInst<
40522(outs),
40523(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
40524"memw($Rs32+#$Ii) = $Rt32",
40525tc_a9edeffa, TypeST>, Requires<[HasV69]> {
40526let addrMode = BaseImmOffset;
40527let accessSize = WordAccess;
40528let AsmVariantName = "NonParsable";
40529let mayStore = 1;
40530let isPseudo = 1;
40531let isExtendable = 1;
40532let opExtendable = 1;
40533let isExtentSigned = 1;
40534let opExtentBits = 13;
40535let opExtentAlign = 2;
40536}
40537def dup_S4_storeirb_io : HInst<
40538(outs),
40539(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
40540"memb($Rs32+#$Ii) = #$II",
40541tc_838c4d7a, TypeV4LDST>, Requires<[HasV69]> {
40542let addrMode = BaseImmOffset;
40543let accessSize = ByteAccess;
40544let AsmVariantName = "NonParsable";
40545let mayStore = 1;
40546let isPseudo = 1;
40547let isExtendable = 1;
40548let opExtendable = 2;
40549let isExtentSigned = 1;
40550let opExtentBits = 8;
40551let opExtentAlign = 0;
40552}
40553def dup_S4_storeiri_io : HInst<
40554(outs),
40555(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
40556"memw($Rs32+#$Ii) = #$II",
40557tc_838c4d7a, TypeV4LDST>, Requires<[HasV69]> {
40558let addrMode = BaseImmOffset;
40559let accessSize = WordAccess;
40560let AsmVariantName = "NonParsable";
40561let mayStore = 1;
40562let isPseudo = 1;
40563let isExtendable = 1;
40564let opExtendable = 2;
40565let isExtentSigned = 1;
40566let opExtentBits = 8;
40567let opExtentAlign = 0;
40568}
40569