xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11def A2_abs : HInst<
12(outs IntRegs:$Rd32),
13(ins IntRegs:$Rs32),
14"$Rd32 = abs($Rs32)",
15tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
16let Inst{13-5} = 0b000000100;
17let Inst{31-21} = 0b10001100100;
18let hasNewValue = 1;
19let opNewValue = 0;
20let prefersSlot3 = 1;
21}
22def A2_absp : HInst<
23(outs DoubleRegs:$Rdd32),
24(ins DoubleRegs:$Rss32),
25"$Rdd32 = abs($Rss32)",
26tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
27let Inst{13-5} = 0b000000110;
28let Inst{31-21} = 0b10000000100;
29let prefersSlot3 = 1;
30}
31def A2_abssat : HInst<
32(outs IntRegs:$Rd32),
33(ins IntRegs:$Rs32),
34"$Rd32 = abs($Rs32):sat",
35tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
36let Inst{13-5} = 0b000000101;
37let Inst{31-21} = 0b10001100100;
38let hasNewValue = 1;
39let opNewValue = 0;
40let prefersSlot3 = 1;
41let Defs = [USR_OVF];
42}
43def A2_add : HInst<
44(outs IntRegs:$Rd32),
45(ins IntRegs:$Rs32, IntRegs:$Rt32),
46"$Rd32 = add($Rs32,$Rt32)",
47tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
48let Inst{7-5} = 0b000;
49let Inst{13-13} = 0b0;
50let Inst{31-21} = 0b11110011000;
51let hasNewValue = 1;
52let opNewValue = 0;
53let BaseOpcode = "A2_add";
54let CextOpcode = "A2_add";
55let InputType = "reg";
56let isCommutable = 1;
57let isPredicable = 1;
58}
59def A2_addh_h16_hh : HInst<
60(outs IntRegs:$Rd32),
61(ins IntRegs:$Rt32, IntRegs:$Rs32),
62"$Rd32 = add($Rt32.h,$Rs32.h):<<16",
63tc_01d44cb2, TypeALU64>, Enc_bd6011 {
64let Inst{7-5} = 0b011;
65let Inst{13-13} = 0b0;
66let Inst{31-21} = 0b11010101010;
67let hasNewValue = 1;
68let opNewValue = 0;
69let prefersSlot3 = 1;
70}
71def A2_addh_h16_hl : HInst<
72(outs IntRegs:$Rd32),
73(ins IntRegs:$Rt32, IntRegs:$Rs32),
74"$Rd32 = add($Rt32.h,$Rs32.l):<<16",
75tc_01d44cb2, TypeALU64>, Enc_bd6011 {
76let Inst{7-5} = 0b010;
77let Inst{13-13} = 0b0;
78let Inst{31-21} = 0b11010101010;
79let hasNewValue = 1;
80let opNewValue = 0;
81let prefersSlot3 = 1;
82}
83def A2_addh_h16_lh : HInst<
84(outs IntRegs:$Rd32),
85(ins IntRegs:$Rt32, IntRegs:$Rs32),
86"$Rd32 = add($Rt32.l,$Rs32.h):<<16",
87tc_01d44cb2, TypeALU64>, Enc_bd6011 {
88let Inst{7-5} = 0b001;
89let Inst{13-13} = 0b0;
90let Inst{31-21} = 0b11010101010;
91let hasNewValue = 1;
92let opNewValue = 0;
93let prefersSlot3 = 1;
94}
95def A2_addh_h16_ll : HInst<
96(outs IntRegs:$Rd32),
97(ins IntRegs:$Rt32, IntRegs:$Rs32),
98"$Rd32 = add($Rt32.l,$Rs32.l):<<16",
99tc_01d44cb2, TypeALU64>, Enc_bd6011 {
100let Inst{7-5} = 0b000;
101let Inst{13-13} = 0b0;
102let Inst{31-21} = 0b11010101010;
103let hasNewValue = 1;
104let opNewValue = 0;
105let prefersSlot3 = 1;
106}
107def A2_addh_h16_sat_hh : HInst<
108(outs IntRegs:$Rd32),
109(ins IntRegs:$Rt32, IntRegs:$Rs32),
110"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
111tc_8a825db2, TypeALU64>, Enc_bd6011 {
112let Inst{7-5} = 0b111;
113let Inst{13-13} = 0b0;
114let Inst{31-21} = 0b11010101010;
115let hasNewValue = 1;
116let opNewValue = 0;
117let prefersSlot3 = 1;
118let Defs = [USR_OVF];
119}
120def A2_addh_h16_sat_hl : HInst<
121(outs IntRegs:$Rd32),
122(ins IntRegs:$Rt32, IntRegs:$Rs32),
123"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
124tc_8a825db2, TypeALU64>, Enc_bd6011 {
125let Inst{7-5} = 0b110;
126let Inst{13-13} = 0b0;
127let Inst{31-21} = 0b11010101010;
128let hasNewValue = 1;
129let opNewValue = 0;
130let prefersSlot3 = 1;
131let Defs = [USR_OVF];
132}
133def A2_addh_h16_sat_lh : HInst<
134(outs IntRegs:$Rd32),
135(ins IntRegs:$Rt32, IntRegs:$Rs32),
136"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
137tc_8a825db2, TypeALU64>, Enc_bd6011 {
138let Inst{7-5} = 0b101;
139let Inst{13-13} = 0b0;
140let Inst{31-21} = 0b11010101010;
141let hasNewValue = 1;
142let opNewValue = 0;
143let prefersSlot3 = 1;
144let Defs = [USR_OVF];
145}
146def A2_addh_h16_sat_ll : HInst<
147(outs IntRegs:$Rd32),
148(ins IntRegs:$Rt32, IntRegs:$Rs32),
149"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
150tc_8a825db2, TypeALU64>, Enc_bd6011 {
151let Inst{7-5} = 0b100;
152let Inst{13-13} = 0b0;
153let Inst{31-21} = 0b11010101010;
154let hasNewValue = 1;
155let opNewValue = 0;
156let prefersSlot3 = 1;
157let Defs = [USR_OVF];
158}
159def A2_addh_l16_hl : HInst<
160(outs IntRegs:$Rd32),
161(ins IntRegs:$Rt32, IntRegs:$Rs32),
162"$Rd32 = add($Rt32.l,$Rs32.h)",
163tc_f34c1c21, TypeALU64>, Enc_bd6011 {
164let Inst{7-5} = 0b010;
165let Inst{13-13} = 0b0;
166let Inst{31-21} = 0b11010101000;
167let hasNewValue = 1;
168let opNewValue = 0;
169let prefersSlot3 = 1;
170}
171def A2_addh_l16_ll : HInst<
172(outs IntRegs:$Rd32),
173(ins IntRegs:$Rt32, IntRegs:$Rs32),
174"$Rd32 = add($Rt32.l,$Rs32.l)",
175tc_f34c1c21, TypeALU64>, Enc_bd6011 {
176let Inst{7-5} = 0b000;
177let Inst{13-13} = 0b0;
178let Inst{31-21} = 0b11010101000;
179let hasNewValue = 1;
180let opNewValue = 0;
181let prefersSlot3 = 1;
182}
183def A2_addh_l16_sat_hl : HInst<
184(outs IntRegs:$Rd32),
185(ins IntRegs:$Rt32, IntRegs:$Rs32),
186"$Rd32 = add($Rt32.l,$Rs32.h):sat",
187tc_8a825db2, TypeALU64>, Enc_bd6011 {
188let Inst{7-5} = 0b110;
189let Inst{13-13} = 0b0;
190let Inst{31-21} = 0b11010101000;
191let hasNewValue = 1;
192let opNewValue = 0;
193let prefersSlot3 = 1;
194let Defs = [USR_OVF];
195}
196def A2_addh_l16_sat_ll : HInst<
197(outs IntRegs:$Rd32),
198(ins IntRegs:$Rt32, IntRegs:$Rs32),
199"$Rd32 = add($Rt32.l,$Rs32.l):sat",
200tc_8a825db2, TypeALU64>, Enc_bd6011 {
201let Inst{7-5} = 0b100;
202let Inst{13-13} = 0b0;
203let Inst{31-21} = 0b11010101000;
204let hasNewValue = 1;
205let opNewValue = 0;
206let prefersSlot3 = 1;
207let Defs = [USR_OVF];
208}
209def A2_addi : HInst<
210(outs IntRegs:$Rd32),
211(ins IntRegs:$Rs32, s32_0Imm:$Ii),
212"$Rd32 = add($Rs32,#$Ii)",
213tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
214let Inst{31-28} = 0b1011;
215let hasNewValue = 1;
216let opNewValue = 0;
217let BaseOpcode = "A2_addi";
218let CextOpcode = "A2_add";
219let InputType = "imm";
220let isPredicable = 1;
221let isAdd = 1;
222let isExtendable = 1;
223let opExtendable = 2;
224let isExtentSigned = 1;
225let opExtentBits = 16;
226let opExtentAlign = 0;
227}
228def A2_addp : HInst<
229(outs DoubleRegs:$Rdd32),
230(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
231"$Rdd32 = add($Rss32,$Rtt32)",
232tc_5da50c4b, TypeALU64>, Enc_a56825 {
233let Inst{7-5} = 0b111;
234let Inst{13-13} = 0b0;
235let Inst{31-21} = 0b11010011000;
236let isCommutable = 1;
237let isAdd = 1;
238}
239def A2_addpsat : HInst<
240(outs DoubleRegs:$Rdd32),
241(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
242"$Rdd32 = add($Rss32,$Rtt32):sat",
243tc_8a825db2, TypeALU64>, Enc_a56825 {
244let Inst{7-5} = 0b101;
245let Inst{13-13} = 0b0;
246let Inst{31-21} = 0b11010011011;
247let prefersSlot3 = 1;
248let Defs = [USR_OVF];
249let isCommutable = 1;
250}
251def A2_addsat : HInst<
252(outs IntRegs:$Rd32),
253(ins IntRegs:$Rs32, IntRegs:$Rt32),
254"$Rd32 = add($Rs32,$Rt32):sat",
255tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
256let Inst{7-5} = 0b000;
257let Inst{13-13} = 0b0;
258let Inst{31-21} = 0b11110110010;
259let hasNewValue = 1;
260let opNewValue = 0;
261let prefersSlot3 = 1;
262let Defs = [USR_OVF];
263let InputType = "reg";
264let isCommutable = 1;
265}
266def A2_addsp : HInst<
267(outs DoubleRegs:$Rdd32),
268(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
269"$Rdd32 = add($Rs32,$Rtt32)",
270tc_01d44cb2, TypeALU64> {
271let isPseudo = 1;
272}
273def A2_addsph : HInst<
274(outs DoubleRegs:$Rdd32),
275(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
276"$Rdd32 = add($Rss32,$Rtt32):raw:hi",
277tc_01d44cb2, TypeALU64>, Enc_a56825 {
278let Inst{7-5} = 0b111;
279let Inst{13-13} = 0b0;
280let Inst{31-21} = 0b11010011011;
281let prefersSlot3 = 1;
282}
283def A2_addspl : HInst<
284(outs DoubleRegs:$Rdd32),
285(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
286"$Rdd32 = add($Rss32,$Rtt32):raw:lo",
287tc_01d44cb2, TypeALU64>, Enc_a56825 {
288let Inst{7-5} = 0b110;
289let Inst{13-13} = 0b0;
290let Inst{31-21} = 0b11010011011;
291let prefersSlot3 = 1;
292}
293def A2_and : HInst<
294(outs IntRegs:$Rd32),
295(ins IntRegs:$Rs32, IntRegs:$Rt32),
296"$Rd32 = and($Rs32,$Rt32)",
297tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
298let Inst{7-5} = 0b000;
299let Inst{13-13} = 0b0;
300let Inst{31-21} = 0b11110001000;
301let hasNewValue = 1;
302let opNewValue = 0;
303let BaseOpcode = "A2_and";
304let CextOpcode = "A2_and";
305let InputType = "reg";
306let isCommutable = 1;
307let isPredicable = 1;
308}
309def A2_andir : HInst<
310(outs IntRegs:$Rd32),
311(ins IntRegs:$Rs32, s32_0Imm:$Ii),
312"$Rd32 = and($Rs32,#$Ii)",
313tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
314let Inst{31-22} = 0b0111011000;
315let hasNewValue = 1;
316let opNewValue = 0;
317let CextOpcode = "A2_and";
318let InputType = "imm";
319let isExtendable = 1;
320let opExtendable = 2;
321let isExtentSigned = 1;
322let opExtentBits = 10;
323let opExtentAlign = 0;
324}
325def A2_andp : HInst<
326(outs DoubleRegs:$Rdd32),
327(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
328"$Rdd32 = and($Rss32,$Rtt32)",
329tc_5da50c4b, TypeALU64>, Enc_a56825 {
330let Inst{7-5} = 0b000;
331let Inst{13-13} = 0b0;
332let Inst{31-21} = 0b11010011111;
333let isCommutable = 1;
334}
335def A2_aslh : HInst<
336(outs IntRegs:$Rd32),
337(ins IntRegs:$Rs32),
338"$Rd32 = aslh($Rs32)",
339tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
340let Inst{13-5} = 0b000000000;
341let Inst{31-21} = 0b01110000000;
342let hasNewValue = 1;
343let opNewValue = 0;
344let BaseOpcode = "A2_aslh";
345let isPredicable = 1;
346}
347def A2_asrh : HInst<
348(outs IntRegs:$Rd32),
349(ins IntRegs:$Rs32),
350"$Rd32 = asrh($Rs32)",
351tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
352let Inst{13-5} = 0b000000000;
353let Inst{31-21} = 0b01110000001;
354let hasNewValue = 1;
355let opNewValue = 0;
356let BaseOpcode = "A2_asrh";
357let isPredicable = 1;
358}
359def A2_combine_hh : HInst<
360(outs IntRegs:$Rd32),
361(ins IntRegs:$Rt32, IntRegs:$Rs32),
362"$Rd32 = combine($Rt32.h,$Rs32.h)",
363tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
364let Inst{7-5} = 0b000;
365let Inst{13-13} = 0b0;
366let Inst{31-21} = 0b11110011100;
367let hasNewValue = 1;
368let opNewValue = 0;
369let InputType = "reg";
370}
371def A2_combine_hl : HInst<
372(outs IntRegs:$Rd32),
373(ins IntRegs:$Rt32, IntRegs:$Rs32),
374"$Rd32 = combine($Rt32.h,$Rs32.l)",
375tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
376let Inst{7-5} = 0b000;
377let Inst{13-13} = 0b0;
378let Inst{31-21} = 0b11110011101;
379let hasNewValue = 1;
380let opNewValue = 0;
381let InputType = "reg";
382}
383def A2_combine_lh : HInst<
384(outs IntRegs:$Rd32),
385(ins IntRegs:$Rt32, IntRegs:$Rs32),
386"$Rd32 = combine($Rt32.l,$Rs32.h)",
387tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
388let Inst{7-5} = 0b000;
389let Inst{13-13} = 0b0;
390let Inst{31-21} = 0b11110011110;
391let hasNewValue = 1;
392let opNewValue = 0;
393let InputType = "reg";
394}
395def A2_combine_ll : HInst<
396(outs IntRegs:$Rd32),
397(ins IntRegs:$Rt32, IntRegs:$Rs32),
398"$Rd32 = combine($Rt32.l,$Rs32.l)",
399tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
400let Inst{7-5} = 0b000;
401let Inst{13-13} = 0b0;
402let Inst{31-21} = 0b11110011111;
403let hasNewValue = 1;
404let opNewValue = 0;
405let InputType = "reg";
406}
407def A2_combineii : HInst<
408(outs DoubleRegs:$Rdd32),
409(ins s32_0Imm:$Ii, s8_0Imm:$II),
410"$Rdd32 = combine(#$Ii,#$II)",
411tc_713b66bf, TypeALU32_2op>, Enc_18c338 {
412let Inst{31-23} = 0b011111000;
413let isReMaterializable = 1;
414let isAsCheapAsAMove = 1;
415let isMoveImm = 1;
416let isExtendable = 1;
417let opExtendable = 1;
418let isExtentSigned = 1;
419let opExtentBits = 8;
420let opExtentAlign = 0;
421}
422def A2_combinew : HInst<
423(outs DoubleRegs:$Rdd32),
424(ins IntRegs:$Rs32, IntRegs:$Rt32),
425"$Rdd32 = combine($Rs32,$Rt32)",
426tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel {
427let Inst{7-5} = 0b000;
428let Inst{13-13} = 0b0;
429let Inst{31-21} = 0b11110101000;
430let BaseOpcode = "A2_combinew";
431let InputType = "reg";
432let isPredicable = 1;
433}
434def A2_max : HInst<
435(outs IntRegs:$Rd32),
436(ins IntRegs:$Rs32, IntRegs:$Rt32),
437"$Rd32 = max($Rs32,$Rt32)",
438tc_8a825db2, TypeALU64>, Enc_5ab2be {
439let Inst{7-5} = 0b000;
440let Inst{13-13} = 0b0;
441let Inst{31-21} = 0b11010101110;
442let hasNewValue = 1;
443let opNewValue = 0;
444let prefersSlot3 = 1;
445}
446def A2_maxp : HInst<
447(outs DoubleRegs:$Rdd32),
448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
449"$Rdd32 = max($Rss32,$Rtt32)",
450tc_8a825db2, TypeALU64>, Enc_a56825 {
451let Inst{7-5} = 0b100;
452let Inst{13-13} = 0b0;
453let Inst{31-21} = 0b11010011110;
454let prefersSlot3 = 1;
455}
456def A2_maxu : HInst<
457(outs IntRegs:$Rd32),
458(ins IntRegs:$Rs32, IntRegs:$Rt32),
459"$Rd32 = maxu($Rs32,$Rt32)",
460tc_8a825db2, TypeALU64>, Enc_5ab2be {
461let Inst{7-5} = 0b100;
462let Inst{13-13} = 0b0;
463let Inst{31-21} = 0b11010101110;
464let hasNewValue = 1;
465let opNewValue = 0;
466let prefersSlot3 = 1;
467}
468def A2_maxup : HInst<
469(outs DoubleRegs:$Rdd32),
470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
471"$Rdd32 = maxu($Rss32,$Rtt32)",
472tc_8a825db2, TypeALU64>, Enc_a56825 {
473let Inst{7-5} = 0b101;
474let Inst{13-13} = 0b0;
475let Inst{31-21} = 0b11010011110;
476let prefersSlot3 = 1;
477}
478def A2_min : HInst<
479(outs IntRegs:$Rd32),
480(ins IntRegs:$Rt32, IntRegs:$Rs32),
481"$Rd32 = min($Rt32,$Rs32)",
482tc_8a825db2, TypeALU64>, Enc_bd6011 {
483let Inst{7-5} = 0b000;
484let Inst{13-13} = 0b0;
485let Inst{31-21} = 0b11010101101;
486let hasNewValue = 1;
487let opNewValue = 0;
488let prefersSlot3 = 1;
489}
490def A2_minp : HInst<
491(outs DoubleRegs:$Rdd32),
492(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
493"$Rdd32 = min($Rtt32,$Rss32)",
494tc_8a825db2, TypeALU64>, Enc_ea23e4 {
495let Inst{7-5} = 0b110;
496let Inst{13-13} = 0b0;
497let Inst{31-21} = 0b11010011101;
498let prefersSlot3 = 1;
499}
500def A2_minu : HInst<
501(outs IntRegs:$Rd32),
502(ins IntRegs:$Rt32, IntRegs:$Rs32),
503"$Rd32 = minu($Rt32,$Rs32)",
504tc_8a825db2, TypeALU64>, Enc_bd6011 {
505let Inst{7-5} = 0b100;
506let Inst{13-13} = 0b0;
507let Inst{31-21} = 0b11010101101;
508let hasNewValue = 1;
509let opNewValue = 0;
510let prefersSlot3 = 1;
511}
512def A2_minup : HInst<
513(outs DoubleRegs:$Rdd32),
514(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
515"$Rdd32 = minu($Rtt32,$Rss32)",
516tc_8a825db2, TypeALU64>, Enc_ea23e4 {
517let Inst{7-5} = 0b111;
518let Inst{13-13} = 0b0;
519let Inst{31-21} = 0b11010011101;
520let prefersSlot3 = 1;
521}
522def A2_neg : HInst<
523(outs IntRegs:$Rd32),
524(ins IntRegs:$Rs32),
525"$Rd32 = neg($Rs32)",
526tc_c57d9f39, TypeALU32_2op> {
527let hasNewValue = 1;
528let opNewValue = 0;
529let isPseudo = 1;
530let isCodeGenOnly = 1;
531}
532def A2_negp : HInst<
533(outs DoubleRegs:$Rdd32),
534(ins DoubleRegs:$Rss32),
535"$Rdd32 = neg($Rss32)",
536tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
537let Inst{13-5} = 0b000000101;
538let Inst{31-21} = 0b10000000100;
539}
540def A2_negsat : HInst<
541(outs IntRegs:$Rd32),
542(ins IntRegs:$Rs32),
543"$Rd32 = neg($Rs32):sat",
544tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
545let Inst{13-5} = 0b000000110;
546let Inst{31-21} = 0b10001100100;
547let hasNewValue = 1;
548let opNewValue = 0;
549let prefersSlot3 = 1;
550let Defs = [USR_OVF];
551}
552def A2_nop : HInst<
553(outs),
554(ins),
555"nop",
556tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 {
557let Inst{13-0} = 0b00000000000000;
558let Inst{31-16} = 0b0111111100000000;
559}
560def A2_not : HInst<
561(outs IntRegs:$Rd32),
562(ins IntRegs:$Rs32),
563"$Rd32 = not($Rs32)",
564tc_c57d9f39, TypeALU32_2op> {
565let hasNewValue = 1;
566let opNewValue = 0;
567let isPseudo = 1;
568let isCodeGenOnly = 1;
569}
570def A2_notp : HInst<
571(outs DoubleRegs:$Rdd32),
572(ins DoubleRegs:$Rss32),
573"$Rdd32 = not($Rss32)",
574tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
575let Inst{13-5} = 0b000000100;
576let Inst{31-21} = 0b10000000100;
577}
578def A2_or : HInst<
579(outs IntRegs:$Rd32),
580(ins IntRegs:$Rs32, IntRegs:$Rt32),
581"$Rd32 = or($Rs32,$Rt32)",
582tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
583let Inst{7-5} = 0b000;
584let Inst{13-13} = 0b0;
585let Inst{31-21} = 0b11110001001;
586let hasNewValue = 1;
587let opNewValue = 0;
588let BaseOpcode = "A2_or";
589let CextOpcode = "A2_or";
590let InputType = "reg";
591let isCommutable = 1;
592let isPredicable = 1;
593}
594def A2_orir : HInst<
595(outs IntRegs:$Rd32),
596(ins IntRegs:$Rs32, s32_0Imm:$Ii),
597"$Rd32 = or($Rs32,#$Ii)",
598tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
599let Inst{31-22} = 0b0111011010;
600let hasNewValue = 1;
601let opNewValue = 0;
602let CextOpcode = "A2_or";
603let InputType = "imm";
604let isExtendable = 1;
605let opExtendable = 2;
606let isExtentSigned = 1;
607let opExtentBits = 10;
608let opExtentAlign = 0;
609}
610def A2_orp : HInst<
611(outs DoubleRegs:$Rdd32),
612(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
613"$Rdd32 = or($Rss32,$Rtt32)",
614tc_5da50c4b, TypeALU64>, Enc_a56825 {
615let Inst{7-5} = 0b010;
616let Inst{13-13} = 0b0;
617let Inst{31-21} = 0b11010011111;
618let isCommutable = 1;
619}
620def A2_paddf : HInst<
621(outs IntRegs:$Rd32),
622(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
623"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
624tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
625let Inst{7-7} = 0b1;
626let Inst{13-13} = 0b0;
627let Inst{31-21} = 0b11111011000;
628let isPredicated = 1;
629let isPredicatedFalse = 1;
630let hasNewValue = 1;
631let opNewValue = 0;
632let BaseOpcode = "A2_add";
633let CextOpcode = "A2_add";
634let InputType = "reg";
635}
636def A2_paddfnew : HInst<
637(outs IntRegs:$Rd32),
638(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
639"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
640tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
641let Inst{7-7} = 0b1;
642let Inst{13-13} = 0b1;
643let Inst{31-21} = 0b11111011000;
644let isPredicated = 1;
645let isPredicatedFalse = 1;
646let hasNewValue = 1;
647let opNewValue = 0;
648let isPredicatedNew = 1;
649let BaseOpcode = "A2_add";
650let CextOpcode = "A2_add";
651let InputType = "reg";
652}
653def A2_paddif : HInst<
654(outs IntRegs:$Rd32),
655(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
656"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
657tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
658let Inst{13-13} = 0b0;
659let Inst{31-23} = 0b011101001;
660let isPredicated = 1;
661let isPredicatedFalse = 1;
662let hasNewValue = 1;
663let opNewValue = 0;
664let BaseOpcode = "A2_addi";
665let CextOpcode = "A2_add";
666let InputType = "imm";
667let isExtendable = 1;
668let opExtendable = 3;
669let isExtentSigned = 1;
670let opExtentBits = 8;
671let opExtentAlign = 0;
672}
673def A2_paddifnew : HInst<
674(outs IntRegs:$Rd32),
675(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
676"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
677tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
678let Inst{13-13} = 0b1;
679let Inst{31-23} = 0b011101001;
680let isPredicated = 1;
681let isPredicatedFalse = 1;
682let hasNewValue = 1;
683let opNewValue = 0;
684let isPredicatedNew = 1;
685let BaseOpcode = "A2_addi";
686let CextOpcode = "A2_add";
687let InputType = "imm";
688let isExtendable = 1;
689let opExtendable = 3;
690let isExtentSigned = 1;
691let opExtentBits = 8;
692let opExtentAlign = 0;
693}
694def A2_paddit : HInst<
695(outs IntRegs:$Rd32),
696(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
697"if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
698tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
699let Inst{13-13} = 0b0;
700let Inst{31-23} = 0b011101000;
701let isPredicated = 1;
702let hasNewValue = 1;
703let opNewValue = 0;
704let BaseOpcode = "A2_addi";
705let CextOpcode = "A2_add";
706let InputType = "imm";
707let isExtendable = 1;
708let opExtendable = 3;
709let isExtentSigned = 1;
710let opExtentBits = 8;
711let opExtentAlign = 0;
712}
713def A2_padditnew : HInst<
714(outs IntRegs:$Rd32),
715(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
716"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
717tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
718let Inst{13-13} = 0b1;
719let Inst{31-23} = 0b011101000;
720let isPredicated = 1;
721let hasNewValue = 1;
722let opNewValue = 0;
723let isPredicatedNew = 1;
724let BaseOpcode = "A2_addi";
725let CextOpcode = "A2_add";
726let InputType = "imm";
727let isExtendable = 1;
728let opExtendable = 3;
729let isExtentSigned = 1;
730let opExtentBits = 8;
731let opExtentAlign = 0;
732}
733def A2_paddt : HInst<
734(outs IntRegs:$Rd32),
735(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
736"if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
737tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
738let Inst{7-7} = 0b0;
739let Inst{13-13} = 0b0;
740let Inst{31-21} = 0b11111011000;
741let isPredicated = 1;
742let hasNewValue = 1;
743let opNewValue = 0;
744let BaseOpcode = "A2_add";
745let CextOpcode = "A2_add";
746let InputType = "reg";
747}
748def A2_paddtnew : HInst<
749(outs IntRegs:$Rd32),
750(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
751"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
752tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
753let Inst{7-7} = 0b0;
754let Inst{13-13} = 0b1;
755let Inst{31-21} = 0b11111011000;
756let isPredicated = 1;
757let hasNewValue = 1;
758let opNewValue = 0;
759let isPredicatedNew = 1;
760let BaseOpcode = "A2_add";
761let CextOpcode = "A2_add";
762let InputType = "reg";
763}
764def A2_pandf : HInst<
765(outs IntRegs:$Rd32),
766(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
767"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
768tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
769let Inst{7-7} = 0b1;
770let Inst{13-13} = 0b0;
771let Inst{31-21} = 0b11111001000;
772let isPredicated = 1;
773let isPredicatedFalse = 1;
774let hasNewValue = 1;
775let opNewValue = 0;
776let BaseOpcode = "A2_and";
777}
778def A2_pandfnew : HInst<
779(outs IntRegs:$Rd32),
780(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
781"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
782tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
783let Inst{7-7} = 0b1;
784let Inst{13-13} = 0b1;
785let Inst{31-21} = 0b11111001000;
786let isPredicated = 1;
787let isPredicatedFalse = 1;
788let hasNewValue = 1;
789let opNewValue = 0;
790let isPredicatedNew = 1;
791let BaseOpcode = "A2_and";
792}
793def A2_pandt : HInst<
794(outs IntRegs:$Rd32),
795(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
796"if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
797tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
798let Inst{7-7} = 0b0;
799let Inst{13-13} = 0b0;
800let Inst{31-21} = 0b11111001000;
801let isPredicated = 1;
802let hasNewValue = 1;
803let opNewValue = 0;
804let BaseOpcode = "A2_and";
805}
806def A2_pandtnew : HInst<
807(outs IntRegs:$Rd32),
808(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
809"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
810tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
811let Inst{7-7} = 0b0;
812let Inst{13-13} = 0b1;
813let Inst{31-21} = 0b11111001000;
814let isPredicated = 1;
815let hasNewValue = 1;
816let opNewValue = 0;
817let isPredicatedNew = 1;
818let BaseOpcode = "A2_and";
819}
820def A2_porf : HInst<
821(outs IntRegs:$Rd32),
822(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
823"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
824tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
825let Inst{7-7} = 0b1;
826let Inst{13-13} = 0b0;
827let Inst{31-21} = 0b11111001001;
828let isPredicated = 1;
829let isPredicatedFalse = 1;
830let hasNewValue = 1;
831let opNewValue = 0;
832let BaseOpcode = "A2_or";
833}
834def A2_porfnew : HInst<
835(outs IntRegs:$Rd32),
836(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
837"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
838tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
839let Inst{7-7} = 0b1;
840let Inst{13-13} = 0b1;
841let Inst{31-21} = 0b11111001001;
842let isPredicated = 1;
843let isPredicatedFalse = 1;
844let hasNewValue = 1;
845let opNewValue = 0;
846let isPredicatedNew = 1;
847let BaseOpcode = "A2_or";
848}
849def A2_port : HInst<
850(outs IntRegs:$Rd32),
851(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
852"if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
853tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
854let Inst{7-7} = 0b0;
855let Inst{13-13} = 0b0;
856let Inst{31-21} = 0b11111001001;
857let isPredicated = 1;
858let hasNewValue = 1;
859let opNewValue = 0;
860let BaseOpcode = "A2_or";
861}
862def A2_portnew : HInst<
863(outs IntRegs:$Rd32),
864(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
865"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
866tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
867let Inst{7-7} = 0b0;
868let Inst{13-13} = 0b1;
869let Inst{31-21} = 0b11111001001;
870let isPredicated = 1;
871let hasNewValue = 1;
872let opNewValue = 0;
873let isPredicatedNew = 1;
874let BaseOpcode = "A2_or";
875}
876def A2_psubf : HInst<
877(outs IntRegs:$Rd32),
878(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
879"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
880tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
881let Inst{7-7} = 0b1;
882let Inst{13-13} = 0b0;
883let Inst{31-21} = 0b11111011001;
884let isPredicated = 1;
885let isPredicatedFalse = 1;
886let hasNewValue = 1;
887let opNewValue = 0;
888let BaseOpcode = "A2_sub";
889}
890def A2_psubfnew : HInst<
891(outs IntRegs:$Rd32),
892(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
893"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
894tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
895let Inst{7-7} = 0b1;
896let Inst{13-13} = 0b1;
897let Inst{31-21} = 0b11111011001;
898let isPredicated = 1;
899let isPredicatedFalse = 1;
900let hasNewValue = 1;
901let opNewValue = 0;
902let isPredicatedNew = 1;
903let BaseOpcode = "A2_sub";
904}
905def A2_psubt : HInst<
906(outs IntRegs:$Rd32),
907(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
908"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
909tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
910let Inst{7-7} = 0b0;
911let Inst{13-13} = 0b0;
912let Inst{31-21} = 0b11111011001;
913let isPredicated = 1;
914let hasNewValue = 1;
915let opNewValue = 0;
916let BaseOpcode = "A2_sub";
917}
918def A2_psubtnew : HInst<
919(outs IntRegs:$Rd32),
920(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
921"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
922tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
923let Inst{7-7} = 0b0;
924let Inst{13-13} = 0b1;
925let Inst{31-21} = 0b11111011001;
926let isPredicated = 1;
927let hasNewValue = 1;
928let opNewValue = 0;
929let isPredicatedNew = 1;
930let BaseOpcode = "A2_sub";
931}
932def A2_pxorf : HInst<
933(outs IntRegs:$Rd32),
934(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
935"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
936tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
937let Inst{7-7} = 0b1;
938let Inst{13-13} = 0b0;
939let Inst{31-21} = 0b11111001011;
940let isPredicated = 1;
941let isPredicatedFalse = 1;
942let hasNewValue = 1;
943let opNewValue = 0;
944let BaseOpcode = "A2_xor";
945}
946def A2_pxorfnew : HInst<
947(outs IntRegs:$Rd32),
948(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
949"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
950tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
951let Inst{7-7} = 0b1;
952let Inst{13-13} = 0b1;
953let Inst{31-21} = 0b11111001011;
954let isPredicated = 1;
955let isPredicatedFalse = 1;
956let hasNewValue = 1;
957let opNewValue = 0;
958let isPredicatedNew = 1;
959let BaseOpcode = "A2_xor";
960}
961def A2_pxort : HInst<
962(outs IntRegs:$Rd32),
963(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
964"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
965tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
966let Inst{7-7} = 0b0;
967let Inst{13-13} = 0b0;
968let Inst{31-21} = 0b11111001011;
969let isPredicated = 1;
970let hasNewValue = 1;
971let opNewValue = 0;
972let BaseOpcode = "A2_xor";
973}
974def A2_pxortnew : HInst<
975(outs IntRegs:$Rd32),
976(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
977"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
978tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
979let Inst{7-7} = 0b0;
980let Inst{13-13} = 0b1;
981let Inst{31-21} = 0b11111001011;
982let isPredicated = 1;
983let hasNewValue = 1;
984let opNewValue = 0;
985let isPredicatedNew = 1;
986let BaseOpcode = "A2_xor";
987}
988def A2_roundsat : HInst<
989(outs IntRegs:$Rd32),
990(ins DoubleRegs:$Rss32),
991"$Rd32 = round($Rss32):sat",
992tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
993let Inst{13-5} = 0b000000001;
994let Inst{31-21} = 0b10001000110;
995let hasNewValue = 1;
996let opNewValue = 0;
997let prefersSlot3 = 1;
998let Defs = [USR_OVF];
999}
1000def A2_sat : HInst<
1001(outs IntRegs:$Rd32),
1002(ins DoubleRegs:$Rss32),
1003"$Rd32 = sat($Rss32)",
1004tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
1005let Inst{13-5} = 0b000000000;
1006let Inst{31-21} = 0b10001000110;
1007let hasNewValue = 1;
1008let opNewValue = 0;
1009let Defs = [USR_OVF];
1010}
1011def A2_satb : HInst<
1012(outs IntRegs:$Rd32),
1013(ins IntRegs:$Rs32),
1014"$Rd32 = satb($Rs32)",
1015tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1016let Inst{13-5} = 0b000000111;
1017let Inst{31-21} = 0b10001100110;
1018let hasNewValue = 1;
1019let opNewValue = 0;
1020let Defs = [USR_OVF];
1021}
1022def A2_sath : HInst<
1023(outs IntRegs:$Rd32),
1024(ins IntRegs:$Rs32),
1025"$Rd32 = sath($Rs32)",
1026tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1027let Inst{13-5} = 0b000000100;
1028let Inst{31-21} = 0b10001100110;
1029let hasNewValue = 1;
1030let opNewValue = 0;
1031let Defs = [USR_OVF];
1032}
1033def A2_satub : HInst<
1034(outs IntRegs:$Rd32),
1035(ins IntRegs:$Rs32),
1036"$Rd32 = satub($Rs32)",
1037tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1038let Inst{13-5} = 0b000000110;
1039let Inst{31-21} = 0b10001100110;
1040let hasNewValue = 1;
1041let opNewValue = 0;
1042let Defs = [USR_OVF];
1043}
1044def A2_satuh : HInst<
1045(outs IntRegs:$Rd32),
1046(ins IntRegs:$Rs32),
1047"$Rd32 = satuh($Rs32)",
1048tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1049let Inst{13-5} = 0b000000101;
1050let Inst{31-21} = 0b10001100110;
1051let hasNewValue = 1;
1052let opNewValue = 0;
1053let Defs = [USR_OVF];
1054}
1055def A2_sub : HInst<
1056(outs IntRegs:$Rd32),
1057(ins IntRegs:$Rt32, IntRegs:$Rs32),
1058"$Rd32 = sub($Rt32,$Rs32)",
1059tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
1060let Inst{7-5} = 0b000;
1061let Inst{13-13} = 0b0;
1062let Inst{31-21} = 0b11110011001;
1063let hasNewValue = 1;
1064let opNewValue = 0;
1065let BaseOpcode = "A2_sub";
1066let CextOpcode = "A2_sub";
1067let InputType = "reg";
1068let isPredicable = 1;
1069}
1070def A2_subh_h16_hh : HInst<
1071(outs IntRegs:$Rd32),
1072(ins IntRegs:$Rt32, IntRegs:$Rs32),
1073"$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
1074tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1075let Inst{7-5} = 0b011;
1076let Inst{13-13} = 0b0;
1077let Inst{31-21} = 0b11010101011;
1078let hasNewValue = 1;
1079let opNewValue = 0;
1080let prefersSlot3 = 1;
1081}
1082def A2_subh_h16_hl : HInst<
1083(outs IntRegs:$Rd32),
1084(ins IntRegs:$Rt32, IntRegs:$Rs32),
1085"$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
1086tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1087let Inst{7-5} = 0b010;
1088let Inst{13-13} = 0b0;
1089let Inst{31-21} = 0b11010101011;
1090let hasNewValue = 1;
1091let opNewValue = 0;
1092let prefersSlot3 = 1;
1093}
1094def A2_subh_h16_lh : HInst<
1095(outs IntRegs:$Rd32),
1096(ins IntRegs:$Rt32, IntRegs:$Rs32),
1097"$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
1098tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1099let Inst{7-5} = 0b001;
1100let Inst{13-13} = 0b0;
1101let Inst{31-21} = 0b11010101011;
1102let hasNewValue = 1;
1103let opNewValue = 0;
1104let prefersSlot3 = 1;
1105}
1106def A2_subh_h16_ll : HInst<
1107(outs IntRegs:$Rd32),
1108(ins IntRegs:$Rt32, IntRegs:$Rs32),
1109"$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
1110tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1111let Inst{7-5} = 0b000;
1112let Inst{13-13} = 0b0;
1113let Inst{31-21} = 0b11010101011;
1114let hasNewValue = 1;
1115let opNewValue = 0;
1116let prefersSlot3 = 1;
1117}
1118def A2_subh_h16_sat_hh : HInst<
1119(outs IntRegs:$Rd32),
1120(ins IntRegs:$Rt32, IntRegs:$Rs32),
1121"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
1122tc_8a825db2, TypeALU64>, Enc_bd6011 {
1123let Inst{7-5} = 0b111;
1124let Inst{13-13} = 0b0;
1125let Inst{31-21} = 0b11010101011;
1126let hasNewValue = 1;
1127let opNewValue = 0;
1128let prefersSlot3 = 1;
1129let Defs = [USR_OVF];
1130}
1131def A2_subh_h16_sat_hl : HInst<
1132(outs IntRegs:$Rd32),
1133(ins IntRegs:$Rt32, IntRegs:$Rs32),
1134"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
1135tc_8a825db2, TypeALU64>, Enc_bd6011 {
1136let Inst{7-5} = 0b110;
1137let Inst{13-13} = 0b0;
1138let Inst{31-21} = 0b11010101011;
1139let hasNewValue = 1;
1140let opNewValue = 0;
1141let prefersSlot3 = 1;
1142let Defs = [USR_OVF];
1143}
1144def A2_subh_h16_sat_lh : HInst<
1145(outs IntRegs:$Rd32),
1146(ins IntRegs:$Rt32, IntRegs:$Rs32),
1147"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
1148tc_8a825db2, TypeALU64>, Enc_bd6011 {
1149let Inst{7-5} = 0b101;
1150let Inst{13-13} = 0b0;
1151let Inst{31-21} = 0b11010101011;
1152let hasNewValue = 1;
1153let opNewValue = 0;
1154let prefersSlot3 = 1;
1155let Defs = [USR_OVF];
1156}
1157def A2_subh_h16_sat_ll : HInst<
1158(outs IntRegs:$Rd32),
1159(ins IntRegs:$Rt32, IntRegs:$Rs32),
1160"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
1161tc_8a825db2, TypeALU64>, Enc_bd6011 {
1162let Inst{7-5} = 0b100;
1163let Inst{13-13} = 0b0;
1164let Inst{31-21} = 0b11010101011;
1165let hasNewValue = 1;
1166let opNewValue = 0;
1167let prefersSlot3 = 1;
1168let Defs = [USR_OVF];
1169}
1170def A2_subh_l16_hl : HInst<
1171(outs IntRegs:$Rd32),
1172(ins IntRegs:$Rt32, IntRegs:$Rs32),
1173"$Rd32 = sub($Rt32.l,$Rs32.h)",
1174tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1175let Inst{7-5} = 0b010;
1176let Inst{13-13} = 0b0;
1177let Inst{31-21} = 0b11010101001;
1178let hasNewValue = 1;
1179let opNewValue = 0;
1180let prefersSlot3 = 1;
1181}
1182def A2_subh_l16_ll : HInst<
1183(outs IntRegs:$Rd32),
1184(ins IntRegs:$Rt32, IntRegs:$Rs32),
1185"$Rd32 = sub($Rt32.l,$Rs32.l)",
1186tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1187let Inst{7-5} = 0b000;
1188let Inst{13-13} = 0b0;
1189let Inst{31-21} = 0b11010101001;
1190let hasNewValue = 1;
1191let opNewValue = 0;
1192let prefersSlot3 = 1;
1193}
1194def A2_subh_l16_sat_hl : HInst<
1195(outs IntRegs:$Rd32),
1196(ins IntRegs:$Rt32, IntRegs:$Rs32),
1197"$Rd32 = sub($Rt32.l,$Rs32.h):sat",
1198tc_8a825db2, TypeALU64>, Enc_bd6011 {
1199let Inst{7-5} = 0b110;
1200let Inst{13-13} = 0b0;
1201let Inst{31-21} = 0b11010101001;
1202let hasNewValue = 1;
1203let opNewValue = 0;
1204let prefersSlot3 = 1;
1205let Defs = [USR_OVF];
1206}
1207def A2_subh_l16_sat_ll : HInst<
1208(outs IntRegs:$Rd32),
1209(ins IntRegs:$Rt32, IntRegs:$Rs32),
1210"$Rd32 = sub($Rt32.l,$Rs32.l):sat",
1211tc_8a825db2, TypeALU64>, Enc_bd6011 {
1212let Inst{7-5} = 0b100;
1213let Inst{13-13} = 0b0;
1214let Inst{31-21} = 0b11010101001;
1215let hasNewValue = 1;
1216let opNewValue = 0;
1217let prefersSlot3 = 1;
1218let Defs = [USR_OVF];
1219}
1220def A2_subp : HInst<
1221(outs DoubleRegs:$Rdd32),
1222(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1223"$Rdd32 = sub($Rtt32,$Rss32)",
1224tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
1225let Inst{7-5} = 0b111;
1226let Inst{13-13} = 0b0;
1227let Inst{31-21} = 0b11010011001;
1228}
1229def A2_subri : HInst<
1230(outs IntRegs:$Rd32),
1231(ins s32_0Imm:$Ii, IntRegs:$Rs32),
1232"$Rd32 = sub(#$Ii,$Rs32)",
1233tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
1234let Inst{31-22} = 0b0111011001;
1235let hasNewValue = 1;
1236let opNewValue = 0;
1237let CextOpcode = "A2_sub";
1238let InputType = "imm";
1239let isExtendable = 1;
1240let opExtendable = 1;
1241let isExtentSigned = 1;
1242let opExtentBits = 10;
1243let opExtentAlign = 0;
1244}
1245def A2_subsat : HInst<
1246(outs IntRegs:$Rd32),
1247(ins IntRegs:$Rt32, IntRegs:$Rs32),
1248"$Rd32 = sub($Rt32,$Rs32):sat",
1249tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1250let Inst{7-5} = 0b000;
1251let Inst{13-13} = 0b0;
1252let Inst{31-21} = 0b11110110110;
1253let hasNewValue = 1;
1254let opNewValue = 0;
1255let prefersSlot3 = 1;
1256let Defs = [USR_OVF];
1257let InputType = "reg";
1258}
1259def A2_svaddh : HInst<
1260(outs IntRegs:$Rd32),
1261(ins IntRegs:$Rs32, IntRegs:$Rt32),
1262"$Rd32 = vaddh($Rs32,$Rt32)",
1263tc_713b66bf, TypeALU32_3op>, Enc_5ab2be {
1264let Inst{7-5} = 0b000;
1265let Inst{13-13} = 0b0;
1266let Inst{31-21} = 0b11110110000;
1267let hasNewValue = 1;
1268let opNewValue = 0;
1269let InputType = "reg";
1270let isCommutable = 1;
1271}
1272def A2_svaddhs : HInst<
1273(outs IntRegs:$Rd32),
1274(ins IntRegs:$Rs32, IntRegs:$Rt32),
1275"$Rd32 = vaddh($Rs32,$Rt32):sat",
1276tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1277let Inst{7-5} = 0b000;
1278let Inst{13-13} = 0b0;
1279let Inst{31-21} = 0b11110110001;
1280let hasNewValue = 1;
1281let opNewValue = 0;
1282let prefersSlot3 = 1;
1283let Defs = [USR_OVF];
1284let InputType = "reg";
1285let isCommutable = 1;
1286}
1287def A2_svadduhs : HInst<
1288(outs IntRegs:$Rd32),
1289(ins IntRegs:$Rs32, IntRegs:$Rt32),
1290"$Rd32 = vadduh($Rs32,$Rt32):sat",
1291tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1292let Inst{7-5} = 0b000;
1293let Inst{13-13} = 0b0;
1294let Inst{31-21} = 0b11110110011;
1295let hasNewValue = 1;
1296let opNewValue = 0;
1297let prefersSlot3 = 1;
1298let Defs = [USR_OVF];
1299let InputType = "reg";
1300let isCommutable = 1;
1301}
1302def A2_svavgh : HInst<
1303(outs IntRegs:$Rd32),
1304(ins IntRegs:$Rs32, IntRegs:$Rt32),
1305"$Rd32 = vavgh($Rs32,$Rt32)",
1306tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be {
1307let Inst{7-5} = 0b000;
1308let Inst{13-13} = 0b0;
1309let Inst{31-21} = 0b11110111000;
1310let hasNewValue = 1;
1311let opNewValue = 0;
1312let prefersSlot3 = 1;
1313let InputType = "reg";
1314let isCommutable = 1;
1315}
1316def A2_svavghs : HInst<
1317(outs IntRegs:$Rd32),
1318(ins IntRegs:$Rs32, IntRegs:$Rt32),
1319"$Rd32 = vavgh($Rs32,$Rt32):rnd",
1320tc_84a7500d, TypeALU32_3op>, Enc_5ab2be {
1321let Inst{7-5} = 0b000;
1322let Inst{13-13} = 0b0;
1323let Inst{31-21} = 0b11110111001;
1324let hasNewValue = 1;
1325let opNewValue = 0;
1326let prefersSlot3 = 1;
1327let InputType = "reg";
1328let isCommutable = 1;
1329}
1330def A2_svnavgh : HInst<
1331(outs IntRegs:$Rd32),
1332(ins IntRegs:$Rt32, IntRegs:$Rs32),
1333"$Rd32 = vnavgh($Rt32,$Rs32)",
1334tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 {
1335let Inst{7-5} = 0b000;
1336let Inst{13-13} = 0b0;
1337let Inst{31-21} = 0b11110111011;
1338let hasNewValue = 1;
1339let opNewValue = 0;
1340let prefersSlot3 = 1;
1341let InputType = "reg";
1342}
1343def A2_svsubh : HInst<
1344(outs IntRegs:$Rd32),
1345(ins IntRegs:$Rt32, IntRegs:$Rs32),
1346"$Rd32 = vsubh($Rt32,$Rs32)",
1347tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
1348let Inst{7-5} = 0b000;
1349let Inst{13-13} = 0b0;
1350let Inst{31-21} = 0b11110110100;
1351let hasNewValue = 1;
1352let opNewValue = 0;
1353let InputType = "reg";
1354}
1355def A2_svsubhs : HInst<
1356(outs IntRegs:$Rd32),
1357(ins IntRegs:$Rt32, IntRegs:$Rs32),
1358"$Rd32 = vsubh($Rt32,$Rs32):sat",
1359tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1360let Inst{7-5} = 0b000;
1361let Inst{13-13} = 0b0;
1362let Inst{31-21} = 0b11110110101;
1363let hasNewValue = 1;
1364let opNewValue = 0;
1365let prefersSlot3 = 1;
1366let Defs = [USR_OVF];
1367let InputType = "reg";
1368}
1369def A2_svsubuhs : HInst<
1370(outs IntRegs:$Rd32),
1371(ins IntRegs:$Rt32, IntRegs:$Rs32),
1372"$Rd32 = vsubuh($Rt32,$Rs32):sat",
1373tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1374let Inst{7-5} = 0b000;
1375let Inst{13-13} = 0b0;
1376let Inst{31-21} = 0b11110110111;
1377let hasNewValue = 1;
1378let opNewValue = 0;
1379let prefersSlot3 = 1;
1380let Defs = [USR_OVF];
1381let InputType = "reg";
1382}
1383def A2_swiz : HInst<
1384(outs IntRegs:$Rd32),
1385(ins IntRegs:$Rs32),
1386"$Rd32 = swiz($Rs32)",
1387tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1388let Inst{13-5} = 0b000000111;
1389let Inst{31-21} = 0b10001100100;
1390let hasNewValue = 1;
1391let opNewValue = 0;
1392}
1393def A2_sxtb : HInst<
1394(outs IntRegs:$Rd32),
1395(ins IntRegs:$Rs32),
1396"$Rd32 = sxtb($Rs32)",
1397tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1398let Inst{13-5} = 0b000000000;
1399let Inst{31-21} = 0b01110000101;
1400let hasNewValue = 1;
1401let opNewValue = 0;
1402let BaseOpcode = "A2_sxtb";
1403let isPredicable = 1;
1404}
1405def A2_sxth : HInst<
1406(outs IntRegs:$Rd32),
1407(ins IntRegs:$Rs32),
1408"$Rd32 = sxth($Rs32)",
1409tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1410let Inst{13-5} = 0b000000000;
1411let Inst{31-21} = 0b01110000111;
1412let hasNewValue = 1;
1413let opNewValue = 0;
1414let BaseOpcode = "A2_sxth";
1415let isPredicable = 1;
1416}
1417def A2_sxtw : HInst<
1418(outs DoubleRegs:$Rdd32),
1419(ins IntRegs:$Rs32),
1420"$Rdd32 = sxtw($Rs32)",
1421tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
1422let Inst{13-5} = 0b000000000;
1423let Inst{31-21} = 0b10000100010;
1424}
1425def A2_tfr : HInst<
1426(outs IntRegs:$Rd32),
1427(ins IntRegs:$Rs32),
1428"$Rd32 = $Rs32",
1429tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1430let Inst{13-5} = 0b000000000;
1431let Inst{31-21} = 0b01110000011;
1432let hasNewValue = 1;
1433let opNewValue = 0;
1434let BaseOpcode = "A2_tfr";
1435let InputType = "reg";
1436let isPredicable = 1;
1437}
1438def A2_tfrcrr : HInst<
1439(outs IntRegs:$Rd32),
1440(ins CtrRegs:$Cs32),
1441"$Rd32 = $Cs32",
1442tc_7476d766, TypeCR>, Enc_0cb018 {
1443let Inst{13-5} = 0b000000000;
1444let Inst{31-21} = 0b01101010000;
1445let hasNewValue = 1;
1446let opNewValue = 0;
1447}
1448def A2_tfrf : HInst<
1449(outs IntRegs:$Rd32),
1450(ins PredRegs:$Pu4, IntRegs:$Rs32),
1451"if (!$Pu4) $Rd32 = $Rs32",
1452tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1453let isPredicated = 1;
1454let isPredicatedFalse = 1;
1455let hasNewValue = 1;
1456let opNewValue = 0;
1457let BaseOpcode = "A2_tfr";
1458let CextOpcode = "A2_tfr";
1459let InputType = "reg";
1460let isPseudo = 1;
1461let isCodeGenOnly = 1;
1462}
1463def A2_tfrfnew : HInst<
1464(outs IntRegs:$Rd32),
1465(ins PredRegs:$Pu4, IntRegs:$Rs32),
1466"if (!$Pu4.new) $Rd32 = $Rs32",
1467tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1468let isPredicated = 1;
1469let isPredicatedFalse = 1;
1470let hasNewValue = 1;
1471let opNewValue = 0;
1472let isPredicatedNew = 1;
1473let BaseOpcode = "A2_tfr";
1474let CextOpcode = "A2_tfr";
1475let InputType = "reg";
1476let isPseudo = 1;
1477let isCodeGenOnly = 1;
1478}
1479def A2_tfrih : HInst<
1480(outs IntRegs:$Rx32),
1481(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1482"$Rx32.h = #$Ii",
1483tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1484let Inst{21-21} = 0b1;
1485let Inst{31-24} = 0b01110010;
1486let hasNewValue = 1;
1487let opNewValue = 0;
1488let Constraints = "$Rx32 = $Rx32in";
1489}
1490def A2_tfril : HInst<
1491(outs IntRegs:$Rx32),
1492(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1493"$Rx32.l = #$Ii",
1494tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1495let Inst{21-21} = 0b1;
1496let Inst{31-24} = 0b01110001;
1497let hasNewValue = 1;
1498let opNewValue = 0;
1499let Constraints = "$Rx32 = $Rx32in";
1500}
1501def A2_tfrp : HInst<
1502(outs DoubleRegs:$Rdd32),
1503(ins DoubleRegs:$Rss32),
1504"$Rdd32 = $Rss32",
1505tc_713b66bf, TypeALU32_2op>, PredNewRel {
1506let BaseOpcode = "A2_tfrp";
1507let isPredicable = 1;
1508let isPseudo = 1;
1509}
1510def A2_tfrpf : HInst<
1511(outs DoubleRegs:$Rdd32),
1512(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1513"if (!$Pu4) $Rdd32 = $Rss32",
1514tc_713b66bf, TypeALU32_2op>, PredNewRel {
1515let isPredicated = 1;
1516let isPredicatedFalse = 1;
1517let BaseOpcode = "A2_tfrp";
1518let isPseudo = 1;
1519}
1520def A2_tfrpfnew : HInst<
1521(outs DoubleRegs:$Rdd32),
1522(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1523"if (!$Pu4.new) $Rdd32 = $Rss32",
1524tc_86173609, TypeALU32_2op>, PredNewRel {
1525let isPredicated = 1;
1526let isPredicatedFalse = 1;
1527let isPredicatedNew = 1;
1528let BaseOpcode = "A2_tfrp";
1529let isPseudo = 1;
1530}
1531def A2_tfrpi : HInst<
1532(outs DoubleRegs:$Rdd32),
1533(ins s8_0Imm:$Ii),
1534"$Rdd32 = #$Ii",
1535tc_713b66bf, TypeALU64> {
1536let isReMaterializable = 1;
1537let isAsCheapAsAMove = 1;
1538let isMoveImm = 1;
1539let isPseudo = 1;
1540}
1541def A2_tfrpt : HInst<
1542(outs DoubleRegs:$Rdd32),
1543(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1544"if ($Pu4) $Rdd32 = $Rss32",
1545tc_713b66bf, TypeALU32_2op>, PredNewRel {
1546let isPredicated = 1;
1547let BaseOpcode = "A2_tfrp";
1548let isPseudo = 1;
1549}
1550def A2_tfrptnew : HInst<
1551(outs DoubleRegs:$Rdd32),
1552(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1553"if ($Pu4.new) $Rdd32 = $Rss32",
1554tc_86173609, TypeALU32_2op>, PredNewRel {
1555let isPredicated = 1;
1556let isPredicatedNew = 1;
1557let BaseOpcode = "A2_tfrp";
1558let isPseudo = 1;
1559}
1560def A2_tfrrcr : HInst<
1561(outs CtrRegs:$Cd32),
1562(ins IntRegs:$Rs32),
1563"$Cd32 = $Rs32",
1564tc_49fdfd4b, TypeCR>, Enc_bd811a {
1565let Inst{13-5} = 0b000000000;
1566let Inst{31-21} = 0b01100010001;
1567let hasNewValue = 1;
1568let opNewValue = 0;
1569}
1570def A2_tfrsi : HInst<
1571(outs IntRegs:$Rd32),
1572(ins s32_0Imm:$Ii),
1573"$Rd32 = #$Ii",
1574tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
1575let Inst{21-21} = 0b0;
1576let Inst{31-24} = 0b01111000;
1577let hasNewValue = 1;
1578let opNewValue = 0;
1579let BaseOpcode = "A2_tfrsi";
1580let CextOpcode = "A2_tfr";
1581let InputType = "imm";
1582let isPredicable = 1;
1583let isReMaterializable = 1;
1584let isAsCheapAsAMove = 1;
1585let isMoveImm = 1;
1586let isExtendable = 1;
1587let opExtendable = 1;
1588let isExtentSigned = 1;
1589let opExtentBits = 16;
1590let opExtentAlign = 0;
1591}
1592def A2_tfrt : HInst<
1593(outs IntRegs:$Rd32),
1594(ins PredRegs:$Pu4, IntRegs:$Rs32),
1595"if ($Pu4) $Rd32 = $Rs32",
1596tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1597let isPredicated = 1;
1598let hasNewValue = 1;
1599let opNewValue = 0;
1600let BaseOpcode = "A2_tfr";
1601let CextOpcode = "A2_tfr";
1602let InputType = "reg";
1603let isPseudo = 1;
1604let isCodeGenOnly = 1;
1605}
1606def A2_tfrtnew : HInst<
1607(outs IntRegs:$Rd32),
1608(ins PredRegs:$Pu4, IntRegs:$Rs32),
1609"if ($Pu4.new) $Rd32 = $Rs32",
1610tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1611let isPredicated = 1;
1612let hasNewValue = 1;
1613let opNewValue = 0;
1614let isPredicatedNew = 1;
1615let BaseOpcode = "A2_tfr";
1616let CextOpcode = "A2_tfr";
1617let InputType = "reg";
1618let isPseudo = 1;
1619let isCodeGenOnly = 1;
1620}
1621def A2_vabsh : HInst<
1622(outs DoubleRegs:$Rdd32),
1623(ins DoubleRegs:$Rss32),
1624"$Rdd32 = vabsh($Rss32)",
1625tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1626let Inst{13-5} = 0b000000100;
1627let Inst{31-21} = 0b10000000010;
1628let prefersSlot3 = 1;
1629}
1630def A2_vabshsat : HInst<
1631(outs DoubleRegs:$Rdd32),
1632(ins DoubleRegs:$Rss32),
1633"$Rdd32 = vabsh($Rss32):sat",
1634tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1635let Inst{13-5} = 0b000000101;
1636let Inst{31-21} = 0b10000000010;
1637let prefersSlot3 = 1;
1638let Defs = [USR_OVF];
1639}
1640def A2_vabsw : HInst<
1641(outs DoubleRegs:$Rdd32),
1642(ins DoubleRegs:$Rss32),
1643"$Rdd32 = vabsw($Rss32)",
1644tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1645let Inst{13-5} = 0b000000110;
1646let Inst{31-21} = 0b10000000010;
1647let prefersSlot3 = 1;
1648}
1649def A2_vabswsat : HInst<
1650(outs DoubleRegs:$Rdd32),
1651(ins DoubleRegs:$Rss32),
1652"$Rdd32 = vabsw($Rss32):sat",
1653tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1654let Inst{13-5} = 0b000000111;
1655let Inst{31-21} = 0b10000000010;
1656let prefersSlot3 = 1;
1657let Defs = [USR_OVF];
1658}
1659def A2_vaddb_map : HInst<
1660(outs DoubleRegs:$Rdd32),
1661(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1662"$Rdd32 = vaddb($Rss32,$Rtt32)",
1663tc_5da50c4b, TypeMAPPING> {
1664let isPseudo = 1;
1665let isCodeGenOnly = 1;
1666}
1667def A2_vaddh : HInst<
1668(outs DoubleRegs:$Rdd32),
1669(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1670"$Rdd32 = vaddh($Rss32,$Rtt32)",
1671tc_5da50c4b, TypeALU64>, Enc_a56825 {
1672let Inst{7-5} = 0b010;
1673let Inst{13-13} = 0b0;
1674let Inst{31-21} = 0b11010011000;
1675}
1676def A2_vaddhs : HInst<
1677(outs DoubleRegs:$Rdd32),
1678(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1679"$Rdd32 = vaddh($Rss32,$Rtt32):sat",
1680tc_8a825db2, TypeALU64>, Enc_a56825 {
1681let Inst{7-5} = 0b011;
1682let Inst{13-13} = 0b0;
1683let Inst{31-21} = 0b11010011000;
1684let prefersSlot3 = 1;
1685let Defs = [USR_OVF];
1686}
1687def A2_vaddub : HInst<
1688(outs DoubleRegs:$Rdd32),
1689(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1690"$Rdd32 = vaddub($Rss32,$Rtt32)",
1691tc_5da50c4b, TypeALU64>, Enc_a56825 {
1692let Inst{7-5} = 0b000;
1693let Inst{13-13} = 0b0;
1694let Inst{31-21} = 0b11010011000;
1695}
1696def A2_vaddubs : HInst<
1697(outs DoubleRegs:$Rdd32),
1698(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1699"$Rdd32 = vaddub($Rss32,$Rtt32):sat",
1700tc_8a825db2, TypeALU64>, Enc_a56825 {
1701let Inst{7-5} = 0b001;
1702let Inst{13-13} = 0b0;
1703let Inst{31-21} = 0b11010011000;
1704let prefersSlot3 = 1;
1705let Defs = [USR_OVF];
1706}
1707def A2_vadduhs : HInst<
1708(outs DoubleRegs:$Rdd32),
1709(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1710"$Rdd32 = vadduh($Rss32,$Rtt32):sat",
1711tc_8a825db2, TypeALU64>, Enc_a56825 {
1712let Inst{7-5} = 0b100;
1713let Inst{13-13} = 0b0;
1714let Inst{31-21} = 0b11010011000;
1715let prefersSlot3 = 1;
1716let Defs = [USR_OVF];
1717}
1718def A2_vaddw : HInst<
1719(outs DoubleRegs:$Rdd32),
1720(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1721"$Rdd32 = vaddw($Rss32,$Rtt32)",
1722tc_5da50c4b, TypeALU64>, Enc_a56825 {
1723let Inst{7-5} = 0b101;
1724let Inst{13-13} = 0b0;
1725let Inst{31-21} = 0b11010011000;
1726}
1727def A2_vaddws : HInst<
1728(outs DoubleRegs:$Rdd32),
1729(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1730"$Rdd32 = vaddw($Rss32,$Rtt32):sat",
1731tc_8a825db2, TypeALU64>, Enc_a56825 {
1732let Inst{7-5} = 0b110;
1733let Inst{13-13} = 0b0;
1734let Inst{31-21} = 0b11010011000;
1735let prefersSlot3 = 1;
1736let Defs = [USR_OVF];
1737}
1738def A2_vavgh : HInst<
1739(outs DoubleRegs:$Rdd32),
1740(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1741"$Rdd32 = vavgh($Rss32,$Rtt32)",
1742tc_f098b237, TypeALU64>, Enc_a56825 {
1743let Inst{7-5} = 0b010;
1744let Inst{13-13} = 0b0;
1745let Inst{31-21} = 0b11010011010;
1746let prefersSlot3 = 1;
1747}
1748def A2_vavghcr : HInst<
1749(outs DoubleRegs:$Rdd32),
1750(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1751"$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
1752tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1753let Inst{7-5} = 0b100;
1754let Inst{13-13} = 0b0;
1755let Inst{31-21} = 0b11010011010;
1756let prefersSlot3 = 1;
1757}
1758def A2_vavghr : HInst<
1759(outs DoubleRegs:$Rdd32),
1760(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1761"$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
1762tc_20131976, TypeALU64>, Enc_a56825 {
1763let Inst{7-5} = 0b011;
1764let Inst{13-13} = 0b0;
1765let Inst{31-21} = 0b11010011010;
1766let prefersSlot3 = 1;
1767}
1768def A2_vavgub : HInst<
1769(outs DoubleRegs:$Rdd32),
1770(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1771"$Rdd32 = vavgub($Rss32,$Rtt32)",
1772tc_f098b237, TypeALU64>, Enc_a56825 {
1773let Inst{7-5} = 0b000;
1774let Inst{13-13} = 0b0;
1775let Inst{31-21} = 0b11010011010;
1776let prefersSlot3 = 1;
1777}
1778def A2_vavgubr : HInst<
1779(outs DoubleRegs:$Rdd32),
1780(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1781"$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
1782tc_20131976, TypeALU64>, Enc_a56825 {
1783let Inst{7-5} = 0b001;
1784let Inst{13-13} = 0b0;
1785let Inst{31-21} = 0b11010011010;
1786let prefersSlot3 = 1;
1787}
1788def A2_vavguh : HInst<
1789(outs DoubleRegs:$Rdd32),
1790(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1791"$Rdd32 = vavguh($Rss32,$Rtt32)",
1792tc_f098b237, TypeALU64>, Enc_a56825 {
1793let Inst{7-5} = 0b101;
1794let Inst{13-13} = 0b0;
1795let Inst{31-21} = 0b11010011010;
1796let prefersSlot3 = 1;
1797}
1798def A2_vavguhr : HInst<
1799(outs DoubleRegs:$Rdd32),
1800(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1801"$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
1802tc_20131976, TypeALU64>, Enc_a56825 {
1803let Inst{7-5} = 0b110;
1804let Inst{13-13} = 0b0;
1805let Inst{31-21} = 0b11010011010;
1806let prefersSlot3 = 1;
1807}
1808def A2_vavguw : HInst<
1809(outs DoubleRegs:$Rdd32),
1810(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1811"$Rdd32 = vavguw($Rss32,$Rtt32)",
1812tc_f098b237, TypeALU64>, Enc_a56825 {
1813let Inst{7-5} = 0b011;
1814let Inst{13-13} = 0b0;
1815let Inst{31-21} = 0b11010011011;
1816let prefersSlot3 = 1;
1817}
1818def A2_vavguwr : HInst<
1819(outs DoubleRegs:$Rdd32),
1820(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1821"$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
1822tc_20131976, TypeALU64>, Enc_a56825 {
1823let Inst{7-5} = 0b100;
1824let Inst{13-13} = 0b0;
1825let Inst{31-21} = 0b11010011011;
1826let prefersSlot3 = 1;
1827}
1828def A2_vavgw : HInst<
1829(outs DoubleRegs:$Rdd32),
1830(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1831"$Rdd32 = vavgw($Rss32,$Rtt32)",
1832tc_f098b237, TypeALU64>, Enc_a56825 {
1833let Inst{7-5} = 0b000;
1834let Inst{13-13} = 0b0;
1835let Inst{31-21} = 0b11010011011;
1836let prefersSlot3 = 1;
1837}
1838def A2_vavgwcr : HInst<
1839(outs DoubleRegs:$Rdd32),
1840(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1841"$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
1842tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1843let Inst{7-5} = 0b010;
1844let Inst{13-13} = 0b0;
1845let Inst{31-21} = 0b11010011011;
1846let prefersSlot3 = 1;
1847}
1848def A2_vavgwr : HInst<
1849(outs DoubleRegs:$Rdd32),
1850(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1851"$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
1852tc_20131976, TypeALU64>, Enc_a56825 {
1853let Inst{7-5} = 0b001;
1854let Inst{13-13} = 0b0;
1855let Inst{31-21} = 0b11010011011;
1856let prefersSlot3 = 1;
1857}
1858def A2_vcmpbeq : HInst<
1859(outs PredRegs:$Pd4),
1860(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1861"$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
1862tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1863let Inst{7-2} = 0b110000;
1864let Inst{13-13} = 0b0;
1865let Inst{31-21} = 0b11010010000;
1866}
1867def A2_vcmpbgtu : HInst<
1868(outs PredRegs:$Pd4),
1869(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1870"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
1871tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1872let Inst{7-2} = 0b111000;
1873let Inst{13-13} = 0b0;
1874let Inst{31-21} = 0b11010010000;
1875}
1876def A2_vcmpheq : HInst<
1877(outs PredRegs:$Pd4),
1878(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1879"$Pd4 = vcmph.eq($Rss32,$Rtt32)",
1880tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1881let Inst{7-2} = 0b011000;
1882let Inst{13-13} = 0b0;
1883let Inst{31-21} = 0b11010010000;
1884}
1885def A2_vcmphgt : HInst<
1886(outs PredRegs:$Pd4),
1887(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1888"$Pd4 = vcmph.gt($Rss32,$Rtt32)",
1889tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1890let Inst{7-2} = 0b100000;
1891let Inst{13-13} = 0b0;
1892let Inst{31-21} = 0b11010010000;
1893}
1894def A2_vcmphgtu : HInst<
1895(outs PredRegs:$Pd4),
1896(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1897"$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
1898tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1899let Inst{7-2} = 0b101000;
1900let Inst{13-13} = 0b0;
1901let Inst{31-21} = 0b11010010000;
1902}
1903def A2_vcmpweq : HInst<
1904(outs PredRegs:$Pd4),
1905(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1906"$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
1907tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1908let Inst{7-2} = 0b000000;
1909let Inst{13-13} = 0b0;
1910let Inst{31-21} = 0b11010010000;
1911}
1912def A2_vcmpwgt : HInst<
1913(outs PredRegs:$Pd4),
1914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1915"$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
1916tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1917let Inst{7-2} = 0b001000;
1918let Inst{13-13} = 0b0;
1919let Inst{31-21} = 0b11010010000;
1920}
1921def A2_vcmpwgtu : HInst<
1922(outs PredRegs:$Pd4),
1923(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1924"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
1925tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1926let Inst{7-2} = 0b010000;
1927let Inst{13-13} = 0b0;
1928let Inst{31-21} = 0b11010010000;
1929}
1930def A2_vconj : HInst<
1931(outs DoubleRegs:$Rdd32),
1932(ins DoubleRegs:$Rss32),
1933"$Rdd32 = vconj($Rss32):sat",
1934tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1935let Inst{13-5} = 0b000000111;
1936let Inst{31-21} = 0b10000000100;
1937let prefersSlot3 = 1;
1938let Defs = [USR_OVF];
1939}
1940def A2_vmaxb : HInst<
1941(outs DoubleRegs:$Rdd32),
1942(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1943"$Rdd32 = vmaxb($Rtt32,$Rss32)",
1944tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1945let Inst{7-5} = 0b110;
1946let Inst{13-13} = 0b0;
1947let Inst{31-21} = 0b11010011110;
1948let prefersSlot3 = 1;
1949}
1950def A2_vmaxh : HInst<
1951(outs DoubleRegs:$Rdd32),
1952(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1953"$Rdd32 = vmaxh($Rtt32,$Rss32)",
1954tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1955let Inst{7-5} = 0b001;
1956let Inst{13-13} = 0b0;
1957let Inst{31-21} = 0b11010011110;
1958let prefersSlot3 = 1;
1959}
1960def A2_vmaxub : HInst<
1961(outs DoubleRegs:$Rdd32),
1962(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1963"$Rdd32 = vmaxub($Rtt32,$Rss32)",
1964tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1965let Inst{7-5} = 0b000;
1966let Inst{13-13} = 0b0;
1967let Inst{31-21} = 0b11010011110;
1968let prefersSlot3 = 1;
1969}
1970def A2_vmaxuh : HInst<
1971(outs DoubleRegs:$Rdd32),
1972(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1973"$Rdd32 = vmaxuh($Rtt32,$Rss32)",
1974tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1975let Inst{7-5} = 0b010;
1976let Inst{13-13} = 0b0;
1977let Inst{31-21} = 0b11010011110;
1978let prefersSlot3 = 1;
1979}
1980def A2_vmaxuw : HInst<
1981(outs DoubleRegs:$Rdd32),
1982(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1983"$Rdd32 = vmaxuw($Rtt32,$Rss32)",
1984tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1985let Inst{7-5} = 0b101;
1986let Inst{13-13} = 0b0;
1987let Inst{31-21} = 0b11010011101;
1988let prefersSlot3 = 1;
1989}
1990def A2_vmaxw : HInst<
1991(outs DoubleRegs:$Rdd32),
1992(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1993"$Rdd32 = vmaxw($Rtt32,$Rss32)",
1994tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1995let Inst{7-5} = 0b011;
1996let Inst{13-13} = 0b0;
1997let Inst{31-21} = 0b11010011110;
1998let prefersSlot3 = 1;
1999}
2000def A2_vminb : HInst<
2001(outs DoubleRegs:$Rdd32),
2002(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2003"$Rdd32 = vminb($Rtt32,$Rss32)",
2004tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2005let Inst{7-5} = 0b111;
2006let Inst{13-13} = 0b0;
2007let Inst{31-21} = 0b11010011110;
2008let prefersSlot3 = 1;
2009}
2010def A2_vminh : HInst<
2011(outs DoubleRegs:$Rdd32),
2012(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2013"$Rdd32 = vminh($Rtt32,$Rss32)",
2014tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2015let Inst{7-5} = 0b001;
2016let Inst{13-13} = 0b0;
2017let Inst{31-21} = 0b11010011101;
2018let prefersSlot3 = 1;
2019}
2020def A2_vminub : HInst<
2021(outs DoubleRegs:$Rdd32),
2022(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2023"$Rdd32 = vminub($Rtt32,$Rss32)",
2024tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2025let Inst{7-5} = 0b000;
2026let Inst{13-13} = 0b0;
2027let Inst{31-21} = 0b11010011101;
2028let prefersSlot3 = 1;
2029}
2030def A2_vminuh : HInst<
2031(outs DoubleRegs:$Rdd32),
2032(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2033"$Rdd32 = vminuh($Rtt32,$Rss32)",
2034tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2035let Inst{7-5} = 0b010;
2036let Inst{13-13} = 0b0;
2037let Inst{31-21} = 0b11010011101;
2038let prefersSlot3 = 1;
2039}
2040def A2_vminuw : HInst<
2041(outs DoubleRegs:$Rdd32),
2042(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2043"$Rdd32 = vminuw($Rtt32,$Rss32)",
2044tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2045let Inst{7-5} = 0b100;
2046let Inst{13-13} = 0b0;
2047let Inst{31-21} = 0b11010011101;
2048let prefersSlot3 = 1;
2049}
2050def A2_vminw : HInst<
2051(outs DoubleRegs:$Rdd32),
2052(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2053"$Rdd32 = vminw($Rtt32,$Rss32)",
2054tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2055let Inst{7-5} = 0b011;
2056let Inst{13-13} = 0b0;
2057let Inst{31-21} = 0b11010011101;
2058let prefersSlot3 = 1;
2059}
2060def A2_vnavgh : HInst<
2061(outs DoubleRegs:$Rdd32),
2062(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2063"$Rdd32 = vnavgh($Rtt32,$Rss32)",
2064tc_f098b237, TypeALU64>, Enc_ea23e4 {
2065let Inst{7-5} = 0b000;
2066let Inst{13-13} = 0b0;
2067let Inst{31-21} = 0b11010011100;
2068let prefersSlot3 = 1;
2069}
2070def A2_vnavghcr : HInst<
2071(outs DoubleRegs:$Rdd32),
2072(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2073"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
2074tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2075let Inst{7-5} = 0b010;
2076let Inst{13-13} = 0b0;
2077let Inst{31-21} = 0b11010011100;
2078let prefersSlot3 = 1;
2079let Defs = [USR_OVF];
2080}
2081def A2_vnavghr : HInst<
2082(outs DoubleRegs:$Rdd32),
2083(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2084"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
2085tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2086let Inst{7-5} = 0b001;
2087let Inst{13-13} = 0b0;
2088let Inst{31-21} = 0b11010011100;
2089let prefersSlot3 = 1;
2090let Defs = [USR_OVF];
2091}
2092def A2_vnavgw : HInst<
2093(outs DoubleRegs:$Rdd32),
2094(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2095"$Rdd32 = vnavgw($Rtt32,$Rss32)",
2096tc_f098b237, TypeALU64>, Enc_ea23e4 {
2097let Inst{7-5} = 0b011;
2098let Inst{13-13} = 0b0;
2099let Inst{31-21} = 0b11010011100;
2100let prefersSlot3 = 1;
2101}
2102def A2_vnavgwcr : HInst<
2103(outs DoubleRegs:$Rdd32),
2104(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2105"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
2106tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2107let Inst{7-5} = 0b110;
2108let Inst{13-13} = 0b0;
2109let Inst{31-21} = 0b11010011100;
2110let prefersSlot3 = 1;
2111let Defs = [USR_OVF];
2112}
2113def A2_vnavgwr : HInst<
2114(outs DoubleRegs:$Rdd32),
2115(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2116"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
2117tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2118let Inst{7-5} = 0b100;
2119let Inst{13-13} = 0b0;
2120let Inst{31-21} = 0b11010011100;
2121let prefersSlot3 = 1;
2122let Defs = [USR_OVF];
2123}
2124def A2_vraddub : HInst<
2125(outs DoubleRegs:$Rdd32),
2126(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2127"$Rdd32 = vraddub($Rss32,$Rtt32)",
2128tc_c21d7447, TypeM>, Enc_a56825 {
2129let Inst{7-5} = 0b001;
2130let Inst{13-13} = 0b0;
2131let Inst{31-21} = 0b11101000010;
2132let prefersSlot3 = 1;
2133}
2134def A2_vraddub_acc : HInst<
2135(outs DoubleRegs:$Rxx32),
2136(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2137"$Rxx32 += vraddub($Rss32,$Rtt32)",
2138tc_7f8ae742, TypeM>, Enc_88c16c {
2139let Inst{7-5} = 0b001;
2140let Inst{13-13} = 0b0;
2141let Inst{31-21} = 0b11101010010;
2142let prefersSlot3 = 1;
2143let Constraints = "$Rxx32 = $Rxx32in";
2144}
2145def A2_vrsadub : HInst<
2146(outs DoubleRegs:$Rdd32),
2147(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2148"$Rdd32 = vrsadub($Rss32,$Rtt32)",
2149tc_c21d7447, TypeM>, Enc_a56825 {
2150let Inst{7-5} = 0b010;
2151let Inst{13-13} = 0b0;
2152let Inst{31-21} = 0b11101000010;
2153let prefersSlot3 = 1;
2154}
2155def A2_vrsadub_acc : HInst<
2156(outs DoubleRegs:$Rxx32),
2157(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2158"$Rxx32 += vrsadub($Rss32,$Rtt32)",
2159tc_7f8ae742, TypeM>, Enc_88c16c {
2160let Inst{7-5} = 0b010;
2161let Inst{13-13} = 0b0;
2162let Inst{31-21} = 0b11101010010;
2163let prefersSlot3 = 1;
2164let Constraints = "$Rxx32 = $Rxx32in";
2165}
2166def A2_vsubb_map : HInst<
2167(outs DoubleRegs:$Rdd32),
2168(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2169"$Rdd32 = vsubb($Rss32,$Rtt32)",
2170tc_5da50c4b, TypeMAPPING> {
2171let isPseudo = 1;
2172let isCodeGenOnly = 1;
2173}
2174def A2_vsubh : HInst<
2175(outs DoubleRegs:$Rdd32),
2176(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2177"$Rdd32 = vsubh($Rtt32,$Rss32)",
2178tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2179let Inst{7-5} = 0b010;
2180let Inst{13-13} = 0b0;
2181let Inst{31-21} = 0b11010011001;
2182}
2183def A2_vsubhs : HInst<
2184(outs DoubleRegs:$Rdd32),
2185(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2186"$Rdd32 = vsubh($Rtt32,$Rss32):sat",
2187tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2188let Inst{7-5} = 0b011;
2189let Inst{13-13} = 0b0;
2190let Inst{31-21} = 0b11010011001;
2191let prefersSlot3 = 1;
2192let Defs = [USR_OVF];
2193}
2194def A2_vsubub : HInst<
2195(outs DoubleRegs:$Rdd32),
2196(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2197"$Rdd32 = vsubub($Rtt32,$Rss32)",
2198tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2199let Inst{7-5} = 0b000;
2200let Inst{13-13} = 0b0;
2201let Inst{31-21} = 0b11010011001;
2202}
2203def A2_vsububs : HInst<
2204(outs DoubleRegs:$Rdd32),
2205(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2206"$Rdd32 = vsubub($Rtt32,$Rss32):sat",
2207tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2208let Inst{7-5} = 0b001;
2209let Inst{13-13} = 0b0;
2210let Inst{31-21} = 0b11010011001;
2211let prefersSlot3 = 1;
2212let Defs = [USR_OVF];
2213}
2214def A2_vsubuhs : HInst<
2215(outs DoubleRegs:$Rdd32),
2216(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2217"$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
2218tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2219let Inst{7-5} = 0b100;
2220let Inst{13-13} = 0b0;
2221let Inst{31-21} = 0b11010011001;
2222let prefersSlot3 = 1;
2223let Defs = [USR_OVF];
2224}
2225def A2_vsubw : HInst<
2226(outs DoubleRegs:$Rdd32),
2227(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2228"$Rdd32 = vsubw($Rtt32,$Rss32)",
2229tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2230let Inst{7-5} = 0b101;
2231let Inst{13-13} = 0b0;
2232let Inst{31-21} = 0b11010011001;
2233}
2234def A2_vsubws : HInst<
2235(outs DoubleRegs:$Rdd32),
2236(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2237"$Rdd32 = vsubw($Rtt32,$Rss32):sat",
2238tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2239let Inst{7-5} = 0b110;
2240let Inst{13-13} = 0b0;
2241let Inst{31-21} = 0b11010011001;
2242let prefersSlot3 = 1;
2243let Defs = [USR_OVF];
2244}
2245def A2_xor : HInst<
2246(outs IntRegs:$Rd32),
2247(ins IntRegs:$Rs32, IntRegs:$Rt32),
2248"$Rd32 = xor($Rs32,$Rt32)",
2249tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
2250let Inst{7-5} = 0b000;
2251let Inst{13-13} = 0b0;
2252let Inst{31-21} = 0b11110001011;
2253let hasNewValue = 1;
2254let opNewValue = 0;
2255let BaseOpcode = "A2_xor";
2256let InputType = "reg";
2257let isCommutable = 1;
2258let isPredicable = 1;
2259}
2260def A2_xorp : HInst<
2261(outs DoubleRegs:$Rdd32),
2262(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2263"$Rdd32 = xor($Rss32,$Rtt32)",
2264tc_5da50c4b, TypeALU64>, Enc_a56825 {
2265let Inst{7-5} = 0b100;
2266let Inst{13-13} = 0b0;
2267let Inst{31-21} = 0b11010011111;
2268let isCommutable = 1;
2269}
2270def A2_zxtb : HInst<
2271(outs IntRegs:$Rd32),
2272(ins IntRegs:$Rs32),
2273"$Rd32 = zxtb($Rs32)",
2274tc_713b66bf, TypeALU32_2op>, PredNewRel {
2275let hasNewValue = 1;
2276let opNewValue = 0;
2277let BaseOpcode = "A2_zxtb";
2278let isPredicable = 1;
2279let isPseudo = 1;
2280let isCodeGenOnly = 1;
2281}
2282def A2_zxth : HInst<
2283(outs IntRegs:$Rd32),
2284(ins IntRegs:$Rs32),
2285"$Rd32 = zxth($Rs32)",
2286tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
2287let Inst{13-5} = 0b000000000;
2288let Inst{31-21} = 0b01110000110;
2289let hasNewValue = 1;
2290let opNewValue = 0;
2291let BaseOpcode = "A2_zxth";
2292let isPredicable = 1;
2293}
2294def A4_addp_c : HInst<
2295(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
2296(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
2297"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
2298tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
2299let Inst{7-7} = 0b0;
2300let Inst{13-13} = 0b0;
2301let Inst{31-21} = 0b11000010110;
2302let isPredicateLate = 1;
2303let Constraints = "$Px4 = $Px4in";
2304}
2305def A4_andn : HInst<
2306(outs IntRegs:$Rd32),
2307(ins IntRegs:$Rt32, IntRegs:$Rs32),
2308"$Rd32 = and($Rt32,~$Rs32)",
2309tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2310let Inst{7-5} = 0b000;
2311let Inst{13-13} = 0b0;
2312let Inst{31-21} = 0b11110001100;
2313let hasNewValue = 1;
2314let opNewValue = 0;
2315let InputType = "reg";
2316}
2317def A4_andnp : HInst<
2318(outs DoubleRegs:$Rdd32),
2319(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2320"$Rdd32 = and($Rtt32,~$Rss32)",
2321tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2322let Inst{7-5} = 0b001;
2323let Inst{13-13} = 0b0;
2324let Inst{31-21} = 0b11010011111;
2325}
2326def A4_bitsplit : HInst<
2327(outs DoubleRegs:$Rdd32),
2328(ins IntRegs:$Rs32, IntRegs:$Rt32),
2329"$Rdd32 = bitsplit($Rs32,$Rt32)",
2330tc_f34c1c21, TypeALU64>, Enc_be32a5 {
2331let Inst{7-5} = 0b000;
2332let Inst{13-13} = 0b0;
2333let Inst{31-21} = 0b11010100001;
2334let prefersSlot3 = 1;
2335}
2336def A4_bitspliti : HInst<
2337(outs DoubleRegs:$Rdd32),
2338(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2339"$Rdd32 = bitsplit($Rs32,#$Ii)",
2340tc_f34c1c21, TypeS_2op>, Enc_311abd {
2341let Inst{7-5} = 0b100;
2342let Inst{13-13} = 0b0;
2343let Inst{31-21} = 0b10001000110;
2344let prefersSlot3 = 1;
2345}
2346def A4_boundscheck : HInst<
2347(outs PredRegs:$Pd4),
2348(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
2349"$Pd4 = boundscheck($Rs32,$Rtt32)",
2350tc_4a55d03c, TypeALU64> {
2351let isPseudo = 1;
2352}
2353def A4_boundscheck_hi : HInst<
2354(outs PredRegs:$Pd4),
2355(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2356"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
2357tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2358let Inst{7-2} = 0b101000;
2359let Inst{13-13} = 0b1;
2360let Inst{31-21} = 0b11010010000;
2361}
2362def A4_boundscheck_lo : HInst<
2363(outs PredRegs:$Pd4),
2364(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2365"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
2366tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2367let Inst{7-2} = 0b100000;
2368let Inst{13-13} = 0b1;
2369let Inst{31-21} = 0b11010010000;
2370}
2371def A4_cmpbeq : HInst<
2372(outs PredRegs:$Pd4),
2373(ins IntRegs:$Rs32, IntRegs:$Rt32),
2374"$Pd4 = cmpb.eq($Rs32,$Rt32)",
2375tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2376let Inst{7-2} = 0b110000;
2377let Inst{13-13} = 0b0;
2378let Inst{31-21} = 0b11000111110;
2379let CextOpcode = "A4_cmpbeq";
2380let InputType = "reg";
2381let isCommutable = 1;
2382let isCompare = 1;
2383}
2384def A4_cmpbeqi : HInst<
2385(outs PredRegs:$Pd4),
2386(ins IntRegs:$Rs32, u8_0Imm:$Ii),
2387"$Pd4 = cmpb.eq($Rs32,#$Ii)",
2388tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2389let Inst{4-2} = 0b000;
2390let Inst{13-13} = 0b0;
2391let Inst{31-21} = 0b11011101000;
2392let CextOpcode = "A4_cmpbeq";
2393let InputType = "imm";
2394let isCommutable = 1;
2395let isCompare = 1;
2396}
2397def A4_cmpbgt : HInst<
2398(outs PredRegs:$Pd4),
2399(ins IntRegs:$Rs32, IntRegs:$Rt32),
2400"$Pd4 = cmpb.gt($Rs32,$Rt32)",
2401tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2402let Inst{7-2} = 0b010000;
2403let Inst{13-13} = 0b0;
2404let Inst{31-21} = 0b11000111110;
2405let CextOpcode = "A4_cmpbgt";
2406let InputType = "reg";
2407let isCompare = 1;
2408}
2409def A4_cmpbgti : HInst<
2410(outs PredRegs:$Pd4),
2411(ins IntRegs:$Rs32, s8_0Imm:$Ii),
2412"$Pd4 = cmpb.gt($Rs32,#$Ii)",
2413tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2414let Inst{4-2} = 0b000;
2415let Inst{13-13} = 0b0;
2416let Inst{31-21} = 0b11011101001;
2417let CextOpcode = "A4_cmpbgt";
2418let InputType = "imm";
2419let isCompare = 1;
2420}
2421def A4_cmpbgtu : HInst<
2422(outs PredRegs:$Pd4),
2423(ins IntRegs:$Rs32, IntRegs:$Rt32),
2424"$Pd4 = cmpb.gtu($Rs32,$Rt32)",
2425tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2426let Inst{7-2} = 0b111000;
2427let Inst{13-13} = 0b0;
2428let Inst{31-21} = 0b11000111110;
2429let CextOpcode = "A4_cmpbgtu";
2430let InputType = "reg";
2431let isCompare = 1;
2432}
2433def A4_cmpbgtui : HInst<
2434(outs PredRegs:$Pd4),
2435(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2436"$Pd4 = cmpb.gtu($Rs32,#$Ii)",
2437tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2438let Inst{4-2} = 0b000;
2439let Inst{13-12} = 0b00;
2440let Inst{31-21} = 0b11011101010;
2441let CextOpcode = "A4_cmpbgtu";
2442let InputType = "imm";
2443let isCompare = 1;
2444let isExtendable = 1;
2445let opExtendable = 2;
2446let isExtentSigned = 0;
2447let opExtentBits = 7;
2448let opExtentAlign = 0;
2449}
2450def A4_cmpheq : HInst<
2451(outs PredRegs:$Pd4),
2452(ins IntRegs:$Rs32, IntRegs:$Rt32),
2453"$Pd4 = cmph.eq($Rs32,$Rt32)",
2454tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2455let Inst{7-2} = 0b011000;
2456let Inst{13-13} = 0b0;
2457let Inst{31-21} = 0b11000111110;
2458let CextOpcode = "A4_cmpheq";
2459let InputType = "reg";
2460let isCommutable = 1;
2461let isCompare = 1;
2462}
2463def A4_cmpheqi : HInst<
2464(outs PredRegs:$Pd4),
2465(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2466"$Pd4 = cmph.eq($Rs32,#$Ii)",
2467tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2468let Inst{4-2} = 0b010;
2469let Inst{13-13} = 0b0;
2470let Inst{31-21} = 0b11011101000;
2471let CextOpcode = "A4_cmpheq";
2472let InputType = "imm";
2473let isCommutable = 1;
2474let isCompare = 1;
2475let isExtendable = 1;
2476let opExtendable = 2;
2477let isExtentSigned = 1;
2478let opExtentBits = 8;
2479let opExtentAlign = 0;
2480}
2481def A4_cmphgt : HInst<
2482(outs PredRegs:$Pd4),
2483(ins IntRegs:$Rs32, IntRegs:$Rt32),
2484"$Pd4 = cmph.gt($Rs32,$Rt32)",
2485tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2486let Inst{7-2} = 0b100000;
2487let Inst{13-13} = 0b0;
2488let Inst{31-21} = 0b11000111110;
2489let CextOpcode = "A4_cmphgt";
2490let InputType = "reg";
2491let isCompare = 1;
2492}
2493def A4_cmphgti : HInst<
2494(outs PredRegs:$Pd4),
2495(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2496"$Pd4 = cmph.gt($Rs32,#$Ii)",
2497tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2498let Inst{4-2} = 0b010;
2499let Inst{13-13} = 0b0;
2500let Inst{31-21} = 0b11011101001;
2501let CextOpcode = "A4_cmphgt";
2502let InputType = "imm";
2503let isCompare = 1;
2504let isExtendable = 1;
2505let opExtendable = 2;
2506let isExtentSigned = 1;
2507let opExtentBits = 8;
2508let opExtentAlign = 0;
2509}
2510def A4_cmphgtu : HInst<
2511(outs PredRegs:$Pd4),
2512(ins IntRegs:$Rs32, IntRegs:$Rt32),
2513"$Pd4 = cmph.gtu($Rs32,$Rt32)",
2514tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2515let Inst{7-2} = 0b101000;
2516let Inst{13-13} = 0b0;
2517let Inst{31-21} = 0b11000111110;
2518let CextOpcode = "A4_cmphgtu";
2519let InputType = "reg";
2520let isCompare = 1;
2521}
2522def A4_cmphgtui : HInst<
2523(outs PredRegs:$Pd4),
2524(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2525"$Pd4 = cmph.gtu($Rs32,#$Ii)",
2526tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2527let Inst{4-2} = 0b010;
2528let Inst{13-12} = 0b00;
2529let Inst{31-21} = 0b11011101010;
2530let CextOpcode = "A4_cmphgtu";
2531let InputType = "imm";
2532let isCompare = 1;
2533let isExtendable = 1;
2534let opExtendable = 2;
2535let isExtentSigned = 0;
2536let opExtentBits = 7;
2537let opExtentAlign = 0;
2538}
2539def A4_combineii : HInst<
2540(outs DoubleRegs:$Rdd32),
2541(ins s8_0Imm:$Ii, u32_0Imm:$II),
2542"$Rdd32 = combine(#$Ii,#$II)",
2543tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 {
2544let Inst{31-21} = 0b01111100100;
2545let isExtendable = 1;
2546let opExtendable = 2;
2547let isExtentSigned = 0;
2548let opExtentBits = 6;
2549let opExtentAlign = 0;
2550}
2551def A4_combineir : HInst<
2552(outs DoubleRegs:$Rdd32),
2553(ins s32_0Imm:$Ii, IntRegs:$Rs32),
2554"$Rdd32 = combine(#$Ii,$Rs32)",
2555tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2556let Inst{13-13} = 0b1;
2557let Inst{31-21} = 0b01110011001;
2558let isExtendable = 1;
2559let opExtendable = 1;
2560let isExtentSigned = 1;
2561let opExtentBits = 8;
2562let opExtentAlign = 0;
2563}
2564def A4_combineri : HInst<
2565(outs DoubleRegs:$Rdd32),
2566(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2567"$Rdd32 = combine($Rs32,#$Ii)",
2568tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2569let Inst{13-13} = 0b1;
2570let Inst{31-21} = 0b01110011000;
2571let isExtendable = 1;
2572let opExtendable = 2;
2573let isExtentSigned = 1;
2574let opExtentBits = 8;
2575let opExtentAlign = 0;
2576}
2577def A4_cround_ri : HInst<
2578(outs IntRegs:$Rd32),
2579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2580"$Rd32 = cround($Rs32,#$Ii)",
2581tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
2582let Inst{7-5} = 0b000;
2583let Inst{13-13} = 0b0;
2584let Inst{31-21} = 0b10001100111;
2585let hasNewValue = 1;
2586let opNewValue = 0;
2587let prefersSlot3 = 1;
2588}
2589def A4_cround_rr : HInst<
2590(outs IntRegs:$Rd32),
2591(ins IntRegs:$Rs32, IntRegs:$Rt32),
2592"$Rd32 = cround($Rs32,$Rt32)",
2593tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
2594let Inst{7-5} = 0b000;
2595let Inst{13-13} = 0b0;
2596let Inst{31-21} = 0b11000110110;
2597let hasNewValue = 1;
2598let opNewValue = 0;
2599let prefersSlot3 = 1;
2600}
2601def A4_ext : HInst<
2602(outs),
2603(ins u26_6Imm:$Ii),
2604"immext(#$Ii)",
2605tc_112d30d6, TypeEXTENDER>, Enc_2b518f {
2606let Inst{31-28} = 0b0000;
2607}
2608def A4_modwrapu : HInst<
2609(outs IntRegs:$Rd32),
2610(ins IntRegs:$Rs32, IntRegs:$Rt32),
2611"$Rd32 = modwrap($Rs32,$Rt32)",
2612tc_8a825db2, TypeALU64>, Enc_5ab2be {
2613let Inst{7-5} = 0b111;
2614let Inst{13-13} = 0b0;
2615let Inst{31-21} = 0b11010011111;
2616let hasNewValue = 1;
2617let opNewValue = 0;
2618let prefersSlot3 = 1;
2619}
2620def A4_orn : HInst<
2621(outs IntRegs:$Rd32),
2622(ins IntRegs:$Rt32, IntRegs:$Rs32),
2623"$Rd32 = or($Rt32,~$Rs32)",
2624tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2625let Inst{7-5} = 0b000;
2626let Inst{13-13} = 0b0;
2627let Inst{31-21} = 0b11110001101;
2628let hasNewValue = 1;
2629let opNewValue = 0;
2630let InputType = "reg";
2631}
2632def A4_ornp : HInst<
2633(outs DoubleRegs:$Rdd32),
2634(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2635"$Rdd32 = or($Rtt32,~$Rss32)",
2636tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2637let Inst{7-5} = 0b011;
2638let Inst{13-13} = 0b0;
2639let Inst{31-21} = 0b11010011111;
2640}
2641def A4_paslhf : HInst<
2642(outs IntRegs:$Rd32),
2643(ins PredRegs:$Pu4, IntRegs:$Rs32),
2644"if (!$Pu4) $Rd32 = aslh($Rs32)",
2645tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2646let Inst{7-5} = 0b000;
2647let Inst{13-10} = 0b1010;
2648let Inst{31-21} = 0b01110000000;
2649let isPredicated = 1;
2650let isPredicatedFalse = 1;
2651let hasNewValue = 1;
2652let opNewValue = 0;
2653let BaseOpcode = "A2_aslh";
2654}
2655def A4_paslhfnew : HInst<
2656(outs IntRegs:$Rd32),
2657(ins PredRegs:$Pu4, IntRegs:$Rs32),
2658"if (!$Pu4.new) $Rd32 = aslh($Rs32)",
2659tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2660let Inst{7-5} = 0b000;
2661let Inst{13-10} = 0b1011;
2662let Inst{31-21} = 0b01110000000;
2663let isPredicated = 1;
2664let isPredicatedFalse = 1;
2665let hasNewValue = 1;
2666let opNewValue = 0;
2667let isPredicatedNew = 1;
2668let BaseOpcode = "A2_aslh";
2669}
2670def A4_paslht : HInst<
2671(outs IntRegs:$Rd32),
2672(ins PredRegs:$Pu4, IntRegs:$Rs32),
2673"if ($Pu4) $Rd32 = aslh($Rs32)",
2674tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2675let Inst{7-5} = 0b000;
2676let Inst{13-10} = 0b1000;
2677let Inst{31-21} = 0b01110000000;
2678let isPredicated = 1;
2679let hasNewValue = 1;
2680let opNewValue = 0;
2681let BaseOpcode = "A2_aslh";
2682}
2683def A4_paslhtnew : HInst<
2684(outs IntRegs:$Rd32),
2685(ins PredRegs:$Pu4, IntRegs:$Rs32),
2686"if ($Pu4.new) $Rd32 = aslh($Rs32)",
2687tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2688let Inst{7-5} = 0b000;
2689let Inst{13-10} = 0b1001;
2690let Inst{31-21} = 0b01110000000;
2691let isPredicated = 1;
2692let hasNewValue = 1;
2693let opNewValue = 0;
2694let isPredicatedNew = 1;
2695let BaseOpcode = "A2_aslh";
2696}
2697def A4_pasrhf : HInst<
2698(outs IntRegs:$Rd32),
2699(ins PredRegs:$Pu4, IntRegs:$Rs32),
2700"if (!$Pu4) $Rd32 = asrh($Rs32)",
2701tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2702let Inst{7-5} = 0b000;
2703let Inst{13-10} = 0b1010;
2704let Inst{31-21} = 0b01110000001;
2705let isPredicated = 1;
2706let isPredicatedFalse = 1;
2707let hasNewValue = 1;
2708let opNewValue = 0;
2709let BaseOpcode = "A2_asrh";
2710}
2711def A4_pasrhfnew : HInst<
2712(outs IntRegs:$Rd32),
2713(ins PredRegs:$Pu4, IntRegs:$Rs32),
2714"if (!$Pu4.new) $Rd32 = asrh($Rs32)",
2715tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2716let Inst{7-5} = 0b000;
2717let Inst{13-10} = 0b1011;
2718let Inst{31-21} = 0b01110000001;
2719let isPredicated = 1;
2720let isPredicatedFalse = 1;
2721let hasNewValue = 1;
2722let opNewValue = 0;
2723let isPredicatedNew = 1;
2724let BaseOpcode = "A2_asrh";
2725}
2726def A4_pasrht : HInst<
2727(outs IntRegs:$Rd32),
2728(ins PredRegs:$Pu4, IntRegs:$Rs32),
2729"if ($Pu4) $Rd32 = asrh($Rs32)",
2730tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2731let Inst{7-5} = 0b000;
2732let Inst{13-10} = 0b1000;
2733let Inst{31-21} = 0b01110000001;
2734let isPredicated = 1;
2735let hasNewValue = 1;
2736let opNewValue = 0;
2737let BaseOpcode = "A2_asrh";
2738}
2739def A4_pasrhtnew : HInst<
2740(outs IntRegs:$Rd32),
2741(ins PredRegs:$Pu4, IntRegs:$Rs32),
2742"if ($Pu4.new) $Rd32 = asrh($Rs32)",
2743tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2744let Inst{7-5} = 0b000;
2745let Inst{13-10} = 0b1001;
2746let Inst{31-21} = 0b01110000001;
2747let isPredicated = 1;
2748let hasNewValue = 1;
2749let opNewValue = 0;
2750let isPredicatedNew = 1;
2751let BaseOpcode = "A2_asrh";
2752}
2753def A4_psxtbf : HInst<
2754(outs IntRegs:$Rd32),
2755(ins PredRegs:$Pu4, IntRegs:$Rs32),
2756"if (!$Pu4) $Rd32 = sxtb($Rs32)",
2757tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2758let Inst{7-5} = 0b000;
2759let Inst{13-10} = 0b1010;
2760let Inst{31-21} = 0b01110000101;
2761let isPredicated = 1;
2762let isPredicatedFalse = 1;
2763let hasNewValue = 1;
2764let opNewValue = 0;
2765let BaseOpcode = "A2_sxtb";
2766}
2767def A4_psxtbfnew : HInst<
2768(outs IntRegs:$Rd32),
2769(ins PredRegs:$Pu4, IntRegs:$Rs32),
2770"if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
2771tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2772let Inst{7-5} = 0b000;
2773let Inst{13-10} = 0b1011;
2774let Inst{31-21} = 0b01110000101;
2775let isPredicated = 1;
2776let isPredicatedFalse = 1;
2777let hasNewValue = 1;
2778let opNewValue = 0;
2779let isPredicatedNew = 1;
2780let BaseOpcode = "A2_sxtb";
2781}
2782def A4_psxtbt : HInst<
2783(outs IntRegs:$Rd32),
2784(ins PredRegs:$Pu4, IntRegs:$Rs32),
2785"if ($Pu4) $Rd32 = sxtb($Rs32)",
2786tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2787let Inst{7-5} = 0b000;
2788let Inst{13-10} = 0b1000;
2789let Inst{31-21} = 0b01110000101;
2790let isPredicated = 1;
2791let hasNewValue = 1;
2792let opNewValue = 0;
2793let BaseOpcode = "A2_sxtb";
2794}
2795def A4_psxtbtnew : HInst<
2796(outs IntRegs:$Rd32),
2797(ins PredRegs:$Pu4, IntRegs:$Rs32),
2798"if ($Pu4.new) $Rd32 = sxtb($Rs32)",
2799tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2800let Inst{7-5} = 0b000;
2801let Inst{13-10} = 0b1001;
2802let Inst{31-21} = 0b01110000101;
2803let isPredicated = 1;
2804let hasNewValue = 1;
2805let opNewValue = 0;
2806let isPredicatedNew = 1;
2807let BaseOpcode = "A2_sxtb";
2808}
2809def A4_psxthf : HInst<
2810(outs IntRegs:$Rd32),
2811(ins PredRegs:$Pu4, IntRegs:$Rs32),
2812"if (!$Pu4) $Rd32 = sxth($Rs32)",
2813tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2814let Inst{7-5} = 0b000;
2815let Inst{13-10} = 0b1010;
2816let Inst{31-21} = 0b01110000111;
2817let isPredicated = 1;
2818let isPredicatedFalse = 1;
2819let hasNewValue = 1;
2820let opNewValue = 0;
2821let BaseOpcode = "A2_sxth";
2822}
2823def A4_psxthfnew : HInst<
2824(outs IntRegs:$Rd32),
2825(ins PredRegs:$Pu4, IntRegs:$Rs32),
2826"if (!$Pu4.new) $Rd32 = sxth($Rs32)",
2827tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2828let Inst{7-5} = 0b000;
2829let Inst{13-10} = 0b1011;
2830let Inst{31-21} = 0b01110000111;
2831let isPredicated = 1;
2832let isPredicatedFalse = 1;
2833let hasNewValue = 1;
2834let opNewValue = 0;
2835let isPredicatedNew = 1;
2836let BaseOpcode = "A2_sxth";
2837}
2838def A4_psxtht : HInst<
2839(outs IntRegs:$Rd32),
2840(ins PredRegs:$Pu4, IntRegs:$Rs32),
2841"if ($Pu4) $Rd32 = sxth($Rs32)",
2842tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2843let Inst{7-5} = 0b000;
2844let Inst{13-10} = 0b1000;
2845let Inst{31-21} = 0b01110000111;
2846let isPredicated = 1;
2847let hasNewValue = 1;
2848let opNewValue = 0;
2849let BaseOpcode = "A2_sxth";
2850}
2851def A4_psxthtnew : HInst<
2852(outs IntRegs:$Rd32),
2853(ins PredRegs:$Pu4, IntRegs:$Rs32),
2854"if ($Pu4.new) $Rd32 = sxth($Rs32)",
2855tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2856let Inst{7-5} = 0b000;
2857let Inst{13-10} = 0b1001;
2858let Inst{31-21} = 0b01110000111;
2859let isPredicated = 1;
2860let hasNewValue = 1;
2861let opNewValue = 0;
2862let isPredicatedNew = 1;
2863let BaseOpcode = "A2_sxth";
2864}
2865def A4_pzxtbf : HInst<
2866(outs IntRegs:$Rd32),
2867(ins PredRegs:$Pu4, IntRegs:$Rs32),
2868"if (!$Pu4) $Rd32 = zxtb($Rs32)",
2869tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2870let Inst{7-5} = 0b000;
2871let Inst{13-10} = 0b1010;
2872let Inst{31-21} = 0b01110000100;
2873let isPredicated = 1;
2874let isPredicatedFalse = 1;
2875let hasNewValue = 1;
2876let opNewValue = 0;
2877let BaseOpcode = "A2_zxtb";
2878}
2879def A4_pzxtbfnew : HInst<
2880(outs IntRegs:$Rd32),
2881(ins PredRegs:$Pu4, IntRegs:$Rs32),
2882"if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
2883tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2884let Inst{7-5} = 0b000;
2885let Inst{13-10} = 0b1011;
2886let Inst{31-21} = 0b01110000100;
2887let isPredicated = 1;
2888let isPredicatedFalse = 1;
2889let hasNewValue = 1;
2890let opNewValue = 0;
2891let isPredicatedNew = 1;
2892let BaseOpcode = "A2_zxtb";
2893}
2894def A4_pzxtbt : HInst<
2895(outs IntRegs:$Rd32),
2896(ins PredRegs:$Pu4, IntRegs:$Rs32),
2897"if ($Pu4) $Rd32 = zxtb($Rs32)",
2898tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2899let Inst{7-5} = 0b000;
2900let Inst{13-10} = 0b1000;
2901let Inst{31-21} = 0b01110000100;
2902let isPredicated = 1;
2903let hasNewValue = 1;
2904let opNewValue = 0;
2905let BaseOpcode = "A2_zxtb";
2906}
2907def A4_pzxtbtnew : HInst<
2908(outs IntRegs:$Rd32),
2909(ins PredRegs:$Pu4, IntRegs:$Rs32),
2910"if ($Pu4.new) $Rd32 = zxtb($Rs32)",
2911tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2912let Inst{7-5} = 0b000;
2913let Inst{13-10} = 0b1001;
2914let Inst{31-21} = 0b01110000100;
2915let isPredicated = 1;
2916let hasNewValue = 1;
2917let opNewValue = 0;
2918let isPredicatedNew = 1;
2919let BaseOpcode = "A2_zxtb";
2920}
2921def A4_pzxthf : HInst<
2922(outs IntRegs:$Rd32),
2923(ins PredRegs:$Pu4, IntRegs:$Rs32),
2924"if (!$Pu4) $Rd32 = zxth($Rs32)",
2925tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2926let Inst{7-5} = 0b000;
2927let Inst{13-10} = 0b1010;
2928let Inst{31-21} = 0b01110000110;
2929let isPredicated = 1;
2930let isPredicatedFalse = 1;
2931let hasNewValue = 1;
2932let opNewValue = 0;
2933let BaseOpcode = "A2_zxth";
2934}
2935def A4_pzxthfnew : HInst<
2936(outs IntRegs:$Rd32),
2937(ins PredRegs:$Pu4, IntRegs:$Rs32),
2938"if (!$Pu4.new) $Rd32 = zxth($Rs32)",
2939tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2940let Inst{7-5} = 0b000;
2941let Inst{13-10} = 0b1011;
2942let Inst{31-21} = 0b01110000110;
2943let isPredicated = 1;
2944let isPredicatedFalse = 1;
2945let hasNewValue = 1;
2946let opNewValue = 0;
2947let isPredicatedNew = 1;
2948let BaseOpcode = "A2_zxth";
2949}
2950def A4_pzxtht : HInst<
2951(outs IntRegs:$Rd32),
2952(ins PredRegs:$Pu4, IntRegs:$Rs32),
2953"if ($Pu4) $Rd32 = zxth($Rs32)",
2954tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2955let Inst{7-5} = 0b000;
2956let Inst{13-10} = 0b1000;
2957let Inst{31-21} = 0b01110000110;
2958let isPredicated = 1;
2959let hasNewValue = 1;
2960let opNewValue = 0;
2961let BaseOpcode = "A2_zxth";
2962}
2963def A4_pzxthtnew : HInst<
2964(outs IntRegs:$Rd32),
2965(ins PredRegs:$Pu4, IntRegs:$Rs32),
2966"if ($Pu4.new) $Rd32 = zxth($Rs32)",
2967tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2968let Inst{7-5} = 0b000;
2969let Inst{13-10} = 0b1001;
2970let Inst{31-21} = 0b01110000110;
2971let isPredicated = 1;
2972let hasNewValue = 1;
2973let opNewValue = 0;
2974let isPredicatedNew = 1;
2975let BaseOpcode = "A2_zxth";
2976}
2977def A4_rcmpeq : HInst<
2978(outs IntRegs:$Rd32),
2979(ins IntRegs:$Rs32, IntRegs:$Rt32),
2980"$Rd32 = cmp.eq($Rs32,$Rt32)",
2981tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
2982let Inst{7-5} = 0b000;
2983let Inst{13-13} = 0b0;
2984let Inst{31-21} = 0b11110011010;
2985let hasNewValue = 1;
2986let opNewValue = 0;
2987let CextOpcode = "A4_rcmpeq";
2988let InputType = "reg";
2989let isCommutable = 1;
2990}
2991def A4_rcmpeqi : HInst<
2992(outs IntRegs:$Rd32),
2993(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2994"$Rd32 = cmp.eq($Rs32,#$Ii)",
2995tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
2996let Inst{13-13} = 0b1;
2997let Inst{31-21} = 0b01110011010;
2998let hasNewValue = 1;
2999let opNewValue = 0;
3000let CextOpcode = "A4_rcmpeqi";
3001let InputType = "imm";
3002let isExtendable = 1;
3003let opExtendable = 2;
3004let isExtentSigned = 1;
3005let opExtentBits = 8;
3006let opExtentAlign = 0;
3007}
3008def A4_rcmpneq : HInst<
3009(outs IntRegs:$Rd32),
3010(ins IntRegs:$Rs32, IntRegs:$Rt32),
3011"$Rd32 = !cmp.eq($Rs32,$Rt32)",
3012tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
3013let Inst{7-5} = 0b000;
3014let Inst{13-13} = 0b0;
3015let Inst{31-21} = 0b11110011011;
3016let hasNewValue = 1;
3017let opNewValue = 0;
3018let CextOpcode = "A4_rcmpneq";
3019let InputType = "reg";
3020let isCommutable = 1;
3021}
3022def A4_rcmpneqi : HInst<
3023(outs IntRegs:$Rd32),
3024(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3025"$Rd32 = !cmp.eq($Rs32,#$Ii)",
3026tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
3027let Inst{13-13} = 0b1;
3028let Inst{31-21} = 0b01110011011;
3029let hasNewValue = 1;
3030let opNewValue = 0;
3031let CextOpcode = "A4_rcmpeqi";
3032let InputType = "imm";
3033let isExtendable = 1;
3034let opExtendable = 2;
3035let isExtentSigned = 1;
3036let opExtentBits = 8;
3037let opExtentAlign = 0;
3038}
3039def A4_round_ri : HInst<
3040(outs IntRegs:$Rd32),
3041(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3042"$Rd32 = round($Rs32,#$Ii)",
3043tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3044let Inst{7-5} = 0b100;
3045let Inst{13-13} = 0b0;
3046let Inst{31-21} = 0b10001100111;
3047let hasNewValue = 1;
3048let opNewValue = 0;
3049let prefersSlot3 = 1;
3050}
3051def A4_round_ri_sat : HInst<
3052(outs IntRegs:$Rd32),
3053(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3054"$Rd32 = round($Rs32,#$Ii):sat",
3055tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3056let Inst{7-5} = 0b110;
3057let Inst{13-13} = 0b0;
3058let Inst{31-21} = 0b10001100111;
3059let hasNewValue = 1;
3060let opNewValue = 0;
3061let prefersSlot3 = 1;
3062let Defs = [USR_OVF];
3063}
3064def A4_round_rr : HInst<
3065(outs IntRegs:$Rd32),
3066(ins IntRegs:$Rs32, IntRegs:$Rt32),
3067"$Rd32 = round($Rs32,$Rt32)",
3068tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3069let Inst{7-5} = 0b100;
3070let Inst{13-13} = 0b0;
3071let Inst{31-21} = 0b11000110110;
3072let hasNewValue = 1;
3073let opNewValue = 0;
3074let prefersSlot3 = 1;
3075}
3076def A4_round_rr_sat : HInst<
3077(outs IntRegs:$Rd32),
3078(ins IntRegs:$Rs32, IntRegs:$Rt32),
3079"$Rd32 = round($Rs32,$Rt32):sat",
3080tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3081let Inst{7-5} = 0b110;
3082let Inst{13-13} = 0b0;
3083let Inst{31-21} = 0b11000110110;
3084let hasNewValue = 1;
3085let opNewValue = 0;
3086let prefersSlot3 = 1;
3087let Defs = [USR_OVF];
3088}
3089def A4_subp_c : HInst<
3090(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
3091(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
3092"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
3093tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
3094let Inst{7-7} = 0b0;
3095let Inst{13-13} = 0b0;
3096let Inst{31-21} = 0b11000010111;
3097let isPredicateLate = 1;
3098let Constraints = "$Px4 = $Px4in";
3099}
3100def A4_tfrcpp : HInst<
3101(outs DoubleRegs:$Rdd32),
3102(ins CtrRegs64:$Css32),
3103"$Rdd32 = $Css32",
3104tc_7476d766, TypeCR>, Enc_667b39 {
3105let Inst{13-5} = 0b000000000;
3106let Inst{31-21} = 0b01101000000;
3107}
3108def A4_tfrpcp : HInst<
3109(outs CtrRegs64:$Cdd32),
3110(ins DoubleRegs:$Rss32),
3111"$Cdd32 = $Rss32",
3112tc_49fdfd4b, TypeCR>, Enc_0ed752 {
3113let Inst{13-5} = 0b000000000;
3114let Inst{31-21} = 0b01100011001;
3115}
3116def A4_tlbmatch : HInst<
3117(outs PredRegs:$Pd4),
3118(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3119"$Pd4 = tlbmatch($Rss32,$Rt32)",
3120tc_d68dca5c, TypeALU64>, Enc_03833b {
3121let Inst{7-2} = 0b011000;
3122let Inst{13-13} = 0b1;
3123let Inst{31-21} = 0b11010010000;
3124let isPredicateLate = 1;
3125}
3126def A4_vcmpbeq_any : HInst<
3127(outs PredRegs:$Pd4),
3128(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3129"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
3130tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3131let Inst{7-2} = 0b000000;
3132let Inst{13-13} = 0b1;
3133let Inst{31-21} = 0b11010010000;
3134}
3135def A4_vcmpbeqi : HInst<
3136(outs PredRegs:$Pd4),
3137(ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
3138"$Pd4 = vcmpb.eq($Rss32,#$Ii)",
3139tc_a1297125, TypeALU64>, Enc_0d8adb {
3140let Inst{4-2} = 0b000;
3141let Inst{13-13} = 0b0;
3142let Inst{31-21} = 0b11011100000;
3143}
3144def A4_vcmpbgt : HInst<
3145(outs PredRegs:$Pd4),
3146(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3147"$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
3148tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3149let Inst{7-2} = 0b010000;
3150let Inst{13-13} = 0b1;
3151let Inst{31-21} = 0b11010010000;
3152}
3153def A4_vcmpbgti : HInst<
3154(outs PredRegs:$Pd4),
3155(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3156"$Pd4 = vcmpb.gt($Rss32,#$Ii)",
3157tc_a1297125, TypeALU64>, Enc_0d8adb {
3158let Inst{4-2} = 0b000;
3159let Inst{13-13} = 0b0;
3160let Inst{31-21} = 0b11011100001;
3161}
3162def A4_vcmpbgtui : HInst<
3163(outs PredRegs:$Pd4),
3164(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3165"$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
3166tc_a1297125, TypeALU64>, Enc_3680c2 {
3167let Inst{4-2} = 0b000;
3168let Inst{13-12} = 0b00;
3169let Inst{31-21} = 0b11011100010;
3170}
3171def A4_vcmpheqi : HInst<
3172(outs PredRegs:$Pd4),
3173(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3174"$Pd4 = vcmph.eq($Rss32,#$Ii)",
3175tc_a1297125, TypeALU64>, Enc_0d8adb {
3176let Inst{4-2} = 0b010;
3177let Inst{13-13} = 0b0;
3178let Inst{31-21} = 0b11011100000;
3179}
3180def A4_vcmphgti : HInst<
3181(outs PredRegs:$Pd4),
3182(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3183"$Pd4 = vcmph.gt($Rss32,#$Ii)",
3184tc_a1297125, TypeALU64>, Enc_0d8adb {
3185let Inst{4-2} = 0b010;
3186let Inst{13-13} = 0b0;
3187let Inst{31-21} = 0b11011100001;
3188}
3189def A4_vcmphgtui : HInst<
3190(outs PredRegs:$Pd4),
3191(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3192"$Pd4 = vcmph.gtu($Rss32,#$Ii)",
3193tc_a1297125, TypeALU64>, Enc_3680c2 {
3194let Inst{4-2} = 0b010;
3195let Inst{13-12} = 0b00;
3196let Inst{31-21} = 0b11011100010;
3197}
3198def A4_vcmpweqi : HInst<
3199(outs PredRegs:$Pd4),
3200(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3201"$Pd4 = vcmpw.eq($Rss32,#$Ii)",
3202tc_a1297125, TypeALU64>, Enc_0d8adb {
3203let Inst{4-2} = 0b100;
3204let Inst{13-13} = 0b0;
3205let Inst{31-21} = 0b11011100000;
3206}
3207def A4_vcmpwgti : HInst<
3208(outs PredRegs:$Pd4),
3209(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3210"$Pd4 = vcmpw.gt($Rss32,#$Ii)",
3211tc_a1297125, TypeALU64>, Enc_0d8adb {
3212let Inst{4-2} = 0b100;
3213let Inst{13-13} = 0b0;
3214let Inst{31-21} = 0b11011100001;
3215}
3216def A4_vcmpwgtui : HInst<
3217(outs PredRegs:$Pd4),
3218(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3219"$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
3220tc_a1297125, TypeALU64>, Enc_3680c2 {
3221let Inst{4-2} = 0b100;
3222let Inst{13-12} = 0b00;
3223let Inst{31-21} = 0b11011100010;
3224}
3225def A4_vrmaxh : HInst<
3226(outs DoubleRegs:$Rxx32),
3227(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3228"$Rxx32 = vrmaxh($Rss32,$Ru32)",
3229tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3230let Inst{7-5} = 0b001;
3231let Inst{13-13} = 0b0;
3232let Inst{31-21} = 0b11001011001;
3233let prefersSlot3 = 1;
3234let Constraints = "$Rxx32 = $Rxx32in";
3235}
3236def A4_vrmaxuh : HInst<
3237(outs DoubleRegs:$Rxx32),
3238(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3239"$Rxx32 = vrmaxuh($Rss32,$Ru32)",
3240tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3241let Inst{7-5} = 0b001;
3242let Inst{13-13} = 0b1;
3243let Inst{31-21} = 0b11001011001;
3244let prefersSlot3 = 1;
3245let Constraints = "$Rxx32 = $Rxx32in";
3246}
3247def A4_vrmaxuw : HInst<
3248(outs DoubleRegs:$Rxx32),
3249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3250"$Rxx32 = vrmaxuw($Rss32,$Ru32)",
3251tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3252let Inst{7-5} = 0b010;
3253let Inst{13-13} = 0b1;
3254let Inst{31-21} = 0b11001011001;
3255let prefersSlot3 = 1;
3256let Constraints = "$Rxx32 = $Rxx32in";
3257}
3258def A4_vrmaxw : HInst<
3259(outs DoubleRegs:$Rxx32),
3260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3261"$Rxx32 = vrmaxw($Rss32,$Ru32)",
3262tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3263let Inst{7-5} = 0b010;
3264let Inst{13-13} = 0b0;
3265let Inst{31-21} = 0b11001011001;
3266let prefersSlot3 = 1;
3267let Constraints = "$Rxx32 = $Rxx32in";
3268}
3269def A4_vrminh : HInst<
3270(outs DoubleRegs:$Rxx32),
3271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3272"$Rxx32 = vrminh($Rss32,$Ru32)",
3273tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3274let Inst{7-5} = 0b101;
3275let Inst{13-13} = 0b0;
3276let Inst{31-21} = 0b11001011001;
3277let prefersSlot3 = 1;
3278let Constraints = "$Rxx32 = $Rxx32in";
3279}
3280def A4_vrminuh : HInst<
3281(outs DoubleRegs:$Rxx32),
3282(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3283"$Rxx32 = vrminuh($Rss32,$Ru32)",
3284tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3285let Inst{7-5} = 0b101;
3286let Inst{13-13} = 0b1;
3287let Inst{31-21} = 0b11001011001;
3288let prefersSlot3 = 1;
3289let Constraints = "$Rxx32 = $Rxx32in";
3290}
3291def A4_vrminuw : HInst<
3292(outs DoubleRegs:$Rxx32),
3293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3294"$Rxx32 = vrminuw($Rss32,$Ru32)",
3295tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3296let Inst{7-5} = 0b110;
3297let Inst{13-13} = 0b1;
3298let Inst{31-21} = 0b11001011001;
3299let prefersSlot3 = 1;
3300let Constraints = "$Rxx32 = $Rxx32in";
3301}
3302def A4_vrminw : HInst<
3303(outs DoubleRegs:$Rxx32),
3304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3305"$Rxx32 = vrminw($Rss32,$Ru32)",
3306tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3307let Inst{7-5} = 0b110;
3308let Inst{13-13} = 0b0;
3309let Inst{31-21} = 0b11001011001;
3310let prefersSlot3 = 1;
3311let Constraints = "$Rxx32 = $Rxx32in";
3312}
3313def A5_ACS : HInst<
3314(outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
3315(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3316"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
3317tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> {
3318let Inst{7-7} = 0b0;
3319let Inst{13-13} = 0b0;
3320let Inst{31-21} = 0b11101010101;
3321let isPredicateLate = 1;
3322let prefersSlot3 = 1;
3323let Defs = [USR_OVF];
3324let Constraints = "$Rxx32 = $Rxx32in";
3325}
3326def A5_vaddhubs : HInst<
3327(outs IntRegs:$Rd32),
3328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3329"$Rd32 = vaddhub($Rss32,$Rtt32):sat",
3330tc_0dfac0a7, TypeS_3op>, Enc_d2216a {
3331let Inst{7-5} = 0b001;
3332let Inst{13-13} = 0b0;
3333let Inst{31-21} = 0b11000001010;
3334let hasNewValue = 1;
3335let opNewValue = 0;
3336let prefersSlot3 = 1;
3337let Defs = [USR_OVF];
3338}
3339def A6_vcmpbeq_notany : HInst<
3340(outs PredRegs:$Pd4),
3341(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3342"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
3343tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> {
3344let Inst{7-2} = 0b001000;
3345let Inst{13-13} = 0b1;
3346let Inst{31-21} = 0b11010010000;
3347}
3348def A6_vminub_RdP : HInst<
3349(outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
3350(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
3351"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
3352tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> {
3353let Inst{7-7} = 0b0;
3354let Inst{13-13} = 0b0;
3355let Inst{31-21} = 0b11101010111;
3356let isPredicateLate = 1;
3357let prefersSlot3 = 1;
3358}
3359def A7_clip : HInst<
3360(outs IntRegs:$Rd32),
3361(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3362"$Rd32 = clip($Rs32,#$Ii)",
3363tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> {
3364let Inst{7-5} = 0b101;
3365let Inst{13-13} = 0b0;
3366let Inst{31-21} = 0b10001000110;
3367let hasNewValue = 1;
3368let opNewValue = 0;
3369}
3370def A7_croundd_ri : HInst<
3371(outs DoubleRegs:$Rdd32),
3372(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
3373"$Rdd32 = cround($Rss32,#$Ii)",
3374tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> {
3375let Inst{7-5} = 0b010;
3376let Inst{31-21} = 0b10001100111;
3377let prefersSlot3 = 1;
3378}
3379def A7_croundd_rr : HInst<
3380(outs DoubleRegs:$Rdd32),
3381(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3382"$Rdd32 = cround($Rss32,$Rt32)",
3383tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> {
3384let Inst{7-5} = 0b010;
3385let Inst{13-13} = 0b0;
3386let Inst{31-21} = 0b11000110110;
3387let prefersSlot3 = 1;
3388}
3389def A7_vclip : HInst<
3390(outs DoubleRegs:$Rdd32),
3391(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
3392"$Rdd32 = vclip($Rss32,#$Ii)",
3393tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> {
3394let Inst{7-5} = 0b110;
3395let Inst{13-13} = 0b0;
3396let Inst{31-21} = 0b10001000110;
3397}
3398def C2_all8 : HInst<
3399(outs PredRegs:$Pd4),
3400(ins PredRegs:$Ps4),
3401"$Pd4 = all8($Ps4)",
3402tc_151bf368, TypeCR>, Enc_65d691 {
3403let Inst{13-2} = 0b000000000000;
3404let Inst{31-18} = 0b01101011101000;
3405}
3406def C2_and : HInst<
3407(outs PredRegs:$Pd4),
3408(ins PredRegs:$Pt4, PredRegs:$Ps4),
3409"$Pd4 = and($Pt4,$Ps4)",
3410tc_651cbe02, TypeCR>, Enc_454a26 {
3411let Inst{7-2} = 0b000000;
3412let Inst{13-10} = 0b0000;
3413let Inst{31-18} = 0b01101011000000;
3414}
3415def C2_andn : HInst<
3416(outs PredRegs:$Pd4),
3417(ins PredRegs:$Pt4, PredRegs:$Ps4),
3418"$Pd4 = and($Pt4,!$Ps4)",
3419tc_651cbe02, TypeCR>, Enc_454a26 {
3420let Inst{7-2} = 0b000000;
3421let Inst{13-10} = 0b0000;
3422let Inst{31-18} = 0b01101011011000;
3423}
3424def C2_any8 : HInst<
3425(outs PredRegs:$Pd4),
3426(ins PredRegs:$Ps4),
3427"$Pd4 = any8($Ps4)",
3428tc_151bf368, TypeCR>, Enc_65d691 {
3429let Inst{13-2} = 0b000000000000;
3430let Inst{31-18} = 0b01101011100000;
3431}
3432def C2_bitsclr : HInst<
3433(outs PredRegs:$Pd4),
3434(ins IntRegs:$Rs32, IntRegs:$Rt32),
3435"$Pd4 = bitsclr($Rs32,$Rt32)",
3436tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3437let Inst{7-2} = 0b000000;
3438let Inst{13-13} = 0b0;
3439let Inst{31-21} = 0b11000111100;
3440}
3441def C2_bitsclri : HInst<
3442(outs PredRegs:$Pd4),
3443(ins IntRegs:$Rs32, u6_0Imm:$Ii),
3444"$Pd4 = bitsclr($Rs32,#$Ii)",
3445tc_a1297125, TypeS_2op>, Enc_5d6c34 {
3446let Inst{7-2} = 0b000000;
3447let Inst{31-21} = 0b10000101100;
3448}
3449def C2_bitsset : HInst<
3450(outs PredRegs:$Pd4),
3451(ins IntRegs:$Rs32, IntRegs:$Rt32),
3452"$Pd4 = bitsset($Rs32,$Rt32)",
3453tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3454let Inst{7-2} = 0b000000;
3455let Inst{13-13} = 0b0;
3456let Inst{31-21} = 0b11000111010;
3457}
3458def C2_ccombinewf : HInst<
3459(outs DoubleRegs:$Rdd32),
3460(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3461"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3462tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3463let Inst{7-7} = 0b1;
3464let Inst{13-13} = 0b0;
3465let Inst{31-21} = 0b11111101000;
3466let isPredicated = 1;
3467let isPredicatedFalse = 1;
3468let BaseOpcode = "A2_combinew";
3469}
3470def C2_ccombinewnewf : HInst<
3471(outs DoubleRegs:$Rdd32),
3472(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3473"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3474tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3475let Inst{7-7} = 0b1;
3476let Inst{13-13} = 0b1;
3477let Inst{31-21} = 0b11111101000;
3478let isPredicated = 1;
3479let isPredicatedFalse = 1;
3480let isPredicatedNew = 1;
3481let BaseOpcode = "A2_combinew";
3482}
3483def C2_ccombinewnewt : HInst<
3484(outs DoubleRegs:$Rdd32),
3485(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3486"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3487tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3488let Inst{7-7} = 0b0;
3489let Inst{13-13} = 0b1;
3490let Inst{31-21} = 0b11111101000;
3491let isPredicated = 1;
3492let isPredicatedNew = 1;
3493let BaseOpcode = "A2_combinew";
3494}
3495def C2_ccombinewt : HInst<
3496(outs DoubleRegs:$Rdd32),
3497(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3498"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3499tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3500let Inst{7-7} = 0b0;
3501let Inst{13-13} = 0b0;
3502let Inst{31-21} = 0b11111101000;
3503let isPredicated = 1;
3504let BaseOpcode = "A2_combinew";
3505}
3506def C2_cmoveif : HInst<
3507(outs IntRegs:$Rd32),
3508(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3509"if (!$Pu4) $Rd32 = #$Ii",
3510tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3511let Inst{13-13} = 0b0;
3512let Inst{20-20} = 0b0;
3513let Inst{31-23} = 0b011111101;
3514let isPredicated = 1;
3515let isPredicatedFalse = 1;
3516let hasNewValue = 1;
3517let opNewValue = 0;
3518let BaseOpcode = "A2_tfrsi";
3519let CextOpcode = "A2_tfr";
3520let InputType = "imm";
3521let isMoveImm = 1;
3522let isExtendable = 1;
3523let opExtendable = 2;
3524let isExtentSigned = 1;
3525let opExtentBits = 12;
3526let opExtentAlign = 0;
3527}
3528def C2_cmoveit : HInst<
3529(outs IntRegs:$Rd32),
3530(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3531"if ($Pu4) $Rd32 = #$Ii",
3532tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3533let Inst{13-13} = 0b0;
3534let Inst{20-20} = 0b0;
3535let Inst{31-23} = 0b011111100;
3536let isPredicated = 1;
3537let hasNewValue = 1;
3538let opNewValue = 0;
3539let BaseOpcode = "A2_tfrsi";
3540let CextOpcode = "A2_tfr";
3541let InputType = "imm";
3542let isMoveImm = 1;
3543let isExtendable = 1;
3544let opExtendable = 2;
3545let isExtentSigned = 1;
3546let opExtentBits = 12;
3547let opExtentAlign = 0;
3548}
3549def C2_cmovenewif : HInst<
3550(outs IntRegs:$Rd32),
3551(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3552"if (!$Pu4.new) $Rd32 = #$Ii",
3553tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3554let Inst{13-13} = 0b1;
3555let Inst{20-20} = 0b0;
3556let Inst{31-23} = 0b011111101;
3557let isPredicated = 1;
3558let isPredicatedFalse = 1;
3559let hasNewValue = 1;
3560let opNewValue = 0;
3561let isPredicatedNew = 1;
3562let BaseOpcode = "A2_tfrsi";
3563let CextOpcode = "A2_tfr";
3564let InputType = "imm";
3565let isMoveImm = 1;
3566let isExtendable = 1;
3567let opExtendable = 2;
3568let isExtentSigned = 1;
3569let opExtentBits = 12;
3570let opExtentAlign = 0;
3571}
3572def C2_cmovenewit : HInst<
3573(outs IntRegs:$Rd32),
3574(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3575"if ($Pu4.new) $Rd32 = #$Ii",
3576tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3577let Inst{13-13} = 0b1;
3578let Inst{20-20} = 0b0;
3579let Inst{31-23} = 0b011111100;
3580let isPredicated = 1;
3581let hasNewValue = 1;
3582let opNewValue = 0;
3583let isPredicatedNew = 1;
3584let BaseOpcode = "A2_tfrsi";
3585let CextOpcode = "A2_tfr";
3586let InputType = "imm";
3587let isMoveImm = 1;
3588let isExtendable = 1;
3589let opExtendable = 2;
3590let isExtentSigned = 1;
3591let opExtentBits = 12;
3592let opExtentAlign = 0;
3593}
3594def C2_cmpeq : HInst<
3595(outs PredRegs:$Pd4),
3596(ins IntRegs:$Rs32, IntRegs:$Rt32),
3597"$Pd4 = cmp.eq($Rs32,$Rt32)",
3598tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3599let Inst{7-2} = 0b000000;
3600let Inst{13-13} = 0b0;
3601let Inst{31-21} = 0b11110010000;
3602let CextOpcode = "C2_cmpeq";
3603let InputType = "reg";
3604let isCommutable = 1;
3605let isCompare = 1;
3606}
3607def C2_cmpeqi : HInst<
3608(outs PredRegs:$Pd4),
3609(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3610"$Pd4 = cmp.eq($Rs32,#$Ii)",
3611tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3612let Inst{4-2} = 0b000;
3613let Inst{31-22} = 0b0111010100;
3614let CextOpcode = "C2_cmpeq";
3615let InputType = "imm";
3616let isCompare = 1;
3617let isExtendable = 1;
3618let opExtendable = 2;
3619let isExtentSigned = 1;
3620let opExtentBits = 10;
3621let opExtentAlign = 0;
3622}
3623def C2_cmpeqp : HInst<
3624(outs PredRegs:$Pd4),
3625(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3626"$Pd4 = cmp.eq($Rss32,$Rtt32)",
3627tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3628let Inst{7-2} = 0b000000;
3629let Inst{13-13} = 0b0;
3630let Inst{31-21} = 0b11010010100;
3631let isCommutable = 1;
3632let isCompare = 1;
3633}
3634def C2_cmpgei : HInst<
3635(outs PredRegs:$Pd4),
3636(ins IntRegs:$Rs32, s8_0Imm:$Ii),
3637"$Pd4 = cmp.ge($Rs32,#$Ii)",
3638tc_d33e5eee, TypeALU32_2op> {
3639let isCompare = 1;
3640let isPseudo = 1;
3641}
3642def C2_cmpgeui : HInst<
3643(outs PredRegs:$Pd4),
3644(ins IntRegs:$Rs32, u8_0Imm:$Ii),
3645"$Pd4 = cmp.geu($Rs32,#$Ii)",
3646tc_d33e5eee, TypeALU32_2op> {
3647let isCompare = 1;
3648let isPseudo = 1;
3649}
3650def C2_cmpgt : HInst<
3651(outs PredRegs:$Pd4),
3652(ins IntRegs:$Rs32, IntRegs:$Rt32),
3653"$Pd4 = cmp.gt($Rs32,$Rt32)",
3654tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3655let Inst{7-2} = 0b000000;
3656let Inst{13-13} = 0b0;
3657let Inst{31-21} = 0b11110010010;
3658let CextOpcode = "C2_cmpgt";
3659let InputType = "reg";
3660let isCompare = 1;
3661}
3662def C2_cmpgti : HInst<
3663(outs PredRegs:$Pd4),
3664(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3665"$Pd4 = cmp.gt($Rs32,#$Ii)",
3666tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3667let Inst{4-2} = 0b000;
3668let Inst{31-22} = 0b0111010101;
3669let CextOpcode = "C2_cmpgt";
3670let InputType = "imm";
3671let isCompare = 1;
3672let isExtendable = 1;
3673let opExtendable = 2;
3674let isExtentSigned = 1;
3675let opExtentBits = 10;
3676let opExtentAlign = 0;
3677}
3678def C2_cmpgtp : HInst<
3679(outs PredRegs:$Pd4),
3680(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3681"$Pd4 = cmp.gt($Rss32,$Rtt32)",
3682tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3683let Inst{7-2} = 0b010000;
3684let Inst{13-13} = 0b0;
3685let Inst{31-21} = 0b11010010100;
3686let isCompare = 1;
3687}
3688def C2_cmpgtu : HInst<
3689(outs PredRegs:$Pd4),
3690(ins IntRegs:$Rs32, IntRegs:$Rt32),
3691"$Pd4 = cmp.gtu($Rs32,$Rt32)",
3692tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3693let Inst{7-2} = 0b000000;
3694let Inst{13-13} = 0b0;
3695let Inst{31-21} = 0b11110010011;
3696let CextOpcode = "C2_cmpgtu";
3697let InputType = "reg";
3698let isCompare = 1;
3699}
3700def C2_cmpgtui : HInst<
3701(outs PredRegs:$Pd4),
3702(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3703"$Pd4 = cmp.gtu($Rs32,#$Ii)",
3704tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3705let Inst{4-2} = 0b000;
3706let Inst{31-21} = 0b01110101100;
3707let CextOpcode = "C2_cmpgtu";
3708let InputType = "imm";
3709let isCompare = 1;
3710let isExtendable = 1;
3711let opExtendable = 2;
3712let isExtentSigned = 0;
3713let opExtentBits = 9;
3714let opExtentAlign = 0;
3715}
3716def C2_cmpgtup : HInst<
3717(outs PredRegs:$Pd4),
3718(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3719"$Pd4 = cmp.gtu($Rss32,$Rtt32)",
3720tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3721let Inst{7-2} = 0b100000;
3722let Inst{13-13} = 0b0;
3723let Inst{31-21} = 0b11010010100;
3724let isCompare = 1;
3725}
3726def C2_cmplt : HInst<
3727(outs PredRegs:$Pd4),
3728(ins IntRegs:$Rs32, IntRegs:$Rt32),
3729"$Pd4 = cmp.lt($Rs32,$Rt32)",
3730tc_d33e5eee, TypeALU32_3op> {
3731let isCompare = 1;
3732let isPseudo = 1;
3733let isCodeGenOnly = 1;
3734}
3735def C2_cmpltu : HInst<
3736(outs PredRegs:$Pd4),
3737(ins IntRegs:$Rs32, IntRegs:$Rt32),
3738"$Pd4 = cmp.ltu($Rs32,$Rt32)",
3739tc_d33e5eee, TypeALU32_3op> {
3740let isCompare = 1;
3741let isPseudo = 1;
3742let isCodeGenOnly = 1;
3743}
3744def C2_mask : HInst<
3745(outs DoubleRegs:$Rdd32),
3746(ins PredRegs:$Pt4),
3747"$Rdd32 = mask($Pt4)",
3748tc_9f6cd987, TypeS_2op>, Enc_78e566 {
3749let Inst{7-5} = 0b000;
3750let Inst{13-10} = 0b0000;
3751let Inst{31-16} = 0b1000011000000000;
3752}
3753def C2_mux : HInst<
3754(outs IntRegs:$Rd32),
3755(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3756"$Rd32 = mux($Pu4,$Rs32,$Rt32)",
3757tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 {
3758let Inst{7-7} = 0b0;
3759let Inst{13-13} = 0b0;
3760let Inst{31-21} = 0b11110100000;
3761let hasNewValue = 1;
3762let opNewValue = 0;
3763let InputType = "reg";
3764}
3765def C2_muxii : HInst<
3766(outs IntRegs:$Rd32),
3767(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
3768"$Rd32 = mux($Pu4,#$Ii,#$II)",
3769tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d {
3770let Inst{31-25} = 0b0111101;
3771let hasNewValue = 1;
3772let opNewValue = 0;
3773let isExtendable = 1;
3774let opExtendable = 2;
3775let isExtentSigned = 1;
3776let opExtentBits = 8;
3777let opExtentAlign = 0;
3778}
3779def C2_muxir : HInst<
3780(outs IntRegs:$Rd32),
3781(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
3782"$Rd32 = mux($Pu4,$Rs32,#$Ii)",
3783tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3784let Inst{13-13} = 0b0;
3785let Inst{31-23} = 0b011100110;
3786let hasNewValue = 1;
3787let opNewValue = 0;
3788let InputType = "imm";
3789let isExtendable = 1;
3790let opExtendable = 3;
3791let isExtentSigned = 1;
3792let opExtentBits = 8;
3793let opExtentAlign = 0;
3794}
3795def C2_muxri : HInst<
3796(outs IntRegs:$Rd32),
3797(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
3798"$Rd32 = mux($Pu4,#$Ii,$Rs32)",
3799tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3800let Inst{13-13} = 0b0;
3801let Inst{31-23} = 0b011100111;
3802let hasNewValue = 1;
3803let opNewValue = 0;
3804let InputType = "imm";
3805let isExtendable = 1;
3806let opExtendable = 2;
3807let isExtentSigned = 1;
3808let opExtentBits = 8;
3809let opExtentAlign = 0;
3810}
3811def C2_not : HInst<
3812(outs PredRegs:$Pd4),
3813(ins PredRegs:$Ps4),
3814"$Pd4 = not($Ps4)",
3815tc_151bf368, TypeCR>, Enc_65d691 {
3816let Inst{13-2} = 0b000000000000;
3817let Inst{31-18} = 0b01101011110000;
3818}
3819def C2_or : HInst<
3820(outs PredRegs:$Pd4),
3821(ins PredRegs:$Pt4, PredRegs:$Ps4),
3822"$Pd4 = or($Pt4,$Ps4)",
3823tc_651cbe02, TypeCR>, Enc_454a26 {
3824let Inst{7-2} = 0b000000;
3825let Inst{13-10} = 0b0000;
3826let Inst{31-18} = 0b01101011001000;
3827}
3828def C2_orn : HInst<
3829(outs PredRegs:$Pd4),
3830(ins PredRegs:$Pt4, PredRegs:$Ps4),
3831"$Pd4 = or($Pt4,!$Ps4)",
3832tc_651cbe02, TypeCR>, Enc_454a26 {
3833let Inst{7-2} = 0b000000;
3834let Inst{13-10} = 0b0000;
3835let Inst{31-18} = 0b01101011111000;
3836}
3837def C2_pxfer_map : HInst<
3838(outs PredRegs:$Pd4),
3839(ins PredRegs:$Ps4),
3840"$Pd4 = $Ps4",
3841tc_651cbe02, TypeMAPPING> {
3842let isPseudo = 1;
3843let isCodeGenOnly = 1;
3844}
3845def C2_tfrpr : HInst<
3846(outs IntRegs:$Rd32),
3847(ins PredRegs:$Ps4),
3848"$Rd32 = $Ps4",
3849tc_9f6cd987, TypeS_2op>, Enc_f5e933 {
3850let Inst{13-5} = 0b000000000;
3851let Inst{31-18} = 0b10001001010000;
3852let hasNewValue = 1;
3853let opNewValue = 0;
3854}
3855def C2_tfrrp : HInst<
3856(outs PredRegs:$Pd4),
3857(ins IntRegs:$Rs32),
3858"$Pd4 = $Rs32",
3859tc_55b33fda, TypeS_2op>, Enc_48b75f {
3860let Inst{13-2} = 0b000000000000;
3861let Inst{31-21} = 0b10000101010;
3862}
3863def C2_vitpack : HInst<
3864(outs IntRegs:$Rd32),
3865(ins PredRegs:$Ps4, PredRegs:$Pt4),
3866"$Rd32 = vitpack($Ps4,$Pt4)",
3867tc_f34c1c21, TypeS_2op>, Enc_527412 {
3868let Inst{7-5} = 0b000;
3869let Inst{13-10} = 0b0000;
3870let Inst{31-18} = 0b10001001000000;
3871let hasNewValue = 1;
3872let opNewValue = 0;
3873let prefersSlot3 = 1;
3874}
3875def C2_vmux : HInst<
3876(outs DoubleRegs:$Rdd32),
3877(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3878"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
3879tc_6fc5dbea, TypeALU64>, Enc_329361 {
3880let Inst{7-7} = 0b0;
3881let Inst{13-13} = 0b0;
3882let Inst{31-21} = 0b11010001000;
3883}
3884def C2_xor : HInst<
3885(outs PredRegs:$Pd4),
3886(ins PredRegs:$Ps4, PredRegs:$Pt4),
3887"$Pd4 = xor($Ps4,$Pt4)",
3888tc_651cbe02, TypeCR>, Enc_284ebb {
3889let Inst{7-2} = 0b000000;
3890let Inst{13-10} = 0b0000;
3891let Inst{31-18} = 0b01101011010000;
3892}
3893def C4_addipc : HInst<
3894(outs IntRegs:$Rd32),
3895(ins u32_0Imm:$Ii),
3896"$Rd32 = add(pc,#$Ii)",
3897tc_3edca78f, TypeCR>, Enc_607661 {
3898let Inst{6-5} = 0b00;
3899let Inst{13-13} = 0b0;
3900let Inst{31-16} = 0b0110101001001001;
3901let hasNewValue = 1;
3902let opNewValue = 0;
3903let isExtendable = 1;
3904let opExtendable = 1;
3905let isExtentSigned = 0;
3906let opExtentBits = 6;
3907let opExtentAlign = 0;
3908}
3909def C4_and_and : HInst<
3910(outs PredRegs:$Pd4),
3911(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3912"$Pd4 = and($Ps4,and($Pt4,$Pu4))",
3913tc_a7a13fac, TypeCR>, Enc_9ac432 {
3914let Inst{5-2} = 0b0000;
3915let Inst{13-10} = 0b0000;
3916let Inst{31-18} = 0b01101011000100;
3917}
3918def C4_and_andn : HInst<
3919(outs PredRegs:$Pd4),
3920(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3921"$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
3922tc_a7a13fac, TypeCR>, Enc_9ac432 {
3923let Inst{5-2} = 0b0000;
3924let Inst{13-10} = 0b0000;
3925let Inst{31-18} = 0b01101011100100;
3926}
3927def C4_and_or : HInst<
3928(outs PredRegs:$Pd4),
3929(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3930"$Pd4 = and($Ps4,or($Pt4,$Pu4))",
3931tc_a7a13fac, TypeCR>, Enc_9ac432 {
3932let Inst{5-2} = 0b0000;
3933let Inst{13-10} = 0b0000;
3934let Inst{31-18} = 0b01101011001100;
3935}
3936def C4_and_orn : HInst<
3937(outs PredRegs:$Pd4),
3938(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3939"$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
3940tc_a7a13fac, TypeCR>, Enc_9ac432 {
3941let Inst{5-2} = 0b0000;
3942let Inst{13-10} = 0b0000;
3943let Inst{31-18} = 0b01101011101100;
3944}
3945def C4_cmplte : HInst<
3946(outs PredRegs:$Pd4),
3947(ins IntRegs:$Rs32, IntRegs:$Rt32),
3948"$Pd4 = !cmp.gt($Rs32,$Rt32)",
3949tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3950let Inst{7-2} = 0b000100;
3951let Inst{13-13} = 0b0;
3952let Inst{31-21} = 0b11110010010;
3953let CextOpcode = "C4_cmplte";
3954let InputType = "reg";
3955let isCompare = 1;
3956}
3957def C4_cmpltei : HInst<
3958(outs PredRegs:$Pd4),
3959(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3960"$Pd4 = !cmp.gt($Rs32,#$Ii)",
3961tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3962let Inst{4-2} = 0b100;
3963let Inst{31-22} = 0b0111010101;
3964let CextOpcode = "C4_cmplte";
3965let InputType = "imm";
3966let isCompare = 1;
3967let isExtendable = 1;
3968let opExtendable = 2;
3969let isExtentSigned = 1;
3970let opExtentBits = 10;
3971let opExtentAlign = 0;
3972}
3973def C4_cmplteu : HInst<
3974(outs PredRegs:$Pd4),
3975(ins IntRegs:$Rs32, IntRegs:$Rt32),
3976"$Pd4 = !cmp.gtu($Rs32,$Rt32)",
3977tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3978let Inst{7-2} = 0b000100;
3979let Inst{13-13} = 0b0;
3980let Inst{31-21} = 0b11110010011;
3981let CextOpcode = "C4_cmplteu";
3982let InputType = "reg";
3983let isCompare = 1;
3984}
3985def C4_cmplteui : HInst<
3986(outs PredRegs:$Pd4),
3987(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3988"$Pd4 = !cmp.gtu($Rs32,#$Ii)",
3989tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3990let Inst{4-2} = 0b100;
3991let Inst{31-21} = 0b01110101100;
3992let CextOpcode = "C4_cmplteu";
3993let InputType = "imm";
3994let isCompare = 1;
3995let isExtendable = 1;
3996let opExtendable = 2;
3997let isExtentSigned = 0;
3998let opExtentBits = 9;
3999let opExtentAlign = 0;
4000}
4001def C4_cmpneq : HInst<
4002(outs PredRegs:$Pd4),
4003(ins IntRegs:$Rs32, IntRegs:$Rt32),
4004"$Pd4 = !cmp.eq($Rs32,$Rt32)",
4005tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
4006let Inst{7-2} = 0b000100;
4007let Inst{13-13} = 0b0;
4008let Inst{31-21} = 0b11110010000;
4009let CextOpcode = "C4_cmpneq";
4010let InputType = "reg";
4011let isCommutable = 1;
4012let isCompare = 1;
4013}
4014def C4_cmpneqi : HInst<
4015(outs PredRegs:$Pd4),
4016(ins IntRegs:$Rs32, s32_0Imm:$Ii),
4017"$Pd4 = !cmp.eq($Rs32,#$Ii)",
4018tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
4019let Inst{4-2} = 0b100;
4020let Inst{31-22} = 0b0111010100;
4021let CextOpcode = "C4_cmpneq";
4022let InputType = "imm";
4023let isCompare = 1;
4024let isExtendable = 1;
4025let opExtendable = 2;
4026let isExtentSigned = 1;
4027let opExtentBits = 10;
4028let opExtentAlign = 0;
4029}
4030def C4_fastcorner9 : HInst<
4031(outs PredRegs:$Pd4),
4032(ins PredRegs:$Ps4, PredRegs:$Pt4),
4033"$Pd4 = fastcorner9($Ps4,$Pt4)",
4034tc_651cbe02, TypeCR>, Enc_284ebb {
4035let Inst{7-2} = 0b100100;
4036let Inst{13-10} = 0b1000;
4037let Inst{31-18} = 0b01101011000000;
4038}
4039def C4_fastcorner9_not : HInst<
4040(outs PredRegs:$Pd4),
4041(ins PredRegs:$Ps4, PredRegs:$Pt4),
4042"$Pd4 = !fastcorner9($Ps4,$Pt4)",
4043tc_651cbe02, TypeCR>, Enc_284ebb {
4044let Inst{7-2} = 0b100100;
4045let Inst{13-10} = 0b1000;
4046let Inst{31-18} = 0b01101011000100;
4047}
4048def C4_nbitsclr : HInst<
4049(outs PredRegs:$Pd4),
4050(ins IntRegs:$Rs32, IntRegs:$Rt32),
4051"$Pd4 = !bitsclr($Rs32,$Rt32)",
4052tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4053let Inst{7-2} = 0b000000;
4054let Inst{13-13} = 0b0;
4055let Inst{31-21} = 0b11000111101;
4056}
4057def C4_nbitsclri : HInst<
4058(outs PredRegs:$Pd4),
4059(ins IntRegs:$Rs32, u6_0Imm:$Ii),
4060"$Pd4 = !bitsclr($Rs32,#$Ii)",
4061tc_a1297125, TypeS_2op>, Enc_5d6c34 {
4062let Inst{7-2} = 0b000000;
4063let Inst{31-21} = 0b10000101101;
4064}
4065def C4_nbitsset : HInst<
4066(outs PredRegs:$Pd4),
4067(ins IntRegs:$Rs32, IntRegs:$Rt32),
4068"$Pd4 = !bitsset($Rs32,$Rt32)",
4069tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4070let Inst{7-2} = 0b000000;
4071let Inst{13-13} = 0b0;
4072let Inst{31-21} = 0b11000111011;
4073}
4074def C4_or_and : HInst<
4075(outs PredRegs:$Pd4),
4076(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4077"$Pd4 = or($Ps4,and($Pt4,$Pu4))",
4078tc_a7a13fac, TypeCR>, Enc_9ac432 {
4079let Inst{5-2} = 0b0000;
4080let Inst{13-10} = 0b0000;
4081let Inst{31-18} = 0b01101011010100;
4082}
4083def C4_or_andn : HInst<
4084(outs PredRegs:$Pd4),
4085(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4086"$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
4087tc_a7a13fac, TypeCR>, Enc_9ac432 {
4088let Inst{5-2} = 0b0000;
4089let Inst{13-10} = 0b0000;
4090let Inst{31-18} = 0b01101011110100;
4091}
4092def C4_or_or : HInst<
4093(outs PredRegs:$Pd4),
4094(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4095"$Pd4 = or($Ps4,or($Pt4,$Pu4))",
4096tc_a7a13fac, TypeCR>, Enc_9ac432 {
4097let Inst{5-2} = 0b0000;
4098let Inst{13-10} = 0b0000;
4099let Inst{31-18} = 0b01101011011100;
4100}
4101def C4_or_orn : HInst<
4102(outs PredRegs:$Pd4),
4103(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4104"$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
4105tc_a7a13fac, TypeCR>, Enc_9ac432 {
4106let Inst{5-2} = 0b0000;
4107let Inst{13-10} = 0b0000;
4108let Inst{31-18} = 0b01101011111100;
4109}
4110def F2_conv_d2df : HInst<
4111(outs DoubleRegs:$Rdd32),
4112(ins DoubleRegs:$Rss32),
4113"$Rdd32 = convert_d2df($Rss32)",
4114tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4115let Inst{13-5} = 0b000000011;
4116let Inst{31-21} = 0b10000000111;
4117let isFP = 1;
4118let Uses = [USR];
4119}
4120def F2_conv_d2sf : HInst<
4121(outs IntRegs:$Rd32),
4122(ins DoubleRegs:$Rss32),
4123"$Rd32 = convert_d2sf($Rss32)",
4124tc_9783714b, TypeS_2op>, Enc_90cd8b {
4125let Inst{13-5} = 0b000000001;
4126let Inst{31-21} = 0b10001000010;
4127let hasNewValue = 1;
4128let opNewValue = 0;
4129let isFP = 1;
4130let Uses = [USR];
4131}
4132def F2_conv_df2d : HInst<
4133(outs DoubleRegs:$Rdd32),
4134(ins DoubleRegs:$Rss32),
4135"$Rdd32 = convert_df2d($Rss32)",
4136tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4137let Inst{13-5} = 0b000000000;
4138let Inst{31-21} = 0b10000000111;
4139let isFP = 1;
4140let Uses = [USR];
4141}
4142def F2_conv_df2d_chop : HInst<
4143(outs DoubleRegs:$Rdd32),
4144(ins DoubleRegs:$Rss32),
4145"$Rdd32 = convert_df2d($Rss32):chop",
4146tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4147let Inst{13-5} = 0b000000110;
4148let Inst{31-21} = 0b10000000111;
4149let isFP = 1;
4150let Uses = [USR];
4151}
4152def F2_conv_df2sf : HInst<
4153(outs IntRegs:$Rd32),
4154(ins DoubleRegs:$Rss32),
4155"$Rd32 = convert_df2sf($Rss32)",
4156tc_9783714b, TypeS_2op>, Enc_90cd8b {
4157let Inst{13-5} = 0b000000001;
4158let Inst{31-21} = 0b10001000000;
4159let hasNewValue = 1;
4160let opNewValue = 0;
4161let isFP = 1;
4162let Uses = [USR];
4163}
4164def F2_conv_df2ud : HInst<
4165(outs DoubleRegs:$Rdd32),
4166(ins DoubleRegs:$Rss32),
4167"$Rdd32 = convert_df2ud($Rss32)",
4168tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4169let Inst{13-5} = 0b000000001;
4170let Inst{31-21} = 0b10000000111;
4171let isFP = 1;
4172let Uses = [USR];
4173}
4174def F2_conv_df2ud_chop : HInst<
4175(outs DoubleRegs:$Rdd32),
4176(ins DoubleRegs:$Rss32),
4177"$Rdd32 = convert_df2ud($Rss32):chop",
4178tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4179let Inst{13-5} = 0b000000111;
4180let Inst{31-21} = 0b10000000111;
4181let isFP = 1;
4182let Uses = [USR];
4183}
4184def F2_conv_df2uw : HInst<
4185(outs IntRegs:$Rd32),
4186(ins DoubleRegs:$Rss32),
4187"$Rd32 = convert_df2uw($Rss32)",
4188tc_9783714b, TypeS_2op>, Enc_90cd8b {
4189let Inst{13-5} = 0b000000001;
4190let Inst{31-21} = 0b10001000011;
4191let hasNewValue = 1;
4192let opNewValue = 0;
4193let isFP = 1;
4194let Uses = [USR];
4195}
4196def F2_conv_df2uw_chop : HInst<
4197(outs IntRegs:$Rd32),
4198(ins DoubleRegs:$Rss32),
4199"$Rd32 = convert_df2uw($Rss32):chop",
4200tc_9783714b, TypeS_2op>, Enc_90cd8b {
4201let Inst{13-5} = 0b000000001;
4202let Inst{31-21} = 0b10001000101;
4203let hasNewValue = 1;
4204let opNewValue = 0;
4205let isFP = 1;
4206let Uses = [USR];
4207}
4208def F2_conv_df2w : HInst<
4209(outs IntRegs:$Rd32),
4210(ins DoubleRegs:$Rss32),
4211"$Rd32 = convert_df2w($Rss32)",
4212tc_9783714b, TypeS_2op>, Enc_90cd8b {
4213let Inst{13-5} = 0b000000001;
4214let Inst{31-21} = 0b10001000100;
4215let hasNewValue = 1;
4216let opNewValue = 0;
4217let isFP = 1;
4218let Uses = [USR];
4219}
4220def F2_conv_df2w_chop : HInst<
4221(outs IntRegs:$Rd32),
4222(ins DoubleRegs:$Rss32),
4223"$Rd32 = convert_df2w($Rss32):chop",
4224tc_9783714b, TypeS_2op>, Enc_90cd8b {
4225let Inst{13-5} = 0b000000001;
4226let Inst{31-21} = 0b10001000111;
4227let hasNewValue = 1;
4228let opNewValue = 0;
4229let isFP = 1;
4230let Uses = [USR];
4231}
4232def F2_conv_sf2d : HInst<
4233(outs DoubleRegs:$Rdd32),
4234(ins IntRegs:$Rs32),
4235"$Rdd32 = convert_sf2d($Rs32)",
4236tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4237let Inst{13-5} = 0b000000100;
4238let Inst{31-21} = 0b10000100100;
4239let isFP = 1;
4240let Uses = [USR];
4241}
4242def F2_conv_sf2d_chop : HInst<
4243(outs DoubleRegs:$Rdd32),
4244(ins IntRegs:$Rs32),
4245"$Rdd32 = convert_sf2d($Rs32):chop",
4246tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4247let Inst{13-5} = 0b000000110;
4248let Inst{31-21} = 0b10000100100;
4249let isFP = 1;
4250let Uses = [USR];
4251}
4252def F2_conv_sf2df : HInst<
4253(outs DoubleRegs:$Rdd32),
4254(ins IntRegs:$Rs32),
4255"$Rdd32 = convert_sf2df($Rs32)",
4256tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4257let Inst{13-5} = 0b000000000;
4258let Inst{31-21} = 0b10000100100;
4259let isFP = 1;
4260let Uses = [USR];
4261}
4262def F2_conv_sf2ud : HInst<
4263(outs DoubleRegs:$Rdd32),
4264(ins IntRegs:$Rs32),
4265"$Rdd32 = convert_sf2ud($Rs32)",
4266tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4267let Inst{13-5} = 0b000000011;
4268let Inst{31-21} = 0b10000100100;
4269let isFP = 1;
4270let Uses = [USR];
4271}
4272def F2_conv_sf2ud_chop : HInst<
4273(outs DoubleRegs:$Rdd32),
4274(ins IntRegs:$Rs32),
4275"$Rdd32 = convert_sf2ud($Rs32):chop",
4276tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4277let Inst{13-5} = 0b000000101;
4278let Inst{31-21} = 0b10000100100;
4279let isFP = 1;
4280let Uses = [USR];
4281}
4282def F2_conv_sf2uw : HInst<
4283(outs IntRegs:$Rd32),
4284(ins IntRegs:$Rs32),
4285"$Rd32 = convert_sf2uw($Rs32)",
4286tc_9783714b, TypeS_2op>, Enc_5e2823 {
4287let Inst{13-5} = 0b000000000;
4288let Inst{31-21} = 0b10001011011;
4289let hasNewValue = 1;
4290let opNewValue = 0;
4291let isFP = 1;
4292let Uses = [USR];
4293}
4294def F2_conv_sf2uw_chop : HInst<
4295(outs IntRegs:$Rd32),
4296(ins IntRegs:$Rs32),
4297"$Rd32 = convert_sf2uw($Rs32):chop",
4298tc_9783714b, TypeS_2op>, Enc_5e2823 {
4299let Inst{13-5} = 0b000000001;
4300let Inst{31-21} = 0b10001011011;
4301let hasNewValue = 1;
4302let opNewValue = 0;
4303let isFP = 1;
4304let Uses = [USR];
4305}
4306def F2_conv_sf2w : HInst<
4307(outs IntRegs:$Rd32),
4308(ins IntRegs:$Rs32),
4309"$Rd32 = convert_sf2w($Rs32)",
4310tc_9783714b, TypeS_2op>, Enc_5e2823 {
4311let Inst{13-5} = 0b000000000;
4312let Inst{31-21} = 0b10001011100;
4313let hasNewValue = 1;
4314let opNewValue = 0;
4315let isFP = 1;
4316let Uses = [USR];
4317}
4318def F2_conv_sf2w_chop : HInst<
4319(outs IntRegs:$Rd32),
4320(ins IntRegs:$Rs32),
4321"$Rd32 = convert_sf2w($Rs32):chop",
4322tc_9783714b, TypeS_2op>, Enc_5e2823 {
4323let Inst{13-5} = 0b000000001;
4324let Inst{31-21} = 0b10001011100;
4325let hasNewValue = 1;
4326let opNewValue = 0;
4327let isFP = 1;
4328let Uses = [USR];
4329}
4330def F2_conv_ud2df : HInst<
4331(outs DoubleRegs:$Rdd32),
4332(ins DoubleRegs:$Rss32),
4333"$Rdd32 = convert_ud2df($Rss32)",
4334tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4335let Inst{13-5} = 0b000000010;
4336let Inst{31-21} = 0b10000000111;
4337let isFP = 1;
4338let Uses = [USR];
4339}
4340def F2_conv_ud2sf : HInst<
4341(outs IntRegs:$Rd32),
4342(ins DoubleRegs:$Rss32),
4343"$Rd32 = convert_ud2sf($Rss32)",
4344tc_9783714b, TypeS_2op>, Enc_90cd8b {
4345let Inst{13-5} = 0b000000001;
4346let Inst{31-21} = 0b10001000001;
4347let hasNewValue = 1;
4348let opNewValue = 0;
4349let isFP = 1;
4350let Uses = [USR];
4351}
4352def F2_conv_uw2df : HInst<
4353(outs DoubleRegs:$Rdd32),
4354(ins IntRegs:$Rs32),
4355"$Rdd32 = convert_uw2df($Rs32)",
4356tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4357let Inst{13-5} = 0b000000001;
4358let Inst{31-21} = 0b10000100100;
4359let isFP = 1;
4360let Uses = [USR];
4361}
4362def F2_conv_uw2sf : HInst<
4363(outs IntRegs:$Rd32),
4364(ins IntRegs:$Rs32),
4365"$Rd32 = convert_uw2sf($Rs32)",
4366tc_9783714b, TypeS_2op>, Enc_5e2823 {
4367let Inst{13-5} = 0b000000000;
4368let Inst{31-21} = 0b10001011001;
4369let hasNewValue = 1;
4370let opNewValue = 0;
4371let isFP = 1;
4372let Uses = [USR];
4373}
4374def F2_conv_w2df : HInst<
4375(outs DoubleRegs:$Rdd32),
4376(ins IntRegs:$Rs32),
4377"$Rdd32 = convert_w2df($Rs32)",
4378tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4379let Inst{13-5} = 0b000000010;
4380let Inst{31-21} = 0b10000100100;
4381let isFP = 1;
4382let Uses = [USR];
4383}
4384def F2_conv_w2sf : HInst<
4385(outs IntRegs:$Rd32),
4386(ins IntRegs:$Rs32),
4387"$Rd32 = convert_w2sf($Rs32)",
4388tc_9783714b, TypeS_2op>, Enc_5e2823 {
4389let Inst{13-5} = 0b000000000;
4390let Inst{31-21} = 0b10001011010;
4391let hasNewValue = 1;
4392let opNewValue = 0;
4393let isFP = 1;
4394let Uses = [USR];
4395}
4396def F2_dfadd : HInst<
4397(outs DoubleRegs:$Rdd32),
4398(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4399"$Rdd32 = dfadd($Rss32,$Rtt32)",
4400tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4401let Inst{7-5} = 0b011;
4402let Inst{13-13} = 0b0;
4403let Inst{31-21} = 0b11101000000;
4404let isFP = 1;
4405let Uses = [USR];
4406}
4407def F2_dfclass : HInst<
4408(outs PredRegs:$Pd4),
4409(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
4410"$Pd4 = dfclass($Rss32,#$Ii)",
4411tc_a1297125, TypeALU64>, Enc_1f19b5 {
4412let Inst{4-2} = 0b100;
4413let Inst{13-10} = 0b0000;
4414let Inst{31-21} = 0b11011100100;
4415let isFP = 1;
4416let Uses = [USR];
4417}
4418def F2_dfcmpeq : HInst<
4419(outs PredRegs:$Pd4),
4420(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4421"$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
4422tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4423let Inst{7-2} = 0b000000;
4424let Inst{13-13} = 0b0;
4425let Inst{31-21} = 0b11010010111;
4426let isFP = 1;
4427let Uses = [USR];
4428let isCompare = 1;
4429}
4430def F2_dfcmpge : HInst<
4431(outs PredRegs:$Pd4),
4432(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4433"$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
4434tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4435let Inst{7-2} = 0b010000;
4436let Inst{13-13} = 0b0;
4437let Inst{31-21} = 0b11010010111;
4438let isFP = 1;
4439let Uses = [USR];
4440let isCompare = 1;
4441}
4442def F2_dfcmpgt : HInst<
4443(outs PredRegs:$Pd4),
4444(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4445"$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
4446tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4447let Inst{7-2} = 0b001000;
4448let Inst{13-13} = 0b0;
4449let Inst{31-21} = 0b11010010111;
4450let isFP = 1;
4451let Uses = [USR];
4452let isCompare = 1;
4453}
4454def F2_dfcmpuo : HInst<
4455(outs PredRegs:$Pd4),
4456(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4457"$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
4458tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4459let Inst{7-2} = 0b011000;
4460let Inst{13-13} = 0b0;
4461let Inst{31-21} = 0b11010010111;
4462let isFP = 1;
4463let Uses = [USR];
4464let isCompare = 1;
4465}
4466def F2_dfimm_n : HInst<
4467(outs DoubleRegs:$Rdd32),
4468(ins u10_0Imm:$Ii),
4469"$Rdd32 = dfmake(#$Ii):neg",
4470tc_65279839, TypeALU64>, Enc_e6c957 {
4471let Inst{20-16} = 0b00000;
4472let Inst{31-22} = 0b1101100101;
4473let prefersSlot3 = 1;
4474}
4475def F2_dfimm_p : HInst<
4476(outs DoubleRegs:$Rdd32),
4477(ins u10_0Imm:$Ii),
4478"$Rdd32 = dfmake(#$Ii):pos",
4479tc_65279839, TypeALU64>, Enc_e6c957 {
4480let Inst{20-16} = 0b00000;
4481let Inst{31-22} = 0b1101100100;
4482let prefersSlot3 = 1;
4483}
4484def F2_dfmax : HInst<
4485(outs DoubleRegs:$Rdd32),
4486(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4487"$Rdd32 = dfmax($Rss32,$Rtt32)",
4488tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4489let Inst{7-5} = 0b011;
4490let Inst{13-13} = 0b0;
4491let Inst{31-21} = 0b11101000001;
4492let isFP = 1;
4493let prefersSlot3 = 1;
4494let Uses = [USR];
4495}
4496def F2_dfmin : HInst<
4497(outs DoubleRegs:$Rdd32),
4498(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4499"$Rdd32 = dfmin($Rss32,$Rtt32)",
4500tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4501let Inst{7-5} = 0b011;
4502let Inst{13-13} = 0b0;
4503let Inst{31-21} = 0b11101000110;
4504let isFP = 1;
4505let prefersSlot3 = 1;
4506let Uses = [USR];
4507}
4508def F2_dfmpyfix : HInst<
4509(outs DoubleRegs:$Rdd32),
4510(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4511"$Rdd32 = dfmpyfix($Rss32,$Rtt32)",
4512tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> {
4513let Inst{7-5} = 0b011;
4514let Inst{13-13} = 0b0;
4515let Inst{31-21} = 0b11101000010;
4516let isFP = 1;
4517let Uses = [USR];
4518}
4519def F2_dfmpyhh : HInst<
4520(outs DoubleRegs:$Rxx32),
4521(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4522"$Rxx32 += dfmpyhh($Rss32,$Rtt32)",
4523tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4524let Inst{7-5} = 0b011;
4525let Inst{13-13} = 0b0;
4526let Inst{31-21} = 0b11101010100;
4527let isFP = 1;
4528let Uses = [USR];
4529let Constraints = "$Rxx32 = $Rxx32in";
4530}
4531def F2_dfmpylh : HInst<
4532(outs DoubleRegs:$Rxx32),
4533(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4534"$Rxx32 += dfmpylh($Rss32,$Rtt32)",
4535tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4536let Inst{7-5} = 0b011;
4537let Inst{13-13} = 0b0;
4538let Inst{31-21} = 0b11101010000;
4539let prefersSlot3 = 1;
4540let Constraints = "$Rxx32 = $Rxx32in";
4541}
4542def F2_dfmpyll : HInst<
4543(outs DoubleRegs:$Rdd32),
4544(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4545"$Rdd32 = dfmpyll($Rss32,$Rtt32)",
4546tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> {
4547let Inst{7-5} = 0b011;
4548let Inst{13-13} = 0b0;
4549let Inst{31-21} = 0b11101000101;
4550let prefersSlot3 = 1;
4551}
4552def F2_dfsub : HInst<
4553(outs DoubleRegs:$Rdd32),
4554(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4555"$Rdd32 = dfsub($Rss32,$Rtt32)",
4556tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4557let Inst{7-5} = 0b011;
4558let Inst{13-13} = 0b0;
4559let Inst{31-21} = 0b11101000100;
4560let isFP = 1;
4561let Uses = [USR];
4562}
4563def F2_sfadd : HInst<
4564(outs IntRegs:$Rd32),
4565(ins IntRegs:$Rs32, IntRegs:$Rt32),
4566"$Rd32 = sfadd($Rs32,$Rt32)",
4567tc_02fe1c65, TypeM>, Enc_5ab2be {
4568let Inst{7-5} = 0b000;
4569let Inst{13-13} = 0b0;
4570let Inst{31-21} = 0b11101011000;
4571let hasNewValue = 1;
4572let opNewValue = 0;
4573let isFP = 1;
4574let Uses = [USR];
4575let isCommutable = 1;
4576}
4577def F2_sfclass : HInst<
4578(outs PredRegs:$Pd4),
4579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
4580"$Pd4 = sfclass($Rs32,#$Ii)",
4581tc_a1297125, TypeS_2op>, Enc_83ee64 {
4582let Inst{7-2} = 0b000000;
4583let Inst{13-13} = 0b0;
4584let Inst{31-21} = 0b10000101111;
4585let isFP = 1;
4586let Uses = [USR];
4587}
4588def F2_sfcmpeq : HInst<
4589(outs PredRegs:$Pd4),
4590(ins IntRegs:$Rs32, IntRegs:$Rt32),
4591"$Pd4 = sfcmp.eq($Rs32,$Rt32)",
4592tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4593let Inst{7-2} = 0b011000;
4594let Inst{13-13} = 0b0;
4595let Inst{31-21} = 0b11000111111;
4596let isFP = 1;
4597let Uses = [USR];
4598let isCompare = 1;
4599}
4600def F2_sfcmpge : HInst<
4601(outs PredRegs:$Pd4),
4602(ins IntRegs:$Rs32, IntRegs:$Rt32),
4603"$Pd4 = sfcmp.ge($Rs32,$Rt32)",
4604tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4605let Inst{7-2} = 0b000000;
4606let Inst{13-13} = 0b0;
4607let Inst{31-21} = 0b11000111111;
4608let isFP = 1;
4609let Uses = [USR];
4610let isCompare = 1;
4611}
4612def F2_sfcmpgt : HInst<
4613(outs PredRegs:$Pd4),
4614(ins IntRegs:$Rs32, IntRegs:$Rt32),
4615"$Pd4 = sfcmp.gt($Rs32,$Rt32)",
4616tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4617let Inst{7-2} = 0b100000;
4618let Inst{13-13} = 0b0;
4619let Inst{31-21} = 0b11000111111;
4620let isFP = 1;
4621let Uses = [USR];
4622let isCompare = 1;
4623}
4624def F2_sfcmpuo : HInst<
4625(outs PredRegs:$Pd4),
4626(ins IntRegs:$Rs32, IntRegs:$Rt32),
4627"$Pd4 = sfcmp.uo($Rs32,$Rt32)",
4628tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4629let Inst{7-2} = 0b001000;
4630let Inst{13-13} = 0b0;
4631let Inst{31-21} = 0b11000111111;
4632let isFP = 1;
4633let Uses = [USR];
4634let isCompare = 1;
4635}
4636def F2_sffixupd : HInst<
4637(outs IntRegs:$Rd32),
4638(ins IntRegs:$Rs32, IntRegs:$Rt32),
4639"$Rd32 = sffixupd($Rs32,$Rt32)",
4640tc_02fe1c65, TypeM>, Enc_5ab2be {
4641let Inst{7-5} = 0b001;
4642let Inst{13-13} = 0b0;
4643let Inst{31-21} = 0b11101011110;
4644let hasNewValue = 1;
4645let opNewValue = 0;
4646let isFP = 1;
4647}
4648def F2_sffixupn : HInst<
4649(outs IntRegs:$Rd32),
4650(ins IntRegs:$Rs32, IntRegs:$Rt32),
4651"$Rd32 = sffixupn($Rs32,$Rt32)",
4652tc_02fe1c65, TypeM>, Enc_5ab2be {
4653let Inst{7-5} = 0b000;
4654let Inst{13-13} = 0b0;
4655let Inst{31-21} = 0b11101011110;
4656let hasNewValue = 1;
4657let opNewValue = 0;
4658let isFP = 1;
4659}
4660def F2_sffixupr : HInst<
4661(outs IntRegs:$Rd32),
4662(ins IntRegs:$Rs32),
4663"$Rd32 = sffixupr($Rs32)",
4664tc_9783714b, TypeS_2op>, Enc_5e2823 {
4665let Inst{13-5} = 0b000000000;
4666let Inst{31-21} = 0b10001011101;
4667let hasNewValue = 1;
4668let opNewValue = 0;
4669let isFP = 1;
4670}
4671def F2_sffma : HInst<
4672(outs IntRegs:$Rx32),
4673(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4674"$Rx32 += sfmpy($Rs32,$Rt32)",
4675tc_9e72dc89, TypeM>, Enc_2ae154 {
4676let Inst{7-5} = 0b100;
4677let Inst{13-13} = 0b0;
4678let Inst{31-21} = 0b11101111000;
4679let hasNewValue = 1;
4680let opNewValue = 0;
4681let isFP = 1;
4682let Uses = [USR];
4683let Constraints = "$Rx32 = $Rx32in";
4684}
4685def F2_sffma_lib : HInst<
4686(outs IntRegs:$Rx32),
4687(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4688"$Rx32 += sfmpy($Rs32,$Rt32):lib",
4689tc_9e72dc89, TypeM>, Enc_2ae154 {
4690let Inst{7-5} = 0b110;
4691let Inst{13-13} = 0b0;
4692let Inst{31-21} = 0b11101111000;
4693let hasNewValue = 1;
4694let opNewValue = 0;
4695let isFP = 1;
4696let Uses = [USR];
4697let Constraints = "$Rx32 = $Rx32in";
4698}
4699def F2_sffma_sc : HInst<
4700(outs IntRegs:$Rx32),
4701(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
4702"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
4703tc_9edb7c77, TypeM>, Enc_437f33 {
4704let Inst{7-7} = 0b1;
4705let Inst{13-13} = 0b0;
4706let Inst{31-21} = 0b11101111011;
4707let hasNewValue = 1;
4708let opNewValue = 0;
4709let isFP = 1;
4710let Uses = [USR];
4711let Constraints = "$Rx32 = $Rx32in";
4712}
4713def F2_sffms : HInst<
4714(outs IntRegs:$Rx32),
4715(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4716"$Rx32 -= sfmpy($Rs32,$Rt32)",
4717tc_9e72dc89, TypeM>, Enc_2ae154 {
4718let Inst{7-5} = 0b101;
4719let Inst{13-13} = 0b0;
4720let Inst{31-21} = 0b11101111000;
4721let hasNewValue = 1;
4722let opNewValue = 0;
4723let isFP = 1;
4724let Uses = [USR];
4725let Constraints = "$Rx32 = $Rx32in";
4726}
4727def F2_sffms_lib : HInst<
4728(outs IntRegs:$Rx32),
4729(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4730"$Rx32 -= sfmpy($Rs32,$Rt32):lib",
4731tc_9e72dc89, TypeM>, Enc_2ae154 {
4732let Inst{7-5} = 0b111;
4733let Inst{13-13} = 0b0;
4734let Inst{31-21} = 0b11101111000;
4735let hasNewValue = 1;
4736let opNewValue = 0;
4737let isFP = 1;
4738let Uses = [USR];
4739let Constraints = "$Rx32 = $Rx32in";
4740}
4741def F2_sfimm_n : HInst<
4742(outs IntRegs:$Rd32),
4743(ins u10_0Imm:$Ii),
4744"$Rd32 = sfmake(#$Ii):neg",
4745tc_65279839, TypeALU64>, Enc_6c9440 {
4746let Inst{20-16} = 0b00000;
4747let Inst{31-22} = 0b1101011001;
4748let hasNewValue = 1;
4749let opNewValue = 0;
4750let prefersSlot3 = 1;
4751}
4752def F2_sfimm_p : HInst<
4753(outs IntRegs:$Rd32),
4754(ins u10_0Imm:$Ii),
4755"$Rd32 = sfmake(#$Ii):pos",
4756tc_65279839, TypeALU64>, Enc_6c9440 {
4757let Inst{20-16} = 0b00000;
4758let Inst{31-22} = 0b1101011000;
4759let hasNewValue = 1;
4760let opNewValue = 0;
4761let prefersSlot3 = 1;
4762}
4763def F2_sfinvsqrta : HInst<
4764(outs IntRegs:$Rd32, PredRegs:$Pe4),
4765(ins IntRegs:$Rs32),
4766"$Rd32,$Pe4 = sfinvsqrta($Rs32)",
4767tc_7f7f45f5, TypeS_2op>, Enc_890909 {
4768let Inst{13-7} = 0b0000000;
4769let Inst{31-21} = 0b10001011111;
4770let hasNewValue = 1;
4771let opNewValue = 0;
4772let isFP = 1;
4773let isPredicateLate = 1;
4774}
4775def F2_sfmax : HInst<
4776(outs IntRegs:$Rd32),
4777(ins IntRegs:$Rs32, IntRegs:$Rt32),
4778"$Rd32 = sfmax($Rs32,$Rt32)",
4779tc_c20701f0, TypeM>, Enc_5ab2be {
4780let Inst{7-5} = 0b000;
4781let Inst{13-13} = 0b0;
4782let Inst{31-21} = 0b11101011100;
4783let hasNewValue = 1;
4784let opNewValue = 0;
4785let isFP = 1;
4786let prefersSlot3 = 1;
4787let Uses = [USR];
4788}
4789def F2_sfmin : HInst<
4790(outs IntRegs:$Rd32),
4791(ins IntRegs:$Rs32, IntRegs:$Rt32),
4792"$Rd32 = sfmin($Rs32,$Rt32)",
4793tc_c20701f0, TypeM>, Enc_5ab2be {
4794let Inst{7-5} = 0b001;
4795let Inst{13-13} = 0b0;
4796let Inst{31-21} = 0b11101011100;
4797let hasNewValue = 1;
4798let opNewValue = 0;
4799let isFP = 1;
4800let prefersSlot3 = 1;
4801let Uses = [USR];
4802}
4803def F2_sfmpy : HInst<
4804(outs IntRegs:$Rd32),
4805(ins IntRegs:$Rs32, IntRegs:$Rt32),
4806"$Rd32 = sfmpy($Rs32,$Rt32)",
4807tc_02fe1c65, TypeM>, Enc_5ab2be {
4808let Inst{7-5} = 0b000;
4809let Inst{13-13} = 0b0;
4810let Inst{31-21} = 0b11101011010;
4811let hasNewValue = 1;
4812let opNewValue = 0;
4813let isFP = 1;
4814let Uses = [USR];
4815let isCommutable = 1;
4816}
4817def F2_sfrecipa : HInst<
4818(outs IntRegs:$Rd32, PredRegs:$Pe4),
4819(ins IntRegs:$Rs32, IntRegs:$Rt32),
4820"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
4821tc_f7569068, TypeM>, Enc_a94f3b {
4822let Inst{7-7} = 0b1;
4823let Inst{13-13} = 0b0;
4824let Inst{31-21} = 0b11101011111;
4825let hasNewValue = 1;
4826let opNewValue = 0;
4827let isFP = 1;
4828let isPredicateLate = 1;
4829}
4830def F2_sfsub : HInst<
4831(outs IntRegs:$Rd32),
4832(ins IntRegs:$Rs32, IntRegs:$Rt32),
4833"$Rd32 = sfsub($Rs32,$Rt32)",
4834tc_02fe1c65, TypeM>, Enc_5ab2be {
4835let Inst{7-5} = 0b001;
4836let Inst{13-13} = 0b0;
4837let Inst{31-21} = 0b11101011000;
4838let hasNewValue = 1;
4839let opNewValue = 0;
4840let isFP = 1;
4841let Uses = [USR];
4842}
4843def G4_tfrgcpp : HInst<
4844(outs DoubleRegs:$Rdd32),
4845(ins GuestRegs64:$Gss32),
4846"$Rdd32 = $Gss32",
4847tc_fae9dfa5, TypeCR>, Enc_0aa344 {
4848let Inst{13-5} = 0b000000000;
4849let Inst{31-21} = 0b01101000001;
4850}
4851def G4_tfrgcrr : HInst<
4852(outs IntRegs:$Rd32),
4853(ins GuestRegs:$Gs32),
4854"$Rd32 = $Gs32",
4855tc_fae9dfa5, TypeCR>, Enc_44271f {
4856let Inst{13-5} = 0b000000000;
4857let Inst{31-21} = 0b01101010001;
4858let hasNewValue = 1;
4859let opNewValue = 0;
4860}
4861def G4_tfrgpcp : HInst<
4862(outs GuestRegs64:$Gdd32),
4863(ins DoubleRegs:$Rss32),
4864"$Gdd32 = $Rss32",
4865tc_6ae3426b, TypeCR>, Enc_ed5027 {
4866let Inst{13-5} = 0b000000000;
4867let Inst{31-21} = 0b01100011000;
4868let hasNewValue = 1;
4869let opNewValue = 0;
4870}
4871def G4_tfrgrcr : HInst<
4872(outs GuestRegs:$Gd32),
4873(ins IntRegs:$Rs32),
4874"$Gd32 = $Rs32",
4875tc_6ae3426b, TypeCR>, Enc_621fba {
4876let Inst{13-5} = 0b000000000;
4877let Inst{31-21} = 0b01100010000;
4878let hasNewValue = 1;
4879let opNewValue = 0;
4880}
4881def J2_call : HInst<
4882(outs),
4883(ins a30_2Imm:$Ii),
4884"call $Ii",
4885tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel {
4886let Inst{0-0} = 0b0;
4887let Inst{31-25} = 0b0101101;
4888let isCall = 1;
4889let prefersSlot3 = 1;
4890let cofRelax2 = 1;
4891let cofMax1 = 1;
4892let Uses = [R29];
4893let Defs = [PC, R31];
4894let BaseOpcode = "J2_call";
4895let isPredicable = 1;
4896let hasSideEffects = 1;
4897let isExtendable = 1;
4898let opExtendable = 0;
4899let isExtentSigned = 1;
4900let opExtentBits = 24;
4901let opExtentAlign = 2;
4902}
4903def J2_callf : HInst<
4904(outs),
4905(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4906"if (!$Pu4) call $Ii",
4907tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4908let Inst{0-0} = 0b0;
4909let Inst{12-10} = 0b000;
4910let Inst{21-21} = 0b1;
4911let Inst{31-24} = 0b01011101;
4912let isPredicated = 1;
4913let isPredicatedFalse = 1;
4914let isCall = 1;
4915let prefersSlot3 = 1;
4916let cofRelax1 = 1;
4917let cofRelax2 = 1;
4918let cofMax1 = 1;
4919let Uses = [R29];
4920let Defs = [PC, R31];
4921let BaseOpcode = "J2_call";
4922let hasSideEffects = 1;
4923let isTaken = Inst{12};
4924let isExtendable = 1;
4925let opExtendable = 1;
4926let isExtentSigned = 1;
4927let opExtentBits = 17;
4928let opExtentAlign = 2;
4929}
4930def J2_callr : HInst<
4931(outs),
4932(ins IntRegs:$Rs32),
4933"callr $Rs32",
4934tc_362b0be2, TypeJ>, Enc_ecbcc8 {
4935let Inst{13-0} = 0b00000000000000;
4936let Inst{31-21} = 0b01010000101;
4937let isCall = 1;
4938let prefersSlot3 = 1;
4939let cofMax1 = 1;
4940let Uses = [R29];
4941let Defs = [PC, R31];
4942let hasSideEffects = 1;
4943}
4944def J2_callrf : HInst<
4945(outs),
4946(ins PredRegs:$Pu4, IntRegs:$Rs32),
4947"if (!$Pu4) callr $Rs32",
4948tc_dc51281d, TypeJ>, Enc_88d4d9 {
4949let Inst{7-0} = 0b00000000;
4950let Inst{13-10} = 0b0000;
4951let Inst{31-21} = 0b01010001001;
4952let isPredicated = 1;
4953let isPredicatedFalse = 1;
4954let isCall = 1;
4955let prefersSlot3 = 1;
4956let cofMax1 = 1;
4957let Uses = [R29];
4958let Defs = [PC, R31];
4959let hasSideEffects = 1;
4960let isTaken = Inst{12};
4961}
4962def J2_callrt : HInst<
4963(outs),
4964(ins PredRegs:$Pu4, IntRegs:$Rs32),
4965"if ($Pu4) callr $Rs32",
4966tc_dc51281d, TypeJ>, Enc_88d4d9 {
4967let Inst{7-0} = 0b00000000;
4968let Inst{13-10} = 0b0000;
4969let Inst{31-21} = 0b01010001000;
4970let isPredicated = 1;
4971let isCall = 1;
4972let prefersSlot3 = 1;
4973let cofMax1 = 1;
4974let Uses = [R29];
4975let Defs = [PC, R31];
4976let hasSideEffects = 1;
4977let isTaken = Inst{12};
4978}
4979def J2_callt : HInst<
4980(outs),
4981(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4982"if ($Pu4) call $Ii",
4983tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4984let Inst{0-0} = 0b0;
4985let Inst{12-10} = 0b000;
4986let Inst{21-21} = 0b0;
4987let Inst{31-24} = 0b01011101;
4988let isPredicated = 1;
4989let isCall = 1;
4990let prefersSlot3 = 1;
4991let cofRelax1 = 1;
4992let cofRelax2 = 1;
4993let cofMax1 = 1;
4994let Uses = [R29];
4995let Defs = [PC, R31];
4996let BaseOpcode = "J2_call";
4997let hasSideEffects = 1;
4998let isTaken = Inst{12};
4999let isExtendable = 1;
5000let opExtendable = 1;
5001let isExtentSigned = 1;
5002let opExtentBits = 17;
5003let opExtentAlign = 2;
5004}
5005def J2_endloop0 : HInst<
5006(outs),
5007(ins),
5008"endloop0",
5009tc_23708a21, TypeJ> {
5010let Uses = [LC0, SA0];
5011let Defs = [LC0, P3, PC, USR];
5012let isBranch = 1;
5013let isTerminator = 1;
5014let isPseudo = 1;
5015}
5016def J2_endloop01 : HInst<
5017(outs),
5018(ins),
5019"endloop01",
5020tc_23708a21, TypeJ> {
5021let Uses = [LC0, LC1, SA0, SA1];
5022let Defs = [LC0, LC1, P3, PC, USR];
5023let isPseudo = 1;
5024}
5025def J2_endloop1 : HInst<
5026(outs),
5027(ins),
5028"endloop1",
5029tc_23708a21, TypeJ> {
5030let Uses = [LC1, SA1];
5031let Defs = [LC1, PC];
5032let isBranch = 1;
5033let isTerminator = 1;
5034let isPseudo = 1;
5035}
5036def J2_jump : HInst<
5037(outs),
5038(ins b30_2Imm:$Ii),
5039"jump $Ii",
5040tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel {
5041let Inst{0-0} = 0b0;
5042let Inst{31-25} = 0b0101100;
5043let isTerminator = 1;
5044let isBranch = 1;
5045let cofRelax2 = 1;
5046let cofMax1 = 1;
5047let Defs = [PC];
5048let BaseOpcode = "J2_jump";
5049let InputType = "imm";
5050let isBarrier = 1;
5051let isPredicable = 1;
5052let isExtendable = 1;
5053let opExtendable = 0;
5054let isExtentSigned = 1;
5055let opExtentBits = 24;
5056let opExtentAlign = 2;
5057}
5058def J2_jumpf : HInst<
5059(outs),
5060(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5061"if (!$Pu4) jump:nt $Ii",
5062tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5063let Inst{0-0} = 0b0;
5064let Inst{12-10} = 0b000;
5065let Inst{21-21} = 0b1;
5066let Inst{31-24} = 0b01011100;
5067let isPredicated = 1;
5068let isPredicatedFalse = 1;
5069let isTerminator = 1;
5070let isBranch = 1;
5071let cofRelax1 = 1;
5072let cofRelax2 = 1;
5073let cofMax1 = 1;
5074let Defs = [PC];
5075let BaseOpcode = "J2_jump";
5076let InputType = "imm";
5077let isTaken = Inst{12};
5078let isExtendable = 1;
5079let opExtendable = 1;
5080let isExtentSigned = 1;
5081let opExtentBits = 17;
5082let opExtentAlign = 2;
5083}
5084def J2_jumpf_nopred_map : HInst<
5085(outs),
5086(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5087"if (!$Pu4) jump $Ii",
5088tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5089let isPseudo = 1;
5090let isCodeGenOnly = 1;
5091}
5092def J2_jumpfnew : HInst<
5093(outs),
5094(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5095"if (!$Pu4.new) jump:nt $Ii",
5096tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5097let Inst{0-0} = 0b0;
5098let Inst{12-10} = 0b010;
5099let Inst{21-21} = 0b1;
5100let Inst{31-24} = 0b01011100;
5101let isPredicated = 1;
5102let isPredicatedFalse = 1;
5103let isTerminator = 1;
5104let isBranch = 1;
5105let isPredicatedNew = 1;
5106let cofRelax1 = 1;
5107let cofRelax2 = 1;
5108let cofMax1 = 1;
5109let Defs = [PC];
5110let BaseOpcode = "J2_jump";
5111let InputType = "imm";
5112let isTaken = Inst{12};
5113let isExtendable = 1;
5114let opExtendable = 1;
5115let isExtentSigned = 1;
5116let opExtentBits = 17;
5117let opExtentAlign = 2;
5118}
5119def J2_jumpfnewpt : HInst<
5120(outs),
5121(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5122"if (!$Pu4.new) jump:t $Ii",
5123tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5124let Inst{0-0} = 0b0;
5125let Inst{12-10} = 0b110;
5126let Inst{21-21} = 0b1;
5127let Inst{31-24} = 0b01011100;
5128let isPredicated = 1;
5129let isPredicatedFalse = 1;
5130let isTerminator = 1;
5131let isBranch = 1;
5132let isPredicatedNew = 1;
5133let cofRelax1 = 1;
5134let cofRelax2 = 1;
5135let cofMax1 = 1;
5136let Defs = [PC];
5137let BaseOpcode = "J2_jump";
5138let InputType = "imm";
5139let isTaken = Inst{12};
5140let isExtendable = 1;
5141let opExtendable = 1;
5142let isExtentSigned = 1;
5143let opExtentBits = 17;
5144let opExtentAlign = 2;
5145}
5146def J2_jumpfpt : HInst<
5147(outs),
5148(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5149"if (!$Pu4) jump:t $Ii",
5150tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5151let Inst{0-0} = 0b0;
5152let Inst{12-10} = 0b100;
5153let Inst{21-21} = 0b1;
5154let Inst{31-24} = 0b01011100;
5155let isPredicated = 1;
5156let isPredicatedFalse = 1;
5157let isTerminator = 1;
5158let isBranch = 1;
5159let cofRelax1 = 1;
5160let cofRelax2 = 1;
5161let cofMax1 = 1;
5162let Defs = [PC];
5163let BaseOpcode = "J2_jump";
5164let InputType = "imm";
5165let isTaken = Inst{12};
5166let isExtendable = 1;
5167let opExtendable = 1;
5168let isExtentSigned = 1;
5169let opExtentBits = 17;
5170let opExtentAlign = 2;
5171}
5172def J2_jumpr : HInst<
5173(outs),
5174(ins IntRegs:$Rs32),
5175"jumpr $Rs32",
5176tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel {
5177let Inst{13-0} = 0b00000000000000;
5178let Inst{31-21} = 0b01010010100;
5179let isTerminator = 1;
5180let isIndirectBranch = 1;
5181let isBranch = 1;
5182let cofMax1 = 1;
5183let Defs = [PC];
5184let BaseOpcode = "J2_jumpr";
5185let InputType = "reg";
5186let isBarrier = 1;
5187let isPredicable = 1;
5188}
5189def J2_jumprf : HInst<
5190(outs),
5191(ins PredRegs:$Pu4, IntRegs:$Rs32),
5192"if (!$Pu4) jumpr:nt $Rs32",
5193tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5194let Inst{7-0} = 0b00000000;
5195let Inst{13-10} = 0b0000;
5196let Inst{31-21} = 0b01010011011;
5197let isPredicated = 1;
5198let isPredicatedFalse = 1;
5199let isTerminator = 1;
5200let isIndirectBranch = 1;
5201let isBranch = 1;
5202let cofMax1 = 1;
5203let Defs = [PC];
5204let BaseOpcode = "J2_jumpr";
5205let InputType = "reg";
5206let isTaken = Inst{12};
5207}
5208def J2_jumprf_nopred_map : HInst<
5209(outs),
5210(ins PredRegs:$Pu4, IntRegs:$Rs32),
5211"if (!$Pu4) jumpr $Rs32",
5212tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5213let isPseudo = 1;
5214let isCodeGenOnly = 1;
5215}
5216def J2_jumprfnew : HInst<
5217(outs),
5218(ins PredRegs:$Pu4, IntRegs:$Rs32),
5219"if (!$Pu4.new) jumpr:nt $Rs32",
5220tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5221let Inst{7-0} = 0b00000000;
5222let Inst{13-10} = 0b0010;
5223let Inst{31-21} = 0b01010011011;
5224let isPredicated = 1;
5225let isPredicatedFalse = 1;
5226let isTerminator = 1;
5227let isIndirectBranch = 1;
5228let isBranch = 1;
5229let isPredicatedNew = 1;
5230let cofMax1 = 1;
5231let Defs = [PC];
5232let BaseOpcode = "J2_jumpr";
5233let InputType = "reg";
5234let isTaken = Inst{12};
5235}
5236def J2_jumprfnewpt : HInst<
5237(outs),
5238(ins PredRegs:$Pu4, IntRegs:$Rs32),
5239"if (!$Pu4.new) jumpr:t $Rs32",
5240tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5241let Inst{7-0} = 0b00000000;
5242let Inst{13-10} = 0b0110;
5243let Inst{31-21} = 0b01010011011;
5244let isPredicated = 1;
5245let isPredicatedFalse = 1;
5246let isTerminator = 1;
5247let isIndirectBranch = 1;
5248let isBranch = 1;
5249let isPredicatedNew = 1;
5250let cofMax1 = 1;
5251let Defs = [PC];
5252let BaseOpcode = "J2_jumpr";
5253let InputType = "reg";
5254let isTaken = Inst{12};
5255}
5256def J2_jumprfpt : HInst<
5257(outs),
5258(ins PredRegs:$Pu4, IntRegs:$Rs32),
5259"if (!$Pu4) jumpr:t $Rs32",
5260tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5261let Inst{7-0} = 0b00000000;
5262let Inst{13-10} = 0b0100;
5263let Inst{31-21} = 0b01010011011;
5264let isPredicated = 1;
5265let isPredicatedFalse = 1;
5266let isTerminator = 1;
5267let isIndirectBranch = 1;
5268let isBranch = 1;
5269let cofMax1 = 1;
5270let Defs = [PC];
5271let BaseOpcode = "J2_jumpr";
5272let InputType = "reg";
5273let isTaken = Inst{12};
5274}
5275def J2_jumprgtez : HInst<
5276(outs),
5277(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5278"if ($Rs32>=#0) jump:nt $Ii",
5279tc_57a55b54, TypeCR>, Enc_0fa531 {
5280let Inst{0-0} = 0b0;
5281let Inst{12-12} = 0b0;
5282let Inst{31-22} = 0b0110000101;
5283let isPredicated = 1;
5284let isTerminator = 1;
5285let isBranch = 1;
5286let isPredicatedNew = 1;
5287let cofRelax1 = 1;
5288let cofRelax2 = 1;
5289let cofMax1 = 1;
5290let Defs = [PC];
5291let isTaken = Inst{12};
5292}
5293def J2_jumprgtezpt : HInst<
5294(outs),
5295(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5296"if ($Rs32>=#0) jump:t $Ii",
5297tc_57a55b54, TypeCR>, Enc_0fa531 {
5298let Inst{0-0} = 0b0;
5299let Inst{12-12} = 0b1;
5300let Inst{31-22} = 0b0110000101;
5301let isPredicated = 1;
5302let isTerminator = 1;
5303let isBranch = 1;
5304let isPredicatedNew = 1;
5305let cofRelax1 = 1;
5306let cofRelax2 = 1;
5307let cofMax1 = 1;
5308let Defs = [PC];
5309let isTaken = Inst{12};
5310}
5311def J2_jumprltez : HInst<
5312(outs),
5313(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5314"if ($Rs32<=#0) jump:nt $Ii",
5315tc_57a55b54, TypeCR>, Enc_0fa531 {
5316let Inst{0-0} = 0b0;
5317let Inst{12-12} = 0b0;
5318let Inst{31-22} = 0b0110000111;
5319let isPredicated = 1;
5320let isTerminator = 1;
5321let isBranch = 1;
5322let isPredicatedNew = 1;
5323let cofRelax1 = 1;
5324let cofRelax2 = 1;
5325let cofMax1 = 1;
5326let Defs = [PC];
5327let isTaken = Inst{12};
5328}
5329def J2_jumprltezpt : HInst<
5330(outs),
5331(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5332"if ($Rs32<=#0) jump:t $Ii",
5333tc_57a55b54, TypeCR>, Enc_0fa531 {
5334let Inst{0-0} = 0b0;
5335let Inst{12-12} = 0b1;
5336let Inst{31-22} = 0b0110000111;
5337let isPredicated = 1;
5338let isTerminator = 1;
5339let isBranch = 1;
5340let isPredicatedNew = 1;
5341let cofRelax1 = 1;
5342let cofRelax2 = 1;
5343let cofMax1 = 1;
5344let Defs = [PC];
5345let isTaken = Inst{12};
5346}
5347def J2_jumprnz : HInst<
5348(outs),
5349(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5350"if ($Rs32==#0) jump:nt $Ii",
5351tc_57a55b54, TypeCR>, Enc_0fa531 {
5352let Inst{0-0} = 0b0;
5353let Inst{12-12} = 0b0;
5354let Inst{31-22} = 0b0110000110;
5355let isPredicated = 1;
5356let isTerminator = 1;
5357let isBranch = 1;
5358let isPredicatedNew = 1;
5359let cofRelax1 = 1;
5360let cofRelax2 = 1;
5361let cofMax1 = 1;
5362let Defs = [PC];
5363let isTaken = Inst{12};
5364}
5365def J2_jumprnzpt : HInst<
5366(outs),
5367(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5368"if ($Rs32==#0) jump:t $Ii",
5369tc_57a55b54, TypeCR>, Enc_0fa531 {
5370let Inst{0-0} = 0b0;
5371let Inst{12-12} = 0b1;
5372let Inst{31-22} = 0b0110000110;
5373let isPredicated = 1;
5374let isTerminator = 1;
5375let isBranch = 1;
5376let isPredicatedNew = 1;
5377let cofRelax1 = 1;
5378let cofRelax2 = 1;
5379let cofMax1 = 1;
5380let Defs = [PC];
5381let isTaken = Inst{12};
5382}
5383def J2_jumprt : HInst<
5384(outs),
5385(ins PredRegs:$Pu4, IntRegs:$Rs32),
5386"if ($Pu4) jumpr:nt $Rs32",
5387tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5388let Inst{7-0} = 0b00000000;
5389let Inst{13-10} = 0b0000;
5390let Inst{31-21} = 0b01010011010;
5391let isPredicated = 1;
5392let isTerminator = 1;
5393let isIndirectBranch = 1;
5394let isBranch = 1;
5395let cofMax1 = 1;
5396let Defs = [PC];
5397let BaseOpcode = "J2_jumpr";
5398let InputType = "reg";
5399let isTaken = Inst{12};
5400}
5401def J2_jumprt_nopred_map : HInst<
5402(outs),
5403(ins PredRegs:$Pu4, IntRegs:$Rs32),
5404"if ($Pu4) jumpr $Rs32",
5405tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5406let isPseudo = 1;
5407let isCodeGenOnly = 1;
5408}
5409def J2_jumprtnew : HInst<
5410(outs),
5411(ins PredRegs:$Pu4, IntRegs:$Rs32),
5412"if ($Pu4.new) jumpr:nt $Rs32",
5413tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5414let Inst{7-0} = 0b00000000;
5415let Inst{13-10} = 0b0010;
5416let Inst{31-21} = 0b01010011010;
5417let isPredicated = 1;
5418let isTerminator = 1;
5419let isIndirectBranch = 1;
5420let isBranch = 1;
5421let isPredicatedNew = 1;
5422let cofMax1 = 1;
5423let Defs = [PC];
5424let BaseOpcode = "J2_jumpr";
5425let InputType = "reg";
5426let isTaken = Inst{12};
5427}
5428def J2_jumprtnewpt : HInst<
5429(outs),
5430(ins PredRegs:$Pu4, IntRegs:$Rs32),
5431"if ($Pu4.new) jumpr:t $Rs32",
5432tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5433let Inst{7-0} = 0b00000000;
5434let Inst{13-10} = 0b0110;
5435let Inst{31-21} = 0b01010011010;
5436let isPredicated = 1;
5437let isTerminator = 1;
5438let isIndirectBranch = 1;
5439let isBranch = 1;
5440let isPredicatedNew = 1;
5441let cofMax1 = 1;
5442let Defs = [PC];
5443let BaseOpcode = "J2_jumpr";
5444let InputType = "reg";
5445let isTaken = Inst{12};
5446}
5447def J2_jumprtpt : HInst<
5448(outs),
5449(ins PredRegs:$Pu4, IntRegs:$Rs32),
5450"if ($Pu4) jumpr:t $Rs32",
5451tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5452let Inst{7-0} = 0b00000000;
5453let Inst{13-10} = 0b0100;
5454let Inst{31-21} = 0b01010011010;
5455let isPredicated = 1;
5456let isTerminator = 1;
5457let isIndirectBranch = 1;
5458let isBranch = 1;
5459let cofMax1 = 1;
5460let Defs = [PC];
5461let BaseOpcode = "J2_jumpr";
5462let InputType = "reg";
5463let isTaken = Inst{12};
5464}
5465def J2_jumprz : HInst<
5466(outs),
5467(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5468"if ($Rs32!=#0) jump:nt $Ii",
5469tc_57a55b54, TypeCR>, Enc_0fa531 {
5470let Inst{0-0} = 0b0;
5471let Inst{12-12} = 0b0;
5472let Inst{31-22} = 0b0110000100;
5473let isPredicated = 1;
5474let isTerminator = 1;
5475let isBranch = 1;
5476let isPredicatedNew = 1;
5477let cofRelax1 = 1;
5478let cofRelax2 = 1;
5479let cofMax1 = 1;
5480let Defs = [PC];
5481let isTaken = Inst{12};
5482}
5483def J2_jumprzpt : HInst<
5484(outs),
5485(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5486"if ($Rs32!=#0) jump:t $Ii",
5487tc_57a55b54, TypeCR>, Enc_0fa531 {
5488let Inst{0-0} = 0b0;
5489let Inst{12-12} = 0b1;
5490let Inst{31-22} = 0b0110000100;
5491let isPredicated = 1;
5492let isTerminator = 1;
5493let isBranch = 1;
5494let isPredicatedNew = 1;
5495let cofRelax1 = 1;
5496let cofRelax2 = 1;
5497let cofMax1 = 1;
5498let Defs = [PC];
5499let isTaken = Inst{12};
5500}
5501def J2_jumpt : HInst<
5502(outs),
5503(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5504"if ($Pu4) jump:nt $Ii",
5505tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5506let Inst{0-0} = 0b0;
5507let Inst{12-10} = 0b000;
5508let Inst{21-21} = 0b0;
5509let Inst{31-24} = 0b01011100;
5510let isPredicated = 1;
5511let isTerminator = 1;
5512let isBranch = 1;
5513let cofRelax1 = 1;
5514let cofRelax2 = 1;
5515let cofMax1 = 1;
5516let Defs = [PC];
5517let BaseOpcode = "J2_jump";
5518let InputType = "imm";
5519let isTaken = Inst{12};
5520let isExtendable = 1;
5521let opExtendable = 1;
5522let isExtentSigned = 1;
5523let opExtentBits = 17;
5524let opExtentAlign = 2;
5525}
5526def J2_jumpt_nopred_map : HInst<
5527(outs),
5528(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5529"if ($Pu4) jump $Ii",
5530tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5531let isPseudo = 1;
5532let isCodeGenOnly = 1;
5533}
5534def J2_jumptnew : HInst<
5535(outs),
5536(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5537"if ($Pu4.new) jump:nt $Ii",
5538tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5539let Inst{0-0} = 0b0;
5540let Inst{12-10} = 0b010;
5541let Inst{21-21} = 0b0;
5542let Inst{31-24} = 0b01011100;
5543let isPredicated = 1;
5544let isTerminator = 1;
5545let isBranch = 1;
5546let isPredicatedNew = 1;
5547let cofRelax1 = 1;
5548let cofRelax2 = 1;
5549let cofMax1 = 1;
5550let Defs = [PC];
5551let BaseOpcode = "J2_jump";
5552let InputType = "imm";
5553let isTaken = Inst{12};
5554let isExtendable = 1;
5555let opExtendable = 1;
5556let isExtentSigned = 1;
5557let opExtentBits = 17;
5558let opExtentAlign = 2;
5559}
5560def J2_jumptnewpt : HInst<
5561(outs),
5562(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5563"if ($Pu4.new) jump:t $Ii",
5564tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5565let Inst{0-0} = 0b0;
5566let Inst{12-10} = 0b110;
5567let Inst{21-21} = 0b0;
5568let Inst{31-24} = 0b01011100;
5569let isPredicated = 1;
5570let isTerminator = 1;
5571let isBranch = 1;
5572let isPredicatedNew = 1;
5573let cofRelax1 = 1;
5574let cofRelax2 = 1;
5575let cofMax1 = 1;
5576let Defs = [PC];
5577let BaseOpcode = "J2_jump";
5578let InputType = "imm";
5579let isTaken = Inst{12};
5580let isExtendable = 1;
5581let opExtendable = 1;
5582let isExtentSigned = 1;
5583let opExtentBits = 17;
5584let opExtentAlign = 2;
5585}
5586def J2_jumptpt : HInst<
5587(outs),
5588(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5589"if ($Pu4) jump:t $Ii",
5590tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5591let Inst{0-0} = 0b0;
5592let Inst{12-10} = 0b100;
5593let Inst{21-21} = 0b0;
5594let Inst{31-24} = 0b01011100;
5595let isPredicated = 1;
5596let isTerminator = 1;
5597let isBranch = 1;
5598let cofRelax1 = 1;
5599let cofRelax2 = 1;
5600let cofMax1 = 1;
5601let Defs = [PC];
5602let BaseOpcode = "J2_jump";
5603let InputType = "imm";
5604let isTaken = Inst{12};
5605let isExtendable = 1;
5606let opExtendable = 1;
5607let isExtentSigned = 1;
5608let opExtentBits = 17;
5609let opExtentAlign = 2;
5610}
5611def J2_loop0i : HInst<
5612(outs),
5613(ins b30_2Imm:$Ii, u10_0Imm:$II),
5614"loop0($Ii,#$II)",
5615tc_1248597c, TypeCR>, Enc_4dc228 {
5616let Inst{2-2} = 0b0;
5617let Inst{13-13} = 0b0;
5618let Inst{31-21} = 0b01101001000;
5619let cofRelax1 = 1;
5620let cofRelax2 = 1;
5621let Defs = [LC0, SA0, USR];
5622let isExtendable = 1;
5623let opExtendable = 0;
5624let isExtentSigned = 1;
5625let opExtentBits = 9;
5626let opExtentAlign = 2;
5627}
5628def J2_loop0r : HInst<
5629(outs),
5630(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5631"loop0($Ii,$Rs32)",
5632tc_9406230a, TypeCR>, Enc_864a5a {
5633let Inst{2-0} = 0b000;
5634let Inst{7-5} = 0b000;
5635let Inst{13-13} = 0b0;
5636let Inst{31-21} = 0b01100000000;
5637let cofRelax1 = 1;
5638let cofRelax2 = 1;
5639let Defs = [LC0, SA0, USR];
5640let isExtendable = 1;
5641let opExtendable = 0;
5642let isExtentSigned = 1;
5643let opExtentBits = 9;
5644let opExtentAlign = 2;
5645}
5646def J2_loop1i : HInst<
5647(outs),
5648(ins b30_2Imm:$Ii, u10_0Imm:$II),
5649"loop1($Ii,#$II)",
5650tc_1248597c, TypeCR>, Enc_4dc228 {
5651let Inst{2-2} = 0b0;
5652let Inst{13-13} = 0b0;
5653let Inst{31-21} = 0b01101001001;
5654let cofRelax1 = 1;
5655let cofRelax2 = 1;
5656let Defs = [LC1, SA1];
5657let isExtendable = 1;
5658let opExtendable = 0;
5659let isExtentSigned = 1;
5660let opExtentBits = 9;
5661let opExtentAlign = 2;
5662}
5663def J2_loop1r : HInst<
5664(outs),
5665(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5666"loop1($Ii,$Rs32)",
5667tc_9406230a, TypeCR>, Enc_864a5a {
5668let Inst{2-0} = 0b000;
5669let Inst{7-5} = 0b000;
5670let Inst{13-13} = 0b0;
5671let Inst{31-21} = 0b01100000001;
5672let cofRelax1 = 1;
5673let cofRelax2 = 1;
5674let Defs = [LC1, SA1];
5675let isExtendable = 1;
5676let opExtendable = 0;
5677let isExtentSigned = 1;
5678let opExtentBits = 9;
5679let opExtentAlign = 2;
5680}
5681def J2_pause : HInst<
5682(outs),
5683(ins u8_0Imm:$Ii),
5684"pause(#$Ii)",
5685tc_d57d649c, TypeJ>, Enc_a51a9a {
5686let Inst{1-0} = 0b00;
5687let Inst{7-5} = 0b000;
5688let Inst{13-13} = 0b0;
5689let Inst{31-16} = 0b0101010001000000;
5690let isSolo = 1;
5691}
5692def J2_ploop1si : HInst<
5693(outs),
5694(ins b30_2Imm:$Ii, u10_0Imm:$II),
5695"p3 = sp1loop0($Ii,#$II)",
5696tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5697let Inst{2-2} = 0b0;
5698let Inst{13-13} = 0b0;
5699let Inst{31-21} = 0b01101001101;
5700let isPredicateLate = 1;
5701let cofRelax1 = 1;
5702let cofRelax2 = 1;
5703let Defs = [LC0, P3, SA0, USR];
5704let isExtendable = 1;
5705let opExtendable = 0;
5706let isExtentSigned = 1;
5707let opExtentBits = 9;
5708let opExtentAlign = 2;
5709}
5710def J2_ploop1sr : HInst<
5711(outs),
5712(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5713"p3 = sp1loop0($Ii,$Rs32)",
5714tc_6d861a95, TypeCR>, Enc_864a5a {
5715let Inst{2-0} = 0b000;
5716let Inst{7-5} = 0b000;
5717let Inst{13-13} = 0b0;
5718let Inst{31-21} = 0b01100000101;
5719let isPredicateLate = 1;
5720let cofRelax1 = 1;
5721let cofRelax2 = 1;
5722let Defs = [LC0, P3, SA0, USR];
5723let isExtendable = 1;
5724let opExtendable = 0;
5725let isExtentSigned = 1;
5726let opExtentBits = 9;
5727let opExtentAlign = 2;
5728}
5729def J2_ploop2si : HInst<
5730(outs),
5731(ins b30_2Imm:$Ii, u10_0Imm:$II),
5732"p3 = sp2loop0($Ii,#$II)",
5733tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5734let Inst{2-2} = 0b0;
5735let Inst{13-13} = 0b0;
5736let Inst{31-21} = 0b01101001110;
5737let isPredicateLate = 1;
5738let cofRelax1 = 1;
5739let cofRelax2 = 1;
5740let Defs = [LC0, P3, SA0, USR];
5741let isExtendable = 1;
5742let opExtendable = 0;
5743let isExtentSigned = 1;
5744let opExtentBits = 9;
5745let opExtentAlign = 2;
5746}
5747def J2_ploop2sr : HInst<
5748(outs),
5749(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5750"p3 = sp2loop0($Ii,$Rs32)",
5751tc_6d861a95, TypeCR>, Enc_864a5a {
5752let Inst{2-0} = 0b000;
5753let Inst{7-5} = 0b000;
5754let Inst{13-13} = 0b0;
5755let Inst{31-21} = 0b01100000110;
5756let isPredicateLate = 1;
5757let cofRelax1 = 1;
5758let cofRelax2 = 1;
5759let Defs = [LC0, P3, SA0, USR];
5760let isExtendable = 1;
5761let opExtendable = 0;
5762let isExtentSigned = 1;
5763let opExtentBits = 9;
5764let opExtentAlign = 2;
5765}
5766def J2_ploop3si : HInst<
5767(outs),
5768(ins b30_2Imm:$Ii, u10_0Imm:$II),
5769"p3 = sp3loop0($Ii,#$II)",
5770tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5771let Inst{2-2} = 0b0;
5772let Inst{13-13} = 0b0;
5773let Inst{31-21} = 0b01101001111;
5774let isPredicateLate = 1;
5775let cofRelax1 = 1;
5776let cofRelax2 = 1;
5777let Defs = [LC0, P3, SA0, USR];
5778let isExtendable = 1;
5779let opExtendable = 0;
5780let isExtentSigned = 1;
5781let opExtentBits = 9;
5782let opExtentAlign = 2;
5783}
5784def J2_ploop3sr : HInst<
5785(outs),
5786(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5787"p3 = sp3loop0($Ii,$Rs32)",
5788tc_6d861a95, TypeCR>, Enc_864a5a {
5789let Inst{2-0} = 0b000;
5790let Inst{7-5} = 0b000;
5791let Inst{13-13} = 0b0;
5792let Inst{31-21} = 0b01100000111;
5793let isPredicateLate = 1;
5794let cofRelax1 = 1;
5795let cofRelax2 = 1;
5796let Defs = [LC0, P3, SA0, USR];
5797let isExtendable = 1;
5798let opExtendable = 0;
5799let isExtentSigned = 1;
5800let opExtentBits = 9;
5801let opExtentAlign = 2;
5802}
5803def J2_trap0 : HInst<
5804(outs),
5805(ins u8_0Imm:$Ii),
5806"trap0(#$Ii)",
5807tc_45f9d1be, TypeJ>, Enc_a51a9a {
5808let Inst{1-0} = 0b00;
5809let Inst{7-5} = 0b000;
5810let Inst{13-13} = 0b0;
5811let Inst{31-16} = 0b0101010000000000;
5812let isSolo = 1;
5813let hasSideEffects = 1;
5814}
5815def J2_trap1 : HInst<
5816(outs IntRegs:$Rx32),
5817(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
5818"trap1($Rx32,#$Ii)",
5819tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> {
5820let Inst{1-0} = 0b00;
5821let Inst{7-5} = 0b000;
5822let Inst{13-13} = 0b0;
5823let Inst{31-21} = 0b01010100100;
5824let hasNewValue = 1;
5825let opNewValue = 0;
5826let isSolo = 1;
5827let Uses = [GOSP];
5828let Defs = [GOSP, PC];
5829let hasSideEffects = 1;
5830let Constraints = "$Rx32 = $Rx32in";
5831}
5832def J2_trap1_noregmap : HInst<
5833(outs),
5834(ins u8_0Imm:$Ii),
5835"trap1(#$Ii)",
5836tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> {
5837let hasSideEffects = 1;
5838let isPseudo = 1;
5839let isCodeGenOnly = 1;
5840}
5841def J4_cmpeq_f_jumpnv_nt : HInst<
5842(outs),
5843(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5844"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5845tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5846let Inst{0-0} = 0b0;
5847let Inst{13-13} = 0b0;
5848let Inst{19-19} = 0b0;
5849let Inst{31-22} = 0b0010000001;
5850let isPredicated = 1;
5851let isPredicatedFalse = 1;
5852let isTerminator = 1;
5853let isBranch = 1;
5854let isNewValue = 1;
5855let cofMax1 = 1;
5856let isRestrictNoSlot1Store = 1;
5857let Defs = [PC];
5858let BaseOpcode = "J4_cmpeqr";
5859let isTaken = Inst{13};
5860let isExtendable = 1;
5861let opExtendable = 2;
5862let isExtentSigned = 1;
5863let opExtentBits = 11;
5864let opExtentAlign = 2;
5865let opNewValue = 0;
5866}
5867def J4_cmpeq_f_jumpnv_t : HInst<
5868(outs),
5869(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5870"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5871tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5872let Inst{0-0} = 0b0;
5873let Inst{13-13} = 0b1;
5874let Inst{19-19} = 0b0;
5875let Inst{31-22} = 0b0010000001;
5876let isPredicated = 1;
5877let isPredicatedFalse = 1;
5878let isTerminator = 1;
5879let isBranch = 1;
5880let isNewValue = 1;
5881let cofMax1 = 1;
5882let isRestrictNoSlot1Store = 1;
5883let Defs = [PC];
5884let BaseOpcode = "J4_cmpeqr";
5885let isTaken = Inst{13};
5886let isExtendable = 1;
5887let opExtendable = 2;
5888let isExtentSigned = 1;
5889let opExtentBits = 11;
5890let opExtentAlign = 2;
5891let opNewValue = 0;
5892}
5893def J4_cmpeq_fp0_jump_nt : HInst<
5894(outs),
5895(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5896"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
5897tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5898let Inst{0-0} = 0b0;
5899let Inst{13-12} = 0b00;
5900let Inst{31-22} = 0b0001010001;
5901let isPredicated = 1;
5902let isPredicatedFalse = 1;
5903let isTerminator = 1;
5904let isBranch = 1;
5905let isPredicatedNew = 1;
5906let cofRelax1 = 1;
5907let cofRelax2 = 1;
5908let cofMax1 = 1;
5909let Uses = [P0];
5910let Defs = [P0, PC];
5911let BaseOpcode = "J4_cmpeqp0";
5912let isTaken = Inst{13};
5913let isExtendable = 1;
5914let opExtendable = 2;
5915let isExtentSigned = 1;
5916let opExtentBits = 11;
5917let opExtentAlign = 2;
5918}
5919def J4_cmpeq_fp0_jump_t : HInst<
5920(outs),
5921(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5922"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
5923tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5924let Inst{0-0} = 0b0;
5925let Inst{13-12} = 0b10;
5926let Inst{31-22} = 0b0001010001;
5927let isPredicated = 1;
5928let isPredicatedFalse = 1;
5929let isTerminator = 1;
5930let isBranch = 1;
5931let isPredicatedNew = 1;
5932let cofRelax1 = 1;
5933let cofRelax2 = 1;
5934let cofMax1 = 1;
5935let Uses = [P0];
5936let Defs = [P0, PC];
5937let BaseOpcode = "J4_cmpeqp0";
5938let isTaken = Inst{13};
5939let isExtendable = 1;
5940let opExtendable = 2;
5941let isExtentSigned = 1;
5942let opExtentBits = 11;
5943let opExtentAlign = 2;
5944}
5945def J4_cmpeq_fp1_jump_nt : HInst<
5946(outs),
5947(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5948"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
5949tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5950let Inst{0-0} = 0b0;
5951let Inst{13-12} = 0b01;
5952let Inst{31-22} = 0b0001010001;
5953let isPredicated = 1;
5954let isPredicatedFalse = 1;
5955let isTerminator = 1;
5956let isBranch = 1;
5957let isPredicatedNew = 1;
5958let cofRelax1 = 1;
5959let cofRelax2 = 1;
5960let cofMax1 = 1;
5961let Uses = [P1];
5962let Defs = [P1, PC];
5963let BaseOpcode = "J4_cmpeqp1";
5964let isTaken = Inst{13};
5965let isExtendable = 1;
5966let opExtendable = 2;
5967let isExtentSigned = 1;
5968let opExtentBits = 11;
5969let opExtentAlign = 2;
5970}
5971def J4_cmpeq_fp1_jump_t : HInst<
5972(outs),
5973(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5974"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
5975tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5976let Inst{0-0} = 0b0;
5977let Inst{13-12} = 0b11;
5978let Inst{31-22} = 0b0001010001;
5979let isPredicated = 1;
5980let isPredicatedFalse = 1;
5981let isTerminator = 1;
5982let isBranch = 1;
5983let isPredicatedNew = 1;
5984let cofRelax1 = 1;
5985let cofRelax2 = 1;
5986let cofMax1 = 1;
5987let Uses = [P1];
5988let Defs = [P1, PC];
5989let BaseOpcode = "J4_cmpeqp1";
5990let isTaken = Inst{13};
5991let isExtendable = 1;
5992let opExtendable = 2;
5993let isExtentSigned = 1;
5994let opExtentBits = 11;
5995let opExtentAlign = 2;
5996}
5997def J4_cmpeq_t_jumpnv_nt : HInst<
5998(outs),
5999(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6000"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
6001tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6002let Inst{0-0} = 0b0;
6003let Inst{13-13} = 0b0;
6004let Inst{19-19} = 0b0;
6005let Inst{31-22} = 0b0010000000;
6006let isPredicated = 1;
6007let isTerminator = 1;
6008let isBranch = 1;
6009let isNewValue = 1;
6010let cofMax1 = 1;
6011let isRestrictNoSlot1Store = 1;
6012let Defs = [PC];
6013let BaseOpcode = "J4_cmpeqr";
6014let isTaken = Inst{13};
6015let isExtendable = 1;
6016let opExtendable = 2;
6017let isExtentSigned = 1;
6018let opExtentBits = 11;
6019let opExtentAlign = 2;
6020let opNewValue = 0;
6021}
6022def J4_cmpeq_t_jumpnv_t : HInst<
6023(outs),
6024(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6025"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
6026tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6027let Inst{0-0} = 0b0;
6028let Inst{13-13} = 0b1;
6029let Inst{19-19} = 0b0;
6030let Inst{31-22} = 0b0010000000;
6031let isPredicated = 1;
6032let isTerminator = 1;
6033let isBranch = 1;
6034let isNewValue = 1;
6035let cofMax1 = 1;
6036let isRestrictNoSlot1Store = 1;
6037let Defs = [PC];
6038let BaseOpcode = "J4_cmpeqr";
6039let isTaken = Inst{13};
6040let isExtendable = 1;
6041let opExtendable = 2;
6042let isExtentSigned = 1;
6043let opExtentBits = 11;
6044let opExtentAlign = 2;
6045let opNewValue = 0;
6046}
6047def J4_cmpeq_tp0_jump_nt : HInst<
6048(outs),
6049(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6050"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6051tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6052let Inst{0-0} = 0b0;
6053let Inst{13-12} = 0b00;
6054let Inst{31-22} = 0b0001010000;
6055let isPredicated = 1;
6056let isTerminator = 1;
6057let isBranch = 1;
6058let isPredicatedNew = 1;
6059let cofRelax1 = 1;
6060let cofRelax2 = 1;
6061let cofMax1 = 1;
6062let Uses = [P0];
6063let Defs = [P0, PC];
6064let BaseOpcode = "J4_cmpeqp0";
6065let isTaken = Inst{13};
6066let isExtendable = 1;
6067let opExtendable = 2;
6068let isExtentSigned = 1;
6069let opExtentBits = 11;
6070let opExtentAlign = 2;
6071}
6072def J4_cmpeq_tp0_jump_t : HInst<
6073(outs),
6074(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6075"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6076tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6077let Inst{0-0} = 0b0;
6078let Inst{13-12} = 0b10;
6079let Inst{31-22} = 0b0001010000;
6080let isPredicated = 1;
6081let isTerminator = 1;
6082let isBranch = 1;
6083let isPredicatedNew = 1;
6084let cofRelax1 = 1;
6085let cofRelax2 = 1;
6086let cofMax1 = 1;
6087let Uses = [P0];
6088let Defs = [P0, PC];
6089let BaseOpcode = "J4_cmpeqp0";
6090let isTaken = Inst{13};
6091let isExtendable = 1;
6092let opExtendable = 2;
6093let isExtentSigned = 1;
6094let opExtentBits = 11;
6095let opExtentAlign = 2;
6096}
6097def J4_cmpeq_tp1_jump_nt : HInst<
6098(outs),
6099(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6100"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
6101tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6102let Inst{0-0} = 0b0;
6103let Inst{13-12} = 0b01;
6104let Inst{31-22} = 0b0001010000;
6105let isPredicated = 1;
6106let isTerminator = 1;
6107let isBranch = 1;
6108let isPredicatedNew = 1;
6109let cofRelax1 = 1;
6110let cofRelax2 = 1;
6111let cofMax1 = 1;
6112let Uses = [P1];
6113let Defs = [P1, PC];
6114let BaseOpcode = "J4_cmpeqp1";
6115let isTaken = Inst{13};
6116let isExtendable = 1;
6117let opExtendable = 2;
6118let isExtentSigned = 1;
6119let opExtentBits = 11;
6120let opExtentAlign = 2;
6121}
6122def J4_cmpeq_tp1_jump_t : HInst<
6123(outs),
6124(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6125"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6126tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6127let Inst{0-0} = 0b0;
6128let Inst{13-12} = 0b11;
6129let Inst{31-22} = 0b0001010000;
6130let isPredicated = 1;
6131let isTerminator = 1;
6132let isBranch = 1;
6133let isPredicatedNew = 1;
6134let cofRelax1 = 1;
6135let cofRelax2 = 1;
6136let cofMax1 = 1;
6137let Uses = [P1];
6138let Defs = [P1, PC];
6139let BaseOpcode = "J4_cmpeqp1";
6140let isTaken = Inst{13};
6141let isExtendable = 1;
6142let opExtendable = 2;
6143let isExtentSigned = 1;
6144let opExtentBits = 11;
6145let opExtentAlign = 2;
6146}
6147def J4_cmpeqi_f_jumpnv_nt : HInst<
6148(outs),
6149(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6150"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6151tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6152let Inst{0-0} = 0b0;
6153let Inst{13-13} = 0b0;
6154let Inst{19-19} = 0b0;
6155let Inst{31-22} = 0b0010010001;
6156let isPredicated = 1;
6157let isPredicatedFalse = 1;
6158let isTerminator = 1;
6159let isBranch = 1;
6160let isNewValue = 1;
6161let cofMax1 = 1;
6162let isRestrictNoSlot1Store = 1;
6163let Defs = [PC];
6164let BaseOpcode = "J4_cmpeqi";
6165let isTaken = Inst{13};
6166let isExtendable = 1;
6167let opExtendable = 2;
6168let isExtentSigned = 1;
6169let opExtentBits = 11;
6170let opExtentAlign = 2;
6171let opNewValue = 0;
6172}
6173def J4_cmpeqi_f_jumpnv_t : HInst<
6174(outs),
6175(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6176"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6177tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6178let Inst{0-0} = 0b0;
6179let Inst{13-13} = 0b1;
6180let Inst{19-19} = 0b0;
6181let Inst{31-22} = 0b0010010001;
6182let isPredicated = 1;
6183let isPredicatedFalse = 1;
6184let isTerminator = 1;
6185let isBranch = 1;
6186let isNewValue = 1;
6187let cofMax1 = 1;
6188let isRestrictNoSlot1Store = 1;
6189let Defs = [PC];
6190let BaseOpcode = "J4_cmpeqi";
6191let isTaken = Inst{13};
6192let isExtendable = 1;
6193let opExtendable = 2;
6194let isExtentSigned = 1;
6195let opExtentBits = 11;
6196let opExtentAlign = 2;
6197let opNewValue = 0;
6198}
6199def J4_cmpeqi_fp0_jump_nt : HInst<
6200(outs),
6201(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6202"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
6203tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6204let Inst{0-0} = 0b0;
6205let Inst{13-13} = 0b0;
6206let Inst{31-22} = 0b0001000001;
6207let isPredicated = 1;
6208let isPredicatedFalse = 1;
6209let isTerminator = 1;
6210let isBranch = 1;
6211let isPredicatedNew = 1;
6212let cofRelax1 = 1;
6213let cofRelax2 = 1;
6214let cofMax1 = 1;
6215let Uses = [P0];
6216let Defs = [P0, PC];
6217let BaseOpcode = "J4_cmpeqip0";
6218let isTaken = Inst{13};
6219let isExtendable = 1;
6220let opExtendable = 2;
6221let isExtentSigned = 1;
6222let opExtentBits = 11;
6223let opExtentAlign = 2;
6224}
6225def J4_cmpeqi_fp0_jump_t : HInst<
6226(outs),
6227(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6228"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
6229tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6230let Inst{0-0} = 0b0;
6231let Inst{13-13} = 0b1;
6232let Inst{31-22} = 0b0001000001;
6233let isPredicated = 1;
6234let isPredicatedFalse = 1;
6235let isTerminator = 1;
6236let isBranch = 1;
6237let isPredicatedNew = 1;
6238let cofRelax1 = 1;
6239let cofRelax2 = 1;
6240let cofMax1 = 1;
6241let Uses = [P0];
6242let Defs = [P0, PC];
6243let BaseOpcode = "J4_cmpeqip0";
6244let isTaken = Inst{13};
6245let isExtendable = 1;
6246let opExtendable = 2;
6247let isExtentSigned = 1;
6248let opExtentBits = 11;
6249let opExtentAlign = 2;
6250}
6251def J4_cmpeqi_fp1_jump_nt : HInst<
6252(outs),
6253(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6254"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6255tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6256let Inst{0-0} = 0b0;
6257let Inst{13-13} = 0b0;
6258let Inst{31-22} = 0b0001001001;
6259let isPredicated = 1;
6260let isPredicatedFalse = 1;
6261let isTerminator = 1;
6262let isBranch = 1;
6263let isPredicatedNew = 1;
6264let cofRelax1 = 1;
6265let cofRelax2 = 1;
6266let cofMax1 = 1;
6267let Uses = [P1];
6268let Defs = [P1, PC];
6269let BaseOpcode = "J4_cmpeqip1";
6270let isTaken = Inst{13};
6271let isExtendable = 1;
6272let opExtendable = 2;
6273let isExtentSigned = 1;
6274let opExtentBits = 11;
6275let opExtentAlign = 2;
6276}
6277def J4_cmpeqi_fp1_jump_t : HInst<
6278(outs),
6279(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6280"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
6281tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6282let Inst{0-0} = 0b0;
6283let Inst{13-13} = 0b1;
6284let Inst{31-22} = 0b0001001001;
6285let isPredicated = 1;
6286let isPredicatedFalse = 1;
6287let isTerminator = 1;
6288let isBranch = 1;
6289let isPredicatedNew = 1;
6290let cofRelax1 = 1;
6291let cofRelax2 = 1;
6292let cofMax1 = 1;
6293let Uses = [P1];
6294let Defs = [P1, PC];
6295let BaseOpcode = "J4_cmpeqip1";
6296let isTaken = Inst{13};
6297let isExtendable = 1;
6298let opExtendable = 2;
6299let isExtentSigned = 1;
6300let opExtentBits = 11;
6301let opExtentAlign = 2;
6302}
6303def J4_cmpeqi_t_jumpnv_nt : HInst<
6304(outs),
6305(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6306"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6307tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6308let Inst{0-0} = 0b0;
6309let Inst{13-13} = 0b0;
6310let Inst{19-19} = 0b0;
6311let Inst{31-22} = 0b0010010000;
6312let isPredicated = 1;
6313let isTerminator = 1;
6314let isBranch = 1;
6315let isNewValue = 1;
6316let cofMax1 = 1;
6317let isRestrictNoSlot1Store = 1;
6318let Defs = [PC];
6319let BaseOpcode = "J4_cmpeqi";
6320let isTaken = Inst{13};
6321let isExtendable = 1;
6322let opExtendable = 2;
6323let isExtentSigned = 1;
6324let opExtentBits = 11;
6325let opExtentAlign = 2;
6326let opNewValue = 0;
6327}
6328def J4_cmpeqi_t_jumpnv_t : HInst<
6329(outs),
6330(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6331"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6332tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6333let Inst{0-0} = 0b0;
6334let Inst{13-13} = 0b1;
6335let Inst{19-19} = 0b0;
6336let Inst{31-22} = 0b0010010000;
6337let isPredicated = 1;
6338let isTerminator = 1;
6339let isBranch = 1;
6340let isNewValue = 1;
6341let cofMax1 = 1;
6342let isRestrictNoSlot1Store = 1;
6343let Defs = [PC];
6344let BaseOpcode = "J4_cmpeqi";
6345let isTaken = Inst{13};
6346let isExtendable = 1;
6347let opExtendable = 2;
6348let isExtentSigned = 1;
6349let opExtentBits = 11;
6350let opExtentAlign = 2;
6351let opNewValue = 0;
6352}
6353def J4_cmpeqi_tp0_jump_nt : HInst<
6354(outs),
6355(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6356"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
6357tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6358let Inst{0-0} = 0b0;
6359let Inst{13-13} = 0b0;
6360let Inst{31-22} = 0b0001000000;
6361let isPredicated = 1;
6362let isTerminator = 1;
6363let isBranch = 1;
6364let isPredicatedNew = 1;
6365let cofRelax1 = 1;
6366let cofRelax2 = 1;
6367let cofMax1 = 1;
6368let Uses = [P0];
6369let Defs = [P0, PC];
6370let BaseOpcode = "J4_cmpeqip0";
6371let isTaken = Inst{13};
6372let isExtendable = 1;
6373let opExtendable = 2;
6374let isExtentSigned = 1;
6375let opExtentBits = 11;
6376let opExtentAlign = 2;
6377}
6378def J4_cmpeqi_tp0_jump_t : HInst<
6379(outs),
6380(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6381"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
6382tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6383let Inst{0-0} = 0b0;
6384let Inst{13-13} = 0b1;
6385let Inst{31-22} = 0b0001000000;
6386let isPredicated = 1;
6387let isTerminator = 1;
6388let isBranch = 1;
6389let isPredicatedNew = 1;
6390let cofRelax1 = 1;
6391let cofRelax2 = 1;
6392let cofMax1 = 1;
6393let Uses = [P0];
6394let Defs = [P0, PC];
6395let BaseOpcode = "J4_cmpeqip0";
6396let isTaken = Inst{13};
6397let isExtendable = 1;
6398let opExtendable = 2;
6399let isExtentSigned = 1;
6400let opExtentBits = 11;
6401let opExtentAlign = 2;
6402}
6403def J4_cmpeqi_tp1_jump_nt : HInst<
6404(outs),
6405(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6406"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
6407tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6408let Inst{0-0} = 0b0;
6409let Inst{13-13} = 0b0;
6410let Inst{31-22} = 0b0001001000;
6411let isPredicated = 1;
6412let isTerminator = 1;
6413let isBranch = 1;
6414let isPredicatedNew = 1;
6415let cofRelax1 = 1;
6416let cofRelax2 = 1;
6417let cofMax1 = 1;
6418let Uses = [P1];
6419let Defs = [P1, PC];
6420let BaseOpcode = "J4_cmpeqip1";
6421let isTaken = Inst{13};
6422let isExtendable = 1;
6423let opExtendable = 2;
6424let isExtentSigned = 1;
6425let opExtentBits = 11;
6426let opExtentAlign = 2;
6427}
6428def J4_cmpeqi_tp1_jump_t : HInst<
6429(outs),
6430(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6431"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
6432tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6433let Inst{0-0} = 0b0;
6434let Inst{13-13} = 0b1;
6435let Inst{31-22} = 0b0001001000;
6436let isPredicated = 1;
6437let isTerminator = 1;
6438let isBranch = 1;
6439let isPredicatedNew = 1;
6440let cofRelax1 = 1;
6441let cofRelax2 = 1;
6442let cofMax1 = 1;
6443let Uses = [P1];
6444let Defs = [P1, PC];
6445let BaseOpcode = "J4_cmpeqip1";
6446let isTaken = Inst{13};
6447let isExtendable = 1;
6448let opExtendable = 2;
6449let isExtentSigned = 1;
6450let opExtentBits = 11;
6451let opExtentAlign = 2;
6452}
6453def J4_cmpeqn1_f_jumpnv_nt : HInst<
6454(outs),
6455(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6456"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6457tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel {
6458let Inst{0-0} = 0b0;
6459let Inst{13-8} = 0b000000;
6460let Inst{19-19} = 0b0;
6461let Inst{31-22} = 0b0010011001;
6462let isPredicated = 1;
6463let isPredicatedFalse = 1;
6464let isTerminator = 1;
6465let isBranch = 1;
6466let isNewValue = 1;
6467let cofMax1 = 1;
6468let isRestrictNoSlot1Store = 1;
6469let Defs = [PC];
6470let BaseOpcode = "J4_cmpeqn1r";
6471let isTaken = Inst{13};
6472let isExtendable = 1;
6473let opExtendable = 2;
6474let isExtentSigned = 1;
6475let opExtentBits = 11;
6476let opExtentAlign = 2;
6477let opNewValue = 0;
6478}
6479def J4_cmpeqn1_f_jumpnv_t : HInst<
6480(outs),
6481(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6482"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6483tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel {
6484let Inst{0-0} = 0b0;
6485let Inst{13-8} = 0b100000;
6486let Inst{19-19} = 0b0;
6487let Inst{31-22} = 0b0010011001;
6488let isPredicated = 1;
6489let isPredicatedFalse = 1;
6490let isTerminator = 1;
6491let isBranch = 1;
6492let isNewValue = 1;
6493let cofMax1 = 1;
6494let isRestrictNoSlot1Store = 1;
6495let Defs = [PC];
6496let BaseOpcode = "J4_cmpeqn1r";
6497let isTaken = Inst{13};
6498let isExtendable = 1;
6499let opExtendable = 2;
6500let isExtentSigned = 1;
6501let opExtentBits = 11;
6502let opExtentAlign = 2;
6503let opNewValue = 0;
6504}
6505def J4_cmpeqn1_fp0_jump_nt : HInst<
6506(outs),
6507(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6508"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
6509tc_24f426ab, TypeCJ>, Enc_1de724, PredRel {
6510let Inst{0-0} = 0b0;
6511let Inst{13-8} = 0b000000;
6512let Inst{31-22} = 0b0001000111;
6513let isPredicated = 1;
6514let isPredicatedFalse = 1;
6515let isTerminator = 1;
6516let isBranch = 1;
6517let isPredicatedNew = 1;
6518let cofRelax1 = 1;
6519let cofRelax2 = 1;
6520let cofMax1 = 1;
6521let Uses = [P0];
6522let Defs = [P0, PC];
6523let BaseOpcode = "J4_cmpeqn1p0";
6524let isTaken = Inst{13};
6525let isExtendable = 1;
6526let opExtendable = 2;
6527let isExtentSigned = 1;
6528let opExtentBits = 11;
6529let opExtentAlign = 2;
6530}
6531def J4_cmpeqn1_fp0_jump_t : HInst<
6532(outs),
6533(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6534"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
6535tc_24f426ab, TypeCJ>, Enc_14640c, PredRel {
6536let Inst{0-0} = 0b0;
6537let Inst{13-8} = 0b100000;
6538let Inst{31-22} = 0b0001000111;
6539let isPredicated = 1;
6540let isPredicatedFalse = 1;
6541let isTerminator = 1;
6542let isBranch = 1;
6543let isPredicatedNew = 1;
6544let cofRelax1 = 1;
6545let cofRelax2 = 1;
6546let cofMax1 = 1;
6547let Uses = [P0];
6548let Defs = [P0, PC];
6549let BaseOpcode = "J4_cmpeqn1p0";
6550let isTaken = Inst{13};
6551let isExtendable = 1;
6552let opExtendable = 2;
6553let isExtentSigned = 1;
6554let opExtentBits = 11;
6555let opExtentAlign = 2;
6556}
6557def J4_cmpeqn1_fp1_jump_nt : HInst<
6558(outs),
6559(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6560"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
6561tc_24f426ab, TypeCJ>, Enc_668704, PredRel {
6562let Inst{0-0} = 0b0;
6563let Inst{13-8} = 0b000000;
6564let Inst{31-22} = 0b0001001111;
6565let isPredicated = 1;
6566let isPredicatedFalse = 1;
6567let isTerminator = 1;
6568let isBranch = 1;
6569let isPredicatedNew = 1;
6570let cofRelax1 = 1;
6571let cofRelax2 = 1;
6572let cofMax1 = 1;
6573let Uses = [P1];
6574let Defs = [P1, PC];
6575let BaseOpcode = "J4_cmpeqn1p1";
6576let isTaken = Inst{13};
6577let isExtendable = 1;
6578let opExtendable = 2;
6579let isExtentSigned = 1;
6580let opExtentBits = 11;
6581let opExtentAlign = 2;
6582}
6583def J4_cmpeqn1_fp1_jump_t : HInst<
6584(outs),
6585(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6586"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
6587tc_24f426ab, TypeCJ>, Enc_800e04, PredRel {
6588let Inst{0-0} = 0b0;
6589let Inst{13-8} = 0b100000;
6590let Inst{31-22} = 0b0001001111;
6591let isPredicated = 1;
6592let isPredicatedFalse = 1;
6593let isTerminator = 1;
6594let isBranch = 1;
6595let isPredicatedNew = 1;
6596let cofRelax1 = 1;
6597let cofRelax2 = 1;
6598let cofMax1 = 1;
6599let Uses = [P1];
6600let Defs = [P1, PC];
6601let BaseOpcode = "J4_cmpeqn1p1";
6602let isTaken = Inst{13};
6603let isExtendable = 1;
6604let opExtendable = 2;
6605let isExtentSigned = 1;
6606let opExtentBits = 11;
6607let opExtentAlign = 2;
6608}
6609def J4_cmpeqn1_t_jumpnv_nt : HInst<
6610(outs),
6611(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6612"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6613tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel {
6614let Inst{0-0} = 0b0;
6615let Inst{13-8} = 0b000000;
6616let Inst{19-19} = 0b0;
6617let Inst{31-22} = 0b0010011000;
6618let isPredicated = 1;
6619let isTerminator = 1;
6620let isBranch = 1;
6621let isNewValue = 1;
6622let cofMax1 = 1;
6623let isRestrictNoSlot1Store = 1;
6624let Defs = [PC];
6625let BaseOpcode = "J4_cmpeqn1r";
6626let isTaken = Inst{13};
6627let isExtendable = 1;
6628let opExtendable = 2;
6629let isExtentSigned = 1;
6630let opExtentBits = 11;
6631let opExtentAlign = 2;
6632let opNewValue = 0;
6633}
6634def J4_cmpeqn1_t_jumpnv_t : HInst<
6635(outs),
6636(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6637"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6638tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel {
6639let Inst{0-0} = 0b0;
6640let Inst{13-8} = 0b100000;
6641let Inst{19-19} = 0b0;
6642let Inst{31-22} = 0b0010011000;
6643let isPredicated = 1;
6644let isTerminator = 1;
6645let isBranch = 1;
6646let isNewValue = 1;
6647let cofMax1 = 1;
6648let isRestrictNoSlot1Store = 1;
6649let Defs = [PC];
6650let BaseOpcode = "J4_cmpeqn1r";
6651let isTaken = Inst{13};
6652let isExtendable = 1;
6653let opExtendable = 2;
6654let isExtentSigned = 1;
6655let opExtentBits = 11;
6656let opExtentAlign = 2;
6657let opNewValue = 0;
6658}
6659def J4_cmpeqn1_tp0_jump_nt : HInst<
6660(outs),
6661(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6662"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
6663tc_24f426ab, TypeCJ>, Enc_405228, PredRel {
6664let Inst{0-0} = 0b0;
6665let Inst{13-8} = 0b000000;
6666let Inst{31-22} = 0b0001000110;
6667let isPredicated = 1;
6668let isTerminator = 1;
6669let isBranch = 1;
6670let isPredicatedNew = 1;
6671let cofRelax1 = 1;
6672let cofRelax2 = 1;
6673let cofMax1 = 1;
6674let Uses = [P0];
6675let Defs = [P0, PC];
6676let BaseOpcode = "J4_cmpeqn1p0";
6677let isTaken = Inst{13};
6678let isExtendable = 1;
6679let opExtendable = 2;
6680let isExtentSigned = 1;
6681let opExtentBits = 11;
6682let opExtentAlign = 2;
6683}
6684def J4_cmpeqn1_tp0_jump_t : HInst<
6685(outs),
6686(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6687"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
6688tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel {
6689let Inst{0-0} = 0b0;
6690let Inst{13-8} = 0b100000;
6691let Inst{31-22} = 0b0001000110;
6692let isPredicated = 1;
6693let isTerminator = 1;
6694let isBranch = 1;
6695let isPredicatedNew = 1;
6696let cofRelax1 = 1;
6697let cofRelax2 = 1;
6698let cofMax1 = 1;
6699let Uses = [P0];
6700let Defs = [P0, PC];
6701let BaseOpcode = "J4_cmpeqn1p0";
6702let isTaken = Inst{13};
6703let isExtendable = 1;
6704let opExtendable = 2;
6705let isExtentSigned = 1;
6706let opExtentBits = 11;
6707let opExtentAlign = 2;
6708}
6709def J4_cmpeqn1_tp1_jump_nt : HInst<
6710(outs),
6711(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6712"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
6713tc_24f426ab, TypeCJ>, Enc_736575, PredRel {
6714let Inst{0-0} = 0b0;
6715let Inst{13-8} = 0b000000;
6716let Inst{31-22} = 0b0001001110;
6717let isPredicated = 1;
6718let isTerminator = 1;
6719let isBranch = 1;
6720let isPredicatedNew = 1;
6721let cofRelax1 = 1;
6722let cofRelax2 = 1;
6723let cofMax1 = 1;
6724let Uses = [P1];
6725let Defs = [P1, PC];
6726let BaseOpcode = "J4_cmpeqn1p1";
6727let isTaken = Inst{13};
6728let isExtendable = 1;
6729let opExtendable = 2;
6730let isExtentSigned = 1;
6731let opExtentBits = 11;
6732let opExtentAlign = 2;
6733}
6734def J4_cmpeqn1_tp1_jump_t : HInst<
6735(outs),
6736(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6737"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
6738tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel {
6739let Inst{0-0} = 0b0;
6740let Inst{13-8} = 0b100000;
6741let Inst{31-22} = 0b0001001110;
6742let isPredicated = 1;
6743let isTerminator = 1;
6744let isBranch = 1;
6745let isPredicatedNew = 1;
6746let cofRelax1 = 1;
6747let cofRelax2 = 1;
6748let cofMax1 = 1;
6749let Uses = [P1];
6750let Defs = [P1, PC];
6751let BaseOpcode = "J4_cmpeqn1p1";
6752let isTaken = Inst{13};
6753let isExtendable = 1;
6754let opExtendable = 2;
6755let isExtentSigned = 1;
6756let opExtentBits = 11;
6757let opExtentAlign = 2;
6758}
6759def J4_cmpgt_f_jumpnv_nt : HInst<
6760(outs),
6761(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6762"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6763tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6764let Inst{0-0} = 0b0;
6765let Inst{13-13} = 0b0;
6766let Inst{19-19} = 0b0;
6767let Inst{31-22} = 0b0010000011;
6768let isPredicated = 1;
6769let isPredicatedFalse = 1;
6770let isTerminator = 1;
6771let isBranch = 1;
6772let isNewValue = 1;
6773let cofMax1 = 1;
6774let isRestrictNoSlot1Store = 1;
6775let Defs = [PC];
6776let BaseOpcode = "J4_cmpgtr";
6777let isTaken = Inst{13};
6778let isExtendable = 1;
6779let opExtendable = 2;
6780let isExtentSigned = 1;
6781let opExtentBits = 11;
6782let opExtentAlign = 2;
6783let opNewValue = 0;
6784}
6785def J4_cmpgt_f_jumpnv_t : HInst<
6786(outs),
6787(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6788"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6789tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6790let Inst{0-0} = 0b0;
6791let Inst{13-13} = 0b1;
6792let Inst{19-19} = 0b0;
6793let Inst{31-22} = 0b0010000011;
6794let isPredicated = 1;
6795let isPredicatedFalse = 1;
6796let isTerminator = 1;
6797let isBranch = 1;
6798let isNewValue = 1;
6799let cofMax1 = 1;
6800let isRestrictNoSlot1Store = 1;
6801let Defs = [PC];
6802let BaseOpcode = "J4_cmpgtr";
6803let isTaken = Inst{13};
6804let isExtendable = 1;
6805let opExtendable = 2;
6806let isExtentSigned = 1;
6807let opExtentBits = 11;
6808let opExtentAlign = 2;
6809let opNewValue = 0;
6810}
6811def J4_cmpgt_fp0_jump_nt : HInst<
6812(outs),
6813(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6814"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
6815tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6816let Inst{0-0} = 0b0;
6817let Inst{13-12} = 0b00;
6818let Inst{31-22} = 0b0001010011;
6819let isPredicated = 1;
6820let isPredicatedFalse = 1;
6821let isTerminator = 1;
6822let isBranch = 1;
6823let isPredicatedNew = 1;
6824let cofRelax1 = 1;
6825let cofRelax2 = 1;
6826let cofMax1 = 1;
6827let Uses = [P0];
6828let Defs = [P0, PC];
6829let BaseOpcode = "J4_cmpgtp0";
6830let isTaken = Inst{13};
6831let isExtendable = 1;
6832let opExtendable = 2;
6833let isExtentSigned = 1;
6834let opExtentBits = 11;
6835let opExtentAlign = 2;
6836}
6837def J4_cmpgt_fp0_jump_t : HInst<
6838(outs),
6839(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6840"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
6841tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6842let Inst{0-0} = 0b0;
6843let Inst{13-12} = 0b10;
6844let Inst{31-22} = 0b0001010011;
6845let isPredicated = 1;
6846let isPredicatedFalse = 1;
6847let isTerminator = 1;
6848let isBranch = 1;
6849let isPredicatedNew = 1;
6850let cofRelax1 = 1;
6851let cofRelax2 = 1;
6852let cofMax1 = 1;
6853let Uses = [P0];
6854let Defs = [P0, PC];
6855let BaseOpcode = "J4_cmpgtp0";
6856let isTaken = Inst{13};
6857let isExtendable = 1;
6858let opExtendable = 2;
6859let isExtentSigned = 1;
6860let opExtentBits = 11;
6861let opExtentAlign = 2;
6862}
6863def J4_cmpgt_fp1_jump_nt : HInst<
6864(outs),
6865(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6866"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
6867tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6868let Inst{0-0} = 0b0;
6869let Inst{13-12} = 0b01;
6870let Inst{31-22} = 0b0001010011;
6871let isPredicated = 1;
6872let isPredicatedFalse = 1;
6873let isTerminator = 1;
6874let isBranch = 1;
6875let isPredicatedNew = 1;
6876let cofRelax1 = 1;
6877let cofRelax2 = 1;
6878let cofMax1 = 1;
6879let Uses = [P1];
6880let Defs = [P1, PC];
6881let BaseOpcode = "J4_cmpgtp1";
6882let isTaken = Inst{13};
6883let isExtendable = 1;
6884let opExtendable = 2;
6885let isExtentSigned = 1;
6886let opExtentBits = 11;
6887let opExtentAlign = 2;
6888}
6889def J4_cmpgt_fp1_jump_t : HInst<
6890(outs),
6891(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6892"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6893tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6894let Inst{0-0} = 0b0;
6895let Inst{13-12} = 0b11;
6896let Inst{31-22} = 0b0001010011;
6897let isPredicated = 1;
6898let isPredicatedFalse = 1;
6899let isTerminator = 1;
6900let isBranch = 1;
6901let isPredicatedNew = 1;
6902let cofRelax1 = 1;
6903let cofRelax2 = 1;
6904let cofMax1 = 1;
6905let Uses = [P1];
6906let Defs = [P1, PC];
6907let BaseOpcode = "J4_cmpgtp1";
6908let isTaken = Inst{13};
6909let isExtendable = 1;
6910let opExtendable = 2;
6911let isExtentSigned = 1;
6912let opExtentBits = 11;
6913let opExtentAlign = 2;
6914}
6915def J4_cmpgt_t_jumpnv_nt : HInst<
6916(outs),
6917(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6918"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6919tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6920let Inst{0-0} = 0b0;
6921let Inst{13-13} = 0b0;
6922let Inst{19-19} = 0b0;
6923let Inst{31-22} = 0b0010000010;
6924let isPredicated = 1;
6925let isTerminator = 1;
6926let isBranch = 1;
6927let isNewValue = 1;
6928let cofMax1 = 1;
6929let isRestrictNoSlot1Store = 1;
6930let Defs = [PC];
6931let BaseOpcode = "J4_cmpgtr";
6932let isTaken = Inst{13};
6933let isExtendable = 1;
6934let opExtendable = 2;
6935let isExtentSigned = 1;
6936let opExtentBits = 11;
6937let opExtentAlign = 2;
6938let opNewValue = 0;
6939}
6940def J4_cmpgt_t_jumpnv_t : HInst<
6941(outs),
6942(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6943"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6944tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6945let Inst{0-0} = 0b0;
6946let Inst{13-13} = 0b1;
6947let Inst{19-19} = 0b0;
6948let Inst{31-22} = 0b0010000010;
6949let isPredicated = 1;
6950let isTerminator = 1;
6951let isBranch = 1;
6952let isNewValue = 1;
6953let cofMax1 = 1;
6954let isRestrictNoSlot1Store = 1;
6955let Defs = [PC];
6956let BaseOpcode = "J4_cmpgtr";
6957let isTaken = Inst{13};
6958let isExtendable = 1;
6959let opExtendable = 2;
6960let isExtentSigned = 1;
6961let opExtentBits = 11;
6962let opExtentAlign = 2;
6963let opNewValue = 0;
6964}
6965def J4_cmpgt_tp0_jump_nt : HInst<
6966(outs),
6967(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6968"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6969tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6970let Inst{0-0} = 0b0;
6971let Inst{13-12} = 0b00;
6972let Inst{31-22} = 0b0001010010;
6973let isPredicated = 1;
6974let isTerminator = 1;
6975let isBranch = 1;
6976let isPredicatedNew = 1;
6977let cofRelax1 = 1;
6978let cofRelax2 = 1;
6979let cofMax1 = 1;
6980let Uses = [P0];
6981let Defs = [P0, PC];
6982let BaseOpcode = "J4_cmpgtp0";
6983let isTaken = Inst{13};
6984let isExtendable = 1;
6985let opExtendable = 2;
6986let isExtentSigned = 1;
6987let opExtentBits = 11;
6988let opExtentAlign = 2;
6989}
6990def J4_cmpgt_tp0_jump_t : HInst<
6991(outs),
6992(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6993"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6994tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6995let Inst{0-0} = 0b0;
6996let Inst{13-12} = 0b10;
6997let Inst{31-22} = 0b0001010010;
6998let isPredicated = 1;
6999let isTerminator = 1;
7000let isBranch = 1;
7001let isPredicatedNew = 1;
7002let cofRelax1 = 1;
7003let cofRelax2 = 1;
7004let cofMax1 = 1;
7005let Uses = [P0];
7006let Defs = [P0, PC];
7007let BaseOpcode = "J4_cmpgtp0";
7008let isTaken = Inst{13};
7009let isExtendable = 1;
7010let opExtendable = 2;
7011let isExtentSigned = 1;
7012let opExtentBits = 11;
7013let opExtentAlign = 2;
7014}
7015def J4_cmpgt_tp1_jump_nt : HInst<
7016(outs),
7017(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7018"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7019tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7020let Inst{0-0} = 0b0;
7021let Inst{13-12} = 0b01;
7022let Inst{31-22} = 0b0001010010;
7023let isPredicated = 1;
7024let isTerminator = 1;
7025let isBranch = 1;
7026let isPredicatedNew = 1;
7027let cofRelax1 = 1;
7028let cofRelax2 = 1;
7029let cofMax1 = 1;
7030let Uses = [P1];
7031let Defs = [P1, PC];
7032let BaseOpcode = "J4_cmpgtp1";
7033let isTaken = Inst{13};
7034let isExtendable = 1;
7035let opExtendable = 2;
7036let isExtentSigned = 1;
7037let opExtentBits = 11;
7038let opExtentAlign = 2;
7039}
7040def J4_cmpgt_tp1_jump_t : HInst<
7041(outs),
7042(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7043"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7044tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7045let Inst{0-0} = 0b0;
7046let Inst{13-12} = 0b11;
7047let Inst{31-22} = 0b0001010010;
7048let isPredicated = 1;
7049let isTerminator = 1;
7050let isBranch = 1;
7051let isPredicatedNew = 1;
7052let cofRelax1 = 1;
7053let cofRelax2 = 1;
7054let cofMax1 = 1;
7055let Uses = [P1];
7056let Defs = [P1, PC];
7057let BaseOpcode = "J4_cmpgtp1";
7058let isTaken = Inst{13};
7059let isExtendable = 1;
7060let opExtendable = 2;
7061let isExtentSigned = 1;
7062let opExtentBits = 11;
7063let opExtentAlign = 2;
7064}
7065def J4_cmpgti_f_jumpnv_nt : HInst<
7066(outs),
7067(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7068"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7069tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7070let Inst{0-0} = 0b0;
7071let Inst{13-13} = 0b0;
7072let Inst{19-19} = 0b0;
7073let Inst{31-22} = 0b0010010011;
7074let isPredicated = 1;
7075let isPredicatedFalse = 1;
7076let isTerminator = 1;
7077let isBranch = 1;
7078let isNewValue = 1;
7079let cofMax1 = 1;
7080let isRestrictNoSlot1Store = 1;
7081let Defs = [PC];
7082let BaseOpcode = "J4_cmpgtir";
7083let isTaken = Inst{13};
7084let isExtendable = 1;
7085let opExtendable = 2;
7086let isExtentSigned = 1;
7087let opExtentBits = 11;
7088let opExtentAlign = 2;
7089let opNewValue = 0;
7090}
7091def J4_cmpgti_f_jumpnv_t : HInst<
7092(outs),
7093(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7094"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7095tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7096let Inst{0-0} = 0b0;
7097let Inst{13-13} = 0b1;
7098let Inst{19-19} = 0b0;
7099let Inst{31-22} = 0b0010010011;
7100let isPredicated = 1;
7101let isPredicatedFalse = 1;
7102let isTerminator = 1;
7103let isBranch = 1;
7104let isNewValue = 1;
7105let cofMax1 = 1;
7106let isRestrictNoSlot1Store = 1;
7107let Defs = [PC];
7108let BaseOpcode = "J4_cmpgtir";
7109let isTaken = Inst{13};
7110let isExtendable = 1;
7111let opExtendable = 2;
7112let isExtentSigned = 1;
7113let opExtentBits = 11;
7114let opExtentAlign = 2;
7115let opNewValue = 0;
7116}
7117def J4_cmpgti_fp0_jump_nt : HInst<
7118(outs),
7119(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7120"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7121tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7122let Inst{0-0} = 0b0;
7123let Inst{13-13} = 0b0;
7124let Inst{31-22} = 0b0001000011;
7125let isPredicated = 1;
7126let isPredicatedFalse = 1;
7127let isTerminator = 1;
7128let isBranch = 1;
7129let isPredicatedNew = 1;
7130let cofRelax1 = 1;
7131let cofRelax2 = 1;
7132let cofMax1 = 1;
7133let Uses = [P0];
7134let Defs = [P0, PC];
7135let BaseOpcode = "J4_cmpgtip0";
7136let isTaken = Inst{13};
7137let isExtendable = 1;
7138let opExtendable = 2;
7139let isExtentSigned = 1;
7140let opExtentBits = 11;
7141let opExtentAlign = 2;
7142}
7143def J4_cmpgti_fp0_jump_t : HInst<
7144(outs),
7145(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7146"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
7147tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7148let Inst{0-0} = 0b0;
7149let Inst{13-13} = 0b1;
7150let Inst{31-22} = 0b0001000011;
7151let isPredicated = 1;
7152let isPredicatedFalse = 1;
7153let isTerminator = 1;
7154let isBranch = 1;
7155let isPredicatedNew = 1;
7156let cofRelax1 = 1;
7157let cofRelax2 = 1;
7158let cofMax1 = 1;
7159let Uses = [P0];
7160let Defs = [P0, PC];
7161let BaseOpcode = "J4_cmpgtip0";
7162let isTaken = Inst{13};
7163let isExtendable = 1;
7164let opExtendable = 2;
7165let isExtentSigned = 1;
7166let opExtentBits = 11;
7167let opExtentAlign = 2;
7168}
7169def J4_cmpgti_fp1_jump_nt : HInst<
7170(outs),
7171(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7172"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7173tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7174let Inst{0-0} = 0b0;
7175let Inst{13-13} = 0b0;
7176let Inst{31-22} = 0b0001001011;
7177let isPredicated = 1;
7178let isPredicatedFalse = 1;
7179let isTerminator = 1;
7180let isBranch = 1;
7181let isPredicatedNew = 1;
7182let cofRelax1 = 1;
7183let cofRelax2 = 1;
7184let cofMax1 = 1;
7185let Uses = [P1];
7186let Defs = [P1, PC];
7187let BaseOpcode = "J4_cmpgtip1";
7188let isTaken = Inst{13};
7189let isExtendable = 1;
7190let opExtendable = 2;
7191let isExtentSigned = 1;
7192let opExtentBits = 11;
7193let opExtentAlign = 2;
7194}
7195def J4_cmpgti_fp1_jump_t : HInst<
7196(outs),
7197(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7198"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
7199tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7200let Inst{0-0} = 0b0;
7201let Inst{13-13} = 0b1;
7202let Inst{31-22} = 0b0001001011;
7203let isPredicated = 1;
7204let isPredicatedFalse = 1;
7205let isTerminator = 1;
7206let isBranch = 1;
7207let isPredicatedNew = 1;
7208let cofRelax1 = 1;
7209let cofRelax2 = 1;
7210let cofMax1 = 1;
7211let Uses = [P1];
7212let Defs = [P1, PC];
7213let BaseOpcode = "J4_cmpgtip1";
7214let isTaken = Inst{13};
7215let isExtendable = 1;
7216let opExtendable = 2;
7217let isExtentSigned = 1;
7218let opExtentBits = 11;
7219let opExtentAlign = 2;
7220}
7221def J4_cmpgti_t_jumpnv_nt : HInst<
7222(outs),
7223(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7224"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7225tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7226let Inst{0-0} = 0b0;
7227let Inst{13-13} = 0b0;
7228let Inst{19-19} = 0b0;
7229let Inst{31-22} = 0b0010010010;
7230let isPredicated = 1;
7231let isTerminator = 1;
7232let isBranch = 1;
7233let isNewValue = 1;
7234let cofMax1 = 1;
7235let isRestrictNoSlot1Store = 1;
7236let Defs = [PC];
7237let BaseOpcode = "J4_cmpgtir";
7238let isTaken = Inst{13};
7239let isExtendable = 1;
7240let opExtendable = 2;
7241let isExtentSigned = 1;
7242let opExtentBits = 11;
7243let opExtentAlign = 2;
7244let opNewValue = 0;
7245}
7246def J4_cmpgti_t_jumpnv_t : HInst<
7247(outs),
7248(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7249"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7250tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7251let Inst{0-0} = 0b0;
7252let Inst{13-13} = 0b1;
7253let Inst{19-19} = 0b0;
7254let Inst{31-22} = 0b0010010010;
7255let isPredicated = 1;
7256let isTerminator = 1;
7257let isBranch = 1;
7258let isNewValue = 1;
7259let cofMax1 = 1;
7260let isRestrictNoSlot1Store = 1;
7261let Defs = [PC];
7262let BaseOpcode = "J4_cmpgtir";
7263let isTaken = Inst{13};
7264let isExtendable = 1;
7265let opExtendable = 2;
7266let isExtentSigned = 1;
7267let opExtentBits = 11;
7268let opExtentAlign = 2;
7269let opNewValue = 0;
7270}
7271def J4_cmpgti_tp0_jump_nt : HInst<
7272(outs),
7273(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7274"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
7275tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7276let Inst{0-0} = 0b0;
7277let Inst{13-13} = 0b0;
7278let Inst{31-22} = 0b0001000010;
7279let isPredicated = 1;
7280let isTerminator = 1;
7281let isBranch = 1;
7282let isPredicatedNew = 1;
7283let cofRelax1 = 1;
7284let cofRelax2 = 1;
7285let cofMax1 = 1;
7286let Uses = [P0];
7287let Defs = [P0, PC];
7288let BaseOpcode = "J4_cmpgtip0";
7289let isTaken = Inst{13};
7290let isExtendable = 1;
7291let opExtendable = 2;
7292let isExtentSigned = 1;
7293let opExtentBits = 11;
7294let opExtentAlign = 2;
7295}
7296def J4_cmpgti_tp0_jump_t : HInst<
7297(outs),
7298(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7299"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
7300tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7301let Inst{0-0} = 0b0;
7302let Inst{13-13} = 0b1;
7303let Inst{31-22} = 0b0001000010;
7304let isPredicated = 1;
7305let isTerminator = 1;
7306let isBranch = 1;
7307let isPredicatedNew = 1;
7308let cofRelax1 = 1;
7309let cofRelax2 = 1;
7310let cofMax1 = 1;
7311let Uses = [P0];
7312let Defs = [P0, PC];
7313let BaseOpcode = "J4_cmpgtip0";
7314let isTaken = Inst{13};
7315let isExtendable = 1;
7316let opExtendable = 2;
7317let isExtentSigned = 1;
7318let opExtentBits = 11;
7319let opExtentAlign = 2;
7320}
7321def J4_cmpgti_tp1_jump_nt : HInst<
7322(outs),
7323(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7324"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
7325tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7326let Inst{0-0} = 0b0;
7327let Inst{13-13} = 0b0;
7328let Inst{31-22} = 0b0001001010;
7329let isPredicated = 1;
7330let isTerminator = 1;
7331let isBranch = 1;
7332let isPredicatedNew = 1;
7333let cofRelax1 = 1;
7334let cofRelax2 = 1;
7335let cofMax1 = 1;
7336let Uses = [P1];
7337let Defs = [P1, PC];
7338let BaseOpcode = "J4_cmpgtip1";
7339let isTaken = Inst{13};
7340let isExtendable = 1;
7341let opExtendable = 2;
7342let isExtentSigned = 1;
7343let opExtentBits = 11;
7344let opExtentAlign = 2;
7345}
7346def J4_cmpgti_tp1_jump_t : HInst<
7347(outs),
7348(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7349"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
7350tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7351let Inst{0-0} = 0b0;
7352let Inst{13-13} = 0b1;
7353let Inst{31-22} = 0b0001001010;
7354let isPredicated = 1;
7355let isTerminator = 1;
7356let isBranch = 1;
7357let isPredicatedNew = 1;
7358let cofRelax1 = 1;
7359let cofRelax2 = 1;
7360let cofMax1 = 1;
7361let Uses = [P1];
7362let Defs = [P1, PC];
7363let BaseOpcode = "J4_cmpgtip1";
7364let isTaken = Inst{13};
7365let isExtendable = 1;
7366let opExtendable = 2;
7367let isExtentSigned = 1;
7368let opExtentBits = 11;
7369let opExtentAlign = 2;
7370}
7371def J4_cmpgtn1_f_jumpnv_nt : HInst<
7372(outs),
7373(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7374"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7375tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel {
7376let Inst{0-0} = 0b0;
7377let Inst{13-8} = 0b000000;
7378let Inst{19-19} = 0b0;
7379let Inst{31-22} = 0b0010011011;
7380let isPredicated = 1;
7381let isPredicatedFalse = 1;
7382let isTerminator = 1;
7383let isBranch = 1;
7384let isNewValue = 1;
7385let cofMax1 = 1;
7386let isRestrictNoSlot1Store = 1;
7387let Defs = [PC];
7388let BaseOpcode = "J4_cmpgtn1r";
7389let isTaken = Inst{13};
7390let isExtendable = 1;
7391let opExtendable = 2;
7392let isExtentSigned = 1;
7393let opExtentBits = 11;
7394let opExtentAlign = 2;
7395let opNewValue = 0;
7396}
7397def J4_cmpgtn1_f_jumpnv_t : HInst<
7398(outs),
7399(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7400"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7401tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel {
7402let Inst{0-0} = 0b0;
7403let Inst{13-8} = 0b100000;
7404let Inst{19-19} = 0b0;
7405let Inst{31-22} = 0b0010011011;
7406let isPredicated = 1;
7407let isPredicatedFalse = 1;
7408let isTerminator = 1;
7409let isBranch = 1;
7410let isNewValue = 1;
7411let cofMax1 = 1;
7412let isRestrictNoSlot1Store = 1;
7413let Defs = [PC];
7414let BaseOpcode = "J4_cmpgtn1r";
7415let isTaken = Inst{13};
7416let isExtendable = 1;
7417let opExtendable = 2;
7418let isExtentSigned = 1;
7419let opExtentBits = 11;
7420let opExtentAlign = 2;
7421let opNewValue = 0;
7422}
7423def J4_cmpgtn1_fp0_jump_nt : HInst<
7424(outs),
7425(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7426"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
7427tc_24f426ab, TypeCJ>, Enc_a42857, PredRel {
7428let Inst{0-0} = 0b0;
7429let Inst{13-8} = 0b000001;
7430let Inst{31-22} = 0b0001000111;
7431let isPredicated = 1;
7432let isPredicatedFalse = 1;
7433let isTerminator = 1;
7434let isBranch = 1;
7435let isPredicatedNew = 1;
7436let cofRelax1 = 1;
7437let cofRelax2 = 1;
7438let cofMax1 = 1;
7439let Uses = [P0];
7440let Defs = [P0, PC];
7441let BaseOpcode = "J4_cmpgtn1p0";
7442let isTaken = Inst{13};
7443let isExtendable = 1;
7444let opExtendable = 2;
7445let isExtentSigned = 1;
7446let opExtentBits = 11;
7447let opExtentAlign = 2;
7448}
7449def J4_cmpgtn1_fp0_jump_t : HInst<
7450(outs),
7451(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7452"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
7453tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel {
7454let Inst{0-0} = 0b0;
7455let Inst{13-8} = 0b100001;
7456let Inst{31-22} = 0b0001000111;
7457let isPredicated = 1;
7458let isPredicatedFalse = 1;
7459let isTerminator = 1;
7460let isBranch = 1;
7461let isPredicatedNew = 1;
7462let cofRelax1 = 1;
7463let cofRelax2 = 1;
7464let cofMax1 = 1;
7465let Uses = [P0];
7466let Defs = [P0, PC];
7467let BaseOpcode = "J4_cmpgtn1p0";
7468let isTaken = Inst{13};
7469let isExtendable = 1;
7470let opExtendable = 2;
7471let isExtentSigned = 1;
7472let opExtentBits = 11;
7473let opExtentAlign = 2;
7474}
7475def J4_cmpgtn1_fp1_jump_nt : HInst<
7476(outs),
7477(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7478"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
7479tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel {
7480let Inst{0-0} = 0b0;
7481let Inst{13-8} = 0b000001;
7482let Inst{31-22} = 0b0001001111;
7483let isPredicated = 1;
7484let isPredicatedFalse = 1;
7485let isTerminator = 1;
7486let isBranch = 1;
7487let isPredicatedNew = 1;
7488let cofRelax1 = 1;
7489let cofRelax2 = 1;
7490let cofMax1 = 1;
7491let Uses = [P1];
7492let Defs = [P1, PC];
7493let BaseOpcode = "J4_cmpgtn1p1";
7494let isTaken = Inst{13};
7495let isExtendable = 1;
7496let opExtendable = 2;
7497let isExtentSigned = 1;
7498let opExtentBits = 11;
7499let opExtentAlign = 2;
7500}
7501def J4_cmpgtn1_fp1_jump_t : HInst<
7502(outs),
7503(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7504"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
7505tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel {
7506let Inst{0-0} = 0b0;
7507let Inst{13-8} = 0b100001;
7508let Inst{31-22} = 0b0001001111;
7509let isPredicated = 1;
7510let isPredicatedFalse = 1;
7511let isTerminator = 1;
7512let isBranch = 1;
7513let isPredicatedNew = 1;
7514let cofRelax1 = 1;
7515let cofRelax2 = 1;
7516let cofMax1 = 1;
7517let Uses = [P1];
7518let Defs = [P1, PC];
7519let BaseOpcode = "J4_cmpgtn1p1";
7520let isTaken = Inst{13};
7521let isExtendable = 1;
7522let opExtendable = 2;
7523let isExtentSigned = 1;
7524let opExtentBits = 11;
7525let opExtentAlign = 2;
7526}
7527def J4_cmpgtn1_t_jumpnv_nt : HInst<
7528(outs),
7529(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7530"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7531tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel {
7532let Inst{0-0} = 0b0;
7533let Inst{13-8} = 0b000000;
7534let Inst{19-19} = 0b0;
7535let Inst{31-22} = 0b0010011010;
7536let isPredicated = 1;
7537let isTerminator = 1;
7538let isBranch = 1;
7539let isNewValue = 1;
7540let cofMax1 = 1;
7541let isRestrictNoSlot1Store = 1;
7542let Defs = [PC];
7543let BaseOpcode = "J4_cmpgtn1r";
7544let isTaken = Inst{13};
7545let isExtendable = 1;
7546let opExtendable = 2;
7547let isExtentSigned = 1;
7548let opExtentBits = 11;
7549let opExtentAlign = 2;
7550let opNewValue = 0;
7551}
7552def J4_cmpgtn1_t_jumpnv_t : HInst<
7553(outs),
7554(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7555"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7556tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel {
7557let Inst{0-0} = 0b0;
7558let Inst{13-8} = 0b100000;
7559let Inst{19-19} = 0b0;
7560let Inst{31-22} = 0b0010011010;
7561let isPredicated = 1;
7562let isTerminator = 1;
7563let isBranch = 1;
7564let isNewValue = 1;
7565let cofMax1 = 1;
7566let isRestrictNoSlot1Store = 1;
7567let Defs = [PC];
7568let BaseOpcode = "J4_cmpgtn1r";
7569let isTaken = Inst{13};
7570let isExtendable = 1;
7571let opExtendable = 2;
7572let isExtentSigned = 1;
7573let opExtentBits = 11;
7574let opExtentAlign = 2;
7575let opNewValue = 0;
7576}
7577def J4_cmpgtn1_tp0_jump_nt : HInst<
7578(outs),
7579(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7580"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
7581tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel {
7582let Inst{0-0} = 0b0;
7583let Inst{13-8} = 0b000001;
7584let Inst{31-22} = 0b0001000110;
7585let isPredicated = 1;
7586let isTerminator = 1;
7587let isBranch = 1;
7588let isPredicatedNew = 1;
7589let cofRelax1 = 1;
7590let cofRelax2 = 1;
7591let cofMax1 = 1;
7592let Uses = [P0];
7593let Defs = [P0, PC];
7594let BaseOpcode = "J4_cmpgtn1p0";
7595let isTaken = Inst{13};
7596let isExtendable = 1;
7597let opExtendable = 2;
7598let isExtentSigned = 1;
7599let opExtentBits = 11;
7600let opExtentAlign = 2;
7601}
7602def J4_cmpgtn1_tp0_jump_t : HInst<
7603(outs),
7604(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7605"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
7606tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel {
7607let Inst{0-0} = 0b0;
7608let Inst{13-8} = 0b100001;
7609let Inst{31-22} = 0b0001000110;
7610let isPredicated = 1;
7611let isTerminator = 1;
7612let isBranch = 1;
7613let isPredicatedNew = 1;
7614let cofRelax1 = 1;
7615let cofRelax2 = 1;
7616let cofMax1 = 1;
7617let Uses = [P0];
7618let Defs = [P0, PC];
7619let BaseOpcode = "J4_cmpgtn1p0";
7620let isTaken = Inst{13};
7621let isExtendable = 1;
7622let opExtendable = 2;
7623let isExtentSigned = 1;
7624let opExtentBits = 11;
7625let opExtentAlign = 2;
7626}
7627def J4_cmpgtn1_tp1_jump_nt : HInst<
7628(outs),
7629(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7630"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
7631tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel {
7632let Inst{0-0} = 0b0;
7633let Inst{13-8} = 0b000001;
7634let Inst{31-22} = 0b0001001110;
7635let isPredicated = 1;
7636let isTerminator = 1;
7637let isBranch = 1;
7638let isPredicatedNew = 1;
7639let cofRelax1 = 1;
7640let cofRelax2 = 1;
7641let cofMax1 = 1;
7642let Uses = [P1];
7643let Defs = [P1, PC];
7644let BaseOpcode = "J4_cmpgtn1p1";
7645let isTaken = Inst{13};
7646let isExtendable = 1;
7647let opExtendable = 2;
7648let isExtentSigned = 1;
7649let opExtentBits = 11;
7650let opExtentAlign = 2;
7651}
7652def J4_cmpgtn1_tp1_jump_t : HInst<
7653(outs),
7654(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7655"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
7656tc_24f426ab, TypeCJ>, Enc_178717, PredRel {
7657let Inst{0-0} = 0b0;
7658let Inst{13-8} = 0b100001;
7659let Inst{31-22} = 0b0001001110;
7660let isPredicated = 1;
7661let isTerminator = 1;
7662let isBranch = 1;
7663let isPredicatedNew = 1;
7664let cofRelax1 = 1;
7665let cofRelax2 = 1;
7666let cofMax1 = 1;
7667let Uses = [P1];
7668let Defs = [P1, PC];
7669let BaseOpcode = "J4_cmpgtn1p1";
7670let isTaken = Inst{13};
7671let isExtendable = 1;
7672let opExtendable = 2;
7673let isExtentSigned = 1;
7674let opExtentBits = 11;
7675let opExtentAlign = 2;
7676}
7677def J4_cmpgtu_f_jumpnv_nt : HInst<
7678(outs),
7679(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7680"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7681tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7682let Inst{0-0} = 0b0;
7683let Inst{13-13} = 0b0;
7684let Inst{19-19} = 0b0;
7685let Inst{31-22} = 0b0010000101;
7686let isPredicated = 1;
7687let isPredicatedFalse = 1;
7688let isTerminator = 1;
7689let isBranch = 1;
7690let isNewValue = 1;
7691let cofMax1 = 1;
7692let isRestrictNoSlot1Store = 1;
7693let Defs = [PC];
7694let BaseOpcode = "J4_cmpgtur";
7695let isTaken = Inst{13};
7696let isExtendable = 1;
7697let opExtendable = 2;
7698let isExtentSigned = 1;
7699let opExtentBits = 11;
7700let opExtentAlign = 2;
7701let opNewValue = 0;
7702}
7703def J4_cmpgtu_f_jumpnv_t : HInst<
7704(outs),
7705(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7706"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7707tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7708let Inst{0-0} = 0b0;
7709let Inst{13-13} = 0b1;
7710let Inst{19-19} = 0b0;
7711let Inst{31-22} = 0b0010000101;
7712let isPredicated = 1;
7713let isPredicatedFalse = 1;
7714let isTerminator = 1;
7715let isBranch = 1;
7716let isNewValue = 1;
7717let cofMax1 = 1;
7718let isRestrictNoSlot1Store = 1;
7719let Defs = [PC];
7720let BaseOpcode = "J4_cmpgtur";
7721let isTaken = Inst{13};
7722let isExtendable = 1;
7723let opExtendable = 2;
7724let isExtentSigned = 1;
7725let opExtentBits = 11;
7726let opExtentAlign = 2;
7727let opNewValue = 0;
7728}
7729def J4_cmpgtu_fp0_jump_nt : HInst<
7730(outs),
7731(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7732"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
7733tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7734let Inst{0-0} = 0b0;
7735let Inst{13-12} = 0b00;
7736let Inst{31-22} = 0b0001010101;
7737let isPredicated = 1;
7738let isPredicatedFalse = 1;
7739let isTerminator = 1;
7740let isBranch = 1;
7741let isPredicatedNew = 1;
7742let cofRelax1 = 1;
7743let cofRelax2 = 1;
7744let cofMax1 = 1;
7745let Uses = [P0];
7746let Defs = [P0, PC];
7747let BaseOpcode = "J4_cmpgtup0";
7748let isTaken = Inst{13};
7749let isExtendable = 1;
7750let opExtendable = 2;
7751let isExtentSigned = 1;
7752let opExtentBits = 11;
7753let opExtentAlign = 2;
7754}
7755def J4_cmpgtu_fp0_jump_t : HInst<
7756(outs),
7757(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7758"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
7759tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7760let Inst{0-0} = 0b0;
7761let Inst{13-12} = 0b10;
7762let Inst{31-22} = 0b0001010101;
7763let isPredicated = 1;
7764let isPredicatedFalse = 1;
7765let isTerminator = 1;
7766let isBranch = 1;
7767let isPredicatedNew = 1;
7768let cofRelax1 = 1;
7769let cofRelax2 = 1;
7770let cofMax1 = 1;
7771let Uses = [P0];
7772let Defs = [P0, PC];
7773let BaseOpcode = "J4_cmpgtup0";
7774let isTaken = Inst{13};
7775let isExtendable = 1;
7776let opExtendable = 2;
7777let isExtentSigned = 1;
7778let opExtentBits = 11;
7779let opExtentAlign = 2;
7780}
7781def J4_cmpgtu_fp1_jump_nt : HInst<
7782(outs),
7783(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7784"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
7785tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7786let Inst{0-0} = 0b0;
7787let Inst{13-12} = 0b01;
7788let Inst{31-22} = 0b0001010101;
7789let isPredicated = 1;
7790let isPredicatedFalse = 1;
7791let isTerminator = 1;
7792let isBranch = 1;
7793let isPredicatedNew = 1;
7794let cofRelax1 = 1;
7795let cofRelax2 = 1;
7796let cofMax1 = 1;
7797let Uses = [P1];
7798let Defs = [P1, PC];
7799let BaseOpcode = "J4_cmpgtup1";
7800let isTaken = Inst{13};
7801let isExtendable = 1;
7802let opExtendable = 2;
7803let isExtentSigned = 1;
7804let opExtentBits = 11;
7805let opExtentAlign = 2;
7806}
7807def J4_cmpgtu_fp1_jump_t : HInst<
7808(outs),
7809(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7810"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
7811tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7812let Inst{0-0} = 0b0;
7813let Inst{13-12} = 0b11;
7814let Inst{31-22} = 0b0001010101;
7815let isPredicated = 1;
7816let isPredicatedFalse = 1;
7817let isTerminator = 1;
7818let isBranch = 1;
7819let isPredicatedNew = 1;
7820let cofRelax1 = 1;
7821let cofRelax2 = 1;
7822let cofMax1 = 1;
7823let Uses = [P1];
7824let Defs = [P1, PC];
7825let BaseOpcode = "J4_cmpgtup1";
7826let isTaken = Inst{13};
7827let isExtendable = 1;
7828let opExtendable = 2;
7829let isExtentSigned = 1;
7830let opExtentBits = 11;
7831let opExtentAlign = 2;
7832}
7833def J4_cmpgtu_t_jumpnv_nt : HInst<
7834(outs),
7835(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7836"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7837tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7838let Inst{0-0} = 0b0;
7839let Inst{13-13} = 0b0;
7840let Inst{19-19} = 0b0;
7841let Inst{31-22} = 0b0010000100;
7842let isPredicated = 1;
7843let isTerminator = 1;
7844let isBranch = 1;
7845let isNewValue = 1;
7846let cofMax1 = 1;
7847let isRestrictNoSlot1Store = 1;
7848let Defs = [PC];
7849let BaseOpcode = "J4_cmpgtur";
7850let isTaken = Inst{13};
7851let isExtendable = 1;
7852let opExtendable = 2;
7853let isExtentSigned = 1;
7854let opExtentBits = 11;
7855let opExtentAlign = 2;
7856let opNewValue = 0;
7857}
7858def J4_cmpgtu_t_jumpnv_t : HInst<
7859(outs),
7860(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7861"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7862tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7863let Inst{0-0} = 0b0;
7864let Inst{13-13} = 0b1;
7865let Inst{19-19} = 0b0;
7866let Inst{31-22} = 0b0010000100;
7867let isPredicated = 1;
7868let isTerminator = 1;
7869let isBranch = 1;
7870let isNewValue = 1;
7871let cofMax1 = 1;
7872let isRestrictNoSlot1Store = 1;
7873let Defs = [PC];
7874let BaseOpcode = "J4_cmpgtur";
7875let isTaken = Inst{13};
7876let isExtendable = 1;
7877let opExtendable = 2;
7878let isExtentSigned = 1;
7879let opExtentBits = 11;
7880let opExtentAlign = 2;
7881let opNewValue = 0;
7882}
7883def J4_cmpgtu_tp0_jump_nt : HInst<
7884(outs),
7885(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7886"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7887tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7888let Inst{0-0} = 0b0;
7889let Inst{13-12} = 0b00;
7890let Inst{31-22} = 0b0001010100;
7891let isPredicated = 1;
7892let isTerminator = 1;
7893let isBranch = 1;
7894let isPredicatedNew = 1;
7895let cofRelax1 = 1;
7896let cofRelax2 = 1;
7897let cofMax1 = 1;
7898let Uses = [P0];
7899let Defs = [P0, PC];
7900let BaseOpcode = "J4_cmpgtup0";
7901let isTaken = Inst{13};
7902let isExtendable = 1;
7903let opExtendable = 2;
7904let isExtentSigned = 1;
7905let opExtentBits = 11;
7906let opExtentAlign = 2;
7907}
7908def J4_cmpgtu_tp0_jump_t : HInst<
7909(outs),
7910(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7911"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7912tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7913let Inst{0-0} = 0b0;
7914let Inst{13-12} = 0b10;
7915let Inst{31-22} = 0b0001010100;
7916let isPredicated = 1;
7917let isTerminator = 1;
7918let isBranch = 1;
7919let isPredicatedNew = 1;
7920let cofRelax1 = 1;
7921let cofRelax2 = 1;
7922let cofMax1 = 1;
7923let Uses = [P0];
7924let Defs = [P0, PC];
7925let BaseOpcode = "J4_cmpgtup0";
7926let isTaken = Inst{13};
7927let isExtendable = 1;
7928let opExtendable = 2;
7929let isExtentSigned = 1;
7930let opExtentBits = 11;
7931let opExtentAlign = 2;
7932}
7933def J4_cmpgtu_tp1_jump_nt : HInst<
7934(outs),
7935(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7936"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7937tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7938let Inst{0-0} = 0b0;
7939let Inst{13-12} = 0b01;
7940let Inst{31-22} = 0b0001010100;
7941let isPredicated = 1;
7942let isTerminator = 1;
7943let isBranch = 1;
7944let isPredicatedNew = 1;
7945let cofRelax1 = 1;
7946let cofRelax2 = 1;
7947let cofMax1 = 1;
7948let Uses = [P1];
7949let Defs = [P1, PC];
7950let BaseOpcode = "J4_cmpgtup1";
7951let isTaken = Inst{13};
7952let isExtendable = 1;
7953let opExtendable = 2;
7954let isExtentSigned = 1;
7955let opExtentBits = 11;
7956let opExtentAlign = 2;
7957}
7958def J4_cmpgtu_tp1_jump_t : HInst<
7959(outs),
7960(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7961"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7962tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7963let Inst{0-0} = 0b0;
7964let Inst{13-12} = 0b11;
7965let Inst{31-22} = 0b0001010100;
7966let isPredicated = 1;
7967let isTerminator = 1;
7968let isBranch = 1;
7969let isPredicatedNew = 1;
7970let cofRelax1 = 1;
7971let cofRelax2 = 1;
7972let cofMax1 = 1;
7973let Uses = [P1];
7974let Defs = [P1, PC];
7975let BaseOpcode = "J4_cmpgtup1";
7976let isTaken = Inst{13};
7977let isExtendable = 1;
7978let opExtendable = 2;
7979let isExtentSigned = 1;
7980let opExtentBits = 11;
7981let opExtentAlign = 2;
7982}
7983def J4_cmpgtui_f_jumpnv_nt : HInst<
7984(outs),
7985(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7986"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
7987tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7988let Inst{0-0} = 0b0;
7989let Inst{13-13} = 0b0;
7990let Inst{19-19} = 0b0;
7991let Inst{31-22} = 0b0010010101;
7992let isPredicated = 1;
7993let isPredicatedFalse = 1;
7994let isTerminator = 1;
7995let isBranch = 1;
7996let isNewValue = 1;
7997let cofMax1 = 1;
7998let isRestrictNoSlot1Store = 1;
7999let Defs = [PC];
8000let BaseOpcode = "J4_cmpgtuir";
8001let isTaken = Inst{13};
8002let isExtendable = 1;
8003let opExtendable = 2;
8004let isExtentSigned = 1;
8005let opExtentBits = 11;
8006let opExtentAlign = 2;
8007let opNewValue = 0;
8008}
8009def J4_cmpgtui_f_jumpnv_t : HInst<
8010(outs),
8011(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8012"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8013tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8014let Inst{0-0} = 0b0;
8015let Inst{13-13} = 0b1;
8016let Inst{19-19} = 0b0;
8017let Inst{31-22} = 0b0010010101;
8018let isPredicated = 1;
8019let isPredicatedFalse = 1;
8020let isTerminator = 1;
8021let isBranch = 1;
8022let isNewValue = 1;
8023let cofMax1 = 1;
8024let isRestrictNoSlot1Store = 1;
8025let Defs = [PC];
8026let BaseOpcode = "J4_cmpgtuir";
8027let isTaken = Inst{13};
8028let isExtendable = 1;
8029let opExtendable = 2;
8030let isExtentSigned = 1;
8031let opExtentBits = 11;
8032let opExtentAlign = 2;
8033let opNewValue = 0;
8034}
8035def J4_cmpgtui_fp0_jump_nt : HInst<
8036(outs),
8037(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8038"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
8039tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8040let Inst{0-0} = 0b0;
8041let Inst{13-13} = 0b0;
8042let Inst{31-22} = 0b0001000101;
8043let isPredicated = 1;
8044let isPredicatedFalse = 1;
8045let isTerminator = 1;
8046let isBranch = 1;
8047let isPredicatedNew = 1;
8048let cofRelax1 = 1;
8049let cofRelax2 = 1;
8050let cofMax1 = 1;
8051let Uses = [P0];
8052let Defs = [P0, PC];
8053let BaseOpcode = "J4_cmpgtuip0";
8054let isTaken = Inst{13};
8055let isExtendable = 1;
8056let opExtendable = 2;
8057let isExtentSigned = 1;
8058let opExtentBits = 11;
8059let opExtentAlign = 2;
8060}
8061def J4_cmpgtui_fp0_jump_t : HInst<
8062(outs),
8063(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8064"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
8065tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8066let Inst{0-0} = 0b0;
8067let Inst{13-13} = 0b1;
8068let Inst{31-22} = 0b0001000101;
8069let isPredicated = 1;
8070let isPredicatedFalse = 1;
8071let isTerminator = 1;
8072let isBranch = 1;
8073let isPredicatedNew = 1;
8074let cofRelax1 = 1;
8075let cofRelax2 = 1;
8076let cofMax1 = 1;
8077let Uses = [P0];
8078let Defs = [P0, PC];
8079let BaseOpcode = "J4_cmpgtuip0";
8080let isTaken = Inst{13};
8081let isExtendable = 1;
8082let opExtendable = 2;
8083let isExtentSigned = 1;
8084let opExtentBits = 11;
8085let opExtentAlign = 2;
8086}
8087def J4_cmpgtui_fp1_jump_nt : HInst<
8088(outs),
8089(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8090"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
8091tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8092let Inst{0-0} = 0b0;
8093let Inst{13-13} = 0b0;
8094let Inst{31-22} = 0b0001001101;
8095let isPredicated = 1;
8096let isPredicatedFalse = 1;
8097let isTerminator = 1;
8098let isBranch = 1;
8099let isPredicatedNew = 1;
8100let cofRelax1 = 1;
8101let cofRelax2 = 1;
8102let cofMax1 = 1;
8103let Uses = [P1];
8104let Defs = [P1, PC];
8105let BaseOpcode = "J4_cmpgtuip1";
8106let isTaken = Inst{13};
8107let isExtendable = 1;
8108let opExtendable = 2;
8109let isExtentSigned = 1;
8110let opExtentBits = 11;
8111let opExtentAlign = 2;
8112}
8113def J4_cmpgtui_fp1_jump_t : HInst<
8114(outs),
8115(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8116"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
8117tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8118let Inst{0-0} = 0b0;
8119let Inst{13-13} = 0b1;
8120let Inst{31-22} = 0b0001001101;
8121let isPredicated = 1;
8122let isPredicatedFalse = 1;
8123let isTerminator = 1;
8124let isBranch = 1;
8125let isPredicatedNew = 1;
8126let cofRelax1 = 1;
8127let cofRelax2 = 1;
8128let cofMax1 = 1;
8129let Uses = [P1];
8130let Defs = [P1, PC];
8131let BaseOpcode = "J4_cmpgtuip1";
8132let isTaken = Inst{13};
8133let isExtendable = 1;
8134let opExtendable = 2;
8135let isExtentSigned = 1;
8136let opExtentBits = 11;
8137let opExtentAlign = 2;
8138}
8139def J4_cmpgtui_t_jumpnv_nt : HInst<
8140(outs),
8141(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8142"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8143tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8144let Inst{0-0} = 0b0;
8145let Inst{13-13} = 0b0;
8146let Inst{19-19} = 0b0;
8147let Inst{31-22} = 0b0010010100;
8148let isPredicated = 1;
8149let isTerminator = 1;
8150let isBranch = 1;
8151let isNewValue = 1;
8152let cofMax1 = 1;
8153let isRestrictNoSlot1Store = 1;
8154let Defs = [PC];
8155let BaseOpcode = "J4_cmpgtuir";
8156let isTaken = Inst{13};
8157let isExtendable = 1;
8158let opExtendable = 2;
8159let isExtentSigned = 1;
8160let opExtentBits = 11;
8161let opExtentAlign = 2;
8162let opNewValue = 0;
8163}
8164def J4_cmpgtui_t_jumpnv_t : HInst<
8165(outs),
8166(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8167"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8168tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8169let Inst{0-0} = 0b0;
8170let Inst{13-13} = 0b1;
8171let Inst{19-19} = 0b0;
8172let Inst{31-22} = 0b0010010100;
8173let isPredicated = 1;
8174let isTerminator = 1;
8175let isBranch = 1;
8176let isNewValue = 1;
8177let cofMax1 = 1;
8178let isRestrictNoSlot1Store = 1;
8179let Defs = [PC];
8180let BaseOpcode = "J4_cmpgtuir";
8181let isTaken = Inst{13};
8182let isExtendable = 1;
8183let opExtendable = 2;
8184let isExtentSigned = 1;
8185let opExtentBits = 11;
8186let opExtentAlign = 2;
8187let opNewValue = 0;
8188}
8189def J4_cmpgtui_tp0_jump_nt : HInst<
8190(outs),
8191(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8192"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
8193tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8194let Inst{0-0} = 0b0;
8195let Inst{13-13} = 0b0;
8196let Inst{31-22} = 0b0001000100;
8197let isPredicated = 1;
8198let isTerminator = 1;
8199let isBranch = 1;
8200let isPredicatedNew = 1;
8201let cofRelax1 = 1;
8202let cofRelax2 = 1;
8203let cofMax1 = 1;
8204let Uses = [P0];
8205let Defs = [P0, PC];
8206let BaseOpcode = "J4_cmpgtuip0";
8207let isTaken = Inst{13};
8208let isExtendable = 1;
8209let opExtendable = 2;
8210let isExtentSigned = 1;
8211let opExtentBits = 11;
8212let opExtentAlign = 2;
8213}
8214def J4_cmpgtui_tp0_jump_t : HInst<
8215(outs),
8216(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8217"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
8218tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8219let Inst{0-0} = 0b0;
8220let Inst{13-13} = 0b1;
8221let Inst{31-22} = 0b0001000100;
8222let isPredicated = 1;
8223let isTerminator = 1;
8224let isBranch = 1;
8225let isPredicatedNew = 1;
8226let cofRelax1 = 1;
8227let cofRelax2 = 1;
8228let cofMax1 = 1;
8229let Uses = [P0];
8230let Defs = [P0, PC];
8231let BaseOpcode = "J4_cmpgtuip0";
8232let isTaken = Inst{13};
8233let isExtendable = 1;
8234let opExtendable = 2;
8235let isExtentSigned = 1;
8236let opExtentBits = 11;
8237let opExtentAlign = 2;
8238}
8239def J4_cmpgtui_tp1_jump_nt : HInst<
8240(outs),
8241(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8242"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
8243tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8244let Inst{0-0} = 0b0;
8245let Inst{13-13} = 0b0;
8246let Inst{31-22} = 0b0001001100;
8247let isPredicated = 1;
8248let isTerminator = 1;
8249let isBranch = 1;
8250let isPredicatedNew = 1;
8251let cofRelax1 = 1;
8252let cofRelax2 = 1;
8253let cofMax1 = 1;
8254let Uses = [P1];
8255let Defs = [P1, PC];
8256let BaseOpcode = "J4_cmpgtuip1";
8257let isTaken = Inst{13};
8258let isExtendable = 1;
8259let opExtendable = 2;
8260let isExtentSigned = 1;
8261let opExtentBits = 11;
8262let opExtentAlign = 2;
8263}
8264def J4_cmpgtui_tp1_jump_t : HInst<
8265(outs),
8266(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8267"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
8268tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8269let Inst{0-0} = 0b0;
8270let Inst{13-13} = 0b1;
8271let Inst{31-22} = 0b0001001100;
8272let isPredicated = 1;
8273let isTerminator = 1;
8274let isBranch = 1;
8275let isPredicatedNew = 1;
8276let cofRelax1 = 1;
8277let cofRelax2 = 1;
8278let cofMax1 = 1;
8279let Uses = [P1];
8280let Defs = [P1, PC];
8281let BaseOpcode = "J4_cmpgtuip1";
8282let isTaken = Inst{13};
8283let isExtendable = 1;
8284let opExtendable = 2;
8285let isExtentSigned = 1;
8286let opExtentBits = 11;
8287let opExtentAlign = 2;
8288}
8289def J4_cmplt_f_jumpnv_nt : HInst<
8290(outs),
8291(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8292"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8293tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8294let Inst{0-0} = 0b0;
8295let Inst{13-13} = 0b0;
8296let Inst{19-19} = 0b0;
8297let Inst{31-22} = 0b0010000111;
8298let isPredicated = 1;
8299let isPredicatedFalse = 1;
8300let isTerminator = 1;
8301let isBranch = 1;
8302let isNewValue = 1;
8303let cofMax1 = 1;
8304let isRestrictNoSlot1Store = 1;
8305let Defs = [PC];
8306let BaseOpcode = "J4_cmpltr";
8307let isTaken = Inst{13};
8308let isExtendable = 1;
8309let opExtendable = 2;
8310let isExtentSigned = 1;
8311let opExtentBits = 11;
8312let opExtentAlign = 2;
8313let opNewValue = 1;
8314}
8315def J4_cmplt_f_jumpnv_t : HInst<
8316(outs),
8317(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8318"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8319tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8320let Inst{0-0} = 0b0;
8321let Inst{13-13} = 0b1;
8322let Inst{19-19} = 0b0;
8323let Inst{31-22} = 0b0010000111;
8324let isPredicated = 1;
8325let isPredicatedFalse = 1;
8326let isTerminator = 1;
8327let isBranch = 1;
8328let isNewValue = 1;
8329let cofMax1 = 1;
8330let isRestrictNoSlot1Store = 1;
8331let Defs = [PC];
8332let BaseOpcode = "J4_cmpltr";
8333let isTaken = Inst{13};
8334let isExtendable = 1;
8335let opExtendable = 2;
8336let isExtentSigned = 1;
8337let opExtentBits = 11;
8338let opExtentAlign = 2;
8339let opNewValue = 1;
8340}
8341def J4_cmplt_t_jumpnv_nt : HInst<
8342(outs),
8343(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8344"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8345tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8346let Inst{0-0} = 0b0;
8347let Inst{13-13} = 0b0;
8348let Inst{19-19} = 0b0;
8349let Inst{31-22} = 0b0010000110;
8350let isPredicated = 1;
8351let isTerminator = 1;
8352let isBranch = 1;
8353let isNewValue = 1;
8354let cofMax1 = 1;
8355let isRestrictNoSlot1Store = 1;
8356let Defs = [PC];
8357let BaseOpcode = "J4_cmpltr";
8358let isTaken = Inst{13};
8359let isExtendable = 1;
8360let opExtendable = 2;
8361let isExtentSigned = 1;
8362let opExtentBits = 11;
8363let opExtentAlign = 2;
8364let opNewValue = 1;
8365}
8366def J4_cmplt_t_jumpnv_t : HInst<
8367(outs),
8368(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8369"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8370tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8371let Inst{0-0} = 0b0;
8372let Inst{13-13} = 0b1;
8373let Inst{19-19} = 0b0;
8374let Inst{31-22} = 0b0010000110;
8375let isPredicated = 1;
8376let isTerminator = 1;
8377let isBranch = 1;
8378let isNewValue = 1;
8379let cofMax1 = 1;
8380let isRestrictNoSlot1Store = 1;
8381let Defs = [PC];
8382let BaseOpcode = "J4_cmpltr";
8383let isTaken = Inst{13};
8384let isExtendable = 1;
8385let opExtendable = 2;
8386let isExtentSigned = 1;
8387let opExtentBits = 11;
8388let opExtentAlign = 2;
8389let opNewValue = 1;
8390}
8391def J4_cmpltu_f_jumpnv_nt : HInst<
8392(outs),
8393(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8394"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8395tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8396let Inst{0-0} = 0b0;
8397let Inst{13-13} = 0b0;
8398let Inst{19-19} = 0b0;
8399let Inst{31-22} = 0b0010001001;
8400let isPredicated = 1;
8401let isPredicatedFalse = 1;
8402let isTerminator = 1;
8403let isBranch = 1;
8404let isNewValue = 1;
8405let cofMax1 = 1;
8406let isRestrictNoSlot1Store = 1;
8407let Defs = [PC];
8408let BaseOpcode = "J4_cmpltur";
8409let isTaken = Inst{13};
8410let isExtendable = 1;
8411let opExtendable = 2;
8412let isExtentSigned = 1;
8413let opExtentBits = 11;
8414let opExtentAlign = 2;
8415let opNewValue = 1;
8416}
8417def J4_cmpltu_f_jumpnv_t : HInst<
8418(outs),
8419(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8420"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8421tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8422let Inst{0-0} = 0b0;
8423let Inst{13-13} = 0b1;
8424let Inst{19-19} = 0b0;
8425let Inst{31-22} = 0b0010001001;
8426let isPredicated = 1;
8427let isPredicatedFalse = 1;
8428let isTerminator = 1;
8429let isBranch = 1;
8430let isNewValue = 1;
8431let cofMax1 = 1;
8432let isRestrictNoSlot1Store = 1;
8433let Defs = [PC];
8434let BaseOpcode = "J4_cmpltur";
8435let isTaken = Inst{13};
8436let isExtendable = 1;
8437let opExtendable = 2;
8438let isExtentSigned = 1;
8439let opExtentBits = 11;
8440let opExtentAlign = 2;
8441let opNewValue = 1;
8442}
8443def J4_cmpltu_t_jumpnv_nt : HInst<
8444(outs),
8445(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8446"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8447tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8448let Inst{0-0} = 0b0;
8449let Inst{13-13} = 0b0;
8450let Inst{19-19} = 0b0;
8451let Inst{31-22} = 0b0010001000;
8452let isPredicated = 1;
8453let isTerminator = 1;
8454let isBranch = 1;
8455let isNewValue = 1;
8456let cofMax1 = 1;
8457let isRestrictNoSlot1Store = 1;
8458let Defs = [PC];
8459let BaseOpcode = "J4_cmpltur";
8460let isTaken = Inst{13};
8461let isExtendable = 1;
8462let opExtendable = 2;
8463let isExtentSigned = 1;
8464let opExtentBits = 11;
8465let opExtentAlign = 2;
8466let opNewValue = 1;
8467}
8468def J4_cmpltu_t_jumpnv_t : HInst<
8469(outs),
8470(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8471"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8472tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8473let Inst{0-0} = 0b0;
8474let Inst{13-13} = 0b1;
8475let Inst{19-19} = 0b0;
8476let Inst{31-22} = 0b0010001000;
8477let isPredicated = 1;
8478let isTerminator = 1;
8479let isBranch = 1;
8480let isNewValue = 1;
8481let cofMax1 = 1;
8482let isRestrictNoSlot1Store = 1;
8483let Defs = [PC];
8484let BaseOpcode = "J4_cmpltur";
8485let isTaken = Inst{13};
8486let isExtendable = 1;
8487let opExtendable = 2;
8488let isExtentSigned = 1;
8489let opExtentBits = 11;
8490let opExtentAlign = 2;
8491let opNewValue = 1;
8492}
8493def J4_hintjumpr : HInst<
8494(outs),
8495(ins IntRegs:$Rs32),
8496"hintjr($Rs32)",
8497tc_60e324ff, TypeJ>, Enc_ecbcc8 {
8498let Inst{13-0} = 0b00000000000000;
8499let Inst{31-21} = 0b01010010101;
8500let isTerminator = 1;
8501let isIndirectBranch = 1;
8502let isBranch = 1;
8503let cofMax1 = 1;
8504}
8505def J4_jumpseti : HInst<
8506(outs GeneralSubRegs:$Rd16),
8507(ins u6_0Imm:$II, b30_2Imm:$Ii),
8508"$Rd16 = #$II ; jump $Ii",
8509tc_5502c366, TypeCJ>, Enc_9e4c3f {
8510let Inst{0-0} = 0b0;
8511let Inst{31-22} = 0b0001011000;
8512let hasNewValue = 1;
8513let opNewValue = 0;
8514let isTerminator = 1;
8515let isBranch = 1;
8516let cofRelax2 = 1;
8517let cofMax1 = 1;
8518let Defs = [PC];
8519let isExtendable = 1;
8520let opExtendable = 2;
8521let isExtentSigned = 1;
8522let opExtentBits = 11;
8523let opExtentAlign = 2;
8524}
8525def J4_jumpsetr : HInst<
8526(outs GeneralSubRegs:$Rd16),
8527(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8528"$Rd16 = $Rs16 ; jump $Ii",
8529tc_5502c366, TypeCJ>, Enc_66bce1 {
8530let Inst{0-0} = 0b0;
8531let Inst{13-12} = 0b00;
8532let Inst{31-22} = 0b0001011100;
8533let hasNewValue = 1;
8534let opNewValue = 0;
8535let isTerminator = 1;
8536let isBranch = 1;
8537let cofRelax2 = 1;
8538let cofMax1 = 1;
8539let Defs = [PC];
8540let isExtendable = 1;
8541let opExtendable = 2;
8542let isExtentSigned = 1;
8543let opExtentBits = 11;
8544let opExtentAlign = 2;
8545}
8546def J4_tstbit0_f_jumpnv_nt : HInst<
8547(outs),
8548(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8549"if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
8550tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8551let Inst{0-0} = 0b0;
8552let Inst{13-8} = 0b000000;
8553let Inst{19-19} = 0b0;
8554let Inst{31-22} = 0b0010010111;
8555let isPredicated = 1;
8556let isPredicatedFalse = 1;
8557let isTerminator = 1;
8558let isBranch = 1;
8559let isNewValue = 1;
8560let cofMax1 = 1;
8561let isRestrictNoSlot1Store = 1;
8562let Defs = [PC];
8563let isTaken = Inst{13};
8564let isExtendable = 1;
8565let opExtendable = 1;
8566let isExtentSigned = 1;
8567let opExtentBits = 11;
8568let opExtentAlign = 2;
8569let opNewValue = 0;
8570}
8571def J4_tstbit0_f_jumpnv_t : HInst<
8572(outs),
8573(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8574"if (!tstbit($Ns8.new,#0)) jump:t $Ii",
8575tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8576let Inst{0-0} = 0b0;
8577let Inst{13-8} = 0b100000;
8578let Inst{19-19} = 0b0;
8579let Inst{31-22} = 0b0010010111;
8580let isPredicated = 1;
8581let isPredicatedFalse = 1;
8582let isTerminator = 1;
8583let isBranch = 1;
8584let isNewValue = 1;
8585let cofMax1 = 1;
8586let isRestrictNoSlot1Store = 1;
8587let Defs = [PC];
8588let isTaken = Inst{13};
8589let isExtendable = 1;
8590let opExtendable = 1;
8591let isExtentSigned = 1;
8592let opExtentBits = 11;
8593let opExtentAlign = 2;
8594let opNewValue = 0;
8595}
8596def J4_tstbit0_fp0_jump_nt : HInst<
8597(outs),
8598(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8599"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
8600tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8601let Inst{0-0} = 0b0;
8602let Inst{13-8} = 0b000011;
8603let Inst{31-22} = 0b0001000111;
8604let isPredicated = 1;
8605let isPredicatedFalse = 1;
8606let isTerminator = 1;
8607let isBranch = 1;
8608let isPredicatedNew = 1;
8609let cofRelax1 = 1;
8610let cofRelax2 = 1;
8611let cofMax1 = 1;
8612let Uses = [P0];
8613let Defs = [P0, PC];
8614let isTaken = Inst{13};
8615let isExtendable = 1;
8616let opExtendable = 1;
8617let isExtentSigned = 1;
8618let opExtentBits = 11;
8619let opExtentAlign = 2;
8620}
8621def J4_tstbit0_fp0_jump_t : HInst<
8622(outs),
8623(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8624"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
8625tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8626let Inst{0-0} = 0b0;
8627let Inst{13-8} = 0b100011;
8628let Inst{31-22} = 0b0001000111;
8629let isPredicated = 1;
8630let isPredicatedFalse = 1;
8631let isTerminator = 1;
8632let isBranch = 1;
8633let isPredicatedNew = 1;
8634let cofRelax1 = 1;
8635let cofRelax2 = 1;
8636let cofMax1 = 1;
8637let Uses = [P0];
8638let Defs = [P0, PC];
8639let isTaken = Inst{13};
8640let isExtendable = 1;
8641let opExtendable = 1;
8642let isExtentSigned = 1;
8643let opExtentBits = 11;
8644let opExtentAlign = 2;
8645}
8646def J4_tstbit0_fp1_jump_nt : HInst<
8647(outs),
8648(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8649"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
8650tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8651let Inst{0-0} = 0b0;
8652let Inst{13-8} = 0b000011;
8653let Inst{31-22} = 0b0001001111;
8654let isPredicated = 1;
8655let isPredicatedFalse = 1;
8656let isTerminator = 1;
8657let isBranch = 1;
8658let isPredicatedNew = 1;
8659let cofRelax1 = 1;
8660let cofRelax2 = 1;
8661let cofMax1 = 1;
8662let Uses = [P1];
8663let Defs = [P1, PC];
8664let isTaken = Inst{13};
8665let isExtendable = 1;
8666let opExtendable = 1;
8667let isExtentSigned = 1;
8668let opExtentBits = 11;
8669let opExtentAlign = 2;
8670}
8671def J4_tstbit0_fp1_jump_t : HInst<
8672(outs),
8673(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8674"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
8675tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8676let Inst{0-0} = 0b0;
8677let Inst{13-8} = 0b100011;
8678let Inst{31-22} = 0b0001001111;
8679let isPredicated = 1;
8680let isPredicatedFalse = 1;
8681let isTerminator = 1;
8682let isBranch = 1;
8683let isPredicatedNew = 1;
8684let cofRelax1 = 1;
8685let cofRelax2 = 1;
8686let cofMax1 = 1;
8687let Uses = [P1];
8688let Defs = [P1, PC];
8689let isTaken = Inst{13};
8690let isExtendable = 1;
8691let opExtendable = 1;
8692let isExtentSigned = 1;
8693let opExtentBits = 11;
8694let opExtentAlign = 2;
8695}
8696def J4_tstbit0_t_jumpnv_nt : HInst<
8697(outs),
8698(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8699"if (tstbit($Ns8.new,#0)) jump:nt $Ii",
8700tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8701let Inst{0-0} = 0b0;
8702let Inst{13-8} = 0b000000;
8703let Inst{19-19} = 0b0;
8704let Inst{31-22} = 0b0010010110;
8705let isPredicated = 1;
8706let isTerminator = 1;
8707let isBranch = 1;
8708let isNewValue = 1;
8709let cofMax1 = 1;
8710let isRestrictNoSlot1Store = 1;
8711let Defs = [PC];
8712let isTaken = Inst{13};
8713let isExtendable = 1;
8714let opExtendable = 1;
8715let isExtentSigned = 1;
8716let opExtentBits = 11;
8717let opExtentAlign = 2;
8718let opNewValue = 0;
8719}
8720def J4_tstbit0_t_jumpnv_t : HInst<
8721(outs),
8722(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8723"if (tstbit($Ns8.new,#0)) jump:t $Ii",
8724tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8725let Inst{0-0} = 0b0;
8726let Inst{13-8} = 0b100000;
8727let Inst{19-19} = 0b0;
8728let Inst{31-22} = 0b0010010110;
8729let isPredicated = 1;
8730let isTerminator = 1;
8731let isBranch = 1;
8732let isNewValue = 1;
8733let cofMax1 = 1;
8734let isRestrictNoSlot1Store = 1;
8735let Defs = [PC];
8736let isTaken = Inst{13};
8737let isExtendable = 1;
8738let opExtendable = 1;
8739let isExtentSigned = 1;
8740let opExtentBits = 11;
8741let opExtentAlign = 2;
8742let opNewValue = 0;
8743}
8744def J4_tstbit0_tp0_jump_nt : HInst<
8745(outs),
8746(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8747"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
8748tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8749let Inst{0-0} = 0b0;
8750let Inst{13-8} = 0b000011;
8751let Inst{31-22} = 0b0001000110;
8752let isPredicated = 1;
8753let isTerminator = 1;
8754let isBranch = 1;
8755let isPredicatedNew = 1;
8756let cofRelax1 = 1;
8757let cofRelax2 = 1;
8758let cofMax1 = 1;
8759let Uses = [P0];
8760let Defs = [P0, PC];
8761let isTaken = Inst{13};
8762let isExtendable = 1;
8763let opExtendable = 1;
8764let isExtentSigned = 1;
8765let opExtentBits = 11;
8766let opExtentAlign = 2;
8767}
8768def J4_tstbit0_tp0_jump_t : HInst<
8769(outs),
8770(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8771"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
8772tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8773let Inst{0-0} = 0b0;
8774let Inst{13-8} = 0b100011;
8775let Inst{31-22} = 0b0001000110;
8776let isPredicated = 1;
8777let isTerminator = 1;
8778let isBranch = 1;
8779let isPredicatedNew = 1;
8780let cofRelax1 = 1;
8781let cofRelax2 = 1;
8782let cofMax1 = 1;
8783let Uses = [P0];
8784let Defs = [P0, PC];
8785let isTaken = Inst{13};
8786let isExtendable = 1;
8787let opExtendable = 1;
8788let isExtentSigned = 1;
8789let opExtentBits = 11;
8790let opExtentAlign = 2;
8791}
8792def J4_tstbit0_tp1_jump_nt : HInst<
8793(outs),
8794(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8795"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
8796tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8797let Inst{0-0} = 0b0;
8798let Inst{13-8} = 0b000011;
8799let Inst{31-22} = 0b0001001110;
8800let isPredicated = 1;
8801let isTerminator = 1;
8802let isBranch = 1;
8803let isPredicatedNew = 1;
8804let cofRelax1 = 1;
8805let cofRelax2 = 1;
8806let cofMax1 = 1;
8807let Uses = [P1];
8808let Defs = [P1, PC];
8809let isTaken = Inst{13};
8810let isExtendable = 1;
8811let opExtendable = 1;
8812let isExtentSigned = 1;
8813let opExtentBits = 11;
8814let opExtentAlign = 2;
8815}
8816def J4_tstbit0_tp1_jump_t : HInst<
8817(outs),
8818(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8819"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
8820tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8821let Inst{0-0} = 0b0;
8822let Inst{13-8} = 0b100011;
8823let Inst{31-22} = 0b0001001110;
8824let isPredicated = 1;
8825let isTerminator = 1;
8826let isBranch = 1;
8827let isPredicatedNew = 1;
8828let cofRelax1 = 1;
8829let cofRelax2 = 1;
8830let cofMax1 = 1;
8831let Uses = [P1];
8832let Defs = [P1, PC];
8833let isTaken = Inst{13};
8834let isExtendable = 1;
8835let opExtendable = 1;
8836let isExtentSigned = 1;
8837let opExtentBits = 11;
8838let opExtentAlign = 2;
8839}
8840def L2_deallocframe : HInst<
8841(outs DoubleRegs:$Rdd32),
8842(ins IntRegs:$Rs32),
8843"$Rdd32 = deallocframe($Rs32):raw",
8844tc_e9170fb7, TypeLD>, Enc_3a3d62 {
8845let Inst{13-5} = 0b000000000;
8846let Inst{31-21} = 0b10010000000;
8847let accessSize = DoubleWordAccess;
8848let mayLoad = 1;
8849let Uses = [FRAMEKEY];
8850let Defs = [R29];
8851}
8852def L2_loadalignb_io : HInst<
8853(outs DoubleRegs:$Ryy32),
8854(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
8855"$Ryy32 = memb_fifo($Rs32+#$Ii)",
8856tc_fedb7e19, TypeLD>, Enc_a27588 {
8857let Inst{24-21} = 0b0100;
8858let Inst{31-27} = 0b10010;
8859let addrMode = BaseImmOffset;
8860let accessSize = ByteAccess;
8861let mayLoad = 1;
8862let isExtendable = 1;
8863let opExtendable = 3;
8864let isExtentSigned = 1;
8865let opExtentBits = 11;
8866let opExtentAlign = 0;
8867let Constraints = "$Ryy32 = $Ryy32in";
8868}
8869def L2_loadalignb_pbr : HInst<
8870(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8871(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8872"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
8873tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8874let Inst{12-5} = 0b00000000;
8875let Inst{31-21} = 0b10011110100;
8876let addrMode = PostInc;
8877let accessSize = ByteAccess;
8878let mayLoad = 1;
8879let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8880}
8881def L2_loadalignb_pci : HInst<
8882(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8883(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
8884"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
8885tc_76bb5435, TypeLD>, Enc_74aef2 {
8886let Inst{12-9} = 0b0000;
8887let Inst{31-21} = 0b10011000100;
8888let addrMode = PostInc;
8889let accessSize = ByteAccess;
8890let mayLoad = 1;
8891let Uses = [CS];
8892let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8893}
8894def L2_loadalignb_pcr : HInst<
8895(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8896(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8897"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
8898tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8899let Inst{12-5} = 0b00010000;
8900let Inst{31-21} = 0b10011000100;
8901let addrMode = PostInc;
8902let accessSize = ByteAccess;
8903let mayLoad = 1;
8904let Uses = [CS];
8905let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8906}
8907def L2_loadalignb_pi : HInst<
8908(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8909(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
8910"$Ryy32 = memb_fifo($Rx32++#$Ii)",
8911tc_1c7522a8, TypeLD>, Enc_6b197f {
8912let Inst{13-9} = 0b00000;
8913let Inst{31-21} = 0b10011010100;
8914let addrMode = PostInc;
8915let accessSize = ByteAccess;
8916let mayLoad = 1;
8917let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8918}
8919def L2_loadalignb_pr : HInst<
8920(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8921(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8922"$Ryy32 = memb_fifo($Rx32++$Mu2)",
8923tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8924let Inst{12-5} = 0b00000000;
8925let Inst{31-21} = 0b10011100100;
8926let addrMode = PostInc;
8927let accessSize = ByteAccess;
8928let mayLoad = 1;
8929let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8930}
8931def L2_loadalignb_zomap : HInst<
8932(outs DoubleRegs:$Ryy32),
8933(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8934"$Ryy32 = memb_fifo($Rs32)",
8935tc_fedb7e19, TypeMAPPING> {
8936let isPseudo = 1;
8937let isCodeGenOnly = 1;
8938let Constraints = "$Ryy32 = $Ryy32in";
8939}
8940def L2_loadalignh_io : HInst<
8941(outs DoubleRegs:$Ryy32),
8942(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
8943"$Ryy32 = memh_fifo($Rs32+#$Ii)",
8944tc_fedb7e19, TypeLD>, Enc_5cd7e9 {
8945let Inst{24-21} = 0b0010;
8946let Inst{31-27} = 0b10010;
8947let addrMode = BaseImmOffset;
8948let accessSize = HalfWordAccess;
8949let mayLoad = 1;
8950let isExtendable = 1;
8951let opExtendable = 3;
8952let isExtentSigned = 1;
8953let opExtentBits = 12;
8954let opExtentAlign = 1;
8955let Constraints = "$Ryy32 = $Ryy32in";
8956}
8957def L2_loadalignh_pbr : HInst<
8958(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8959(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8960"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
8961tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8962let Inst{12-5} = 0b00000000;
8963let Inst{31-21} = 0b10011110010;
8964let addrMode = PostInc;
8965let accessSize = HalfWordAccess;
8966let mayLoad = 1;
8967let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8968}
8969def L2_loadalignh_pci : HInst<
8970(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8971(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
8972"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
8973tc_76bb5435, TypeLD>, Enc_9e2e1c {
8974let Inst{12-9} = 0b0000;
8975let Inst{31-21} = 0b10011000010;
8976let addrMode = PostInc;
8977let accessSize = HalfWordAccess;
8978let mayLoad = 1;
8979let Uses = [CS];
8980let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8981}
8982def L2_loadalignh_pcr : HInst<
8983(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8984(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8985"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
8986tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8987let Inst{12-5} = 0b00010000;
8988let Inst{31-21} = 0b10011000010;
8989let addrMode = PostInc;
8990let accessSize = HalfWordAccess;
8991let mayLoad = 1;
8992let Uses = [CS];
8993let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8994}
8995def L2_loadalignh_pi : HInst<
8996(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8997(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
8998"$Ryy32 = memh_fifo($Rx32++#$Ii)",
8999tc_1c7522a8, TypeLD>, Enc_bd1cbc {
9000let Inst{13-9} = 0b00000;
9001let Inst{31-21} = 0b10011010010;
9002let addrMode = PostInc;
9003let accessSize = HalfWordAccess;
9004let mayLoad = 1;
9005let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9006}
9007def L2_loadalignh_pr : HInst<
9008(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9009(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9010"$Ryy32 = memh_fifo($Rx32++$Mu2)",
9011tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9012let Inst{12-5} = 0b00000000;
9013let Inst{31-21} = 0b10011100010;
9014let addrMode = PostInc;
9015let accessSize = HalfWordAccess;
9016let mayLoad = 1;
9017let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9018}
9019def L2_loadalignh_zomap : HInst<
9020(outs DoubleRegs:$Ryy32),
9021(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
9022"$Ryy32 = memh_fifo($Rs32)",
9023tc_fedb7e19, TypeMAPPING> {
9024let isPseudo = 1;
9025let isCodeGenOnly = 1;
9026let Constraints = "$Ryy32 = $Ryy32in";
9027}
9028def L2_loadbsw2_io : HInst<
9029(outs IntRegs:$Rd32),
9030(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9031"$Rd32 = membh($Rs32+#$Ii)",
9032tc_4222e6bf, TypeLD>, Enc_de0214 {
9033let Inst{24-21} = 0b0001;
9034let Inst{31-27} = 0b10010;
9035let hasNewValue = 1;
9036let opNewValue = 0;
9037let addrMode = BaseImmOffset;
9038let accessSize = HalfWordAccess;
9039let mayLoad = 1;
9040let isExtendable = 1;
9041let opExtendable = 2;
9042let isExtentSigned = 1;
9043let opExtentBits = 12;
9044let opExtentAlign = 1;
9045}
9046def L2_loadbsw2_pbr : HInst<
9047(outs IntRegs:$Rd32, IntRegs:$Rx32),
9048(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9049"$Rd32 = membh($Rx32++$Mu2:brev)",
9050tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9051let Inst{12-5} = 0b00000000;
9052let Inst{31-21} = 0b10011110001;
9053let hasNewValue = 1;
9054let opNewValue = 0;
9055let addrMode = PostInc;
9056let accessSize = HalfWordAccess;
9057let mayLoad = 1;
9058let Constraints = "$Rx32 = $Rx32in";
9059}
9060def L2_loadbsw2_pci : HInst<
9061(outs IntRegs:$Rd32, IntRegs:$Rx32),
9062(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9063"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
9064tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9065let Inst{12-9} = 0b0000;
9066let Inst{31-21} = 0b10011000001;
9067let hasNewValue = 1;
9068let opNewValue = 0;
9069let addrMode = PostInc;
9070let accessSize = HalfWordAccess;
9071let mayLoad = 1;
9072let Uses = [CS];
9073let Constraints = "$Rx32 = $Rx32in";
9074}
9075def L2_loadbsw2_pcr : HInst<
9076(outs IntRegs:$Rd32, IntRegs:$Rx32),
9077(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9078"$Rd32 = membh($Rx32++I:circ($Mu2))",
9079tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9080let Inst{12-5} = 0b00010000;
9081let Inst{31-21} = 0b10011000001;
9082let hasNewValue = 1;
9083let opNewValue = 0;
9084let addrMode = PostInc;
9085let accessSize = HalfWordAccess;
9086let mayLoad = 1;
9087let Uses = [CS];
9088let Constraints = "$Rx32 = $Rx32in";
9089}
9090def L2_loadbsw2_pi : HInst<
9091(outs IntRegs:$Rd32, IntRegs:$Rx32),
9092(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9093"$Rd32 = membh($Rx32++#$Ii)",
9094tc_075c8dd8, TypeLD>, Enc_152467 {
9095let Inst{13-9} = 0b00000;
9096let Inst{31-21} = 0b10011010001;
9097let hasNewValue = 1;
9098let opNewValue = 0;
9099let addrMode = PostInc;
9100let accessSize = HalfWordAccess;
9101let mayLoad = 1;
9102let Constraints = "$Rx32 = $Rx32in";
9103}
9104def L2_loadbsw2_pr : HInst<
9105(outs IntRegs:$Rd32, IntRegs:$Rx32),
9106(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9107"$Rd32 = membh($Rx32++$Mu2)",
9108tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9109let Inst{12-5} = 0b00000000;
9110let Inst{31-21} = 0b10011100001;
9111let hasNewValue = 1;
9112let opNewValue = 0;
9113let addrMode = PostInc;
9114let accessSize = HalfWordAccess;
9115let mayLoad = 1;
9116let Constraints = "$Rx32 = $Rx32in";
9117}
9118def L2_loadbsw2_zomap : HInst<
9119(outs IntRegs:$Rd32),
9120(ins IntRegs:$Rs32),
9121"$Rd32 = membh($Rs32)",
9122tc_4222e6bf, TypeMAPPING> {
9123let hasNewValue = 1;
9124let opNewValue = 0;
9125let isPseudo = 1;
9126let isCodeGenOnly = 1;
9127}
9128def L2_loadbsw4_io : HInst<
9129(outs DoubleRegs:$Rdd32),
9130(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9131"$Rdd32 = membh($Rs32+#$Ii)",
9132tc_4222e6bf, TypeLD>, Enc_2d7491 {
9133let Inst{24-21} = 0b0111;
9134let Inst{31-27} = 0b10010;
9135let addrMode = BaseImmOffset;
9136let accessSize = WordAccess;
9137let mayLoad = 1;
9138let isExtendable = 1;
9139let opExtendable = 2;
9140let isExtentSigned = 1;
9141let opExtentBits = 13;
9142let opExtentAlign = 2;
9143}
9144def L2_loadbsw4_pbr : HInst<
9145(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9146(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9147"$Rdd32 = membh($Rx32++$Mu2:brev)",
9148tc_075c8dd8, TypeLD>, Enc_7eee72 {
9149let Inst{12-5} = 0b00000000;
9150let Inst{31-21} = 0b10011110111;
9151let addrMode = PostInc;
9152let accessSize = WordAccess;
9153let mayLoad = 1;
9154let Constraints = "$Rx32 = $Rx32in";
9155}
9156def L2_loadbsw4_pci : HInst<
9157(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9158(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9159"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
9160tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9161let Inst{12-9} = 0b0000;
9162let Inst{31-21} = 0b10011000111;
9163let addrMode = PostInc;
9164let accessSize = WordAccess;
9165let mayLoad = 1;
9166let Uses = [CS];
9167let Constraints = "$Rx32 = $Rx32in";
9168}
9169def L2_loadbsw4_pcr : HInst<
9170(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9171(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9172"$Rdd32 = membh($Rx32++I:circ($Mu2))",
9173tc_075c8dd8, TypeLD>, Enc_7eee72 {
9174let Inst{12-5} = 0b00010000;
9175let Inst{31-21} = 0b10011000111;
9176let addrMode = PostInc;
9177let accessSize = WordAccess;
9178let mayLoad = 1;
9179let Uses = [CS];
9180let Constraints = "$Rx32 = $Rx32in";
9181}
9182def L2_loadbsw4_pi : HInst<
9183(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9184(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9185"$Rdd32 = membh($Rx32++#$Ii)",
9186tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9187let Inst{13-9} = 0b00000;
9188let Inst{31-21} = 0b10011010111;
9189let addrMode = PostInc;
9190let accessSize = WordAccess;
9191let mayLoad = 1;
9192let Constraints = "$Rx32 = $Rx32in";
9193}
9194def L2_loadbsw4_pr : HInst<
9195(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9196(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9197"$Rdd32 = membh($Rx32++$Mu2)",
9198tc_075c8dd8, TypeLD>, Enc_7eee72 {
9199let Inst{12-5} = 0b00000000;
9200let Inst{31-21} = 0b10011100111;
9201let addrMode = PostInc;
9202let accessSize = WordAccess;
9203let mayLoad = 1;
9204let Constraints = "$Rx32 = $Rx32in";
9205}
9206def L2_loadbsw4_zomap : HInst<
9207(outs DoubleRegs:$Rdd32),
9208(ins IntRegs:$Rs32),
9209"$Rdd32 = membh($Rs32)",
9210tc_4222e6bf, TypeMAPPING> {
9211let isPseudo = 1;
9212let isCodeGenOnly = 1;
9213}
9214def L2_loadbzw2_io : HInst<
9215(outs IntRegs:$Rd32),
9216(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9217"$Rd32 = memubh($Rs32+#$Ii)",
9218tc_4222e6bf, TypeLD>, Enc_de0214 {
9219let Inst{24-21} = 0b0011;
9220let Inst{31-27} = 0b10010;
9221let hasNewValue = 1;
9222let opNewValue = 0;
9223let addrMode = BaseImmOffset;
9224let accessSize = HalfWordAccess;
9225let mayLoad = 1;
9226let isExtendable = 1;
9227let opExtendable = 2;
9228let isExtentSigned = 1;
9229let opExtentBits = 12;
9230let opExtentAlign = 1;
9231}
9232def L2_loadbzw2_pbr : HInst<
9233(outs IntRegs:$Rd32, IntRegs:$Rx32),
9234(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9235"$Rd32 = memubh($Rx32++$Mu2:brev)",
9236tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9237let Inst{12-5} = 0b00000000;
9238let Inst{31-21} = 0b10011110011;
9239let hasNewValue = 1;
9240let opNewValue = 0;
9241let addrMode = PostInc;
9242let accessSize = HalfWordAccess;
9243let mayLoad = 1;
9244let Constraints = "$Rx32 = $Rx32in";
9245}
9246def L2_loadbzw2_pci : HInst<
9247(outs IntRegs:$Rd32, IntRegs:$Rx32),
9248(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9249"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9250tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9251let Inst{12-9} = 0b0000;
9252let Inst{31-21} = 0b10011000011;
9253let hasNewValue = 1;
9254let opNewValue = 0;
9255let addrMode = PostInc;
9256let accessSize = HalfWordAccess;
9257let mayLoad = 1;
9258let Uses = [CS];
9259let Constraints = "$Rx32 = $Rx32in";
9260}
9261def L2_loadbzw2_pcr : HInst<
9262(outs IntRegs:$Rd32, IntRegs:$Rx32),
9263(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9264"$Rd32 = memubh($Rx32++I:circ($Mu2))",
9265tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9266let Inst{12-5} = 0b00010000;
9267let Inst{31-21} = 0b10011000011;
9268let hasNewValue = 1;
9269let opNewValue = 0;
9270let addrMode = PostInc;
9271let accessSize = HalfWordAccess;
9272let mayLoad = 1;
9273let Uses = [CS];
9274let Constraints = "$Rx32 = $Rx32in";
9275}
9276def L2_loadbzw2_pi : HInst<
9277(outs IntRegs:$Rd32, IntRegs:$Rx32),
9278(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9279"$Rd32 = memubh($Rx32++#$Ii)",
9280tc_075c8dd8, TypeLD>, Enc_152467 {
9281let Inst{13-9} = 0b00000;
9282let Inst{31-21} = 0b10011010011;
9283let hasNewValue = 1;
9284let opNewValue = 0;
9285let addrMode = PostInc;
9286let accessSize = HalfWordAccess;
9287let mayLoad = 1;
9288let Constraints = "$Rx32 = $Rx32in";
9289}
9290def L2_loadbzw2_pr : HInst<
9291(outs IntRegs:$Rd32, IntRegs:$Rx32),
9292(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9293"$Rd32 = memubh($Rx32++$Mu2)",
9294tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9295let Inst{12-5} = 0b00000000;
9296let Inst{31-21} = 0b10011100011;
9297let hasNewValue = 1;
9298let opNewValue = 0;
9299let addrMode = PostInc;
9300let accessSize = HalfWordAccess;
9301let mayLoad = 1;
9302let Constraints = "$Rx32 = $Rx32in";
9303}
9304def L2_loadbzw2_zomap : HInst<
9305(outs IntRegs:$Rd32),
9306(ins IntRegs:$Rs32),
9307"$Rd32 = memubh($Rs32)",
9308tc_4222e6bf, TypeMAPPING> {
9309let hasNewValue = 1;
9310let opNewValue = 0;
9311let isPseudo = 1;
9312let isCodeGenOnly = 1;
9313}
9314def L2_loadbzw4_io : HInst<
9315(outs DoubleRegs:$Rdd32),
9316(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9317"$Rdd32 = memubh($Rs32+#$Ii)",
9318tc_4222e6bf, TypeLD>, Enc_2d7491 {
9319let Inst{24-21} = 0b0101;
9320let Inst{31-27} = 0b10010;
9321let addrMode = BaseImmOffset;
9322let accessSize = WordAccess;
9323let mayLoad = 1;
9324let isExtendable = 1;
9325let opExtendable = 2;
9326let isExtentSigned = 1;
9327let opExtentBits = 13;
9328let opExtentAlign = 2;
9329}
9330def L2_loadbzw4_pbr : HInst<
9331(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9332(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9333"$Rdd32 = memubh($Rx32++$Mu2:brev)",
9334tc_075c8dd8, TypeLD>, Enc_7eee72 {
9335let Inst{12-5} = 0b00000000;
9336let Inst{31-21} = 0b10011110101;
9337let addrMode = PostInc;
9338let accessSize = WordAccess;
9339let mayLoad = 1;
9340let Constraints = "$Rx32 = $Rx32in";
9341}
9342def L2_loadbzw4_pci : HInst<
9343(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9344(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9345"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9346tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9347let Inst{12-9} = 0b0000;
9348let Inst{31-21} = 0b10011000101;
9349let addrMode = PostInc;
9350let accessSize = WordAccess;
9351let mayLoad = 1;
9352let Uses = [CS];
9353let Constraints = "$Rx32 = $Rx32in";
9354}
9355def L2_loadbzw4_pcr : HInst<
9356(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9357(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9358"$Rdd32 = memubh($Rx32++I:circ($Mu2))",
9359tc_075c8dd8, TypeLD>, Enc_7eee72 {
9360let Inst{12-5} = 0b00010000;
9361let Inst{31-21} = 0b10011000101;
9362let addrMode = PostInc;
9363let accessSize = WordAccess;
9364let mayLoad = 1;
9365let Uses = [CS];
9366let Constraints = "$Rx32 = $Rx32in";
9367}
9368def L2_loadbzw4_pi : HInst<
9369(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9370(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9371"$Rdd32 = memubh($Rx32++#$Ii)",
9372tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9373let Inst{13-9} = 0b00000;
9374let Inst{31-21} = 0b10011010101;
9375let addrMode = PostInc;
9376let accessSize = WordAccess;
9377let mayLoad = 1;
9378let Constraints = "$Rx32 = $Rx32in";
9379}
9380def L2_loadbzw4_pr : HInst<
9381(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9382(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9383"$Rdd32 = memubh($Rx32++$Mu2)",
9384tc_075c8dd8, TypeLD>, Enc_7eee72 {
9385let Inst{12-5} = 0b00000000;
9386let Inst{31-21} = 0b10011100101;
9387let addrMode = PostInc;
9388let accessSize = WordAccess;
9389let mayLoad = 1;
9390let Constraints = "$Rx32 = $Rx32in";
9391}
9392def L2_loadbzw4_zomap : HInst<
9393(outs DoubleRegs:$Rdd32),
9394(ins IntRegs:$Rs32),
9395"$Rdd32 = memubh($Rs32)",
9396tc_4222e6bf, TypeMAPPING> {
9397let isPseudo = 1;
9398let isCodeGenOnly = 1;
9399}
9400def L2_loadrb_io : HInst<
9401(outs IntRegs:$Rd32),
9402(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9403"$Rd32 = memb($Rs32+#$Ii)",
9404tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9405let Inst{24-21} = 0b1000;
9406let Inst{31-27} = 0b10010;
9407let hasNewValue = 1;
9408let opNewValue = 0;
9409let addrMode = BaseImmOffset;
9410let accessSize = ByteAccess;
9411let mayLoad = 1;
9412let BaseOpcode = "L2_loadrb_io";
9413let CextOpcode = "L2_loadrb";
9414let isPredicable = 1;
9415let isExtendable = 1;
9416let opExtendable = 2;
9417let isExtentSigned = 1;
9418let opExtentBits = 11;
9419let opExtentAlign = 0;
9420}
9421def L2_loadrb_pbr : HInst<
9422(outs IntRegs:$Rd32, IntRegs:$Rx32),
9423(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9424"$Rd32 = memb($Rx32++$Mu2:brev)",
9425tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9426let Inst{12-5} = 0b00000000;
9427let Inst{31-21} = 0b10011111000;
9428let hasNewValue = 1;
9429let opNewValue = 0;
9430let addrMode = PostInc;
9431let accessSize = ByteAccess;
9432let mayLoad = 1;
9433let Constraints = "$Rx32 = $Rx32in";
9434}
9435def L2_loadrb_pci : HInst<
9436(outs IntRegs:$Rd32, IntRegs:$Rx32),
9437(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9438"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
9439tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9440let Inst{12-9} = 0b0000;
9441let Inst{31-21} = 0b10011001000;
9442let hasNewValue = 1;
9443let opNewValue = 0;
9444let addrMode = PostInc;
9445let accessSize = ByteAccess;
9446let mayLoad = 1;
9447let Uses = [CS];
9448let Constraints = "$Rx32 = $Rx32in";
9449}
9450def L2_loadrb_pcr : HInst<
9451(outs IntRegs:$Rd32, IntRegs:$Rx32),
9452(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9453"$Rd32 = memb($Rx32++I:circ($Mu2))",
9454tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9455let Inst{12-5} = 0b00010000;
9456let Inst{31-21} = 0b10011001000;
9457let hasNewValue = 1;
9458let opNewValue = 0;
9459let addrMode = PostInc;
9460let accessSize = ByteAccess;
9461let mayLoad = 1;
9462let Uses = [CS];
9463let Constraints = "$Rx32 = $Rx32in";
9464}
9465def L2_loadrb_pi : HInst<
9466(outs IntRegs:$Rd32, IntRegs:$Rx32),
9467(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9468"$Rd32 = memb($Rx32++#$Ii)",
9469tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9470let Inst{13-9} = 0b00000;
9471let Inst{31-21} = 0b10011011000;
9472let hasNewValue = 1;
9473let opNewValue = 0;
9474let addrMode = PostInc;
9475let accessSize = ByteAccess;
9476let mayLoad = 1;
9477let BaseOpcode = "L2_loadrb_pi";
9478let CextOpcode = "L2_loadrb";
9479let isPredicable = 1;
9480let Constraints = "$Rx32 = $Rx32in";
9481}
9482def L2_loadrb_pr : HInst<
9483(outs IntRegs:$Rd32, IntRegs:$Rx32),
9484(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9485"$Rd32 = memb($Rx32++$Mu2)",
9486tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9487let Inst{12-5} = 0b00000000;
9488let Inst{31-21} = 0b10011101000;
9489let hasNewValue = 1;
9490let opNewValue = 0;
9491let addrMode = PostInc;
9492let accessSize = ByteAccess;
9493let mayLoad = 1;
9494let Constraints = "$Rx32 = $Rx32in";
9495}
9496def L2_loadrb_zomap : HInst<
9497(outs IntRegs:$Rd32),
9498(ins IntRegs:$Rs32),
9499"$Rd32 = memb($Rs32)",
9500tc_4222e6bf, TypeMAPPING> {
9501let hasNewValue = 1;
9502let opNewValue = 0;
9503let isPseudo = 1;
9504let isCodeGenOnly = 1;
9505}
9506def L2_loadrbgp : HInst<
9507(outs IntRegs:$Rd32),
9508(ins u32_0Imm:$Ii),
9509"$Rd32 = memb(gp+#$Ii)",
9510tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9511let Inst{24-21} = 0b1000;
9512let Inst{31-27} = 0b01001;
9513let hasNewValue = 1;
9514let opNewValue = 0;
9515let accessSize = ByteAccess;
9516let mayLoad = 1;
9517let Uses = [GP];
9518let BaseOpcode = "L4_loadrb_abs";
9519let isPredicable = 1;
9520let opExtendable = 1;
9521let isExtentSigned = 0;
9522let opExtentBits = 16;
9523let opExtentAlign = 0;
9524}
9525def L2_loadrd_io : HInst<
9526(outs DoubleRegs:$Rdd32),
9527(ins IntRegs:$Rs32, s29_3Imm:$Ii),
9528"$Rdd32 = memd($Rs32+#$Ii)",
9529tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
9530let Inst{24-21} = 0b1110;
9531let Inst{31-27} = 0b10010;
9532let addrMode = BaseImmOffset;
9533let accessSize = DoubleWordAccess;
9534let mayLoad = 1;
9535let BaseOpcode = "L2_loadrd_io";
9536let CextOpcode = "L2_loadrd";
9537let isPredicable = 1;
9538let isExtendable = 1;
9539let opExtendable = 2;
9540let isExtentSigned = 1;
9541let opExtentBits = 14;
9542let opExtentAlign = 3;
9543}
9544def L2_loadrd_pbr : HInst<
9545(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9546(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9547"$Rdd32 = memd($Rx32++$Mu2:brev)",
9548tc_075c8dd8, TypeLD>, Enc_7eee72 {
9549let Inst{12-5} = 0b00000000;
9550let Inst{31-21} = 0b10011111110;
9551let addrMode = PostInc;
9552let accessSize = DoubleWordAccess;
9553let mayLoad = 1;
9554let Constraints = "$Rx32 = $Rx32in";
9555}
9556def L2_loadrd_pci : HInst<
9557(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9558(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
9559"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
9560tc_5ceb2f9e, TypeLD>, Enc_b05839 {
9561let Inst{12-9} = 0b0000;
9562let Inst{31-21} = 0b10011001110;
9563let addrMode = PostInc;
9564let accessSize = DoubleWordAccess;
9565let mayLoad = 1;
9566let Uses = [CS];
9567let Constraints = "$Rx32 = $Rx32in";
9568}
9569def L2_loadrd_pcr : HInst<
9570(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9571(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9572"$Rdd32 = memd($Rx32++I:circ($Mu2))",
9573tc_075c8dd8, TypeLD>, Enc_7eee72 {
9574let Inst{12-5} = 0b00010000;
9575let Inst{31-21} = 0b10011001110;
9576let addrMode = PostInc;
9577let accessSize = DoubleWordAccess;
9578let mayLoad = 1;
9579let Uses = [CS];
9580let Constraints = "$Rx32 = $Rx32in";
9581}
9582def L2_loadrd_pi : HInst<
9583(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9584(ins IntRegs:$Rx32in, s4_3Imm:$Ii),
9585"$Rdd32 = memd($Rx32++#$Ii)",
9586tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
9587let Inst{13-9} = 0b00000;
9588let Inst{31-21} = 0b10011011110;
9589let addrMode = PostInc;
9590let accessSize = DoubleWordAccess;
9591let mayLoad = 1;
9592let BaseOpcode = "L2_loadrd_pi";
9593let CextOpcode = "L2_loadrd";
9594let isPredicable = 1;
9595let Constraints = "$Rx32 = $Rx32in";
9596}
9597def L2_loadrd_pr : HInst<
9598(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9599(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9600"$Rdd32 = memd($Rx32++$Mu2)",
9601tc_075c8dd8, TypeLD>, Enc_7eee72 {
9602let Inst{12-5} = 0b00000000;
9603let Inst{31-21} = 0b10011101110;
9604let addrMode = PostInc;
9605let accessSize = DoubleWordAccess;
9606let mayLoad = 1;
9607let Constraints = "$Rx32 = $Rx32in";
9608}
9609def L2_loadrd_zomap : HInst<
9610(outs DoubleRegs:$Rdd32),
9611(ins IntRegs:$Rs32),
9612"$Rdd32 = memd($Rs32)",
9613tc_4222e6bf, TypeMAPPING> {
9614let isPseudo = 1;
9615let isCodeGenOnly = 1;
9616}
9617def L2_loadrdgp : HInst<
9618(outs DoubleRegs:$Rdd32),
9619(ins u29_3Imm:$Ii),
9620"$Rdd32 = memd(gp+#$Ii)",
9621tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
9622let Inst{24-21} = 0b1110;
9623let Inst{31-27} = 0b01001;
9624let accessSize = DoubleWordAccess;
9625let mayLoad = 1;
9626let Uses = [GP];
9627let BaseOpcode = "L4_loadrd_abs";
9628let isPredicable = 1;
9629let opExtendable = 1;
9630let isExtentSigned = 0;
9631let opExtentBits = 19;
9632let opExtentAlign = 3;
9633}
9634def L2_loadrh_io : HInst<
9635(outs IntRegs:$Rd32),
9636(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9637"$Rd32 = memh($Rs32+#$Ii)",
9638tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9639let Inst{24-21} = 0b1010;
9640let Inst{31-27} = 0b10010;
9641let hasNewValue = 1;
9642let opNewValue = 0;
9643let addrMode = BaseImmOffset;
9644let accessSize = HalfWordAccess;
9645let mayLoad = 1;
9646let BaseOpcode = "L2_loadrh_io";
9647let CextOpcode = "L2_loadrh";
9648let isPredicable = 1;
9649let isExtendable = 1;
9650let opExtendable = 2;
9651let isExtentSigned = 1;
9652let opExtentBits = 12;
9653let opExtentAlign = 1;
9654}
9655def L2_loadrh_pbr : HInst<
9656(outs IntRegs:$Rd32, IntRegs:$Rx32),
9657(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9658"$Rd32 = memh($Rx32++$Mu2:brev)",
9659tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9660let Inst{12-5} = 0b00000000;
9661let Inst{31-21} = 0b10011111010;
9662let hasNewValue = 1;
9663let opNewValue = 0;
9664let addrMode = PostInc;
9665let accessSize = HalfWordAccess;
9666let mayLoad = 1;
9667let Constraints = "$Rx32 = $Rx32in";
9668}
9669def L2_loadrh_pci : HInst<
9670(outs IntRegs:$Rd32, IntRegs:$Rx32),
9671(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9672"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
9673tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9674let Inst{12-9} = 0b0000;
9675let Inst{31-21} = 0b10011001010;
9676let hasNewValue = 1;
9677let opNewValue = 0;
9678let addrMode = PostInc;
9679let accessSize = HalfWordAccess;
9680let mayLoad = 1;
9681let Uses = [CS];
9682let Constraints = "$Rx32 = $Rx32in";
9683}
9684def L2_loadrh_pcr : HInst<
9685(outs IntRegs:$Rd32, IntRegs:$Rx32),
9686(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9687"$Rd32 = memh($Rx32++I:circ($Mu2))",
9688tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9689let Inst{12-5} = 0b00010000;
9690let Inst{31-21} = 0b10011001010;
9691let hasNewValue = 1;
9692let opNewValue = 0;
9693let addrMode = PostInc;
9694let accessSize = HalfWordAccess;
9695let mayLoad = 1;
9696let Uses = [CS];
9697let Constraints = "$Rx32 = $Rx32in";
9698}
9699def L2_loadrh_pi : HInst<
9700(outs IntRegs:$Rd32, IntRegs:$Rx32),
9701(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9702"$Rd32 = memh($Rx32++#$Ii)",
9703tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9704let Inst{13-9} = 0b00000;
9705let Inst{31-21} = 0b10011011010;
9706let hasNewValue = 1;
9707let opNewValue = 0;
9708let addrMode = PostInc;
9709let accessSize = HalfWordAccess;
9710let mayLoad = 1;
9711let BaseOpcode = "L2_loadrh_pi";
9712let CextOpcode = "L2_loadrh";
9713let isPredicable = 1;
9714let Constraints = "$Rx32 = $Rx32in";
9715}
9716def L2_loadrh_pr : HInst<
9717(outs IntRegs:$Rd32, IntRegs:$Rx32),
9718(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9719"$Rd32 = memh($Rx32++$Mu2)",
9720tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9721let Inst{12-5} = 0b00000000;
9722let Inst{31-21} = 0b10011101010;
9723let hasNewValue = 1;
9724let opNewValue = 0;
9725let addrMode = PostInc;
9726let accessSize = HalfWordAccess;
9727let mayLoad = 1;
9728let Constraints = "$Rx32 = $Rx32in";
9729}
9730def L2_loadrh_zomap : HInst<
9731(outs IntRegs:$Rd32),
9732(ins IntRegs:$Rs32),
9733"$Rd32 = memh($Rs32)",
9734tc_4222e6bf, TypeMAPPING> {
9735let hasNewValue = 1;
9736let opNewValue = 0;
9737let isPseudo = 1;
9738let isCodeGenOnly = 1;
9739}
9740def L2_loadrhgp : HInst<
9741(outs IntRegs:$Rd32),
9742(ins u31_1Imm:$Ii),
9743"$Rd32 = memh(gp+#$Ii)",
9744tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9745let Inst{24-21} = 0b1010;
9746let Inst{31-27} = 0b01001;
9747let hasNewValue = 1;
9748let opNewValue = 0;
9749let accessSize = HalfWordAccess;
9750let mayLoad = 1;
9751let Uses = [GP];
9752let BaseOpcode = "L4_loadrh_abs";
9753let isPredicable = 1;
9754let opExtendable = 1;
9755let isExtentSigned = 0;
9756let opExtentBits = 17;
9757let opExtentAlign = 1;
9758}
9759def L2_loadri_io : HInst<
9760(outs IntRegs:$Rd32),
9761(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9762"$Rd32 = memw($Rs32+#$Ii)",
9763tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
9764let Inst{24-21} = 0b1100;
9765let Inst{31-27} = 0b10010;
9766let hasNewValue = 1;
9767let opNewValue = 0;
9768let addrMode = BaseImmOffset;
9769let accessSize = WordAccess;
9770let mayLoad = 1;
9771let BaseOpcode = "L2_loadri_io";
9772let CextOpcode = "L2_loadri";
9773let isPredicable = 1;
9774let isExtendable = 1;
9775let opExtendable = 2;
9776let isExtentSigned = 1;
9777let opExtentBits = 13;
9778let opExtentAlign = 2;
9779}
9780def L2_loadri_pbr : HInst<
9781(outs IntRegs:$Rd32, IntRegs:$Rx32),
9782(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9783"$Rd32 = memw($Rx32++$Mu2:brev)",
9784tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9785let Inst{12-5} = 0b00000000;
9786let Inst{31-21} = 0b10011111100;
9787let hasNewValue = 1;
9788let opNewValue = 0;
9789let addrMode = PostInc;
9790let accessSize = WordAccess;
9791let mayLoad = 1;
9792let Constraints = "$Rx32 = $Rx32in";
9793}
9794def L2_loadri_pci : HInst<
9795(outs IntRegs:$Rd32, IntRegs:$Rx32),
9796(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9797"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
9798tc_5ceb2f9e, TypeLD>, Enc_27fd0e {
9799let Inst{12-9} = 0b0000;
9800let Inst{31-21} = 0b10011001100;
9801let hasNewValue = 1;
9802let opNewValue = 0;
9803let addrMode = PostInc;
9804let accessSize = WordAccess;
9805let mayLoad = 1;
9806let Uses = [CS];
9807let Constraints = "$Rx32 = $Rx32in";
9808}
9809def L2_loadri_pcr : HInst<
9810(outs IntRegs:$Rd32, IntRegs:$Rx32),
9811(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9812"$Rd32 = memw($Rx32++I:circ($Mu2))",
9813tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9814let Inst{12-5} = 0b00010000;
9815let Inst{31-21} = 0b10011001100;
9816let hasNewValue = 1;
9817let opNewValue = 0;
9818let addrMode = PostInc;
9819let accessSize = WordAccess;
9820let mayLoad = 1;
9821let Uses = [CS];
9822let Constraints = "$Rx32 = $Rx32in";
9823}
9824def L2_loadri_pi : HInst<
9825(outs IntRegs:$Rd32, IntRegs:$Rx32),
9826(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9827"$Rd32 = memw($Rx32++#$Ii)",
9828tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
9829let Inst{13-9} = 0b00000;
9830let Inst{31-21} = 0b10011011100;
9831let hasNewValue = 1;
9832let opNewValue = 0;
9833let addrMode = PostInc;
9834let accessSize = WordAccess;
9835let mayLoad = 1;
9836let BaseOpcode = "L2_loadri_pi";
9837let CextOpcode = "L2_loadri";
9838let isPredicable = 1;
9839let Constraints = "$Rx32 = $Rx32in";
9840}
9841def L2_loadri_pr : HInst<
9842(outs IntRegs:$Rd32, IntRegs:$Rx32),
9843(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9844"$Rd32 = memw($Rx32++$Mu2)",
9845tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9846let Inst{12-5} = 0b00000000;
9847let Inst{31-21} = 0b10011101100;
9848let hasNewValue = 1;
9849let opNewValue = 0;
9850let addrMode = PostInc;
9851let accessSize = WordAccess;
9852let mayLoad = 1;
9853let Constraints = "$Rx32 = $Rx32in";
9854}
9855def L2_loadri_zomap : HInst<
9856(outs IntRegs:$Rd32),
9857(ins IntRegs:$Rs32),
9858"$Rd32 = memw($Rs32)",
9859tc_4222e6bf, TypeMAPPING> {
9860let hasNewValue = 1;
9861let opNewValue = 0;
9862let isPseudo = 1;
9863let isCodeGenOnly = 1;
9864}
9865def L2_loadrigp : HInst<
9866(outs IntRegs:$Rd32),
9867(ins u30_2Imm:$Ii),
9868"$Rd32 = memw(gp+#$Ii)",
9869tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
9870let Inst{24-21} = 0b1100;
9871let Inst{31-27} = 0b01001;
9872let hasNewValue = 1;
9873let opNewValue = 0;
9874let accessSize = WordAccess;
9875let mayLoad = 1;
9876let Uses = [GP];
9877let BaseOpcode = "L4_loadri_abs";
9878let isPredicable = 1;
9879let opExtendable = 1;
9880let isExtentSigned = 0;
9881let opExtentBits = 18;
9882let opExtentAlign = 2;
9883}
9884def L2_loadrub_io : HInst<
9885(outs IntRegs:$Rd32),
9886(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9887"$Rd32 = memub($Rs32+#$Ii)",
9888tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9889let Inst{24-21} = 0b1001;
9890let Inst{31-27} = 0b10010;
9891let hasNewValue = 1;
9892let opNewValue = 0;
9893let addrMode = BaseImmOffset;
9894let accessSize = ByteAccess;
9895let mayLoad = 1;
9896let BaseOpcode = "L2_loadrub_io";
9897let CextOpcode = "L2_loadrub";
9898let isPredicable = 1;
9899let isExtendable = 1;
9900let opExtendable = 2;
9901let isExtentSigned = 1;
9902let opExtentBits = 11;
9903let opExtentAlign = 0;
9904}
9905def L2_loadrub_pbr : HInst<
9906(outs IntRegs:$Rd32, IntRegs:$Rx32),
9907(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9908"$Rd32 = memub($Rx32++$Mu2:brev)",
9909tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9910let Inst{12-5} = 0b00000000;
9911let Inst{31-21} = 0b10011111001;
9912let hasNewValue = 1;
9913let opNewValue = 0;
9914let addrMode = PostInc;
9915let accessSize = ByteAccess;
9916let mayLoad = 1;
9917let Constraints = "$Rx32 = $Rx32in";
9918}
9919def L2_loadrub_pci : HInst<
9920(outs IntRegs:$Rd32, IntRegs:$Rx32),
9921(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9922"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
9923tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9924let Inst{12-9} = 0b0000;
9925let Inst{31-21} = 0b10011001001;
9926let hasNewValue = 1;
9927let opNewValue = 0;
9928let addrMode = PostInc;
9929let accessSize = ByteAccess;
9930let mayLoad = 1;
9931let Uses = [CS];
9932let Constraints = "$Rx32 = $Rx32in";
9933}
9934def L2_loadrub_pcr : HInst<
9935(outs IntRegs:$Rd32, IntRegs:$Rx32),
9936(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9937"$Rd32 = memub($Rx32++I:circ($Mu2))",
9938tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9939let Inst{12-5} = 0b00010000;
9940let Inst{31-21} = 0b10011001001;
9941let hasNewValue = 1;
9942let opNewValue = 0;
9943let addrMode = PostInc;
9944let accessSize = ByteAccess;
9945let mayLoad = 1;
9946let Uses = [CS];
9947let Constraints = "$Rx32 = $Rx32in";
9948}
9949def L2_loadrub_pi : HInst<
9950(outs IntRegs:$Rd32, IntRegs:$Rx32),
9951(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9952"$Rd32 = memub($Rx32++#$Ii)",
9953tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9954let Inst{13-9} = 0b00000;
9955let Inst{31-21} = 0b10011011001;
9956let hasNewValue = 1;
9957let opNewValue = 0;
9958let addrMode = PostInc;
9959let accessSize = ByteAccess;
9960let mayLoad = 1;
9961let BaseOpcode = "L2_loadrub_pi";
9962let CextOpcode = "L2_loadrub";
9963let isPredicable = 1;
9964let Constraints = "$Rx32 = $Rx32in";
9965}
9966def L2_loadrub_pr : HInst<
9967(outs IntRegs:$Rd32, IntRegs:$Rx32),
9968(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9969"$Rd32 = memub($Rx32++$Mu2)",
9970tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9971let Inst{12-5} = 0b00000000;
9972let Inst{31-21} = 0b10011101001;
9973let hasNewValue = 1;
9974let opNewValue = 0;
9975let addrMode = PostInc;
9976let accessSize = ByteAccess;
9977let mayLoad = 1;
9978let Constraints = "$Rx32 = $Rx32in";
9979}
9980def L2_loadrub_zomap : HInst<
9981(outs IntRegs:$Rd32),
9982(ins IntRegs:$Rs32),
9983"$Rd32 = memub($Rs32)",
9984tc_4222e6bf, TypeMAPPING> {
9985let hasNewValue = 1;
9986let opNewValue = 0;
9987let isPseudo = 1;
9988let isCodeGenOnly = 1;
9989}
9990def L2_loadrubgp : HInst<
9991(outs IntRegs:$Rd32),
9992(ins u32_0Imm:$Ii),
9993"$Rd32 = memub(gp+#$Ii)",
9994tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9995let Inst{24-21} = 0b1001;
9996let Inst{31-27} = 0b01001;
9997let hasNewValue = 1;
9998let opNewValue = 0;
9999let accessSize = ByteAccess;
10000let mayLoad = 1;
10001let Uses = [GP];
10002let BaseOpcode = "L4_loadrub_abs";
10003let isPredicable = 1;
10004let opExtendable = 1;
10005let isExtentSigned = 0;
10006let opExtentBits = 16;
10007let opExtentAlign = 0;
10008}
10009def L2_loadruh_io : HInst<
10010(outs IntRegs:$Rd32),
10011(ins IntRegs:$Rs32, s31_1Imm:$Ii),
10012"$Rd32 = memuh($Rs32+#$Ii)",
10013tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
10014let Inst{24-21} = 0b1011;
10015let Inst{31-27} = 0b10010;
10016let hasNewValue = 1;
10017let opNewValue = 0;
10018let addrMode = BaseImmOffset;
10019let accessSize = HalfWordAccess;
10020let mayLoad = 1;
10021let BaseOpcode = "L2_loadruh_io";
10022let CextOpcode = "L2_loadruh";
10023let isPredicable = 1;
10024let isExtendable = 1;
10025let opExtendable = 2;
10026let isExtentSigned = 1;
10027let opExtentBits = 12;
10028let opExtentAlign = 1;
10029}
10030def L2_loadruh_pbr : HInst<
10031(outs IntRegs:$Rd32, IntRegs:$Rx32),
10032(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10033"$Rd32 = memuh($Rx32++$Mu2:brev)",
10034tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10035let Inst{12-5} = 0b00000000;
10036let Inst{31-21} = 0b10011111011;
10037let hasNewValue = 1;
10038let opNewValue = 0;
10039let addrMode = PostInc;
10040let accessSize = HalfWordAccess;
10041let mayLoad = 1;
10042let Constraints = "$Rx32 = $Rx32in";
10043}
10044def L2_loadruh_pci : HInst<
10045(outs IntRegs:$Rd32, IntRegs:$Rx32),
10046(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
10047"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
10048tc_5ceb2f9e, TypeLD>, Enc_e83554 {
10049let Inst{12-9} = 0b0000;
10050let Inst{31-21} = 0b10011001011;
10051let hasNewValue = 1;
10052let opNewValue = 0;
10053let addrMode = PostInc;
10054let accessSize = HalfWordAccess;
10055let mayLoad = 1;
10056let Uses = [CS];
10057let Constraints = "$Rx32 = $Rx32in";
10058}
10059def L2_loadruh_pcr : HInst<
10060(outs IntRegs:$Rd32, IntRegs:$Rx32),
10061(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10062"$Rd32 = memuh($Rx32++I:circ($Mu2))",
10063tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10064let Inst{12-5} = 0b00010000;
10065let Inst{31-21} = 0b10011001011;
10066let hasNewValue = 1;
10067let opNewValue = 0;
10068let addrMode = PostInc;
10069let accessSize = HalfWordAccess;
10070let mayLoad = 1;
10071let Uses = [CS];
10072let Constraints = "$Rx32 = $Rx32in";
10073}
10074def L2_loadruh_pi : HInst<
10075(outs IntRegs:$Rd32, IntRegs:$Rx32),
10076(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
10077"$Rd32 = memuh($Rx32++#$Ii)",
10078tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
10079let Inst{13-9} = 0b00000;
10080let Inst{31-21} = 0b10011011011;
10081let hasNewValue = 1;
10082let opNewValue = 0;
10083let addrMode = PostInc;
10084let accessSize = HalfWordAccess;
10085let mayLoad = 1;
10086let BaseOpcode = "L2_loadruh_pi";
10087let CextOpcode = "L2_loadruh";
10088let isPredicable = 1;
10089let Constraints = "$Rx32 = $Rx32in";
10090}
10091def L2_loadruh_pr : HInst<
10092(outs IntRegs:$Rd32, IntRegs:$Rx32),
10093(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10094"$Rd32 = memuh($Rx32++$Mu2)",
10095tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10096let Inst{12-5} = 0b00000000;
10097let Inst{31-21} = 0b10011101011;
10098let hasNewValue = 1;
10099let opNewValue = 0;
10100let addrMode = PostInc;
10101let accessSize = HalfWordAccess;
10102let mayLoad = 1;
10103let Constraints = "$Rx32 = $Rx32in";
10104}
10105def L2_loadruh_zomap : HInst<
10106(outs IntRegs:$Rd32),
10107(ins IntRegs:$Rs32),
10108"$Rd32 = memuh($Rs32)",
10109tc_4222e6bf, TypeMAPPING> {
10110let hasNewValue = 1;
10111let opNewValue = 0;
10112let isPseudo = 1;
10113let isCodeGenOnly = 1;
10114}
10115def L2_loadruhgp : HInst<
10116(outs IntRegs:$Rd32),
10117(ins u31_1Imm:$Ii),
10118"$Rd32 = memuh(gp+#$Ii)",
10119tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
10120let Inst{24-21} = 0b1011;
10121let Inst{31-27} = 0b01001;
10122let hasNewValue = 1;
10123let opNewValue = 0;
10124let accessSize = HalfWordAccess;
10125let mayLoad = 1;
10126let Uses = [GP];
10127let BaseOpcode = "L4_loadruh_abs";
10128let isPredicable = 1;
10129let opExtendable = 1;
10130let isExtentSigned = 0;
10131let opExtentBits = 17;
10132let opExtentAlign = 1;
10133}
10134def L2_loadw_locked : HInst<
10135(outs IntRegs:$Rd32),
10136(ins IntRegs:$Rs32),
10137"$Rd32 = memw_locked($Rs32)",
10138tc_64b00d8a, TypeLD>, Enc_5e2823 {
10139let Inst{13-5} = 0b000000000;
10140let Inst{31-21} = 0b10010010000;
10141let hasNewValue = 1;
10142let opNewValue = 0;
10143let accessSize = WordAccess;
10144let mayLoad = 1;
10145let isSoloAX = 1;
10146}
10147def L2_ploadrbf_io : HInst<
10148(outs IntRegs:$Rd32),
10149(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10150"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
10151tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10152let Inst{13-13} = 0b0;
10153let Inst{31-21} = 0b01000101000;
10154let isPredicated = 1;
10155let isPredicatedFalse = 1;
10156let hasNewValue = 1;
10157let opNewValue = 0;
10158let addrMode = BaseImmOffset;
10159let accessSize = ByteAccess;
10160let mayLoad = 1;
10161let BaseOpcode = "L2_loadrb_io";
10162let CextOpcode = "L2_loadrb";
10163let isExtendable = 1;
10164let opExtendable = 3;
10165let isExtentSigned = 0;
10166let opExtentBits = 6;
10167let opExtentAlign = 0;
10168}
10169def L2_ploadrbf_pi : HInst<
10170(outs IntRegs:$Rd32, IntRegs:$Rx32),
10171(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10172"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
10173tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10174let Inst{13-11} = 0b101;
10175let Inst{31-21} = 0b10011011000;
10176let isPredicated = 1;
10177let isPredicatedFalse = 1;
10178let hasNewValue = 1;
10179let opNewValue = 0;
10180let addrMode = PostInc;
10181let accessSize = ByteAccess;
10182let mayLoad = 1;
10183let BaseOpcode = "L2_loadrb_pi";
10184let Constraints = "$Rx32 = $Rx32in";
10185}
10186def L2_ploadrbf_zomap : HInst<
10187(outs IntRegs:$Rd32),
10188(ins PredRegs:$Pt4, IntRegs:$Rs32),
10189"if (!$Pt4) $Rd32 = memb($Rs32)",
10190tc_fedb7e19, TypeMAPPING> {
10191let hasNewValue = 1;
10192let opNewValue = 0;
10193let isPseudo = 1;
10194let isCodeGenOnly = 1;
10195}
10196def L2_ploadrbfnew_io : HInst<
10197(outs IntRegs:$Rd32),
10198(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10199"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10200tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10201let Inst{13-13} = 0b0;
10202let Inst{31-21} = 0b01000111000;
10203let isPredicated = 1;
10204let isPredicatedFalse = 1;
10205let hasNewValue = 1;
10206let opNewValue = 0;
10207let addrMode = BaseImmOffset;
10208let accessSize = ByteAccess;
10209let isPredicatedNew = 1;
10210let mayLoad = 1;
10211let BaseOpcode = "L2_loadrb_io";
10212let CextOpcode = "L2_loadrb";
10213let isExtendable = 1;
10214let opExtendable = 3;
10215let isExtentSigned = 0;
10216let opExtentBits = 6;
10217let opExtentAlign = 0;
10218}
10219def L2_ploadrbfnew_pi : HInst<
10220(outs IntRegs:$Rd32, IntRegs:$Rx32),
10221(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10222"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10223tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10224let Inst{13-11} = 0b111;
10225let Inst{31-21} = 0b10011011000;
10226let isPredicated = 1;
10227let isPredicatedFalse = 1;
10228let hasNewValue = 1;
10229let opNewValue = 0;
10230let addrMode = PostInc;
10231let accessSize = ByteAccess;
10232let isPredicatedNew = 1;
10233let mayLoad = 1;
10234let BaseOpcode = "L2_loadrb_pi";
10235let Constraints = "$Rx32 = $Rx32in";
10236}
10237def L2_ploadrbfnew_zomap : HInst<
10238(outs IntRegs:$Rd32),
10239(ins PredRegs:$Pt4, IntRegs:$Rs32),
10240"if (!$Pt4.new) $Rd32 = memb($Rs32)",
10241tc_075c8dd8, TypeMAPPING> {
10242let hasNewValue = 1;
10243let opNewValue = 0;
10244let isPseudo = 1;
10245let isCodeGenOnly = 1;
10246}
10247def L2_ploadrbt_io : HInst<
10248(outs IntRegs:$Rd32),
10249(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10250"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
10251tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10252let Inst{13-13} = 0b0;
10253let Inst{31-21} = 0b01000001000;
10254let isPredicated = 1;
10255let hasNewValue = 1;
10256let opNewValue = 0;
10257let addrMode = BaseImmOffset;
10258let accessSize = ByteAccess;
10259let mayLoad = 1;
10260let BaseOpcode = "L2_loadrb_io";
10261let CextOpcode = "L2_loadrb";
10262let isExtendable = 1;
10263let opExtendable = 3;
10264let isExtentSigned = 0;
10265let opExtentBits = 6;
10266let opExtentAlign = 0;
10267}
10268def L2_ploadrbt_pi : HInst<
10269(outs IntRegs:$Rd32, IntRegs:$Rx32),
10270(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10271"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
10272tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10273let Inst{13-11} = 0b100;
10274let Inst{31-21} = 0b10011011000;
10275let isPredicated = 1;
10276let hasNewValue = 1;
10277let opNewValue = 0;
10278let addrMode = PostInc;
10279let accessSize = ByteAccess;
10280let mayLoad = 1;
10281let BaseOpcode = "L2_loadrb_pi";
10282let Constraints = "$Rx32 = $Rx32in";
10283}
10284def L2_ploadrbt_zomap : HInst<
10285(outs IntRegs:$Rd32),
10286(ins PredRegs:$Pt4, IntRegs:$Rs32),
10287"if ($Pt4) $Rd32 = memb($Rs32)",
10288tc_fedb7e19, TypeMAPPING> {
10289let hasNewValue = 1;
10290let opNewValue = 0;
10291let isPseudo = 1;
10292let isCodeGenOnly = 1;
10293}
10294def L2_ploadrbtnew_io : HInst<
10295(outs IntRegs:$Rd32),
10296(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10297"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10298tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10299let Inst{13-13} = 0b0;
10300let Inst{31-21} = 0b01000011000;
10301let isPredicated = 1;
10302let hasNewValue = 1;
10303let opNewValue = 0;
10304let addrMode = BaseImmOffset;
10305let accessSize = ByteAccess;
10306let isPredicatedNew = 1;
10307let mayLoad = 1;
10308let BaseOpcode = "L2_loadrb_io";
10309let CextOpcode = "L2_loadrb";
10310let isExtendable = 1;
10311let opExtendable = 3;
10312let isExtentSigned = 0;
10313let opExtentBits = 6;
10314let opExtentAlign = 0;
10315}
10316def L2_ploadrbtnew_pi : HInst<
10317(outs IntRegs:$Rd32, IntRegs:$Rx32),
10318(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10319"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10320tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10321let Inst{13-11} = 0b110;
10322let Inst{31-21} = 0b10011011000;
10323let isPredicated = 1;
10324let hasNewValue = 1;
10325let opNewValue = 0;
10326let addrMode = PostInc;
10327let accessSize = ByteAccess;
10328let isPredicatedNew = 1;
10329let mayLoad = 1;
10330let BaseOpcode = "L2_loadrb_pi";
10331let Constraints = "$Rx32 = $Rx32in";
10332}
10333def L2_ploadrbtnew_zomap : HInst<
10334(outs IntRegs:$Rd32),
10335(ins PredRegs:$Pt4, IntRegs:$Rs32),
10336"if ($Pt4.new) $Rd32 = memb($Rs32)",
10337tc_075c8dd8, TypeMAPPING> {
10338let hasNewValue = 1;
10339let opNewValue = 0;
10340let isPseudo = 1;
10341let isCodeGenOnly = 1;
10342}
10343def L2_ploadrdf_io : HInst<
10344(outs DoubleRegs:$Rdd32),
10345(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10346"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10347tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10348let Inst{13-13} = 0b0;
10349let Inst{31-21} = 0b01000101110;
10350let isPredicated = 1;
10351let isPredicatedFalse = 1;
10352let addrMode = BaseImmOffset;
10353let accessSize = DoubleWordAccess;
10354let mayLoad = 1;
10355let BaseOpcode = "L2_loadrd_io";
10356let CextOpcode = "L2_loadrd";
10357let isExtendable = 1;
10358let opExtendable = 3;
10359let isExtentSigned = 0;
10360let opExtentBits = 9;
10361let opExtentAlign = 3;
10362}
10363def L2_ploadrdf_pi : HInst<
10364(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10365(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10366"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10367tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10368let Inst{13-11} = 0b101;
10369let Inst{31-21} = 0b10011011110;
10370let isPredicated = 1;
10371let isPredicatedFalse = 1;
10372let addrMode = PostInc;
10373let accessSize = DoubleWordAccess;
10374let mayLoad = 1;
10375let BaseOpcode = "L2_loadrd_pi";
10376let Constraints = "$Rx32 = $Rx32in";
10377}
10378def L2_ploadrdf_zomap : HInst<
10379(outs DoubleRegs:$Rdd32),
10380(ins PredRegs:$Pt4, IntRegs:$Rs32),
10381"if (!$Pt4) $Rdd32 = memd($Rs32)",
10382tc_fedb7e19, TypeMAPPING> {
10383let isPseudo = 1;
10384let isCodeGenOnly = 1;
10385}
10386def L2_ploadrdfnew_io : HInst<
10387(outs DoubleRegs:$Rdd32),
10388(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10389"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10390tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10391let Inst{13-13} = 0b0;
10392let Inst{31-21} = 0b01000111110;
10393let isPredicated = 1;
10394let isPredicatedFalse = 1;
10395let addrMode = BaseImmOffset;
10396let accessSize = DoubleWordAccess;
10397let isPredicatedNew = 1;
10398let mayLoad = 1;
10399let BaseOpcode = "L2_loadrd_io";
10400let CextOpcode = "L2_loadrd";
10401let isExtendable = 1;
10402let opExtendable = 3;
10403let isExtentSigned = 0;
10404let opExtentBits = 9;
10405let opExtentAlign = 3;
10406}
10407def L2_ploadrdfnew_pi : HInst<
10408(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10409(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10410"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10411tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10412let Inst{13-11} = 0b111;
10413let Inst{31-21} = 0b10011011110;
10414let isPredicated = 1;
10415let isPredicatedFalse = 1;
10416let addrMode = PostInc;
10417let accessSize = DoubleWordAccess;
10418let isPredicatedNew = 1;
10419let mayLoad = 1;
10420let BaseOpcode = "L2_loadrd_pi";
10421let Constraints = "$Rx32 = $Rx32in";
10422}
10423def L2_ploadrdfnew_zomap : HInst<
10424(outs DoubleRegs:$Rdd32),
10425(ins PredRegs:$Pt4, IntRegs:$Rs32),
10426"if (!$Pt4.new) $Rdd32 = memd($Rs32)",
10427tc_075c8dd8, TypeMAPPING> {
10428let isPseudo = 1;
10429let isCodeGenOnly = 1;
10430}
10431def L2_ploadrdt_io : HInst<
10432(outs DoubleRegs:$Rdd32),
10433(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10434"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10435tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10436let Inst{13-13} = 0b0;
10437let Inst{31-21} = 0b01000001110;
10438let isPredicated = 1;
10439let addrMode = BaseImmOffset;
10440let accessSize = DoubleWordAccess;
10441let mayLoad = 1;
10442let BaseOpcode = "L2_loadrd_io";
10443let CextOpcode = "L2_loadrd";
10444let isExtendable = 1;
10445let opExtendable = 3;
10446let isExtentSigned = 0;
10447let opExtentBits = 9;
10448let opExtentAlign = 3;
10449}
10450def L2_ploadrdt_pi : HInst<
10451(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10452(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10453"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10454tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10455let Inst{13-11} = 0b100;
10456let Inst{31-21} = 0b10011011110;
10457let isPredicated = 1;
10458let addrMode = PostInc;
10459let accessSize = DoubleWordAccess;
10460let mayLoad = 1;
10461let BaseOpcode = "L2_loadrd_pi";
10462let Constraints = "$Rx32 = $Rx32in";
10463}
10464def L2_ploadrdt_zomap : HInst<
10465(outs DoubleRegs:$Rdd32),
10466(ins PredRegs:$Pt4, IntRegs:$Rs32),
10467"if ($Pt4) $Rdd32 = memd($Rs32)",
10468tc_fedb7e19, TypeMAPPING> {
10469let isPseudo = 1;
10470let isCodeGenOnly = 1;
10471}
10472def L2_ploadrdtnew_io : HInst<
10473(outs DoubleRegs:$Rdd32),
10474(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10475"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10476tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10477let Inst{13-13} = 0b0;
10478let Inst{31-21} = 0b01000011110;
10479let isPredicated = 1;
10480let addrMode = BaseImmOffset;
10481let accessSize = DoubleWordAccess;
10482let isPredicatedNew = 1;
10483let mayLoad = 1;
10484let BaseOpcode = "L2_loadrd_io";
10485let CextOpcode = "L2_loadrd";
10486let isExtendable = 1;
10487let opExtendable = 3;
10488let isExtentSigned = 0;
10489let opExtentBits = 9;
10490let opExtentAlign = 3;
10491}
10492def L2_ploadrdtnew_pi : HInst<
10493(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10494(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10495"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10496tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10497let Inst{13-11} = 0b110;
10498let Inst{31-21} = 0b10011011110;
10499let isPredicated = 1;
10500let addrMode = PostInc;
10501let accessSize = DoubleWordAccess;
10502let isPredicatedNew = 1;
10503let mayLoad = 1;
10504let BaseOpcode = "L2_loadrd_pi";
10505let Constraints = "$Rx32 = $Rx32in";
10506}
10507def L2_ploadrdtnew_zomap : HInst<
10508(outs DoubleRegs:$Rdd32),
10509(ins PredRegs:$Pt4, IntRegs:$Rs32),
10510"if ($Pt4.new) $Rdd32 = memd($Rs32)",
10511tc_075c8dd8, TypeMAPPING> {
10512let isPseudo = 1;
10513let isCodeGenOnly = 1;
10514}
10515def L2_ploadrhf_io : HInst<
10516(outs IntRegs:$Rd32),
10517(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10518"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
10519tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10520let Inst{13-13} = 0b0;
10521let Inst{31-21} = 0b01000101010;
10522let isPredicated = 1;
10523let isPredicatedFalse = 1;
10524let hasNewValue = 1;
10525let opNewValue = 0;
10526let addrMode = BaseImmOffset;
10527let accessSize = HalfWordAccess;
10528let mayLoad = 1;
10529let BaseOpcode = "L2_loadrh_io";
10530let CextOpcode = "L2_loadrh";
10531let isExtendable = 1;
10532let opExtendable = 3;
10533let isExtentSigned = 0;
10534let opExtentBits = 7;
10535let opExtentAlign = 1;
10536}
10537def L2_ploadrhf_pi : HInst<
10538(outs IntRegs:$Rd32, IntRegs:$Rx32),
10539(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10540"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
10541tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10542let Inst{13-11} = 0b101;
10543let Inst{31-21} = 0b10011011010;
10544let isPredicated = 1;
10545let isPredicatedFalse = 1;
10546let hasNewValue = 1;
10547let opNewValue = 0;
10548let addrMode = PostInc;
10549let accessSize = HalfWordAccess;
10550let mayLoad = 1;
10551let BaseOpcode = "L2_loadrh_pi";
10552let Constraints = "$Rx32 = $Rx32in";
10553}
10554def L2_ploadrhf_zomap : HInst<
10555(outs IntRegs:$Rd32),
10556(ins PredRegs:$Pt4, IntRegs:$Rs32),
10557"if (!$Pt4) $Rd32 = memh($Rs32)",
10558tc_fedb7e19, TypeMAPPING> {
10559let hasNewValue = 1;
10560let opNewValue = 0;
10561let isPseudo = 1;
10562let isCodeGenOnly = 1;
10563}
10564def L2_ploadrhfnew_io : HInst<
10565(outs IntRegs:$Rd32),
10566(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10567"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10568tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10569let Inst{13-13} = 0b0;
10570let Inst{31-21} = 0b01000111010;
10571let isPredicated = 1;
10572let isPredicatedFalse = 1;
10573let hasNewValue = 1;
10574let opNewValue = 0;
10575let addrMode = BaseImmOffset;
10576let accessSize = HalfWordAccess;
10577let isPredicatedNew = 1;
10578let mayLoad = 1;
10579let BaseOpcode = "L2_loadrh_io";
10580let CextOpcode = "L2_loadrh";
10581let isExtendable = 1;
10582let opExtendable = 3;
10583let isExtentSigned = 0;
10584let opExtentBits = 7;
10585let opExtentAlign = 1;
10586}
10587def L2_ploadrhfnew_pi : HInst<
10588(outs IntRegs:$Rd32, IntRegs:$Rx32),
10589(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10590"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10591tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10592let Inst{13-11} = 0b111;
10593let Inst{31-21} = 0b10011011010;
10594let isPredicated = 1;
10595let isPredicatedFalse = 1;
10596let hasNewValue = 1;
10597let opNewValue = 0;
10598let addrMode = PostInc;
10599let accessSize = HalfWordAccess;
10600let isPredicatedNew = 1;
10601let mayLoad = 1;
10602let BaseOpcode = "L2_loadrh_pi";
10603let Constraints = "$Rx32 = $Rx32in";
10604}
10605def L2_ploadrhfnew_zomap : HInst<
10606(outs IntRegs:$Rd32),
10607(ins PredRegs:$Pt4, IntRegs:$Rs32),
10608"if (!$Pt4.new) $Rd32 = memh($Rs32)",
10609tc_075c8dd8, TypeMAPPING> {
10610let hasNewValue = 1;
10611let opNewValue = 0;
10612let isPseudo = 1;
10613let isCodeGenOnly = 1;
10614}
10615def L2_ploadrht_io : HInst<
10616(outs IntRegs:$Rd32),
10617(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10618"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
10619tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10620let Inst{13-13} = 0b0;
10621let Inst{31-21} = 0b01000001010;
10622let isPredicated = 1;
10623let hasNewValue = 1;
10624let opNewValue = 0;
10625let addrMode = BaseImmOffset;
10626let accessSize = HalfWordAccess;
10627let mayLoad = 1;
10628let BaseOpcode = "L2_loadrh_io";
10629let CextOpcode = "L2_loadrh";
10630let isExtendable = 1;
10631let opExtendable = 3;
10632let isExtentSigned = 0;
10633let opExtentBits = 7;
10634let opExtentAlign = 1;
10635}
10636def L2_ploadrht_pi : HInst<
10637(outs IntRegs:$Rd32, IntRegs:$Rx32),
10638(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10639"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
10640tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10641let Inst{13-11} = 0b100;
10642let Inst{31-21} = 0b10011011010;
10643let isPredicated = 1;
10644let hasNewValue = 1;
10645let opNewValue = 0;
10646let addrMode = PostInc;
10647let accessSize = HalfWordAccess;
10648let mayLoad = 1;
10649let BaseOpcode = "L2_loadrh_pi";
10650let Constraints = "$Rx32 = $Rx32in";
10651}
10652def L2_ploadrht_zomap : HInst<
10653(outs IntRegs:$Rd32),
10654(ins PredRegs:$Pt4, IntRegs:$Rs32),
10655"if ($Pt4) $Rd32 = memh($Rs32)",
10656tc_fedb7e19, TypeMAPPING> {
10657let hasNewValue = 1;
10658let opNewValue = 0;
10659let isPseudo = 1;
10660let isCodeGenOnly = 1;
10661}
10662def L2_ploadrhtnew_io : HInst<
10663(outs IntRegs:$Rd32),
10664(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10665"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10666tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10667let Inst{13-13} = 0b0;
10668let Inst{31-21} = 0b01000011010;
10669let isPredicated = 1;
10670let hasNewValue = 1;
10671let opNewValue = 0;
10672let addrMode = BaseImmOffset;
10673let accessSize = HalfWordAccess;
10674let isPredicatedNew = 1;
10675let mayLoad = 1;
10676let BaseOpcode = "L2_loadrh_io";
10677let CextOpcode = "L2_loadrh";
10678let isExtendable = 1;
10679let opExtendable = 3;
10680let isExtentSigned = 0;
10681let opExtentBits = 7;
10682let opExtentAlign = 1;
10683}
10684def L2_ploadrhtnew_pi : HInst<
10685(outs IntRegs:$Rd32, IntRegs:$Rx32),
10686(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10687"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10688tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10689let Inst{13-11} = 0b110;
10690let Inst{31-21} = 0b10011011010;
10691let isPredicated = 1;
10692let hasNewValue = 1;
10693let opNewValue = 0;
10694let addrMode = PostInc;
10695let accessSize = HalfWordAccess;
10696let isPredicatedNew = 1;
10697let mayLoad = 1;
10698let BaseOpcode = "L2_loadrh_pi";
10699let Constraints = "$Rx32 = $Rx32in";
10700}
10701def L2_ploadrhtnew_zomap : HInst<
10702(outs IntRegs:$Rd32),
10703(ins PredRegs:$Pt4, IntRegs:$Rs32),
10704"if ($Pt4.new) $Rd32 = memh($Rs32)",
10705tc_075c8dd8, TypeMAPPING> {
10706let hasNewValue = 1;
10707let opNewValue = 0;
10708let isPseudo = 1;
10709let isCodeGenOnly = 1;
10710}
10711def L2_ploadrif_io : HInst<
10712(outs IntRegs:$Rd32),
10713(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10714"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
10715tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10716let Inst{13-13} = 0b0;
10717let Inst{31-21} = 0b01000101100;
10718let isPredicated = 1;
10719let isPredicatedFalse = 1;
10720let hasNewValue = 1;
10721let opNewValue = 0;
10722let addrMode = BaseImmOffset;
10723let accessSize = WordAccess;
10724let mayLoad = 1;
10725let BaseOpcode = "L2_loadri_io";
10726let CextOpcode = "L2_loadri";
10727let isExtendable = 1;
10728let opExtendable = 3;
10729let isExtentSigned = 0;
10730let opExtentBits = 8;
10731let opExtentAlign = 2;
10732}
10733def L2_ploadrif_pi : HInst<
10734(outs IntRegs:$Rd32, IntRegs:$Rx32),
10735(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10736"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
10737tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10738let Inst{13-11} = 0b101;
10739let Inst{31-21} = 0b10011011100;
10740let isPredicated = 1;
10741let isPredicatedFalse = 1;
10742let hasNewValue = 1;
10743let opNewValue = 0;
10744let addrMode = PostInc;
10745let accessSize = WordAccess;
10746let mayLoad = 1;
10747let BaseOpcode = "L2_loadri_pi";
10748let Constraints = "$Rx32 = $Rx32in";
10749}
10750def L2_ploadrif_zomap : HInst<
10751(outs IntRegs:$Rd32),
10752(ins PredRegs:$Pt4, IntRegs:$Rs32),
10753"if (!$Pt4) $Rd32 = memw($Rs32)",
10754tc_fedb7e19, TypeMAPPING> {
10755let hasNewValue = 1;
10756let opNewValue = 0;
10757let isPseudo = 1;
10758let isCodeGenOnly = 1;
10759}
10760def L2_ploadrifnew_io : HInst<
10761(outs IntRegs:$Rd32),
10762(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10763"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10764tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10765let Inst{13-13} = 0b0;
10766let Inst{31-21} = 0b01000111100;
10767let isPredicated = 1;
10768let isPredicatedFalse = 1;
10769let hasNewValue = 1;
10770let opNewValue = 0;
10771let addrMode = BaseImmOffset;
10772let accessSize = WordAccess;
10773let isPredicatedNew = 1;
10774let mayLoad = 1;
10775let BaseOpcode = "L2_loadri_io";
10776let CextOpcode = "L2_loadri";
10777let isExtendable = 1;
10778let opExtendable = 3;
10779let isExtentSigned = 0;
10780let opExtentBits = 8;
10781let opExtentAlign = 2;
10782}
10783def L2_ploadrifnew_pi : HInst<
10784(outs IntRegs:$Rd32, IntRegs:$Rx32),
10785(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10786"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10787tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10788let Inst{13-11} = 0b111;
10789let Inst{31-21} = 0b10011011100;
10790let isPredicated = 1;
10791let isPredicatedFalse = 1;
10792let hasNewValue = 1;
10793let opNewValue = 0;
10794let addrMode = PostInc;
10795let accessSize = WordAccess;
10796let isPredicatedNew = 1;
10797let mayLoad = 1;
10798let BaseOpcode = "L2_loadri_pi";
10799let Constraints = "$Rx32 = $Rx32in";
10800}
10801def L2_ploadrifnew_zomap : HInst<
10802(outs IntRegs:$Rd32),
10803(ins PredRegs:$Pt4, IntRegs:$Rs32),
10804"if (!$Pt4.new) $Rd32 = memw($Rs32)",
10805tc_075c8dd8, TypeMAPPING> {
10806let hasNewValue = 1;
10807let opNewValue = 0;
10808let isPseudo = 1;
10809let isCodeGenOnly = 1;
10810}
10811def L2_ploadrit_io : HInst<
10812(outs IntRegs:$Rd32),
10813(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10814"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
10815tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10816let Inst{13-13} = 0b0;
10817let Inst{31-21} = 0b01000001100;
10818let isPredicated = 1;
10819let hasNewValue = 1;
10820let opNewValue = 0;
10821let addrMode = BaseImmOffset;
10822let accessSize = WordAccess;
10823let mayLoad = 1;
10824let BaseOpcode = "L2_loadri_io";
10825let CextOpcode = "L2_loadri";
10826let isExtendable = 1;
10827let opExtendable = 3;
10828let isExtentSigned = 0;
10829let opExtentBits = 8;
10830let opExtentAlign = 2;
10831}
10832def L2_ploadrit_pi : HInst<
10833(outs IntRegs:$Rd32, IntRegs:$Rx32),
10834(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10835"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
10836tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10837let Inst{13-11} = 0b100;
10838let Inst{31-21} = 0b10011011100;
10839let isPredicated = 1;
10840let hasNewValue = 1;
10841let opNewValue = 0;
10842let addrMode = PostInc;
10843let accessSize = WordAccess;
10844let mayLoad = 1;
10845let BaseOpcode = "L2_loadri_pi";
10846let Constraints = "$Rx32 = $Rx32in";
10847}
10848def L2_ploadrit_zomap : HInst<
10849(outs IntRegs:$Rd32),
10850(ins PredRegs:$Pt4, IntRegs:$Rs32),
10851"if ($Pt4) $Rd32 = memw($Rs32)",
10852tc_fedb7e19, TypeMAPPING> {
10853let hasNewValue = 1;
10854let opNewValue = 0;
10855let isPseudo = 1;
10856let isCodeGenOnly = 1;
10857}
10858def L2_ploadritnew_io : HInst<
10859(outs IntRegs:$Rd32),
10860(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10861"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10862tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10863let Inst{13-13} = 0b0;
10864let Inst{31-21} = 0b01000011100;
10865let isPredicated = 1;
10866let hasNewValue = 1;
10867let opNewValue = 0;
10868let addrMode = BaseImmOffset;
10869let accessSize = WordAccess;
10870let isPredicatedNew = 1;
10871let mayLoad = 1;
10872let BaseOpcode = "L2_loadri_io";
10873let CextOpcode = "L2_loadri";
10874let isExtendable = 1;
10875let opExtendable = 3;
10876let isExtentSigned = 0;
10877let opExtentBits = 8;
10878let opExtentAlign = 2;
10879}
10880def L2_ploadritnew_pi : HInst<
10881(outs IntRegs:$Rd32, IntRegs:$Rx32),
10882(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10883"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10884tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10885let Inst{13-11} = 0b110;
10886let Inst{31-21} = 0b10011011100;
10887let isPredicated = 1;
10888let hasNewValue = 1;
10889let opNewValue = 0;
10890let addrMode = PostInc;
10891let accessSize = WordAccess;
10892let isPredicatedNew = 1;
10893let mayLoad = 1;
10894let BaseOpcode = "L2_loadri_pi";
10895let Constraints = "$Rx32 = $Rx32in";
10896}
10897def L2_ploadritnew_zomap : HInst<
10898(outs IntRegs:$Rd32),
10899(ins PredRegs:$Pt4, IntRegs:$Rs32),
10900"if ($Pt4.new) $Rd32 = memw($Rs32)",
10901tc_075c8dd8, TypeMAPPING> {
10902let hasNewValue = 1;
10903let opNewValue = 0;
10904let isPseudo = 1;
10905let isCodeGenOnly = 1;
10906}
10907def L2_ploadrubf_io : HInst<
10908(outs IntRegs:$Rd32),
10909(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10910"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
10911tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10912let Inst{13-13} = 0b0;
10913let Inst{31-21} = 0b01000101001;
10914let isPredicated = 1;
10915let isPredicatedFalse = 1;
10916let hasNewValue = 1;
10917let opNewValue = 0;
10918let addrMode = BaseImmOffset;
10919let accessSize = ByteAccess;
10920let mayLoad = 1;
10921let BaseOpcode = "L2_loadrub_io";
10922let CextOpcode = "L2_loadrub";
10923let isExtendable = 1;
10924let opExtendable = 3;
10925let isExtentSigned = 0;
10926let opExtentBits = 6;
10927let opExtentAlign = 0;
10928}
10929def L2_ploadrubf_pi : HInst<
10930(outs IntRegs:$Rd32, IntRegs:$Rx32),
10931(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10932"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
10933tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10934let Inst{13-11} = 0b101;
10935let Inst{31-21} = 0b10011011001;
10936let isPredicated = 1;
10937let isPredicatedFalse = 1;
10938let hasNewValue = 1;
10939let opNewValue = 0;
10940let addrMode = PostInc;
10941let accessSize = ByteAccess;
10942let mayLoad = 1;
10943let BaseOpcode = "L2_loadrub_pi";
10944let Constraints = "$Rx32 = $Rx32in";
10945}
10946def L2_ploadrubf_zomap : HInst<
10947(outs IntRegs:$Rd32),
10948(ins PredRegs:$Pt4, IntRegs:$Rs32),
10949"if (!$Pt4) $Rd32 = memub($Rs32)",
10950tc_fedb7e19, TypeMAPPING> {
10951let hasNewValue = 1;
10952let opNewValue = 0;
10953let isPseudo = 1;
10954let isCodeGenOnly = 1;
10955}
10956def L2_ploadrubfnew_io : HInst<
10957(outs IntRegs:$Rd32),
10958(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10959"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
10960tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10961let Inst{13-13} = 0b0;
10962let Inst{31-21} = 0b01000111001;
10963let isPredicated = 1;
10964let isPredicatedFalse = 1;
10965let hasNewValue = 1;
10966let opNewValue = 0;
10967let addrMode = BaseImmOffset;
10968let accessSize = ByteAccess;
10969let isPredicatedNew = 1;
10970let mayLoad = 1;
10971let BaseOpcode = "L2_loadrub_io";
10972let CextOpcode = "L2_loadrub";
10973let isExtendable = 1;
10974let opExtendable = 3;
10975let isExtentSigned = 0;
10976let opExtentBits = 6;
10977let opExtentAlign = 0;
10978}
10979def L2_ploadrubfnew_pi : HInst<
10980(outs IntRegs:$Rd32, IntRegs:$Rx32),
10981(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10982"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
10983tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10984let Inst{13-11} = 0b111;
10985let Inst{31-21} = 0b10011011001;
10986let isPredicated = 1;
10987let isPredicatedFalse = 1;
10988let hasNewValue = 1;
10989let opNewValue = 0;
10990let addrMode = PostInc;
10991let accessSize = ByteAccess;
10992let isPredicatedNew = 1;
10993let mayLoad = 1;
10994let BaseOpcode = "L2_loadrub_pi";
10995let Constraints = "$Rx32 = $Rx32in";
10996}
10997def L2_ploadrubfnew_zomap : HInst<
10998(outs IntRegs:$Rd32),
10999(ins PredRegs:$Pt4, IntRegs:$Rs32),
11000"if (!$Pt4.new) $Rd32 = memub($Rs32)",
11001tc_075c8dd8, TypeMAPPING> {
11002let hasNewValue = 1;
11003let opNewValue = 0;
11004let isPseudo = 1;
11005let isCodeGenOnly = 1;
11006}
11007def L2_ploadrubt_io : HInst<
11008(outs IntRegs:$Rd32),
11009(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11010"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
11011tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11012let Inst{13-13} = 0b0;
11013let Inst{31-21} = 0b01000001001;
11014let isPredicated = 1;
11015let hasNewValue = 1;
11016let opNewValue = 0;
11017let addrMode = BaseImmOffset;
11018let accessSize = ByteAccess;
11019let mayLoad = 1;
11020let BaseOpcode = "L2_loadrub_io";
11021let CextOpcode = "L2_loadrub";
11022let isExtendable = 1;
11023let opExtendable = 3;
11024let isExtentSigned = 0;
11025let opExtentBits = 6;
11026let opExtentAlign = 0;
11027}
11028def L2_ploadrubt_pi : HInst<
11029(outs IntRegs:$Rd32, IntRegs:$Rx32),
11030(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11031"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
11032tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
11033let Inst{13-11} = 0b100;
11034let Inst{31-21} = 0b10011011001;
11035let isPredicated = 1;
11036let hasNewValue = 1;
11037let opNewValue = 0;
11038let addrMode = PostInc;
11039let accessSize = ByteAccess;
11040let mayLoad = 1;
11041let BaseOpcode = "L2_loadrub_pi";
11042let Constraints = "$Rx32 = $Rx32in";
11043}
11044def L2_ploadrubt_zomap : HInst<
11045(outs IntRegs:$Rd32),
11046(ins PredRegs:$Pt4, IntRegs:$Rs32),
11047"if ($Pt4) $Rd32 = memub($Rs32)",
11048tc_fedb7e19, TypeMAPPING> {
11049let hasNewValue = 1;
11050let opNewValue = 0;
11051let isPseudo = 1;
11052let isCodeGenOnly = 1;
11053}
11054def L2_ploadrubtnew_io : HInst<
11055(outs IntRegs:$Rd32),
11056(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11057"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
11058tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11059let Inst{13-13} = 0b0;
11060let Inst{31-21} = 0b01000011001;
11061let isPredicated = 1;
11062let hasNewValue = 1;
11063let opNewValue = 0;
11064let addrMode = BaseImmOffset;
11065let accessSize = ByteAccess;
11066let isPredicatedNew = 1;
11067let mayLoad = 1;
11068let BaseOpcode = "L2_loadrub_io";
11069let CextOpcode = "L2_loadrub";
11070let isExtendable = 1;
11071let opExtendable = 3;
11072let isExtentSigned = 0;
11073let opExtentBits = 6;
11074let opExtentAlign = 0;
11075}
11076def L2_ploadrubtnew_pi : HInst<
11077(outs IntRegs:$Rd32, IntRegs:$Rx32),
11078(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11079"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
11080tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
11081let Inst{13-11} = 0b110;
11082let Inst{31-21} = 0b10011011001;
11083let isPredicated = 1;
11084let hasNewValue = 1;
11085let opNewValue = 0;
11086let addrMode = PostInc;
11087let accessSize = ByteAccess;
11088let isPredicatedNew = 1;
11089let mayLoad = 1;
11090let BaseOpcode = "L2_loadrub_pi";
11091let Constraints = "$Rx32 = $Rx32in";
11092}
11093def L2_ploadrubtnew_zomap : HInst<
11094(outs IntRegs:$Rd32),
11095(ins PredRegs:$Pt4, IntRegs:$Rs32),
11096"if ($Pt4.new) $Rd32 = memub($Rs32)",
11097tc_075c8dd8, TypeMAPPING> {
11098let hasNewValue = 1;
11099let opNewValue = 0;
11100let isPseudo = 1;
11101let isCodeGenOnly = 1;
11102}
11103def L2_ploadruhf_io : HInst<
11104(outs IntRegs:$Rd32),
11105(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11106"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11107tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11108let Inst{13-13} = 0b0;
11109let Inst{31-21} = 0b01000101011;
11110let isPredicated = 1;
11111let isPredicatedFalse = 1;
11112let hasNewValue = 1;
11113let opNewValue = 0;
11114let addrMode = BaseImmOffset;
11115let accessSize = HalfWordAccess;
11116let mayLoad = 1;
11117let BaseOpcode = "L2_loadruh_io";
11118let CextOpcode = "L2_loadruh";
11119let isExtendable = 1;
11120let opExtendable = 3;
11121let isExtentSigned = 0;
11122let opExtentBits = 7;
11123let opExtentAlign = 1;
11124}
11125def L2_ploadruhf_pi : HInst<
11126(outs IntRegs:$Rd32, IntRegs:$Rx32),
11127(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11128"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11129tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11130let Inst{13-11} = 0b101;
11131let Inst{31-21} = 0b10011011011;
11132let isPredicated = 1;
11133let isPredicatedFalse = 1;
11134let hasNewValue = 1;
11135let opNewValue = 0;
11136let addrMode = PostInc;
11137let accessSize = HalfWordAccess;
11138let mayLoad = 1;
11139let BaseOpcode = "L2_loadruh_pi";
11140let Constraints = "$Rx32 = $Rx32in";
11141}
11142def L2_ploadruhf_zomap : HInst<
11143(outs IntRegs:$Rd32),
11144(ins PredRegs:$Pt4, IntRegs:$Rs32),
11145"if (!$Pt4) $Rd32 = memuh($Rs32)",
11146tc_fedb7e19, TypeMAPPING> {
11147let hasNewValue = 1;
11148let opNewValue = 0;
11149let isPseudo = 1;
11150let isCodeGenOnly = 1;
11151}
11152def L2_ploadruhfnew_io : HInst<
11153(outs IntRegs:$Rd32),
11154(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11155"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11156tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11157let Inst{13-13} = 0b0;
11158let Inst{31-21} = 0b01000111011;
11159let isPredicated = 1;
11160let isPredicatedFalse = 1;
11161let hasNewValue = 1;
11162let opNewValue = 0;
11163let addrMode = BaseImmOffset;
11164let accessSize = HalfWordAccess;
11165let isPredicatedNew = 1;
11166let mayLoad = 1;
11167let BaseOpcode = "L2_loadruh_io";
11168let CextOpcode = "L2_loadruh";
11169let isExtendable = 1;
11170let opExtendable = 3;
11171let isExtentSigned = 0;
11172let opExtentBits = 7;
11173let opExtentAlign = 1;
11174}
11175def L2_ploadruhfnew_pi : HInst<
11176(outs IntRegs:$Rd32, IntRegs:$Rx32),
11177(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11178"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11179tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11180let Inst{13-11} = 0b111;
11181let Inst{31-21} = 0b10011011011;
11182let isPredicated = 1;
11183let isPredicatedFalse = 1;
11184let hasNewValue = 1;
11185let opNewValue = 0;
11186let addrMode = PostInc;
11187let accessSize = HalfWordAccess;
11188let isPredicatedNew = 1;
11189let mayLoad = 1;
11190let BaseOpcode = "L2_loadruh_pi";
11191let Constraints = "$Rx32 = $Rx32in";
11192}
11193def L2_ploadruhfnew_zomap : HInst<
11194(outs IntRegs:$Rd32),
11195(ins PredRegs:$Pt4, IntRegs:$Rs32),
11196"if (!$Pt4.new) $Rd32 = memuh($Rs32)",
11197tc_075c8dd8, TypeMAPPING> {
11198let hasNewValue = 1;
11199let opNewValue = 0;
11200let isPseudo = 1;
11201let isCodeGenOnly = 1;
11202}
11203def L2_ploadruht_io : HInst<
11204(outs IntRegs:$Rd32),
11205(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11206"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11207tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11208let Inst{13-13} = 0b0;
11209let Inst{31-21} = 0b01000001011;
11210let isPredicated = 1;
11211let hasNewValue = 1;
11212let opNewValue = 0;
11213let addrMode = BaseImmOffset;
11214let accessSize = HalfWordAccess;
11215let mayLoad = 1;
11216let BaseOpcode = "L2_loadruh_io";
11217let CextOpcode = "L2_loadruh";
11218let isExtendable = 1;
11219let opExtendable = 3;
11220let isExtentSigned = 0;
11221let opExtentBits = 7;
11222let opExtentAlign = 1;
11223}
11224def L2_ploadruht_pi : HInst<
11225(outs IntRegs:$Rd32, IntRegs:$Rx32),
11226(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11227"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11228tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11229let Inst{13-11} = 0b100;
11230let Inst{31-21} = 0b10011011011;
11231let isPredicated = 1;
11232let hasNewValue = 1;
11233let opNewValue = 0;
11234let addrMode = PostInc;
11235let accessSize = HalfWordAccess;
11236let mayLoad = 1;
11237let BaseOpcode = "L2_loadruh_pi";
11238let Constraints = "$Rx32 = $Rx32in";
11239}
11240def L2_ploadruht_zomap : HInst<
11241(outs IntRegs:$Rd32),
11242(ins PredRegs:$Pt4, IntRegs:$Rs32),
11243"if ($Pt4) $Rd32 = memuh($Rs32)",
11244tc_fedb7e19, TypeMAPPING> {
11245let hasNewValue = 1;
11246let opNewValue = 0;
11247let isPseudo = 1;
11248let isCodeGenOnly = 1;
11249}
11250def L2_ploadruhtnew_io : HInst<
11251(outs IntRegs:$Rd32),
11252(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11253"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11254tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11255let Inst{13-13} = 0b0;
11256let Inst{31-21} = 0b01000011011;
11257let isPredicated = 1;
11258let hasNewValue = 1;
11259let opNewValue = 0;
11260let addrMode = BaseImmOffset;
11261let accessSize = HalfWordAccess;
11262let isPredicatedNew = 1;
11263let mayLoad = 1;
11264let BaseOpcode = "L2_loadruh_io";
11265let CextOpcode = "L2_loadruh";
11266let isExtendable = 1;
11267let opExtendable = 3;
11268let isExtentSigned = 0;
11269let opExtentBits = 7;
11270let opExtentAlign = 1;
11271}
11272def L2_ploadruhtnew_pi : HInst<
11273(outs IntRegs:$Rd32, IntRegs:$Rx32),
11274(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11275"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11276tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11277let Inst{13-11} = 0b110;
11278let Inst{31-21} = 0b10011011011;
11279let isPredicated = 1;
11280let hasNewValue = 1;
11281let opNewValue = 0;
11282let addrMode = PostInc;
11283let accessSize = HalfWordAccess;
11284let isPredicatedNew = 1;
11285let mayLoad = 1;
11286let BaseOpcode = "L2_loadruh_pi";
11287let Constraints = "$Rx32 = $Rx32in";
11288}
11289def L2_ploadruhtnew_zomap : HInst<
11290(outs IntRegs:$Rd32),
11291(ins PredRegs:$Pt4, IntRegs:$Rs32),
11292"if ($Pt4.new) $Rd32 = memuh($Rs32)",
11293tc_075c8dd8, TypeMAPPING> {
11294let hasNewValue = 1;
11295let opNewValue = 0;
11296let isPseudo = 1;
11297let isCodeGenOnly = 1;
11298}
11299def L4_add_memopb_io : HInst<
11300(outs),
11301(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11302"memb($Rs32+#$Ii) += $Rt32",
11303tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11304let Inst{6-5} = 0b00;
11305let Inst{13-13} = 0b0;
11306let Inst{31-21} = 0b00111110000;
11307let addrMode = BaseImmOffset;
11308let accessSize = ByteAccess;
11309let mayLoad = 1;
11310let isRestrictNoSlot1Store = 1;
11311let mayStore = 1;
11312let isExtendable = 1;
11313let opExtendable = 1;
11314let isExtentSigned = 0;
11315let opExtentBits = 6;
11316let opExtentAlign = 0;
11317}
11318def L4_add_memopb_zomap : HInst<
11319(outs),
11320(ins IntRegs:$Rs32, IntRegs:$Rt32),
11321"memb($Rs32) += $Rt32",
11322tc_9bcfb2ee, TypeMAPPING> {
11323let isPseudo = 1;
11324let isCodeGenOnly = 1;
11325}
11326def L4_add_memoph_io : HInst<
11327(outs),
11328(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11329"memh($Rs32+#$Ii) += $Rt32",
11330tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11331let Inst{6-5} = 0b00;
11332let Inst{13-13} = 0b0;
11333let Inst{31-21} = 0b00111110001;
11334let addrMode = BaseImmOffset;
11335let accessSize = HalfWordAccess;
11336let mayLoad = 1;
11337let isRestrictNoSlot1Store = 1;
11338let mayStore = 1;
11339let isExtendable = 1;
11340let opExtendable = 1;
11341let isExtentSigned = 0;
11342let opExtentBits = 7;
11343let opExtentAlign = 1;
11344}
11345def L4_add_memoph_zomap : HInst<
11346(outs),
11347(ins IntRegs:$Rs32, IntRegs:$Rt32),
11348"memh($Rs32) += $Rt32",
11349tc_9bcfb2ee, TypeMAPPING> {
11350let isPseudo = 1;
11351let isCodeGenOnly = 1;
11352}
11353def L4_add_memopw_io : HInst<
11354(outs),
11355(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11356"memw($Rs32+#$Ii) += $Rt32",
11357tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11358let Inst{6-5} = 0b00;
11359let Inst{13-13} = 0b0;
11360let Inst{31-21} = 0b00111110010;
11361let addrMode = BaseImmOffset;
11362let accessSize = WordAccess;
11363let mayLoad = 1;
11364let isRestrictNoSlot1Store = 1;
11365let mayStore = 1;
11366let isExtendable = 1;
11367let opExtendable = 1;
11368let isExtentSigned = 0;
11369let opExtentBits = 8;
11370let opExtentAlign = 2;
11371}
11372def L4_add_memopw_zomap : HInst<
11373(outs),
11374(ins IntRegs:$Rs32, IntRegs:$Rt32),
11375"memw($Rs32) += $Rt32",
11376tc_9bcfb2ee, TypeMAPPING> {
11377let isPseudo = 1;
11378let isCodeGenOnly = 1;
11379}
11380def L4_and_memopb_io : HInst<
11381(outs),
11382(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11383"memb($Rs32+#$Ii) &= $Rt32",
11384tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11385let Inst{6-5} = 0b10;
11386let Inst{13-13} = 0b0;
11387let Inst{31-21} = 0b00111110000;
11388let addrMode = BaseImmOffset;
11389let accessSize = ByteAccess;
11390let mayLoad = 1;
11391let isRestrictNoSlot1Store = 1;
11392let mayStore = 1;
11393let isExtendable = 1;
11394let opExtendable = 1;
11395let isExtentSigned = 0;
11396let opExtentBits = 6;
11397let opExtentAlign = 0;
11398}
11399def L4_and_memopb_zomap : HInst<
11400(outs),
11401(ins IntRegs:$Rs32, IntRegs:$Rt32),
11402"memb($Rs32) &= $Rt32",
11403tc_9bcfb2ee, TypeMAPPING> {
11404let isPseudo = 1;
11405let isCodeGenOnly = 1;
11406}
11407def L4_and_memoph_io : HInst<
11408(outs),
11409(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11410"memh($Rs32+#$Ii) &= $Rt32",
11411tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11412let Inst{6-5} = 0b10;
11413let Inst{13-13} = 0b0;
11414let Inst{31-21} = 0b00111110001;
11415let addrMode = BaseImmOffset;
11416let accessSize = HalfWordAccess;
11417let mayLoad = 1;
11418let isRestrictNoSlot1Store = 1;
11419let mayStore = 1;
11420let isExtendable = 1;
11421let opExtendable = 1;
11422let isExtentSigned = 0;
11423let opExtentBits = 7;
11424let opExtentAlign = 1;
11425}
11426def L4_and_memoph_zomap : HInst<
11427(outs),
11428(ins IntRegs:$Rs32, IntRegs:$Rt32),
11429"memh($Rs32) &= $Rt32",
11430tc_9bcfb2ee, TypeMAPPING> {
11431let isPseudo = 1;
11432let isCodeGenOnly = 1;
11433}
11434def L4_and_memopw_io : HInst<
11435(outs),
11436(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11437"memw($Rs32+#$Ii) &= $Rt32",
11438tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11439let Inst{6-5} = 0b10;
11440let Inst{13-13} = 0b0;
11441let Inst{31-21} = 0b00111110010;
11442let addrMode = BaseImmOffset;
11443let accessSize = WordAccess;
11444let mayLoad = 1;
11445let isRestrictNoSlot1Store = 1;
11446let mayStore = 1;
11447let isExtendable = 1;
11448let opExtendable = 1;
11449let isExtentSigned = 0;
11450let opExtentBits = 8;
11451let opExtentAlign = 2;
11452}
11453def L4_and_memopw_zomap : HInst<
11454(outs),
11455(ins IntRegs:$Rs32, IntRegs:$Rt32),
11456"memw($Rs32) &= $Rt32",
11457tc_9bcfb2ee, TypeMAPPING> {
11458let isPseudo = 1;
11459let isCodeGenOnly = 1;
11460}
11461def L4_iadd_memopb_io : HInst<
11462(outs),
11463(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11464"memb($Rs32+#$Ii) += #$II",
11465tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11466let Inst{6-5} = 0b00;
11467let Inst{13-13} = 0b0;
11468let Inst{31-21} = 0b00111111000;
11469let addrMode = BaseImmOffset;
11470let accessSize = ByteAccess;
11471let mayLoad = 1;
11472let isRestrictNoSlot1Store = 1;
11473let mayStore = 1;
11474let isExtendable = 1;
11475let opExtendable = 1;
11476let isExtentSigned = 0;
11477let opExtentBits = 6;
11478let opExtentAlign = 0;
11479}
11480def L4_iadd_memopb_zomap : HInst<
11481(outs),
11482(ins IntRegs:$Rs32, u5_0Imm:$II),
11483"memb($Rs32) += #$II",
11484tc_158aa3f7, TypeMAPPING> {
11485let isPseudo = 1;
11486let isCodeGenOnly = 1;
11487}
11488def L4_iadd_memoph_io : HInst<
11489(outs),
11490(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11491"memh($Rs32+#$Ii) += #$II",
11492tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11493let Inst{6-5} = 0b00;
11494let Inst{13-13} = 0b0;
11495let Inst{31-21} = 0b00111111001;
11496let addrMode = BaseImmOffset;
11497let accessSize = HalfWordAccess;
11498let mayLoad = 1;
11499let isRestrictNoSlot1Store = 1;
11500let mayStore = 1;
11501let isExtendable = 1;
11502let opExtendable = 1;
11503let isExtentSigned = 0;
11504let opExtentBits = 7;
11505let opExtentAlign = 1;
11506}
11507def L4_iadd_memoph_zomap : HInst<
11508(outs),
11509(ins IntRegs:$Rs32, u5_0Imm:$II),
11510"memh($Rs32) += #$II",
11511tc_158aa3f7, TypeMAPPING> {
11512let isPseudo = 1;
11513let isCodeGenOnly = 1;
11514}
11515def L4_iadd_memopw_io : HInst<
11516(outs),
11517(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11518"memw($Rs32+#$Ii) += #$II",
11519tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11520let Inst{6-5} = 0b00;
11521let Inst{13-13} = 0b0;
11522let Inst{31-21} = 0b00111111010;
11523let addrMode = BaseImmOffset;
11524let accessSize = WordAccess;
11525let mayLoad = 1;
11526let isRestrictNoSlot1Store = 1;
11527let mayStore = 1;
11528let isExtendable = 1;
11529let opExtendable = 1;
11530let isExtentSigned = 0;
11531let opExtentBits = 8;
11532let opExtentAlign = 2;
11533}
11534def L4_iadd_memopw_zomap : HInst<
11535(outs),
11536(ins IntRegs:$Rs32, u5_0Imm:$II),
11537"memw($Rs32) += #$II",
11538tc_158aa3f7, TypeMAPPING> {
11539let isPseudo = 1;
11540let isCodeGenOnly = 1;
11541}
11542def L4_iand_memopb_io : HInst<
11543(outs),
11544(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11545"memb($Rs32+#$Ii) = clrbit(#$II)",
11546tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11547let Inst{6-5} = 0b10;
11548let Inst{13-13} = 0b0;
11549let Inst{31-21} = 0b00111111000;
11550let addrMode = BaseImmOffset;
11551let accessSize = ByteAccess;
11552let mayLoad = 1;
11553let isRestrictNoSlot1Store = 1;
11554let mayStore = 1;
11555let isExtendable = 1;
11556let opExtendable = 1;
11557let isExtentSigned = 0;
11558let opExtentBits = 6;
11559let opExtentAlign = 0;
11560}
11561def L4_iand_memopb_zomap : HInst<
11562(outs),
11563(ins IntRegs:$Rs32, u5_0Imm:$II),
11564"memb($Rs32) = clrbit(#$II)",
11565tc_158aa3f7, TypeMAPPING> {
11566let isPseudo = 1;
11567let isCodeGenOnly = 1;
11568}
11569def L4_iand_memoph_io : HInst<
11570(outs),
11571(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11572"memh($Rs32+#$Ii) = clrbit(#$II)",
11573tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11574let Inst{6-5} = 0b10;
11575let Inst{13-13} = 0b0;
11576let Inst{31-21} = 0b00111111001;
11577let addrMode = BaseImmOffset;
11578let accessSize = HalfWordAccess;
11579let mayLoad = 1;
11580let isRestrictNoSlot1Store = 1;
11581let mayStore = 1;
11582let isExtendable = 1;
11583let opExtendable = 1;
11584let isExtentSigned = 0;
11585let opExtentBits = 7;
11586let opExtentAlign = 1;
11587}
11588def L4_iand_memoph_zomap : HInst<
11589(outs),
11590(ins IntRegs:$Rs32, u5_0Imm:$II),
11591"memh($Rs32) = clrbit(#$II)",
11592tc_158aa3f7, TypeMAPPING> {
11593let isPseudo = 1;
11594let isCodeGenOnly = 1;
11595}
11596def L4_iand_memopw_io : HInst<
11597(outs),
11598(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11599"memw($Rs32+#$Ii) = clrbit(#$II)",
11600tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11601let Inst{6-5} = 0b10;
11602let Inst{13-13} = 0b0;
11603let Inst{31-21} = 0b00111111010;
11604let addrMode = BaseImmOffset;
11605let accessSize = WordAccess;
11606let mayLoad = 1;
11607let isRestrictNoSlot1Store = 1;
11608let mayStore = 1;
11609let isExtendable = 1;
11610let opExtendable = 1;
11611let isExtentSigned = 0;
11612let opExtentBits = 8;
11613let opExtentAlign = 2;
11614}
11615def L4_iand_memopw_zomap : HInst<
11616(outs),
11617(ins IntRegs:$Rs32, u5_0Imm:$II),
11618"memw($Rs32) = clrbit(#$II)",
11619tc_158aa3f7, TypeMAPPING> {
11620let isPseudo = 1;
11621let isCodeGenOnly = 1;
11622}
11623def L4_ior_memopb_io : HInst<
11624(outs),
11625(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11626"memb($Rs32+#$Ii) = setbit(#$II)",
11627tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11628let Inst{6-5} = 0b11;
11629let Inst{13-13} = 0b0;
11630let Inst{31-21} = 0b00111111000;
11631let addrMode = BaseImmOffset;
11632let accessSize = ByteAccess;
11633let mayLoad = 1;
11634let isRestrictNoSlot1Store = 1;
11635let mayStore = 1;
11636let isExtendable = 1;
11637let opExtendable = 1;
11638let isExtentSigned = 0;
11639let opExtentBits = 6;
11640let opExtentAlign = 0;
11641}
11642def L4_ior_memopb_zomap : HInst<
11643(outs),
11644(ins IntRegs:$Rs32, u5_0Imm:$II),
11645"memb($Rs32) = setbit(#$II)",
11646tc_158aa3f7, TypeMAPPING> {
11647let isPseudo = 1;
11648let isCodeGenOnly = 1;
11649}
11650def L4_ior_memoph_io : HInst<
11651(outs),
11652(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11653"memh($Rs32+#$Ii) = setbit(#$II)",
11654tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11655let Inst{6-5} = 0b11;
11656let Inst{13-13} = 0b0;
11657let Inst{31-21} = 0b00111111001;
11658let addrMode = BaseImmOffset;
11659let accessSize = HalfWordAccess;
11660let mayLoad = 1;
11661let isRestrictNoSlot1Store = 1;
11662let mayStore = 1;
11663let isExtendable = 1;
11664let opExtendable = 1;
11665let isExtentSigned = 0;
11666let opExtentBits = 7;
11667let opExtentAlign = 1;
11668}
11669def L4_ior_memoph_zomap : HInst<
11670(outs),
11671(ins IntRegs:$Rs32, u5_0Imm:$II),
11672"memh($Rs32) = setbit(#$II)",
11673tc_158aa3f7, TypeMAPPING> {
11674let isPseudo = 1;
11675let isCodeGenOnly = 1;
11676}
11677def L4_ior_memopw_io : HInst<
11678(outs),
11679(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11680"memw($Rs32+#$Ii) = setbit(#$II)",
11681tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11682let Inst{6-5} = 0b11;
11683let Inst{13-13} = 0b0;
11684let Inst{31-21} = 0b00111111010;
11685let addrMode = BaseImmOffset;
11686let accessSize = WordAccess;
11687let mayLoad = 1;
11688let isRestrictNoSlot1Store = 1;
11689let mayStore = 1;
11690let isExtendable = 1;
11691let opExtendable = 1;
11692let isExtentSigned = 0;
11693let opExtentBits = 8;
11694let opExtentAlign = 2;
11695}
11696def L4_ior_memopw_zomap : HInst<
11697(outs),
11698(ins IntRegs:$Rs32, u5_0Imm:$II),
11699"memw($Rs32) = setbit(#$II)",
11700tc_158aa3f7, TypeMAPPING> {
11701let isPseudo = 1;
11702let isCodeGenOnly = 1;
11703}
11704def L4_isub_memopb_io : HInst<
11705(outs),
11706(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11707"memb($Rs32+#$Ii) -= #$II",
11708tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11709let Inst{6-5} = 0b01;
11710let Inst{13-13} = 0b0;
11711let Inst{31-21} = 0b00111111000;
11712let addrMode = BaseImmOffset;
11713let accessSize = ByteAccess;
11714let mayLoad = 1;
11715let isRestrictNoSlot1Store = 1;
11716let mayStore = 1;
11717let isExtendable = 1;
11718let opExtendable = 1;
11719let isExtentSigned = 0;
11720let opExtentBits = 6;
11721let opExtentAlign = 0;
11722}
11723def L4_isub_memopb_zomap : HInst<
11724(outs),
11725(ins IntRegs:$Rs32, u5_0Imm:$II),
11726"memb($Rs32) -= #$II",
11727tc_158aa3f7, TypeMAPPING> {
11728let isPseudo = 1;
11729let isCodeGenOnly = 1;
11730}
11731def L4_isub_memoph_io : HInst<
11732(outs),
11733(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11734"memh($Rs32+#$Ii) -= #$II",
11735tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11736let Inst{6-5} = 0b01;
11737let Inst{13-13} = 0b0;
11738let Inst{31-21} = 0b00111111001;
11739let addrMode = BaseImmOffset;
11740let accessSize = HalfWordAccess;
11741let mayLoad = 1;
11742let isRestrictNoSlot1Store = 1;
11743let mayStore = 1;
11744let isExtendable = 1;
11745let opExtendable = 1;
11746let isExtentSigned = 0;
11747let opExtentBits = 7;
11748let opExtentAlign = 1;
11749}
11750def L4_isub_memoph_zomap : HInst<
11751(outs),
11752(ins IntRegs:$Rs32, u5_0Imm:$II),
11753"memh($Rs32) -= #$II",
11754tc_158aa3f7, TypeMAPPING> {
11755let isPseudo = 1;
11756let isCodeGenOnly = 1;
11757}
11758def L4_isub_memopw_io : HInst<
11759(outs),
11760(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11761"memw($Rs32+#$Ii) -= #$II",
11762tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11763let Inst{6-5} = 0b01;
11764let Inst{13-13} = 0b0;
11765let Inst{31-21} = 0b00111111010;
11766let addrMode = BaseImmOffset;
11767let accessSize = WordAccess;
11768let mayLoad = 1;
11769let isRestrictNoSlot1Store = 1;
11770let mayStore = 1;
11771let isExtendable = 1;
11772let opExtendable = 1;
11773let isExtentSigned = 0;
11774let opExtentBits = 8;
11775let opExtentAlign = 2;
11776}
11777def L4_isub_memopw_zomap : HInst<
11778(outs),
11779(ins IntRegs:$Rs32, u5_0Imm:$II),
11780"memw($Rs32) -= #$II",
11781tc_158aa3f7, TypeMAPPING> {
11782let isPseudo = 1;
11783let isCodeGenOnly = 1;
11784}
11785def L4_loadalignb_ap : HInst<
11786(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11787(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11788"$Ryy32 = memb_fifo($Re32=#$II)",
11789tc_ac65613f, TypeLD>, Enc_f394d3 {
11790let Inst{7-7} = 0b0;
11791let Inst{13-12} = 0b01;
11792let Inst{31-21} = 0b10011010100;
11793let addrMode = AbsoluteSet;
11794let accessSize = ByteAccess;
11795let mayLoad = 1;
11796let isExtended = 1;
11797let DecoderNamespace = "MustExtend";
11798let isExtendable = 1;
11799let opExtendable = 3;
11800let isExtentSigned = 0;
11801let opExtentBits = 6;
11802let opExtentAlign = 0;
11803let Constraints = "$Ryy32 = $Ryy32in";
11804}
11805def L4_loadalignb_ur : HInst<
11806(outs DoubleRegs:$Ryy32),
11807(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11808"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
11809tc_a32e03e7, TypeLD>, Enc_04c959 {
11810let Inst{12-12} = 0b1;
11811let Inst{31-21} = 0b10011100100;
11812let addrMode = BaseLongOffset;
11813let accessSize = ByteAccess;
11814let mayLoad = 1;
11815let isExtended = 1;
11816let InputType = "imm";
11817let DecoderNamespace = "MustExtend";
11818let isExtendable = 1;
11819let opExtendable = 4;
11820let isExtentSigned = 0;
11821let opExtentBits = 6;
11822let opExtentAlign = 0;
11823let Constraints = "$Ryy32 = $Ryy32in";
11824}
11825def L4_loadalignh_ap : HInst<
11826(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11827(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11828"$Ryy32 = memh_fifo($Re32=#$II)",
11829tc_ac65613f, TypeLD>, Enc_f394d3 {
11830let Inst{7-7} = 0b0;
11831let Inst{13-12} = 0b01;
11832let Inst{31-21} = 0b10011010010;
11833let addrMode = AbsoluteSet;
11834let accessSize = HalfWordAccess;
11835let mayLoad = 1;
11836let isExtended = 1;
11837let DecoderNamespace = "MustExtend";
11838let isExtendable = 1;
11839let opExtendable = 3;
11840let isExtentSigned = 0;
11841let opExtentBits = 6;
11842let opExtentAlign = 0;
11843let Constraints = "$Ryy32 = $Ryy32in";
11844}
11845def L4_loadalignh_ur : HInst<
11846(outs DoubleRegs:$Ryy32),
11847(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11848"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
11849tc_a32e03e7, TypeLD>, Enc_04c959 {
11850let Inst{12-12} = 0b1;
11851let Inst{31-21} = 0b10011100010;
11852let addrMode = BaseLongOffset;
11853let accessSize = HalfWordAccess;
11854let mayLoad = 1;
11855let isExtended = 1;
11856let InputType = "imm";
11857let DecoderNamespace = "MustExtend";
11858let isExtendable = 1;
11859let opExtendable = 4;
11860let isExtentSigned = 0;
11861let opExtentBits = 6;
11862let opExtentAlign = 0;
11863let Constraints = "$Ryy32 = $Ryy32in";
11864}
11865def L4_loadbsw2_ap : HInst<
11866(outs IntRegs:$Rd32, IntRegs:$Re32),
11867(ins u32_0Imm:$II),
11868"$Rd32 = membh($Re32=#$II)",
11869tc_822c3c68, TypeLD>, Enc_323f2d {
11870let Inst{7-7} = 0b0;
11871let Inst{13-12} = 0b01;
11872let Inst{31-21} = 0b10011010001;
11873let hasNewValue = 1;
11874let opNewValue = 0;
11875let addrMode = AbsoluteSet;
11876let accessSize = HalfWordAccess;
11877let mayLoad = 1;
11878let isExtended = 1;
11879let DecoderNamespace = "MustExtend";
11880let isExtendable = 1;
11881let opExtendable = 2;
11882let isExtentSigned = 0;
11883let opExtentBits = 6;
11884let opExtentAlign = 0;
11885}
11886def L4_loadbsw2_ur : HInst<
11887(outs IntRegs:$Rd32),
11888(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11889"$Rd32 = membh($Rt32<<#$Ii+#$II)",
11890tc_abfd9a6d, TypeLD>, Enc_4f677b {
11891let Inst{12-12} = 0b1;
11892let Inst{31-21} = 0b10011100001;
11893let hasNewValue = 1;
11894let opNewValue = 0;
11895let addrMode = BaseLongOffset;
11896let accessSize = HalfWordAccess;
11897let mayLoad = 1;
11898let isExtended = 1;
11899let InputType = "imm";
11900let DecoderNamespace = "MustExtend";
11901let isExtendable = 1;
11902let opExtendable = 3;
11903let isExtentSigned = 0;
11904let opExtentBits = 6;
11905let opExtentAlign = 0;
11906}
11907def L4_loadbsw4_ap : HInst<
11908(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11909(ins u32_0Imm:$II),
11910"$Rdd32 = membh($Re32=#$II)",
11911tc_822c3c68, TypeLD>, Enc_7fa7f6 {
11912let Inst{7-7} = 0b0;
11913let Inst{13-12} = 0b01;
11914let Inst{31-21} = 0b10011010111;
11915let addrMode = AbsoluteSet;
11916let accessSize = WordAccess;
11917let mayLoad = 1;
11918let isExtended = 1;
11919let DecoderNamespace = "MustExtend";
11920let isExtendable = 1;
11921let opExtendable = 2;
11922let isExtentSigned = 0;
11923let opExtentBits = 6;
11924let opExtentAlign = 0;
11925}
11926def L4_loadbsw4_ur : HInst<
11927(outs DoubleRegs:$Rdd32),
11928(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11929"$Rdd32 = membh($Rt32<<#$Ii+#$II)",
11930tc_abfd9a6d, TypeLD>, Enc_6185fe {
11931let Inst{12-12} = 0b1;
11932let Inst{31-21} = 0b10011100111;
11933let addrMode = BaseLongOffset;
11934let accessSize = WordAccess;
11935let mayLoad = 1;
11936let isExtended = 1;
11937let InputType = "imm";
11938let DecoderNamespace = "MustExtend";
11939let isExtendable = 1;
11940let opExtendable = 3;
11941let isExtentSigned = 0;
11942let opExtentBits = 6;
11943let opExtentAlign = 0;
11944}
11945def L4_loadbzw2_ap : HInst<
11946(outs IntRegs:$Rd32, IntRegs:$Re32),
11947(ins u32_0Imm:$II),
11948"$Rd32 = memubh($Re32=#$II)",
11949tc_822c3c68, TypeLD>, Enc_323f2d {
11950let Inst{7-7} = 0b0;
11951let Inst{13-12} = 0b01;
11952let Inst{31-21} = 0b10011010011;
11953let hasNewValue = 1;
11954let opNewValue = 0;
11955let addrMode = AbsoluteSet;
11956let accessSize = HalfWordAccess;
11957let mayLoad = 1;
11958let isExtended = 1;
11959let DecoderNamespace = "MustExtend";
11960let isExtendable = 1;
11961let opExtendable = 2;
11962let isExtentSigned = 0;
11963let opExtentBits = 6;
11964let opExtentAlign = 0;
11965}
11966def L4_loadbzw2_ur : HInst<
11967(outs IntRegs:$Rd32),
11968(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11969"$Rd32 = memubh($Rt32<<#$Ii+#$II)",
11970tc_abfd9a6d, TypeLD>, Enc_4f677b {
11971let Inst{12-12} = 0b1;
11972let Inst{31-21} = 0b10011100011;
11973let hasNewValue = 1;
11974let opNewValue = 0;
11975let addrMode = BaseLongOffset;
11976let accessSize = HalfWordAccess;
11977let mayLoad = 1;
11978let isExtended = 1;
11979let InputType = "imm";
11980let DecoderNamespace = "MustExtend";
11981let isExtendable = 1;
11982let opExtendable = 3;
11983let isExtentSigned = 0;
11984let opExtentBits = 6;
11985let opExtentAlign = 0;
11986}
11987def L4_loadbzw4_ap : HInst<
11988(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11989(ins u32_0Imm:$II),
11990"$Rdd32 = memubh($Re32=#$II)",
11991tc_822c3c68, TypeLD>, Enc_7fa7f6 {
11992let Inst{7-7} = 0b0;
11993let Inst{13-12} = 0b01;
11994let Inst{31-21} = 0b10011010101;
11995let addrMode = AbsoluteSet;
11996let accessSize = WordAccess;
11997let mayLoad = 1;
11998let isExtended = 1;
11999let DecoderNamespace = "MustExtend";
12000let isExtendable = 1;
12001let opExtendable = 2;
12002let isExtentSigned = 0;
12003let opExtentBits = 6;
12004let opExtentAlign = 0;
12005}
12006def L4_loadbzw4_ur : HInst<
12007(outs DoubleRegs:$Rdd32),
12008(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12009"$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
12010tc_abfd9a6d, TypeLD>, Enc_6185fe {
12011let Inst{12-12} = 0b1;
12012let Inst{31-21} = 0b10011100101;
12013let addrMode = BaseLongOffset;
12014let accessSize = WordAccess;
12015let mayLoad = 1;
12016let isExtended = 1;
12017let InputType = "imm";
12018let DecoderNamespace = "MustExtend";
12019let isExtendable = 1;
12020let opExtendable = 3;
12021let isExtentSigned = 0;
12022let opExtentBits = 6;
12023let opExtentAlign = 0;
12024}
12025def L4_loadd_locked : HInst<
12026(outs DoubleRegs:$Rdd32),
12027(ins IntRegs:$Rs32),
12028"$Rdd32 = memd_locked($Rs32)",
12029tc_64b00d8a, TypeLD>, Enc_3a3d62 {
12030let Inst{13-5} = 0b010000000;
12031let Inst{31-21} = 0b10010010000;
12032let accessSize = DoubleWordAccess;
12033let mayLoad = 1;
12034let isSoloAX = 1;
12035}
12036def L4_loadrb_ap : HInst<
12037(outs IntRegs:$Rd32, IntRegs:$Re32),
12038(ins u32_0Imm:$II),
12039"$Rd32 = memb($Re32=#$II)",
12040tc_822c3c68, TypeLD>, Enc_323f2d {
12041let Inst{7-7} = 0b0;
12042let Inst{13-12} = 0b01;
12043let Inst{31-21} = 0b10011011000;
12044let hasNewValue = 1;
12045let opNewValue = 0;
12046let addrMode = AbsoluteSet;
12047let accessSize = ByteAccess;
12048let mayLoad = 1;
12049let isExtended = 1;
12050let DecoderNamespace = "MustExtend";
12051let isExtendable = 1;
12052let opExtendable = 2;
12053let isExtentSigned = 0;
12054let opExtentBits = 6;
12055let opExtentAlign = 0;
12056}
12057def L4_loadrb_rr : HInst<
12058(outs IntRegs:$Rd32),
12059(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12060"$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12061tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12062let Inst{6-5} = 0b00;
12063let Inst{31-21} = 0b00111010000;
12064let hasNewValue = 1;
12065let opNewValue = 0;
12066let addrMode = BaseRegOffset;
12067let accessSize = ByteAccess;
12068let mayLoad = 1;
12069let BaseOpcode = "L4_loadrb_rr";
12070let CextOpcode = "L2_loadrb";
12071let InputType = "reg";
12072let isPredicable = 1;
12073}
12074def L4_loadrb_ur : HInst<
12075(outs IntRegs:$Rd32),
12076(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12077"$Rd32 = memb($Rt32<<#$Ii+#$II)",
12078tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12079let Inst{12-12} = 0b1;
12080let Inst{31-21} = 0b10011101000;
12081let hasNewValue = 1;
12082let opNewValue = 0;
12083let addrMode = BaseLongOffset;
12084let accessSize = ByteAccess;
12085let mayLoad = 1;
12086let isExtended = 1;
12087let CextOpcode = "L2_loadrb";
12088let InputType = "imm";
12089let DecoderNamespace = "MustExtend";
12090let isExtendable = 1;
12091let opExtendable = 3;
12092let isExtentSigned = 0;
12093let opExtentBits = 6;
12094let opExtentAlign = 0;
12095}
12096def L4_loadrd_ap : HInst<
12097(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12098(ins u32_0Imm:$II),
12099"$Rdd32 = memd($Re32=#$II)",
12100tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12101let Inst{7-7} = 0b0;
12102let Inst{13-12} = 0b01;
12103let Inst{31-21} = 0b10011011110;
12104let addrMode = AbsoluteSet;
12105let accessSize = DoubleWordAccess;
12106let mayLoad = 1;
12107let isExtended = 1;
12108let DecoderNamespace = "MustExtend";
12109let isExtendable = 1;
12110let opExtendable = 2;
12111let isExtentSigned = 0;
12112let opExtentBits = 6;
12113let opExtentAlign = 0;
12114}
12115def L4_loadrd_rr : HInst<
12116(outs DoubleRegs:$Rdd32),
12117(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12118"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12119tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
12120let Inst{6-5} = 0b00;
12121let Inst{31-21} = 0b00111010110;
12122let addrMode = BaseRegOffset;
12123let accessSize = DoubleWordAccess;
12124let mayLoad = 1;
12125let BaseOpcode = "L4_loadrd_rr";
12126let CextOpcode = "L2_loadrd";
12127let InputType = "reg";
12128let isPredicable = 1;
12129}
12130def L4_loadrd_ur : HInst<
12131(outs DoubleRegs:$Rdd32),
12132(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12133"$Rdd32 = memd($Rt32<<#$Ii+#$II)",
12134tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
12135let Inst{12-12} = 0b1;
12136let Inst{31-21} = 0b10011101110;
12137let addrMode = BaseLongOffset;
12138let accessSize = DoubleWordAccess;
12139let mayLoad = 1;
12140let isExtended = 1;
12141let CextOpcode = "L2_loadrd";
12142let InputType = "imm";
12143let DecoderNamespace = "MustExtend";
12144let isExtendable = 1;
12145let opExtendable = 3;
12146let isExtentSigned = 0;
12147let opExtentBits = 6;
12148let opExtentAlign = 0;
12149}
12150def L4_loadrh_ap : HInst<
12151(outs IntRegs:$Rd32, IntRegs:$Re32),
12152(ins u32_0Imm:$II),
12153"$Rd32 = memh($Re32=#$II)",
12154tc_822c3c68, TypeLD>, Enc_323f2d {
12155let Inst{7-7} = 0b0;
12156let Inst{13-12} = 0b01;
12157let Inst{31-21} = 0b10011011010;
12158let hasNewValue = 1;
12159let opNewValue = 0;
12160let addrMode = AbsoluteSet;
12161let accessSize = HalfWordAccess;
12162let mayLoad = 1;
12163let isExtended = 1;
12164let DecoderNamespace = "MustExtend";
12165let isExtendable = 1;
12166let opExtendable = 2;
12167let isExtentSigned = 0;
12168let opExtentBits = 6;
12169let opExtentAlign = 0;
12170}
12171def L4_loadrh_rr : HInst<
12172(outs IntRegs:$Rd32),
12173(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12174"$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12175tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12176let Inst{6-5} = 0b00;
12177let Inst{31-21} = 0b00111010010;
12178let hasNewValue = 1;
12179let opNewValue = 0;
12180let addrMode = BaseRegOffset;
12181let accessSize = HalfWordAccess;
12182let mayLoad = 1;
12183let BaseOpcode = "L4_loadrh_rr";
12184let CextOpcode = "L2_loadrh";
12185let InputType = "reg";
12186let isPredicable = 1;
12187}
12188def L4_loadrh_ur : HInst<
12189(outs IntRegs:$Rd32),
12190(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12191"$Rd32 = memh($Rt32<<#$Ii+#$II)",
12192tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12193let Inst{12-12} = 0b1;
12194let Inst{31-21} = 0b10011101010;
12195let hasNewValue = 1;
12196let opNewValue = 0;
12197let addrMode = BaseLongOffset;
12198let accessSize = HalfWordAccess;
12199let mayLoad = 1;
12200let isExtended = 1;
12201let CextOpcode = "L2_loadrh";
12202let InputType = "imm";
12203let DecoderNamespace = "MustExtend";
12204let isExtendable = 1;
12205let opExtendable = 3;
12206let isExtentSigned = 0;
12207let opExtentBits = 6;
12208let opExtentAlign = 0;
12209}
12210def L4_loadri_ap : HInst<
12211(outs IntRegs:$Rd32, IntRegs:$Re32),
12212(ins u32_0Imm:$II),
12213"$Rd32 = memw($Re32=#$II)",
12214tc_822c3c68, TypeLD>, Enc_323f2d {
12215let Inst{7-7} = 0b0;
12216let Inst{13-12} = 0b01;
12217let Inst{31-21} = 0b10011011100;
12218let hasNewValue = 1;
12219let opNewValue = 0;
12220let addrMode = AbsoluteSet;
12221let accessSize = WordAccess;
12222let mayLoad = 1;
12223let isExtended = 1;
12224let DecoderNamespace = "MustExtend";
12225let isExtendable = 1;
12226let opExtendable = 2;
12227let isExtentSigned = 0;
12228let opExtentBits = 6;
12229let opExtentAlign = 0;
12230}
12231def L4_loadri_rr : HInst<
12232(outs IntRegs:$Rd32),
12233(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12234"$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12235tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12236let Inst{6-5} = 0b00;
12237let Inst{31-21} = 0b00111010100;
12238let hasNewValue = 1;
12239let opNewValue = 0;
12240let addrMode = BaseRegOffset;
12241let accessSize = WordAccess;
12242let mayLoad = 1;
12243let BaseOpcode = "L4_loadri_rr";
12244let CextOpcode = "L2_loadri";
12245let InputType = "reg";
12246let isPredicable = 1;
12247}
12248def L4_loadri_ur : HInst<
12249(outs IntRegs:$Rd32),
12250(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12251"$Rd32 = memw($Rt32<<#$Ii+#$II)",
12252tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12253let Inst{12-12} = 0b1;
12254let Inst{31-21} = 0b10011101100;
12255let hasNewValue = 1;
12256let opNewValue = 0;
12257let addrMode = BaseLongOffset;
12258let accessSize = WordAccess;
12259let mayLoad = 1;
12260let isExtended = 1;
12261let CextOpcode = "L2_loadri";
12262let InputType = "imm";
12263let DecoderNamespace = "MustExtend";
12264let isExtendable = 1;
12265let opExtendable = 3;
12266let isExtentSigned = 0;
12267let opExtentBits = 6;
12268let opExtentAlign = 0;
12269}
12270def L4_loadrub_ap : HInst<
12271(outs IntRegs:$Rd32, IntRegs:$Re32),
12272(ins u32_0Imm:$II),
12273"$Rd32 = memub($Re32=#$II)",
12274tc_822c3c68, TypeLD>, Enc_323f2d {
12275let Inst{7-7} = 0b0;
12276let Inst{13-12} = 0b01;
12277let Inst{31-21} = 0b10011011001;
12278let hasNewValue = 1;
12279let opNewValue = 0;
12280let addrMode = AbsoluteSet;
12281let accessSize = ByteAccess;
12282let mayLoad = 1;
12283let isExtended = 1;
12284let DecoderNamespace = "MustExtend";
12285let isExtendable = 1;
12286let opExtendable = 2;
12287let isExtentSigned = 0;
12288let opExtentBits = 6;
12289let opExtentAlign = 0;
12290}
12291def L4_loadrub_rr : HInst<
12292(outs IntRegs:$Rd32),
12293(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12294"$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12295tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12296let Inst{6-5} = 0b00;
12297let Inst{31-21} = 0b00111010001;
12298let hasNewValue = 1;
12299let opNewValue = 0;
12300let addrMode = BaseRegOffset;
12301let accessSize = ByteAccess;
12302let mayLoad = 1;
12303let BaseOpcode = "L4_loadrub_rr";
12304let CextOpcode = "L2_loadrub";
12305let InputType = "reg";
12306let isPredicable = 1;
12307}
12308def L4_loadrub_ur : HInst<
12309(outs IntRegs:$Rd32),
12310(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12311"$Rd32 = memub($Rt32<<#$Ii+#$II)",
12312tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12313let Inst{12-12} = 0b1;
12314let Inst{31-21} = 0b10011101001;
12315let hasNewValue = 1;
12316let opNewValue = 0;
12317let addrMode = BaseLongOffset;
12318let accessSize = ByteAccess;
12319let mayLoad = 1;
12320let isExtended = 1;
12321let CextOpcode = "L2_loadrub";
12322let InputType = "imm";
12323let DecoderNamespace = "MustExtend";
12324let isExtendable = 1;
12325let opExtendable = 3;
12326let isExtentSigned = 0;
12327let opExtentBits = 6;
12328let opExtentAlign = 0;
12329}
12330def L4_loadruh_ap : HInst<
12331(outs IntRegs:$Rd32, IntRegs:$Re32),
12332(ins u32_0Imm:$II),
12333"$Rd32 = memuh($Re32=#$II)",
12334tc_822c3c68, TypeLD>, Enc_323f2d {
12335let Inst{7-7} = 0b0;
12336let Inst{13-12} = 0b01;
12337let Inst{31-21} = 0b10011011011;
12338let hasNewValue = 1;
12339let opNewValue = 0;
12340let addrMode = AbsoluteSet;
12341let accessSize = HalfWordAccess;
12342let mayLoad = 1;
12343let isExtended = 1;
12344let DecoderNamespace = "MustExtend";
12345let isExtendable = 1;
12346let opExtendable = 2;
12347let isExtentSigned = 0;
12348let opExtentBits = 6;
12349let opExtentAlign = 0;
12350}
12351def L4_loadruh_rr : HInst<
12352(outs IntRegs:$Rd32),
12353(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12354"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
12355tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12356let Inst{6-5} = 0b00;
12357let Inst{31-21} = 0b00111010011;
12358let hasNewValue = 1;
12359let opNewValue = 0;
12360let addrMode = BaseRegOffset;
12361let accessSize = HalfWordAccess;
12362let mayLoad = 1;
12363let BaseOpcode = "L4_loadruh_rr";
12364let CextOpcode = "L2_loadruh";
12365let InputType = "reg";
12366let isPredicable = 1;
12367}
12368def L4_loadruh_ur : HInst<
12369(outs IntRegs:$Rd32),
12370(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12371"$Rd32 = memuh($Rt32<<#$Ii+#$II)",
12372tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12373let Inst{12-12} = 0b1;
12374let Inst{31-21} = 0b10011101011;
12375let hasNewValue = 1;
12376let opNewValue = 0;
12377let addrMode = BaseLongOffset;
12378let accessSize = HalfWordAccess;
12379let mayLoad = 1;
12380let isExtended = 1;
12381let CextOpcode = "L2_loadruh";
12382let InputType = "imm";
12383let DecoderNamespace = "MustExtend";
12384let isExtendable = 1;
12385let opExtendable = 3;
12386let isExtentSigned = 0;
12387let opExtentBits = 6;
12388let opExtentAlign = 0;
12389}
12390def L4_or_memopb_io : HInst<
12391(outs),
12392(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
12393"memb($Rs32+#$Ii) |= $Rt32",
12394tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
12395let Inst{6-5} = 0b11;
12396let Inst{13-13} = 0b0;
12397let Inst{31-21} = 0b00111110000;
12398let addrMode = BaseImmOffset;
12399let accessSize = ByteAccess;
12400let mayLoad = 1;
12401let isRestrictNoSlot1Store = 1;
12402let mayStore = 1;
12403let isExtendable = 1;
12404let opExtendable = 1;
12405let isExtentSigned = 0;
12406let opExtentBits = 6;
12407let opExtentAlign = 0;
12408}
12409def L4_or_memopb_zomap : HInst<
12410(outs),
12411(ins IntRegs:$Rs32, IntRegs:$Rt32),
12412"memb($Rs32) |= $Rt32",
12413tc_9bcfb2ee, TypeMAPPING> {
12414let isPseudo = 1;
12415let isCodeGenOnly = 1;
12416}
12417def L4_or_memoph_io : HInst<
12418(outs),
12419(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
12420"memh($Rs32+#$Ii) |= $Rt32",
12421tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
12422let Inst{6-5} = 0b11;
12423let Inst{13-13} = 0b0;
12424let Inst{31-21} = 0b00111110001;
12425let addrMode = BaseImmOffset;
12426let accessSize = HalfWordAccess;
12427let mayLoad = 1;
12428let isRestrictNoSlot1Store = 1;
12429let mayStore = 1;
12430let isExtendable = 1;
12431let opExtendable = 1;
12432let isExtentSigned = 0;
12433let opExtentBits = 7;
12434let opExtentAlign = 1;
12435}
12436def L4_or_memoph_zomap : HInst<
12437(outs),
12438(ins IntRegs:$Rs32, IntRegs:$Rt32),
12439"memh($Rs32) |= $Rt32",
12440tc_9bcfb2ee, TypeMAPPING> {
12441let isPseudo = 1;
12442let isCodeGenOnly = 1;
12443}
12444def L4_or_memopw_io : HInst<
12445(outs),
12446(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
12447"memw($Rs32+#$Ii) |= $Rt32",
12448tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
12449let Inst{6-5} = 0b11;
12450let Inst{13-13} = 0b0;
12451let Inst{31-21} = 0b00111110010;
12452let addrMode = BaseImmOffset;
12453let accessSize = WordAccess;
12454let mayLoad = 1;
12455let isRestrictNoSlot1Store = 1;
12456let mayStore = 1;
12457let isExtendable = 1;
12458let opExtendable = 1;
12459let isExtentSigned = 0;
12460let opExtentBits = 8;
12461let opExtentAlign = 2;
12462}
12463def L4_or_memopw_zomap : HInst<
12464(outs),
12465(ins IntRegs:$Rs32, IntRegs:$Rt32),
12466"memw($Rs32) |= $Rt32",
12467tc_9bcfb2ee, TypeMAPPING> {
12468let isPseudo = 1;
12469let isCodeGenOnly = 1;
12470}
12471def L4_ploadrbf_abs : HInst<
12472(outs IntRegs:$Rd32),
12473(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12474"if (!$Pt4) $Rd32 = memb(#$Ii)",
12475tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12476let Inst{7-5} = 0b100;
12477let Inst{13-11} = 0b101;
12478let Inst{31-21} = 0b10011111000;
12479let isPredicated = 1;
12480let isPredicatedFalse = 1;
12481let hasNewValue = 1;
12482let opNewValue = 0;
12483let addrMode = Absolute;
12484let accessSize = ByteAccess;
12485let mayLoad = 1;
12486let isExtended = 1;
12487let BaseOpcode = "L4_loadrb_abs";
12488let CextOpcode = "L2_loadrb";
12489let DecoderNamespace = "MustExtend";
12490let isExtendable = 1;
12491let opExtendable = 2;
12492let isExtentSigned = 0;
12493let opExtentBits = 6;
12494let opExtentAlign = 0;
12495}
12496def L4_ploadrbf_rr : HInst<
12497(outs IntRegs:$Rd32),
12498(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12499"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12500tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12501let Inst{31-21} = 0b00110001000;
12502let isPredicated = 1;
12503let isPredicatedFalse = 1;
12504let hasNewValue = 1;
12505let opNewValue = 0;
12506let addrMode = BaseRegOffset;
12507let accessSize = ByteAccess;
12508let mayLoad = 1;
12509let BaseOpcode = "L4_loadrb_rr";
12510let CextOpcode = "L2_loadrb";
12511let InputType = "reg";
12512}
12513def L4_ploadrbfnew_abs : HInst<
12514(outs IntRegs:$Rd32),
12515(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12516"if (!$Pt4.new) $Rd32 = memb(#$Ii)",
12517tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12518let Inst{7-5} = 0b100;
12519let Inst{13-11} = 0b111;
12520let Inst{31-21} = 0b10011111000;
12521let isPredicated = 1;
12522let isPredicatedFalse = 1;
12523let hasNewValue = 1;
12524let opNewValue = 0;
12525let addrMode = Absolute;
12526let accessSize = ByteAccess;
12527let isPredicatedNew = 1;
12528let mayLoad = 1;
12529let isExtended = 1;
12530let BaseOpcode = "L4_loadrb_abs";
12531let CextOpcode = "L2_loadrb";
12532let DecoderNamespace = "MustExtend";
12533let isExtendable = 1;
12534let opExtendable = 2;
12535let isExtentSigned = 0;
12536let opExtentBits = 6;
12537let opExtentAlign = 0;
12538}
12539def L4_ploadrbfnew_rr : HInst<
12540(outs IntRegs:$Rd32),
12541(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12542"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12543tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12544let Inst{31-21} = 0b00110011000;
12545let isPredicated = 1;
12546let isPredicatedFalse = 1;
12547let hasNewValue = 1;
12548let opNewValue = 0;
12549let addrMode = BaseRegOffset;
12550let accessSize = ByteAccess;
12551let isPredicatedNew = 1;
12552let mayLoad = 1;
12553let BaseOpcode = "L4_loadrb_rr";
12554let CextOpcode = "L2_loadrb";
12555let InputType = "reg";
12556}
12557def L4_ploadrbt_abs : HInst<
12558(outs IntRegs:$Rd32),
12559(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12560"if ($Pt4) $Rd32 = memb(#$Ii)",
12561tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12562let Inst{7-5} = 0b100;
12563let Inst{13-11} = 0b100;
12564let Inst{31-21} = 0b10011111000;
12565let isPredicated = 1;
12566let hasNewValue = 1;
12567let opNewValue = 0;
12568let addrMode = Absolute;
12569let accessSize = ByteAccess;
12570let mayLoad = 1;
12571let isExtended = 1;
12572let BaseOpcode = "L4_loadrb_abs";
12573let CextOpcode = "L2_loadrb";
12574let DecoderNamespace = "MustExtend";
12575let isExtendable = 1;
12576let opExtendable = 2;
12577let isExtentSigned = 0;
12578let opExtentBits = 6;
12579let opExtentAlign = 0;
12580}
12581def L4_ploadrbt_rr : HInst<
12582(outs IntRegs:$Rd32),
12583(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12584"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12585tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12586let Inst{31-21} = 0b00110000000;
12587let isPredicated = 1;
12588let hasNewValue = 1;
12589let opNewValue = 0;
12590let addrMode = BaseRegOffset;
12591let accessSize = ByteAccess;
12592let mayLoad = 1;
12593let BaseOpcode = "L4_loadrb_rr";
12594let CextOpcode = "L2_loadrb";
12595let InputType = "reg";
12596}
12597def L4_ploadrbtnew_abs : HInst<
12598(outs IntRegs:$Rd32),
12599(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12600"if ($Pt4.new) $Rd32 = memb(#$Ii)",
12601tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12602let Inst{7-5} = 0b100;
12603let Inst{13-11} = 0b110;
12604let Inst{31-21} = 0b10011111000;
12605let isPredicated = 1;
12606let hasNewValue = 1;
12607let opNewValue = 0;
12608let addrMode = Absolute;
12609let accessSize = ByteAccess;
12610let isPredicatedNew = 1;
12611let mayLoad = 1;
12612let isExtended = 1;
12613let BaseOpcode = "L4_loadrb_abs";
12614let CextOpcode = "L2_loadrb";
12615let DecoderNamespace = "MustExtend";
12616let isExtendable = 1;
12617let opExtendable = 2;
12618let isExtentSigned = 0;
12619let opExtentBits = 6;
12620let opExtentAlign = 0;
12621}
12622def L4_ploadrbtnew_rr : HInst<
12623(outs IntRegs:$Rd32),
12624(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12625"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12626tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12627let Inst{31-21} = 0b00110010000;
12628let isPredicated = 1;
12629let hasNewValue = 1;
12630let opNewValue = 0;
12631let addrMode = BaseRegOffset;
12632let accessSize = ByteAccess;
12633let isPredicatedNew = 1;
12634let mayLoad = 1;
12635let BaseOpcode = "L4_loadrb_rr";
12636let CextOpcode = "L2_loadrb";
12637let InputType = "reg";
12638}
12639def L4_ploadrdf_abs : HInst<
12640(outs DoubleRegs:$Rdd32),
12641(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12642"if (!$Pt4) $Rdd32 = memd(#$Ii)",
12643tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12644let Inst{7-5} = 0b100;
12645let Inst{13-11} = 0b101;
12646let Inst{31-21} = 0b10011111110;
12647let isPredicated = 1;
12648let isPredicatedFalse = 1;
12649let addrMode = Absolute;
12650let accessSize = DoubleWordAccess;
12651let mayLoad = 1;
12652let isExtended = 1;
12653let BaseOpcode = "L4_loadrd_abs";
12654let CextOpcode = "L2_loadrd";
12655let DecoderNamespace = "MustExtend";
12656let isExtendable = 1;
12657let opExtendable = 2;
12658let isExtentSigned = 0;
12659let opExtentBits = 6;
12660let opExtentAlign = 0;
12661}
12662def L4_ploadrdf_rr : HInst<
12663(outs DoubleRegs:$Rdd32),
12664(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12665"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12666tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12667let Inst{31-21} = 0b00110001110;
12668let isPredicated = 1;
12669let isPredicatedFalse = 1;
12670let addrMode = BaseRegOffset;
12671let accessSize = DoubleWordAccess;
12672let mayLoad = 1;
12673let BaseOpcode = "L4_loadrd_rr";
12674let CextOpcode = "L2_loadrd";
12675let InputType = "reg";
12676}
12677def L4_ploadrdfnew_abs : HInst<
12678(outs DoubleRegs:$Rdd32),
12679(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12680"if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
12681tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12682let Inst{7-5} = 0b100;
12683let Inst{13-11} = 0b111;
12684let Inst{31-21} = 0b10011111110;
12685let isPredicated = 1;
12686let isPredicatedFalse = 1;
12687let addrMode = Absolute;
12688let accessSize = DoubleWordAccess;
12689let isPredicatedNew = 1;
12690let mayLoad = 1;
12691let isExtended = 1;
12692let BaseOpcode = "L4_loadrd_abs";
12693let CextOpcode = "L2_loadrd";
12694let DecoderNamespace = "MustExtend";
12695let isExtendable = 1;
12696let opExtendable = 2;
12697let isExtentSigned = 0;
12698let opExtentBits = 6;
12699let opExtentAlign = 0;
12700}
12701def L4_ploadrdfnew_rr : HInst<
12702(outs DoubleRegs:$Rdd32),
12703(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12704"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12705tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12706let Inst{31-21} = 0b00110011110;
12707let isPredicated = 1;
12708let isPredicatedFalse = 1;
12709let addrMode = BaseRegOffset;
12710let accessSize = DoubleWordAccess;
12711let isPredicatedNew = 1;
12712let mayLoad = 1;
12713let BaseOpcode = "L4_loadrd_rr";
12714let CextOpcode = "L2_loadrd";
12715let InputType = "reg";
12716}
12717def L4_ploadrdt_abs : HInst<
12718(outs DoubleRegs:$Rdd32),
12719(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12720"if ($Pt4) $Rdd32 = memd(#$Ii)",
12721tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12722let Inst{7-5} = 0b100;
12723let Inst{13-11} = 0b100;
12724let Inst{31-21} = 0b10011111110;
12725let isPredicated = 1;
12726let addrMode = Absolute;
12727let accessSize = DoubleWordAccess;
12728let mayLoad = 1;
12729let isExtended = 1;
12730let BaseOpcode = "L4_loadrd_abs";
12731let CextOpcode = "L2_loadrd";
12732let DecoderNamespace = "MustExtend";
12733let isExtendable = 1;
12734let opExtendable = 2;
12735let isExtentSigned = 0;
12736let opExtentBits = 6;
12737let opExtentAlign = 0;
12738}
12739def L4_ploadrdt_rr : HInst<
12740(outs DoubleRegs:$Rdd32),
12741(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12742"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12743tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12744let Inst{31-21} = 0b00110000110;
12745let isPredicated = 1;
12746let addrMode = BaseRegOffset;
12747let accessSize = DoubleWordAccess;
12748let mayLoad = 1;
12749let BaseOpcode = "L4_loadrd_rr";
12750let CextOpcode = "L2_loadrd";
12751let InputType = "reg";
12752}
12753def L4_ploadrdtnew_abs : HInst<
12754(outs DoubleRegs:$Rdd32),
12755(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12756"if ($Pt4.new) $Rdd32 = memd(#$Ii)",
12757tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12758let Inst{7-5} = 0b100;
12759let Inst{13-11} = 0b110;
12760let Inst{31-21} = 0b10011111110;
12761let isPredicated = 1;
12762let addrMode = Absolute;
12763let accessSize = DoubleWordAccess;
12764let isPredicatedNew = 1;
12765let mayLoad = 1;
12766let isExtended = 1;
12767let BaseOpcode = "L4_loadrd_abs";
12768let CextOpcode = "L2_loadrd";
12769let DecoderNamespace = "MustExtend";
12770let isExtendable = 1;
12771let opExtendable = 2;
12772let isExtentSigned = 0;
12773let opExtentBits = 6;
12774let opExtentAlign = 0;
12775}
12776def L4_ploadrdtnew_rr : HInst<
12777(outs DoubleRegs:$Rdd32),
12778(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12779"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12780tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12781let Inst{31-21} = 0b00110010110;
12782let isPredicated = 1;
12783let addrMode = BaseRegOffset;
12784let accessSize = DoubleWordAccess;
12785let isPredicatedNew = 1;
12786let mayLoad = 1;
12787let BaseOpcode = "L4_loadrd_rr";
12788let CextOpcode = "L2_loadrd";
12789let InputType = "reg";
12790}
12791def L4_ploadrhf_abs : HInst<
12792(outs IntRegs:$Rd32),
12793(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12794"if (!$Pt4) $Rd32 = memh(#$Ii)",
12795tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12796let Inst{7-5} = 0b100;
12797let Inst{13-11} = 0b101;
12798let Inst{31-21} = 0b10011111010;
12799let isPredicated = 1;
12800let isPredicatedFalse = 1;
12801let hasNewValue = 1;
12802let opNewValue = 0;
12803let addrMode = Absolute;
12804let accessSize = HalfWordAccess;
12805let mayLoad = 1;
12806let isExtended = 1;
12807let BaseOpcode = "L4_loadrh_abs";
12808let CextOpcode = "L2_loadrh";
12809let DecoderNamespace = "MustExtend";
12810let isExtendable = 1;
12811let opExtendable = 2;
12812let isExtentSigned = 0;
12813let opExtentBits = 6;
12814let opExtentAlign = 0;
12815}
12816def L4_ploadrhf_rr : HInst<
12817(outs IntRegs:$Rd32),
12818(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12819"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12820tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12821let Inst{31-21} = 0b00110001010;
12822let isPredicated = 1;
12823let isPredicatedFalse = 1;
12824let hasNewValue = 1;
12825let opNewValue = 0;
12826let addrMode = BaseRegOffset;
12827let accessSize = HalfWordAccess;
12828let mayLoad = 1;
12829let BaseOpcode = "L4_loadrh_rr";
12830let CextOpcode = "L2_loadrh";
12831let InputType = "reg";
12832}
12833def L4_ploadrhfnew_abs : HInst<
12834(outs IntRegs:$Rd32),
12835(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12836"if (!$Pt4.new) $Rd32 = memh(#$Ii)",
12837tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12838let Inst{7-5} = 0b100;
12839let Inst{13-11} = 0b111;
12840let Inst{31-21} = 0b10011111010;
12841let isPredicated = 1;
12842let isPredicatedFalse = 1;
12843let hasNewValue = 1;
12844let opNewValue = 0;
12845let addrMode = Absolute;
12846let accessSize = HalfWordAccess;
12847let isPredicatedNew = 1;
12848let mayLoad = 1;
12849let isExtended = 1;
12850let BaseOpcode = "L4_loadrh_abs";
12851let CextOpcode = "L2_loadrh";
12852let DecoderNamespace = "MustExtend";
12853let isExtendable = 1;
12854let opExtendable = 2;
12855let isExtentSigned = 0;
12856let opExtentBits = 6;
12857let opExtentAlign = 0;
12858}
12859def L4_ploadrhfnew_rr : HInst<
12860(outs IntRegs:$Rd32),
12861(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12862"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12863tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12864let Inst{31-21} = 0b00110011010;
12865let isPredicated = 1;
12866let isPredicatedFalse = 1;
12867let hasNewValue = 1;
12868let opNewValue = 0;
12869let addrMode = BaseRegOffset;
12870let accessSize = HalfWordAccess;
12871let isPredicatedNew = 1;
12872let mayLoad = 1;
12873let BaseOpcode = "L4_loadrh_rr";
12874let CextOpcode = "L2_loadrh";
12875let InputType = "reg";
12876}
12877def L4_ploadrht_abs : HInst<
12878(outs IntRegs:$Rd32),
12879(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12880"if ($Pt4) $Rd32 = memh(#$Ii)",
12881tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12882let Inst{7-5} = 0b100;
12883let Inst{13-11} = 0b100;
12884let Inst{31-21} = 0b10011111010;
12885let isPredicated = 1;
12886let hasNewValue = 1;
12887let opNewValue = 0;
12888let addrMode = Absolute;
12889let accessSize = HalfWordAccess;
12890let mayLoad = 1;
12891let isExtended = 1;
12892let BaseOpcode = "L4_loadrh_abs";
12893let CextOpcode = "L2_loadrh";
12894let DecoderNamespace = "MustExtend";
12895let isExtendable = 1;
12896let opExtendable = 2;
12897let isExtentSigned = 0;
12898let opExtentBits = 6;
12899let opExtentAlign = 0;
12900}
12901def L4_ploadrht_rr : HInst<
12902(outs IntRegs:$Rd32),
12903(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12904"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12905tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12906let Inst{31-21} = 0b00110000010;
12907let isPredicated = 1;
12908let hasNewValue = 1;
12909let opNewValue = 0;
12910let addrMode = BaseRegOffset;
12911let accessSize = HalfWordAccess;
12912let mayLoad = 1;
12913let BaseOpcode = "L4_loadrh_rr";
12914let CextOpcode = "L2_loadrh";
12915let InputType = "reg";
12916}
12917def L4_ploadrhtnew_abs : HInst<
12918(outs IntRegs:$Rd32),
12919(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12920"if ($Pt4.new) $Rd32 = memh(#$Ii)",
12921tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12922let Inst{7-5} = 0b100;
12923let Inst{13-11} = 0b110;
12924let Inst{31-21} = 0b10011111010;
12925let isPredicated = 1;
12926let hasNewValue = 1;
12927let opNewValue = 0;
12928let addrMode = Absolute;
12929let accessSize = HalfWordAccess;
12930let isPredicatedNew = 1;
12931let mayLoad = 1;
12932let isExtended = 1;
12933let BaseOpcode = "L4_loadrh_abs";
12934let CextOpcode = "L2_loadrh";
12935let DecoderNamespace = "MustExtend";
12936let isExtendable = 1;
12937let opExtendable = 2;
12938let isExtentSigned = 0;
12939let opExtentBits = 6;
12940let opExtentAlign = 0;
12941}
12942def L4_ploadrhtnew_rr : HInst<
12943(outs IntRegs:$Rd32),
12944(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12945"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12946tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12947let Inst{31-21} = 0b00110010010;
12948let isPredicated = 1;
12949let hasNewValue = 1;
12950let opNewValue = 0;
12951let addrMode = BaseRegOffset;
12952let accessSize = HalfWordAccess;
12953let isPredicatedNew = 1;
12954let mayLoad = 1;
12955let BaseOpcode = "L4_loadrh_rr";
12956let CextOpcode = "L2_loadrh";
12957let InputType = "reg";
12958}
12959def L4_ploadrif_abs : HInst<
12960(outs IntRegs:$Rd32),
12961(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12962"if (!$Pt4) $Rd32 = memw(#$Ii)",
12963tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12964let Inst{7-5} = 0b100;
12965let Inst{13-11} = 0b101;
12966let Inst{31-21} = 0b10011111100;
12967let isPredicated = 1;
12968let isPredicatedFalse = 1;
12969let hasNewValue = 1;
12970let opNewValue = 0;
12971let addrMode = Absolute;
12972let accessSize = WordAccess;
12973let mayLoad = 1;
12974let isExtended = 1;
12975let BaseOpcode = "L4_loadri_abs";
12976let CextOpcode = "L2_loadri";
12977let DecoderNamespace = "MustExtend";
12978let isExtendable = 1;
12979let opExtendable = 2;
12980let isExtentSigned = 0;
12981let opExtentBits = 6;
12982let opExtentAlign = 0;
12983}
12984def L4_ploadrif_rr : HInst<
12985(outs IntRegs:$Rd32),
12986(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12987"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12988tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12989let Inst{31-21} = 0b00110001100;
12990let isPredicated = 1;
12991let isPredicatedFalse = 1;
12992let hasNewValue = 1;
12993let opNewValue = 0;
12994let addrMode = BaseRegOffset;
12995let accessSize = WordAccess;
12996let mayLoad = 1;
12997let BaseOpcode = "L4_loadri_rr";
12998let CextOpcode = "L2_loadri";
12999let InputType = "reg";
13000}
13001def L4_ploadrifnew_abs : HInst<
13002(outs IntRegs:$Rd32),
13003(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13004"if (!$Pt4.new) $Rd32 = memw(#$Ii)",
13005tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13006let Inst{7-5} = 0b100;
13007let Inst{13-11} = 0b111;
13008let Inst{31-21} = 0b10011111100;
13009let isPredicated = 1;
13010let isPredicatedFalse = 1;
13011let hasNewValue = 1;
13012let opNewValue = 0;
13013let addrMode = Absolute;
13014let accessSize = WordAccess;
13015let isPredicatedNew = 1;
13016let mayLoad = 1;
13017let isExtended = 1;
13018let BaseOpcode = "L4_loadri_abs";
13019let CextOpcode = "L2_loadri";
13020let DecoderNamespace = "MustExtend";
13021let isExtendable = 1;
13022let opExtendable = 2;
13023let isExtentSigned = 0;
13024let opExtentBits = 6;
13025let opExtentAlign = 0;
13026}
13027def L4_ploadrifnew_rr : HInst<
13028(outs IntRegs:$Rd32),
13029(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13030"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13031tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13032let Inst{31-21} = 0b00110011100;
13033let isPredicated = 1;
13034let isPredicatedFalse = 1;
13035let hasNewValue = 1;
13036let opNewValue = 0;
13037let addrMode = BaseRegOffset;
13038let accessSize = WordAccess;
13039let isPredicatedNew = 1;
13040let mayLoad = 1;
13041let BaseOpcode = "L4_loadri_rr";
13042let CextOpcode = "L2_loadri";
13043let InputType = "reg";
13044}
13045def L4_ploadrit_abs : HInst<
13046(outs IntRegs:$Rd32),
13047(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13048"if ($Pt4) $Rd32 = memw(#$Ii)",
13049tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13050let Inst{7-5} = 0b100;
13051let Inst{13-11} = 0b100;
13052let Inst{31-21} = 0b10011111100;
13053let isPredicated = 1;
13054let hasNewValue = 1;
13055let opNewValue = 0;
13056let addrMode = Absolute;
13057let accessSize = WordAccess;
13058let mayLoad = 1;
13059let isExtended = 1;
13060let BaseOpcode = "L4_loadri_abs";
13061let CextOpcode = "L2_loadri";
13062let DecoderNamespace = "MustExtend";
13063let isExtendable = 1;
13064let opExtendable = 2;
13065let isExtentSigned = 0;
13066let opExtentBits = 6;
13067let opExtentAlign = 0;
13068}
13069def L4_ploadrit_rr : HInst<
13070(outs IntRegs:$Rd32),
13071(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13072"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13073tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13074let Inst{31-21} = 0b00110000100;
13075let isPredicated = 1;
13076let hasNewValue = 1;
13077let opNewValue = 0;
13078let addrMode = BaseRegOffset;
13079let accessSize = WordAccess;
13080let mayLoad = 1;
13081let BaseOpcode = "L4_loadri_rr";
13082let CextOpcode = "L2_loadri";
13083let InputType = "reg";
13084}
13085def L4_ploadritnew_abs : HInst<
13086(outs IntRegs:$Rd32),
13087(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13088"if ($Pt4.new) $Rd32 = memw(#$Ii)",
13089tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13090let Inst{7-5} = 0b100;
13091let Inst{13-11} = 0b110;
13092let Inst{31-21} = 0b10011111100;
13093let isPredicated = 1;
13094let hasNewValue = 1;
13095let opNewValue = 0;
13096let addrMode = Absolute;
13097let accessSize = WordAccess;
13098let isPredicatedNew = 1;
13099let mayLoad = 1;
13100let isExtended = 1;
13101let BaseOpcode = "L4_loadri_abs";
13102let CextOpcode = "L2_loadri";
13103let DecoderNamespace = "MustExtend";
13104let isExtendable = 1;
13105let opExtendable = 2;
13106let isExtentSigned = 0;
13107let opExtentBits = 6;
13108let opExtentAlign = 0;
13109}
13110def L4_ploadritnew_rr : HInst<
13111(outs IntRegs:$Rd32),
13112(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13113"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13114tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13115let Inst{31-21} = 0b00110010100;
13116let isPredicated = 1;
13117let hasNewValue = 1;
13118let opNewValue = 0;
13119let addrMode = BaseRegOffset;
13120let accessSize = WordAccess;
13121let isPredicatedNew = 1;
13122let mayLoad = 1;
13123let BaseOpcode = "L4_loadri_rr";
13124let CextOpcode = "L2_loadri";
13125let InputType = "reg";
13126}
13127def L4_ploadrubf_abs : HInst<
13128(outs IntRegs:$Rd32),
13129(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13130"if (!$Pt4) $Rd32 = memub(#$Ii)",
13131tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13132let Inst{7-5} = 0b100;
13133let Inst{13-11} = 0b101;
13134let Inst{31-21} = 0b10011111001;
13135let isPredicated = 1;
13136let isPredicatedFalse = 1;
13137let hasNewValue = 1;
13138let opNewValue = 0;
13139let addrMode = Absolute;
13140let accessSize = ByteAccess;
13141let mayLoad = 1;
13142let isExtended = 1;
13143let BaseOpcode = "L4_loadrub_abs";
13144let CextOpcode = "L2_loadrub";
13145let DecoderNamespace = "MustExtend";
13146let isExtendable = 1;
13147let opExtendable = 2;
13148let isExtentSigned = 0;
13149let opExtentBits = 6;
13150let opExtentAlign = 0;
13151}
13152def L4_ploadrubf_rr : HInst<
13153(outs IntRegs:$Rd32),
13154(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13155"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13156tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13157let Inst{31-21} = 0b00110001001;
13158let isPredicated = 1;
13159let isPredicatedFalse = 1;
13160let hasNewValue = 1;
13161let opNewValue = 0;
13162let addrMode = BaseRegOffset;
13163let accessSize = ByteAccess;
13164let mayLoad = 1;
13165let BaseOpcode = "L4_loadrub_rr";
13166let CextOpcode = "L2_loadrub";
13167let InputType = "reg";
13168}
13169def L4_ploadrubfnew_abs : HInst<
13170(outs IntRegs:$Rd32),
13171(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13172"if (!$Pt4.new) $Rd32 = memub(#$Ii)",
13173tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13174let Inst{7-5} = 0b100;
13175let Inst{13-11} = 0b111;
13176let Inst{31-21} = 0b10011111001;
13177let isPredicated = 1;
13178let isPredicatedFalse = 1;
13179let hasNewValue = 1;
13180let opNewValue = 0;
13181let addrMode = Absolute;
13182let accessSize = ByteAccess;
13183let isPredicatedNew = 1;
13184let mayLoad = 1;
13185let isExtended = 1;
13186let BaseOpcode = "L4_loadrub_abs";
13187let CextOpcode = "L2_loadrub";
13188let DecoderNamespace = "MustExtend";
13189let isExtendable = 1;
13190let opExtendable = 2;
13191let isExtentSigned = 0;
13192let opExtentBits = 6;
13193let opExtentAlign = 0;
13194}
13195def L4_ploadrubfnew_rr : HInst<
13196(outs IntRegs:$Rd32),
13197(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13198"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13199tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13200let Inst{31-21} = 0b00110011001;
13201let isPredicated = 1;
13202let isPredicatedFalse = 1;
13203let hasNewValue = 1;
13204let opNewValue = 0;
13205let addrMode = BaseRegOffset;
13206let accessSize = ByteAccess;
13207let isPredicatedNew = 1;
13208let mayLoad = 1;
13209let BaseOpcode = "L4_loadrub_rr";
13210let CextOpcode = "L2_loadrub";
13211let InputType = "reg";
13212}
13213def L4_ploadrubt_abs : HInst<
13214(outs IntRegs:$Rd32),
13215(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13216"if ($Pt4) $Rd32 = memub(#$Ii)",
13217tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13218let Inst{7-5} = 0b100;
13219let Inst{13-11} = 0b100;
13220let Inst{31-21} = 0b10011111001;
13221let isPredicated = 1;
13222let hasNewValue = 1;
13223let opNewValue = 0;
13224let addrMode = Absolute;
13225let accessSize = ByteAccess;
13226let mayLoad = 1;
13227let isExtended = 1;
13228let BaseOpcode = "L4_loadrub_abs";
13229let CextOpcode = "L2_loadrub";
13230let DecoderNamespace = "MustExtend";
13231let isExtendable = 1;
13232let opExtendable = 2;
13233let isExtentSigned = 0;
13234let opExtentBits = 6;
13235let opExtentAlign = 0;
13236}
13237def L4_ploadrubt_rr : HInst<
13238(outs IntRegs:$Rd32),
13239(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13240"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13241tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13242let Inst{31-21} = 0b00110000001;
13243let isPredicated = 1;
13244let hasNewValue = 1;
13245let opNewValue = 0;
13246let addrMode = BaseRegOffset;
13247let accessSize = ByteAccess;
13248let mayLoad = 1;
13249let BaseOpcode = "L4_loadrub_rr";
13250let CextOpcode = "L2_loadrub";
13251let InputType = "reg";
13252}
13253def L4_ploadrubtnew_abs : HInst<
13254(outs IntRegs:$Rd32),
13255(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13256"if ($Pt4.new) $Rd32 = memub(#$Ii)",
13257tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13258let Inst{7-5} = 0b100;
13259let Inst{13-11} = 0b110;
13260let Inst{31-21} = 0b10011111001;
13261let isPredicated = 1;
13262let hasNewValue = 1;
13263let opNewValue = 0;
13264let addrMode = Absolute;
13265let accessSize = ByteAccess;
13266let isPredicatedNew = 1;
13267let mayLoad = 1;
13268let isExtended = 1;
13269let BaseOpcode = "L4_loadrub_abs";
13270let CextOpcode = "L2_loadrub";
13271let DecoderNamespace = "MustExtend";
13272let isExtendable = 1;
13273let opExtendable = 2;
13274let isExtentSigned = 0;
13275let opExtentBits = 6;
13276let opExtentAlign = 0;
13277}
13278def L4_ploadrubtnew_rr : HInst<
13279(outs IntRegs:$Rd32),
13280(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13281"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13282tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13283let Inst{31-21} = 0b00110010001;
13284let isPredicated = 1;
13285let hasNewValue = 1;
13286let opNewValue = 0;
13287let addrMode = BaseRegOffset;
13288let accessSize = ByteAccess;
13289let isPredicatedNew = 1;
13290let mayLoad = 1;
13291let BaseOpcode = "L4_loadrub_rr";
13292let CextOpcode = "L2_loadrub";
13293let InputType = "reg";
13294}
13295def L4_ploadruhf_abs : HInst<
13296(outs IntRegs:$Rd32),
13297(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13298"if (!$Pt4) $Rd32 = memuh(#$Ii)",
13299tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13300let Inst{7-5} = 0b100;
13301let Inst{13-11} = 0b101;
13302let Inst{31-21} = 0b10011111011;
13303let isPredicated = 1;
13304let isPredicatedFalse = 1;
13305let hasNewValue = 1;
13306let opNewValue = 0;
13307let addrMode = Absolute;
13308let accessSize = HalfWordAccess;
13309let mayLoad = 1;
13310let isExtended = 1;
13311let BaseOpcode = "L4_loadruh_abs";
13312let CextOpcode = "L2_loadruh";
13313let DecoderNamespace = "MustExtend";
13314let isExtendable = 1;
13315let opExtendable = 2;
13316let isExtentSigned = 0;
13317let opExtentBits = 6;
13318let opExtentAlign = 0;
13319}
13320def L4_ploadruhf_rr : HInst<
13321(outs IntRegs:$Rd32),
13322(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13323"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13324tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13325let Inst{31-21} = 0b00110001011;
13326let isPredicated = 1;
13327let isPredicatedFalse = 1;
13328let hasNewValue = 1;
13329let opNewValue = 0;
13330let addrMode = BaseRegOffset;
13331let accessSize = HalfWordAccess;
13332let mayLoad = 1;
13333let BaseOpcode = "L4_loadruh_rr";
13334let CextOpcode = "L2_loadruh";
13335let InputType = "reg";
13336}
13337def L4_ploadruhfnew_abs : HInst<
13338(outs IntRegs:$Rd32),
13339(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13340"if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
13341tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13342let Inst{7-5} = 0b100;
13343let Inst{13-11} = 0b111;
13344let Inst{31-21} = 0b10011111011;
13345let isPredicated = 1;
13346let isPredicatedFalse = 1;
13347let hasNewValue = 1;
13348let opNewValue = 0;
13349let addrMode = Absolute;
13350let accessSize = HalfWordAccess;
13351let isPredicatedNew = 1;
13352let mayLoad = 1;
13353let isExtended = 1;
13354let BaseOpcode = "L4_loadruh_abs";
13355let CextOpcode = "L2_loadruh";
13356let DecoderNamespace = "MustExtend";
13357let isExtendable = 1;
13358let opExtendable = 2;
13359let isExtentSigned = 0;
13360let opExtentBits = 6;
13361let opExtentAlign = 0;
13362}
13363def L4_ploadruhfnew_rr : HInst<
13364(outs IntRegs:$Rd32),
13365(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13366"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13367tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13368let Inst{31-21} = 0b00110011011;
13369let isPredicated = 1;
13370let isPredicatedFalse = 1;
13371let hasNewValue = 1;
13372let opNewValue = 0;
13373let addrMode = BaseRegOffset;
13374let accessSize = HalfWordAccess;
13375let isPredicatedNew = 1;
13376let mayLoad = 1;
13377let BaseOpcode = "L4_loadruh_rr";
13378let CextOpcode = "L2_loadruh";
13379let InputType = "reg";
13380}
13381def L4_ploadruht_abs : HInst<
13382(outs IntRegs:$Rd32),
13383(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13384"if ($Pt4) $Rd32 = memuh(#$Ii)",
13385tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13386let Inst{7-5} = 0b100;
13387let Inst{13-11} = 0b100;
13388let Inst{31-21} = 0b10011111011;
13389let isPredicated = 1;
13390let hasNewValue = 1;
13391let opNewValue = 0;
13392let addrMode = Absolute;
13393let accessSize = HalfWordAccess;
13394let mayLoad = 1;
13395let isExtended = 1;
13396let BaseOpcode = "L4_loadruh_abs";
13397let CextOpcode = "L2_loadruh";
13398let DecoderNamespace = "MustExtend";
13399let isExtendable = 1;
13400let opExtendable = 2;
13401let isExtentSigned = 0;
13402let opExtentBits = 6;
13403let opExtentAlign = 0;
13404}
13405def L4_ploadruht_rr : HInst<
13406(outs IntRegs:$Rd32),
13407(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13408"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13409tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13410let Inst{31-21} = 0b00110000011;
13411let isPredicated = 1;
13412let hasNewValue = 1;
13413let opNewValue = 0;
13414let addrMode = BaseRegOffset;
13415let accessSize = HalfWordAccess;
13416let mayLoad = 1;
13417let BaseOpcode = "L4_loadruh_rr";
13418let CextOpcode = "L2_loadruh";
13419let InputType = "reg";
13420}
13421def L4_ploadruhtnew_abs : HInst<
13422(outs IntRegs:$Rd32),
13423(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13424"if ($Pt4.new) $Rd32 = memuh(#$Ii)",
13425tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13426let Inst{7-5} = 0b100;
13427let Inst{13-11} = 0b110;
13428let Inst{31-21} = 0b10011111011;
13429let isPredicated = 1;
13430let hasNewValue = 1;
13431let opNewValue = 0;
13432let addrMode = Absolute;
13433let accessSize = HalfWordAccess;
13434let isPredicatedNew = 1;
13435let mayLoad = 1;
13436let isExtended = 1;
13437let BaseOpcode = "L4_loadruh_abs";
13438let CextOpcode = "L2_loadruh";
13439let DecoderNamespace = "MustExtend";
13440let isExtendable = 1;
13441let opExtendable = 2;
13442let isExtentSigned = 0;
13443let opExtentBits = 6;
13444let opExtentAlign = 0;
13445}
13446def L4_ploadruhtnew_rr : HInst<
13447(outs IntRegs:$Rd32),
13448(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13449"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13450tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13451let Inst{31-21} = 0b00110010011;
13452let isPredicated = 1;
13453let hasNewValue = 1;
13454let opNewValue = 0;
13455let addrMode = BaseRegOffset;
13456let accessSize = HalfWordAccess;
13457let isPredicatedNew = 1;
13458let mayLoad = 1;
13459let BaseOpcode = "L4_loadruh_rr";
13460let CextOpcode = "L2_loadruh";
13461let InputType = "reg";
13462}
13463def L4_return : HInst<
13464(outs DoubleRegs:$Rdd32),
13465(ins IntRegs:$Rs32),
13466"$Rdd32 = dealloc_return($Rs32):raw",
13467tc_40d64c94, TypeLD>, Enc_3a3d62, PredNewRel {
13468let Inst{13-5} = 0b000000000;
13469let Inst{31-21} = 0b10010110000;
13470let isTerminator = 1;
13471let isIndirectBranch = 1;
13472let accessSize = DoubleWordAccess;
13473let mayLoad = 1;
13474let cofMax1 = 1;
13475let isRestrictNoSlot1Store = 1;
13476let isReturn = 1;
13477let Uses = [FRAMEKEY];
13478let Defs = [PC, R29];
13479let BaseOpcode = "L4_return";
13480let isBarrier = 1;
13481let isPredicable = 1;
13482let isTaken = 1;
13483}
13484def L4_return_f : HInst<
13485(outs DoubleRegs:$Rdd32),
13486(ins PredRegs:$Pv4, IntRegs:$Rs32),
13487"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13488tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13489let Inst{7-5} = 0b000;
13490let Inst{13-10} = 0b1100;
13491let Inst{31-21} = 0b10010110000;
13492let isPredicated = 1;
13493let isPredicatedFalse = 1;
13494let isTerminator = 1;
13495let isIndirectBranch = 1;
13496let accessSize = DoubleWordAccess;
13497let mayLoad = 1;
13498let cofMax1 = 1;
13499let isRestrictNoSlot1Store = 1;
13500let isReturn = 1;
13501let Uses = [FRAMEKEY];
13502let Defs = [PC, R29];
13503let BaseOpcode = "L4_return";
13504let isTaken = Inst{12};
13505}
13506def L4_return_fnew_pnt : HInst<
13507(outs DoubleRegs:$Rdd32),
13508(ins PredRegs:$Pv4, IntRegs:$Rs32),
13509"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13510tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13511let Inst{7-5} = 0b000;
13512let Inst{13-10} = 0b1010;
13513let Inst{31-21} = 0b10010110000;
13514let isPredicated = 1;
13515let isPredicatedFalse = 1;
13516let isTerminator = 1;
13517let isIndirectBranch = 1;
13518let accessSize = DoubleWordAccess;
13519let isPredicatedNew = 1;
13520let mayLoad = 1;
13521let cofMax1 = 1;
13522let isRestrictNoSlot1Store = 1;
13523let isReturn = 1;
13524let Uses = [FRAMEKEY];
13525let Defs = [PC, R29];
13526let BaseOpcode = "L4_return";
13527let isTaken = Inst{12};
13528}
13529def L4_return_fnew_pt : HInst<
13530(outs DoubleRegs:$Rdd32),
13531(ins PredRegs:$Pv4, IntRegs:$Rs32),
13532"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13533tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13534let Inst{7-5} = 0b000;
13535let Inst{13-10} = 0b1110;
13536let Inst{31-21} = 0b10010110000;
13537let isPredicated = 1;
13538let isPredicatedFalse = 1;
13539let isTerminator = 1;
13540let isIndirectBranch = 1;
13541let accessSize = DoubleWordAccess;
13542let isPredicatedNew = 1;
13543let mayLoad = 1;
13544let cofMax1 = 1;
13545let isRestrictNoSlot1Store = 1;
13546let isReturn = 1;
13547let Uses = [FRAMEKEY];
13548let Defs = [PC, R29];
13549let BaseOpcode = "L4_return";
13550let isTaken = Inst{12};
13551}
13552def L4_return_map_to_raw_f : HInst<
13553(outs),
13554(ins PredRegs:$Pv4),
13555"if (!$Pv4) dealloc_return",
13556tc_df5d53f9, TypeMAPPING>, Requires<[HasV65]> {
13557let isPseudo = 1;
13558let isCodeGenOnly = 1;
13559}
13560def L4_return_map_to_raw_fnew_pnt : HInst<
13561(outs),
13562(ins PredRegs:$Pv4),
13563"if (!$Pv4.new) dealloc_return:nt",
13564tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13565let isPseudo = 1;
13566let isCodeGenOnly = 1;
13567}
13568def L4_return_map_to_raw_fnew_pt : HInst<
13569(outs),
13570(ins PredRegs:$Pv4),
13571"if (!$Pv4.new) dealloc_return:t",
13572tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13573let isPseudo = 1;
13574let isCodeGenOnly = 1;
13575}
13576def L4_return_map_to_raw_t : HInst<
13577(outs),
13578(ins PredRegs:$Pv4),
13579"if ($Pv4) dealloc_return",
13580tc_f38f92e1, TypeMAPPING>, Requires<[HasV65]> {
13581let isPseudo = 1;
13582let isCodeGenOnly = 1;
13583}
13584def L4_return_map_to_raw_tnew_pnt : HInst<
13585(outs),
13586(ins PredRegs:$Pv4),
13587"if ($Pv4.new) dealloc_return:nt",
13588tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13589let isPseudo = 1;
13590let isCodeGenOnly = 1;
13591}
13592def L4_return_map_to_raw_tnew_pt : HInst<
13593(outs),
13594(ins PredRegs:$Pv4),
13595"if ($Pv4.new) dealloc_return:t",
13596tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13597let isPseudo = 1;
13598let isCodeGenOnly = 1;
13599}
13600def L4_return_t : HInst<
13601(outs DoubleRegs:$Rdd32),
13602(ins PredRegs:$Pv4, IntRegs:$Rs32),
13603"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13604tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13605let Inst{7-5} = 0b000;
13606let Inst{13-10} = 0b0100;
13607let Inst{31-21} = 0b10010110000;
13608let isPredicated = 1;
13609let isTerminator = 1;
13610let isIndirectBranch = 1;
13611let accessSize = DoubleWordAccess;
13612let mayLoad = 1;
13613let cofMax1 = 1;
13614let isRestrictNoSlot1Store = 1;
13615let isReturn = 1;
13616let Uses = [FRAMEKEY];
13617let Defs = [PC, R29];
13618let BaseOpcode = "L4_return";
13619let isTaken = Inst{12};
13620}
13621def L4_return_tnew_pnt : HInst<
13622(outs DoubleRegs:$Rdd32),
13623(ins PredRegs:$Pv4, IntRegs:$Rs32),
13624"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13625tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13626let Inst{7-5} = 0b000;
13627let Inst{13-10} = 0b0010;
13628let Inst{31-21} = 0b10010110000;
13629let isPredicated = 1;
13630let isTerminator = 1;
13631let isIndirectBranch = 1;
13632let accessSize = DoubleWordAccess;
13633let isPredicatedNew = 1;
13634let mayLoad = 1;
13635let cofMax1 = 1;
13636let isRestrictNoSlot1Store = 1;
13637let isReturn = 1;
13638let Uses = [FRAMEKEY];
13639let Defs = [PC, R29];
13640let BaseOpcode = "L4_return";
13641let isTaken = Inst{12};
13642}
13643def L4_return_tnew_pt : HInst<
13644(outs DoubleRegs:$Rdd32),
13645(ins PredRegs:$Pv4, IntRegs:$Rs32),
13646"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13647tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13648let Inst{7-5} = 0b000;
13649let Inst{13-10} = 0b0110;
13650let Inst{31-21} = 0b10010110000;
13651let isPredicated = 1;
13652let isTerminator = 1;
13653let isIndirectBranch = 1;
13654let accessSize = DoubleWordAccess;
13655let isPredicatedNew = 1;
13656let mayLoad = 1;
13657let cofMax1 = 1;
13658let isRestrictNoSlot1Store = 1;
13659let isReturn = 1;
13660let Uses = [FRAMEKEY];
13661let Defs = [PC, R29];
13662let BaseOpcode = "L4_return";
13663let isTaken = Inst{12};
13664}
13665def L4_sub_memopb_io : HInst<
13666(outs),
13667(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
13668"memb($Rs32+#$Ii) -= $Rt32",
13669tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
13670let Inst{6-5} = 0b01;
13671let Inst{13-13} = 0b0;
13672let Inst{31-21} = 0b00111110000;
13673let addrMode = BaseImmOffset;
13674let accessSize = ByteAccess;
13675let mayLoad = 1;
13676let isRestrictNoSlot1Store = 1;
13677let mayStore = 1;
13678let isExtendable = 1;
13679let opExtendable = 1;
13680let isExtentSigned = 0;
13681let opExtentBits = 6;
13682let opExtentAlign = 0;
13683}
13684def L4_sub_memopb_zomap : HInst<
13685(outs),
13686(ins IntRegs:$Rs32, IntRegs:$Rt32),
13687"memb($Rs32) -= $Rt32",
13688tc_9bcfb2ee, TypeMAPPING> {
13689let isPseudo = 1;
13690let isCodeGenOnly = 1;
13691}
13692def L4_sub_memoph_io : HInst<
13693(outs),
13694(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
13695"memh($Rs32+#$Ii) -= $Rt32",
13696tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
13697let Inst{6-5} = 0b01;
13698let Inst{13-13} = 0b0;
13699let Inst{31-21} = 0b00111110001;
13700let addrMode = BaseImmOffset;
13701let accessSize = HalfWordAccess;
13702let mayLoad = 1;
13703let isRestrictNoSlot1Store = 1;
13704let mayStore = 1;
13705let isExtendable = 1;
13706let opExtendable = 1;
13707let isExtentSigned = 0;
13708let opExtentBits = 7;
13709let opExtentAlign = 1;
13710}
13711def L4_sub_memoph_zomap : HInst<
13712(outs),
13713(ins IntRegs:$Rs32, IntRegs:$Rt32),
13714"memh($Rs32) -= $Rt32",
13715tc_9bcfb2ee, TypeMAPPING> {
13716let isPseudo = 1;
13717let isCodeGenOnly = 1;
13718}
13719def L4_sub_memopw_io : HInst<
13720(outs),
13721(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
13722"memw($Rs32+#$Ii) -= $Rt32",
13723tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
13724let Inst{6-5} = 0b01;
13725let Inst{13-13} = 0b0;
13726let Inst{31-21} = 0b00111110010;
13727let addrMode = BaseImmOffset;
13728let accessSize = WordAccess;
13729let mayLoad = 1;
13730let isRestrictNoSlot1Store = 1;
13731let mayStore = 1;
13732let isExtendable = 1;
13733let opExtendable = 1;
13734let isExtentSigned = 0;
13735let opExtentBits = 8;
13736let opExtentAlign = 2;
13737}
13738def L4_sub_memopw_zomap : HInst<
13739(outs),
13740(ins IntRegs:$Rs32, IntRegs:$Rt32),
13741"memw($Rs32) -= $Rt32",
13742tc_9bcfb2ee, TypeMAPPING> {
13743let isPseudo = 1;
13744let isCodeGenOnly = 1;
13745}
13746def L6_deallocframe_map_to_raw : HInst<
13747(outs),
13748(ins),
13749"deallocframe",
13750tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> {
13751let isPseudo = 1;
13752let isCodeGenOnly = 1;
13753}
13754def L6_memcpy : HInst<
13755(outs),
13756(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
13757"memcpy($Rs32,$Rt32,$Mu2)",
13758tc_5944960d, TypeLD>, Enc_a75aa6, Requires<[HasV66]> {
13759let Inst{7-0} = 0b01000000;
13760let Inst{31-21} = 0b10010010000;
13761let mayLoad = 1;
13762let isSolo = 1;
13763let mayStore = 1;
13764}
13765def L6_return_map_to_raw : HInst<
13766(outs),
13767(ins),
13768"dealloc_return",
13769tc_40d64c94, TypeMAPPING>, Requires<[HasV65]> {
13770let isPseudo = 1;
13771let isCodeGenOnly = 1;
13772}
13773def M2_acci : HInst<
13774(outs IntRegs:$Rx32),
13775(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13776"$Rx32 += add($Rs32,$Rt32)",
13777tc_2c13e7f5, TypeM>, Enc_2ae154, ImmRegRel {
13778let Inst{7-5} = 0b001;
13779let Inst{13-13} = 0b0;
13780let Inst{31-21} = 0b11101111000;
13781let hasNewValue = 1;
13782let opNewValue = 0;
13783let prefersSlot3 = 1;
13784let CextOpcode = "M2_acci";
13785let InputType = "reg";
13786let Constraints = "$Rx32 = $Rx32in";
13787}
13788def M2_accii : HInst<
13789(outs IntRegs:$Rx32),
13790(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
13791"$Rx32 += add($Rs32,#$Ii)",
13792tc_2c13e7f5, TypeM>, Enc_c90aca, ImmRegRel {
13793let Inst{13-13} = 0b0;
13794let Inst{31-21} = 0b11100010000;
13795let hasNewValue = 1;
13796let opNewValue = 0;
13797let prefersSlot3 = 1;
13798let CextOpcode = "M2_acci";
13799let InputType = "imm";
13800let isExtendable = 1;
13801let opExtendable = 3;
13802let isExtentSigned = 1;
13803let opExtentBits = 8;
13804let opExtentAlign = 0;
13805let Constraints = "$Rx32 = $Rx32in";
13806}
13807def M2_cmaci_s0 : HInst<
13808(outs DoubleRegs:$Rxx32),
13809(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13810"$Rxx32 += cmpyi($Rs32,$Rt32)",
13811tc_7f8ae742, TypeM>, Enc_61f0b0 {
13812let Inst{7-5} = 0b001;
13813let Inst{13-13} = 0b0;
13814let Inst{31-21} = 0b11100111000;
13815let prefersSlot3 = 1;
13816let Constraints = "$Rxx32 = $Rxx32in";
13817}
13818def M2_cmacr_s0 : HInst<
13819(outs DoubleRegs:$Rxx32),
13820(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13821"$Rxx32 += cmpyr($Rs32,$Rt32)",
13822tc_7f8ae742, TypeM>, Enc_61f0b0 {
13823let Inst{7-5} = 0b010;
13824let Inst{13-13} = 0b0;
13825let Inst{31-21} = 0b11100111000;
13826let prefersSlot3 = 1;
13827let Constraints = "$Rxx32 = $Rxx32in";
13828}
13829def M2_cmacs_s0 : HInst<
13830(outs DoubleRegs:$Rxx32),
13831(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13832"$Rxx32 += cmpy($Rs32,$Rt32):sat",
13833tc_7f8ae742, TypeM>, Enc_61f0b0 {
13834let Inst{7-5} = 0b110;
13835let Inst{13-13} = 0b0;
13836let Inst{31-21} = 0b11100111000;
13837let prefersSlot3 = 1;
13838let Defs = [USR_OVF];
13839let Constraints = "$Rxx32 = $Rxx32in";
13840}
13841def M2_cmacs_s1 : HInst<
13842(outs DoubleRegs:$Rxx32),
13843(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13844"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
13845tc_7f8ae742, TypeM>, Enc_61f0b0 {
13846let Inst{7-5} = 0b110;
13847let Inst{13-13} = 0b0;
13848let Inst{31-21} = 0b11100111100;
13849let prefersSlot3 = 1;
13850let Defs = [USR_OVF];
13851let Constraints = "$Rxx32 = $Rxx32in";
13852}
13853def M2_cmacsc_s0 : HInst<
13854(outs DoubleRegs:$Rxx32),
13855(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13856"$Rxx32 += cmpy($Rs32,$Rt32*):sat",
13857tc_7f8ae742, TypeM>, Enc_61f0b0 {
13858let Inst{7-5} = 0b110;
13859let Inst{13-13} = 0b0;
13860let Inst{31-21} = 0b11100111010;
13861let prefersSlot3 = 1;
13862let Defs = [USR_OVF];
13863let Constraints = "$Rxx32 = $Rxx32in";
13864}
13865def M2_cmacsc_s1 : HInst<
13866(outs DoubleRegs:$Rxx32),
13867(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13868"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
13869tc_7f8ae742, TypeM>, Enc_61f0b0 {
13870let Inst{7-5} = 0b110;
13871let Inst{13-13} = 0b0;
13872let Inst{31-21} = 0b11100111110;
13873let prefersSlot3 = 1;
13874let Defs = [USR_OVF];
13875let Constraints = "$Rxx32 = $Rxx32in";
13876}
13877def M2_cmpyi_s0 : HInst<
13878(outs DoubleRegs:$Rdd32),
13879(ins IntRegs:$Rs32, IntRegs:$Rt32),
13880"$Rdd32 = cmpyi($Rs32,$Rt32)",
13881tc_c21d7447, TypeM>, Enc_be32a5 {
13882let Inst{7-5} = 0b001;
13883let Inst{13-13} = 0b0;
13884let Inst{31-21} = 0b11100101000;
13885let prefersSlot3 = 1;
13886}
13887def M2_cmpyr_s0 : HInst<
13888(outs DoubleRegs:$Rdd32),
13889(ins IntRegs:$Rs32, IntRegs:$Rt32),
13890"$Rdd32 = cmpyr($Rs32,$Rt32)",
13891tc_c21d7447, TypeM>, Enc_be32a5 {
13892let Inst{7-5} = 0b010;
13893let Inst{13-13} = 0b0;
13894let Inst{31-21} = 0b11100101000;
13895let prefersSlot3 = 1;
13896}
13897def M2_cmpyrs_s0 : HInst<
13898(outs IntRegs:$Rd32),
13899(ins IntRegs:$Rs32, IntRegs:$Rt32),
13900"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
13901tc_c21d7447, TypeM>, Enc_5ab2be {
13902let Inst{7-5} = 0b110;
13903let Inst{13-13} = 0b0;
13904let Inst{31-21} = 0b11101101001;
13905let hasNewValue = 1;
13906let opNewValue = 0;
13907let prefersSlot3 = 1;
13908let Defs = [USR_OVF];
13909}
13910def M2_cmpyrs_s1 : HInst<
13911(outs IntRegs:$Rd32),
13912(ins IntRegs:$Rs32, IntRegs:$Rt32),
13913"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
13914tc_c21d7447, TypeM>, Enc_5ab2be {
13915let Inst{7-5} = 0b110;
13916let Inst{13-13} = 0b0;
13917let Inst{31-21} = 0b11101101101;
13918let hasNewValue = 1;
13919let opNewValue = 0;
13920let prefersSlot3 = 1;
13921let Defs = [USR_OVF];
13922}
13923def M2_cmpyrsc_s0 : HInst<
13924(outs IntRegs:$Rd32),
13925(ins IntRegs:$Rs32, IntRegs:$Rt32),
13926"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
13927tc_c21d7447, TypeM>, Enc_5ab2be {
13928let Inst{7-5} = 0b110;
13929let Inst{13-13} = 0b0;
13930let Inst{31-21} = 0b11101101011;
13931let hasNewValue = 1;
13932let opNewValue = 0;
13933let prefersSlot3 = 1;
13934let Defs = [USR_OVF];
13935}
13936def M2_cmpyrsc_s1 : HInst<
13937(outs IntRegs:$Rd32),
13938(ins IntRegs:$Rs32, IntRegs:$Rt32),
13939"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
13940tc_c21d7447, TypeM>, Enc_5ab2be {
13941let Inst{7-5} = 0b110;
13942let Inst{13-13} = 0b0;
13943let Inst{31-21} = 0b11101101111;
13944let hasNewValue = 1;
13945let opNewValue = 0;
13946let prefersSlot3 = 1;
13947let Defs = [USR_OVF];
13948}
13949def M2_cmpys_s0 : HInst<
13950(outs DoubleRegs:$Rdd32),
13951(ins IntRegs:$Rs32, IntRegs:$Rt32),
13952"$Rdd32 = cmpy($Rs32,$Rt32):sat",
13953tc_c21d7447, TypeM>, Enc_be32a5 {
13954let Inst{7-5} = 0b110;
13955let Inst{13-13} = 0b0;
13956let Inst{31-21} = 0b11100101000;
13957let prefersSlot3 = 1;
13958let Defs = [USR_OVF];
13959}
13960def M2_cmpys_s1 : HInst<
13961(outs DoubleRegs:$Rdd32),
13962(ins IntRegs:$Rs32, IntRegs:$Rt32),
13963"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
13964tc_c21d7447, TypeM>, Enc_be32a5 {
13965let Inst{7-5} = 0b110;
13966let Inst{13-13} = 0b0;
13967let Inst{31-21} = 0b11100101100;
13968let prefersSlot3 = 1;
13969let Defs = [USR_OVF];
13970}
13971def M2_cmpysc_s0 : HInst<
13972(outs DoubleRegs:$Rdd32),
13973(ins IntRegs:$Rs32, IntRegs:$Rt32),
13974"$Rdd32 = cmpy($Rs32,$Rt32*):sat",
13975tc_c21d7447, TypeM>, Enc_be32a5 {
13976let Inst{7-5} = 0b110;
13977let Inst{13-13} = 0b0;
13978let Inst{31-21} = 0b11100101010;
13979let prefersSlot3 = 1;
13980let Defs = [USR_OVF];
13981}
13982def M2_cmpysc_s1 : HInst<
13983(outs DoubleRegs:$Rdd32),
13984(ins IntRegs:$Rs32, IntRegs:$Rt32),
13985"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
13986tc_c21d7447, TypeM>, Enc_be32a5 {
13987let Inst{7-5} = 0b110;
13988let Inst{13-13} = 0b0;
13989let Inst{31-21} = 0b11100101110;
13990let prefersSlot3 = 1;
13991let Defs = [USR_OVF];
13992}
13993def M2_cnacs_s0 : HInst<
13994(outs DoubleRegs:$Rxx32),
13995(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13996"$Rxx32 -= cmpy($Rs32,$Rt32):sat",
13997tc_7f8ae742, TypeM>, Enc_61f0b0 {
13998let Inst{7-5} = 0b111;
13999let Inst{13-13} = 0b0;
14000let Inst{31-21} = 0b11100111000;
14001let prefersSlot3 = 1;
14002let Defs = [USR_OVF];
14003let Constraints = "$Rxx32 = $Rxx32in";
14004}
14005def M2_cnacs_s1 : HInst<
14006(outs DoubleRegs:$Rxx32),
14007(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14008"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
14009tc_7f8ae742, TypeM>, Enc_61f0b0 {
14010let Inst{7-5} = 0b111;
14011let Inst{13-13} = 0b0;
14012let Inst{31-21} = 0b11100111100;
14013let prefersSlot3 = 1;
14014let Defs = [USR_OVF];
14015let Constraints = "$Rxx32 = $Rxx32in";
14016}
14017def M2_cnacsc_s0 : HInst<
14018(outs DoubleRegs:$Rxx32),
14019(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14020"$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
14021tc_7f8ae742, TypeM>, Enc_61f0b0 {
14022let Inst{7-5} = 0b111;
14023let Inst{13-13} = 0b0;
14024let Inst{31-21} = 0b11100111010;
14025let prefersSlot3 = 1;
14026let Defs = [USR_OVF];
14027let Constraints = "$Rxx32 = $Rxx32in";
14028}
14029def M2_cnacsc_s1 : HInst<
14030(outs DoubleRegs:$Rxx32),
14031(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14032"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
14033tc_7f8ae742, TypeM>, Enc_61f0b0 {
14034let Inst{7-5} = 0b111;
14035let Inst{13-13} = 0b0;
14036let Inst{31-21} = 0b11100111110;
14037let prefersSlot3 = 1;
14038let Defs = [USR_OVF];
14039let Constraints = "$Rxx32 = $Rxx32in";
14040}
14041def M2_dpmpyss_acc_s0 : HInst<
14042(outs DoubleRegs:$Rxx32),
14043(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14044"$Rxx32 += mpy($Rs32,$Rt32)",
14045tc_7f8ae742, TypeM>, Enc_61f0b0 {
14046let Inst{7-5} = 0b000;
14047let Inst{13-13} = 0b0;
14048let Inst{31-21} = 0b11100111000;
14049let prefersSlot3 = 1;
14050let Constraints = "$Rxx32 = $Rxx32in";
14051}
14052def M2_dpmpyss_nac_s0 : HInst<
14053(outs DoubleRegs:$Rxx32),
14054(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14055"$Rxx32 -= mpy($Rs32,$Rt32)",
14056tc_7f8ae742, TypeM>, Enc_61f0b0 {
14057let Inst{7-5} = 0b000;
14058let Inst{13-13} = 0b0;
14059let Inst{31-21} = 0b11100111001;
14060let prefersSlot3 = 1;
14061let Constraints = "$Rxx32 = $Rxx32in";
14062}
14063def M2_dpmpyss_rnd_s0 : HInst<
14064(outs IntRegs:$Rd32),
14065(ins IntRegs:$Rs32, IntRegs:$Rt32),
14066"$Rd32 = mpy($Rs32,$Rt32):rnd",
14067tc_c21d7447, TypeM>, Enc_5ab2be {
14068let Inst{7-5} = 0b001;
14069let Inst{13-13} = 0b0;
14070let Inst{31-21} = 0b11101101001;
14071let hasNewValue = 1;
14072let opNewValue = 0;
14073let prefersSlot3 = 1;
14074}
14075def M2_dpmpyss_s0 : HInst<
14076(outs DoubleRegs:$Rdd32),
14077(ins IntRegs:$Rs32, IntRegs:$Rt32),
14078"$Rdd32 = mpy($Rs32,$Rt32)",
14079tc_c21d7447, TypeM>, Enc_be32a5 {
14080let Inst{7-5} = 0b000;
14081let Inst{13-13} = 0b0;
14082let Inst{31-21} = 0b11100101000;
14083let prefersSlot3 = 1;
14084}
14085def M2_dpmpyuu_acc_s0 : HInst<
14086(outs DoubleRegs:$Rxx32),
14087(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14088"$Rxx32 += mpyu($Rs32,$Rt32)",
14089tc_7f8ae742, TypeM>, Enc_61f0b0 {
14090let Inst{7-5} = 0b000;
14091let Inst{13-13} = 0b0;
14092let Inst{31-21} = 0b11100111010;
14093let prefersSlot3 = 1;
14094let Constraints = "$Rxx32 = $Rxx32in";
14095}
14096def M2_dpmpyuu_nac_s0 : HInst<
14097(outs DoubleRegs:$Rxx32),
14098(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14099"$Rxx32 -= mpyu($Rs32,$Rt32)",
14100tc_7f8ae742, TypeM>, Enc_61f0b0 {
14101let Inst{7-5} = 0b000;
14102let Inst{13-13} = 0b0;
14103let Inst{31-21} = 0b11100111011;
14104let prefersSlot3 = 1;
14105let Constraints = "$Rxx32 = $Rxx32in";
14106}
14107def M2_dpmpyuu_s0 : HInst<
14108(outs DoubleRegs:$Rdd32),
14109(ins IntRegs:$Rs32, IntRegs:$Rt32),
14110"$Rdd32 = mpyu($Rs32,$Rt32)",
14111tc_c21d7447, TypeM>, Enc_be32a5 {
14112let Inst{7-5} = 0b000;
14113let Inst{13-13} = 0b0;
14114let Inst{31-21} = 0b11100101010;
14115let prefersSlot3 = 1;
14116}
14117def M2_hmmpyh_rs1 : HInst<
14118(outs IntRegs:$Rd32),
14119(ins IntRegs:$Rs32, IntRegs:$Rt32),
14120"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
14121tc_c21d7447, TypeM>, Enc_5ab2be {
14122let Inst{7-5} = 0b100;
14123let Inst{13-13} = 0b0;
14124let Inst{31-21} = 0b11101101101;
14125let hasNewValue = 1;
14126let opNewValue = 0;
14127let prefersSlot3 = 1;
14128let Defs = [USR_OVF];
14129}
14130def M2_hmmpyh_s1 : HInst<
14131(outs IntRegs:$Rd32),
14132(ins IntRegs:$Rs32, IntRegs:$Rt32),
14133"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
14134tc_c21d7447, TypeM>, Enc_5ab2be {
14135let Inst{7-5} = 0b000;
14136let Inst{13-13} = 0b0;
14137let Inst{31-21} = 0b11101101101;
14138let hasNewValue = 1;
14139let opNewValue = 0;
14140let prefersSlot3 = 1;
14141let Defs = [USR_OVF];
14142}
14143def M2_hmmpyl_rs1 : HInst<
14144(outs IntRegs:$Rd32),
14145(ins IntRegs:$Rs32, IntRegs:$Rt32),
14146"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
14147tc_c21d7447, TypeM>, Enc_5ab2be {
14148let Inst{7-5} = 0b100;
14149let Inst{13-13} = 0b0;
14150let Inst{31-21} = 0b11101101111;
14151let hasNewValue = 1;
14152let opNewValue = 0;
14153let prefersSlot3 = 1;
14154let Defs = [USR_OVF];
14155}
14156def M2_hmmpyl_s1 : HInst<
14157(outs IntRegs:$Rd32),
14158(ins IntRegs:$Rs32, IntRegs:$Rt32),
14159"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
14160tc_c21d7447, TypeM>, Enc_5ab2be {
14161let Inst{7-5} = 0b001;
14162let Inst{13-13} = 0b0;
14163let Inst{31-21} = 0b11101101101;
14164let hasNewValue = 1;
14165let opNewValue = 0;
14166let prefersSlot3 = 1;
14167let Defs = [USR_OVF];
14168}
14169def M2_maci : HInst<
14170(outs IntRegs:$Rx32),
14171(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14172"$Rx32 += mpyi($Rs32,$Rt32)",
14173tc_7f8ae742, TypeM>, Enc_2ae154, ImmRegRel {
14174let Inst{7-5} = 0b000;
14175let Inst{13-13} = 0b0;
14176let Inst{31-21} = 0b11101111000;
14177let hasNewValue = 1;
14178let opNewValue = 0;
14179let prefersSlot3 = 1;
14180let CextOpcode = "M2_maci";
14181let InputType = "reg";
14182let Constraints = "$Rx32 = $Rx32in";
14183}
14184def M2_macsin : HInst<
14185(outs IntRegs:$Rx32),
14186(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14187"$Rx32 -= mpyi($Rs32,#$Ii)",
14188tc_a154b476, TypeM>, Enc_c90aca {
14189let Inst{13-13} = 0b0;
14190let Inst{31-21} = 0b11100001100;
14191let hasNewValue = 1;
14192let opNewValue = 0;
14193let prefersSlot3 = 1;
14194let InputType = "imm";
14195let isExtendable = 1;
14196let opExtendable = 3;
14197let isExtentSigned = 0;
14198let opExtentBits = 8;
14199let opExtentAlign = 0;
14200let Constraints = "$Rx32 = $Rx32in";
14201}
14202def M2_macsip : HInst<
14203(outs IntRegs:$Rx32),
14204(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14205"$Rx32 += mpyi($Rs32,#$Ii)",
14206tc_a154b476, TypeM>, Enc_c90aca, ImmRegRel {
14207let Inst{13-13} = 0b0;
14208let Inst{31-21} = 0b11100001000;
14209let hasNewValue = 1;
14210let opNewValue = 0;
14211let prefersSlot3 = 1;
14212let CextOpcode = "M2_maci";
14213let InputType = "imm";
14214let isExtendable = 1;
14215let opExtendable = 3;
14216let isExtentSigned = 0;
14217let opExtentBits = 8;
14218let opExtentAlign = 0;
14219let Constraints = "$Rx32 = $Rx32in";
14220}
14221def M2_mmachs_rs0 : HInst<
14222(outs DoubleRegs:$Rxx32),
14223(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14224"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
14225tc_7f8ae742, TypeM>, Enc_88c16c {
14226let Inst{7-5} = 0b111;
14227let Inst{13-13} = 0b0;
14228let Inst{31-21} = 0b11101010001;
14229let prefersSlot3 = 1;
14230let Defs = [USR_OVF];
14231let Constraints = "$Rxx32 = $Rxx32in";
14232}
14233def M2_mmachs_rs1 : HInst<
14234(outs DoubleRegs:$Rxx32),
14235(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14236"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14237tc_7f8ae742, TypeM>, Enc_88c16c {
14238let Inst{7-5} = 0b111;
14239let Inst{13-13} = 0b0;
14240let Inst{31-21} = 0b11101010101;
14241let prefersSlot3 = 1;
14242let Defs = [USR_OVF];
14243let Constraints = "$Rxx32 = $Rxx32in";
14244}
14245def M2_mmachs_s0 : HInst<
14246(outs DoubleRegs:$Rxx32),
14247(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14248"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
14249tc_7f8ae742, TypeM>, Enc_88c16c {
14250let Inst{7-5} = 0b111;
14251let Inst{13-13} = 0b0;
14252let Inst{31-21} = 0b11101010000;
14253let prefersSlot3 = 1;
14254let Defs = [USR_OVF];
14255let Constraints = "$Rxx32 = $Rxx32in";
14256}
14257def M2_mmachs_s1 : HInst<
14258(outs DoubleRegs:$Rxx32),
14259(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14260"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
14261tc_7f8ae742, TypeM>, Enc_88c16c {
14262let Inst{7-5} = 0b111;
14263let Inst{13-13} = 0b0;
14264let Inst{31-21} = 0b11101010100;
14265let prefersSlot3 = 1;
14266let Defs = [USR_OVF];
14267let Constraints = "$Rxx32 = $Rxx32in";
14268}
14269def M2_mmacls_rs0 : HInst<
14270(outs DoubleRegs:$Rxx32),
14271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14272"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
14273tc_7f8ae742, TypeM>, Enc_88c16c {
14274let Inst{7-5} = 0b101;
14275let Inst{13-13} = 0b0;
14276let Inst{31-21} = 0b11101010001;
14277let prefersSlot3 = 1;
14278let Defs = [USR_OVF];
14279let Constraints = "$Rxx32 = $Rxx32in";
14280}
14281def M2_mmacls_rs1 : HInst<
14282(outs DoubleRegs:$Rxx32),
14283(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14284"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14285tc_7f8ae742, TypeM>, Enc_88c16c {
14286let Inst{7-5} = 0b101;
14287let Inst{13-13} = 0b0;
14288let Inst{31-21} = 0b11101010101;
14289let prefersSlot3 = 1;
14290let Defs = [USR_OVF];
14291let Constraints = "$Rxx32 = $Rxx32in";
14292}
14293def M2_mmacls_s0 : HInst<
14294(outs DoubleRegs:$Rxx32),
14295(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14296"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
14297tc_7f8ae742, TypeM>, Enc_88c16c {
14298let Inst{7-5} = 0b101;
14299let Inst{13-13} = 0b0;
14300let Inst{31-21} = 0b11101010000;
14301let prefersSlot3 = 1;
14302let Defs = [USR_OVF];
14303let Constraints = "$Rxx32 = $Rxx32in";
14304}
14305def M2_mmacls_s1 : HInst<
14306(outs DoubleRegs:$Rxx32),
14307(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14308"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
14309tc_7f8ae742, TypeM>, Enc_88c16c {
14310let Inst{7-5} = 0b101;
14311let Inst{13-13} = 0b0;
14312let Inst{31-21} = 0b11101010100;
14313let prefersSlot3 = 1;
14314let Defs = [USR_OVF];
14315let Constraints = "$Rxx32 = $Rxx32in";
14316}
14317def M2_mmacuhs_rs0 : HInst<
14318(outs DoubleRegs:$Rxx32),
14319(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14320"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
14321tc_7f8ae742, TypeM>, Enc_88c16c {
14322let Inst{7-5} = 0b111;
14323let Inst{13-13} = 0b0;
14324let Inst{31-21} = 0b11101010011;
14325let prefersSlot3 = 1;
14326let Defs = [USR_OVF];
14327let Constraints = "$Rxx32 = $Rxx32in";
14328}
14329def M2_mmacuhs_rs1 : HInst<
14330(outs DoubleRegs:$Rxx32),
14331(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14332"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14333tc_7f8ae742, TypeM>, Enc_88c16c {
14334let Inst{7-5} = 0b111;
14335let Inst{13-13} = 0b0;
14336let Inst{31-21} = 0b11101010111;
14337let prefersSlot3 = 1;
14338let Defs = [USR_OVF];
14339let Constraints = "$Rxx32 = $Rxx32in";
14340}
14341def M2_mmacuhs_s0 : HInst<
14342(outs DoubleRegs:$Rxx32),
14343(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14344"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
14345tc_7f8ae742, TypeM>, Enc_88c16c {
14346let Inst{7-5} = 0b111;
14347let Inst{13-13} = 0b0;
14348let Inst{31-21} = 0b11101010010;
14349let prefersSlot3 = 1;
14350let Defs = [USR_OVF];
14351let Constraints = "$Rxx32 = $Rxx32in";
14352}
14353def M2_mmacuhs_s1 : HInst<
14354(outs DoubleRegs:$Rxx32),
14355(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14356"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
14357tc_7f8ae742, TypeM>, Enc_88c16c {
14358let Inst{7-5} = 0b111;
14359let Inst{13-13} = 0b0;
14360let Inst{31-21} = 0b11101010110;
14361let prefersSlot3 = 1;
14362let Defs = [USR_OVF];
14363let Constraints = "$Rxx32 = $Rxx32in";
14364}
14365def M2_mmaculs_rs0 : HInst<
14366(outs DoubleRegs:$Rxx32),
14367(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14368"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
14369tc_7f8ae742, TypeM>, Enc_88c16c {
14370let Inst{7-5} = 0b101;
14371let Inst{13-13} = 0b0;
14372let Inst{31-21} = 0b11101010011;
14373let prefersSlot3 = 1;
14374let Defs = [USR_OVF];
14375let Constraints = "$Rxx32 = $Rxx32in";
14376}
14377def M2_mmaculs_rs1 : HInst<
14378(outs DoubleRegs:$Rxx32),
14379(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14380"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14381tc_7f8ae742, TypeM>, Enc_88c16c {
14382let Inst{7-5} = 0b101;
14383let Inst{13-13} = 0b0;
14384let Inst{31-21} = 0b11101010111;
14385let prefersSlot3 = 1;
14386let Defs = [USR_OVF];
14387let Constraints = "$Rxx32 = $Rxx32in";
14388}
14389def M2_mmaculs_s0 : HInst<
14390(outs DoubleRegs:$Rxx32),
14391(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14392"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
14393tc_7f8ae742, TypeM>, Enc_88c16c {
14394let Inst{7-5} = 0b101;
14395let Inst{13-13} = 0b0;
14396let Inst{31-21} = 0b11101010010;
14397let prefersSlot3 = 1;
14398let Defs = [USR_OVF];
14399let Constraints = "$Rxx32 = $Rxx32in";
14400}
14401def M2_mmaculs_s1 : HInst<
14402(outs DoubleRegs:$Rxx32),
14403(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14404"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
14405tc_7f8ae742, TypeM>, Enc_88c16c {
14406let Inst{7-5} = 0b101;
14407let Inst{13-13} = 0b0;
14408let Inst{31-21} = 0b11101010110;
14409let prefersSlot3 = 1;
14410let Defs = [USR_OVF];
14411let Constraints = "$Rxx32 = $Rxx32in";
14412}
14413def M2_mmpyh_rs0 : HInst<
14414(outs DoubleRegs:$Rdd32),
14415(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14416"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
14417tc_c21d7447, TypeM>, Enc_a56825 {
14418let Inst{7-5} = 0b111;
14419let Inst{13-13} = 0b0;
14420let Inst{31-21} = 0b11101000001;
14421let prefersSlot3 = 1;
14422let Defs = [USR_OVF];
14423}
14424def M2_mmpyh_rs1 : HInst<
14425(outs DoubleRegs:$Rdd32),
14426(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14427"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14428tc_c21d7447, TypeM>, Enc_a56825 {
14429let Inst{7-5} = 0b111;
14430let Inst{13-13} = 0b0;
14431let Inst{31-21} = 0b11101000101;
14432let prefersSlot3 = 1;
14433let Defs = [USR_OVF];
14434}
14435def M2_mmpyh_s0 : HInst<
14436(outs DoubleRegs:$Rdd32),
14437(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14438"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
14439tc_c21d7447, TypeM>, Enc_a56825 {
14440let Inst{7-5} = 0b111;
14441let Inst{13-13} = 0b0;
14442let Inst{31-21} = 0b11101000000;
14443let prefersSlot3 = 1;
14444let Defs = [USR_OVF];
14445}
14446def M2_mmpyh_s1 : HInst<
14447(outs DoubleRegs:$Rdd32),
14448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14449"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
14450tc_c21d7447, TypeM>, Enc_a56825 {
14451let Inst{7-5} = 0b111;
14452let Inst{13-13} = 0b0;
14453let Inst{31-21} = 0b11101000100;
14454let prefersSlot3 = 1;
14455let Defs = [USR_OVF];
14456}
14457def M2_mmpyl_rs0 : HInst<
14458(outs DoubleRegs:$Rdd32),
14459(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14460"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
14461tc_c21d7447, TypeM>, Enc_a56825 {
14462let Inst{7-5} = 0b101;
14463let Inst{13-13} = 0b0;
14464let Inst{31-21} = 0b11101000001;
14465let prefersSlot3 = 1;
14466let Defs = [USR_OVF];
14467}
14468def M2_mmpyl_rs1 : HInst<
14469(outs DoubleRegs:$Rdd32),
14470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14471"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14472tc_c21d7447, TypeM>, Enc_a56825 {
14473let Inst{7-5} = 0b101;
14474let Inst{13-13} = 0b0;
14475let Inst{31-21} = 0b11101000101;
14476let prefersSlot3 = 1;
14477let Defs = [USR_OVF];
14478}
14479def M2_mmpyl_s0 : HInst<
14480(outs DoubleRegs:$Rdd32),
14481(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14482"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
14483tc_c21d7447, TypeM>, Enc_a56825 {
14484let Inst{7-5} = 0b101;
14485let Inst{13-13} = 0b0;
14486let Inst{31-21} = 0b11101000000;
14487let prefersSlot3 = 1;
14488let Defs = [USR_OVF];
14489}
14490def M2_mmpyl_s1 : HInst<
14491(outs DoubleRegs:$Rdd32),
14492(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14493"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
14494tc_c21d7447, TypeM>, Enc_a56825 {
14495let Inst{7-5} = 0b101;
14496let Inst{13-13} = 0b0;
14497let Inst{31-21} = 0b11101000100;
14498let prefersSlot3 = 1;
14499let Defs = [USR_OVF];
14500}
14501def M2_mmpyuh_rs0 : HInst<
14502(outs DoubleRegs:$Rdd32),
14503(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14504"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
14505tc_c21d7447, TypeM>, Enc_a56825 {
14506let Inst{7-5} = 0b111;
14507let Inst{13-13} = 0b0;
14508let Inst{31-21} = 0b11101000011;
14509let prefersSlot3 = 1;
14510let Defs = [USR_OVF];
14511}
14512def M2_mmpyuh_rs1 : HInst<
14513(outs DoubleRegs:$Rdd32),
14514(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14515"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14516tc_c21d7447, TypeM>, Enc_a56825 {
14517let Inst{7-5} = 0b111;
14518let Inst{13-13} = 0b0;
14519let Inst{31-21} = 0b11101000111;
14520let prefersSlot3 = 1;
14521let Defs = [USR_OVF];
14522}
14523def M2_mmpyuh_s0 : HInst<
14524(outs DoubleRegs:$Rdd32),
14525(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14526"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
14527tc_c21d7447, TypeM>, Enc_a56825 {
14528let Inst{7-5} = 0b111;
14529let Inst{13-13} = 0b0;
14530let Inst{31-21} = 0b11101000010;
14531let prefersSlot3 = 1;
14532let Defs = [USR_OVF];
14533}
14534def M2_mmpyuh_s1 : HInst<
14535(outs DoubleRegs:$Rdd32),
14536(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14537"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
14538tc_c21d7447, TypeM>, Enc_a56825 {
14539let Inst{7-5} = 0b111;
14540let Inst{13-13} = 0b0;
14541let Inst{31-21} = 0b11101000110;
14542let prefersSlot3 = 1;
14543let Defs = [USR_OVF];
14544}
14545def M2_mmpyul_rs0 : HInst<
14546(outs DoubleRegs:$Rdd32),
14547(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14548"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
14549tc_c21d7447, TypeM>, Enc_a56825 {
14550let Inst{7-5} = 0b101;
14551let Inst{13-13} = 0b0;
14552let Inst{31-21} = 0b11101000011;
14553let prefersSlot3 = 1;
14554let Defs = [USR_OVF];
14555}
14556def M2_mmpyul_rs1 : HInst<
14557(outs DoubleRegs:$Rdd32),
14558(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14559"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14560tc_c21d7447, TypeM>, Enc_a56825 {
14561let Inst{7-5} = 0b101;
14562let Inst{13-13} = 0b0;
14563let Inst{31-21} = 0b11101000111;
14564let prefersSlot3 = 1;
14565let Defs = [USR_OVF];
14566}
14567def M2_mmpyul_s0 : HInst<
14568(outs DoubleRegs:$Rdd32),
14569(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14570"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
14571tc_c21d7447, TypeM>, Enc_a56825 {
14572let Inst{7-5} = 0b101;
14573let Inst{13-13} = 0b0;
14574let Inst{31-21} = 0b11101000010;
14575let prefersSlot3 = 1;
14576let Defs = [USR_OVF];
14577}
14578def M2_mmpyul_s1 : HInst<
14579(outs DoubleRegs:$Rdd32),
14580(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14581"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
14582tc_c21d7447, TypeM>, Enc_a56825 {
14583let Inst{7-5} = 0b101;
14584let Inst{13-13} = 0b0;
14585let Inst{31-21} = 0b11101000110;
14586let prefersSlot3 = 1;
14587let Defs = [USR_OVF];
14588}
14589def M2_mnaci : HInst<
14590(outs IntRegs:$Rx32),
14591(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14592"$Rx32 -= mpyi($Rs32,$Rt32)",
14593tc_01e1be3b, TypeM>, Enc_2ae154, Requires<[HasV66]> {
14594let Inst{7-5} = 0b000;
14595let Inst{13-13} = 0b0;
14596let Inst{31-21} = 0b11101111100;
14597let hasNewValue = 1;
14598let opNewValue = 0;
14599let prefersSlot3 = 1;
14600let Constraints = "$Rx32 = $Rx32in";
14601}
14602def M2_mpy_acc_hh_s0 : HInst<
14603(outs IntRegs:$Rx32),
14604(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14605"$Rx32 += mpy($Rs32.h,$Rt32.h)",
14606tc_7f8ae742, TypeM>, Enc_2ae154 {
14607let Inst{7-5} = 0b011;
14608let Inst{13-13} = 0b0;
14609let Inst{31-21} = 0b11101110000;
14610let hasNewValue = 1;
14611let opNewValue = 0;
14612let prefersSlot3 = 1;
14613let Constraints = "$Rx32 = $Rx32in";
14614}
14615def M2_mpy_acc_hh_s1 : HInst<
14616(outs IntRegs:$Rx32),
14617(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14618"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
14619tc_7f8ae742, TypeM>, Enc_2ae154 {
14620let Inst{7-5} = 0b011;
14621let Inst{13-13} = 0b0;
14622let Inst{31-21} = 0b11101110100;
14623let hasNewValue = 1;
14624let opNewValue = 0;
14625let prefersSlot3 = 1;
14626let Constraints = "$Rx32 = $Rx32in";
14627}
14628def M2_mpy_acc_hl_s0 : HInst<
14629(outs IntRegs:$Rx32),
14630(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14631"$Rx32 += mpy($Rs32.h,$Rt32.l)",
14632tc_7f8ae742, TypeM>, Enc_2ae154 {
14633let Inst{7-5} = 0b010;
14634let Inst{13-13} = 0b0;
14635let Inst{31-21} = 0b11101110000;
14636let hasNewValue = 1;
14637let opNewValue = 0;
14638let prefersSlot3 = 1;
14639let Constraints = "$Rx32 = $Rx32in";
14640}
14641def M2_mpy_acc_hl_s1 : HInst<
14642(outs IntRegs:$Rx32),
14643(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14644"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
14645tc_7f8ae742, TypeM>, Enc_2ae154 {
14646let Inst{7-5} = 0b010;
14647let Inst{13-13} = 0b0;
14648let Inst{31-21} = 0b11101110100;
14649let hasNewValue = 1;
14650let opNewValue = 0;
14651let prefersSlot3 = 1;
14652let Constraints = "$Rx32 = $Rx32in";
14653}
14654def M2_mpy_acc_lh_s0 : HInst<
14655(outs IntRegs:$Rx32),
14656(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14657"$Rx32 += mpy($Rs32.l,$Rt32.h)",
14658tc_7f8ae742, TypeM>, Enc_2ae154 {
14659let Inst{7-5} = 0b001;
14660let Inst{13-13} = 0b0;
14661let Inst{31-21} = 0b11101110000;
14662let hasNewValue = 1;
14663let opNewValue = 0;
14664let prefersSlot3 = 1;
14665let Constraints = "$Rx32 = $Rx32in";
14666}
14667def M2_mpy_acc_lh_s1 : HInst<
14668(outs IntRegs:$Rx32),
14669(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14670"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
14671tc_7f8ae742, TypeM>, Enc_2ae154 {
14672let Inst{7-5} = 0b001;
14673let Inst{13-13} = 0b0;
14674let Inst{31-21} = 0b11101110100;
14675let hasNewValue = 1;
14676let opNewValue = 0;
14677let prefersSlot3 = 1;
14678let Constraints = "$Rx32 = $Rx32in";
14679}
14680def M2_mpy_acc_ll_s0 : HInst<
14681(outs IntRegs:$Rx32),
14682(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14683"$Rx32 += mpy($Rs32.l,$Rt32.l)",
14684tc_7f8ae742, TypeM>, Enc_2ae154 {
14685let Inst{7-5} = 0b000;
14686let Inst{13-13} = 0b0;
14687let Inst{31-21} = 0b11101110000;
14688let hasNewValue = 1;
14689let opNewValue = 0;
14690let prefersSlot3 = 1;
14691let Constraints = "$Rx32 = $Rx32in";
14692}
14693def M2_mpy_acc_ll_s1 : HInst<
14694(outs IntRegs:$Rx32),
14695(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14696"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
14697tc_7f8ae742, TypeM>, Enc_2ae154 {
14698let Inst{7-5} = 0b000;
14699let Inst{13-13} = 0b0;
14700let Inst{31-21} = 0b11101110100;
14701let hasNewValue = 1;
14702let opNewValue = 0;
14703let prefersSlot3 = 1;
14704let Constraints = "$Rx32 = $Rx32in";
14705}
14706def M2_mpy_acc_sat_hh_s0 : HInst<
14707(outs IntRegs:$Rx32),
14708(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14709"$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
14710tc_7f8ae742, TypeM>, Enc_2ae154 {
14711let Inst{7-5} = 0b111;
14712let Inst{13-13} = 0b0;
14713let Inst{31-21} = 0b11101110000;
14714let hasNewValue = 1;
14715let opNewValue = 0;
14716let prefersSlot3 = 1;
14717let Defs = [USR_OVF];
14718let Constraints = "$Rx32 = $Rx32in";
14719}
14720def M2_mpy_acc_sat_hh_s1 : HInst<
14721(outs IntRegs:$Rx32),
14722(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14723"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
14724tc_7f8ae742, TypeM>, Enc_2ae154 {
14725let Inst{7-5} = 0b111;
14726let Inst{13-13} = 0b0;
14727let Inst{31-21} = 0b11101110100;
14728let hasNewValue = 1;
14729let opNewValue = 0;
14730let prefersSlot3 = 1;
14731let Defs = [USR_OVF];
14732let Constraints = "$Rx32 = $Rx32in";
14733}
14734def M2_mpy_acc_sat_hl_s0 : HInst<
14735(outs IntRegs:$Rx32),
14736(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14737"$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
14738tc_7f8ae742, TypeM>, Enc_2ae154 {
14739let Inst{7-5} = 0b110;
14740let Inst{13-13} = 0b0;
14741let Inst{31-21} = 0b11101110000;
14742let hasNewValue = 1;
14743let opNewValue = 0;
14744let prefersSlot3 = 1;
14745let Defs = [USR_OVF];
14746let Constraints = "$Rx32 = $Rx32in";
14747}
14748def M2_mpy_acc_sat_hl_s1 : HInst<
14749(outs IntRegs:$Rx32),
14750(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14751"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
14752tc_7f8ae742, TypeM>, Enc_2ae154 {
14753let Inst{7-5} = 0b110;
14754let Inst{13-13} = 0b0;
14755let Inst{31-21} = 0b11101110100;
14756let hasNewValue = 1;
14757let opNewValue = 0;
14758let prefersSlot3 = 1;
14759let Defs = [USR_OVF];
14760let Constraints = "$Rx32 = $Rx32in";
14761}
14762def M2_mpy_acc_sat_lh_s0 : HInst<
14763(outs IntRegs:$Rx32),
14764(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14765"$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
14766tc_7f8ae742, TypeM>, Enc_2ae154 {
14767let Inst{7-5} = 0b101;
14768let Inst{13-13} = 0b0;
14769let Inst{31-21} = 0b11101110000;
14770let hasNewValue = 1;
14771let opNewValue = 0;
14772let prefersSlot3 = 1;
14773let Defs = [USR_OVF];
14774let Constraints = "$Rx32 = $Rx32in";
14775}
14776def M2_mpy_acc_sat_lh_s1 : HInst<
14777(outs IntRegs:$Rx32),
14778(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14779"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
14780tc_7f8ae742, TypeM>, Enc_2ae154 {
14781let Inst{7-5} = 0b101;
14782let Inst{13-13} = 0b0;
14783let Inst{31-21} = 0b11101110100;
14784let hasNewValue = 1;
14785let opNewValue = 0;
14786let prefersSlot3 = 1;
14787let Defs = [USR_OVF];
14788let Constraints = "$Rx32 = $Rx32in";
14789}
14790def M2_mpy_acc_sat_ll_s0 : HInst<
14791(outs IntRegs:$Rx32),
14792(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14793"$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
14794tc_7f8ae742, TypeM>, Enc_2ae154 {
14795let Inst{7-5} = 0b100;
14796let Inst{13-13} = 0b0;
14797let Inst{31-21} = 0b11101110000;
14798let hasNewValue = 1;
14799let opNewValue = 0;
14800let prefersSlot3 = 1;
14801let Defs = [USR_OVF];
14802let Constraints = "$Rx32 = $Rx32in";
14803}
14804def M2_mpy_acc_sat_ll_s1 : HInst<
14805(outs IntRegs:$Rx32),
14806(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14807"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
14808tc_7f8ae742, TypeM>, Enc_2ae154 {
14809let Inst{7-5} = 0b100;
14810let Inst{13-13} = 0b0;
14811let Inst{31-21} = 0b11101110100;
14812let hasNewValue = 1;
14813let opNewValue = 0;
14814let prefersSlot3 = 1;
14815let Defs = [USR_OVF];
14816let Constraints = "$Rx32 = $Rx32in";
14817}
14818def M2_mpy_hh_s0 : HInst<
14819(outs IntRegs:$Rd32),
14820(ins IntRegs:$Rs32, IntRegs:$Rt32),
14821"$Rd32 = mpy($Rs32.h,$Rt32.h)",
14822tc_c21d7447, TypeM>, Enc_5ab2be {
14823let Inst{7-5} = 0b011;
14824let Inst{13-13} = 0b0;
14825let Inst{31-21} = 0b11101100000;
14826let hasNewValue = 1;
14827let opNewValue = 0;
14828let prefersSlot3 = 1;
14829}
14830def M2_mpy_hh_s1 : HInst<
14831(outs IntRegs:$Rd32),
14832(ins IntRegs:$Rs32, IntRegs:$Rt32),
14833"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
14834tc_c21d7447, TypeM>, Enc_5ab2be {
14835let Inst{7-5} = 0b011;
14836let Inst{13-13} = 0b0;
14837let Inst{31-21} = 0b11101100100;
14838let hasNewValue = 1;
14839let opNewValue = 0;
14840let prefersSlot3 = 1;
14841}
14842def M2_mpy_hl_s0 : HInst<
14843(outs IntRegs:$Rd32),
14844(ins IntRegs:$Rs32, IntRegs:$Rt32),
14845"$Rd32 = mpy($Rs32.h,$Rt32.l)",
14846tc_c21d7447, TypeM>, Enc_5ab2be {
14847let Inst{7-5} = 0b010;
14848let Inst{13-13} = 0b0;
14849let Inst{31-21} = 0b11101100000;
14850let hasNewValue = 1;
14851let opNewValue = 0;
14852let prefersSlot3 = 1;
14853}
14854def M2_mpy_hl_s1 : HInst<
14855(outs IntRegs:$Rd32),
14856(ins IntRegs:$Rs32, IntRegs:$Rt32),
14857"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
14858tc_c21d7447, TypeM>, Enc_5ab2be {
14859let Inst{7-5} = 0b010;
14860let Inst{13-13} = 0b0;
14861let Inst{31-21} = 0b11101100100;
14862let hasNewValue = 1;
14863let opNewValue = 0;
14864let prefersSlot3 = 1;
14865}
14866def M2_mpy_lh_s0 : HInst<
14867(outs IntRegs:$Rd32),
14868(ins IntRegs:$Rs32, IntRegs:$Rt32),
14869"$Rd32 = mpy($Rs32.l,$Rt32.h)",
14870tc_c21d7447, TypeM>, Enc_5ab2be {
14871let Inst{7-5} = 0b001;
14872let Inst{13-13} = 0b0;
14873let Inst{31-21} = 0b11101100000;
14874let hasNewValue = 1;
14875let opNewValue = 0;
14876let prefersSlot3 = 1;
14877}
14878def M2_mpy_lh_s1 : HInst<
14879(outs IntRegs:$Rd32),
14880(ins IntRegs:$Rs32, IntRegs:$Rt32),
14881"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
14882tc_c21d7447, TypeM>, Enc_5ab2be {
14883let Inst{7-5} = 0b001;
14884let Inst{13-13} = 0b0;
14885let Inst{31-21} = 0b11101100100;
14886let hasNewValue = 1;
14887let opNewValue = 0;
14888let prefersSlot3 = 1;
14889}
14890def M2_mpy_ll_s0 : HInst<
14891(outs IntRegs:$Rd32),
14892(ins IntRegs:$Rs32, IntRegs:$Rt32),
14893"$Rd32 = mpy($Rs32.l,$Rt32.l)",
14894tc_c21d7447, TypeM>, Enc_5ab2be {
14895let Inst{7-5} = 0b000;
14896let Inst{13-13} = 0b0;
14897let Inst{31-21} = 0b11101100000;
14898let hasNewValue = 1;
14899let opNewValue = 0;
14900let prefersSlot3 = 1;
14901}
14902def M2_mpy_ll_s1 : HInst<
14903(outs IntRegs:$Rd32),
14904(ins IntRegs:$Rs32, IntRegs:$Rt32),
14905"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
14906tc_c21d7447, TypeM>, Enc_5ab2be {
14907let Inst{7-5} = 0b000;
14908let Inst{13-13} = 0b0;
14909let Inst{31-21} = 0b11101100100;
14910let hasNewValue = 1;
14911let opNewValue = 0;
14912let prefersSlot3 = 1;
14913}
14914def M2_mpy_nac_hh_s0 : HInst<
14915(outs IntRegs:$Rx32),
14916(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14917"$Rx32 -= mpy($Rs32.h,$Rt32.h)",
14918tc_7f8ae742, TypeM>, Enc_2ae154 {
14919let Inst{7-5} = 0b011;
14920let Inst{13-13} = 0b0;
14921let Inst{31-21} = 0b11101110001;
14922let hasNewValue = 1;
14923let opNewValue = 0;
14924let prefersSlot3 = 1;
14925let Constraints = "$Rx32 = $Rx32in";
14926}
14927def M2_mpy_nac_hh_s1 : HInst<
14928(outs IntRegs:$Rx32),
14929(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14930"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
14931tc_7f8ae742, TypeM>, Enc_2ae154 {
14932let Inst{7-5} = 0b011;
14933let Inst{13-13} = 0b0;
14934let Inst{31-21} = 0b11101110101;
14935let hasNewValue = 1;
14936let opNewValue = 0;
14937let prefersSlot3 = 1;
14938let Constraints = "$Rx32 = $Rx32in";
14939}
14940def M2_mpy_nac_hl_s0 : HInst<
14941(outs IntRegs:$Rx32),
14942(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14943"$Rx32 -= mpy($Rs32.h,$Rt32.l)",
14944tc_7f8ae742, TypeM>, Enc_2ae154 {
14945let Inst{7-5} = 0b010;
14946let Inst{13-13} = 0b0;
14947let Inst{31-21} = 0b11101110001;
14948let hasNewValue = 1;
14949let opNewValue = 0;
14950let prefersSlot3 = 1;
14951let Constraints = "$Rx32 = $Rx32in";
14952}
14953def M2_mpy_nac_hl_s1 : HInst<
14954(outs IntRegs:$Rx32),
14955(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14956"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
14957tc_7f8ae742, TypeM>, Enc_2ae154 {
14958let Inst{7-5} = 0b010;
14959let Inst{13-13} = 0b0;
14960let Inst{31-21} = 0b11101110101;
14961let hasNewValue = 1;
14962let opNewValue = 0;
14963let prefersSlot3 = 1;
14964let Constraints = "$Rx32 = $Rx32in";
14965}
14966def M2_mpy_nac_lh_s0 : HInst<
14967(outs IntRegs:$Rx32),
14968(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14969"$Rx32 -= mpy($Rs32.l,$Rt32.h)",
14970tc_7f8ae742, TypeM>, Enc_2ae154 {
14971let Inst{7-5} = 0b001;
14972let Inst{13-13} = 0b0;
14973let Inst{31-21} = 0b11101110001;
14974let hasNewValue = 1;
14975let opNewValue = 0;
14976let prefersSlot3 = 1;
14977let Constraints = "$Rx32 = $Rx32in";
14978}
14979def M2_mpy_nac_lh_s1 : HInst<
14980(outs IntRegs:$Rx32),
14981(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14982"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
14983tc_7f8ae742, TypeM>, Enc_2ae154 {
14984let Inst{7-5} = 0b001;
14985let Inst{13-13} = 0b0;
14986let Inst{31-21} = 0b11101110101;
14987let hasNewValue = 1;
14988let opNewValue = 0;
14989let prefersSlot3 = 1;
14990let Constraints = "$Rx32 = $Rx32in";
14991}
14992def M2_mpy_nac_ll_s0 : HInst<
14993(outs IntRegs:$Rx32),
14994(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14995"$Rx32 -= mpy($Rs32.l,$Rt32.l)",
14996tc_7f8ae742, TypeM>, Enc_2ae154 {
14997let Inst{7-5} = 0b000;
14998let Inst{13-13} = 0b0;
14999let Inst{31-21} = 0b11101110001;
15000let hasNewValue = 1;
15001let opNewValue = 0;
15002let prefersSlot3 = 1;
15003let Constraints = "$Rx32 = $Rx32in";
15004}
15005def M2_mpy_nac_ll_s1 : HInst<
15006(outs IntRegs:$Rx32),
15007(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15008"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15009tc_7f8ae742, TypeM>, Enc_2ae154 {
15010let Inst{7-5} = 0b000;
15011let Inst{13-13} = 0b0;
15012let Inst{31-21} = 0b11101110101;
15013let hasNewValue = 1;
15014let opNewValue = 0;
15015let prefersSlot3 = 1;
15016let Constraints = "$Rx32 = $Rx32in";
15017}
15018def M2_mpy_nac_sat_hh_s0 : HInst<
15019(outs IntRegs:$Rx32),
15020(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15021"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
15022tc_7f8ae742, TypeM>, Enc_2ae154 {
15023let Inst{7-5} = 0b111;
15024let Inst{13-13} = 0b0;
15025let Inst{31-21} = 0b11101110001;
15026let hasNewValue = 1;
15027let opNewValue = 0;
15028let prefersSlot3 = 1;
15029let Defs = [USR_OVF];
15030let Constraints = "$Rx32 = $Rx32in";
15031}
15032def M2_mpy_nac_sat_hh_s1 : HInst<
15033(outs IntRegs:$Rx32),
15034(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15035"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
15036tc_7f8ae742, TypeM>, Enc_2ae154 {
15037let Inst{7-5} = 0b111;
15038let Inst{13-13} = 0b0;
15039let Inst{31-21} = 0b11101110101;
15040let hasNewValue = 1;
15041let opNewValue = 0;
15042let prefersSlot3 = 1;
15043let Defs = [USR_OVF];
15044let Constraints = "$Rx32 = $Rx32in";
15045}
15046def M2_mpy_nac_sat_hl_s0 : HInst<
15047(outs IntRegs:$Rx32),
15048(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15049"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
15050tc_7f8ae742, TypeM>, Enc_2ae154 {
15051let Inst{7-5} = 0b110;
15052let Inst{13-13} = 0b0;
15053let Inst{31-21} = 0b11101110001;
15054let hasNewValue = 1;
15055let opNewValue = 0;
15056let prefersSlot3 = 1;
15057let Defs = [USR_OVF];
15058let Constraints = "$Rx32 = $Rx32in";
15059}
15060def M2_mpy_nac_sat_hl_s1 : HInst<
15061(outs IntRegs:$Rx32),
15062(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15063"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
15064tc_7f8ae742, TypeM>, Enc_2ae154 {
15065let Inst{7-5} = 0b110;
15066let Inst{13-13} = 0b0;
15067let Inst{31-21} = 0b11101110101;
15068let hasNewValue = 1;
15069let opNewValue = 0;
15070let prefersSlot3 = 1;
15071let Defs = [USR_OVF];
15072let Constraints = "$Rx32 = $Rx32in";
15073}
15074def M2_mpy_nac_sat_lh_s0 : HInst<
15075(outs IntRegs:$Rx32),
15076(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15077"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
15078tc_7f8ae742, TypeM>, Enc_2ae154 {
15079let Inst{7-5} = 0b101;
15080let Inst{13-13} = 0b0;
15081let Inst{31-21} = 0b11101110001;
15082let hasNewValue = 1;
15083let opNewValue = 0;
15084let prefersSlot3 = 1;
15085let Defs = [USR_OVF];
15086let Constraints = "$Rx32 = $Rx32in";
15087}
15088def M2_mpy_nac_sat_lh_s1 : HInst<
15089(outs IntRegs:$Rx32),
15090(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15091"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
15092tc_7f8ae742, TypeM>, Enc_2ae154 {
15093let Inst{7-5} = 0b101;
15094let Inst{13-13} = 0b0;
15095let Inst{31-21} = 0b11101110101;
15096let hasNewValue = 1;
15097let opNewValue = 0;
15098let prefersSlot3 = 1;
15099let Defs = [USR_OVF];
15100let Constraints = "$Rx32 = $Rx32in";
15101}
15102def M2_mpy_nac_sat_ll_s0 : HInst<
15103(outs IntRegs:$Rx32),
15104(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15105"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
15106tc_7f8ae742, TypeM>, Enc_2ae154 {
15107let Inst{7-5} = 0b100;
15108let Inst{13-13} = 0b0;
15109let Inst{31-21} = 0b11101110001;
15110let hasNewValue = 1;
15111let opNewValue = 0;
15112let prefersSlot3 = 1;
15113let Defs = [USR_OVF];
15114let Constraints = "$Rx32 = $Rx32in";
15115}
15116def M2_mpy_nac_sat_ll_s1 : HInst<
15117(outs IntRegs:$Rx32),
15118(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15119"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
15120tc_7f8ae742, TypeM>, Enc_2ae154 {
15121let Inst{7-5} = 0b100;
15122let Inst{13-13} = 0b0;
15123let Inst{31-21} = 0b11101110101;
15124let hasNewValue = 1;
15125let opNewValue = 0;
15126let prefersSlot3 = 1;
15127let Defs = [USR_OVF];
15128let Constraints = "$Rx32 = $Rx32in";
15129}
15130def M2_mpy_rnd_hh_s0 : HInst<
15131(outs IntRegs:$Rd32),
15132(ins IntRegs:$Rs32, IntRegs:$Rt32),
15133"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
15134tc_c21d7447, TypeM>, Enc_5ab2be {
15135let Inst{7-5} = 0b011;
15136let Inst{13-13} = 0b0;
15137let Inst{31-21} = 0b11101100001;
15138let hasNewValue = 1;
15139let opNewValue = 0;
15140let prefersSlot3 = 1;
15141}
15142def M2_mpy_rnd_hh_s1 : HInst<
15143(outs IntRegs:$Rd32),
15144(ins IntRegs:$Rs32, IntRegs:$Rt32),
15145"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15146tc_c21d7447, TypeM>, Enc_5ab2be {
15147let Inst{7-5} = 0b011;
15148let Inst{13-13} = 0b0;
15149let Inst{31-21} = 0b11101100101;
15150let hasNewValue = 1;
15151let opNewValue = 0;
15152let prefersSlot3 = 1;
15153}
15154def M2_mpy_rnd_hl_s0 : HInst<
15155(outs IntRegs:$Rd32),
15156(ins IntRegs:$Rs32, IntRegs:$Rt32),
15157"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
15158tc_c21d7447, TypeM>, Enc_5ab2be {
15159let Inst{7-5} = 0b010;
15160let Inst{13-13} = 0b0;
15161let Inst{31-21} = 0b11101100001;
15162let hasNewValue = 1;
15163let opNewValue = 0;
15164let prefersSlot3 = 1;
15165}
15166def M2_mpy_rnd_hl_s1 : HInst<
15167(outs IntRegs:$Rd32),
15168(ins IntRegs:$Rs32, IntRegs:$Rt32),
15169"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15170tc_c21d7447, TypeM>, Enc_5ab2be {
15171let Inst{7-5} = 0b010;
15172let Inst{13-13} = 0b0;
15173let Inst{31-21} = 0b11101100101;
15174let hasNewValue = 1;
15175let opNewValue = 0;
15176let prefersSlot3 = 1;
15177}
15178def M2_mpy_rnd_lh_s0 : HInst<
15179(outs IntRegs:$Rd32),
15180(ins IntRegs:$Rs32, IntRegs:$Rt32),
15181"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
15182tc_c21d7447, TypeM>, Enc_5ab2be {
15183let Inst{7-5} = 0b001;
15184let Inst{13-13} = 0b0;
15185let Inst{31-21} = 0b11101100001;
15186let hasNewValue = 1;
15187let opNewValue = 0;
15188let prefersSlot3 = 1;
15189}
15190def M2_mpy_rnd_lh_s1 : HInst<
15191(outs IntRegs:$Rd32),
15192(ins IntRegs:$Rs32, IntRegs:$Rt32),
15193"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15194tc_c21d7447, TypeM>, Enc_5ab2be {
15195let Inst{7-5} = 0b001;
15196let Inst{13-13} = 0b0;
15197let Inst{31-21} = 0b11101100101;
15198let hasNewValue = 1;
15199let opNewValue = 0;
15200let prefersSlot3 = 1;
15201}
15202def M2_mpy_rnd_ll_s0 : HInst<
15203(outs IntRegs:$Rd32),
15204(ins IntRegs:$Rs32, IntRegs:$Rt32),
15205"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
15206tc_c21d7447, TypeM>, Enc_5ab2be {
15207let Inst{7-5} = 0b000;
15208let Inst{13-13} = 0b0;
15209let Inst{31-21} = 0b11101100001;
15210let hasNewValue = 1;
15211let opNewValue = 0;
15212let prefersSlot3 = 1;
15213}
15214def M2_mpy_rnd_ll_s1 : HInst<
15215(outs IntRegs:$Rd32),
15216(ins IntRegs:$Rs32, IntRegs:$Rt32),
15217"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15218tc_c21d7447, TypeM>, Enc_5ab2be {
15219let Inst{7-5} = 0b000;
15220let Inst{13-13} = 0b0;
15221let Inst{31-21} = 0b11101100101;
15222let hasNewValue = 1;
15223let opNewValue = 0;
15224let prefersSlot3 = 1;
15225}
15226def M2_mpy_sat_hh_s0 : HInst<
15227(outs IntRegs:$Rd32),
15228(ins IntRegs:$Rs32, IntRegs:$Rt32),
15229"$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
15230tc_c21d7447, TypeM>, Enc_5ab2be {
15231let Inst{7-5} = 0b111;
15232let Inst{13-13} = 0b0;
15233let Inst{31-21} = 0b11101100000;
15234let hasNewValue = 1;
15235let opNewValue = 0;
15236let prefersSlot3 = 1;
15237let Defs = [USR_OVF];
15238}
15239def M2_mpy_sat_hh_s1 : HInst<
15240(outs IntRegs:$Rd32),
15241(ins IntRegs:$Rs32, IntRegs:$Rt32),
15242"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
15243tc_c21d7447, TypeM>, Enc_5ab2be {
15244let Inst{7-5} = 0b111;
15245let Inst{13-13} = 0b0;
15246let Inst{31-21} = 0b11101100100;
15247let hasNewValue = 1;
15248let opNewValue = 0;
15249let prefersSlot3 = 1;
15250let Defs = [USR_OVF];
15251}
15252def M2_mpy_sat_hl_s0 : HInst<
15253(outs IntRegs:$Rd32),
15254(ins IntRegs:$Rs32, IntRegs:$Rt32),
15255"$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
15256tc_c21d7447, TypeM>, Enc_5ab2be {
15257let Inst{7-5} = 0b110;
15258let Inst{13-13} = 0b0;
15259let Inst{31-21} = 0b11101100000;
15260let hasNewValue = 1;
15261let opNewValue = 0;
15262let prefersSlot3 = 1;
15263let Defs = [USR_OVF];
15264}
15265def M2_mpy_sat_hl_s1 : HInst<
15266(outs IntRegs:$Rd32),
15267(ins IntRegs:$Rs32, IntRegs:$Rt32),
15268"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
15269tc_c21d7447, TypeM>, Enc_5ab2be {
15270let Inst{7-5} = 0b110;
15271let Inst{13-13} = 0b0;
15272let Inst{31-21} = 0b11101100100;
15273let hasNewValue = 1;
15274let opNewValue = 0;
15275let prefersSlot3 = 1;
15276let Defs = [USR_OVF];
15277}
15278def M2_mpy_sat_lh_s0 : HInst<
15279(outs IntRegs:$Rd32),
15280(ins IntRegs:$Rs32, IntRegs:$Rt32),
15281"$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
15282tc_c21d7447, TypeM>, Enc_5ab2be {
15283let Inst{7-5} = 0b101;
15284let Inst{13-13} = 0b0;
15285let Inst{31-21} = 0b11101100000;
15286let hasNewValue = 1;
15287let opNewValue = 0;
15288let prefersSlot3 = 1;
15289let Defs = [USR_OVF];
15290}
15291def M2_mpy_sat_lh_s1 : HInst<
15292(outs IntRegs:$Rd32),
15293(ins IntRegs:$Rs32, IntRegs:$Rt32),
15294"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
15295tc_c21d7447, TypeM>, Enc_5ab2be {
15296let Inst{7-5} = 0b101;
15297let Inst{13-13} = 0b0;
15298let Inst{31-21} = 0b11101100100;
15299let hasNewValue = 1;
15300let opNewValue = 0;
15301let prefersSlot3 = 1;
15302let Defs = [USR_OVF];
15303}
15304def M2_mpy_sat_ll_s0 : HInst<
15305(outs IntRegs:$Rd32),
15306(ins IntRegs:$Rs32, IntRegs:$Rt32),
15307"$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
15308tc_c21d7447, TypeM>, Enc_5ab2be {
15309let Inst{7-5} = 0b100;
15310let Inst{13-13} = 0b0;
15311let Inst{31-21} = 0b11101100000;
15312let hasNewValue = 1;
15313let opNewValue = 0;
15314let prefersSlot3 = 1;
15315let Defs = [USR_OVF];
15316}
15317def M2_mpy_sat_ll_s1 : HInst<
15318(outs IntRegs:$Rd32),
15319(ins IntRegs:$Rs32, IntRegs:$Rt32),
15320"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
15321tc_c21d7447, TypeM>, Enc_5ab2be {
15322let Inst{7-5} = 0b100;
15323let Inst{13-13} = 0b0;
15324let Inst{31-21} = 0b11101100100;
15325let hasNewValue = 1;
15326let opNewValue = 0;
15327let prefersSlot3 = 1;
15328let Defs = [USR_OVF];
15329}
15330def M2_mpy_sat_rnd_hh_s0 : HInst<
15331(outs IntRegs:$Rd32),
15332(ins IntRegs:$Rs32, IntRegs:$Rt32),
15333"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
15334tc_c21d7447, TypeM>, Enc_5ab2be {
15335let Inst{7-5} = 0b111;
15336let Inst{13-13} = 0b0;
15337let Inst{31-21} = 0b11101100001;
15338let hasNewValue = 1;
15339let opNewValue = 0;
15340let prefersSlot3 = 1;
15341let Defs = [USR_OVF];
15342}
15343def M2_mpy_sat_rnd_hh_s1 : HInst<
15344(outs IntRegs:$Rd32),
15345(ins IntRegs:$Rs32, IntRegs:$Rt32),
15346"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
15347tc_c21d7447, TypeM>, Enc_5ab2be {
15348let Inst{7-5} = 0b111;
15349let Inst{13-13} = 0b0;
15350let Inst{31-21} = 0b11101100101;
15351let hasNewValue = 1;
15352let opNewValue = 0;
15353let prefersSlot3 = 1;
15354let Defs = [USR_OVF];
15355}
15356def M2_mpy_sat_rnd_hl_s0 : HInst<
15357(outs IntRegs:$Rd32),
15358(ins IntRegs:$Rs32, IntRegs:$Rt32),
15359"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
15360tc_c21d7447, TypeM>, Enc_5ab2be {
15361let Inst{7-5} = 0b110;
15362let Inst{13-13} = 0b0;
15363let Inst{31-21} = 0b11101100001;
15364let hasNewValue = 1;
15365let opNewValue = 0;
15366let prefersSlot3 = 1;
15367let Defs = [USR_OVF];
15368}
15369def M2_mpy_sat_rnd_hl_s1 : HInst<
15370(outs IntRegs:$Rd32),
15371(ins IntRegs:$Rs32, IntRegs:$Rt32),
15372"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
15373tc_c21d7447, TypeM>, Enc_5ab2be {
15374let Inst{7-5} = 0b110;
15375let Inst{13-13} = 0b0;
15376let Inst{31-21} = 0b11101100101;
15377let hasNewValue = 1;
15378let opNewValue = 0;
15379let prefersSlot3 = 1;
15380let Defs = [USR_OVF];
15381}
15382def M2_mpy_sat_rnd_lh_s0 : HInst<
15383(outs IntRegs:$Rd32),
15384(ins IntRegs:$Rs32, IntRegs:$Rt32),
15385"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
15386tc_c21d7447, TypeM>, Enc_5ab2be {
15387let Inst{7-5} = 0b101;
15388let Inst{13-13} = 0b0;
15389let Inst{31-21} = 0b11101100001;
15390let hasNewValue = 1;
15391let opNewValue = 0;
15392let prefersSlot3 = 1;
15393let Defs = [USR_OVF];
15394}
15395def M2_mpy_sat_rnd_lh_s1 : HInst<
15396(outs IntRegs:$Rd32),
15397(ins IntRegs:$Rs32, IntRegs:$Rt32),
15398"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
15399tc_c21d7447, TypeM>, Enc_5ab2be {
15400let Inst{7-5} = 0b101;
15401let Inst{13-13} = 0b0;
15402let Inst{31-21} = 0b11101100101;
15403let hasNewValue = 1;
15404let opNewValue = 0;
15405let prefersSlot3 = 1;
15406let Defs = [USR_OVF];
15407}
15408def M2_mpy_sat_rnd_ll_s0 : HInst<
15409(outs IntRegs:$Rd32),
15410(ins IntRegs:$Rs32, IntRegs:$Rt32),
15411"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
15412tc_c21d7447, TypeM>, Enc_5ab2be {
15413let Inst{7-5} = 0b100;
15414let Inst{13-13} = 0b0;
15415let Inst{31-21} = 0b11101100001;
15416let hasNewValue = 1;
15417let opNewValue = 0;
15418let prefersSlot3 = 1;
15419let Defs = [USR_OVF];
15420}
15421def M2_mpy_sat_rnd_ll_s1 : HInst<
15422(outs IntRegs:$Rd32),
15423(ins IntRegs:$Rs32, IntRegs:$Rt32),
15424"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
15425tc_c21d7447, TypeM>, Enc_5ab2be {
15426let Inst{7-5} = 0b100;
15427let Inst{13-13} = 0b0;
15428let Inst{31-21} = 0b11101100101;
15429let hasNewValue = 1;
15430let opNewValue = 0;
15431let prefersSlot3 = 1;
15432let Defs = [USR_OVF];
15433}
15434def M2_mpy_up : HInst<
15435(outs IntRegs:$Rd32),
15436(ins IntRegs:$Rs32, IntRegs:$Rt32),
15437"$Rd32 = mpy($Rs32,$Rt32)",
15438tc_c21d7447, TypeM>, Enc_5ab2be {
15439let Inst{7-5} = 0b001;
15440let Inst{13-13} = 0b0;
15441let Inst{31-21} = 0b11101101000;
15442let hasNewValue = 1;
15443let opNewValue = 0;
15444let prefersSlot3 = 1;
15445}
15446def M2_mpy_up_s1 : HInst<
15447(outs IntRegs:$Rd32),
15448(ins IntRegs:$Rs32, IntRegs:$Rt32),
15449"$Rd32 = mpy($Rs32,$Rt32):<<1",
15450tc_c21d7447, TypeM>, Enc_5ab2be {
15451let Inst{7-5} = 0b010;
15452let Inst{13-13} = 0b0;
15453let Inst{31-21} = 0b11101101101;
15454let hasNewValue = 1;
15455let opNewValue = 0;
15456let prefersSlot3 = 1;
15457}
15458def M2_mpy_up_s1_sat : HInst<
15459(outs IntRegs:$Rd32),
15460(ins IntRegs:$Rs32, IntRegs:$Rt32),
15461"$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
15462tc_c21d7447, TypeM>, Enc_5ab2be {
15463let Inst{7-5} = 0b000;
15464let Inst{13-13} = 0b0;
15465let Inst{31-21} = 0b11101101111;
15466let hasNewValue = 1;
15467let opNewValue = 0;
15468let prefersSlot3 = 1;
15469let Defs = [USR_OVF];
15470}
15471def M2_mpyd_acc_hh_s0 : HInst<
15472(outs DoubleRegs:$Rxx32),
15473(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15474"$Rxx32 += mpy($Rs32.h,$Rt32.h)",
15475tc_7f8ae742, TypeM>, Enc_61f0b0 {
15476let Inst{7-5} = 0b011;
15477let Inst{13-13} = 0b0;
15478let Inst{31-21} = 0b11100110000;
15479let prefersSlot3 = 1;
15480let Constraints = "$Rxx32 = $Rxx32in";
15481}
15482def M2_mpyd_acc_hh_s1 : HInst<
15483(outs DoubleRegs:$Rxx32),
15484(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15485"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
15486tc_7f8ae742, TypeM>, Enc_61f0b0 {
15487let Inst{7-5} = 0b011;
15488let Inst{13-13} = 0b0;
15489let Inst{31-21} = 0b11100110100;
15490let prefersSlot3 = 1;
15491let Constraints = "$Rxx32 = $Rxx32in";
15492}
15493def M2_mpyd_acc_hl_s0 : HInst<
15494(outs DoubleRegs:$Rxx32),
15495(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15496"$Rxx32 += mpy($Rs32.h,$Rt32.l)",
15497tc_7f8ae742, TypeM>, Enc_61f0b0 {
15498let Inst{7-5} = 0b010;
15499let Inst{13-13} = 0b0;
15500let Inst{31-21} = 0b11100110000;
15501let prefersSlot3 = 1;
15502let Constraints = "$Rxx32 = $Rxx32in";
15503}
15504def M2_mpyd_acc_hl_s1 : HInst<
15505(outs DoubleRegs:$Rxx32),
15506(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15507"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
15508tc_7f8ae742, TypeM>, Enc_61f0b0 {
15509let Inst{7-5} = 0b010;
15510let Inst{13-13} = 0b0;
15511let Inst{31-21} = 0b11100110100;
15512let prefersSlot3 = 1;
15513let Constraints = "$Rxx32 = $Rxx32in";
15514}
15515def M2_mpyd_acc_lh_s0 : HInst<
15516(outs DoubleRegs:$Rxx32),
15517(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15518"$Rxx32 += mpy($Rs32.l,$Rt32.h)",
15519tc_7f8ae742, TypeM>, Enc_61f0b0 {
15520let Inst{7-5} = 0b001;
15521let Inst{13-13} = 0b0;
15522let Inst{31-21} = 0b11100110000;
15523let prefersSlot3 = 1;
15524let Constraints = "$Rxx32 = $Rxx32in";
15525}
15526def M2_mpyd_acc_lh_s1 : HInst<
15527(outs DoubleRegs:$Rxx32),
15528(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15529"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
15530tc_7f8ae742, TypeM>, Enc_61f0b0 {
15531let Inst{7-5} = 0b001;
15532let Inst{13-13} = 0b0;
15533let Inst{31-21} = 0b11100110100;
15534let prefersSlot3 = 1;
15535let Constraints = "$Rxx32 = $Rxx32in";
15536}
15537def M2_mpyd_acc_ll_s0 : HInst<
15538(outs DoubleRegs:$Rxx32),
15539(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15540"$Rxx32 += mpy($Rs32.l,$Rt32.l)",
15541tc_7f8ae742, TypeM>, Enc_61f0b0 {
15542let Inst{7-5} = 0b000;
15543let Inst{13-13} = 0b0;
15544let Inst{31-21} = 0b11100110000;
15545let prefersSlot3 = 1;
15546let Constraints = "$Rxx32 = $Rxx32in";
15547}
15548def M2_mpyd_acc_ll_s1 : HInst<
15549(outs DoubleRegs:$Rxx32),
15550(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15551"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
15552tc_7f8ae742, TypeM>, Enc_61f0b0 {
15553let Inst{7-5} = 0b000;
15554let Inst{13-13} = 0b0;
15555let Inst{31-21} = 0b11100110100;
15556let prefersSlot3 = 1;
15557let Constraints = "$Rxx32 = $Rxx32in";
15558}
15559def M2_mpyd_hh_s0 : HInst<
15560(outs DoubleRegs:$Rdd32),
15561(ins IntRegs:$Rs32, IntRegs:$Rt32),
15562"$Rdd32 = mpy($Rs32.h,$Rt32.h)",
15563tc_c21d7447, TypeM>, Enc_be32a5 {
15564let Inst{7-5} = 0b011;
15565let Inst{13-13} = 0b0;
15566let Inst{31-21} = 0b11100100000;
15567let prefersSlot3 = 1;
15568}
15569def M2_mpyd_hh_s1 : HInst<
15570(outs DoubleRegs:$Rdd32),
15571(ins IntRegs:$Rs32, IntRegs:$Rt32),
15572"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
15573tc_c21d7447, TypeM>, Enc_be32a5 {
15574let Inst{7-5} = 0b011;
15575let Inst{13-13} = 0b0;
15576let Inst{31-21} = 0b11100100100;
15577let prefersSlot3 = 1;
15578}
15579def M2_mpyd_hl_s0 : HInst<
15580(outs DoubleRegs:$Rdd32),
15581(ins IntRegs:$Rs32, IntRegs:$Rt32),
15582"$Rdd32 = mpy($Rs32.h,$Rt32.l)",
15583tc_c21d7447, TypeM>, Enc_be32a5 {
15584let Inst{7-5} = 0b010;
15585let Inst{13-13} = 0b0;
15586let Inst{31-21} = 0b11100100000;
15587let prefersSlot3 = 1;
15588}
15589def M2_mpyd_hl_s1 : HInst<
15590(outs DoubleRegs:$Rdd32),
15591(ins IntRegs:$Rs32, IntRegs:$Rt32),
15592"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
15593tc_c21d7447, TypeM>, Enc_be32a5 {
15594let Inst{7-5} = 0b010;
15595let Inst{13-13} = 0b0;
15596let Inst{31-21} = 0b11100100100;
15597let prefersSlot3 = 1;
15598}
15599def M2_mpyd_lh_s0 : HInst<
15600(outs DoubleRegs:$Rdd32),
15601(ins IntRegs:$Rs32, IntRegs:$Rt32),
15602"$Rdd32 = mpy($Rs32.l,$Rt32.h)",
15603tc_c21d7447, TypeM>, Enc_be32a5 {
15604let Inst{7-5} = 0b001;
15605let Inst{13-13} = 0b0;
15606let Inst{31-21} = 0b11100100000;
15607let prefersSlot3 = 1;
15608}
15609def M2_mpyd_lh_s1 : HInst<
15610(outs DoubleRegs:$Rdd32),
15611(ins IntRegs:$Rs32, IntRegs:$Rt32),
15612"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
15613tc_c21d7447, TypeM>, Enc_be32a5 {
15614let Inst{7-5} = 0b001;
15615let Inst{13-13} = 0b0;
15616let Inst{31-21} = 0b11100100100;
15617let prefersSlot3 = 1;
15618}
15619def M2_mpyd_ll_s0 : HInst<
15620(outs DoubleRegs:$Rdd32),
15621(ins IntRegs:$Rs32, IntRegs:$Rt32),
15622"$Rdd32 = mpy($Rs32.l,$Rt32.l)",
15623tc_c21d7447, TypeM>, Enc_be32a5 {
15624let Inst{7-5} = 0b000;
15625let Inst{13-13} = 0b0;
15626let Inst{31-21} = 0b11100100000;
15627let prefersSlot3 = 1;
15628}
15629def M2_mpyd_ll_s1 : HInst<
15630(outs DoubleRegs:$Rdd32),
15631(ins IntRegs:$Rs32, IntRegs:$Rt32),
15632"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
15633tc_c21d7447, TypeM>, Enc_be32a5 {
15634let Inst{7-5} = 0b000;
15635let Inst{13-13} = 0b0;
15636let Inst{31-21} = 0b11100100100;
15637let prefersSlot3 = 1;
15638}
15639def M2_mpyd_nac_hh_s0 : HInst<
15640(outs DoubleRegs:$Rxx32),
15641(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15642"$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
15643tc_7f8ae742, TypeM>, Enc_61f0b0 {
15644let Inst{7-5} = 0b011;
15645let Inst{13-13} = 0b0;
15646let Inst{31-21} = 0b11100110001;
15647let prefersSlot3 = 1;
15648let Constraints = "$Rxx32 = $Rxx32in";
15649}
15650def M2_mpyd_nac_hh_s1 : HInst<
15651(outs DoubleRegs:$Rxx32),
15652(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15653"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15654tc_7f8ae742, TypeM>, Enc_61f0b0 {
15655let Inst{7-5} = 0b011;
15656let Inst{13-13} = 0b0;
15657let Inst{31-21} = 0b11100110101;
15658let prefersSlot3 = 1;
15659let Constraints = "$Rxx32 = $Rxx32in";
15660}
15661def M2_mpyd_nac_hl_s0 : HInst<
15662(outs DoubleRegs:$Rxx32),
15663(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15664"$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
15665tc_7f8ae742, TypeM>, Enc_61f0b0 {
15666let Inst{7-5} = 0b010;
15667let Inst{13-13} = 0b0;
15668let Inst{31-21} = 0b11100110001;
15669let prefersSlot3 = 1;
15670let Constraints = "$Rxx32 = $Rxx32in";
15671}
15672def M2_mpyd_nac_hl_s1 : HInst<
15673(outs DoubleRegs:$Rxx32),
15674(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15675"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15676tc_7f8ae742, TypeM>, Enc_61f0b0 {
15677let Inst{7-5} = 0b010;
15678let Inst{13-13} = 0b0;
15679let Inst{31-21} = 0b11100110101;
15680let prefersSlot3 = 1;
15681let Constraints = "$Rxx32 = $Rxx32in";
15682}
15683def M2_mpyd_nac_lh_s0 : HInst<
15684(outs DoubleRegs:$Rxx32),
15685(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15686"$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
15687tc_7f8ae742, TypeM>, Enc_61f0b0 {
15688let Inst{7-5} = 0b001;
15689let Inst{13-13} = 0b0;
15690let Inst{31-21} = 0b11100110001;
15691let prefersSlot3 = 1;
15692let Constraints = "$Rxx32 = $Rxx32in";
15693}
15694def M2_mpyd_nac_lh_s1 : HInst<
15695(outs DoubleRegs:$Rxx32),
15696(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15697"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15698tc_7f8ae742, TypeM>, Enc_61f0b0 {
15699let Inst{7-5} = 0b001;
15700let Inst{13-13} = 0b0;
15701let Inst{31-21} = 0b11100110101;
15702let prefersSlot3 = 1;
15703let Constraints = "$Rxx32 = $Rxx32in";
15704}
15705def M2_mpyd_nac_ll_s0 : HInst<
15706(outs DoubleRegs:$Rxx32),
15707(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15708"$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
15709tc_7f8ae742, TypeM>, Enc_61f0b0 {
15710let Inst{7-5} = 0b000;
15711let Inst{13-13} = 0b0;
15712let Inst{31-21} = 0b11100110001;
15713let prefersSlot3 = 1;
15714let Constraints = "$Rxx32 = $Rxx32in";
15715}
15716def M2_mpyd_nac_ll_s1 : HInst<
15717(outs DoubleRegs:$Rxx32),
15718(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15719"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15720tc_7f8ae742, TypeM>, Enc_61f0b0 {
15721let Inst{7-5} = 0b000;
15722let Inst{13-13} = 0b0;
15723let Inst{31-21} = 0b11100110101;
15724let prefersSlot3 = 1;
15725let Constraints = "$Rxx32 = $Rxx32in";
15726}
15727def M2_mpyd_rnd_hh_s0 : HInst<
15728(outs DoubleRegs:$Rdd32),
15729(ins IntRegs:$Rs32, IntRegs:$Rt32),
15730"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
15731tc_c21d7447, TypeM>, Enc_be32a5 {
15732let Inst{7-5} = 0b011;
15733let Inst{13-13} = 0b0;
15734let Inst{31-21} = 0b11100100001;
15735let prefersSlot3 = 1;
15736}
15737def M2_mpyd_rnd_hh_s1 : HInst<
15738(outs DoubleRegs:$Rdd32),
15739(ins IntRegs:$Rs32, IntRegs:$Rt32),
15740"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15741tc_c21d7447, TypeM>, Enc_be32a5 {
15742let Inst{7-5} = 0b011;
15743let Inst{13-13} = 0b0;
15744let Inst{31-21} = 0b11100100101;
15745let prefersSlot3 = 1;
15746}
15747def M2_mpyd_rnd_hl_s0 : HInst<
15748(outs DoubleRegs:$Rdd32),
15749(ins IntRegs:$Rs32, IntRegs:$Rt32),
15750"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
15751tc_c21d7447, TypeM>, Enc_be32a5 {
15752let Inst{7-5} = 0b010;
15753let Inst{13-13} = 0b0;
15754let Inst{31-21} = 0b11100100001;
15755let prefersSlot3 = 1;
15756}
15757def M2_mpyd_rnd_hl_s1 : HInst<
15758(outs DoubleRegs:$Rdd32),
15759(ins IntRegs:$Rs32, IntRegs:$Rt32),
15760"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15761tc_c21d7447, TypeM>, Enc_be32a5 {
15762let Inst{7-5} = 0b010;
15763let Inst{13-13} = 0b0;
15764let Inst{31-21} = 0b11100100101;
15765let prefersSlot3 = 1;
15766}
15767def M2_mpyd_rnd_lh_s0 : HInst<
15768(outs DoubleRegs:$Rdd32),
15769(ins IntRegs:$Rs32, IntRegs:$Rt32),
15770"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
15771tc_c21d7447, TypeM>, Enc_be32a5 {
15772let Inst{7-5} = 0b001;
15773let Inst{13-13} = 0b0;
15774let Inst{31-21} = 0b11100100001;
15775let prefersSlot3 = 1;
15776}
15777def M2_mpyd_rnd_lh_s1 : HInst<
15778(outs DoubleRegs:$Rdd32),
15779(ins IntRegs:$Rs32, IntRegs:$Rt32),
15780"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15781tc_c21d7447, TypeM>, Enc_be32a5 {
15782let Inst{7-5} = 0b001;
15783let Inst{13-13} = 0b0;
15784let Inst{31-21} = 0b11100100101;
15785let prefersSlot3 = 1;
15786}
15787def M2_mpyd_rnd_ll_s0 : HInst<
15788(outs DoubleRegs:$Rdd32),
15789(ins IntRegs:$Rs32, IntRegs:$Rt32),
15790"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
15791tc_c21d7447, TypeM>, Enc_be32a5 {
15792let Inst{7-5} = 0b000;
15793let Inst{13-13} = 0b0;
15794let Inst{31-21} = 0b11100100001;
15795let prefersSlot3 = 1;
15796}
15797def M2_mpyd_rnd_ll_s1 : HInst<
15798(outs DoubleRegs:$Rdd32),
15799(ins IntRegs:$Rs32, IntRegs:$Rt32),
15800"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15801tc_c21d7447, TypeM>, Enc_be32a5 {
15802let Inst{7-5} = 0b000;
15803let Inst{13-13} = 0b0;
15804let Inst{31-21} = 0b11100100101;
15805let prefersSlot3 = 1;
15806}
15807def M2_mpyi : HInst<
15808(outs IntRegs:$Rd32),
15809(ins IntRegs:$Rs32, IntRegs:$Rt32),
15810"$Rd32 = mpyi($Rs32,$Rt32)",
15811tc_c21d7447, TypeM>, Enc_5ab2be, ImmRegRel {
15812let Inst{7-5} = 0b000;
15813let Inst{13-13} = 0b0;
15814let Inst{31-21} = 0b11101101000;
15815let hasNewValue = 1;
15816let opNewValue = 0;
15817let prefersSlot3 = 1;
15818let CextOpcode = "M2_mpyi";
15819let InputType = "reg";
15820}
15821def M2_mpysin : HInst<
15822(outs IntRegs:$Rd32),
15823(ins IntRegs:$Rs32, u8_0Imm:$Ii),
15824"$Rd32 = -mpyi($Rs32,#$Ii)",
15825tc_38382228, TypeM>, Enc_b8c967 {
15826let Inst{13-13} = 0b0;
15827let Inst{31-21} = 0b11100000100;
15828let hasNewValue = 1;
15829let opNewValue = 0;
15830let prefersSlot3 = 1;
15831}
15832def M2_mpysip : HInst<
15833(outs IntRegs:$Rd32),
15834(ins IntRegs:$Rs32, u32_0Imm:$Ii),
15835"$Rd32 = +mpyi($Rs32,#$Ii)",
15836tc_38382228, TypeM>, Enc_b8c967 {
15837let Inst{13-13} = 0b0;
15838let Inst{31-21} = 0b11100000000;
15839let hasNewValue = 1;
15840let opNewValue = 0;
15841let prefersSlot3 = 1;
15842let isExtendable = 1;
15843let opExtendable = 2;
15844let isExtentSigned = 0;
15845let opExtentBits = 8;
15846let opExtentAlign = 0;
15847}
15848def M2_mpysmi : HInst<
15849(outs IntRegs:$Rd32),
15850(ins IntRegs:$Rs32, m32_0Imm:$Ii),
15851"$Rd32 = mpyi($Rs32,#$Ii)",
15852tc_38382228, TypeM>, ImmRegRel {
15853let hasNewValue = 1;
15854let opNewValue = 0;
15855let CextOpcode = "M2_mpyi";
15856let InputType = "imm";
15857let isPseudo = 1;
15858let isExtendable = 1;
15859let opExtendable = 2;
15860let isExtentSigned = 1;
15861let opExtentBits = 9;
15862let opExtentAlign = 0;
15863}
15864def M2_mpysu_up : HInst<
15865(outs IntRegs:$Rd32),
15866(ins IntRegs:$Rs32, IntRegs:$Rt32),
15867"$Rd32 = mpysu($Rs32,$Rt32)",
15868tc_c21d7447, TypeM>, Enc_5ab2be {
15869let Inst{7-5} = 0b001;
15870let Inst{13-13} = 0b0;
15871let Inst{31-21} = 0b11101101011;
15872let hasNewValue = 1;
15873let opNewValue = 0;
15874let prefersSlot3 = 1;
15875}
15876def M2_mpyu_acc_hh_s0 : HInst<
15877(outs IntRegs:$Rx32),
15878(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15879"$Rx32 += mpyu($Rs32.h,$Rt32.h)",
15880tc_7f8ae742, TypeM>, Enc_2ae154 {
15881let Inst{7-5} = 0b011;
15882let Inst{13-13} = 0b0;
15883let Inst{31-21} = 0b11101110010;
15884let hasNewValue = 1;
15885let opNewValue = 0;
15886let prefersSlot3 = 1;
15887let Constraints = "$Rx32 = $Rx32in";
15888}
15889def M2_mpyu_acc_hh_s1 : HInst<
15890(outs IntRegs:$Rx32),
15891(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15892"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15893tc_7f8ae742, TypeM>, Enc_2ae154 {
15894let Inst{7-5} = 0b011;
15895let Inst{13-13} = 0b0;
15896let Inst{31-21} = 0b11101110110;
15897let hasNewValue = 1;
15898let opNewValue = 0;
15899let prefersSlot3 = 1;
15900let Constraints = "$Rx32 = $Rx32in";
15901}
15902def M2_mpyu_acc_hl_s0 : HInst<
15903(outs IntRegs:$Rx32),
15904(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15905"$Rx32 += mpyu($Rs32.h,$Rt32.l)",
15906tc_7f8ae742, TypeM>, Enc_2ae154 {
15907let Inst{7-5} = 0b010;
15908let Inst{13-13} = 0b0;
15909let Inst{31-21} = 0b11101110010;
15910let hasNewValue = 1;
15911let opNewValue = 0;
15912let prefersSlot3 = 1;
15913let Constraints = "$Rx32 = $Rx32in";
15914}
15915def M2_mpyu_acc_hl_s1 : HInst<
15916(outs IntRegs:$Rx32),
15917(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15918"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
15919tc_7f8ae742, TypeM>, Enc_2ae154 {
15920let Inst{7-5} = 0b010;
15921let Inst{13-13} = 0b0;
15922let Inst{31-21} = 0b11101110110;
15923let hasNewValue = 1;
15924let opNewValue = 0;
15925let prefersSlot3 = 1;
15926let Constraints = "$Rx32 = $Rx32in";
15927}
15928def M2_mpyu_acc_lh_s0 : HInst<
15929(outs IntRegs:$Rx32),
15930(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15931"$Rx32 += mpyu($Rs32.l,$Rt32.h)",
15932tc_7f8ae742, TypeM>, Enc_2ae154 {
15933let Inst{7-5} = 0b001;
15934let Inst{13-13} = 0b0;
15935let Inst{31-21} = 0b11101110010;
15936let hasNewValue = 1;
15937let opNewValue = 0;
15938let prefersSlot3 = 1;
15939let Constraints = "$Rx32 = $Rx32in";
15940}
15941def M2_mpyu_acc_lh_s1 : HInst<
15942(outs IntRegs:$Rx32),
15943(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15944"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
15945tc_7f8ae742, TypeM>, Enc_2ae154 {
15946let Inst{7-5} = 0b001;
15947let Inst{13-13} = 0b0;
15948let Inst{31-21} = 0b11101110110;
15949let hasNewValue = 1;
15950let opNewValue = 0;
15951let prefersSlot3 = 1;
15952let Constraints = "$Rx32 = $Rx32in";
15953}
15954def M2_mpyu_acc_ll_s0 : HInst<
15955(outs IntRegs:$Rx32),
15956(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15957"$Rx32 += mpyu($Rs32.l,$Rt32.l)",
15958tc_7f8ae742, TypeM>, Enc_2ae154 {
15959let Inst{7-5} = 0b000;
15960let Inst{13-13} = 0b0;
15961let Inst{31-21} = 0b11101110010;
15962let hasNewValue = 1;
15963let opNewValue = 0;
15964let prefersSlot3 = 1;
15965let Constraints = "$Rx32 = $Rx32in";
15966}
15967def M2_mpyu_acc_ll_s1 : HInst<
15968(outs IntRegs:$Rx32),
15969(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15970"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
15971tc_7f8ae742, TypeM>, Enc_2ae154 {
15972let Inst{7-5} = 0b000;
15973let Inst{13-13} = 0b0;
15974let Inst{31-21} = 0b11101110110;
15975let hasNewValue = 1;
15976let opNewValue = 0;
15977let prefersSlot3 = 1;
15978let Constraints = "$Rx32 = $Rx32in";
15979}
15980def M2_mpyu_hh_s0 : HInst<
15981(outs IntRegs:$Rd32),
15982(ins IntRegs:$Rs32, IntRegs:$Rt32),
15983"$Rd32 = mpyu($Rs32.h,$Rt32.h)",
15984tc_c21d7447, TypeM>, Enc_5ab2be {
15985let Inst{7-5} = 0b011;
15986let Inst{13-13} = 0b0;
15987let Inst{31-21} = 0b11101100010;
15988let hasNewValue = 1;
15989let opNewValue = 0;
15990let prefersSlot3 = 1;
15991}
15992def M2_mpyu_hh_s1 : HInst<
15993(outs IntRegs:$Rd32),
15994(ins IntRegs:$Rs32, IntRegs:$Rt32),
15995"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
15996tc_c21d7447, TypeM>, Enc_5ab2be {
15997let Inst{7-5} = 0b011;
15998let Inst{13-13} = 0b0;
15999let Inst{31-21} = 0b11101100110;
16000let hasNewValue = 1;
16001let opNewValue = 0;
16002let prefersSlot3 = 1;
16003}
16004def M2_mpyu_hl_s0 : HInst<
16005(outs IntRegs:$Rd32),
16006(ins IntRegs:$Rs32, IntRegs:$Rt32),
16007"$Rd32 = mpyu($Rs32.h,$Rt32.l)",
16008tc_c21d7447, TypeM>, Enc_5ab2be {
16009let Inst{7-5} = 0b010;
16010let Inst{13-13} = 0b0;
16011let Inst{31-21} = 0b11101100010;
16012let hasNewValue = 1;
16013let opNewValue = 0;
16014let prefersSlot3 = 1;
16015}
16016def M2_mpyu_hl_s1 : HInst<
16017(outs IntRegs:$Rd32),
16018(ins IntRegs:$Rs32, IntRegs:$Rt32),
16019"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16020tc_c21d7447, TypeM>, Enc_5ab2be {
16021let Inst{7-5} = 0b010;
16022let Inst{13-13} = 0b0;
16023let Inst{31-21} = 0b11101100110;
16024let hasNewValue = 1;
16025let opNewValue = 0;
16026let prefersSlot3 = 1;
16027}
16028def M2_mpyu_lh_s0 : HInst<
16029(outs IntRegs:$Rd32),
16030(ins IntRegs:$Rs32, IntRegs:$Rt32),
16031"$Rd32 = mpyu($Rs32.l,$Rt32.h)",
16032tc_c21d7447, TypeM>, Enc_5ab2be {
16033let Inst{7-5} = 0b001;
16034let Inst{13-13} = 0b0;
16035let Inst{31-21} = 0b11101100010;
16036let hasNewValue = 1;
16037let opNewValue = 0;
16038let prefersSlot3 = 1;
16039}
16040def M2_mpyu_lh_s1 : HInst<
16041(outs IntRegs:$Rd32),
16042(ins IntRegs:$Rs32, IntRegs:$Rt32),
16043"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16044tc_c21d7447, TypeM>, Enc_5ab2be {
16045let Inst{7-5} = 0b001;
16046let Inst{13-13} = 0b0;
16047let Inst{31-21} = 0b11101100110;
16048let hasNewValue = 1;
16049let opNewValue = 0;
16050let prefersSlot3 = 1;
16051}
16052def M2_mpyu_ll_s0 : HInst<
16053(outs IntRegs:$Rd32),
16054(ins IntRegs:$Rs32, IntRegs:$Rt32),
16055"$Rd32 = mpyu($Rs32.l,$Rt32.l)",
16056tc_c21d7447, TypeM>, Enc_5ab2be {
16057let Inst{7-5} = 0b000;
16058let Inst{13-13} = 0b0;
16059let Inst{31-21} = 0b11101100010;
16060let hasNewValue = 1;
16061let opNewValue = 0;
16062let prefersSlot3 = 1;
16063}
16064def M2_mpyu_ll_s1 : HInst<
16065(outs IntRegs:$Rd32),
16066(ins IntRegs:$Rs32, IntRegs:$Rt32),
16067"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16068tc_c21d7447, TypeM>, Enc_5ab2be {
16069let Inst{7-5} = 0b000;
16070let Inst{13-13} = 0b0;
16071let Inst{31-21} = 0b11101100110;
16072let hasNewValue = 1;
16073let opNewValue = 0;
16074let prefersSlot3 = 1;
16075}
16076def M2_mpyu_nac_hh_s0 : HInst<
16077(outs IntRegs:$Rx32),
16078(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16079"$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
16080tc_7f8ae742, TypeM>, Enc_2ae154 {
16081let Inst{7-5} = 0b011;
16082let Inst{13-13} = 0b0;
16083let Inst{31-21} = 0b11101110011;
16084let hasNewValue = 1;
16085let opNewValue = 0;
16086let prefersSlot3 = 1;
16087let Constraints = "$Rx32 = $Rx32in";
16088}
16089def M2_mpyu_nac_hh_s1 : HInst<
16090(outs IntRegs:$Rx32),
16091(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16092"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16093tc_7f8ae742, TypeM>, Enc_2ae154 {
16094let Inst{7-5} = 0b011;
16095let Inst{13-13} = 0b0;
16096let Inst{31-21} = 0b11101110111;
16097let hasNewValue = 1;
16098let opNewValue = 0;
16099let prefersSlot3 = 1;
16100let Constraints = "$Rx32 = $Rx32in";
16101}
16102def M2_mpyu_nac_hl_s0 : HInst<
16103(outs IntRegs:$Rx32),
16104(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16105"$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
16106tc_7f8ae742, TypeM>, Enc_2ae154 {
16107let Inst{7-5} = 0b010;
16108let Inst{13-13} = 0b0;
16109let Inst{31-21} = 0b11101110011;
16110let hasNewValue = 1;
16111let opNewValue = 0;
16112let prefersSlot3 = 1;
16113let Constraints = "$Rx32 = $Rx32in";
16114}
16115def M2_mpyu_nac_hl_s1 : HInst<
16116(outs IntRegs:$Rx32),
16117(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16118"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16119tc_7f8ae742, TypeM>, Enc_2ae154 {
16120let Inst{7-5} = 0b010;
16121let Inst{13-13} = 0b0;
16122let Inst{31-21} = 0b11101110111;
16123let hasNewValue = 1;
16124let opNewValue = 0;
16125let prefersSlot3 = 1;
16126let Constraints = "$Rx32 = $Rx32in";
16127}
16128def M2_mpyu_nac_lh_s0 : HInst<
16129(outs IntRegs:$Rx32),
16130(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16131"$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
16132tc_7f8ae742, TypeM>, Enc_2ae154 {
16133let Inst{7-5} = 0b001;
16134let Inst{13-13} = 0b0;
16135let Inst{31-21} = 0b11101110011;
16136let hasNewValue = 1;
16137let opNewValue = 0;
16138let prefersSlot3 = 1;
16139let Constraints = "$Rx32 = $Rx32in";
16140}
16141def M2_mpyu_nac_lh_s1 : HInst<
16142(outs IntRegs:$Rx32),
16143(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16144"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16145tc_7f8ae742, TypeM>, Enc_2ae154 {
16146let Inst{7-5} = 0b001;
16147let Inst{13-13} = 0b0;
16148let Inst{31-21} = 0b11101110111;
16149let hasNewValue = 1;
16150let opNewValue = 0;
16151let prefersSlot3 = 1;
16152let Constraints = "$Rx32 = $Rx32in";
16153}
16154def M2_mpyu_nac_ll_s0 : HInst<
16155(outs IntRegs:$Rx32),
16156(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16157"$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
16158tc_7f8ae742, TypeM>, Enc_2ae154 {
16159let Inst{7-5} = 0b000;
16160let Inst{13-13} = 0b0;
16161let Inst{31-21} = 0b11101110011;
16162let hasNewValue = 1;
16163let opNewValue = 0;
16164let prefersSlot3 = 1;
16165let Constraints = "$Rx32 = $Rx32in";
16166}
16167def M2_mpyu_nac_ll_s1 : HInst<
16168(outs IntRegs:$Rx32),
16169(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16170"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16171tc_7f8ae742, TypeM>, Enc_2ae154 {
16172let Inst{7-5} = 0b000;
16173let Inst{13-13} = 0b0;
16174let Inst{31-21} = 0b11101110111;
16175let hasNewValue = 1;
16176let opNewValue = 0;
16177let prefersSlot3 = 1;
16178let Constraints = "$Rx32 = $Rx32in";
16179}
16180def M2_mpyu_up : HInst<
16181(outs IntRegs:$Rd32),
16182(ins IntRegs:$Rs32, IntRegs:$Rt32),
16183"$Rd32 = mpyu($Rs32,$Rt32)",
16184tc_c21d7447, TypeM>, Enc_5ab2be {
16185let Inst{7-5} = 0b001;
16186let Inst{13-13} = 0b0;
16187let Inst{31-21} = 0b11101101010;
16188let hasNewValue = 1;
16189let opNewValue = 0;
16190let prefersSlot3 = 1;
16191}
16192def M2_mpyud_acc_hh_s0 : HInst<
16193(outs DoubleRegs:$Rxx32),
16194(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16195"$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
16196tc_7f8ae742, TypeM>, Enc_61f0b0 {
16197let Inst{7-5} = 0b011;
16198let Inst{13-13} = 0b0;
16199let Inst{31-21} = 0b11100110010;
16200let prefersSlot3 = 1;
16201let Constraints = "$Rxx32 = $Rxx32in";
16202}
16203def M2_mpyud_acc_hh_s1 : HInst<
16204(outs DoubleRegs:$Rxx32),
16205(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16206"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
16207tc_7f8ae742, TypeM>, Enc_61f0b0 {
16208let Inst{7-5} = 0b011;
16209let Inst{13-13} = 0b0;
16210let Inst{31-21} = 0b11100110110;
16211let prefersSlot3 = 1;
16212let Constraints = "$Rxx32 = $Rxx32in";
16213}
16214def M2_mpyud_acc_hl_s0 : HInst<
16215(outs DoubleRegs:$Rxx32),
16216(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16217"$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
16218tc_7f8ae742, TypeM>, Enc_61f0b0 {
16219let Inst{7-5} = 0b010;
16220let Inst{13-13} = 0b0;
16221let Inst{31-21} = 0b11100110010;
16222let prefersSlot3 = 1;
16223let Constraints = "$Rxx32 = $Rxx32in";
16224}
16225def M2_mpyud_acc_hl_s1 : HInst<
16226(outs DoubleRegs:$Rxx32),
16227(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16228"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
16229tc_7f8ae742, TypeM>, Enc_61f0b0 {
16230let Inst{7-5} = 0b010;
16231let Inst{13-13} = 0b0;
16232let Inst{31-21} = 0b11100110110;
16233let prefersSlot3 = 1;
16234let Constraints = "$Rxx32 = $Rxx32in";
16235}
16236def M2_mpyud_acc_lh_s0 : HInst<
16237(outs DoubleRegs:$Rxx32),
16238(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16239"$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
16240tc_7f8ae742, TypeM>, Enc_61f0b0 {
16241let Inst{7-5} = 0b001;
16242let Inst{13-13} = 0b0;
16243let Inst{31-21} = 0b11100110010;
16244let prefersSlot3 = 1;
16245let Constraints = "$Rxx32 = $Rxx32in";
16246}
16247def M2_mpyud_acc_lh_s1 : HInst<
16248(outs DoubleRegs:$Rxx32),
16249(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16250"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16251tc_7f8ae742, TypeM>, Enc_61f0b0 {
16252let Inst{7-5} = 0b001;
16253let Inst{13-13} = 0b0;
16254let Inst{31-21} = 0b11100110110;
16255let prefersSlot3 = 1;
16256let Constraints = "$Rxx32 = $Rxx32in";
16257}
16258def M2_mpyud_acc_ll_s0 : HInst<
16259(outs DoubleRegs:$Rxx32),
16260(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16261"$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
16262tc_7f8ae742, TypeM>, Enc_61f0b0 {
16263let Inst{7-5} = 0b000;
16264let Inst{13-13} = 0b0;
16265let Inst{31-21} = 0b11100110010;
16266let prefersSlot3 = 1;
16267let Constraints = "$Rxx32 = $Rxx32in";
16268}
16269def M2_mpyud_acc_ll_s1 : HInst<
16270(outs DoubleRegs:$Rxx32),
16271(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16272"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16273tc_7f8ae742, TypeM>, Enc_61f0b0 {
16274let Inst{7-5} = 0b000;
16275let Inst{13-13} = 0b0;
16276let Inst{31-21} = 0b11100110110;
16277let prefersSlot3 = 1;
16278let Constraints = "$Rxx32 = $Rxx32in";
16279}
16280def M2_mpyud_hh_s0 : HInst<
16281(outs DoubleRegs:$Rdd32),
16282(ins IntRegs:$Rs32, IntRegs:$Rt32),
16283"$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
16284tc_c21d7447, TypeM>, Enc_be32a5 {
16285let Inst{7-5} = 0b011;
16286let Inst{13-13} = 0b0;
16287let Inst{31-21} = 0b11100100010;
16288let prefersSlot3 = 1;
16289}
16290def M2_mpyud_hh_s1 : HInst<
16291(outs DoubleRegs:$Rdd32),
16292(ins IntRegs:$Rs32, IntRegs:$Rt32),
16293"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16294tc_c21d7447, TypeM>, Enc_be32a5 {
16295let Inst{7-5} = 0b011;
16296let Inst{13-13} = 0b0;
16297let Inst{31-21} = 0b11100100110;
16298let prefersSlot3 = 1;
16299}
16300def M2_mpyud_hl_s0 : HInst<
16301(outs DoubleRegs:$Rdd32),
16302(ins IntRegs:$Rs32, IntRegs:$Rt32),
16303"$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
16304tc_c21d7447, TypeM>, Enc_be32a5 {
16305let Inst{7-5} = 0b010;
16306let Inst{13-13} = 0b0;
16307let Inst{31-21} = 0b11100100010;
16308let prefersSlot3 = 1;
16309}
16310def M2_mpyud_hl_s1 : HInst<
16311(outs DoubleRegs:$Rdd32),
16312(ins IntRegs:$Rs32, IntRegs:$Rt32),
16313"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16314tc_c21d7447, TypeM>, Enc_be32a5 {
16315let Inst{7-5} = 0b010;
16316let Inst{13-13} = 0b0;
16317let Inst{31-21} = 0b11100100110;
16318let prefersSlot3 = 1;
16319}
16320def M2_mpyud_lh_s0 : HInst<
16321(outs DoubleRegs:$Rdd32),
16322(ins IntRegs:$Rs32, IntRegs:$Rt32),
16323"$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
16324tc_c21d7447, TypeM>, Enc_be32a5 {
16325let Inst{7-5} = 0b001;
16326let Inst{13-13} = 0b0;
16327let Inst{31-21} = 0b11100100010;
16328let prefersSlot3 = 1;
16329}
16330def M2_mpyud_lh_s1 : HInst<
16331(outs DoubleRegs:$Rdd32),
16332(ins IntRegs:$Rs32, IntRegs:$Rt32),
16333"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16334tc_c21d7447, TypeM>, Enc_be32a5 {
16335let Inst{7-5} = 0b001;
16336let Inst{13-13} = 0b0;
16337let Inst{31-21} = 0b11100100110;
16338let prefersSlot3 = 1;
16339}
16340def M2_mpyud_ll_s0 : HInst<
16341(outs DoubleRegs:$Rdd32),
16342(ins IntRegs:$Rs32, IntRegs:$Rt32),
16343"$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
16344tc_c21d7447, TypeM>, Enc_be32a5 {
16345let Inst{7-5} = 0b000;
16346let Inst{13-13} = 0b0;
16347let Inst{31-21} = 0b11100100010;
16348let prefersSlot3 = 1;
16349}
16350def M2_mpyud_ll_s1 : HInst<
16351(outs DoubleRegs:$Rdd32),
16352(ins IntRegs:$Rs32, IntRegs:$Rt32),
16353"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16354tc_c21d7447, TypeM>, Enc_be32a5 {
16355let Inst{7-5} = 0b000;
16356let Inst{13-13} = 0b0;
16357let Inst{31-21} = 0b11100100110;
16358let prefersSlot3 = 1;
16359}
16360def M2_mpyud_nac_hh_s0 : HInst<
16361(outs DoubleRegs:$Rxx32),
16362(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16363"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
16364tc_7f8ae742, TypeM>, Enc_61f0b0 {
16365let Inst{7-5} = 0b011;
16366let Inst{13-13} = 0b0;
16367let Inst{31-21} = 0b11100110011;
16368let prefersSlot3 = 1;
16369let Constraints = "$Rxx32 = $Rxx32in";
16370}
16371def M2_mpyud_nac_hh_s1 : HInst<
16372(outs DoubleRegs:$Rxx32),
16373(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16374"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16375tc_7f8ae742, TypeM>, Enc_61f0b0 {
16376let Inst{7-5} = 0b011;
16377let Inst{13-13} = 0b0;
16378let Inst{31-21} = 0b11100110111;
16379let prefersSlot3 = 1;
16380let Constraints = "$Rxx32 = $Rxx32in";
16381}
16382def M2_mpyud_nac_hl_s0 : HInst<
16383(outs DoubleRegs:$Rxx32),
16384(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16385"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
16386tc_7f8ae742, TypeM>, Enc_61f0b0 {
16387let Inst{7-5} = 0b010;
16388let Inst{13-13} = 0b0;
16389let Inst{31-21} = 0b11100110011;
16390let prefersSlot3 = 1;
16391let Constraints = "$Rxx32 = $Rxx32in";
16392}
16393def M2_mpyud_nac_hl_s1 : HInst<
16394(outs DoubleRegs:$Rxx32),
16395(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16396"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16397tc_7f8ae742, TypeM>, Enc_61f0b0 {
16398let Inst{7-5} = 0b010;
16399let Inst{13-13} = 0b0;
16400let Inst{31-21} = 0b11100110111;
16401let prefersSlot3 = 1;
16402let Constraints = "$Rxx32 = $Rxx32in";
16403}
16404def M2_mpyud_nac_lh_s0 : HInst<
16405(outs DoubleRegs:$Rxx32),
16406(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16407"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
16408tc_7f8ae742, TypeM>, Enc_61f0b0 {
16409let Inst{7-5} = 0b001;
16410let Inst{13-13} = 0b0;
16411let Inst{31-21} = 0b11100110011;
16412let prefersSlot3 = 1;
16413let Constraints = "$Rxx32 = $Rxx32in";
16414}
16415def M2_mpyud_nac_lh_s1 : HInst<
16416(outs DoubleRegs:$Rxx32),
16417(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16418"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16419tc_7f8ae742, TypeM>, Enc_61f0b0 {
16420let Inst{7-5} = 0b001;
16421let Inst{13-13} = 0b0;
16422let Inst{31-21} = 0b11100110111;
16423let prefersSlot3 = 1;
16424let Constraints = "$Rxx32 = $Rxx32in";
16425}
16426def M2_mpyud_nac_ll_s0 : HInst<
16427(outs DoubleRegs:$Rxx32),
16428(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16429"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
16430tc_7f8ae742, TypeM>, Enc_61f0b0 {
16431let Inst{7-5} = 0b000;
16432let Inst{13-13} = 0b0;
16433let Inst{31-21} = 0b11100110011;
16434let prefersSlot3 = 1;
16435let Constraints = "$Rxx32 = $Rxx32in";
16436}
16437def M2_mpyud_nac_ll_s1 : HInst<
16438(outs DoubleRegs:$Rxx32),
16439(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16440"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16441tc_7f8ae742, TypeM>, Enc_61f0b0 {
16442let Inst{7-5} = 0b000;
16443let Inst{13-13} = 0b0;
16444let Inst{31-21} = 0b11100110111;
16445let prefersSlot3 = 1;
16446let Constraints = "$Rxx32 = $Rxx32in";
16447}
16448def M2_mpyui : HInst<
16449(outs IntRegs:$Rd32),
16450(ins IntRegs:$Rs32, IntRegs:$Rt32),
16451"$Rd32 = mpyui($Rs32,$Rt32)",
16452tc_c21d7447, TypeM> {
16453let hasNewValue = 1;
16454let opNewValue = 0;
16455let isPseudo = 1;
16456let isCodeGenOnly = 1;
16457}
16458def M2_nacci : HInst<
16459(outs IntRegs:$Rx32),
16460(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16461"$Rx32 -= add($Rs32,$Rt32)",
16462tc_2c13e7f5, TypeM>, Enc_2ae154 {
16463let Inst{7-5} = 0b001;
16464let Inst{13-13} = 0b0;
16465let Inst{31-21} = 0b11101111100;
16466let hasNewValue = 1;
16467let opNewValue = 0;
16468let prefersSlot3 = 1;
16469let InputType = "reg";
16470let Constraints = "$Rx32 = $Rx32in";
16471}
16472def M2_naccii : HInst<
16473(outs IntRegs:$Rx32),
16474(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
16475"$Rx32 -= add($Rs32,#$Ii)",
16476tc_2c13e7f5, TypeM>, Enc_c90aca {
16477let Inst{13-13} = 0b0;
16478let Inst{31-21} = 0b11100010100;
16479let hasNewValue = 1;
16480let opNewValue = 0;
16481let prefersSlot3 = 1;
16482let InputType = "imm";
16483let isExtendable = 1;
16484let opExtendable = 3;
16485let isExtentSigned = 1;
16486let opExtentBits = 8;
16487let opExtentAlign = 0;
16488let Constraints = "$Rx32 = $Rx32in";
16489}
16490def M2_subacc : HInst<
16491(outs IntRegs:$Rx32),
16492(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
16493"$Rx32 += sub($Rt32,$Rs32)",
16494tc_2c13e7f5, TypeM>, Enc_a568d4 {
16495let Inst{7-5} = 0b011;
16496let Inst{13-13} = 0b0;
16497let Inst{31-21} = 0b11101111000;
16498let hasNewValue = 1;
16499let opNewValue = 0;
16500let prefersSlot3 = 1;
16501let InputType = "reg";
16502let Constraints = "$Rx32 = $Rx32in";
16503}
16504def M2_vabsdiffh : HInst<
16505(outs DoubleRegs:$Rdd32),
16506(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16507"$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
16508tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16509let Inst{7-5} = 0b000;
16510let Inst{13-13} = 0b0;
16511let Inst{31-21} = 0b11101000011;
16512let prefersSlot3 = 1;
16513}
16514def M2_vabsdiffw : HInst<
16515(outs DoubleRegs:$Rdd32),
16516(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16517"$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
16518tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16519let Inst{7-5} = 0b000;
16520let Inst{13-13} = 0b0;
16521let Inst{31-21} = 0b11101000001;
16522let prefersSlot3 = 1;
16523}
16524def M2_vcmac_s0_sat_i : HInst<
16525(outs DoubleRegs:$Rxx32),
16526(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16527"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
16528tc_7f8ae742, TypeM>, Enc_88c16c {
16529let Inst{7-5} = 0b100;
16530let Inst{13-13} = 0b0;
16531let Inst{31-21} = 0b11101010010;
16532let prefersSlot3 = 1;
16533let Defs = [USR_OVF];
16534let Constraints = "$Rxx32 = $Rxx32in";
16535}
16536def M2_vcmac_s0_sat_r : HInst<
16537(outs DoubleRegs:$Rxx32),
16538(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16539"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
16540tc_7f8ae742, TypeM>, Enc_88c16c {
16541let Inst{7-5} = 0b100;
16542let Inst{13-13} = 0b0;
16543let Inst{31-21} = 0b11101010001;
16544let prefersSlot3 = 1;
16545let Defs = [USR_OVF];
16546let Constraints = "$Rxx32 = $Rxx32in";
16547}
16548def M2_vcmpy_s0_sat_i : HInst<
16549(outs DoubleRegs:$Rdd32),
16550(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16551"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
16552tc_c21d7447, TypeM>, Enc_a56825 {
16553let Inst{7-5} = 0b110;
16554let Inst{13-13} = 0b0;
16555let Inst{31-21} = 0b11101000010;
16556let prefersSlot3 = 1;
16557let Defs = [USR_OVF];
16558}
16559def M2_vcmpy_s0_sat_r : HInst<
16560(outs DoubleRegs:$Rdd32),
16561(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16562"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
16563tc_c21d7447, TypeM>, Enc_a56825 {
16564let Inst{7-5} = 0b110;
16565let Inst{13-13} = 0b0;
16566let Inst{31-21} = 0b11101000001;
16567let prefersSlot3 = 1;
16568let Defs = [USR_OVF];
16569}
16570def M2_vcmpy_s1_sat_i : HInst<
16571(outs DoubleRegs:$Rdd32),
16572(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16573"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
16574tc_c21d7447, TypeM>, Enc_a56825 {
16575let Inst{7-5} = 0b110;
16576let Inst{13-13} = 0b0;
16577let Inst{31-21} = 0b11101000110;
16578let prefersSlot3 = 1;
16579let Defs = [USR_OVF];
16580}
16581def M2_vcmpy_s1_sat_r : HInst<
16582(outs DoubleRegs:$Rdd32),
16583(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16584"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
16585tc_c21d7447, TypeM>, Enc_a56825 {
16586let Inst{7-5} = 0b110;
16587let Inst{13-13} = 0b0;
16588let Inst{31-21} = 0b11101000101;
16589let prefersSlot3 = 1;
16590let Defs = [USR_OVF];
16591}
16592def M2_vdmacs_s0 : HInst<
16593(outs DoubleRegs:$Rxx32),
16594(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16595"$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
16596tc_7f8ae742, TypeM>, Enc_88c16c {
16597let Inst{7-5} = 0b100;
16598let Inst{13-13} = 0b0;
16599let Inst{31-21} = 0b11101010000;
16600let prefersSlot3 = 1;
16601let Defs = [USR_OVF];
16602let Constraints = "$Rxx32 = $Rxx32in";
16603}
16604def M2_vdmacs_s1 : HInst<
16605(outs DoubleRegs:$Rxx32),
16606(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16607"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
16608tc_7f8ae742, TypeM>, Enc_88c16c {
16609let Inst{7-5} = 0b100;
16610let Inst{13-13} = 0b0;
16611let Inst{31-21} = 0b11101010100;
16612let prefersSlot3 = 1;
16613let Defs = [USR_OVF];
16614let Constraints = "$Rxx32 = $Rxx32in";
16615}
16616def M2_vdmpyrs_s0 : HInst<
16617(outs IntRegs:$Rd32),
16618(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16619"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
16620tc_c21d7447, TypeM>, Enc_d2216a {
16621let Inst{7-5} = 0b000;
16622let Inst{13-13} = 0b0;
16623let Inst{31-21} = 0b11101001000;
16624let hasNewValue = 1;
16625let opNewValue = 0;
16626let prefersSlot3 = 1;
16627let Defs = [USR_OVF];
16628}
16629def M2_vdmpyrs_s1 : HInst<
16630(outs IntRegs:$Rd32),
16631(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16632"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
16633tc_c21d7447, TypeM>, Enc_d2216a {
16634let Inst{7-5} = 0b000;
16635let Inst{13-13} = 0b0;
16636let Inst{31-21} = 0b11101001100;
16637let hasNewValue = 1;
16638let opNewValue = 0;
16639let prefersSlot3 = 1;
16640let Defs = [USR_OVF];
16641}
16642def M2_vdmpys_s0 : HInst<
16643(outs DoubleRegs:$Rdd32),
16644(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16645"$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
16646tc_c21d7447, TypeM>, Enc_a56825 {
16647let Inst{7-5} = 0b100;
16648let Inst{13-13} = 0b0;
16649let Inst{31-21} = 0b11101000000;
16650let prefersSlot3 = 1;
16651let Defs = [USR_OVF];
16652}
16653def M2_vdmpys_s1 : HInst<
16654(outs DoubleRegs:$Rdd32),
16655(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16656"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
16657tc_c21d7447, TypeM>, Enc_a56825 {
16658let Inst{7-5} = 0b100;
16659let Inst{13-13} = 0b0;
16660let Inst{31-21} = 0b11101000100;
16661let prefersSlot3 = 1;
16662let Defs = [USR_OVF];
16663}
16664def M2_vmac2 : HInst<
16665(outs DoubleRegs:$Rxx32),
16666(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16667"$Rxx32 += vmpyh($Rs32,$Rt32)",
16668tc_7f8ae742, TypeM>, Enc_61f0b0 {
16669let Inst{7-5} = 0b001;
16670let Inst{13-13} = 0b0;
16671let Inst{31-21} = 0b11100111001;
16672let prefersSlot3 = 1;
16673let Constraints = "$Rxx32 = $Rxx32in";
16674}
16675def M2_vmac2es : HInst<
16676(outs DoubleRegs:$Rxx32),
16677(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16678"$Rxx32 += vmpyeh($Rss32,$Rtt32)",
16679tc_7f8ae742, TypeM>, Enc_88c16c {
16680let Inst{7-5} = 0b010;
16681let Inst{13-13} = 0b0;
16682let Inst{31-21} = 0b11101010001;
16683let prefersSlot3 = 1;
16684let Constraints = "$Rxx32 = $Rxx32in";
16685}
16686def M2_vmac2es_s0 : HInst<
16687(outs DoubleRegs:$Rxx32),
16688(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16689"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
16690tc_7f8ae742, TypeM>, Enc_88c16c {
16691let Inst{7-5} = 0b110;
16692let Inst{13-13} = 0b0;
16693let Inst{31-21} = 0b11101010000;
16694let prefersSlot3 = 1;
16695let Defs = [USR_OVF];
16696let Constraints = "$Rxx32 = $Rxx32in";
16697}
16698def M2_vmac2es_s1 : HInst<
16699(outs DoubleRegs:$Rxx32),
16700(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16701"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
16702tc_7f8ae742, TypeM>, Enc_88c16c {
16703let Inst{7-5} = 0b110;
16704let Inst{13-13} = 0b0;
16705let Inst{31-21} = 0b11101010100;
16706let prefersSlot3 = 1;
16707let Defs = [USR_OVF];
16708let Constraints = "$Rxx32 = $Rxx32in";
16709}
16710def M2_vmac2s_s0 : HInst<
16711(outs DoubleRegs:$Rxx32),
16712(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16713"$Rxx32 += vmpyh($Rs32,$Rt32):sat",
16714tc_7f8ae742, TypeM>, Enc_61f0b0 {
16715let Inst{7-5} = 0b101;
16716let Inst{13-13} = 0b0;
16717let Inst{31-21} = 0b11100111000;
16718let prefersSlot3 = 1;
16719let Defs = [USR_OVF];
16720let Constraints = "$Rxx32 = $Rxx32in";
16721}
16722def M2_vmac2s_s1 : HInst<
16723(outs DoubleRegs:$Rxx32),
16724(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16725"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
16726tc_7f8ae742, TypeM>, Enc_61f0b0 {
16727let Inst{7-5} = 0b101;
16728let Inst{13-13} = 0b0;
16729let Inst{31-21} = 0b11100111100;
16730let prefersSlot3 = 1;
16731let Defs = [USR_OVF];
16732let Constraints = "$Rxx32 = $Rxx32in";
16733}
16734def M2_vmac2su_s0 : HInst<
16735(outs DoubleRegs:$Rxx32),
16736(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16737"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
16738tc_7f8ae742, TypeM>, Enc_61f0b0 {
16739let Inst{7-5} = 0b101;
16740let Inst{13-13} = 0b0;
16741let Inst{31-21} = 0b11100111011;
16742let prefersSlot3 = 1;
16743let Defs = [USR_OVF];
16744let Constraints = "$Rxx32 = $Rxx32in";
16745}
16746def M2_vmac2su_s1 : HInst<
16747(outs DoubleRegs:$Rxx32),
16748(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16749"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
16750tc_7f8ae742, TypeM>, Enc_61f0b0 {
16751let Inst{7-5} = 0b101;
16752let Inst{13-13} = 0b0;
16753let Inst{31-21} = 0b11100111111;
16754let prefersSlot3 = 1;
16755let Defs = [USR_OVF];
16756let Constraints = "$Rxx32 = $Rxx32in";
16757}
16758def M2_vmpy2es_s0 : HInst<
16759(outs DoubleRegs:$Rdd32),
16760(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16761"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
16762tc_c21d7447, TypeM>, Enc_a56825 {
16763let Inst{7-5} = 0b110;
16764let Inst{13-13} = 0b0;
16765let Inst{31-21} = 0b11101000000;
16766let prefersSlot3 = 1;
16767let Defs = [USR_OVF];
16768}
16769def M2_vmpy2es_s1 : HInst<
16770(outs DoubleRegs:$Rdd32),
16771(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16772"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
16773tc_c21d7447, TypeM>, Enc_a56825 {
16774let Inst{7-5} = 0b110;
16775let Inst{13-13} = 0b0;
16776let Inst{31-21} = 0b11101000100;
16777let prefersSlot3 = 1;
16778let Defs = [USR_OVF];
16779}
16780def M2_vmpy2s_s0 : HInst<
16781(outs DoubleRegs:$Rdd32),
16782(ins IntRegs:$Rs32, IntRegs:$Rt32),
16783"$Rdd32 = vmpyh($Rs32,$Rt32):sat",
16784tc_c21d7447, TypeM>, Enc_be32a5 {
16785let Inst{7-5} = 0b101;
16786let Inst{13-13} = 0b0;
16787let Inst{31-21} = 0b11100101000;
16788let prefersSlot3 = 1;
16789let Defs = [USR_OVF];
16790}
16791def M2_vmpy2s_s0pack : HInst<
16792(outs IntRegs:$Rd32),
16793(ins IntRegs:$Rs32, IntRegs:$Rt32),
16794"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
16795tc_c21d7447, TypeM>, Enc_5ab2be {
16796let Inst{7-5} = 0b111;
16797let Inst{13-13} = 0b0;
16798let Inst{31-21} = 0b11101101001;
16799let hasNewValue = 1;
16800let opNewValue = 0;
16801let prefersSlot3 = 1;
16802let Defs = [USR_OVF];
16803}
16804def M2_vmpy2s_s1 : HInst<
16805(outs DoubleRegs:$Rdd32),
16806(ins IntRegs:$Rs32, IntRegs:$Rt32),
16807"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
16808tc_c21d7447, TypeM>, Enc_be32a5 {
16809let Inst{7-5} = 0b101;
16810let Inst{13-13} = 0b0;
16811let Inst{31-21} = 0b11100101100;
16812let prefersSlot3 = 1;
16813let Defs = [USR_OVF];
16814}
16815def M2_vmpy2s_s1pack : HInst<
16816(outs IntRegs:$Rd32),
16817(ins IntRegs:$Rs32, IntRegs:$Rt32),
16818"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
16819tc_c21d7447, TypeM>, Enc_5ab2be {
16820let Inst{7-5} = 0b111;
16821let Inst{13-13} = 0b0;
16822let Inst{31-21} = 0b11101101101;
16823let hasNewValue = 1;
16824let opNewValue = 0;
16825let prefersSlot3 = 1;
16826let Defs = [USR_OVF];
16827}
16828def M2_vmpy2su_s0 : HInst<
16829(outs DoubleRegs:$Rdd32),
16830(ins IntRegs:$Rs32, IntRegs:$Rt32),
16831"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
16832tc_c21d7447, TypeM>, Enc_be32a5 {
16833let Inst{7-5} = 0b111;
16834let Inst{13-13} = 0b0;
16835let Inst{31-21} = 0b11100101000;
16836let prefersSlot3 = 1;
16837let Defs = [USR_OVF];
16838}
16839def M2_vmpy2su_s1 : HInst<
16840(outs DoubleRegs:$Rdd32),
16841(ins IntRegs:$Rs32, IntRegs:$Rt32),
16842"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
16843tc_c21d7447, TypeM>, Enc_be32a5 {
16844let Inst{7-5} = 0b111;
16845let Inst{13-13} = 0b0;
16846let Inst{31-21} = 0b11100101100;
16847let prefersSlot3 = 1;
16848let Defs = [USR_OVF];
16849}
16850def M2_vraddh : HInst<
16851(outs IntRegs:$Rd32),
16852(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16853"$Rd32 = vraddh($Rss32,$Rtt32)",
16854tc_c21d7447, TypeM>, Enc_d2216a {
16855let Inst{7-5} = 0b111;
16856let Inst{13-13} = 0b0;
16857let Inst{31-21} = 0b11101001001;
16858let hasNewValue = 1;
16859let opNewValue = 0;
16860let prefersSlot3 = 1;
16861}
16862def M2_vradduh : HInst<
16863(outs IntRegs:$Rd32),
16864(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16865"$Rd32 = vradduh($Rss32,$Rtt32)",
16866tc_c21d7447, TypeM>, Enc_d2216a {
16867let Inst{7-5} = 0b001;
16868let Inst{13-13} = 0b0;
16869let Inst{31-21} = 0b11101001000;
16870let hasNewValue = 1;
16871let opNewValue = 0;
16872let prefersSlot3 = 1;
16873}
16874def M2_vrcmaci_s0 : HInst<
16875(outs DoubleRegs:$Rxx32),
16876(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16877"$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
16878tc_7f8ae742, TypeM>, Enc_88c16c {
16879let Inst{7-5} = 0b000;
16880let Inst{13-13} = 0b0;
16881let Inst{31-21} = 0b11101010000;
16882let prefersSlot3 = 1;
16883let Constraints = "$Rxx32 = $Rxx32in";
16884}
16885def M2_vrcmaci_s0c : HInst<
16886(outs DoubleRegs:$Rxx32),
16887(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16888"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
16889tc_7f8ae742, TypeM>, Enc_88c16c {
16890let Inst{7-5} = 0b000;
16891let Inst{13-13} = 0b0;
16892let Inst{31-21} = 0b11101010010;
16893let prefersSlot3 = 1;
16894let Constraints = "$Rxx32 = $Rxx32in";
16895}
16896def M2_vrcmacr_s0 : HInst<
16897(outs DoubleRegs:$Rxx32),
16898(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16899"$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
16900tc_7f8ae742, TypeM>, Enc_88c16c {
16901let Inst{7-5} = 0b001;
16902let Inst{13-13} = 0b0;
16903let Inst{31-21} = 0b11101010000;
16904let prefersSlot3 = 1;
16905let Constraints = "$Rxx32 = $Rxx32in";
16906}
16907def M2_vrcmacr_s0c : HInst<
16908(outs DoubleRegs:$Rxx32),
16909(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16910"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
16911tc_7f8ae742, TypeM>, Enc_88c16c {
16912let Inst{7-5} = 0b001;
16913let Inst{13-13} = 0b0;
16914let Inst{31-21} = 0b11101010011;
16915let prefersSlot3 = 1;
16916let Constraints = "$Rxx32 = $Rxx32in";
16917}
16918def M2_vrcmpyi_s0 : HInst<
16919(outs DoubleRegs:$Rdd32),
16920(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16921"$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
16922tc_c21d7447, TypeM>, Enc_a56825 {
16923let Inst{7-5} = 0b000;
16924let Inst{13-13} = 0b0;
16925let Inst{31-21} = 0b11101000000;
16926let prefersSlot3 = 1;
16927}
16928def M2_vrcmpyi_s0c : HInst<
16929(outs DoubleRegs:$Rdd32),
16930(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16931"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
16932tc_c21d7447, TypeM>, Enc_a56825 {
16933let Inst{7-5} = 0b000;
16934let Inst{13-13} = 0b0;
16935let Inst{31-21} = 0b11101000010;
16936let prefersSlot3 = 1;
16937}
16938def M2_vrcmpyr_s0 : HInst<
16939(outs DoubleRegs:$Rdd32),
16940(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16941"$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
16942tc_c21d7447, TypeM>, Enc_a56825 {
16943let Inst{7-5} = 0b001;
16944let Inst{13-13} = 0b0;
16945let Inst{31-21} = 0b11101000000;
16946let prefersSlot3 = 1;
16947}
16948def M2_vrcmpyr_s0c : HInst<
16949(outs DoubleRegs:$Rdd32),
16950(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16951"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
16952tc_c21d7447, TypeM>, Enc_a56825 {
16953let Inst{7-5} = 0b001;
16954let Inst{13-13} = 0b0;
16955let Inst{31-21} = 0b11101000011;
16956let prefersSlot3 = 1;
16957}
16958def M2_vrcmpys_acc_s1 : HInst<
16959(outs DoubleRegs:$Rxx32),
16960(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
16961"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
16962tc_7f8ae742, TypeM> {
16963let isPseudo = 1;
16964let Constraints = "$Rxx32 = $Rxx32in";
16965}
16966def M2_vrcmpys_acc_s1_h : HInst<
16967(outs DoubleRegs:$Rxx32),
16968(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16969"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
16970tc_7f8ae742, TypeM>, Enc_88c16c {
16971let Inst{7-5} = 0b100;
16972let Inst{13-13} = 0b0;
16973let Inst{31-21} = 0b11101010101;
16974let prefersSlot3 = 1;
16975let Defs = [USR_OVF];
16976let Constraints = "$Rxx32 = $Rxx32in";
16977}
16978def M2_vrcmpys_acc_s1_l : HInst<
16979(outs DoubleRegs:$Rxx32),
16980(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16981"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
16982tc_7f8ae742, TypeM>, Enc_88c16c {
16983let Inst{7-5} = 0b100;
16984let Inst{13-13} = 0b0;
16985let Inst{31-21} = 0b11101010111;
16986let prefersSlot3 = 1;
16987let Defs = [USR_OVF];
16988let Constraints = "$Rxx32 = $Rxx32in";
16989}
16990def M2_vrcmpys_s1 : HInst<
16991(outs DoubleRegs:$Rdd32),
16992(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16993"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
16994tc_c21d7447, TypeM> {
16995let isPseudo = 1;
16996}
16997def M2_vrcmpys_s1_h : HInst<
16998(outs DoubleRegs:$Rdd32),
16999(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17000"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
17001tc_c21d7447, TypeM>, Enc_a56825 {
17002let Inst{7-5} = 0b100;
17003let Inst{13-13} = 0b0;
17004let Inst{31-21} = 0b11101000101;
17005let prefersSlot3 = 1;
17006let Defs = [USR_OVF];
17007}
17008def M2_vrcmpys_s1_l : HInst<
17009(outs DoubleRegs:$Rdd32),
17010(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17011"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17012tc_c21d7447, TypeM>, Enc_a56825 {
17013let Inst{7-5} = 0b100;
17014let Inst{13-13} = 0b0;
17015let Inst{31-21} = 0b11101000111;
17016let prefersSlot3 = 1;
17017let Defs = [USR_OVF];
17018}
17019def M2_vrcmpys_s1rp : HInst<
17020(outs IntRegs:$Rd32),
17021(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17022"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
17023tc_c21d7447, TypeM> {
17024let hasNewValue = 1;
17025let opNewValue = 0;
17026let isPseudo = 1;
17027}
17028def M2_vrcmpys_s1rp_h : HInst<
17029(outs IntRegs:$Rd32),
17030(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17031"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
17032tc_c21d7447, TypeM>, Enc_d2216a {
17033let Inst{7-5} = 0b110;
17034let Inst{13-13} = 0b0;
17035let Inst{31-21} = 0b11101001101;
17036let hasNewValue = 1;
17037let opNewValue = 0;
17038let prefersSlot3 = 1;
17039let Defs = [USR_OVF];
17040}
17041def M2_vrcmpys_s1rp_l : HInst<
17042(outs IntRegs:$Rd32),
17043(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17044"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
17045tc_c21d7447, TypeM>, Enc_d2216a {
17046let Inst{7-5} = 0b111;
17047let Inst{13-13} = 0b0;
17048let Inst{31-21} = 0b11101001101;
17049let hasNewValue = 1;
17050let opNewValue = 0;
17051let prefersSlot3 = 1;
17052let Defs = [USR_OVF];
17053}
17054def M2_vrmac_s0 : HInst<
17055(outs DoubleRegs:$Rxx32),
17056(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17057"$Rxx32 += vrmpyh($Rss32,$Rtt32)",
17058tc_7f8ae742, TypeM>, Enc_88c16c {
17059let Inst{7-5} = 0b010;
17060let Inst{13-13} = 0b0;
17061let Inst{31-21} = 0b11101010000;
17062let prefersSlot3 = 1;
17063let Constraints = "$Rxx32 = $Rxx32in";
17064}
17065def M2_vrmpy_s0 : HInst<
17066(outs DoubleRegs:$Rdd32),
17067(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17068"$Rdd32 = vrmpyh($Rss32,$Rtt32)",
17069tc_c21d7447, TypeM>, Enc_a56825 {
17070let Inst{7-5} = 0b010;
17071let Inst{13-13} = 0b0;
17072let Inst{31-21} = 0b11101000000;
17073let prefersSlot3 = 1;
17074}
17075def M2_xor_xacc : HInst<
17076(outs IntRegs:$Rx32),
17077(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17078"$Rx32 ^= xor($Rs32,$Rt32)",
17079tc_a4e22bbd, TypeM>, Enc_2ae154 {
17080let Inst{7-5} = 0b011;
17081let Inst{13-13} = 0b0;
17082let Inst{31-21} = 0b11101111100;
17083let hasNewValue = 1;
17084let opNewValue = 0;
17085let prefersSlot3 = 1;
17086let InputType = "reg";
17087let Constraints = "$Rx32 = $Rx32in";
17088}
17089def M4_and_and : HInst<
17090(outs IntRegs:$Rx32),
17091(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17092"$Rx32 &= and($Rs32,$Rt32)",
17093tc_a4e22bbd, TypeM>, Enc_2ae154 {
17094let Inst{7-5} = 0b000;
17095let Inst{13-13} = 0b0;
17096let Inst{31-21} = 0b11101111010;
17097let hasNewValue = 1;
17098let opNewValue = 0;
17099let prefersSlot3 = 1;
17100let InputType = "reg";
17101let Constraints = "$Rx32 = $Rx32in";
17102}
17103def M4_and_andn : HInst<
17104(outs IntRegs:$Rx32),
17105(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17106"$Rx32 &= and($Rs32,~$Rt32)",
17107tc_a4e22bbd, TypeM>, Enc_2ae154 {
17108let Inst{7-5} = 0b001;
17109let Inst{13-13} = 0b0;
17110let Inst{31-21} = 0b11101111001;
17111let hasNewValue = 1;
17112let opNewValue = 0;
17113let prefersSlot3 = 1;
17114let InputType = "reg";
17115let Constraints = "$Rx32 = $Rx32in";
17116}
17117def M4_and_or : HInst<
17118(outs IntRegs:$Rx32),
17119(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17120"$Rx32 &= or($Rs32,$Rt32)",
17121tc_a4e22bbd, TypeM>, Enc_2ae154 {
17122let Inst{7-5} = 0b001;
17123let Inst{13-13} = 0b0;
17124let Inst{31-21} = 0b11101111010;
17125let hasNewValue = 1;
17126let opNewValue = 0;
17127let prefersSlot3 = 1;
17128let InputType = "reg";
17129let Constraints = "$Rx32 = $Rx32in";
17130}
17131def M4_and_xor : HInst<
17132(outs IntRegs:$Rx32),
17133(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17134"$Rx32 &= xor($Rs32,$Rt32)",
17135tc_a4e22bbd, TypeM>, Enc_2ae154 {
17136let Inst{7-5} = 0b010;
17137let Inst{13-13} = 0b0;
17138let Inst{31-21} = 0b11101111010;
17139let hasNewValue = 1;
17140let opNewValue = 0;
17141let prefersSlot3 = 1;
17142let InputType = "reg";
17143let Constraints = "$Rx32 = $Rx32in";
17144}
17145def M4_cmpyi_wh : HInst<
17146(outs IntRegs:$Rd32),
17147(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17148"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
17149tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17150let Inst{7-5} = 0b100;
17151let Inst{13-13} = 0b0;
17152let Inst{31-21} = 0b11000101000;
17153let hasNewValue = 1;
17154let opNewValue = 0;
17155let prefersSlot3 = 1;
17156let Defs = [USR_OVF];
17157}
17158def M4_cmpyi_whc : HInst<
17159(outs IntRegs:$Rd32),
17160(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17161"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
17162tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17163let Inst{7-5} = 0b101;
17164let Inst{13-13} = 0b0;
17165let Inst{31-21} = 0b11000101000;
17166let hasNewValue = 1;
17167let opNewValue = 0;
17168let prefersSlot3 = 1;
17169let Defs = [USR_OVF];
17170}
17171def M4_cmpyr_wh : HInst<
17172(outs IntRegs:$Rd32),
17173(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17174"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
17175tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17176let Inst{7-5} = 0b110;
17177let Inst{13-13} = 0b0;
17178let Inst{31-21} = 0b11000101000;
17179let hasNewValue = 1;
17180let opNewValue = 0;
17181let prefersSlot3 = 1;
17182let Defs = [USR_OVF];
17183}
17184def M4_cmpyr_whc : HInst<
17185(outs IntRegs:$Rd32),
17186(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17187"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
17188tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17189let Inst{7-5} = 0b111;
17190let Inst{13-13} = 0b0;
17191let Inst{31-21} = 0b11000101000;
17192let hasNewValue = 1;
17193let opNewValue = 0;
17194let prefersSlot3 = 1;
17195let Defs = [USR_OVF];
17196}
17197def M4_mac_up_s1_sat : HInst<
17198(outs IntRegs:$Rx32),
17199(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17200"$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
17201tc_7f8ae742, TypeM>, Enc_2ae154 {
17202let Inst{7-5} = 0b000;
17203let Inst{13-13} = 0b0;
17204let Inst{31-21} = 0b11101111011;
17205let hasNewValue = 1;
17206let opNewValue = 0;
17207let prefersSlot3 = 1;
17208let Defs = [USR_OVF];
17209let InputType = "reg";
17210let Constraints = "$Rx32 = $Rx32in";
17211}
17212def M4_mpyri_addi : HInst<
17213(outs IntRegs:$Rd32),
17214(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
17215"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
17216tc_a154b476, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel {
17217let Inst{31-24} = 0b11011000;
17218let hasNewValue = 1;
17219let opNewValue = 0;
17220let prefersSlot3 = 1;
17221let CextOpcode = "M4_mpyri_addr";
17222let isExtendable = 1;
17223let opExtendable = 1;
17224let isExtentSigned = 0;
17225let opExtentBits = 6;
17226let opExtentAlign = 0;
17227}
17228def M4_mpyri_addr : HInst<
17229(outs IntRegs:$Rd32),
17230(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
17231"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
17232tc_a154b476, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel {
17233let Inst{31-23} = 0b110111111;
17234let hasNewValue = 1;
17235let opNewValue = 0;
17236let prefersSlot3 = 1;
17237let CextOpcode = "M4_mpyri_addr";
17238let InputType = "imm";
17239let isExtendable = 1;
17240let opExtendable = 3;
17241let isExtentSigned = 0;
17242let opExtentBits = 6;
17243let opExtentAlign = 0;
17244}
17245def M4_mpyri_addr_u2 : HInst<
17246(outs IntRegs:$Rd32),
17247(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
17248"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17249tc_503ce0f3, TypeALU64>, Enc_277737, Requires<[UseCompound]> {
17250let Inst{31-23} = 0b110111110;
17251let hasNewValue = 1;
17252let opNewValue = 0;
17253let prefersSlot3 = 1;
17254}
17255def M4_mpyrr_addi : HInst<
17256(outs IntRegs:$Rd32),
17257(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
17258"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17259tc_7f8ae742, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel {
17260let Inst{31-23} = 0b110101110;
17261let hasNewValue = 1;
17262let opNewValue = 0;
17263let prefersSlot3 = 1;
17264let CextOpcode = "M4_mpyrr_addr";
17265let InputType = "imm";
17266let isExtendable = 1;
17267let opExtendable = 1;
17268let isExtentSigned = 0;
17269let opExtentBits = 6;
17270let opExtentAlign = 0;
17271}
17272def M4_mpyrr_addr : HInst<
17273(outs IntRegs:$Ry32),
17274(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
17275"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17276tc_7f8ae742, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel {
17277let Inst{7-5} = 0b000;
17278let Inst{13-13} = 0b0;
17279let Inst{31-21} = 0b11100011000;
17280let hasNewValue = 1;
17281let opNewValue = 0;
17282let prefersSlot3 = 1;
17283let CextOpcode = "M4_mpyrr_addr";
17284let InputType = "reg";
17285let Constraints = "$Ry32 = $Ry32in";
17286}
17287def M4_nac_up_s1_sat : HInst<
17288(outs IntRegs:$Rx32),
17289(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17290"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
17291tc_7f8ae742, TypeM>, Enc_2ae154 {
17292let Inst{7-5} = 0b001;
17293let Inst{13-13} = 0b0;
17294let Inst{31-21} = 0b11101111011;
17295let hasNewValue = 1;
17296let opNewValue = 0;
17297let prefersSlot3 = 1;
17298let Defs = [USR_OVF];
17299let InputType = "reg";
17300let Constraints = "$Rx32 = $Rx32in";
17301}
17302def M4_or_and : HInst<
17303(outs IntRegs:$Rx32),
17304(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17305"$Rx32 |= and($Rs32,$Rt32)",
17306tc_a4e22bbd, TypeM>, Enc_2ae154 {
17307let Inst{7-5} = 0b011;
17308let Inst{13-13} = 0b0;
17309let Inst{31-21} = 0b11101111010;
17310let hasNewValue = 1;
17311let opNewValue = 0;
17312let prefersSlot3 = 1;
17313let InputType = "reg";
17314let Constraints = "$Rx32 = $Rx32in";
17315}
17316def M4_or_andn : HInst<
17317(outs IntRegs:$Rx32),
17318(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17319"$Rx32 |= and($Rs32,~$Rt32)",
17320tc_a4e22bbd, TypeM>, Enc_2ae154 {
17321let Inst{7-5} = 0b000;
17322let Inst{13-13} = 0b0;
17323let Inst{31-21} = 0b11101111001;
17324let hasNewValue = 1;
17325let opNewValue = 0;
17326let prefersSlot3 = 1;
17327let InputType = "reg";
17328let Constraints = "$Rx32 = $Rx32in";
17329}
17330def M4_or_or : HInst<
17331(outs IntRegs:$Rx32),
17332(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17333"$Rx32 |= or($Rs32,$Rt32)",
17334tc_a4e22bbd, TypeM>, Enc_2ae154 {
17335let Inst{7-5} = 0b000;
17336let Inst{13-13} = 0b0;
17337let Inst{31-21} = 0b11101111110;
17338let hasNewValue = 1;
17339let opNewValue = 0;
17340let prefersSlot3 = 1;
17341let InputType = "reg";
17342let Constraints = "$Rx32 = $Rx32in";
17343}
17344def M4_or_xor : HInst<
17345(outs IntRegs:$Rx32),
17346(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17347"$Rx32 |= xor($Rs32,$Rt32)",
17348tc_a4e22bbd, TypeM>, Enc_2ae154 {
17349let Inst{7-5} = 0b001;
17350let Inst{13-13} = 0b0;
17351let Inst{31-21} = 0b11101111110;
17352let hasNewValue = 1;
17353let opNewValue = 0;
17354let prefersSlot3 = 1;
17355let InputType = "reg";
17356let Constraints = "$Rx32 = $Rx32in";
17357}
17358def M4_pmpyw : HInst<
17359(outs DoubleRegs:$Rdd32),
17360(ins IntRegs:$Rs32, IntRegs:$Rt32),
17361"$Rdd32 = pmpyw($Rs32,$Rt32)",
17362tc_c21d7447, TypeM>, Enc_be32a5 {
17363let Inst{7-5} = 0b111;
17364let Inst{13-13} = 0b0;
17365let Inst{31-21} = 0b11100101010;
17366let prefersSlot3 = 1;
17367}
17368def M4_pmpyw_acc : HInst<
17369(outs DoubleRegs:$Rxx32),
17370(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17371"$Rxx32 ^= pmpyw($Rs32,$Rt32)",
17372tc_7f8ae742, TypeM>, Enc_61f0b0 {
17373let Inst{7-5} = 0b111;
17374let Inst{13-13} = 0b0;
17375let Inst{31-21} = 0b11100111001;
17376let prefersSlot3 = 1;
17377let Constraints = "$Rxx32 = $Rxx32in";
17378}
17379def M4_vpmpyh : HInst<
17380(outs DoubleRegs:$Rdd32),
17381(ins IntRegs:$Rs32, IntRegs:$Rt32),
17382"$Rdd32 = vpmpyh($Rs32,$Rt32)",
17383tc_c21d7447, TypeM>, Enc_be32a5 {
17384let Inst{7-5} = 0b111;
17385let Inst{13-13} = 0b0;
17386let Inst{31-21} = 0b11100101110;
17387let prefersSlot3 = 1;
17388}
17389def M4_vpmpyh_acc : HInst<
17390(outs DoubleRegs:$Rxx32),
17391(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17392"$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
17393tc_7f8ae742, TypeM>, Enc_61f0b0 {
17394let Inst{7-5} = 0b111;
17395let Inst{13-13} = 0b0;
17396let Inst{31-21} = 0b11100111101;
17397let prefersSlot3 = 1;
17398let Constraints = "$Rxx32 = $Rxx32in";
17399}
17400def M4_vrmpyeh_acc_s0 : HInst<
17401(outs DoubleRegs:$Rxx32),
17402(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17403"$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
17404tc_7f8ae742, TypeM>, Enc_88c16c {
17405let Inst{7-5} = 0b110;
17406let Inst{13-13} = 0b0;
17407let Inst{31-21} = 0b11101010001;
17408let prefersSlot3 = 1;
17409let Constraints = "$Rxx32 = $Rxx32in";
17410}
17411def M4_vrmpyeh_acc_s1 : HInst<
17412(outs DoubleRegs:$Rxx32),
17413(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17414"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
17415tc_7f8ae742, TypeM>, Enc_88c16c {
17416let Inst{7-5} = 0b110;
17417let Inst{13-13} = 0b0;
17418let Inst{31-21} = 0b11101010101;
17419let prefersSlot3 = 1;
17420let Constraints = "$Rxx32 = $Rxx32in";
17421}
17422def M4_vrmpyeh_s0 : HInst<
17423(outs DoubleRegs:$Rdd32),
17424(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17425"$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
17426tc_c21d7447, TypeM>, Enc_a56825 {
17427let Inst{7-5} = 0b100;
17428let Inst{13-13} = 0b0;
17429let Inst{31-21} = 0b11101000010;
17430let prefersSlot3 = 1;
17431}
17432def M4_vrmpyeh_s1 : HInst<
17433(outs DoubleRegs:$Rdd32),
17434(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17435"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
17436tc_c21d7447, TypeM>, Enc_a56825 {
17437let Inst{7-5} = 0b100;
17438let Inst{13-13} = 0b0;
17439let Inst{31-21} = 0b11101000110;
17440let prefersSlot3 = 1;
17441}
17442def M4_vrmpyoh_acc_s0 : HInst<
17443(outs DoubleRegs:$Rxx32),
17444(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17445"$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
17446tc_7f8ae742, TypeM>, Enc_88c16c {
17447let Inst{7-5} = 0b110;
17448let Inst{13-13} = 0b0;
17449let Inst{31-21} = 0b11101010011;
17450let prefersSlot3 = 1;
17451let Constraints = "$Rxx32 = $Rxx32in";
17452}
17453def M4_vrmpyoh_acc_s1 : HInst<
17454(outs DoubleRegs:$Rxx32),
17455(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17456"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
17457tc_7f8ae742, TypeM>, Enc_88c16c {
17458let Inst{7-5} = 0b110;
17459let Inst{13-13} = 0b0;
17460let Inst{31-21} = 0b11101010111;
17461let prefersSlot3 = 1;
17462let Constraints = "$Rxx32 = $Rxx32in";
17463}
17464def M4_vrmpyoh_s0 : HInst<
17465(outs DoubleRegs:$Rdd32),
17466(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17467"$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
17468tc_c21d7447, TypeM>, Enc_a56825 {
17469let Inst{7-5} = 0b010;
17470let Inst{13-13} = 0b0;
17471let Inst{31-21} = 0b11101000001;
17472let prefersSlot3 = 1;
17473}
17474def M4_vrmpyoh_s1 : HInst<
17475(outs DoubleRegs:$Rdd32),
17476(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17477"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
17478tc_c21d7447, TypeM>, Enc_a56825 {
17479let Inst{7-5} = 0b010;
17480let Inst{13-13} = 0b0;
17481let Inst{31-21} = 0b11101000101;
17482let prefersSlot3 = 1;
17483}
17484def M4_xor_and : HInst<
17485(outs IntRegs:$Rx32),
17486(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17487"$Rx32 ^= and($Rs32,$Rt32)",
17488tc_a4e22bbd, TypeM>, Enc_2ae154 {
17489let Inst{7-5} = 0b010;
17490let Inst{13-13} = 0b0;
17491let Inst{31-21} = 0b11101111110;
17492let hasNewValue = 1;
17493let opNewValue = 0;
17494let prefersSlot3 = 1;
17495let InputType = "reg";
17496let Constraints = "$Rx32 = $Rx32in";
17497}
17498def M4_xor_andn : HInst<
17499(outs IntRegs:$Rx32),
17500(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17501"$Rx32 ^= and($Rs32,~$Rt32)",
17502tc_a4e22bbd, TypeM>, Enc_2ae154 {
17503let Inst{7-5} = 0b010;
17504let Inst{13-13} = 0b0;
17505let Inst{31-21} = 0b11101111001;
17506let hasNewValue = 1;
17507let opNewValue = 0;
17508let prefersSlot3 = 1;
17509let InputType = "reg";
17510let Constraints = "$Rx32 = $Rx32in";
17511}
17512def M4_xor_or : HInst<
17513(outs IntRegs:$Rx32),
17514(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17515"$Rx32 ^= or($Rs32,$Rt32)",
17516tc_a4e22bbd, TypeM>, Enc_2ae154 {
17517let Inst{7-5} = 0b011;
17518let Inst{13-13} = 0b0;
17519let Inst{31-21} = 0b11101111110;
17520let hasNewValue = 1;
17521let opNewValue = 0;
17522let prefersSlot3 = 1;
17523let InputType = "reg";
17524let Constraints = "$Rx32 = $Rx32in";
17525}
17526def M4_xor_xacc : HInst<
17527(outs DoubleRegs:$Rxx32),
17528(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17529"$Rxx32 ^= xor($Rss32,$Rtt32)",
17530tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
17531let Inst{7-5} = 0b000;
17532let Inst{13-13} = 0b0;
17533let Inst{31-21} = 0b11001010100;
17534let prefersSlot3 = 1;
17535let Constraints = "$Rxx32 = $Rxx32in";
17536}
17537def M5_vdmacbsu : HInst<
17538(outs DoubleRegs:$Rxx32),
17539(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17540"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
17541tc_7f8ae742, TypeM>, Enc_88c16c {
17542let Inst{7-5} = 0b001;
17543let Inst{13-13} = 0b0;
17544let Inst{31-21} = 0b11101010001;
17545let prefersSlot3 = 1;
17546let Defs = [USR_OVF];
17547let Constraints = "$Rxx32 = $Rxx32in";
17548}
17549def M5_vdmpybsu : HInst<
17550(outs DoubleRegs:$Rdd32),
17551(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17552"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
17553tc_c21d7447, TypeM>, Enc_a56825 {
17554let Inst{7-5} = 0b001;
17555let Inst{13-13} = 0b0;
17556let Inst{31-21} = 0b11101000101;
17557let prefersSlot3 = 1;
17558let Defs = [USR_OVF];
17559}
17560def M5_vmacbsu : HInst<
17561(outs DoubleRegs:$Rxx32),
17562(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17563"$Rxx32 += vmpybsu($Rs32,$Rt32)",
17564tc_7f8ae742, TypeM>, Enc_61f0b0 {
17565let Inst{7-5} = 0b001;
17566let Inst{13-13} = 0b0;
17567let Inst{31-21} = 0b11100111110;
17568let prefersSlot3 = 1;
17569let Constraints = "$Rxx32 = $Rxx32in";
17570}
17571def M5_vmacbuu : HInst<
17572(outs DoubleRegs:$Rxx32),
17573(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17574"$Rxx32 += vmpybu($Rs32,$Rt32)",
17575tc_7f8ae742, TypeM>, Enc_61f0b0 {
17576let Inst{7-5} = 0b001;
17577let Inst{13-13} = 0b0;
17578let Inst{31-21} = 0b11100111100;
17579let prefersSlot3 = 1;
17580let Constraints = "$Rxx32 = $Rxx32in";
17581}
17582def M5_vmpybsu : HInst<
17583(outs DoubleRegs:$Rdd32),
17584(ins IntRegs:$Rs32, IntRegs:$Rt32),
17585"$Rdd32 = vmpybsu($Rs32,$Rt32)",
17586tc_c21d7447, TypeM>, Enc_be32a5 {
17587let Inst{7-5} = 0b001;
17588let Inst{13-13} = 0b0;
17589let Inst{31-21} = 0b11100101010;
17590let prefersSlot3 = 1;
17591}
17592def M5_vmpybuu : HInst<
17593(outs DoubleRegs:$Rdd32),
17594(ins IntRegs:$Rs32, IntRegs:$Rt32),
17595"$Rdd32 = vmpybu($Rs32,$Rt32)",
17596tc_c21d7447, TypeM>, Enc_be32a5 {
17597let Inst{7-5} = 0b001;
17598let Inst{13-13} = 0b0;
17599let Inst{31-21} = 0b11100101100;
17600let prefersSlot3 = 1;
17601}
17602def M5_vrmacbsu : HInst<
17603(outs DoubleRegs:$Rxx32),
17604(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17605"$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
17606tc_7f8ae742, TypeM>, Enc_88c16c {
17607let Inst{7-5} = 0b001;
17608let Inst{13-13} = 0b0;
17609let Inst{31-21} = 0b11101010110;
17610let prefersSlot3 = 1;
17611let Constraints = "$Rxx32 = $Rxx32in";
17612}
17613def M5_vrmacbuu : HInst<
17614(outs DoubleRegs:$Rxx32),
17615(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17616"$Rxx32 += vrmpybu($Rss32,$Rtt32)",
17617tc_7f8ae742, TypeM>, Enc_88c16c {
17618let Inst{7-5} = 0b001;
17619let Inst{13-13} = 0b0;
17620let Inst{31-21} = 0b11101010100;
17621let prefersSlot3 = 1;
17622let Constraints = "$Rxx32 = $Rxx32in";
17623}
17624def M5_vrmpybsu : HInst<
17625(outs DoubleRegs:$Rdd32),
17626(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17627"$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
17628tc_c21d7447, TypeM>, Enc_a56825 {
17629let Inst{7-5} = 0b001;
17630let Inst{13-13} = 0b0;
17631let Inst{31-21} = 0b11101000110;
17632let prefersSlot3 = 1;
17633}
17634def M5_vrmpybuu : HInst<
17635(outs DoubleRegs:$Rdd32),
17636(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17637"$Rdd32 = vrmpybu($Rss32,$Rtt32)",
17638tc_c21d7447, TypeM>, Enc_a56825 {
17639let Inst{7-5} = 0b001;
17640let Inst{13-13} = 0b0;
17641let Inst{31-21} = 0b11101000100;
17642let prefersSlot3 = 1;
17643}
17644def M6_vabsdiffb : HInst<
17645(outs DoubleRegs:$Rdd32),
17646(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17647"$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
17648tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17649let Inst{7-5} = 0b000;
17650let Inst{13-13} = 0b0;
17651let Inst{31-21} = 0b11101000111;
17652let prefersSlot3 = 1;
17653}
17654def M6_vabsdiffub : HInst<
17655(outs DoubleRegs:$Rdd32),
17656(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17657"$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
17658tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17659let Inst{7-5} = 0b000;
17660let Inst{13-13} = 0b0;
17661let Inst{31-21} = 0b11101000101;
17662let prefersSlot3 = 1;
17663}
17664def M7_dcmpyiw : HInst<
17665(outs DoubleRegs:$Rdd32),
17666(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17667"$Rdd32 = cmpyiw($Rss32,$Rtt32)",
17668tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17669let Inst{7-5} = 0b010;
17670let Inst{13-13} = 0b0;
17671let Inst{31-21} = 0b11101000011;
17672let prefersSlot3 = 1;
17673}
17674def M7_dcmpyiw_acc : HInst<
17675(outs DoubleRegs:$Rxx32),
17676(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17677"$Rxx32 += cmpyiw($Rss32,$Rtt32)",
17678tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17679let Inst{7-5} = 0b010;
17680let Inst{13-13} = 0b0;
17681let Inst{31-21} = 0b11101010011;
17682let prefersSlot3 = 1;
17683let Constraints = "$Rxx32 = $Rxx32in";
17684}
17685def M7_dcmpyiwc : HInst<
17686(outs DoubleRegs:$Rdd32),
17687(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17688"$Rdd32 = cmpyiw($Rss32,$Rtt32*)",
17689tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17690let Inst{7-5} = 0b010;
17691let Inst{13-13} = 0b0;
17692let Inst{31-21} = 0b11101000111;
17693let prefersSlot3 = 1;
17694}
17695def M7_dcmpyiwc_acc : HInst<
17696(outs DoubleRegs:$Rxx32),
17697(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17698"$Rxx32 += cmpyiw($Rss32,$Rtt32*)",
17699tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17700let Inst{7-5} = 0b110;
17701let Inst{13-13} = 0b0;
17702let Inst{31-21} = 0b11101010010;
17703let prefersSlot3 = 1;
17704let Constraints = "$Rxx32 = $Rxx32in";
17705}
17706def M7_dcmpyrw : HInst<
17707(outs DoubleRegs:$Rdd32),
17708(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17709"$Rdd32 = cmpyrw($Rss32,$Rtt32)",
17710tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17711let Inst{7-5} = 0b010;
17712let Inst{13-13} = 0b0;
17713let Inst{31-21} = 0b11101000100;
17714let prefersSlot3 = 1;
17715}
17716def M7_dcmpyrw_acc : HInst<
17717(outs DoubleRegs:$Rxx32),
17718(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17719"$Rxx32 += cmpyrw($Rss32,$Rtt32)",
17720tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17721let Inst{7-5} = 0b010;
17722let Inst{13-13} = 0b0;
17723let Inst{31-21} = 0b11101010100;
17724let prefersSlot3 = 1;
17725let Constraints = "$Rxx32 = $Rxx32in";
17726}
17727def M7_dcmpyrwc : HInst<
17728(outs DoubleRegs:$Rdd32),
17729(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17730"$Rdd32 = cmpyrw($Rss32,$Rtt32*)",
17731tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17732let Inst{7-5} = 0b010;
17733let Inst{13-13} = 0b0;
17734let Inst{31-21} = 0b11101000110;
17735let prefersSlot3 = 1;
17736}
17737def M7_dcmpyrwc_acc : HInst<
17738(outs DoubleRegs:$Rxx32),
17739(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17740"$Rxx32 += cmpyrw($Rss32,$Rtt32*)",
17741tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17742let Inst{7-5} = 0b010;
17743let Inst{13-13} = 0b0;
17744let Inst{31-21} = 0b11101010110;
17745let prefersSlot3 = 1;
17746let Constraints = "$Rxx32 = $Rxx32in";
17747}
17748def M7_vdmpy : HInst<
17749(outs DoubleRegs:$Rdd32),
17750(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17751"$Rdd32 = vdmpyw($Rss32,$Rtt32)",
17752tc_5a4b5e58, TypeM>, Requires<[HasV67]> {
17753let isPseudo = 1;
17754let isCodeGenOnly = 1;
17755}
17756def M7_vdmpy_acc : HInst<
17757(outs DoubleRegs:$Rxx32),
17758(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17759"$Rxx32 += vdmpyw($Rss32,$Rtt32)",
17760tc_197dce51, TypeM>, Requires<[HasV67]> {
17761let isPseudo = 1;
17762let isCodeGenOnly = 1;
17763let Constraints = "$Rxx32 = $Rxx32in";
17764}
17765def M7_wcmpyiw : HInst<
17766(outs IntRegs:$Rd32),
17767(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17768"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:sat",
17769tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17770let Inst{7-5} = 0b000;
17771let Inst{13-13} = 0b0;
17772let Inst{31-21} = 0b11101001001;
17773let hasNewValue = 1;
17774let opNewValue = 0;
17775let prefersSlot3 = 1;
17776let Defs = [USR_OVF];
17777}
17778def M7_wcmpyiw_rnd : HInst<
17779(outs IntRegs:$Rd32),
17780(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17781"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:rnd:sat",
17782tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17783let Inst{7-5} = 0b000;
17784let Inst{13-13} = 0b0;
17785let Inst{31-21} = 0b11101001101;
17786let hasNewValue = 1;
17787let opNewValue = 0;
17788let prefersSlot3 = 1;
17789let Defs = [USR_OVF];
17790}
17791def M7_wcmpyiwc : HInst<
17792(outs IntRegs:$Rd32),
17793(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17794"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:sat",
17795tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17796let Inst{7-5} = 0b100;
17797let Inst{13-13} = 0b0;
17798let Inst{31-21} = 0b11101001000;
17799let hasNewValue = 1;
17800let opNewValue = 0;
17801let prefersSlot3 = 1;
17802let Defs = [USR_OVF];
17803}
17804def M7_wcmpyiwc_rnd : HInst<
17805(outs IntRegs:$Rd32),
17806(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17807"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:rnd:sat",
17808tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17809let Inst{7-5} = 0b100;
17810let Inst{13-13} = 0b0;
17811let Inst{31-21} = 0b11101001100;
17812let hasNewValue = 1;
17813let opNewValue = 0;
17814let prefersSlot3 = 1;
17815let Defs = [USR_OVF];
17816}
17817def M7_wcmpyrw : HInst<
17818(outs IntRegs:$Rd32),
17819(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17820"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:sat",
17821tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17822let Inst{7-5} = 0b000;
17823let Inst{13-13} = 0b0;
17824let Inst{31-21} = 0b11101001010;
17825let hasNewValue = 1;
17826let opNewValue = 0;
17827let prefersSlot3 = 1;
17828let Defs = [USR_OVF];
17829}
17830def M7_wcmpyrw_rnd : HInst<
17831(outs IntRegs:$Rd32),
17832(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17833"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:rnd:sat",
17834tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17835let Inst{7-5} = 0b000;
17836let Inst{13-13} = 0b0;
17837let Inst{31-21} = 0b11101001110;
17838let hasNewValue = 1;
17839let opNewValue = 0;
17840let prefersSlot3 = 1;
17841let Defs = [USR_OVF];
17842}
17843def M7_wcmpyrwc : HInst<
17844(outs IntRegs:$Rd32),
17845(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17846"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:sat",
17847tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17848let Inst{7-5} = 0b000;
17849let Inst{13-13} = 0b0;
17850let Inst{31-21} = 0b11101001011;
17851let hasNewValue = 1;
17852let opNewValue = 0;
17853let prefersSlot3 = 1;
17854let Defs = [USR_OVF];
17855}
17856def M7_wcmpyrwc_rnd : HInst<
17857(outs IntRegs:$Rd32),
17858(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17859"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:rnd:sat",
17860tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17861let Inst{7-5} = 0b000;
17862let Inst{13-13} = 0b0;
17863let Inst{31-21} = 0b11101001111;
17864let hasNewValue = 1;
17865let opNewValue = 0;
17866let prefersSlot3 = 1;
17867let Defs = [USR_OVF];
17868}
17869def PS_loadrbabs : HInst<
17870(outs IntRegs:$Rd32),
17871(ins u32_0Imm:$Ii),
17872"$Rd32 = memb(#$Ii)",
17873tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17874let Inst{24-21} = 0b1000;
17875let Inst{31-27} = 0b01001;
17876let hasNewValue = 1;
17877let opNewValue = 0;
17878let addrMode = Absolute;
17879let accessSize = ByteAccess;
17880let mayLoad = 1;
17881let isExtended = 1;
17882let BaseOpcode = "L4_loadrb_abs";
17883let CextOpcode = "L2_loadrb";
17884let isPredicable = 1;
17885let DecoderNamespace = "MustExtend";
17886let isExtended = 1;
17887let opExtendable = 1;
17888let isExtentSigned = 0;
17889let opExtentBits = 16;
17890let opExtentAlign = 0;
17891}
17892def PS_loadrdabs : HInst<
17893(outs DoubleRegs:$Rdd32),
17894(ins u29_3Imm:$Ii),
17895"$Rdd32 = memd(#$Ii)",
17896tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
17897let Inst{24-21} = 0b1110;
17898let Inst{31-27} = 0b01001;
17899let addrMode = Absolute;
17900let accessSize = DoubleWordAccess;
17901let mayLoad = 1;
17902let isExtended = 1;
17903let BaseOpcode = "L4_loadrd_abs";
17904let CextOpcode = "L2_loadrd";
17905let isPredicable = 1;
17906let DecoderNamespace = "MustExtend";
17907let isExtended = 1;
17908let opExtendable = 1;
17909let isExtentSigned = 0;
17910let opExtentBits = 19;
17911let opExtentAlign = 3;
17912}
17913def PS_loadrhabs : HInst<
17914(outs IntRegs:$Rd32),
17915(ins u31_1Imm:$Ii),
17916"$Rd32 = memh(#$Ii)",
17917tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17918let Inst{24-21} = 0b1010;
17919let Inst{31-27} = 0b01001;
17920let hasNewValue = 1;
17921let opNewValue = 0;
17922let addrMode = Absolute;
17923let accessSize = HalfWordAccess;
17924let mayLoad = 1;
17925let isExtended = 1;
17926let BaseOpcode = "L4_loadrh_abs";
17927let CextOpcode = "L2_loadrh";
17928let isPredicable = 1;
17929let DecoderNamespace = "MustExtend";
17930let isExtended = 1;
17931let opExtendable = 1;
17932let isExtentSigned = 0;
17933let opExtentBits = 17;
17934let opExtentAlign = 1;
17935}
17936def PS_loadriabs : HInst<
17937(outs IntRegs:$Rd32),
17938(ins u30_2Imm:$Ii),
17939"$Rd32 = memw(#$Ii)",
17940tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
17941let Inst{24-21} = 0b1100;
17942let Inst{31-27} = 0b01001;
17943let hasNewValue = 1;
17944let opNewValue = 0;
17945let addrMode = Absolute;
17946let accessSize = WordAccess;
17947let mayLoad = 1;
17948let isExtended = 1;
17949let BaseOpcode = "L4_loadri_abs";
17950let CextOpcode = "L2_loadri";
17951let isPredicable = 1;
17952let DecoderNamespace = "MustExtend";
17953let isExtended = 1;
17954let opExtendable = 1;
17955let isExtentSigned = 0;
17956let opExtentBits = 18;
17957let opExtentAlign = 2;
17958}
17959def PS_loadrubabs : HInst<
17960(outs IntRegs:$Rd32),
17961(ins u32_0Imm:$Ii),
17962"$Rd32 = memub(#$Ii)",
17963tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17964let Inst{24-21} = 0b1001;
17965let Inst{31-27} = 0b01001;
17966let hasNewValue = 1;
17967let opNewValue = 0;
17968let addrMode = Absolute;
17969let accessSize = ByteAccess;
17970let mayLoad = 1;
17971let isExtended = 1;
17972let BaseOpcode = "L4_loadrub_abs";
17973let CextOpcode = "L2_loadrub";
17974let isPredicable = 1;
17975let DecoderNamespace = "MustExtend";
17976let isExtended = 1;
17977let opExtendable = 1;
17978let isExtentSigned = 0;
17979let opExtentBits = 16;
17980let opExtentAlign = 0;
17981}
17982def PS_loadruhabs : HInst<
17983(outs IntRegs:$Rd32),
17984(ins u31_1Imm:$Ii),
17985"$Rd32 = memuh(#$Ii)",
17986tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17987let Inst{24-21} = 0b1011;
17988let Inst{31-27} = 0b01001;
17989let hasNewValue = 1;
17990let opNewValue = 0;
17991let addrMode = Absolute;
17992let accessSize = HalfWordAccess;
17993let mayLoad = 1;
17994let isExtended = 1;
17995let BaseOpcode = "L4_loadruh_abs";
17996let CextOpcode = "L2_loadruh";
17997let isPredicable = 1;
17998let DecoderNamespace = "MustExtend";
17999let isExtended = 1;
18000let opExtendable = 1;
18001let isExtentSigned = 0;
18002let opExtentBits = 17;
18003let opExtentAlign = 1;
18004}
18005def PS_storerbabs : HInst<
18006(outs),
18007(ins u32_0Imm:$Ii, IntRegs:$Rt32),
18008"memb(#$Ii) = $Rt32",
18009tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
18010let Inst{24-21} = 0b0000;
18011let Inst{31-27} = 0b01001;
18012let addrMode = Absolute;
18013let accessSize = ByteAccess;
18014let isExtended = 1;
18015let mayStore = 1;
18016let BaseOpcode = "S2_storerbabs";
18017let CextOpcode = "S2_storerb";
18018let isPredicable = 1;
18019let isNVStorable = 1;
18020let DecoderNamespace = "MustExtend";
18021let isExtended = 1;
18022let opExtendable = 0;
18023let isExtentSigned = 0;
18024let opExtentBits = 16;
18025let opExtentAlign = 0;
18026}
18027def PS_storerbnewabs : HInst<
18028(outs),
18029(ins u32_0Imm:$Ii, IntRegs:$Nt8),
18030"memb(#$Ii) = $Nt8.new",
18031tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
18032let Inst{12-11} = 0b00;
18033let Inst{24-21} = 0b0101;
18034let Inst{31-27} = 0b01001;
18035let addrMode = Absolute;
18036let accessSize = ByteAccess;
18037let isNVStore = 1;
18038let isNewValue = 1;
18039let isExtended = 1;
18040let isRestrictNoSlot1Store = 1;
18041let mayStore = 1;
18042let BaseOpcode = "S2_storerbabs";
18043let CextOpcode = "S2_storerb";
18044let isPredicable = 1;
18045let DecoderNamespace = "MustExtend";
18046let isExtended = 1;
18047let opExtendable = 0;
18048let isExtentSigned = 0;
18049let opExtentBits = 16;
18050let opExtentAlign = 0;
18051let opNewValue = 1;
18052}
18053def PS_storerdabs : HInst<
18054(outs),
18055(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
18056"memd(#$Ii) = $Rtt32",
18057tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
18058let Inst{24-21} = 0b0110;
18059let Inst{31-27} = 0b01001;
18060let addrMode = Absolute;
18061let accessSize = DoubleWordAccess;
18062let isExtended = 1;
18063let mayStore = 1;
18064let BaseOpcode = "S2_storerdabs";
18065let CextOpcode = "S2_storerd";
18066let isPredicable = 1;
18067let DecoderNamespace = "MustExtend";
18068let isExtended = 1;
18069let opExtendable = 0;
18070let isExtentSigned = 0;
18071let opExtentBits = 19;
18072let opExtentAlign = 3;
18073}
18074def PS_storerfabs : HInst<
18075(outs),
18076(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18077"memh(#$Ii) = $Rt32.h",
18078tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18079let Inst{24-21} = 0b0011;
18080let Inst{31-27} = 0b01001;
18081let addrMode = Absolute;
18082let accessSize = HalfWordAccess;
18083let isExtended = 1;
18084let mayStore = 1;
18085let BaseOpcode = "S2_storerfabs";
18086let CextOpcode = "S2_storerf";
18087let isPredicable = 1;
18088let DecoderNamespace = "MustExtend";
18089let isExtended = 1;
18090let opExtendable = 0;
18091let isExtentSigned = 0;
18092let opExtentBits = 17;
18093let opExtentAlign = 1;
18094}
18095def PS_storerhabs : HInst<
18096(outs),
18097(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18098"memh(#$Ii) = $Rt32",
18099tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18100let Inst{24-21} = 0b0010;
18101let Inst{31-27} = 0b01001;
18102let addrMode = Absolute;
18103let accessSize = HalfWordAccess;
18104let isExtended = 1;
18105let mayStore = 1;
18106let BaseOpcode = "S2_storerhabs";
18107let CextOpcode = "S2_storerh";
18108let isPredicable = 1;
18109let isNVStorable = 1;
18110let DecoderNamespace = "MustExtend";
18111let isExtended = 1;
18112let opExtendable = 0;
18113let isExtentSigned = 0;
18114let opExtentBits = 17;
18115let opExtentAlign = 1;
18116}
18117def PS_storerhnewabs : HInst<
18118(outs),
18119(ins u31_1Imm:$Ii, IntRegs:$Nt8),
18120"memh(#$Ii) = $Nt8.new",
18121tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
18122let Inst{12-11} = 0b01;
18123let Inst{24-21} = 0b0101;
18124let Inst{31-27} = 0b01001;
18125let addrMode = Absolute;
18126let accessSize = HalfWordAccess;
18127let isNVStore = 1;
18128let isNewValue = 1;
18129let isExtended = 1;
18130let isRestrictNoSlot1Store = 1;
18131let mayStore = 1;
18132let BaseOpcode = "S2_storerhabs";
18133let CextOpcode = "S2_storerh";
18134let isPredicable = 1;
18135let DecoderNamespace = "MustExtend";
18136let isExtended = 1;
18137let opExtendable = 0;
18138let isExtentSigned = 0;
18139let opExtentBits = 17;
18140let opExtentAlign = 1;
18141let opNewValue = 1;
18142}
18143def PS_storeriabs : HInst<
18144(outs),
18145(ins u30_2Imm:$Ii, IntRegs:$Rt32),
18146"memw(#$Ii) = $Rt32",
18147tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
18148let Inst{24-21} = 0b0100;
18149let Inst{31-27} = 0b01001;
18150let addrMode = Absolute;
18151let accessSize = WordAccess;
18152let isExtended = 1;
18153let mayStore = 1;
18154let BaseOpcode = "S2_storeriabs";
18155let CextOpcode = "S2_storeri";
18156let isPredicable = 1;
18157let isNVStorable = 1;
18158let DecoderNamespace = "MustExtend";
18159let isExtended = 1;
18160let opExtendable = 0;
18161let isExtentSigned = 0;
18162let opExtentBits = 18;
18163let opExtentAlign = 2;
18164}
18165def PS_storerinewabs : HInst<
18166(outs),
18167(ins u30_2Imm:$Ii, IntRegs:$Nt8),
18168"memw(#$Ii) = $Nt8.new",
18169tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
18170let Inst{12-11} = 0b10;
18171let Inst{24-21} = 0b0101;
18172let Inst{31-27} = 0b01001;
18173let addrMode = Absolute;
18174let accessSize = WordAccess;
18175let isNVStore = 1;
18176let isNewValue = 1;
18177let isExtended = 1;
18178let isRestrictNoSlot1Store = 1;
18179let mayStore = 1;
18180let BaseOpcode = "S2_storeriabs";
18181let CextOpcode = "S2_storeri";
18182let isPredicable = 1;
18183let DecoderNamespace = "MustExtend";
18184let isExtended = 1;
18185let opExtendable = 0;
18186let isExtentSigned = 0;
18187let opExtentBits = 18;
18188let opExtentAlign = 2;
18189let opNewValue = 1;
18190}
18191def PS_trap1 : HInst<
18192(outs),
18193(ins u8_0Imm:$Ii),
18194"trap1(#$Ii)",
18195tc_53c851ab, TypeJ>, Enc_a51a9a, Requires<[HasPreV65]> {
18196let Inst{1-0} = 0b00;
18197let Inst{7-5} = 0b000;
18198let Inst{13-13} = 0b0;
18199let Inst{31-16} = 0b0101010010000000;
18200let isSolo = 1;
18201}
18202def S2_addasl_rrri : HInst<
18203(outs IntRegs:$Rd32),
18204(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
18205"$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
18206tc_2c13e7f5, TypeS_3op>, Enc_47ef61 {
18207let Inst{13-13} = 0b0;
18208let Inst{31-21} = 0b11000100000;
18209let hasNewValue = 1;
18210let opNewValue = 0;
18211let prefersSlot3 = 1;
18212}
18213def S2_allocframe : HInst<
18214(outs IntRegs:$Rx32),
18215(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
18216"allocframe($Rx32,#$Ii):raw",
18217tc_934753bb, TypeST>, Enc_22c845 {
18218let Inst{13-11} = 0b000;
18219let Inst{31-21} = 0b10100000100;
18220let hasNewValue = 1;
18221let opNewValue = 0;
18222let addrMode = BaseImmOffset;
18223let accessSize = DoubleWordAccess;
18224let mayStore = 1;
18225let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
18226let Defs = [R30];
18227let Constraints = "$Rx32 = $Rx32in";
18228}
18229def S2_asl_i_p : HInst<
18230(outs DoubleRegs:$Rdd32),
18231(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18232"$Rdd32 = asl($Rss32,#$Ii)",
18233tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18234let Inst{7-5} = 0b010;
18235let Inst{31-21} = 0b10000000000;
18236}
18237def S2_asl_i_p_acc : HInst<
18238(outs DoubleRegs:$Rxx32),
18239(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18240"$Rxx32 += asl($Rss32,#$Ii)",
18241tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18242let Inst{7-5} = 0b110;
18243let Inst{31-21} = 0b10000010000;
18244let prefersSlot3 = 1;
18245let Constraints = "$Rxx32 = $Rxx32in";
18246}
18247def S2_asl_i_p_and : HInst<
18248(outs DoubleRegs:$Rxx32),
18249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18250"$Rxx32 &= asl($Rss32,#$Ii)",
18251tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18252let Inst{7-5} = 0b010;
18253let Inst{31-21} = 0b10000010010;
18254let prefersSlot3 = 1;
18255let Constraints = "$Rxx32 = $Rxx32in";
18256}
18257def S2_asl_i_p_nac : HInst<
18258(outs DoubleRegs:$Rxx32),
18259(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18260"$Rxx32 -= asl($Rss32,#$Ii)",
18261tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18262let Inst{7-5} = 0b010;
18263let Inst{31-21} = 0b10000010000;
18264let prefersSlot3 = 1;
18265let Constraints = "$Rxx32 = $Rxx32in";
18266}
18267def S2_asl_i_p_or : HInst<
18268(outs DoubleRegs:$Rxx32),
18269(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18270"$Rxx32 |= asl($Rss32,#$Ii)",
18271tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18272let Inst{7-5} = 0b110;
18273let Inst{31-21} = 0b10000010010;
18274let prefersSlot3 = 1;
18275let Constraints = "$Rxx32 = $Rxx32in";
18276}
18277def S2_asl_i_p_xacc : HInst<
18278(outs DoubleRegs:$Rxx32),
18279(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18280"$Rxx32 ^= asl($Rss32,#$Ii)",
18281tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18282let Inst{7-5} = 0b010;
18283let Inst{31-21} = 0b10000010100;
18284let prefersSlot3 = 1;
18285let Constraints = "$Rxx32 = $Rxx32in";
18286}
18287def S2_asl_i_r : HInst<
18288(outs IntRegs:$Rd32),
18289(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18290"$Rd32 = asl($Rs32,#$Ii)",
18291tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18292let Inst{7-5} = 0b010;
18293let Inst{13-13} = 0b0;
18294let Inst{31-21} = 0b10001100000;
18295let hasNewValue = 1;
18296let opNewValue = 0;
18297}
18298def S2_asl_i_r_acc : HInst<
18299(outs IntRegs:$Rx32),
18300(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18301"$Rx32 += asl($Rs32,#$Ii)",
18302tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18303let Inst{7-5} = 0b110;
18304let Inst{13-13} = 0b0;
18305let Inst{31-21} = 0b10001110000;
18306let hasNewValue = 1;
18307let opNewValue = 0;
18308let prefersSlot3 = 1;
18309let Constraints = "$Rx32 = $Rx32in";
18310}
18311def S2_asl_i_r_and : HInst<
18312(outs IntRegs:$Rx32),
18313(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18314"$Rx32 &= asl($Rs32,#$Ii)",
18315tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18316let Inst{7-5} = 0b010;
18317let Inst{13-13} = 0b0;
18318let Inst{31-21} = 0b10001110010;
18319let hasNewValue = 1;
18320let opNewValue = 0;
18321let prefersSlot3 = 1;
18322let Constraints = "$Rx32 = $Rx32in";
18323}
18324def S2_asl_i_r_nac : HInst<
18325(outs IntRegs:$Rx32),
18326(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18327"$Rx32 -= asl($Rs32,#$Ii)",
18328tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18329let Inst{7-5} = 0b010;
18330let Inst{13-13} = 0b0;
18331let Inst{31-21} = 0b10001110000;
18332let hasNewValue = 1;
18333let opNewValue = 0;
18334let prefersSlot3 = 1;
18335let Constraints = "$Rx32 = $Rx32in";
18336}
18337def S2_asl_i_r_or : HInst<
18338(outs IntRegs:$Rx32),
18339(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18340"$Rx32 |= asl($Rs32,#$Ii)",
18341tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18342let Inst{7-5} = 0b110;
18343let Inst{13-13} = 0b0;
18344let Inst{31-21} = 0b10001110010;
18345let hasNewValue = 1;
18346let opNewValue = 0;
18347let prefersSlot3 = 1;
18348let Constraints = "$Rx32 = $Rx32in";
18349}
18350def S2_asl_i_r_sat : HInst<
18351(outs IntRegs:$Rd32),
18352(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18353"$Rd32 = asl($Rs32,#$Ii):sat",
18354tc_8a825db2, TypeS_2op>, Enc_a05677 {
18355let Inst{7-5} = 0b010;
18356let Inst{13-13} = 0b0;
18357let Inst{31-21} = 0b10001100010;
18358let hasNewValue = 1;
18359let opNewValue = 0;
18360let prefersSlot3 = 1;
18361let Defs = [USR_OVF];
18362}
18363def S2_asl_i_r_xacc : HInst<
18364(outs IntRegs:$Rx32),
18365(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18366"$Rx32 ^= asl($Rs32,#$Ii)",
18367tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18368let Inst{7-5} = 0b010;
18369let Inst{13-13} = 0b0;
18370let Inst{31-21} = 0b10001110100;
18371let hasNewValue = 1;
18372let opNewValue = 0;
18373let prefersSlot3 = 1;
18374let Constraints = "$Rx32 = $Rx32in";
18375}
18376def S2_asl_i_vh : HInst<
18377(outs DoubleRegs:$Rdd32),
18378(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18379"$Rdd32 = vaslh($Rss32,#$Ii)",
18380tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18381let Inst{7-5} = 0b010;
18382let Inst{13-12} = 0b00;
18383let Inst{31-21} = 0b10000000100;
18384}
18385def S2_asl_i_vw : HInst<
18386(outs DoubleRegs:$Rdd32),
18387(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18388"$Rdd32 = vaslw($Rss32,#$Ii)",
18389tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18390let Inst{7-5} = 0b010;
18391let Inst{13-13} = 0b0;
18392let Inst{31-21} = 0b10000000010;
18393}
18394def S2_asl_r_p : HInst<
18395(outs DoubleRegs:$Rdd32),
18396(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18397"$Rdd32 = asl($Rss32,$Rt32)",
18398tc_5da50c4b, TypeS_3op>, Enc_927852 {
18399let Inst{7-5} = 0b100;
18400let Inst{13-13} = 0b0;
18401let Inst{31-21} = 0b11000011100;
18402}
18403def S2_asl_r_p_acc : HInst<
18404(outs DoubleRegs:$Rxx32),
18405(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18406"$Rxx32 += asl($Rss32,$Rt32)",
18407tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18408let Inst{7-5} = 0b100;
18409let Inst{13-13} = 0b0;
18410let Inst{31-21} = 0b11001011110;
18411let prefersSlot3 = 1;
18412let Constraints = "$Rxx32 = $Rxx32in";
18413}
18414def S2_asl_r_p_and : HInst<
18415(outs DoubleRegs:$Rxx32),
18416(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18417"$Rxx32 &= asl($Rss32,$Rt32)",
18418tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18419let Inst{7-5} = 0b100;
18420let Inst{13-13} = 0b0;
18421let Inst{31-21} = 0b11001011010;
18422let prefersSlot3 = 1;
18423let Constraints = "$Rxx32 = $Rxx32in";
18424}
18425def S2_asl_r_p_nac : HInst<
18426(outs DoubleRegs:$Rxx32),
18427(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18428"$Rxx32 -= asl($Rss32,$Rt32)",
18429tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18430let Inst{7-5} = 0b100;
18431let Inst{13-13} = 0b0;
18432let Inst{31-21} = 0b11001011100;
18433let prefersSlot3 = 1;
18434let Constraints = "$Rxx32 = $Rxx32in";
18435}
18436def S2_asl_r_p_or : HInst<
18437(outs DoubleRegs:$Rxx32),
18438(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18439"$Rxx32 |= asl($Rss32,$Rt32)",
18440tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18441let Inst{7-5} = 0b100;
18442let Inst{13-13} = 0b0;
18443let Inst{31-21} = 0b11001011000;
18444let prefersSlot3 = 1;
18445let Constraints = "$Rxx32 = $Rxx32in";
18446}
18447def S2_asl_r_p_xor : HInst<
18448(outs DoubleRegs:$Rxx32),
18449(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18450"$Rxx32 ^= asl($Rss32,$Rt32)",
18451tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18452let Inst{7-5} = 0b100;
18453let Inst{13-13} = 0b0;
18454let Inst{31-21} = 0b11001011011;
18455let prefersSlot3 = 1;
18456let Constraints = "$Rxx32 = $Rxx32in";
18457}
18458def S2_asl_r_r : HInst<
18459(outs IntRegs:$Rd32),
18460(ins IntRegs:$Rs32, IntRegs:$Rt32),
18461"$Rd32 = asl($Rs32,$Rt32)",
18462tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18463let Inst{7-5} = 0b100;
18464let Inst{13-13} = 0b0;
18465let Inst{31-21} = 0b11000110010;
18466let hasNewValue = 1;
18467let opNewValue = 0;
18468}
18469def S2_asl_r_r_acc : HInst<
18470(outs IntRegs:$Rx32),
18471(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18472"$Rx32 += asl($Rs32,$Rt32)",
18473tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18474let Inst{7-5} = 0b100;
18475let Inst{13-13} = 0b0;
18476let Inst{31-21} = 0b11001100110;
18477let hasNewValue = 1;
18478let opNewValue = 0;
18479let prefersSlot3 = 1;
18480let Constraints = "$Rx32 = $Rx32in";
18481}
18482def S2_asl_r_r_and : HInst<
18483(outs IntRegs:$Rx32),
18484(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18485"$Rx32 &= asl($Rs32,$Rt32)",
18486tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18487let Inst{7-5} = 0b100;
18488let Inst{13-13} = 0b0;
18489let Inst{31-21} = 0b11001100010;
18490let hasNewValue = 1;
18491let opNewValue = 0;
18492let prefersSlot3 = 1;
18493let Constraints = "$Rx32 = $Rx32in";
18494}
18495def S2_asl_r_r_nac : HInst<
18496(outs IntRegs:$Rx32),
18497(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18498"$Rx32 -= asl($Rs32,$Rt32)",
18499tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18500let Inst{7-5} = 0b100;
18501let Inst{13-13} = 0b0;
18502let Inst{31-21} = 0b11001100100;
18503let hasNewValue = 1;
18504let opNewValue = 0;
18505let prefersSlot3 = 1;
18506let Constraints = "$Rx32 = $Rx32in";
18507}
18508def S2_asl_r_r_or : HInst<
18509(outs IntRegs:$Rx32),
18510(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18511"$Rx32 |= asl($Rs32,$Rt32)",
18512tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18513let Inst{7-5} = 0b100;
18514let Inst{13-13} = 0b0;
18515let Inst{31-21} = 0b11001100000;
18516let hasNewValue = 1;
18517let opNewValue = 0;
18518let prefersSlot3 = 1;
18519let Constraints = "$Rx32 = $Rx32in";
18520}
18521def S2_asl_r_r_sat : HInst<
18522(outs IntRegs:$Rd32),
18523(ins IntRegs:$Rs32, IntRegs:$Rt32),
18524"$Rd32 = asl($Rs32,$Rt32):sat",
18525tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18526let Inst{7-5} = 0b100;
18527let Inst{13-13} = 0b0;
18528let Inst{31-21} = 0b11000110000;
18529let hasNewValue = 1;
18530let opNewValue = 0;
18531let prefersSlot3 = 1;
18532let Defs = [USR_OVF];
18533}
18534def S2_asl_r_vh : HInst<
18535(outs DoubleRegs:$Rdd32),
18536(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18537"$Rdd32 = vaslh($Rss32,$Rt32)",
18538tc_5da50c4b, TypeS_3op>, Enc_927852 {
18539let Inst{7-5} = 0b100;
18540let Inst{13-13} = 0b0;
18541let Inst{31-21} = 0b11000011010;
18542}
18543def S2_asl_r_vw : HInst<
18544(outs DoubleRegs:$Rdd32),
18545(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18546"$Rdd32 = vaslw($Rss32,$Rt32)",
18547tc_5da50c4b, TypeS_3op>, Enc_927852 {
18548let Inst{7-5} = 0b100;
18549let Inst{13-13} = 0b0;
18550let Inst{31-21} = 0b11000011000;
18551}
18552def S2_asr_i_p : HInst<
18553(outs DoubleRegs:$Rdd32),
18554(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18555"$Rdd32 = asr($Rss32,#$Ii)",
18556tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18557let Inst{7-5} = 0b000;
18558let Inst{31-21} = 0b10000000000;
18559}
18560def S2_asr_i_p_acc : HInst<
18561(outs DoubleRegs:$Rxx32),
18562(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18563"$Rxx32 += asr($Rss32,#$Ii)",
18564tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18565let Inst{7-5} = 0b100;
18566let Inst{31-21} = 0b10000010000;
18567let prefersSlot3 = 1;
18568let Constraints = "$Rxx32 = $Rxx32in";
18569}
18570def S2_asr_i_p_and : HInst<
18571(outs DoubleRegs:$Rxx32),
18572(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18573"$Rxx32 &= asr($Rss32,#$Ii)",
18574tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18575let Inst{7-5} = 0b000;
18576let Inst{31-21} = 0b10000010010;
18577let prefersSlot3 = 1;
18578let Constraints = "$Rxx32 = $Rxx32in";
18579}
18580def S2_asr_i_p_nac : HInst<
18581(outs DoubleRegs:$Rxx32),
18582(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18583"$Rxx32 -= asr($Rss32,#$Ii)",
18584tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18585let Inst{7-5} = 0b000;
18586let Inst{31-21} = 0b10000010000;
18587let prefersSlot3 = 1;
18588let Constraints = "$Rxx32 = $Rxx32in";
18589}
18590def S2_asr_i_p_or : HInst<
18591(outs DoubleRegs:$Rxx32),
18592(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18593"$Rxx32 |= asr($Rss32,#$Ii)",
18594tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18595let Inst{7-5} = 0b100;
18596let Inst{31-21} = 0b10000010010;
18597let prefersSlot3 = 1;
18598let Constraints = "$Rxx32 = $Rxx32in";
18599}
18600def S2_asr_i_p_rnd : HInst<
18601(outs DoubleRegs:$Rdd32),
18602(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18603"$Rdd32 = asr($Rss32,#$Ii):rnd",
18604tc_0dfac0a7, TypeS_2op>, Enc_5eac98 {
18605let Inst{7-5} = 0b111;
18606let Inst{31-21} = 0b10000000110;
18607let prefersSlot3 = 1;
18608}
18609def S2_asr_i_p_rnd_goodsyntax : HInst<
18610(outs DoubleRegs:$Rdd32),
18611(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18612"$Rdd32 = asrrnd($Rss32,#$Ii)",
18613tc_0dfac0a7, TypeS_2op> {
18614let isPseudo = 1;
18615}
18616def S2_asr_i_r : HInst<
18617(outs IntRegs:$Rd32),
18618(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18619"$Rd32 = asr($Rs32,#$Ii)",
18620tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18621let Inst{7-5} = 0b000;
18622let Inst{13-13} = 0b0;
18623let Inst{31-21} = 0b10001100000;
18624let hasNewValue = 1;
18625let opNewValue = 0;
18626}
18627def S2_asr_i_r_acc : HInst<
18628(outs IntRegs:$Rx32),
18629(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18630"$Rx32 += asr($Rs32,#$Ii)",
18631tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18632let Inst{7-5} = 0b100;
18633let Inst{13-13} = 0b0;
18634let Inst{31-21} = 0b10001110000;
18635let hasNewValue = 1;
18636let opNewValue = 0;
18637let prefersSlot3 = 1;
18638let Constraints = "$Rx32 = $Rx32in";
18639}
18640def S2_asr_i_r_and : HInst<
18641(outs IntRegs:$Rx32),
18642(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18643"$Rx32 &= asr($Rs32,#$Ii)",
18644tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18645let Inst{7-5} = 0b000;
18646let Inst{13-13} = 0b0;
18647let Inst{31-21} = 0b10001110010;
18648let hasNewValue = 1;
18649let opNewValue = 0;
18650let prefersSlot3 = 1;
18651let Constraints = "$Rx32 = $Rx32in";
18652}
18653def S2_asr_i_r_nac : HInst<
18654(outs IntRegs:$Rx32),
18655(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18656"$Rx32 -= asr($Rs32,#$Ii)",
18657tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18658let Inst{7-5} = 0b000;
18659let Inst{13-13} = 0b0;
18660let Inst{31-21} = 0b10001110000;
18661let hasNewValue = 1;
18662let opNewValue = 0;
18663let prefersSlot3 = 1;
18664let Constraints = "$Rx32 = $Rx32in";
18665}
18666def S2_asr_i_r_or : HInst<
18667(outs IntRegs:$Rx32),
18668(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18669"$Rx32 |= asr($Rs32,#$Ii)",
18670tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18671let Inst{7-5} = 0b100;
18672let Inst{13-13} = 0b0;
18673let Inst{31-21} = 0b10001110010;
18674let hasNewValue = 1;
18675let opNewValue = 0;
18676let prefersSlot3 = 1;
18677let Constraints = "$Rx32 = $Rx32in";
18678}
18679def S2_asr_i_r_rnd : HInst<
18680(outs IntRegs:$Rd32),
18681(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18682"$Rd32 = asr($Rs32,#$Ii):rnd",
18683tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
18684let Inst{7-5} = 0b000;
18685let Inst{13-13} = 0b0;
18686let Inst{31-21} = 0b10001100010;
18687let hasNewValue = 1;
18688let opNewValue = 0;
18689let prefersSlot3 = 1;
18690}
18691def S2_asr_i_r_rnd_goodsyntax : HInst<
18692(outs IntRegs:$Rd32),
18693(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18694"$Rd32 = asrrnd($Rs32,#$Ii)",
18695tc_0dfac0a7, TypeS_2op> {
18696let hasNewValue = 1;
18697let opNewValue = 0;
18698let isPseudo = 1;
18699}
18700def S2_asr_i_svw_trun : HInst<
18701(outs IntRegs:$Rd32),
18702(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18703"$Rd32 = vasrw($Rss32,#$Ii)",
18704tc_f34c1c21, TypeS_2op>, Enc_8dec2e {
18705let Inst{7-5} = 0b010;
18706let Inst{13-13} = 0b0;
18707let Inst{31-21} = 0b10001000110;
18708let hasNewValue = 1;
18709let opNewValue = 0;
18710let prefersSlot3 = 1;
18711}
18712def S2_asr_i_vh : HInst<
18713(outs DoubleRegs:$Rdd32),
18714(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18715"$Rdd32 = vasrh($Rss32,#$Ii)",
18716tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18717let Inst{7-5} = 0b000;
18718let Inst{13-12} = 0b00;
18719let Inst{31-21} = 0b10000000100;
18720}
18721def S2_asr_i_vw : HInst<
18722(outs DoubleRegs:$Rdd32),
18723(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18724"$Rdd32 = vasrw($Rss32,#$Ii)",
18725tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18726let Inst{7-5} = 0b000;
18727let Inst{13-13} = 0b0;
18728let Inst{31-21} = 0b10000000010;
18729}
18730def S2_asr_r_p : HInst<
18731(outs DoubleRegs:$Rdd32),
18732(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18733"$Rdd32 = asr($Rss32,$Rt32)",
18734tc_5da50c4b, TypeS_3op>, Enc_927852 {
18735let Inst{7-5} = 0b000;
18736let Inst{13-13} = 0b0;
18737let Inst{31-21} = 0b11000011100;
18738}
18739def S2_asr_r_p_acc : HInst<
18740(outs DoubleRegs:$Rxx32),
18741(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18742"$Rxx32 += asr($Rss32,$Rt32)",
18743tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18744let Inst{7-5} = 0b000;
18745let Inst{13-13} = 0b0;
18746let Inst{31-21} = 0b11001011110;
18747let prefersSlot3 = 1;
18748let Constraints = "$Rxx32 = $Rxx32in";
18749}
18750def S2_asr_r_p_and : HInst<
18751(outs DoubleRegs:$Rxx32),
18752(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18753"$Rxx32 &= asr($Rss32,$Rt32)",
18754tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18755let Inst{7-5} = 0b000;
18756let Inst{13-13} = 0b0;
18757let Inst{31-21} = 0b11001011010;
18758let prefersSlot3 = 1;
18759let Constraints = "$Rxx32 = $Rxx32in";
18760}
18761def S2_asr_r_p_nac : HInst<
18762(outs DoubleRegs:$Rxx32),
18763(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18764"$Rxx32 -= asr($Rss32,$Rt32)",
18765tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18766let Inst{7-5} = 0b000;
18767let Inst{13-13} = 0b0;
18768let Inst{31-21} = 0b11001011100;
18769let prefersSlot3 = 1;
18770let Constraints = "$Rxx32 = $Rxx32in";
18771}
18772def S2_asr_r_p_or : HInst<
18773(outs DoubleRegs:$Rxx32),
18774(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18775"$Rxx32 |= asr($Rss32,$Rt32)",
18776tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18777let Inst{7-5} = 0b000;
18778let Inst{13-13} = 0b0;
18779let Inst{31-21} = 0b11001011000;
18780let prefersSlot3 = 1;
18781let Constraints = "$Rxx32 = $Rxx32in";
18782}
18783def S2_asr_r_p_xor : HInst<
18784(outs DoubleRegs:$Rxx32),
18785(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18786"$Rxx32 ^= asr($Rss32,$Rt32)",
18787tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18788let Inst{7-5} = 0b000;
18789let Inst{13-13} = 0b0;
18790let Inst{31-21} = 0b11001011011;
18791let prefersSlot3 = 1;
18792let Constraints = "$Rxx32 = $Rxx32in";
18793}
18794def S2_asr_r_r : HInst<
18795(outs IntRegs:$Rd32),
18796(ins IntRegs:$Rs32, IntRegs:$Rt32),
18797"$Rd32 = asr($Rs32,$Rt32)",
18798tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18799let Inst{7-5} = 0b000;
18800let Inst{13-13} = 0b0;
18801let Inst{31-21} = 0b11000110010;
18802let hasNewValue = 1;
18803let opNewValue = 0;
18804}
18805def S2_asr_r_r_acc : HInst<
18806(outs IntRegs:$Rx32),
18807(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18808"$Rx32 += asr($Rs32,$Rt32)",
18809tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18810let Inst{7-5} = 0b000;
18811let Inst{13-13} = 0b0;
18812let Inst{31-21} = 0b11001100110;
18813let hasNewValue = 1;
18814let opNewValue = 0;
18815let prefersSlot3 = 1;
18816let Constraints = "$Rx32 = $Rx32in";
18817}
18818def S2_asr_r_r_and : HInst<
18819(outs IntRegs:$Rx32),
18820(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18821"$Rx32 &= asr($Rs32,$Rt32)",
18822tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18823let Inst{7-5} = 0b000;
18824let Inst{13-13} = 0b0;
18825let Inst{31-21} = 0b11001100010;
18826let hasNewValue = 1;
18827let opNewValue = 0;
18828let prefersSlot3 = 1;
18829let Constraints = "$Rx32 = $Rx32in";
18830}
18831def S2_asr_r_r_nac : HInst<
18832(outs IntRegs:$Rx32),
18833(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18834"$Rx32 -= asr($Rs32,$Rt32)",
18835tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18836let Inst{7-5} = 0b000;
18837let Inst{13-13} = 0b0;
18838let Inst{31-21} = 0b11001100100;
18839let hasNewValue = 1;
18840let opNewValue = 0;
18841let prefersSlot3 = 1;
18842let Constraints = "$Rx32 = $Rx32in";
18843}
18844def S2_asr_r_r_or : HInst<
18845(outs IntRegs:$Rx32),
18846(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18847"$Rx32 |= asr($Rs32,$Rt32)",
18848tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18849let Inst{7-5} = 0b000;
18850let Inst{13-13} = 0b0;
18851let Inst{31-21} = 0b11001100000;
18852let hasNewValue = 1;
18853let opNewValue = 0;
18854let prefersSlot3 = 1;
18855let Constraints = "$Rx32 = $Rx32in";
18856}
18857def S2_asr_r_r_sat : HInst<
18858(outs IntRegs:$Rd32),
18859(ins IntRegs:$Rs32, IntRegs:$Rt32),
18860"$Rd32 = asr($Rs32,$Rt32):sat",
18861tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18862let Inst{7-5} = 0b000;
18863let Inst{13-13} = 0b0;
18864let Inst{31-21} = 0b11000110000;
18865let hasNewValue = 1;
18866let opNewValue = 0;
18867let prefersSlot3 = 1;
18868let Defs = [USR_OVF];
18869}
18870def S2_asr_r_svw_trun : HInst<
18871(outs IntRegs:$Rd32),
18872(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18873"$Rd32 = vasrw($Rss32,$Rt32)",
18874tc_f34c1c21, TypeS_3op>, Enc_3d5b28 {
18875let Inst{7-5} = 0b010;
18876let Inst{13-13} = 0b0;
18877let Inst{31-21} = 0b11000101000;
18878let hasNewValue = 1;
18879let opNewValue = 0;
18880let prefersSlot3 = 1;
18881}
18882def S2_asr_r_vh : HInst<
18883(outs DoubleRegs:$Rdd32),
18884(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18885"$Rdd32 = vasrh($Rss32,$Rt32)",
18886tc_5da50c4b, TypeS_3op>, Enc_927852 {
18887let Inst{7-5} = 0b000;
18888let Inst{13-13} = 0b0;
18889let Inst{31-21} = 0b11000011010;
18890}
18891def S2_asr_r_vw : HInst<
18892(outs DoubleRegs:$Rdd32),
18893(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18894"$Rdd32 = vasrw($Rss32,$Rt32)",
18895tc_5da50c4b, TypeS_3op>, Enc_927852 {
18896let Inst{7-5} = 0b000;
18897let Inst{13-13} = 0b0;
18898let Inst{31-21} = 0b11000011000;
18899}
18900def S2_brev : HInst<
18901(outs IntRegs:$Rd32),
18902(ins IntRegs:$Rs32),
18903"$Rd32 = brev($Rs32)",
18904tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18905let Inst{13-5} = 0b000000110;
18906let Inst{31-21} = 0b10001100010;
18907let hasNewValue = 1;
18908let opNewValue = 0;
18909let prefersSlot3 = 1;
18910}
18911def S2_brevp : HInst<
18912(outs DoubleRegs:$Rdd32),
18913(ins DoubleRegs:$Rss32),
18914"$Rdd32 = brev($Rss32)",
18915tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
18916let Inst{13-5} = 0b000000110;
18917let Inst{31-21} = 0b10000000110;
18918let prefersSlot3 = 1;
18919}
18920def S2_cabacdecbin : HInst<
18921(outs DoubleRegs:$Rdd32),
18922(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18923"$Rdd32 = decbin($Rss32,$Rtt32)",
18924tc_db596beb, TypeS_3op>, Enc_a56825 {
18925let Inst{7-5} = 0b110;
18926let Inst{13-13} = 0b0;
18927let Inst{31-21} = 0b11000001110;
18928let isPredicateLate = 1;
18929let prefersSlot3 = 1;
18930let Defs = [P0];
18931}
18932def S2_cl0 : HInst<
18933(outs IntRegs:$Rd32),
18934(ins IntRegs:$Rs32),
18935"$Rd32 = cl0($Rs32)",
18936tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18937let Inst{13-5} = 0b000000101;
18938let Inst{31-21} = 0b10001100000;
18939let hasNewValue = 1;
18940let opNewValue = 0;
18941let prefersSlot3 = 1;
18942}
18943def S2_cl0p : HInst<
18944(outs IntRegs:$Rd32),
18945(ins DoubleRegs:$Rss32),
18946"$Rd32 = cl0($Rss32)",
18947tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
18948let Inst{13-5} = 0b000000010;
18949let Inst{31-21} = 0b10001000010;
18950let hasNewValue = 1;
18951let opNewValue = 0;
18952let prefersSlot3 = 1;
18953}
18954def S2_cl1 : HInst<
18955(outs IntRegs:$Rd32),
18956(ins IntRegs:$Rs32),
18957"$Rd32 = cl1($Rs32)",
18958tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18959let Inst{13-5} = 0b000000110;
18960let Inst{31-21} = 0b10001100000;
18961let hasNewValue = 1;
18962let opNewValue = 0;
18963let prefersSlot3 = 1;
18964}
18965def S2_cl1p : HInst<
18966(outs IntRegs:$Rd32),
18967(ins DoubleRegs:$Rss32),
18968"$Rd32 = cl1($Rss32)",
18969tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
18970let Inst{13-5} = 0b000000100;
18971let Inst{31-21} = 0b10001000010;
18972let hasNewValue = 1;
18973let opNewValue = 0;
18974let prefersSlot3 = 1;
18975}
18976def S2_clb : HInst<
18977(outs IntRegs:$Rd32),
18978(ins IntRegs:$Rs32),
18979"$Rd32 = clb($Rs32)",
18980tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18981let Inst{13-5} = 0b000000100;
18982let Inst{31-21} = 0b10001100000;
18983let hasNewValue = 1;
18984let opNewValue = 0;
18985let prefersSlot3 = 1;
18986}
18987def S2_clbnorm : HInst<
18988(outs IntRegs:$Rd32),
18989(ins IntRegs:$Rs32),
18990"$Rd32 = normamt($Rs32)",
18991tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18992let Inst{13-5} = 0b000000111;
18993let Inst{31-21} = 0b10001100000;
18994let hasNewValue = 1;
18995let opNewValue = 0;
18996let prefersSlot3 = 1;
18997}
18998def S2_clbp : HInst<
18999(outs IntRegs:$Rd32),
19000(ins DoubleRegs:$Rss32),
19001"$Rd32 = clb($Rss32)",
19002tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19003let Inst{13-5} = 0b000000000;
19004let Inst{31-21} = 0b10001000010;
19005let hasNewValue = 1;
19006let opNewValue = 0;
19007let prefersSlot3 = 1;
19008}
19009def S2_clrbit_i : HInst<
19010(outs IntRegs:$Rd32),
19011(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19012"$Rd32 = clrbit($Rs32,#$Ii)",
19013tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19014let Inst{7-5} = 0b001;
19015let Inst{13-13} = 0b0;
19016let Inst{31-21} = 0b10001100110;
19017let hasNewValue = 1;
19018let opNewValue = 0;
19019}
19020def S2_clrbit_r : HInst<
19021(outs IntRegs:$Rd32),
19022(ins IntRegs:$Rs32, IntRegs:$Rt32),
19023"$Rd32 = clrbit($Rs32,$Rt32)",
19024tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19025let Inst{7-5} = 0b010;
19026let Inst{13-13} = 0b0;
19027let Inst{31-21} = 0b11000110100;
19028let hasNewValue = 1;
19029let opNewValue = 0;
19030}
19031def S2_ct0 : HInst<
19032(outs IntRegs:$Rd32),
19033(ins IntRegs:$Rs32),
19034"$Rd32 = ct0($Rs32)",
19035tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19036let Inst{13-5} = 0b000000100;
19037let Inst{31-21} = 0b10001100010;
19038let hasNewValue = 1;
19039let opNewValue = 0;
19040let prefersSlot3 = 1;
19041}
19042def S2_ct0p : HInst<
19043(outs IntRegs:$Rd32),
19044(ins DoubleRegs:$Rss32),
19045"$Rd32 = ct0($Rss32)",
19046tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19047let Inst{13-5} = 0b000000010;
19048let Inst{31-21} = 0b10001000111;
19049let hasNewValue = 1;
19050let opNewValue = 0;
19051let prefersSlot3 = 1;
19052}
19053def S2_ct1 : HInst<
19054(outs IntRegs:$Rd32),
19055(ins IntRegs:$Rs32),
19056"$Rd32 = ct1($Rs32)",
19057tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19058let Inst{13-5} = 0b000000101;
19059let Inst{31-21} = 0b10001100010;
19060let hasNewValue = 1;
19061let opNewValue = 0;
19062let prefersSlot3 = 1;
19063}
19064def S2_ct1p : HInst<
19065(outs IntRegs:$Rd32),
19066(ins DoubleRegs:$Rss32),
19067"$Rd32 = ct1($Rss32)",
19068tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19069let Inst{13-5} = 0b000000100;
19070let Inst{31-21} = 0b10001000111;
19071let hasNewValue = 1;
19072let opNewValue = 0;
19073let prefersSlot3 = 1;
19074}
19075def S2_deinterleave : HInst<
19076(outs DoubleRegs:$Rdd32),
19077(ins DoubleRegs:$Rss32),
19078"$Rdd32 = deinterleave($Rss32)",
19079tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19080let Inst{13-5} = 0b000000100;
19081let Inst{31-21} = 0b10000000110;
19082let prefersSlot3 = 1;
19083}
19084def S2_extractu : HInst<
19085(outs IntRegs:$Rd32),
19086(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19087"$Rd32 = extractu($Rs32,#$Ii,#$II)",
19088tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
19089let Inst{13-13} = 0b0;
19090let Inst{31-23} = 0b100011010;
19091let hasNewValue = 1;
19092let opNewValue = 0;
19093let prefersSlot3 = 1;
19094}
19095def S2_extractu_rp : HInst<
19096(outs IntRegs:$Rd32),
19097(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
19098"$Rd32 = extractu($Rs32,$Rtt32)",
19099tc_a08b630b, TypeS_3op>, Enc_e07374 {
19100let Inst{7-5} = 0b000;
19101let Inst{13-13} = 0b0;
19102let Inst{31-21} = 0b11001001000;
19103let hasNewValue = 1;
19104let opNewValue = 0;
19105let prefersSlot3 = 1;
19106}
19107def S2_extractup : HInst<
19108(outs DoubleRegs:$Rdd32),
19109(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19110"$Rdd32 = extractu($Rss32,#$Ii,#$II)",
19111tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
19112let Inst{31-24} = 0b10000001;
19113let prefersSlot3 = 1;
19114}
19115def S2_extractup_rp : HInst<
19116(outs DoubleRegs:$Rdd32),
19117(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19118"$Rdd32 = extractu($Rss32,$Rtt32)",
19119tc_a08b630b, TypeS_3op>, Enc_a56825 {
19120let Inst{7-5} = 0b000;
19121let Inst{13-13} = 0b0;
19122let Inst{31-21} = 0b11000001000;
19123let prefersSlot3 = 1;
19124}
19125def S2_insert : HInst<
19126(outs IntRegs:$Rx32),
19127(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19128"$Rx32 = insert($Rs32,#$Ii,#$II)",
19129tc_bb831a7c, TypeS_2op>, Enc_a1e29d {
19130let Inst{13-13} = 0b0;
19131let Inst{31-23} = 0b100011110;
19132let hasNewValue = 1;
19133let opNewValue = 0;
19134let prefersSlot3 = 1;
19135let Constraints = "$Rx32 = $Rx32in";
19136}
19137def S2_insert_rp : HInst<
19138(outs IntRegs:$Rx32),
19139(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19140"$Rx32 = insert($Rs32,$Rtt32)",
19141tc_a4e22bbd, TypeS_3op>, Enc_179b35 {
19142let Inst{7-5} = 0b000;
19143let Inst{13-13} = 0b0;
19144let Inst{31-21} = 0b11001000000;
19145let hasNewValue = 1;
19146let opNewValue = 0;
19147let prefersSlot3 = 1;
19148let Constraints = "$Rx32 = $Rx32in";
19149}
19150def S2_insertp : HInst<
19151(outs DoubleRegs:$Rxx32),
19152(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19153"$Rxx32 = insert($Rss32,#$Ii,#$II)",
19154tc_bb831a7c, TypeS_2op>, Enc_143a3c {
19155let Inst{31-24} = 0b10000011;
19156let prefersSlot3 = 1;
19157let Constraints = "$Rxx32 = $Rxx32in";
19158}
19159def S2_insertp_rp : HInst<
19160(outs DoubleRegs:$Rxx32),
19161(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19162"$Rxx32 = insert($Rss32,$Rtt32)",
19163tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
19164let Inst{7-5} = 0b000;
19165let Inst{13-13} = 0b0;
19166let Inst{31-21} = 0b11001010000;
19167let prefersSlot3 = 1;
19168let Constraints = "$Rxx32 = $Rxx32in";
19169}
19170def S2_interleave : HInst<
19171(outs DoubleRegs:$Rdd32),
19172(ins DoubleRegs:$Rss32),
19173"$Rdd32 = interleave($Rss32)",
19174tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19175let Inst{13-5} = 0b000000101;
19176let Inst{31-21} = 0b10000000110;
19177let prefersSlot3 = 1;
19178}
19179def S2_lfsp : HInst<
19180(outs DoubleRegs:$Rdd32),
19181(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19182"$Rdd32 = lfs($Rss32,$Rtt32)",
19183tc_a08b630b, TypeS_3op>, Enc_a56825 {
19184let Inst{7-5} = 0b110;
19185let Inst{13-13} = 0b0;
19186let Inst{31-21} = 0b11000001100;
19187let prefersSlot3 = 1;
19188}
19189def S2_lsl_r_p : HInst<
19190(outs DoubleRegs:$Rdd32),
19191(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19192"$Rdd32 = lsl($Rss32,$Rt32)",
19193tc_5da50c4b, TypeS_3op>, Enc_927852 {
19194let Inst{7-5} = 0b110;
19195let Inst{13-13} = 0b0;
19196let Inst{31-21} = 0b11000011100;
19197}
19198def S2_lsl_r_p_acc : HInst<
19199(outs DoubleRegs:$Rxx32),
19200(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19201"$Rxx32 += lsl($Rss32,$Rt32)",
19202tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19203let Inst{7-5} = 0b110;
19204let Inst{13-13} = 0b0;
19205let Inst{31-21} = 0b11001011110;
19206let prefersSlot3 = 1;
19207let Constraints = "$Rxx32 = $Rxx32in";
19208}
19209def S2_lsl_r_p_and : HInst<
19210(outs DoubleRegs:$Rxx32),
19211(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19212"$Rxx32 &= lsl($Rss32,$Rt32)",
19213tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19214let Inst{7-5} = 0b110;
19215let Inst{13-13} = 0b0;
19216let Inst{31-21} = 0b11001011010;
19217let prefersSlot3 = 1;
19218let Constraints = "$Rxx32 = $Rxx32in";
19219}
19220def S2_lsl_r_p_nac : HInst<
19221(outs DoubleRegs:$Rxx32),
19222(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19223"$Rxx32 -= lsl($Rss32,$Rt32)",
19224tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19225let Inst{7-5} = 0b110;
19226let Inst{13-13} = 0b0;
19227let Inst{31-21} = 0b11001011100;
19228let prefersSlot3 = 1;
19229let Constraints = "$Rxx32 = $Rxx32in";
19230}
19231def S2_lsl_r_p_or : HInst<
19232(outs DoubleRegs:$Rxx32),
19233(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19234"$Rxx32 |= lsl($Rss32,$Rt32)",
19235tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19236let Inst{7-5} = 0b110;
19237let Inst{13-13} = 0b0;
19238let Inst{31-21} = 0b11001011000;
19239let prefersSlot3 = 1;
19240let Constraints = "$Rxx32 = $Rxx32in";
19241}
19242def S2_lsl_r_p_xor : HInst<
19243(outs DoubleRegs:$Rxx32),
19244(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19245"$Rxx32 ^= lsl($Rss32,$Rt32)",
19246tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19247let Inst{7-5} = 0b110;
19248let Inst{13-13} = 0b0;
19249let Inst{31-21} = 0b11001011011;
19250let prefersSlot3 = 1;
19251let Constraints = "$Rxx32 = $Rxx32in";
19252}
19253def S2_lsl_r_r : HInst<
19254(outs IntRegs:$Rd32),
19255(ins IntRegs:$Rs32, IntRegs:$Rt32),
19256"$Rd32 = lsl($Rs32,$Rt32)",
19257tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19258let Inst{7-5} = 0b110;
19259let Inst{13-13} = 0b0;
19260let Inst{31-21} = 0b11000110010;
19261let hasNewValue = 1;
19262let opNewValue = 0;
19263}
19264def S2_lsl_r_r_acc : HInst<
19265(outs IntRegs:$Rx32),
19266(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19267"$Rx32 += lsl($Rs32,$Rt32)",
19268tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19269let Inst{7-5} = 0b110;
19270let Inst{13-13} = 0b0;
19271let Inst{31-21} = 0b11001100110;
19272let hasNewValue = 1;
19273let opNewValue = 0;
19274let prefersSlot3 = 1;
19275let Constraints = "$Rx32 = $Rx32in";
19276}
19277def S2_lsl_r_r_and : HInst<
19278(outs IntRegs:$Rx32),
19279(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19280"$Rx32 &= lsl($Rs32,$Rt32)",
19281tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19282let Inst{7-5} = 0b110;
19283let Inst{13-13} = 0b0;
19284let Inst{31-21} = 0b11001100010;
19285let hasNewValue = 1;
19286let opNewValue = 0;
19287let prefersSlot3 = 1;
19288let Constraints = "$Rx32 = $Rx32in";
19289}
19290def S2_lsl_r_r_nac : HInst<
19291(outs IntRegs:$Rx32),
19292(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19293"$Rx32 -= lsl($Rs32,$Rt32)",
19294tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19295let Inst{7-5} = 0b110;
19296let Inst{13-13} = 0b0;
19297let Inst{31-21} = 0b11001100100;
19298let hasNewValue = 1;
19299let opNewValue = 0;
19300let prefersSlot3 = 1;
19301let Constraints = "$Rx32 = $Rx32in";
19302}
19303def S2_lsl_r_r_or : HInst<
19304(outs IntRegs:$Rx32),
19305(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19306"$Rx32 |= lsl($Rs32,$Rt32)",
19307tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19308let Inst{7-5} = 0b110;
19309let Inst{13-13} = 0b0;
19310let Inst{31-21} = 0b11001100000;
19311let hasNewValue = 1;
19312let opNewValue = 0;
19313let prefersSlot3 = 1;
19314let Constraints = "$Rx32 = $Rx32in";
19315}
19316def S2_lsl_r_vh : HInst<
19317(outs DoubleRegs:$Rdd32),
19318(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19319"$Rdd32 = vlslh($Rss32,$Rt32)",
19320tc_5da50c4b, TypeS_3op>, Enc_927852 {
19321let Inst{7-5} = 0b110;
19322let Inst{13-13} = 0b0;
19323let Inst{31-21} = 0b11000011010;
19324}
19325def S2_lsl_r_vw : HInst<
19326(outs DoubleRegs:$Rdd32),
19327(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19328"$Rdd32 = vlslw($Rss32,$Rt32)",
19329tc_5da50c4b, TypeS_3op>, Enc_927852 {
19330let Inst{7-5} = 0b110;
19331let Inst{13-13} = 0b0;
19332let Inst{31-21} = 0b11000011000;
19333}
19334def S2_lsr_i_p : HInst<
19335(outs DoubleRegs:$Rdd32),
19336(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
19337"$Rdd32 = lsr($Rss32,#$Ii)",
19338tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
19339let Inst{7-5} = 0b001;
19340let Inst{31-21} = 0b10000000000;
19341}
19342def S2_lsr_i_p_acc : HInst<
19343(outs DoubleRegs:$Rxx32),
19344(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19345"$Rxx32 += lsr($Rss32,#$Ii)",
19346tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19347let Inst{7-5} = 0b101;
19348let Inst{31-21} = 0b10000010000;
19349let prefersSlot3 = 1;
19350let Constraints = "$Rxx32 = $Rxx32in";
19351}
19352def S2_lsr_i_p_and : HInst<
19353(outs DoubleRegs:$Rxx32),
19354(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19355"$Rxx32 &= lsr($Rss32,#$Ii)",
19356tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19357let Inst{7-5} = 0b001;
19358let Inst{31-21} = 0b10000010010;
19359let prefersSlot3 = 1;
19360let Constraints = "$Rxx32 = $Rxx32in";
19361}
19362def S2_lsr_i_p_nac : HInst<
19363(outs DoubleRegs:$Rxx32),
19364(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19365"$Rxx32 -= lsr($Rss32,#$Ii)",
19366tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19367let Inst{7-5} = 0b001;
19368let Inst{31-21} = 0b10000010000;
19369let prefersSlot3 = 1;
19370let Constraints = "$Rxx32 = $Rxx32in";
19371}
19372def S2_lsr_i_p_or : HInst<
19373(outs DoubleRegs:$Rxx32),
19374(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19375"$Rxx32 |= lsr($Rss32,#$Ii)",
19376tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19377let Inst{7-5} = 0b101;
19378let Inst{31-21} = 0b10000010010;
19379let prefersSlot3 = 1;
19380let Constraints = "$Rxx32 = $Rxx32in";
19381}
19382def S2_lsr_i_p_xacc : HInst<
19383(outs DoubleRegs:$Rxx32),
19384(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19385"$Rxx32 ^= lsr($Rss32,#$Ii)",
19386tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19387let Inst{7-5} = 0b001;
19388let Inst{31-21} = 0b10000010100;
19389let prefersSlot3 = 1;
19390let Constraints = "$Rxx32 = $Rxx32in";
19391}
19392def S2_lsr_i_r : HInst<
19393(outs IntRegs:$Rd32),
19394(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19395"$Rd32 = lsr($Rs32,#$Ii)",
19396tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19397let Inst{7-5} = 0b001;
19398let Inst{13-13} = 0b0;
19399let Inst{31-21} = 0b10001100000;
19400let hasNewValue = 1;
19401let opNewValue = 0;
19402}
19403def S2_lsr_i_r_acc : HInst<
19404(outs IntRegs:$Rx32),
19405(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19406"$Rx32 += lsr($Rs32,#$Ii)",
19407tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19408let Inst{7-5} = 0b101;
19409let Inst{13-13} = 0b0;
19410let Inst{31-21} = 0b10001110000;
19411let hasNewValue = 1;
19412let opNewValue = 0;
19413let prefersSlot3 = 1;
19414let Constraints = "$Rx32 = $Rx32in";
19415}
19416def S2_lsr_i_r_and : HInst<
19417(outs IntRegs:$Rx32),
19418(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19419"$Rx32 &= lsr($Rs32,#$Ii)",
19420tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19421let Inst{7-5} = 0b001;
19422let Inst{13-13} = 0b0;
19423let Inst{31-21} = 0b10001110010;
19424let hasNewValue = 1;
19425let opNewValue = 0;
19426let prefersSlot3 = 1;
19427let Constraints = "$Rx32 = $Rx32in";
19428}
19429def S2_lsr_i_r_nac : HInst<
19430(outs IntRegs:$Rx32),
19431(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19432"$Rx32 -= lsr($Rs32,#$Ii)",
19433tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19434let Inst{7-5} = 0b001;
19435let Inst{13-13} = 0b0;
19436let Inst{31-21} = 0b10001110000;
19437let hasNewValue = 1;
19438let opNewValue = 0;
19439let prefersSlot3 = 1;
19440let Constraints = "$Rx32 = $Rx32in";
19441}
19442def S2_lsr_i_r_or : HInst<
19443(outs IntRegs:$Rx32),
19444(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19445"$Rx32 |= lsr($Rs32,#$Ii)",
19446tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19447let Inst{7-5} = 0b101;
19448let Inst{13-13} = 0b0;
19449let Inst{31-21} = 0b10001110010;
19450let hasNewValue = 1;
19451let opNewValue = 0;
19452let prefersSlot3 = 1;
19453let Constraints = "$Rx32 = $Rx32in";
19454}
19455def S2_lsr_i_r_xacc : HInst<
19456(outs IntRegs:$Rx32),
19457(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19458"$Rx32 ^= lsr($Rs32,#$Ii)",
19459tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19460let Inst{7-5} = 0b001;
19461let Inst{13-13} = 0b0;
19462let Inst{31-21} = 0b10001110100;
19463let hasNewValue = 1;
19464let opNewValue = 0;
19465let prefersSlot3 = 1;
19466let Constraints = "$Rx32 = $Rx32in";
19467}
19468def S2_lsr_i_vh : HInst<
19469(outs DoubleRegs:$Rdd32),
19470(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
19471"$Rdd32 = vlsrh($Rss32,#$Ii)",
19472tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
19473let Inst{7-5} = 0b001;
19474let Inst{13-12} = 0b00;
19475let Inst{31-21} = 0b10000000100;
19476}
19477def S2_lsr_i_vw : HInst<
19478(outs DoubleRegs:$Rdd32),
19479(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
19480"$Rdd32 = vlsrw($Rss32,#$Ii)",
19481tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
19482let Inst{7-5} = 0b001;
19483let Inst{13-13} = 0b0;
19484let Inst{31-21} = 0b10000000010;
19485}
19486def S2_lsr_r_p : HInst<
19487(outs DoubleRegs:$Rdd32),
19488(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19489"$Rdd32 = lsr($Rss32,$Rt32)",
19490tc_5da50c4b, TypeS_3op>, Enc_927852 {
19491let Inst{7-5} = 0b010;
19492let Inst{13-13} = 0b0;
19493let Inst{31-21} = 0b11000011100;
19494}
19495def S2_lsr_r_p_acc : HInst<
19496(outs DoubleRegs:$Rxx32),
19497(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19498"$Rxx32 += lsr($Rss32,$Rt32)",
19499tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19500let Inst{7-5} = 0b010;
19501let Inst{13-13} = 0b0;
19502let Inst{31-21} = 0b11001011110;
19503let prefersSlot3 = 1;
19504let Constraints = "$Rxx32 = $Rxx32in";
19505}
19506def S2_lsr_r_p_and : HInst<
19507(outs DoubleRegs:$Rxx32),
19508(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19509"$Rxx32 &= lsr($Rss32,$Rt32)",
19510tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19511let Inst{7-5} = 0b010;
19512let Inst{13-13} = 0b0;
19513let Inst{31-21} = 0b11001011010;
19514let prefersSlot3 = 1;
19515let Constraints = "$Rxx32 = $Rxx32in";
19516}
19517def S2_lsr_r_p_nac : HInst<
19518(outs DoubleRegs:$Rxx32),
19519(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19520"$Rxx32 -= lsr($Rss32,$Rt32)",
19521tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19522let Inst{7-5} = 0b010;
19523let Inst{13-13} = 0b0;
19524let Inst{31-21} = 0b11001011100;
19525let prefersSlot3 = 1;
19526let Constraints = "$Rxx32 = $Rxx32in";
19527}
19528def S2_lsr_r_p_or : HInst<
19529(outs DoubleRegs:$Rxx32),
19530(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19531"$Rxx32 |= lsr($Rss32,$Rt32)",
19532tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19533let Inst{7-5} = 0b010;
19534let Inst{13-13} = 0b0;
19535let Inst{31-21} = 0b11001011000;
19536let prefersSlot3 = 1;
19537let Constraints = "$Rxx32 = $Rxx32in";
19538}
19539def S2_lsr_r_p_xor : HInst<
19540(outs DoubleRegs:$Rxx32),
19541(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19542"$Rxx32 ^= lsr($Rss32,$Rt32)",
19543tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19544let Inst{7-5} = 0b010;
19545let Inst{13-13} = 0b0;
19546let Inst{31-21} = 0b11001011011;
19547let prefersSlot3 = 1;
19548let Constraints = "$Rxx32 = $Rxx32in";
19549}
19550def S2_lsr_r_r : HInst<
19551(outs IntRegs:$Rd32),
19552(ins IntRegs:$Rs32, IntRegs:$Rt32),
19553"$Rd32 = lsr($Rs32,$Rt32)",
19554tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19555let Inst{7-5} = 0b010;
19556let Inst{13-13} = 0b0;
19557let Inst{31-21} = 0b11000110010;
19558let hasNewValue = 1;
19559let opNewValue = 0;
19560}
19561def S2_lsr_r_r_acc : HInst<
19562(outs IntRegs:$Rx32),
19563(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19564"$Rx32 += lsr($Rs32,$Rt32)",
19565tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19566let Inst{7-5} = 0b010;
19567let Inst{13-13} = 0b0;
19568let Inst{31-21} = 0b11001100110;
19569let hasNewValue = 1;
19570let opNewValue = 0;
19571let prefersSlot3 = 1;
19572let Constraints = "$Rx32 = $Rx32in";
19573}
19574def S2_lsr_r_r_and : HInst<
19575(outs IntRegs:$Rx32),
19576(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19577"$Rx32 &= lsr($Rs32,$Rt32)",
19578tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19579let Inst{7-5} = 0b010;
19580let Inst{13-13} = 0b0;
19581let Inst{31-21} = 0b11001100010;
19582let hasNewValue = 1;
19583let opNewValue = 0;
19584let prefersSlot3 = 1;
19585let Constraints = "$Rx32 = $Rx32in";
19586}
19587def S2_lsr_r_r_nac : HInst<
19588(outs IntRegs:$Rx32),
19589(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19590"$Rx32 -= lsr($Rs32,$Rt32)",
19591tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19592let Inst{7-5} = 0b010;
19593let Inst{13-13} = 0b0;
19594let Inst{31-21} = 0b11001100100;
19595let hasNewValue = 1;
19596let opNewValue = 0;
19597let prefersSlot3 = 1;
19598let Constraints = "$Rx32 = $Rx32in";
19599}
19600def S2_lsr_r_r_or : HInst<
19601(outs IntRegs:$Rx32),
19602(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19603"$Rx32 |= lsr($Rs32,$Rt32)",
19604tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19605let Inst{7-5} = 0b010;
19606let Inst{13-13} = 0b0;
19607let Inst{31-21} = 0b11001100000;
19608let hasNewValue = 1;
19609let opNewValue = 0;
19610let prefersSlot3 = 1;
19611let Constraints = "$Rx32 = $Rx32in";
19612}
19613def S2_lsr_r_vh : HInst<
19614(outs DoubleRegs:$Rdd32),
19615(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19616"$Rdd32 = vlsrh($Rss32,$Rt32)",
19617tc_5da50c4b, TypeS_3op>, Enc_927852 {
19618let Inst{7-5} = 0b010;
19619let Inst{13-13} = 0b0;
19620let Inst{31-21} = 0b11000011010;
19621}
19622def S2_lsr_r_vw : HInst<
19623(outs DoubleRegs:$Rdd32),
19624(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19625"$Rdd32 = vlsrw($Rss32,$Rt32)",
19626tc_5da50c4b, TypeS_3op>, Enc_927852 {
19627let Inst{7-5} = 0b010;
19628let Inst{13-13} = 0b0;
19629let Inst{31-21} = 0b11000011000;
19630}
19631def S2_mask : HInst<
19632(outs IntRegs:$Rd32),
19633(ins u5_0Imm:$Ii, u5_0Imm:$II),
19634"$Rd32 = mask(#$Ii,#$II)",
19635tc_1fcb8495, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> {
19636let Inst{13-13} = 0b1;
19637let Inst{20-16} = 0b00000;
19638let Inst{31-23} = 0b100011010;
19639let hasNewValue = 1;
19640let opNewValue = 0;
19641let prefersSlot3 = 1;
19642}
19643def S2_packhl : HInst<
19644(outs DoubleRegs:$Rdd32),
19645(ins IntRegs:$Rs32, IntRegs:$Rt32),
19646"$Rdd32 = packhl($Rs32,$Rt32)",
19647tc_713b66bf, TypeALU32_3op>, Enc_be32a5 {
19648let Inst{7-5} = 0b000;
19649let Inst{13-13} = 0b0;
19650let Inst{31-21} = 0b11110101100;
19651let InputType = "reg";
19652}
19653def S2_parityp : HInst<
19654(outs IntRegs:$Rd32),
19655(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19656"$Rd32 = parity($Rss32,$Rtt32)",
19657tc_a08b630b, TypeALU64>, Enc_d2216a {
19658let Inst{7-5} = 0b000;
19659let Inst{13-13} = 0b0;
19660let Inst{31-21} = 0b11010000000;
19661let hasNewValue = 1;
19662let opNewValue = 0;
19663let prefersSlot3 = 1;
19664}
19665def S2_pstorerbf_io : HInst<
19666(outs),
19667(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19668"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
19669tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19670let Inst{2-2} = 0b0;
19671let Inst{31-21} = 0b01000100000;
19672let isPredicated = 1;
19673let isPredicatedFalse = 1;
19674let addrMode = BaseImmOffset;
19675let accessSize = ByteAccess;
19676let mayStore = 1;
19677let BaseOpcode = "S2_storerb_io";
19678let CextOpcode = "S2_storerb";
19679let InputType = "imm";
19680let isNVStorable = 1;
19681let isExtendable = 1;
19682let opExtendable = 2;
19683let isExtentSigned = 0;
19684let opExtentBits = 6;
19685let opExtentAlign = 0;
19686}
19687def S2_pstorerbf_pi : HInst<
19688(outs IntRegs:$Rx32),
19689(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19690"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
19691tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19692let Inst{2-2} = 0b1;
19693let Inst{7-7} = 0b0;
19694let Inst{13-13} = 0b1;
19695let Inst{31-21} = 0b10101011000;
19696let isPredicated = 1;
19697let isPredicatedFalse = 1;
19698let addrMode = PostInc;
19699let accessSize = ByteAccess;
19700let mayStore = 1;
19701let BaseOpcode = "S2_storerb_pi";
19702let isNVStorable = 1;
19703let Constraints = "$Rx32 = $Rx32in";
19704}
19705def S2_pstorerbf_zomap : HInst<
19706(outs),
19707(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19708"if (!$Pv4) memb($Rs32) = $Rt32",
19709tc_8035e91f, TypeMAPPING> {
19710let isPseudo = 1;
19711let isCodeGenOnly = 1;
19712}
19713def S2_pstorerbfnew_pi : HInst<
19714(outs IntRegs:$Rx32),
19715(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19716"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19717tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19718let Inst{2-2} = 0b1;
19719let Inst{7-7} = 0b1;
19720let Inst{13-13} = 0b1;
19721let Inst{31-21} = 0b10101011000;
19722let isPredicated = 1;
19723let isPredicatedFalse = 1;
19724let addrMode = PostInc;
19725let accessSize = ByteAccess;
19726let isPredicatedNew = 1;
19727let mayStore = 1;
19728let BaseOpcode = "S2_storerb_pi";
19729let isNVStorable = 1;
19730let Constraints = "$Rx32 = $Rx32in";
19731}
19732def S2_pstorerbnewf_io : HInst<
19733(outs),
19734(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19735"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19736tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19737let Inst{2-2} = 0b0;
19738let Inst{12-11} = 0b00;
19739let Inst{31-21} = 0b01000100101;
19740let isPredicated = 1;
19741let isPredicatedFalse = 1;
19742let addrMode = BaseImmOffset;
19743let accessSize = ByteAccess;
19744let isNVStore = 1;
19745let isNewValue = 1;
19746let isRestrictNoSlot1Store = 1;
19747let mayStore = 1;
19748let BaseOpcode = "S2_storerb_io";
19749let CextOpcode = "S2_storerb";
19750let InputType = "imm";
19751let isExtendable = 1;
19752let opExtendable = 2;
19753let isExtentSigned = 0;
19754let opExtentBits = 6;
19755let opExtentAlign = 0;
19756let opNewValue = 3;
19757}
19758def S2_pstorerbnewf_pi : HInst<
19759(outs IntRegs:$Rx32),
19760(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19761"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19762tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19763let Inst{2-2} = 0b1;
19764let Inst{7-7} = 0b0;
19765let Inst{13-11} = 0b100;
19766let Inst{31-21} = 0b10101011101;
19767let isPredicated = 1;
19768let isPredicatedFalse = 1;
19769let addrMode = PostInc;
19770let accessSize = ByteAccess;
19771let isNVStore = 1;
19772let isNewValue = 1;
19773let isRestrictNoSlot1Store = 1;
19774let mayStore = 1;
19775let BaseOpcode = "S2_storerb_pi";
19776let CextOpcode = "S2_storerb";
19777let opNewValue = 4;
19778let Constraints = "$Rx32 = $Rx32in";
19779}
19780def S2_pstorerbnewf_zomap : HInst<
19781(outs),
19782(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19783"if (!$Pv4) memb($Rs32) = $Nt8.new",
19784tc_011e0e9d, TypeMAPPING> {
19785let isPseudo = 1;
19786let isCodeGenOnly = 1;
19787let opNewValue = 2;
19788}
19789def S2_pstorerbnewfnew_pi : HInst<
19790(outs IntRegs:$Rx32),
19791(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19792"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19793tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19794let Inst{2-2} = 0b1;
19795let Inst{7-7} = 0b1;
19796let Inst{13-11} = 0b100;
19797let Inst{31-21} = 0b10101011101;
19798let isPredicated = 1;
19799let isPredicatedFalse = 1;
19800let addrMode = PostInc;
19801let accessSize = ByteAccess;
19802let isNVStore = 1;
19803let isPredicatedNew = 1;
19804let isNewValue = 1;
19805let isRestrictNoSlot1Store = 1;
19806let mayStore = 1;
19807let BaseOpcode = "S2_storerb_pi";
19808let CextOpcode = "S2_storerb";
19809let opNewValue = 4;
19810let Constraints = "$Rx32 = $Rx32in";
19811}
19812def S2_pstorerbnewt_io : HInst<
19813(outs),
19814(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19815"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19816tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19817let Inst{2-2} = 0b0;
19818let Inst{12-11} = 0b00;
19819let Inst{31-21} = 0b01000000101;
19820let isPredicated = 1;
19821let addrMode = BaseImmOffset;
19822let accessSize = ByteAccess;
19823let isNVStore = 1;
19824let isNewValue = 1;
19825let isRestrictNoSlot1Store = 1;
19826let mayStore = 1;
19827let BaseOpcode = "S2_storerb_io";
19828let CextOpcode = "S2_storerb";
19829let InputType = "imm";
19830let isExtendable = 1;
19831let opExtendable = 2;
19832let isExtentSigned = 0;
19833let opExtentBits = 6;
19834let opExtentAlign = 0;
19835let opNewValue = 3;
19836}
19837def S2_pstorerbnewt_pi : HInst<
19838(outs IntRegs:$Rx32),
19839(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19840"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19841tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19842let Inst{2-2} = 0b0;
19843let Inst{7-7} = 0b0;
19844let Inst{13-11} = 0b100;
19845let Inst{31-21} = 0b10101011101;
19846let isPredicated = 1;
19847let addrMode = PostInc;
19848let accessSize = ByteAccess;
19849let isNVStore = 1;
19850let isNewValue = 1;
19851let isRestrictNoSlot1Store = 1;
19852let mayStore = 1;
19853let BaseOpcode = "S2_storerb_pi";
19854let CextOpcode = "S2_storerb";
19855let opNewValue = 4;
19856let Constraints = "$Rx32 = $Rx32in";
19857}
19858def S2_pstorerbnewt_zomap : HInst<
19859(outs),
19860(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19861"if ($Pv4) memb($Rs32) = $Nt8.new",
19862tc_011e0e9d, TypeMAPPING> {
19863let isPseudo = 1;
19864let isCodeGenOnly = 1;
19865let opNewValue = 2;
19866}
19867def S2_pstorerbnewtnew_pi : HInst<
19868(outs IntRegs:$Rx32),
19869(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19870"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19871tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19872let Inst{2-2} = 0b0;
19873let Inst{7-7} = 0b1;
19874let Inst{13-11} = 0b100;
19875let Inst{31-21} = 0b10101011101;
19876let isPredicated = 1;
19877let addrMode = PostInc;
19878let accessSize = ByteAccess;
19879let isNVStore = 1;
19880let isPredicatedNew = 1;
19881let isNewValue = 1;
19882let isRestrictNoSlot1Store = 1;
19883let mayStore = 1;
19884let BaseOpcode = "S2_storerb_pi";
19885let CextOpcode = "S2_storerb";
19886let opNewValue = 4;
19887let Constraints = "$Rx32 = $Rx32in";
19888}
19889def S2_pstorerbt_io : HInst<
19890(outs),
19891(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19892"if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
19893tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19894let Inst{2-2} = 0b0;
19895let Inst{31-21} = 0b01000000000;
19896let isPredicated = 1;
19897let addrMode = BaseImmOffset;
19898let accessSize = ByteAccess;
19899let mayStore = 1;
19900let BaseOpcode = "S2_storerb_io";
19901let CextOpcode = "S2_storerb";
19902let InputType = "imm";
19903let isNVStorable = 1;
19904let isExtendable = 1;
19905let opExtendable = 2;
19906let isExtentSigned = 0;
19907let opExtentBits = 6;
19908let opExtentAlign = 0;
19909}
19910def S2_pstorerbt_pi : HInst<
19911(outs IntRegs:$Rx32),
19912(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19913"if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
19914tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19915let Inst{2-2} = 0b0;
19916let Inst{7-7} = 0b0;
19917let Inst{13-13} = 0b1;
19918let Inst{31-21} = 0b10101011000;
19919let isPredicated = 1;
19920let addrMode = PostInc;
19921let accessSize = ByteAccess;
19922let mayStore = 1;
19923let BaseOpcode = "S2_storerb_pi";
19924let isNVStorable = 1;
19925let Constraints = "$Rx32 = $Rx32in";
19926}
19927def S2_pstorerbt_zomap : HInst<
19928(outs),
19929(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19930"if ($Pv4) memb($Rs32) = $Rt32",
19931tc_8035e91f, TypeMAPPING> {
19932let isPseudo = 1;
19933let isCodeGenOnly = 1;
19934}
19935def S2_pstorerbtnew_pi : HInst<
19936(outs IntRegs:$Rx32),
19937(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19938"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19939tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19940let Inst{2-2} = 0b0;
19941let Inst{7-7} = 0b1;
19942let Inst{13-13} = 0b1;
19943let Inst{31-21} = 0b10101011000;
19944let isPredicated = 1;
19945let addrMode = PostInc;
19946let accessSize = ByteAccess;
19947let isPredicatedNew = 1;
19948let mayStore = 1;
19949let BaseOpcode = "S2_storerb_pi";
19950let isNVStorable = 1;
19951let Constraints = "$Rx32 = $Rx32in";
19952}
19953def S2_pstorerdf_io : HInst<
19954(outs),
19955(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
19956"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
19957tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
19958let Inst{2-2} = 0b0;
19959let Inst{31-21} = 0b01000100110;
19960let isPredicated = 1;
19961let isPredicatedFalse = 1;
19962let addrMode = BaseImmOffset;
19963let accessSize = DoubleWordAccess;
19964let mayStore = 1;
19965let BaseOpcode = "S2_storerd_io";
19966let CextOpcode = "S2_storerd";
19967let InputType = "imm";
19968let isExtendable = 1;
19969let opExtendable = 2;
19970let isExtentSigned = 0;
19971let opExtentBits = 9;
19972let opExtentAlign = 3;
19973}
19974def S2_pstorerdf_pi : HInst<
19975(outs IntRegs:$Rx32),
19976(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19977"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
19978tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
19979let Inst{2-2} = 0b1;
19980let Inst{7-7} = 0b0;
19981let Inst{13-13} = 0b1;
19982let Inst{31-21} = 0b10101011110;
19983let isPredicated = 1;
19984let isPredicatedFalse = 1;
19985let addrMode = PostInc;
19986let accessSize = DoubleWordAccess;
19987let mayStore = 1;
19988let BaseOpcode = "S2_storerd_pi";
19989let CextOpcode = "S2_storerd";
19990let Constraints = "$Rx32 = $Rx32in";
19991}
19992def S2_pstorerdf_zomap : HInst<
19993(outs),
19994(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19995"if (!$Pv4) memd($Rs32) = $Rtt32",
19996tc_8035e91f, TypeMAPPING> {
19997let isPseudo = 1;
19998let isCodeGenOnly = 1;
19999}
20000def S2_pstorerdfnew_pi : HInst<
20001(outs IntRegs:$Rx32),
20002(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20003"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20004tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20005let Inst{2-2} = 0b1;
20006let Inst{7-7} = 0b1;
20007let Inst{13-13} = 0b1;
20008let Inst{31-21} = 0b10101011110;
20009let isPredicated = 1;
20010let isPredicatedFalse = 1;
20011let addrMode = PostInc;
20012let accessSize = DoubleWordAccess;
20013let isPredicatedNew = 1;
20014let mayStore = 1;
20015let BaseOpcode = "S2_storerd_pi";
20016let CextOpcode = "S2_storerd";
20017let Constraints = "$Rx32 = $Rx32in";
20018}
20019def S2_pstorerdt_io : HInst<
20020(outs),
20021(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20022"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
20023tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20024let Inst{2-2} = 0b0;
20025let Inst{31-21} = 0b01000000110;
20026let isPredicated = 1;
20027let addrMode = BaseImmOffset;
20028let accessSize = DoubleWordAccess;
20029let mayStore = 1;
20030let BaseOpcode = "S2_storerd_io";
20031let CextOpcode = "S2_storerd";
20032let InputType = "imm";
20033let isExtendable = 1;
20034let opExtendable = 2;
20035let isExtentSigned = 0;
20036let opExtentBits = 9;
20037let opExtentAlign = 3;
20038}
20039def S2_pstorerdt_pi : HInst<
20040(outs IntRegs:$Rx32),
20041(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20042"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
20043tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20044let Inst{2-2} = 0b0;
20045let Inst{7-7} = 0b0;
20046let Inst{13-13} = 0b1;
20047let Inst{31-21} = 0b10101011110;
20048let isPredicated = 1;
20049let addrMode = PostInc;
20050let accessSize = DoubleWordAccess;
20051let mayStore = 1;
20052let BaseOpcode = "S2_storerd_pi";
20053let CextOpcode = "S2_storerd";
20054let Constraints = "$Rx32 = $Rx32in";
20055}
20056def S2_pstorerdt_zomap : HInst<
20057(outs),
20058(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20059"if ($Pv4) memd($Rs32) = $Rtt32",
20060tc_8035e91f, TypeMAPPING> {
20061let isPseudo = 1;
20062let isCodeGenOnly = 1;
20063}
20064def S2_pstorerdtnew_pi : HInst<
20065(outs IntRegs:$Rx32),
20066(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20067"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20068tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20069let Inst{2-2} = 0b0;
20070let Inst{7-7} = 0b1;
20071let Inst{13-13} = 0b1;
20072let Inst{31-21} = 0b10101011110;
20073let isPredicated = 1;
20074let addrMode = PostInc;
20075let accessSize = DoubleWordAccess;
20076let isPredicatedNew = 1;
20077let mayStore = 1;
20078let BaseOpcode = "S2_storerd_pi";
20079let CextOpcode = "S2_storerd";
20080let Constraints = "$Rx32 = $Rx32in";
20081}
20082def S2_pstorerff_io : HInst<
20083(outs),
20084(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20085"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20086tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20087let Inst{2-2} = 0b0;
20088let Inst{31-21} = 0b01000100011;
20089let isPredicated = 1;
20090let isPredicatedFalse = 1;
20091let addrMode = BaseImmOffset;
20092let accessSize = HalfWordAccess;
20093let mayStore = 1;
20094let BaseOpcode = "S2_storerf_io";
20095let CextOpcode = "S2_storerf";
20096let InputType = "imm";
20097let isExtendable = 1;
20098let opExtendable = 2;
20099let isExtentSigned = 0;
20100let opExtentBits = 7;
20101let opExtentAlign = 1;
20102}
20103def S2_pstorerff_pi : HInst<
20104(outs IntRegs:$Rx32),
20105(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20106"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20107tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20108let Inst{2-2} = 0b1;
20109let Inst{7-7} = 0b0;
20110let Inst{13-13} = 0b1;
20111let Inst{31-21} = 0b10101011011;
20112let isPredicated = 1;
20113let isPredicatedFalse = 1;
20114let addrMode = PostInc;
20115let accessSize = HalfWordAccess;
20116let mayStore = 1;
20117let BaseOpcode = "S2_storerf_pi";
20118let CextOpcode = "S2_storerf";
20119let Constraints = "$Rx32 = $Rx32in";
20120}
20121def S2_pstorerff_zomap : HInst<
20122(outs),
20123(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20124"if (!$Pv4) memh($Rs32) = $Rt32.h",
20125tc_8035e91f, TypeMAPPING> {
20126let isPseudo = 1;
20127let isCodeGenOnly = 1;
20128}
20129def S2_pstorerffnew_pi : HInst<
20130(outs IntRegs:$Rx32),
20131(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20132"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20133tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20134let Inst{2-2} = 0b1;
20135let Inst{7-7} = 0b1;
20136let Inst{13-13} = 0b1;
20137let Inst{31-21} = 0b10101011011;
20138let isPredicated = 1;
20139let isPredicatedFalse = 1;
20140let addrMode = PostInc;
20141let accessSize = HalfWordAccess;
20142let isPredicatedNew = 1;
20143let mayStore = 1;
20144let BaseOpcode = "S2_storerf_pi";
20145let CextOpcode = "S2_storerf";
20146let Constraints = "$Rx32 = $Rx32in";
20147}
20148def S2_pstorerft_io : HInst<
20149(outs),
20150(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20151"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20152tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20153let Inst{2-2} = 0b0;
20154let Inst{31-21} = 0b01000000011;
20155let isPredicated = 1;
20156let addrMode = BaseImmOffset;
20157let accessSize = HalfWordAccess;
20158let mayStore = 1;
20159let BaseOpcode = "S2_storerf_io";
20160let CextOpcode = "S2_storerf";
20161let InputType = "imm";
20162let isExtendable = 1;
20163let opExtendable = 2;
20164let isExtentSigned = 0;
20165let opExtentBits = 7;
20166let opExtentAlign = 1;
20167}
20168def S2_pstorerft_pi : HInst<
20169(outs IntRegs:$Rx32),
20170(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20171"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20172tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20173let Inst{2-2} = 0b0;
20174let Inst{7-7} = 0b0;
20175let Inst{13-13} = 0b1;
20176let Inst{31-21} = 0b10101011011;
20177let isPredicated = 1;
20178let addrMode = PostInc;
20179let accessSize = HalfWordAccess;
20180let mayStore = 1;
20181let BaseOpcode = "S2_storerf_pi";
20182let CextOpcode = "S2_storerf";
20183let Constraints = "$Rx32 = $Rx32in";
20184}
20185def S2_pstorerft_zomap : HInst<
20186(outs),
20187(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20188"if ($Pv4) memh($Rs32) = $Rt32.h",
20189tc_8035e91f, TypeMAPPING> {
20190let isPseudo = 1;
20191let isCodeGenOnly = 1;
20192}
20193def S2_pstorerftnew_pi : HInst<
20194(outs IntRegs:$Rx32),
20195(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20196"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20197tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20198let Inst{2-2} = 0b0;
20199let Inst{7-7} = 0b1;
20200let Inst{13-13} = 0b1;
20201let Inst{31-21} = 0b10101011011;
20202let isPredicated = 1;
20203let addrMode = PostInc;
20204let accessSize = HalfWordAccess;
20205let isPredicatedNew = 1;
20206let mayStore = 1;
20207let BaseOpcode = "S2_storerf_pi";
20208let CextOpcode = "S2_storerf";
20209let Constraints = "$Rx32 = $Rx32in";
20210}
20211def S2_pstorerhf_io : HInst<
20212(outs),
20213(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20214"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
20215tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20216let Inst{2-2} = 0b0;
20217let Inst{31-21} = 0b01000100010;
20218let isPredicated = 1;
20219let isPredicatedFalse = 1;
20220let addrMode = BaseImmOffset;
20221let accessSize = HalfWordAccess;
20222let mayStore = 1;
20223let BaseOpcode = "S2_storerh_io";
20224let CextOpcode = "S2_storerh";
20225let InputType = "imm";
20226let isNVStorable = 1;
20227let isExtendable = 1;
20228let opExtendable = 2;
20229let isExtentSigned = 0;
20230let opExtentBits = 7;
20231let opExtentAlign = 1;
20232}
20233def S2_pstorerhf_pi : HInst<
20234(outs IntRegs:$Rx32),
20235(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20236"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
20237tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20238let Inst{2-2} = 0b1;
20239let Inst{7-7} = 0b0;
20240let Inst{13-13} = 0b1;
20241let Inst{31-21} = 0b10101011010;
20242let isPredicated = 1;
20243let isPredicatedFalse = 1;
20244let addrMode = PostInc;
20245let accessSize = HalfWordAccess;
20246let mayStore = 1;
20247let BaseOpcode = "S2_storerh_pi";
20248let isNVStorable = 1;
20249let Constraints = "$Rx32 = $Rx32in";
20250}
20251def S2_pstorerhf_zomap : HInst<
20252(outs),
20253(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20254"if (!$Pv4) memh($Rs32) = $Rt32",
20255tc_8035e91f, TypeMAPPING> {
20256let isPseudo = 1;
20257let isCodeGenOnly = 1;
20258}
20259def S2_pstorerhfnew_pi : HInst<
20260(outs IntRegs:$Rx32),
20261(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20262"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20263tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20264let Inst{2-2} = 0b1;
20265let Inst{7-7} = 0b1;
20266let Inst{13-13} = 0b1;
20267let Inst{31-21} = 0b10101011010;
20268let isPredicated = 1;
20269let isPredicatedFalse = 1;
20270let addrMode = PostInc;
20271let accessSize = HalfWordAccess;
20272let isPredicatedNew = 1;
20273let mayStore = 1;
20274let BaseOpcode = "S2_storerh_pi";
20275let isNVStorable = 1;
20276let Constraints = "$Rx32 = $Rx32in";
20277}
20278def S2_pstorerhnewf_io : HInst<
20279(outs),
20280(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20281"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20282tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20283let Inst{2-2} = 0b0;
20284let Inst{12-11} = 0b01;
20285let Inst{31-21} = 0b01000100101;
20286let isPredicated = 1;
20287let isPredicatedFalse = 1;
20288let addrMode = BaseImmOffset;
20289let accessSize = HalfWordAccess;
20290let isNVStore = 1;
20291let isNewValue = 1;
20292let isRestrictNoSlot1Store = 1;
20293let mayStore = 1;
20294let BaseOpcode = "S2_storerh_io";
20295let CextOpcode = "S2_storerh";
20296let InputType = "imm";
20297let isExtendable = 1;
20298let opExtendable = 2;
20299let isExtentSigned = 0;
20300let opExtentBits = 7;
20301let opExtentAlign = 1;
20302let opNewValue = 3;
20303}
20304def S2_pstorerhnewf_pi : HInst<
20305(outs IntRegs:$Rx32),
20306(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20307"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20308tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20309let Inst{2-2} = 0b1;
20310let Inst{7-7} = 0b0;
20311let Inst{13-11} = 0b101;
20312let Inst{31-21} = 0b10101011101;
20313let isPredicated = 1;
20314let isPredicatedFalse = 1;
20315let addrMode = PostInc;
20316let accessSize = HalfWordAccess;
20317let isNVStore = 1;
20318let isNewValue = 1;
20319let isRestrictNoSlot1Store = 1;
20320let mayStore = 1;
20321let BaseOpcode = "S2_storerh_pi";
20322let CextOpcode = "S2_storerh";
20323let opNewValue = 4;
20324let Constraints = "$Rx32 = $Rx32in";
20325}
20326def S2_pstorerhnewf_zomap : HInst<
20327(outs),
20328(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20329"if (!$Pv4) memh($Rs32) = $Nt8.new",
20330tc_011e0e9d, TypeMAPPING> {
20331let isPseudo = 1;
20332let isCodeGenOnly = 1;
20333let opNewValue = 2;
20334}
20335def S2_pstorerhnewfnew_pi : HInst<
20336(outs IntRegs:$Rx32),
20337(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20338"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20339tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20340let Inst{2-2} = 0b1;
20341let Inst{7-7} = 0b1;
20342let Inst{13-11} = 0b101;
20343let Inst{31-21} = 0b10101011101;
20344let isPredicated = 1;
20345let isPredicatedFalse = 1;
20346let addrMode = PostInc;
20347let accessSize = HalfWordAccess;
20348let isNVStore = 1;
20349let isPredicatedNew = 1;
20350let isNewValue = 1;
20351let isRestrictNoSlot1Store = 1;
20352let mayStore = 1;
20353let BaseOpcode = "S2_storerh_pi";
20354let CextOpcode = "S2_storerh";
20355let opNewValue = 4;
20356let Constraints = "$Rx32 = $Rx32in";
20357}
20358def S2_pstorerhnewt_io : HInst<
20359(outs),
20360(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20361"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20362tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20363let Inst{2-2} = 0b0;
20364let Inst{12-11} = 0b01;
20365let Inst{31-21} = 0b01000000101;
20366let isPredicated = 1;
20367let addrMode = BaseImmOffset;
20368let accessSize = HalfWordAccess;
20369let isNVStore = 1;
20370let isNewValue = 1;
20371let isRestrictNoSlot1Store = 1;
20372let mayStore = 1;
20373let BaseOpcode = "S2_storerh_io";
20374let CextOpcode = "S2_storerh";
20375let InputType = "imm";
20376let isExtendable = 1;
20377let opExtendable = 2;
20378let isExtentSigned = 0;
20379let opExtentBits = 7;
20380let opExtentAlign = 1;
20381let opNewValue = 3;
20382}
20383def S2_pstorerhnewt_pi : HInst<
20384(outs IntRegs:$Rx32),
20385(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20386"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20387tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20388let Inst{2-2} = 0b0;
20389let Inst{7-7} = 0b0;
20390let Inst{13-11} = 0b101;
20391let Inst{31-21} = 0b10101011101;
20392let isPredicated = 1;
20393let addrMode = PostInc;
20394let accessSize = HalfWordAccess;
20395let isNVStore = 1;
20396let isNewValue = 1;
20397let isRestrictNoSlot1Store = 1;
20398let mayStore = 1;
20399let BaseOpcode = "S2_storerh_pi";
20400let CextOpcode = "S2_storerh";
20401let opNewValue = 4;
20402let Constraints = "$Rx32 = $Rx32in";
20403}
20404def S2_pstorerhnewt_zomap : HInst<
20405(outs),
20406(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20407"if ($Pv4) memh($Rs32) = $Nt8.new",
20408tc_011e0e9d, TypeMAPPING> {
20409let isPseudo = 1;
20410let isCodeGenOnly = 1;
20411let opNewValue = 2;
20412}
20413def S2_pstorerhnewtnew_pi : HInst<
20414(outs IntRegs:$Rx32),
20415(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20416"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20417tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20418let Inst{2-2} = 0b0;
20419let Inst{7-7} = 0b1;
20420let Inst{13-11} = 0b101;
20421let Inst{31-21} = 0b10101011101;
20422let isPredicated = 1;
20423let addrMode = PostInc;
20424let accessSize = HalfWordAccess;
20425let isNVStore = 1;
20426let isPredicatedNew = 1;
20427let isNewValue = 1;
20428let isRestrictNoSlot1Store = 1;
20429let mayStore = 1;
20430let BaseOpcode = "S2_storerh_pi";
20431let CextOpcode = "S2_storerh";
20432let opNewValue = 4;
20433let Constraints = "$Rx32 = $Rx32in";
20434}
20435def S2_pstorerht_io : HInst<
20436(outs),
20437(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20438"if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
20439tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20440let Inst{2-2} = 0b0;
20441let Inst{31-21} = 0b01000000010;
20442let isPredicated = 1;
20443let addrMode = BaseImmOffset;
20444let accessSize = HalfWordAccess;
20445let mayStore = 1;
20446let BaseOpcode = "S2_storerh_io";
20447let CextOpcode = "S2_storerh";
20448let InputType = "imm";
20449let isNVStorable = 1;
20450let isExtendable = 1;
20451let opExtendable = 2;
20452let isExtentSigned = 0;
20453let opExtentBits = 7;
20454let opExtentAlign = 1;
20455}
20456def S2_pstorerht_pi : HInst<
20457(outs IntRegs:$Rx32),
20458(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20459"if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
20460tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20461let Inst{2-2} = 0b0;
20462let Inst{7-7} = 0b0;
20463let Inst{13-13} = 0b1;
20464let Inst{31-21} = 0b10101011010;
20465let isPredicated = 1;
20466let addrMode = PostInc;
20467let accessSize = HalfWordAccess;
20468let mayStore = 1;
20469let BaseOpcode = "S2_storerh_pi";
20470let isNVStorable = 1;
20471let Constraints = "$Rx32 = $Rx32in";
20472}
20473def S2_pstorerht_zomap : HInst<
20474(outs),
20475(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20476"if ($Pv4) memh($Rs32) = $Rt32",
20477tc_8035e91f, TypeMAPPING> {
20478let isPseudo = 1;
20479let isCodeGenOnly = 1;
20480}
20481def S2_pstorerhtnew_pi : HInst<
20482(outs IntRegs:$Rx32),
20483(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20484"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20485tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20486let Inst{2-2} = 0b0;
20487let Inst{7-7} = 0b1;
20488let Inst{13-13} = 0b1;
20489let Inst{31-21} = 0b10101011010;
20490let isPredicated = 1;
20491let addrMode = PostInc;
20492let accessSize = HalfWordAccess;
20493let isPredicatedNew = 1;
20494let mayStore = 1;
20495let BaseOpcode = "S2_storerh_pi";
20496let isNVStorable = 1;
20497let Constraints = "$Rx32 = $Rx32in";
20498}
20499def S2_pstorerif_io : HInst<
20500(outs),
20501(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20502"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
20503tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20504let Inst{2-2} = 0b0;
20505let Inst{31-21} = 0b01000100100;
20506let isPredicated = 1;
20507let isPredicatedFalse = 1;
20508let addrMode = BaseImmOffset;
20509let accessSize = WordAccess;
20510let mayStore = 1;
20511let BaseOpcode = "S2_storeri_io";
20512let CextOpcode = "S2_storeri";
20513let InputType = "imm";
20514let isNVStorable = 1;
20515let isExtendable = 1;
20516let opExtendable = 2;
20517let isExtentSigned = 0;
20518let opExtentBits = 8;
20519let opExtentAlign = 2;
20520}
20521def S2_pstorerif_pi : HInst<
20522(outs IntRegs:$Rx32),
20523(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20524"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
20525tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20526let Inst{2-2} = 0b1;
20527let Inst{7-7} = 0b0;
20528let Inst{13-13} = 0b1;
20529let Inst{31-21} = 0b10101011100;
20530let isPredicated = 1;
20531let isPredicatedFalse = 1;
20532let addrMode = PostInc;
20533let accessSize = WordAccess;
20534let mayStore = 1;
20535let BaseOpcode = "S2_storeri_pi";
20536let isNVStorable = 1;
20537let Constraints = "$Rx32 = $Rx32in";
20538}
20539def S2_pstorerif_zomap : HInst<
20540(outs),
20541(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20542"if (!$Pv4) memw($Rs32) = $Rt32",
20543tc_8035e91f, TypeMAPPING> {
20544let isPseudo = 1;
20545let isCodeGenOnly = 1;
20546}
20547def S2_pstorerifnew_pi : HInst<
20548(outs IntRegs:$Rx32),
20549(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20550"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20551tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20552let Inst{2-2} = 0b1;
20553let Inst{7-7} = 0b1;
20554let Inst{13-13} = 0b1;
20555let Inst{31-21} = 0b10101011100;
20556let isPredicated = 1;
20557let isPredicatedFalse = 1;
20558let addrMode = PostInc;
20559let accessSize = WordAccess;
20560let isPredicatedNew = 1;
20561let mayStore = 1;
20562let BaseOpcode = "S2_storeri_pi";
20563let CextOpcode = "S2_storeri";
20564let isNVStorable = 1;
20565let Constraints = "$Rx32 = $Rx32in";
20566}
20567def S2_pstorerinewf_io : HInst<
20568(outs),
20569(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20570"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20571tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20572let Inst{2-2} = 0b0;
20573let Inst{12-11} = 0b10;
20574let Inst{31-21} = 0b01000100101;
20575let isPredicated = 1;
20576let isPredicatedFalse = 1;
20577let addrMode = BaseImmOffset;
20578let accessSize = WordAccess;
20579let isNVStore = 1;
20580let isNewValue = 1;
20581let isRestrictNoSlot1Store = 1;
20582let mayStore = 1;
20583let BaseOpcode = "S2_storeri_io";
20584let CextOpcode = "S2_storeri";
20585let InputType = "imm";
20586let isExtendable = 1;
20587let opExtendable = 2;
20588let isExtentSigned = 0;
20589let opExtentBits = 8;
20590let opExtentAlign = 2;
20591let opNewValue = 3;
20592}
20593def S2_pstorerinewf_pi : HInst<
20594(outs IntRegs:$Rx32),
20595(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20596"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20597tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20598let Inst{2-2} = 0b1;
20599let Inst{7-7} = 0b0;
20600let Inst{13-11} = 0b110;
20601let Inst{31-21} = 0b10101011101;
20602let isPredicated = 1;
20603let isPredicatedFalse = 1;
20604let addrMode = PostInc;
20605let accessSize = WordAccess;
20606let isNVStore = 1;
20607let isNewValue = 1;
20608let isRestrictNoSlot1Store = 1;
20609let mayStore = 1;
20610let BaseOpcode = "S2_storeri_pi";
20611let CextOpcode = "S2_storeri";
20612let opNewValue = 4;
20613let Constraints = "$Rx32 = $Rx32in";
20614}
20615def S2_pstorerinewf_zomap : HInst<
20616(outs),
20617(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20618"if (!$Pv4) memw($Rs32) = $Nt8.new",
20619tc_011e0e9d, TypeMAPPING> {
20620let isPseudo = 1;
20621let isCodeGenOnly = 1;
20622let opNewValue = 2;
20623}
20624def S2_pstorerinewfnew_pi : HInst<
20625(outs IntRegs:$Rx32),
20626(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20627"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20628tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20629let Inst{2-2} = 0b1;
20630let Inst{7-7} = 0b1;
20631let Inst{13-11} = 0b110;
20632let Inst{31-21} = 0b10101011101;
20633let isPredicated = 1;
20634let isPredicatedFalse = 1;
20635let addrMode = PostInc;
20636let accessSize = WordAccess;
20637let isNVStore = 1;
20638let isPredicatedNew = 1;
20639let isNewValue = 1;
20640let isRestrictNoSlot1Store = 1;
20641let mayStore = 1;
20642let BaseOpcode = "S2_storeri_pi";
20643let CextOpcode = "S2_storeri";
20644let opNewValue = 4;
20645let Constraints = "$Rx32 = $Rx32in";
20646}
20647def S2_pstorerinewt_io : HInst<
20648(outs),
20649(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20650"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20651tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20652let Inst{2-2} = 0b0;
20653let Inst{12-11} = 0b10;
20654let Inst{31-21} = 0b01000000101;
20655let isPredicated = 1;
20656let addrMode = BaseImmOffset;
20657let accessSize = WordAccess;
20658let isNVStore = 1;
20659let isNewValue = 1;
20660let isRestrictNoSlot1Store = 1;
20661let mayStore = 1;
20662let BaseOpcode = "S2_storeri_io";
20663let CextOpcode = "S2_storeri";
20664let InputType = "imm";
20665let isExtendable = 1;
20666let opExtendable = 2;
20667let isExtentSigned = 0;
20668let opExtentBits = 8;
20669let opExtentAlign = 2;
20670let opNewValue = 3;
20671}
20672def S2_pstorerinewt_pi : HInst<
20673(outs IntRegs:$Rx32),
20674(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20675"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20676tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20677let Inst{2-2} = 0b0;
20678let Inst{7-7} = 0b0;
20679let Inst{13-11} = 0b110;
20680let Inst{31-21} = 0b10101011101;
20681let isPredicated = 1;
20682let addrMode = PostInc;
20683let accessSize = WordAccess;
20684let isNVStore = 1;
20685let isNewValue = 1;
20686let isRestrictNoSlot1Store = 1;
20687let mayStore = 1;
20688let BaseOpcode = "S2_storeri_pi";
20689let CextOpcode = "S2_storeri";
20690let opNewValue = 4;
20691let Constraints = "$Rx32 = $Rx32in";
20692}
20693def S2_pstorerinewt_zomap : HInst<
20694(outs),
20695(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20696"if ($Pv4) memw($Rs32) = $Nt8.new",
20697tc_011e0e9d, TypeMAPPING> {
20698let isPseudo = 1;
20699let isCodeGenOnly = 1;
20700let opNewValue = 2;
20701}
20702def S2_pstorerinewtnew_pi : HInst<
20703(outs IntRegs:$Rx32),
20704(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20705"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20706tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20707let Inst{2-2} = 0b0;
20708let Inst{7-7} = 0b1;
20709let Inst{13-11} = 0b110;
20710let Inst{31-21} = 0b10101011101;
20711let isPredicated = 1;
20712let addrMode = PostInc;
20713let accessSize = WordAccess;
20714let isNVStore = 1;
20715let isPredicatedNew = 1;
20716let isNewValue = 1;
20717let isRestrictNoSlot1Store = 1;
20718let mayStore = 1;
20719let BaseOpcode = "S2_storeri_pi";
20720let CextOpcode = "S2_storeri";
20721let opNewValue = 4;
20722let Constraints = "$Rx32 = $Rx32in";
20723}
20724def S2_pstorerit_io : HInst<
20725(outs),
20726(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20727"if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
20728tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20729let Inst{2-2} = 0b0;
20730let Inst{31-21} = 0b01000000100;
20731let isPredicated = 1;
20732let addrMode = BaseImmOffset;
20733let accessSize = WordAccess;
20734let mayStore = 1;
20735let BaseOpcode = "S2_storeri_io";
20736let CextOpcode = "S2_storeri";
20737let InputType = "imm";
20738let isNVStorable = 1;
20739let isExtendable = 1;
20740let opExtendable = 2;
20741let isExtentSigned = 0;
20742let opExtentBits = 8;
20743let opExtentAlign = 2;
20744}
20745def S2_pstorerit_pi : HInst<
20746(outs IntRegs:$Rx32),
20747(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20748"if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
20749tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20750let Inst{2-2} = 0b0;
20751let Inst{7-7} = 0b0;
20752let Inst{13-13} = 0b1;
20753let Inst{31-21} = 0b10101011100;
20754let isPredicated = 1;
20755let addrMode = PostInc;
20756let accessSize = WordAccess;
20757let mayStore = 1;
20758let BaseOpcode = "S2_storeri_pi";
20759let isNVStorable = 1;
20760let Constraints = "$Rx32 = $Rx32in";
20761}
20762def S2_pstorerit_zomap : HInst<
20763(outs),
20764(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20765"if ($Pv4) memw($Rs32) = $Rt32",
20766tc_8035e91f, TypeMAPPING> {
20767let isPseudo = 1;
20768let isCodeGenOnly = 1;
20769}
20770def S2_pstoreritnew_pi : HInst<
20771(outs IntRegs:$Rx32),
20772(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20773"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20774tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20775let Inst{2-2} = 0b0;
20776let Inst{7-7} = 0b1;
20777let Inst{13-13} = 0b1;
20778let Inst{31-21} = 0b10101011100;
20779let isPredicated = 1;
20780let addrMode = PostInc;
20781let accessSize = WordAccess;
20782let isPredicatedNew = 1;
20783let mayStore = 1;
20784let BaseOpcode = "S2_storeri_pi";
20785let isNVStorable = 1;
20786let Constraints = "$Rx32 = $Rx32in";
20787}
20788def S2_setbit_i : HInst<
20789(outs IntRegs:$Rd32),
20790(ins IntRegs:$Rs32, u5_0Imm:$Ii),
20791"$Rd32 = setbit($Rs32,#$Ii)",
20792tc_5da50c4b, TypeS_2op>, Enc_a05677 {
20793let Inst{7-5} = 0b000;
20794let Inst{13-13} = 0b0;
20795let Inst{31-21} = 0b10001100110;
20796let hasNewValue = 1;
20797let opNewValue = 0;
20798}
20799def S2_setbit_r : HInst<
20800(outs IntRegs:$Rd32),
20801(ins IntRegs:$Rs32, IntRegs:$Rt32),
20802"$Rd32 = setbit($Rs32,$Rt32)",
20803tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
20804let Inst{7-5} = 0b000;
20805let Inst{13-13} = 0b0;
20806let Inst{31-21} = 0b11000110100;
20807let hasNewValue = 1;
20808let opNewValue = 0;
20809}
20810def S2_shuffeb : HInst<
20811(outs DoubleRegs:$Rdd32),
20812(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20813"$Rdd32 = shuffeb($Rss32,$Rtt32)",
20814tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20815let Inst{7-5} = 0b010;
20816let Inst{13-13} = 0b0;
20817let Inst{31-21} = 0b11000001000;
20818}
20819def S2_shuffeh : HInst<
20820(outs DoubleRegs:$Rdd32),
20821(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20822"$Rdd32 = shuffeh($Rss32,$Rtt32)",
20823tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20824let Inst{7-5} = 0b110;
20825let Inst{13-13} = 0b0;
20826let Inst{31-21} = 0b11000001000;
20827}
20828def S2_shuffob : HInst<
20829(outs DoubleRegs:$Rdd32),
20830(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20831"$Rdd32 = shuffob($Rtt32,$Rss32)",
20832tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20833let Inst{7-5} = 0b100;
20834let Inst{13-13} = 0b0;
20835let Inst{31-21} = 0b11000001000;
20836}
20837def S2_shuffoh : HInst<
20838(outs DoubleRegs:$Rdd32),
20839(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20840"$Rdd32 = shuffoh($Rtt32,$Rss32)",
20841tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20842let Inst{7-5} = 0b000;
20843let Inst{13-13} = 0b0;
20844let Inst{31-21} = 0b11000001100;
20845}
20846def S2_storerb_io : HInst<
20847(outs),
20848(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
20849"memb($Rs32+#$Ii) = $Rt32",
20850tc_ae5babd7, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
20851let Inst{24-21} = 0b1000;
20852let Inst{31-27} = 0b10100;
20853let addrMode = BaseImmOffset;
20854let accessSize = ByteAccess;
20855let mayStore = 1;
20856let BaseOpcode = "S2_storerb_io";
20857let CextOpcode = "S2_storerb";
20858let InputType = "imm";
20859let isPredicable = 1;
20860let isNVStorable = 1;
20861let isExtendable = 1;
20862let opExtendable = 1;
20863let isExtentSigned = 1;
20864let opExtentBits = 11;
20865let opExtentAlign = 0;
20866}
20867def S2_storerb_pbr : HInst<
20868(outs IntRegs:$Rx32),
20869(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20870"memb($Rx32++$Mu2:brev) = $Rt32",
20871tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20872let Inst{7-0} = 0b00000000;
20873let Inst{31-21} = 0b10101111000;
20874let addrMode = PostInc;
20875let accessSize = ByteAccess;
20876let mayStore = 1;
20877let BaseOpcode = "S2_storerb_pbr";
20878let isNVStorable = 1;
20879let Constraints = "$Rx32 = $Rx32in";
20880}
20881def S2_storerb_pci : HInst<
20882(outs IntRegs:$Rx32),
20883(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20884"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20885tc_b4dc7630, TypeST>, Enc_b15941, AddrModeRel {
20886let Inst{2-0} = 0b000;
20887let Inst{7-7} = 0b0;
20888let Inst{31-21} = 0b10101001000;
20889let addrMode = PostInc;
20890let accessSize = ByteAccess;
20891let mayStore = 1;
20892let Uses = [CS];
20893let BaseOpcode = "S2_storerb_pci";
20894let isNVStorable = 1;
20895let Constraints = "$Rx32 = $Rx32in";
20896}
20897def S2_storerb_pcr : HInst<
20898(outs IntRegs:$Rx32),
20899(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20900"memb($Rx32++I:circ($Mu2)) = $Rt32",
20901tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20902let Inst{7-0} = 0b00000010;
20903let Inst{31-21} = 0b10101001000;
20904let addrMode = PostInc;
20905let accessSize = ByteAccess;
20906let mayStore = 1;
20907let Uses = [CS];
20908let BaseOpcode = "S2_storerb_pcr";
20909let isNVStorable = 1;
20910let Constraints = "$Rx32 = $Rx32in";
20911}
20912def S2_storerb_pi : HInst<
20913(outs IntRegs:$Rx32),
20914(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20915"memb($Rx32++#$Ii) = $Rt32",
20916tc_a2b365d2, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
20917let Inst{2-0} = 0b000;
20918let Inst{7-7} = 0b0;
20919let Inst{13-13} = 0b0;
20920let Inst{31-21} = 0b10101011000;
20921let addrMode = PostInc;
20922let accessSize = ByteAccess;
20923let mayStore = 1;
20924let BaseOpcode = "S2_storerb_pi";
20925let CextOpcode = "S2_storerb";
20926let isPredicable = 1;
20927let isNVStorable = 1;
20928let Constraints = "$Rx32 = $Rx32in";
20929}
20930def S2_storerb_pr : HInst<
20931(outs IntRegs:$Rx32),
20932(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20933"memb($Rx32++$Mu2) = $Rt32",
20934tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20935let Inst{7-0} = 0b00000000;
20936let Inst{31-21} = 0b10101101000;
20937let addrMode = PostInc;
20938let accessSize = ByteAccess;
20939let mayStore = 1;
20940let BaseOpcode = "S2_storerb_pr";
20941let isNVStorable = 1;
20942let Constraints = "$Rx32 = $Rx32in";
20943}
20944def S2_storerb_zomap : HInst<
20945(outs),
20946(ins IntRegs:$Rs32, IntRegs:$Rt32),
20947"memb($Rs32) = $Rt32",
20948tc_ae5babd7, TypeMAPPING> {
20949let isPseudo = 1;
20950let isCodeGenOnly = 1;
20951}
20952def S2_storerbgp : HInst<
20953(outs),
20954(ins u32_0Imm:$Ii, IntRegs:$Rt32),
20955"memb(gp+#$Ii) = $Rt32",
20956tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
20957let Inst{24-21} = 0b0000;
20958let Inst{31-27} = 0b01001;
20959let accessSize = ByteAccess;
20960let mayStore = 1;
20961let Uses = [GP];
20962let BaseOpcode = "S2_storerbabs";
20963let isPredicable = 1;
20964let isNVStorable = 1;
20965let opExtendable = 0;
20966let isExtentSigned = 0;
20967let opExtentBits = 16;
20968let opExtentAlign = 0;
20969}
20970def S2_storerbnew_io : HInst<
20971(outs),
20972(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
20973"memb($Rs32+#$Ii) = $Nt8.new",
20974tc_5deb5e47, TypeST>, Enc_4df4e9, AddrModeRel {
20975let Inst{12-11} = 0b00;
20976let Inst{24-21} = 0b1101;
20977let Inst{31-27} = 0b10100;
20978let addrMode = BaseImmOffset;
20979let accessSize = ByteAccess;
20980let isNVStore = 1;
20981let isNewValue = 1;
20982let isRestrictNoSlot1Store = 1;
20983let mayStore = 1;
20984let BaseOpcode = "S2_storerb_io";
20985let CextOpcode = "S2_storerb";
20986let InputType = "imm";
20987let isPredicable = 1;
20988let isExtendable = 1;
20989let opExtendable = 1;
20990let isExtentSigned = 1;
20991let opExtentBits = 11;
20992let opExtentAlign = 0;
20993let opNewValue = 2;
20994}
20995def S2_storerbnew_pbr : HInst<
20996(outs IntRegs:$Rx32),
20997(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
20998"memb($Rx32++$Mu2:brev) = $Nt8.new",
20999tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21000let Inst{7-0} = 0b00000000;
21001let Inst{12-11} = 0b00;
21002let Inst{31-21} = 0b10101111101;
21003let addrMode = PostInc;
21004let accessSize = ByteAccess;
21005let isNVStore = 1;
21006let isNewValue = 1;
21007let isRestrictNoSlot1Store = 1;
21008let mayStore = 1;
21009let BaseOpcode = "S2_storerb_pbr";
21010let opNewValue = 3;
21011let Constraints = "$Rx32 = $Rx32in";
21012}
21013def S2_storerbnew_pci : HInst<
21014(outs IntRegs:$Rx32),
21015(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21016"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21017tc_addc37a8, TypeST>, Enc_96ce4f, AddrModeRel {
21018let Inst{2-0} = 0b000;
21019let Inst{7-7} = 0b0;
21020let Inst{12-11} = 0b00;
21021let Inst{31-21} = 0b10101001101;
21022let addrMode = PostInc;
21023let accessSize = ByteAccess;
21024let isNVStore = 1;
21025let isNewValue = 1;
21026let isRestrictNoSlot1Store = 1;
21027let mayStore = 1;
21028let Uses = [CS];
21029let BaseOpcode = "S2_storerb_pci";
21030let opNewValue = 4;
21031let Constraints = "$Rx32 = $Rx32in";
21032}
21033def S2_storerbnew_pcr : HInst<
21034(outs IntRegs:$Rx32),
21035(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21036"memb($Rx32++I:circ($Mu2)) = $Nt8.new",
21037tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21038let Inst{7-0} = 0b00000010;
21039let Inst{12-11} = 0b00;
21040let Inst{31-21} = 0b10101001101;
21041let addrMode = PostInc;
21042let accessSize = ByteAccess;
21043let isNVStore = 1;
21044let isNewValue = 1;
21045let isRestrictNoSlot1Store = 1;
21046let mayStore = 1;
21047let Uses = [CS];
21048let BaseOpcode = "S2_storerb_pcr";
21049let opNewValue = 3;
21050let Constraints = "$Rx32 = $Rx32in";
21051}
21052def S2_storerbnew_pi : HInst<
21053(outs IntRegs:$Rx32),
21054(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
21055"memb($Rx32++#$Ii) = $Nt8.new",
21056tc_92240447, TypeST>, Enc_c7cd90, AddrModeRel {
21057let Inst{2-0} = 0b000;
21058let Inst{7-7} = 0b0;
21059let Inst{13-11} = 0b000;
21060let Inst{31-21} = 0b10101011101;
21061let addrMode = PostInc;
21062let accessSize = ByteAccess;
21063let isNVStore = 1;
21064let isNewValue = 1;
21065let isRestrictNoSlot1Store = 1;
21066let mayStore = 1;
21067let BaseOpcode = "S2_storerb_pi";
21068let isPredicable = 1;
21069let isNVStorable = 1;
21070let opNewValue = 3;
21071let Constraints = "$Rx32 = $Rx32in";
21072}
21073def S2_storerbnew_pr : HInst<
21074(outs IntRegs:$Rx32),
21075(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21076"memb($Rx32++$Mu2) = $Nt8.new",
21077tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21078let Inst{7-0} = 0b00000000;
21079let Inst{12-11} = 0b00;
21080let Inst{31-21} = 0b10101101101;
21081let addrMode = PostInc;
21082let accessSize = ByteAccess;
21083let isNVStore = 1;
21084let isNewValue = 1;
21085let isRestrictNoSlot1Store = 1;
21086let mayStore = 1;
21087let BaseOpcode = "S2_storerb_pr";
21088let opNewValue = 3;
21089let Constraints = "$Rx32 = $Rx32in";
21090}
21091def S2_storerbnew_zomap : HInst<
21092(outs),
21093(ins IntRegs:$Rs32, IntRegs:$Nt8),
21094"memb($Rs32) = $Nt8.new",
21095tc_5deb5e47, TypeMAPPING> {
21096let isPseudo = 1;
21097let isCodeGenOnly = 1;
21098let opNewValue = 1;
21099}
21100def S2_storerbnewgp : HInst<
21101(outs),
21102(ins u32_0Imm:$Ii, IntRegs:$Nt8),
21103"memb(gp+#$Ii) = $Nt8.new",
21104tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
21105let Inst{12-11} = 0b00;
21106let Inst{24-21} = 0b0101;
21107let Inst{31-27} = 0b01001;
21108let accessSize = ByteAccess;
21109let isNVStore = 1;
21110let isNewValue = 1;
21111let isRestrictNoSlot1Store = 1;
21112let mayStore = 1;
21113let Uses = [GP];
21114let BaseOpcode = "S2_storerbabs";
21115let isPredicable = 1;
21116let opExtendable = 0;
21117let isExtentSigned = 0;
21118let opExtentBits = 16;
21119let opExtentAlign = 0;
21120let opNewValue = 1;
21121}
21122def S2_storerd_io : HInst<
21123(outs),
21124(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
21125"memd($Rs32+#$Ii) = $Rtt32",
21126tc_ae5babd7, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
21127let Inst{24-21} = 0b1110;
21128let Inst{31-27} = 0b10100;
21129let addrMode = BaseImmOffset;
21130let accessSize = DoubleWordAccess;
21131let mayStore = 1;
21132let BaseOpcode = "S2_storerd_io";
21133let CextOpcode = "S2_storerd";
21134let InputType = "imm";
21135let isPredicable = 1;
21136let isExtendable = 1;
21137let opExtendable = 1;
21138let isExtentSigned = 1;
21139let opExtentBits = 14;
21140let opExtentAlign = 3;
21141}
21142def S2_storerd_pbr : HInst<
21143(outs IntRegs:$Rx32),
21144(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21145"memd($Rx32++$Mu2:brev) = $Rtt32",
21146tc_a2b365d2, TypeST>, Enc_928ca1 {
21147let Inst{7-0} = 0b00000000;
21148let Inst{31-21} = 0b10101111110;
21149let addrMode = PostInc;
21150let accessSize = DoubleWordAccess;
21151let mayStore = 1;
21152let Constraints = "$Rx32 = $Rx32in";
21153}
21154def S2_storerd_pci : HInst<
21155(outs IntRegs:$Rx32),
21156(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21157"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
21158tc_b4dc7630, TypeST>, Enc_395cc4 {
21159let Inst{2-0} = 0b000;
21160let Inst{7-7} = 0b0;
21161let Inst{31-21} = 0b10101001110;
21162let addrMode = PostInc;
21163let accessSize = DoubleWordAccess;
21164let mayStore = 1;
21165let Uses = [CS];
21166let Constraints = "$Rx32 = $Rx32in";
21167}
21168def S2_storerd_pcr : HInst<
21169(outs IntRegs:$Rx32),
21170(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21171"memd($Rx32++I:circ($Mu2)) = $Rtt32",
21172tc_a2b365d2, TypeST>, Enc_928ca1 {
21173let Inst{7-0} = 0b00000010;
21174let Inst{31-21} = 0b10101001110;
21175let addrMode = PostInc;
21176let accessSize = DoubleWordAccess;
21177let mayStore = 1;
21178let Uses = [CS];
21179let Constraints = "$Rx32 = $Rx32in";
21180}
21181def S2_storerd_pi : HInst<
21182(outs IntRegs:$Rx32),
21183(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
21184"memd($Rx32++#$Ii) = $Rtt32",
21185tc_a2b365d2, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
21186let Inst{2-0} = 0b000;
21187let Inst{7-7} = 0b0;
21188let Inst{13-13} = 0b0;
21189let Inst{31-21} = 0b10101011110;
21190let addrMode = PostInc;
21191let accessSize = DoubleWordAccess;
21192let mayStore = 1;
21193let BaseOpcode = "S2_storerd_pi";
21194let CextOpcode = "S2_storerd";
21195let isPredicable = 1;
21196let Constraints = "$Rx32 = $Rx32in";
21197}
21198def S2_storerd_pr : HInst<
21199(outs IntRegs:$Rx32),
21200(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21201"memd($Rx32++$Mu2) = $Rtt32",
21202tc_a2b365d2, TypeST>, Enc_928ca1 {
21203let Inst{7-0} = 0b00000000;
21204let Inst{31-21} = 0b10101101110;
21205let addrMode = PostInc;
21206let accessSize = DoubleWordAccess;
21207let mayStore = 1;
21208let Constraints = "$Rx32 = $Rx32in";
21209}
21210def S2_storerd_zomap : HInst<
21211(outs),
21212(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
21213"memd($Rs32) = $Rtt32",
21214tc_ae5babd7, TypeMAPPING> {
21215let isPseudo = 1;
21216let isCodeGenOnly = 1;
21217}
21218def S2_storerdgp : HInst<
21219(outs),
21220(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
21221"memd(gp+#$Ii) = $Rtt32",
21222tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
21223let Inst{24-21} = 0b0110;
21224let Inst{31-27} = 0b01001;
21225let accessSize = DoubleWordAccess;
21226let mayStore = 1;
21227let Uses = [GP];
21228let BaseOpcode = "S2_storerdabs";
21229let isPredicable = 1;
21230let opExtendable = 0;
21231let isExtentSigned = 0;
21232let opExtentBits = 19;
21233let opExtentAlign = 3;
21234}
21235def S2_storerf_io : HInst<
21236(outs),
21237(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21238"memh($Rs32+#$Ii) = $Rt32.h",
21239tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21240let Inst{24-21} = 0b1011;
21241let Inst{31-27} = 0b10100;
21242let addrMode = BaseImmOffset;
21243let accessSize = HalfWordAccess;
21244let mayStore = 1;
21245let BaseOpcode = "S2_storerf_io";
21246let CextOpcode = "S2_storerf";
21247let InputType = "imm";
21248let isPredicable = 1;
21249let isExtendable = 1;
21250let opExtendable = 1;
21251let isExtentSigned = 1;
21252let opExtentBits = 12;
21253let opExtentAlign = 1;
21254}
21255def S2_storerf_pbr : HInst<
21256(outs IntRegs:$Rx32),
21257(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21258"memh($Rx32++$Mu2:brev) = $Rt32.h",
21259tc_a2b365d2, TypeST>, Enc_d5c73f {
21260let Inst{7-0} = 0b00000000;
21261let Inst{31-21} = 0b10101111011;
21262let addrMode = PostInc;
21263let accessSize = HalfWordAccess;
21264let mayStore = 1;
21265let Constraints = "$Rx32 = $Rx32in";
21266}
21267def S2_storerf_pci : HInst<
21268(outs IntRegs:$Rx32),
21269(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21270"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
21271tc_b4dc7630, TypeST>, Enc_935d9b {
21272let Inst{2-0} = 0b000;
21273let Inst{7-7} = 0b0;
21274let Inst{31-21} = 0b10101001011;
21275let addrMode = PostInc;
21276let accessSize = HalfWordAccess;
21277let mayStore = 1;
21278let Uses = [CS];
21279let Constraints = "$Rx32 = $Rx32in";
21280}
21281def S2_storerf_pcr : HInst<
21282(outs IntRegs:$Rx32),
21283(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21284"memh($Rx32++I:circ($Mu2)) = $Rt32.h",
21285tc_a2b365d2, TypeST>, Enc_d5c73f {
21286let Inst{7-0} = 0b00000010;
21287let Inst{31-21} = 0b10101001011;
21288let addrMode = PostInc;
21289let accessSize = HalfWordAccess;
21290let mayStore = 1;
21291let Uses = [CS];
21292let Constraints = "$Rx32 = $Rx32in";
21293}
21294def S2_storerf_pi : HInst<
21295(outs IntRegs:$Rx32),
21296(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21297"memh($Rx32++#$Ii) = $Rt32.h",
21298tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21299let Inst{2-0} = 0b000;
21300let Inst{7-7} = 0b0;
21301let Inst{13-13} = 0b0;
21302let Inst{31-21} = 0b10101011011;
21303let addrMode = PostInc;
21304let accessSize = HalfWordAccess;
21305let mayStore = 1;
21306let BaseOpcode = "S2_storerf_pi";
21307let CextOpcode = "S2_storerf";
21308let isPredicable = 1;
21309let Constraints = "$Rx32 = $Rx32in";
21310}
21311def S2_storerf_pr : HInst<
21312(outs IntRegs:$Rx32),
21313(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21314"memh($Rx32++$Mu2) = $Rt32.h",
21315tc_a2b365d2, TypeST>, Enc_d5c73f {
21316let Inst{7-0} = 0b00000000;
21317let Inst{31-21} = 0b10101101011;
21318let addrMode = PostInc;
21319let accessSize = HalfWordAccess;
21320let mayStore = 1;
21321let Constraints = "$Rx32 = $Rx32in";
21322}
21323def S2_storerf_zomap : HInst<
21324(outs),
21325(ins IntRegs:$Rs32, IntRegs:$Rt32),
21326"memh($Rs32) = $Rt32.h",
21327tc_ae5babd7, TypeMAPPING> {
21328let isPseudo = 1;
21329let isCodeGenOnly = 1;
21330}
21331def S2_storerfgp : HInst<
21332(outs),
21333(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21334"memh(gp+#$Ii) = $Rt32.h",
21335tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21336let Inst{24-21} = 0b0011;
21337let Inst{31-27} = 0b01001;
21338let accessSize = HalfWordAccess;
21339let mayStore = 1;
21340let Uses = [GP];
21341let BaseOpcode = "S2_storerfabs";
21342let isPredicable = 1;
21343let opExtendable = 0;
21344let isExtentSigned = 0;
21345let opExtentBits = 17;
21346let opExtentAlign = 1;
21347}
21348def S2_storerh_io : HInst<
21349(outs),
21350(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21351"memh($Rs32+#$Ii) = $Rt32",
21352tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21353let Inst{24-21} = 0b1010;
21354let Inst{31-27} = 0b10100;
21355let addrMode = BaseImmOffset;
21356let accessSize = HalfWordAccess;
21357let mayStore = 1;
21358let BaseOpcode = "S2_storerh_io";
21359let CextOpcode = "S2_storerh";
21360let InputType = "imm";
21361let isPredicable = 1;
21362let isNVStorable = 1;
21363let isExtendable = 1;
21364let opExtendable = 1;
21365let isExtentSigned = 1;
21366let opExtentBits = 12;
21367let opExtentAlign = 1;
21368}
21369def S2_storerh_pbr : HInst<
21370(outs IntRegs:$Rx32),
21371(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21372"memh($Rx32++$Mu2:brev) = $Rt32",
21373tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21374let Inst{7-0} = 0b00000000;
21375let Inst{31-21} = 0b10101111010;
21376let addrMode = PostInc;
21377let accessSize = HalfWordAccess;
21378let mayStore = 1;
21379let BaseOpcode = "S2_storerh_pbr";
21380let isNVStorable = 1;
21381let Constraints = "$Rx32 = $Rx32in";
21382}
21383def S2_storerh_pci : HInst<
21384(outs IntRegs:$Rx32),
21385(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21386"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21387tc_b4dc7630, TypeST>, Enc_935d9b, AddrModeRel {
21388let Inst{2-0} = 0b000;
21389let Inst{7-7} = 0b0;
21390let Inst{31-21} = 0b10101001010;
21391let addrMode = PostInc;
21392let accessSize = HalfWordAccess;
21393let mayStore = 1;
21394let Uses = [CS];
21395let BaseOpcode = "S2_storerh_pci";
21396let isNVStorable = 1;
21397let Constraints = "$Rx32 = $Rx32in";
21398}
21399def S2_storerh_pcr : HInst<
21400(outs IntRegs:$Rx32),
21401(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21402"memh($Rx32++I:circ($Mu2)) = $Rt32",
21403tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21404let Inst{7-0} = 0b00000010;
21405let Inst{31-21} = 0b10101001010;
21406let addrMode = PostInc;
21407let accessSize = HalfWordAccess;
21408let mayStore = 1;
21409let Uses = [CS];
21410let BaseOpcode = "S2_storerh_pcr";
21411let isNVStorable = 1;
21412let Constraints = "$Rx32 = $Rx32in";
21413}
21414def S2_storerh_pi : HInst<
21415(outs IntRegs:$Rx32),
21416(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21417"memh($Rx32++#$Ii) = $Rt32",
21418tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21419let Inst{2-0} = 0b000;
21420let Inst{7-7} = 0b0;
21421let Inst{13-13} = 0b0;
21422let Inst{31-21} = 0b10101011010;
21423let addrMode = PostInc;
21424let accessSize = HalfWordAccess;
21425let mayStore = 1;
21426let BaseOpcode = "S2_storerh_pi";
21427let CextOpcode = "S2_storerh";
21428let isPredicable = 1;
21429let isNVStorable = 1;
21430let Constraints = "$Rx32 = $Rx32in";
21431}
21432def S2_storerh_pr : HInst<
21433(outs IntRegs:$Rx32),
21434(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21435"memh($Rx32++$Mu2) = $Rt32",
21436tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21437let Inst{7-0} = 0b00000000;
21438let Inst{31-21} = 0b10101101010;
21439let addrMode = PostInc;
21440let accessSize = HalfWordAccess;
21441let mayStore = 1;
21442let BaseOpcode = "S2_storerh_pr";
21443let isNVStorable = 1;
21444let Constraints = "$Rx32 = $Rx32in";
21445}
21446def S2_storerh_zomap : HInst<
21447(outs),
21448(ins IntRegs:$Rs32, IntRegs:$Rt32),
21449"memh($Rs32) = $Rt32",
21450tc_ae5babd7, TypeMAPPING> {
21451let isPseudo = 1;
21452let isCodeGenOnly = 1;
21453}
21454def S2_storerhgp : HInst<
21455(outs),
21456(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21457"memh(gp+#$Ii) = $Rt32",
21458tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21459let Inst{24-21} = 0b0010;
21460let Inst{31-27} = 0b01001;
21461let accessSize = HalfWordAccess;
21462let mayStore = 1;
21463let Uses = [GP];
21464let BaseOpcode = "S2_storerhabs";
21465let isPredicable = 1;
21466let isNVStorable = 1;
21467let opExtendable = 0;
21468let isExtentSigned = 0;
21469let opExtentBits = 17;
21470let opExtentAlign = 1;
21471}
21472def S2_storerhnew_io : HInst<
21473(outs),
21474(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
21475"memh($Rs32+#$Ii) = $Nt8.new",
21476tc_5deb5e47, TypeST>, Enc_0d8870, AddrModeRel {
21477let Inst{12-11} = 0b01;
21478let Inst{24-21} = 0b1101;
21479let Inst{31-27} = 0b10100;
21480let addrMode = BaseImmOffset;
21481let accessSize = HalfWordAccess;
21482let isNVStore = 1;
21483let isNewValue = 1;
21484let isRestrictNoSlot1Store = 1;
21485let mayStore = 1;
21486let BaseOpcode = "S2_storerh_io";
21487let CextOpcode = "S2_storerh";
21488let InputType = "imm";
21489let isPredicable = 1;
21490let isExtendable = 1;
21491let opExtendable = 1;
21492let isExtentSigned = 1;
21493let opExtentBits = 12;
21494let opExtentAlign = 1;
21495let opNewValue = 2;
21496}
21497def S2_storerhnew_pbr : HInst<
21498(outs IntRegs:$Rx32),
21499(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21500"memh($Rx32++$Mu2:brev) = $Nt8.new",
21501tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21502let Inst{7-0} = 0b00000000;
21503let Inst{12-11} = 0b01;
21504let Inst{31-21} = 0b10101111101;
21505let addrMode = PostInc;
21506let accessSize = HalfWordAccess;
21507let isNVStore = 1;
21508let isNewValue = 1;
21509let isRestrictNoSlot1Store = 1;
21510let mayStore = 1;
21511let BaseOpcode = "S2_storerh_pbr";
21512let opNewValue = 3;
21513let Constraints = "$Rx32 = $Rx32in";
21514}
21515def S2_storerhnew_pci : HInst<
21516(outs IntRegs:$Rx32),
21517(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21518"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21519tc_addc37a8, TypeST>, Enc_91b9fe, AddrModeRel {
21520let Inst{2-0} = 0b000;
21521let Inst{7-7} = 0b0;
21522let Inst{12-11} = 0b01;
21523let Inst{31-21} = 0b10101001101;
21524let addrMode = PostInc;
21525let accessSize = HalfWordAccess;
21526let isNVStore = 1;
21527let isNewValue = 1;
21528let isRestrictNoSlot1Store = 1;
21529let mayStore = 1;
21530let Uses = [CS];
21531let BaseOpcode = "S2_storerh_pci";
21532let opNewValue = 4;
21533let Constraints = "$Rx32 = $Rx32in";
21534}
21535def S2_storerhnew_pcr : HInst<
21536(outs IntRegs:$Rx32),
21537(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21538"memh($Rx32++I:circ($Mu2)) = $Nt8.new",
21539tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21540let Inst{7-0} = 0b00000010;
21541let Inst{12-11} = 0b01;
21542let Inst{31-21} = 0b10101001101;
21543let addrMode = PostInc;
21544let accessSize = HalfWordAccess;
21545let isNVStore = 1;
21546let isNewValue = 1;
21547let isRestrictNoSlot1Store = 1;
21548let mayStore = 1;
21549let Uses = [CS];
21550let BaseOpcode = "S2_storerh_pcr";
21551let opNewValue = 3;
21552let Constraints = "$Rx32 = $Rx32in";
21553}
21554def S2_storerhnew_pi : HInst<
21555(outs IntRegs:$Rx32),
21556(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
21557"memh($Rx32++#$Ii) = $Nt8.new",
21558tc_92240447, TypeST>, Enc_e26546, AddrModeRel {
21559let Inst{2-0} = 0b000;
21560let Inst{7-7} = 0b0;
21561let Inst{13-11} = 0b001;
21562let Inst{31-21} = 0b10101011101;
21563let addrMode = PostInc;
21564let accessSize = HalfWordAccess;
21565let isNVStore = 1;
21566let isNewValue = 1;
21567let isRestrictNoSlot1Store = 1;
21568let mayStore = 1;
21569let BaseOpcode = "S2_storerh_pi";
21570let isNVStorable = 1;
21571let isPredicable = 1;
21572let opNewValue = 3;
21573let Constraints = "$Rx32 = $Rx32in";
21574}
21575def S2_storerhnew_pr : HInst<
21576(outs IntRegs:$Rx32),
21577(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21578"memh($Rx32++$Mu2) = $Nt8.new",
21579tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21580let Inst{7-0} = 0b00000000;
21581let Inst{12-11} = 0b01;
21582let Inst{31-21} = 0b10101101101;
21583let addrMode = PostInc;
21584let accessSize = HalfWordAccess;
21585let isNVStore = 1;
21586let isNewValue = 1;
21587let isRestrictNoSlot1Store = 1;
21588let mayStore = 1;
21589let BaseOpcode = "S2_storerh_pr";
21590let opNewValue = 3;
21591let Constraints = "$Rx32 = $Rx32in";
21592}
21593def S2_storerhnew_zomap : HInst<
21594(outs),
21595(ins IntRegs:$Rs32, IntRegs:$Nt8),
21596"memh($Rs32) = $Nt8.new",
21597tc_5deb5e47, TypeMAPPING> {
21598let isPseudo = 1;
21599let isCodeGenOnly = 1;
21600let opNewValue = 1;
21601}
21602def S2_storerhnewgp : HInst<
21603(outs),
21604(ins u31_1Imm:$Ii, IntRegs:$Nt8),
21605"memh(gp+#$Ii) = $Nt8.new",
21606tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
21607let Inst{12-11} = 0b01;
21608let Inst{24-21} = 0b0101;
21609let Inst{31-27} = 0b01001;
21610let accessSize = HalfWordAccess;
21611let isNVStore = 1;
21612let isNewValue = 1;
21613let isRestrictNoSlot1Store = 1;
21614let mayStore = 1;
21615let Uses = [GP];
21616let BaseOpcode = "S2_storerhabs";
21617let isPredicable = 1;
21618let opExtendable = 0;
21619let isExtentSigned = 0;
21620let opExtentBits = 17;
21621let opExtentAlign = 1;
21622let opNewValue = 1;
21623}
21624def S2_storeri_io : HInst<
21625(outs),
21626(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
21627"memw($Rs32+#$Ii) = $Rt32",
21628tc_ae5babd7, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
21629let Inst{24-21} = 0b1100;
21630let Inst{31-27} = 0b10100;
21631let addrMode = BaseImmOffset;
21632let accessSize = WordAccess;
21633let mayStore = 1;
21634let BaseOpcode = "S2_storeri_io";
21635let CextOpcode = "S2_storeri";
21636let InputType = "imm";
21637let isPredicable = 1;
21638let isNVStorable = 1;
21639let isExtendable = 1;
21640let opExtendable = 1;
21641let isExtentSigned = 1;
21642let opExtentBits = 13;
21643let opExtentAlign = 2;
21644}
21645def S2_storeri_pbr : HInst<
21646(outs IntRegs:$Rx32),
21647(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21648"memw($Rx32++$Mu2:brev) = $Rt32",
21649tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21650let Inst{7-0} = 0b00000000;
21651let Inst{31-21} = 0b10101111100;
21652let addrMode = PostInc;
21653let accessSize = WordAccess;
21654let mayStore = 1;
21655let BaseOpcode = "S2_storeri_pbr";
21656let isNVStorable = 1;
21657let Constraints = "$Rx32 = $Rx32in";
21658}
21659def S2_storeri_pci : HInst<
21660(outs IntRegs:$Rx32),
21661(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21662"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21663tc_b4dc7630, TypeST>, Enc_79b8c8, AddrModeRel {
21664let Inst{2-0} = 0b000;
21665let Inst{7-7} = 0b0;
21666let Inst{31-21} = 0b10101001100;
21667let addrMode = PostInc;
21668let accessSize = WordAccess;
21669let mayStore = 1;
21670let Uses = [CS];
21671let BaseOpcode = "S2_storeri_pci";
21672let isNVStorable = 1;
21673let Constraints = "$Rx32 = $Rx32in";
21674}
21675def S2_storeri_pcr : HInst<
21676(outs IntRegs:$Rx32),
21677(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21678"memw($Rx32++I:circ($Mu2)) = $Rt32",
21679tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21680let Inst{7-0} = 0b00000010;
21681let Inst{31-21} = 0b10101001100;
21682let addrMode = PostInc;
21683let accessSize = WordAccess;
21684let mayStore = 1;
21685let Uses = [CS];
21686let BaseOpcode = "S2_storeri_pcr";
21687let isNVStorable = 1;
21688let Constraints = "$Rx32 = $Rx32in";
21689}
21690def S2_storeri_pi : HInst<
21691(outs IntRegs:$Rx32),
21692(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
21693"memw($Rx32++#$Ii) = $Rt32",
21694tc_a2b365d2, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
21695let Inst{2-0} = 0b000;
21696let Inst{7-7} = 0b0;
21697let Inst{13-13} = 0b0;
21698let Inst{31-21} = 0b10101011100;
21699let addrMode = PostInc;
21700let accessSize = WordAccess;
21701let mayStore = 1;
21702let BaseOpcode = "S2_storeri_pi";
21703let CextOpcode = "S2_storeri";
21704let isPredicable = 1;
21705let isNVStorable = 1;
21706let Constraints = "$Rx32 = $Rx32in";
21707}
21708def S2_storeri_pr : HInst<
21709(outs IntRegs:$Rx32),
21710(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21711"memw($Rx32++$Mu2) = $Rt32",
21712tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21713let Inst{7-0} = 0b00000000;
21714let Inst{31-21} = 0b10101101100;
21715let addrMode = PostInc;
21716let accessSize = WordAccess;
21717let mayStore = 1;
21718let BaseOpcode = "S2_storeri_pr";
21719let isNVStorable = 1;
21720let Constraints = "$Rx32 = $Rx32in";
21721}
21722def S2_storeri_zomap : HInst<
21723(outs),
21724(ins IntRegs:$Rs32, IntRegs:$Rt32),
21725"memw($Rs32) = $Rt32",
21726tc_ae5babd7, TypeMAPPING> {
21727let isPseudo = 1;
21728let isCodeGenOnly = 1;
21729}
21730def S2_storerigp : HInst<
21731(outs),
21732(ins u30_2Imm:$Ii, IntRegs:$Rt32),
21733"memw(gp+#$Ii) = $Rt32",
21734tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
21735let Inst{24-21} = 0b0100;
21736let Inst{31-27} = 0b01001;
21737let accessSize = WordAccess;
21738let mayStore = 1;
21739let Uses = [GP];
21740let BaseOpcode = "S2_storeriabs";
21741let isPredicable = 1;
21742let isNVStorable = 1;
21743let opExtendable = 0;
21744let isExtentSigned = 0;
21745let opExtentBits = 18;
21746let opExtentAlign = 2;
21747}
21748def S2_storerinew_io : HInst<
21749(outs),
21750(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
21751"memw($Rs32+#$Ii) = $Nt8.new",
21752tc_5deb5e47, TypeST>, Enc_690862, AddrModeRel {
21753let Inst{12-11} = 0b10;
21754let Inst{24-21} = 0b1101;
21755let Inst{31-27} = 0b10100;
21756let addrMode = BaseImmOffset;
21757let accessSize = WordAccess;
21758let isNVStore = 1;
21759let isNewValue = 1;
21760let isRestrictNoSlot1Store = 1;
21761let mayStore = 1;
21762let BaseOpcode = "S2_storeri_io";
21763let CextOpcode = "S2_storeri";
21764let InputType = "imm";
21765let isPredicable = 1;
21766let isExtendable = 1;
21767let opExtendable = 1;
21768let isExtentSigned = 1;
21769let opExtentBits = 13;
21770let opExtentAlign = 2;
21771let opNewValue = 2;
21772}
21773def S2_storerinew_pbr : HInst<
21774(outs IntRegs:$Rx32),
21775(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21776"memw($Rx32++$Mu2:brev) = $Nt8.new",
21777tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21778let Inst{7-0} = 0b00000000;
21779let Inst{12-11} = 0b10;
21780let Inst{31-21} = 0b10101111101;
21781let addrMode = PostInc;
21782let accessSize = WordAccess;
21783let isNVStore = 1;
21784let isNewValue = 1;
21785let isRestrictNoSlot1Store = 1;
21786let mayStore = 1;
21787let BaseOpcode = "S2_storeri_pbr";
21788let opNewValue = 3;
21789let Constraints = "$Rx32 = $Rx32in";
21790}
21791def S2_storerinew_pci : HInst<
21792(outs IntRegs:$Rx32),
21793(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21794"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21795tc_addc37a8, TypeST>, Enc_3f97c8, AddrModeRel {
21796let Inst{2-0} = 0b000;
21797let Inst{7-7} = 0b0;
21798let Inst{12-11} = 0b10;
21799let Inst{31-21} = 0b10101001101;
21800let addrMode = PostInc;
21801let accessSize = WordAccess;
21802let isNVStore = 1;
21803let isNewValue = 1;
21804let isRestrictNoSlot1Store = 1;
21805let mayStore = 1;
21806let Uses = [CS];
21807let BaseOpcode = "S2_storeri_pci";
21808let opNewValue = 4;
21809let Constraints = "$Rx32 = $Rx32in";
21810}
21811def S2_storerinew_pcr : HInst<
21812(outs IntRegs:$Rx32),
21813(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21814"memw($Rx32++I:circ($Mu2)) = $Nt8.new",
21815tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21816let Inst{7-0} = 0b00000010;
21817let Inst{12-11} = 0b10;
21818let Inst{31-21} = 0b10101001101;
21819let addrMode = PostInc;
21820let accessSize = WordAccess;
21821let isNVStore = 1;
21822let isNewValue = 1;
21823let isRestrictNoSlot1Store = 1;
21824let mayStore = 1;
21825let Uses = [CS];
21826let BaseOpcode = "S2_storeri_pcr";
21827let opNewValue = 3;
21828let Constraints = "$Rx32 = $Rx32in";
21829}
21830def S2_storerinew_pi : HInst<
21831(outs IntRegs:$Rx32),
21832(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
21833"memw($Rx32++#$Ii) = $Nt8.new",
21834tc_92240447, TypeST>, Enc_223005, AddrModeRel {
21835let Inst{2-0} = 0b000;
21836let Inst{7-7} = 0b0;
21837let Inst{13-11} = 0b010;
21838let Inst{31-21} = 0b10101011101;
21839let addrMode = PostInc;
21840let accessSize = WordAccess;
21841let isNVStore = 1;
21842let isNewValue = 1;
21843let isRestrictNoSlot1Store = 1;
21844let mayStore = 1;
21845let BaseOpcode = "S2_storeri_pi";
21846let isPredicable = 1;
21847let opNewValue = 3;
21848let Constraints = "$Rx32 = $Rx32in";
21849}
21850def S2_storerinew_pr : HInst<
21851(outs IntRegs:$Rx32),
21852(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21853"memw($Rx32++$Mu2) = $Nt8.new",
21854tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21855let Inst{7-0} = 0b00000000;
21856let Inst{12-11} = 0b10;
21857let Inst{31-21} = 0b10101101101;
21858let addrMode = PostInc;
21859let accessSize = WordAccess;
21860let isNVStore = 1;
21861let isNewValue = 1;
21862let isRestrictNoSlot1Store = 1;
21863let mayStore = 1;
21864let BaseOpcode = "S2_storeri_pr";
21865let opNewValue = 3;
21866let Constraints = "$Rx32 = $Rx32in";
21867}
21868def S2_storerinew_zomap : HInst<
21869(outs),
21870(ins IntRegs:$Rs32, IntRegs:$Nt8),
21871"memw($Rs32) = $Nt8.new",
21872tc_5deb5e47, TypeMAPPING> {
21873let isPseudo = 1;
21874let isCodeGenOnly = 1;
21875let opNewValue = 1;
21876}
21877def S2_storerinewgp : HInst<
21878(outs),
21879(ins u30_2Imm:$Ii, IntRegs:$Nt8),
21880"memw(gp+#$Ii) = $Nt8.new",
21881tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
21882let Inst{12-11} = 0b10;
21883let Inst{24-21} = 0b0101;
21884let Inst{31-27} = 0b01001;
21885let accessSize = WordAccess;
21886let isNVStore = 1;
21887let isNewValue = 1;
21888let isRestrictNoSlot1Store = 1;
21889let mayStore = 1;
21890let Uses = [GP];
21891let BaseOpcode = "S2_storeriabs";
21892let isPredicable = 1;
21893let opExtendable = 0;
21894let isExtentSigned = 0;
21895let opExtentBits = 18;
21896let opExtentAlign = 2;
21897let opNewValue = 1;
21898}
21899def S2_storew_locked : HInst<
21900(outs PredRegs:$Pd4),
21901(ins IntRegs:$Rs32, IntRegs:$Rt32),
21902"memw_locked($Rs32,$Pd4) = $Rt32",
21903tc_6f42bc60, TypeST>, Enc_c2b48e {
21904let Inst{7-2} = 0b000000;
21905let Inst{13-13} = 0b0;
21906let Inst{31-21} = 0b10100000101;
21907let accessSize = WordAccess;
21908let isPredicateLate = 1;
21909let isSoloAX = 1;
21910let mayStore = 1;
21911}
21912def S2_svsathb : HInst<
21913(outs IntRegs:$Rd32),
21914(ins IntRegs:$Rs32),
21915"$Rd32 = vsathb($Rs32)",
21916tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
21917let Inst{13-5} = 0b000000000;
21918let Inst{31-21} = 0b10001100100;
21919let hasNewValue = 1;
21920let opNewValue = 0;
21921let Defs = [USR_OVF];
21922}
21923def S2_svsathub : HInst<
21924(outs IntRegs:$Rd32),
21925(ins IntRegs:$Rs32),
21926"$Rd32 = vsathub($Rs32)",
21927tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
21928let Inst{13-5} = 0b000000010;
21929let Inst{31-21} = 0b10001100100;
21930let hasNewValue = 1;
21931let opNewValue = 0;
21932let Defs = [USR_OVF];
21933}
21934def S2_tableidxb : HInst<
21935(outs IntRegs:$Rx32),
21936(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21937"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
21938tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
21939let Inst{31-22} = 0b1000011100;
21940let hasNewValue = 1;
21941let opNewValue = 0;
21942let prefersSlot3 = 1;
21943let Constraints = "$Rx32 = $Rx32in";
21944}
21945def S2_tableidxb_goodsyntax : HInst<
21946(outs IntRegs:$Rx32),
21947(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21948"$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
21949tc_bb831a7c, TypeS_2op> {
21950let hasNewValue = 1;
21951let opNewValue = 0;
21952let isPseudo = 1;
21953let isCodeGenOnly = 1;
21954let Constraints = "$Rx32 = $Rx32in";
21955}
21956def S2_tableidxd : HInst<
21957(outs IntRegs:$Rx32),
21958(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21959"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
21960tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
21961let Inst{31-22} = 0b1000011111;
21962let hasNewValue = 1;
21963let opNewValue = 0;
21964let prefersSlot3 = 1;
21965let Constraints = "$Rx32 = $Rx32in";
21966}
21967def S2_tableidxd_goodsyntax : HInst<
21968(outs IntRegs:$Rx32),
21969(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21970"$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
21971tc_bb831a7c, TypeS_2op> {
21972let hasNewValue = 1;
21973let opNewValue = 0;
21974let isPseudo = 1;
21975let Constraints = "$Rx32 = $Rx32in";
21976}
21977def S2_tableidxh : HInst<
21978(outs IntRegs:$Rx32),
21979(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21980"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
21981tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
21982let Inst{31-22} = 0b1000011101;
21983let hasNewValue = 1;
21984let opNewValue = 0;
21985let prefersSlot3 = 1;
21986let Constraints = "$Rx32 = $Rx32in";
21987}
21988def S2_tableidxh_goodsyntax : HInst<
21989(outs IntRegs:$Rx32),
21990(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21991"$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
21992tc_bb831a7c, TypeS_2op> {
21993let hasNewValue = 1;
21994let opNewValue = 0;
21995let isPseudo = 1;
21996let Constraints = "$Rx32 = $Rx32in";
21997}
21998def S2_tableidxw : HInst<
21999(outs IntRegs:$Rx32),
22000(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22001"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
22002tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22003let Inst{31-22} = 0b1000011110;
22004let hasNewValue = 1;
22005let opNewValue = 0;
22006let prefersSlot3 = 1;
22007let Constraints = "$Rx32 = $Rx32in";
22008}
22009def S2_tableidxw_goodsyntax : HInst<
22010(outs IntRegs:$Rx32),
22011(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22012"$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
22013tc_bb831a7c, TypeS_2op> {
22014let hasNewValue = 1;
22015let opNewValue = 0;
22016let isPseudo = 1;
22017let Constraints = "$Rx32 = $Rx32in";
22018}
22019def S2_togglebit_i : HInst<
22020(outs IntRegs:$Rd32),
22021(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22022"$Rd32 = togglebit($Rs32,#$Ii)",
22023tc_5da50c4b, TypeS_2op>, Enc_a05677 {
22024let Inst{7-5} = 0b010;
22025let Inst{13-13} = 0b0;
22026let Inst{31-21} = 0b10001100110;
22027let hasNewValue = 1;
22028let opNewValue = 0;
22029}
22030def S2_togglebit_r : HInst<
22031(outs IntRegs:$Rd32),
22032(ins IntRegs:$Rs32, IntRegs:$Rt32),
22033"$Rd32 = togglebit($Rs32,$Rt32)",
22034tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
22035let Inst{7-5} = 0b100;
22036let Inst{13-13} = 0b0;
22037let Inst{31-21} = 0b11000110100;
22038let hasNewValue = 1;
22039let opNewValue = 0;
22040}
22041def S2_tstbit_i : HInst<
22042(outs PredRegs:$Pd4),
22043(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22044"$Pd4 = tstbit($Rs32,#$Ii)",
22045tc_a1297125, TypeS_2op>, Enc_83ee64 {
22046let Inst{7-2} = 0b000000;
22047let Inst{13-13} = 0b0;
22048let Inst{31-21} = 0b10000101000;
22049}
22050def S2_tstbit_r : HInst<
22051(outs PredRegs:$Pd4),
22052(ins IntRegs:$Rs32, IntRegs:$Rt32),
22053"$Pd4 = tstbit($Rs32,$Rt32)",
22054tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22055let Inst{7-2} = 0b000000;
22056let Inst{13-13} = 0b0;
22057let Inst{31-21} = 0b11000111000;
22058}
22059def S2_valignib : HInst<
22060(outs DoubleRegs:$Rdd32),
22061(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
22062"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
22063tc_6fc5dbea, TypeS_3op>, Enc_729ff7 {
22064let Inst{13-13} = 0b0;
22065let Inst{31-21} = 0b11000000000;
22066}
22067def S2_valignrb : HInst<
22068(outs DoubleRegs:$Rdd32),
22069(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
22070"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
22071tc_6fc5dbea, TypeS_3op>, Enc_8c6530 {
22072let Inst{7-7} = 0b0;
22073let Inst{13-13} = 0b0;
22074let Inst{31-21} = 0b11000010000;
22075}
22076def S2_vcnegh : HInst<
22077(outs DoubleRegs:$Rdd32),
22078(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22079"$Rdd32 = vcnegh($Rss32,$Rt32)",
22080tc_8a825db2, TypeS_3op>, Enc_927852 {
22081let Inst{7-5} = 0b010;
22082let Inst{13-13} = 0b0;
22083let Inst{31-21} = 0b11000011110;
22084let prefersSlot3 = 1;
22085let Defs = [USR_OVF];
22086}
22087def S2_vcrotate : HInst<
22088(outs DoubleRegs:$Rdd32),
22089(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22090"$Rdd32 = vcrotate($Rss32,$Rt32)",
22091tc_0dfac0a7, TypeS_3op>, Enc_927852 {
22092let Inst{7-5} = 0b000;
22093let Inst{13-13} = 0b0;
22094let Inst{31-21} = 0b11000011110;
22095let prefersSlot3 = 1;
22096let Defs = [USR_OVF];
22097}
22098def S2_vrcnegh : HInst<
22099(outs DoubleRegs:$Rxx32),
22100(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
22101"$Rxx32 += vrcnegh($Rss32,$Rt32)",
22102tc_7f8ae742, TypeS_3op>, Enc_1aa186 {
22103let Inst{7-5} = 0b111;
22104let Inst{13-13} = 0b1;
22105let Inst{31-21} = 0b11001011001;
22106let prefersSlot3 = 1;
22107let Constraints = "$Rxx32 = $Rxx32in";
22108}
22109def S2_vrndpackwh : HInst<
22110(outs IntRegs:$Rd32),
22111(ins DoubleRegs:$Rss32),
22112"$Rd32 = vrndwh($Rss32)",
22113tc_e3d699e3, TypeS_2op>, Enc_90cd8b {
22114let Inst{13-5} = 0b000000100;
22115let Inst{31-21} = 0b10001000100;
22116let hasNewValue = 1;
22117let opNewValue = 0;
22118let prefersSlot3 = 1;
22119}
22120def S2_vrndpackwhs : HInst<
22121(outs IntRegs:$Rd32),
22122(ins DoubleRegs:$Rss32),
22123"$Rd32 = vrndwh($Rss32):sat",
22124tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
22125let Inst{13-5} = 0b000000110;
22126let Inst{31-21} = 0b10001000100;
22127let hasNewValue = 1;
22128let opNewValue = 0;
22129let prefersSlot3 = 1;
22130let Defs = [USR_OVF];
22131}
22132def S2_vsathb : HInst<
22133(outs IntRegs:$Rd32),
22134(ins DoubleRegs:$Rss32),
22135"$Rd32 = vsathb($Rss32)",
22136tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22137let Inst{13-5} = 0b000000110;
22138let Inst{31-21} = 0b10001000000;
22139let hasNewValue = 1;
22140let opNewValue = 0;
22141let Defs = [USR_OVF];
22142}
22143def S2_vsathb_nopack : HInst<
22144(outs DoubleRegs:$Rdd32),
22145(ins DoubleRegs:$Rss32),
22146"$Rdd32 = vsathb($Rss32)",
22147tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22148let Inst{13-5} = 0b000000111;
22149let Inst{31-21} = 0b10000000000;
22150let Defs = [USR_OVF];
22151}
22152def S2_vsathub : HInst<
22153(outs IntRegs:$Rd32),
22154(ins DoubleRegs:$Rss32),
22155"$Rd32 = vsathub($Rss32)",
22156tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22157let Inst{13-5} = 0b000000000;
22158let Inst{31-21} = 0b10001000000;
22159let hasNewValue = 1;
22160let opNewValue = 0;
22161let Defs = [USR_OVF];
22162}
22163def S2_vsathub_nopack : HInst<
22164(outs DoubleRegs:$Rdd32),
22165(ins DoubleRegs:$Rss32),
22166"$Rdd32 = vsathub($Rss32)",
22167tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22168let Inst{13-5} = 0b000000100;
22169let Inst{31-21} = 0b10000000000;
22170let Defs = [USR_OVF];
22171}
22172def S2_vsatwh : HInst<
22173(outs IntRegs:$Rd32),
22174(ins DoubleRegs:$Rss32),
22175"$Rd32 = vsatwh($Rss32)",
22176tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22177let Inst{13-5} = 0b000000010;
22178let Inst{31-21} = 0b10001000000;
22179let hasNewValue = 1;
22180let opNewValue = 0;
22181let Defs = [USR_OVF];
22182}
22183def S2_vsatwh_nopack : HInst<
22184(outs DoubleRegs:$Rdd32),
22185(ins DoubleRegs:$Rss32),
22186"$Rdd32 = vsatwh($Rss32)",
22187tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22188let Inst{13-5} = 0b000000110;
22189let Inst{31-21} = 0b10000000000;
22190let Defs = [USR_OVF];
22191}
22192def S2_vsatwuh : HInst<
22193(outs IntRegs:$Rd32),
22194(ins DoubleRegs:$Rss32),
22195"$Rd32 = vsatwuh($Rss32)",
22196tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22197let Inst{13-5} = 0b000000100;
22198let Inst{31-21} = 0b10001000000;
22199let hasNewValue = 1;
22200let opNewValue = 0;
22201let Defs = [USR_OVF];
22202}
22203def S2_vsatwuh_nopack : HInst<
22204(outs DoubleRegs:$Rdd32),
22205(ins DoubleRegs:$Rss32),
22206"$Rdd32 = vsatwuh($Rss32)",
22207tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22208let Inst{13-5} = 0b000000101;
22209let Inst{31-21} = 0b10000000000;
22210let Defs = [USR_OVF];
22211}
22212def S2_vsplatrb : HInst<
22213(outs IntRegs:$Rd32),
22214(ins IntRegs:$Rs32),
22215"$Rd32 = vsplatb($Rs32)",
22216tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22217let Inst{13-5} = 0b000000111;
22218let Inst{31-21} = 0b10001100010;
22219let hasNewValue = 1;
22220let opNewValue = 0;
22221let isReMaterializable = 1;
22222let isAsCheapAsAMove = 1;
22223}
22224def S2_vsplatrh : HInst<
22225(outs DoubleRegs:$Rdd32),
22226(ins IntRegs:$Rs32),
22227"$Rdd32 = vsplath($Rs32)",
22228tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22229let Inst{13-5} = 0b000000010;
22230let Inst{31-21} = 0b10000100010;
22231let isReMaterializable = 1;
22232let isAsCheapAsAMove = 1;
22233}
22234def S2_vspliceib : HInst<
22235(outs DoubleRegs:$Rdd32),
22236(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
22237"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
22238tc_6fc5dbea, TypeS_3op>, Enc_d50cd3 {
22239let Inst{13-13} = 0b0;
22240let Inst{31-21} = 0b11000000100;
22241}
22242def S2_vsplicerb : HInst<
22243(outs DoubleRegs:$Rdd32),
22244(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
22245"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
22246tc_6fc5dbea, TypeS_3op>, Enc_dbd70c {
22247let Inst{7-7} = 0b0;
22248let Inst{13-13} = 0b0;
22249let Inst{31-21} = 0b11000010100;
22250}
22251def S2_vsxtbh : HInst<
22252(outs DoubleRegs:$Rdd32),
22253(ins IntRegs:$Rs32),
22254"$Rdd32 = vsxtbh($Rs32)",
22255tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22256let Inst{13-5} = 0b000000000;
22257let Inst{31-21} = 0b10000100000;
22258let isReMaterializable = 1;
22259let isAsCheapAsAMove = 1;
22260}
22261def S2_vsxthw : HInst<
22262(outs DoubleRegs:$Rdd32),
22263(ins IntRegs:$Rs32),
22264"$Rdd32 = vsxthw($Rs32)",
22265tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22266let Inst{13-5} = 0b000000100;
22267let Inst{31-21} = 0b10000100000;
22268let isReMaterializable = 1;
22269let isAsCheapAsAMove = 1;
22270}
22271def S2_vtrunehb : HInst<
22272(outs IntRegs:$Rd32),
22273(ins DoubleRegs:$Rss32),
22274"$Rd32 = vtrunehb($Rss32)",
22275tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22276let Inst{13-5} = 0b000000010;
22277let Inst{31-21} = 0b10001000100;
22278let hasNewValue = 1;
22279let opNewValue = 0;
22280}
22281def S2_vtrunewh : HInst<
22282(outs DoubleRegs:$Rdd32),
22283(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22284"$Rdd32 = vtrunewh($Rss32,$Rtt32)",
22285tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22286let Inst{7-5} = 0b010;
22287let Inst{13-13} = 0b0;
22288let Inst{31-21} = 0b11000001100;
22289}
22290def S2_vtrunohb : HInst<
22291(outs IntRegs:$Rd32),
22292(ins DoubleRegs:$Rss32),
22293"$Rd32 = vtrunohb($Rss32)",
22294tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22295let Inst{13-5} = 0b000000000;
22296let Inst{31-21} = 0b10001000100;
22297let hasNewValue = 1;
22298let opNewValue = 0;
22299}
22300def S2_vtrunowh : HInst<
22301(outs DoubleRegs:$Rdd32),
22302(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22303"$Rdd32 = vtrunowh($Rss32,$Rtt32)",
22304tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22305let Inst{7-5} = 0b100;
22306let Inst{13-13} = 0b0;
22307let Inst{31-21} = 0b11000001100;
22308}
22309def S2_vzxtbh : HInst<
22310(outs DoubleRegs:$Rdd32),
22311(ins IntRegs:$Rs32),
22312"$Rdd32 = vzxtbh($Rs32)",
22313tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22314let Inst{13-5} = 0b000000010;
22315let Inst{31-21} = 0b10000100000;
22316let isReMaterializable = 1;
22317let isAsCheapAsAMove = 1;
22318}
22319def S2_vzxthw : HInst<
22320(outs DoubleRegs:$Rdd32),
22321(ins IntRegs:$Rs32),
22322"$Rdd32 = vzxthw($Rs32)",
22323tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22324let Inst{13-5} = 0b000000110;
22325let Inst{31-21} = 0b10000100000;
22326let isReMaterializable = 1;
22327let isAsCheapAsAMove = 1;
22328}
22329def S4_addaddi : HInst<
22330(outs IntRegs:$Rd32),
22331(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
22332"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
22333tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
22334let Inst{31-23} = 0b110110110;
22335let hasNewValue = 1;
22336let opNewValue = 0;
22337let prefersSlot3 = 1;
22338let isExtendable = 1;
22339let opExtendable = 3;
22340let isExtentSigned = 1;
22341let opExtentBits = 6;
22342let opExtentAlign = 0;
22343}
22344def S4_addi_asl_ri : HInst<
22345(outs IntRegs:$Rx32),
22346(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22347"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
22348tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22349let Inst{2-0} = 0b100;
22350let Inst{4-4} = 0b0;
22351let Inst{31-24} = 0b11011110;
22352let hasNewValue = 1;
22353let opNewValue = 0;
22354let prefersSlot3 = 1;
22355let isExtendable = 1;
22356let opExtendable = 1;
22357let isExtentSigned = 0;
22358let opExtentBits = 8;
22359let opExtentAlign = 0;
22360let Constraints = "$Rx32 = $Rx32in";
22361}
22362def S4_addi_lsr_ri : HInst<
22363(outs IntRegs:$Rx32),
22364(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22365"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
22366tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22367let Inst{2-0} = 0b100;
22368let Inst{4-4} = 0b1;
22369let Inst{31-24} = 0b11011110;
22370let hasNewValue = 1;
22371let opNewValue = 0;
22372let prefersSlot3 = 1;
22373let isExtendable = 1;
22374let opExtendable = 1;
22375let isExtentSigned = 0;
22376let opExtentBits = 8;
22377let opExtentAlign = 0;
22378let Constraints = "$Rx32 = $Rx32in";
22379}
22380def S4_andi_asl_ri : HInst<
22381(outs IntRegs:$Rx32),
22382(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22383"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
22384tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22385let Inst{2-0} = 0b000;
22386let Inst{4-4} = 0b0;
22387let Inst{31-24} = 0b11011110;
22388let hasNewValue = 1;
22389let opNewValue = 0;
22390let prefersSlot3 = 1;
22391let isExtendable = 1;
22392let opExtendable = 1;
22393let isExtentSigned = 0;
22394let opExtentBits = 8;
22395let opExtentAlign = 0;
22396let Constraints = "$Rx32 = $Rx32in";
22397}
22398def S4_andi_lsr_ri : HInst<
22399(outs IntRegs:$Rx32),
22400(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22401"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
22402tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22403let Inst{2-0} = 0b000;
22404let Inst{4-4} = 0b1;
22405let Inst{31-24} = 0b11011110;
22406let hasNewValue = 1;
22407let opNewValue = 0;
22408let prefersSlot3 = 1;
22409let isExtendable = 1;
22410let opExtendable = 1;
22411let isExtentSigned = 0;
22412let opExtentBits = 8;
22413let opExtentAlign = 0;
22414let Constraints = "$Rx32 = $Rx32in";
22415}
22416def S4_clbaddi : HInst<
22417(outs IntRegs:$Rd32),
22418(ins IntRegs:$Rs32, s6_0Imm:$Ii),
22419"$Rd32 = add(clb($Rs32),#$Ii)",
22420tc_a08b630b, TypeS_2op>, Enc_9fae8a {
22421let Inst{7-5} = 0b000;
22422let Inst{31-21} = 0b10001100001;
22423let hasNewValue = 1;
22424let opNewValue = 0;
22425let prefersSlot3 = 1;
22426}
22427def S4_clbpaddi : HInst<
22428(outs IntRegs:$Rd32),
22429(ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
22430"$Rd32 = add(clb($Rss32),#$Ii)",
22431tc_a08b630b, TypeS_2op>, Enc_a1640c {
22432let Inst{7-5} = 0b010;
22433let Inst{31-21} = 0b10001000011;
22434let hasNewValue = 1;
22435let opNewValue = 0;
22436let prefersSlot3 = 1;
22437}
22438def S4_clbpnorm : HInst<
22439(outs IntRegs:$Rd32),
22440(ins DoubleRegs:$Rss32),
22441"$Rd32 = normamt($Rss32)",
22442tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
22443let Inst{13-5} = 0b000000000;
22444let Inst{31-21} = 0b10001000011;
22445let hasNewValue = 1;
22446let opNewValue = 0;
22447let prefersSlot3 = 1;
22448}
22449def S4_extract : HInst<
22450(outs IntRegs:$Rd32),
22451(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
22452"$Rd32 = extract($Rs32,#$Ii,#$II)",
22453tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
22454let Inst{13-13} = 0b0;
22455let Inst{31-23} = 0b100011011;
22456let hasNewValue = 1;
22457let opNewValue = 0;
22458let prefersSlot3 = 1;
22459}
22460def S4_extract_rp : HInst<
22461(outs IntRegs:$Rd32),
22462(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
22463"$Rd32 = extract($Rs32,$Rtt32)",
22464tc_a08b630b, TypeS_3op>, Enc_e07374 {
22465let Inst{7-5} = 0b010;
22466let Inst{13-13} = 0b0;
22467let Inst{31-21} = 0b11001001000;
22468let hasNewValue = 1;
22469let opNewValue = 0;
22470let prefersSlot3 = 1;
22471}
22472def S4_extractp : HInst<
22473(outs DoubleRegs:$Rdd32),
22474(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
22475"$Rdd32 = extract($Rss32,#$Ii,#$II)",
22476tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
22477let Inst{31-24} = 0b10001010;
22478let prefersSlot3 = 1;
22479}
22480def S4_extractp_rp : HInst<
22481(outs DoubleRegs:$Rdd32),
22482(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22483"$Rdd32 = extract($Rss32,$Rtt32)",
22484tc_a08b630b, TypeS_3op>, Enc_a56825 {
22485let Inst{7-5} = 0b100;
22486let Inst{13-13} = 0b0;
22487let Inst{31-21} = 0b11000001110;
22488let prefersSlot3 = 1;
22489}
22490def S4_lsli : HInst<
22491(outs IntRegs:$Rd32),
22492(ins s6_0Imm:$Ii, IntRegs:$Rt32),
22493"$Rd32 = lsl(#$Ii,$Rt32)",
22494tc_5da50c4b, TypeS_3op>, Enc_fef969 {
22495let Inst{7-6} = 0b11;
22496let Inst{13-13} = 0b0;
22497let Inst{31-21} = 0b11000110100;
22498let hasNewValue = 1;
22499let opNewValue = 0;
22500}
22501def S4_ntstbit_i : HInst<
22502(outs PredRegs:$Pd4),
22503(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22504"$Pd4 = !tstbit($Rs32,#$Ii)",
22505tc_a1297125, TypeS_2op>, Enc_83ee64 {
22506let Inst{7-2} = 0b000000;
22507let Inst{13-13} = 0b0;
22508let Inst{31-21} = 0b10000101001;
22509}
22510def S4_ntstbit_r : HInst<
22511(outs PredRegs:$Pd4),
22512(ins IntRegs:$Rs32, IntRegs:$Rt32),
22513"$Pd4 = !tstbit($Rs32,$Rt32)",
22514tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22515let Inst{7-2} = 0b000000;
22516let Inst{13-13} = 0b0;
22517let Inst{31-21} = 0b11000111001;
22518}
22519def S4_or_andi : HInst<
22520(outs IntRegs:$Rx32),
22521(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22522"$Rx32 |= and($Rs32,#$Ii)",
22523tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22524let Inst{31-22} = 0b1101101000;
22525let hasNewValue = 1;
22526let opNewValue = 0;
22527let prefersSlot3 = 1;
22528let InputType = "imm";
22529let isExtendable = 1;
22530let opExtendable = 3;
22531let isExtentSigned = 1;
22532let opExtentBits = 10;
22533let opExtentAlign = 0;
22534let Constraints = "$Rx32 = $Rx32in";
22535}
22536def S4_or_andix : HInst<
22537(outs IntRegs:$Rx32),
22538(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
22539"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22540tc_a4e22bbd, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> {
22541let Inst{31-22} = 0b1101101001;
22542let hasNewValue = 1;
22543let opNewValue = 0;
22544let prefersSlot3 = 1;
22545let isExtendable = 1;
22546let opExtendable = 3;
22547let isExtentSigned = 1;
22548let opExtentBits = 10;
22549let opExtentAlign = 0;
22550let Constraints = "$Rx32 = $Rx32in";
22551}
22552def S4_or_ori : HInst<
22553(outs IntRegs:$Rx32),
22554(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22555"$Rx32 |= or($Rs32,#$Ii)",
22556tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22557let Inst{31-22} = 0b1101101010;
22558let hasNewValue = 1;
22559let opNewValue = 0;
22560let prefersSlot3 = 1;
22561let InputType = "imm";
22562let isExtendable = 1;
22563let opExtendable = 3;
22564let isExtentSigned = 1;
22565let opExtentBits = 10;
22566let opExtentAlign = 0;
22567let Constraints = "$Rx32 = $Rx32in";
22568}
22569def S4_ori_asl_ri : HInst<
22570(outs IntRegs:$Rx32),
22571(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22572"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22573tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22574let Inst{2-0} = 0b010;
22575let Inst{4-4} = 0b0;
22576let Inst{31-24} = 0b11011110;
22577let hasNewValue = 1;
22578let opNewValue = 0;
22579let prefersSlot3 = 1;
22580let isExtendable = 1;
22581let opExtendable = 1;
22582let isExtentSigned = 0;
22583let opExtentBits = 8;
22584let opExtentAlign = 0;
22585let Constraints = "$Rx32 = $Rx32in";
22586}
22587def S4_ori_lsr_ri : HInst<
22588(outs IntRegs:$Rx32),
22589(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22590"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22591tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22592let Inst{2-0} = 0b010;
22593let Inst{4-4} = 0b1;
22594let Inst{31-24} = 0b11011110;
22595let hasNewValue = 1;
22596let opNewValue = 0;
22597let prefersSlot3 = 1;
22598let isExtendable = 1;
22599let opExtendable = 1;
22600let isExtentSigned = 0;
22601let opExtentBits = 8;
22602let opExtentAlign = 0;
22603let Constraints = "$Rx32 = $Rx32in";
22604}
22605def S4_parity : HInst<
22606(outs IntRegs:$Rd32),
22607(ins IntRegs:$Rs32, IntRegs:$Rt32),
22608"$Rd32 = parity($Rs32,$Rt32)",
22609tc_a08b630b, TypeALU64>, Enc_5ab2be {
22610let Inst{7-5} = 0b000;
22611let Inst{13-13} = 0b0;
22612let Inst{31-21} = 0b11010101111;
22613let hasNewValue = 1;
22614let opNewValue = 0;
22615let prefersSlot3 = 1;
22616}
22617def S4_pstorerbf_abs : HInst<
22618(outs),
22619(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22620"if (!$Pv4) memb(#$Ii) = $Rt32",
22621tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
22622let Inst{2-2} = 0b1;
22623let Inst{7-7} = 0b1;
22624let Inst{13-13} = 0b0;
22625let Inst{31-18} = 0b10101111000000;
22626let isPredicated = 1;
22627let isPredicatedFalse = 1;
22628let addrMode = Absolute;
22629let accessSize = ByteAccess;
22630let isExtended = 1;
22631let mayStore = 1;
22632let BaseOpcode = "S2_storerbabs";
22633let CextOpcode = "S2_storerb";
22634let isNVStorable = 1;
22635let DecoderNamespace = "MustExtend";
22636let isExtendable = 1;
22637let opExtendable = 1;
22638let isExtentSigned = 0;
22639let opExtentBits = 6;
22640let opExtentAlign = 0;
22641}
22642def S4_pstorerbf_rr : HInst<
22643(outs),
22644(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22645"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22646tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
22647let Inst{31-21} = 0b00110101000;
22648let isPredicated = 1;
22649let isPredicatedFalse = 1;
22650let addrMode = BaseRegOffset;
22651let accessSize = ByteAccess;
22652let mayStore = 1;
22653let BaseOpcode = "S4_storerb_rr";
22654let CextOpcode = "S2_storerb";
22655let InputType = "reg";
22656let isNVStorable = 1;
22657}
22658def S4_pstorerbfnew_abs : HInst<
22659(outs),
22660(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22661"if (!$Pv4.new) memb(#$Ii) = $Rt32",
22662tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
22663let Inst{2-2} = 0b1;
22664let Inst{7-7} = 0b1;
22665let Inst{13-13} = 0b1;
22666let Inst{31-18} = 0b10101111000000;
22667let isPredicated = 1;
22668let isPredicatedFalse = 1;
22669let addrMode = Absolute;
22670let accessSize = ByteAccess;
22671let isPredicatedNew = 1;
22672let isExtended = 1;
22673let mayStore = 1;
22674let BaseOpcode = "S2_storerbabs";
22675let CextOpcode = "S2_storerb";
22676let isNVStorable = 1;
22677let DecoderNamespace = "MustExtend";
22678let isExtendable = 1;
22679let opExtendable = 1;
22680let isExtentSigned = 0;
22681let opExtentBits = 6;
22682let opExtentAlign = 0;
22683}
22684def S4_pstorerbfnew_io : HInst<
22685(outs),
22686(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22687"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22688tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22689let Inst{2-2} = 0b0;
22690let Inst{31-21} = 0b01000110000;
22691let isPredicated = 1;
22692let isPredicatedFalse = 1;
22693let addrMode = BaseImmOffset;
22694let accessSize = ByteAccess;
22695let isPredicatedNew = 1;
22696let mayStore = 1;
22697let BaseOpcode = "S2_storerb_io";
22698let CextOpcode = "S2_storerb";
22699let InputType = "imm";
22700let isNVStorable = 1;
22701let isExtendable = 1;
22702let opExtendable = 2;
22703let isExtentSigned = 0;
22704let opExtentBits = 6;
22705let opExtentAlign = 0;
22706}
22707def S4_pstorerbfnew_rr : HInst<
22708(outs),
22709(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22710"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22711tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
22712let Inst{31-21} = 0b00110111000;
22713let isPredicated = 1;
22714let isPredicatedFalse = 1;
22715let addrMode = BaseRegOffset;
22716let accessSize = ByteAccess;
22717let isPredicatedNew = 1;
22718let mayStore = 1;
22719let BaseOpcode = "S4_storerb_rr";
22720let CextOpcode = "S2_storerb";
22721let InputType = "reg";
22722let isNVStorable = 1;
22723}
22724def S4_pstorerbfnew_zomap : HInst<
22725(outs),
22726(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22727"if (!$Pv4.new) memb($Rs32) = $Rt32",
22728tc_a2b365d2, TypeMAPPING> {
22729let isPseudo = 1;
22730let isCodeGenOnly = 1;
22731}
22732def S4_pstorerbnewf_abs : HInst<
22733(outs),
22734(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22735"if (!$Pv4) memb(#$Ii) = $Nt8.new",
22736tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22737let Inst{2-2} = 0b1;
22738let Inst{7-7} = 0b1;
22739let Inst{13-11} = 0b000;
22740let Inst{31-18} = 0b10101111101000;
22741let isPredicated = 1;
22742let isPredicatedFalse = 1;
22743let addrMode = Absolute;
22744let accessSize = ByteAccess;
22745let isNVStore = 1;
22746let isNewValue = 1;
22747let isExtended = 1;
22748let isRestrictNoSlot1Store = 1;
22749let mayStore = 1;
22750let BaseOpcode = "S2_storerbabs";
22751let CextOpcode = "S2_storerb";
22752let DecoderNamespace = "MustExtend";
22753let isExtendable = 1;
22754let opExtendable = 1;
22755let isExtentSigned = 0;
22756let opExtentBits = 6;
22757let opExtentAlign = 0;
22758let opNewValue = 2;
22759}
22760def S4_pstorerbnewf_rr : HInst<
22761(outs),
22762(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22763"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22764tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22765let Inst{4-3} = 0b00;
22766let Inst{31-21} = 0b00110101101;
22767let isPredicated = 1;
22768let isPredicatedFalse = 1;
22769let addrMode = BaseRegOffset;
22770let accessSize = ByteAccess;
22771let isNVStore = 1;
22772let isNewValue = 1;
22773let isRestrictNoSlot1Store = 1;
22774let mayStore = 1;
22775let BaseOpcode = "S4_storerb_rr";
22776let CextOpcode = "S2_storerb";
22777let InputType = "reg";
22778let opNewValue = 4;
22779}
22780def S4_pstorerbnewfnew_abs : HInst<
22781(outs),
22782(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22783"if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
22784tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22785let Inst{2-2} = 0b1;
22786let Inst{7-7} = 0b1;
22787let Inst{13-11} = 0b100;
22788let Inst{31-18} = 0b10101111101000;
22789let isPredicated = 1;
22790let isPredicatedFalse = 1;
22791let addrMode = Absolute;
22792let accessSize = ByteAccess;
22793let isNVStore = 1;
22794let isPredicatedNew = 1;
22795let isNewValue = 1;
22796let isExtended = 1;
22797let isRestrictNoSlot1Store = 1;
22798let mayStore = 1;
22799let BaseOpcode = "S2_storerbabs";
22800let CextOpcode = "S2_storerb";
22801let DecoderNamespace = "MustExtend";
22802let isExtendable = 1;
22803let opExtendable = 1;
22804let isExtentSigned = 0;
22805let opExtentBits = 6;
22806let opExtentAlign = 0;
22807let opNewValue = 2;
22808}
22809def S4_pstorerbnewfnew_io : HInst<
22810(outs),
22811(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22812"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22813tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
22814let Inst{2-2} = 0b0;
22815let Inst{12-11} = 0b00;
22816let Inst{31-21} = 0b01000110101;
22817let isPredicated = 1;
22818let isPredicatedFalse = 1;
22819let addrMode = BaseImmOffset;
22820let accessSize = ByteAccess;
22821let isNVStore = 1;
22822let isPredicatedNew = 1;
22823let isNewValue = 1;
22824let isRestrictNoSlot1Store = 1;
22825let mayStore = 1;
22826let BaseOpcode = "S2_storerb_io";
22827let CextOpcode = "S2_storerb";
22828let InputType = "imm";
22829let isExtendable = 1;
22830let opExtendable = 2;
22831let isExtentSigned = 0;
22832let opExtentBits = 6;
22833let opExtentAlign = 0;
22834let opNewValue = 3;
22835}
22836def S4_pstorerbnewfnew_rr : HInst<
22837(outs),
22838(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22839"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22840tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
22841let Inst{4-3} = 0b00;
22842let Inst{31-21} = 0b00110111101;
22843let isPredicated = 1;
22844let isPredicatedFalse = 1;
22845let addrMode = BaseRegOffset;
22846let accessSize = ByteAccess;
22847let isNVStore = 1;
22848let isPredicatedNew = 1;
22849let isNewValue = 1;
22850let isRestrictNoSlot1Store = 1;
22851let mayStore = 1;
22852let BaseOpcode = "S4_storerb_rr";
22853let CextOpcode = "S2_storerb";
22854let InputType = "reg";
22855let opNewValue = 4;
22856}
22857def S4_pstorerbnewfnew_zomap : HInst<
22858(outs),
22859(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22860"if (!$Pv4.new) memb($Rs32) = $Nt8.new",
22861tc_92240447, TypeMAPPING> {
22862let isPseudo = 1;
22863let isCodeGenOnly = 1;
22864let opNewValue = 2;
22865}
22866def S4_pstorerbnewt_abs : HInst<
22867(outs),
22868(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22869"if ($Pv4) memb(#$Ii) = $Nt8.new",
22870tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22871let Inst{2-2} = 0b0;
22872let Inst{7-7} = 0b1;
22873let Inst{13-11} = 0b000;
22874let Inst{31-18} = 0b10101111101000;
22875let isPredicated = 1;
22876let addrMode = Absolute;
22877let accessSize = ByteAccess;
22878let isNVStore = 1;
22879let isNewValue = 1;
22880let isExtended = 1;
22881let isRestrictNoSlot1Store = 1;
22882let mayStore = 1;
22883let BaseOpcode = "S2_storerbabs";
22884let CextOpcode = "S2_storerb";
22885let DecoderNamespace = "MustExtend";
22886let isExtendable = 1;
22887let opExtendable = 1;
22888let isExtentSigned = 0;
22889let opExtentBits = 6;
22890let opExtentAlign = 0;
22891let opNewValue = 2;
22892}
22893def S4_pstorerbnewt_rr : HInst<
22894(outs),
22895(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22896"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22897tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22898let Inst{4-3} = 0b00;
22899let Inst{31-21} = 0b00110100101;
22900let isPredicated = 1;
22901let addrMode = BaseRegOffset;
22902let accessSize = ByteAccess;
22903let isNVStore = 1;
22904let isNewValue = 1;
22905let isRestrictNoSlot1Store = 1;
22906let mayStore = 1;
22907let BaseOpcode = "S4_storerb_rr";
22908let CextOpcode = "S2_storerb";
22909let InputType = "reg";
22910let opNewValue = 4;
22911}
22912def S4_pstorerbnewtnew_abs : HInst<
22913(outs),
22914(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22915"if ($Pv4.new) memb(#$Ii) = $Nt8.new",
22916tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22917let Inst{2-2} = 0b0;
22918let Inst{7-7} = 0b1;
22919let Inst{13-11} = 0b100;
22920let Inst{31-18} = 0b10101111101000;
22921let isPredicated = 1;
22922let addrMode = Absolute;
22923let accessSize = ByteAccess;
22924let isNVStore = 1;
22925let isPredicatedNew = 1;
22926let isNewValue = 1;
22927let isExtended = 1;
22928let isRestrictNoSlot1Store = 1;
22929let mayStore = 1;
22930let BaseOpcode = "S2_storerbabs";
22931let CextOpcode = "S2_storerb";
22932let DecoderNamespace = "MustExtend";
22933let isExtendable = 1;
22934let opExtendable = 1;
22935let isExtentSigned = 0;
22936let opExtentBits = 6;
22937let opExtentAlign = 0;
22938let opNewValue = 2;
22939}
22940def S4_pstorerbnewtnew_io : HInst<
22941(outs),
22942(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22943"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22944tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
22945let Inst{2-2} = 0b0;
22946let Inst{12-11} = 0b00;
22947let Inst{31-21} = 0b01000010101;
22948let isPredicated = 1;
22949let addrMode = BaseImmOffset;
22950let accessSize = ByteAccess;
22951let isNVStore = 1;
22952let isPredicatedNew = 1;
22953let isNewValue = 1;
22954let isRestrictNoSlot1Store = 1;
22955let mayStore = 1;
22956let BaseOpcode = "S2_storerb_io";
22957let CextOpcode = "S2_storerb";
22958let InputType = "imm";
22959let isExtendable = 1;
22960let opExtendable = 2;
22961let isExtentSigned = 0;
22962let opExtentBits = 6;
22963let opExtentAlign = 0;
22964let opNewValue = 3;
22965}
22966def S4_pstorerbnewtnew_rr : HInst<
22967(outs),
22968(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22969"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22970tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
22971let Inst{4-3} = 0b00;
22972let Inst{31-21} = 0b00110110101;
22973let isPredicated = 1;
22974let addrMode = BaseRegOffset;
22975let accessSize = ByteAccess;
22976let isNVStore = 1;
22977let isPredicatedNew = 1;
22978let isNewValue = 1;
22979let isRestrictNoSlot1Store = 1;
22980let mayStore = 1;
22981let BaseOpcode = "S4_storerb_rr";
22982let CextOpcode = "S2_storerb";
22983let InputType = "reg";
22984let opNewValue = 4;
22985}
22986def S4_pstorerbnewtnew_zomap : HInst<
22987(outs),
22988(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22989"if ($Pv4.new) memb($Rs32) = $Nt8.new",
22990tc_92240447, TypeMAPPING> {
22991let isPseudo = 1;
22992let isCodeGenOnly = 1;
22993let opNewValue = 2;
22994}
22995def S4_pstorerbt_abs : HInst<
22996(outs),
22997(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22998"if ($Pv4) memb(#$Ii) = $Rt32",
22999tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23000let Inst{2-2} = 0b0;
23001let Inst{7-7} = 0b1;
23002let Inst{13-13} = 0b0;
23003let Inst{31-18} = 0b10101111000000;
23004let isPredicated = 1;
23005let addrMode = Absolute;
23006let accessSize = ByteAccess;
23007let isExtended = 1;
23008let mayStore = 1;
23009let BaseOpcode = "S2_storerbabs";
23010let CextOpcode = "S2_storerb";
23011let isNVStorable = 1;
23012let DecoderNamespace = "MustExtend";
23013let isExtendable = 1;
23014let opExtendable = 1;
23015let isExtentSigned = 0;
23016let opExtentBits = 6;
23017let opExtentAlign = 0;
23018}
23019def S4_pstorerbt_rr : HInst<
23020(outs),
23021(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23022"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23023tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23024let Inst{31-21} = 0b00110100000;
23025let isPredicated = 1;
23026let addrMode = BaseRegOffset;
23027let accessSize = ByteAccess;
23028let mayStore = 1;
23029let BaseOpcode = "S4_storerb_rr";
23030let CextOpcode = "S2_storerb";
23031let InputType = "reg";
23032let isNVStorable = 1;
23033}
23034def S4_pstorerbtnew_abs : HInst<
23035(outs),
23036(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23037"if ($Pv4.new) memb(#$Ii) = $Rt32",
23038tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23039let Inst{2-2} = 0b0;
23040let Inst{7-7} = 0b1;
23041let Inst{13-13} = 0b1;
23042let Inst{31-18} = 0b10101111000000;
23043let isPredicated = 1;
23044let addrMode = Absolute;
23045let accessSize = ByteAccess;
23046let isPredicatedNew = 1;
23047let isExtended = 1;
23048let mayStore = 1;
23049let BaseOpcode = "S2_storerbabs";
23050let CextOpcode = "S2_storerb";
23051let isNVStorable = 1;
23052let DecoderNamespace = "MustExtend";
23053let isExtendable = 1;
23054let opExtendable = 1;
23055let isExtentSigned = 0;
23056let opExtentBits = 6;
23057let opExtentAlign = 0;
23058}
23059def S4_pstorerbtnew_io : HInst<
23060(outs),
23061(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
23062"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
23063tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
23064let Inst{2-2} = 0b0;
23065let Inst{31-21} = 0b01000010000;
23066let isPredicated = 1;
23067let addrMode = BaseImmOffset;
23068let accessSize = ByteAccess;
23069let isPredicatedNew = 1;
23070let mayStore = 1;
23071let BaseOpcode = "S2_storerb_io";
23072let CextOpcode = "S2_storerb";
23073let InputType = "imm";
23074let isNVStorable = 1;
23075let isExtendable = 1;
23076let opExtendable = 2;
23077let isExtentSigned = 0;
23078let opExtentBits = 6;
23079let opExtentAlign = 0;
23080}
23081def S4_pstorerbtnew_rr : HInst<
23082(outs),
23083(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23084"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23085tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23086let Inst{31-21} = 0b00110110000;
23087let isPredicated = 1;
23088let addrMode = BaseRegOffset;
23089let accessSize = ByteAccess;
23090let isPredicatedNew = 1;
23091let mayStore = 1;
23092let BaseOpcode = "S4_storerb_rr";
23093let CextOpcode = "S2_storerb";
23094let InputType = "reg";
23095let isNVStorable = 1;
23096}
23097def S4_pstorerbtnew_zomap : HInst<
23098(outs),
23099(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23100"if ($Pv4.new) memb($Rs32) = $Rt32",
23101tc_a2b365d2, TypeMAPPING> {
23102let isPseudo = 1;
23103let isCodeGenOnly = 1;
23104}
23105def S4_pstorerdf_abs : HInst<
23106(outs),
23107(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23108"if (!$Pv4) memd(#$Ii) = $Rtt32",
23109tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23110let Inst{2-2} = 0b1;
23111let Inst{7-7} = 0b1;
23112let Inst{13-13} = 0b0;
23113let Inst{31-18} = 0b10101111110000;
23114let isPredicated = 1;
23115let isPredicatedFalse = 1;
23116let addrMode = Absolute;
23117let accessSize = DoubleWordAccess;
23118let isExtended = 1;
23119let mayStore = 1;
23120let BaseOpcode = "S2_storerdabs";
23121let CextOpcode = "S2_storerd";
23122let DecoderNamespace = "MustExtend";
23123let isExtendable = 1;
23124let opExtendable = 1;
23125let isExtentSigned = 0;
23126let opExtentBits = 6;
23127let opExtentAlign = 0;
23128}
23129def S4_pstorerdf_rr : HInst<
23130(outs),
23131(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23132"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23133tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23134let Inst{31-21} = 0b00110101110;
23135let isPredicated = 1;
23136let isPredicatedFalse = 1;
23137let addrMode = BaseRegOffset;
23138let accessSize = DoubleWordAccess;
23139let mayStore = 1;
23140let BaseOpcode = "S2_storerd_rr";
23141let CextOpcode = "S2_storerd";
23142let InputType = "reg";
23143}
23144def S4_pstorerdfnew_abs : HInst<
23145(outs),
23146(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23147"if (!$Pv4.new) memd(#$Ii) = $Rtt32",
23148tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23149let Inst{2-2} = 0b1;
23150let Inst{7-7} = 0b1;
23151let Inst{13-13} = 0b1;
23152let Inst{31-18} = 0b10101111110000;
23153let isPredicated = 1;
23154let isPredicatedFalse = 1;
23155let addrMode = Absolute;
23156let accessSize = DoubleWordAccess;
23157let isPredicatedNew = 1;
23158let isExtended = 1;
23159let mayStore = 1;
23160let BaseOpcode = "S2_storerdabs";
23161let CextOpcode = "S2_storerd";
23162let DecoderNamespace = "MustExtend";
23163let isExtendable = 1;
23164let opExtendable = 1;
23165let isExtentSigned = 0;
23166let opExtentBits = 6;
23167let opExtentAlign = 0;
23168}
23169def S4_pstorerdfnew_io : HInst<
23170(outs),
23171(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23172"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23173tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23174let Inst{2-2} = 0b0;
23175let Inst{31-21} = 0b01000110110;
23176let isPredicated = 1;
23177let isPredicatedFalse = 1;
23178let addrMode = BaseImmOffset;
23179let accessSize = DoubleWordAccess;
23180let isPredicatedNew = 1;
23181let mayStore = 1;
23182let BaseOpcode = "S2_storerd_io";
23183let CextOpcode = "S2_storerd";
23184let InputType = "imm";
23185let isExtendable = 1;
23186let opExtendable = 2;
23187let isExtentSigned = 0;
23188let opExtentBits = 9;
23189let opExtentAlign = 3;
23190}
23191def S4_pstorerdfnew_rr : HInst<
23192(outs),
23193(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23194"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23195tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23196let Inst{31-21} = 0b00110111110;
23197let isPredicated = 1;
23198let isPredicatedFalse = 1;
23199let addrMode = BaseRegOffset;
23200let accessSize = DoubleWordAccess;
23201let isPredicatedNew = 1;
23202let mayStore = 1;
23203let BaseOpcode = "S2_storerd_rr";
23204let CextOpcode = "S2_storerd";
23205let InputType = "reg";
23206}
23207def S4_pstorerdfnew_zomap : HInst<
23208(outs),
23209(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23210"if (!$Pv4.new) memd($Rs32) = $Rtt32",
23211tc_a2b365d2, TypeMAPPING> {
23212let isPseudo = 1;
23213let isCodeGenOnly = 1;
23214}
23215def S4_pstorerdt_abs : HInst<
23216(outs),
23217(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23218"if ($Pv4) memd(#$Ii) = $Rtt32",
23219tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23220let Inst{2-2} = 0b0;
23221let Inst{7-7} = 0b1;
23222let Inst{13-13} = 0b0;
23223let Inst{31-18} = 0b10101111110000;
23224let isPredicated = 1;
23225let addrMode = Absolute;
23226let accessSize = DoubleWordAccess;
23227let isExtended = 1;
23228let mayStore = 1;
23229let BaseOpcode = "S2_storerdabs";
23230let CextOpcode = "S2_storerd";
23231let DecoderNamespace = "MustExtend";
23232let isExtendable = 1;
23233let opExtendable = 1;
23234let isExtentSigned = 0;
23235let opExtentBits = 6;
23236let opExtentAlign = 0;
23237}
23238def S4_pstorerdt_rr : HInst<
23239(outs),
23240(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23241"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23242tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23243let Inst{31-21} = 0b00110100110;
23244let isPredicated = 1;
23245let addrMode = BaseRegOffset;
23246let accessSize = DoubleWordAccess;
23247let mayStore = 1;
23248let BaseOpcode = "S2_storerd_rr";
23249let CextOpcode = "S2_storerd";
23250let InputType = "reg";
23251}
23252def S4_pstorerdtnew_abs : HInst<
23253(outs),
23254(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23255"if ($Pv4.new) memd(#$Ii) = $Rtt32",
23256tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23257let Inst{2-2} = 0b0;
23258let Inst{7-7} = 0b1;
23259let Inst{13-13} = 0b1;
23260let Inst{31-18} = 0b10101111110000;
23261let isPredicated = 1;
23262let addrMode = Absolute;
23263let accessSize = DoubleWordAccess;
23264let isPredicatedNew = 1;
23265let isExtended = 1;
23266let mayStore = 1;
23267let BaseOpcode = "S2_storerdabs";
23268let CextOpcode = "S2_storerd";
23269let DecoderNamespace = "MustExtend";
23270let isExtendable = 1;
23271let opExtendable = 1;
23272let isExtentSigned = 0;
23273let opExtentBits = 6;
23274let opExtentAlign = 0;
23275}
23276def S4_pstorerdtnew_io : HInst<
23277(outs),
23278(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23279"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23280tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23281let Inst{2-2} = 0b0;
23282let Inst{31-21} = 0b01000010110;
23283let isPredicated = 1;
23284let addrMode = BaseImmOffset;
23285let accessSize = DoubleWordAccess;
23286let isPredicatedNew = 1;
23287let mayStore = 1;
23288let BaseOpcode = "S2_storerd_io";
23289let CextOpcode = "S2_storerd";
23290let InputType = "imm";
23291let isExtendable = 1;
23292let opExtendable = 2;
23293let isExtentSigned = 0;
23294let opExtentBits = 9;
23295let opExtentAlign = 3;
23296}
23297def S4_pstorerdtnew_rr : HInst<
23298(outs),
23299(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23300"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23301tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23302let Inst{31-21} = 0b00110110110;
23303let isPredicated = 1;
23304let addrMode = BaseRegOffset;
23305let accessSize = DoubleWordAccess;
23306let isPredicatedNew = 1;
23307let mayStore = 1;
23308let BaseOpcode = "S2_storerd_rr";
23309let CextOpcode = "S2_storerd";
23310let InputType = "reg";
23311}
23312def S4_pstorerdtnew_zomap : HInst<
23313(outs),
23314(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23315"if ($Pv4.new) memd($Rs32) = $Rtt32",
23316tc_a2b365d2, TypeMAPPING> {
23317let isPseudo = 1;
23318let isCodeGenOnly = 1;
23319}
23320def S4_pstorerff_abs : HInst<
23321(outs),
23322(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23323"if (!$Pv4) memh(#$Ii) = $Rt32.h",
23324tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23325let Inst{2-2} = 0b1;
23326let Inst{7-7} = 0b1;
23327let Inst{13-13} = 0b0;
23328let Inst{31-18} = 0b10101111011000;
23329let isPredicated = 1;
23330let isPredicatedFalse = 1;
23331let addrMode = Absolute;
23332let accessSize = HalfWordAccess;
23333let isExtended = 1;
23334let mayStore = 1;
23335let BaseOpcode = "S2_storerfabs";
23336let CextOpcode = "S2_storerf";
23337let DecoderNamespace = "MustExtend";
23338let isExtendable = 1;
23339let opExtendable = 1;
23340let isExtentSigned = 0;
23341let opExtentBits = 6;
23342let opExtentAlign = 0;
23343}
23344def S4_pstorerff_rr : HInst<
23345(outs),
23346(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23347"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23348tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23349let Inst{31-21} = 0b00110101011;
23350let isPredicated = 1;
23351let isPredicatedFalse = 1;
23352let addrMode = BaseRegOffset;
23353let accessSize = HalfWordAccess;
23354let mayStore = 1;
23355let BaseOpcode = "S4_storerf_rr";
23356let CextOpcode = "S2_storerf";
23357let InputType = "reg";
23358}
23359def S4_pstorerffnew_abs : HInst<
23360(outs),
23361(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23362"if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
23363tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23364let Inst{2-2} = 0b1;
23365let Inst{7-7} = 0b1;
23366let Inst{13-13} = 0b1;
23367let Inst{31-18} = 0b10101111011000;
23368let isPredicated = 1;
23369let isPredicatedFalse = 1;
23370let addrMode = Absolute;
23371let accessSize = HalfWordAccess;
23372let isPredicatedNew = 1;
23373let isExtended = 1;
23374let mayStore = 1;
23375let BaseOpcode = "S2_storerfabs";
23376let CextOpcode = "S2_storerf";
23377let DecoderNamespace = "MustExtend";
23378let isExtendable = 1;
23379let opExtendable = 1;
23380let isExtentSigned = 0;
23381let opExtentBits = 6;
23382let opExtentAlign = 0;
23383}
23384def S4_pstorerffnew_io : HInst<
23385(outs),
23386(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23387"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23388tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23389let Inst{2-2} = 0b0;
23390let Inst{31-21} = 0b01000110011;
23391let isPredicated = 1;
23392let isPredicatedFalse = 1;
23393let addrMode = BaseImmOffset;
23394let accessSize = HalfWordAccess;
23395let isPredicatedNew = 1;
23396let mayStore = 1;
23397let BaseOpcode = "S2_storerf_io";
23398let CextOpcode = "S2_storerf";
23399let InputType = "imm";
23400let isExtendable = 1;
23401let opExtendable = 2;
23402let isExtentSigned = 0;
23403let opExtentBits = 7;
23404let opExtentAlign = 1;
23405}
23406def S4_pstorerffnew_rr : HInst<
23407(outs),
23408(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23409"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23410tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23411let Inst{31-21} = 0b00110111011;
23412let isPredicated = 1;
23413let isPredicatedFalse = 1;
23414let addrMode = BaseRegOffset;
23415let accessSize = HalfWordAccess;
23416let isPredicatedNew = 1;
23417let mayStore = 1;
23418let BaseOpcode = "S4_storerf_rr";
23419let CextOpcode = "S2_storerf";
23420let InputType = "reg";
23421}
23422def S4_pstorerffnew_zomap : HInst<
23423(outs),
23424(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23425"if (!$Pv4.new) memh($Rs32) = $Rt32.h",
23426tc_a2b365d2, TypeMAPPING> {
23427let isPseudo = 1;
23428let isCodeGenOnly = 1;
23429}
23430def S4_pstorerft_abs : HInst<
23431(outs),
23432(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23433"if ($Pv4) memh(#$Ii) = $Rt32.h",
23434tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23435let Inst{2-2} = 0b0;
23436let Inst{7-7} = 0b1;
23437let Inst{13-13} = 0b0;
23438let Inst{31-18} = 0b10101111011000;
23439let isPredicated = 1;
23440let addrMode = Absolute;
23441let accessSize = HalfWordAccess;
23442let isExtended = 1;
23443let mayStore = 1;
23444let BaseOpcode = "S2_storerfabs";
23445let CextOpcode = "S2_storerf";
23446let DecoderNamespace = "MustExtend";
23447let isExtendable = 1;
23448let opExtendable = 1;
23449let isExtentSigned = 0;
23450let opExtentBits = 6;
23451let opExtentAlign = 0;
23452}
23453def S4_pstorerft_rr : HInst<
23454(outs),
23455(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23456"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23457tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23458let Inst{31-21} = 0b00110100011;
23459let isPredicated = 1;
23460let addrMode = BaseRegOffset;
23461let accessSize = HalfWordAccess;
23462let mayStore = 1;
23463let BaseOpcode = "S4_storerf_rr";
23464let CextOpcode = "S2_storerf";
23465let InputType = "reg";
23466}
23467def S4_pstorerftnew_abs : HInst<
23468(outs),
23469(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23470"if ($Pv4.new) memh(#$Ii) = $Rt32.h",
23471tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23472let Inst{2-2} = 0b0;
23473let Inst{7-7} = 0b1;
23474let Inst{13-13} = 0b1;
23475let Inst{31-18} = 0b10101111011000;
23476let isPredicated = 1;
23477let addrMode = Absolute;
23478let accessSize = HalfWordAccess;
23479let isPredicatedNew = 1;
23480let isExtended = 1;
23481let mayStore = 1;
23482let BaseOpcode = "S2_storerfabs";
23483let CextOpcode = "S2_storerf";
23484let DecoderNamespace = "MustExtend";
23485let isExtendable = 1;
23486let opExtendable = 1;
23487let isExtentSigned = 0;
23488let opExtentBits = 6;
23489let opExtentAlign = 0;
23490}
23491def S4_pstorerftnew_io : HInst<
23492(outs),
23493(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23494"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23495tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23496let Inst{2-2} = 0b0;
23497let Inst{31-21} = 0b01000010011;
23498let isPredicated = 1;
23499let addrMode = BaseImmOffset;
23500let accessSize = HalfWordAccess;
23501let isPredicatedNew = 1;
23502let mayStore = 1;
23503let BaseOpcode = "S2_storerf_io";
23504let CextOpcode = "S2_storerf";
23505let InputType = "imm";
23506let isExtendable = 1;
23507let opExtendable = 2;
23508let isExtentSigned = 0;
23509let opExtentBits = 7;
23510let opExtentAlign = 1;
23511}
23512def S4_pstorerftnew_rr : HInst<
23513(outs),
23514(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23515"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23516tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23517let Inst{31-21} = 0b00110110011;
23518let isPredicated = 1;
23519let addrMode = BaseRegOffset;
23520let accessSize = HalfWordAccess;
23521let isPredicatedNew = 1;
23522let mayStore = 1;
23523let BaseOpcode = "S4_storerf_rr";
23524let CextOpcode = "S2_storerf";
23525let InputType = "reg";
23526}
23527def S4_pstorerftnew_zomap : HInst<
23528(outs),
23529(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23530"if ($Pv4.new) memh($Rs32) = $Rt32.h",
23531tc_a2b365d2, TypeMAPPING> {
23532let isPseudo = 1;
23533let isCodeGenOnly = 1;
23534}
23535def S4_pstorerhf_abs : HInst<
23536(outs),
23537(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23538"if (!$Pv4) memh(#$Ii) = $Rt32",
23539tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23540let Inst{2-2} = 0b1;
23541let Inst{7-7} = 0b1;
23542let Inst{13-13} = 0b0;
23543let Inst{31-18} = 0b10101111010000;
23544let isPredicated = 1;
23545let isPredicatedFalse = 1;
23546let addrMode = Absolute;
23547let accessSize = HalfWordAccess;
23548let isExtended = 1;
23549let mayStore = 1;
23550let BaseOpcode = "S2_storerhabs";
23551let CextOpcode = "S2_storerh";
23552let isNVStorable = 1;
23553let DecoderNamespace = "MustExtend";
23554let isExtendable = 1;
23555let opExtendable = 1;
23556let isExtentSigned = 0;
23557let opExtentBits = 6;
23558let opExtentAlign = 0;
23559}
23560def S4_pstorerhf_rr : HInst<
23561(outs),
23562(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23563"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23564tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23565let Inst{31-21} = 0b00110101010;
23566let isPredicated = 1;
23567let isPredicatedFalse = 1;
23568let addrMode = BaseRegOffset;
23569let accessSize = HalfWordAccess;
23570let mayStore = 1;
23571let BaseOpcode = "S2_storerh_rr";
23572let CextOpcode = "S2_storerh";
23573let InputType = "reg";
23574let isNVStorable = 1;
23575}
23576def S4_pstorerhfnew_abs : HInst<
23577(outs),
23578(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23579"if (!$Pv4.new) memh(#$Ii) = $Rt32",
23580tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23581let Inst{2-2} = 0b1;
23582let Inst{7-7} = 0b1;
23583let Inst{13-13} = 0b1;
23584let Inst{31-18} = 0b10101111010000;
23585let isPredicated = 1;
23586let isPredicatedFalse = 1;
23587let addrMode = Absolute;
23588let accessSize = HalfWordAccess;
23589let isPredicatedNew = 1;
23590let isExtended = 1;
23591let mayStore = 1;
23592let BaseOpcode = "S2_storerhabs";
23593let CextOpcode = "S2_storerh";
23594let isNVStorable = 1;
23595let DecoderNamespace = "MustExtend";
23596let isExtendable = 1;
23597let opExtendable = 1;
23598let isExtentSigned = 0;
23599let opExtentBits = 6;
23600let opExtentAlign = 0;
23601}
23602def S4_pstorerhfnew_io : HInst<
23603(outs),
23604(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23605"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23606tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23607let Inst{2-2} = 0b0;
23608let Inst{31-21} = 0b01000110010;
23609let isPredicated = 1;
23610let isPredicatedFalse = 1;
23611let addrMode = BaseImmOffset;
23612let accessSize = HalfWordAccess;
23613let isPredicatedNew = 1;
23614let mayStore = 1;
23615let BaseOpcode = "S2_storerh_io";
23616let CextOpcode = "S2_storerh";
23617let InputType = "imm";
23618let isNVStorable = 1;
23619let isExtendable = 1;
23620let opExtendable = 2;
23621let isExtentSigned = 0;
23622let opExtentBits = 7;
23623let opExtentAlign = 1;
23624}
23625def S4_pstorerhfnew_rr : HInst<
23626(outs),
23627(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23628"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23629tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23630let Inst{31-21} = 0b00110111010;
23631let isPredicated = 1;
23632let isPredicatedFalse = 1;
23633let addrMode = BaseRegOffset;
23634let accessSize = HalfWordAccess;
23635let isPredicatedNew = 1;
23636let mayStore = 1;
23637let BaseOpcode = "S2_storerh_rr";
23638let CextOpcode = "S2_storerh";
23639let InputType = "reg";
23640let isNVStorable = 1;
23641}
23642def S4_pstorerhfnew_zomap : HInst<
23643(outs),
23644(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23645"if (!$Pv4.new) memh($Rs32) = $Rt32",
23646tc_a2b365d2, TypeMAPPING> {
23647let isPseudo = 1;
23648let isCodeGenOnly = 1;
23649}
23650def S4_pstorerhnewf_abs : HInst<
23651(outs),
23652(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23653"if (!$Pv4) memh(#$Ii) = $Nt8.new",
23654tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23655let Inst{2-2} = 0b1;
23656let Inst{7-7} = 0b1;
23657let Inst{13-11} = 0b001;
23658let Inst{31-18} = 0b10101111101000;
23659let isPredicated = 1;
23660let isPredicatedFalse = 1;
23661let addrMode = Absolute;
23662let accessSize = HalfWordAccess;
23663let isNVStore = 1;
23664let isNewValue = 1;
23665let isExtended = 1;
23666let isRestrictNoSlot1Store = 1;
23667let mayStore = 1;
23668let BaseOpcode = "S2_storerhabs";
23669let CextOpcode = "S2_storerh";
23670let DecoderNamespace = "MustExtend";
23671let isExtendable = 1;
23672let opExtendable = 1;
23673let isExtentSigned = 0;
23674let opExtentBits = 6;
23675let opExtentAlign = 0;
23676let opNewValue = 2;
23677}
23678def S4_pstorerhnewf_rr : HInst<
23679(outs),
23680(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23681"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23682tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23683let Inst{4-3} = 0b01;
23684let Inst{31-21} = 0b00110101101;
23685let isPredicated = 1;
23686let isPredicatedFalse = 1;
23687let addrMode = BaseRegOffset;
23688let accessSize = HalfWordAccess;
23689let isNVStore = 1;
23690let isNewValue = 1;
23691let isRestrictNoSlot1Store = 1;
23692let mayStore = 1;
23693let BaseOpcode = "S2_storerh_rr";
23694let CextOpcode = "S2_storerh";
23695let InputType = "reg";
23696let opNewValue = 4;
23697}
23698def S4_pstorerhnewfnew_abs : HInst<
23699(outs),
23700(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23701"if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
23702tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23703let Inst{2-2} = 0b1;
23704let Inst{7-7} = 0b1;
23705let Inst{13-11} = 0b101;
23706let Inst{31-18} = 0b10101111101000;
23707let isPredicated = 1;
23708let isPredicatedFalse = 1;
23709let addrMode = Absolute;
23710let accessSize = HalfWordAccess;
23711let isNVStore = 1;
23712let isPredicatedNew = 1;
23713let isNewValue = 1;
23714let isExtended = 1;
23715let isRestrictNoSlot1Store = 1;
23716let mayStore = 1;
23717let BaseOpcode = "S2_storerhabs";
23718let CextOpcode = "S2_storerh";
23719let DecoderNamespace = "MustExtend";
23720let isExtendable = 1;
23721let opExtendable = 1;
23722let isExtentSigned = 0;
23723let opExtentBits = 6;
23724let opExtentAlign = 0;
23725let opNewValue = 2;
23726}
23727def S4_pstorerhnewfnew_io : HInst<
23728(outs),
23729(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23730"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23731tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23732let Inst{2-2} = 0b0;
23733let Inst{12-11} = 0b01;
23734let Inst{31-21} = 0b01000110101;
23735let isPredicated = 1;
23736let isPredicatedFalse = 1;
23737let addrMode = BaseImmOffset;
23738let accessSize = HalfWordAccess;
23739let isNVStore = 1;
23740let isPredicatedNew = 1;
23741let isNewValue = 1;
23742let isRestrictNoSlot1Store = 1;
23743let mayStore = 1;
23744let BaseOpcode = "S2_storerh_io";
23745let CextOpcode = "S2_storerh";
23746let InputType = "imm";
23747let isExtendable = 1;
23748let opExtendable = 2;
23749let isExtentSigned = 0;
23750let opExtentBits = 7;
23751let opExtentAlign = 1;
23752let opNewValue = 3;
23753}
23754def S4_pstorerhnewfnew_rr : HInst<
23755(outs),
23756(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23757"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23758tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23759let Inst{4-3} = 0b01;
23760let Inst{31-21} = 0b00110111101;
23761let isPredicated = 1;
23762let isPredicatedFalse = 1;
23763let addrMode = BaseRegOffset;
23764let accessSize = HalfWordAccess;
23765let isNVStore = 1;
23766let isPredicatedNew = 1;
23767let isNewValue = 1;
23768let isRestrictNoSlot1Store = 1;
23769let mayStore = 1;
23770let BaseOpcode = "S2_storerh_rr";
23771let CextOpcode = "S2_storerh";
23772let InputType = "reg";
23773let opNewValue = 4;
23774}
23775def S4_pstorerhnewfnew_zomap : HInst<
23776(outs),
23777(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23778"if (!$Pv4.new) memh($Rs32) = $Nt8.new",
23779tc_92240447, TypeMAPPING> {
23780let isPseudo = 1;
23781let isCodeGenOnly = 1;
23782let opNewValue = 2;
23783}
23784def S4_pstorerhnewt_abs : HInst<
23785(outs),
23786(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23787"if ($Pv4) memh(#$Ii) = $Nt8.new",
23788tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23789let Inst{2-2} = 0b0;
23790let Inst{7-7} = 0b1;
23791let Inst{13-11} = 0b001;
23792let Inst{31-18} = 0b10101111101000;
23793let isPredicated = 1;
23794let addrMode = Absolute;
23795let accessSize = HalfWordAccess;
23796let isNVStore = 1;
23797let isNewValue = 1;
23798let isExtended = 1;
23799let isRestrictNoSlot1Store = 1;
23800let mayStore = 1;
23801let BaseOpcode = "S2_storerhabs";
23802let CextOpcode = "S2_storerh";
23803let DecoderNamespace = "MustExtend";
23804let isExtendable = 1;
23805let opExtendable = 1;
23806let isExtentSigned = 0;
23807let opExtentBits = 6;
23808let opExtentAlign = 0;
23809let opNewValue = 2;
23810}
23811def S4_pstorerhnewt_rr : HInst<
23812(outs),
23813(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23814"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23815tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23816let Inst{4-3} = 0b01;
23817let Inst{31-21} = 0b00110100101;
23818let isPredicated = 1;
23819let addrMode = BaseRegOffset;
23820let accessSize = HalfWordAccess;
23821let isNVStore = 1;
23822let isNewValue = 1;
23823let isRestrictNoSlot1Store = 1;
23824let mayStore = 1;
23825let BaseOpcode = "S2_storerh_rr";
23826let CextOpcode = "S2_storerh";
23827let InputType = "reg";
23828let opNewValue = 4;
23829}
23830def S4_pstorerhnewtnew_abs : HInst<
23831(outs),
23832(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23833"if ($Pv4.new) memh(#$Ii) = $Nt8.new",
23834tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23835let Inst{2-2} = 0b0;
23836let Inst{7-7} = 0b1;
23837let Inst{13-11} = 0b101;
23838let Inst{31-18} = 0b10101111101000;
23839let isPredicated = 1;
23840let addrMode = Absolute;
23841let accessSize = HalfWordAccess;
23842let isNVStore = 1;
23843let isPredicatedNew = 1;
23844let isNewValue = 1;
23845let isExtended = 1;
23846let isRestrictNoSlot1Store = 1;
23847let mayStore = 1;
23848let BaseOpcode = "S2_storerhabs";
23849let CextOpcode = "S2_storerh";
23850let DecoderNamespace = "MustExtend";
23851let isExtendable = 1;
23852let opExtendable = 1;
23853let isExtentSigned = 0;
23854let opExtentBits = 6;
23855let opExtentAlign = 0;
23856let opNewValue = 2;
23857}
23858def S4_pstorerhnewtnew_io : HInst<
23859(outs),
23860(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23861"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23862tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23863let Inst{2-2} = 0b0;
23864let Inst{12-11} = 0b01;
23865let Inst{31-21} = 0b01000010101;
23866let isPredicated = 1;
23867let addrMode = BaseImmOffset;
23868let accessSize = HalfWordAccess;
23869let isNVStore = 1;
23870let isPredicatedNew = 1;
23871let isNewValue = 1;
23872let isRestrictNoSlot1Store = 1;
23873let mayStore = 1;
23874let BaseOpcode = "S2_storerh_io";
23875let CextOpcode = "S2_storerh";
23876let InputType = "imm";
23877let isExtendable = 1;
23878let opExtendable = 2;
23879let isExtentSigned = 0;
23880let opExtentBits = 7;
23881let opExtentAlign = 1;
23882let opNewValue = 3;
23883}
23884def S4_pstorerhnewtnew_rr : HInst<
23885(outs),
23886(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23887"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23888tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23889let Inst{4-3} = 0b01;
23890let Inst{31-21} = 0b00110110101;
23891let isPredicated = 1;
23892let addrMode = BaseRegOffset;
23893let accessSize = HalfWordAccess;
23894let isNVStore = 1;
23895let isPredicatedNew = 1;
23896let isNewValue = 1;
23897let isRestrictNoSlot1Store = 1;
23898let mayStore = 1;
23899let BaseOpcode = "S2_storerh_rr";
23900let CextOpcode = "S2_storerh";
23901let InputType = "reg";
23902let opNewValue = 4;
23903}
23904def S4_pstorerhnewtnew_zomap : HInst<
23905(outs),
23906(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23907"if ($Pv4.new) memh($Rs32) = $Nt8.new",
23908tc_92240447, TypeMAPPING> {
23909let isPseudo = 1;
23910let isCodeGenOnly = 1;
23911let opNewValue = 2;
23912}
23913def S4_pstorerht_abs : HInst<
23914(outs),
23915(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23916"if ($Pv4) memh(#$Ii) = $Rt32",
23917tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23918let Inst{2-2} = 0b0;
23919let Inst{7-7} = 0b1;
23920let Inst{13-13} = 0b0;
23921let Inst{31-18} = 0b10101111010000;
23922let isPredicated = 1;
23923let addrMode = Absolute;
23924let accessSize = HalfWordAccess;
23925let isExtended = 1;
23926let mayStore = 1;
23927let BaseOpcode = "S2_storerhabs";
23928let CextOpcode = "S2_storerh";
23929let isNVStorable = 1;
23930let DecoderNamespace = "MustExtend";
23931let isExtendable = 1;
23932let opExtendable = 1;
23933let isExtentSigned = 0;
23934let opExtentBits = 6;
23935let opExtentAlign = 0;
23936}
23937def S4_pstorerht_rr : HInst<
23938(outs),
23939(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23940"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23941tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23942let Inst{31-21} = 0b00110100010;
23943let isPredicated = 1;
23944let addrMode = BaseRegOffset;
23945let accessSize = HalfWordAccess;
23946let mayStore = 1;
23947let BaseOpcode = "S2_storerh_rr";
23948let CextOpcode = "S2_storerh";
23949let InputType = "reg";
23950let isNVStorable = 1;
23951}
23952def S4_pstorerhtnew_abs : HInst<
23953(outs),
23954(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23955"if ($Pv4.new) memh(#$Ii) = $Rt32",
23956tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23957let Inst{2-2} = 0b0;
23958let Inst{7-7} = 0b1;
23959let Inst{13-13} = 0b1;
23960let Inst{31-18} = 0b10101111010000;
23961let isPredicated = 1;
23962let addrMode = Absolute;
23963let accessSize = HalfWordAccess;
23964let isPredicatedNew = 1;
23965let isExtended = 1;
23966let mayStore = 1;
23967let BaseOpcode = "S2_storerhabs";
23968let CextOpcode = "S2_storerh";
23969let isNVStorable = 1;
23970let DecoderNamespace = "MustExtend";
23971let isExtendable = 1;
23972let opExtendable = 1;
23973let isExtentSigned = 0;
23974let opExtentBits = 6;
23975let opExtentAlign = 0;
23976}
23977def S4_pstorerhtnew_io : HInst<
23978(outs),
23979(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23980"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23981tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23982let Inst{2-2} = 0b0;
23983let Inst{31-21} = 0b01000010010;
23984let isPredicated = 1;
23985let addrMode = BaseImmOffset;
23986let accessSize = HalfWordAccess;
23987let isPredicatedNew = 1;
23988let mayStore = 1;
23989let BaseOpcode = "S2_storerh_io";
23990let CextOpcode = "S2_storerh";
23991let InputType = "imm";
23992let isNVStorable = 1;
23993let isExtendable = 1;
23994let opExtendable = 2;
23995let isExtentSigned = 0;
23996let opExtentBits = 7;
23997let opExtentAlign = 1;
23998}
23999def S4_pstorerhtnew_rr : HInst<
24000(outs),
24001(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24002"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24003tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24004let Inst{31-21} = 0b00110110010;
24005let isPredicated = 1;
24006let addrMode = BaseRegOffset;
24007let accessSize = HalfWordAccess;
24008let isPredicatedNew = 1;
24009let mayStore = 1;
24010let BaseOpcode = "S2_storerh_rr";
24011let CextOpcode = "S2_storerh";
24012let InputType = "reg";
24013let isNVStorable = 1;
24014}
24015def S4_pstorerhtnew_zomap : HInst<
24016(outs),
24017(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24018"if ($Pv4.new) memh($Rs32) = $Rt32",
24019tc_a2b365d2, TypeMAPPING> {
24020let isPseudo = 1;
24021let isCodeGenOnly = 1;
24022}
24023def S4_pstorerif_abs : HInst<
24024(outs),
24025(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24026"if (!$Pv4) memw(#$Ii) = $Rt32",
24027tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24028let Inst{2-2} = 0b1;
24029let Inst{7-7} = 0b1;
24030let Inst{13-13} = 0b0;
24031let Inst{31-18} = 0b10101111100000;
24032let isPredicated = 1;
24033let isPredicatedFalse = 1;
24034let addrMode = Absolute;
24035let accessSize = WordAccess;
24036let isExtended = 1;
24037let mayStore = 1;
24038let BaseOpcode = "S2_storeriabs";
24039let CextOpcode = "S2_storeri";
24040let isNVStorable = 1;
24041let DecoderNamespace = "MustExtend";
24042let isExtendable = 1;
24043let opExtendable = 1;
24044let isExtentSigned = 0;
24045let opExtentBits = 6;
24046let opExtentAlign = 0;
24047}
24048def S4_pstorerif_rr : HInst<
24049(outs),
24050(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24051"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24052tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24053let Inst{31-21} = 0b00110101100;
24054let isPredicated = 1;
24055let isPredicatedFalse = 1;
24056let addrMode = BaseRegOffset;
24057let accessSize = WordAccess;
24058let mayStore = 1;
24059let BaseOpcode = "S2_storeri_rr";
24060let CextOpcode = "S2_storeri";
24061let InputType = "reg";
24062let isNVStorable = 1;
24063}
24064def S4_pstorerifnew_abs : HInst<
24065(outs),
24066(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24067"if (!$Pv4.new) memw(#$Ii) = $Rt32",
24068tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24069let Inst{2-2} = 0b1;
24070let Inst{7-7} = 0b1;
24071let Inst{13-13} = 0b1;
24072let Inst{31-18} = 0b10101111100000;
24073let isPredicated = 1;
24074let isPredicatedFalse = 1;
24075let addrMode = Absolute;
24076let accessSize = WordAccess;
24077let isPredicatedNew = 1;
24078let isExtended = 1;
24079let mayStore = 1;
24080let BaseOpcode = "S2_storeriabs";
24081let CextOpcode = "S2_storeri";
24082let isNVStorable = 1;
24083let DecoderNamespace = "MustExtend";
24084let isExtendable = 1;
24085let opExtendable = 1;
24086let isExtentSigned = 0;
24087let opExtentBits = 6;
24088let opExtentAlign = 0;
24089}
24090def S4_pstorerifnew_io : HInst<
24091(outs),
24092(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24093"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24094tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24095let Inst{2-2} = 0b0;
24096let Inst{31-21} = 0b01000110100;
24097let isPredicated = 1;
24098let isPredicatedFalse = 1;
24099let addrMode = BaseImmOffset;
24100let accessSize = WordAccess;
24101let isPredicatedNew = 1;
24102let mayStore = 1;
24103let BaseOpcode = "S2_storeri_io";
24104let CextOpcode = "S2_storeri";
24105let InputType = "imm";
24106let isNVStorable = 1;
24107let isExtendable = 1;
24108let opExtendable = 2;
24109let isExtentSigned = 0;
24110let opExtentBits = 8;
24111let opExtentAlign = 2;
24112}
24113def S4_pstorerifnew_rr : HInst<
24114(outs),
24115(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24116"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24117tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24118let Inst{31-21} = 0b00110111100;
24119let isPredicated = 1;
24120let isPredicatedFalse = 1;
24121let addrMode = BaseRegOffset;
24122let accessSize = WordAccess;
24123let isPredicatedNew = 1;
24124let mayStore = 1;
24125let BaseOpcode = "S2_storeri_rr";
24126let CextOpcode = "S2_storeri";
24127let InputType = "reg";
24128let isNVStorable = 1;
24129}
24130def S4_pstorerifnew_zomap : HInst<
24131(outs),
24132(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24133"if (!$Pv4.new) memw($Rs32) = $Rt32",
24134tc_a2b365d2, TypeMAPPING> {
24135let isPseudo = 1;
24136let isCodeGenOnly = 1;
24137}
24138def S4_pstorerinewf_abs : HInst<
24139(outs),
24140(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24141"if (!$Pv4) memw(#$Ii) = $Nt8.new",
24142tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24143let Inst{2-2} = 0b1;
24144let Inst{7-7} = 0b1;
24145let Inst{13-11} = 0b010;
24146let Inst{31-18} = 0b10101111101000;
24147let isPredicated = 1;
24148let isPredicatedFalse = 1;
24149let addrMode = Absolute;
24150let accessSize = WordAccess;
24151let isNVStore = 1;
24152let isNewValue = 1;
24153let isExtended = 1;
24154let isRestrictNoSlot1Store = 1;
24155let mayStore = 1;
24156let BaseOpcode = "S2_storeriabs";
24157let CextOpcode = "S2_storeri";
24158let DecoderNamespace = "MustExtend";
24159let isExtendable = 1;
24160let opExtendable = 1;
24161let isExtentSigned = 0;
24162let opExtentBits = 6;
24163let opExtentAlign = 0;
24164let opNewValue = 2;
24165}
24166def S4_pstorerinewf_rr : HInst<
24167(outs),
24168(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24169"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24170tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24171let Inst{4-3} = 0b10;
24172let Inst{31-21} = 0b00110101101;
24173let isPredicated = 1;
24174let isPredicatedFalse = 1;
24175let addrMode = BaseRegOffset;
24176let accessSize = WordAccess;
24177let isNVStore = 1;
24178let isNewValue = 1;
24179let isRestrictNoSlot1Store = 1;
24180let mayStore = 1;
24181let BaseOpcode = "S2_storeri_rr";
24182let CextOpcode = "S2_storeri";
24183let InputType = "reg";
24184let opNewValue = 4;
24185}
24186def S4_pstorerinewfnew_abs : HInst<
24187(outs),
24188(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24189"if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
24190tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24191let Inst{2-2} = 0b1;
24192let Inst{7-7} = 0b1;
24193let Inst{13-11} = 0b110;
24194let Inst{31-18} = 0b10101111101000;
24195let isPredicated = 1;
24196let isPredicatedFalse = 1;
24197let addrMode = Absolute;
24198let accessSize = WordAccess;
24199let isNVStore = 1;
24200let isPredicatedNew = 1;
24201let isNewValue = 1;
24202let isExtended = 1;
24203let isRestrictNoSlot1Store = 1;
24204let mayStore = 1;
24205let BaseOpcode = "S2_storeriabs";
24206let CextOpcode = "S2_storeri";
24207let DecoderNamespace = "MustExtend";
24208let isExtendable = 1;
24209let opExtendable = 1;
24210let isExtentSigned = 0;
24211let opExtentBits = 6;
24212let opExtentAlign = 0;
24213let opNewValue = 2;
24214}
24215def S4_pstorerinewfnew_io : HInst<
24216(outs),
24217(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24218"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24219tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24220let Inst{2-2} = 0b0;
24221let Inst{12-11} = 0b10;
24222let Inst{31-21} = 0b01000110101;
24223let isPredicated = 1;
24224let isPredicatedFalse = 1;
24225let addrMode = BaseImmOffset;
24226let accessSize = WordAccess;
24227let isNVStore = 1;
24228let isPredicatedNew = 1;
24229let isNewValue = 1;
24230let isRestrictNoSlot1Store = 1;
24231let mayStore = 1;
24232let BaseOpcode = "S2_storeri_io";
24233let CextOpcode = "S2_storeri";
24234let InputType = "imm";
24235let isExtendable = 1;
24236let opExtendable = 2;
24237let isExtentSigned = 0;
24238let opExtentBits = 8;
24239let opExtentAlign = 2;
24240let opNewValue = 3;
24241}
24242def S4_pstorerinewfnew_rr : HInst<
24243(outs),
24244(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24245"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24246tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24247let Inst{4-3} = 0b10;
24248let Inst{31-21} = 0b00110111101;
24249let isPredicated = 1;
24250let isPredicatedFalse = 1;
24251let addrMode = BaseRegOffset;
24252let accessSize = WordAccess;
24253let isNVStore = 1;
24254let isPredicatedNew = 1;
24255let isNewValue = 1;
24256let isRestrictNoSlot1Store = 1;
24257let mayStore = 1;
24258let BaseOpcode = "S2_storeri_rr";
24259let CextOpcode = "S2_storeri";
24260let InputType = "reg";
24261let opNewValue = 4;
24262}
24263def S4_pstorerinewfnew_zomap : HInst<
24264(outs),
24265(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24266"if (!$Pv4.new) memw($Rs32) = $Nt8.new",
24267tc_92240447, TypeMAPPING> {
24268let isPseudo = 1;
24269let isCodeGenOnly = 1;
24270let opNewValue = 2;
24271}
24272def S4_pstorerinewt_abs : HInst<
24273(outs),
24274(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24275"if ($Pv4) memw(#$Ii) = $Nt8.new",
24276tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24277let Inst{2-2} = 0b0;
24278let Inst{7-7} = 0b1;
24279let Inst{13-11} = 0b010;
24280let Inst{31-18} = 0b10101111101000;
24281let isPredicated = 1;
24282let addrMode = Absolute;
24283let accessSize = WordAccess;
24284let isNVStore = 1;
24285let isNewValue = 1;
24286let isExtended = 1;
24287let isRestrictNoSlot1Store = 1;
24288let mayStore = 1;
24289let BaseOpcode = "S2_storeriabs";
24290let CextOpcode = "S2_storeri";
24291let DecoderNamespace = "MustExtend";
24292let isExtendable = 1;
24293let opExtendable = 1;
24294let isExtentSigned = 0;
24295let opExtentBits = 6;
24296let opExtentAlign = 0;
24297let opNewValue = 2;
24298}
24299def S4_pstorerinewt_rr : HInst<
24300(outs),
24301(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24302"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24303tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24304let Inst{4-3} = 0b10;
24305let Inst{31-21} = 0b00110100101;
24306let isPredicated = 1;
24307let addrMode = BaseRegOffset;
24308let accessSize = WordAccess;
24309let isNVStore = 1;
24310let isNewValue = 1;
24311let isRestrictNoSlot1Store = 1;
24312let mayStore = 1;
24313let BaseOpcode = "S2_storeri_rr";
24314let CextOpcode = "S2_storeri";
24315let InputType = "reg";
24316let opNewValue = 4;
24317}
24318def S4_pstorerinewtnew_abs : HInst<
24319(outs),
24320(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24321"if ($Pv4.new) memw(#$Ii) = $Nt8.new",
24322tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24323let Inst{2-2} = 0b0;
24324let Inst{7-7} = 0b1;
24325let Inst{13-11} = 0b110;
24326let Inst{31-18} = 0b10101111101000;
24327let isPredicated = 1;
24328let addrMode = Absolute;
24329let accessSize = WordAccess;
24330let isNVStore = 1;
24331let isPredicatedNew = 1;
24332let isNewValue = 1;
24333let isExtended = 1;
24334let isRestrictNoSlot1Store = 1;
24335let mayStore = 1;
24336let BaseOpcode = "S2_storeriabs";
24337let CextOpcode = "S2_storeri";
24338let DecoderNamespace = "MustExtend";
24339let isExtendable = 1;
24340let opExtendable = 1;
24341let isExtentSigned = 0;
24342let opExtentBits = 6;
24343let opExtentAlign = 0;
24344let opNewValue = 2;
24345}
24346def S4_pstorerinewtnew_io : HInst<
24347(outs),
24348(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24349"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24350tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24351let Inst{2-2} = 0b0;
24352let Inst{12-11} = 0b10;
24353let Inst{31-21} = 0b01000010101;
24354let isPredicated = 1;
24355let addrMode = BaseImmOffset;
24356let accessSize = WordAccess;
24357let isNVStore = 1;
24358let isPredicatedNew = 1;
24359let isNewValue = 1;
24360let isRestrictNoSlot1Store = 1;
24361let mayStore = 1;
24362let BaseOpcode = "S2_storeri_io";
24363let CextOpcode = "S2_storeri";
24364let InputType = "imm";
24365let isExtendable = 1;
24366let opExtendable = 2;
24367let isExtentSigned = 0;
24368let opExtentBits = 8;
24369let opExtentAlign = 2;
24370let opNewValue = 3;
24371}
24372def S4_pstorerinewtnew_rr : HInst<
24373(outs),
24374(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24375"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24376tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24377let Inst{4-3} = 0b10;
24378let Inst{31-21} = 0b00110110101;
24379let isPredicated = 1;
24380let addrMode = BaseRegOffset;
24381let accessSize = WordAccess;
24382let isNVStore = 1;
24383let isPredicatedNew = 1;
24384let isNewValue = 1;
24385let isRestrictNoSlot1Store = 1;
24386let mayStore = 1;
24387let BaseOpcode = "S2_storeri_rr";
24388let CextOpcode = "S2_storeri";
24389let InputType = "reg";
24390let opNewValue = 4;
24391}
24392def S4_pstorerinewtnew_zomap : HInst<
24393(outs),
24394(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24395"if ($Pv4.new) memw($Rs32) = $Nt8.new",
24396tc_92240447, TypeMAPPING> {
24397let isPseudo = 1;
24398let isCodeGenOnly = 1;
24399let opNewValue = 2;
24400}
24401def S4_pstorerit_abs : HInst<
24402(outs),
24403(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24404"if ($Pv4) memw(#$Ii) = $Rt32",
24405tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24406let Inst{2-2} = 0b0;
24407let Inst{7-7} = 0b1;
24408let Inst{13-13} = 0b0;
24409let Inst{31-18} = 0b10101111100000;
24410let isPredicated = 1;
24411let addrMode = Absolute;
24412let accessSize = WordAccess;
24413let isExtended = 1;
24414let mayStore = 1;
24415let BaseOpcode = "S2_storeriabs";
24416let CextOpcode = "S2_storeri";
24417let isNVStorable = 1;
24418let DecoderNamespace = "MustExtend";
24419let isExtendable = 1;
24420let opExtendable = 1;
24421let isExtentSigned = 0;
24422let opExtentBits = 6;
24423let opExtentAlign = 0;
24424}
24425def S4_pstorerit_rr : HInst<
24426(outs),
24427(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24428"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24429tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24430let Inst{31-21} = 0b00110100100;
24431let isPredicated = 1;
24432let addrMode = BaseRegOffset;
24433let accessSize = WordAccess;
24434let mayStore = 1;
24435let BaseOpcode = "S2_storeri_rr";
24436let CextOpcode = "S2_storeri";
24437let InputType = "reg";
24438let isNVStorable = 1;
24439}
24440def S4_pstoreritnew_abs : HInst<
24441(outs),
24442(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24443"if ($Pv4.new) memw(#$Ii) = $Rt32",
24444tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24445let Inst{2-2} = 0b0;
24446let Inst{7-7} = 0b1;
24447let Inst{13-13} = 0b1;
24448let Inst{31-18} = 0b10101111100000;
24449let isPredicated = 1;
24450let addrMode = Absolute;
24451let accessSize = WordAccess;
24452let isPredicatedNew = 1;
24453let isExtended = 1;
24454let mayStore = 1;
24455let BaseOpcode = "S2_storeriabs";
24456let CextOpcode = "S2_storeri";
24457let isNVStorable = 1;
24458let DecoderNamespace = "MustExtend";
24459let isExtendable = 1;
24460let opExtendable = 1;
24461let isExtentSigned = 0;
24462let opExtentBits = 6;
24463let opExtentAlign = 0;
24464}
24465def S4_pstoreritnew_io : HInst<
24466(outs),
24467(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24468"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24469tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24470let Inst{2-2} = 0b0;
24471let Inst{31-21} = 0b01000010100;
24472let isPredicated = 1;
24473let addrMode = BaseImmOffset;
24474let accessSize = WordAccess;
24475let isPredicatedNew = 1;
24476let mayStore = 1;
24477let BaseOpcode = "S2_storeri_io";
24478let CextOpcode = "S2_storeri";
24479let InputType = "imm";
24480let isNVStorable = 1;
24481let isExtendable = 1;
24482let opExtendable = 2;
24483let isExtentSigned = 0;
24484let opExtentBits = 8;
24485let opExtentAlign = 2;
24486}
24487def S4_pstoreritnew_rr : HInst<
24488(outs),
24489(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24490"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24491tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24492let Inst{31-21} = 0b00110110100;
24493let isPredicated = 1;
24494let addrMode = BaseRegOffset;
24495let accessSize = WordAccess;
24496let isPredicatedNew = 1;
24497let mayStore = 1;
24498let BaseOpcode = "S2_storeri_rr";
24499let CextOpcode = "S2_storeri";
24500let InputType = "reg";
24501let isNVStorable = 1;
24502}
24503def S4_pstoreritnew_zomap : HInst<
24504(outs),
24505(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24506"if ($Pv4.new) memw($Rs32) = $Rt32",
24507tc_a2b365d2, TypeMAPPING> {
24508let isPseudo = 1;
24509let isCodeGenOnly = 1;
24510}
24511def S4_stored_locked : HInst<
24512(outs PredRegs:$Pd4),
24513(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24514"memd_locked($Rs32,$Pd4) = $Rtt32",
24515tc_6f42bc60, TypeST>, Enc_d7dc10 {
24516let Inst{7-2} = 0b000000;
24517let Inst{13-13} = 0b0;
24518let Inst{31-21} = 0b10100000111;
24519let accessSize = DoubleWordAccess;
24520let isPredicateLate = 1;
24521let isSoloAX = 1;
24522let mayStore = 1;
24523}
24524def S4_storeirb_io : HInst<
24525(outs),
24526(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24527"memb($Rs32+#$Ii) = #$II",
24528tc_7c31e19a, TypeST>, Enc_8203bb, PredNewRel {
24529let Inst{31-21} = 0b00111100000;
24530let addrMode = BaseImmOffset;
24531let accessSize = ByteAccess;
24532let mayStore = 1;
24533let BaseOpcode = "S4_storeirb_io";
24534let CextOpcode = "S2_storerb";
24535let InputType = "imm";
24536let isPredicable = 1;
24537let isExtendable = 1;
24538let opExtendable = 2;
24539let isExtentSigned = 1;
24540let opExtentBits = 8;
24541let opExtentAlign = 0;
24542}
24543def S4_storeirb_zomap : HInst<
24544(outs),
24545(ins IntRegs:$Rs32, s8_0Imm:$II),
24546"memb($Rs32) = #$II",
24547tc_7c31e19a, TypeMAPPING> {
24548let isPseudo = 1;
24549let isCodeGenOnly = 1;
24550}
24551def S4_storeirbf_io : HInst<
24552(outs),
24553(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24554"if (!$Pv4) memb($Rs32+#$Ii) = #$II",
24555tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24556let Inst{31-21} = 0b00111000100;
24557let isPredicated = 1;
24558let isPredicatedFalse = 1;
24559let addrMode = BaseImmOffset;
24560let accessSize = ByteAccess;
24561let mayStore = 1;
24562let BaseOpcode = "S4_storeirb_io";
24563let CextOpcode = "S2_storerb";
24564let InputType = "imm";
24565let isExtendable = 1;
24566let opExtendable = 3;
24567let isExtentSigned = 1;
24568let opExtentBits = 6;
24569let opExtentAlign = 0;
24570}
24571def S4_storeirbf_zomap : HInst<
24572(outs),
24573(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24574"if (!$Pv4) memb($Rs32) = #$II",
24575tc_d03278fd, TypeMAPPING> {
24576let isPseudo = 1;
24577let isCodeGenOnly = 1;
24578}
24579def S4_storeirbfnew_io : HInst<
24580(outs),
24581(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24582"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
24583tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24584let Inst{31-21} = 0b00111001100;
24585let isPredicated = 1;
24586let isPredicatedFalse = 1;
24587let addrMode = BaseImmOffset;
24588let accessSize = ByteAccess;
24589let isPredicatedNew = 1;
24590let mayStore = 1;
24591let BaseOpcode = "S4_storeirb_io";
24592let CextOpcode = "S2_storerb";
24593let InputType = "imm";
24594let isExtendable = 1;
24595let opExtendable = 3;
24596let isExtentSigned = 1;
24597let opExtentBits = 6;
24598let opExtentAlign = 0;
24599}
24600def S4_storeirbfnew_zomap : HInst<
24601(outs),
24602(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24603"if (!$Pv4.new) memb($Rs32) = #$II",
24604tc_65cbd974, TypeMAPPING> {
24605let isPseudo = 1;
24606let isCodeGenOnly = 1;
24607}
24608def S4_storeirbt_io : HInst<
24609(outs),
24610(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24611"if ($Pv4) memb($Rs32+#$Ii) = #$II",
24612tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24613let Inst{31-21} = 0b00111000000;
24614let isPredicated = 1;
24615let addrMode = BaseImmOffset;
24616let accessSize = ByteAccess;
24617let mayStore = 1;
24618let BaseOpcode = "S4_storeirb_io";
24619let CextOpcode = "S2_storerb";
24620let InputType = "imm";
24621let isExtendable = 1;
24622let opExtendable = 3;
24623let isExtentSigned = 1;
24624let opExtentBits = 6;
24625let opExtentAlign = 0;
24626}
24627def S4_storeirbt_zomap : HInst<
24628(outs),
24629(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24630"if ($Pv4) memb($Rs32) = #$II",
24631tc_d03278fd, TypeMAPPING> {
24632let isPseudo = 1;
24633let isCodeGenOnly = 1;
24634}
24635def S4_storeirbtnew_io : HInst<
24636(outs),
24637(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24638"if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
24639tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24640let Inst{31-21} = 0b00111001000;
24641let isPredicated = 1;
24642let addrMode = BaseImmOffset;
24643let accessSize = ByteAccess;
24644let isPredicatedNew = 1;
24645let mayStore = 1;
24646let BaseOpcode = "S4_storeirb_io";
24647let CextOpcode = "S2_storerb";
24648let InputType = "imm";
24649let isExtendable = 1;
24650let opExtendable = 3;
24651let isExtentSigned = 1;
24652let opExtentBits = 6;
24653let opExtentAlign = 0;
24654}
24655def S4_storeirbtnew_zomap : HInst<
24656(outs),
24657(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24658"if ($Pv4.new) memb($Rs32) = #$II",
24659tc_65cbd974, TypeMAPPING> {
24660let isPseudo = 1;
24661let isCodeGenOnly = 1;
24662}
24663def S4_storeirh_io : HInst<
24664(outs),
24665(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24666"memh($Rs32+#$Ii) = #$II",
24667tc_7c31e19a, TypeST>, Enc_a803e0, PredNewRel {
24668let Inst{31-21} = 0b00111100001;
24669let addrMode = BaseImmOffset;
24670let accessSize = HalfWordAccess;
24671let mayStore = 1;
24672let BaseOpcode = "S4_storeirh_io";
24673let CextOpcode = "S2_storerh";
24674let InputType = "imm";
24675let isPredicable = 1;
24676let isExtendable = 1;
24677let opExtendable = 2;
24678let isExtentSigned = 1;
24679let opExtentBits = 8;
24680let opExtentAlign = 0;
24681}
24682def S4_storeirh_zomap : HInst<
24683(outs),
24684(ins IntRegs:$Rs32, s8_0Imm:$II),
24685"memh($Rs32) = #$II",
24686tc_7c31e19a, TypeMAPPING> {
24687let isPseudo = 1;
24688let isCodeGenOnly = 1;
24689}
24690def S4_storeirhf_io : HInst<
24691(outs),
24692(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24693"if (!$Pv4) memh($Rs32+#$Ii) = #$II",
24694tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24695let Inst{31-21} = 0b00111000101;
24696let isPredicated = 1;
24697let isPredicatedFalse = 1;
24698let addrMode = BaseImmOffset;
24699let accessSize = HalfWordAccess;
24700let mayStore = 1;
24701let BaseOpcode = "S4_storeirh_io";
24702let CextOpcode = "S2_storerh";
24703let InputType = "imm";
24704let isExtendable = 1;
24705let opExtendable = 3;
24706let isExtentSigned = 1;
24707let opExtentBits = 6;
24708let opExtentAlign = 0;
24709}
24710def S4_storeirhf_zomap : HInst<
24711(outs),
24712(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24713"if (!$Pv4) memh($Rs32) = #$II",
24714tc_d03278fd, TypeMAPPING> {
24715let isPseudo = 1;
24716let isCodeGenOnly = 1;
24717}
24718def S4_storeirhfnew_io : HInst<
24719(outs),
24720(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24721"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
24722tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24723let Inst{31-21} = 0b00111001101;
24724let isPredicated = 1;
24725let isPredicatedFalse = 1;
24726let addrMode = BaseImmOffset;
24727let accessSize = HalfWordAccess;
24728let isPredicatedNew = 1;
24729let mayStore = 1;
24730let BaseOpcode = "S4_storeirh_io";
24731let CextOpcode = "S2_storerh";
24732let InputType = "imm";
24733let isExtendable = 1;
24734let opExtendable = 3;
24735let isExtentSigned = 1;
24736let opExtentBits = 6;
24737let opExtentAlign = 0;
24738}
24739def S4_storeirhfnew_zomap : HInst<
24740(outs),
24741(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24742"if (!$Pv4.new) memh($Rs32) = #$II",
24743tc_65cbd974, TypeMAPPING> {
24744let isPseudo = 1;
24745let isCodeGenOnly = 1;
24746}
24747def S4_storeirht_io : HInst<
24748(outs),
24749(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24750"if ($Pv4) memh($Rs32+#$Ii) = #$II",
24751tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24752let Inst{31-21} = 0b00111000001;
24753let isPredicated = 1;
24754let addrMode = BaseImmOffset;
24755let accessSize = HalfWordAccess;
24756let mayStore = 1;
24757let BaseOpcode = "S4_storeirh_io";
24758let CextOpcode = "S2_storerh";
24759let InputType = "imm";
24760let isExtendable = 1;
24761let opExtendable = 3;
24762let isExtentSigned = 1;
24763let opExtentBits = 6;
24764let opExtentAlign = 0;
24765}
24766def S4_storeirht_zomap : HInst<
24767(outs),
24768(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24769"if ($Pv4) memh($Rs32) = #$II",
24770tc_d03278fd, TypeMAPPING> {
24771let isPseudo = 1;
24772let isCodeGenOnly = 1;
24773}
24774def S4_storeirhtnew_io : HInst<
24775(outs),
24776(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24777"if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
24778tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24779let Inst{31-21} = 0b00111001001;
24780let isPredicated = 1;
24781let addrMode = BaseImmOffset;
24782let accessSize = HalfWordAccess;
24783let isPredicatedNew = 1;
24784let mayStore = 1;
24785let BaseOpcode = "S4_storeirh_io";
24786let CextOpcode = "S2_storerh";
24787let InputType = "imm";
24788let isExtendable = 1;
24789let opExtendable = 3;
24790let isExtentSigned = 1;
24791let opExtentBits = 6;
24792let opExtentAlign = 0;
24793}
24794def S4_storeirhtnew_zomap : HInst<
24795(outs),
24796(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24797"if ($Pv4.new) memh($Rs32) = #$II",
24798tc_65cbd974, TypeMAPPING> {
24799let isPseudo = 1;
24800let isCodeGenOnly = 1;
24801}
24802def S4_storeiri_io : HInst<
24803(outs),
24804(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24805"memw($Rs32+#$Ii) = #$II",
24806tc_7c31e19a, TypeST>, Enc_f37377, PredNewRel {
24807let Inst{31-21} = 0b00111100010;
24808let addrMode = BaseImmOffset;
24809let accessSize = WordAccess;
24810let mayStore = 1;
24811let BaseOpcode = "S4_storeiri_io";
24812let CextOpcode = "S2_storeri";
24813let InputType = "imm";
24814let isPredicable = 1;
24815let isExtendable = 1;
24816let opExtendable = 2;
24817let isExtentSigned = 1;
24818let opExtentBits = 8;
24819let opExtentAlign = 0;
24820}
24821def S4_storeiri_zomap : HInst<
24822(outs),
24823(ins IntRegs:$Rs32, s8_0Imm:$II),
24824"memw($Rs32) = #$II",
24825tc_7c31e19a, TypeMAPPING> {
24826let isPseudo = 1;
24827let isCodeGenOnly = 1;
24828}
24829def S4_storeirif_io : HInst<
24830(outs),
24831(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24832"if (!$Pv4) memw($Rs32+#$Ii) = #$II",
24833tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24834let Inst{31-21} = 0b00111000110;
24835let isPredicated = 1;
24836let isPredicatedFalse = 1;
24837let addrMode = BaseImmOffset;
24838let accessSize = WordAccess;
24839let mayStore = 1;
24840let BaseOpcode = "S4_storeiri_io";
24841let CextOpcode = "S2_storeri";
24842let InputType = "imm";
24843let isExtendable = 1;
24844let opExtendable = 3;
24845let isExtentSigned = 1;
24846let opExtentBits = 6;
24847let opExtentAlign = 0;
24848}
24849def S4_storeirif_zomap : HInst<
24850(outs),
24851(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24852"if (!$Pv4) memw($Rs32) = #$II",
24853tc_d03278fd, TypeMAPPING> {
24854let isPseudo = 1;
24855let isCodeGenOnly = 1;
24856}
24857def S4_storeirifnew_io : HInst<
24858(outs),
24859(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24860"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
24861tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
24862let Inst{31-21} = 0b00111001110;
24863let isPredicated = 1;
24864let isPredicatedFalse = 1;
24865let addrMode = BaseImmOffset;
24866let accessSize = WordAccess;
24867let isPredicatedNew = 1;
24868let mayStore = 1;
24869let BaseOpcode = "S4_storeiri_io";
24870let CextOpcode = "S2_storeri";
24871let InputType = "imm";
24872let isExtendable = 1;
24873let opExtendable = 3;
24874let isExtentSigned = 1;
24875let opExtentBits = 6;
24876let opExtentAlign = 0;
24877}
24878def S4_storeirifnew_zomap : HInst<
24879(outs),
24880(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24881"if (!$Pv4.new) memw($Rs32) = #$II",
24882tc_65cbd974, TypeMAPPING> {
24883let isPseudo = 1;
24884let isCodeGenOnly = 1;
24885}
24886def S4_storeirit_io : HInst<
24887(outs),
24888(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24889"if ($Pv4) memw($Rs32+#$Ii) = #$II",
24890tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24891let Inst{31-21} = 0b00111000010;
24892let isPredicated = 1;
24893let addrMode = BaseImmOffset;
24894let accessSize = WordAccess;
24895let mayStore = 1;
24896let BaseOpcode = "S4_storeiri_io";
24897let CextOpcode = "S2_storeri";
24898let InputType = "imm";
24899let isExtendable = 1;
24900let opExtendable = 3;
24901let isExtentSigned = 1;
24902let opExtentBits = 6;
24903let opExtentAlign = 0;
24904}
24905def S4_storeirit_zomap : HInst<
24906(outs),
24907(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24908"if ($Pv4) memw($Rs32) = #$II",
24909tc_d03278fd, TypeMAPPING> {
24910let isPseudo = 1;
24911let isCodeGenOnly = 1;
24912}
24913def S4_storeiritnew_io : HInst<
24914(outs),
24915(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24916"if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
24917tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
24918let Inst{31-21} = 0b00111001010;
24919let isPredicated = 1;
24920let addrMode = BaseImmOffset;
24921let accessSize = WordAccess;
24922let isPredicatedNew = 1;
24923let mayStore = 1;
24924let BaseOpcode = "S4_storeiri_io";
24925let CextOpcode = "S2_storeri";
24926let InputType = "imm";
24927let isExtendable = 1;
24928let opExtendable = 3;
24929let isExtentSigned = 1;
24930let opExtentBits = 6;
24931let opExtentAlign = 0;
24932}
24933def S4_storeiritnew_zomap : HInst<
24934(outs),
24935(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24936"if ($Pv4.new) memw($Rs32) = #$II",
24937tc_65cbd974, TypeMAPPING> {
24938let isPseudo = 1;
24939let isCodeGenOnly = 1;
24940}
24941def S4_storerb_ap : HInst<
24942(outs IntRegs:$Re32),
24943(ins u32_0Imm:$II, IntRegs:$Rt32),
24944"memb($Re32=#$II) = $Rt32",
24945tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
24946let Inst{7-6} = 0b10;
24947let Inst{13-13} = 0b0;
24948let Inst{31-21} = 0b10101011000;
24949let addrMode = AbsoluteSet;
24950let accessSize = ByteAccess;
24951let isExtended = 1;
24952let mayStore = 1;
24953let BaseOpcode = "S2_storerb_ap";
24954let isNVStorable = 1;
24955let DecoderNamespace = "MustExtend";
24956let isExtendable = 1;
24957let opExtendable = 1;
24958let isExtentSigned = 0;
24959let opExtentBits = 6;
24960let opExtentAlign = 0;
24961}
24962def S4_storerb_rr : HInst<
24963(outs),
24964(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24965"memb($Rs32+$Ru32<<#$Ii) = $Rt32",
24966tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24967let Inst{6-5} = 0b00;
24968let Inst{31-21} = 0b00111011000;
24969let addrMode = BaseRegOffset;
24970let accessSize = ByteAccess;
24971let mayStore = 1;
24972let BaseOpcode = "S4_storerb_rr";
24973let CextOpcode = "S2_storerb";
24974let InputType = "reg";
24975let isNVStorable = 1;
24976let isPredicable = 1;
24977}
24978def S4_storerb_ur : HInst<
24979(outs),
24980(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24981"memb($Ru32<<#$Ii+#$II) = $Rt32",
24982tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24983let Inst{7-7} = 0b1;
24984let Inst{31-21} = 0b10101101000;
24985let addrMode = BaseLongOffset;
24986let accessSize = ByteAccess;
24987let isExtended = 1;
24988let mayStore = 1;
24989let BaseOpcode = "S4_storerb_ur";
24990let CextOpcode = "S2_storerb";
24991let InputType = "imm";
24992let isNVStorable = 1;
24993let DecoderNamespace = "MustExtend";
24994let isExtendable = 1;
24995let opExtendable = 2;
24996let isExtentSigned = 0;
24997let opExtentBits = 6;
24998let opExtentAlign = 0;
24999}
25000def S4_storerbnew_ap : HInst<
25001(outs IntRegs:$Re32),
25002(ins u32_0Imm:$II, IntRegs:$Nt8),
25003"memb($Re32=#$II) = $Nt8.new",
25004tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25005let Inst{7-6} = 0b10;
25006let Inst{13-11} = 0b000;
25007let Inst{31-21} = 0b10101011101;
25008let addrMode = AbsoluteSet;
25009let accessSize = ByteAccess;
25010let isNVStore = 1;
25011let isNewValue = 1;
25012let isExtended = 1;
25013let isRestrictNoSlot1Store = 1;
25014let mayStore = 1;
25015let BaseOpcode = "S2_storerb_ap";
25016let DecoderNamespace = "MustExtend";
25017let isExtendable = 1;
25018let opExtendable = 1;
25019let isExtentSigned = 0;
25020let opExtentBits = 6;
25021let opExtentAlign = 0;
25022let opNewValue = 2;
25023}
25024def S4_storerbnew_rr : HInst<
25025(outs),
25026(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25027"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25028tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25029let Inst{6-3} = 0b0000;
25030let Inst{31-21} = 0b00111011101;
25031let addrMode = BaseRegOffset;
25032let accessSize = ByteAccess;
25033let isNVStore = 1;
25034let isNewValue = 1;
25035let isRestrictNoSlot1Store = 1;
25036let mayStore = 1;
25037let BaseOpcode = "S4_storerb_rr";
25038let CextOpcode = "S2_storerb";
25039let InputType = "reg";
25040let isPredicable = 1;
25041let opNewValue = 3;
25042}
25043def S4_storerbnew_ur : HInst<
25044(outs),
25045(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25046"memb($Ru32<<#$Ii+#$II) = $Nt8.new",
25047tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25048let Inst{7-7} = 0b1;
25049let Inst{12-11} = 0b00;
25050let Inst{31-21} = 0b10101101101;
25051let addrMode = BaseLongOffset;
25052let accessSize = ByteAccess;
25053let isNVStore = 1;
25054let isNewValue = 1;
25055let isExtended = 1;
25056let isRestrictNoSlot1Store = 1;
25057let mayStore = 1;
25058let BaseOpcode = "S4_storerb_ur";
25059let CextOpcode = "S2_storerb";
25060let DecoderNamespace = "MustExtend";
25061let isExtendable = 1;
25062let opExtendable = 2;
25063let isExtentSigned = 0;
25064let opExtentBits = 6;
25065let opExtentAlign = 0;
25066let opNewValue = 3;
25067}
25068def S4_storerd_ap : HInst<
25069(outs IntRegs:$Re32),
25070(ins u32_0Imm:$II, DoubleRegs:$Rtt32),
25071"memd($Re32=#$II) = $Rtt32",
25072tc_bb07f2c5, TypeST>, Enc_c7a204 {
25073let Inst{7-6} = 0b10;
25074let Inst{13-13} = 0b0;
25075let Inst{31-21} = 0b10101011110;
25076let addrMode = AbsoluteSet;
25077let accessSize = DoubleWordAccess;
25078let isExtended = 1;
25079let mayStore = 1;
25080let BaseOpcode = "S4_storerd_ap";
25081let DecoderNamespace = "MustExtend";
25082let isExtendable = 1;
25083let opExtendable = 1;
25084let isExtentSigned = 0;
25085let opExtentBits = 6;
25086let opExtentAlign = 0;
25087}
25088def S4_storerd_rr : HInst<
25089(outs),
25090(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
25091"memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
25092tc_280f7fe1, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
25093let Inst{6-5} = 0b00;
25094let Inst{31-21} = 0b00111011110;
25095let addrMode = BaseRegOffset;
25096let accessSize = DoubleWordAccess;
25097let mayStore = 1;
25098let BaseOpcode = "S2_storerd_rr";
25099let CextOpcode = "S2_storerd";
25100let InputType = "reg";
25101let isPredicable = 1;
25102}
25103def S4_storerd_ur : HInst<
25104(outs),
25105(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
25106"memd($Ru32<<#$Ii+#$II) = $Rtt32",
25107tc_887d1bb7, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
25108let Inst{7-7} = 0b1;
25109let Inst{31-21} = 0b10101101110;
25110let addrMode = BaseLongOffset;
25111let accessSize = DoubleWordAccess;
25112let isExtended = 1;
25113let mayStore = 1;
25114let BaseOpcode = "S2_storerd_ur";
25115let CextOpcode = "S2_storerd";
25116let InputType = "imm";
25117let DecoderNamespace = "MustExtend";
25118let isExtendable = 1;
25119let opExtendable = 2;
25120let isExtentSigned = 0;
25121let opExtentBits = 6;
25122let opExtentAlign = 0;
25123}
25124def S4_storerf_ap : HInst<
25125(outs IntRegs:$Re32),
25126(ins u32_0Imm:$II, IntRegs:$Rt32),
25127"memh($Re32=#$II) = $Rt32.h",
25128tc_bb07f2c5, TypeST>, Enc_8bcba4 {
25129let Inst{7-6} = 0b10;
25130let Inst{13-13} = 0b0;
25131let Inst{31-21} = 0b10101011011;
25132let addrMode = AbsoluteSet;
25133let accessSize = HalfWordAccess;
25134let isExtended = 1;
25135let mayStore = 1;
25136let BaseOpcode = "S4_storerf_ap";
25137let DecoderNamespace = "MustExtend";
25138let isExtendable = 1;
25139let opExtendable = 1;
25140let isExtentSigned = 0;
25141let opExtentBits = 6;
25142let opExtentAlign = 0;
25143}
25144def S4_storerf_rr : HInst<
25145(outs),
25146(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25147"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
25148tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25149let Inst{6-5} = 0b00;
25150let Inst{31-21} = 0b00111011011;
25151let addrMode = BaseRegOffset;
25152let accessSize = HalfWordAccess;
25153let mayStore = 1;
25154let BaseOpcode = "S4_storerf_rr";
25155let CextOpcode = "S2_storerf";
25156let InputType = "reg";
25157let isPredicable = 1;
25158}
25159def S4_storerf_ur : HInst<
25160(outs),
25161(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25162"memh($Ru32<<#$Ii+#$II) = $Rt32.h",
25163tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25164let Inst{7-7} = 0b1;
25165let Inst{31-21} = 0b10101101011;
25166let addrMode = BaseLongOffset;
25167let accessSize = HalfWordAccess;
25168let isExtended = 1;
25169let mayStore = 1;
25170let BaseOpcode = "S4_storerf_rr";
25171let CextOpcode = "S2_storerf";
25172let InputType = "imm";
25173let DecoderNamespace = "MustExtend";
25174let isExtendable = 1;
25175let opExtendable = 2;
25176let isExtentSigned = 0;
25177let opExtentBits = 6;
25178let opExtentAlign = 0;
25179}
25180def S4_storerh_ap : HInst<
25181(outs IntRegs:$Re32),
25182(ins u32_0Imm:$II, IntRegs:$Rt32),
25183"memh($Re32=#$II) = $Rt32",
25184tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25185let Inst{7-6} = 0b10;
25186let Inst{13-13} = 0b0;
25187let Inst{31-21} = 0b10101011010;
25188let addrMode = AbsoluteSet;
25189let accessSize = HalfWordAccess;
25190let isExtended = 1;
25191let mayStore = 1;
25192let BaseOpcode = "S2_storerh_ap";
25193let isNVStorable = 1;
25194let DecoderNamespace = "MustExtend";
25195let isExtendable = 1;
25196let opExtendable = 1;
25197let isExtentSigned = 0;
25198let opExtentBits = 6;
25199let opExtentAlign = 0;
25200}
25201def S4_storerh_rr : HInst<
25202(outs),
25203(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25204"memh($Rs32+$Ru32<<#$Ii) = $Rt32",
25205tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25206let Inst{6-5} = 0b00;
25207let Inst{31-21} = 0b00111011010;
25208let addrMode = BaseRegOffset;
25209let accessSize = HalfWordAccess;
25210let mayStore = 1;
25211let BaseOpcode = "S2_storerh_rr";
25212let CextOpcode = "S2_storerh";
25213let InputType = "reg";
25214let isNVStorable = 1;
25215let isPredicable = 1;
25216}
25217def S4_storerh_ur : HInst<
25218(outs),
25219(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25220"memh($Ru32<<#$Ii+#$II) = $Rt32",
25221tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25222let Inst{7-7} = 0b1;
25223let Inst{31-21} = 0b10101101010;
25224let addrMode = BaseLongOffset;
25225let accessSize = HalfWordAccess;
25226let isExtended = 1;
25227let mayStore = 1;
25228let BaseOpcode = "S2_storerh_ur";
25229let CextOpcode = "S2_storerh";
25230let InputType = "imm";
25231let isNVStorable = 1;
25232let DecoderNamespace = "MustExtend";
25233let isExtendable = 1;
25234let opExtendable = 2;
25235let isExtentSigned = 0;
25236let opExtentBits = 6;
25237let opExtentAlign = 0;
25238}
25239def S4_storerhnew_ap : HInst<
25240(outs IntRegs:$Re32),
25241(ins u32_0Imm:$II, IntRegs:$Nt8),
25242"memh($Re32=#$II) = $Nt8.new",
25243tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25244let Inst{7-6} = 0b10;
25245let Inst{13-11} = 0b001;
25246let Inst{31-21} = 0b10101011101;
25247let addrMode = AbsoluteSet;
25248let accessSize = HalfWordAccess;
25249let isNVStore = 1;
25250let isNewValue = 1;
25251let isExtended = 1;
25252let isRestrictNoSlot1Store = 1;
25253let mayStore = 1;
25254let BaseOpcode = "S2_storerh_ap";
25255let DecoderNamespace = "MustExtend";
25256let isExtendable = 1;
25257let opExtendable = 1;
25258let isExtentSigned = 0;
25259let opExtentBits = 6;
25260let opExtentAlign = 0;
25261let opNewValue = 2;
25262}
25263def S4_storerhnew_rr : HInst<
25264(outs),
25265(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25266"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25267tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25268let Inst{6-3} = 0b0001;
25269let Inst{31-21} = 0b00111011101;
25270let addrMode = BaseRegOffset;
25271let accessSize = HalfWordAccess;
25272let isNVStore = 1;
25273let isNewValue = 1;
25274let isRestrictNoSlot1Store = 1;
25275let mayStore = 1;
25276let BaseOpcode = "S2_storerh_rr";
25277let CextOpcode = "S2_storerh";
25278let InputType = "reg";
25279let isPredicable = 1;
25280let opNewValue = 3;
25281}
25282def S4_storerhnew_ur : HInst<
25283(outs),
25284(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25285"memh($Ru32<<#$Ii+#$II) = $Nt8.new",
25286tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25287let Inst{7-7} = 0b1;
25288let Inst{12-11} = 0b01;
25289let Inst{31-21} = 0b10101101101;
25290let addrMode = BaseLongOffset;
25291let accessSize = HalfWordAccess;
25292let isNVStore = 1;
25293let isNewValue = 1;
25294let isExtended = 1;
25295let isRestrictNoSlot1Store = 1;
25296let mayStore = 1;
25297let BaseOpcode = "S2_storerh_ur";
25298let CextOpcode = "S2_storerh";
25299let DecoderNamespace = "MustExtend";
25300let isExtendable = 1;
25301let opExtendable = 2;
25302let isExtentSigned = 0;
25303let opExtentBits = 6;
25304let opExtentAlign = 0;
25305let opNewValue = 3;
25306}
25307def S4_storeri_ap : HInst<
25308(outs IntRegs:$Re32),
25309(ins u32_0Imm:$II, IntRegs:$Rt32),
25310"memw($Re32=#$II) = $Rt32",
25311tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25312let Inst{7-6} = 0b10;
25313let Inst{13-13} = 0b0;
25314let Inst{31-21} = 0b10101011100;
25315let addrMode = AbsoluteSet;
25316let accessSize = WordAccess;
25317let isExtended = 1;
25318let mayStore = 1;
25319let BaseOpcode = "S2_storeri_ap";
25320let isNVStorable = 1;
25321let DecoderNamespace = "MustExtend";
25322let isExtendable = 1;
25323let opExtendable = 1;
25324let isExtentSigned = 0;
25325let opExtentBits = 6;
25326let opExtentAlign = 0;
25327}
25328def S4_storeri_rr : HInst<
25329(outs),
25330(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25331"memw($Rs32+$Ru32<<#$Ii) = $Rt32",
25332tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25333let Inst{6-5} = 0b00;
25334let Inst{31-21} = 0b00111011100;
25335let addrMode = BaseRegOffset;
25336let accessSize = WordAccess;
25337let mayStore = 1;
25338let BaseOpcode = "S2_storeri_rr";
25339let CextOpcode = "S2_storeri";
25340let InputType = "reg";
25341let isNVStorable = 1;
25342let isPredicable = 1;
25343}
25344def S4_storeri_ur : HInst<
25345(outs),
25346(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25347"memw($Ru32<<#$Ii+#$II) = $Rt32",
25348tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25349let Inst{7-7} = 0b1;
25350let Inst{31-21} = 0b10101101100;
25351let addrMode = BaseLongOffset;
25352let accessSize = WordAccess;
25353let isExtended = 1;
25354let mayStore = 1;
25355let BaseOpcode = "S2_storeri_ur";
25356let CextOpcode = "S2_storeri";
25357let InputType = "imm";
25358let isNVStorable = 1;
25359let DecoderNamespace = "MustExtend";
25360let isExtendable = 1;
25361let opExtendable = 2;
25362let isExtentSigned = 0;
25363let opExtentBits = 6;
25364let opExtentAlign = 0;
25365}
25366def S4_storerinew_ap : HInst<
25367(outs IntRegs:$Re32),
25368(ins u32_0Imm:$II, IntRegs:$Nt8),
25369"memw($Re32=#$II) = $Nt8.new",
25370tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25371let Inst{7-6} = 0b10;
25372let Inst{13-11} = 0b010;
25373let Inst{31-21} = 0b10101011101;
25374let addrMode = AbsoluteSet;
25375let accessSize = WordAccess;
25376let isNVStore = 1;
25377let isNewValue = 1;
25378let isExtended = 1;
25379let isRestrictNoSlot1Store = 1;
25380let mayStore = 1;
25381let BaseOpcode = "S2_storeri_ap";
25382let DecoderNamespace = "MustExtend";
25383let isExtendable = 1;
25384let opExtendable = 1;
25385let isExtentSigned = 0;
25386let opExtentBits = 6;
25387let opExtentAlign = 0;
25388let opNewValue = 2;
25389}
25390def S4_storerinew_rr : HInst<
25391(outs),
25392(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25393"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25394tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25395let Inst{6-3} = 0b0010;
25396let Inst{31-21} = 0b00111011101;
25397let addrMode = BaseRegOffset;
25398let accessSize = WordAccess;
25399let isNVStore = 1;
25400let isNewValue = 1;
25401let isRestrictNoSlot1Store = 1;
25402let mayStore = 1;
25403let BaseOpcode = "S2_storeri_rr";
25404let CextOpcode = "S2_storeri";
25405let InputType = "reg";
25406let isPredicable = 1;
25407let opNewValue = 3;
25408}
25409def S4_storerinew_ur : HInst<
25410(outs),
25411(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25412"memw($Ru32<<#$Ii+#$II) = $Nt8.new",
25413tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25414let Inst{7-7} = 0b1;
25415let Inst{12-11} = 0b10;
25416let Inst{31-21} = 0b10101101101;
25417let addrMode = BaseLongOffset;
25418let accessSize = WordAccess;
25419let isNVStore = 1;
25420let isNewValue = 1;
25421let isExtended = 1;
25422let isRestrictNoSlot1Store = 1;
25423let mayStore = 1;
25424let BaseOpcode = "S2_storeri_ur";
25425let CextOpcode = "S2_storeri";
25426let DecoderNamespace = "MustExtend";
25427let isExtendable = 1;
25428let opExtendable = 2;
25429let isExtentSigned = 0;
25430let opExtentBits = 6;
25431let opExtentAlign = 0;
25432let opNewValue = 3;
25433}
25434def S4_subaddi : HInst<
25435(outs IntRegs:$Rd32),
25436(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
25437"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
25438tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
25439let Inst{31-23} = 0b110110111;
25440let hasNewValue = 1;
25441let opNewValue = 0;
25442let prefersSlot3 = 1;
25443let isExtendable = 1;
25444let opExtendable = 2;
25445let isExtentSigned = 1;
25446let opExtentBits = 6;
25447let opExtentAlign = 0;
25448}
25449def S4_subi_asl_ri : HInst<
25450(outs IntRegs:$Rx32),
25451(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25452"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
25453tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25454let Inst{2-0} = 0b110;
25455let Inst{4-4} = 0b0;
25456let Inst{31-24} = 0b11011110;
25457let hasNewValue = 1;
25458let opNewValue = 0;
25459let prefersSlot3 = 1;
25460let isExtendable = 1;
25461let opExtendable = 1;
25462let isExtentSigned = 0;
25463let opExtentBits = 8;
25464let opExtentAlign = 0;
25465let Constraints = "$Rx32 = $Rx32in";
25466}
25467def S4_subi_lsr_ri : HInst<
25468(outs IntRegs:$Rx32),
25469(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25470"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
25471tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25472let Inst{2-0} = 0b110;
25473let Inst{4-4} = 0b1;
25474let Inst{31-24} = 0b11011110;
25475let hasNewValue = 1;
25476let opNewValue = 0;
25477let prefersSlot3 = 1;
25478let isExtendable = 1;
25479let opExtendable = 1;
25480let isExtentSigned = 0;
25481let opExtentBits = 8;
25482let opExtentAlign = 0;
25483let Constraints = "$Rx32 = $Rx32in";
25484}
25485def S4_vrcrotate : HInst<
25486(outs DoubleRegs:$Rdd32),
25487(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25488"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
25489tc_f0cdeccf, TypeS_3op>, Enc_645d54 {
25490let Inst{7-6} = 0b11;
25491let Inst{31-21} = 0b11000011110;
25492let prefersSlot3 = 1;
25493}
25494def S4_vrcrotate_acc : HInst<
25495(outs DoubleRegs:$Rxx32),
25496(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25497"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
25498tc_a38c45dc, TypeS_3op>, Enc_b72622 {
25499let Inst{7-6} = 0b00;
25500let Inst{31-21} = 0b11001011101;
25501let prefersSlot3 = 1;
25502let Constraints = "$Rxx32 = $Rxx32in";
25503}
25504def S4_vxaddsubh : HInst<
25505(outs DoubleRegs:$Rdd32),
25506(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25507"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
25508tc_8a825db2, TypeS_3op>, Enc_a56825 {
25509let Inst{7-5} = 0b100;
25510let Inst{13-13} = 0b0;
25511let Inst{31-21} = 0b11000001010;
25512let prefersSlot3 = 1;
25513let Defs = [USR_OVF];
25514}
25515def S4_vxaddsubhr : HInst<
25516(outs DoubleRegs:$Rdd32),
25517(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25518"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
25519tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25520let Inst{7-5} = 0b000;
25521let Inst{13-13} = 0b0;
25522let Inst{31-21} = 0b11000001110;
25523let prefersSlot3 = 1;
25524let Defs = [USR_OVF];
25525}
25526def S4_vxaddsubw : HInst<
25527(outs DoubleRegs:$Rdd32),
25528(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25529"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
25530tc_8a825db2, TypeS_3op>, Enc_a56825 {
25531let Inst{7-5} = 0b000;
25532let Inst{13-13} = 0b0;
25533let Inst{31-21} = 0b11000001010;
25534let prefersSlot3 = 1;
25535let Defs = [USR_OVF];
25536}
25537def S4_vxsubaddh : HInst<
25538(outs DoubleRegs:$Rdd32),
25539(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25540"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
25541tc_8a825db2, TypeS_3op>, Enc_a56825 {
25542let Inst{7-5} = 0b110;
25543let Inst{13-13} = 0b0;
25544let Inst{31-21} = 0b11000001010;
25545let prefersSlot3 = 1;
25546let Defs = [USR_OVF];
25547}
25548def S4_vxsubaddhr : HInst<
25549(outs DoubleRegs:$Rdd32),
25550(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25551"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
25552tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25553let Inst{7-5} = 0b010;
25554let Inst{13-13} = 0b0;
25555let Inst{31-21} = 0b11000001110;
25556let prefersSlot3 = 1;
25557let Defs = [USR_OVF];
25558}
25559def S4_vxsubaddw : HInst<
25560(outs DoubleRegs:$Rdd32),
25561(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25562"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
25563tc_8a825db2, TypeS_3op>, Enc_a56825 {
25564let Inst{7-5} = 0b010;
25565let Inst{13-13} = 0b0;
25566let Inst{31-21} = 0b11000001010;
25567let prefersSlot3 = 1;
25568let Defs = [USR_OVF];
25569}
25570def S5_asrhub_rnd_sat : HInst<
25571(outs IntRegs:$Rd32),
25572(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25573"$Rd32 = vasrhub($Rss32,#$Ii):raw",
25574tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25575let Inst{7-5} = 0b100;
25576let Inst{13-12} = 0b00;
25577let Inst{31-21} = 0b10001000011;
25578let hasNewValue = 1;
25579let opNewValue = 0;
25580let prefersSlot3 = 1;
25581let Defs = [USR_OVF];
25582}
25583def S5_asrhub_rnd_sat_goodsyntax : HInst<
25584(outs IntRegs:$Rd32),
25585(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25586"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
25587tc_0dfac0a7, TypeS_2op> {
25588let hasNewValue = 1;
25589let opNewValue = 0;
25590let isPseudo = 1;
25591}
25592def S5_asrhub_sat : HInst<
25593(outs IntRegs:$Rd32),
25594(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25595"$Rd32 = vasrhub($Rss32,#$Ii):sat",
25596tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25597let Inst{7-5} = 0b101;
25598let Inst{13-12} = 0b00;
25599let Inst{31-21} = 0b10001000011;
25600let hasNewValue = 1;
25601let opNewValue = 0;
25602let prefersSlot3 = 1;
25603let Defs = [USR_OVF];
25604}
25605def S5_popcountp : HInst<
25606(outs IntRegs:$Rd32),
25607(ins DoubleRegs:$Rss32),
25608"$Rd32 = popcount($Rss32)",
25609tc_d3632d88, TypeS_2op>, Enc_90cd8b {
25610let Inst{13-5} = 0b000000011;
25611let Inst{31-21} = 0b10001000011;
25612let hasNewValue = 1;
25613let opNewValue = 0;
25614let prefersSlot3 = 1;
25615}
25616def S5_vasrhrnd : HInst<
25617(outs DoubleRegs:$Rdd32),
25618(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25619"$Rdd32 = vasrh($Rss32,#$Ii):raw",
25620tc_0dfac0a7, TypeS_2op>, Enc_12b6e9 {
25621let Inst{7-5} = 0b000;
25622let Inst{13-12} = 0b00;
25623let Inst{31-21} = 0b10000000001;
25624let prefersSlot3 = 1;
25625}
25626def S5_vasrhrnd_goodsyntax : HInst<
25627(outs DoubleRegs:$Rdd32),
25628(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25629"$Rdd32 = vasrh($Rss32,#$Ii):rnd",
25630tc_0dfac0a7, TypeS_2op> {
25631let isPseudo = 1;
25632}
25633def S6_allocframe_to_raw : HInst<
25634(outs),
25635(ins u11_3Imm:$Ii),
25636"allocframe(#$Ii)",
25637tc_934753bb, TypeMAPPING>, Requires<[HasV65]> {
25638let isPseudo = 1;
25639let isCodeGenOnly = 1;
25640}
25641def S6_rol_i_p : HInst<
25642(outs DoubleRegs:$Rdd32),
25643(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
25644"$Rdd32 = rol($Rss32,#$Ii)",
25645tc_407e96f9, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> {
25646let Inst{7-5} = 0b011;
25647let Inst{31-21} = 0b10000000000;
25648}
25649def S6_rol_i_p_acc : HInst<
25650(outs DoubleRegs:$Rxx32),
25651(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25652"$Rxx32 += rol($Rss32,#$Ii)",
25653tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25654let Inst{7-5} = 0b111;
25655let Inst{31-21} = 0b10000010000;
25656let prefersSlot3 = 1;
25657let Constraints = "$Rxx32 = $Rxx32in";
25658}
25659def S6_rol_i_p_and : HInst<
25660(outs DoubleRegs:$Rxx32),
25661(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25662"$Rxx32 &= rol($Rss32,#$Ii)",
25663tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25664let Inst{7-5} = 0b011;
25665let Inst{31-21} = 0b10000010010;
25666let prefersSlot3 = 1;
25667let Constraints = "$Rxx32 = $Rxx32in";
25668}
25669def S6_rol_i_p_nac : HInst<
25670(outs DoubleRegs:$Rxx32),
25671(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25672"$Rxx32 -= rol($Rss32,#$Ii)",
25673tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25674let Inst{7-5} = 0b011;
25675let Inst{31-21} = 0b10000010000;
25676let prefersSlot3 = 1;
25677let Constraints = "$Rxx32 = $Rxx32in";
25678}
25679def S6_rol_i_p_or : HInst<
25680(outs DoubleRegs:$Rxx32),
25681(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25682"$Rxx32 |= rol($Rss32,#$Ii)",
25683tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25684let Inst{7-5} = 0b111;
25685let Inst{31-21} = 0b10000010010;
25686let prefersSlot3 = 1;
25687let Constraints = "$Rxx32 = $Rxx32in";
25688}
25689def S6_rol_i_p_xacc : HInst<
25690(outs DoubleRegs:$Rxx32),
25691(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25692"$Rxx32 ^= rol($Rss32,#$Ii)",
25693tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25694let Inst{7-5} = 0b011;
25695let Inst{31-21} = 0b10000010100;
25696let prefersSlot3 = 1;
25697let Constraints = "$Rxx32 = $Rxx32in";
25698}
25699def S6_rol_i_r : HInst<
25700(outs IntRegs:$Rd32),
25701(ins IntRegs:$Rs32, u5_0Imm:$Ii),
25702"$Rd32 = rol($Rs32,#$Ii)",
25703tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV60]> {
25704let Inst{7-5} = 0b011;
25705let Inst{13-13} = 0b0;
25706let Inst{31-21} = 0b10001100000;
25707let hasNewValue = 1;
25708let opNewValue = 0;
25709}
25710def S6_rol_i_r_acc : HInst<
25711(outs IntRegs:$Rx32),
25712(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25713"$Rx32 += rol($Rs32,#$Ii)",
25714tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25715let Inst{7-5} = 0b111;
25716let Inst{13-13} = 0b0;
25717let Inst{31-21} = 0b10001110000;
25718let hasNewValue = 1;
25719let opNewValue = 0;
25720let prefersSlot3 = 1;
25721let Constraints = "$Rx32 = $Rx32in";
25722}
25723def S6_rol_i_r_and : HInst<
25724(outs IntRegs:$Rx32),
25725(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25726"$Rx32 &= rol($Rs32,#$Ii)",
25727tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25728let Inst{7-5} = 0b011;
25729let Inst{13-13} = 0b0;
25730let Inst{31-21} = 0b10001110010;
25731let hasNewValue = 1;
25732let opNewValue = 0;
25733let prefersSlot3 = 1;
25734let Constraints = "$Rx32 = $Rx32in";
25735}
25736def S6_rol_i_r_nac : HInst<
25737(outs IntRegs:$Rx32),
25738(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25739"$Rx32 -= rol($Rs32,#$Ii)",
25740tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25741let Inst{7-5} = 0b011;
25742let Inst{13-13} = 0b0;
25743let Inst{31-21} = 0b10001110000;
25744let hasNewValue = 1;
25745let opNewValue = 0;
25746let prefersSlot3 = 1;
25747let Constraints = "$Rx32 = $Rx32in";
25748}
25749def S6_rol_i_r_or : HInst<
25750(outs IntRegs:$Rx32),
25751(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25752"$Rx32 |= rol($Rs32,#$Ii)",
25753tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25754let Inst{7-5} = 0b111;
25755let Inst{13-13} = 0b0;
25756let Inst{31-21} = 0b10001110010;
25757let hasNewValue = 1;
25758let opNewValue = 0;
25759let prefersSlot3 = 1;
25760let Constraints = "$Rx32 = $Rx32in";
25761}
25762def S6_rol_i_r_xacc : HInst<
25763(outs IntRegs:$Rx32),
25764(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25765"$Rx32 ^= rol($Rs32,#$Ii)",
25766tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25767let Inst{7-5} = 0b011;
25768let Inst{13-13} = 0b0;
25769let Inst{31-21} = 0b10001110100;
25770let hasNewValue = 1;
25771let opNewValue = 0;
25772let prefersSlot3 = 1;
25773let Constraints = "$Rx32 = $Rx32in";
25774}
25775def S6_vsplatrbp : HInst<
25776(outs DoubleRegs:$Rdd32),
25777(ins IntRegs:$Rs32),
25778"$Rdd32 = vsplatb($Rs32)",
25779tc_ef921005, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> {
25780let Inst{13-5} = 0b000000100;
25781let Inst{31-21} = 0b10000100010;
25782}
25783def S6_vtrunehb_ppp : HInst<
25784(outs DoubleRegs:$Rdd32),
25785(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25786"$Rdd32 = vtrunehb($Rss32,$Rtt32)",
25787tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25788let Inst{7-5} = 0b011;
25789let Inst{13-13} = 0b0;
25790let Inst{31-21} = 0b11000001100;
25791}
25792def S6_vtrunohb_ppp : HInst<
25793(outs DoubleRegs:$Rdd32),
25794(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25795"$Rdd32 = vtrunohb($Rss32,$Rtt32)",
25796tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25797let Inst{7-5} = 0b101;
25798let Inst{13-13} = 0b0;
25799let Inst{31-21} = 0b11000001100;
25800}
25801def SA1_addi : HInst<
25802(outs GeneralSubRegs:$Rx16),
25803(ins IntRegs:$Rx16in, s32_0Imm:$Ii),
25804"$Rx16 = add($Rx16in,#$Ii)",
25805tc_5b347363, TypeSUBINSN>, Enc_93af4c {
25806let Inst{12-11} = 0b00;
25807let hasNewValue = 1;
25808let opNewValue = 0;
25809let AsmVariantName = "NonParsable";
25810let DecoderNamespace = "SUBINSN_A";
25811let isExtendable = 1;
25812let opExtendable = 2;
25813let isExtentSigned = 1;
25814let opExtentBits = 7;
25815let opExtentAlign = 0;
25816let Constraints = "$Rx16 = $Rx16in";
25817}
25818def SA1_addrx : HInst<
25819(outs GeneralSubRegs:$Rx16),
25820(ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16),
25821"$Rx16 = add($Rx16in,$Rs16)",
25822tc_5b347363, TypeSUBINSN>, Enc_0527db {
25823let Inst{12-8} = 0b11000;
25824let hasNewValue = 1;
25825let opNewValue = 0;
25826let AsmVariantName = "NonParsable";
25827let DecoderNamespace = "SUBINSN_A";
25828let Constraints = "$Rx16 = $Rx16in";
25829}
25830def SA1_addsp : HInst<
25831(outs GeneralSubRegs:$Rd16),
25832(ins u6_2Imm:$Ii),
25833"$Rd16 = add(r29,#$Ii)",
25834tc_3d14a17b, TypeSUBINSN>, Enc_2df31d {
25835let Inst{12-10} = 0b011;
25836let hasNewValue = 1;
25837let opNewValue = 0;
25838let AsmVariantName = "NonParsable";
25839let Uses = [R29];
25840let DecoderNamespace = "SUBINSN_A";
25841}
25842def SA1_and1 : HInst<
25843(outs GeneralSubRegs:$Rd16),
25844(ins GeneralSubRegs:$Rs16),
25845"$Rd16 = and($Rs16,#1)",
25846tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
25847let Inst{12-8} = 0b10010;
25848let hasNewValue = 1;
25849let opNewValue = 0;
25850let AsmVariantName = "NonParsable";
25851let DecoderNamespace = "SUBINSN_A";
25852}
25853def SA1_clrf : HInst<
25854(outs GeneralSubRegs:$Rd16),
25855(ins),
25856"if (!p0) $Rd16 = #0",
25857tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25858let Inst{12-4} = 0b110100111;
25859let isPredicated = 1;
25860let isPredicatedFalse = 1;
25861let hasNewValue = 1;
25862let opNewValue = 0;
25863let AsmVariantName = "NonParsable";
25864let Uses = [P0];
25865let DecoderNamespace = "SUBINSN_A";
25866}
25867def SA1_clrfnew : HInst<
25868(outs GeneralSubRegs:$Rd16),
25869(ins),
25870"if (!p0.new) $Rd16 = #0",
25871tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
25872let Inst{12-4} = 0b110100101;
25873let isPredicated = 1;
25874let isPredicatedFalse = 1;
25875let hasNewValue = 1;
25876let opNewValue = 0;
25877let AsmVariantName = "NonParsable";
25878let isPredicatedNew = 1;
25879let Uses = [P0];
25880let DecoderNamespace = "SUBINSN_A";
25881}
25882def SA1_clrt : HInst<
25883(outs GeneralSubRegs:$Rd16),
25884(ins),
25885"if (p0) $Rd16 = #0",
25886tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25887let Inst{12-4} = 0b110100110;
25888let isPredicated = 1;
25889let hasNewValue = 1;
25890let opNewValue = 0;
25891let AsmVariantName = "NonParsable";
25892let Uses = [P0];
25893let DecoderNamespace = "SUBINSN_A";
25894}
25895def SA1_clrtnew : HInst<
25896(outs GeneralSubRegs:$Rd16),
25897(ins),
25898"if (p0.new) $Rd16 = #0",
25899tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
25900let Inst{12-4} = 0b110100100;
25901let isPredicated = 1;
25902let hasNewValue = 1;
25903let opNewValue = 0;
25904let AsmVariantName = "NonParsable";
25905let isPredicatedNew = 1;
25906let Uses = [P0];
25907let DecoderNamespace = "SUBINSN_A";
25908}
25909def SA1_cmpeqi : HInst<
25910(outs),
25911(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
25912"p0 = cmp.eq($Rs16,#$Ii)",
25913tc_59a7822c, TypeSUBINSN>, Enc_63eaeb {
25914let Inst{3-2} = 0b00;
25915let Inst{12-8} = 0b11001;
25916let AsmVariantName = "NonParsable";
25917let Defs = [P0];
25918let DecoderNamespace = "SUBINSN_A";
25919}
25920def SA1_combine0i : HInst<
25921(outs GeneralDoubleLow8Regs:$Rdd8),
25922(ins u2_0Imm:$Ii),
25923"$Rdd8 = combine(#0,#$Ii)",
25924tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
25925let Inst{4-3} = 0b00;
25926let Inst{12-7} = 0b111000;
25927let hasNewValue = 1;
25928let opNewValue = 0;
25929let AsmVariantName = "NonParsable";
25930let DecoderNamespace = "SUBINSN_A";
25931}
25932def SA1_combine1i : HInst<
25933(outs GeneralDoubleLow8Regs:$Rdd8),
25934(ins u2_0Imm:$Ii),
25935"$Rdd8 = combine(#1,#$Ii)",
25936tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
25937let Inst{4-3} = 0b01;
25938let Inst{12-7} = 0b111000;
25939let hasNewValue = 1;
25940let opNewValue = 0;
25941let AsmVariantName = "NonParsable";
25942let DecoderNamespace = "SUBINSN_A";
25943}
25944def SA1_combine2i : HInst<
25945(outs GeneralDoubleLow8Regs:$Rdd8),
25946(ins u2_0Imm:$Ii),
25947"$Rdd8 = combine(#2,#$Ii)",
25948tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
25949let Inst{4-3} = 0b10;
25950let Inst{12-7} = 0b111000;
25951let hasNewValue = 1;
25952let opNewValue = 0;
25953let AsmVariantName = "NonParsable";
25954let DecoderNamespace = "SUBINSN_A";
25955}
25956def SA1_combine3i : HInst<
25957(outs GeneralDoubleLow8Regs:$Rdd8),
25958(ins u2_0Imm:$Ii),
25959"$Rdd8 = combine(#3,#$Ii)",
25960tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
25961let Inst{4-3} = 0b11;
25962let Inst{12-7} = 0b111000;
25963let hasNewValue = 1;
25964let opNewValue = 0;
25965let AsmVariantName = "NonParsable";
25966let DecoderNamespace = "SUBINSN_A";
25967}
25968def SA1_combinerz : HInst<
25969(outs GeneralDoubleLow8Regs:$Rdd8),
25970(ins GeneralSubRegs:$Rs16),
25971"$Rdd8 = combine($Rs16,#0)",
25972tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
25973let Inst{3-3} = 0b1;
25974let Inst{12-8} = 0b11101;
25975let hasNewValue = 1;
25976let opNewValue = 0;
25977let AsmVariantName = "NonParsable";
25978let DecoderNamespace = "SUBINSN_A";
25979}
25980def SA1_combinezr : HInst<
25981(outs GeneralDoubleLow8Regs:$Rdd8),
25982(ins GeneralSubRegs:$Rs16),
25983"$Rdd8 = combine(#0,$Rs16)",
25984tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
25985let Inst{3-3} = 0b0;
25986let Inst{12-8} = 0b11101;
25987let hasNewValue = 1;
25988let opNewValue = 0;
25989let AsmVariantName = "NonParsable";
25990let DecoderNamespace = "SUBINSN_A";
25991}
25992def SA1_dec : HInst<
25993(outs GeneralSubRegs:$Rd16),
25994(ins GeneralSubRegs:$Rs16, n1Const:$n1),
25995"$Rd16 = add($Rs16,#$n1)",
25996tc_5b347363, TypeSUBINSN>, Enc_ee5ed0 {
25997let Inst{12-8} = 0b10011;
25998let hasNewValue = 1;
25999let opNewValue = 0;
26000let AsmVariantName = "NonParsable";
26001let DecoderNamespace = "SUBINSN_A";
26002}
26003def SA1_inc : HInst<
26004(outs GeneralSubRegs:$Rd16),
26005(ins GeneralSubRegs:$Rs16),
26006"$Rd16 = add($Rs16,#1)",
26007tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26008let Inst{12-8} = 0b10001;
26009let hasNewValue = 1;
26010let opNewValue = 0;
26011let AsmVariantName = "NonParsable";
26012let DecoderNamespace = "SUBINSN_A";
26013}
26014def SA1_seti : HInst<
26015(outs GeneralSubRegs:$Rd16),
26016(ins u32_0Imm:$Ii),
26017"$Rd16 = #$Ii",
26018tc_3d14a17b, TypeSUBINSN>, Enc_e39bb2 {
26019let Inst{12-10} = 0b010;
26020let hasNewValue = 1;
26021let opNewValue = 0;
26022let AsmVariantName = "NonParsable";
26023let DecoderNamespace = "SUBINSN_A";
26024let isExtendable = 1;
26025let opExtendable = 1;
26026let isExtentSigned = 0;
26027let opExtentBits = 6;
26028let opExtentAlign = 0;
26029}
26030def SA1_setin1 : HInst<
26031(outs GeneralSubRegs:$Rd16),
26032(ins n1Const:$n1),
26033"$Rd16 = #$n1",
26034tc_3d14a17b, TypeSUBINSN>, Enc_7a0ea6 {
26035let Inst{12-4} = 0b110100000;
26036let hasNewValue = 1;
26037let opNewValue = 0;
26038let AsmVariantName = "NonParsable";
26039let DecoderNamespace = "SUBINSN_A";
26040}
26041def SA1_sxtb : HInst<
26042(outs GeneralSubRegs:$Rd16),
26043(ins GeneralSubRegs:$Rs16),
26044"$Rd16 = sxtb($Rs16)",
26045tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26046let Inst{12-8} = 0b10101;
26047let hasNewValue = 1;
26048let opNewValue = 0;
26049let AsmVariantName = "NonParsable";
26050let DecoderNamespace = "SUBINSN_A";
26051}
26052def SA1_sxth : HInst<
26053(outs GeneralSubRegs:$Rd16),
26054(ins GeneralSubRegs:$Rs16),
26055"$Rd16 = sxth($Rs16)",
26056tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26057let Inst{12-8} = 0b10100;
26058let hasNewValue = 1;
26059let opNewValue = 0;
26060let AsmVariantName = "NonParsable";
26061let DecoderNamespace = "SUBINSN_A";
26062}
26063def SA1_tfr : HInst<
26064(outs GeneralSubRegs:$Rd16),
26065(ins GeneralSubRegs:$Rs16),
26066"$Rd16 = $Rs16",
26067tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26068let Inst{12-8} = 0b10000;
26069let hasNewValue = 1;
26070let opNewValue = 0;
26071let AsmVariantName = "NonParsable";
26072let DecoderNamespace = "SUBINSN_A";
26073}
26074def SA1_zxtb : HInst<
26075(outs GeneralSubRegs:$Rd16),
26076(ins GeneralSubRegs:$Rs16),
26077"$Rd16 = and($Rs16,#255)",
26078tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26079let Inst{12-8} = 0b10111;
26080let hasNewValue = 1;
26081let opNewValue = 0;
26082let AsmVariantName = "NonParsable";
26083let DecoderNamespace = "SUBINSN_A";
26084}
26085def SA1_zxth : HInst<
26086(outs GeneralSubRegs:$Rd16),
26087(ins GeneralSubRegs:$Rs16),
26088"$Rd16 = zxth($Rs16)",
26089tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26090let Inst{12-8} = 0b10110;
26091let hasNewValue = 1;
26092let opNewValue = 0;
26093let AsmVariantName = "NonParsable";
26094let DecoderNamespace = "SUBINSN_A";
26095}
26096def SL1_loadri_io : HInst<
26097(outs GeneralSubRegs:$Rd16),
26098(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26099"$Rd16 = memw($Rs16+#$Ii)",
26100tc_4222e6bf, TypeSUBINSN>, Enc_53dca9 {
26101let Inst{12-12} = 0b0;
26102let hasNewValue = 1;
26103let opNewValue = 0;
26104let addrMode = BaseImmOffset;
26105let accessSize = WordAccess;
26106let AsmVariantName = "NonParsable";
26107let mayLoad = 1;
26108let DecoderNamespace = "SUBINSN_L1";
26109}
26110def SL1_loadrub_io : HInst<
26111(outs GeneralSubRegs:$Rd16),
26112(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26113"$Rd16 = memub($Rs16+#$Ii)",
26114tc_4222e6bf, TypeSUBINSN>, Enc_c175d0 {
26115let Inst{12-12} = 0b1;
26116let hasNewValue = 1;
26117let opNewValue = 0;
26118let addrMode = BaseImmOffset;
26119let accessSize = ByteAccess;
26120let AsmVariantName = "NonParsable";
26121let mayLoad = 1;
26122let DecoderNamespace = "SUBINSN_L1";
26123}
26124def SL2_deallocframe : HInst<
26125(outs),
26126(ins),
26127"deallocframe",
26128tc_937dd41c, TypeSUBINSN>, Enc_e3b0c4 {
26129let Inst{12-0} = 0b1111100000000;
26130let accessSize = DoubleWordAccess;
26131let AsmVariantName = "NonParsable";
26132let mayLoad = 1;
26133let Uses = [FRAMEKEY, R30];
26134let Defs = [R29, R30, R31];
26135let DecoderNamespace = "SUBINSN_L2";
26136}
26137def SL2_jumpr31 : HInst<
26138(outs),
26139(ins),
26140"jumpr r31",
26141tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26142let Inst{12-0} = 0b1111111000000;
26143let isTerminator = 1;
26144let isIndirectBranch = 1;
26145let AsmVariantName = "NonParsable";
26146let cofMax1 = 1;
26147let isReturn = 1;
26148let Uses = [R31];
26149let Defs = [PC];
26150let DecoderNamespace = "SUBINSN_L2";
26151}
26152def SL2_jumpr31_f : HInst<
26153(outs),
26154(ins),
26155"if (!p0) jumpr r31",
26156tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26157let Inst{12-0} = 0b1111111000101;
26158let isPredicated = 1;
26159let isPredicatedFalse = 1;
26160let isTerminator = 1;
26161let isIndirectBranch = 1;
26162let AsmVariantName = "NonParsable";
26163let cofMax1 = 1;
26164let isReturn = 1;
26165let Uses = [P0, R31];
26166let Defs = [PC];
26167let isTaken = Inst{4};
26168let DecoderNamespace = "SUBINSN_L2";
26169}
26170def SL2_jumpr31_fnew : HInst<
26171(outs),
26172(ins),
26173"if (!p0.new) jumpr:nt r31",
26174tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26175let Inst{12-0} = 0b1111111000111;
26176let isPredicated = 1;
26177let isPredicatedFalse = 1;
26178let isTerminator = 1;
26179let isIndirectBranch = 1;
26180let AsmVariantName = "NonParsable";
26181let isPredicatedNew = 1;
26182let cofMax1 = 1;
26183let isReturn = 1;
26184let Uses = [P0, R31];
26185let Defs = [PC];
26186let isTaken = Inst{4};
26187let DecoderNamespace = "SUBINSN_L2";
26188}
26189def SL2_jumpr31_t : HInst<
26190(outs),
26191(ins),
26192"if (p0) jumpr r31",
26193tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26194let Inst{12-0} = 0b1111111000100;
26195let isPredicated = 1;
26196let isTerminator = 1;
26197let isIndirectBranch = 1;
26198let AsmVariantName = "NonParsable";
26199let cofMax1 = 1;
26200let isReturn = 1;
26201let Uses = [P0, R31];
26202let Defs = [PC];
26203let isTaken = Inst{4};
26204let DecoderNamespace = "SUBINSN_L2";
26205}
26206def SL2_jumpr31_tnew : HInst<
26207(outs),
26208(ins),
26209"if (p0.new) jumpr:nt r31",
26210tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26211let Inst{12-0} = 0b1111111000110;
26212let isPredicated = 1;
26213let isTerminator = 1;
26214let isIndirectBranch = 1;
26215let AsmVariantName = "NonParsable";
26216let isPredicatedNew = 1;
26217let cofMax1 = 1;
26218let isReturn = 1;
26219let Uses = [P0, R31];
26220let Defs = [PC];
26221let isTaken = Inst{4};
26222let DecoderNamespace = "SUBINSN_L2";
26223}
26224def SL2_loadrb_io : HInst<
26225(outs GeneralSubRegs:$Rd16),
26226(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
26227"$Rd16 = memb($Rs16+#$Ii)",
26228tc_4222e6bf, TypeSUBINSN>, Enc_2fbf3c {
26229let Inst{12-11} = 0b10;
26230let hasNewValue = 1;
26231let opNewValue = 0;
26232let addrMode = BaseImmOffset;
26233let accessSize = ByteAccess;
26234let AsmVariantName = "NonParsable";
26235let mayLoad = 1;
26236let DecoderNamespace = "SUBINSN_L2";
26237}
26238def SL2_loadrd_sp : HInst<
26239(outs GeneralDoubleLow8Regs:$Rdd8),
26240(ins u5_3Imm:$Ii),
26241"$Rdd8 = memd(r29+#$Ii)",
26242tc_8a6d0d94, TypeSUBINSN>, Enc_86a14b {
26243let Inst{12-8} = 0b11110;
26244let hasNewValue = 1;
26245let opNewValue = 0;
26246let addrMode = BaseImmOffset;
26247let accessSize = DoubleWordAccess;
26248let AsmVariantName = "NonParsable";
26249let mayLoad = 1;
26250let Uses = [R29];
26251let DecoderNamespace = "SUBINSN_L2";
26252}
26253def SL2_loadrh_io : HInst<
26254(outs GeneralSubRegs:$Rd16),
26255(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26256"$Rd16 = memh($Rs16+#$Ii)",
26257tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26258let Inst{12-11} = 0b00;
26259let hasNewValue = 1;
26260let opNewValue = 0;
26261let addrMode = BaseImmOffset;
26262let accessSize = HalfWordAccess;
26263let AsmVariantName = "NonParsable";
26264let mayLoad = 1;
26265let DecoderNamespace = "SUBINSN_L2";
26266}
26267def SL2_loadri_sp : HInst<
26268(outs GeneralSubRegs:$Rd16),
26269(ins u5_2Imm:$Ii),
26270"$Rd16 = memw(r29+#$Ii)",
26271tc_8a6d0d94, TypeSUBINSN>, Enc_51635c {
26272let Inst{12-9} = 0b1110;
26273let hasNewValue = 1;
26274let opNewValue = 0;
26275let addrMode = BaseImmOffset;
26276let accessSize = WordAccess;
26277let AsmVariantName = "NonParsable";
26278let mayLoad = 1;
26279let Uses = [R29];
26280let DecoderNamespace = "SUBINSN_L2";
26281}
26282def SL2_loadruh_io : HInst<
26283(outs GeneralSubRegs:$Rd16),
26284(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26285"$Rd16 = memuh($Rs16+#$Ii)",
26286tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26287let Inst{12-11} = 0b01;
26288let hasNewValue = 1;
26289let opNewValue = 0;
26290let addrMode = BaseImmOffset;
26291let accessSize = HalfWordAccess;
26292let AsmVariantName = "NonParsable";
26293let mayLoad = 1;
26294let DecoderNamespace = "SUBINSN_L2";
26295}
26296def SL2_return : HInst<
26297(outs),
26298(ins),
26299"dealloc_return",
26300tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26301let Inst{12-0} = 0b1111101000000;
26302let isTerminator = 1;
26303let isIndirectBranch = 1;
26304let accessSize = DoubleWordAccess;
26305let AsmVariantName = "NonParsable";
26306let mayLoad = 1;
26307let cofMax1 = 1;
26308let isRestrictNoSlot1Store = 1;
26309let isReturn = 1;
26310let Uses = [FRAMEKEY, R30];
26311let Defs = [PC, R29, R30, R31];
26312let DecoderNamespace = "SUBINSN_L2";
26313}
26314def SL2_return_f : HInst<
26315(outs),
26316(ins),
26317"if (!p0) dealloc_return",
26318tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26319let Inst{12-0} = 0b1111101000101;
26320let isPredicated = 1;
26321let isPredicatedFalse = 1;
26322let isTerminator = 1;
26323let isIndirectBranch = 1;
26324let accessSize = DoubleWordAccess;
26325let AsmVariantName = "NonParsable";
26326let mayLoad = 1;
26327let cofMax1 = 1;
26328let isRestrictNoSlot1Store = 1;
26329let isReturn = 1;
26330let Uses = [FRAMEKEY, P0, R30];
26331let Defs = [PC, R29, R30, R31];
26332let isTaken = Inst{4};
26333let DecoderNamespace = "SUBINSN_L2";
26334}
26335def SL2_return_fnew : HInst<
26336(outs),
26337(ins),
26338"if (!p0.new) dealloc_return:nt",
26339tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26340let Inst{12-0} = 0b1111101000111;
26341let isPredicated = 1;
26342let isPredicatedFalse = 1;
26343let isTerminator = 1;
26344let isIndirectBranch = 1;
26345let accessSize = DoubleWordAccess;
26346let AsmVariantName = "NonParsable";
26347let isPredicatedNew = 1;
26348let mayLoad = 1;
26349let cofMax1 = 1;
26350let isRestrictNoSlot1Store = 1;
26351let isReturn = 1;
26352let Uses = [FRAMEKEY, P0, R30];
26353let Defs = [PC, R29, R30, R31];
26354let isTaken = Inst{4};
26355let DecoderNamespace = "SUBINSN_L2";
26356}
26357def SL2_return_t : HInst<
26358(outs),
26359(ins),
26360"if (p0) dealloc_return",
26361tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26362let Inst{12-0} = 0b1111101000100;
26363let isPredicated = 1;
26364let isTerminator = 1;
26365let isIndirectBranch = 1;
26366let accessSize = DoubleWordAccess;
26367let AsmVariantName = "NonParsable";
26368let mayLoad = 1;
26369let cofMax1 = 1;
26370let isRestrictNoSlot1Store = 1;
26371let isReturn = 1;
26372let Uses = [FRAMEKEY, P0, R30];
26373let Defs = [PC, R29, R30, R31];
26374let isTaken = Inst{4};
26375let DecoderNamespace = "SUBINSN_L2";
26376}
26377def SL2_return_tnew : HInst<
26378(outs),
26379(ins),
26380"if (p0.new) dealloc_return:nt",
26381tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26382let Inst{12-0} = 0b1111101000110;
26383let isPredicated = 1;
26384let isTerminator = 1;
26385let isIndirectBranch = 1;
26386let accessSize = DoubleWordAccess;
26387let AsmVariantName = "NonParsable";
26388let isPredicatedNew = 1;
26389let mayLoad = 1;
26390let cofMax1 = 1;
26391let isRestrictNoSlot1Store = 1;
26392let isReturn = 1;
26393let Uses = [FRAMEKEY, P0, R30];
26394let Defs = [PC, R29, R30, R31];
26395let isTaken = Inst{4};
26396let DecoderNamespace = "SUBINSN_L2";
26397}
26398def SS1_storeb_io : HInst<
26399(outs),
26400(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
26401"memb($Rs16+#$Ii) = $Rt16",
26402tc_ae5babd7, TypeSUBINSN>, Enc_b38ffc {
26403let Inst{12-12} = 0b1;
26404let addrMode = BaseImmOffset;
26405let accessSize = ByteAccess;
26406let AsmVariantName = "NonParsable";
26407let mayStore = 1;
26408let DecoderNamespace = "SUBINSN_S1";
26409}
26410def SS1_storew_io : HInst<
26411(outs),
26412(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
26413"memw($Rs16+#$Ii) = $Rt16",
26414tc_ae5babd7, TypeSUBINSN>, Enc_f55a0c {
26415let Inst{12-12} = 0b0;
26416let addrMode = BaseImmOffset;
26417let accessSize = WordAccess;
26418let AsmVariantName = "NonParsable";
26419let mayStore = 1;
26420let DecoderNamespace = "SUBINSN_S1";
26421}
26422def SS2_allocframe : HInst<
26423(outs),
26424(ins u5_3Imm:$Ii),
26425"allocframe(#$Ii)",
26426tc_1242dc2a, TypeSUBINSN>, Enc_6f70ca {
26427let Inst{3-0} = 0b0000;
26428let Inst{12-9} = 0b1110;
26429let addrMode = BaseImmOffset;
26430let accessSize = DoubleWordAccess;
26431let AsmVariantName = "NonParsable";
26432let mayStore = 1;
26433let Uses = [FRAMEKEY, FRAMELIMIT, R29, R30, R31];
26434let Defs = [R29, R30];
26435let DecoderNamespace = "SUBINSN_S2";
26436}
26437def SS2_storebi0 : HInst<
26438(outs),
26439(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26440"memb($Rs16+#$Ii) = #0",
26441tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26442let Inst{12-8} = 0b10010;
26443let addrMode = BaseImmOffset;
26444let accessSize = ByteAccess;
26445let AsmVariantName = "NonParsable";
26446let mayStore = 1;
26447let DecoderNamespace = "SUBINSN_S2";
26448}
26449def SS2_storebi1 : HInst<
26450(outs),
26451(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26452"memb($Rs16+#$Ii) = #1",
26453tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26454let Inst{12-8} = 0b10011;
26455let addrMode = BaseImmOffset;
26456let accessSize = ByteAccess;
26457let AsmVariantName = "NonParsable";
26458let mayStore = 1;
26459let DecoderNamespace = "SUBINSN_S2";
26460}
26461def SS2_stored_sp : HInst<
26462(outs),
26463(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
26464"memd(r29+#$Ii) = $Rtt8",
26465tc_0655b949, TypeSUBINSN>, Enc_b8309d {
26466let Inst{12-9} = 0b0101;
26467let addrMode = BaseImmOffset;
26468let accessSize = DoubleWordAccess;
26469let AsmVariantName = "NonParsable";
26470let mayStore = 1;
26471let Uses = [R29];
26472let DecoderNamespace = "SUBINSN_S2";
26473}
26474def SS2_storeh_io : HInst<
26475(outs),
26476(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
26477"memh($Rs16+#$Ii) = $Rt16",
26478tc_ae5babd7, TypeSUBINSN>, Enc_625deb {
26479let Inst{12-11} = 0b00;
26480let addrMode = BaseImmOffset;
26481let accessSize = HalfWordAccess;
26482let AsmVariantName = "NonParsable";
26483let mayStore = 1;
26484let DecoderNamespace = "SUBINSN_S2";
26485}
26486def SS2_storew_sp : HInst<
26487(outs),
26488(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
26489"memw(r29+#$Ii) = $Rt16",
26490tc_0655b949, TypeSUBINSN>, Enc_87c142 {
26491let Inst{12-9} = 0b0100;
26492let addrMode = BaseImmOffset;
26493let accessSize = WordAccess;
26494let AsmVariantName = "NonParsable";
26495let mayStore = 1;
26496let Uses = [R29];
26497let DecoderNamespace = "SUBINSN_S2";
26498}
26499def SS2_storewi0 : HInst<
26500(outs),
26501(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26502"memw($Rs16+#$Ii) = #0",
26503tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26504let Inst{12-8} = 0b10000;
26505let addrMode = BaseImmOffset;
26506let accessSize = WordAccess;
26507let AsmVariantName = "NonParsable";
26508let mayStore = 1;
26509let DecoderNamespace = "SUBINSN_S2";
26510}
26511def SS2_storewi1 : HInst<
26512(outs),
26513(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26514"memw($Rs16+#$Ii) = #1",
26515tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26516let Inst{12-8} = 0b10001;
26517let addrMode = BaseImmOffset;
26518let accessSize = WordAccess;
26519let AsmVariantName = "NonParsable";
26520let mayStore = 1;
26521let DecoderNamespace = "SUBINSN_S2";
26522}
26523def V6_MAP_equb : HInst<
26524(outs HvxQR:$Qd4),
26525(ins HvxVR:$Vu32, HvxVR:$Vv32),
26526"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
26527PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26528let hasNewValue = 1;
26529let opNewValue = 0;
26530let isCVI = 1;
26531let isPseudo = 1;
26532let isCodeGenOnly = 1;
26533let DecoderNamespace = "EXT_mmvec";
26534}
26535def V6_MAP_equb_and : HInst<
26536(outs HvxQR:$Qx4),
26537(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26538"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
26539PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26540let isCVI = 1;
26541let isPseudo = 1;
26542let isCodeGenOnly = 1;
26543let DecoderNamespace = "EXT_mmvec";
26544let Constraints = "$Qx4 = $Qx4in";
26545}
26546def V6_MAP_equb_ior : HInst<
26547(outs HvxQR:$Qx4),
26548(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26549"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
26550PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26551let isAccumulator = 1;
26552let isCVI = 1;
26553let isPseudo = 1;
26554let isCodeGenOnly = 1;
26555let DecoderNamespace = "EXT_mmvec";
26556let Constraints = "$Qx4 = $Qx4in";
26557}
26558def V6_MAP_equb_xor : HInst<
26559(outs HvxQR:$Qx4),
26560(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26561"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
26562PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26563let isCVI = 1;
26564let isPseudo = 1;
26565let isCodeGenOnly = 1;
26566let DecoderNamespace = "EXT_mmvec";
26567let Constraints = "$Qx4 = $Qx4in";
26568}
26569def V6_MAP_equh : HInst<
26570(outs HvxQR:$Qd4),
26571(ins HvxVR:$Vu32, HvxVR:$Vv32),
26572"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
26573PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26574let hasNewValue = 1;
26575let opNewValue = 0;
26576let isCVI = 1;
26577let isPseudo = 1;
26578let isCodeGenOnly = 1;
26579let DecoderNamespace = "EXT_mmvec";
26580}
26581def V6_MAP_equh_and : HInst<
26582(outs HvxQR:$Qx4),
26583(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26584"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
26585PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26586let isCVI = 1;
26587let isPseudo = 1;
26588let isCodeGenOnly = 1;
26589let DecoderNamespace = "EXT_mmvec";
26590let Constraints = "$Qx4 = $Qx4in";
26591}
26592def V6_MAP_equh_ior : HInst<
26593(outs HvxQR:$Qx4),
26594(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26595"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
26596PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26597let isAccumulator = 1;
26598let isCVI = 1;
26599let isPseudo = 1;
26600let isCodeGenOnly = 1;
26601let DecoderNamespace = "EXT_mmvec";
26602let Constraints = "$Qx4 = $Qx4in";
26603}
26604def V6_MAP_equh_xor : HInst<
26605(outs HvxQR:$Qx4),
26606(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26607"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
26608PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26609let isCVI = 1;
26610let isPseudo = 1;
26611let isCodeGenOnly = 1;
26612let DecoderNamespace = "EXT_mmvec";
26613let Constraints = "$Qx4 = $Qx4in";
26614}
26615def V6_MAP_equw : HInst<
26616(outs HvxQR:$Qd4),
26617(ins HvxVR:$Vu32, HvxVR:$Vv32),
26618"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
26619PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26620let hasNewValue = 1;
26621let opNewValue = 0;
26622let isCVI = 1;
26623let isPseudo = 1;
26624let isCodeGenOnly = 1;
26625let DecoderNamespace = "EXT_mmvec";
26626}
26627def V6_MAP_equw_and : HInst<
26628(outs HvxQR:$Qx4),
26629(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26630"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
26631PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26632let isCVI = 1;
26633let isPseudo = 1;
26634let isCodeGenOnly = 1;
26635let DecoderNamespace = "EXT_mmvec";
26636let Constraints = "$Qx4 = $Qx4in";
26637}
26638def V6_MAP_equw_ior : HInst<
26639(outs HvxQR:$Qx4),
26640(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26641"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
26642PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26643let isAccumulator = 1;
26644let isCVI = 1;
26645let isPseudo = 1;
26646let isCodeGenOnly = 1;
26647let DecoderNamespace = "EXT_mmvec";
26648let Constraints = "$Qx4 = $Qx4in";
26649}
26650def V6_MAP_equw_xor : HInst<
26651(outs HvxQR:$Qx4),
26652(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26653"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
26654PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26655let isCVI = 1;
26656let isPseudo = 1;
26657let isCodeGenOnly = 1;
26658let DecoderNamespace = "EXT_mmvec";
26659let Constraints = "$Qx4 = $Qx4in";
26660}
26661def V6_extractw : HInst<
26662(outs IntRegs:$Rd32),
26663(ins HvxVR:$Vu32, IntRegs:$Rs32),
26664"$Rd32 = vextract($Vu32,$Rs32)",
26665tc_540c3da3, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
26666let Inst{7-5} = 0b001;
26667let Inst{13-13} = 0b0;
26668let Inst{31-21} = 0b10010010000;
26669let hasNewValue = 1;
26670let opNewValue = 0;
26671let isCVI = 1;
26672let isSolo = 1;
26673let mayLoad = 1;
26674let DecoderNamespace = "EXT_mmvec";
26675}
26676def V6_extractw_alt : HInst<
26677(outs IntRegs:$Rd32),
26678(ins HvxVR:$Vu32, IntRegs:$Rs32),
26679"$Rd32.w = vextract($Vu32,$Rs32)",
26680PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26681let hasNewValue = 1;
26682let opNewValue = 0;
26683let isCVI = 1;
26684let isPseudo = 1;
26685let isCodeGenOnly = 1;
26686let DecoderNamespace = "EXT_mmvec";
26687}
26688def V6_hi : HInst<
26689(outs HvxVR:$Vd32),
26690(ins HvxWR:$Vss32),
26691"$Vd32 = hi($Vss32)",
26692CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26693let hasNewValue = 1;
26694let opNewValue = 0;
26695let isCVI = 1;
26696let isPseudo = 1;
26697let DecoderNamespace = "EXT_mmvec";
26698}
26699def V6_ld0 : HInst<
26700(outs HvxVR:$Vd32),
26701(ins IntRegs:$Rt32),
26702"$Vd32 = vmem($Rt32)",
26703PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26704let hasNewValue = 1;
26705let opNewValue = 0;
26706let isCVI = 1;
26707let isPseudo = 1;
26708let isCodeGenOnly = 1;
26709let DecoderNamespace = "EXT_mmvec";
26710}
26711def V6_ldcnp0 : HInst<
26712(outs HvxVR:$Vd32),
26713(ins PredRegs:$Pv4, IntRegs:$Rt32),
26714"if (!$Pv4) $Vd32.cur = vmem($Rt32)",
26715PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26716let hasNewValue = 1;
26717let opNewValue = 0;
26718let isCVI = 1;
26719let isPseudo = 1;
26720let isCodeGenOnly = 1;
26721let DecoderNamespace = "EXT_mmvec";
26722}
26723def V6_ldcnpnt0 : HInst<
26724(outs HvxVR:$Vd32),
26725(ins PredRegs:$Pv4, IntRegs:$Rt32),
26726"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
26727PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26728let hasNewValue = 1;
26729let opNewValue = 0;
26730let isCVI = 1;
26731let isPseudo = 1;
26732let isCodeGenOnly = 1;
26733let DecoderNamespace = "EXT_mmvec";
26734}
26735def V6_ldcp0 : HInst<
26736(outs HvxVR:$Vd32),
26737(ins PredRegs:$Pv4, IntRegs:$Rt32),
26738"if ($Pv4) $Vd32.cur = vmem($Rt32)",
26739PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26740let hasNewValue = 1;
26741let opNewValue = 0;
26742let isCVI = 1;
26743let isPseudo = 1;
26744let isCodeGenOnly = 1;
26745let DecoderNamespace = "EXT_mmvec";
26746}
26747def V6_ldcpnt0 : HInst<
26748(outs HvxVR:$Vd32),
26749(ins PredRegs:$Pv4, IntRegs:$Rt32),
26750"if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
26751PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26752let hasNewValue = 1;
26753let opNewValue = 0;
26754let isCVI = 1;
26755let isPseudo = 1;
26756let isCodeGenOnly = 1;
26757let DecoderNamespace = "EXT_mmvec";
26758}
26759def V6_ldnp0 : HInst<
26760(outs HvxVR:$Vd32),
26761(ins PredRegs:$Pv4, IntRegs:$Rt32),
26762"if (!$Pv4) $Vd32 = vmem($Rt32)",
26763PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26764let hasNewValue = 1;
26765let opNewValue = 0;
26766let isCVI = 1;
26767let isPseudo = 1;
26768let isCodeGenOnly = 1;
26769let DecoderNamespace = "EXT_mmvec";
26770}
26771def V6_ldnpnt0 : HInst<
26772(outs HvxVR:$Vd32),
26773(ins PredRegs:$Pv4, IntRegs:$Rt32),
26774"if (!$Pv4) $Vd32 = vmem($Rt32):nt",
26775PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26776let hasNewValue = 1;
26777let opNewValue = 0;
26778let isCVI = 1;
26779let isPseudo = 1;
26780let isCodeGenOnly = 1;
26781let DecoderNamespace = "EXT_mmvec";
26782}
26783def V6_ldnt0 : HInst<
26784(outs HvxVR:$Vd32),
26785(ins IntRegs:$Rt32),
26786"$Vd32 = vmem($Rt32):nt",
26787PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26788let hasNewValue = 1;
26789let opNewValue = 0;
26790let isCVI = 1;
26791let isPseudo = 1;
26792let isCodeGenOnly = 1;
26793let DecoderNamespace = "EXT_mmvec";
26794}
26795def V6_ldntnt0 : HInst<
26796(outs HvxVR:$Vd32),
26797(ins IntRegs:$Rt32),
26798"$Vd32 = vmem($Rt32):nt",
26799PSEUDO, TypeMAPPING>, Requires<[HasV62]> {
26800let hasNewValue = 1;
26801let opNewValue = 0;
26802let isPseudo = 1;
26803let isCodeGenOnly = 1;
26804let DecoderNamespace = "EXT_mmvec";
26805}
26806def V6_ldp0 : HInst<
26807(outs HvxVR:$Vd32),
26808(ins PredRegs:$Pv4, IntRegs:$Rt32),
26809"if ($Pv4) $Vd32 = vmem($Rt32)",
26810PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26811let hasNewValue = 1;
26812let opNewValue = 0;
26813let isCVI = 1;
26814let isPseudo = 1;
26815let isCodeGenOnly = 1;
26816let DecoderNamespace = "EXT_mmvec";
26817}
26818def V6_ldpnt0 : HInst<
26819(outs HvxVR:$Vd32),
26820(ins PredRegs:$Pv4, IntRegs:$Rt32),
26821"if ($Pv4) $Vd32 = vmem($Rt32):nt",
26822PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26823let hasNewValue = 1;
26824let opNewValue = 0;
26825let isCVI = 1;
26826let isPseudo = 1;
26827let isCodeGenOnly = 1;
26828let DecoderNamespace = "EXT_mmvec";
26829}
26830def V6_ldtnp0 : HInst<
26831(outs HvxVR:$Vd32),
26832(ins PredRegs:$Pv4, IntRegs:$Rt32),
26833"if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
26834PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26835let hasNewValue = 1;
26836let opNewValue = 0;
26837let isCVI = 1;
26838let isPseudo = 1;
26839let isCodeGenOnly = 1;
26840let DecoderNamespace = "EXT_mmvec";
26841}
26842def V6_ldtnpnt0 : HInst<
26843(outs HvxVR:$Vd32),
26844(ins PredRegs:$Pv4, IntRegs:$Rt32),
26845"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
26846PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26847let hasNewValue = 1;
26848let opNewValue = 0;
26849let isCVI = 1;
26850let isPseudo = 1;
26851let isCodeGenOnly = 1;
26852let DecoderNamespace = "EXT_mmvec";
26853}
26854def V6_ldtp0 : HInst<
26855(outs HvxVR:$Vd32),
26856(ins PredRegs:$Pv4, IntRegs:$Rt32),
26857"if ($Pv4) $Vd32.tmp = vmem($Rt32)",
26858PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26859let hasNewValue = 1;
26860let opNewValue = 0;
26861let isCVI = 1;
26862let isPseudo = 1;
26863let isCodeGenOnly = 1;
26864let DecoderNamespace = "EXT_mmvec";
26865}
26866def V6_ldtpnt0 : HInst<
26867(outs HvxVR:$Vd32),
26868(ins PredRegs:$Pv4, IntRegs:$Rt32),
26869"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
26870PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26871let hasNewValue = 1;
26872let opNewValue = 0;
26873let isCVI = 1;
26874let isPseudo = 1;
26875let isCodeGenOnly = 1;
26876let DecoderNamespace = "EXT_mmvec";
26877}
26878def V6_ldu0 : HInst<
26879(outs HvxVR:$Vd32),
26880(ins IntRegs:$Rt32),
26881"$Vd32 = vmemu($Rt32)",
26882PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26883let hasNewValue = 1;
26884let opNewValue = 0;
26885let isCVI = 1;
26886let isPseudo = 1;
26887let isCodeGenOnly = 1;
26888let DecoderNamespace = "EXT_mmvec";
26889}
26890def V6_lo : HInst<
26891(outs HvxVR:$Vd32),
26892(ins HvxWR:$Vss32),
26893"$Vd32 = lo($Vss32)",
26894CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26895let hasNewValue = 1;
26896let opNewValue = 0;
26897let isCVI = 1;
26898let isPseudo = 1;
26899let DecoderNamespace = "EXT_mmvec";
26900}
26901def V6_lvsplatb : HInst<
26902(outs HvxVR:$Vd32),
26903(ins IntRegs:$Rt32),
26904"$Vd32.b = vsplat($Rt32)",
26905tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26906let Inst{13-5} = 0b000000010;
26907let Inst{31-21} = 0b00011001110;
26908let hasNewValue = 1;
26909let opNewValue = 0;
26910let isCVI = 1;
26911let DecoderNamespace = "EXT_mmvec";
26912}
26913def V6_lvsplath : HInst<
26914(outs HvxVR:$Vd32),
26915(ins IntRegs:$Rt32),
26916"$Vd32.h = vsplat($Rt32)",
26917tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26918let Inst{13-5} = 0b000000001;
26919let Inst{31-21} = 0b00011001110;
26920let hasNewValue = 1;
26921let opNewValue = 0;
26922let isCVI = 1;
26923let DecoderNamespace = "EXT_mmvec";
26924}
26925def V6_lvsplatw : HInst<
26926(outs HvxVR:$Vd32),
26927(ins IntRegs:$Rt32),
26928"$Vd32 = vsplat($Rt32)",
26929tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
26930let Inst{13-5} = 0b000000001;
26931let Inst{31-21} = 0b00011001101;
26932let hasNewValue = 1;
26933let opNewValue = 0;
26934let isCVI = 1;
26935let DecoderNamespace = "EXT_mmvec";
26936}
26937def V6_pred_and : HInst<
26938(outs HvxQR:$Qd4),
26939(ins HvxQR:$Qs4, HvxQR:$Qt4),
26940"$Qd4 = and($Qs4,$Qt4)",
26941tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26942let Inst{7-2} = 0b000000;
26943let Inst{13-10} = 0b0000;
26944let Inst{21-16} = 0b000011;
26945let Inst{31-24} = 0b00011110;
26946let hasNewValue = 1;
26947let opNewValue = 0;
26948let isCVI = 1;
26949let DecoderNamespace = "EXT_mmvec";
26950}
26951def V6_pred_and_n : HInst<
26952(outs HvxQR:$Qd4),
26953(ins HvxQR:$Qs4, HvxQR:$Qt4),
26954"$Qd4 = and($Qs4,!$Qt4)",
26955tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26956let Inst{7-2} = 0b000101;
26957let Inst{13-10} = 0b0000;
26958let Inst{21-16} = 0b000011;
26959let Inst{31-24} = 0b00011110;
26960let hasNewValue = 1;
26961let opNewValue = 0;
26962let isCVI = 1;
26963let DecoderNamespace = "EXT_mmvec";
26964}
26965def V6_pred_not : HInst<
26966(outs HvxQR:$Qd4),
26967(ins HvxQR:$Qs4),
26968"$Qd4 = not($Qs4)",
26969tc_0ec46cf9, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
26970let Inst{7-2} = 0b000010;
26971let Inst{13-10} = 0b0000;
26972let Inst{31-16} = 0b0001111000000011;
26973let hasNewValue = 1;
26974let opNewValue = 0;
26975let isCVI = 1;
26976let DecoderNamespace = "EXT_mmvec";
26977}
26978def V6_pred_or : HInst<
26979(outs HvxQR:$Qd4),
26980(ins HvxQR:$Qs4, HvxQR:$Qt4),
26981"$Qd4 = or($Qs4,$Qt4)",
26982tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26983let Inst{7-2} = 0b000001;
26984let Inst{13-10} = 0b0000;
26985let Inst{21-16} = 0b000011;
26986let Inst{31-24} = 0b00011110;
26987let hasNewValue = 1;
26988let opNewValue = 0;
26989let isCVI = 1;
26990let DecoderNamespace = "EXT_mmvec";
26991}
26992def V6_pred_or_n : HInst<
26993(outs HvxQR:$Qd4),
26994(ins HvxQR:$Qs4, HvxQR:$Qt4),
26995"$Qd4 = or($Qs4,!$Qt4)",
26996tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26997let Inst{7-2} = 0b000100;
26998let Inst{13-10} = 0b0000;
26999let Inst{21-16} = 0b000011;
27000let Inst{31-24} = 0b00011110;
27001let hasNewValue = 1;
27002let opNewValue = 0;
27003let isCVI = 1;
27004let DecoderNamespace = "EXT_mmvec";
27005}
27006def V6_pred_scalar2 : HInst<
27007(outs HvxQR:$Qd4),
27008(ins IntRegs:$Rt32),
27009"$Qd4 = vsetq($Rt32)",
27010tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
27011let Inst{13-2} = 0b000000010001;
27012let Inst{31-21} = 0b00011001101;
27013let hasNewValue = 1;
27014let opNewValue = 0;
27015let isCVI = 1;
27016let DecoderNamespace = "EXT_mmvec";
27017}
27018def V6_pred_scalar2v2 : HInst<
27019(outs HvxQR:$Qd4),
27020(ins IntRegs:$Rt32),
27021"$Qd4 = vsetq2($Rt32)",
27022tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
27023let Inst{13-2} = 0b000000010011;
27024let Inst{31-21} = 0b00011001101;
27025let hasNewValue = 1;
27026let opNewValue = 0;
27027let isCVI = 1;
27028let DecoderNamespace = "EXT_mmvec";
27029}
27030def V6_pred_xor : HInst<
27031(outs HvxQR:$Qd4),
27032(ins HvxQR:$Qs4, HvxQR:$Qt4),
27033"$Qd4 = xor($Qs4,$Qt4)",
27034tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27035let Inst{7-2} = 0b000011;
27036let Inst{13-10} = 0b0000;
27037let Inst{21-16} = 0b000011;
27038let Inst{31-24} = 0b00011110;
27039let hasNewValue = 1;
27040let opNewValue = 0;
27041let isCVI = 1;
27042let DecoderNamespace = "EXT_mmvec";
27043}
27044def V6_shuffeqh : HInst<
27045(outs HvxQR:$Qd4),
27046(ins HvxQR:$Qs4, HvxQR:$Qt4),
27047"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
27048tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27049let Inst{7-2} = 0b000110;
27050let Inst{13-10} = 0b0000;
27051let Inst{21-16} = 0b000011;
27052let Inst{31-24} = 0b00011110;
27053let hasNewValue = 1;
27054let opNewValue = 0;
27055let isCVI = 1;
27056let DecoderNamespace = "EXT_mmvec";
27057}
27058def V6_shuffeqw : HInst<
27059(outs HvxQR:$Qd4),
27060(ins HvxQR:$Qs4, HvxQR:$Qt4),
27061"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
27062tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27063let Inst{7-2} = 0b000111;
27064let Inst{13-10} = 0b0000;
27065let Inst{21-16} = 0b000011;
27066let Inst{31-24} = 0b00011110;
27067let hasNewValue = 1;
27068let opNewValue = 0;
27069let isCVI = 1;
27070let DecoderNamespace = "EXT_mmvec";
27071}
27072def V6_st0 : HInst<
27073(outs),
27074(ins IntRegs:$Rt32, HvxVR:$Vs32),
27075"vmem($Rt32) = $Vs32",
27076PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27077let isCVI = 1;
27078let isPseudo = 1;
27079let isCodeGenOnly = 1;
27080let DecoderNamespace = "EXT_mmvec";
27081}
27082def V6_stn0 : HInst<
27083(outs),
27084(ins IntRegs:$Rt32, HvxVR:$Os8),
27085"vmem($Rt32) = $Os8.new",
27086PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27087let isCVI = 1;
27088let isPseudo = 1;
27089let isCodeGenOnly = 1;
27090let DecoderNamespace = "EXT_mmvec";
27091let opNewValue = 1;
27092}
27093def V6_stnnt0 : HInst<
27094(outs),
27095(ins IntRegs:$Rt32, HvxVR:$Os8),
27096"vmem($Rt32):nt = $Os8.new",
27097PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27098let isCVI = 1;
27099let isPseudo = 1;
27100let isCodeGenOnly = 1;
27101let DecoderNamespace = "EXT_mmvec";
27102let opNewValue = 1;
27103}
27104def V6_stnp0 : HInst<
27105(outs),
27106(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27107"if (!$Pv4) vmem($Rt32) = $Vs32",
27108PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27109let isCVI = 1;
27110let isPseudo = 1;
27111let isCodeGenOnly = 1;
27112let DecoderNamespace = "EXT_mmvec";
27113}
27114def V6_stnpnt0 : HInst<
27115(outs),
27116(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27117"if (!$Pv4) vmem($Rt32):nt = $Vs32",
27118PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27119let isCVI = 1;
27120let isPseudo = 1;
27121let isCodeGenOnly = 1;
27122let DecoderNamespace = "EXT_mmvec";
27123}
27124def V6_stnq0 : HInst<
27125(outs),
27126(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27127"if (!$Qv4) vmem($Rt32) = $Vs32",
27128PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27129let isCVI = 1;
27130let isPseudo = 1;
27131let isCodeGenOnly = 1;
27132let DecoderNamespace = "EXT_mmvec";
27133}
27134def V6_stnqnt0 : HInst<
27135(outs),
27136(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27137"if (!$Qv4) vmem($Rt32):nt = $Vs32",
27138PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27139let isCVI = 1;
27140let isPseudo = 1;
27141let isCodeGenOnly = 1;
27142let DecoderNamespace = "EXT_mmvec";
27143}
27144def V6_stnt0 : HInst<
27145(outs),
27146(ins IntRegs:$Rt32, HvxVR:$Vs32),
27147"vmem($Rt32):nt = $Vs32",
27148PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27149let isCVI = 1;
27150let isPseudo = 1;
27151let isCodeGenOnly = 1;
27152let DecoderNamespace = "EXT_mmvec";
27153}
27154def V6_stp0 : HInst<
27155(outs),
27156(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27157"if ($Pv4) vmem($Rt32) = $Vs32",
27158PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27159let isCVI = 1;
27160let isPseudo = 1;
27161let isCodeGenOnly = 1;
27162let DecoderNamespace = "EXT_mmvec";
27163}
27164def V6_stpnt0 : HInst<
27165(outs),
27166(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27167"if ($Pv4) vmem($Rt32):nt = $Vs32",
27168PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27169let isCVI = 1;
27170let isPseudo = 1;
27171let isCodeGenOnly = 1;
27172let DecoderNamespace = "EXT_mmvec";
27173}
27174def V6_stq0 : HInst<
27175(outs),
27176(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27177"if ($Qv4) vmem($Rt32) = $Vs32",
27178PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27179let isCVI = 1;
27180let isPseudo = 1;
27181let isCodeGenOnly = 1;
27182let DecoderNamespace = "EXT_mmvec";
27183}
27184def V6_stqnt0 : HInst<
27185(outs),
27186(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27187"if ($Qv4) vmem($Rt32):nt = $Vs32",
27188PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27189let isCVI = 1;
27190let isPseudo = 1;
27191let isCodeGenOnly = 1;
27192let DecoderNamespace = "EXT_mmvec";
27193}
27194def V6_stu0 : HInst<
27195(outs),
27196(ins IntRegs:$Rt32, HvxVR:$Vs32),
27197"vmemu($Rt32) = $Vs32",
27198PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27199let isCVI = 1;
27200let isPseudo = 1;
27201let isCodeGenOnly = 1;
27202let DecoderNamespace = "EXT_mmvec";
27203}
27204def V6_stunp0 : HInst<
27205(outs),
27206(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27207"if (!$Pv4) vmemu($Rt32) = $Vs32",
27208PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27209let isCVI = 1;
27210let isPseudo = 1;
27211let isCodeGenOnly = 1;
27212let DecoderNamespace = "EXT_mmvec";
27213}
27214def V6_stup0 : HInst<
27215(outs),
27216(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27217"if ($Pv4) vmemu($Rt32) = $Vs32",
27218PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27219let isCVI = 1;
27220let isPseudo = 1;
27221let isCodeGenOnly = 1;
27222let DecoderNamespace = "EXT_mmvec";
27223}
27224def V6_vL32Ub_ai : HInst<
27225(outs HvxVR:$Vd32),
27226(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27227"$Vd32 = vmemu($Rt32+#$Ii)",
27228tc_a7e6707d, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> {
27229let Inst{7-5} = 0b111;
27230let Inst{12-11} = 0b00;
27231let Inst{31-21} = 0b00101000000;
27232let hasNewValue = 1;
27233let opNewValue = 0;
27234let addrMode = BaseImmOffset;
27235let accessSize = HVXVectorAccess;
27236let isCVLoad = 1;
27237let isCVI = 1;
27238let mayLoad = 1;
27239let isRestrictNoSlot1Store = 1;
27240let DecoderNamespace = "EXT_mmvec";
27241}
27242def V6_vL32Ub_pi : HInst<
27243(outs HvxVR:$Vd32, IntRegs:$Rx32),
27244(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27245"$Vd32 = vmemu($Rx32++#$Ii)",
27246tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> {
27247let Inst{7-5} = 0b111;
27248let Inst{13-11} = 0b000;
27249let Inst{31-21} = 0b00101001000;
27250let hasNewValue = 1;
27251let opNewValue = 0;
27252let addrMode = PostInc;
27253let accessSize = HVXVectorAccess;
27254let isCVLoad = 1;
27255let isCVI = 1;
27256let mayLoad = 1;
27257let isRestrictNoSlot1Store = 1;
27258let BaseOpcode = "V6_vL32b_pi";
27259let DecoderNamespace = "EXT_mmvec";
27260let Constraints = "$Rx32 = $Rx32in";
27261}
27262def V6_vL32Ub_ppu : HInst<
27263(outs HvxVR:$Vd32, IntRegs:$Rx32),
27264(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27265"$Vd32 = vmemu($Rx32++$Mu2)",
27266tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
27267let Inst{12-5} = 0b00000111;
27268let Inst{31-21} = 0b00101011000;
27269let hasNewValue = 1;
27270let opNewValue = 0;
27271let addrMode = PostInc;
27272let accessSize = HVXVectorAccess;
27273let isCVLoad = 1;
27274let isCVI = 1;
27275let mayLoad = 1;
27276let isRestrictNoSlot1Store = 1;
27277let DecoderNamespace = "EXT_mmvec";
27278let Constraints = "$Rx32 = $Rx32in";
27279}
27280def V6_vL32b_ai : HInst<
27281(outs HvxVR:$Vd32),
27282(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27283"$Vd32 = vmem($Rt32+#$Ii)",
27284tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27285let Inst{7-5} = 0b000;
27286let Inst{12-11} = 0b00;
27287let Inst{31-21} = 0b00101000000;
27288let hasNewValue = 1;
27289let opNewValue = 0;
27290let addrMode = BaseImmOffset;
27291let accessSize = HVXVectorAccess;
27292let isCVLoad = 1;
27293let isCVI = 1;
27294let mayLoad = 1;
27295let isRestrictNoSlot1Store = 1;
27296let BaseOpcode = "V6_vL32b_ai";
27297let isCVLoadable = 1;
27298let isPredicable = 1;
27299let DecoderNamespace = "EXT_mmvec";
27300}
27301def V6_vL32b_cur_ai : HInst<
27302(outs HvxVR:$Vd32),
27303(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27304"$Vd32.cur = vmem($Rt32+#$Ii)",
27305tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27306let Inst{7-5} = 0b001;
27307let Inst{12-11} = 0b00;
27308let Inst{31-21} = 0b00101000000;
27309let hasNewValue = 1;
27310let opNewValue = 0;
27311let addrMode = BaseImmOffset;
27312let accessSize = HVXVectorAccess;
27313let isCVLoad = 1;
27314let isCVI = 1;
27315let CVINew = 1;
27316let mayLoad = 1;
27317let isRestrictNoSlot1Store = 1;
27318let BaseOpcode = "V6_vL32b_cur_ai";
27319let isPredicable = 1;
27320let DecoderNamespace = "EXT_mmvec";
27321}
27322def V6_vL32b_cur_npred_ai : HInst<
27323(outs HvxVR:$Vd32),
27324(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27325"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27326tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27327let Inst{7-5} = 0b101;
27328let Inst{31-21} = 0b00101000100;
27329let isPredicated = 1;
27330let isPredicatedFalse = 1;
27331let hasNewValue = 1;
27332let opNewValue = 0;
27333let addrMode = BaseImmOffset;
27334let accessSize = HVXVectorAccess;
27335let isCVLoad = 1;
27336let isCVI = 1;
27337let CVINew = 1;
27338let mayLoad = 1;
27339let isRestrictNoSlot1Store = 1;
27340let BaseOpcode = "V6_vL32b_cur_ai";
27341let DecoderNamespace = "EXT_mmvec";
27342}
27343def V6_vL32b_cur_npred_pi : HInst<
27344(outs HvxVR:$Vd32, IntRegs:$Rx32),
27345(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27346"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27347tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27348let Inst{7-5} = 0b101;
27349let Inst{13-13} = 0b0;
27350let Inst{31-21} = 0b00101001100;
27351let isPredicated = 1;
27352let isPredicatedFalse = 1;
27353let hasNewValue = 1;
27354let opNewValue = 0;
27355let addrMode = PostInc;
27356let accessSize = HVXVectorAccess;
27357let isCVLoad = 1;
27358let isCVI = 1;
27359let CVINew = 1;
27360let mayLoad = 1;
27361let isRestrictNoSlot1Store = 1;
27362let BaseOpcode = "V6_vL32b_cur_pi";
27363let DecoderNamespace = "EXT_mmvec";
27364let Constraints = "$Rx32 = $Rx32in";
27365}
27366def V6_vL32b_cur_npred_ppu : HInst<
27367(outs HvxVR:$Vd32, IntRegs:$Rx32),
27368(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27369"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27370tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27371let Inst{10-5} = 0b000101;
27372let Inst{31-21} = 0b00101011100;
27373let isPredicated = 1;
27374let isPredicatedFalse = 1;
27375let hasNewValue = 1;
27376let opNewValue = 0;
27377let addrMode = PostInc;
27378let accessSize = HVXVectorAccess;
27379let isCVLoad = 1;
27380let isCVI = 1;
27381let CVINew = 1;
27382let mayLoad = 1;
27383let isRestrictNoSlot1Store = 1;
27384let BaseOpcode = "V6_vL32b_cur_ppu";
27385let DecoderNamespace = "EXT_mmvec";
27386let Constraints = "$Rx32 = $Rx32in";
27387}
27388def V6_vL32b_cur_pi : HInst<
27389(outs HvxVR:$Vd32, IntRegs:$Rx32),
27390(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27391"$Vd32.cur = vmem($Rx32++#$Ii)",
27392tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27393let Inst{7-5} = 0b001;
27394let Inst{13-11} = 0b000;
27395let Inst{31-21} = 0b00101001000;
27396let hasNewValue = 1;
27397let opNewValue = 0;
27398let addrMode = PostInc;
27399let accessSize = HVXVectorAccess;
27400let isCVLoad = 1;
27401let isCVI = 1;
27402let CVINew = 1;
27403let mayLoad = 1;
27404let isRestrictNoSlot1Store = 1;
27405let BaseOpcode = "V6_vL32b_cur_pi";
27406let isPredicable = 1;
27407let DecoderNamespace = "EXT_mmvec";
27408let Constraints = "$Rx32 = $Rx32in";
27409}
27410def V6_vL32b_cur_ppu : HInst<
27411(outs HvxVR:$Vd32, IntRegs:$Rx32),
27412(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27413"$Vd32.cur = vmem($Rx32++$Mu2)",
27414tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27415let Inst{12-5} = 0b00000001;
27416let Inst{31-21} = 0b00101011000;
27417let hasNewValue = 1;
27418let opNewValue = 0;
27419let addrMode = PostInc;
27420let accessSize = HVXVectorAccess;
27421let isCVLoad = 1;
27422let isCVI = 1;
27423let CVINew = 1;
27424let mayLoad = 1;
27425let isRestrictNoSlot1Store = 1;
27426let BaseOpcode = "V6_vL32b_cur_ppu";
27427let isPredicable = 1;
27428let DecoderNamespace = "EXT_mmvec";
27429let Constraints = "$Rx32 = $Rx32in";
27430}
27431def V6_vL32b_cur_pred_ai : HInst<
27432(outs HvxVR:$Vd32),
27433(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27434"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27435tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27436let Inst{7-5} = 0b100;
27437let Inst{31-21} = 0b00101000100;
27438let isPredicated = 1;
27439let hasNewValue = 1;
27440let opNewValue = 0;
27441let addrMode = BaseImmOffset;
27442let accessSize = HVXVectorAccess;
27443let isCVLoad = 1;
27444let isCVI = 1;
27445let CVINew = 1;
27446let mayLoad = 1;
27447let isRestrictNoSlot1Store = 1;
27448let BaseOpcode = "V6_vL32b_cur_ai";
27449let DecoderNamespace = "EXT_mmvec";
27450}
27451def V6_vL32b_cur_pred_pi : HInst<
27452(outs HvxVR:$Vd32, IntRegs:$Rx32),
27453(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27454"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27455tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27456let Inst{7-5} = 0b100;
27457let Inst{13-13} = 0b0;
27458let Inst{31-21} = 0b00101001100;
27459let isPredicated = 1;
27460let hasNewValue = 1;
27461let opNewValue = 0;
27462let addrMode = PostInc;
27463let accessSize = HVXVectorAccess;
27464let isCVLoad = 1;
27465let isCVI = 1;
27466let CVINew = 1;
27467let mayLoad = 1;
27468let isRestrictNoSlot1Store = 1;
27469let BaseOpcode = "V6_vL32b_cur_pi";
27470let DecoderNamespace = "EXT_mmvec";
27471let Constraints = "$Rx32 = $Rx32in";
27472}
27473def V6_vL32b_cur_pred_ppu : HInst<
27474(outs HvxVR:$Vd32, IntRegs:$Rx32),
27475(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27476"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27477tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27478let Inst{10-5} = 0b000100;
27479let Inst{31-21} = 0b00101011100;
27480let isPredicated = 1;
27481let hasNewValue = 1;
27482let opNewValue = 0;
27483let addrMode = PostInc;
27484let accessSize = HVXVectorAccess;
27485let isCVLoad = 1;
27486let isCVI = 1;
27487let CVINew = 1;
27488let mayLoad = 1;
27489let isRestrictNoSlot1Store = 1;
27490let BaseOpcode = "V6_vL32b_cur_ppu";
27491let DecoderNamespace = "EXT_mmvec";
27492let Constraints = "$Rx32 = $Rx32in";
27493}
27494def V6_vL32b_npred_ai : HInst<
27495(outs HvxVR:$Vd32),
27496(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27497"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27498tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27499let Inst{7-5} = 0b011;
27500let Inst{31-21} = 0b00101000100;
27501let isPredicated = 1;
27502let isPredicatedFalse = 1;
27503let hasNewValue = 1;
27504let opNewValue = 0;
27505let addrMode = BaseImmOffset;
27506let accessSize = HVXVectorAccess;
27507let isCVLoad = 1;
27508let isCVI = 1;
27509let mayLoad = 1;
27510let isRestrictNoSlot1Store = 1;
27511let BaseOpcode = "V6_vL32b_ai";
27512let DecoderNamespace = "EXT_mmvec";
27513}
27514def V6_vL32b_npred_pi : HInst<
27515(outs HvxVR:$Vd32, IntRegs:$Rx32),
27516(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27517"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27518tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27519let Inst{7-5} = 0b011;
27520let Inst{13-13} = 0b0;
27521let Inst{31-21} = 0b00101001100;
27522let isPredicated = 1;
27523let isPredicatedFalse = 1;
27524let hasNewValue = 1;
27525let opNewValue = 0;
27526let addrMode = PostInc;
27527let accessSize = HVXVectorAccess;
27528let isCVLoad = 1;
27529let isCVI = 1;
27530let mayLoad = 1;
27531let isRestrictNoSlot1Store = 1;
27532let BaseOpcode = "V6_vL32b_pi";
27533let DecoderNamespace = "EXT_mmvec";
27534let Constraints = "$Rx32 = $Rx32in";
27535}
27536def V6_vL32b_npred_ppu : HInst<
27537(outs HvxVR:$Vd32, IntRegs:$Rx32),
27538(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27539"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27540tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27541let Inst{10-5} = 0b000011;
27542let Inst{31-21} = 0b00101011100;
27543let isPredicated = 1;
27544let isPredicatedFalse = 1;
27545let hasNewValue = 1;
27546let opNewValue = 0;
27547let addrMode = PostInc;
27548let accessSize = HVXVectorAccess;
27549let isCVLoad = 1;
27550let isCVI = 1;
27551let mayLoad = 1;
27552let isRestrictNoSlot1Store = 1;
27553let BaseOpcode = "V6_vL32b_ppu";
27554let DecoderNamespace = "EXT_mmvec";
27555let Constraints = "$Rx32 = $Rx32in";
27556}
27557def V6_vL32b_nt_ai : HInst<
27558(outs HvxVR:$Vd32),
27559(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27560"$Vd32 = vmem($Rt32+#$Ii):nt",
27561tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27562let Inst{7-5} = 0b000;
27563let Inst{12-11} = 0b00;
27564let Inst{31-21} = 0b00101000010;
27565let hasNewValue = 1;
27566let opNewValue = 0;
27567let addrMode = BaseImmOffset;
27568let accessSize = HVXVectorAccess;
27569let isCVLoad = 1;
27570let isCVI = 1;
27571let mayLoad = 1;
27572let isNonTemporal = 1;
27573let isRestrictNoSlot1Store = 1;
27574let BaseOpcode = "V6_vL32b_nt_ai";
27575let isCVLoadable = 1;
27576let isPredicable = 1;
27577let DecoderNamespace = "EXT_mmvec";
27578}
27579def V6_vL32b_nt_cur_ai : HInst<
27580(outs HvxVR:$Vd32),
27581(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27582"$Vd32.cur = vmem($Rt32+#$Ii):nt",
27583tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27584let Inst{7-5} = 0b001;
27585let Inst{12-11} = 0b00;
27586let Inst{31-21} = 0b00101000010;
27587let hasNewValue = 1;
27588let opNewValue = 0;
27589let addrMode = BaseImmOffset;
27590let accessSize = HVXVectorAccess;
27591let isCVLoad = 1;
27592let isCVI = 1;
27593let CVINew = 1;
27594let mayLoad = 1;
27595let isNonTemporal = 1;
27596let isRestrictNoSlot1Store = 1;
27597let BaseOpcode = "V6_vL32b_nt_cur_ai";
27598let isPredicable = 1;
27599let DecoderNamespace = "EXT_mmvec";
27600}
27601def V6_vL32b_nt_cur_npred_ai : HInst<
27602(outs HvxVR:$Vd32),
27603(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27604"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27605tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27606let Inst{7-5} = 0b101;
27607let Inst{31-21} = 0b00101000110;
27608let isPredicated = 1;
27609let isPredicatedFalse = 1;
27610let hasNewValue = 1;
27611let opNewValue = 0;
27612let addrMode = BaseImmOffset;
27613let accessSize = HVXVectorAccess;
27614let isCVLoad = 1;
27615let isCVI = 1;
27616let CVINew = 1;
27617let mayLoad = 1;
27618let isNonTemporal = 1;
27619let isRestrictNoSlot1Store = 1;
27620let BaseOpcode = "V6_vL32b_nt_cur_ai";
27621let DecoderNamespace = "EXT_mmvec";
27622}
27623def V6_vL32b_nt_cur_npred_pi : HInst<
27624(outs HvxVR:$Vd32, IntRegs:$Rx32),
27625(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27626"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27627tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27628let Inst{7-5} = 0b101;
27629let Inst{13-13} = 0b0;
27630let Inst{31-21} = 0b00101001110;
27631let isPredicated = 1;
27632let isPredicatedFalse = 1;
27633let hasNewValue = 1;
27634let opNewValue = 0;
27635let addrMode = PostInc;
27636let accessSize = HVXVectorAccess;
27637let isCVLoad = 1;
27638let isCVI = 1;
27639let CVINew = 1;
27640let mayLoad = 1;
27641let isNonTemporal = 1;
27642let isRestrictNoSlot1Store = 1;
27643let BaseOpcode = "V6_vL32b_nt_cur_pi";
27644let DecoderNamespace = "EXT_mmvec";
27645let Constraints = "$Rx32 = $Rx32in";
27646}
27647def V6_vL32b_nt_cur_npred_ppu : HInst<
27648(outs HvxVR:$Vd32, IntRegs:$Rx32),
27649(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27650"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27651tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27652let Inst{10-5} = 0b000101;
27653let Inst{31-21} = 0b00101011110;
27654let isPredicated = 1;
27655let isPredicatedFalse = 1;
27656let hasNewValue = 1;
27657let opNewValue = 0;
27658let addrMode = PostInc;
27659let accessSize = HVXVectorAccess;
27660let isCVLoad = 1;
27661let isCVI = 1;
27662let CVINew = 1;
27663let mayLoad = 1;
27664let isNonTemporal = 1;
27665let isRestrictNoSlot1Store = 1;
27666let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27667let DecoderNamespace = "EXT_mmvec";
27668let Constraints = "$Rx32 = $Rx32in";
27669}
27670def V6_vL32b_nt_cur_pi : HInst<
27671(outs HvxVR:$Vd32, IntRegs:$Rx32),
27672(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27673"$Vd32.cur = vmem($Rx32++#$Ii):nt",
27674tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27675let Inst{7-5} = 0b001;
27676let Inst{13-11} = 0b000;
27677let Inst{31-21} = 0b00101001010;
27678let hasNewValue = 1;
27679let opNewValue = 0;
27680let addrMode = PostInc;
27681let accessSize = HVXVectorAccess;
27682let isCVLoad = 1;
27683let isCVI = 1;
27684let CVINew = 1;
27685let mayLoad = 1;
27686let isNonTemporal = 1;
27687let isRestrictNoSlot1Store = 1;
27688let BaseOpcode = "V6_vL32b_nt_cur_pi";
27689let isPredicable = 1;
27690let DecoderNamespace = "EXT_mmvec";
27691let Constraints = "$Rx32 = $Rx32in";
27692}
27693def V6_vL32b_nt_cur_ppu : HInst<
27694(outs HvxVR:$Vd32, IntRegs:$Rx32),
27695(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27696"$Vd32.cur = vmem($Rx32++$Mu2):nt",
27697tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27698let Inst{12-5} = 0b00000001;
27699let Inst{31-21} = 0b00101011010;
27700let hasNewValue = 1;
27701let opNewValue = 0;
27702let addrMode = PostInc;
27703let accessSize = HVXVectorAccess;
27704let isCVLoad = 1;
27705let isCVI = 1;
27706let CVINew = 1;
27707let mayLoad = 1;
27708let isNonTemporal = 1;
27709let isRestrictNoSlot1Store = 1;
27710let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27711let isPredicable = 1;
27712let DecoderNamespace = "EXT_mmvec";
27713let Constraints = "$Rx32 = $Rx32in";
27714}
27715def V6_vL32b_nt_cur_pred_ai : HInst<
27716(outs HvxVR:$Vd32),
27717(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27718"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27719tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27720let Inst{7-5} = 0b100;
27721let Inst{31-21} = 0b00101000110;
27722let isPredicated = 1;
27723let hasNewValue = 1;
27724let opNewValue = 0;
27725let addrMode = BaseImmOffset;
27726let accessSize = HVXVectorAccess;
27727let isCVLoad = 1;
27728let isCVI = 1;
27729let CVINew = 1;
27730let mayLoad = 1;
27731let isNonTemporal = 1;
27732let isRestrictNoSlot1Store = 1;
27733let BaseOpcode = "V6_vL32b_nt_cur_ai";
27734let DecoderNamespace = "EXT_mmvec";
27735}
27736def V6_vL32b_nt_cur_pred_pi : HInst<
27737(outs HvxVR:$Vd32, IntRegs:$Rx32),
27738(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27739"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27740tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27741let Inst{7-5} = 0b100;
27742let Inst{13-13} = 0b0;
27743let Inst{31-21} = 0b00101001110;
27744let isPredicated = 1;
27745let hasNewValue = 1;
27746let opNewValue = 0;
27747let addrMode = PostInc;
27748let accessSize = HVXVectorAccess;
27749let isCVLoad = 1;
27750let isCVI = 1;
27751let CVINew = 1;
27752let mayLoad = 1;
27753let isNonTemporal = 1;
27754let isRestrictNoSlot1Store = 1;
27755let BaseOpcode = "V6_vL32b_nt_cur_pi";
27756let DecoderNamespace = "EXT_mmvec";
27757let Constraints = "$Rx32 = $Rx32in";
27758}
27759def V6_vL32b_nt_cur_pred_ppu : HInst<
27760(outs HvxVR:$Vd32, IntRegs:$Rx32),
27761(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27762"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27763tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27764let Inst{10-5} = 0b000100;
27765let Inst{31-21} = 0b00101011110;
27766let isPredicated = 1;
27767let hasNewValue = 1;
27768let opNewValue = 0;
27769let addrMode = PostInc;
27770let accessSize = HVXVectorAccess;
27771let isCVLoad = 1;
27772let isCVI = 1;
27773let CVINew = 1;
27774let mayLoad = 1;
27775let isNonTemporal = 1;
27776let isRestrictNoSlot1Store = 1;
27777let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27778let DecoderNamespace = "EXT_mmvec";
27779let Constraints = "$Rx32 = $Rx32in";
27780}
27781def V6_vL32b_nt_npred_ai : HInst<
27782(outs HvxVR:$Vd32),
27783(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27784"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27785tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27786let Inst{7-5} = 0b011;
27787let Inst{31-21} = 0b00101000110;
27788let isPredicated = 1;
27789let isPredicatedFalse = 1;
27790let hasNewValue = 1;
27791let opNewValue = 0;
27792let addrMode = BaseImmOffset;
27793let accessSize = HVXVectorAccess;
27794let isCVLoad = 1;
27795let isCVI = 1;
27796let mayLoad = 1;
27797let isNonTemporal = 1;
27798let isRestrictNoSlot1Store = 1;
27799let BaseOpcode = "V6_vL32b_nt_ai";
27800let DecoderNamespace = "EXT_mmvec";
27801}
27802def V6_vL32b_nt_npred_pi : HInst<
27803(outs HvxVR:$Vd32, IntRegs:$Rx32),
27804(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27805"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27806tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27807let Inst{7-5} = 0b011;
27808let Inst{13-13} = 0b0;
27809let Inst{31-21} = 0b00101001110;
27810let isPredicated = 1;
27811let isPredicatedFalse = 1;
27812let hasNewValue = 1;
27813let opNewValue = 0;
27814let addrMode = PostInc;
27815let accessSize = HVXVectorAccess;
27816let isCVLoad = 1;
27817let isCVI = 1;
27818let mayLoad = 1;
27819let isNonTemporal = 1;
27820let isRestrictNoSlot1Store = 1;
27821let BaseOpcode = "V6_vL32b_nt_pi";
27822let DecoderNamespace = "EXT_mmvec";
27823let Constraints = "$Rx32 = $Rx32in";
27824}
27825def V6_vL32b_nt_npred_ppu : HInst<
27826(outs HvxVR:$Vd32, IntRegs:$Rx32),
27827(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27828"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
27829tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27830let Inst{10-5} = 0b000011;
27831let Inst{31-21} = 0b00101011110;
27832let isPredicated = 1;
27833let isPredicatedFalse = 1;
27834let hasNewValue = 1;
27835let opNewValue = 0;
27836let addrMode = PostInc;
27837let accessSize = HVXVectorAccess;
27838let isCVLoad = 1;
27839let isCVI = 1;
27840let mayLoad = 1;
27841let isNonTemporal = 1;
27842let isRestrictNoSlot1Store = 1;
27843let BaseOpcode = "V6_vL32b_nt_ppu";
27844let DecoderNamespace = "EXT_mmvec";
27845let Constraints = "$Rx32 = $Rx32in";
27846}
27847def V6_vL32b_nt_pi : HInst<
27848(outs HvxVR:$Vd32, IntRegs:$Rx32),
27849(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27850"$Vd32 = vmem($Rx32++#$Ii):nt",
27851tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27852let Inst{7-5} = 0b000;
27853let Inst{13-11} = 0b000;
27854let Inst{31-21} = 0b00101001010;
27855let hasNewValue = 1;
27856let opNewValue = 0;
27857let addrMode = PostInc;
27858let accessSize = HVXVectorAccess;
27859let isCVLoad = 1;
27860let isCVI = 1;
27861let mayLoad = 1;
27862let isNonTemporal = 1;
27863let isRestrictNoSlot1Store = 1;
27864let BaseOpcode = "V6_vL32b_nt_pi";
27865let isCVLoadable = 1;
27866let isPredicable = 1;
27867let DecoderNamespace = "EXT_mmvec";
27868let Constraints = "$Rx32 = $Rx32in";
27869}
27870def V6_vL32b_nt_ppu : HInst<
27871(outs HvxVR:$Vd32, IntRegs:$Rx32),
27872(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27873"$Vd32 = vmem($Rx32++$Mu2):nt",
27874tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27875let Inst{12-5} = 0b00000000;
27876let Inst{31-21} = 0b00101011010;
27877let hasNewValue = 1;
27878let opNewValue = 0;
27879let addrMode = PostInc;
27880let accessSize = HVXVectorAccess;
27881let isCVLoad = 1;
27882let isCVI = 1;
27883let mayLoad = 1;
27884let isNonTemporal = 1;
27885let isRestrictNoSlot1Store = 1;
27886let BaseOpcode = "V6_vL32b_nt_ppu";
27887let isCVLoadable = 1;
27888let isPredicable = 1;
27889let DecoderNamespace = "EXT_mmvec";
27890let Constraints = "$Rx32 = $Rx32in";
27891}
27892def V6_vL32b_nt_pred_ai : HInst<
27893(outs HvxVR:$Vd32),
27894(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27895"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27896tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27897let Inst{7-5} = 0b010;
27898let Inst{31-21} = 0b00101000110;
27899let isPredicated = 1;
27900let hasNewValue = 1;
27901let opNewValue = 0;
27902let addrMode = BaseImmOffset;
27903let accessSize = HVXVectorAccess;
27904let isCVLoad = 1;
27905let isCVI = 1;
27906let mayLoad = 1;
27907let isNonTemporal = 1;
27908let isRestrictNoSlot1Store = 1;
27909let BaseOpcode = "V6_vL32b_nt_ai";
27910let DecoderNamespace = "EXT_mmvec";
27911}
27912def V6_vL32b_nt_pred_pi : HInst<
27913(outs HvxVR:$Vd32, IntRegs:$Rx32),
27914(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27915"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27916tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27917let Inst{7-5} = 0b010;
27918let Inst{13-13} = 0b0;
27919let Inst{31-21} = 0b00101001110;
27920let isPredicated = 1;
27921let hasNewValue = 1;
27922let opNewValue = 0;
27923let addrMode = PostInc;
27924let accessSize = HVXVectorAccess;
27925let isCVLoad = 1;
27926let isCVI = 1;
27927let mayLoad = 1;
27928let isNonTemporal = 1;
27929let isRestrictNoSlot1Store = 1;
27930let BaseOpcode = "V6_vL32b_nt_pi";
27931let DecoderNamespace = "EXT_mmvec";
27932let Constraints = "$Rx32 = $Rx32in";
27933}
27934def V6_vL32b_nt_pred_ppu : HInst<
27935(outs HvxVR:$Vd32, IntRegs:$Rx32),
27936(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27937"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
27938tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27939let Inst{10-5} = 0b000010;
27940let Inst{31-21} = 0b00101011110;
27941let isPredicated = 1;
27942let hasNewValue = 1;
27943let opNewValue = 0;
27944let addrMode = PostInc;
27945let accessSize = HVXVectorAccess;
27946let isCVLoad = 1;
27947let isCVI = 1;
27948let mayLoad = 1;
27949let isNonTemporal = 1;
27950let isRestrictNoSlot1Store = 1;
27951let BaseOpcode = "V6_vL32b_nt_ppu";
27952let DecoderNamespace = "EXT_mmvec";
27953let Constraints = "$Rx32 = $Rx32in";
27954}
27955def V6_vL32b_nt_tmp_ai : HInst<
27956(outs HvxVR:$Vd32),
27957(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27958"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
27959tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27960let Inst{7-5} = 0b010;
27961let Inst{12-11} = 0b00;
27962let Inst{31-21} = 0b00101000010;
27963let hasNewValue = 1;
27964let opNewValue = 0;
27965let addrMode = BaseImmOffset;
27966let accessSize = HVXVectorAccess;
27967let isCVLoad = 1;
27968let isCVI = 1;
27969let mayLoad = 1;
27970let isNonTemporal = 1;
27971let isRestrictNoSlot1Store = 1;
27972let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27973let isPredicable = 1;
27974let DecoderNamespace = "EXT_mmvec";
27975}
27976def V6_vL32b_nt_tmp_npred_ai : HInst<
27977(outs HvxVR:$Vd32),
27978(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27979"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
27980tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27981let Inst{7-5} = 0b111;
27982let Inst{31-21} = 0b00101000110;
27983let isPredicated = 1;
27984let isPredicatedFalse = 1;
27985let hasNewValue = 1;
27986let opNewValue = 0;
27987let addrMode = BaseImmOffset;
27988let accessSize = HVXVectorAccess;
27989let isCVLoad = 1;
27990let isCVI = 1;
27991let mayLoad = 1;
27992let isNonTemporal = 1;
27993let isRestrictNoSlot1Store = 1;
27994let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27995let DecoderNamespace = "EXT_mmvec";
27996}
27997def V6_vL32b_nt_tmp_npred_pi : HInst<
27998(outs HvxVR:$Vd32, IntRegs:$Rx32),
27999(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28000"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28001tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28002let Inst{7-5} = 0b111;
28003let Inst{13-13} = 0b0;
28004let Inst{31-21} = 0b00101001110;
28005let isPredicated = 1;
28006let isPredicatedFalse = 1;
28007let hasNewValue = 1;
28008let opNewValue = 0;
28009let addrMode = PostInc;
28010let accessSize = HVXVectorAccess;
28011let isCVLoad = 1;
28012let isCVI = 1;
28013let mayLoad = 1;
28014let isNonTemporal = 1;
28015let isRestrictNoSlot1Store = 1;
28016let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28017let DecoderNamespace = "EXT_mmvec";
28018let Constraints = "$Rx32 = $Rx32in";
28019}
28020def V6_vL32b_nt_tmp_npred_ppu : HInst<
28021(outs HvxVR:$Vd32, IntRegs:$Rx32),
28022(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28023"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28024tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28025let Inst{10-5} = 0b000111;
28026let Inst{31-21} = 0b00101011110;
28027let isPredicated = 1;
28028let isPredicatedFalse = 1;
28029let hasNewValue = 1;
28030let opNewValue = 0;
28031let addrMode = PostInc;
28032let accessSize = HVXVectorAccess;
28033let isCVLoad = 1;
28034let isCVI = 1;
28035let mayLoad = 1;
28036let isNonTemporal = 1;
28037let isRestrictNoSlot1Store = 1;
28038let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28039let DecoderNamespace = "EXT_mmvec";
28040let Constraints = "$Rx32 = $Rx32in";
28041}
28042def V6_vL32b_nt_tmp_pi : HInst<
28043(outs HvxVR:$Vd32, IntRegs:$Rx32),
28044(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28045"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
28046tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
28047let Inst{7-5} = 0b010;
28048let Inst{13-11} = 0b000;
28049let Inst{31-21} = 0b00101001010;
28050let hasNewValue = 1;
28051let opNewValue = 0;
28052let addrMode = PostInc;
28053let accessSize = HVXVectorAccess;
28054let isCVLoad = 1;
28055let isCVI = 1;
28056let mayLoad = 1;
28057let isNonTemporal = 1;
28058let isRestrictNoSlot1Store = 1;
28059let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28060let isPredicable = 1;
28061let DecoderNamespace = "EXT_mmvec";
28062let Constraints = "$Rx32 = $Rx32in";
28063}
28064def V6_vL32b_nt_tmp_ppu : HInst<
28065(outs HvxVR:$Vd32, IntRegs:$Rx32),
28066(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28067"$Vd32.tmp = vmem($Rx32++$Mu2):nt",
28068tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28069let Inst{12-5} = 0b00000010;
28070let Inst{31-21} = 0b00101011010;
28071let hasNewValue = 1;
28072let opNewValue = 0;
28073let addrMode = PostInc;
28074let accessSize = HVXVectorAccess;
28075let isCVLoad = 1;
28076let isCVI = 1;
28077let mayLoad = 1;
28078let isNonTemporal = 1;
28079let isRestrictNoSlot1Store = 1;
28080let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28081let isPredicable = 1;
28082let DecoderNamespace = "EXT_mmvec";
28083let Constraints = "$Rx32 = $Rx32in";
28084}
28085def V6_vL32b_nt_tmp_pred_ai : HInst<
28086(outs HvxVR:$Vd32),
28087(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28088"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28089tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28090let Inst{7-5} = 0b110;
28091let Inst{31-21} = 0b00101000110;
28092let isPredicated = 1;
28093let hasNewValue = 1;
28094let opNewValue = 0;
28095let addrMode = BaseImmOffset;
28096let accessSize = HVXVectorAccess;
28097let isCVLoad = 1;
28098let isCVI = 1;
28099let mayLoad = 1;
28100let isNonTemporal = 1;
28101let isRestrictNoSlot1Store = 1;
28102let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28103let DecoderNamespace = "EXT_mmvec";
28104}
28105def V6_vL32b_nt_tmp_pred_pi : HInst<
28106(outs HvxVR:$Vd32, IntRegs:$Rx32),
28107(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28108"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28109tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28110let Inst{7-5} = 0b110;
28111let Inst{13-13} = 0b0;
28112let Inst{31-21} = 0b00101001110;
28113let isPredicated = 1;
28114let hasNewValue = 1;
28115let opNewValue = 0;
28116let addrMode = PostInc;
28117let accessSize = HVXVectorAccess;
28118let isCVLoad = 1;
28119let isCVI = 1;
28120let mayLoad = 1;
28121let isNonTemporal = 1;
28122let isRestrictNoSlot1Store = 1;
28123let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28124let DecoderNamespace = "EXT_mmvec";
28125let Constraints = "$Rx32 = $Rx32in";
28126}
28127def V6_vL32b_nt_tmp_pred_ppu : HInst<
28128(outs HvxVR:$Vd32, IntRegs:$Rx32),
28129(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28130"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28131tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28132let Inst{10-5} = 0b000110;
28133let Inst{31-21} = 0b00101011110;
28134let isPredicated = 1;
28135let hasNewValue = 1;
28136let opNewValue = 0;
28137let addrMode = PostInc;
28138let accessSize = HVXVectorAccess;
28139let isCVLoad = 1;
28140let isCVI = 1;
28141let mayLoad = 1;
28142let isNonTemporal = 1;
28143let isRestrictNoSlot1Store = 1;
28144let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28145let DecoderNamespace = "EXT_mmvec";
28146let Constraints = "$Rx32 = $Rx32in";
28147}
28148def V6_vL32b_pi : HInst<
28149(outs HvxVR:$Vd32, IntRegs:$Rx32),
28150(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28151"$Vd32 = vmem($Rx32++#$Ii)",
28152tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
28153let Inst{7-5} = 0b000;
28154let Inst{13-11} = 0b000;
28155let Inst{31-21} = 0b00101001000;
28156let hasNewValue = 1;
28157let opNewValue = 0;
28158let addrMode = PostInc;
28159let accessSize = HVXVectorAccess;
28160let isCVLoad = 1;
28161let isCVI = 1;
28162let mayLoad = 1;
28163let isRestrictNoSlot1Store = 1;
28164let BaseOpcode = "V6_vL32b_pi";
28165let isCVLoadable = 1;
28166let isPredicable = 1;
28167let DecoderNamespace = "EXT_mmvec";
28168let Constraints = "$Rx32 = $Rx32in";
28169}
28170def V6_vL32b_ppu : HInst<
28171(outs HvxVR:$Vd32, IntRegs:$Rx32),
28172(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28173"$Vd32 = vmem($Rx32++$Mu2)",
28174tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28175let Inst{12-5} = 0b00000000;
28176let Inst{31-21} = 0b00101011000;
28177let hasNewValue = 1;
28178let opNewValue = 0;
28179let addrMode = PostInc;
28180let accessSize = HVXVectorAccess;
28181let isCVLoad = 1;
28182let isCVI = 1;
28183let mayLoad = 1;
28184let isRestrictNoSlot1Store = 1;
28185let BaseOpcode = "V6_vL32b_ppu";
28186let isCVLoadable = 1;
28187let isPredicable = 1;
28188let DecoderNamespace = "EXT_mmvec";
28189let Constraints = "$Rx32 = $Rx32in";
28190}
28191def V6_vL32b_pred_ai : HInst<
28192(outs HvxVR:$Vd32),
28193(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28194"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
28195tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28196let Inst{7-5} = 0b010;
28197let Inst{31-21} = 0b00101000100;
28198let isPredicated = 1;
28199let hasNewValue = 1;
28200let opNewValue = 0;
28201let addrMode = BaseImmOffset;
28202let accessSize = HVXVectorAccess;
28203let isCVLoad = 1;
28204let isCVI = 1;
28205let mayLoad = 1;
28206let isRestrictNoSlot1Store = 1;
28207let BaseOpcode = "V6_vL32b_ai";
28208let DecoderNamespace = "EXT_mmvec";
28209}
28210def V6_vL32b_pred_pi : HInst<
28211(outs HvxVR:$Vd32, IntRegs:$Rx32),
28212(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28213"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
28214tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28215let Inst{7-5} = 0b010;
28216let Inst{13-13} = 0b0;
28217let Inst{31-21} = 0b00101001100;
28218let isPredicated = 1;
28219let hasNewValue = 1;
28220let opNewValue = 0;
28221let addrMode = PostInc;
28222let accessSize = HVXVectorAccess;
28223let isCVLoad = 1;
28224let isCVI = 1;
28225let mayLoad = 1;
28226let isRestrictNoSlot1Store = 1;
28227let BaseOpcode = "V6_vL32b_pi";
28228let DecoderNamespace = "EXT_mmvec";
28229let Constraints = "$Rx32 = $Rx32in";
28230}
28231def V6_vL32b_pred_ppu : HInst<
28232(outs HvxVR:$Vd32, IntRegs:$Rx32),
28233(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28234"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
28235tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28236let Inst{10-5} = 0b000010;
28237let Inst{31-21} = 0b00101011100;
28238let isPredicated = 1;
28239let hasNewValue = 1;
28240let opNewValue = 0;
28241let addrMode = PostInc;
28242let accessSize = HVXVectorAccess;
28243let isCVLoad = 1;
28244let isCVI = 1;
28245let mayLoad = 1;
28246let isRestrictNoSlot1Store = 1;
28247let BaseOpcode = "V6_vL32b_ppu";
28248let DecoderNamespace = "EXT_mmvec";
28249let Constraints = "$Rx32 = $Rx32in";
28250}
28251def V6_vL32b_tmp_ai : HInst<
28252(outs HvxVR:$Vd32),
28253(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28254"$Vd32.tmp = vmem($Rt32+#$Ii)",
28255tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
28256let Inst{7-5} = 0b010;
28257let Inst{12-11} = 0b00;
28258let Inst{31-21} = 0b00101000000;
28259let hasNewValue = 1;
28260let opNewValue = 0;
28261let addrMode = BaseImmOffset;
28262let accessSize = HVXVectorAccess;
28263let isCVLoad = 1;
28264let isCVI = 1;
28265let mayLoad = 1;
28266let isRestrictNoSlot1Store = 1;
28267let BaseOpcode = "V6_vL32b_tmp_ai";
28268let isPredicable = 1;
28269let DecoderNamespace = "EXT_mmvec";
28270}
28271def V6_vL32b_tmp_npred_ai : HInst<
28272(outs HvxVR:$Vd32),
28273(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28274"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28275tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28276let Inst{7-5} = 0b111;
28277let Inst{31-21} = 0b00101000100;
28278let isPredicated = 1;
28279let isPredicatedFalse = 1;
28280let hasNewValue = 1;
28281let opNewValue = 0;
28282let addrMode = BaseImmOffset;
28283let accessSize = HVXVectorAccess;
28284let isCVLoad = 1;
28285let isCVI = 1;
28286let mayLoad = 1;
28287let isRestrictNoSlot1Store = 1;
28288let BaseOpcode = "V6_vL32b_tmp_ai";
28289let DecoderNamespace = "EXT_mmvec";
28290}
28291def V6_vL32b_tmp_npred_pi : HInst<
28292(outs HvxVR:$Vd32, IntRegs:$Rx32),
28293(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28294"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28295tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28296let Inst{7-5} = 0b111;
28297let Inst{13-13} = 0b0;
28298let Inst{31-21} = 0b00101001100;
28299let isPredicated = 1;
28300let isPredicatedFalse = 1;
28301let hasNewValue = 1;
28302let opNewValue = 0;
28303let addrMode = PostInc;
28304let accessSize = HVXVectorAccess;
28305let isCVLoad = 1;
28306let isCVI = 1;
28307let mayLoad = 1;
28308let isRestrictNoSlot1Store = 1;
28309let BaseOpcode = "V6_vL32b_tmp_pi";
28310let DecoderNamespace = "EXT_mmvec";
28311let Constraints = "$Rx32 = $Rx32in";
28312}
28313def V6_vL32b_tmp_npred_ppu : HInst<
28314(outs HvxVR:$Vd32, IntRegs:$Rx32),
28315(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28316"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28317tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28318let Inst{10-5} = 0b000111;
28319let Inst{31-21} = 0b00101011100;
28320let isPredicated = 1;
28321let isPredicatedFalse = 1;
28322let hasNewValue = 1;
28323let opNewValue = 0;
28324let addrMode = PostInc;
28325let accessSize = HVXVectorAccess;
28326let isCVLoad = 1;
28327let isCVI = 1;
28328let mayLoad = 1;
28329let isRestrictNoSlot1Store = 1;
28330let BaseOpcode = "V6_vL32b_tmp_ppu";
28331let DecoderNamespace = "EXT_mmvec";
28332let Constraints = "$Rx32 = $Rx32in";
28333}
28334def V6_vL32b_tmp_pi : HInst<
28335(outs HvxVR:$Vd32, IntRegs:$Rx32),
28336(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28337"$Vd32.tmp = vmem($Rx32++#$Ii)",
28338tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
28339let Inst{7-5} = 0b010;
28340let Inst{13-11} = 0b000;
28341let Inst{31-21} = 0b00101001000;
28342let hasNewValue = 1;
28343let opNewValue = 0;
28344let addrMode = PostInc;
28345let accessSize = HVXVectorAccess;
28346let isCVLoad = 1;
28347let isCVI = 1;
28348let mayLoad = 1;
28349let isRestrictNoSlot1Store = 1;
28350let BaseOpcode = "V6_vL32b_tmp_pi";
28351let isPredicable = 1;
28352let DecoderNamespace = "EXT_mmvec";
28353let Constraints = "$Rx32 = $Rx32in";
28354}
28355def V6_vL32b_tmp_ppu : HInst<
28356(outs HvxVR:$Vd32, IntRegs:$Rx32),
28357(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28358"$Vd32.tmp = vmem($Rx32++$Mu2)",
28359tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28360let Inst{12-5} = 0b00000010;
28361let Inst{31-21} = 0b00101011000;
28362let hasNewValue = 1;
28363let opNewValue = 0;
28364let addrMode = PostInc;
28365let accessSize = HVXVectorAccess;
28366let isCVLoad = 1;
28367let isCVI = 1;
28368let mayLoad = 1;
28369let isRestrictNoSlot1Store = 1;
28370let BaseOpcode = "V6_vL32b_tmp_ppu";
28371let isPredicable = 1;
28372let DecoderNamespace = "EXT_mmvec";
28373let Constraints = "$Rx32 = $Rx32in";
28374}
28375def V6_vL32b_tmp_pred_ai : HInst<
28376(outs HvxVR:$Vd32),
28377(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28378"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28379tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28380let Inst{7-5} = 0b110;
28381let Inst{31-21} = 0b00101000100;
28382let isPredicated = 1;
28383let hasNewValue = 1;
28384let opNewValue = 0;
28385let addrMode = BaseImmOffset;
28386let accessSize = HVXVectorAccess;
28387let isCVLoad = 1;
28388let isCVI = 1;
28389let mayLoad = 1;
28390let isRestrictNoSlot1Store = 1;
28391let BaseOpcode = "V6_vL32b_tmp_ai";
28392let DecoderNamespace = "EXT_mmvec";
28393}
28394def V6_vL32b_tmp_pred_pi : HInst<
28395(outs HvxVR:$Vd32, IntRegs:$Rx32),
28396(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28397"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28398tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28399let Inst{7-5} = 0b110;
28400let Inst{13-13} = 0b0;
28401let Inst{31-21} = 0b00101001100;
28402let isPredicated = 1;
28403let hasNewValue = 1;
28404let opNewValue = 0;
28405let addrMode = PostInc;
28406let accessSize = HVXVectorAccess;
28407let isCVLoad = 1;
28408let isCVI = 1;
28409let mayLoad = 1;
28410let isRestrictNoSlot1Store = 1;
28411let BaseOpcode = "V6_vL32b_tmp_pi";
28412let DecoderNamespace = "EXT_mmvec";
28413let Constraints = "$Rx32 = $Rx32in";
28414}
28415def V6_vL32b_tmp_pred_ppu : HInst<
28416(outs HvxVR:$Vd32, IntRegs:$Rx32),
28417(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28418"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28419tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28420let Inst{10-5} = 0b000110;
28421let Inst{31-21} = 0b00101011100;
28422let isPredicated = 1;
28423let hasNewValue = 1;
28424let opNewValue = 0;
28425let addrMode = PostInc;
28426let accessSize = HVXVectorAccess;
28427let isCVLoad = 1;
28428let isCVI = 1;
28429let mayLoad = 1;
28430let isRestrictNoSlot1Store = 1;
28431let BaseOpcode = "V6_vL32b_tmp_ppu";
28432let DecoderNamespace = "EXT_mmvec";
28433let Constraints = "$Rx32 = $Rx32in";
28434}
28435def V6_vS32Ub_ai : HInst<
28436(outs),
28437(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28438"vmemu($Rt32+#$Ii) = $Vs32",
28439tc_f21e8abb, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28440let Inst{7-5} = 0b111;
28441let Inst{12-11} = 0b00;
28442let Inst{31-21} = 0b00101000001;
28443let addrMode = BaseImmOffset;
28444let accessSize = HVXVectorAccess;
28445let isCVI = 1;
28446let mayStore = 1;
28447let BaseOpcode = "V6_vS32Ub_ai";
28448let isPredicable = 1;
28449let DecoderNamespace = "EXT_mmvec";
28450}
28451def V6_vS32Ub_npred_ai : HInst<
28452(outs),
28453(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28454"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28455tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28456let Inst{7-5} = 0b111;
28457let Inst{31-21} = 0b00101000101;
28458let isPredicated = 1;
28459let isPredicatedFalse = 1;
28460let addrMode = BaseImmOffset;
28461let accessSize = HVXVectorAccess;
28462let isCVI = 1;
28463let mayStore = 1;
28464let BaseOpcode = "V6_vS32Ub_ai";
28465let DecoderNamespace = "EXT_mmvec";
28466}
28467def V6_vS32Ub_npred_pi : HInst<
28468(outs IntRegs:$Rx32),
28469(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28470"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28471tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28472let Inst{7-5} = 0b111;
28473let Inst{13-13} = 0b0;
28474let Inst{31-21} = 0b00101001101;
28475let isPredicated = 1;
28476let isPredicatedFalse = 1;
28477let addrMode = PostInc;
28478let accessSize = HVXVectorAccess;
28479let isCVI = 1;
28480let mayStore = 1;
28481let BaseOpcode = "V6_vS32Ub_pi";
28482let DecoderNamespace = "EXT_mmvec";
28483let Constraints = "$Rx32 = $Rx32in";
28484}
28485def V6_vS32Ub_npred_ppu : HInst<
28486(outs IntRegs:$Rx32),
28487(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28488"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28489tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28490let Inst{10-5} = 0b000111;
28491let Inst{31-21} = 0b00101011101;
28492let isPredicated = 1;
28493let isPredicatedFalse = 1;
28494let addrMode = PostInc;
28495let accessSize = HVXVectorAccess;
28496let isCVI = 1;
28497let mayStore = 1;
28498let BaseOpcode = "V6_vS32Ub_ppu";
28499let DecoderNamespace = "EXT_mmvec";
28500let Constraints = "$Rx32 = $Rx32in";
28501}
28502def V6_vS32Ub_pi : HInst<
28503(outs IntRegs:$Rx32),
28504(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28505"vmemu($Rx32++#$Ii) = $Vs32",
28506tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
28507let Inst{7-5} = 0b111;
28508let Inst{13-11} = 0b000;
28509let Inst{31-21} = 0b00101001001;
28510let addrMode = PostInc;
28511let accessSize = HVXVectorAccess;
28512let isCVI = 1;
28513let mayStore = 1;
28514let BaseOpcode = "V6_vS32Ub_pi";
28515let isPredicable = 1;
28516let DecoderNamespace = "EXT_mmvec";
28517let Constraints = "$Rx32 = $Rx32in";
28518}
28519def V6_vS32Ub_ppu : HInst<
28520(outs IntRegs:$Rx32),
28521(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28522"vmemu($Rx32++$Mu2) = $Vs32",
28523tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28524let Inst{12-5} = 0b00000111;
28525let Inst{31-21} = 0b00101011001;
28526let addrMode = PostInc;
28527let accessSize = HVXVectorAccess;
28528let isCVI = 1;
28529let mayStore = 1;
28530let BaseOpcode = "V6_vS32Ub_ppu";
28531let isPredicable = 1;
28532let DecoderNamespace = "EXT_mmvec";
28533let Constraints = "$Rx32 = $Rx32in";
28534}
28535def V6_vS32Ub_pred_ai : HInst<
28536(outs),
28537(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28538"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28539tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28540let Inst{7-5} = 0b110;
28541let Inst{31-21} = 0b00101000101;
28542let isPredicated = 1;
28543let addrMode = BaseImmOffset;
28544let accessSize = HVXVectorAccess;
28545let isCVI = 1;
28546let mayStore = 1;
28547let BaseOpcode = "V6_vS32Ub_ai";
28548let DecoderNamespace = "EXT_mmvec";
28549}
28550def V6_vS32Ub_pred_pi : HInst<
28551(outs IntRegs:$Rx32),
28552(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28553"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28554tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28555let Inst{7-5} = 0b110;
28556let Inst{13-13} = 0b0;
28557let Inst{31-21} = 0b00101001101;
28558let isPredicated = 1;
28559let addrMode = PostInc;
28560let accessSize = HVXVectorAccess;
28561let isCVI = 1;
28562let mayStore = 1;
28563let BaseOpcode = "V6_vS32Ub_pi";
28564let DecoderNamespace = "EXT_mmvec";
28565let Constraints = "$Rx32 = $Rx32in";
28566}
28567def V6_vS32Ub_pred_ppu : HInst<
28568(outs IntRegs:$Rx32),
28569(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28570"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28571tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28572let Inst{10-5} = 0b000110;
28573let Inst{31-21} = 0b00101011101;
28574let isPredicated = 1;
28575let addrMode = PostInc;
28576let accessSize = HVXVectorAccess;
28577let isCVI = 1;
28578let mayStore = 1;
28579let BaseOpcode = "V6_vS32Ub_ppu";
28580let DecoderNamespace = "EXT_mmvec";
28581let Constraints = "$Rx32 = $Rx32in";
28582}
28583def V6_vS32b_ai : HInst<
28584(outs),
28585(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28586"vmem($Rt32+#$Ii) = $Vs32",
28587tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28588let Inst{7-5} = 0b000;
28589let Inst{12-11} = 0b00;
28590let Inst{31-21} = 0b00101000001;
28591let addrMode = BaseImmOffset;
28592let accessSize = HVXVectorAccess;
28593let isCVI = 1;
28594let mayStore = 1;
28595let BaseOpcode = "V6_vS32b_ai";
28596let isNVStorable = 1;
28597let isPredicable = 1;
28598let DecoderNamespace = "EXT_mmvec";
28599}
28600def V6_vS32b_new_ai : HInst<
28601(outs),
28602(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28603"vmem($Rt32+#$Ii) = $Os8.new",
28604tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
28605let Inst{7-3} = 0b00100;
28606let Inst{12-11} = 0b00;
28607let Inst{31-21} = 0b00101000001;
28608let addrMode = BaseImmOffset;
28609let accessSize = HVXVectorAccess;
28610let isNVStore = 1;
28611let isCVI = 1;
28612let CVINew = 1;
28613let isNewValue = 1;
28614let mayStore = 1;
28615let BaseOpcode = "V6_vS32b_ai";
28616let isPredicable = 1;
28617let DecoderNamespace = "EXT_mmvec";
28618let opNewValue = 2;
28619}
28620def V6_vS32b_new_npred_ai : HInst<
28621(outs),
28622(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28623"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28624tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28625let Inst{7-3} = 0b01101;
28626let Inst{31-21} = 0b00101000101;
28627let isPredicated = 1;
28628let isPredicatedFalse = 1;
28629let addrMode = BaseImmOffset;
28630let accessSize = HVXVectorAccess;
28631let isNVStore = 1;
28632let isCVI = 1;
28633let CVINew = 1;
28634let isNewValue = 1;
28635let mayStore = 1;
28636let BaseOpcode = "V6_vS32b_ai";
28637let DecoderNamespace = "EXT_mmvec";
28638let opNewValue = 3;
28639}
28640def V6_vS32b_new_npred_pi : HInst<
28641(outs IntRegs:$Rx32),
28642(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28643"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28644tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28645let Inst{7-3} = 0b01101;
28646let Inst{13-13} = 0b0;
28647let Inst{31-21} = 0b00101001101;
28648let isPredicated = 1;
28649let isPredicatedFalse = 1;
28650let addrMode = PostInc;
28651let accessSize = HVXVectorAccess;
28652let isNVStore = 1;
28653let isCVI = 1;
28654let CVINew = 1;
28655let isNewValue = 1;
28656let mayStore = 1;
28657let BaseOpcode = "V6_vS32b_pi";
28658let DecoderNamespace = "EXT_mmvec";
28659let opNewValue = 4;
28660let Constraints = "$Rx32 = $Rx32in";
28661}
28662def V6_vS32b_new_npred_ppu : HInst<
28663(outs IntRegs:$Rx32),
28664(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28665"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28666tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28667let Inst{10-3} = 0b00001101;
28668let Inst{31-21} = 0b00101011101;
28669let isPredicated = 1;
28670let isPredicatedFalse = 1;
28671let addrMode = PostInc;
28672let accessSize = HVXVectorAccess;
28673let isNVStore = 1;
28674let isCVI = 1;
28675let CVINew = 1;
28676let isNewValue = 1;
28677let mayStore = 1;
28678let BaseOpcode = "V6_vS32b_ppu";
28679let DecoderNamespace = "EXT_mmvec";
28680let opNewValue = 4;
28681let Constraints = "$Rx32 = $Rx32in";
28682}
28683def V6_vS32b_new_pi : HInst<
28684(outs IntRegs:$Rx32),
28685(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28686"vmem($Rx32++#$Ii) = $Os8.new",
28687tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
28688let Inst{7-3} = 0b00100;
28689let Inst{13-11} = 0b000;
28690let Inst{31-21} = 0b00101001001;
28691let addrMode = PostInc;
28692let accessSize = HVXVectorAccess;
28693let isNVStore = 1;
28694let isCVI = 1;
28695let CVINew = 1;
28696let isNewValue = 1;
28697let mayStore = 1;
28698let BaseOpcode = "V6_vS32b_pi";
28699let isPredicable = 1;
28700let DecoderNamespace = "EXT_mmvec";
28701let opNewValue = 3;
28702let Constraints = "$Rx32 = $Rx32in";
28703}
28704def V6_vS32b_new_ppu : HInst<
28705(outs IntRegs:$Rx32),
28706(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28707"vmem($Rx32++$Mu2) = $Os8.new",
28708tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
28709let Inst{12-3} = 0b0000000100;
28710let Inst{31-21} = 0b00101011001;
28711let addrMode = PostInc;
28712let accessSize = HVXVectorAccess;
28713let isNVStore = 1;
28714let isCVI = 1;
28715let CVINew = 1;
28716let isNewValue = 1;
28717let mayStore = 1;
28718let BaseOpcode = "V6_vS32b_ppu";
28719let isPredicable = 1;
28720let DecoderNamespace = "EXT_mmvec";
28721let opNewValue = 3;
28722let Constraints = "$Rx32 = $Rx32in";
28723}
28724def V6_vS32b_new_pred_ai : HInst<
28725(outs),
28726(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28727"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28728tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28729let Inst{7-3} = 0b01000;
28730let Inst{31-21} = 0b00101000101;
28731let isPredicated = 1;
28732let addrMode = BaseImmOffset;
28733let accessSize = HVXVectorAccess;
28734let isNVStore = 1;
28735let isCVI = 1;
28736let CVINew = 1;
28737let isNewValue = 1;
28738let mayStore = 1;
28739let BaseOpcode = "V6_vS32b_ai";
28740let DecoderNamespace = "EXT_mmvec";
28741let opNewValue = 3;
28742}
28743def V6_vS32b_new_pred_pi : HInst<
28744(outs IntRegs:$Rx32),
28745(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28746"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28747tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28748let Inst{7-3} = 0b01000;
28749let Inst{13-13} = 0b0;
28750let Inst{31-21} = 0b00101001101;
28751let isPredicated = 1;
28752let addrMode = PostInc;
28753let accessSize = HVXVectorAccess;
28754let isNVStore = 1;
28755let isCVI = 1;
28756let CVINew = 1;
28757let isNewValue = 1;
28758let mayStore = 1;
28759let BaseOpcode = "V6_vS32b_pi";
28760let DecoderNamespace = "EXT_mmvec";
28761let opNewValue = 4;
28762let Constraints = "$Rx32 = $Rx32in";
28763}
28764def V6_vS32b_new_pred_ppu : HInst<
28765(outs IntRegs:$Rx32),
28766(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28767"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28768tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28769let Inst{10-3} = 0b00001000;
28770let Inst{31-21} = 0b00101011101;
28771let isPredicated = 1;
28772let addrMode = PostInc;
28773let accessSize = HVXVectorAccess;
28774let isNVStore = 1;
28775let isCVI = 1;
28776let CVINew = 1;
28777let isNewValue = 1;
28778let mayStore = 1;
28779let BaseOpcode = "V6_vS32b_ppu";
28780let DecoderNamespace = "EXT_mmvec";
28781let opNewValue = 4;
28782let Constraints = "$Rx32 = $Rx32in";
28783}
28784def V6_vS32b_npred_ai : HInst<
28785(outs),
28786(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28787"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
28788tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28789let Inst{7-5} = 0b001;
28790let Inst{31-21} = 0b00101000101;
28791let isPredicated = 1;
28792let isPredicatedFalse = 1;
28793let addrMode = BaseImmOffset;
28794let accessSize = HVXVectorAccess;
28795let isCVI = 1;
28796let mayStore = 1;
28797let BaseOpcode = "V6_vS32b_ai";
28798let isNVStorable = 1;
28799let DecoderNamespace = "EXT_mmvec";
28800}
28801def V6_vS32b_npred_pi : HInst<
28802(outs IntRegs:$Rx32),
28803(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28804"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
28805tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28806let Inst{7-5} = 0b001;
28807let Inst{13-13} = 0b0;
28808let Inst{31-21} = 0b00101001101;
28809let isPredicated = 1;
28810let isPredicatedFalse = 1;
28811let addrMode = PostInc;
28812let accessSize = HVXVectorAccess;
28813let isCVI = 1;
28814let mayStore = 1;
28815let BaseOpcode = "V6_vS32b_pi";
28816let isNVStorable = 1;
28817let DecoderNamespace = "EXT_mmvec";
28818let Constraints = "$Rx32 = $Rx32in";
28819}
28820def V6_vS32b_npred_ppu : HInst<
28821(outs IntRegs:$Rx32),
28822(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28823"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
28824tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28825let Inst{10-5} = 0b000001;
28826let Inst{31-21} = 0b00101011101;
28827let isPredicated = 1;
28828let isPredicatedFalse = 1;
28829let addrMode = PostInc;
28830let accessSize = HVXVectorAccess;
28831let isCVI = 1;
28832let mayStore = 1;
28833let BaseOpcode = "V6_vS32b_ppu";
28834let isNVStorable = 1;
28835let DecoderNamespace = "EXT_mmvec";
28836let Constraints = "$Rx32 = $Rx32in";
28837}
28838def V6_vS32b_nqpred_ai : HInst<
28839(outs),
28840(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28841"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
28842tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28843let Inst{7-5} = 0b001;
28844let Inst{31-21} = 0b00101000100;
28845let addrMode = BaseImmOffset;
28846let accessSize = HVXVectorAccess;
28847let isCVI = 1;
28848let mayStore = 1;
28849let DecoderNamespace = "EXT_mmvec";
28850}
28851def V6_vS32b_nqpred_pi : HInst<
28852(outs IntRegs:$Rx32),
28853(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28854"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
28855tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28856let Inst{7-5} = 0b001;
28857let Inst{13-13} = 0b0;
28858let Inst{31-21} = 0b00101001100;
28859let addrMode = PostInc;
28860let accessSize = HVXVectorAccess;
28861let isCVI = 1;
28862let mayStore = 1;
28863let DecoderNamespace = "EXT_mmvec";
28864let Constraints = "$Rx32 = $Rx32in";
28865}
28866def V6_vS32b_nqpred_ppu : HInst<
28867(outs IntRegs:$Rx32),
28868(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28869"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
28870tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28871let Inst{10-5} = 0b000001;
28872let Inst{31-21} = 0b00101011100;
28873let addrMode = PostInc;
28874let accessSize = HVXVectorAccess;
28875let isCVI = 1;
28876let mayStore = 1;
28877let DecoderNamespace = "EXT_mmvec";
28878let Constraints = "$Rx32 = $Rx32in";
28879}
28880def V6_vS32b_nt_ai : HInst<
28881(outs),
28882(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28883"vmem($Rt32+#$Ii):nt = $Vs32",
28884tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28885let Inst{7-5} = 0b000;
28886let Inst{12-11} = 0b00;
28887let Inst{31-21} = 0b00101000011;
28888let addrMode = BaseImmOffset;
28889let accessSize = HVXVectorAccess;
28890let isCVI = 1;
28891let isNonTemporal = 1;
28892let mayStore = 1;
28893let BaseOpcode = "V6_vS32b_ai";
28894let isNVStorable = 1;
28895let isPredicable = 1;
28896let DecoderNamespace = "EXT_mmvec";
28897}
28898def V6_vS32b_nt_new_ai : HInst<
28899(outs),
28900(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28901"vmem($Rt32+#$Ii):nt = $Os8.new",
28902tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
28903let Inst{7-3} = 0b00100;
28904let Inst{12-11} = 0b00;
28905let Inst{31-21} = 0b00101000011;
28906let addrMode = BaseImmOffset;
28907let accessSize = HVXVectorAccess;
28908let isNVStore = 1;
28909let isCVI = 1;
28910let CVINew = 1;
28911let isNewValue = 1;
28912let isNonTemporal = 1;
28913let mayStore = 1;
28914let BaseOpcode = "V6_vS32b_ai";
28915let isPredicable = 1;
28916let DecoderNamespace = "EXT_mmvec";
28917let opNewValue = 2;
28918}
28919def V6_vS32b_nt_new_npred_ai : HInst<
28920(outs),
28921(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28922"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
28923tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28924let Inst{7-3} = 0b01111;
28925let Inst{31-21} = 0b00101000111;
28926let isPredicated = 1;
28927let isPredicatedFalse = 1;
28928let addrMode = BaseImmOffset;
28929let accessSize = HVXVectorAccess;
28930let isNVStore = 1;
28931let isCVI = 1;
28932let CVINew = 1;
28933let isNewValue = 1;
28934let isNonTemporal = 1;
28935let mayStore = 1;
28936let BaseOpcode = "V6_vS32b_ai";
28937let DecoderNamespace = "EXT_mmvec";
28938let opNewValue = 3;
28939}
28940def V6_vS32b_nt_new_npred_pi : HInst<
28941(outs IntRegs:$Rx32),
28942(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28943"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
28944tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28945let Inst{7-3} = 0b01111;
28946let Inst{13-13} = 0b0;
28947let Inst{31-21} = 0b00101001111;
28948let isPredicated = 1;
28949let isPredicatedFalse = 1;
28950let addrMode = PostInc;
28951let accessSize = HVXVectorAccess;
28952let isNVStore = 1;
28953let isCVI = 1;
28954let CVINew = 1;
28955let isNewValue = 1;
28956let isNonTemporal = 1;
28957let mayStore = 1;
28958let BaseOpcode = "V6_vS32b_pi";
28959let DecoderNamespace = "EXT_mmvec";
28960let opNewValue = 4;
28961let Constraints = "$Rx32 = $Rx32in";
28962}
28963def V6_vS32b_nt_new_npred_ppu : HInst<
28964(outs IntRegs:$Rx32),
28965(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28966"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
28967tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28968let Inst{10-3} = 0b00001111;
28969let Inst{31-21} = 0b00101011111;
28970let isPredicated = 1;
28971let isPredicatedFalse = 1;
28972let addrMode = PostInc;
28973let accessSize = HVXVectorAccess;
28974let isNVStore = 1;
28975let isCVI = 1;
28976let CVINew = 1;
28977let isNewValue = 1;
28978let isNonTemporal = 1;
28979let mayStore = 1;
28980let BaseOpcode = "V6_vS32b_ppu";
28981let DecoderNamespace = "EXT_mmvec";
28982let opNewValue = 4;
28983let Constraints = "$Rx32 = $Rx32in";
28984}
28985def V6_vS32b_nt_new_pi : HInst<
28986(outs IntRegs:$Rx32),
28987(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28988"vmem($Rx32++#$Ii):nt = $Os8.new",
28989tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
28990let Inst{7-3} = 0b00100;
28991let Inst{13-11} = 0b000;
28992let Inst{31-21} = 0b00101001011;
28993let addrMode = PostInc;
28994let accessSize = HVXVectorAccess;
28995let isNVStore = 1;
28996let isCVI = 1;
28997let CVINew = 1;
28998let isNewValue = 1;
28999let isNonTemporal = 1;
29000let mayStore = 1;
29001let BaseOpcode = "V6_vS32b_pi";
29002let isPredicable = 1;
29003let DecoderNamespace = "EXT_mmvec";
29004let opNewValue = 3;
29005let Constraints = "$Rx32 = $Rx32in";
29006}
29007def V6_vS32b_nt_new_ppu : HInst<
29008(outs IntRegs:$Rx32),
29009(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29010"vmem($Rx32++$Mu2):nt = $Os8.new",
29011tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
29012let Inst{12-3} = 0b0000000100;
29013let Inst{31-21} = 0b00101011011;
29014let addrMode = PostInc;
29015let accessSize = HVXVectorAccess;
29016let isNVStore = 1;
29017let isCVI = 1;
29018let CVINew = 1;
29019let isNewValue = 1;
29020let isNonTemporal = 1;
29021let mayStore = 1;
29022let BaseOpcode = "V6_vS32b_ppu";
29023let isPredicable = 1;
29024let DecoderNamespace = "EXT_mmvec";
29025let opNewValue = 3;
29026let Constraints = "$Rx32 = $Rx32in";
29027}
29028def V6_vS32b_nt_new_pred_ai : HInst<
29029(outs),
29030(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29031"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29032tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29033let Inst{7-3} = 0b01010;
29034let Inst{31-21} = 0b00101000111;
29035let isPredicated = 1;
29036let addrMode = BaseImmOffset;
29037let accessSize = HVXVectorAccess;
29038let isNVStore = 1;
29039let isCVI = 1;
29040let CVINew = 1;
29041let isNewValue = 1;
29042let isNonTemporal = 1;
29043let mayStore = 1;
29044let BaseOpcode = "V6_vS32b_ai";
29045let DecoderNamespace = "EXT_mmvec";
29046let opNewValue = 3;
29047}
29048def V6_vS32b_nt_new_pred_pi : HInst<
29049(outs IntRegs:$Rx32),
29050(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29051"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29052tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29053let Inst{7-3} = 0b01010;
29054let Inst{13-13} = 0b0;
29055let Inst{31-21} = 0b00101001111;
29056let isPredicated = 1;
29057let addrMode = PostInc;
29058let accessSize = HVXVectorAccess;
29059let isNVStore = 1;
29060let isCVI = 1;
29061let CVINew = 1;
29062let isNewValue = 1;
29063let isNonTemporal = 1;
29064let mayStore = 1;
29065let BaseOpcode = "V6_vS32b_pi";
29066let DecoderNamespace = "EXT_mmvec";
29067let opNewValue = 4;
29068let Constraints = "$Rx32 = $Rx32in";
29069}
29070def V6_vS32b_nt_new_pred_ppu : HInst<
29071(outs IntRegs:$Rx32),
29072(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29073"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29074tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29075let Inst{10-3} = 0b00001010;
29076let Inst{31-21} = 0b00101011111;
29077let isPredicated = 1;
29078let addrMode = PostInc;
29079let accessSize = HVXVectorAccess;
29080let isNVStore = 1;
29081let isCVI = 1;
29082let CVINew = 1;
29083let isNewValue = 1;
29084let isNonTemporal = 1;
29085let mayStore = 1;
29086let BaseOpcode = "V6_vS32b_ppu";
29087let DecoderNamespace = "EXT_mmvec";
29088let opNewValue = 4;
29089let Constraints = "$Rx32 = $Rx32in";
29090}
29091def V6_vS32b_nt_npred_ai : HInst<
29092(outs),
29093(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29094"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29095tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29096let Inst{7-5} = 0b001;
29097let Inst{31-21} = 0b00101000111;
29098let isPredicated = 1;
29099let isPredicatedFalse = 1;
29100let addrMode = BaseImmOffset;
29101let accessSize = HVXVectorAccess;
29102let isCVI = 1;
29103let isNonTemporal = 1;
29104let mayStore = 1;
29105let BaseOpcode = "V6_vS32b_ai";
29106let isNVStorable = 1;
29107let DecoderNamespace = "EXT_mmvec";
29108}
29109def V6_vS32b_nt_npred_pi : HInst<
29110(outs IntRegs:$Rx32),
29111(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29112"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29113tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29114let Inst{7-5} = 0b001;
29115let Inst{13-13} = 0b0;
29116let Inst{31-21} = 0b00101001111;
29117let isPredicated = 1;
29118let isPredicatedFalse = 1;
29119let addrMode = PostInc;
29120let accessSize = HVXVectorAccess;
29121let isCVI = 1;
29122let isNonTemporal = 1;
29123let mayStore = 1;
29124let BaseOpcode = "V6_vS32b_pi";
29125let isNVStorable = 1;
29126let DecoderNamespace = "EXT_mmvec";
29127let Constraints = "$Rx32 = $Rx32in";
29128}
29129def V6_vS32b_nt_npred_ppu : HInst<
29130(outs IntRegs:$Rx32),
29131(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29132"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29133tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29134let Inst{10-5} = 0b000001;
29135let Inst{31-21} = 0b00101011111;
29136let isPredicated = 1;
29137let isPredicatedFalse = 1;
29138let addrMode = PostInc;
29139let accessSize = HVXVectorAccess;
29140let isCVI = 1;
29141let isNonTemporal = 1;
29142let mayStore = 1;
29143let BaseOpcode = "V6_vS32b_ppu";
29144let isNVStorable = 1;
29145let DecoderNamespace = "EXT_mmvec";
29146let Constraints = "$Rx32 = $Rx32in";
29147}
29148def V6_vS32b_nt_nqpred_ai : HInst<
29149(outs),
29150(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29151"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29152tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29153let Inst{7-5} = 0b001;
29154let Inst{31-21} = 0b00101000110;
29155let addrMode = BaseImmOffset;
29156let accessSize = HVXVectorAccess;
29157let isCVI = 1;
29158let isNonTemporal = 1;
29159let mayStore = 1;
29160let DecoderNamespace = "EXT_mmvec";
29161}
29162def V6_vS32b_nt_nqpred_pi : HInst<
29163(outs IntRegs:$Rx32),
29164(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29165"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29166tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29167let Inst{7-5} = 0b001;
29168let Inst{13-13} = 0b0;
29169let Inst{31-21} = 0b00101001110;
29170let addrMode = PostInc;
29171let accessSize = HVXVectorAccess;
29172let isCVI = 1;
29173let isNonTemporal = 1;
29174let mayStore = 1;
29175let DecoderNamespace = "EXT_mmvec";
29176let Constraints = "$Rx32 = $Rx32in";
29177}
29178def V6_vS32b_nt_nqpred_ppu : HInst<
29179(outs IntRegs:$Rx32),
29180(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29181"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29182tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29183let Inst{10-5} = 0b000001;
29184let Inst{31-21} = 0b00101011110;
29185let addrMode = PostInc;
29186let accessSize = HVXVectorAccess;
29187let isCVI = 1;
29188let isNonTemporal = 1;
29189let mayStore = 1;
29190let DecoderNamespace = "EXT_mmvec";
29191let Constraints = "$Rx32 = $Rx32in";
29192}
29193def V6_vS32b_nt_pi : HInst<
29194(outs IntRegs:$Rx32),
29195(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29196"vmem($Rx32++#$Ii):nt = $Vs32",
29197tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
29198let Inst{7-5} = 0b000;
29199let Inst{13-11} = 0b000;
29200let Inst{31-21} = 0b00101001011;
29201let addrMode = PostInc;
29202let accessSize = HVXVectorAccess;
29203let isCVI = 1;
29204let isNonTemporal = 1;
29205let mayStore = 1;
29206let BaseOpcode = "V6_vS32b_pi";
29207let isNVStorable = 1;
29208let isPredicable = 1;
29209let DecoderNamespace = "EXT_mmvec";
29210let Constraints = "$Rx32 = $Rx32in";
29211}
29212def V6_vS32b_nt_ppu : HInst<
29213(outs IntRegs:$Rx32),
29214(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29215"vmem($Rx32++$Mu2):nt = $Vs32",
29216tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29217let Inst{12-5} = 0b00000000;
29218let Inst{31-21} = 0b00101011011;
29219let addrMode = PostInc;
29220let accessSize = HVXVectorAccess;
29221let isCVI = 1;
29222let isNonTemporal = 1;
29223let mayStore = 1;
29224let BaseOpcode = "V6_vS32b_ppu";
29225let isNVStorable = 1;
29226let isPredicable = 1;
29227let DecoderNamespace = "EXT_mmvec";
29228let Constraints = "$Rx32 = $Rx32in";
29229}
29230def V6_vS32b_nt_pred_ai : HInst<
29231(outs),
29232(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29233"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29234tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29235let Inst{7-5} = 0b000;
29236let Inst{31-21} = 0b00101000111;
29237let isPredicated = 1;
29238let addrMode = BaseImmOffset;
29239let accessSize = HVXVectorAccess;
29240let isCVI = 1;
29241let isNonTemporal = 1;
29242let mayStore = 1;
29243let BaseOpcode = "V6_vS32b_ai";
29244let isNVStorable = 1;
29245let DecoderNamespace = "EXT_mmvec";
29246}
29247def V6_vS32b_nt_pred_pi : HInst<
29248(outs IntRegs:$Rx32),
29249(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29250"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29251tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29252let Inst{7-5} = 0b000;
29253let Inst{13-13} = 0b0;
29254let Inst{31-21} = 0b00101001111;
29255let isPredicated = 1;
29256let addrMode = PostInc;
29257let accessSize = HVXVectorAccess;
29258let isCVI = 1;
29259let isNonTemporal = 1;
29260let mayStore = 1;
29261let BaseOpcode = "V6_vS32b_pi";
29262let isNVStorable = 1;
29263let DecoderNamespace = "EXT_mmvec";
29264let Constraints = "$Rx32 = $Rx32in";
29265}
29266def V6_vS32b_nt_pred_ppu : HInst<
29267(outs IntRegs:$Rx32),
29268(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29269"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29270tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29271let Inst{10-5} = 0b000000;
29272let Inst{31-21} = 0b00101011111;
29273let isPredicated = 1;
29274let addrMode = PostInc;
29275let accessSize = HVXVectorAccess;
29276let isCVI = 1;
29277let isNonTemporal = 1;
29278let mayStore = 1;
29279let BaseOpcode = "V6_vS32b_ppu";
29280let isNVStorable = 1;
29281let DecoderNamespace = "EXT_mmvec";
29282let Constraints = "$Rx32 = $Rx32in";
29283}
29284def V6_vS32b_nt_qpred_ai : HInst<
29285(outs),
29286(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29287"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29288tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29289let Inst{7-5} = 0b000;
29290let Inst{31-21} = 0b00101000110;
29291let addrMode = BaseImmOffset;
29292let accessSize = HVXVectorAccess;
29293let isCVI = 1;
29294let isNonTemporal = 1;
29295let mayStore = 1;
29296let DecoderNamespace = "EXT_mmvec";
29297}
29298def V6_vS32b_nt_qpred_pi : HInst<
29299(outs IntRegs:$Rx32),
29300(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29301"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29302tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29303let Inst{7-5} = 0b000;
29304let Inst{13-13} = 0b0;
29305let Inst{31-21} = 0b00101001110;
29306let addrMode = PostInc;
29307let accessSize = HVXVectorAccess;
29308let isCVI = 1;
29309let isNonTemporal = 1;
29310let mayStore = 1;
29311let DecoderNamespace = "EXT_mmvec";
29312let Constraints = "$Rx32 = $Rx32in";
29313}
29314def V6_vS32b_nt_qpred_ppu : HInst<
29315(outs IntRegs:$Rx32),
29316(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29317"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29318tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29319let Inst{10-5} = 0b000000;
29320let Inst{31-21} = 0b00101011110;
29321let addrMode = PostInc;
29322let accessSize = HVXVectorAccess;
29323let isCVI = 1;
29324let isNonTemporal = 1;
29325let mayStore = 1;
29326let DecoderNamespace = "EXT_mmvec";
29327let Constraints = "$Rx32 = $Rx32in";
29328}
29329def V6_vS32b_pi : HInst<
29330(outs IntRegs:$Rx32),
29331(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29332"vmem($Rx32++#$Ii) = $Vs32",
29333tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
29334let Inst{7-5} = 0b000;
29335let Inst{13-11} = 0b000;
29336let Inst{31-21} = 0b00101001001;
29337let addrMode = PostInc;
29338let accessSize = HVXVectorAccess;
29339let isCVI = 1;
29340let mayStore = 1;
29341let BaseOpcode = "V6_vS32b_pi";
29342let isNVStorable = 1;
29343let isPredicable = 1;
29344let DecoderNamespace = "EXT_mmvec";
29345let Constraints = "$Rx32 = $Rx32in";
29346}
29347def V6_vS32b_ppu : HInst<
29348(outs IntRegs:$Rx32),
29349(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29350"vmem($Rx32++$Mu2) = $Vs32",
29351tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29352let Inst{12-5} = 0b00000000;
29353let Inst{31-21} = 0b00101011001;
29354let addrMode = PostInc;
29355let accessSize = HVXVectorAccess;
29356let isCVI = 1;
29357let mayStore = 1;
29358let BaseOpcode = "V6_vS32b_ppu";
29359let isNVStorable = 1;
29360let isPredicable = 1;
29361let DecoderNamespace = "EXT_mmvec";
29362let Constraints = "$Rx32 = $Rx32in";
29363}
29364def V6_vS32b_pred_ai : HInst<
29365(outs),
29366(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29367"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
29368tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29369let Inst{7-5} = 0b000;
29370let Inst{31-21} = 0b00101000101;
29371let isPredicated = 1;
29372let addrMode = BaseImmOffset;
29373let accessSize = HVXVectorAccess;
29374let isCVI = 1;
29375let mayStore = 1;
29376let BaseOpcode = "V6_vS32b_ai";
29377let isNVStorable = 1;
29378let DecoderNamespace = "EXT_mmvec";
29379}
29380def V6_vS32b_pred_pi : HInst<
29381(outs IntRegs:$Rx32),
29382(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29383"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
29384tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29385let Inst{7-5} = 0b000;
29386let Inst{13-13} = 0b0;
29387let Inst{31-21} = 0b00101001101;
29388let isPredicated = 1;
29389let addrMode = PostInc;
29390let accessSize = HVXVectorAccess;
29391let isCVI = 1;
29392let mayStore = 1;
29393let BaseOpcode = "V6_vS32b_pi";
29394let isNVStorable = 1;
29395let DecoderNamespace = "EXT_mmvec";
29396let Constraints = "$Rx32 = $Rx32in";
29397}
29398def V6_vS32b_pred_ppu : HInst<
29399(outs IntRegs:$Rx32),
29400(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29401"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
29402tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29403let Inst{10-5} = 0b000000;
29404let Inst{31-21} = 0b00101011101;
29405let isPredicated = 1;
29406let addrMode = PostInc;
29407let accessSize = HVXVectorAccess;
29408let isCVI = 1;
29409let mayStore = 1;
29410let BaseOpcode = "V6_vS32b_ppu";
29411let isNVStorable = 1;
29412let DecoderNamespace = "EXT_mmvec";
29413let Constraints = "$Rx32 = $Rx32in";
29414}
29415def V6_vS32b_qpred_ai : HInst<
29416(outs),
29417(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29418"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
29419tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29420let Inst{7-5} = 0b000;
29421let Inst{31-21} = 0b00101000100;
29422let addrMode = BaseImmOffset;
29423let accessSize = HVXVectorAccess;
29424let isCVI = 1;
29425let mayStore = 1;
29426let DecoderNamespace = "EXT_mmvec";
29427}
29428def V6_vS32b_qpred_pi : HInst<
29429(outs IntRegs:$Rx32),
29430(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29431"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
29432tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29433let Inst{7-5} = 0b000;
29434let Inst{13-13} = 0b0;
29435let Inst{31-21} = 0b00101001100;
29436let addrMode = PostInc;
29437let accessSize = HVXVectorAccess;
29438let isCVI = 1;
29439let mayStore = 1;
29440let DecoderNamespace = "EXT_mmvec";
29441let Constraints = "$Rx32 = $Rx32in";
29442}
29443def V6_vS32b_qpred_ppu : HInst<
29444(outs IntRegs:$Rx32),
29445(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29446"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
29447tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29448let Inst{10-5} = 0b000000;
29449let Inst{31-21} = 0b00101011100;
29450let addrMode = PostInc;
29451let accessSize = HVXVectorAccess;
29452let isCVI = 1;
29453let mayStore = 1;
29454let DecoderNamespace = "EXT_mmvec";
29455let Constraints = "$Rx32 = $Rx32in";
29456}
29457def V6_vS32b_srls_ai : HInst<
29458(outs),
29459(ins IntRegs:$Rt32, s4_0Imm:$Ii),
29460"vmem($Rt32+#$Ii):scatter_release",
29461tc_3ce09744, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
29462let Inst{7-0} = 0b00101000;
29463let Inst{12-11} = 0b00;
29464let Inst{31-21} = 0b00101000001;
29465let addrMode = BaseImmOffset;
29466let accessSize = HVXVectorAccess;
29467let isCVI = 1;
29468let CVINew = 1;
29469let mayStore = 1;
29470let DecoderNamespace = "EXT_mmvec";
29471}
29472def V6_vS32b_srls_pi : HInst<
29473(outs IntRegs:$Rx32),
29474(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
29475"vmem($Rx32++#$Ii):scatter_release",
29476tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
29477let Inst{7-0} = 0b00101000;
29478let Inst{13-11} = 0b000;
29479let Inst{31-21} = 0b00101001001;
29480let addrMode = PostInc;
29481let accessSize = HVXVectorAccess;
29482let isCVI = 1;
29483let CVINew = 1;
29484let mayStore = 1;
29485let DecoderNamespace = "EXT_mmvec";
29486let Constraints = "$Rx32 = $Rx32in";
29487}
29488def V6_vS32b_srls_ppu : HInst<
29489(outs IntRegs:$Rx32),
29490(ins IntRegs:$Rx32in, ModRegs:$Mu2),
29491"vmem($Rx32++$Mu2):scatter_release",
29492tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
29493let Inst{12-0} = 0b0000000101000;
29494let Inst{31-21} = 0b00101011001;
29495let addrMode = PostInc;
29496let accessSize = HVXVectorAccess;
29497let isCVI = 1;
29498let CVINew = 1;
29499let mayStore = 1;
29500let DecoderNamespace = "EXT_mmvec";
29501let Constraints = "$Rx32 = $Rx32in";
29502}
29503def V6_vabsb : HInst<
29504(outs HvxVR:$Vd32),
29505(ins HvxVR:$Vu32),
29506"$Vd32.b = vabs($Vu32.b)",
29507tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29508let Inst{7-5} = 0b100;
29509let Inst{13-13} = 0b0;
29510let Inst{31-16} = 0b0001111000000001;
29511let hasNewValue = 1;
29512let opNewValue = 0;
29513let isCVI = 1;
29514let DecoderNamespace = "EXT_mmvec";
29515}
29516def V6_vabsb_alt : HInst<
29517(outs HvxVR:$Vd32),
29518(ins HvxVR:$Vu32),
29519"$Vd32 = vabsb($Vu32)",
29520PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29521let hasNewValue = 1;
29522let opNewValue = 0;
29523let isCVI = 1;
29524let isPseudo = 1;
29525let isCodeGenOnly = 1;
29526let DecoderNamespace = "EXT_mmvec";
29527}
29528def V6_vabsb_sat : HInst<
29529(outs HvxVR:$Vd32),
29530(ins HvxVR:$Vu32),
29531"$Vd32.b = vabs($Vu32.b):sat",
29532tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29533let Inst{7-5} = 0b101;
29534let Inst{13-13} = 0b0;
29535let Inst{31-16} = 0b0001111000000001;
29536let hasNewValue = 1;
29537let opNewValue = 0;
29538let isCVI = 1;
29539let DecoderNamespace = "EXT_mmvec";
29540}
29541def V6_vabsb_sat_alt : HInst<
29542(outs HvxVR:$Vd32),
29543(ins HvxVR:$Vu32),
29544"$Vd32 = vabsb($Vu32):sat",
29545PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29546let hasNewValue = 1;
29547let opNewValue = 0;
29548let isCVI = 1;
29549let isPseudo = 1;
29550let isCodeGenOnly = 1;
29551let DecoderNamespace = "EXT_mmvec";
29552}
29553def V6_vabsdiffh : HInst<
29554(outs HvxVR:$Vd32),
29555(ins HvxVR:$Vu32, HvxVR:$Vv32),
29556"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
29557tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29558let Inst{7-5} = 0b001;
29559let Inst{13-13} = 0b0;
29560let Inst{31-21} = 0b00011100110;
29561let hasNewValue = 1;
29562let opNewValue = 0;
29563let isCVI = 1;
29564let DecoderNamespace = "EXT_mmvec";
29565}
29566def V6_vabsdiffh_alt : HInst<
29567(outs HvxVR:$Vd32),
29568(ins HvxVR:$Vu32, HvxVR:$Vv32),
29569"$Vd32 = vabsdiffh($Vu32,$Vv32)",
29570PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29571let hasNewValue = 1;
29572let opNewValue = 0;
29573let isCVI = 1;
29574let isPseudo = 1;
29575let isCodeGenOnly = 1;
29576let DecoderNamespace = "EXT_mmvec";
29577}
29578def V6_vabsdiffub : HInst<
29579(outs HvxVR:$Vd32),
29580(ins HvxVR:$Vu32, HvxVR:$Vv32),
29581"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
29582tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29583let Inst{7-5} = 0b000;
29584let Inst{13-13} = 0b0;
29585let Inst{31-21} = 0b00011100110;
29586let hasNewValue = 1;
29587let opNewValue = 0;
29588let isCVI = 1;
29589let DecoderNamespace = "EXT_mmvec";
29590}
29591def V6_vabsdiffub_alt : HInst<
29592(outs HvxVR:$Vd32),
29593(ins HvxVR:$Vu32, HvxVR:$Vv32),
29594"$Vd32 = vabsdiffub($Vu32,$Vv32)",
29595PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29596let hasNewValue = 1;
29597let opNewValue = 0;
29598let isCVI = 1;
29599let isPseudo = 1;
29600let isCodeGenOnly = 1;
29601let DecoderNamespace = "EXT_mmvec";
29602}
29603def V6_vabsdiffuh : HInst<
29604(outs HvxVR:$Vd32),
29605(ins HvxVR:$Vu32, HvxVR:$Vv32),
29606"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
29607tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29608let Inst{7-5} = 0b010;
29609let Inst{13-13} = 0b0;
29610let Inst{31-21} = 0b00011100110;
29611let hasNewValue = 1;
29612let opNewValue = 0;
29613let isCVI = 1;
29614let DecoderNamespace = "EXT_mmvec";
29615}
29616def V6_vabsdiffuh_alt : HInst<
29617(outs HvxVR:$Vd32),
29618(ins HvxVR:$Vu32, HvxVR:$Vv32),
29619"$Vd32 = vabsdiffuh($Vu32,$Vv32)",
29620PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29621let hasNewValue = 1;
29622let opNewValue = 0;
29623let isCVI = 1;
29624let isPseudo = 1;
29625let isCodeGenOnly = 1;
29626let DecoderNamespace = "EXT_mmvec";
29627}
29628def V6_vabsdiffw : HInst<
29629(outs HvxVR:$Vd32),
29630(ins HvxVR:$Vu32, HvxVR:$Vv32),
29631"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
29632tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29633let Inst{7-5} = 0b011;
29634let Inst{13-13} = 0b0;
29635let Inst{31-21} = 0b00011100110;
29636let hasNewValue = 1;
29637let opNewValue = 0;
29638let isCVI = 1;
29639let DecoderNamespace = "EXT_mmvec";
29640}
29641def V6_vabsdiffw_alt : HInst<
29642(outs HvxVR:$Vd32),
29643(ins HvxVR:$Vu32, HvxVR:$Vv32),
29644"$Vd32 = vabsdiffw($Vu32,$Vv32)",
29645PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29646let hasNewValue = 1;
29647let opNewValue = 0;
29648let isCVI = 1;
29649let isPseudo = 1;
29650let isCodeGenOnly = 1;
29651let DecoderNamespace = "EXT_mmvec";
29652}
29653def V6_vabsh : HInst<
29654(outs HvxVR:$Vd32),
29655(ins HvxVR:$Vu32),
29656"$Vd32.h = vabs($Vu32.h)",
29657tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29658let Inst{7-5} = 0b000;
29659let Inst{13-13} = 0b0;
29660let Inst{31-16} = 0b0001111000000000;
29661let hasNewValue = 1;
29662let opNewValue = 0;
29663let isCVI = 1;
29664let DecoderNamespace = "EXT_mmvec";
29665}
29666def V6_vabsh_alt : HInst<
29667(outs HvxVR:$Vd32),
29668(ins HvxVR:$Vu32),
29669"$Vd32 = vabsh($Vu32)",
29670PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29671let hasNewValue = 1;
29672let opNewValue = 0;
29673let isCVI = 1;
29674let isPseudo = 1;
29675let isCodeGenOnly = 1;
29676let DecoderNamespace = "EXT_mmvec";
29677}
29678def V6_vabsh_sat : HInst<
29679(outs HvxVR:$Vd32),
29680(ins HvxVR:$Vu32),
29681"$Vd32.h = vabs($Vu32.h):sat",
29682tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29683let Inst{7-5} = 0b001;
29684let Inst{13-13} = 0b0;
29685let Inst{31-16} = 0b0001111000000000;
29686let hasNewValue = 1;
29687let opNewValue = 0;
29688let isCVI = 1;
29689let DecoderNamespace = "EXT_mmvec";
29690}
29691def V6_vabsh_sat_alt : HInst<
29692(outs HvxVR:$Vd32),
29693(ins HvxVR:$Vu32),
29694"$Vd32 = vabsh($Vu32):sat",
29695PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29696let hasNewValue = 1;
29697let opNewValue = 0;
29698let isCVI = 1;
29699let isPseudo = 1;
29700let isCodeGenOnly = 1;
29701let DecoderNamespace = "EXT_mmvec";
29702}
29703def V6_vabsub_alt : HInst<
29704(outs HvxVR:$Vd32),
29705(ins HvxVR:$Vu32),
29706"$Vd32.ub = vabs($Vu32.b)",
29707tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29708let hasNewValue = 1;
29709let opNewValue = 0;
29710let isCVI = 1;
29711let isPseudo = 1;
29712let isCodeGenOnly = 1;
29713let DecoderNamespace = "EXT_mmvec";
29714}
29715def V6_vabsuh_alt : HInst<
29716(outs HvxVR:$Vd32),
29717(ins HvxVR:$Vu32),
29718"$Vd32.uh = vabs($Vu32.h)",
29719tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29720let hasNewValue = 1;
29721let opNewValue = 0;
29722let isCVI = 1;
29723let isPseudo = 1;
29724let isCodeGenOnly = 1;
29725let DecoderNamespace = "EXT_mmvec";
29726}
29727def V6_vabsuw_alt : HInst<
29728(outs HvxVR:$Vd32),
29729(ins HvxVR:$Vu32),
29730"$Vd32.uw = vabs($Vu32.w)",
29731tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29732let hasNewValue = 1;
29733let opNewValue = 0;
29734let isCVI = 1;
29735let isPseudo = 1;
29736let isCodeGenOnly = 1;
29737let DecoderNamespace = "EXT_mmvec";
29738}
29739def V6_vabsw : HInst<
29740(outs HvxVR:$Vd32),
29741(ins HvxVR:$Vu32),
29742"$Vd32.w = vabs($Vu32.w)",
29743tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29744let Inst{7-5} = 0b010;
29745let Inst{13-13} = 0b0;
29746let Inst{31-16} = 0b0001111000000000;
29747let hasNewValue = 1;
29748let opNewValue = 0;
29749let isCVI = 1;
29750let DecoderNamespace = "EXT_mmvec";
29751}
29752def V6_vabsw_alt : HInst<
29753(outs HvxVR:$Vd32),
29754(ins HvxVR:$Vu32),
29755"$Vd32 = vabsw($Vu32)",
29756PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29757let hasNewValue = 1;
29758let opNewValue = 0;
29759let isCVI = 1;
29760let isPseudo = 1;
29761let isCodeGenOnly = 1;
29762let DecoderNamespace = "EXT_mmvec";
29763}
29764def V6_vabsw_sat : HInst<
29765(outs HvxVR:$Vd32),
29766(ins HvxVR:$Vu32),
29767"$Vd32.w = vabs($Vu32.w):sat",
29768tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29769let Inst{7-5} = 0b011;
29770let Inst{13-13} = 0b0;
29771let Inst{31-16} = 0b0001111000000000;
29772let hasNewValue = 1;
29773let opNewValue = 0;
29774let isCVI = 1;
29775let DecoderNamespace = "EXT_mmvec";
29776}
29777def V6_vabsw_sat_alt : HInst<
29778(outs HvxVR:$Vd32),
29779(ins HvxVR:$Vu32),
29780"$Vd32 = vabsw($Vu32):sat",
29781PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29782let hasNewValue = 1;
29783let opNewValue = 0;
29784let isCVI = 1;
29785let isPseudo = 1;
29786let isCodeGenOnly = 1;
29787let DecoderNamespace = "EXT_mmvec";
29788}
29789def V6_vaddb : HInst<
29790(outs HvxVR:$Vd32),
29791(ins HvxVR:$Vu32, HvxVR:$Vv32),
29792"$Vd32.b = vadd($Vu32.b,$Vv32.b)",
29793tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29794let Inst{7-5} = 0b110;
29795let Inst{13-13} = 0b0;
29796let Inst{31-21} = 0b00011111101;
29797let hasNewValue = 1;
29798let opNewValue = 0;
29799let isCVI = 1;
29800let DecoderNamespace = "EXT_mmvec";
29801}
29802def V6_vaddb_alt : HInst<
29803(outs HvxVR:$Vd32),
29804(ins HvxVR:$Vu32, HvxVR:$Vv32),
29805"$Vd32 = vaddb($Vu32,$Vv32)",
29806PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29807let hasNewValue = 1;
29808let opNewValue = 0;
29809let isCVI = 1;
29810let isPseudo = 1;
29811let isCodeGenOnly = 1;
29812let DecoderNamespace = "EXT_mmvec";
29813}
29814def V6_vaddb_dv : HInst<
29815(outs HvxWR:$Vdd32),
29816(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29817"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
29818tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29819let Inst{7-5} = 0b100;
29820let Inst{13-13} = 0b0;
29821let Inst{31-21} = 0b00011100011;
29822let hasNewValue = 1;
29823let opNewValue = 0;
29824let isCVI = 1;
29825let DecoderNamespace = "EXT_mmvec";
29826}
29827def V6_vaddb_dv_alt : HInst<
29828(outs HvxWR:$Vdd32),
29829(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29830"$Vdd32 = vaddb($Vuu32,$Vvv32)",
29831PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29832let hasNewValue = 1;
29833let opNewValue = 0;
29834let isCVI = 1;
29835let isPseudo = 1;
29836let isCodeGenOnly = 1;
29837let DecoderNamespace = "EXT_mmvec";
29838}
29839def V6_vaddbnq : HInst<
29840(outs HvxVR:$Vx32),
29841(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29842"if (!$Qv4) $Vx32.b += $Vu32.b",
29843tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29844let Inst{7-5} = 0b011;
29845let Inst{13-13} = 0b1;
29846let Inst{21-16} = 0b000001;
29847let Inst{31-24} = 0b00011110;
29848let hasNewValue = 1;
29849let opNewValue = 0;
29850let isAccumulator = 1;
29851let isCVI = 1;
29852let DecoderNamespace = "EXT_mmvec";
29853let Constraints = "$Vx32 = $Vx32in";
29854}
29855def V6_vaddbnq_alt : HInst<
29856(outs HvxVR:$Vx32),
29857(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29858"if (!$Qv4.b) $Vx32.b += $Vu32.b",
29859PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29860let hasNewValue = 1;
29861let opNewValue = 0;
29862let isAccumulator = 1;
29863let isCVI = 1;
29864let isPseudo = 1;
29865let isCodeGenOnly = 1;
29866let DecoderNamespace = "EXT_mmvec";
29867let Constraints = "$Vx32 = $Vx32in";
29868}
29869def V6_vaddbq : HInst<
29870(outs HvxVR:$Vx32),
29871(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29872"if ($Qv4) $Vx32.b += $Vu32.b",
29873tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29874let Inst{7-5} = 0b000;
29875let Inst{13-13} = 0b1;
29876let Inst{21-16} = 0b000001;
29877let Inst{31-24} = 0b00011110;
29878let hasNewValue = 1;
29879let opNewValue = 0;
29880let isAccumulator = 1;
29881let isCVI = 1;
29882let DecoderNamespace = "EXT_mmvec";
29883let Constraints = "$Vx32 = $Vx32in";
29884}
29885def V6_vaddbq_alt : HInst<
29886(outs HvxVR:$Vx32),
29887(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29888"if ($Qv4.b) $Vx32.b += $Vu32.b",
29889PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29890let hasNewValue = 1;
29891let opNewValue = 0;
29892let isAccumulator = 1;
29893let isCVI = 1;
29894let isPseudo = 1;
29895let isCodeGenOnly = 1;
29896let DecoderNamespace = "EXT_mmvec";
29897let Constraints = "$Vx32 = $Vx32in";
29898}
29899def V6_vaddbsat : HInst<
29900(outs HvxVR:$Vd32),
29901(ins HvxVR:$Vu32, HvxVR:$Vv32),
29902"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
29903tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
29904let Inst{7-5} = 0b000;
29905let Inst{13-13} = 0b0;
29906let Inst{31-21} = 0b00011111000;
29907let hasNewValue = 1;
29908let opNewValue = 0;
29909let isCVI = 1;
29910let DecoderNamespace = "EXT_mmvec";
29911}
29912def V6_vaddbsat_alt : HInst<
29913(outs HvxVR:$Vd32),
29914(ins HvxVR:$Vu32, HvxVR:$Vv32),
29915"$Vd32 = vaddb($Vu32,$Vv32):sat",
29916PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29917let hasNewValue = 1;
29918let opNewValue = 0;
29919let isCVI = 1;
29920let isPseudo = 1;
29921let isCodeGenOnly = 1;
29922let DecoderNamespace = "EXT_mmvec";
29923}
29924def V6_vaddbsat_dv : HInst<
29925(outs HvxWR:$Vdd32),
29926(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29927"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
29928tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
29929let Inst{7-5} = 0b000;
29930let Inst{13-13} = 0b0;
29931let Inst{31-21} = 0b00011110101;
29932let hasNewValue = 1;
29933let opNewValue = 0;
29934let isCVI = 1;
29935let DecoderNamespace = "EXT_mmvec";
29936}
29937def V6_vaddbsat_dv_alt : HInst<
29938(outs HvxWR:$Vdd32),
29939(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29940"$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
29941PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29942let hasNewValue = 1;
29943let opNewValue = 0;
29944let isCVI = 1;
29945let isPseudo = 1;
29946let isCodeGenOnly = 1;
29947let DecoderNamespace = "EXT_mmvec";
29948}
29949def V6_vaddcarry : HInst<
29950(outs HvxVR:$Vd32, HvxQR:$Qx4),
29951(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
29952"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
29953tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
29954let Inst{7-7} = 0b0;
29955let Inst{13-13} = 0b1;
29956let Inst{31-21} = 0b00011100101;
29957let hasNewValue = 1;
29958let opNewValue = 0;
29959let isCVI = 1;
29960let DecoderNamespace = "EXT_mmvec";
29961let Constraints = "$Qx4 = $Qx4in";
29962}
29963def V6_vaddcarryo : HInst<
29964(outs HvxVR:$Vd32, HvxQR:$Qe4),
29965(ins HvxVR:$Vu32, HvxVR:$Vv32),
29966"$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry",
29967tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
29968let Inst{7-7} = 0b0;
29969let Inst{13-13} = 0b1;
29970let Inst{31-21} = 0b00011101101;
29971let hasNewValue = 1;
29972let opNewValue = 0;
29973let hasNewValue2 = 1;
29974let opNewValue2 = 1;
29975let isCVI = 1;
29976let DecoderNamespace = "EXT_mmvec";
29977}
29978def V6_vaddcarrysat : HInst<
29979(outs HvxVR:$Vd32),
29980(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qs4),
29981"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qs4):carry:sat",
29982tc_257f6f7c, TypeCVI_VA>, Enc_e0820b, Requires<[UseHVXV66]> {
29983let Inst{7-7} = 0b0;
29984let Inst{13-13} = 0b1;
29985let Inst{31-21} = 0b00011101100;
29986let hasNewValue = 1;
29987let opNewValue = 0;
29988let isCVI = 1;
29989let DecoderNamespace = "EXT_mmvec";
29990}
29991def V6_vaddclbh : HInst<
29992(outs HvxVR:$Vd32),
29993(ins HvxVR:$Vu32, HvxVR:$Vv32),
29994"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
29995tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
29996let Inst{7-5} = 0b000;
29997let Inst{13-13} = 0b1;
29998let Inst{31-21} = 0b00011111000;
29999let hasNewValue = 1;
30000let opNewValue = 0;
30001let isCVI = 1;
30002let DecoderNamespace = "EXT_mmvec";
30003}
30004def V6_vaddclbw : HInst<
30005(outs HvxVR:$Vd32),
30006(ins HvxVR:$Vu32, HvxVR:$Vv32),
30007"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
30008tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30009let Inst{7-5} = 0b001;
30010let Inst{13-13} = 0b1;
30011let Inst{31-21} = 0b00011111000;
30012let hasNewValue = 1;
30013let opNewValue = 0;
30014let isCVI = 1;
30015let DecoderNamespace = "EXT_mmvec";
30016}
30017def V6_vaddh : HInst<
30018(outs HvxVR:$Vd32),
30019(ins HvxVR:$Vu32, HvxVR:$Vv32),
30020"$Vd32.h = vadd($Vu32.h,$Vv32.h)",
30021tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30022let Inst{7-5} = 0b111;
30023let Inst{13-13} = 0b0;
30024let Inst{31-21} = 0b00011111101;
30025let hasNewValue = 1;
30026let opNewValue = 0;
30027let isCVI = 1;
30028let DecoderNamespace = "EXT_mmvec";
30029}
30030def V6_vaddh_alt : HInst<
30031(outs HvxVR:$Vd32),
30032(ins HvxVR:$Vu32, HvxVR:$Vv32),
30033"$Vd32 = vaddh($Vu32,$Vv32)",
30034PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30035let hasNewValue = 1;
30036let opNewValue = 0;
30037let isCVI = 1;
30038let isPseudo = 1;
30039let isCodeGenOnly = 1;
30040let DecoderNamespace = "EXT_mmvec";
30041}
30042def V6_vaddh_dv : HInst<
30043(outs HvxWR:$Vdd32),
30044(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30045"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
30046tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30047let Inst{7-5} = 0b101;
30048let Inst{13-13} = 0b0;
30049let Inst{31-21} = 0b00011100011;
30050let hasNewValue = 1;
30051let opNewValue = 0;
30052let isCVI = 1;
30053let DecoderNamespace = "EXT_mmvec";
30054}
30055def V6_vaddh_dv_alt : HInst<
30056(outs HvxWR:$Vdd32),
30057(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30058"$Vdd32 = vaddh($Vuu32,$Vvv32)",
30059PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30060let hasNewValue = 1;
30061let opNewValue = 0;
30062let isCVI = 1;
30063let isPseudo = 1;
30064let isCodeGenOnly = 1;
30065let DecoderNamespace = "EXT_mmvec";
30066}
30067def V6_vaddhnq : HInst<
30068(outs HvxVR:$Vx32),
30069(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30070"if (!$Qv4) $Vx32.h += $Vu32.h",
30071tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30072let Inst{7-5} = 0b100;
30073let Inst{13-13} = 0b1;
30074let Inst{21-16} = 0b000001;
30075let Inst{31-24} = 0b00011110;
30076let hasNewValue = 1;
30077let opNewValue = 0;
30078let isAccumulator = 1;
30079let isCVI = 1;
30080let DecoderNamespace = "EXT_mmvec";
30081let Constraints = "$Vx32 = $Vx32in";
30082}
30083def V6_vaddhnq_alt : HInst<
30084(outs HvxVR:$Vx32),
30085(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30086"if (!$Qv4.h) $Vx32.h += $Vu32.h",
30087PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30088let hasNewValue = 1;
30089let opNewValue = 0;
30090let isAccumulator = 1;
30091let isCVI = 1;
30092let isPseudo = 1;
30093let isCodeGenOnly = 1;
30094let DecoderNamespace = "EXT_mmvec";
30095let Constraints = "$Vx32 = $Vx32in";
30096}
30097def V6_vaddhq : HInst<
30098(outs HvxVR:$Vx32),
30099(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30100"if ($Qv4) $Vx32.h += $Vu32.h",
30101tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30102let Inst{7-5} = 0b001;
30103let Inst{13-13} = 0b1;
30104let Inst{21-16} = 0b000001;
30105let Inst{31-24} = 0b00011110;
30106let hasNewValue = 1;
30107let opNewValue = 0;
30108let isAccumulator = 1;
30109let isCVI = 1;
30110let DecoderNamespace = "EXT_mmvec";
30111let Constraints = "$Vx32 = $Vx32in";
30112}
30113def V6_vaddhq_alt : HInst<
30114(outs HvxVR:$Vx32),
30115(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30116"if ($Qv4.h) $Vx32.h += $Vu32.h",
30117PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30118let hasNewValue = 1;
30119let opNewValue = 0;
30120let isAccumulator = 1;
30121let isCVI = 1;
30122let isPseudo = 1;
30123let isCodeGenOnly = 1;
30124let DecoderNamespace = "EXT_mmvec";
30125let Constraints = "$Vx32 = $Vx32in";
30126}
30127def V6_vaddhsat : HInst<
30128(outs HvxVR:$Vd32),
30129(ins HvxVR:$Vu32, HvxVR:$Vv32),
30130"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
30131tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30132let Inst{7-5} = 0b011;
30133let Inst{13-13} = 0b0;
30134let Inst{31-21} = 0b00011100010;
30135let hasNewValue = 1;
30136let opNewValue = 0;
30137let isCVI = 1;
30138let DecoderNamespace = "EXT_mmvec";
30139}
30140def V6_vaddhsat_alt : HInst<
30141(outs HvxVR:$Vd32),
30142(ins HvxVR:$Vu32, HvxVR:$Vv32),
30143"$Vd32 = vaddh($Vu32,$Vv32):sat",
30144PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30145let hasNewValue = 1;
30146let opNewValue = 0;
30147let isCVI = 1;
30148let isPseudo = 1;
30149let isCodeGenOnly = 1;
30150let DecoderNamespace = "EXT_mmvec";
30151}
30152def V6_vaddhsat_dv : HInst<
30153(outs HvxWR:$Vdd32),
30154(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30155"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
30156tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30157let Inst{7-5} = 0b001;
30158let Inst{13-13} = 0b0;
30159let Inst{31-21} = 0b00011100100;
30160let hasNewValue = 1;
30161let opNewValue = 0;
30162let isCVI = 1;
30163let DecoderNamespace = "EXT_mmvec";
30164}
30165def V6_vaddhsat_dv_alt : HInst<
30166(outs HvxWR:$Vdd32),
30167(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30168"$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
30169PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30170let hasNewValue = 1;
30171let opNewValue = 0;
30172let isCVI = 1;
30173let isPseudo = 1;
30174let isCodeGenOnly = 1;
30175let DecoderNamespace = "EXT_mmvec";
30176}
30177def V6_vaddhw : HInst<
30178(outs HvxWR:$Vdd32),
30179(ins HvxVR:$Vu32, HvxVR:$Vv32),
30180"$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
30181tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30182let Inst{7-5} = 0b100;
30183let Inst{13-13} = 0b0;
30184let Inst{31-21} = 0b00011100101;
30185let hasNewValue = 1;
30186let opNewValue = 0;
30187let isCVI = 1;
30188let DecoderNamespace = "EXT_mmvec";
30189}
30190def V6_vaddhw_acc : HInst<
30191(outs HvxWR:$Vxx32),
30192(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30193"$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
30194tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30195let Inst{7-5} = 0b010;
30196let Inst{13-13} = 0b1;
30197let Inst{31-21} = 0b00011100001;
30198let hasNewValue = 1;
30199let opNewValue = 0;
30200let isAccumulator = 1;
30201let isCVI = 1;
30202let DecoderNamespace = "EXT_mmvec";
30203let Constraints = "$Vxx32 = $Vxx32in";
30204}
30205def V6_vaddhw_acc_alt : HInst<
30206(outs HvxWR:$Vxx32),
30207(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30208"$Vxx32 += vaddh($Vu32,$Vv32)",
30209PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30210let hasNewValue = 1;
30211let opNewValue = 0;
30212let isAccumulator = 1;
30213let isCVI = 1;
30214let isPseudo = 1;
30215let isCodeGenOnly = 1;
30216let DecoderNamespace = "EXT_mmvec";
30217let Constraints = "$Vxx32 = $Vxx32in";
30218}
30219def V6_vaddhw_alt : HInst<
30220(outs HvxWR:$Vdd32),
30221(ins HvxVR:$Vu32, HvxVR:$Vv32),
30222"$Vdd32 = vaddh($Vu32,$Vv32)",
30223PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30224let hasNewValue = 1;
30225let opNewValue = 0;
30226let isCVI = 1;
30227let isPseudo = 1;
30228let isCodeGenOnly = 1;
30229let DecoderNamespace = "EXT_mmvec";
30230}
30231def V6_vaddubh : HInst<
30232(outs HvxWR:$Vdd32),
30233(ins HvxVR:$Vu32, HvxVR:$Vv32),
30234"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
30235tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30236let Inst{7-5} = 0b010;
30237let Inst{13-13} = 0b0;
30238let Inst{31-21} = 0b00011100101;
30239let hasNewValue = 1;
30240let opNewValue = 0;
30241let isCVI = 1;
30242let DecoderNamespace = "EXT_mmvec";
30243}
30244def V6_vaddubh_acc : HInst<
30245(outs HvxWR:$Vxx32),
30246(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30247"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
30248tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30249let Inst{7-5} = 0b101;
30250let Inst{13-13} = 0b1;
30251let Inst{31-21} = 0b00011100010;
30252let hasNewValue = 1;
30253let opNewValue = 0;
30254let isAccumulator = 1;
30255let isCVI = 1;
30256let DecoderNamespace = "EXT_mmvec";
30257let Constraints = "$Vxx32 = $Vxx32in";
30258}
30259def V6_vaddubh_acc_alt : HInst<
30260(outs HvxWR:$Vxx32),
30261(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30262"$Vxx32 += vaddub($Vu32,$Vv32)",
30263PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30264let hasNewValue = 1;
30265let opNewValue = 0;
30266let isAccumulator = 1;
30267let isCVI = 1;
30268let isPseudo = 1;
30269let isCodeGenOnly = 1;
30270let DecoderNamespace = "EXT_mmvec";
30271let Constraints = "$Vxx32 = $Vxx32in";
30272}
30273def V6_vaddubh_alt : HInst<
30274(outs HvxWR:$Vdd32),
30275(ins HvxVR:$Vu32, HvxVR:$Vv32),
30276"$Vdd32 = vaddub($Vu32,$Vv32)",
30277PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30278let hasNewValue = 1;
30279let opNewValue = 0;
30280let isCVI = 1;
30281let isPseudo = 1;
30282let isCodeGenOnly = 1;
30283let DecoderNamespace = "EXT_mmvec";
30284}
30285def V6_vaddubsat : HInst<
30286(outs HvxVR:$Vd32),
30287(ins HvxVR:$Vu32, HvxVR:$Vv32),
30288"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
30289tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30290let Inst{7-5} = 0b001;
30291let Inst{13-13} = 0b0;
30292let Inst{31-21} = 0b00011100010;
30293let hasNewValue = 1;
30294let opNewValue = 0;
30295let isCVI = 1;
30296let DecoderNamespace = "EXT_mmvec";
30297}
30298def V6_vaddubsat_alt : HInst<
30299(outs HvxVR:$Vd32),
30300(ins HvxVR:$Vu32, HvxVR:$Vv32),
30301"$Vd32 = vaddub($Vu32,$Vv32):sat",
30302PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30303let hasNewValue = 1;
30304let opNewValue = 0;
30305let isCVI = 1;
30306let isPseudo = 1;
30307let isCodeGenOnly = 1;
30308let DecoderNamespace = "EXT_mmvec";
30309}
30310def V6_vaddubsat_dv : HInst<
30311(outs HvxWR:$Vdd32),
30312(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30313"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
30314tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30315let Inst{7-5} = 0b111;
30316let Inst{13-13} = 0b0;
30317let Inst{31-21} = 0b00011100011;
30318let hasNewValue = 1;
30319let opNewValue = 0;
30320let isCVI = 1;
30321let DecoderNamespace = "EXT_mmvec";
30322}
30323def V6_vaddubsat_dv_alt : HInst<
30324(outs HvxWR:$Vdd32),
30325(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30326"$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
30327PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30328let hasNewValue = 1;
30329let opNewValue = 0;
30330let isCVI = 1;
30331let isPseudo = 1;
30332let isCodeGenOnly = 1;
30333let DecoderNamespace = "EXT_mmvec";
30334}
30335def V6_vaddububb_sat : HInst<
30336(outs HvxVR:$Vd32),
30337(ins HvxVR:$Vu32, HvxVR:$Vv32),
30338"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
30339tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30340let Inst{7-5} = 0b100;
30341let Inst{13-13} = 0b0;
30342let Inst{31-21} = 0b00011110101;
30343let hasNewValue = 1;
30344let opNewValue = 0;
30345let isCVI = 1;
30346let DecoderNamespace = "EXT_mmvec";
30347}
30348def V6_vadduhsat : HInst<
30349(outs HvxVR:$Vd32),
30350(ins HvxVR:$Vu32, HvxVR:$Vv32),
30351"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
30352tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30353let Inst{7-5} = 0b010;
30354let Inst{13-13} = 0b0;
30355let Inst{31-21} = 0b00011100010;
30356let hasNewValue = 1;
30357let opNewValue = 0;
30358let isCVI = 1;
30359let DecoderNamespace = "EXT_mmvec";
30360}
30361def V6_vadduhsat_alt : HInst<
30362(outs HvxVR:$Vd32),
30363(ins HvxVR:$Vu32, HvxVR:$Vv32),
30364"$Vd32 = vadduh($Vu32,$Vv32):sat",
30365PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30366let hasNewValue = 1;
30367let opNewValue = 0;
30368let isCVI = 1;
30369let isPseudo = 1;
30370let isCodeGenOnly = 1;
30371let DecoderNamespace = "EXT_mmvec";
30372}
30373def V6_vadduhsat_dv : HInst<
30374(outs HvxWR:$Vdd32),
30375(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30376"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
30377tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30378let Inst{7-5} = 0b000;
30379let Inst{13-13} = 0b0;
30380let Inst{31-21} = 0b00011100100;
30381let hasNewValue = 1;
30382let opNewValue = 0;
30383let isCVI = 1;
30384let DecoderNamespace = "EXT_mmvec";
30385}
30386def V6_vadduhsat_dv_alt : HInst<
30387(outs HvxWR:$Vdd32),
30388(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30389"$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
30390PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30391let hasNewValue = 1;
30392let opNewValue = 0;
30393let isCVI = 1;
30394let isPseudo = 1;
30395let isCodeGenOnly = 1;
30396let DecoderNamespace = "EXT_mmvec";
30397}
30398def V6_vadduhw : HInst<
30399(outs HvxWR:$Vdd32),
30400(ins HvxVR:$Vu32, HvxVR:$Vv32),
30401"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
30402tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30403let Inst{7-5} = 0b011;
30404let Inst{13-13} = 0b0;
30405let Inst{31-21} = 0b00011100101;
30406let hasNewValue = 1;
30407let opNewValue = 0;
30408let isCVI = 1;
30409let DecoderNamespace = "EXT_mmvec";
30410}
30411def V6_vadduhw_acc : HInst<
30412(outs HvxWR:$Vxx32),
30413(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30414"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
30415tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30416let Inst{7-5} = 0b100;
30417let Inst{13-13} = 0b1;
30418let Inst{31-21} = 0b00011100010;
30419let hasNewValue = 1;
30420let opNewValue = 0;
30421let isAccumulator = 1;
30422let isCVI = 1;
30423let DecoderNamespace = "EXT_mmvec";
30424let Constraints = "$Vxx32 = $Vxx32in";
30425}
30426def V6_vadduhw_acc_alt : HInst<
30427(outs HvxWR:$Vxx32),
30428(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30429"$Vxx32 += vadduh($Vu32,$Vv32)",
30430PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30431let hasNewValue = 1;
30432let opNewValue = 0;
30433let isAccumulator = 1;
30434let isCVI = 1;
30435let isPseudo = 1;
30436let isCodeGenOnly = 1;
30437let DecoderNamespace = "EXT_mmvec";
30438let Constraints = "$Vxx32 = $Vxx32in";
30439}
30440def V6_vadduhw_alt : HInst<
30441(outs HvxWR:$Vdd32),
30442(ins HvxVR:$Vu32, HvxVR:$Vv32),
30443"$Vdd32 = vadduh($Vu32,$Vv32)",
30444PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30445let hasNewValue = 1;
30446let opNewValue = 0;
30447let isCVI = 1;
30448let isPseudo = 1;
30449let isCodeGenOnly = 1;
30450let DecoderNamespace = "EXT_mmvec";
30451}
30452def V6_vadduwsat : HInst<
30453(outs HvxVR:$Vd32),
30454(ins HvxVR:$Vu32, HvxVR:$Vv32),
30455"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
30456tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30457let Inst{7-5} = 0b001;
30458let Inst{13-13} = 0b0;
30459let Inst{31-21} = 0b00011111011;
30460let hasNewValue = 1;
30461let opNewValue = 0;
30462let isCVI = 1;
30463let DecoderNamespace = "EXT_mmvec";
30464}
30465def V6_vadduwsat_alt : HInst<
30466(outs HvxVR:$Vd32),
30467(ins HvxVR:$Vu32, HvxVR:$Vv32),
30468"$Vd32 = vadduw($Vu32,$Vv32):sat",
30469PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30470let hasNewValue = 1;
30471let opNewValue = 0;
30472let isCVI = 1;
30473let isPseudo = 1;
30474let isCodeGenOnly = 1;
30475let DecoderNamespace = "EXT_mmvec";
30476}
30477def V6_vadduwsat_dv : HInst<
30478(outs HvxWR:$Vdd32),
30479(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30480"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
30481tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
30482let Inst{7-5} = 0b010;
30483let Inst{13-13} = 0b0;
30484let Inst{31-21} = 0b00011110101;
30485let hasNewValue = 1;
30486let opNewValue = 0;
30487let isCVI = 1;
30488let DecoderNamespace = "EXT_mmvec";
30489}
30490def V6_vadduwsat_dv_alt : HInst<
30491(outs HvxWR:$Vdd32),
30492(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30493"$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
30494PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30495let hasNewValue = 1;
30496let opNewValue = 0;
30497let isCVI = 1;
30498let isPseudo = 1;
30499let isCodeGenOnly = 1;
30500let DecoderNamespace = "EXT_mmvec";
30501}
30502def V6_vaddw : HInst<
30503(outs HvxVR:$Vd32),
30504(ins HvxVR:$Vu32, HvxVR:$Vv32),
30505"$Vd32.w = vadd($Vu32.w,$Vv32.w)",
30506tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30507let Inst{7-5} = 0b000;
30508let Inst{13-13} = 0b0;
30509let Inst{31-21} = 0b00011100010;
30510let hasNewValue = 1;
30511let opNewValue = 0;
30512let isCVI = 1;
30513let DecoderNamespace = "EXT_mmvec";
30514}
30515def V6_vaddw_alt : HInst<
30516(outs HvxVR:$Vd32),
30517(ins HvxVR:$Vu32, HvxVR:$Vv32),
30518"$Vd32 = vaddw($Vu32,$Vv32)",
30519PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30520let hasNewValue = 1;
30521let opNewValue = 0;
30522let isCVI = 1;
30523let isPseudo = 1;
30524let isCodeGenOnly = 1;
30525let DecoderNamespace = "EXT_mmvec";
30526}
30527def V6_vaddw_dv : HInst<
30528(outs HvxWR:$Vdd32),
30529(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30530"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
30531tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30532let Inst{7-5} = 0b110;
30533let Inst{13-13} = 0b0;
30534let Inst{31-21} = 0b00011100011;
30535let hasNewValue = 1;
30536let opNewValue = 0;
30537let isCVI = 1;
30538let DecoderNamespace = "EXT_mmvec";
30539}
30540def V6_vaddw_dv_alt : HInst<
30541(outs HvxWR:$Vdd32),
30542(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30543"$Vdd32 = vaddw($Vuu32,$Vvv32)",
30544PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30545let hasNewValue = 1;
30546let opNewValue = 0;
30547let isCVI = 1;
30548let isPseudo = 1;
30549let isCodeGenOnly = 1;
30550let DecoderNamespace = "EXT_mmvec";
30551}
30552def V6_vaddwnq : HInst<
30553(outs HvxVR:$Vx32),
30554(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30555"if (!$Qv4) $Vx32.w += $Vu32.w",
30556tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30557let Inst{7-5} = 0b101;
30558let Inst{13-13} = 0b1;
30559let Inst{21-16} = 0b000001;
30560let Inst{31-24} = 0b00011110;
30561let hasNewValue = 1;
30562let opNewValue = 0;
30563let isAccumulator = 1;
30564let isCVI = 1;
30565let DecoderNamespace = "EXT_mmvec";
30566let Constraints = "$Vx32 = $Vx32in";
30567}
30568def V6_vaddwnq_alt : HInst<
30569(outs HvxVR:$Vx32),
30570(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30571"if (!$Qv4.w) $Vx32.w += $Vu32.w",
30572PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30573let hasNewValue = 1;
30574let opNewValue = 0;
30575let isAccumulator = 1;
30576let isCVI = 1;
30577let isPseudo = 1;
30578let isCodeGenOnly = 1;
30579let DecoderNamespace = "EXT_mmvec";
30580let Constraints = "$Vx32 = $Vx32in";
30581}
30582def V6_vaddwq : HInst<
30583(outs HvxVR:$Vx32),
30584(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30585"if ($Qv4) $Vx32.w += $Vu32.w",
30586tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30587let Inst{7-5} = 0b010;
30588let Inst{13-13} = 0b1;
30589let Inst{21-16} = 0b000001;
30590let Inst{31-24} = 0b00011110;
30591let hasNewValue = 1;
30592let opNewValue = 0;
30593let isAccumulator = 1;
30594let isCVI = 1;
30595let DecoderNamespace = "EXT_mmvec";
30596let Constraints = "$Vx32 = $Vx32in";
30597}
30598def V6_vaddwq_alt : HInst<
30599(outs HvxVR:$Vx32),
30600(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30601"if ($Qv4.w) $Vx32.w += $Vu32.w",
30602PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30603let hasNewValue = 1;
30604let opNewValue = 0;
30605let isAccumulator = 1;
30606let isCVI = 1;
30607let isPseudo = 1;
30608let isCodeGenOnly = 1;
30609let DecoderNamespace = "EXT_mmvec";
30610let Constraints = "$Vx32 = $Vx32in";
30611}
30612def V6_vaddwsat : HInst<
30613(outs HvxVR:$Vd32),
30614(ins HvxVR:$Vu32, HvxVR:$Vv32),
30615"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
30616tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30617let Inst{7-5} = 0b100;
30618let Inst{13-13} = 0b0;
30619let Inst{31-21} = 0b00011100010;
30620let hasNewValue = 1;
30621let opNewValue = 0;
30622let isCVI = 1;
30623let DecoderNamespace = "EXT_mmvec";
30624}
30625def V6_vaddwsat_alt : HInst<
30626(outs HvxVR:$Vd32),
30627(ins HvxVR:$Vu32, HvxVR:$Vv32),
30628"$Vd32 = vaddw($Vu32,$Vv32):sat",
30629PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30630let hasNewValue = 1;
30631let opNewValue = 0;
30632let isCVI = 1;
30633let isPseudo = 1;
30634let isCodeGenOnly = 1;
30635let DecoderNamespace = "EXT_mmvec";
30636}
30637def V6_vaddwsat_dv : HInst<
30638(outs HvxWR:$Vdd32),
30639(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30640"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
30641tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30642let Inst{7-5} = 0b010;
30643let Inst{13-13} = 0b0;
30644let Inst{31-21} = 0b00011100100;
30645let hasNewValue = 1;
30646let opNewValue = 0;
30647let isCVI = 1;
30648let DecoderNamespace = "EXT_mmvec";
30649}
30650def V6_vaddwsat_dv_alt : HInst<
30651(outs HvxWR:$Vdd32),
30652(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30653"$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
30654PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30655let hasNewValue = 1;
30656let opNewValue = 0;
30657let isCVI = 1;
30658let isPseudo = 1;
30659let isCodeGenOnly = 1;
30660let DecoderNamespace = "EXT_mmvec";
30661}
30662def V6_valignb : HInst<
30663(outs HvxVR:$Vd32),
30664(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30665"$Vd32 = valign($Vu32,$Vv32,$Rt8)",
30666tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
30667let Inst{7-5} = 0b000;
30668let Inst{13-13} = 0b0;
30669let Inst{31-24} = 0b00011011;
30670let hasNewValue = 1;
30671let opNewValue = 0;
30672let isCVI = 1;
30673let DecoderNamespace = "EXT_mmvec";
30674}
30675def V6_valignbi : HInst<
30676(outs HvxVR:$Vd32),
30677(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
30678"$Vd32 = valign($Vu32,$Vv32,#$Ii)",
30679tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
30680let Inst{13-13} = 0b1;
30681let Inst{31-21} = 0b00011110001;
30682let hasNewValue = 1;
30683let opNewValue = 0;
30684let isCVI = 1;
30685let DecoderNamespace = "EXT_mmvec";
30686}
30687def V6_vand : HInst<
30688(outs HvxVR:$Vd32),
30689(ins HvxVR:$Vu32, HvxVR:$Vv32),
30690"$Vd32 = vand($Vu32,$Vv32)",
30691tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30692let Inst{7-5} = 0b101;
30693let Inst{13-13} = 0b0;
30694let Inst{31-21} = 0b00011100001;
30695let hasNewValue = 1;
30696let opNewValue = 0;
30697let isCVI = 1;
30698let DecoderNamespace = "EXT_mmvec";
30699}
30700def V6_vandnqrt : HInst<
30701(outs HvxVR:$Vd32),
30702(ins HvxQR:$Qu4, IntRegs:$Rt32),
30703"$Vd32 = vand(!$Qu4,$Rt32)",
30704tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV62]> {
30705let Inst{7-5} = 0b101;
30706let Inst{13-10} = 0b0001;
30707let Inst{31-21} = 0b00011001101;
30708let hasNewValue = 1;
30709let opNewValue = 0;
30710let isCVI = 1;
30711let DecoderNamespace = "EXT_mmvec";
30712}
30713def V6_vandnqrt_acc : HInst<
30714(outs HvxVR:$Vx32),
30715(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30716"$Vx32 |= vand(!$Qu4,$Rt32)",
30717tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV62]> {
30718let Inst{7-5} = 0b011;
30719let Inst{13-10} = 0b1001;
30720let Inst{31-21} = 0b00011001011;
30721let hasNewValue = 1;
30722let opNewValue = 0;
30723let isAccumulator = 1;
30724let isCVI = 1;
30725let DecoderNamespace = "EXT_mmvec";
30726let Constraints = "$Vx32 = $Vx32in";
30727}
30728def V6_vandnqrt_acc_alt : HInst<
30729(outs HvxVR:$Vx32),
30730(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30731"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
30732PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30733let hasNewValue = 1;
30734let opNewValue = 0;
30735let isAccumulator = 1;
30736let isCVI = 1;
30737let isPseudo = 1;
30738let isCodeGenOnly = 1;
30739let DecoderNamespace = "EXT_mmvec";
30740let Constraints = "$Vx32 = $Vx32in";
30741}
30742def V6_vandnqrt_alt : HInst<
30743(outs HvxVR:$Vd32),
30744(ins HvxQR:$Qu4, IntRegs:$Rt32),
30745"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
30746PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30747let hasNewValue = 1;
30748let opNewValue = 0;
30749let isCVI = 1;
30750let isPseudo = 1;
30751let isCodeGenOnly = 1;
30752let DecoderNamespace = "EXT_mmvec";
30753}
30754def V6_vandqrt : HInst<
30755(outs HvxVR:$Vd32),
30756(ins HvxQR:$Qu4, IntRegs:$Rt32),
30757"$Vd32 = vand($Qu4,$Rt32)",
30758tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
30759let Inst{7-5} = 0b101;
30760let Inst{13-10} = 0b0000;
30761let Inst{31-21} = 0b00011001101;
30762let hasNewValue = 1;
30763let opNewValue = 0;
30764let isCVI = 1;
30765let DecoderNamespace = "EXT_mmvec";
30766}
30767def V6_vandqrt_acc : HInst<
30768(outs HvxVR:$Vx32),
30769(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30770"$Vx32 |= vand($Qu4,$Rt32)",
30771tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
30772let Inst{7-5} = 0b011;
30773let Inst{13-10} = 0b1000;
30774let Inst{31-21} = 0b00011001011;
30775let hasNewValue = 1;
30776let opNewValue = 0;
30777let isAccumulator = 1;
30778let isCVI = 1;
30779let DecoderNamespace = "EXT_mmvec";
30780let Constraints = "$Vx32 = $Vx32in";
30781}
30782def V6_vandqrt_acc_alt : HInst<
30783(outs HvxVR:$Vx32),
30784(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30785"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
30786PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30787let hasNewValue = 1;
30788let opNewValue = 0;
30789let isAccumulator = 1;
30790let isCVI = 1;
30791let isPseudo = 1;
30792let isCodeGenOnly = 1;
30793let DecoderNamespace = "EXT_mmvec";
30794let Constraints = "$Vx32 = $Vx32in";
30795}
30796def V6_vandqrt_alt : HInst<
30797(outs HvxVR:$Vd32),
30798(ins HvxQR:$Qu4, IntRegs:$Rt32),
30799"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
30800PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30801let hasNewValue = 1;
30802let opNewValue = 0;
30803let isCVI = 1;
30804let isPseudo = 1;
30805let isCodeGenOnly = 1;
30806let DecoderNamespace = "EXT_mmvec";
30807}
30808def V6_vandvnqv : HInst<
30809(outs HvxVR:$Vd32),
30810(ins HvxQR:$Qv4, HvxVR:$Vu32),
30811"$Vd32 = vand(!$Qv4,$Vu32)",
30812tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
30813let Inst{7-5} = 0b001;
30814let Inst{13-13} = 0b1;
30815let Inst{21-16} = 0b000011;
30816let Inst{31-24} = 0b00011110;
30817let hasNewValue = 1;
30818let opNewValue = 0;
30819let isCVI = 1;
30820let DecoderNamespace = "EXT_mmvec";
30821}
30822def V6_vandvqv : HInst<
30823(outs HvxVR:$Vd32),
30824(ins HvxQR:$Qv4, HvxVR:$Vu32),
30825"$Vd32 = vand($Qv4,$Vu32)",
30826tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
30827let Inst{7-5} = 0b000;
30828let Inst{13-13} = 0b1;
30829let Inst{21-16} = 0b000011;
30830let Inst{31-24} = 0b00011110;
30831let hasNewValue = 1;
30832let opNewValue = 0;
30833let isCVI = 1;
30834let DecoderNamespace = "EXT_mmvec";
30835}
30836def V6_vandvrt : HInst<
30837(outs HvxQR:$Qd4),
30838(ins HvxVR:$Vu32, IntRegs:$Rt32),
30839"$Qd4 = vand($Vu32,$Rt32)",
30840tc_ac4046bc, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
30841let Inst{7-2} = 0b010010;
30842let Inst{13-13} = 0b0;
30843let Inst{31-21} = 0b00011001101;
30844let hasNewValue = 1;
30845let opNewValue = 0;
30846let isCVI = 1;
30847let DecoderNamespace = "EXT_mmvec";
30848}
30849def V6_vandvrt_acc : HInst<
30850(outs HvxQR:$Qx4),
30851(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
30852"$Qx4 |= vand($Vu32,$Rt32)",
30853tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
30854let Inst{7-2} = 0b100000;
30855let Inst{13-13} = 0b1;
30856let Inst{31-21} = 0b00011001011;
30857let isAccumulator = 1;
30858let isCVI = 1;
30859let DecoderNamespace = "EXT_mmvec";
30860let Constraints = "$Qx4 = $Qx4in";
30861}
30862def V6_vandvrt_acc_alt : HInst<
30863(outs HvxQR:$Qx4),
30864(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
30865"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
30866PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30867let isAccumulator = 1;
30868let isCVI = 1;
30869let isPseudo = 1;
30870let isCodeGenOnly = 1;
30871let DecoderNamespace = "EXT_mmvec";
30872let Constraints = "$Qx4 = $Qx4in";
30873}
30874def V6_vandvrt_alt : HInst<
30875(outs HvxQR:$Qd4),
30876(ins HvxVR:$Vu32, IntRegs:$Rt32),
30877"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
30878PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30879let hasNewValue = 1;
30880let opNewValue = 0;
30881let isCVI = 1;
30882let isPseudo = 1;
30883let isCodeGenOnly = 1;
30884let DecoderNamespace = "EXT_mmvec";
30885}
30886def V6_vaslh : HInst<
30887(outs HvxVR:$Vd32),
30888(ins HvxVR:$Vu32, IntRegs:$Rt32),
30889"$Vd32.h = vasl($Vu32.h,$Rt32)",
30890tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30891let Inst{7-5} = 0b000;
30892let Inst{13-13} = 0b0;
30893let Inst{31-21} = 0b00011001100;
30894let hasNewValue = 1;
30895let opNewValue = 0;
30896let isCVI = 1;
30897let DecoderNamespace = "EXT_mmvec";
30898}
30899def V6_vaslh_acc : HInst<
30900(outs HvxVR:$Vx32),
30901(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30902"$Vx32.h += vasl($Vu32.h,$Rt32)",
30903tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
30904let Inst{7-5} = 0b101;
30905let Inst{13-13} = 0b1;
30906let Inst{31-21} = 0b00011001101;
30907let hasNewValue = 1;
30908let opNewValue = 0;
30909let isAccumulator = 1;
30910let isCVI = 1;
30911let DecoderNamespace = "EXT_mmvec";
30912let Constraints = "$Vx32 = $Vx32in";
30913}
30914def V6_vaslh_acc_alt : HInst<
30915(outs HvxVR:$Vx32),
30916(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30917"$Vx32 += vaslh($Vu32,$Rt32)",
30918PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30919let hasNewValue = 1;
30920let opNewValue = 0;
30921let isAccumulator = 1;
30922let isCVI = 1;
30923let isPseudo = 1;
30924let isCodeGenOnly = 1;
30925let DecoderNamespace = "EXT_mmvec";
30926let Constraints = "$Vx32 = $Vx32in";
30927}
30928def V6_vaslh_alt : HInst<
30929(outs HvxVR:$Vd32),
30930(ins HvxVR:$Vu32, IntRegs:$Rt32),
30931"$Vd32 = vaslh($Vu32,$Rt32)",
30932PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30933let hasNewValue = 1;
30934let opNewValue = 0;
30935let isCVI = 1;
30936let isPseudo = 1;
30937let isCodeGenOnly = 1;
30938let DecoderNamespace = "EXT_mmvec";
30939}
30940def V6_vaslhv : HInst<
30941(outs HvxVR:$Vd32),
30942(ins HvxVR:$Vu32, HvxVR:$Vv32),
30943"$Vd32.h = vasl($Vu32.h,$Vv32.h)",
30944tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30945let Inst{7-5} = 0b101;
30946let Inst{13-13} = 0b0;
30947let Inst{31-21} = 0b00011111101;
30948let hasNewValue = 1;
30949let opNewValue = 0;
30950let isCVI = 1;
30951let DecoderNamespace = "EXT_mmvec";
30952}
30953def V6_vaslhv_alt : HInst<
30954(outs HvxVR:$Vd32),
30955(ins HvxVR:$Vu32, HvxVR:$Vv32),
30956"$Vd32 = vaslh($Vu32,$Vv32)",
30957PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30958let hasNewValue = 1;
30959let opNewValue = 0;
30960let isCVI = 1;
30961let isPseudo = 1;
30962let isCodeGenOnly = 1;
30963let DecoderNamespace = "EXT_mmvec";
30964}
30965def V6_vaslw : HInst<
30966(outs HvxVR:$Vd32),
30967(ins HvxVR:$Vu32, IntRegs:$Rt32),
30968"$Vd32.w = vasl($Vu32.w,$Rt32)",
30969tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30970let Inst{7-5} = 0b111;
30971let Inst{13-13} = 0b0;
30972let Inst{31-21} = 0b00011001011;
30973let hasNewValue = 1;
30974let opNewValue = 0;
30975let isCVI = 1;
30976let DecoderNamespace = "EXT_mmvec";
30977}
30978def V6_vaslw_acc : HInst<
30979(outs HvxVR:$Vx32),
30980(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30981"$Vx32.w += vasl($Vu32.w,$Rt32)",
30982tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
30983let Inst{7-5} = 0b010;
30984let Inst{13-13} = 0b1;
30985let Inst{31-21} = 0b00011001011;
30986let hasNewValue = 1;
30987let opNewValue = 0;
30988let isAccumulator = 1;
30989let isCVI = 1;
30990let DecoderNamespace = "EXT_mmvec";
30991let Constraints = "$Vx32 = $Vx32in";
30992}
30993def V6_vaslw_acc_alt : HInst<
30994(outs HvxVR:$Vx32),
30995(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30996"$Vx32 += vaslw($Vu32,$Rt32)",
30997PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30998let hasNewValue = 1;
30999let opNewValue = 0;
31000let isAccumulator = 1;
31001let isCVI = 1;
31002let isPseudo = 1;
31003let isCodeGenOnly = 1;
31004let DecoderNamespace = "EXT_mmvec";
31005let Constraints = "$Vx32 = $Vx32in";
31006}
31007def V6_vaslw_alt : HInst<
31008(outs HvxVR:$Vd32),
31009(ins HvxVR:$Vu32, IntRegs:$Rt32),
31010"$Vd32 = vaslw($Vu32,$Rt32)",
31011PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31012let hasNewValue = 1;
31013let opNewValue = 0;
31014let isCVI = 1;
31015let isPseudo = 1;
31016let isCodeGenOnly = 1;
31017let DecoderNamespace = "EXT_mmvec";
31018}
31019def V6_vaslwv : HInst<
31020(outs HvxVR:$Vd32),
31021(ins HvxVR:$Vu32, HvxVR:$Vv32),
31022"$Vd32.w = vasl($Vu32.w,$Vv32.w)",
31023tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31024let Inst{7-5} = 0b100;
31025let Inst{13-13} = 0b0;
31026let Inst{31-21} = 0b00011111101;
31027let hasNewValue = 1;
31028let opNewValue = 0;
31029let isCVI = 1;
31030let DecoderNamespace = "EXT_mmvec";
31031}
31032def V6_vaslwv_alt : HInst<
31033(outs HvxVR:$Vd32),
31034(ins HvxVR:$Vu32, HvxVR:$Vv32),
31035"$Vd32 = vaslw($Vu32,$Vv32)",
31036PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31037let hasNewValue = 1;
31038let opNewValue = 0;
31039let isCVI = 1;
31040let isPseudo = 1;
31041let isCodeGenOnly = 1;
31042let DecoderNamespace = "EXT_mmvec";
31043}
31044def V6_vasr_into : HInst<
31045(outs HvxWR:$Vxx32),
31046(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31047"$Vxx32.w = vasrinto($Vu32.w,$Vv32.w)",
31048tc_df80eeb0, TypeCVI_VP_VS>, Enc_3fc427, Requires<[UseHVXV66]> {
31049let Inst{7-5} = 0b111;
31050let Inst{13-13} = 0b1;
31051let Inst{31-21} = 0b00011010101;
31052let hasNewValue = 1;
31053let opNewValue = 0;
31054let isCVI = 1;
31055let DecoderNamespace = "EXT_mmvec";
31056let Constraints = "$Vxx32 = $Vxx32in";
31057}
31058def V6_vasr_into_alt : HInst<
31059(outs HvxWR:$Vxx32),
31060(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31061"$Vxx32 = vasrinto($Vu32,$Vv32)",
31062PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
31063let hasNewValue = 1;
31064let opNewValue = 0;
31065let isCVI = 1;
31066let isPseudo = 1;
31067let isCodeGenOnly = 1;
31068let DecoderNamespace = "EXT_mmvec";
31069let Constraints = "$Vxx32 = $Vxx32in";
31070}
31071def V6_vasrh : HInst<
31072(outs HvxVR:$Vd32),
31073(ins HvxVR:$Vu32, IntRegs:$Rt32),
31074"$Vd32.h = vasr($Vu32.h,$Rt32)",
31075tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31076let Inst{7-5} = 0b110;
31077let Inst{13-13} = 0b0;
31078let Inst{31-21} = 0b00011001011;
31079let hasNewValue = 1;
31080let opNewValue = 0;
31081let isCVI = 1;
31082let DecoderNamespace = "EXT_mmvec";
31083}
31084def V6_vasrh_acc : HInst<
31085(outs HvxVR:$Vx32),
31086(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31087"$Vx32.h += vasr($Vu32.h,$Rt32)",
31088tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31089let Inst{7-5} = 0b111;
31090let Inst{13-13} = 0b1;
31091let Inst{31-21} = 0b00011001100;
31092let hasNewValue = 1;
31093let opNewValue = 0;
31094let isAccumulator = 1;
31095let isCVI = 1;
31096let DecoderNamespace = "EXT_mmvec";
31097let Constraints = "$Vx32 = $Vx32in";
31098}
31099def V6_vasrh_acc_alt : HInst<
31100(outs HvxVR:$Vx32),
31101(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31102"$Vx32 += vasrh($Vu32,$Rt32)",
31103PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31104let hasNewValue = 1;
31105let opNewValue = 0;
31106let isAccumulator = 1;
31107let isCVI = 1;
31108let isPseudo = 1;
31109let isCodeGenOnly = 1;
31110let DecoderNamespace = "EXT_mmvec";
31111let Constraints = "$Vx32 = $Vx32in";
31112}
31113def V6_vasrh_alt : HInst<
31114(outs HvxVR:$Vd32),
31115(ins HvxVR:$Vu32, IntRegs:$Rt32),
31116"$Vd32 = vasrh($Vu32,$Rt32)",
31117PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31118let hasNewValue = 1;
31119let opNewValue = 0;
31120let isCVI = 1;
31121let isPseudo = 1;
31122let isCodeGenOnly = 1;
31123let DecoderNamespace = "EXT_mmvec";
31124}
31125def V6_vasrhbrndsat : HInst<
31126(outs HvxVR:$Vd32),
31127(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31128"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31129tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31130let Inst{7-5} = 0b000;
31131let Inst{13-13} = 0b1;
31132let Inst{31-24} = 0b00011011;
31133let hasNewValue = 1;
31134let opNewValue = 0;
31135let isCVI = 1;
31136let DecoderNamespace = "EXT_mmvec";
31137}
31138def V6_vasrhbsat : HInst<
31139(outs HvxVR:$Vd32),
31140(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31141"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31142tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31143let Inst{7-5} = 0b000;
31144let Inst{13-13} = 0b0;
31145let Inst{31-24} = 0b00011000;
31146let hasNewValue = 1;
31147let opNewValue = 0;
31148let isCVI = 1;
31149let DecoderNamespace = "EXT_mmvec";
31150}
31151def V6_vasrhubrndsat : HInst<
31152(outs HvxVR:$Vd32),
31153(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31154"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31155tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31156let Inst{7-5} = 0b111;
31157let Inst{13-13} = 0b0;
31158let Inst{31-24} = 0b00011011;
31159let hasNewValue = 1;
31160let opNewValue = 0;
31161let isCVI = 1;
31162let DecoderNamespace = "EXT_mmvec";
31163}
31164def V6_vasrhubsat : HInst<
31165(outs HvxVR:$Vd32),
31166(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31167"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31168tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31169let Inst{7-5} = 0b110;
31170let Inst{13-13} = 0b0;
31171let Inst{31-24} = 0b00011011;
31172let hasNewValue = 1;
31173let opNewValue = 0;
31174let isCVI = 1;
31175let DecoderNamespace = "EXT_mmvec";
31176}
31177def V6_vasrhv : HInst<
31178(outs HvxVR:$Vd32),
31179(ins HvxVR:$Vu32, HvxVR:$Vv32),
31180"$Vd32.h = vasr($Vu32.h,$Vv32.h)",
31181tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31182let Inst{7-5} = 0b011;
31183let Inst{13-13} = 0b0;
31184let Inst{31-21} = 0b00011111101;
31185let hasNewValue = 1;
31186let opNewValue = 0;
31187let isCVI = 1;
31188let DecoderNamespace = "EXT_mmvec";
31189}
31190def V6_vasrhv_alt : HInst<
31191(outs HvxVR:$Vd32),
31192(ins HvxVR:$Vu32, HvxVR:$Vv32),
31193"$Vd32 = vasrh($Vu32,$Vv32)",
31194PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31195let hasNewValue = 1;
31196let opNewValue = 0;
31197let isCVI = 1;
31198let isPseudo = 1;
31199let isCodeGenOnly = 1;
31200let DecoderNamespace = "EXT_mmvec";
31201}
31202def V6_vasruhubrndsat : HInst<
31203(outs HvxVR:$Vd32),
31204(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31205"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
31206tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31207let Inst{7-5} = 0b111;
31208let Inst{13-13} = 0b0;
31209let Inst{31-24} = 0b00011000;
31210let hasNewValue = 1;
31211let opNewValue = 0;
31212let isCVI = 1;
31213let DecoderNamespace = "EXT_mmvec";
31214}
31215def V6_vasruhubsat : HInst<
31216(outs HvxVR:$Vd32),
31217(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31218"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
31219tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31220let Inst{7-5} = 0b101;
31221let Inst{13-13} = 0b1;
31222let Inst{31-24} = 0b00011000;
31223let hasNewValue = 1;
31224let opNewValue = 0;
31225let isCVI = 1;
31226let DecoderNamespace = "EXT_mmvec";
31227}
31228def V6_vasruwuhrndsat : HInst<
31229(outs HvxVR:$Vd32),
31230(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31231"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
31232tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31233let Inst{7-5} = 0b001;
31234let Inst{13-13} = 0b0;
31235let Inst{31-24} = 0b00011000;
31236let hasNewValue = 1;
31237let opNewValue = 0;
31238let isCVI = 1;
31239let DecoderNamespace = "EXT_mmvec";
31240}
31241def V6_vasruwuhsat : HInst<
31242(outs HvxVR:$Vd32),
31243(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31244"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
31245tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31246let Inst{7-5} = 0b100;
31247let Inst{13-13} = 0b1;
31248let Inst{31-24} = 0b00011000;
31249let hasNewValue = 1;
31250let opNewValue = 0;
31251let isCVI = 1;
31252let DecoderNamespace = "EXT_mmvec";
31253}
31254def V6_vasrw : HInst<
31255(outs HvxVR:$Vd32),
31256(ins HvxVR:$Vu32, IntRegs:$Rt32),
31257"$Vd32.w = vasr($Vu32.w,$Rt32)",
31258tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31259let Inst{7-5} = 0b101;
31260let Inst{13-13} = 0b0;
31261let Inst{31-21} = 0b00011001011;
31262let hasNewValue = 1;
31263let opNewValue = 0;
31264let isCVI = 1;
31265let DecoderNamespace = "EXT_mmvec";
31266}
31267def V6_vasrw_acc : HInst<
31268(outs HvxVR:$Vx32),
31269(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31270"$Vx32.w += vasr($Vu32.w,$Rt32)",
31271tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31272let Inst{7-5} = 0b101;
31273let Inst{13-13} = 0b1;
31274let Inst{31-21} = 0b00011001011;
31275let hasNewValue = 1;
31276let opNewValue = 0;
31277let isAccumulator = 1;
31278let isCVI = 1;
31279let DecoderNamespace = "EXT_mmvec";
31280let Constraints = "$Vx32 = $Vx32in";
31281}
31282def V6_vasrw_acc_alt : HInst<
31283(outs HvxVR:$Vx32),
31284(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31285"$Vx32 += vasrw($Vu32,$Rt32)",
31286PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31287let hasNewValue = 1;
31288let opNewValue = 0;
31289let isAccumulator = 1;
31290let isCVI = 1;
31291let isPseudo = 1;
31292let isCodeGenOnly = 1;
31293let DecoderNamespace = "EXT_mmvec";
31294let Constraints = "$Vx32 = $Vx32in";
31295}
31296def V6_vasrw_alt : HInst<
31297(outs HvxVR:$Vd32),
31298(ins HvxVR:$Vu32, IntRegs:$Rt32),
31299"$Vd32 = vasrw($Vu32,$Rt32)",
31300PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31301let hasNewValue = 1;
31302let opNewValue = 0;
31303let isCVI = 1;
31304let isPseudo = 1;
31305let isCodeGenOnly = 1;
31306let DecoderNamespace = "EXT_mmvec";
31307}
31308def V6_vasrwh : HInst<
31309(outs HvxVR:$Vd32),
31310(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31311"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
31312tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31313let Inst{7-5} = 0b010;
31314let Inst{13-13} = 0b0;
31315let Inst{31-24} = 0b00011011;
31316let hasNewValue = 1;
31317let opNewValue = 0;
31318let isCVI = 1;
31319let DecoderNamespace = "EXT_mmvec";
31320}
31321def V6_vasrwhrndsat : HInst<
31322(outs HvxVR:$Vd32),
31323(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31324"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31325tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31326let Inst{7-5} = 0b100;
31327let Inst{13-13} = 0b0;
31328let Inst{31-24} = 0b00011011;
31329let hasNewValue = 1;
31330let opNewValue = 0;
31331let isCVI = 1;
31332let DecoderNamespace = "EXT_mmvec";
31333}
31334def V6_vasrwhsat : HInst<
31335(outs HvxVR:$Vd32),
31336(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31337"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31338tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31339let Inst{7-5} = 0b011;
31340let Inst{13-13} = 0b0;
31341let Inst{31-24} = 0b00011011;
31342let hasNewValue = 1;
31343let opNewValue = 0;
31344let isCVI = 1;
31345let DecoderNamespace = "EXT_mmvec";
31346}
31347def V6_vasrwuhrndsat : HInst<
31348(outs HvxVR:$Vd32),
31349(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31350"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31351tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31352let Inst{7-5} = 0b010;
31353let Inst{13-13} = 0b0;
31354let Inst{31-24} = 0b00011000;
31355let hasNewValue = 1;
31356let opNewValue = 0;
31357let isCVI = 1;
31358let DecoderNamespace = "EXT_mmvec";
31359}
31360def V6_vasrwuhsat : HInst<
31361(outs HvxVR:$Vd32),
31362(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31363"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31364tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31365let Inst{7-5} = 0b101;
31366let Inst{13-13} = 0b0;
31367let Inst{31-24} = 0b00011011;
31368let hasNewValue = 1;
31369let opNewValue = 0;
31370let isCVI = 1;
31371let DecoderNamespace = "EXT_mmvec";
31372}
31373def V6_vasrwv : HInst<
31374(outs HvxVR:$Vd32),
31375(ins HvxVR:$Vu32, HvxVR:$Vv32),
31376"$Vd32.w = vasr($Vu32.w,$Vv32.w)",
31377tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31378let Inst{7-5} = 0b000;
31379let Inst{13-13} = 0b0;
31380let Inst{31-21} = 0b00011111101;
31381let hasNewValue = 1;
31382let opNewValue = 0;
31383let isCVI = 1;
31384let DecoderNamespace = "EXT_mmvec";
31385}
31386def V6_vasrwv_alt : HInst<
31387(outs HvxVR:$Vd32),
31388(ins HvxVR:$Vu32, HvxVR:$Vv32),
31389"$Vd32 = vasrw($Vu32,$Vv32)",
31390PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31391let hasNewValue = 1;
31392let opNewValue = 0;
31393let isCVI = 1;
31394let isPseudo = 1;
31395let isCodeGenOnly = 1;
31396let DecoderNamespace = "EXT_mmvec";
31397}
31398def V6_vassign : HInst<
31399(outs HvxVR:$Vd32),
31400(ins HvxVR:$Vu32),
31401"$Vd32 = $Vu32",
31402tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
31403let Inst{7-5} = 0b111;
31404let Inst{13-13} = 0b1;
31405let Inst{31-16} = 0b0001111000000011;
31406let hasNewValue = 1;
31407let opNewValue = 0;
31408let isCVI = 1;
31409let DecoderNamespace = "EXT_mmvec";
31410}
31411def V6_vassignp : HInst<
31412(outs HvxWR:$Vdd32),
31413(ins HvxWR:$Vuu32),
31414"$Vdd32 = $Vuu32",
31415CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
31416let hasNewValue = 1;
31417let opNewValue = 0;
31418let isCVI = 1;
31419let isPseudo = 1;
31420let DecoderNamespace = "EXT_mmvec";
31421}
31422def V6_vavgb : HInst<
31423(outs HvxVR:$Vd32),
31424(ins HvxVR:$Vu32, HvxVR:$Vv32),
31425"$Vd32.b = vavg($Vu32.b,$Vv32.b)",
31426tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31427let Inst{7-5} = 0b100;
31428let Inst{13-13} = 0b1;
31429let Inst{31-21} = 0b00011111000;
31430let hasNewValue = 1;
31431let opNewValue = 0;
31432let isCVI = 1;
31433let DecoderNamespace = "EXT_mmvec";
31434}
31435def V6_vavgb_alt : HInst<
31436(outs HvxVR:$Vd32),
31437(ins HvxVR:$Vu32, HvxVR:$Vv32),
31438"$Vd32 = vavgb($Vu32,$Vv32)",
31439PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31440let hasNewValue = 1;
31441let opNewValue = 0;
31442let isCVI = 1;
31443let isPseudo = 1;
31444let isCodeGenOnly = 1;
31445let DecoderNamespace = "EXT_mmvec";
31446}
31447def V6_vavgbrnd : HInst<
31448(outs HvxVR:$Vd32),
31449(ins HvxVR:$Vu32, HvxVR:$Vv32),
31450"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
31451tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31452let Inst{7-5} = 0b101;
31453let Inst{13-13} = 0b1;
31454let Inst{31-21} = 0b00011111000;
31455let hasNewValue = 1;
31456let opNewValue = 0;
31457let isCVI = 1;
31458let DecoderNamespace = "EXT_mmvec";
31459}
31460def V6_vavgbrnd_alt : HInst<
31461(outs HvxVR:$Vd32),
31462(ins HvxVR:$Vu32, HvxVR:$Vv32),
31463"$Vd32 = vavgb($Vu32,$Vv32):rnd",
31464PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31465let hasNewValue = 1;
31466let opNewValue = 0;
31467let isCVI = 1;
31468let isPseudo = 1;
31469let isCodeGenOnly = 1;
31470let DecoderNamespace = "EXT_mmvec";
31471}
31472def V6_vavgh : HInst<
31473(outs HvxVR:$Vd32),
31474(ins HvxVR:$Vu32, HvxVR:$Vv32),
31475"$Vd32.h = vavg($Vu32.h,$Vv32.h)",
31476tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31477let Inst{7-5} = 0b110;
31478let Inst{13-13} = 0b0;
31479let Inst{31-21} = 0b00011100110;
31480let hasNewValue = 1;
31481let opNewValue = 0;
31482let isCVI = 1;
31483let DecoderNamespace = "EXT_mmvec";
31484}
31485def V6_vavgh_alt : HInst<
31486(outs HvxVR:$Vd32),
31487(ins HvxVR:$Vu32, HvxVR:$Vv32),
31488"$Vd32 = vavgh($Vu32,$Vv32)",
31489PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31490let hasNewValue = 1;
31491let opNewValue = 0;
31492let isCVI = 1;
31493let isPseudo = 1;
31494let isCodeGenOnly = 1;
31495let DecoderNamespace = "EXT_mmvec";
31496}
31497def V6_vavghrnd : HInst<
31498(outs HvxVR:$Vd32),
31499(ins HvxVR:$Vu32, HvxVR:$Vv32),
31500"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
31501tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31502let Inst{7-5} = 0b101;
31503let Inst{13-13} = 0b0;
31504let Inst{31-21} = 0b00011100111;
31505let hasNewValue = 1;
31506let opNewValue = 0;
31507let isCVI = 1;
31508let DecoderNamespace = "EXT_mmvec";
31509}
31510def V6_vavghrnd_alt : HInst<
31511(outs HvxVR:$Vd32),
31512(ins HvxVR:$Vu32, HvxVR:$Vv32),
31513"$Vd32 = vavgh($Vu32,$Vv32):rnd",
31514PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31515let hasNewValue = 1;
31516let opNewValue = 0;
31517let isCVI = 1;
31518let isPseudo = 1;
31519let isCodeGenOnly = 1;
31520let DecoderNamespace = "EXT_mmvec";
31521}
31522def V6_vavgub : HInst<
31523(outs HvxVR:$Vd32),
31524(ins HvxVR:$Vu32, HvxVR:$Vv32),
31525"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
31526tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31527let Inst{7-5} = 0b100;
31528let Inst{13-13} = 0b0;
31529let Inst{31-21} = 0b00011100110;
31530let hasNewValue = 1;
31531let opNewValue = 0;
31532let isCVI = 1;
31533let DecoderNamespace = "EXT_mmvec";
31534}
31535def V6_vavgub_alt : HInst<
31536(outs HvxVR:$Vd32),
31537(ins HvxVR:$Vu32, HvxVR:$Vv32),
31538"$Vd32 = vavgub($Vu32,$Vv32)",
31539PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31540let hasNewValue = 1;
31541let opNewValue = 0;
31542let isCVI = 1;
31543let isPseudo = 1;
31544let isCodeGenOnly = 1;
31545let DecoderNamespace = "EXT_mmvec";
31546}
31547def V6_vavgubrnd : HInst<
31548(outs HvxVR:$Vd32),
31549(ins HvxVR:$Vu32, HvxVR:$Vv32),
31550"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
31551tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31552let Inst{7-5} = 0b011;
31553let Inst{13-13} = 0b0;
31554let Inst{31-21} = 0b00011100111;
31555let hasNewValue = 1;
31556let opNewValue = 0;
31557let isCVI = 1;
31558let DecoderNamespace = "EXT_mmvec";
31559}
31560def V6_vavgubrnd_alt : HInst<
31561(outs HvxVR:$Vd32),
31562(ins HvxVR:$Vu32, HvxVR:$Vv32),
31563"$Vd32 = vavgub($Vu32,$Vv32):rnd",
31564PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31565let hasNewValue = 1;
31566let opNewValue = 0;
31567let isCVI = 1;
31568let isPseudo = 1;
31569let isCodeGenOnly = 1;
31570let DecoderNamespace = "EXT_mmvec";
31571}
31572def V6_vavguh : HInst<
31573(outs HvxVR:$Vd32),
31574(ins HvxVR:$Vu32, HvxVR:$Vv32),
31575"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
31576tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31577let Inst{7-5} = 0b101;
31578let Inst{13-13} = 0b0;
31579let Inst{31-21} = 0b00011100110;
31580let hasNewValue = 1;
31581let opNewValue = 0;
31582let isCVI = 1;
31583let DecoderNamespace = "EXT_mmvec";
31584}
31585def V6_vavguh_alt : HInst<
31586(outs HvxVR:$Vd32),
31587(ins HvxVR:$Vu32, HvxVR:$Vv32),
31588"$Vd32 = vavguh($Vu32,$Vv32)",
31589PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31590let hasNewValue = 1;
31591let opNewValue = 0;
31592let isCVI = 1;
31593let isPseudo = 1;
31594let isCodeGenOnly = 1;
31595let DecoderNamespace = "EXT_mmvec";
31596}
31597def V6_vavguhrnd : HInst<
31598(outs HvxVR:$Vd32),
31599(ins HvxVR:$Vu32, HvxVR:$Vv32),
31600"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
31601tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31602let Inst{7-5} = 0b100;
31603let Inst{13-13} = 0b0;
31604let Inst{31-21} = 0b00011100111;
31605let hasNewValue = 1;
31606let opNewValue = 0;
31607let isCVI = 1;
31608let DecoderNamespace = "EXT_mmvec";
31609}
31610def V6_vavguhrnd_alt : HInst<
31611(outs HvxVR:$Vd32),
31612(ins HvxVR:$Vu32, HvxVR:$Vv32),
31613"$Vd32 = vavguh($Vu32,$Vv32):rnd",
31614PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31615let hasNewValue = 1;
31616let opNewValue = 0;
31617let isCVI = 1;
31618let isPseudo = 1;
31619let isCodeGenOnly = 1;
31620let DecoderNamespace = "EXT_mmvec";
31621}
31622def V6_vavguw : HInst<
31623(outs HvxVR:$Vd32),
31624(ins HvxVR:$Vu32, HvxVR:$Vv32),
31625"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
31626tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31627let Inst{7-5} = 0b010;
31628let Inst{13-13} = 0b1;
31629let Inst{31-21} = 0b00011111000;
31630let hasNewValue = 1;
31631let opNewValue = 0;
31632let isCVI = 1;
31633let DecoderNamespace = "EXT_mmvec";
31634}
31635def V6_vavguw_alt : HInst<
31636(outs HvxVR:$Vd32),
31637(ins HvxVR:$Vu32, HvxVR:$Vv32),
31638"$Vd32 = vavguw($Vu32,$Vv32)",
31639PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31640let hasNewValue = 1;
31641let opNewValue = 0;
31642let isCVI = 1;
31643let isPseudo = 1;
31644let isCodeGenOnly = 1;
31645let DecoderNamespace = "EXT_mmvec";
31646}
31647def V6_vavguwrnd : HInst<
31648(outs HvxVR:$Vd32),
31649(ins HvxVR:$Vu32, HvxVR:$Vv32),
31650"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
31651tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31652let Inst{7-5} = 0b011;
31653let Inst{13-13} = 0b1;
31654let Inst{31-21} = 0b00011111000;
31655let hasNewValue = 1;
31656let opNewValue = 0;
31657let isCVI = 1;
31658let DecoderNamespace = "EXT_mmvec";
31659}
31660def V6_vavguwrnd_alt : HInst<
31661(outs HvxVR:$Vd32),
31662(ins HvxVR:$Vu32, HvxVR:$Vv32),
31663"$Vd32 = vavguw($Vu32,$Vv32):rnd",
31664PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31665let hasNewValue = 1;
31666let opNewValue = 0;
31667let isCVI = 1;
31668let isPseudo = 1;
31669let isCodeGenOnly = 1;
31670let DecoderNamespace = "EXT_mmvec";
31671}
31672def V6_vavgw : HInst<
31673(outs HvxVR:$Vd32),
31674(ins HvxVR:$Vu32, HvxVR:$Vv32),
31675"$Vd32.w = vavg($Vu32.w,$Vv32.w)",
31676tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31677let Inst{7-5} = 0b111;
31678let Inst{13-13} = 0b0;
31679let Inst{31-21} = 0b00011100110;
31680let hasNewValue = 1;
31681let opNewValue = 0;
31682let isCVI = 1;
31683let DecoderNamespace = "EXT_mmvec";
31684}
31685def V6_vavgw_alt : HInst<
31686(outs HvxVR:$Vd32),
31687(ins HvxVR:$Vu32, HvxVR:$Vv32),
31688"$Vd32 = vavgw($Vu32,$Vv32)",
31689PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31690let hasNewValue = 1;
31691let opNewValue = 0;
31692let isCVI = 1;
31693let isPseudo = 1;
31694let isCodeGenOnly = 1;
31695let DecoderNamespace = "EXT_mmvec";
31696}
31697def V6_vavgwrnd : HInst<
31698(outs HvxVR:$Vd32),
31699(ins HvxVR:$Vu32, HvxVR:$Vv32),
31700"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
31701tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31702let Inst{7-5} = 0b110;
31703let Inst{13-13} = 0b0;
31704let Inst{31-21} = 0b00011100111;
31705let hasNewValue = 1;
31706let opNewValue = 0;
31707let isCVI = 1;
31708let DecoderNamespace = "EXT_mmvec";
31709}
31710def V6_vavgwrnd_alt : HInst<
31711(outs HvxVR:$Vd32),
31712(ins HvxVR:$Vu32, HvxVR:$Vv32),
31713"$Vd32 = vavgw($Vu32,$Vv32):rnd",
31714PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31715let hasNewValue = 1;
31716let opNewValue = 0;
31717let isCVI = 1;
31718let isPseudo = 1;
31719let isCodeGenOnly = 1;
31720let DecoderNamespace = "EXT_mmvec";
31721}
31722def V6_vccombine : HInst<
31723(outs HvxWR:$Vdd32),
31724(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
31725"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
31726tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
31727let Inst{7-7} = 0b0;
31728let Inst{13-13} = 0b0;
31729let Inst{31-21} = 0b00011010011;
31730let isPredicated = 1;
31731let hasNewValue = 1;
31732let opNewValue = 0;
31733let isCVI = 1;
31734let DecoderNamespace = "EXT_mmvec";
31735}
31736def V6_vcl0h : HInst<
31737(outs HvxVR:$Vd32),
31738(ins HvxVR:$Vu32),
31739"$Vd32.uh = vcl0($Vu32.uh)",
31740tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
31741let Inst{7-5} = 0b111;
31742let Inst{13-13} = 0b0;
31743let Inst{31-16} = 0b0001111000000010;
31744let hasNewValue = 1;
31745let opNewValue = 0;
31746let isCVI = 1;
31747let DecoderNamespace = "EXT_mmvec";
31748}
31749def V6_vcl0h_alt : HInst<
31750(outs HvxVR:$Vd32),
31751(ins HvxVR:$Vu32),
31752"$Vd32 = vcl0h($Vu32)",
31753PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31754let hasNewValue = 1;
31755let opNewValue = 0;
31756let isCVI = 1;
31757let isPseudo = 1;
31758let isCodeGenOnly = 1;
31759let DecoderNamespace = "EXT_mmvec";
31760}
31761def V6_vcl0w : HInst<
31762(outs HvxVR:$Vd32),
31763(ins HvxVR:$Vu32),
31764"$Vd32.uw = vcl0($Vu32.uw)",
31765tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
31766let Inst{7-5} = 0b101;
31767let Inst{13-13} = 0b0;
31768let Inst{31-16} = 0b0001111000000010;
31769let hasNewValue = 1;
31770let opNewValue = 0;
31771let isCVI = 1;
31772let DecoderNamespace = "EXT_mmvec";
31773}
31774def V6_vcl0w_alt : HInst<
31775(outs HvxVR:$Vd32),
31776(ins HvxVR:$Vu32),
31777"$Vd32 = vcl0w($Vu32)",
31778PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31779let hasNewValue = 1;
31780let opNewValue = 0;
31781let isCVI = 1;
31782let isPseudo = 1;
31783let isCodeGenOnly = 1;
31784let DecoderNamespace = "EXT_mmvec";
31785}
31786def V6_vcmov : HInst<
31787(outs HvxVR:$Vd32),
31788(ins PredRegs:$Ps4, HvxVR:$Vu32),
31789"if ($Ps4) $Vd32 = $Vu32",
31790tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
31791let Inst{7-7} = 0b0;
31792let Inst{13-13} = 0b0;
31793let Inst{31-16} = 0b0001101000000000;
31794let isPredicated = 1;
31795let hasNewValue = 1;
31796let opNewValue = 0;
31797let isCVI = 1;
31798let DecoderNamespace = "EXT_mmvec";
31799}
31800def V6_vcombine : HInst<
31801(outs HvxWR:$Vdd32),
31802(ins HvxVR:$Vu32, HvxVR:$Vv32),
31803"$Vdd32 = vcombine($Vu32,$Vv32)",
31804tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
31805let Inst{7-5} = 0b111;
31806let Inst{13-13} = 0b0;
31807let Inst{31-21} = 0b00011111010;
31808let hasNewValue = 1;
31809let opNewValue = 0;
31810let isCVI = 1;
31811let isRegSequence = 1;
31812let DecoderNamespace = "EXT_mmvec";
31813}
31814def V6_vd0 : HInst<
31815(outs HvxVR:$Vd32),
31816(ins),
31817"$Vd32 = #0",
31818CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
31819let hasNewValue = 1;
31820let opNewValue = 0;
31821let isCVI = 1;
31822let isPseudo = 1;
31823let isCodeGenOnly = 1;
31824let DecoderNamespace = "EXT_mmvec";
31825}
31826def V6_vdd0 : HInst<
31827(outs HvxWR:$Vdd32),
31828(ins),
31829"$Vdd32 = #0",
31830tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> {
31831let hasNewValue = 1;
31832let opNewValue = 0;
31833let isCVI = 1;
31834let isPseudo = 1;
31835let isCodeGenOnly = 1;
31836let DecoderNamespace = "EXT_mmvec";
31837}
31838def V6_vdeal : HInst<
31839(outs HvxVR:$Vy32, HvxVR:$Vx32),
31840(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
31841"vdeal($Vy32,$Vx32,$Rt32)",
31842tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
31843let Inst{7-5} = 0b010;
31844let Inst{13-13} = 0b1;
31845let Inst{31-21} = 0b00011001111;
31846let hasNewValue = 1;
31847let opNewValue = 0;
31848let hasNewValue2 = 1;
31849let opNewValue2 = 1;
31850let isCVI = 1;
31851let DecoderNamespace = "EXT_mmvec";
31852let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
31853}
31854def V6_vdealb : HInst<
31855(outs HvxVR:$Vd32),
31856(ins HvxVR:$Vu32),
31857"$Vd32.b = vdeal($Vu32.b)",
31858tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
31859let Inst{7-5} = 0b111;
31860let Inst{13-13} = 0b0;
31861let Inst{31-16} = 0b0001111000000000;
31862let hasNewValue = 1;
31863let opNewValue = 0;
31864let isCVI = 1;
31865let DecoderNamespace = "EXT_mmvec";
31866}
31867def V6_vdealb4w : HInst<
31868(outs HvxVR:$Vd32),
31869(ins HvxVR:$Vu32, HvxVR:$Vv32),
31870"$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
31871tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
31872let Inst{7-5} = 0b111;
31873let Inst{13-13} = 0b0;
31874let Inst{31-21} = 0b00011111001;
31875let hasNewValue = 1;
31876let opNewValue = 0;
31877let isCVI = 1;
31878let DecoderNamespace = "EXT_mmvec";
31879}
31880def V6_vdealb4w_alt : HInst<
31881(outs HvxVR:$Vd32),
31882(ins HvxVR:$Vu32, HvxVR:$Vv32),
31883"$Vd32 = vdealb4w($Vu32,$Vv32)",
31884PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31885let hasNewValue = 1;
31886let opNewValue = 0;
31887let isCVI = 1;
31888let isPseudo = 1;
31889let isCodeGenOnly = 1;
31890let DecoderNamespace = "EXT_mmvec";
31891}
31892def V6_vdealb_alt : HInst<
31893(outs HvxVR:$Vd32),
31894(ins HvxVR:$Vu32),
31895"$Vd32 = vdealb($Vu32)",
31896PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31897let hasNewValue = 1;
31898let opNewValue = 0;
31899let isCVI = 1;
31900let isPseudo = 1;
31901let isCodeGenOnly = 1;
31902let DecoderNamespace = "EXT_mmvec";
31903}
31904def V6_vdealh : HInst<
31905(outs HvxVR:$Vd32),
31906(ins HvxVR:$Vu32),
31907"$Vd32.h = vdeal($Vu32.h)",
31908tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
31909let Inst{7-5} = 0b110;
31910let Inst{13-13} = 0b0;
31911let Inst{31-16} = 0b0001111000000000;
31912let hasNewValue = 1;
31913let opNewValue = 0;
31914let isCVI = 1;
31915let DecoderNamespace = "EXT_mmvec";
31916}
31917def V6_vdealh_alt : HInst<
31918(outs HvxVR:$Vd32),
31919(ins HvxVR:$Vu32),
31920"$Vd32 = vdealh($Vu32)",
31921PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31922let hasNewValue = 1;
31923let opNewValue = 0;
31924let isCVI = 1;
31925let isPseudo = 1;
31926let isCodeGenOnly = 1;
31927let DecoderNamespace = "EXT_mmvec";
31928}
31929def V6_vdealvdd : HInst<
31930(outs HvxWR:$Vdd32),
31931(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31932"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
31933tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
31934let Inst{7-5} = 0b100;
31935let Inst{13-13} = 0b1;
31936let Inst{31-24} = 0b00011011;
31937let hasNewValue = 1;
31938let opNewValue = 0;
31939let isCVI = 1;
31940let DecoderNamespace = "EXT_mmvec";
31941}
31942def V6_vdelta : HInst<
31943(outs HvxVR:$Vd32),
31944(ins HvxVR:$Vu32, HvxVR:$Vv32),
31945"$Vd32 = vdelta($Vu32,$Vv32)",
31946tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
31947let Inst{7-5} = 0b001;
31948let Inst{13-13} = 0b0;
31949let Inst{31-21} = 0b00011111001;
31950let hasNewValue = 1;
31951let opNewValue = 0;
31952let isCVI = 1;
31953let DecoderNamespace = "EXT_mmvec";
31954}
31955def V6_vdmpybus : HInst<
31956(outs HvxVR:$Vd32),
31957(ins HvxVR:$Vu32, IntRegs:$Rt32),
31958"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
31959tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
31960let Inst{7-5} = 0b110;
31961let Inst{13-13} = 0b0;
31962let Inst{31-21} = 0b00011001000;
31963let hasNewValue = 1;
31964let opNewValue = 0;
31965let isCVI = 1;
31966let DecoderNamespace = "EXT_mmvec";
31967}
31968def V6_vdmpybus_acc : HInst<
31969(outs HvxVR:$Vx32),
31970(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31971"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
31972tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
31973let Inst{7-5} = 0b110;
31974let Inst{13-13} = 0b1;
31975let Inst{31-21} = 0b00011001000;
31976let hasNewValue = 1;
31977let opNewValue = 0;
31978let isAccumulator = 1;
31979let isCVI = 1;
31980let DecoderNamespace = "EXT_mmvec";
31981let Constraints = "$Vx32 = $Vx32in";
31982}
31983def V6_vdmpybus_acc_alt : HInst<
31984(outs HvxVR:$Vx32),
31985(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31986"$Vx32 += vdmpybus($Vu32,$Rt32)",
31987PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31988let hasNewValue = 1;
31989let opNewValue = 0;
31990let isAccumulator = 1;
31991let isCVI = 1;
31992let isPseudo = 1;
31993let isCodeGenOnly = 1;
31994let DecoderNamespace = "EXT_mmvec";
31995let Constraints = "$Vx32 = $Vx32in";
31996}
31997def V6_vdmpybus_alt : HInst<
31998(outs HvxVR:$Vd32),
31999(ins HvxVR:$Vu32, IntRegs:$Rt32),
32000"$Vd32 = vdmpybus($Vu32,$Rt32)",
32001PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32002let hasNewValue = 1;
32003let opNewValue = 0;
32004let isCVI = 1;
32005let isPseudo = 1;
32006let isCodeGenOnly = 1;
32007let DecoderNamespace = "EXT_mmvec";
32008}
32009def V6_vdmpybus_dv : HInst<
32010(outs HvxWR:$Vdd32),
32011(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32012"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
32013tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32014let Inst{7-5} = 0b111;
32015let Inst{13-13} = 0b0;
32016let Inst{31-21} = 0b00011001000;
32017let hasNewValue = 1;
32018let opNewValue = 0;
32019let isCVI = 1;
32020let DecoderNamespace = "EXT_mmvec";
32021}
32022def V6_vdmpybus_dv_acc : HInst<
32023(outs HvxWR:$Vxx32),
32024(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32025"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
32026tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32027let Inst{7-5} = 0b111;
32028let Inst{13-13} = 0b1;
32029let Inst{31-21} = 0b00011001000;
32030let hasNewValue = 1;
32031let opNewValue = 0;
32032let isAccumulator = 1;
32033let isCVI = 1;
32034let DecoderNamespace = "EXT_mmvec";
32035let Constraints = "$Vxx32 = $Vxx32in";
32036}
32037def V6_vdmpybus_dv_acc_alt : HInst<
32038(outs HvxWR:$Vxx32),
32039(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32040"$Vxx32 += vdmpybus($Vuu32,$Rt32)",
32041PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32042let hasNewValue = 1;
32043let opNewValue = 0;
32044let isAccumulator = 1;
32045let isCVI = 1;
32046let isPseudo = 1;
32047let isCodeGenOnly = 1;
32048let DecoderNamespace = "EXT_mmvec";
32049let Constraints = "$Vxx32 = $Vxx32in";
32050}
32051def V6_vdmpybus_dv_alt : HInst<
32052(outs HvxWR:$Vdd32),
32053(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32054"$Vdd32 = vdmpybus($Vuu32,$Rt32)",
32055PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32056let hasNewValue = 1;
32057let opNewValue = 0;
32058let isCVI = 1;
32059let isPseudo = 1;
32060let isCodeGenOnly = 1;
32061let DecoderNamespace = "EXT_mmvec";
32062}
32063def V6_vdmpyhb : HInst<
32064(outs HvxVR:$Vd32),
32065(ins HvxVR:$Vu32, IntRegs:$Rt32),
32066"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
32067tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32068let Inst{7-5} = 0b010;
32069let Inst{13-13} = 0b0;
32070let Inst{31-21} = 0b00011001000;
32071let hasNewValue = 1;
32072let opNewValue = 0;
32073let isCVI = 1;
32074let DecoderNamespace = "EXT_mmvec";
32075}
32076def V6_vdmpyhb_acc : HInst<
32077(outs HvxVR:$Vx32),
32078(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32079"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
32080tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32081let Inst{7-5} = 0b011;
32082let Inst{13-13} = 0b1;
32083let Inst{31-21} = 0b00011001000;
32084let hasNewValue = 1;
32085let opNewValue = 0;
32086let isAccumulator = 1;
32087let isCVI = 1;
32088let DecoderNamespace = "EXT_mmvec";
32089let Constraints = "$Vx32 = $Vx32in";
32090}
32091def V6_vdmpyhb_acc_alt : HInst<
32092(outs HvxVR:$Vx32),
32093(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32094"$Vx32 += vdmpyhb($Vu32,$Rt32)",
32095PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32096let hasNewValue = 1;
32097let opNewValue = 0;
32098let isAccumulator = 1;
32099let isCVI = 1;
32100let isPseudo = 1;
32101let isCodeGenOnly = 1;
32102let DecoderNamespace = "EXT_mmvec";
32103let Constraints = "$Vx32 = $Vx32in";
32104}
32105def V6_vdmpyhb_alt : HInst<
32106(outs HvxVR:$Vd32),
32107(ins HvxVR:$Vu32, IntRegs:$Rt32),
32108"$Vd32 = vdmpyhb($Vu32,$Rt32)",
32109PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32110let hasNewValue = 1;
32111let opNewValue = 0;
32112let isCVI = 1;
32113let isPseudo = 1;
32114let isCodeGenOnly = 1;
32115let DecoderNamespace = "EXT_mmvec";
32116}
32117def V6_vdmpyhb_dv : HInst<
32118(outs HvxWR:$Vdd32),
32119(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32120"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
32121tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32122let Inst{7-5} = 0b100;
32123let Inst{13-13} = 0b0;
32124let Inst{31-21} = 0b00011001001;
32125let hasNewValue = 1;
32126let opNewValue = 0;
32127let isCVI = 1;
32128let DecoderNamespace = "EXT_mmvec";
32129}
32130def V6_vdmpyhb_dv_acc : HInst<
32131(outs HvxWR:$Vxx32),
32132(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32133"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
32134tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32135let Inst{7-5} = 0b100;
32136let Inst{13-13} = 0b1;
32137let Inst{31-21} = 0b00011001001;
32138let hasNewValue = 1;
32139let opNewValue = 0;
32140let isAccumulator = 1;
32141let isCVI = 1;
32142let DecoderNamespace = "EXT_mmvec";
32143let Constraints = "$Vxx32 = $Vxx32in";
32144}
32145def V6_vdmpyhb_dv_acc_alt : HInst<
32146(outs HvxWR:$Vxx32),
32147(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32148"$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
32149PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32150let hasNewValue = 1;
32151let opNewValue = 0;
32152let isAccumulator = 1;
32153let isCVI = 1;
32154let isPseudo = 1;
32155let isCodeGenOnly = 1;
32156let DecoderNamespace = "EXT_mmvec";
32157let Constraints = "$Vxx32 = $Vxx32in";
32158}
32159def V6_vdmpyhb_dv_alt : HInst<
32160(outs HvxWR:$Vdd32),
32161(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32162"$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
32163PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32164let hasNewValue = 1;
32165let opNewValue = 0;
32166let isCVI = 1;
32167let isPseudo = 1;
32168let isCodeGenOnly = 1;
32169let DecoderNamespace = "EXT_mmvec";
32170}
32171def V6_vdmpyhisat : HInst<
32172(outs HvxVR:$Vd32),
32173(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32174"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
32175tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
32176let Inst{7-5} = 0b011;
32177let Inst{13-13} = 0b0;
32178let Inst{31-21} = 0b00011001001;
32179let hasNewValue = 1;
32180let opNewValue = 0;
32181let isCVI = 1;
32182let DecoderNamespace = "EXT_mmvec";
32183}
32184def V6_vdmpyhisat_acc : HInst<
32185(outs HvxVR:$Vx32),
32186(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32187"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
32188tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
32189let Inst{7-5} = 0b010;
32190let Inst{13-13} = 0b1;
32191let Inst{31-21} = 0b00011001001;
32192let hasNewValue = 1;
32193let opNewValue = 0;
32194let isAccumulator = 1;
32195let isCVI = 1;
32196let DecoderNamespace = "EXT_mmvec";
32197let Constraints = "$Vx32 = $Vx32in";
32198}
32199def V6_vdmpyhisat_acc_alt : HInst<
32200(outs HvxVR:$Vx32),
32201(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32202"$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
32203PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32204let hasNewValue = 1;
32205let opNewValue = 0;
32206let isAccumulator = 1;
32207let isCVI = 1;
32208let isPseudo = 1;
32209let isCodeGenOnly = 1;
32210let DecoderNamespace = "EXT_mmvec";
32211let Constraints = "$Vx32 = $Vx32in";
32212}
32213def V6_vdmpyhisat_alt : HInst<
32214(outs HvxVR:$Vd32),
32215(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32216"$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
32217PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32218let hasNewValue = 1;
32219let opNewValue = 0;
32220let isCVI = 1;
32221let isPseudo = 1;
32222let isCodeGenOnly = 1;
32223let DecoderNamespace = "EXT_mmvec";
32224}
32225def V6_vdmpyhsat : HInst<
32226(outs HvxVR:$Vd32),
32227(ins HvxVR:$Vu32, IntRegs:$Rt32),
32228"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
32229tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
32230let Inst{7-5} = 0b010;
32231let Inst{13-13} = 0b0;
32232let Inst{31-21} = 0b00011001001;
32233let hasNewValue = 1;
32234let opNewValue = 0;
32235let isCVI = 1;
32236let DecoderNamespace = "EXT_mmvec";
32237}
32238def V6_vdmpyhsat_acc : HInst<
32239(outs HvxVR:$Vx32),
32240(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32241"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
32242tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
32243let Inst{7-5} = 0b011;
32244let Inst{13-13} = 0b1;
32245let Inst{31-21} = 0b00011001001;
32246let hasNewValue = 1;
32247let opNewValue = 0;
32248let isAccumulator = 1;
32249let isCVI = 1;
32250let DecoderNamespace = "EXT_mmvec";
32251let Constraints = "$Vx32 = $Vx32in";
32252}
32253def V6_vdmpyhsat_acc_alt : HInst<
32254(outs HvxVR:$Vx32),
32255(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32256"$Vx32 += vdmpyh($Vu32,$Rt32):sat",
32257PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32258let hasNewValue = 1;
32259let opNewValue = 0;
32260let isAccumulator = 1;
32261let isCVI = 1;
32262let isPseudo = 1;
32263let isCodeGenOnly = 1;
32264let DecoderNamespace = "EXT_mmvec";
32265let Constraints = "$Vx32 = $Vx32in";
32266}
32267def V6_vdmpyhsat_alt : HInst<
32268(outs HvxVR:$Vd32),
32269(ins HvxVR:$Vu32, IntRegs:$Rt32),
32270"$Vd32 = vdmpyh($Vu32,$Rt32):sat",
32271PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32272let hasNewValue = 1;
32273let opNewValue = 0;
32274let isCVI = 1;
32275let isPseudo = 1;
32276let isCodeGenOnly = 1;
32277let DecoderNamespace = "EXT_mmvec";
32278}
32279def V6_vdmpyhsuisat : HInst<
32280(outs HvxVR:$Vd32),
32281(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32282"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
32283tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
32284let Inst{7-5} = 0b001;
32285let Inst{13-13} = 0b0;
32286let Inst{31-21} = 0b00011001001;
32287let hasNewValue = 1;
32288let opNewValue = 0;
32289let isCVI = 1;
32290let DecoderNamespace = "EXT_mmvec";
32291}
32292def V6_vdmpyhsuisat_acc : HInst<
32293(outs HvxVR:$Vx32),
32294(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32295"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
32296tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
32297let Inst{7-5} = 0b001;
32298let Inst{13-13} = 0b1;
32299let Inst{31-21} = 0b00011001001;
32300let hasNewValue = 1;
32301let opNewValue = 0;
32302let isAccumulator = 1;
32303let isCVI = 1;
32304let DecoderNamespace = "EXT_mmvec";
32305let Constraints = "$Vx32 = $Vx32in";
32306}
32307def V6_vdmpyhsuisat_acc_alt : HInst<
32308(outs HvxVR:$Vx32),
32309(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32310"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
32311PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32312let hasNewValue = 1;
32313let opNewValue = 0;
32314let isAccumulator = 1;
32315let isCVI = 1;
32316let isPseudo = 1;
32317let isCodeGenOnly = 1;
32318let DecoderNamespace = "EXT_mmvec";
32319let Constraints = "$Vx32 = $Vx32in";
32320}
32321def V6_vdmpyhsuisat_alt : HInst<
32322(outs HvxVR:$Vd32),
32323(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32324"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
32325PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32326let hasNewValue = 1;
32327let opNewValue = 0;
32328let isCVI = 1;
32329let isPseudo = 1;
32330let isCodeGenOnly = 1;
32331let DecoderNamespace = "EXT_mmvec";
32332}
32333def V6_vdmpyhsusat : HInst<
32334(outs HvxVR:$Vd32),
32335(ins HvxVR:$Vu32, IntRegs:$Rt32),
32336"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
32337tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
32338let Inst{7-5} = 0b000;
32339let Inst{13-13} = 0b0;
32340let Inst{31-21} = 0b00011001001;
32341let hasNewValue = 1;
32342let opNewValue = 0;
32343let isCVI = 1;
32344let DecoderNamespace = "EXT_mmvec";
32345}
32346def V6_vdmpyhsusat_acc : HInst<
32347(outs HvxVR:$Vx32),
32348(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32349"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
32350tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
32351let Inst{7-5} = 0b000;
32352let Inst{13-13} = 0b1;
32353let Inst{31-21} = 0b00011001001;
32354let hasNewValue = 1;
32355let opNewValue = 0;
32356let isAccumulator = 1;
32357let isCVI = 1;
32358let DecoderNamespace = "EXT_mmvec";
32359let Constraints = "$Vx32 = $Vx32in";
32360}
32361def V6_vdmpyhsusat_acc_alt : HInst<
32362(outs HvxVR:$Vx32),
32363(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32364"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
32365PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32366let hasNewValue = 1;
32367let opNewValue = 0;
32368let isAccumulator = 1;
32369let isCVI = 1;
32370let isPseudo = 1;
32371let isCodeGenOnly = 1;
32372let DecoderNamespace = "EXT_mmvec";
32373let Constraints = "$Vx32 = $Vx32in";
32374}
32375def V6_vdmpyhsusat_alt : HInst<
32376(outs HvxVR:$Vd32),
32377(ins HvxVR:$Vu32, IntRegs:$Rt32),
32378"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
32379PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32380let hasNewValue = 1;
32381let opNewValue = 0;
32382let isCVI = 1;
32383let isPseudo = 1;
32384let isCodeGenOnly = 1;
32385let DecoderNamespace = "EXT_mmvec";
32386}
32387def V6_vdmpyhvsat : HInst<
32388(outs HvxVR:$Vd32),
32389(ins HvxVR:$Vu32, HvxVR:$Vv32),
32390"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
32391tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
32392let Inst{7-5} = 0b011;
32393let Inst{13-13} = 0b0;
32394let Inst{31-21} = 0b00011100000;
32395let hasNewValue = 1;
32396let opNewValue = 0;
32397let isCVI = 1;
32398let DecoderNamespace = "EXT_mmvec";
32399}
32400def V6_vdmpyhvsat_acc : HInst<
32401(outs HvxVR:$Vx32),
32402(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
32403"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
32404tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
32405let Inst{7-5} = 0b011;
32406let Inst{13-13} = 0b1;
32407let Inst{31-21} = 0b00011100000;
32408let hasNewValue = 1;
32409let opNewValue = 0;
32410let isAccumulator = 1;
32411let isCVI = 1;
32412let DecoderNamespace = "EXT_mmvec";
32413let Constraints = "$Vx32 = $Vx32in";
32414}
32415def V6_vdmpyhvsat_acc_alt : HInst<
32416(outs HvxVR:$Vx32),
32417(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
32418"$Vx32 += vdmpyh($Vu32,$Vv32):sat",
32419PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32420let hasNewValue = 1;
32421let opNewValue = 0;
32422let isAccumulator = 1;
32423let isCVI = 1;
32424let isPseudo = 1;
32425let isCodeGenOnly = 1;
32426let DecoderNamespace = "EXT_mmvec";
32427let Constraints = "$Vx32 = $Vx32in";
32428}
32429def V6_vdmpyhvsat_alt : HInst<
32430(outs HvxVR:$Vd32),
32431(ins HvxVR:$Vu32, HvxVR:$Vv32),
32432"$Vd32 = vdmpyh($Vu32,$Vv32):sat",
32433PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32434let hasNewValue = 1;
32435let opNewValue = 0;
32436let isCVI = 1;
32437let isPseudo = 1;
32438let isCodeGenOnly = 1;
32439let DecoderNamespace = "EXT_mmvec";
32440}
32441def V6_vdsaduh : HInst<
32442(outs HvxWR:$Vdd32),
32443(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32444"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
32445tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32446let Inst{7-5} = 0b101;
32447let Inst{13-13} = 0b0;
32448let Inst{31-21} = 0b00011001000;
32449let hasNewValue = 1;
32450let opNewValue = 0;
32451let isCVI = 1;
32452let DecoderNamespace = "EXT_mmvec";
32453}
32454def V6_vdsaduh_acc : HInst<
32455(outs HvxWR:$Vxx32),
32456(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32457"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
32458tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32459let Inst{7-5} = 0b000;
32460let Inst{13-13} = 0b1;
32461let Inst{31-21} = 0b00011001011;
32462let hasNewValue = 1;
32463let opNewValue = 0;
32464let isAccumulator = 1;
32465let isCVI = 1;
32466let DecoderNamespace = "EXT_mmvec";
32467let Constraints = "$Vxx32 = $Vxx32in";
32468}
32469def V6_vdsaduh_acc_alt : HInst<
32470(outs HvxWR:$Vxx32),
32471(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32472"$Vxx32 += vdsaduh($Vuu32,$Rt32)",
32473PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32474let hasNewValue = 1;
32475let opNewValue = 0;
32476let isAccumulator = 1;
32477let isCVI = 1;
32478let isPseudo = 1;
32479let isCodeGenOnly = 1;
32480let DecoderNamespace = "EXT_mmvec";
32481let Constraints = "$Vxx32 = $Vxx32in";
32482}
32483def V6_vdsaduh_alt : HInst<
32484(outs HvxWR:$Vdd32),
32485(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32486"$Vdd32 = vdsaduh($Vuu32,$Rt32)",
32487PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32488let hasNewValue = 1;
32489let opNewValue = 0;
32490let isCVI = 1;
32491let isPseudo = 1;
32492let isCodeGenOnly = 1;
32493let DecoderNamespace = "EXT_mmvec";
32494}
32495def V6_veqb : HInst<
32496(outs HvxQR:$Qd4),
32497(ins HvxVR:$Vu32, HvxVR:$Vv32),
32498"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
32499tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32500let Inst{7-2} = 0b000000;
32501let Inst{13-13} = 0b0;
32502let Inst{31-21} = 0b00011111100;
32503let hasNewValue = 1;
32504let opNewValue = 0;
32505let isCVI = 1;
32506let DecoderNamespace = "EXT_mmvec";
32507}
32508def V6_veqb_and : HInst<
32509(outs HvxQR:$Qx4),
32510(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32511"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
32512tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32513let Inst{7-2} = 0b000000;
32514let Inst{13-13} = 0b1;
32515let Inst{31-21} = 0b00011100100;
32516let isCVI = 1;
32517let DecoderNamespace = "EXT_mmvec";
32518let Constraints = "$Qx4 = $Qx4in";
32519}
32520def V6_veqb_or : HInst<
32521(outs HvxQR:$Qx4),
32522(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32523"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
32524tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32525let Inst{7-2} = 0b010000;
32526let Inst{13-13} = 0b1;
32527let Inst{31-21} = 0b00011100100;
32528let isAccumulator = 1;
32529let isCVI = 1;
32530let DecoderNamespace = "EXT_mmvec";
32531let Constraints = "$Qx4 = $Qx4in";
32532}
32533def V6_veqb_xor : HInst<
32534(outs HvxQR:$Qx4),
32535(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32536"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
32537tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32538let Inst{7-2} = 0b100000;
32539let Inst{13-13} = 0b1;
32540let Inst{31-21} = 0b00011100100;
32541let isCVI = 1;
32542let DecoderNamespace = "EXT_mmvec";
32543let Constraints = "$Qx4 = $Qx4in";
32544}
32545def V6_veqh : HInst<
32546(outs HvxQR:$Qd4),
32547(ins HvxVR:$Vu32, HvxVR:$Vv32),
32548"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
32549tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32550let Inst{7-2} = 0b000001;
32551let Inst{13-13} = 0b0;
32552let Inst{31-21} = 0b00011111100;
32553let hasNewValue = 1;
32554let opNewValue = 0;
32555let isCVI = 1;
32556let DecoderNamespace = "EXT_mmvec";
32557}
32558def V6_veqh_and : HInst<
32559(outs HvxQR:$Qx4),
32560(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32561"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
32562tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32563let Inst{7-2} = 0b000001;
32564let Inst{13-13} = 0b1;
32565let Inst{31-21} = 0b00011100100;
32566let isCVI = 1;
32567let DecoderNamespace = "EXT_mmvec";
32568let Constraints = "$Qx4 = $Qx4in";
32569}
32570def V6_veqh_or : HInst<
32571(outs HvxQR:$Qx4),
32572(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32573"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
32574tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32575let Inst{7-2} = 0b010001;
32576let Inst{13-13} = 0b1;
32577let Inst{31-21} = 0b00011100100;
32578let isAccumulator = 1;
32579let isCVI = 1;
32580let DecoderNamespace = "EXT_mmvec";
32581let Constraints = "$Qx4 = $Qx4in";
32582}
32583def V6_veqh_xor : HInst<
32584(outs HvxQR:$Qx4),
32585(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32586"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
32587tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32588let Inst{7-2} = 0b100001;
32589let Inst{13-13} = 0b1;
32590let Inst{31-21} = 0b00011100100;
32591let isCVI = 1;
32592let DecoderNamespace = "EXT_mmvec";
32593let Constraints = "$Qx4 = $Qx4in";
32594}
32595def V6_veqw : HInst<
32596(outs HvxQR:$Qd4),
32597(ins HvxVR:$Vu32, HvxVR:$Vv32),
32598"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
32599tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32600let Inst{7-2} = 0b000010;
32601let Inst{13-13} = 0b0;
32602let Inst{31-21} = 0b00011111100;
32603let hasNewValue = 1;
32604let opNewValue = 0;
32605let isCVI = 1;
32606let DecoderNamespace = "EXT_mmvec";
32607}
32608def V6_veqw_and : HInst<
32609(outs HvxQR:$Qx4),
32610(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32611"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
32612tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32613let Inst{7-2} = 0b000010;
32614let Inst{13-13} = 0b1;
32615let Inst{31-21} = 0b00011100100;
32616let isCVI = 1;
32617let DecoderNamespace = "EXT_mmvec";
32618let Constraints = "$Qx4 = $Qx4in";
32619}
32620def V6_veqw_or : HInst<
32621(outs HvxQR:$Qx4),
32622(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32623"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
32624tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32625let Inst{7-2} = 0b010010;
32626let Inst{13-13} = 0b1;
32627let Inst{31-21} = 0b00011100100;
32628let isAccumulator = 1;
32629let isCVI = 1;
32630let DecoderNamespace = "EXT_mmvec";
32631let Constraints = "$Qx4 = $Qx4in";
32632}
32633def V6_veqw_xor : HInst<
32634(outs HvxQR:$Qx4),
32635(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32636"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
32637tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32638let Inst{7-2} = 0b100010;
32639let Inst{13-13} = 0b1;
32640let Inst{31-21} = 0b00011100100;
32641let isCVI = 1;
32642let DecoderNamespace = "EXT_mmvec";
32643let Constraints = "$Qx4 = $Qx4in";
32644}
32645def V6_vgathermh : HInst<
32646(outs),
32647(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32648"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
32649tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
32650let Inst{12-5} = 0b00001000;
32651let Inst{31-21} = 0b00101111000;
32652let hasNewValue = 1;
32653let opNewValue = 0;
32654let accessSize = HalfWordAccess;
32655let isCVLoad = 1;
32656let isCVI = 1;
32657let hasTmpDst = 1;
32658let mayLoad = 1;
32659let Defs = [VTMP];
32660let DecoderNamespace = "EXT_mmvec";
32661}
32662def V6_vgathermhq : HInst<
32663(outs),
32664(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32665"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
32666tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
32667let Inst{12-7} = 0b001010;
32668let Inst{31-21} = 0b00101111000;
32669let hasNewValue = 1;
32670let opNewValue = 0;
32671let accessSize = HalfWordAccess;
32672let isCVLoad = 1;
32673let isCVI = 1;
32674let hasTmpDst = 1;
32675let mayLoad = 1;
32676let Defs = [VTMP];
32677let DecoderNamespace = "EXT_mmvec";
32678}
32679def V6_vgathermhw : HInst<
32680(outs),
32681(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
32682"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
32683tc_05058f6f, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> {
32684let Inst{12-5} = 0b00010000;
32685let Inst{31-21} = 0b00101111000;
32686let hasNewValue = 1;
32687let opNewValue = 0;
32688let accessSize = HalfWordAccess;
32689let isCVLoad = 1;
32690let isCVI = 1;
32691let hasTmpDst = 1;
32692let mayLoad = 1;
32693let Defs = [VTMP];
32694let DecoderNamespace = "EXT_mmvec";
32695}
32696def V6_vgathermhwq : HInst<
32697(outs),
32698(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
32699"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
32700tc_fd7610da, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> {
32701let Inst{12-7} = 0b001100;
32702let Inst{31-21} = 0b00101111000;
32703let hasNewValue = 1;
32704let opNewValue = 0;
32705let accessSize = HalfWordAccess;
32706let isCVLoad = 1;
32707let isCVI = 1;
32708let hasTmpDst = 1;
32709let mayLoad = 1;
32710let Defs = [VTMP];
32711let DecoderNamespace = "EXT_mmvec";
32712}
32713def V6_vgathermw : HInst<
32714(outs),
32715(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32716"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
32717tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
32718let Inst{12-5} = 0b00000000;
32719let Inst{31-21} = 0b00101111000;
32720let hasNewValue = 1;
32721let opNewValue = 0;
32722let accessSize = WordAccess;
32723let isCVLoad = 1;
32724let isCVI = 1;
32725let hasTmpDst = 1;
32726let mayLoad = 1;
32727let Defs = [VTMP];
32728let DecoderNamespace = "EXT_mmvec";
32729}
32730def V6_vgathermwq : HInst<
32731(outs),
32732(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32733"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
32734tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
32735let Inst{12-7} = 0b001000;
32736let Inst{31-21} = 0b00101111000;
32737let hasNewValue = 1;
32738let opNewValue = 0;
32739let accessSize = WordAccess;
32740let isCVLoad = 1;
32741let isCVI = 1;
32742let hasTmpDst = 1;
32743let mayLoad = 1;
32744let Defs = [VTMP];
32745let DecoderNamespace = "EXT_mmvec";
32746}
32747def V6_vgtb : HInst<
32748(outs HvxQR:$Qd4),
32749(ins HvxVR:$Vu32, HvxVR:$Vv32),
32750"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
32751tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32752let Inst{7-2} = 0b000100;
32753let Inst{13-13} = 0b0;
32754let Inst{31-21} = 0b00011111100;
32755let hasNewValue = 1;
32756let opNewValue = 0;
32757let isCVI = 1;
32758let DecoderNamespace = "EXT_mmvec";
32759}
32760def V6_vgtb_and : HInst<
32761(outs HvxQR:$Qx4),
32762(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32763"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
32764tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32765let Inst{7-2} = 0b000100;
32766let Inst{13-13} = 0b1;
32767let Inst{31-21} = 0b00011100100;
32768let isCVI = 1;
32769let DecoderNamespace = "EXT_mmvec";
32770let Constraints = "$Qx4 = $Qx4in";
32771}
32772def V6_vgtb_or : HInst<
32773(outs HvxQR:$Qx4),
32774(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32775"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
32776tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32777let Inst{7-2} = 0b010100;
32778let Inst{13-13} = 0b1;
32779let Inst{31-21} = 0b00011100100;
32780let isAccumulator = 1;
32781let isCVI = 1;
32782let DecoderNamespace = "EXT_mmvec";
32783let Constraints = "$Qx4 = $Qx4in";
32784}
32785def V6_vgtb_xor : HInst<
32786(outs HvxQR:$Qx4),
32787(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32788"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
32789tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32790let Inst{7-2} = 0b100100;
32791let Inst{13-13} = 0b1;
32792let Inst{31-21} = 0b00011100100;
32793let isCVI = 1;
32794let DecoderNamespace = "EXT_mmvec";
32795let Constraints = "$Qx4 = $Qx4in";
32796}
32797def V6_vgth : HInst<
32798(outs HvxQR:$Qd4),
32799(ins HvxVR:$Vu32, HvxVR:$Vv32),
32800"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
32801tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32802let Inst{7-2} = 0b000101;
32803let Inst{13-13} = 0b0;
32804let Inst{31-21} = 0b00011111100;
32805let hasNewValue = 1;
32806let opNewValue = 0;
32807let isCVI = 1;
32808let DecoderNamespace = "EXT_mmvec";
32809}
32810def V6_vgth_and : HInst<
32811(outs HvxQR:$Qx4),
32812(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32813"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
32814tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32815let Inst{7-2} = 0b000101;
32816let Inst{13-13} = 0b1;
32817let Inst{31-21} = 0b00011100100;
32818let isCVI = 1;
32819let DecoderNamespace = "EXT_mmvec";
32820let Constraints = "$Qx4 = $Qx4in";
32821}
32822def V6_vgth_or : HInst<
32823(outs HvxQR:$Qx4),
32824(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32825"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
32826tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32827let Inst{7-2} = 0b010101;
32828let Inst{13-13} = 0b1;
32829let Inst{31-21} = 0b00011100100;
32830let isAccumulator = 1;
32831let isCVI = 1;
32832let DecoderNamespace = "EXT_mmvec";
32833let Constraints = "$Qx4 = $Qx4in";
32834}
32835def V6_vgth_xor : HInst<
32836(outs HvxQR:$Qx4),
32837(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32838"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
32839tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32840let Inst{7-2} = 0b100101;
32841let Inst{13-13} = 0b1;
32842let Inst{31-21} = 0b00011100100;
32843let isCVI = 1;
32844let DecoderNamespace = "EXT_mmvec";
32845let Constraints = "$Qx4 = $Qx4in";
32846}
32847def V6_vgtub : HInst<
32848(outs HvxQR:$Qd4),
32849(ins HvxVR:$Vu32, HvxVR:$Vv32),
32850"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
32851tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32852let Inst{7-2} = 0b001000;
32853let Inst{13-13} = 0b0;
32854let Inst{31-21} = 0b00011111100;
32855let hasNewValue = 1;
32856let opNewValue = 0;
32857let isCVI = 1;
32858let DecoderNamespace = "EXT_mmvec";
32859}
32860def V6_vgtub_and : HInst<
32861(outs HvxQR:$Qx4),
32862(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32863"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
32864tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32865let Inst{7-2} = 0b001000;
32866let Inst{13-13} = 0b1;
32867let Inst{31-21} = 0b00011100100;
32868let isCVI = 1;
32869let DecoderNamespace = "EXT_mmvec";
32870let Constraints = "$Qx4 = $Qx4in";
32871}
32872def V6_vgtub_or : HInst<
32873(outs HvxQR:$Qx4),
32874(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32875"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
32876tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32877let Inst{7-2} = 0b011000;
32878let Inst{13-13} = 0b1;
32879let Inst{31-21} = 0b00011100100;
32880let isAccumulator = 1;
32881let isCVI = 1;
32882let DecoderNamespace = "EXT_mmvec";
32883let Constraints = "$Qx4 = $Qx4in";
32884}
32885def V6_vgtub_xor : HInst<
32886(outs HvxQR:$Qx4),
32887(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32888"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
32889tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32890let Inst{7-2} = 0b101000;
32891let Inst{13-13} = 0b1;
32892let Inst{31-21} = 0b00011100100;
32893let isCVI = 1;
32894let DecoderNamespace = "EXT_mmvec";
32895let Constraints = "$Qx4 = $Qx4in";
32896}
32897def V6_vgtuh : HInst<
32898(outs HvxQR:$Qd4),
32899(ins HvxVR:$Vu32, HvxVR:$Vv32),
32900"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
32901tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32902let Inst{7-2} = 0b001001;
32903let Inst{13-13} = 0b0;
32904let Inst{31-21} = 0b00011111100;
32905let hasNewValue = 1;
32906let opNewValue = 0;
32907let isCVI = 1;
32908let DecoderNamespace = "EXT_mmvec";
32909}
32910def V6_vgtuh_and : HInst<
32911(outs HvxQR:$Qx4),
32912(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32913"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
32914tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32915let Inst{7-2} = 0b001001;
32916let Inst{13-13} = 0b1;
32917let Inst{31-21} = 0b00011100100;
32918let isCVI = 1;
32919let DecoderNamespace = "EXT_mmvec";
32920let Constraints = "$Qx4 = $Qx4in";
32921}
32922def V6_vgtuh_or : HInst<
32923(outs HvxQR:$Qx4),
32924(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32925"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
32926tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32927let Inst{7-2} = 0b011001;
32928let Inst{13-13} = 0b1;
32929let Inst{31-21} = 0b00011100100;
32930let isAccumulator = 1;
32931let isCVI = 1;
32932let DecoderNamespace = "EXT_mmvec";
32933let Constraints = "$Qx4 = $Qx4in";
32934}
32935def V6_vgtuh_xor : HInst<
32936(outs HvxQR:$Qx4),
32937(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32938"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
32939tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32940let Inst{7-2} = 0b101001;
32941let Inst{13-13} = 0b1;
32942let Inst{31-21} = 0b00011100100;
32943let isCVI = 1;
32944let DecoderNamespace = "EXT_mmvec";
32945let Constraints = "$Qx4 = $Qx4in";
32946}
32947def V6_vgtuw : HInst<
32948(outs HvxQR:$Qd4),
32949(ins HvxVR:$Vu32, HvxVR:$Vv32),
32950"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
32951tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32952let Inst{7-2} = 0b001010;
32953let Inst{13-13} = 0b0;
32954let Inst{31-21} = 0b00011111100;
32955let hasNewValue = 1;
32956let opNewValue = 0;
32957let isCVI = 1;
32958let DecoderNamespace = "EXT_mmvec";
32959}
32960def V6_vgtuw_and : HInst<
32961(outs HvxQR:$Qx4),
32962(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32963"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
32964tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32965let Inst{7-2} = 0b001010;
32966let Inst{13-13} = 0b1;
32967let Inst{31-21} = 0b00011100100;
32968let isCVI = 1;
32969let DecoderNamespace = "EXT_mmvec";
32970let Constraints = "$Qx4 = $Qx4in";
32971}
32972def V6_vgtuw_or : HInst<
32973(outs HvxQR:$Qx4),
32974(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32975"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
32976tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32977let Inst{7-2} = 0b011010;
32978let Inst{13-13} = 0b1;
32979let Inst{31-21} = 0b00011100100;
32980let isAccumulator = 1;
32981let isCVI = 1;
32982let DecoderNamespace = "EXT_mmvec";
32983let Constraints = "$Qx4 = $Qx4in";
32984}
32985def V6_vgtuw_xor : HInst<
32986(outs HvxQR:$Qx4),
32987(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32988"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
32989tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32990let Inst{7-2} = 0b101010;
32991let Inst{13-13} = 0b1;
32992let Inst{31-21} = 0b00011100100;
32993let isCVI = 1;
32994let DecoderNamespace = "EXT_mmvec";
32995let Constraints = "$Qx4 = $Qx4in";
32996}
32997def V6_vgtw : HInst<
32998(outs HvxQR:$Qd4),
32999(ins HvxVR:$Vu32, HvxVR:$Vv32),
33000"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
33001tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33002let Inst{7-2} = 0b000110;
33003let Inst{13-13} = 0b0;
33004let Inst{31-21} = 0b00011111100;
33005let hasNewValue = 1;
33006let opNewValue = 0;
33007let isCVI = 1;
33008let DecoderNamespace = "EXT_mmvec";
33009}
33010def V6_vgtw_and : HInst<
33011(outs HvxQR:$Qx4),
33012(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33013"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
33014tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33015let Inst{7-2} = 0b000110;
33016let Inst{13-13} = 0b1;
33017let Inst{31-21} = 0b00011100100;
33018let isCVI = 1;
33019let DecoderNamespace = "EXT_mmvec";
33020let Constraints = "$Qx4 = $Qx4in";
33021}
33022def V6_vgtw_or : HInst<
33023(outs HvxQR:$Qx4),
33024(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33025"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
33026tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33027let Inst{7-2} = 0b010110;
33028let Inst{13-13} = 0b1;
33029let Inst{31-21} = 0b00011100100;
33030let isAccumulator = 1;
33031let isCVI = 1;
33032let DecoderNamespace = "EXT_mmvec";
33033let Constraints = "$Qx4 = $Qx4in";
33034}
33035def V6_vgtw_xor : HInst<
33036(outs HvxQR:$Qx4),
33037(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33038"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
33039tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33040let Inst{7-2} = 0b100110;
33041let Inst{13-13} = 0b1;
33042let Inst{31-21} = 0b00011100100;
33043let isCVI = 1;
33044let DecoderNamespace = "EXT_mmvec";
33045let Constraints = "$Qx4 = $Qx4in";
33046}
33047def V6_vhist : HInst<
33048(outs),
33049(ins),
33050"vhist",
33051tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
33052let Inst{13-0} = 0b10000010000000;
33053let Inst{31-16} = 0b0001111000000000;
33054let isCVI = 1;
33055let DecoderNamespace = "EXT_mmvec";
33056}
33057def V6_vhistq : HInst<
33058(outs),
33059(ins HvxQR:$Qv4),
33060"vhist($Qv4)",
33061tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
33062let Inst{13-0} = 0b10000010000000;
33063let Inst{21-16} = 0b000010;
33064let Inst{31-24} = 0b00011110;
33065let isCVI = 1;
33066let DecoderNamespace = "EXT_mmvec";
33067}
33068def V6_vinsertwr : HInst<
33069(outs HvxVR:$Vx32),
33070(ins HvxVR:$Vx32in, IntRegs:$Rt32),
33071"$Vx32.w = vinsert($Rt32)",
33072tc_ac4046bc, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
33073let Inst{13-5} = 0b100000001;
33074let Inst{31-21} = 0b00011001101;
33075let hasNewValue = 1;
33076let opNewValue = 0;
33077let isCVI = 1;
33078let DecoderNamespace = "EXT_mmvec";
33079let Constraints = "$Vx32 = $Vx32in";
33080}
33081def V6_vlalignb : HInst<
33082(outs HvxVR:$Vd32),
33083(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33084"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
33085tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
33086let Inst{7-5} = 0b001;
33087let Inst{13-13} = 0b0;
33088let Inst{31-24} = 0b00011011;
33089let hasNewValue = 1;
33090let opNewValue = 0;
33091let isCVI = 1;
33092let DecoderNamespace = "EXT_mmvec";
33093}
33094def V6_vlalignbi : HInst<
33095(outs HvxVR:$Vd32),
33096(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33097"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
33098tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
33099let Inst{13-13} = 0b1;
33100let Inst{31-21} = 0b00011110011;
33101let hasNewValue = 1;
33102let opNewValue = 0;
33103let isCVI = 1;
33104let DecoderNamespace = "EXT_mmvec";
33105}
33106def V6_vlsrb : HInst<
33107(outs HvxVR:$Vd32),
33108(ins HvxVR:$Vu32, IntRegs:$Rt32),
33109"$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
33110tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
33111let Inst{7-5} = 0b011;
33112let Inst{13-13} = 0b0;
33113let Inst{31-21} = 0b00011001100;
33114let hasNewValue = 1;
33115let opNewValue = 0;
33116let isCVI = 1;
33117let DecoderNamespace = "EXT_mmvec";
33118}
33119def V6_vlsrh : HInst<
33120(outs HvxVR:$Vd32),
33121(ins HvxVR:$Vu32, IntRegs:$Rt32),
33122"$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
33123tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
33124let Inst{7-5} = 0b010;
33125let Inst{13-13} = 0b0;
33126let Inst{31-21} = 0b00011001100;
33127let hasNewValue = 1;
33128let opNewValue = 0;
33129let isCVI = 1;
33130let DecoderNamespace = "EXT_mmvec";
33131}
33132def V6_vlsrh_alt : HInst<
33133(outs HvxVR:$Vd32),
33134(ins HvxVR:$Vu32, IntRegs:$Rt32),
33135"$Vd32 = vlsrh($Vu32,$Rt32)",
33136PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33137let hasNewValue = 1;
33138let opNewValue = 0;
33139let isCVI = 1;
33140let isPseudo = 1;
33141let isCodeGenOnly = 1;
33142let DecoderNamespace = "EXT_mmvec";
33143}
33144def V6_vlsrhv : HInst<
33145(outs HvxVR:$Vd32),
33146(ins HvxVR:$Vu32, HvxVR:$Vv32),
33147"$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
33148tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
33149let Inst{7-5} = 0b010;
33150let Inst{13-13} = 0b0;
33151let Inst{31-21} = 0b00011111101;
33152let hasNewValue = 1;
33153let opNewValue = 0;
33154let isCVI = 1;
33155let DecoderNamespace = "EXT_mmvec";
33156}
33157def V6_vlsrhv_alt : HInst<
33158(outs HvxVR:$Vd32),
33159(ins HvxVR:$Vu32, HvxVR:$Vv32),
33160"$Vd32 = vlsrh($Vu32,$Vv32)",
33161PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33162let hasNewValue = 1;
33163let opNewValue = 0;
33164let isCVI = 1;
33165let isPseudo = 1;
33166let isCodeGenOnly = 1;
33167let DecoderNamespace = "EXT_mmvec";
33168}
33169def V6_vlsrw : HInst<
33170(outs HvxVR:$Vd32),
33171(ins HvxVR:$Vu32, IntRegs:$Rt32),
33172"$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
33173tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
33174let Inst{7-5} = 0b001;
33175let Inst{13-13} = 0b0;
33176let Inst{31-21} = 0b00011001100;
33177let hasNewValue = 1;
33178let opNewValue = 0;
33179let isCVI = 1;
33180let DecoderNamespace = "EXT_mmvec";
33181}
33182def V6_vlsrw_alt : HInst<
33183(outs HvxVR:$Vd32),
33184(ins HvxVR:$Vu32, IntRegs:$Rt32),
33185"$Vd32 = vlsrw($Vu32,$Rt32)",
33186PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33187let hasNewValue = 1;
33188let opNewValue = 0;
33189let isCVI = 1;
33190let isPseudo = 1;
33191let isCodeGenOnly = 1;
33192let DecoderNamespace = "EXT_mmvec";
33193}
33194def V6_vlsrwv : HInst<
33195(outs HvxVR:$Vd32),
33196(ins HvxVR:$Vu32, HvxVR:$Vv32),
33197"$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
33198tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
33199let Inst{7-5} = 0b001;
33200let Inst{13-13} = 0b0;
33201let Inst{31-21} = 0b00011111101;
33202let hasNewValue = 1;
33203let opNewValue = 0;
33204let isCVI = 1;
33205let DecoderNamespace = "EXT_mmvec";
33206}
33207def V6_vlsrwv_alt : HInst<
33208(outs HvxVR:$Vd32),
33209(ins HvxVR:$Vu32, HvxVR:$Vv32),
33210"$Vd32 = vlsrw($Vu32,$Vv32)",
33211PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33212let hasNewValue = 1;
33213let opNewValue = 0;
33214let isCVI = 1;
33215let isPseudo = 1;
33216let isCodeGenOnly = 1;
33217let DecoderNamespace = "EXT_mmvec";
33218}
33219def V6_vlut4 : HInst<
33220(outs HvxVR:$Vd32),
33221(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
33222"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
33223tc_f1de44ef, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
33224let Inst{7-5} = 0b100;
33225let Inst{13-13} = 0b0;
33226let Inst{31-21} = 0b00011001011;
33227let hasNewValue = 1;
33228let opNewValue = 0;
33229let isCVI = 1;
33230let DecoderNamespace = "EXT_mmvec";
33231}
33232def V6_vlutvvb : HInst<
33233(outs HvxVR:$Vd32),
33234(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33235"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
33236tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
33237let Inst{7-5} = 0b001;
33238let Inst{13-13} = 0b1;
33239let Inst{31-24} = 0b00011011;
33240let hasNewValue = 1;
33241let opNewValue = 0;
33242let isCVI = 1;
33243let DecoderNamespace = "EXT_mmvec";
33244}
33245def V6_vlutvvb_nm : HInst<
33246(outs HvxVR:$Vd32),
33247(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33248"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
33249tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
33250let Inst{7-5} = 0b011;
33251let Inst{13-13} = 0b0;
33252let Inst{31-24} = 0b00011000;
33253let hasNewValue = 1;
33254let opNewValue = 0;
33255let isCVI = 1;
33256let DecoderNamespace = "EXT_mmvec";
33257}
33258def V6_vlutvvb_oracc : HInst<
33259(outs HvxVR:$Vx32),
33260(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33261"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
33262tc_9d1dc972, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
33263let Inst{7-5} = 0b101;
33264let Inst{13-13} = 0b1;
33265let Inst{31-24} = 0b00011011;
33266let hasNewValue = 1;
33267let opNewValue = 0;
33268let isAccumulator = 1;
33269let isCVI = 1;
33270let DecoderNamespace = "EXT_mmvec";
33271let Constraints = "$Vx32 = $Vx32in";
33272}
33273def V6_vlutvvb_oracci : HInst<
33274(outs HvxVR:$Vx32),
33275(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33276"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
33277tc_9d1dc972, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
33278let Inst{13-13} = 0b1;
33279let Inst{31-21} = 0b00011100110;
33280let hasNewValue = 1;
33281let opNewValue = 0;
33282let isAccumulator = 1;
33283let isCVI = 1;
33284let DecoderNamespace = "EXT_mmvec";
33285let Constraints = "$Vx32 = $Vx32in";
33286}
33287def V6_vlutvvbi : HInst<
33288(outs HvxVR:$Vd32),
33289(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33290"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
33291tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
33292let Inst{13-13} = 0b0;
33293let Inst{31-21} = 0b00011110001;
33294let hasNewValue = 1;
33295let opNewValue = 0;
33296let isCVI = 1;
33297let DecoderNamespace = "EXT_mmvec";
33298}
33299def V6_vlutvwh : HInst<
33300(outs HvxWR:$Vdd32),
33301(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33302"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
33303tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
33304let Inst{7-5} = 0b110;
33305let Inst{13-13} = 0b1;
33306let Inst{31-24} = 0b00011011;
33307let hasNewValue = 1;
33308let opNewValue = 0;
33309let isCVI = 1;
33310let DecoderNamespace = "EXT_mmvec";
33311}
33312def V6_vlutvwh_nm : HInst<
33313(outs HvxWR:$Vdd32),
33314(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33315"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
33316tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
33317let Inst{7-5} = 0b100;
33318let Inst{13-13} = 0b0;
33319let Inst{31-24} = 0b00011000;
33320let hasNewValue = 1;
33321let opNewValue = 0;
33322let isCVI = 1;
33323let DecoderNamespace = "EXT_mmvec";
33324}
33325def V6_vlutvwh_oracc : HInst<
33326(outs HvxWR:$Vxx32),
33327(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33328"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
33329tc_9d1dc972, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
33330let Inst{7-5} = 0b111;
33331let Inst{13-13} = 0b1;
33332let Inst{31-24} = 0b00011011;
33333let hasNewValue = 1;
33334let opNewValue = 0;
33335let isAccumulator = 1;
33336let isCVI = 1;
33337let DecoderNamespace = "EXT_mmvec";
33338let Constraints = "$Vxx32 = $Vxx32in";
33339}
33340def V6_vlutvwh_oracci : HInst<
33341(outs HvxWR:$Vxx32),
33342(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33343"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
33344tc_9d1dc972, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
33345let Inst{13-13} = 0b1;
33346let Inst{31-21} = 0b00011100111;
33347let hasNewValue = 1;
33348let opNewValue = 0;
33349let isAccumulator = 1;
33350let isCVI = 1;
33351let DecoderNamespace = "EXT_mmvec";
33352let Constraints = "$Vxx32 = $Vxx32in";
33353}
33354def V6_vlutvwhi : HInst<
33355(outs HvxWR:$Vdd32),
33356(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33357"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
33358tc_87adc037, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
33359let Inst{13-13} = 0b0;
33360let Inst{31-21} = 0b00011110011;
33361let hasNewValue = 1;
33362let opNewValue = 0;
33363let isCVI = 1;
33364let DecoderNamespace = "EXT_mmvec";
33365}
33366def V6_vmaxb : HInst<
33367(outs HvxVR:$Vd32),
33368(ins HvxVR:$Vu32, HvxVR:$Vv32),
33369"$Vd32.b = vmax($Vu32.b,$Vv32.b)",
33370tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
33371let Inst{7-5} = 0b101;
33372let Inst{13-13} = 0b0;
33373let Inst{31-21} = 0b00011111001;
33374let hasNewValue = 1;
33375let opNewValue = 0;
33376let isCVI = 1;
33377let DecoderNamespace = "EXT_mmvec";
33378}
33379def V6_vmaxb_alt : HInst<
33380(outs HvxVR:$Vd32),
33381(ins HvxVR:$Vu32, HvxVR:$Vv32),
33382"$Vd32 = vmaxb($Vu32,$Vv32)",
33383PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33384let hasNewValue = 1;
33385let opNewValue = 0;
33386let isCVI = 1;
33387let isPseudo = 1;
33388let isCodeGenOnly = 1;
33389let DecoderNamespace = "EXT_mmvec";
33390}
33391def V6_vmaxh : HInst<
33392(outs HvxVR:$Vd32),
33393(ins HvxVR:$Vu32, HvxVR:$Vv32),
33394"$Vd32.h = vmax($Vu32.h,$Vv32.h)",
33395tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33396let Inst{7-5} = 0b111;
33397let Inst{13-13} = 0b0;
33398let Inst{31-21} = 0b00011111000;
33399let hasNewValue = 1;
33400let opNewValue = 0;
33401let isCVI = 1;
33402let DecoderNamespace = "EXT_mmvec";
33403}
33404def V6_vmaxh_alt : HInst<
33405(outs HvxVR:$Vd32),
33406(ins HvxVR:$Vu32, HvxVR:$Vv32),
33407"$Vd32 = vmaxh($Vu32,$Vv32)",
33408PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33409let hasNewValue = 1;
33410let opNewValue = 0;
33411let isCVI = 1;
33412let isPseudo = 1;
33413let isCodeGenOnly = 1;
33414let DecoderNamespace = "EXT_mmvec";
33415}
33416def V6_vmaxub : HInst<
33417(outs HvxVR:$Vd32),
33418(ins HvxVR:$Vu32, HvxVR:$Vv32),
33419"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
33420tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33421let Inst{7-5} = 0b101;
33422let Inst{13-13} = 0b0;
33423let Inst{31-21} = 0b00011111000;
33424let hasNewValue = 1;
33425let opNewValue = 0;
33426let isCVI = 1;
33427let DecoderNamespace = "EXT_mmvec";
33428}
33429def V6_vmaxub_alt : HInst<
33430(outs HvxVR:$Vd32),
33431(ins HvxVR:$Vu32, HvxVR:$Vv32),
33432"$Vd32 = vmaxub($Vu32,$Vv32)",
33433PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33434let hasNewValue = 1;
33435let opNewValue = 0;
33436let isCVI = 1;
33437let isPseudo = 1;
33438let isCodeGenOnly = 1;
33439let DecoderNamespace = "EXT_mmvec";
33440}
33441def V6_vmaxuh : HInst<
33442(outs HvxVR:$Vd32),
33443(ins HvxVR:$Vu32, HvxVR:$Vv32),
33444"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
33445tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33446let Inst{7-5} = 0b110;
33447let Inst{13-13} = 0b0;
33448let Inst{31-21} = 0b00011111000;
33449let hasNewValue = 1;
33450let opNewValue = 0;
33451let isCVI = 1;
33452let DecoderNamespace = "EXT_mmvec";
33453}
33454def V6_vmaxuh_alt : HInst<
33455(outs HvxVR:$Vd32),
33456(ins HvxVR:$Vu32, HvxVR:$Vv32),
33457"$Vd32 = vmaxuh($Vu32,$Vv32)",
33458PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33459let hasNewValue = 1;
33460let opNewValue = 0;
33461let isCVI = 1;
33462let isPseudo = 1;
33463let isCodeGenOnly = 1;
33464let DecoderNamespace = "EXT_mmvec";
33465}
33466def V6_vmaxw : HInst<
33467(outs HvxVR:$Vd32),
33468(ins HvxVR:$Vu32, HvxVR:$Vv32),
33469"$Vd32.w = vmax($Vu32.w,$Vv32.w)",
33470tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33471let Inst{7-5} = 0b000;
33472let Inst{13-13} = 0b0;
33473let Inst{31-21} = 0b00011111001;
33474let hasNewValue = 1;
33475let opNewValue = 0;
33476let isCVI = 1;
33477let DecoderNamespace = "EXT_mmvec";
33478}
33479def V6_vmaxw_alt : HInst<
33480(outs HvxVR:$Vd32),
33481(ins HvxVR:$Vu32, HvxVR:$Vv32),
33482"$Vd32 = vmaxw($Vu32,$Vv32)",
33483PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33484let hasNewValue = 1;
33485let opNewValue = 0;
33486let isCVI = 1;
33487let isPseudo = 1;
33488let isCodeGenOnly = 1;
33489let DecoderNamespace = "EXT_mmvec";
33490}
33491def V6_vminb : HInst<
33492(outs HvxVR:$Vd32),
33493(ins HvxVR:$Vu32, HvxVR:$Vv32),
33494"$Vd32.b = vmin($Vu32.b,$Vv32.b)",
33495tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
33496let Inst{7-5} = 0b100;
33497let Inst{13-13} = 0b0;
33498let Inst{31-21} = 0b00011111001;
33499let hasNewValue = 1;
33500let opNewValue = 0;
33501let isCVI = 1;
33502let DecoderNamespace = "EXT_mmvec";
33503}
33504def V6_vminb_alt : HInst<
33505(outs HvxVR:$Vd32),
33506(ins HvxVR:$Vu32, HvxVR:$Vv32),
33507"$Vd32 = vminb($Vu32,$Vv32)",
33508PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33509let hasNewValue = 1;
33510let opNewValue = 0;
33511let isCVI = 1;
33512let isPseudo = 1;
33513let isCodeGenOnly = 1;
33514let DecoderNamespace = "EXT_mmvec";
33515}
33516def V6_vminh : HInst<
33517(outs HvxVR:$Vd32),
33518(ins HvxVR:$Vu32, HvxVR:$Vv32),
33519"$Vd32.h = vmin($Vu32.h,$Vv32.h)",
33520tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33521let Inst{7-5} = 0b011;
33522let Inst{13-13} = 0b0;
33523let Inst{31-21} = 0b00011111000;
33524let hasNewValue = 1;
33525let opNewValue = 0;
33526let isCVI = 1;
33527let DecoderNamespace = "EXT_mmvec";
33528}
33529def V6_vminh_alt : HInst<
33530(outs HvxVR:$Vd32),
33531(ins HvxVR:$Vu32, HvxVR:$Vv32),
33532"$Vd32 = vminh($Vu32,$Vv32)",
33533PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33534let hasNewValue = 1;
33535let opNewValue = 0;
33536let isCVI = 1;
33537let isPseudo = 1;
33538let isCodeGenOnly = 1;
33539let DecoderNamespace = "EXT_mmvec";
33540}
33541def V6_vminub : HInst<
33542(outs HvxVR:$Vd32),
33543(ins HvxVR:$Vu32, HvxVR:$Vv32),
33544"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
33545tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33546let Inst{7-5} = 0b001;
33547let Inst{13-13} = 0b0;
33548let Inst{31-21} = 0b00011111000;
33549let hasNewValue = 1;
33550let opNewValue = 0;
33551let isCVI = 1;
33552let DecoderNamespace = "EXT_mmvec";
33553}
33554def V6_vminub_alt : HInst<
33555(outs HvxVR:$Vd32),
33556(ins HvxVR:$Vu32, HvxVR:$Vv32),
33557"$Vd32 = vminub($Vu32,$Vv32)",
33558PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33559let hasNewValue = 1;
33560let opNewValue = 0;
33561let isCVI = 1;
33562let isPseudo = 1;
33563let isCodeGenOnly = 1;
33564let DecoderNamespace = "EXT_mmvec";
33565}
33566def V6_vminuh : HInst<
33567(outs HvxVR:$Vd32),
33568(ins HvxVR:$Vu32, HvxVR:$Vv32),
33569"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
33570tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33571let Inst{7-5} = 0b010;
33572let Inst{13-13} = 0b0;
33573let Inst{31-21} = 0b00011111000;
33574let hasNewValue = 1;
33575let opNewValue = 0;
33576let isCVI = 1;
33577let DecoderNamespace = "EXT_mmvec";
33578}
33579def V6_vminuh_alt : HInst<
33580(outs HvxVR:$Vd32),
33581(ins HvxVR:$Vu32, HvxVR:$Vv32),
33582"$Vd32 = vminuh($Vu32,$Vv32)",
33583PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33584let hasNewValue = 1;
33585let opNewValue = 0;
33586let isCVI = 1;
33587let isPseudo = 1;
33588let isCodeGenOnly = 1;
33589let DecoderNamespace = "EXT_mmvec";
33590}
33591def V6_vminw : HInst<
33592(outs HvxVR:$Vd32),
33593(ins HvxVR:$Vu32, HvxVR:$Vv32),
33594"$Vd32.w = vmin($Vu32.w,$Vv32.w)",
33595tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33596let Inst{7-5} = 0b100;
33597let Inst{13-13} = 0b0;
33598let Inst{31-21} = 0b00011111000;
33599let hasNewValue = 1;
33600let opNewValue = 0;
33601let isCVI = 1;
33602let DecoderNamespace = "EXT_mmvec";
33603}
33604def V6_vminw_alt : HInst<
33605(outs HvxVR:$Vd32),
33606(ins HvxVR:$Vu32, HvxVR:$Vv32),
33607"$Vd32 = vminw($Vu32,$Vv32)",
33608PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33609let hasNewValue = 1;
33610let opNewValue = 0;
33611let isCVI = 1;
33612let isPseudo = 1;
33613let isCodeGenOnly = 1;
33614let DecoderNamespace = "EXT_mmvec";
33615}
33616def V6_vmpabus : HInst<
33617(outs HvxWR:$Vdd32),
33618(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33619"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
33620tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33621let Inst{7-5} = 0b110;
33622let Inst{13-13} = 0b0;
33623let Inst{31-21} = 0b00011001001;
33624let hasNewValue = 1;
33625let opNewValue = 0;
33626let isCVI = 1;
33627let DecoderNamespace = "EXT_mmvec";
33628}
33629def V6_vmpabus_acc : HInst<
33630(outs HvxWR:$Vxx32),
33631(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33632"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
33633tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33634let Inst{7-5} = 0b110;
33635let Inst{13-13} = 0b1;
33636let Inst{31-21} = 0b00011001001;
33637let hasNewValue = 1;
33638let opNewValue = 0;
33639let isAccumulator = 1;
33640let isCVI = 1;
33641let DecoderNamespace = "EXT_mmvec";
33642let Constraints = "$Vxx32 = $Vxx32in";
33643}
33644def V6_vmpabus_acc_alt : HInst<
33645(outs HvxWR:$Vxx32),
33646(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33647"$Vxx32 += vmpabus($Vuu32,$Rt32)",
33648PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33649let hasNewValue = 1;
33650let opNewValue = 0;
33651let isAccumulator = 1;
33652let isCVI = 1;
33653let isPseudo = 1;
33654let isCodeGenOnly = 1;
33655let DecoderNamespace = "EXT_mmvec";
33656let Constraints = "$Vxx32 = $Vxx32in";
33657}
33658def V6_vmpabus_alt : HInst<
33659(outs HvxWR:$Vdd32),
33660(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33661"$Vdd32 = vmpabus($Vuu32,$Rt32)",
33662PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33663let hasNewValue = 1;
33664let opNewValue = 0;
33665let isCVI = 1;
33666let isPseudo = 1;
33667let isCodeGenOnly = 1;
33668let DecoderNamespace = "EXT_mmvec";
33669}
33670def V6_vmpabusv : HInst<
33671(outs HvxWR:$Vdd32),
33672(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33673"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
33674tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
33675let Inst{7-5} = 0b011;
33676let Inst{13-13} = 0b0;
33677let Inst{31-21} = 0b00011100001;
33678let hasNewValue = 1;
33679let opNewValue = 0;
33680let isCVI = 1;
33681let DecoderNamespace = "EXT_mmvec";
33682}
33683def V6_vmpabusv_alt : HInst<
33684(outs HvxWR:$Vdd32),
33685(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33686"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
33687PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33688let hasNewValue = 1;
33689let opNewValue = 0;
33690let isCVI = 1;
33691let isPseudo = 1;
33692let isCodeGenOnly = 1;
33693let DecoderNamespace = "EXT_mmvec";
33694}
33695def V6_vmpabuu : HInst<
33696(outs HvxWR:$Vdd32),
33697(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33698"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
33699tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
33700let Inst{7-5} = 0b011;
33701let Inst{13-13} = 0b0;
33702let Inst{31-21} = 0b00011001011;
33703let hasNewValue = 1;
33704let opNewValue = 0;
33705let isCVI = 1;
33706let DecoderNamespace = "EXT_mmvec";
33707}
33708def V6_vmpabuu_acc : HInst<
33709(outs HvxWR:$Vxx32),
33710(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33711"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
33712tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
33713let Inst{7-5} = 0b100;
33714let Inst{13-13} = 0b1;
33715let Inst{31-21} = 0b00011001101;
33716let hasNewValue = 1;
33717let opNewValue = 0;
33718let isAccumulator = 1;
33719let isCVI = 1;
33720let DecoderNamespace = "EXT_mmvec";
33721let Constraints = "$Vxx32 = $Vxx32in";
33722}
33723def V6_vmpabuu_acc_alt : HInst<
33724(outs HvxWR:$Vxx32),
33725(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33726"$Vxx32 += vmpabuu($Vuu32,$Rt32)",
33727PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
33728let hasNewValue = 1;
33729let opNewValue = 0;
33730let isAccumulator = 1;
33731let isCVI = 1;
33732let isPseudo = 1;
33733let isCodeGenOnly = 1;
33734let DecoderNamespace = "EXT_mmvec";
33735let Constraints = "$Vxx32 = $Vxx32in";
33736}
33737def V6_vmpabuu_alt : HInst<
33738(outs HvxWR:$Vdd32),
33739(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33740"$Vdd32 = vmpabuu($Vuu32,$Rt32)",
33741PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
33742let hasNewValue = 1;
33743let opNewValue = 0;
33744let isCVI = 1;
33745let isPseudo = 1;
33746let isCodeGenOnly = 1;
33747let DecoderNamespace = "EXT_mmvec";
33748}
33749def V6_vmpabuuv : HInst<
33750(outs HvxWR:$Vdd32),
33751(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33752"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
33753tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
33754let Inst{7-5} = 0b111;
33755let Inst{13-13} = 0b0;
33756let Inst{31-21} = 0b00011100111;
33757let hasNewValue = 1;
33758let opNewValue = 0;
33759let isCVI = 1;
33760let DecoderNamespace = "EXT_mmvec";
33761}
33762def V6_vmpabuuv_alt : HInst<
33763(outs HvxWR:$Vdd32),
33764(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33765"$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
33766PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33767let hasNewValue = 1;
33768let opNewValue = 0;
33769let isCVI = 1;
33770let isPseudo = 1;
33771let isCodeGenOnly = 1;
33772let DecoderNamespace = "EXT_mmvec";
33773}
33774def V6_vmpahb : HInst<
33775(outs HvxWR:$Vdd32),
33776(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33777"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
33778tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33779let Inst{7-5} = 0b111;
33780let Inst{13-13} = 0b0;
33781let Inst{31-21} = 0b00011001001;
33782let hasNewValue = 1;
33783let opNewValue = 0;
33784let isCVI = 1;
33785let DecoderNamespace = "EXT_mmvec";
33786}
33787def V6_vmpahb_acc : HInst<
33788(outs HvxWR:$Vxx32),
33789(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33790"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
33791tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33792let Inst{7-5} = 0b111;
33793let Inst{13-13} = 0b1;
33794let Inst{31-21} = 0b00011001001;
33795let hasNewValue = 1;
33796let opNewValue = 0;
33797let isAccumulator = 1;
33798let isCVI = 1;
33799let DecoderNamespace = "EXT_mmvec";
33800let Constraints = "$Vxx32 = $Vxx32in";
33801}
33802def V6_vmpahb_acc_alt : HInst<
33803(outs HvxWR:$Vxx32),
33804(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33805"$Vxx32 += vmpahb($Vuu32,$Rt32)",
33806PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33807let hasNewValue = 1;
33808let opNewValue = 0;
33809let isAccumulator = 1;
33810let isCVI = 1;
33811let isPseudo = 1;
33812let isCodeGenOnly = 1;
33813let DecoderNamespace = "EXT_mmvec";
33814let Constraints = "$Vxx32 = $Vxx32in";
33815}
33816def V6_vmpahb_alt : HInst<
33817(outs HvxWR:$Vdd32),
33818(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33819"$Vdd32 = vmpahb($Vuu32,$Rt32)",
33820PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33821let hasNewValue = 1;
33822let opNewValue = 0;
33823let isCVI = 1;
33824let isPseudo = 1;
33825let isCodeGenOnly = 1;
33826let DecoderNamespace = "EXT_mmvec";
33827}
33828def V6_vmpahhsat : HInst<
33829(outs HvxVR:$Vx32),
33830(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
33831"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
33832tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
33833let Inst{7-5} = 0b100;
33834let Inst{13-13} = 0b1;
33835let Inst{31-21} = 0b00011001100;
33836let hasNewValue = 1;
33837let opNewValue = 0;
33838let isCVI = 1;
33839let DecoderNamespace = "EXT_mmvec";
33840let Constraints = "$Vx32 = $Vx32in";
33841}
33842def V6_vmpauhb : HInst<
33843(outs HvxWR:$Vdd32),
33844(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33845"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
33846tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
33847let Inst{7-5} = 0b101;
33848let Inst{13-13} = 0b0;
33849let Inst{31-21} = 0b00011001100;
33850let hasNewValue = 1;
33851let opNewValue = 0;
33852let isCVI = 1;
33853let DecoderNamespace = "EXT_mmvec";
33854}
33855def V6_vmpauhb_acc : HInst<
33856(outs HvxWR:$Vxx32),
33857(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33858"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
33859tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
33860let Inst{7-5} = 0b010;
33861let Inst{13-13} = 0b1;
33862let Inst{31-21} = 0b00011001100;
33863let hasNewValue = 1;
33864let opNewValue = 0;
33865let isAccumulator = 1;
33866let isCVI = 1;
33867let DecoderNamespace = "EXT_mmvec";
33868let Constraints = "$Vxx32 = $Vxx32in";
33869}
33870def V6_vmpauhb_acc_alt : HInst<
33871(outs HvxWR:$Vxx32),
33872(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33873"$Vxx32 += vmpauhb($Vuu32,$Rt32)",
33874PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33875let hasNewValue = 1;
33876let opNewValue = 0;
33877let isAccumulator = 1;
33878let isCVI = 1;
33879let isPseudo = 1;
33880let isCodeGenOnly = 1;
33881let DecoderNamespace = "EXT_mmvec";
33882let Constraints = "$Vxx32 = $Vxx32in";
33883}
33884def V6_vmpauhb_alt : HInst<
33885(outs HvxWR:$Vdd32),
33886(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33887"$Vdd32 = vmpauhb($Vuu32,$Rt32)",
33888PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33889let hasNewValue = 1;
33890let opNewValue = 0;
33891let isCVI = 1;
33892let isPseudo = 1;
33893let isCodeGenOnly = 1;
33894let DecoderNamespace = "EXT_mmvec";
33895}
33896def V6_vmpauhuhsat : HInst<
33897(outs HvxVR:$Vx32),
33898(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
33899"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
33900tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
33901let Inst{7-5} = 0b101;
33902let Inst{13-13} = 0b1;
33903let Inst{31-21} = 0b00011001100;
33904let hasNewValue = 1;
33905let opNewValue = 0;
33906let isCVI = 1;
33907let DecoderNamespace = "EXT_mmvec";
33908let Constraints = "$Vx32 = $Vx32in";
33909}
33910def V6_vmpsuhuhsat : HInst<
33911(outs HvxVR:$Vx32),
33912(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
33913"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
33914tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
33915let Inst{7-5} = 0b110;
33916let Inst{13-13} = 0b1;
33917let Inst{31-21} = 0b00011001100;
33918let hasNewValue = 1;
33919let opNewValue = 0;
33920let isCVI = 1;
33921let DecoderNamespace = "EXT_mmvec";
33922let Constraints = "$Vx32 = $Vx32in";
33923}
33924def V6_vmpybus : HInst<
33925(outs HvxWR:$Vdd32),
33926(ins HvxVR:$Vu32, IntRegs:$Rt32),
33927"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
33928tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
33929let Inst{7-5} = 0b101;
33930let Inst{13-13} = 0b0;
33931let Inst{31-21} = 0b00011001001;
33932let hasNewValue = 1;
33933let opNewValue = 0;
33934let isCVI = 1;
33935let DecoderNamespace = "EXT_mmvec";
33936}
33937def V6_vmpybus_acc : HInst<
33938(outs HvxWR:$Vxx32),
33939(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33940"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
33941tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
33942let Inst{7-5} = 0b101;
33943let Inst{13-13} = 0b1;
33944let Inst{31-21} = 0b00011001001;
33945let hasNewValue = 1;
33946let opNewValue = 0;
33947let isAccumulator = 1;
33948let isCVI = 1;
33949let DecoderNamespace = "EXT_mmvec";
33950let Constraints = "$Vxx32 = $Vxx32in";
33951}
33952def V6_vmpybus_acc_alt : HInst<
33953(outs HvxWR:$Vxx32),
33954(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33955"$Vxx32 += vmpybus($Vu32,$Rt32)",
33956PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33957let hasNewValue = 1;
33958let opNewValue = 0;
33959let isAccumulator = 1;
33960let isCVI = 1;
33961let isPseudo = 1;
33962let isCodeGenOnly = 1;
33963let DecoderNamespace = "EXT_mmvec";
33964let Constraints = "$Vxx32 = $Vxx32in";
33965}
33966def V6_vmpybus_alt : HInst<
33967(outs HvxWR:$Vdd32),
33968(ins HvxVR:$Vu32, IntRegs:$Rt32),
33969"$Vdd32 = vmpybus($Vu32,$Rt32)",
33970PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33971let hasNewValue = 1;
33972let opNewValue = 0;
33973let isCVI = 1;
33974let isPseudo = 1;
33975let isCodeGenOnly = 1;
33976let DecoderNamespace = "EXT_mmvec";
33977}
33978def V6_vmpybusv : HInst<
33979(outs HvxWR:$Vdd32),
33980(ins HvxVR:$Vu32, HvxVR:$Vv32),
33981"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
33982tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33983let Inst{7-5} = 0b110;
33984let Inst{13-13} = 0b0;
33985let Inst{31-21} = 0b00011100000;
33986let hasNewValue = 1;
33987let opNewValue = 0;
33988let isCVI = 1;
33989let DecoderNamespace = "EXT_mmvec";
33990}
33991def V6_vmpybusv_acc : HInst<
33992(outs HvxWR:$Vxx32),
33993(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33994"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
33995tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33996let Inst{7-5} = 0b110;
33997let Inst{13-13} = 0b1;
33998let Inst{31-21} = 0b00011100000;
33999let hasNewValue = 1;
34000let opNewValue = 0;
34001let isAccumulator = 1;
34002let isCVI = 1;
34003let DecoderNamespace = "EXT_mmvec";
34004let Constraints = "$Vxx32 = $Vxx32in";
34005}
34006def V6_vmpybusv_acc_alt : HInst<
34007(outs HvxWR:$Vxx32),
34008(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34009"$Vxx32 += vmpybus($Vu32,$Vv32)",
34010PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34011let hasNewValue = 1;
34012let opNewValue = 0;
34013let isAccumulator = 1;
34014let isCVI = 1;
34015let isPseudo = 1;
34016let isCodeGenOnly = 1;
34017let DecoderNamespace = "EXT_mmvec";
34018let Constraints = "$Vxx32 = $Vxx32in";
34019}
34020def V6_vmpybusv_alt : HInst<
34021(outs HvxWR:$Vdd32),
34022(ins HvxVR:$Vu32, HvxVR:$Vv32),
34023"$Vdd32 = vmpybus($Vu32,$Vv32)",
34024PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34025let hasNewValue = 1;
34026let opNewValue = 0;
34027let isCVI = 1;
34028let isPseudo = 1;
34029let isCodeGenOnly = 1;
34030let DecoderNamespace = "EXT_mmvec";
34031}
34032def V6_vmpybv : HInst<
34033(outs HvxWR:$Vdd32),
34034(ins HvxVR:$Vu32, HvxVR:$Vv32),
34035"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
34036tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34037let Inst{7-5} = 0b100;
34038let Inst{13-13} = 0b0;
34039let Inst{31-21} = 0b00011100000;
34040let hasNewValue = 1;
34041let opNewValue = 0;
34042let isCVI = 1;
34043let DecoderNamespace = "EXT_mmvec";
34044}
34045def V6_vmpybv_acc : HInst<
34046(outs HvxWR:$Vxx32),
34047(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34048"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
34049tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34050let Inst{7-5} = 0b100;
34051let Inst{13-13} = 0b1;
34052let Inst{31-21} = 0b00011100000;
34053let hasNewValue = 1;
34054let opNewValue = 0;
34055let isAccumulator = 1;
34056let isCVI = 1;
34057let DecoderNamespace = "EXT_mmvec";
34058let Constraints = "$Vxx32 = $Vxx32in";
34059}
34060def V6_vmpybv_acc_alt : HInst<
34061(outs HvxWR:$Vxx32),
34062(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34063"$Vxx32 += vmpyb($Vu32,$Vv32)",
34064PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34065let hasNewValue = 1;
34066let opNewValue = 0;
34067let isAccumulator = 1;
34068let isCVI = 1;
34069let isPseudo = 1;
34070let isCodeGenOnly = 1;
34071let DecoderNamespace = "EXT_mmvec";
34072let Constraints = "$Vxx32 = $Vxx32in";
34073}
34074def V6_vmpybv_alt : HInst<
34075(outs HvxWR:$Vdd32),
34076(ins HvxVR:$Vu32, HvxVR:$Vv32),
34077"$Vdd32 = vmpyb($Vu32,$Vv32)",
34078PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34079let hasNewValue = 1;
34080let opNewValue = 0;
34081let isCVI = 1;
34082let isPseudo = 1;
34083let isCodeGenOnly = 1;
34084let DecoderNamespace = "EXT_mmvec";
34085}
34086def V6_vmpyewuh : HInst<
34087(outs HvxVR:$Vd32),
34088(ins HvxVR:$Vu32, HvxVR:$Vv32),
34089"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
34090tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34091let Inst{7-5} = 0b101;
34092let Inst{13-13} = 0b0;
34093let Inst{31-21} = 0b00011111111;
34094let hasNewValue = 1;
34095let opNewValue = 0;
34096let isCVI = 1;
34097let DecoderNamespace = "EXT_mmvec";
34098}
34099def V6_vmpyewuh_64 : HInst<
34100(outs HvxWR:$Vdd32),
34101(ins HvxVR:$Vu32, HvxVR:$Vv32),
34102"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
34103tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
34104let Inst{7-5} = 0b110;
34105let Inst{13-13} = 0b0;
34106let Inst{31-21} = 0b00011110101;
34107let hasNewValue = 1;
34108let opNewValue = 0;
34109let isCVI = 1;
34110let DecoderNamespace = "EXT_mmvec";
34111}
34112def V6_vmpyewuh_alt : HInst<
34113(outs HvxVR:$Vd32),
34114(ins HvxVR:$Vu32, HvxVR:$Vv32),
34115"$Vd32 = vmpyewuh($Vu32,$Vv32)",
34116PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34117let hasNewValue = 1;
34118let opNewValue = 0;
34119let isCVI = 1;
34120let isPseudo = 1;
34121let isCodeGenOnly = 1;
34122let DecoderNamespace = "EXT_mmvec";
34123}
34124def V6_vmpyh : HInst<
34125(outs HvxWR:$Vdd32),
34126(ins HvxVR:$Vu32, IntRegs:$Rt32),
34127"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
34128tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
34129let Inst{7-5} = 0b000;
34130let Inst{13-13} = 0b0;
34131let Inst{31-21} = 0b00011001010;
34132let hasNewValue = 1;
34133let opNewValue = 0;
34134let isCVI = 1;
34135let DecoderNamespace = "EXT_mmvec";
34136}
34137def V6_vmpyh_acc : HInst<
34138(outs HvxWR:$Vxx32),
34139(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34140"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
34141tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
34142let Inst{7-5} = 0b110;
34143let Inst{13-13} = 0b1;
34144let Inst{31-21} = 0b00011001101;
34145let hasNewValue = 1;
34146let opNewValue = 0;
34147let isAccumulator = 1;
34148let isCVI = 1;
34149let DecoderNamespace = "EXT_mmvec";
34150let Constraints = "$Vxx32 = $Vxx32in";
34151}
34152def V6_vmpyh_acc_alt : HInst<
34153(outs HvxWR:$Vxx32),
34154(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34155"$Vxx32 += vmpyh($Vu32,$Rt32)",
34156PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34157let hasNewValue = 1;
34158let opNewValue = 0;
34159let isAccumulator = 1;
34160let isCVI = 1;
34161let isPseudo = 1;
34162let isCodeGenOnly = 1;
34163let DecoderNamespace = "EXT_mmvec";
34164let Constraints = "$Vxx32 = $Vxx32in";
34165}
34166def V6_vmpyh_alt : HInst<
34167(outs HvxWR:$Vdd32),
34168(ins HvxVR:$Vu32, IntRegs:$Rt32),
34169"$Vdd32 = vmpyh($Vu32,$Rt32)",
34170PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34171let hasNewValue = 1;
34172let opNewValue = 0;
34173let isCVI = 1;
34174let isPseudo = 1;
34175let isCodeGenOnly = 1;
34176let DecoderNamespace = "EXT_mmvec";
34177}
34178def V6_vmpyhsat_acc : HInst<
34179(outs HvxWR:$Vxx32),
34180(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34181"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
34182tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
34183let Inst{7-5} = 0b000;
34184let Inst{13-13} = 0b1;
34185let Inst{31-21} = 0b00011001010;
34186let hasNewValue = 1;
34187let opNewValue = 0;
34188let isAccumulator = 1;
34189let isCVI = 1;
34190let DecoderNamespace = "EXT_mmvec";
34191let Constraints = "$Vxx32 = $Vxx32in";
34192}
34193def V6_vmpyhsat_acc_alt : HInst<
34194(outs HvxWR:$Vxx32),
34195(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34196"$Vxx32 += vmpyh($Vu32,$Rt32):sat",
34197PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34198let hasNewValue = 1;
34199let opNewValue = 0;
34200let isAccumulator = 1;
34201let isCVI = 1;
34202let isPseudo = 1;
34203let isCodeGenOnly = 1;
34204let DecoderNamespace = "EXT_mmvec";
34205let Constraints = "$Vxx32 = $Vxx32in";
34206}
34207def V6_vmpyhsrs : HInst<
34208(outs HvxVR:$Vd32),
34209(ins HvxVR:$Vu32, IntRegs:$Rt32),
34210"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
34211tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
34212let Inst{7-5} = 0b010;
34213let Inst{13-13} = 0b0;
34214let Inst{31-21} = 0b00011001010;
34215let hasNewValue = 1;
34216let opNewValue = 0;
34217let isCVI = 1;
34218let DecoderNamespace = "EXT_mmvec";
34219}
34220def V6_vmpyhsrs_alt : HInst<
34221(outs HvxVR:$Vd32),
34222(ins HvxVR:$Vu32, IntRegs:$Rt32),
34223"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
34224PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34225let hasNewValue = 1;
34226let opNewValue = 0;
34227let isCVI = 1;
34228let isPseudo = 1;
34229let isCodeGenOnly = 1;
34230let DecoderNamespace = "EXT_mmvec";
34231}
34232def V6_vmpyhss : HInst<
34233(outs HvxVR:$Vd32),
34234(ins HvxVR:$Vu32, IntRegs:$Rt32),
34235"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
34236tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
34237let Inst{7-5} = 0b001;
34238let Inst{13-13} = 0b0;
34239let Inst{31-21} = 0b00011001010;
34240let hasNewValue = 1;
34241let opNewValue = 0;
34242let isCVI = 1;
34243let DecoderNamespace = "EXT_mmvec";
34244}
34245def V6_vmpyhss_alt : HInst<
34246(outs HvxVR:$Vd32),
34247(ins HvxVR:$Vu32, IntRegs:$Rt32),
34248"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
34249PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34250let hasNewValue = 1;
34251let opNewValue = 0;
34252let isCVI = 1;
34253let isPseudo = 1;
34254let isCodeGenOnly = 1;
34255let DecoderNamespace = "EXT_mmvec";
34256}
34257def V6_vmpyhus : HInst<
34258(outs HvxWR:$Vdd32),
34259(ins HvxVR:$Vu32, HvxVR:$Vv32),
34260"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
34261tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34262let Inst{7-5} = 0b010;
34263let Inst{13-13} = 0b0;
34264let Inst{31-21} = 0b00011100001;
34265let hasNewValue = 1;
34266let opNewValue = 0;
34267let isCVI = 1;
34268let DecoderNamespace = "EXT_mmvec";
34269}
34270def V6_vmpyhus_acc : HInst<
34271(outs HvxWR:$Vxx32),
34272(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34273"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
34274tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34275let Inst{7-5} = 0b001;
34276let Inst{13-13} = 0b1;
34277let Inst{31-21} = 0b00011100001;
34278let hasNewValue = 1;
34279let opNewValue = 0;
34280let isAccumulator = 1;
34281let isCVI = 1;
34282let DecoderNamespace = "EXT_mmvec";
34283let Constraints = "$Vxx32 = $Vxx32in";
34284}
34285def V6_vmpyhus_acc_alt : HInst<
34286(outs HvxWR:$Vxx32),
34287(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34288"$Vxx32 += vmpyhus($Vu32,$Vv32)",
34289PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34290let hasNewValue = 1;
34291let opNewValue = 0;
34292let isAccumulator = 1;
34293let isCVI = 1;
34294let isPseudo = 1;
34295let isCodeGenOnly = 1;
34296let DecoderNamespace = "EXT_mmvec";
34297let Constraints = "$Vxx32 = $Vxx32in";
34298}
34299def V6_vmpyhus_alt : HInst<
34300(outs HvxWR:$Vdd32),
34301(ins HvxVR:$Vu32, HvxVR:$Vv32),
34302"$Vdd32 = vmpyhus($Vu32,$Vv32)",
34303PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34304let hasNewValue = 1;
34305let opNewValue = 0;
34306let isCVI = 1;
34307let isPseudo = 1;
34308let isCodeGenOnly = 1;
34309let DecoderNamespace = "EXT_mmvec";
34310}
34311def V6_vmpyhv : HInst<
34312(outs HvxWR:$Vdd32),
34313(ins HvxVR:$Vu32, HvxVR:$Vv32),
34314"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
34315tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34316let Inst{7-5} = 0b111;
34317let Inst{13-13} = 0b0;
34318let Inst{31-21} = 0b00011100000;
34319let hasNewValue = 1;
34320let opNewValue = 0;
34321let isCVI = 1;
34322let DecoderNamespace = "EXT_mmvec";
34323}
34324def V6_vmpyhv_acc : HInst<
34325(outs HvxWR:$Vxx32),
34326(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34327"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
34328tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34329let Inst{7-5} = 0b111;
34330let Inst{13-13} = 0b1;
34331let Inst{31-21} = 0b00011100000;
34332let hasNewValue = 1;
34333let opNewValue = 0;
34334let isAccumulator = 1;
34335let isCVI = 1;
34336let DecoderNamespace = "EXT_mmvec";
34337let Constraints = "$Vxx32 = $Vxx32in";
34338}
34339def V6_vmpyhv_acc_alt : HInst<
34340(outs HvxWR:$Vxx32),
34341(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34342"$Vxx32 += vmpyh($Vu32,$Vv32)",
34343PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34344let hasNewValue = 1;
34345let opNewValue = 0;
34346let isAccumulator = 1;
34347let isCVI = 1;
34348let isPseudo = 1;
34349let isCodeGenOnly = 1;
34350let DecoderNamespace = "EXT_mmvec";
34351let Constraints = "$Vxx32 = $Vxx32in";
34352}
34353def V6_vmpyhv_alt : HInst<
34354(outs HvxWR:$Vdd32),
34355(ins HvxVR:$Vu32, HvxVR:$Vv32),
34356"$Vdd32 = vmpyh($Vu32,$Vv32)",
34357PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34358let hasNewValue = 1;
34359let opNewValue = 0;
34360let isCVI = 1;
34361let isPseudo = 1;
34362let isCodeGenOnly = 1;
34363let DecoderNamespace = "EXT_mmvec";
34364}
34365def V6_vmpyhvsrs : HInst<
34366(outs HvxVR:$Vd32),
34367(ins HvxVR:$Vu32, HvxVR:$Vv32),
34368"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
34369tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34370let Inst{7-5} = 0b001;
34371let Inst{13-13} = 0b0;
34372let Inst{31-21} = 0b00011100001;
34373let hasNewValue = 1;
34374let opNewValue = 0;
34375let isCVI = 1;
34376let DecoderNamespace = "EXT_mmvec";
34377}
34378def V6_vmpyhvsrs_alt : HInst<
34379(outs HvxVR:$Vd32),
34380(ins HvxVR:$Vu32, HvxVR:$Vv32),
34381"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
34382PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34383let hasNewValue = 1;
34384let opNewValue = 0;
34385let isCVI = 1;
34386let isPseudo = 1;
34387let isCodeGenOnly = 1;
34388let DecoderNamespace = "EXT_mmvec";
34389}
34390def V6_vmpyieoh : HInst<
34391(outs HvxVR:$Vd32),
34392(ins HvxVR:$Vu32, HvxVR:$Vv32),
34393"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
34394tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
34395let Inst{7-5} = 0b000;
34396let Inst{13-13} = 0b0;
34397let Inst{31-21} = 0b00011111011;
34398let hasNewValue = 1;
34399let opNewValue = 0;
34400let isCVI = 1;
34401let DecoderNamespace = "EXT_mmvec";
34402}
34403def V6_vmpyiewh_acc : HInst<
34404(outs HvxVR:$Vx32),
34405(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34406"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
34407tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34408let Inst{7-5} = 0b000;
34409let Inst{13-13} = 0b1;
34410let Inst{31-21} = 0b00011100010;
34411let hasNewValue = 1;
34412let opNewValue = 0;
34413let isAccumulator = 1;
34414let isCVI = 1;
34415let DecoderNamespace = "EXT_mmvec";
34416let Constraints = "$Vx32 = $Vx32in";
34417}
34418def V6_vmpyiewh_acc_alt : HInst<
34419(outs HvxVR:$Vx32),
34420(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34421"$Vx32 += vmpyiewh($Vu32,$Vv32)",
34422PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34423let hasNewValue = 1;
34424let opNewValue = 0;
34425let isAccumulator = 1;
34426let isCVI = 1;
34427let isPseudo = 1;
34428let isCodeGenOnly = 1;
34429let DecoderNamespace = "EXT_mmvec";
34430let Constraints = "$Vx32 = $Vx32in";
34431}
34432def V6_vmpyiewuh : HInst<
34433(outs HvxVR:$Vd32),
34434(ins HvxVR:$Vu32, HvxVR:$Vv32),
34435"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
34436tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34437let Inst{7-5} = 0b000;
34438let Inst{13-13} = 0b0;
34439let Inst{31-21} = 0b00011111110;
34440let hasNewValue = 1;
34441let opNewValue = 0;
34442let isCVI = 1;
34443let DecoderNamespace = "EXT_mmvec";
34444}
34445def V6_vmpyiewuh_acc : HInst<
34446(outs HvxVR:$Vx32),
34447(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34448"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
34449tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34450let Inst{7-5} = 0b101;
34451let Inst{13-13} = 0b1;
34452let Inst{31-21} = 0b00011100001;
34453let hasNewValue = 1;
34454let opNewValue = 0;
34455let isAccumulator = 1;
34456let isCVI = 1;
34457let DecoderNamespace = "EXT_mmvec";
34458let Constraints = "$Vx32 = $Vx32in";
34459}
34460def V6_vmpyiewuh_acc_alt : HInst<
34461(outs HvxVR:$Vx32),
34462(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34463"$Vx32 += vmpyiewuh($Vu32,$Vv32)",
34464PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34465let hasNewValue = 1;
34466let opNewValue = 0;
34467let isAccumulator = 1;
34468let isCVI = 1;
34469let isPseudo = 1;
34470let isCodeGenOnly = 1;
34471let DecoderNamespace = "EXT_mmvec";
34472let Constraints = "$Vx32 = $Vx32in";
34473}
34474def V6_vmpyiewuh_alt : HInst<
34475(outs HvxVR:$Vd32),
34476(ins HvxVR:$Vu32, HvxVR:$Vv32),
34477"$Vd32 = vmpyiewuh($Vu32,$Vv32)",
34478PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34479let hasNewValue = 1;
34480let opNewValue = 0;
34481let isCVI = 1;
34482let isPseudo = 1;
34483let isCodeGenOnly = 1;
34484let DecoderNamespace = "EXT_mmvec";
34485}
34486def V6_vmpyih : HInst<
34487(outs HvxVR:$Vd32),
34488(ins HvxVR:$Vu32, HvxVR:$Vv32),
34489"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
34490tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34491let Inst{7-5} = 0b100;
34492let Inst{13-13} = 0b0;
34493let Inst{31-21} = 0b00011100001;
34494let hasNewValue = 1;
34495let opNewValue = 0;
34496let isCVI = 1;
34497let DecoderNamespace = "EXT_mmvec";
34498}
34499def V6_vmpyih_acc : HInst<
34500(outs HvxVR:$Vx32),
34501(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34502"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
34503tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34504let Inst{7-5} = 0b100;
34505let Inst{13-13} = 0b1;
34506let Inst{31-21} = 0b00011100001;
34507let hasNewValue = 1;
34508let opNewValue = 0;
34509let isAccumulator = 1;
34510let isCVI = 1;
34511let DecoderNamespace = "EXT_mmvec";
34512let Constraints = "$Vx32 = $Vx32in";
34513}
34514def V6_vmpyih_acc_alt : HInst<
34515(outs HvxVR:$Vx32),
34516(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34517"$Vx32 += vmpyih($Vu32,$Vv32)",
34518PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34519let hasNewValue = 1;
34520let opNewValue = 0;
34521let isAccumulator = 1;
34522let isCVI = 1;
34523let isPseudo = 1;
34524let isCodeGenOnly = 1;
34525let DecoderNamespace = "EXT_mmvec";
34526let Constraints = "$Vx32 = $Vx32in";
34527}
34528def V6_vmpyih_alt : HInst<
34529(outs HvxVR:$Vd32),
34530(ins HvxVR:$Vu32, HvxVR:$Vv32),
34531"$Vd32 = vmpyih($Vu32,$Vv32)",
34532PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34533let hasNewValue = 1;
34534let opNewValue = 0;
34535let isCVI = 1;
34536let isPseudo = 1;
34537let isCodeGenOnly = 1;
34538let DecoderNamespace = "EXT_mmvec";
34539}
34540def V6_vmpyihb : HInst<
34541(outs HvxVR:$Vd32),
34542(ins HvxVR:$Vu32, IntRegs:$Rt32),
34543"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
34544tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34545let Inst{7-5} = 0b000;
34546let Inst{13-13} = 0b0;
34547let Inst{31-21} = 0b00011001011;
34548let hasNewValue = 1;
34549let opNewValue = 0;
34550let isCVI = 1;
34551let DecoderNamespace = "EXT_mmvec";
34552}
34553def V6_vmpyihb_acc : HInst<
34554(outs HvxVR:$Vx32),
34555(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34556"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
34557tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
34558let Inst{7-5} = 0b001;
34559let Inst{13-13} = 0b1;
34560let Inst{31-21} = 0b00011001011;
34561let hasNewValue = 1;
34562let opNewValue = 0;
34563let isAccumulator = 1;
34564let isCVI = 1;
34565let DecoderNamespace = "EXT_mmvec";
34566let Constraints = "$Vx32 = $Vx32in";
34567}
34568def V6_vmpyihb_acc_alt : HInst<
34569(outs HvxVR:$Vx32),
34570(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34571"$Vx32 += vmpyihb($Vu32,$Rt32)",
34572PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34573let hasNewValue = 1;
34574let opNewValue = 0;
34575let isAccumulator = 1;
34576let isCVI = 1;
34577let isPseudo = 1;
34578let isCodeGenOnly = 1;
34579let DecoderNamespace = "EXT_mmvec";
34580let Constraints = "$Vx32 = $Vx32in";
34581}
34582def V6_vmpyihb_alt : HInst<
34583(outs HvxVR:$Vd32),
34584(ins HvxVR:$Vu32, IntRegs:$Rt32),
34585"$Vd32 = vmpyihb($Vu32,$Rt32)",
34586PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34587let hasNewValue = 1;
34588let opNewValue = 0;
34589let isCVI = 1;
34590let isPseudo = 1;
34591let isCodeGenOnly = 1;
34592let DecoderNamespace = "EXT_mmvec";
34593}
34594def V6_vmpyiowh : HInst<
34595(outs HvxVR:$Vd32),
34596(ins HvxVR:$Vu32, HvxVR:$Vv32),
34597"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
34598tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34599let Inst{7-5} = 0b001;
34600let Inst{13-13} = 0b0;
34601let Inst{31-21} = 0b00011111110;
34602let hasNewValue = 1;
34603let opNewValue = 0;
34604let isCVI = 1;
34605let DecoderNamespace = "EXT_mmvec";
34606}
34607def V6_vmpyiowh_alt : HInst<
34608(outs HvxVR:$Vd32),
34609(ins HvxVR:$Vu32, HvxVR:$Vv32),
34610"$Vd32 = vmpyiowh($Vu32,$Vv32)",
34611PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34612let hasNewValue = 1;
34613let opNewValue = 0;
34614let isCVI = 1;
34615let isPseudo = 1;
34616let isCodeGenOnly = 1;
34617let DecoderNamespace = "EXT_mmvec";
34618}
34619def V6_vmpyiwb : HInst<
34620(outs HvxVR:$Vd32),
34621(ins HvxVR:$Vu32, IntRegs:$Rt32),
34622"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
34623tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34624let Inst{7-5} = 0b000;
34625let Inst{13-13} = 0b0;
34626let Inst{31-21} = 0b00011001101;
34627let hasNewValue = 1;
34628let opNewValue = 0;
34629let isCVI = 1;
34630let DecoderNamespace = "EXT_mmvec";
34631}
34632def V6_vmpyiwb_acc : HInst<
34633(outs HvxVR:$Vx32),
34634(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34635"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
34636tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
34637let Inst{7-5} = 0b010;
34638let Inst{13-13} = 0b1;
34639let Inst{31-21} = 0b00011001010;
34640let hasNewValue = 1;
34641let opNewValue = 0;
34642let isAccumulator = 1;
34643let isCVI = 1;
34644let DecoderNamespace = "EXT_mmvec";
34645let Constraints = "$Vx32 = $Vx32in";
34646}
34647def V6_vmpyiwb_acc_alt : HInst<
34648(outs HvxVR:$Vx32),
34649(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34650"$Vx32 += vmpyiwb($Vu32,$Rt32)",
34651PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34652let hasNewValue = 1;
34653let opNewValue = 0;
34654let isAccumulator = 1;
34655let isCVI = 1;
34656let isPseudo = 1;
34657let isCodeGenOnly = 1;
34658let DecoderNamespace = "EXT_mmvec";
34659let Constraints = "$Vx32 = $Vx32in";
34660}
34661def V6_vmpyiwb_alt : HInst<
34662(outs HvxVR:$Vd32),
34663(ins HvxVR:$Vu32, IntRegs:$Rt32),
34664"$Vd32 = vmpyiwb($Vu32,$Rt32)",
34665PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34666let hasNewValue = 1;
34667let opNewValue = 0;
34668let isCVI = 1;
34669let isPseudo = 1;
34670let isCodeGenOnly = 1;
34671let DecoderNamespace = "EXT_mmvec";
34672}
34673def V6_vmpyiwh : HInst<
34674(outs HvxVR:$Vd32),
34675(ins HvxVR:$Vu32, IntRegs:$Rt32),
34676"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
34677tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
34678let Inst{7-5} = 0b111;
34679let Inst{13-13} = 0b0;
34680let Inst{31-21} = 0b00011001100;
34681let hasNewValue = 1;
34682let opNewValue = 0;
34683let isCVI = 1;
34684let DecoderNamespace = "EXT_mmvec";
34685}
34686def V6_vmpyiwh_acc : HInst<
34687(outs HvxVR:$Vx32),
34688(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34689"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
34690tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
34691let Inst{7-5} = 0b011;
34692let Inst{13-13} = 0b1;
34693let Inst{31-21} = 0b00011001010;
34694let hasNewValue = 1;
34695let opNewValue = 0;
34696let isAccumulator = 1;
34697let isCVI = 1;
34698let DecoderNamespace = "EXT_mmvec";
34699let Constraints = "$Vx32 = $Vx32in";
34700}
34701def V6_vmpyiwh_acc_alt : HInst<
34702(outs HvxVR:$Vx32),
34703(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34704"$Vx32 += vmpyiwh($Vu32,$Rt32)",
34705PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34706let hasNewValue = 1;
34707let opNewValue = 0;
34708let isAccumulator = 1;
34709let isCVI = 1;
34710let isPseudo = 1;
34711let isCodeGenOnly = 1;
34712let DecoderNamespace = "EXT_mmvec";
34713let Constraints = "$Vx32 = $Vx32in";
34714}
34715def V6_vmpyiwh_alt : HInst<
34716(outs HvxVR:$Vd32),
34717(ins HvxVR:$Vu32, IntRegs:$Rt32),
34718"$Vd32 = vmpyiwh($Vu32,$Rt32)",
34719PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34720let hasNewValue = 1;
34721let opNewValue = 0;
34722let isCVI = 1;
34723let isPseudo = 1;
34724let isCodeGenOnly = 1;
34725let DecoderNamespace = "EXT_mmvec";
34726}
34727def V6_vmpyiwub : HInst<
34728(outs HvxVR:$Vd32),
34729(ins HvxVR:$Vu32, IntRegs:$Rt32),
34730"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
34731tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
34732let Inst{7-5} = 0b110;
34733let Inst{13-13} = 0b0;
34734let Inst{31-21} = 0b00011001100;
34735let hasNewValue = 1;
34736let opNewValue = 0;
34737let isCVI = 1;
34738let DecoderNamespace = "EXT_mmvec";
34739}
34740def V6_vmpyiwub_acc : HInst<
34741(outs HvxVR:$Vx32),
34742(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34743"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
34744tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
34745let Inst{7-5} = 0b001;
34746let Inst{13-13} = 0b1;
34747let Inst{31-21} = 0b00011001100;
34748let hasNewValue = 1;
34749let opNewValue = 0;
34750let isAccumulator = 1;
34751let isCVI = 1;
34752let DecoderNamespace = "EXT_mmvec";
34753let Constraints = "$Vx32 = $Vx32in";
34754}
34755def V6_vmpyiwub_acc_alt : HInst<
34756(outs HvxVR:$Vx32),
34757(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34758"$Vx32 += vmpyiwub($Vu32,$Rt32)",
34759PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34760let hasNewValue = 1;
34761let opNewValue = 0;
34762let isAccumulator = 1;
34763let isCVI = 1;
34764let isPseudo = 1;
34765let isCodeGenOnly = 1;
34766let DecoderNamespace = "EXT_mmvec";
34767let Constraints = "$Vx32 = $Vx32in";
34768}
34769def V6_vmpyiwub_alt : HInst<
34770(outs HvxVR:$Vd32),
34771(ins HvxVR:$Vu32, IntRegs:$Rt32),
34772"$Vd32 = vmpyiwub($Vu32,$Rt32)",
34773PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34774let hasNewValue = 1;
34775let opNewValue = 0;
34776let isCVI = 1;
34777let isPseudo = 1;
34778let isCodeGenOnly = 1;
34779let DecoderNamespace = "EXT_mmvec";
34780}
34781def V6_vmpyowh : HInst<
34782(outs HvxVR:$Vd32),
34783(ins HvxVR:$Vu32, HvxVR:$Vv32),
34784"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
34785tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34786let Inst{7-5} = 0b111;
34787let Inst{13-13} = 0b0;
34788let Inst{31-21} = 0b00011111111;
34789let hasNewValue = 1;
34790let opNewValue = 0;
34791let isCVI = 1;
34792let DecoderNamespace = "EXT_mmvec";
34793}
34794def V6_vmpyowh_64_acc : HInst<
34795(outs HvxWR:$Vxx32),
34796(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34797"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
34798tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
34799let Inst{7-5} = 0b011;
34800let Inst{13-13} = 0b1;
34801let Inst{31-21} = 0b00011100001;
34802let hasNewValue = 1;
34803let opNewValue = 0;
34804let isAccumulator = 1;
34805let isCVI = 1;
34806let DecoderNamespace = "EXT_mmvec";
34807let Constraints = "$Vxx32 = $Vxx32in";
34808}
34809def V6_vmpyowh_alt : HInst<
34810(outs HvxVR:$Vd32),
34811(ins HvxVR:$Vu32, HvxVR:$Vv32),
34812"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
34813PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34814let hasNewValue = 1;
34815let opNewValue = 0;
34816let isCVI = 1;
34817let isPseudo = 1;
34818let isCodeGenOnly = 1;
34819let DecoderNamespace = "EXT_mmvec";
34820}
34821def V6_vmpyowh_rnd : HInst<
34822(outs HvxVR:$Vd32),
34823(ins HvxVR:$Vu32, HvxVR:$Vv32),
34824"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
34825tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34826let Inst{7-5} = 0b000;
34827let Inst{13-13} = 0b0;
34828let Inst{31-21} = 0b00011111010;
34829let hasNewValue = 1;
34830let opNewValue = 0;
34831let isCVI = 1;
34832let DecoderNamespace = "EXT_mmvec";
34833}
34834def V6_vmpyowh_rnd_alt : HInst<
34835(outs HvxVR:$Vd32),
34836(ins HvxVR:$Vu32, HvxVR:$Vv32),
34837"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
34838PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34839let hasNewValue = 1;
34840let opNewValue = 0;
34841let isCVI = 1;
34842let isPseudo = 1;
34843let isCodeGenOnly = 1;
34844let DecoderNamespace = "EXT_mmvec";
34845}
34846def V6_vmpyowh_rnd_sacc : HInst<
34847(outs HvxVR:$Vx32),
34848(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34849"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
34850tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34851let Inst{7-5} = 0b111;
34852let Inst{13-13} = 0b1;
34853let Inst{31-21} = 0b00011100001;
34854let hasNewValue = 1;
34855let opNewValue = 0;
34856let isAccumulator = 1;
34857let isCVI = 1;
34858let DecoderNamespace = "EXT_mmvec";
34859let Constraints = "$Vx32 = $Vx32in";
34860}
34861def V6_vmpyowh_rnd_sacc_alt : HInst<
34862(outs HvxVR:$Vx32),
34863(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34864"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
34865PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34866let hasNewValue = 1;
34867let opNewValue = 0;
34868let isAccumulator = 1;
34869let isCVI = 1;
34870let isPseudo = 1;
34871let DecoderNamespace = "EXT_mmvec";
34872let Constraints = "$Vx32 = $Vx32in";
34873}
34874def V6_vmpyowh_sacc : HInst<
34875(outs HvxVR:$Vx32),
34876(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34877"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
34878tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34879let Inst{7-5} = 0b110;
34880let Inst{13-13} = 0b1;
34881let Inst{31-21} = 0b00011100001;
34882let hasNewValue = 1;
34883let opNewValue = 0;
34884let isAccumulator = 1;
34885let isCVI = 1;
34886let DecoderNamespace = "EXT_mmvec";
34887let Constraints = "$Vx32 = $Vx32in";
34888}
34889def V6_vmpyowh_sacc_alt : HInst<
34890(outs HvxVR:$Vx32),
34891(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34892"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
34893PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34894let hasNewValue = 1;
34895let opNewValue = 0;
34896let isAccumulator = 1;
34897let isCVI = 1;
34898let isPseudo = 1;
34899let DecoderNamespace = "EXT_mmvec";
34900let Constraints = "$Vx32 = $Vx32in";
34901}
34902def V6_vmpyub : HInst<
34903(outs HvxWR:$Vdd32),
34904(ins HvxVR:$Vu32, IntRegs:$Rt32),
34905"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
34906tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
34907let Inst{7-5} = 0b000;
34908let Inst{13-13} = 0b0;
34909let Inst{31-21} = 0b00011001110;
34910let hasNewValue = 1;
34911let opNewValue = 0;
34912let isCVI = 1;
34913let DecoderNamespace = "EXT_mmvec";
34914}
34915def V6_vmpyub_acc : HInst<
34916(outs HvxWR:$Vxx32),
34917(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34918"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
34919tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
34920let Inst{7-5} = 0b000;
34921let Inst{13-13} = 0b1;
34922let Inst{31-21} = 0b00011001100;
34923let hasNewValue = 1;
34924let opNewValue = 0;
34925let isAccumulator = 1;
34926let isCVI = 1;
34927let DecoderNamespace = "EXT_mmvec";
34928let Constraints = "$Vxx32 = $Vxx32in";
34929}
34930def V6_vmpyub_acc_alt : HInst<
34931(outs HvxWR:$Vxx32),
34932(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34933"$Vxx32 += vmpyub($Vu32,$Rt32)",
34934PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34935let hasNewValue = 1;
34936let opNewValue = 0;
34937let isAccumulator = 1;
34938let isCVI = 1;
34939let isPseudo = 1;
34940let isCodeGenOnly = 1;
34941let DecoderNamespace = "EXT_mmvec";
34942let Constraints = "$Vxx32 = $Vxx32in";
34943}
34944def V6_vmpyub_alt : HInst<
34945(outs HvxWR:$Vdd32),
34946(ins HvxVR:$Vu32, IntRegs:$Rt32),
34947"$Vdd32 = vmpyub($Vu32,$Rt32)",
34948PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34949let hasNewValue = 1;
34950let opNewValue = 0;
34951let isCVI = 1;
34952let isPseudo = 1;
34953let isCodeGenOnly = 1;
34954let DecoderNamespace = "EXT_mmvec";
34955}
34956def V6_vmpyubv : HInst<
34957(outs HvxWR:$Vdd32),
34958(ins HvxVR:$Vu32, HvxVR:$Vv32),
34959"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
34960tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34961let Inst{7-5} = 0b101;
34962let Inst{13-13} = 0b0;
34963let Inst{31-21} = 0b00011100000;
34964let hasNewValue = 1;
34965let opNewValue = 0;
34966let isCVI = 1;
34967let DecoderNamespace = "EXT_mmvec";
34968}
34969def V6_vmpyubv_acc : HInst<
34970(outs HvxWR:$Vxx32),
34971(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34972"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
34973tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34974let Inst{7-5} = 0b101;
34975let Inst{13-13} = 0b1;
34976let Inst{31-21} = 0b00011100000;
34977let hasNewValue = 1;
34978let opNewValue = 0;
34979let isAccumulator = 1;
34980let isCVI = 1;
34981let DecoderNamespace = "EXT_mmvec";
34982let Constraints = "$Vxx32 = $Vxx32in";
34983}
34984def V6_vmpyubv_acc_alt : HInst<
34985(outs HvxWR:$Vxx32),
34986(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34987"$Vxx32 += vmpyub($Vu32,$Vv32)",
34988PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34989let hasNewValue = 1;
34990let opNewValue = 0;
34991let isAccumulator = 1;
34992let isCVI = 1;
34993let isPseudo = 1;
34994let isCodeGenOnly = 1;
34995let DecoderNamespace = "EXT_mmvec";
34996let Constraints = "$Vxx32 = $Vxx32in";
34997}
34998def V6_vmpyubv_alt : HInst<
34999(outs HvxWR:$Vdd32),
35000(ins HvxVR:$Vu32, HvxVR:$Vv32),
35001"$Vdd32 = vmpyub($Vu32,$Vv32)",
35002PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35003let hasNewValue = 1;
35004let opNewValue = 0;
35005let isCVI = 1;
35006let isPseudo = 1;
35007let isCodeGenOnly = 1;
35008let DecoderNamespace = "EXT_mmvec";
35009}
35010def V6_vmpyuh : HInst<
35011(outs HvxWR:$Vdd32),
35012(ins HvxVR:$Vu32, IntRegs:$Rt32),
35013"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
35014tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35015let Inst{7-5} = 0b011;
35016let Inst{13-13} = 0b0;
35017let Inst{31-21} = 0b00011001010;
35018let hasNewValue = 1;
35019let opNewValue = 0;
35020let isCVI = 1;
35021let DecoderNamespace = "EXT_mmvec";
35022}
35023def V6_vmpyuh_acc : HInst<
35024(outs HvxWR:$Vxx32),
35025(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35026"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
35027tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35028let Inst{7-5} = 0b001;
35029let Inst{13-13} = 0b1;
35030let Inst{31-21} = 0b00011001010;
35031let hasNewValue = 1;
35032let opNewValue = 0;
35033let isAccumulator = 1;
35034let isCVI = 1;
35035let DecoderNamespace = "EXT_mmvec";
35036let Constraints = "$Vxx32 = $Vxx32in";
35037}
35038def V6_vmpyuh_acc_alt : HInst<
35039(outs HvxWR:$Vxx32),
35040(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35041"$Vxx32 += vmpyuh($Vu32,$Rt32)",
35042PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35043let hasNewValue = 1;
35044let opNewValue = 0;
35045let isAccumulator = 1;
35046let isCVI = 1;
35047let isPseudo = 1;
35048let isCodeGenOnly = 1;
35049let DecoderNamespace = "EXT_mmvec";
35050let Constraints = "$Vxx32 = $Vxx32in";
35051}
35052def V6_vmpyuh_alt : HInst<
35053(outs HvxWR:$Vdd32),
35054(ins HvxVR:$Vu32, IntRegs:$Rt32),
35055"$Vdd32 = vmpyuh($Vu32,$Rt32)",
35056PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35057let hasNewValue = 1;
35058let opNewValue = 0;
35059let isCVI = 1;
35060let isPseudo = 1;
35061let isCodeGenOnly = 1;
35062let DecoderNamespace = "EXT_mmvec";
35063}
35064def V6_vmpyuhe : HInst<
35065(outs HvxVR:$Vd32),
35066(ins HvxVR:$Vu32, IntRegs:$Rt32),
35067"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
35068tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
35069let Inst{7-5} = 0b010;
35070let Inst{13-13} = 0b0;
35071let Inst{31-21} = 0b00011001011;
35072let hasNewValue = 1;
35073let opNewValue = 0;
35074let isCVI = 1;
35075let DecoderNamespace = "EXT_mmvec";
35076}
35077def V6_vmpyuhe_acc : HInst<
35078(outs HvxVR:$Vx32),
35079(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35080"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
35081tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
35082let Inst{7-5} = 0b011;
35083let Inst{13-13} = 0b1;
35084let Inst{31-21} = 0b00011001100;
35085let hasNewValue = 1;
35086let opNewValue = 0;
35087let isAccumulator = 1;
35088let isCVI = 1;
35089let DecoderNamespace = "EXT_mmvec";
35090let Constraints = "$Vx32 = $Vx32in";
35091}
35092def V6_vmpyuhv : HInst<
35093(outs HvxWR:$Vdd32),
35094(ins HvxVR:$Vu32, HvxVR:$Vv32),
35095"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
35096tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35097let Inst{7-5} = 0b000;
35098let Inst{13-13} = 0b0;
35099let Inst{31-21} = 0b00011100001;
35100let hasNewValue = 1;
35101let opNewValue = 0;
35102let isCVI = 1;
35103let DecoderNamespace = "EXT_mmvec";
35104}
35105def V6_vmpyuhv_acc : HInst<
35106(outs HvxWR:$Vxx32),
35107(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35108"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
35109tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35110let Inst{7-5} = 0b000;
35111let Inst{13-13} = 0b1;
35112let Inst{31-21} = 0b00011100001;
35113let hasNewValue = 1;
35114let opNewValue = 0;
35115let isAccumulator = 1;
35116let isCVI = 1;
35117let DecoderNamespace = "EXT_mmvec";
35118let Constraints = "$Vxx32 = $Vxx32in";
35119}
35120def V6_vmpyuhv_acc_alt : HInst<
35121(outs HvxWR:$Vxx32),
35122(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35123"$Vxx32 += vmpyuh($Vu32,$Vv32)",
35124PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35125let hasNewValue = 1;
35126let opNewValue = 0;
35127let isAccumulator = 1;
35128let isCVI = 1;
35129let isPseudo = 1;
35130let isCodeGenOnly = 1;
35131let DecoderNamespace = "EXT_mmvec";
35132let Constraints = "$Vxx32 = $Vxx32in";
35133}
35134def V6_vmpyuhv_alt : HInst<
35135(outs HvxWR:$Vdd32),
35136(ins HvxVR:$Vu32, HvxVR:$Vv32),
35137"$Vdd32 = vmpyuh($Vu32,$Vv32)",
35138PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35139let hasNewValue = 1;
35140let opNewValue = 0;
35141let isCVI = 1;
35142let isPseudo = 1;
35143let isCodeGenOnly = 1;
35144let DecoderNamespace = "EXT_mmvec";
35145}
35146def V6_vmux : HInst<
35147(outs HvxVR:$Vd32),
35148(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
35149"$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
35150tc_257f6f7c, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
35151let Inst{7-7} = 0b0;
35152let Inst{13-13} = 0b1;
35153let Inst{31-21} = 0b00011110111;
35154let hasNewValue = 1;
35155let opNewValue = 0;
35156let isCVI = 1;
35157let DecoderNamespace = "EXT_mmvec";
35158}
35159def V6_vnavgb : HInst<
35160(outs HvxVR:$Vd32),
35161(ins HvxVR:$Vu32, HvxVR:$Vv32),
35162"$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
35163tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
35164let Inst{7-5} = 0b110;
35165let Inst{13-13} = 0b1;
35166let Inst{31-21} = 0b00011111000;
35167let hasNewValue = 1;
35168let opNewValue = 0;
35169let isCVI = 1;
35170let DecoderNamespace = "EXT_mmvec";
35171}
35172def V6_vnavgb_alt : HInst<
35173(outs HvxVR:$Vd32),
35174(ins HvxVR:$Vu32, HvxVR:$Vv32),
35175"$Vd32 = vnavgb($Vu32,$Vv32)",
35176PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35177let hasNewValue = 1;
35178let opNewValue = 0;
35179let isCVI = 1;
35180let isPseudo = 1;
35181let isCodeGenOnly = 1;
35182let DecoderNamespace = "EXT_mmvec";
35183}
35184def V6_vnavgh : HInst<
35185(outs HvxVR:$Vd32),
35186(ins HvxVR:$Vu32, HvxVR:$Vv32),
35187"$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
35188tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35189let Inst{7-5} = 0b001;
35190let Inst{13-13} = 0b0;
35191let Inst{31-21} = 0b00011100111;
35192let hasNewValue = 1;
35193let opNewValue = 0;
35194let isCVI = 1;
35195let DecoderNamespace = "EXT_mmvec";
35196}
35197def V6_vnavgh_alt : HInst<
35198(outs HvxVR:$Vd32),
35199(ins HvxVR:$Vu32, HvxVR:$Vv32),
35200"$Vd32 = vnavgh($Vu32,$Vv32)",
35201PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35202let hasNewValue = 1;
35203let opNewValue = 0;
35204let isCVI = 1;
35205let isPseudo = 1;
35206let isCodeGenOnly = 1;
35207let DecoderNamespace = "EXT_mmvec";
35208}
35209def V6_vnavgub : HInst<
35210(outs HvxVR:$Vd32),
35211(ins HvxVR:$Vu32, HvxVR:$Vv32),
35212"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
35213tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35214let Inst{7-5} = 0b000;
35215let Inst{13-13} = 0b0;
35216let Inst{31-21} = 0b00011100111;
35217let hasNewValue = 1;
35218let opNewValue = 0;
35219let isCVI = 1;
35220let DecoderNamespace = "EXT_mmvec";
35221}
35222def V6_vnavgub_alt : HInst<
35223(outs HvxVR:$Vd32),
35224(ins HvxVR:$Vu32, HvxVR:$Vv32),
35225"$Vd32 = vnavgub($Vu32,$Vv32)",
35226PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35227let hasNewValue = 1;
35228let opNewValue = 0;
35229let isCVI = 1;
35230let isPseudo = 1;
35231let isCodeGenOnly = 1;
35232let DecoderNamespace = "EXT_mmvec";
35233}
35234def V6_vnavgw : HInst<
35235(outs HvxVR:$Vd32),
35236(ins HvxVR:$Vu32, HvxVR:$Vv32),
35237"$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
35238tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35239let Inst{7-5} = 0b010;
35240let Inst{13-13} = 0b0;
35241let Inst{31-21} = 0b00011100111;
35242let hasNewValue = 1;
35243let opNewValue = 0;
35244let isCVI = 1;
35245let DecoderNamespace = "EXT_mmvec";
35246}
35247def V6_vnavgw_alt : HInst<
35248(outs HvxVR:$Vd32),
35249(ins HvxVR:$Vu32, HvxVR:$Vv32),
35250"$Vd32 = vnavgw($Vu32,$Vv32)",
35251PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35252let hasNewValue = 1;
35253let opNewValue = 0;
35254let isCVI = 1;
35255let isPseudo = 1;
35256let isCodeGenOnly = 1;
35257let DecoderNamespace = "EXT_mmvec";
35258}
35259def V6_vnccombine : HInst<
35260(outs HvxWR:$Vdd32),
35261(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
35262"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
35263tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
35264let Inst{7-7} = 0b0;
35265let Inst{13-13} = 0b0;
35266let Inst{31-21} = 0b00011010010;
35267let isPredicated = 1;
35268let isPredicatedFalse = 1;
35269let hasNewValue = 1;
35270let opNewValue = 0;
35271let isCVI = 1;
35272let DecoderNamespace = "EXT_mmvec";
35273}
35274def V6_vncmov : HInst<
35275(outs HvxVR:$Vd32),
35276(ins PredRegs:$Ps4, HvxVR:$Vu32),
35277"if (!$Ps4) $Vd32 = $Vu32",
35278tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
35279let Inst{7-7} = 0b0;
35280let Inst{13-13} = 0b0;
35281let Inst{31-16} = 0b0001101000100000;
35282let isPredicated = 1;
35283let isPredicatedFalse = 1;
35284let hasNewValue = 1;
35285let opNewValue = 0;
35286let isCVI = 1;
35287let DecoderNamespace = "EXT_mmvec";
35288}
35289def V6_vnormamth : HInst<
35290(outs HvxVR:$Vd32),
35291(ins HvxVR:$Vu32),
35292"$Vd32.h = vnormamt($Vu32.h)",
35293tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
35294let Inst{7-5} = 0b101;
35295let Inst{13-13} = 0b0;
35296let Inst{31-16} = 0b0001111000000011;
35297let hasNewValue = 1;
35298let opNewValue = 0;
35299let isCVI = 1;
35300let DecoderNamespace = "EXT_mmvec";
35301}
35302def V6_vnormamth_alt : HInst<
35303(outs HvxVR:$Vd32),
35304(ins HvxVR:$Vu32),
35305"$Vd32 = vnormamth($Vu32)",
35306PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35307let hasNewValue = 1;
35308let opNewValue = 0;
35309let isCVI = 1;
35310let isPseudo = 1;
35311let isCodeGenOnly = 1;
35312let DecoderNamespace = "EXT_mmvec";
35313}
35314def V6_vnormamtw : HInst<
35315(outs HvxVR:$Vd32),
35316(ins HvxVR:$Vu32),
35317"$Vd32.w = vnormamt($Vu32.w)",
35318tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
35319let Inst{7-5} = 0b100;
35320let Inst{13-13} = 0b0;
35321let Inst{31-16} = 0b0001111000000011;
35322let hasNewValue = 1;
35323let opNewValue = 0;
35324let isCVI = 1;
35325let DecoderNamespace = "EXT_mmvec";
35326}
35327def V6_vnormamtw_alt : HInst<
35328(outs HvxVR:$Vd32),
35329(ins HvxVR:$Vu32),
35330"$Vd32 = vnormamtw($Vu32)",
35331PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35332let hasNewValue = 1;
35333let opNewValue = 0;
35334let isCVI = 1;
35335let isPseudo = 1;
35336let isCodeGenOnly = 1;
35337let DecoderNamespace = "EXT_mmvec";
35338}
35339def V6_vnot : HInst<
35340(outs HvxVR:$Vd32),
35341(ins HvxVR:$Vu32),
35342"$Vd32 = vnot($Vu32)",
35343tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
35344let Inst{7-5} = 0b100;
35345let Inst{13-13} = 0b0;
35346let Inst{31-16} = 0b0001111000000000;
35347let hasNewValue = 1;
35348let opNewValue = 0;
35349let isCVI = 1;
35350let DecoderNamespace = "EXT_mmvec";
35351}
35352def V6_vor : HInst<
35353(outs HvxVR:$Vd32),
35354(ins HvxVR:$Vu32, HvxVR:$Vv32),
35355"$Vd32 = vor($Vu32,$Vv32)",
35356tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35357let Inst{7-5} = 0b110;
35358let Inst{13-13} = 0b0;
35359let Inst{31-21} = 0b00011100001;
35360let hasNewValue = 1;
35361let opNewValue = 0;
35362let isCVI = 1;
35363let DecoderNamespace = "EXT_mmvec";
35364}
35365def V6_vpackeb : HInst<
35366(outs HvxVR:$Vd32),
35367(ins HvxVR:$Vu32, HvxVR:$Vv32),
35368"$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
35369tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35370let Inst{7-5} = 0b010;
35371let Inst{13-13} = 0b0;
35372let Inst{31-21} = 0b00011111110;
35373let hasNewValue = 1;
35374let opNewValue = 0;
35375let isCVI = 1;
35376let DecoderNamespace = "EXT_mmvec";
35377}
35378def V6_vpackeb_alt : HInst<
35379(outs HvxVR:$Vd32),
35380(ins HvxVR:$Vu32, HvxVR:$Vv32),
35381"$Vd32 = vpackeb($Vu32,$Vv32)",
35382PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35383let hasNewValue = 1;
35384let opNewValue = 0;
35385let isCVI = 1;
35386let isPseudo = 1;
35387let isCodeGenOnly = 1;
35388let DecoderNamespace = "EXT_mmvec";
35389}
35390def V6_vpackeh : HInst<
35391(outs HvxVR:$Vd32),
35392(ins HvxVR:$Vu32, HvxVR:$Vv32),
35393"$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
35394tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35395let Inst{7-5} = 0b011;
35396let Inst{13-13} = 0b0;
35397let Inst{31-21} = 0b00011111110;
35398let hasNewValue = 1;
35399let opNewValue = 0;
35400let isCVI = 1;
35401let DecoderNamespace = "EXT_mmvec";
35402}
35403def V6_vpackeh_alt : HInst<
35404(outs HvxVR:$Vd32),
35405(ins HvxVR:$Vu32, HvxVR:$Vv32),
35406"$Vd32 = vpackeh($Vu32,$Vv32)",
35407PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35408let hasNewValue = 1;
35409let opNewValue = 0;
35410let isCVI = 1;
35411let isPseudo = 1;
35412let isCodeGenOnly = 1;
35413let DecoderNamespace = "EXT_mmvec";
35414}
35415def V6_vpackhb_sat : HInst<
35416(outs HvxVR:$Vd32),
35417(ins HvxVR:$Vu32, HvxVR:$Vv32),
35418"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
35419tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35420let Inst{7-5} = 0b110;
35421let Inst{13-13} = 0b0;
35422let Inst{31-21} = 0b00011111110;
35423let hasNewValue = 1;
35424let opNewValue = 0;
35425let isCVI = 1;
35426let DecoderNamespace = "EXT_mmvec";
35427}
35428def V6_vpackhb_sat_alt : HInst<
35429(outs HvxVR:$Vd32),
35430(ins HvxVR:$Vu32, HvxVR:$Vv32),
35431"$Vd32 = vpackhb($Vu32,$Vv32):sat",
35432PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35433let hasNewValue = 1;
35434let opNewValue = 0;
35435let isCVI = 1;
35436let isPseudo = 1;
35437let isCodeGenOnly = 1;
35438let DecoderNamespace = "EXT_mmvec";
35439}
35440def V6_vpackhub_sat : HInst<
35441(outs HvxVR:$Vd32),
35442(ins HvxVR:$Vu32, HvxVR:$Vv32),
35443"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
35444tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35445let Inst{7-5} = 0b101;
35446let Inst{13-13} = 0b0;
35447let Inst{31-21} = 0b00011111110;
35448let hasNewValue = 1;
35449let opNewValue = 0;
35450let isCVI = 1;
35451let DecoderNamespace = "EXT_mmvec";
35452}
35453def V6_vpackhub_sat_alt : HInst<
35454(outs HvxVR:$Vd32),
35455(ins HvxVR:$Vu32, HvxVR:$Vv32),
35456"$Vd32 = vpackhub($Vu32,$Vv32):sat",
35457PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35458let hasNewValue = 1;
35459let opNewValue = 0;
35460let isCVI = 1;
35461let isPseudo = 1;
35462let isCodeGenOnly = 1;
35463let DecoderNamespace = "EXT_mmvec";
35464}
35465def V6_vpackob : HInst<
35466(outs HvxVR:$Vd32),
35467(ins HvxVR:$Vu32, HvxVR:$Vv32),
35468"$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
35469tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35470let Inst{7-5} = 0b001;
35471let Inst{13-13} = 0b0;
35472let Inst{31-21} = 0b00011111111;
35473let hasNewValue = 1;
35474let opNewValue = 0;
35475let isCVI = 1;
35476let DecoderNamespace = "EXT_mmvec";
35477}
35478def V6_vpackob_alt : HInst<
35479(outs HvxVR:$Vd32),
35480(ins HvxVR:$Vu32, HvxVR:$Vv32),
35481"$Vd32 = vpackob($Vu32,$Vv32)",
35482PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35483let hasNewValue = 1;
35484let opNewValue = 0;
35485let isCVI = 1;
35486let isPseudo = 1;
35487let isCodeGenOnly = 1;
35488let DecoderNamespace = "EXT_mmvec";
35489}
35490def V6_vpackoh : HInst<
35491(outs HvxVR:$Vd32),
35492(ins HvxVR:$Vu32, HvxVR:$Vv32),
35493"$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
35494tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35495let Inst{7-5} = 0b010;
35496let Inst{13-13} = 0b0;
35497let Inst{31-21} = 0b00011111111;
35498let hasNewValue = 1;
35499let opNewValue = 0;
35500let isCVI = 1;
35501let DecoderNamespace = "EXT_mmvec";
35502}
35503def V6_vpackoh_alt : HInst<
35504(outs HvxVR:$Vd32),
35505(ins HvxVR:$Vu32, HvxVR:$Vv32),
35506"$Vd32 = vpackoh($Vu32,$Vv32)",
35507PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35508let hasNewValue = 1;
35509let opNewValue = 0;
35510let isCVI = 1;
35511let isPseudo = 1;
35512let isCodeGenOnly = 1;
35513let DecoderNamespace = "EXT_mmvec";
35514}
35515def V6_vpackwh_sat : HInst<
35516(outs HvxVR:$Vd32),
35517(ins HvxVR:$Vu32, HvxVR:$Vv32),
35518"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
35519tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35520let Inst{7-5} = 0b000;
35521let Inst{13-13} = 0b0;
35522let Inst{31-21} = 0b00011111111;
35523let hasNewValue = 1;
35524let opNewValue = 0;
35525let isCVI = 1;
35526let DecoderNamespace = "EXT_mmvec";
35527}
35528def V6_vpackwh_sat_alt : HInst<
35529(outs HvxVR:$Vd32),
35530(ins HvxVR:$Vu32, HvxVR:$Vv32),
35531"$Vd32 = vpackwh($Vu32,$Vv32):sat",
35532PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35533let hasNewValue = 1;
35534let opNewValue = 0;
35535let isCVI = 1;
35536let isPseudo = 1;
35537let isCodeGenOnly = 1;
35538let DecoderNamespace = "EXT_mmvec";
35539}
35540def V6_vpackwuh_sat : HInst<
35541(outs HvxVR:$Vd32),
35542(ins HvxVR:$Vu32, HvxVR:$Vv32),
35543"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
35544tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35545let Inst{7-5} = 0b111;
35546let Inst{13-13} = 0b0;
35547let Inst{31-21} = 0b00011111110;
35548let hasNewValue = 1;
35549let opNewValue = 0;
35550let isCVI = 1;
35551let DecoderNamespace = "EXT_mmvec";
35552}
35553def V6_vpackwuh_sat_alt : HInst<
35554(outs HvxVR:$Vd32),
35555(ins HvxVR:$Vu32, HvxVR:$Vv32),
35556"$Vd32 = vpackwuh($Vu32,$Vv32):sat",
35557PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35558let hasNewValue = 1;
35559let opNewValue = 0;
35560let isCVI = 1;
35561let isPseudo = 1;
35562let isCodeGenOnly = 1;
35563let DecoderNamespace = "EXT_mmvec";
35564}
35565def V6_vpopcounth : HInst<
35566(outs HvxVR:$Vd32),
35567(ins HvxVR:$Vu32),
35568"$Vd32.h = vpopcount($Vu32.h)",
35569tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
35570let Inst{7-5} = 0b110;
35571let Inst{13-13} = 0b0;
35572let Inst{31-16} = 0b0001111000000010;
35573let hasNewValue = 1;
35574let opNewValue = 0;
35575let isCVI = 1;
35576let DecoderNamespace = "EXT_mmvec";
35577}
35578def V6_vpopcounth_alt : HInst<
35579(outs HvxVR:$Vd32),
35580(ins HvxVR:$Vu32),
35581"$Vd32 = vpopcounth($Vu32)",
35582PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35583let hasNewValue = 1;
35584let opNewValue = 0;
35585let isCVI = 1;
35586let isPseudo = 1;
35587let isCodeGenOnly = 1;
35588let DecoderNamespace = "EXT_mmvec";
35589}
35590def V6_vprefixqb : HInst<
35591(outs HvxVR:$Vd32),
35592(ins HvxQR:$Qv4),
35593"$Vd32.b = prefixsum($Qv4)",
35594tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
35595let Inst{13-5} = 0b100000010;
35596let Inst{21-16} = 0b000011;
35597let Inst{31-24} = 0b00011110;
35598let hasNewValue = 1;
35599let opNewValue = 0;
35600let isCVI = 1;
35601let DecoderNamespace = "EXT_mmvec";
35602}
35603def V6_vprefixqh : HInst<
35604(outs HvxVR:$Vd32),
35605(ins HvxQR:$Qv4),
35606"$Vd32.h = prefixsum($Qv4)",
35607tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
35608let Inst{13-5} = 0b100001010;
35609let Inst{21-16} = 0b000011;
35610let Inst{31-24} = 0b00011110;
35611let hasNewValue = 1;
35612let opNewValue = 0;
35613let isCVI = 1;
35614let DecoderNamespace = "EXT_mmvec";
35615}
35616def V6_vprefixqw : HInst<
35617(outs HvxVR:$Vd32),
35618(ins HvxQR:$Qv4),
35619"$Vd32.w = prefixsum($Qv4)",
35620tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
35621let Inst{13-5} = 0b100010010;
35622let Inst{21-16} = 0b000011;
35623let Inst{31-24} = 0b00011110;
35624let hasNewValue = 1;
35625let opNewValue = 0;
35626let isCVI = 1;
35627let DecoderNamespace = "EXT_mmvec";
35628}
35629def V6_vrdelta : HInst<
35630(outs HvxVR:$Vd32),
35631(ins HvxVR:$Vu32, HvxVR:$Vv32),
35632"$Vd32 = vrdelta($Vu32,$Vv32)",
35633tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35634let Inst{7-5} = 0b011;
35635let Inst{13-13} = 0b0;
35636let Inst{31-21} = 0b00011111001;
35637let hasNewValue = 1;
35638let opNewValue = 0;
35639let isCVI = 1;
35640let DecoderNamespace = "EXT_mmvec";
35641}
35642def V6_vrmpybub_rtt : HInst<
35643(outs HvxWR:$Vdd32),
35644(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
35645"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
35646tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
35647let Inst{7-5} = 0b101;
35648let Inst{13-13} = 0b0;
35649let Inst{31-21} = 0b00011001110;
35650let hasNewValue = 1;
35651let opNewValue = 0;
35652let isCVI = 1;
35653let DecoderNamespace = "EXT_mmvec";
35654}
35655def V6_vrmpybub_rtt_acc : HInst<
35656(outs HvxWR:$Vxx32),
35657(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35658"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
35659tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
35660let Inst{7-5} = 0b000;
35661let Inst{13-13} = 0b1;
35662let Inst{31-21} = 0b00011001101;
35663let hasNewValue = 1;
35664let opNewValue = 0;
35665let isAccumulator = 1;
35666let isCVI = 1;
35667let DecoderNamespace = "EXT_mmvec";
35668let Constraints = "$Vxx32 = $Vxx32in";
35669}
35670def V6_vrmpybub_rtt_acc_alt : HInst<
35671(outs HvxWR:$Vxx32),
35672(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35673"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
35674PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35675let hasNewValue = 1;
35676let opNewValue = 0;
35677let isAccumulator = 1;
35678let isCVI = 1;
35679let isPseudo = 1;
35680let isCodeGenOnly = 1;
35681let DecoderNamespace = "EXT_mmvec";
35682let Constraints = "$Vxx32 = $Vxx32in";
35683}
35684def V6_vrmpybub_rtt_alt : HInst<
35685(outs HvxWR:$Vdd32),
35686(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
35687"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
35688PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35689let hasNewValue = 1;
35690let opNewValue = 0;
35691let isCVI = 1;
35692let isPseudo = 1;
35693let isCodeGenOnly = 1;
35694let DecoderNamespace = "EXT_mmvec";
35695}
35696def V6_vrmpybus : HInst<
35697(outs HvxVR:$Vd32),
35698(ins HvxVR:$Vu32, IntRegs:$Rt32),
35699"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
35700tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35701let Inst{7-5} = 0b100;
35702let Inst{13-13} = 0b0;
35703let Inst{31-21} = 0b00011001000;
35704let hasNewValue = 1;
35705let opNewValue = 0;
35706let isCVI = 1;
35707let DecoderNamespace = "EXT_mmvec";
35708}
35709def V6_vrmpybus_acc : HInst<
35710(outs HvxVR:$Vx32),
35711(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35712"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
35713tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
35714let Inst{7-5} = 0b101;
35715let Inst{13-13} = 0b1;
35716let Inst{31-21} = 0b00011001000;
35717let hasNewValue = 1;
35718let opNewValue = 0;
35719let isAccumulator = 1;
35720let isCVI = 1;
35721let DecoderNamespace = "EXT_mmvec";
35722let Constraints = "$Vx32 = $Vx32in";
35723}
35724def V6_vrmpybus_acc_alt : HInst<
35725(outs HvxVR:$Vx32),
35726(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35727"$Vx32 += vrmpybus($Vu32,$Rt32)",
35728PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35729let hasNewValue = 1;
35730let opNewValue = 0;
35731let isAccumulator = 1;
35732let isCVI = 1;
35733let isPseudo = 1;
35734let isCodeGenOnly = 1;
35735let DecoderNamespace = "EXT_mmvec";
35736let Constraints = "$Vx32 = $Vx32in";
35737}
35738def V6_vrmpybus_alt : HInst<
35739(outs HvxVR:$Vd32),
35740(ins HvxVR:$Vu32, IntRegs:$Rt32),
35741"$Vd32 = vrmpybus($Vu32,$Rt32)",
35742PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35743let hasNewValue = 1;
35744let opNewValue = 0;
35745let isCVI = 1;
35746let isPseudo = 1;
35747let isCodeGenOnly = 1;
35748let DecoderNamespace = "EXT_mmvec";
35749}
35750def V6_vrmpybusi : HInst<
35751(outs HvxWR:$Vdd32),
35752(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35753"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
35754tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
35755let Inst{7-6} = 0b10;
35756let Inst{13-13} = 0b0;
35757let Inst{31-21} = 0b00011001010;
35758let hasNewValue = 1;
35759let opNewValue = 0;
35760let isCVI = 1;
35761let DecoderNamespace = "EXT_mmvec";
35762}
35763def V6_vrmpybusi_acc : HInst<
35764(outs HvxWR:$Vxx32),
35765(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35766"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
35767tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
35768let Inst{7-6} = 0b10;
35769let Inst{13-13} = 0b1;
35770let Inst{31-21} = 0b00011001010;
35771let hasNewValue = 1;
35772let opNewValue = 0;
35773let isAccumulator = 1;
35774let isCVI = 1;
35775let DecoderNamespace = "EXT_mmvec";
35776let Constraints = "$Vxx32 = $Vxx32in";
35777}
35778def V6_vrmpybusi_acc_alt : HInst<
35779(outs HvxWR:$Vxx32),
35780(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35781"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
35782PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35783let hasNewValue = 1;
35784let opNewValue = 0;
35785let isAccumulator = 1;
35786let isCVI = 1;
35787let isPseudo = 1;
35788let isCodeGenOnly = 1;
35789let DecoderNamespace = "EXT_mmvec";
35790let Constraints = "$Vxx32 = $Vxx32in";
35791}
35792def V6_vrmpybusi_alt : HInst<
35793(outs HvxWR:$Vdd32),
35794(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35795"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
35796PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35797let hasNewValue = 1;
35798let opNewValue = 0;
35799let isCVI = 1;
35800let isPseudo = 1;
35801let isCodeGenOnly = 1;
35802let DecoderNamespace = "EXT_mmvec";
35803}
35804def V6_vrmpybusv : HInst<
35805(outs HvxVR:$Vd32),
35806(ins HvxVR:$Vu32, HvxVR:$Vv32),
35807"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
35808tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35809let Inst{7-5} = 0b010;
35810let Inst{13-13} = 0b0;
35811let Inst{31-21} = 0b00011100000;
35812let hasNewValue = 1;
35813let opNewValue = 0;
35814let isCVI = 1;
35815let DecoderNamespace = "EXT_mmvec";
35816}
35817def V6_vrmpybusv_acc : HInst<
35818(outs HvxVR:$Vx32),
35819(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35820"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
35821tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35822let Inst{7-5} = 0b010;
35823let Inst{13-13} = 0b1;
35824let Inst{31-21} = 0b00011100000;
35825let hasNewValue = 1;
35826let opNewValue = 0;
35827let isAccumulator = 1;
35828let isCVI = 1;
35829let DecoderNamespace = "EXT_mmvec";
35830let Constraints = "$Vx32 = $Vx32in";
35831}
35832def V6_vrmpybusv_acc_alt : HInst<
35833(outs HvxVR:$Vx32),
35834(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35835"$Vx32 += vrmpybus($Vu32,$Vv32)",
35836PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35837let hasNewValue = 1;
35838let opNewValue = 0;
35839let isAccumulator = 1;
35840let isCVI = 1;
35841let isPseudo = 1;
35842let isCodeGenOnly = 1;
35843let DecoderNamespace = "EXT_mmvec";
35844let Constraints = "$Vx32 = $Vx32in";
35845}
35846def V6_vrmpybusv_alt : HInst<
35847(outs HvxVR:$Vd32),
35848(ins HvxVR:$Vu32, HvxVR:$Vv32),
35849"$Vd32 = vrmpybus($Vu32,$Vv32)",
35850PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35851let hasNewValue = 1;
35852let opNewValue = 0;
35853let isCVI = 1;
35854let isPseudo = 1;
35855let isCodeGenOnly = 1;
35856let DecoderNamespace = "EXT_mmvec";
35857}
35858def V6_vrmpybv : HInst<
35859(outs HvxVR:$Vd32),
35860(ins HvxVR:$Vu32, HvxVR:$Vv32),
35861"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
35862tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35863let Inst{7-5} = 0b001;
35864let Inst{13-13} = 0b0;
35865let Inst{31-21} = 0b00011100000;
35866let hasNewValue = 1;
35867let opNewValue = 0;
35868let isCVI = 1;
35869let DecoderNamespace = "EXT_mmvec";
35870}
35871def V6_vrmpybv_acc : HInst<
35872(outs HvxVR:$Vx32),
35873(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35874"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
35875tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35876let Inst{7-5} = 0b001;
35877let Inst{13-13} = 0b1;
35878let Inst{31-21} = 0b00011100000;
35879let hasNewValue = 1;
35880let opNewValue = 0;
35881let isAccumulator = 1;
35882let isCVI = 1;
35883let DecoderNamespace = "EXT_mmvec";
35884let Constraints = "$Vx32 = $Vx32in";
35885}
35886def V6_vrmpybv_acc_alt : HInst<
35887(outs HvxVR:$Vx32),
35888(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35889"$Vx32 += vrmpyb($Vu32,$Vv32)",
35890PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35891let hasNewValue = 1;
35892let opNewValue = 0;
35893let isAccumulator = 1;
35894let isCVI = 1;
35895let isPseudo = 1;
35896let isCodeGenOnly = 1;
35897let DecoderNamespace = "EXT_mmvec";
35898let Constraints = "$Vx32 = $Vx32in";
35899}
35900def V6_vrmpybv_alt : HInst<
35901(outs HvxVR:$Vd32),
35902(ins HvxVR:$Vu32, HvxVR:$Vv32),
35903"$Vd32 = vrmpyb($Vu32,$Vv32)",
35904PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35905let hasNewValue = 1;
35906let opNewValue = 0;
35907let isCVI = 1;
35908let isPseudo = 1;
35909let isCodeGenOnly = 1;
35910let DecoderNamespace = "EXT_mmvec";
35911}
35912def V6_vrmpyub : HInst<
35913(outs HvxVR:$Vd32),
35914(ins HvxVR:$Vu32, IntRegs:$Rt32),
35915"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
35916tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35917let Inst{7-5} = 0b011;
35918let Inst{13-13} = 0b0;
35919let Inst{31-21} = 0b00011001000;
35920let hasNewValue = 1;
35921let opNewValue = 0;
35922let isCVI = 1;
35923let DecoderNamespace = "EXT_mmvec";
35924}
35925def V6_vrmpyub_acc : HInst<
35926(outs HvxVR:$Vx32),
35927(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35928"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
35929tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
35930let Inst{7-5} = 0b100;
35931let Inst{13-13} = 0b1;
35932let Inst{31-21} = 0b00011001000;
35933let hasNewValue = 1;
35934let opNewValue = 0;
35935let isAccumulator = 1;
35936let isCVI = 1;
35937let DecoderNamespace = "EXT_mmvec";
35938let Constraints = "$Vx32 = $Vx32in";
35939}
35940def V6_vrmpyub_acc_alt : HInst<
35941(outs HvxVR:$Vx32),
35942(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35943"$Vx32 += vrmpyub($Vu32,$Rt32)",
35944PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35945let hasNewValue = 1;
35946let opNewValue = 0;
35947let isAccumulator = 1;
35948let isCVI = 1;
35949let isPseudo = 1;
35950let isCodeGenOnly = 1;
35951let DecoderNamespace = "EXT_mmvec";
35952let Constraints = "$Vx32 = $Vx32in";
35953}
35954def V6_vrmpyub_alt : HInst<
35955(outs HvxVR:$Vd32),
35956(ins HvxVR:$Vu32, IntRegs:$Rt32),
35957"$Vd32 = vrmpyub($Vu32,$Rt32)",
35958PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35959let hasNewValue = 1;
35960let opNewValue = 0;
35961let isCVI = 1;
35962let isPseudo = 1;
35963let isCodeGenOnly = 1;
35964let DecoderNamespace = "EXT_mmvec";
35965}
35966def V6_vrmpyub_rtt : HInst<
35967(outs HvxWR:$Vdd32),
35968(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
35969"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
35970tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
35971let Inst{7-5} = 0b100;
35972let Inst{13-13} = 0b0;
35973let Inst{31-21} = 0b00011001110;
35974let hasNewValue = 1;
35975let opNewValue = 0;
35976let isCVI = 1;
35977let DecoderNamespace = "EXT_mmvec";
35978}
35979def V6_vrmpyub_rtt_acc : HInst<
35980(outs HvxWR:$Vxx32),
35981(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35982"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
35983tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
35984let Inst{7-5} = 0b111;
35985let Inst{13-13} = 0b1;
35986let Inst{31-21} = 0b00011001101;
35987let hasNewValue = 1;
35988let opNewValue = 0;
35989let isAccumulator = 1;
35990let isCVI = 1;
35991let DecoderNamespace = "EXT_mmvec";
35992let Constraints = "$Vxx32 = $Vxx32in";
35993}
35994def V6_vrmpyub_rtt_acc_alt : HInst<
35995(outs HvxWR:$Vxx32),
35996(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35997"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
35998PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35999let hasNewValue = 1;
36000let opNewValue = 0;
36001let isAccumulator = 1;
36002let isCVI = 1;
36003let isPseudo = 1;
36004let isCodeGenOnly = 1;
36005let DecoderNamespace = "EXT_mmvec";
36006let Constraints = "$Vxx32 = $Vxx32in";
36007}
36008def V6_vrmpyub_rtt_alt : HInst<
36009(outs HvxWR:$Vdd32),
36010(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
36011"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
36012PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36013let hasNewValue = 1;
36014let opNewValue = 0;
36015let isCVI = 1;
36016let isPseudo = 1;
36017let isCodeGenOnly = 1;
36018let DecoderNamespace = "EXT_mmvec";
36019}
36020def V6_vrmpyubi : HInst<
36021(outs HvxWR:$Vdd32),
36022(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36023"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
36024tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
36025let Inst{7-6} = 0b11;
36026let Inst{13-13} = 0b0;
36027let Inst{31-21} = 0b00011001101;
36028let hasNewValue = 1;
36029let opNewValue = 0;
36030let isCVI = 1;
36031let DecoderNamespace = "EXT_mmvec";
36032}
36033def V6_vrmpyubi_acc : HInst<
36034(outs HvxWR:$Vxx32),
36035(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36036"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
36037tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
36038let Inst{7-6} = 0b11;
36039let Inst{13-13} = 0b1;
36040let Inst{31-21} = 0b00011001011;
36041let hasNewValue = 1;
36042let opNewValue = 0;
36043let isAccumulator = 1;
36044let isCVI = 1;
36045let DecoderNamespace = "EXT_mmvec";
36046let Constraints = "$Vxx32 = $Vxx32in";
36047}
36048def V6_vrmpyubi_acc_alt : HInst<
36049(outs HvxWR:$Vxx32),
36050(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36051"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
36052PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36053let hasNewValue = 1;
36054let opNewValue = 0;
36055let isAccumulator = 1;
36056let isCVI = 1;
36057let isPseudo = 1;
36058let isCodeGenOnly = 1;
36059let DecoderNamespace = "EXT_mmvec";
36060let Constraints = "$Vxx32 = $Vxx32in";
36061}
36062def V6_vrmpyubi_alt : HInst<
36063(outs HvxWR:$Vdd32),
36064(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36065"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
36066PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36067let hasNewValue = 1;
36068let opNewValue = 0;
36069let isCVI = 1;
36070let isPseudo = 1;
36071let isCodeGenOnly = 1;
36072let DecoderNamespace = "EXT_mmvec";
36073}
36074def V6_vrmpyubv : HInst<
36075(outs HvxVR:$Vd32),
36076(ins HvxVR:$Vu32, HvxVR:$Vv32),
36077"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
36078tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
36079let Inst{7-5} = 0b000;
36080let Inst{13-13} = 0b0;
36081let Inst{31-21} = 0b00011100000;
36082let hasNewValue = 1;
36083let opNewValue = 0;
36084let isCVI = 1;
36085let DecoderNamespace = "EXT_mmvec";
36086}
36087def V6_vrmpyubv_acc : HInst<
36088(outs HvxVR:$Vx32),
36089(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36090"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
36091tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36092let Inst{7-5} = 0b000;
36093let Inst{13-13} = 0b1;
36094let Inst{31-21} = 0b00011100000;
36095let hasNewValue = 1;
36096let opNewValue = 0;
36097let isAccumulator = 1;
36098let isCVI = 1;
36099let DecoderNamespace = "EXT_mmvec";
36100let Constraints = "$Vx32 = $Vx32in";
36101}
36102def V6_vrmpyubv_acc_alt : HInst<
36103(outs HvxVR:$Vx32),
36104(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36105"$Vx32 += vrmpyub($Vu32,$Vv32)",
36106PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36107let hasNewValue = 1;
36108let opNewValue = 0;
36109let isAccumulator = 1;
36110let isCVI = 1;
36111let isPseudo = 1;
36112let isCodeGenOnly = 1;
36113let DecoderNamespace = "EXT_mmvec";
36114let Constraints = "$Vx32 = $Vx32in";
36115}
36116def V6_vrmpyubv_alt : HInst<
36117(outs HvxVR:$Vd32),
36118(ins HvxVR:$Vu32, HvxVR:$Vv32),
36119"$Vd32 = vrmpyub($Vu32,$Vv32)",
36120PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36121let hasNewValue = 1;
36122let opNewValue = 0;
36123let isCVI = 1;
36124let isPseudo = 1;
36125let isCodeGenOnly = 1;
36126let DecoderNamespace = "EXT_mmvec";
36127}
36128def V6_vrmpyzbb_rt : HInst<
36129(outs HvxVQR:$Vdddd32),
36130(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36131"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.b)",
36132tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36133let Inst{7-5} = 0b000;
36134let Inst{13-13} = 0b0;
36135let Inst{31-19} = 0b0001100111101;
36136let hasNewValue = 1;
36137let opNewValue = 0;
36138let isCVI = 1;
36139let DecoderNamespace = "EXT_mmvec";
36140}
36141def V6_vrmpyzbb_rt_acc : HInst<
36142(outs HvxVQR:$Vyyyy32),
36143(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36144"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.b)",
36145tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36146let Inst{7-5} = 0b010;
36147let Inst{13-13} = 0b1;
36148let Inst{31-19} = 0b0001100111000;
36149let hasNewValue = 1;
36150let opNewValue = 0;
36151let isAccumulator = 1;
36152let isCVI = 1;
36153let DecoderNamespace = "EXT_mmvec";
36154let Constraints = "$Vyyyy32 = $Vyyyy32in";
36155}
36156def V6_vrmpyzbb_rx : HInst<
36157(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36158(ins HvxVR:$Vu32, IntRegs:$Rx8in),
36159"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)",
36160tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36161let Inst{7-5} = 0b000;
36162let Inst{13-13} = 0b0;
36163let Inst{31-19} = 0b0001100111100;
36164let hasNewValue = 1;
36165let opNewValue = 0;
36166let isCVI = 1;
36167let DecoderNamespace = "EXT_mmvec";
36168let Constraints = "$Rx8 = $Rx8in";
36169}
36170def V6_vrmpyzbb_rx_acc : HInst<
36171(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36172(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
36173"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)",
36174tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36175let Inst{7-5} = 0b010;
36176let Inst{13-13} = 0b1;
36177let Inst{31-19} = 0b0001100111001;
36178let hasNewValue = 1;
36179let opNewValue = 0;
36180let isAccumulator = 1;
36181let isCVI = 1;
36182let DecoderNamespace = "EXT_mmvec";
36183let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36184}
36185def V6_vrmpyzbub_rt : HInst<
36186(outs HvxVQR:$Vdddd32),
36187(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36188"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.ub)",
36189tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36190let Inst{7-5} = 0b010;
36191let Inst{13-13} = 0b0;
36192let Inst{31-19} = 0b0001100111111;
36193let hasNewValue = 1;
36194let opNewValue = 0;
36195let isCVI = 1;
36196let DecoderNamespace = "EXT_mmvec";
36197}
36198def V6_vrmpyzbub_rt_acc : HInst<
36199(outs HvxVQR:$Vyyyy32),
36200(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36201"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.ub)",
36202tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36203let Inst{7-5} = 0b001;
36204let Inst{13-13} = 0b1;
36205let Inst{31-19} = 0b0001100111010;
36206let hasNewValue = 1;
36207let opNewValue = 0;
36208let isAccumulator = 1;
36209let isCVI = 1;
36210let DecoderNamespace = "EXT_mmvec";
36211let Constraints = "$Vyyyy32 = $Vyyyy32in";
36212}
36213def V6_vrmpyzbub_rx : HInst<
36214(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36215(ins HvxVR:$Vu32, IntRegs:$Rx8in),
36216"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)",
36217tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36218let Inst{7-5} = 0b010;
36219let Inst{13-13} = 0b0;
36220let Inst{31-19} = 0b0001100111110;
36221let hasNewValue = 1;
36222let opNewValue = 0;
36223let isCVI = 1;
36224let DecoderNamespace = "EXT_mmvec";
36225let Constraints = "$Rx8 = $Rx8in";
36226}
36227def V6_vrmpyzbub_rx_acc : HInst<
36228(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36229(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
36230"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)",
36231tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36232let Inst{7-5} = 0b001;
36233let Inst{13-13} = 0b1;
36234let Inst{31-19} = 0b0001100111011;
36235let hasNewValue = 1;
36236let opNewValue = 0;
36237let isAccumulator = 1;
36238let isCVI = 1;
36239let DecoderNamespace = "EXT_mmvec";
36240let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36241}
36242def V6_vrmpyzcb_rt : HInst<
36243(outs HvxVQR:$Vdddd32),
36244(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36245"$Vdddd32.w = vr16mpyz($Vu32.c,$Rt8.b)",
36246tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36247let Inst{7-5} = 0b001;
36248let Inst{13-13} = 0b0;
36249let Inst{31-19} = 0b0001100111101;
36250let hasNewValue = 1;
36251let opNewValue = 0;
36252let isCVI = 1;
36253let DecoderNamespace = "EXT_mmvec";
36254}
36255def V6_vrmpyzcb_rt_acc : HInst<
36256(outs HvxVQR:$Vyyyy32),
36257(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36258"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rt8.b)",
36259tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36260let Inst{7-5} = 0b011;
36261let Inst{13-13} = 0b1;
36262let Inst{31-19} = 0b0001100111000;
36263let hasNewValue = 1;
36264let opNewValue = 0;
36265let isAccumulator = 1;
36266let isCVI = 1;
36267let DecoderNamespace = "EXT_mmvec";
36268let Constraints = "$Vyyyy32 = $Vyyyy32in";
36269}
36270def V6_vrmpyzcb_rx : HInst<
36271(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36272(ins HvxVR:$Vu32, IntRegs:$Rx8in),
36273"$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)",
36274tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36275let Inst{7-5} = 0b001;
36276let Inst{13-13} = 0b0;
36277let Inst{31-19} = 0b0001100111100;
36278let hasNewValue = 1;
36279let opNewValue = 0;
36280let isCVI = 1;
36281let DecoderNamespace = "EXT_mmvec";
36282let Constraints = "$Rx8 = $Rx8in";
36283}
36284def V6_vrmpyzcb_rx_acc : HInst<
36285(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36286(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
36287"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)",
36288tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36289let Inst{7-5} = 0b011;
36290let Inst{13-13} = 0b1;
36291let Inst{31-19} = 0b0001100111001;
36292let hasNewValue = 1;
36293let opNewValue = 0;
36294let isAccumulator = 1;
36295let isCVI = 1;
36296let DecoderNamespace = "EXT_mmvec";
36297let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36298}
36299def V6_vrmpyzcbs_rt : HInst<
36300(outs HvxVQR:$Vdddd32),
36301(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36302"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rt8.b)",
36303tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36304let Inst{7-5} = 0b010;
36305let Inst{13-13} = 0b0;
36306let Inst{31-19} = 0b0001100111101;
36307let hasNewValue = 1;
36308let opNewValue = 0;
36309let isCVI = 1;
36310let DecoderNamespace = "EXT_mmvec";
36311}
36312def V6_vrmpyzcbs_rt_acc : HInst<
36313(outs HvxVQR:$Vyyyy32),
36314(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36315"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rt8.b)",
36316tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36317let Inst{7-5} = 0b001;
36318let Inst{13-13} = 0b1;
36319let Inst{31-19} = 0b0001100111000;
36320let hasNewValue = 1;
36321let opNewValue = 0;
36322let isAccumulator = 1;
36323let isCVI = 1;
36324let DecoderNamespace = "EXT_mmvec";
36325let Constraints = "$Vyyyy32 = $Vyyyy32in";
36326}
36327def V6_vrmpyzcbs_rx : HInst<
36328(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36329(ins HvxVR:$Vu32, IntRegs:$Rx8in),
36330"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)",
36331tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36332let Inst{7-5} = 0b010;
36333let Inst{13-13} = 0b0;
36334let Inst{31-19} = 0b0001100111100;
36335let hasNewValue = 1;
36336let opNewValue = 0;
36337let isCVI = 1;
36338let DecoderNamespace = "EXT_mmvec";
36339let Constraints = "$Rx8 = $Rx8in";
36340}
36341def V6_vrmpyzcbs_rx_acc : HInst<
36342(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36343(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
36344"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)",
36345tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36346let Inst{7-5} = 0b001;
36347let Inst{13-13} = 0b1;
36348let Inst{31-19} = 0b0001100111001;
36349let hasNewValue = 1;
36350let opNewValue = 0;
36351let isAccumulator = 1;
36352let isCVI = 1;
36353let DecoderNamespace = "EXT_mmvec";
36354let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36355}
36356def V6_vrmpyznb_rt : HInst<
36357(outs HvxVQR:$Vdddd32),
36358(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36359"$Vdddd32.w = vr8mpyz($Vu32.n,$Rt8.b)",
36360tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36361let Inst{7-5} = 0b000;
36362let Inst{13-13} = 0b0;
36363let Inst{31-19} = 0b0001100111111;
36364let hasNewValue = 1;
36365let opNewValue = 0;
36366let isCVI = 1;
36367let DecoderNamespace = "EXT_mmvec";
36368}
36369def V6_vrmpyznb_rt_acc : HInst<
36370(outs HvxVQR:$Vyyyy32),
36371(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36372"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rt8.b)",
36373tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36374let Inst{7-5} = 0b010;
36375let Inst{13-13} = 0b1;
36376let Inst{31-19} = 0b0001100111010;
36377let hasNewValue = 1;
36378let opNewValue = 0;
36379let isAccumulator = 1;
36380let isCVI = 1;
36381let DecoderNamespace = "EXT_mmvec";
36382let Constraints = "$Vyyyy32 = $Vyyyy32in";
36383}
36384def V6_vrmpyznb_rx : HInst<
36385(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36386(ins HvxVR:$Vu32, IntRegs:$Rx8in),
36387"$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)",
36388tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36389let Inst{7-5} = 0b000;
36390let Inst{13-13} = 0b0;
36391let Inst{31-19} = 0b0001100111110;
36392let hasNewValue = 1;
36393let opNewValue = 0;
36394let isCVI = 1;
36395let DecoderNamespace = "EXT_mmvec";
36396let Constraints = "$Rx8 = $Rx8in";
36397}
36398def V6_vrmpyznb_rx_acc : HInst<
36399(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36400(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
36401"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)",
36402tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36403let Inst{7-5} = 0b010;
36404let Inst{13-13} = 0b1;
36405let Inst{31-19} = 0b0001100111011;
36406let hasNewValue = 1;
36407let opNewValue = 0;
36408let isAccumulator = 1;
36409let isCVI = 1;
36410let DecoderNamespace = "EXT_mmvec";
36411let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36412}
36413def V6_vror : HInst<
36414(outs HvxVR:$Vd32),
36415(ins HvxVR:$Vu32, IntRegs:$Rt32),
36416"$Vd32 = vror($Vu32,$Rt32)",
36417tc_6e7fa133, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
36418let Inst{7-5} = 0b001;
36419let Inst{13-13} = 0b0;
36420let Inst{31-21} = 0b00011001011;
36421let hasNewValue = 1;
36422let opNewValue = 0;
36423let isCVI = 1;
36424let DecoderNamespace = "EXT_mmvec";
36425}
36426def V6_vrotr : HInst<
36427(outs HvxVR:$Vd32),
36428(ins HvxVR:$Vu32, HvxVR:$Vv32),
36429"$Vd32.uw = vrotr($Vu32.uw,$Vv32.uw)",
36430tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV66]> {
36431let Inst{7-5} = 0b111;
36432let Inst{13-13} = 0b1;
36433let Inst{31-21} = 0b00011010100;
36434let hasNewValue = 1;
36435let opNewValue = 0;
36436let isCVI = 1;
36437let DecoderNamespace = "EXT_mmvec";
36438}
36439def V6_vrotr_alt : HInst<
36440(outs HvxVR:$Vd32),
36441(ins HvxVR:$Vu32, HvxVR:$Vv32),
36442"$Vd32 = vrotr($Vu32,$Vv32)",
36443PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
36444let hasNewValue = 1;
36445let opNewValue = 0;
36446let isCVI = 1;
36447let isPseudo = 1;
36448let isCodeGenOnly = 1;
36449let DecoderNamespace = "EXT_mmvec";
36450}
36451def V6_vroundhb : HInst<
36452(outs HvxVR:$Vd32),
36453(ins HvxVR:$Vu32, HvxVR:$Vv32),
36454"$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
36455tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36456let Inst{7-5} = 0b110;
36457let Inst{13-13} = 0b0;
36458let Inst{31-21} = 0b00011111011;
36459let hasNewValue = 1;
36460let opNewValue = 0;
36461let isCVI = 1;
36462let DecoderNamespace = "EXT_mmvec";
36463}
36464def V6_vroundhb_alt : HInst<
36465(outs HvxVR:$Vd32),
36466(ins HvxVR:$Vu32, HvxVR:$Vv32),
36467"$Vd32 = vroundhb($Vu32,$Vv32):sat",
36468PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36469let hasNewValue = 1;
36470let opNewValue = 0;
36471let isCVI = 1;
36472let isPseudo = 1;
36473let isCodeGenOnly = 1;
36474let DecoderNamespace = "EXT_mmvec";
36475}
36476def V6_vroundhub : HInst<
36477(outs HvxVR:$Vd32),
36478(ins HvxVR:$Vu32, HvxVR:$Vv32),
36479"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
36480tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36481let Inst{7-5} = 0b111;
36482let Inst{13-13} = 0b0;
36483let Inst{31-21} = 0b00011111011;
36484let hasNewValue = 1;
36485let opNewValue = 0;
36486let isCVI = 1;
36487let DecoderNamespace = "EXT_mmvec";
36488}
36489def V6_vroundhub_alt : HInst<
36490(outs HvxVR:$Vd32),
36491(ins HvxVR:$Vu32, HvxVR:$Vv32),
36492"$Vd32 = vroundhub($Vu32,$Vv32):sat",
36493PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36494let hasNewValue = 1;
36495let opNewValue = 0;
36496let isCVI = 1;
36497let isPseudo = 1;
36498let isCodeGenOnly = 1;
36499let DecoderNamespace = "EXT_mmvec";
36500}
36501def V6_vrounduhub : HInst<
36502(outs HvxVR:$Vd32),
36503(ins HvxVR:$Vu32, HvxVR:$Vv32),
36504"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
36505tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
36506let Inst{7-5} = 0b011;
36507let Inst{13-13} = 0b0;
36508let Inst{31-21} = 0b00011111111;
36509let hasNewValue = 1;
36510let opNewValue = 0;
36511let isCVI = 1;
36512let DecoderNamespace = "EXT_mmvec";
36513}
36514def V6_vrounduhub_alt : HInst<
36515(outs HvxVR:$Vd32),
36516(ins HvxVR:$Vu32, HvxVR:$Vv32),
36517"$Vd32 = vrounduhub($Vu32,$Vv32):sat",
36518PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36519let hasNewValue = 1;
36520let opNewValue = 0;
36521let isCVI = 1;
36522let isPseudo = 1;
36523let isCodeGenOnly = 1;
36524let DecoderNamespace = "EXT_mmvec";
36525}
36526def V6_vrounduwuh : HInst<
36527(outs HvxVR:$Vd32),
36528(ins HvxVR:$Vu32, HvxVR:$Vv32),
36529"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
36530tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
36531let Inst{7-5} = 0b100;
36532let Inst{13-13} = 0b0;
36533let Inst{31-21} = 0b00011111111;
36534let hasNewValue = 1;
36535let opNewValue = 0;
36536let isCVI = 1;
36537let DecoderNamespace = "EXT_mmvec";
36538}
36539def V6_vrounduwuh_alt : HInst<
36540(outs HvxVR:$Vd32),
36541(ins HvxVR:$Vu32, HvxVR:$Vv32),
36542"$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
36543PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36544let hasNewValue = 1;
36545let opNewValue = 0;
36546let isCVI = 1;
36547let isPseudo = 1;
36548let isCodeGenOnly = 1;
36549let DecoderNamespace = "EXT_mmvec";
36550}
36551def V6_vroundwh : HInst<
36552(outs HvxVR:$Vd32),
36553(ins HvxVR:$Vu32, HvxVR:$Vv32),
36554"$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
36555tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36556let Inst{7-5} = 0b100;
36557let Inst{13-13} = 0b0;
36558let Inst{31-21} = 0b00011111011;
36559let hasNewValue = 1;
36560let opNewValue = 0;
36561let isCVI = 1;
36562let DecoderNamespace = "EXT_mmvec";
36563}
36564def V6_vroundwh_alt : HInst<
36565(outs HvxVR:$Vd32),
36566(ins HvxVR:$Vu32, HvxVR:$Vv32),
36567"$Vd32 = vroundwh($Vu32,$Vv32):sat",
36568PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36569let hasNewValue = 1;
36570let opNewValue = 0;
36571let isCVI = 1;
36572let isPseudo = 1;
36573let isCodeGenOnly = 1;
36574let DecoderNamespace = "EXT_mmvec";
36575}
36576def V6_vroundwuh : HInst<
36577(outs HvxVR:$Vd32),
36578(ins HvxVR:$Vu32, HvxVR:$Vv32),
36579"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
36580tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36581let Inst{7-5} = 0b101;
36582let Inst{13-13} = 0b0;
36583let Inst{31-21} = 0b00011111011;
36584let hasNewValue = 1;
36585let opNewValue = 0;
36586let isCVI = 1;
36587let DecoderNamespace = "EXT_mmvec";
36588}
36589def V6_vroundwuh_alt : HInst<
36590(outs HvxVR:$Vd32),
36591(ins HvxVR:$Vu32, HvxVR:$Vv32),
36592"$Vd32 = vroundwuh($Vu32,$Vv32):sat",
36593PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36594let hasNewValue = 1;
36595let opNewValue = 0;
36596let isCVI = 1;
36597let isPseudo = 1;
36598let isCodeGenOnly = 1;
36599let DecoderNamespace = "EXT_mmvec";
36600}
36601def V6_vrsadubi : HInst<
36602(outs HvxWR:$Vdd32),
36603(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36604"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
36605tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
36606let Inst{7-6} = 0b11;
36607let Inst{13-13} = 0b0;
36608let Inst{31-21} = 0b00011001010;
36609let hasNewValue = 1;
36610let opNewValue = 0;
36611let isCVI = 1;
36612let DecoderNamespace = "EXT_mmvec";
36613}
36614def V6_vrsadubi_acc : HInst<
36615(outs HvxWR:$Vxx32),
36616(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36617"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
36618tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
36619let Inst{7-6} = 0b11;
36620let Inst{13-13} = 0b1;
36621let Inst{31-21} = 0b00011001010;
36622let hasNewValue = 1;
36623let opNewValue = 0;
36624let isAccumulator = 1;
36625let isCVI = 1;
36626let DecoderNamespace = "EXT_mmvec";
36627let Constraints = "$Vxx32 = $Vxx32in";
36628}
36629def V6_vrsadubi_acc_alt : HInst<
36630(outs HvxWR:$Vxx32),
36631(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36632"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
36633PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36634let hasNewValue = 1;
36635let opNewValue = 0;
36636let isAccumulator = 1;
36637let isCVI = 1;
36638let isPseudo = 1;
36639let isCodeGenOnly = 1;
36640let DecoderNamespace = "EXT_mmvec";
36641let Constraints = "$Vxx32 = $Vxx32in";
36642}
36643def V6_vrsadubi_alt : HInst<
36644(outs HvxWR:$Vdd32),
36645(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36646"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
36647PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36648let hasNewValue = 1;
36649let opNewValue = 0;
36650let isCVI = 1;
36651let isPseudo = 1;
36652let isCodeGenOnly = 1;
36653let DecoderNamespace = "EXT_mmvec";
36654}
36655def V6_vsatdw : HInst<
36656(outs HvxVR:$Vd32),
36657(ins HvxVR:$Vu32, HvxVR:$Vv32),
36658"$Vd32.w = vsatdw($Vu32.w,$Vv32.w)",
36659tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV66]> {
36660let Inst{7-5} = 0b111;
36661let Inst{13-13} = 0b1;
36662let Inst{31-21} = 0b00011101100;
36663let hasNewValue = 1;
36664let opNewValue = 0;
36665let isCVI = 1;
36666let DecoderNamespace = "EXT_mmvec";
36667}
36668def V6_vsathub : HInst<
36669(outs HvxVR:$Vd32),
36670(ins HvxVR:$Vu32, HvxVR:$Vv32),
36671"$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
36672tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36673let Inst{7-5} = 0b010;
36674let Inst{13-13} = 0b0;
36675let Inst{31-21} = 0b00011111011;
36676let hasNewValue = 1;
36677let opNewValue = 0;
36678let isCVI = 1;
36679let DecoderNamespace = "EXT_mmvec";
36680}
36681def V6_vsathub_alt : HInst<
36682(outs HvxVR:$Vd32),
36683(ins HvxVR:$Vu32, HvxVR:$Vv32),
36684"$Vd32 = vsathub($Vu32,$Vv32)",
36685PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36686let hasNewValue = 1;
36687let opNewValue = 0;
36688let isCVI = 1;
36689let isPseudo = 1;
36690let isCodeGenOnly = 1;
36691let DecoderNamespace = "EXT_mmvec";
36692}
36693def V6_vsatuwuh : HInst<
36694(outs HvxVR:$Vd32),
36695(ins HvxVR:$Vu32, HvxVR:$Vv32),
36696"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
36697tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
36698let Inst{7-5} = 0b110;
36699let Inst{13-13} = 0b0;
36700let Inst{31-21} = 0b00011111001;
36701let hasNewValue = 1;
36702let opNewValue = 0;
36703let isCVI = 1;
36704let DecoderNamespace = "EXT_mmvec";
36705}
36706def V6_vsatuwuh_alt : HInst<
36707(outs HvxVR:$Vd32),
36708(ins HvxVR:$Vu32, HvxVR:$Vv32),
36709"$Vd32 = vsatuwuh($Vu32,$Vv32)",
36710PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36711let hasNewValue = 1;
36712let opNewValue = 0;
36713let isCVI = 1;
36714let isPseudo = 1;
36715let isCodeGenOnly = 1;
36716let DecoderNamespace = "EXT_mmvec";
36717}
36718def V6_vsatwh : HInst<
36719(outs HvxVR:$Vd32),
36720(ins HvxVR:$Vu32, HvxVR:$Vv32),
36721"$Vd32.h = vsat($Vu32.w,$Vv32.w)",
36722tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36723let Inst{7-5} = 0b011;
36724let Inst{13-13} = 0b0;
36725let Inst{31-21} = 0b00011111011;
36726let hasNewValue = 1;
36727let opNewValue = 0;
36728let isCVI = 1;
36729let DecoderNamespace = "EXT_mmvec";
36730}
36731def V6_vsatwh_alt : HInst<
36732(outs HvxVR:$Vd32),
36733(ins HvxVR:$Vu32, HvxVR:$Vv32),
36734"$Vd32 = vsatwh($Vu32,$Vv32)",
36735PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36736let hasNewValue = 1;
36737let opNewValue = 0;
36738let isCVI = 1;
36739let isPseudo = 1;
36740let isCodeGenOnly = 1;
36741let DecoderNamespace = "EXT_mmvec";
36742}
36743def V6_vsb : HInst<
36744(outs HvxWR:$Vdd32),
36745(ins HvxVR:$Vu32),
36746"$Vdd32.h = vsxt($Vu32.b)",
36747tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
36748let Inst{7-5} = 0b011;
36749let Inst{13-13} = 0b0;
36750let Inst{31-16} = 0b0001111000000010;
36751let hasNewValue = 1;
36752let opNewValue = 0;
36753let isCVI = 1;
36754let DecoderNamespace = "EXT_mmvec";
36755}
36756def V6_vsb_alt : HInst<
36757(outs HvxWR:$Vdd32),
36758(ins HvxVR:$Vu32),
36759"$Vdd32 = vsxtb($Vu32)",
36760PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36761let hasNewValue = 1;
36762let opNewValue = 0;
36763let isCVI = 1;
36764let isPseudo = 1;
36765let isCodeGenOnly = 1;
36766let DecoderNamespace = "EXT_mmvec";
36767}
36768def V6_vscattermh : HInst<
36769(outs),
36770(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36771"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
36772tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
36773let Inst{7-5} = 0b001;
36774let Inst{31-21} = 0b00101111001;
36775let accessSize = HalfWordAccess;
36776let isCVI = 1;
36777let mayStore = 1;
36778let DecoderNamespace = "EXT_mmvec";
36779}
36780def V6_vscattermh_add : HInst<
36781(outs),
36782(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36783"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
36784tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
36785let Inst{7-5} = 0b101;
36786let Inst{31-21} = 0b00101111001;
36787let accessSize = HalfWordAccess;
36788let isAccumulator = 1;
36789let isCVI = 1;
36790let mayStore = 1;
36791let DecoderNamespace = "EXT_mmvec";
36792}
36793def V6_vscattermh_add_alt : HInst<
36794(outs),
36795(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36796"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
36797PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36798let isAccumulator = 1;
36799let isCVI = 1;
36800let isPseudo = 1;
36801let isCodeGenOnly = 1;
36802let DecoderNamespace = "EXT_mmvec";
36803}
36804def V6_vscattermh_alt : HInst<
36805(outs),
36806(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36807"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
36808PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36809let isCVI = 1;
36810let isPseudo = 1;
36811let isCodeGenOnly = 1;
36812let DecoderNamespace = "EXT_mmvec";
36813}
36814def V6_vscattermhq : HInst<
36815(outs),
36816(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36817"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
36818tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
36819let Inst{7-7} = 0b1;
36820let Inst{31-21} = 0b00101111100;
36821let accessSize = HalfWordAccess;
36822let isCVI = 1;
36823let mayStore = 1;
36824let DecoderNamespace = "EXT_mmvec";
36825}
36826def V6_vscattermhq_alt : HInst<
36827(outs),
36828(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36829"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
36830PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36831let isCVI = 1;
36832let isPseudo = 1;
36833let isCodeGenOnly = 1;
36834let DecoderNamespace = "EXT_mmvec";
36835}
36836def V6_vscattermhw : HInst<
36837(outs),
36838(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
36839"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
36840tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
36841let Inst{7-5} = 0b010;
36842let Inst{31-21} = 0b00101111001;
36843let accessSize = HalfWordAccess;
36844let isCVI = 1;
36845let mayStore = 1;
36846let DecoderNamespace = "EXT_mmvec";
36847}
36848def V6_vscattermhw_add : HInst<
36849(outs),
36850(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
36851"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
36852tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
36853let Inst{7-5} = 0b110;
36854let Inst{31-21} = 0b00101111001;
36855let accessSize = HalfWordAccess;
36856let isAccumulator = 1;
36857let isCVI = 1;
36858let mayStore = 1;
36859let DecoderNamespace = "EXT_mmvec";
36860}
36861def V6_vscattermhwq : HInst<
36862(outs),
36863(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
36864"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
36865tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
36866let Inst{7-7} = 0b0;
36867let Inst{31-21} = 0b00101111101;
36868let accessSize = HalfWordAccess;
36869let isCVI = 1;
36870let mayStore = 1;
36871let DecoderNamespace = "EXT_mmvec";
36872}
36873def V6_vscattermw : HInst<
36874(outs),
36875(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36876"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
36877tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
36878let Inst{7-5} = 0b000;
36879let Inst{31-21} = 0b00101111001;
36880let accessSize = WordAccess;
36881let isCVI = 1;
36882let mayStore = 1;
36883let DecoderNamespace = "EXT_mmvec";
36884}
36885def V6_vscattermw_add : HInst<
36886(outs),
36887(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36888"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
36889tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
36890let Inst{7-5} = 0b100;
36891let Inst{31-21} = 0b00101111001;
36892let accessSize = WordAccess;
36893let isAccumulator = 1;
36894let isCVI = 1;
36895let mayStore = 1;
36896let DecoderNamespace = "EXT_mmvec";
36897}
36898def V6_vscattermw_add_alt : HInst<
36899(outs),
36900(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36901"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
36902PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36903let isAccumulator = 1;
36904let isCVI = 1;
36905let isPseudo = 1;
36906let isCodeGenOnly = 1;
36907let DecoderNamespace = "EXT_mmvec";
36908}
36909def V6_vscattermw_alt : HInst<
36910(outs),
36911(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36912"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
36913PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36914let isCVI = 1;
36915let isPseudo = 1;
36916let isCodeGenOnly = 1;
36917let DecoderNamespace = "EXT_mmvec";
36918}
36919def V6_vscattermwh_add_alt : HInst<
36920(outs),
36921(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
36922"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
36923PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36924let isAccumulator = 1;
36925let isCVI = 1;
36926let isPseudo = 1;
36927let isCodeGenOnly = 1;
36928let DecoderNamespace = "EXT_mmvec";
36929}
36930def V6_vscattermwh_alt : HInst<
36931(outs),
36932(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
36933"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
36934PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36935let isCVI = 1;
36936let isPseudo = 1;
36937let isCodeGenOnly = 1;
36938let DecoderNamespace = "EXT_mmvec";
36939}
36940def V6_vscattermwhq_alt : HInst<
36941(outs),
36942(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
36943"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
36944PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36945let isCVI = 1;
36946let isPseudo = 1;
36947let isCodeGenOnly = 1;
36948let DecoderNamespace = "EXT_mmvec";
36949}
36950def V6_vscattermwq : HInst<
36951(outs),
36952(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36953"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
36954tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
36955let Inst{7-7} = 0b0;
36956let Inst{31-21} = 0b00101111100;
36957let accessSize = WordAccess;
36958let isCVI = 1;
36959let mayStore = 1;
36960let DecoderNamespace = "EXT_mmvec";
36961}
36962def V6_vscattermwq_alt : HInst<
36963(outs),
36964(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36965"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
36966PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36967let isCVI = 1;
36968let isPseudo = 1;
36969let isCodeGenOnly = 1;
36970let DecoderNamespace = "EXT_mmvec";
36971}
36972def V6_vsh : HInst<
36973(outs HvxWR:$Vdd32),
36974(ins HvxVR:$Vu32),
36975"$Vdd32.w = vsxt($Vu32.h)",
36976tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
36977let Inst{7-5} = 0b100;
36978let Inst{13-13} = 0b0;
36979let Inst{31-16} = 0b0001111000000010;
36980let hasNewValue = 1;
36981let opNewValue = 0;
36982let isCVI = 1;
36983let DecoderNamespace = "EXT_mmvec";
36984}
36985def V6_vsh_alt : HInst<
36986(outs HvxWR:$Vdd32),
36987(ins HvxVR:$Vu32),
36988"$Vdd32 = vsxth($Vu32)",
36989PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36990let hasNewValue = 1;
36991let opNewValue = 0;
36992let isCVI = 1;
36993let isPseudo = 1;
36994let isCodeGenOnly = 1;
36995let DecoderNamespace = "EXT_mmvec";
36996}
36997def V6_vshufeh : HInst<
36998(outs HvxVR:$Vd32),
36999(ins HvxVR:$Vu32, HvxVR:$Vv32),
37000"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
37001tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37002let Inst{7-5} = 0b011;
37003let Inst{13-13} = 0b0;
37004let Inst{31-21} = 0b00011111010;
37005let hasNewValue = 1;
37006let opNewValue = 0;
37007let isCVI = 1;
37008let DecoderNamespace = "EXT_mmvec";
37009}
37010def V6_vshufeh_alt : HInst<
37011(outs HvxVR:$Vd32),
37012(ins HvxVR:$Vu32, HvxVR:$Vv32),
37013"$Vd32 = vshuffeh($Vu32,$Vv32)",
37014PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37015let hasNewValue = 1;
37016let opNewValue = 0;
37017let isCVI = 1;
37018let isPseudo = 1;
37019let isCodeGenOnly = 1;
37020let DecoderNamespace = "EXT_mmvec";
37021}
37022def V6_vshuff : HInst<
37023(outs HvxVR:$Vy32, HvxVR:$Vx32),
37024(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
37025"vshuff($Vy32,$Vx32,$Rt32)",
37026tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
37027let Inst{7-5} = 0b001;
37028let Inst{13-13} = 0b1;
37029let Inst{31-21} = 0b00011001111;
37030let hasNewValue = 1;
37031let opNewValue = 0;
37032let hasNewValue2 = 1;
37033let opNewValue2 = 1;
37034let isCVI = 1;
37035let DecoderNamespace = "EXT_mmvec";
37036let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
37037}
37038def V6_vshuffb : HInst<
37039(outs HvxVR:$Vd32),
37040(ins HvxVR:$Vu32),
37041"$Vd32.b = vshuff($Vu32.b)",
37042tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
37043let Inst{7-5} = 0b000;
37044let Inst{13-13} = 0b0;
37045let Inst{31-16} = 0b0001111000000010;
37046let hasNewValue = 1;
37047let opNewValue = 0;
37048let isCVI = 1;
37049let DecoderNamespace = "EXT_mmvec";
37050}
37051def V6_vshuffb_alt : HInst<
37052(outs HvxVR:$Vd32),
37053(ins HvxVR:$Vu32),
37054"$Vd32 = vshuffb($Vu32)",
37055PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37056let hasNewValue = 1;
37057let opNewValue = 0;
37058let isCVI = 1;
37059let isPseudo = 1;
37060let isCodeGenOnly = 1;
37061let DecoderNamespace = "EXT_mmvec";
37062}
37063def V6_vshuffeb : HInst<
37064(outs HvxVR:$Vd32),
37065(ins HvxVR:$Vu32, HvxVR:$Vv32),
37066"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
37067tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37068let Inst{7-5} = 0b001;
37069let Inst{13-13} = 0b0;
37070let Inst{31-21} = 0b00011111010;
37071let hasNewValue = 1;
37072let opNewValue = 0;
37073let isCVI = 1;
37074let DecoderNamespace = "EXT_mmvec";
37075}
37076def V6_vshuffeb_alt : HInst<
37077(outs HvxVR:$Vd32),
37078(ins HvxVR:$Vu32, HvxVR:$Vv32),
37079"$Vd32 = vshuffeb($Vu32,$Vv32)",
37080PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37081let hasNewValue = 1;
37082let opNewValue = 0;
37083let isCVI = 1;
37084let isPseudo = 1;
37085let isCodeGenOnly = 1;
37086let DecoderNamespace = "EXT_mmvec";
37087}
37088def V6_vshuffh : HInst<
37089(outs HvxVR:$Vd32),
37090(ins HvxVR:$Vu32),
37091"$Vd32.h = vshuff($Vu32.h)",
37092tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
37093let Inst{7-5} = 0b111;
37094let Inst{13-13} = 0b0;
37095let Inst{31-16} = 0b0001111000000001;
37096let hasNewValue = 1;
37097let opNewValue = 0;
37098let isCVI = 1;
37099let DecoderNamespace = "EXT_mmvec";
37100}
37101def V6_vshuffh_alt : HInst<
37102(outs HvxVR:$Vd32),
37103(ins HvxVR:$Vu32),
37104"$Vd32 = vshuffh($Vu32)",
37105PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37106let hasNewValue = 1;
37107let opNewValue = 0;
37108let isCVI = 1;
37109let isPseudo = 1;
37110let isCodeGenOnly = 1;
37111let DecoderNamespace = "EXT_mmvec";
37112}
37113def V6_vshuffob : HInst<
37114(outs HvxVR:$Vd32),
37115(ins HvxVR:$Vu32, HvxVR:$Vv32),
37116"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
37117tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37118let Inst{7-5} = 0b010;
37119let Inst{13-13} = 0b0;
37120let Inst{31-21} = 0b00011111010;
37121let hasNewValue = 1;
37122let opNewValue = 0;
37123let isCVI = 1;
37124let DecoderNamespace = "EXT_mmvec";
37125}
37126def V6_vshuffob_alt : HInst<
37127(outs HvxVR:$Vd32),
37128(ins HvxVR:$Vu32, HvxVR:$Vv32),
37129"$Vd32 = vshuffob($Vu32,$Vv32)",
37130PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37131let hasNewValue = 1;
37132let opNewValue = 0;
37133let isCVI = 1;
37134let isPseudo = 1;
37135let isCodeGenOnly = 1;
37136let DecoderNamespace = "EXT_mmvec";
37137}
37138def V6_vshuffvdd : HInst<
37139(outs HvxWR:$Vdd32),
37140(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
37141"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
37142tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
37143let Inst{7-5} = 0b011;
37144let Inst{13-13} = 0b1;
37145let Inst{31-24} = 0b00011011;
37146let hasNewValue = 1;
37147let opNewValue = 0;
37148let isCVI = 1;
37149let DecoderNamespace = "EXT_mmvec";
37150}
37151def V6_vshufoeb : HInst<
37152(outs HvxWR:$Vdd32),
37153(ins HvxVR:$Vu32, HvxVR:$Vv32),
37154"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
37155tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37156let Inst{7-5} = 0b110;
37157let Inst{13-13} = 0b0;
37158let Inst{31-21} = 0b00011111010;
37159let hasNewValue = 1;
37160let opNewValue = 0;
37161let isCVI = 1;
37162let DecoderNamespace = "EXT_mmvec";
37163}
37164def V6_vshufoeb_alt : HInst<
37165(outs HvxWR:$Vdd32),
37166(ins HvxVR:$Vu32, HvxVR:$Vv32),
37167"$Vdd32 = vshuffoeb($Vu32,$Vv32)",
37168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37169let hasNewValue = 1;
37170let opNewValue = 0;
37171let isCVI = 1;
37172let isPseudo = 1;
37173let isCodeGenOnly = 1;
37174let DecoderNamespace = "EXT_mmvec";
37175}
37176def V6_vshufoeh : HInst<
37177(outs HvxWR:$Vdd32),
37178(ins HvxVR:$Vu32, HvxVR:$Vv32),
37179"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
37180tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37181let Inst{7-5} = 0b101;
37182let Inst{13-13} = 0b0;
37183let Inst{31-21} = 0b00011111010;
37184let hasNewValue = 1;
37185let opNewValue = 0;
37186let isCVI = 1;
37187let DecoderNamespace = "EXT_mmvec";
37188}
37189def V6_vshufoeh_alt : HInst<
37190(outs HvxWR:$Vdd32),
37191(ins HvxVR:$Vu32, HvxVR:$Vv32),
37192"$Vdd32 = vshuffoeh($Vu32,$Vv32)",
37193PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37194let hasNewValue = 1;
37195let opNewValue = 0;
37196let isCVI = 1;
37197let isPseudo = 1;
37198let isCodeGenOnly = 1;
37199let DecoderNamespace = "EXT_mmvec";
37200}
37201def V6_vshufoh : HInst<
37202(outs HvxVR:$Vd32),
37203(ins HvxVR:$Vu32, HvxVR:$Vv32),
37204"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
37205tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37206let Inst{7-5} = 0b100;
37207let Inst{13-13} = 0b0;
37208let Inst{31-21} = 0b00011111010;
37209let hasNewValue = 1;
37210let opNewValue = 0;
37211let isCVI = 1;
37212let DecoderNamespace = "EXT_mmvec";
37213}
37214def V6_vshufoh_alt : HInst<
37215(outs HvxVR:$Vd32),
37216(ins HvxVR:$Vu32, HvxVR:$Vv32),
37217"$Vd32 = vshuffoh($Vu32,$Vv32)",
37218PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37219let hasNewValue = 1;
37220let opNewValue = 0;
37221let isCVI = 1;
37222let isPseudo = 1;
37223let isCodeGenOnly = 1;
37224let DecoderNamespace = "EXT_mmvec";
37225}
37226def V6_vsubb : HInst<
37227(outs HvxVR:$Vd32),
37228(ins HvxVR:$Vu32, HvxVR:$Vv32),
37229"$Vd32.b = vsub($Vu32.b,$Vv32.b)",
37230tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37231let Inst{7-5} = 0b101;
37232let Inst{13-13} = 0b0;
37233let Inst{31-21} = 0b00011100010;
37234let hasNewValue = 1;
37235let opNewValue = 0;
37236let isCVI = 1;
37237let DecoderNamespace = "EXT_mmvec";
37238}
37239def V6_vsubb_alt : HInst<
37240(outs HvxVR:$Vd32),
37241(ins HvxVR:$Vu32, HvxVR:$Vv32),
37242"$Vd32 = vsubb($Vu32,$Vv32)",
37243PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37244let hasNewValue = 1;
37245let opNewValue = 0;
37246let isCVI = 1;
37247let isPseudo = 1;
37248let isCodeGenOnly = 1;
37249let DecoderNamespace = "EXT_mmvec";
37250}
37251def V6_vsubb_dv : HInst<
37252(outs HvxWR:$Vdd32),
37253(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37254"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
37255tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37256let Inst{7-5} = 0b011;
37257let Inst{13-13} = 0b0;
37258let Inst{31-21} = 0b00011100100;
37259let hasNewValue = 1;
37260let opNewValue = 0;
37261let isCVI = 1;
37262let DecoderNamespace = "EXT_mmvec";
37263}
37264def V6_vsubb_dv_alt : HInst<
37265(outs HvxWR:$Vdd32),
37266(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37267"$Vdd32 = vsubb($Vuu32,$Vvv32)",
37268PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37269let hasNewValue = 1;
37270let opNewValue = 0;
37271let isCVI = 1;
37272let isPseudo = 1;
37273let isCodeGenOnly = 1;
37274let DecoderNamespace = "EXT_mmvec";
37275}
37276def V6_vsubbnq : HInst<
37277(outs HvxVR:$Vx32),
37278(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37279"if (!$Qv4) $Vx32.b -= $Vu32.b",
37280tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37281let Inst{7-5} = 0b001;
37282let Inst{13-13} = 0b1;
37283let Inst{21-16} = 0b000010;
37284let Inst{31-24} = 0b00011110;
37285let hasNewValue = 1;
37286let opNewValue = 0;
37287let isCVI = 1;
37288let DecoderNamespace = "EXT_mmvec";
37289let Constraints = "$Vx32 = $Vx32in";
37290}
37291def V6_vsubbnq_alt : HInst<
37292(outs HvxVR:$Vx32),
37293(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37294"if (!$Qv4.b) $Vx32.b -= $Vu32.b",
37295PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37296let hasNewValue = 1;
37297let opNewValue = 0;
37298let isCVI = 1;
37299let isPseudo = 1;
37300let isCodeGenOnly = 1;
37301let DecoderNamespace = "EXT_mmvec";
37302let Constraints = "$Vx32 = $Vx32in";
37303}
37304def V6_vsubbq : HInst<
37305(outs HvxVR:$Vx32),
37306(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37307"if ($Qv4) $Vx32.b -= $Vu32.b",
37308tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37309let Inst{7-5} = 0b110;
37310let Inst{13-13} = 0b1;
37311let Inst{21-16} = 0b000001;
37312let Inst{31-24} = 0b00011110;
37313let hasNewValue = 1;
37314let opNewValue = 0;
37315let isCVI = 1;
37316let DecoderNamespace = "EXT_mmvec";
37317let Constraints = "$Vx32 = $Vx32in";
37318}
37319def V6_vsubbq_alt : HInst<
37320(outs HvxVR:$Vx32),
37321(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37322"if ($Qv4.b) $Vx32.b -= $Vu32.b",
37323PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37324let hasNewValue = 1;
37325let opNewValue = 0;
37326let isCVI = 1;
37327let isPseudo = 1;
37328let isCodeGenOnly = 1;
37329let DecoderNamespace = "EXT_mmvec";
37330let Constraints = "$Vx32 = $Vx32in";
37331}
37332def V6_vsubbsat : HInst<
37333(outs HvxVR:$Vd32),
37334(ins HvxVR:$Vu32, HvxVR:$Vv32),
37335"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
37336tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
37337let Inst{7-5} = 0b010;
37338let Inst{13-13} = 0b0;
37339let Inst{31-21} = 0b00011111001;
37340let hasNewValue = 1;
37341let opNewValue = 0;
37342let isCVI = 1;
37343let DecoderNamespace = "EXT_mmvec";
37344}
37345def V6_vsubbsat_alt : HInst<
37346(outs HvxVR:$Vd32),
37347(ins HvxVR:$Vu32, HvxVR:$Vv32),
37348"$Vd32 = vsubb($Vu32,$Vv32):sat",
37349PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37350let hasNewValue = 1;
37351let opNewValue = 0;
37352let isCVI = 1;
37353let isPseudo = 1;
37354let isCodeGenOnly = 1;
37355let DecoderNamespace = "EXT_mmvec";
37356}
37357def V6_vsubbsat_dv : HInst<
37358(outs HvxWR:$Vdd32),
37359(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37360"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
37361tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
37362let Inst{7-5} = 0b001;
37363let Inst{13-13} = 0b0;
37364let Inst{31-21} = 0b00011110101;
37365let hasNewValue = 1;
37366let opNewValue = 0;
37367let isCVI = 1;
37368let DecoderNamespace = "EXT_mmvec";
37369}
37370def V6_vsubbsat_dv_alt : HInst<
37371(outs HvxWR:$Vdd32),
37372(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37373"$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
37374PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37375let hasNewValue = 1;
37376let opNewValue = 0;
37377let isCVI = 1;
37378let isPseudo = 1;
37379let isCodeGenOnly = 1;
37380let DecoderNamespace = "EXT_mmvec";
37381}
37382def V6_vsubcarry : HInst<
37383(outs HvxVR:$Vd32, HvxQR:$Qx4),
37384(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
37385"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
37386tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
37387let Inst{7-7} = 0b1;
37388let Inst{13-13} = 0b1;
37389let Inst{31-21} = 0b00011100101;
37390let hasNewValue = 1;
37391let opNewValue = 0;
37392let isCVI = 1;
37393let DecoderNamespace = "EXT_mmvec";
37394let Constraints = "$Qx4 = $Qx4in";
37395}
37396def V6_vsubcarryo : HInst<
37397(outs HvxVR:$Vd32, HvxQR:$Qe4),
37398(ins HvxVR:$Vu32, HvxVR:$Vv32),
37399"$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry",
37400tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
37401let Inst{7-7} = 0b1;
37402let Inst{13-13} = 0b1;
37403let Inst{31-21} = 0b00011101101;
37404let hasNewValue = 1;
37405let opNewValue = 0;
37406let hasNewValue2 = 1;
37407let opNewValue2 = 1;
37408let isCVI = 1;
37409let DecoderNamespace = "EXT_mmvec";
37410}
37411def V6_vsubh : HInst<
37412(outs HvxVR:$Vd32),
37413(ins HvxVR:$Vu32, HvxVR:$Vv32),
37414"$Vd32.h = vsub($Vu32.h,$Vv32.h)",
37415tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37416let Inst{7-5} = 0b110;
37417let Inst{13-13} = 0b0;
37418let Inst{31-21} = 0b00011100010;
37419let hasNewValue = 1;
37420let opNewValue = 0;
37421let isCVI = 1;
37422let DecoderNamespace = "EXT_mmvec";
37423}
37424def V6_vsubh_alt : HInst<
37425(outs HvxVR:$Vd32),
37426(ins HvxVR:$Vu32, HvxVR:$Vv32),
37427"$Vd32 = vsubh($Vu32,$Vv32)",
37428PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37429let hasNewValue = 1;
37430let opNewValue = 0;
37431let isCVI = 1;
37432let isPseudo = 1;
37433let isCodeGenOnly = 1;
37434let DecoderNamespace = "EXT_mmvec";
37435}
37436def V6_vsubh_dv : HInst<
37437(outs HvxWR:$Vdd32),
37438(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37439"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
37440tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37441let Inst{7-5} = 0b100;
37442let Inst{13-13} = 0b0;
37443let Inst{31-21} = 0b00011100100;
37444let hasNewValue = 1;
37445let opNewValue = 0;
37446let isCVI = 1;
37447let DecoderNamespace = "EXT_mmvec";
37448}
37449def V6_vsubh_dv_alt : HInst<
37450(outs HvxWR:$Vdd32),
37451(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37452"$Vdd32 = vsubh($Vuu32,$Vvv32)",
37453PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37454let hasNewValue = 1;
37455let opNewValue = 0;
37456let isCVI = 1;
37457let isPseudo = 1;
37458let isCodeGenOnly = 1;
37459let DecoderNamespace = "EXT_mmvec";
37460}
37461def V6_vsubhnq : HInst<
37462(outs HvxVR:$Vx32),
37463(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37464"if (!$Qv4) $Vx32.h -= $Vu32.h",
37465tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37466let Inst{7-5} = 0b010;
37467let Inst{13-13} = 0b1;
37468let Inst{21-16} = 0b000010;
37469let Inst{31-24} = 0b00011110;
37470let hasNewValue = 1;
37471let opNewValue = 0;
37472let isCVI = 1;
37473let DecoderNamespace = "EXT_mmvec";
37474let Constraints = "$Vx32 = $Vx32in";
37475}
37476def V6_vsubhnq_alt : HInst<
37477(outs HvxVR:$Vx32),
37478(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37479"if (!$Qv4.h) $Vx32.h -= $Vu32.h",
37480PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37481let hasNewValue = 1;
37482let opNewValue = 0;
37483let isCVI = 1;
37484let isPseudo = 1;
37485let isCodeGenOnly = 1;
37486let DecoderNamespace = "EXT_mmvec";
37487let Constraints = "$Vx32 = $Vx32in";
37488}
37489def V6_vsubhq : HInst<
37490(outs HvxVR:$Vx32),
37491(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37492"if ($Qv4) $Vx32.h -= $Vu32.h",
37493tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37494let Inst{7-5} = 0b111;
37495let Inst{13-13} = 0b1;
37496let Inst{21-16} = 0b000001;
37497let Inst{31-24} = 0b00011110;
37498let hasNewValue = 1;
37499let opNewValue = 0;
37500let isCVI = 1;
37501let DecoderNamespace = "EXT_mmvec";
37502let Constraints = "$Vx32 = $Vx32in";
37503}
37504def V6_vsubhq_alt : HInst<
37505(outs HvxVR:$Vx32),
37506(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37507"if ($Qv4.h) $Vx32.h -= $Vu32.h",
37508PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37509let hasNewValue = 1;
37510let opNewValue = 0;
37511let isCVI = 1;
37512let isPseudo = 1;
37513let isCodeGenOnly = 1;
37514let DecoderNamespace = "EXT_mmvec";
37515let Constraints = "$Vx32 = $Vx32in";
37516}
37517def V6_vsubhsat : HInst<
37518(outs HvxVR:$Vd32),
37519(ins HvxVR:$Vu32, HvxVR:$Vv32),
37520"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
37521tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37522let Inst{7-5} = 0b010;
37523let Inst{13-13} = 0b0;
37524let Inst{31-21} = 0b00011100011;
37525let hasNewValue = 1;
37526let opNewValue = 0;
37527let isCVI = 1;
37528let DecoderNamespace = "EXT_mmvec";
37529}
37530def V6_vsubhsat_alt : HInst<
37531(outs HvxVR:$Vd32),
37532(ins HvxVR:$Vu32, HvxVR:$Vv32),
37533"$Vd32 = vsubh($Vu32,$Vv32):sat",
37534PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37535let hasNewValue = 1;
37536let opNewValue = 0;
37537let isCVI = 1;
37538let isPseudo = 1;
37539let isCodeGenOnly = 1;
37540let DecoderNamespace = "EXT_mmvec";
37541}
37542def V6_vsubhsat_dv : HInst<
37543(outs HvxWR:$Vdd32),
37544(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37545"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
37546tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37547let Inst{7-5} = 0b000;
37548let Inst{13-13} = 0b0;
37549let Inst{31-21} = 0b00011100101;
37550let hasNewValue = 1;
37551let opNewValue = 0;
37552let isCVI = 1;
37553let DecoderNamespace = "EXT_mmvec";
37554}
37555def V6_vsubhsat_dv_alt : HInst<
37556(outs HvxWR:$Vdd32),
37557(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37558"$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
37559PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37560let hasNewValue = 1;
37561let opNewValue = 0;
37562let isCVI = 1;
37563let isPseudo = 1;
37564let isCodeGenOnly = 1;
37565let DecoderNamespace = "EXT_mmvec";
37566}
37567def V6_vsubhw : HInst<
37568(outs HvxWR:$Vdd32),
37569(ins HvxVR:$Vu32, HvxVR:$Vv32),
37570"$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
37571tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37572let Inst{7-5} = 0b111;
37573let Inst{13-13} = 0b0;
37574let Inst{31-21} = 0b00011100101;
37575let hasNewValue = 1;
37576let opNewValue = 0;
37577let isCVI = 1;
37578let DecoderNamespace = "EXT_mmvec";
37579}
37580def V6_vsubhw_alt : HInst<
37581(outs HvxWR:$Vdd32),
37582(ins HvxVR:$Vu32, HvxVR:$Vv32),
37583"$Vdd32 = vsubh($Vu32,$Vv32)",
37584PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37585let hasNewValue = 1;
37586let opNewValue = 0;
37587let isCVI = 1;
37588let isPseudo = 1;
37589let isCodeGenOnly = 1;
37590let DecoderNamespace = "EXT_mmvec";
37591}
37592def V6_vsububh : HInst<
37593(outs HvxWR:$Vdd32),
37594(ins HvxVR:$Vu32, HvxVR:$Vv32),
37595"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
37596tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37597let Inst{7-5} = 0b101;
37598let Inst{13-13} = 0b0;
37599let Inst{31-21} = 0b00011100101;
37600let hasNewValue = 1;
37601let opNewValue = 0;
37602let isCVI = 1;
37603let DecoderNamespace = "EXT_mmvec";
37604}
37605def V6_vsububh_alt : HInst<
37606(outs HvxWR:$Vdd32),
37607(ins HvxVR:$Vu32, HvxVR:$Vv32),
37608"$Vdd32 = vsubub($Vu32,$Vv32)",
37609PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37610let hasNewValue = 1;
37611let opNewValue = 0;
37612let isCVI = 1;
37613let isPseudo = 1;
37614let isCodeGenOnly = 1;
37615let DecoderNamespace = "EXT_mmvec";
37616}
37617def V6_vsububsat : HInst<
37618(outs HvxVR:$Vd32),
37619(ins HvxVR:$Vu32, HvxVR:$Vv32),
37620"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
37621tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37622let Inst{7-5} = 0b000;
37623let Inst{13-13} = 0b0;
37624let Inst{31-21} = 0b00011100011;
37625let hasNewValue = 1;
37626let opNewValue = 0;
37627let isCVI = 1;
37628let DecoderNamespace = "EXT_mmvec";
37629}
37630def V6_vsububsat_alt : HInst<
37631(outs HvxVR:$Vd32),
37632(ins HvxVR:$Vu32, HvxVR:$Vv32),
37633"$Vd32 = vsubub($Vu32,$Vv32):sat",
37634PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37635let hasNewValue = 1;
37636let opNewValue = 0;
37637let isCVI = 1;
37638let isPseudo = 1;
37639let isCodeGenOnly = 1;
37640let DecoderNamespace = "EXT_mmvec";
37641}
37642def V6_vsububsat_dv : HInst<
37643(outs HvxWR:$Vdd32),
37644(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37645"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
37646tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37647let Inst{7-5} = 0b110;
37648let Inst{13-13} = 0b0;
37649let Inst{31-21} = 0b00011100100;
37650let hasNewValue = 1;
37651let opNewValue = 0;
37652let isCVI = 1;
37653let DecoderNamespace = "EXT_mmvec";
37654}
37655def V6_vsububsat_dv_alt : HInst<
37656(outs HvxWR:$Vdd32),
37657(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37658"$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
37659PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37660let hasNewValue = 1;
37661let opNewValue = 0;
37662let isCVI = 1;
37663let isPseudo = 1;
37664let isCodeGenOnly = 1;
37665let DecoderNamespace = "EXT_mmvec";
37666}
37667def V6_vsubububb_sat : HInst<
37668(outs HvxVR:$Vd32),
37669(ins HvxVR:$Vu32, HvxVR:$Vv32),
37670"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
37671tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
37672let Inst{7-5} = 0b101;
37673let Inst{13-13} = 0b0;
37674let Inst{31-21} = 0b00011110101;
37675let hasNewValue = 1;
37676let opNewValue = 0;
37677let isCVI = 1;
37678let DecoderNamespace = "EXT_mmvec";
37679}
37680def V6_vsubuhsat : HInst<
37681(outs HvxVR:$Vd32),
37682(ins HvxVR:$Vu32, HvxVR:$Vv32),
37683"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
37684tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37685let Inst{7-5} = 0b001;
37686let Inst{13-13} = 0b0;
37687let Inst{31-21} = 0b00011100011;
37688let hasNewValue = 1;
37689let opNewValue = 0;
37690let isCVI = 1;
37691let DecoderNamespace = "EXT_mmvec";
37692}
37693def V6_vsubuhsat_alt : HInst<
37694(outs HvxVR:$Vd32),
37695(ins HvxVR:$Vu32, HvxVR:$Vv32),
37696"$Vd32 = vsubuh($Vu32,$Vv32):sat",
37697PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37698let hasNewValue = 1;
37699let opNewValue = 0;
37700let isCVI = 1;
37701let isPseudo = 1;
37702let isCodeGenOnly = 1;
37703let DecoderNamespace = "EXT_mmvec";
37704}
37705def V6_vsubuhsat_dv : HInst<
37706(outs HvxWR:$Vdd32),
37707(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37708"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
37709tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37710let Inst{7-5} = 0b111;
37711let Inst{13-13} = 0b0;
37712let Inst{31-21} = 0b00011100100;
37713let hasNewValue = 1;
37714let opNewValue = 0;
37715let isCVI = 1;
37716let DecoderNamespace = "EXT_mmvec";
37717}
37718def V6_vsubuhsat_dv_alt : HInst<
37719(outs HvxWR:$Vdd32),
37720(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37721"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
37722PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37723let hasNewValue = 1;
37724let opNewValue = 0;
37725let isCVI = 1;
37726let isPseudo = 1;
37727let isCodeGenOnly = 1;
37728let DecoderNamespace = "EXT_mmvec";
37729}
37730def V6_vsubuhw : HInst<
37731(outs HvxWR:$Vdd32),
37732(ins HvxVR:$Vu32, HvxVR:$Vv32),
37733"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
37734tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37735let Inst{7-5} = 0b110;
37736let Inst{13-13} = 0b0;
37737let Inst{31-21} = 0b00011100101;
37738let hasNewValue = 1;
37739let opNewValue = 0;
37740let isCVI = 1;
37741let DecoderNamespace = "EXT_mmvec";
37742}
37743def V6_vsubuhw_alt : HInst<
37744(outs HvxWR:$Vdd32),
37745(ins HvxVR:$Vu32, HvxVR:$Vv32),
37746"$Vdd32 = vsubuh($Vu32,$Vv32)",
37747PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37748let hasNewValue = 1;
37749let opNewValue = 0;
37750let isCVI = 1;
37751let isPseudo = 1;
37752let isCodeGenOnly = 1;
37753let DecoderNamespace = "EXT_mmvec";
37754}
37755def V6_vsubuwsat : HInst<
37756(outs HvxVR:$Vd32),
37757(ins HvxVR:$Vu32, HvxVR:$Vv32),
37758"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
37759tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
37760let Inst{7-5} = 0b100;
37761let Inst{13-13} = 0b0;
37762let Inst{31-21} = 0b00011111110;
37763let hasNewValue = 1;
37764let opNewValue = 0;
37765let isCVI = 1;
37766let DecoderNamespace = "EXT_mmvec";
37767}
37768def V6_vsubuwsat_alt : HInst<
37769(outs HvxVR:$Vd32),
37770(ins HvxVR:$Vu32, HvxVR:$Vv32),
37771"$Vd32 = vsubuw($Vu32,$Vv32):sat",
37772PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37773let hasNewValue = 1;
37774let opNewValue = 0;
37775let isCVI = 1;
37776let isPseudo = 1;
37777let isCodeGenOnly = 1;
37778let DecoderNamespace = "EXT_mmvec";
37779}
37780def V6_vsubuwsat_dv : HInst<
37781(outs HvxWR:$Vdd32),
37782(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37783"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
37784tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
37785let Inst{7-5} = 0b011;
37786let Inst{13-13} = 0b0;
37787let Inst{31-21} = 0b00011110101;
37788let hasNewValue = 1;
37789let opNewValue = 0;
37790let isCVI = 1;
37791let DecoderNamespace = "EXT_mmvec";
37792}
37793def V6_vsubuwsat_dv_alt : HInst<
37794(outs HvxWR:$Vdd32),
37795(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37796"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
37797PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37798let hasNewValue = 1;
37799let opNewValue = 0;
37800let isCVI = 1;
37801let isPseudo = 1;
37802let isCodeGenOnly = 1;
37803let DecoderNamespace = "EXT_mmvec";
37804}
37805def V6_vsubw : HInst<
37806(outs HvxVR:$Vd32),
37807(ins HvxVR:$Vu32, HvxVR:$Vv32),
37808"$Vd32.w = vsub($Vu32.w,$Vv32.w)",
37809tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37810let Inst{7-5} = 0b111;
37811let Inst{13-13} = 0b0;
37812let Inst{31-21} = 0b00011100010;
37813let hasNewValue = 1;
37814let opNewValue = 0;
37815let isCVI = 1;
37816let DecoderNamespace = "EXT_mmvec";
37817}
37818def V6_vsubw_alt : HInst<
37819(outs HvxVR:$Vd32),
37820(ins HvxVR:$Vu32, HvxVR:$Vv32),
37821"$Vd32 = vsubw($Vu32,$Vv32)",
37822PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37823let hasNewValue = 1;
37824let opNewValue = 0;
37825let isCVI = 1;
37826let isPseudo = 1;
37827let isCodeGenOnly = 1;
37828let DecoderNamespace = "EXT_mmvec";
37829}
37830def V6_vsubw_dv : HInst<
37831(outs HvxWR:$Vdd32),
37832(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37833"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
37834tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37835let Inst{7-5} = 0b101;
37836let Inst{13-13} = 0b0;
37837let Inst{31-21} = 0b00011100100;
37838let hasNewValue = 1;
37839let opNewValue = 0;
37840let isCVI = 1;
37841let DecoderNamespace = "EXT_mmvec";
37842}
37843def V6_vsubw_dv_alt : HInst<
37844(outs HvxWR:$Vdd32),
37845(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37846"$Vdd32 = vsubw($Vuu32,$Vvv32)",
37847PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37848let hasNewValue = 1;
37849let opNewValue = 0;
37850let isCVI = 1;
37851let isPseudo = 1;
37852let isCodeGenOnly = 1;
37853let DecoderNamespace = "EXT_mmvec";
37854}
37855def V6_vsubwnq : HInst<
37856(outs HvxVR:$Vx32),
37857(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37858"if (!$Qv4) $Vx32.w -= $Vu32.w",
37859tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37860let Inst{7-5} = 0b011;
37861let Inst{13-13} = 0b1;
37862let Inst{21-16} = 0b000010;
37863let Inst{31-24} = 0b00011110;
37864let hasNewValue = 1;
37865let opNewValue = 0;
37866let isCVI = 1;
37867let DecoderNamespace = "EXT_mmvec";
37868let Constraints = "$Vx32 = $Vx32in";
37869}
37870def V6_vsubwnq_alt : HInst<
37871(outs HvxVR:$Vx32),
37872(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37873"if (!$Qv4.w) $Vx32.w -= $Vu32.w",
37874PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37875let hasNewValue = 1;
37876let opNewValue = 0;
37877let isCVI = 1;
37878let isPseudo = 1;
37879let isCodeGenOnly = 1;
37880let DecoderNamespace = "EXT_mmvec";
37881let Constraints = "$Vx32 = $Vx32in";
37882}
37883def V6_vsubwq : HInst<
37884(outs HvxVR:$Vx32),
37885(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37886"if ($Qv4) $Vx32.w -= $Vu32.w",
37887tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37888let Inst{7-5} = 0b000;
37889let Inst{13-13} = 0b1;
37890let Inst{21-16} = 0b000010;
37891let Inst{31-24} = 0b00011110;
37892let hasNewValue = 1;
37893let opNewValue = 0;
37894let isCVI = 1;
37895let DecoderNamespace = "EXT_mmvec";
37896let Constraints = "$Vx32 = $Vx32in";
37897}
37898def V6_vsubwq_alt : HInst<
37899(outs HvxVR:$Vx32),
37900(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37901"if ($Qv4.w) $Vx32.w -= $Vu32.w",
37902PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37903let hasNewValue = 1;
37904let opNewValue = 0;
37905let isCVI = 1;
37906let isPseudo = 1;
37907let isCodeGenOnly = 1;
37908let DecoderNamespace = "EXT_mmvec";
37909let Constraints = "$Vx32 = $Vx32in";
37910}
37911def V6_vsubwsat : HInst<
37912(outs HvxVR:$Vd32),
37913(ins HvxVR:$Vu32, HvxVR:$Vv32),
37914"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
37915tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37916let Inst{7-5} = 0b011;
37917let Inst{13-13} = 0b0;
37918let Inst{31-21} = 0b00011100011;
37919let hasNewValue = 1;
37920let opNewValue = 0;
37921let isCVI = 1;
37922let DecoderNamespace = "EXT_mmvec";
37923}
37924def V6_vsubwsat_alt : HInst<
37925(outs HvxVR:$Vd32),
37926(ins HvxVR:$Vu32, HvxVR:$Vv32),
37927"$Vd32 = vsubw($Vu32,$Vv32):sat",
37928PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37929let hasNewValue = 1;
37930let opNewValue = 0;
37931let isCVI = 1;
37932let isPseudo = 1;
37933let isCodeGenOnly = 1;
37934let DecoderNamespace = "EXT_mmvec";
37935}
37936def V6_vsubwsat_dv : HInst<
37937(outs HvxWR:$Vdd32),
37938(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37939"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
37940tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37941let Inst{7-5} = 0b001;
37942let Inst{13-13} = 0b0;
37943let Inst{31-21} = 0b00011100101;
37944let hasNewValue = 1;
37945let opNewValue = 0;
37946let isCVI = 1;
37947let DecoderNamespace = "EXT_mmvec";
37948}
37949def V6_vsubwsat_dv_alt : HInst<
37950(outs HvxWR:$Vdd32),
37951(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37952"$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
37953PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37954let hasNewValue = 1;
37955let opNewValue = 0;
37956let isCVI = 1;
37957let isPseudo = 1;
37958let isCodeGenOnly = 1;
37959let DecoderNamespace = "EXT_mmvec";
37960}
37961def V6_vswap : HInst<
37962(outs HvxWR:$Vdd32),
37963(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
37964"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
37965tc_71646d06, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
37966let Inst{7-7} = 0b0;
37967let Inst{13-13} = 0b1;
37968let Inst{31-21} = 0b00011110101;
37969let hasNewValue = 1;
37970let opNewValue = 0;
37971let isCVI = 1;
37972let DecoderNamespace = "EXT_mmvec";
37973}
37974def V6_vtmpyb : HInst<
37975(outs HvxWR:$Vdd32),
37976(ins HvxWR:$Vuu32, IntRegs:$Rt32),
37977"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
37978tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
37979let Inst{7-5} = 0b000;
37980let Inst{13-13} = 0b0;
37981let Inst{31-21} = 0b00011001000;
37982let hasNewValue = 1;
37983let opNewValue = 0;
37984let isCVI = 1;
37985let DecoderNamespace = "EXT_mmvec";
37986}
37987def V6_vtmpyb_acc : HInst<
37988(outs HvxWR:$Vxx32),
37989(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
37990"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
37991tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
37992let Inst{7-5} = 0b000;
37993let Inst{13-13} = 0b1;
37994let Inst{31-21} = 0b00011001000;
37995let hasNewValue = 1;
37996let opNewValue = 0;
37997let isAccumulator = 1;
37998let isCVI = 1;
37999let DecoderNamespace = "EXT_mmvec";
38000let Constraints = "$Vxx32 = $Vxx32in";
38001}
38002def V6_vtmpyb_acc_alt : HInst<
38003(outs HvxWR:$Vxx32),
38004(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38005"$Vxx32 += vtmpyb($Vuu32,$Rt32)",
38006PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38007let hasNewValue = 1;
38008let opNewValue = 0;
38009let isAccumulator = 1;
38010let isCVI = 1;
38011let isPseudo = 1;
38012let isCodeGenOnly = 1;
38013let DecoderNamespace = "EXT_mmvec";
38014let Constraints = "$Vxx32 = $Vxx32in";
38015}
38016def V6_vtmpyb_alt : HInst<
38017(outs HvxWR:$Vdd32),
38018(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38019"$Vdd32 = vtmpyb($Vuu32,$Rt32)",
38020PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38021let hasNewValue = 1;
38022let opNewValue = 0;
38023let isCVI = 1;
38024let isPseudo = 1;
38025let isCodeGenOnly = 1;
38026let DecoderNamespace = "EXT_mmvec";
38027}
38028def V6_vtmpybus : HInst<
38029(outs HvxWR:$Vdd32),
38030(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38031"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
38032tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
38033let Inst{7-5} = 0b001;
38034let Inst{13-13} = 0b0;
38035let Inst{31-21} = 0b00011001000;
38036let hasNewValue = 1;
38037let opNewValue = 0;
38038let isCVI = 1;
38039let DecoderNamespace = "EXT_mmvec";
38040}
38041def V6_vtmpybus_acc : HInst<
38042(outs HvxWR:$Vxx32),
38043(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38044"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
38045tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
38046let Inst{7-5} = 0b001;
38047let Inst{13-13} = 0b1;
38048let Inst{31-21} = 0b00011001000;
38049let hasNewValue = 1;
38050let opNewValue = 0;
38051let isAccumulator = 1;
38052let isCVI = 1;
38053let DecoderNamespace = "EXT_mmvec";
38054let Constraints = "$Vxx32 = $Vxx32in";
38055}
38056def V6_vtmpybus_acc_alt : HInst<
38057(outs HvxWR:$Vxx32),
38058(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38059"$Vxx32 += vtmpybus($Vuu32,$Rt32)",
38060PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38061let hasNewValue = 1;
38062let opNewValue = 0;
38063let isAccumulator = 1;
38064let isCVI = 1;
38065let isPseudo = 1;
38066let isCodeGenOnly = 1;
38067let DecoderNamespace = "EXT_mmvec";
38068let Constraints = "$Vxx32 = $Vxx32in";
38069}
38070def V6_vtmpybus_alt : HInst<
38071(outs HvxWR:$Vdd32),
38072(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38073"$Vdd32 = vtmpybus($Vuu32,$Rt32)",
38074PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38075let hasNewValue = 1;
38076let opNewValue = 0;
38077let isCVI = 1;
38078let isPseudo = 1;
38079let isCodeGenOnly = 1;
38080let DecoderNamespace = "EXT_mmvec";
38081}
38082def V6_vtmpyhb : HInst<
38083(outs HvxWR:$Vdd32),
38084(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38085"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
38086tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
38087let Inst{7-5} = 0b100;
38088let Inst{13-13} = 0b0;
38089let Inst{31-21} = 0b00011001101;
38090let hasNewValue = 1;
38091let opNewValue = 0;
38092let isCVI = 1;
38093let DecoderNamespace = "EXT_mmvec";
38094}
38095def V6_vtmpyhb_acc : HInst<
38096(outs HvxWR:$Vxx32),
38097(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38098"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
38099tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
38100let Inst{7-5} = 0b010;
38101let Inst{13-13} = 0b1;
38102let Inst{31-21} = 0b00011001000;
38103let hasNewValue = 1;
38104let opNewValue = 0;
38105let isAccumulator = 1;
38106let isCVI = 1;
38107let DecoderNamespace = "EXT_mmvec";
38108let Constraints = "$Vxx32 = $Vxx32in";
38109}
38110def V6_vtmpyhb_acc_alt : HInst<
38111(outs HvxWR:$Vxx32),
38112(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38113"$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
38114PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38115let hasNewValue = 1;
38116let opNewValue = 0;
38117let isAccumulator = 1;
38118let isCVI = 1;
38119let isPseudo = 1;
38120let isCodeGenOnly = 1;
38121let DecoderNamespace = "EXT_mmvec";
38122let Constraints = "$Vxx32 = $Vxx32in";
38123}
38124def V6_vtmpyhb_alt : HInst<
38125(outs HvxWR:$Vdd32),
38126(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38127"$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
38128PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38129let hasNewValue = 1;
38130let opNewValue = 0;
38131let isCVI = 1;
38132let isPseudo = 1;
38133let isCodeGenOnly = 1;
38134let DecoderNamespace = "EXT_mmvec";
38135}
38136def V6_vtran2x2_map : HInst<
38137(outs HvxVR:$Vy32, HvxVR:$Vx32),
38138(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
38139"vtrans2x2($Vy32,$Vx32,$Rt32)",
38140PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38141let hasNewValue = 1;
38142let opNewValue = 0;
38143let hasNewValue2 = 1;
38144let opNewValue2 = 1;
38145let isCVI = 1;
38146let isPseudo = 1;
38147let isCodeGenOnly = 1;
38148let DecoderNamespace = "EXT_mmvec";
38149let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
38150}
38151def V6_vunpackb : HInst<
38152(outs HvxWR:$Vdd32),
38153(ins HvxVR:$Vu32),
38154"$Vdd32.h = vunpack($Vu32.b)",
38155tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38156let Inst{7-5} = 0b010;
38157let Inst{13-13} = 0b0;
38158let Inst{31-16} = 0b0001111000000001;
38159let hasNewValue = 1;
38160let opNewValue = 0;
38161let isCVI = 1;
38162let DecoderNamespace = "EXT_mmvec";
38163}
38164def V6_vunpackb_alt : HInst<
38165(outs HvxWR:$Vdd32),
38166(ins HvxVR:$Vu32),
38167"$Vdd32 = vunpackb($Vu32)",
38168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38169let hasNewValue = 1;
38170let opNewValue = 0;
38171let isCVI = 1;
38172let isPseudo = 1;
38173let isCodeGenOnly = 1;
38174let DecoderNamespace = "EXT_mmvec";
38175}
38176def V6_vunpackh : HInst<
38177(outs HvxWR:$Vdd32),
38178(ins HvxVR:$Vu32),
38179"$Vdd32.w = vunpack($Vu32.h)",
38180tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38181let Inst{7-5} = 0b011;
38182let Inst{13-13} = 0b0;
38183let Inst{31-16} = 0b0001111000000001;
38184let hasNewValue = 1;
38185let opNewValue = 0;
38186let isCVI = 1;
38187let DecoderNamespace = "EXT_mmvec";
38188}
38189def V6_vunpackh_alt : HInst<
38190(outs HvxWR:$Vdd32),
38191(ins HvxVR:$Vu32),
38192"$Vdd32 = vunpackh($Vu32)",
38193PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38194let hasNewValue = 1;
38195let opNewValue = 0;
38196let isCVI = 1;
38197let isPseudo = 1;
38198let isCodeGenOnly = 1;
38199let DecoderNamespace = "EXT_mmvec";
38200}
38201def V6_vunpackob : HInst<
38202(outs HvxWR:$Vxx32),
38203(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38204"$Vxx32.h |= vunpacko($Vu32.b)",
38205tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
38206let Inst{7-5} = 0b000;
38207let Inst{13-13} = 0b1;
38208let Inst{31-16} = 0b0001111000000000;
38209let hasNewValue = 1;
38210let opNewValue = 0;
38211let isAccumulator = 1;
38212let isCVI = 1;
38213let DecoderNamespace = "EXT_mmvec";
38214let Constraints = "$Vxx32 = $Vxx32in";
38215}
38216def V6_vunpackob_alt : HInst<
38217(outs HvxWR:$Vxx32),
38218(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38219"$Vxx32 |= vunpackob($Vu32)",
38220PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38221let hasNewValue = 1;
38222let opNewValue = 0;
38223let isAccumulator = 1;
38224let isCVI = 1;
38225let isPseudo = 1;
38226let DecoderNamespace = "EXT_mmvec";
38227let Constraints = "$Vxx32 = $Vxx32in";
38228}
38229def V6_vunpackoh : HInst<
38230(outs HvxWR:$Vxx32),
38231(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38232"$Vxx32.w |= vunpacko($Vu32.h)",
38233tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
38234let Inst{7-5} = 0b001;
38235let Inst{13-13} = 0b1;
38236let Inst{31-16} = 0b0001111000000000;
38237let hasNewValue = 1;
38238let opNewValue = 0;
38239let isAccumulator = 1;
38240let isCVI = 1;
38241let DecoderNamespace = "EXT_mmvec";
38242let Constraints = "$Vxx32 = $Vxx32in";
38243}
38244def V6_vunpackoh_alt : HInst<
38245(outs HvxWR:$Vxx32),
38246(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38247"$Vxx32 |= vunpackoh($Vu32)",
38248PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38249let hasNewValue = 1;
38250let opNewValue = 0;
38251let isAccumulator = 1;
38252let isCVI = 1;
38253let isPseudo = 1;
38254let isCodeGenOnly = 1;
38255let DecoderNamespace = "EXT_mmvec";
38256let Constraints = "$Vxx32 = $Vxx32in";
38257}
38258def V6_vunpackub : HInst<
38259(outs HvxWR:$Vdd32),
38260(ins HvxVR:$Vu32),
38261"$Vdd32.uh = vunpack($Vu32.ub)",
38262tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38263let Inst{7-5} = 0b000;
38264let Inst{13-13} = 0b0;
38265let Inst{31-16} = 0b0001111000000001;
38266let hasNewValue = 1;
38267let opNewValue = 0;
38268let isCVI = 1;
38269let DecoderNamespace = "EXT_mmvec";
38270}
38271def V6_vunpackub_alt : HInst<
38272(outs HvxWR:$Vdd32),
38273(ins HvxVR:$Vu32),
38274"$Vdd32 = vunpackub($Vu32)",
38275PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38276let hasNewValue = 1;
38277let opNewValue = 0;
38278let isCVI = 1;
38279let isPseudo = 1;
38280let isCodeGenOnly = 1;
38281let DecoderNamespace = "EXT_mmvec";
38282}
38283def V6_vunpackuh : HInst<
38284(outs HvxWR:$Vdd32),
38285(ins HvxVR:$Vu32),
38286"$Vdd32.uw = vunpack($Vu32.uh)",
38287tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38288let Inst{7-5} = 0b001;
38289let Inst{13-13} = 0b0;
38290let Inst{31-16} = 0b0001111000000001;
38291let hasNewValue = 1;
38292let opNewValue = 0;
38293let isCVI = 1;
38294let DecoderNamespace = "EXT_mmvec";
38295}
38296def V6_vunpackuh_alt : HInst<
38297(outs HvxWR:$Vdd32),
38298(ins HvxVR:$Vu32),
38299"$Vdd32 = vunpackuh($Vu32)",
38300PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38301let hasNewValue = 1;
38302let opNewValue = 0;
38303let isCVI = 1;
38304let isPseudo = 1;
38305let isCodeGenOnly = 1;
38306let DecoderNamespace = "EXT_mmvec";
38307}
38308def V6_vwhist128 : HInst<
38309(outs),
38310(ins),
38311"vwhist128",
38312tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
38313let Inst{13-0} = 0b10010010000000;
38314let Inst{31-16} = 0b0001111000000000;
38315let isCVI = 1;
38316let DecoderNamespace = "EXT_mmvec";
38317}
38318def V6_vwhist128m : HInst<
38319(outs),
38320(ins u1_0Imm:$Ii),
38321"vwhist128(#$Ii)",
38322tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
38323let Inst{7-0} = 0b10000000;
38324let Inst{13-9} = 0b10011;
38325let Inst{31-16} = 0b0001111000000000;
38326let isCVI = 1;
38327let DecoderNamespace = "EXT_mmvec";
38328}
38329def V6_vwhist128q : HInst<
38330(outs),
38331(ins HvxQR:$Qv4),
38332"vwhist128($Qv4)",
38333tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
38334let Inst{13-0} = 0b10010010000000;
38335let Inst{21-16} = 0b000010;
38336let Inst{31-24} = 0b00011110;
38337let isCVI = 1;
38338let DecoderNamespace = "EXT_mmvec";
38339}
38340def V6_vwhist128qm : HInst<
38341(outs),
38342(ins HvxQR:$Qv4, u1_0Imm:$Ii),
38343"vwhist128($Qv4,#$Ii)",
38344tc_767c4e9d, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
38345let Inst{7-0} = 0b10000000;
38346let Inst{13-9} = 0b10011;
38347let Inst{21-16} = 0b000010;
38348let Inst{31-24} = 0b00011110;
38349let isCVI = 1;
38350let DecoderNamespace = "EXT_mmvec";
38351}
38352def V6_vwhist256 : HInst<
38353(outs),
38354(ins),
38355"vwhist256",
38356tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
38357let Inst{13-0} = 0b10001010000000;
38358let Inst{31-16} = 0b0001111000000000;
38359let isCVI = 1;
38360let DecoderNamespace = "EXT_mmvec";
38361}
38362def V6_vwhist256_sat : HInst<
38363(outs),
38364(ins),
38365"vwhist256:sat",
38366tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
38367let Inst{13-0} = 0b10001110000000;
38368let Inst{31-16} = 0b0001111000000000;
38369let isCVI = 1;
38370let DecoderNamespace = "EXT_mmvec";
38371}
38372def V6_vwhist256q : HInst<
38373(outs),
38374(ins HvxQR:$Qv4),
38375"vwhist256($Qv4)",
38376tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
38377let Inst{13-0} = 0b10001010000000;
38378let Inst{21-16} = 0b000010;
38379let Inst{31-24} = 0b00011110;
38380let isCVI = 1;
38381let DecoderNamespace = "EXT_mmvec";
38382}
38383def V6_vwhist256q_sat : HInst<
38384(outs),
38385(ins HvxQR:$Qv4),
38386"vwhist256($Qv4):sat",
38387tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
38388let Inst{13-0} = 0b10001110000000;
38389let Inst{21-16} = 0b000010;
38390let Inst{31-24} = 0b00011110;
38391let isCVI = 1;
38392let DecoderNamespace = "EXT_mmvec";
38393}
38394def V6_vxor : HInst<
38395(outs HvxVR:$Vd32),
38396(ins HvxVR:$Vu32, HvxVR:$Vv32),
38397"$Vd32 = vxor($Vu32,$Vv32)",
38398tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38399let Inst{7-5} = 0b111;
38400let Inst{13-13} = 0b0;
38401let Inst{31-21} = 0b00011100001;
38402let hasNewValue = 1;
38403let opNewValue = 0;
38404let isCVI = 1;
38405let DecoderNamespace = "EXT_mmvec";
38406}
38407def V6_vzb : HInst<
38408(outs HvxWR:$Vdd32),
38409(ins HvxVR:$Vu32),
38410"$Vdd32.uh = vzxt($Vu32.ub)",
38411tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38412let Inst{7-5} = 0b001;
38413let Inst{13-13} = 0b0;
38414let Inst{31-16} = 0b0001111000000010;
38415let hasNewValue = 1;
38416let opNewValue = 0;
38417let isCVI = 1;
38418let DecoderNamespace = "EXT_mmvec";
38419}
38420def V6_vzb_alt : HInst<
38421(outs HvxWR:$Vdd32),
38422(ins HvxVR:$Vu32),
38423"$Vdd32 = vzxtb($Vu32)",
38424PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38425let hasNewValue = 1;
38426let opNewValue = 0;
38427let isCVI = 1;
38428let isPseudo = 1;
38429let isCodeGenOnly = 1;
38430let DecoderNamespace = "EXT_mmvec";
38431}
38432def V6_vzh : HInst<
38433(outs HvxWR:$Vdd32),
38434(ins HvxVR:$Vu32),
38435"$Vdd32.uw = vzxt($Vu32.uh)",
38436tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38437let Inst{7-5} = 0b010;
38438let Inst{13-13} = 0b0;
38439let Inst{31-16} = 0b0001111000000010;
38440let hasNewValue = 1;
38441let opNewValue = 0;
38442let isCVI = 1;
38443let DecoderNamespace = "EXT_mmvec";
38444}
38445def V6_vzh_alt : HInst<
38446(outs HvxWR:$Vdd32),
38447(ins HvxVR:$Vu32),
38448"$Vdd32 = vzxth($Vu32)",
38449PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38450let hasNewValue = 1;
38451let opNewValue = 0;
38452let isCVI = 1;
38453let isPseudo = 1;
38454let isCodeGenOnly = 1;
38455let DecoderNamespace = "EXT_mmvec";
38456}
38457def V6_zLd_ai : HInst<
38458(outs),
38459(ins IntRegs:$Rt32, s4_0Imm:$Ii),
38460"z = vmem($Rt32+#$Ii)",
38461tc_e699ae41, TypeCVI_ZW>, Enc_ff3442, Requires<[UseHVXV66,UseZReg]> {
38462let Inst{7-0} = 0b00000000;
38463let Inst{12-11} = 0b00;
38464let Inst{31-21} = 0b00101100000;
38465let addrMode = BaseImmOffset;
38466let isCVI = 1;
38467let mayLoad = 1;
38468let isRestrictNoSlot1Store = 1;
38469let DecoderNamespace = "EXT_mmvec";
38470}
38471def V6_zLd_pi : HInst<
38472(outs IntRegs:$Rx32),
38473(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
38474"z = vmem($Rx32++#$Ii)",
38475tc_a0dbea28, TypeCVI_ZW>, Enc_6c9ee0, Requires<[UseHVXV66,UseZReg]> {
38476let Inst{7-0} = 0b00000000;
38477let Inst{13-11} = 0b000;
38478let Inst{31-21} = 0b00101101000;
38479let addrMode = PostInc;
38480let isCVI = 1;
38481let mayLoad = 1;
38482let isRestrictNoSlot1Store = 1;
38483let DecoderNamespace = "EXT_mmvec";
38484let Constraints = "$Rx32 = $Rx32in";
38485}
38486def V6_zLd_ppu : HInst<
38487(outs IntRegs:$Rx32),
38488(ins IntRegs:$Rx32in, ModRegs:$Mu2),
38489"z = vmem($Rx32++$Mu2)",
38490tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> {
38491let Inst{12-0} = 0b0000000000001;
38492let Inst{31-21} = 0b00101101000;
38493let addrMode = PostInc;
38494let isCVI = 1;
38495let mayLoad = 1;
38496let isRestrictNoSlot1Store = 1;
38497let DecoderNamespace = "EXT_mmvec";
38498let Constraints = "$Rx32 = $Rx32in";
38499}
38500def V6_zLd_pred_ai : HInst<
38501(outs),
38502(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
38503"if ($Pv4) z = vmem($Rt32+#$Ii)",
38504tc_dd5b0695, TypeCVI_ZW>, Enc_ef601b, Requires<[UseHVXV66,UseZReg]> {
38505let Inst{7-0} = 0b00000000;
38506let Inst{31-21} = 0b00101100100;
38507let isPredicated = 1;
38508let addrMode = BaseImmOffset;
38509let isCVI = 1;
38510let mayLoad = 1;
38511let isRestrictNoSlot1Store = 1;
38512let DecoderNamespace = "EXT_mmvec";
38513}
38514def V6_zLd_pred_pi : HInst<
38515(outs IntRegs:$Rx32),
38516(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
38517"if ($Pv4) z = vmem($Rx32++#$Ii)",
38518tc_3ad719fb, TypeCVI_ZW>, Enc_6baed4, Requires<[UseHVXV66,UseZReg]> {
38519let Inst{7-0} = 0b00000000;
38520let Inst{13-13} = 0b0;
38521let Inst{31-21} = 0b00101101100;
38522let isPredicated = 1;
38523let addrMode = PostInc;
38524let isCVI = 1;
38525let mayLoad = 1;
38526let isRestrictNoSlot1Store = 1;
38527let DecoderNamespace = "EXT_mmvec";
38528let Constraints = "$Rx32 = $Rx32in";
38529}
38530def V6_zLd_pred_ppu : HInst<
38531(outs IntRegs:$Rx32),
38532(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
38533"if ($Pv4) z = vmem($Rx32++$Mu2)",
38534tc_3ad719fb, TypeCVI_ZW>, Enc_691712, Requires<[UseHVXV66,UseZReg]> {
38535let Inst{10-0} = 0b00000000001;
38536let Inst{31-21} = 0b00101101100;
38537let isPredicated = 1;
38538let addrMode = PostInc;
38539let isCVI = 1;
38540let mayLoad = 1;
38541let isRestrictNoSlot1Store = 1;
38542let DecoderNamespace = "EXT_mmvec";
38543let Constraints = "$Rx32 = $Rx32in";
38544}
38545def V6_zextract : HInst<
38546(outs HvxVR:$Vd32),
38547(ins IntRegs:$Rt32),
38548"$Vd32 = zextract($Rt32)",
38549tc_5bf8afbb, TypeCVI_VP>, Enc_a5ed8a, Requires<[UseHVXV66,UseZReg]> {
38550let Inst{13-5} = 0b000001001;
38551let Inst{31-21} = 0b00011001101;
38552let hasNewValue = 1;
38553let opNewValue = 0;
38554let isCVI = 1;
38555let DecoderNamespace = "EXT_mmvec";
38556}
38557def V6_zld0 : HInst<
38558(outs),
38559(ins IntRegs:$Rt32),
38560"z = vmem($Rt32)",
38561PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
38562let isCVI = 1;
38563let isPseudo = 1;
38564let isCodeGenOnly = 1;
38565let DecoderNamespace = "EXT_mmvec";
38566}
38567def V6_zldp0 : HInst<
38568(outs),
38569(ins PredRegs:$Pv4, IntRegs:$Rt32),
38570"if ($Pv4) z = vmem($Rt32)",
38571PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
38572let isCVI = 1;
38573let isPseudo = 1;
38574let isCodeGenOnly = 1;
38575let DecoderNamespace = "EXT_mmvec";
38576}
38577def Y2_barrier : HInst<
38578(outs),
38579(ins),
38580"barrier",
38581tc_77f94a5e, TypeST>, Enc_e3b0c4 {
38582let Inst{13-0} = 0b00000000000000;
38583let Inst{31-16} = 0b1010100000000000;
38584let isSoloAX = 1;
38585let hasSideEffects = 1;
38586}
38587def Y2_break : HInst<
38588(outs),
38589(ins),
38590"brkpt",
38591tc_55255f2b, TypeCR>, Enc_e3b0c4 {
38592let Inst{13-0} = 0b00000000000000;
38593let Inst{31-16} = 0b0110110000100000;
38594let isSolo = 1;
38595}
38596def Y2_dccleana : HInst<
38597(outs),
38598(ins IntRegs:$Rs32),
38599"dccleana($Rs32)",
38600tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38601let Inst{13-0} = 0b00000000000000;
38602let Inst{31-21} = 0b10100000000;
38603let isRestrictSlot1AOK = 1;
38604let hasSideEffects = 1;
38605}
38606def Y2_dccleaninva : HInst<
38607(outs),
38608(ins IntRegs:$Rs32),
38609"dccleaninva($Rs32)",
38610tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38611let Inst{13-0} = 0b00000000000000;
38612let Inst{31-21} = 0b10100000010;
38613let isRestrictSlot1AOK = 1;
38614let hasSideEffects = 1;
38615}
38616def Y2_dcfetch : HInst<
38617(outs),
38618(ins IntRegs:$Rs32),
38619"dcfetch($Rs32)",
38620tc_d45ba9cd, TypeMAPPING> {
38621let hasSideEffects = 1;
38622let isPseudo = 1;
38623let isCodeGenOnly = 1;
38624}
38625def Y2_dcfetchbo : HInst<
38626(outs),
38627(ins IntRegs:$Rs32, u11_3Imm:$Ii),
38628"dcfetch($Rs32+#$Ii)",
38629tc_2237d952, TypeLD>, Enc_2d829e {
38630let Inst{13-11} = 0b000;
38631let Inst{31-21} = 0b10010100000;
38632let addrMode = BaseImmOffset;
38633let isRestrictNoSlot1Store = 1;
38634let hasSideEffects = 1;
38635}
38636def Y2_dcinva : HInst<
38637(outs),
38638(ins IntRegs:$Rs32),
38639"dcinva($Rs32)",
38640tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38641let Inst{13-0} = 0b00000000000000;
38642let Inst{31-21} = 0b10100000001;
38643let isRestrictSlot1AOK = 1;
38644let hasSideEffects = 1;
38645}
38646def Y2_dczeroa : HInst<
38647(outs),
38648(ins IntRegs:$Rs32),
38649"dczeroa($Rs32)",
38650tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38651let Inst{13-0} = 0b00000000000000;
38652let Inst{31-21} = 0b10100000110;
38653let isRestrictSlot1AOK = 1;
38654let mayStore = 1;
38655let hasSideEffects = 1;
38656}
38657def Y2_icinva : HInst<
38658(outs),
38659(ins IntRegs:$Rs32),
38660"icinva($Rs32)",
38661tc_0ba0d5da, TypeJ>, Enc_ecbcc8 {
38662let Inst{13-0} = 0b00000000000000;
38663let Inst{31-21} = 0b01010110110;
38664let isSolo = 1;
38665}
38666def Y2_isync : HInst<
38667(outs),
38668(ins),
38669"isync",
38670tc_9b34f5e0, TypeJ>, Enc_e3b0c4 {
38671let Inst{13-0} = 0b00000000000010;
38672let Inst{31-16} = 0b0101011111000000;
38673let isSolo = 1;
38674}
38675def Y2_syncht : HInst<
38676(outs),
38677(ins),
38678"syncht",
38679tc_77f94a5e, TypeST>, Enc_e3b0c4 {
38680let Inst{13-0} = 0b00000000000000;
38681let Inst{31-16} = 0b1010100001000000;
38682let isSolo = 1;
38683}
38684def Y2_wait : HInst<
38685(outs),
38686(ins IntRegs:$Rs32),
38687"wait($Rs32)",
38688tc_d7718fbe, TypeCR>, Enc_ecbcc8 {
38689let Inst{13-0} = 0b00000000000000;
38690let Inst{31-21} = 0b01100100010;
38691let isSolo = 1;
38692}
38693def Y4_l2fetch : HInst<
38694(outs),
38695(ins IntRegs:$Rs32, IntRegs:$Rt32),
38696"l2fetch($Rs32,$Rt32)",
38697tc_a3070909, TypeST>, Enc_ca3887 {
38698let Inst{7-0} = 0b00000000;
38699let Inst{13-13} = 0b0;
38700let Inst{31-21} = 0b10100110000;
38701let isSoloAX = 1;
38702let mayStore = 1;
38703let hasSideEffects = 1;
38704}
38705def Y4_trace : HInst<
38706(outs),
38707(ins IntRegs:$Rs32),
38708"trace($Rs32)",
38709tc_d7718fbe, TypeCR>, Enc_ecbcc8 {
38710let Inst{13-0} = 0b00000000000000;
38711let Inst{31-21} = 0b01100010010;
38712let isSoloAX = 1;
38713}
38714def Y5_l2fetch : HInst<
38715(outs),
38716(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
38717"l2fetch($Rs32,$Rtt32)",
38718tc_a3070909, TypeST>, Enc_e6abcf {
38719let Inst{7-0} = 0b00000000;
38720let Inst{13-13} = 0b0;
38721let Inst{31-21} = 0b10100110100;
38722let isSoloAX = 1;
38723let mayStore = 1;
38724let hasSideEffects = 1;
38725}
38726def Y6_diag : HInst<
38727(outs),
38728(ins IntRegs:$Rs32),
38729"diag($Rs32)",
38730tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV67]> {
38731let Inst{13-0} = 0b00000000100000;
38732let Inst{31-21} = 0b01100010010;
38733}
38734def Y6_diag0 : HInst<
38735(outs),
38736(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
38737"diag0($Rss32,$Rtt32)",
38738tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
38739let Inst{7-0} = 0b01000000;
38740let Inst{13-13} = 0b0;
38741let Inst{31-21} = 0b01100010010;
38742}
38743def Y6_diag1 : HInst<
38744(outs),
38745(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
38746"diag1($Rss32,$Rtt32)",
38747tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
38748let Inst{7-0} = 0b01100000;
38749let Inst{13-13} = 0b0;
38750let Inst{31-21} = 0b01100010010;
38751}
38752def dep_A2_addsat : HInst<
38753(outs IntRegs:$Rd32),
38754(ins IntRegs:$Rs32, IntRegs:$Rt32),
38755"$Rd32 = add($Rs32,$Rt32):sat:deprecated",
38756tc_8a825db2, TypeALU64>, Enc_5ab2be {
38757let Inst{7-5} = 0b000;
38758let Inst{13-13} = 0b0;
38759let Inst{31-21} = 0b11010101100;
38760let hasNewValue = 1;
38761let opNewValue = 0;
38762let prefersSlot3 = 1;
38763let Defs = [USR_OVF];
38764}
38765def dep_A2_subsat : HInst<
38766(outs IntRegs:$Rd32),
38767(ins IntRegs:$Rt32, IntRegs:$Rs32),
38768"$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
38769tc_8a825db2, TypeALU64>, Enc_bd6011 {
38770let Inst{7-5} = 0b100;
38771let Inst{13-13} = 0b0;
38772let Inst{31-21} = 0b11010101100;
38773let hasNewValue = 1;
38774let opNewValue = 0;
38775let prefersSlot3 = 1;
38776let Defs = [USR_OVF];
38777}
38778def dep_S2_packhl : HInst<
38779(outs DoubleRegs:$Rdd32),
38780(ins IntRegs:$Rs32, IntRegs:$Rt32),
38781"$Rdd32 = packhl($Rs32,$Rt32):deprecated",
38782tc_5da50c4b, TypeALU64>, Enc_be32a5 {
38783let Inst{7-5} = 0b000;
38784let Inst{13-13} = 0b0;
38785let Inst{31-21} = 0b11010100000;
38786}
38787def dup_A2_add : HInst<
38788(outs IntRegs:$Rd32),
38789(ins IntRegs:$Rs32, IntRegs:$Rt32),
38790"$Rd32 = add($Rs32,$Rt32)",
38791tc_388f9897, TypeALU32_3op>, Requires<[HasV67]> {
38792let hasNewValue = 1;
38793let opNewValue = 0;
38794let AsmVariantName = "NonParsable";
38795let isPseudo = 1;
38796}
38797def dup_A2_addi : HInst<
38798(outs IntRegs:$Rd32),
38799(ins IntRegs:$Rs32, s32_0Imm:$Ii),
38800"$Rd32 = add($Rs32,#$Ii)",
38801tc_388f9897, TypeALU32_ADDI>, Requires<[HasV67]> {
38802let hasNewValue = 1;
38803let opNewValue = 0;
38804let AsmVariantName = "NonParsable";
38805let isPseudo = 1;
38806let isExtendable = 1;
38807let opExtendable = 2;
38808let isExtentSigned = 1;
38809let opExtentBits = 16;
38810let opExtentAlign = 0;
38811}
38812def dup_A2_andir : HInst<
38813(outs IntRegs:$Rd32),
38814(ins IntRegs:$Rs32, s32_0Imm:$Ii),
38815"$Rd32 = and($Rs32,#$Ii)",
38816tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
38817let hasNewValue = 1;
38818let opNewValue = 0;
38819let AsmVariantName = "NonParsable";
38820let isPseudo = 1;
38821let isExtendable = 1;
38822let opExtendable = 2;
38823let isExtentSigned = 1;
38824let opExtentBits = 10;
38825let opExtentAlign = 0;
38826}
38827def dup_A2_combineii : HInst<
38828(outs DoubleRegs:$Rdd32),
38829(ins s32_0Imm:$Ii, s8_0Imm:$II),
38830"$Rdd32 = combine(#$Ii,#$II)",
38831tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
38832let AsmVariantName = "NonParsable";
38833let isPseudo = 1;
38834let isExtendable = 1;
38835let opExtendable = 1;
38836let isExtentSigned = 1;
38837let opExtentBits = 8;
38838let opExtentAlign = 0;
38839}
38840def dup_A2_sxtb : HInst<
38841(outs IntRegs:$Rd32),
38842(ins IntRegs:$Rs32),
38843"$Rd32 = sxtb($Rs32)",
38844tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> {
38845let hasNewValue = 1;
38846let opNewValue = 0;
38847let AsmVariantName = "NonParsable";
38848let isPseudo = 1;
38849}
38850def dup_A2_sxth : HInst<
38851(outs IntRegs:$Rd32),
38852(ins IntRegs:$Rs32),
38853"$Rd32 = sxth($Rs32)",
38854tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> {
38855let hasNewValue = 1;
38856let opNewValue = 0;
38857let AsmVariantName = "NonParsable";
38858let isPseudo = 1;
38859}
38860def dup_A2_tfr : HInst<
38861(outs IntRegs:$Rd32),
38862(ins IntRegs:$Rs32),
38863"$Rd32 = $Rs32",
38864tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> {
38865let hasNewValue = 1;
38866let opNewValue = 0;
38867let AsmVariantName = "NonParsable";
38868let isPseudo = 1;
38869}
38870def dup_A2_tfrsi : HInst<
38871(outs IntRegs:$Rd32),
38872(ins s32_0Imm:$Ii),
38873"$Rd32 = #$Ii",
38874tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> {
38875let hasNewValue = 1;
38876let opNewValue = 0;
38877let AsmVariantName = "NonParsable";
38878let isPseudo = 1;
38879let isExtendable = 1;
38880let opExtendable = 1;
38881let isExtentSigned = 1;
38882let opExtentBits = 16;
38883let opExtentAlign = 0;
38884}
38885def dup_A2_zxtb : HInst<
38886(outs IntRegs:$Rd32),
38887(ins IntRegs:$Rs32),
38888"$Rd32 = zxtb($Rs32)",
38889PSEUDO, TypeMAPPING>, Requires<[HasV67]> {
38890let hasNewValue = 1;
38891let opNewValue = 0;
38892let AsmVariantName = "NonParsable";
38893let isPseudo = 1;
38894}
38895def dup_A2_zxth : HInst<
38896(outs IntRegs:$Rd32),
38897(ins IntRegs:$Rs32),
38898"$Rd32 = zxth($Rs32)",
38899tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> {
38900let hasNewValue = 1;
38901let opNewValue = 0;
38902let AsmVariantName = "NonParsable";
38903let isPseudo = 1;
38904}
38905def dup_A4_combineii : HInst<
38906(outs DoubleRegs:$Rdd32),
38907(ins s8_0Imm:$Ii, u32_0Imm:$II),
38908"$Rdd32 = combine(#$Ii,#$II)",
38909tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
38910let AsmVariantName = "NonParsable";
38911let isPseudo = 1;
38912let isExtendable = 1;
38913let opExtendable = 2;
38914let isExtentSigned = 0;
38915let opExtentBits = 6;
38916let opExtentAlign = 0;
38917}
38918def dup_A4_combineir : HInst<
38919(outs DoubleRegs:$Rdd32),
38920(ins s32_0Imm:$Ii, IntRegs:$Rs32),
38921"$Rdd32 = combine(#$Ii,$Rs32)",
38922tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
38923let AsmVariantName = "NonParsable";
38924let isPseudo = 1;
38925let isExtendable = 1;
38926let opExtendable = 1;
38927let isExtentSigned = 1;
38928let opExtentBits = 8;
38929let opExtentAlign = 0;
38930}
38931def dup_A4_combineri : HInst<
38932(outs DoubleRegs:$Rdd32),
38933(ins IntRegs:$Rs32, s32_0Imm:$Ii),
38934"$Rdd32 = combine($Rs32,#$Ii)",
38935tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
38936let AsmVariantName = "NonParsable";
38937let isPseudo = 1;
38938let isExtendable = 1;
38939let opExtendable = 2;
38940let isExtentSigned = 1;
38941let opExtentBits = 8;
38942let opExtentAlign = 0;
38943}
38944def dup_C2_cmoveif : HInst<
38945(outs IntRegs:$Rd32),
38946(ins PredRegs:$Pu4, s32_0Imm:$Ii),
38947"if (!$Pu4) $Rd32 = #$Ii",
38948tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
38949let isPredicated = 1;
38950let isPredicatedFalse = 1;
38951let hasNewValue = 1;
38952let opNewValue = 0;
38953let AsmVariantName = "NonParsable";
38954let isPseudo = 1;
38955let isExtendable = 1;
38956let opExtendable = 2;
38957let isExtentSigned = 1;
38958let opExtentBits = 12;
38959let opExtentAlign = 0;
38960}
38961def dup_C2_cmoveit : HInst<
38962(outs IntRegs:$Rd32),
38963(ins PredRegs:$Pu4, s32_0Imm:$Ii),
38964"if ($Pu4) $Rd32 = #$Ii",
38965tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
38966let isPredicated = 1;
38967let hasNewValue = 1;
38968let opNewValue = 0;
38969let AsmVariantName = "NonParsable";
38970let isPseudo = 1;
38971let isExtendable = 1;
38972let opExtendable = 2;
38973let isExtentSigned = 1;
38974let opExtentBits = 12;
38975let opExtentAlign = 0;
38976}
38977def dup_C2_cmovenewif : HInst<
38978(outs IntRegs:$Rd32),
38979(ins PredRegs:$Pu4, s32_0Imm:$Ii),
38980"if (!$Pu4.new) $Rd32 = #$Ii",
38981tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> {
38982let isPredicated = 1;
38983let isPredicatedFalse = 1;
38984let hasNewValue = 1;
38985let opNewValue = 0;
38986let AsmVariantName = "NonParsable";
38987let isPredicatedNew = 1;
38988let isPseudo = 1;
38989let isExtendable = 1;
38990let opExtendable = 2;
38991let isExtentSigned = 1;
38992let opExtentBits = 12;
38993let opExtentAlign = 0;
38994}
38995def dup_C2_cmovenewit : HInst<
38996(outs IntRegs:$Rd32),
38997(ins PredRegs:$Pu4, s32_0Imm:$Ii),
38998"if ($Pu4.new) $Rd32 = #$Ii",
38999tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> {
39000let isPredicated = 1;
39001let hasNewValue = 1;
39002let opNewValue = 0;
39003let AsmVariantName = "NonParsable";
39004let isPredicatedNew = 1;
39005let isPseudo = 1;
39006let isExtendable = 1;
39007let opExtendable = 2;
39008let isExtentSigned = 1;
39009let opExtentBits = 12;
39010let opExtentAlign = 0;
39011}
39012def dup_C2_cmpeqi : HInst<
39013(outs PredRegs:$Pd4),
39014(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39015"$Pd4 = cmp.eq($Rs32,#$Ii)",
39016tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> {
39017let AsmVariantName = "NonParsable";
39018let isPseudo = 1;
39019let isExtendable = 1;
39020let opExtendable = 2;
39021let isExtentSigned = 1;
39022let opExtentBits = 10;
39023let opExtentAlign = 0;
39024}
39025def dup_L2_deallocframe : HInst<
39026(outs DoubleRegs:$Rdd32),
39027(ins IntRegs:$Rs32),
39028"$Rdd32 = deallocframe($Rs32):raw",
39029tc_aee6250c, TypeLD>, Requires<[HasV67]> {
39030let accessSize = DoubleWordAccess;
39031let AsmVariantName = "NonParsable";
39032let mayLoad = 1;
39033let Uses = [FRAMEKEY];
39034let Defs = [R29];
39035let isPseudo = 1;
39036}
39037def dup_L2_loadrb_io : HInst<
39038(outs IntRegs:$Rd32),
39039(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39040"$Rd32 = memb($Rs32+#$Ii)",
39041tc_eed07714, TypeLD>, Requires<[HasV67]> {
39042let hasNewValue = 1;
39043let opNewValue = 0;
39044let addrMode = BaseImmOffset;
39045let accessSize = ByteAccess;
39046let AsmVariantName = "NonParsable";
39047let mayLoad = 1;
39048let isPseudo = 1;
39049let isExtendable = 1;
39050let opExtendable = 2;
39051let isExtentSigned = 1;
39052let opExtentBits = 11;
39053let opExtentAlign = 0;
39054}
39055def dup_L2_loadrd_io : HInst<
39056(outs DoubleRegs:$Rdd32),
39057(ins IntRegs:$Rs32, s29_3Imm:$Ii),
39058"$Rdd32 = memd($Rs32+#$Ii)",
39059tc_eed07714, TypeLD>, Requires<[HasV67]> {
39060let addrMode = BaseImmOffset;
39061let accessSize = DoubleWordAccess;
39062let AsmVariantName = "NonParsable";
39063let mayLoad = 1;
39064let isPseudo = 1;
39065let isExtendable = 1;
39066let opExtendable = 2;
39067let isExtentSigned = 1;
39068let opExtentBits = 14;
39069let opExtentAlign = 3;
39070}
39071def dup_L2_loadrh_io : HInst<
39072(outs IntRegs:$Rd32),
39073(ins IntRegs:$Rs32, s31_1Imm:$Ii),
39074"$Rd32 = memh($Rs32+#$Ii)",
39075tc_eed07714, TypeLD>, Requires<[HasV67]> {
39076let hasNewValue = 1;
39077let opNewValue = 0;
39078let addrMode = BaseImmOffset;
39079let accessSize = HalfWordAccess;
39080let AsmVariantName = "NonParsable";
39081let mayLoad = 1;
39082let isPseudo = 1;
39083let isExtendable = 1;
39084let opExtendable = 2;
39085let isExtentSigned = 1;
39086let opExtentBits = 12;
39087let opExtentAlign = 1;
39088}
39089def dup_L2_loadri_io : HInst<
39090(outs IntRegs:$Rd32),
39091(ins IntRegs:$Rs32, s30_2Imm:$Ii),
39092"$Rd32 = memw($Rs32+#$Ii)",
39093tc_eed07714, TypeLD>, Requires<[HasV67]> {
39094let hasNewValue = 1;
39095let opNewValue = 0;
39096let addrMode = BaseImmOffset;
39097let accessSize = WordAccess;
39098let AsmVariantName = "NonParsable";
39099let mayLoad = 1;
39100let isPseudo = 1;
39101let isExtendable = 1;
39102let opExtendable = 2;
39103let isExtentSigned = 1;
39104let opExtentBits = 13;
39105let opExtentAlign = 2;
39106}
39107def dup_L2_loadrub_io : HInst<
39108(outs IntRegs:$Rd32),
39109(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39110"$Rd32 = memub($Rs32+#$Ii)",
39111tc_eed07714, TypeLD>, Requires<[HasV67]> {
39112let hasNewValue = 1;
39113let opNewValue = 0;
39114let addrMode = BaseImmOffset;
39115let accessSize = ByteAccess;
39116let AsmVariantName = "NonParsable";
39117let mayLoad = 1;
39118let isPseudo = 1;
39119let isExtendable = 1;
39120let opExtendable = 2;
39121let isExtentSigned = 1;
39122let opExtentBits = 11;
39123let opExtentAlign = 0;
39124}
39125def dup_L2_loadruh_io : HInst<
39126(outs IntRegs:$Rd32),
39127(ins IntRegs:$Rs32, s31_1Imm:$Ii),
39128"$Rd32 = memuh($Rs32+#$Ii)",
39129tc_eed07714, TypeLD>, Requires<[HasV67]> {
39130let hasNewValue = 1;
39131let opNewValue = 0;
39132let addrMode = BaseImmOffset;
39133let accessSize = HalfWordAccess;
39134let AsmVariantName = "NonParsable";
39135let mayLoad = 1;
39136let isPseudo = 1;
39137let isExtendable = 1;
39138let opExtendable = 2;
39139let isExtentSigned = 1;
39140let opExtentBits = 12;
39141let opExtentAlign = 1;
39142}
39143def dup_S2_allocframe : HInst<
39144(outs IntRegs:$Rx32),
39145(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
39146"allocframe($Rx32,#$Ii):raw",
39147tc_74a42bda, TypeST>, Requires<[HasV67]> {
39148let hasNewValue = 1;
39149let opNewValue = 0;
39150let addrMode = BaseImmOffset;
39151let accessSize = DoubleWordAccess;
39152let AsmVariantName = "NonParsable";
39153let mayStore = 1;
39154let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
39155let Defs = [R30];
39156let isPseudo = 1;
39157let Constraints = "$Rx32 = $Rx32in";
39158}
39159def dup_S2_storerb_io : HInst<
39160(outs),
39161(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
39162"memb($Rs32+#$Ii) = $Rt32",
39163tc_a9edeffa, TypeST>, Requires<[HasV67]> {
39164let addrMode = BaseImmOffset;
39165let accessSize = ByteAccess;
39166let AsmVariantName = "NonParsable";
39167let mayStore = 1;
39168let isPseudo = 1;
39169let isExtendable = 1;
39170let opExtendable = 1;
39171let isExtentSigned = 1;
39172let opExtentBits = 11;
39173let opExtentAlign = 0;
39174}
39175def dup_S2_storerd_io : HInst<
39176(outs),
39177(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
39178"memd($Rs32+#$Ii) = $Rtt32",
39179tc_a9edeffa, TypeST>, Requires<[HasV67]> {
39180let addrMode = BaseImmOffset;
39181let accessSize = DoubleWordAccess;
39182let AsmVariantName = "NonParsable";
39183let mayStore = 1;
39184let isPseudo = 1;
39185let isExtendable = 1;
39186let opExtendable = 1;
39187let isExtentSigned = 1;
39188let opExtentBits = 14;
39189let opExtentAlign = 3;
39190}
39191def dup_S2_storerh_io : HInst<
39192(outs),
39193(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
39194"memh($Rs32+#$Ii) = $Rt32",
39195tc_a9edeffa, TypeST>, Requires<[HasV67]> {
39196let addrMode = BaseImmOffset;
39197let accessSize = HalfWordAccess;
39198let AsmVariantName = "NonParsable";
39199let mayStore = 1;
39200let isPseudo = 1;
39201let isExtendable = 1;
39202let opExtendable = 1;
39203let isExtentSigned = 1;
39204let opExtentBits = 12;
39205let opExtentAlign = 1;
39206}
39207def dup_S2_storeri_io : HInst<
39208(outs),
39209(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
39210"memw($Rs32+#$Ii) = $Rt32",
39211tc_a9edeffa, TypeST>, Requires<[HasV67]> {
39212let addrMode = BaseImmOffset;
39213let accessSize = WordAccess;
39214let AsmVariantName = "NonParsable";
39215let mayStore = 1;
39216let isPseudo = 1;
39217let isExtendable = 1;
39218let opExtendable = 1;
39219let isExtentSigned = 1;
39220let opExtentBits = 13;
39221let opExtentAlign = 2;
39222}
39223def dup_S4_storeirb_io : HInst<
39224(outs),
39225(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
39226"memb($Rs32+#$Ii) = #$II",
39227tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> {
39228let addrMode = BaseImmOffset;
39229let accessSize = ByteAccess;
39230let AsmVariantName = "NonParsable";
39231let mayStore = 1;
39232let isPseudo = 1;
39233let isExtendable = 1;
39234let opExtendable = 2;
39235let isExtentSigned = 1;
39236let opExtentBits = 8;
39237let opExtentAlign = 0;
39238}
39239def dup_S4_storeiri_io : HInst<
39240(outs),
39241(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
39242"memw($Rs32+#$Ii) = #$II",
39243tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> {
39244let addrMode = BaseImmOffset;
39245let accessSize = WordAccess;
39246let AsmVariantName = "NonParsable";
39247let mayStore = 1;
39248let isPseudo = 1;
39249let isExtendable = 1;
39250let opExtendable = 2;
39251let isExtentSigned = 1;
39252let opExtentBits = 8;
39253let opExtentAlign = 0;
39254}
39255