xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (revision 6f63e88c0166ed3e5f2805a9e667c7d24d304cf1) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, please consult code owner before editing.
9//===----------------------------------------------------------------------===//
10
11def A2_abs : HInst<
12(outs IntRegs:$Rd32),
13(ins IntRegs:$Rs32),
14"$Rd32 = abs($Rs32)",
15tc_cf8126ae, TypeS_2op>, Enc_5e2823 {
16let Inst{13-5} = 0b000000100;
17let Inst{31-21} = 0b10001100100;
18let hasNewValue = 1;
19let opNewValue = 0;
20let prefersSlot3 = 1;
21}
22def A2_absp : HInst<
23(outs DoubleRegs:$Rdd32),
24(ins DoubleRegs:$Rss32),
25"$Rdd32 = abs($Rss32)",
26tc_cf8126ae, TypeS_2op>, Enc_b9c5fb {
27let Inst{13-5} = 0b000000110;
28let Inst{31-21} = 0b10000000100;
29let prefersSlot3 = 1;
30}
31def A2_abssat : HInst<
32(outs IntRegs:$Rd32),
33(ins IntRegs:$Rs32),
34"$Rd32 = abs($Rs32):sat",
35tc_cf8126ae, TypeS_2op>, Enc_5e2823 {
36let Inst{13-5} = 0b000000101;
37let Inst{31-21} = 0b10001100100;
38let hasNewValue = 1;
39let opNewValue = 0;
40let prefersSlot3 = 1;
41let Defs = [USR_OVF];
42}
43def A2_add : HInst<
44(outs IntRegs:$Rd32),
45(ins IntRegs:$Rs32, IntRegs:$Rt32),
46"$Rd32 = add($Rs32,$Rt32)",
47tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
48let Inst{7-5} = 0b000;
49let Inst{13-13} = 0b0;
50let Inst{31-21} = 0b11110011000;
51let hasNewValue = 1;
52let opNewValue = 0;
53let CextOpcode = "A2_add";
54let InputType = "reg";
55let BaseOpcode = "A2_add";
56let isCommutable = 1;
57let isPredicable = 1;
58}
59def A2_addh_h16_hh : HInst<
60(outs IntRegs:$Rd32),
61(ins IntRegs:$Rt32, IntRegs:$Rs32),
62"$Rd32 = add($Rt32.h,$Rs32.h):<<16",
63tc_679309b8, TypeALU64>, Enc_bd6011 {
64let Inst{7-5} = 0b011;
65let Inst{13-13} = 0b0;
66let Inst{31-21} = 0b11010101010;
67let hasNewValue = 1;
68let opNewValue = 0;
69let prefersSlot3 = 1;
70}
71def A2_addh_h16_hl : HInst<
72(outs IntRegs:$Rd32),
73(ins IntRegs:$Rt32, IntRegs:$Rs32),
74"$Rd32 = add($Rt32.h,$Rs32.l):<<16",
75tc_679309b8, TypeALU64>, Enc_bd6011 {
76let Inst{7-5} = 0b010;
77let Inst{13-13} = 0b0;
78let Inst{31-21} = 0b11010101010;
79let hasNewValue = 1;
80let opNewValue = 0;
81let prefersSlot3 = 1;
82}
83def A2_addh_h16_lh : HInst<
84(outs IntRegs:$Rd32),
85(ins IntRegs:$Rt32, IntRegs:$Rs32),
86"$Rd32 = add($Rt32.l,$Rs32.h):<<16",
87tc_679309b8, TypeALU64>, Enc_bd6011 {
88let Inst{7-5} = 0b001;
89let Inst{13-13} = 0b0;
90let Inst{31-21} = 0b11010101010;
91let hasNewValue = 1;
92let opNewValue = 0;
93let prefersSlot3 = 1;
94}
95def A2_addh_h16_ll : HInst<
96(outs IntRegs:$Rd32),
97(ins IntRegs:$Rt32, IntRegs:$Rs32),
98"$Rd32 = add($Rt32.l,$Rs32.l):<<16",
99tc_679309b8, TypeALU64>, Enc_bd6011 {
100let Inst{7-5} = 0b000;
101let Inst{13-13} = 0b0;
102let Inst{31-21} = 0b11010101010;
103let hasNewValue = 1;
104let opNewValue = 0;
105let prefersSlot3 = 1;
106}
107def A2_addh_h16_sat_hh : HInst<
108(outs IntRegs:$Rd32),
109(ins IntRegs:$Rt32, IntRegs:$Rs32),
110"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
111tc_779080bf, TypeALU64>, Enc_bd6011 {
112let Inst{7-5} = 0b111;
113let Inst{13-13} = 0b0;
114let Inst{31-21} = 0b11010101010;
115let hasNewValue = 1;
116let opNewValue = 0;
117let prefersSlot3 = 1;
118let Defs = [USR_OVF];
119}
120def A2_addh_h16_sat_hl : HInst<
121(outs IntRegs:$Rd32),
122(ins IntRegs:$Rt32, IntRegs:$Rs32),
123"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
124tc_779080bf, TypeALU64>, Enc_bd6011 {
125let Inst{7-5} = 0b110;
126let Inst{13-13} = 0b0;
127let Inst{31-21} = 0b11010101010;
128let hasNewValue = 1;
129let opNewValue = 0;
130let prefersSlot3 = 1;
131let Defs = [USR_OVF];
132}
133def A2_addh_h16_sat_lh : HInst<
134(outs IntRegs:$Rd32),
135(ins IntRegs:$Rt32, IntRegs:$Rs32),
136"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
137tc_779080bf, TypeALU64>, Enc_bd6011 {
138let Inst{7-5} = 0b101;
139let Inst{13-13} = 0b0;
140let Inst{31-21} = 0b11010101010;
141let hasNewValue = 1;
142let opNewValue = 0;
143let prefersSlot3 = 1;
144let Defs = [USR_OVF];
145}
146def A2_addh_h16_sat_ll : HInst<
147(outs IntRegs:$Rd32),
148(ins IntRegs:$Rt32, IntRegs:$Rs32),
149"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
150tc_779080bf, TypeALU64>, Enc_bd6011 {
151let Inst{7-5} = 0b100;
152let Inst{13-13} = 0b0;
153let Inst{31-21} = 0b11010101010;
154let hasNewValue = 1;
155let opNewValue = 0;
156let prefersSlot3 = 1;
157let Defs = [USR_OVF];
158}
159def A2_addh_l16_hl : HInst<
160(outs IntRegs:$Rd32),
161(ins IntRegs:$Rt32, IntRegs:$Rs32),
162"$Rd32 = add($Rt32.l,$Rs32.h)",
163tc_4414d8b1, TypeALU64>, Enc_bd6011 {
164let Inst{7-5} = 0b010;
165let Inst{13-13} = 0b0;
166let Inst{31-21} = 0b11010101000;
167let hasNewValue = 1;
168let opNewValue = 0;
169let prefersSlot3 = 1;
170}
171def A2_addh_l16_ll : HInst<
172(outs IntRegs:$Rd32),
173(ins IntRegs:$Rt32, IntRegs:$Rs32),
174"$Rd32 = add($Rt32.l,$Rs32.l)",
175tc_4414d8b1, TypeALU64>, Enc_bd6011 {
176let Inst{7-5} = 0b000;
177let Inst{13-13} = 0b0;
178let Inst{31-21} = 0b11010101000;
179let hasNewValue = 1;
180let opNewValue = 0;
181let prefersSlot3 = 1;
182}
183def A2_addh_l16_sat_hl : HInst<
184(outs IntRegs:$Rd32),
185(ins IntRegs:$Rt32, IntRegs:$Rs32),
186"$Rd32 = add($Rt32.l,$Rs32.h):sat",
187tc_779080bf, TypeALU64>, Enc_bd6011 {
188let Inst{7-5} = 0b110;
189let Inst{13-13} = 0b0;
190let Inst{31-21} = 0b11010101000;
191let hasNewValue = 1;
192let opNewValue = 0;
193let prefersSlot3 = 1;
194let Defs = [USR_OVF];
195}
196def A2_addh_l16_sat_ll : HInst<
197(outs IntRegs:$Rd32),
198(ins IntRegs:$Rt32, IntRegs:$Rs32),
199"$Rd32 = add($Rt32.l,$Rs32.l):sat",
200tc_779080bf, TypeALU64>, Enc_bd6011 {
201let Inst{7-5} = 0b100;
202let Inst{13-13} = 0b0;
203let Inst{31-21} = 0b11010101000;
204let hasNewValue = 1;
205let opNewValue = 0;
206let prefersSlot3 = 1;
207let Defs = [USR_OVF];
208}
209def A2_addi : HInst<
210(outs IntRegs:$Rd32),
211(ins IntRegs:$Rs32, s32_0Imm:$Ii),
212"$Rd32 = add($Rs32,#$Ii)",
213tc_5a2711e5, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
214let Inst{31-28} = 0b1011;
215let hasNewValue = 1;
216let opNewValue = 0;
217let CextOpcode = "A2_add";
218let InputType = "imm";
219let BaseOpcode = "A2_addi";
220let isPredicable = 1;
221let isAdd = 1;
222let isExtendable = 1;
223let opExtendable = 2;
224let isExtentSigned = 1;
225let opExtentBits = 16;
226let opExtentAlign = 0;
227}
228def A2_addp : HInst<
229(outs DoubleRegs:$Rdd32),
230(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
231"$Rdd32 = add($Rss32,$Rtt32)",
232tc_946df596, TypeALU64>, Enc_a56825 {
233let Inst{7-5} = 0b111;
234let Inst{13-13} = 0b0;
235let Inst{31-21} = 0b11010011000;
236let isCommutable = 1;
237let isAdd = 1;
238}
239def A2_addpsat : HInst<
240(outs DoubleRegs:$Rdd32),
241(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
242"$Rdd32 = add($Rss32,$Rtt32):sat",
243tc_779080bf, TypeALU64>, Enc_a56825 {
244let Inst{7-5} = 0b101;
245let Inst{13-13} = 0b0;
246let Inst{31-21} = 0b11010011011;
247let prefersSlot3 = 1;
248let Defs = [USR_OVF];
249let isCommutable = 1;
250}
251def A2_addsat : HInst<
252(outs IntRegs:$Rd32),
253(ins IntRegs:$Rs32, IntRegs:$Rt32),
254"$Rd32 = add($Rs32,$Rt32):sat",
255tc_61830035, TypeALU32_3op>, Enc_5ab2be {
256let Inst{7-5} = 0b000;
257let Inst{13-13} = 0b0;
258let Inst{31-21} = 0b11110110010;
259let hasNewValue = 1;
260let opNewValue = 0;
261let prefersSlot3 = 1;
262let Defs = [USR_OVF];
263let InputType = "reg";
264let isCommutable = 1;
265}
266def A2_addsp : HInst<
267(outs DoubleRegs:$Rdd32),
268(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
269"$Rdd32 = add($Rs32,$Rtt32)",
270tc_679309b8, TypeALU64> {
271let isPseudo = 1;
272}
273def A2_addsph : HInst<
274(outs DoubleRegs:$Rdd32),
275(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
276"$Rdd32 = add($Rss32,$Rtt32):raw:hi",
277tc_679309b8, TypeALU64>, Enc_a56825 {
278let Inst{7-5} = 0b111;
279let Inst{13-13} = 0b0;
280let Inst{31-21} = 0b11010011011;
281let prefersSlot3 = 1;
282}
283def A2_addspl : HInst<
284(outs DoubleRegs:$Rdd32),
285(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
286"$Rdd32 = add($Rss32,$Rtt32):raw:lo",
287tc_679309b8, TypeALU64>, Enc_a56825 {
288let Inst{7-5} = 0b110;
289let Inst{13-13} = 0b0;
290let Inst{31-21} = 0b11010011011;
291let prefersSlot3 = 1;
292}
293def A2_and : HInst<
294(outs IntRegs:$Rd32),
295(ins IntRegs:$Rs32, IntRegs:$Rt32),
296"$Rd32 = and($Rs32,$Rt32)",
297tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
298let Inst{7-5} = 0b000;
299let Inst{13-13} = 0b0;
300let Inst{31-21} = 0b11110001000;
301let hasNewValue = 1;
302let opNewValue = 0;
303let CextOpcode = "A2_and";
304let InputType = "reg";
305let BaseOpcode = "A2_and";
306let isCommutable = 1;
307let isPredicable = 1;
308}
309def A2_andir : HInst<
310(outs IntRegs:$Rd32),
311(ins IntRegs:$Rs32, s32_0Imm:$Ii),
312"$Rd32 = and($Rs32,#$Ii)",
313tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel {
314let Inst{31-22} = 0b0111011000;
315let hasNewValue = 1;
316let opNewValue = 0;
317let CextOpcode = "A2_and";
318let InputType = "imm";
319let isExtendable = 1;
320let opExtendable = 2;
321let isExtentSigned = 1;
322let opExtentBits = 10;
323let opExtentAlign = 0;
324}
325def A2_andp : HInst<
326(outs DoubleRegs:$Rdd32),
327(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
328"$Rdd32 = and($Rss32,$Rtt32)",
329tc_946df596, TypeALU64>, Enc_a56825 {
330let Inst{7-5} = 0b000;
331let Inst{13-13} = 0b0;
332let Inst{31-21} = 0b11010011111;
333let isCommutable = 1;
334}
335def A2_aslh : HInst<
336(outs IntRegs:$Rd32),
337(ins IntRegs:$Rs32),
338"$Rd32 = aslh($Rs32)",
339tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel {
340let Inst{13-5} = 0b000000000;
341let Inst{31-21} = 0b01110000000;
342let hasNewValue = 1;
343let opNewValue = 0;
344let BaseOpcode = "A2_aslh";
345let isPredicable = 1;
346}
347def A2_asrh : HInst<
348(outs IntRegs:$Rd32),
349(ins IntRegs:$Rs32),
350"$Rd32 = asrh($Rs32)",
351tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel {
352let Inst{13-5} = 0b000000000;
353let Inst{31-21} = 0b01110000001;
354let hasNewValue = 1;
355let opNewValue = 0;
356let BaseOpcode = "A2_asrh";
357let isPredicable = 1;
358}
359def A2_combine_hh : HInst<
360(outs IntRegs:$Rd32),
361(ins IntRegs:$Rt32, IntRegs:$Rs32),
362"$Rd32 = combine($Rt32.h,$Rs32.h)",
363tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 {
364let Inst{7-5} = 0b000;
365let Inst{13-13} = 0b0;
366let Inst{31-21} = 0b11110011100;
367let hasNewValue = 1;
368let opNewValue = 0;
369let InputType = "reg";
370}
371def A2_combine_hl : HInst<
372(outs IntRegs:$Rd32),
373(ins IntRegs:$Rt32, IntRegs:$Rs32),
374"$Rd32 = combine($Rt32.h,$Rs32.l)",
375tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 {
376let Inst{7-5} = 0b000;
377let Inst{13-13} = 0b0;
378let Inst{31-21} = 0b11110011101;
379let hasNewValue = 1;
380let opNewValue = 0;
381let InputType = "reg";
382}
383def A2_combine_lh : HInst<
384(outs IntRegs:$Rd32),
385(ins IntRegs:$Rt32, IntRegs:$Rs32),
386"$Rd32 = combine($Rt32.l,$Rs32.h)",
387tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 {
388let Inst{7-5} = 0b000;
389let Inst{13-13} = 0b0;
390let Inst{31-21} = 0b11110011110;
391let hasNewValue = 1;
392let opNewValue = 0;
393let InputType = "reg";
394}
395def A2_combine_ll : HInst<
396(outs IntRegs:$Rd32),
397(ins IntRegs:$Rt32, IntRegs:$Rs32),
398"$Rd32 = combine($Rt32.l,$Rs32.l)",
399tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 {
400let Inst{7-5} = 0b000;
401let Inst{13-13} = 0b0;
402let Inst{31-21} = 0b11110011111;
403let hasNewValue = 1;
404let opNewValue = 0;
405let InputType = "reg";
406}
407def A2_combineii : HInst<
408(outs DoubleRegs:$Rdd32),
409(ins s32_0Imm:$Ii, s8_0Imm:$II),
410"$Rdd32 = combine(#$Ii,#$II)",
411tc_5a2711e5, TypeALU32_2op>, Enc_18c338 {
412let Inst{31-23} = 0b011111000;
413let isReMaterializable = 1;
414let isAsCheapAsAMove = 1;
415let isMoveImm = 1;
416let isExtendable = 1;
417let opExtendable = 1;
418let isExtentSigned = 1;
419let opExtentBits = 8;
420let opExtentAlign = 0;
421}
422def A2_combinew : HInst<
423(outs DoubleRegs:$Rdd32),
424(ins IntRegs:$Rs32, IntRegs:$Rt32),
425"$Rdd32 = combine($Rs32,$Rt32)",
426tc_5a2711e5, TypeALU32_3op>, Enc_be32a5, PredNewRel {
427let Inst{7-5} = 0b000;
428let Inst{13-13} = 0b0;
429let Inst{31-21} = 0b11110101000;
430let InputType = "reg";
431let BaseOpcode = "A2_combinew";
432let isPredicable = 1;
433}
434def A2_max : HInst<
435(outs IntRegs:$Rd32),
436(ins IntRegs:$Rs32, IntRegs:$Rt32),
437"$Rd32 = max($Rs32,$Rt32)",
438tc_779080bf, TypeALU64>, Enc_5ab2be {
439let Inst{7-5} = 0b000;
440let Inst{13-13} = 0b0;
441let Inst{31-21} = 0b11010101110;
442let hasNewValue = 1;
443let opNewValue = 0;
444let prefersSlot3 = 1;
445}
446def A2_maxp : HInst<
447(outs DoubleRegs:$Rdd32),
448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
449"$Rdd32 = max($Rss32,$Rtt32)",
450tc_779080bf, TypeALU64>, Enc_a56825 {
451let Inst{7-5} = 0b100;
452let Inst{13-13} = 0b0;
453let Inst{31-21} = 0b11010011110;
454let prefersSlot3 = 1;
455}
456def A2_maxu : HInst<
457(outs IntRegs:$Rd32),
458(ins IntRegs:$Rs32, IntRegs:$Rt32),
459"$Rd32 = maxu($Rs32,$Rt32)",
460tc_779080bf, TypeALU64>, Enc_5ab2be {
461let Inst{7-5} = 0b100;
462let Inst{13-13} = 0b0;
463let Inst{31-21} = 0b11010101110;
464let hasNewValue = 1;
465let opNewValue = 0;
466let prefersSlot3 = 1;
467}
468def A2_maxup : HInst<
469(outs DoubleRegs:$Rdd32),
470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
471"$Rdd32 = maxu($Rss32,$Rtt32)",
472tc_779080bf, TypeALU64>, Enc_a56825 {
473let Inst{7-5} = 0b101;
474let Inst{13-13} = 0b0;
475let Inst{31-21} = 0b11010011110;
476let prefersSlot3 = 1;
477}
478def A2_min : HInst<
479(outs IntRegs:$Rd32),
480(ins IntRegs:$Rt32, IntRegs:$Rs32),
481"$Rd32 = min($Rt32,$Rs32)",
482tc_779080bf, TypeALU64>, Enc_bd6011 {
483let Inst{7-5} = 0b000;
484let Inst{13-13} = 0b0;
485let Inst{31-21} = 0b11010101101;
486let hasNewValue = 1;
487let opNewValue = 0;
488let prefersSlot3 = 1;
489}
490def A2_minp : HInst<
491(outs DoubleRegs:$Rdd32),
492(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
493"$Rdd32 = min($Rtt32,$Rss32)",
494tc_779080bf, TypeALU64>, Enc_ea23e4 {
495let Inst{7-5} = 0b110;
496let Inst{13-13} = 0b0;
497let Inst{31-21} = 0b11010011101;
498let prefersSlot3 = 1;
499}
500def A2_minu : HInst<
501(outs IntRegs:$Rd32),
502(ins IntRegs:$Rt32, IntRegs:$Rs32),
503"$Rd32 = minu($Rt32,$Rs32)",
504tc_779080bf, TypeALU64>, Enc_bd6011 {
505let Inst{7-5} = 0b100;
506let Inst{13-13} = 0b0;
507let Inst{31-21} = 0b11010101101;
508let hasNewValue = 1;
509let opNewValue = 0;
510let prefersSlot3 = 1;
511}
512def A2_minup : HInst<
513(outs DoubleRegs:$Rdd32),
514(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
515"$Rdd32 = minu($Rtt32,$Rss32)",
516tc_779080bf, TypeALU64>, Enc_ea23e4 {
517let Inst{7-5} = 0b111;
518let Inst{13-13} = 0b0;
519let Inst{31-21} = 0b11010011101;
520let prefersSlot3 = 1;
521}
522def A2_neg : HInst<
523(outs IntRegs:$Rd32),
524(ins IntRegs:$Rs32),
525"$Rd32 = neg($Rs32)",
526tc_57890846, TypeALU32_2op> {
527let hasNewValue = 1;
528let opNewValue = 0;
529let isPseudo = 1;
530let isCodeGenOnly = 1;
531}
532def A2_negp : HInst<
533(outs DoubleRegs:$Rdd32),
534(ins DoubleRegs:$Rss32),
535"$Rdd32 = neg($Rss32)",
536tc_0ae0825c, TypeS_2op>, Enc_b9c5fb {
537let Inst{13-5} = 0b000000101;
538let Inst{31-21} = 0b10000000100;
539}
540def A2_negsat : HInst<
541(outs IntRegs:$Rd32),
542(ins IntRegs:$Rs32),
543"$Rd32 = neg($Rs32):sat",
544tc_cf8126ae, TypeS_2op>, Enc_5e2823 {
545let Inst{13-5} = 0b000000110;
546let Inst{31-21} = 0b10001100100;
547let hasNewValue = 1;
548let opNewValue = 0;
549let prefersSlot3 = 1;
550let Defs = [USR_OVF];
551}
552def A2_nop : HInst<
553(outs),
554(ins),
555"nop",
556tc_2eabeebe, TypeALU32_2op>, Enc_e3b0c4 {
557let Inst{13-0} = 0b00000000000000;
558let Inst{31-16} = 0b0111111100000000;
559}
560def A2_not : HInst<
561(outs IntRegs:$Rd32),
562(ins IntRegs:$Rs32),
563"$Rd32 = not($Rs32)",
564tc_57890846, TypeALU32_2op> {
565let hasNewValue = 1;
566let opNewValue = 0;
567let isPseudo = 1;
568let isCodeGenOnly = 1;
569}
570def A2_notp : HInst<
571(outs DoubleRegs:$Rdd32),
572(ins DoubleRegs:$Rss32),
573"$Rdd32 = not($Rss32)",
574tc_0ae0825c, TypeS_2op>, Enc_b9c5fb {
575let Inst{13-5} = 0b000000100;
576let Inst{31-21} = 0b10000000100;
577}
578def A2_or : HInst<
579(outs IntRegs:$Rd32),
580(ins IntRegs:$Rs32, IntRegs:$Rt32),
581"$Rd32 = or($Rs32,$Rt32)",
582tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
583let Inst{7-5} = 0b000;
584let Inst{13-13} = 0b0;
585let Inst{31-21} = 0b11110001001;
586let hasNewValue = 1;
587let opNewValue = 0;
588let CextOpcode = "A2_or";
589let InputType = "reg";
590let BaseOpcode = "A2_or";
591let isCommutable = 1;
592let isPredicable = 1;
593}
594def A2_orir : HInst<
595(outs IntRegs:$Rd32),
596(ins IntRegs:$Rs32, s32_0Imm:$Ii),
597"$Rd32 = or($Rs32,#$Ii)",
598tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel {
599let Inst{31-22} = 0b0111011010;
600let hasNewValue = 1;
601let opNewValue = 0;
602let CextOpcode = "A2_or";
603let InputType = "imm";
604let isExtendable = 1;
605let opExtendable = 2;
606let isExtentSigned = 1;
607let opExtentBits = 10;
608let opExtentAlign = 0;
609}
610def A2_orp : HInst<
611(outs DoubleRegs:$Rdd32),
612(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
613"$Rdd32 = or($Rss32,$Rtt32)",
614tc_946df596, TypeALU64>, Enc_a56825 {
615let Inst{7-5} = 0b010;
616let Inst{13-13} = 0b0;
617let Inst{31-21} = 0b11010011111;
618let isCommutable = 1;
619}
620def A2_paddf : HInst<
621(outs IntRegs:$Rd32),
622(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
623"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
624tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
625let Inst{7-7} = 0b1;
626let Inst{13-13} = 0b0;
627let Inst{31-21} = 0b11111011000;
628let isPredicated = 1;
629let isPredicatedFalse = 1;
630let hasNewValue = 1;
631let opNewValue = 0;
632let CextOpcode = "A2_add";
633let InputType = "reg";
634let BaseOpcode = "A2_add";
635}
636def A2_paddfnew : HInst<
637(outs IntRegs:$Rd32),
638(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
639"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
640tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
641let Inst{7-7} = 0b1;
642let Inst{13-13} = 0b1;
643let Inst{31-21} = 0b11111011000;
644let isPredicated = 1;
645let isPredicatedFalse = 1;
646let hasNewValue = 1;
647let opNewValue = 0;
648let isPredicatedNew = 1;
649let CextOpcode = "A2_add";
650let InputType = "reg";
651let BaseOpcode = "A2_add";
652}
653def A2_paddif : HInst<
654(outs IntRegs:$Rd32),
655(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
656"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
657tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
658let Inst{13-13} = 0b0;
659let Inst{31-23} = 0b011101001;
660let isPredicated = 1;
661let isPredicatedFalse = 1;
662let hasNewValue = 1;
663let opNewValue = 0;
664let CextOpcode = "A2_add";
665let InputType = "imm";
666let BaseOpcode = "A2_addi";
667let isExtendable = 1;
668let opExtendable = 3;
669let isExtentSigned = 1;
670let opExtentBits = 8;
671let opExtentAlign = 0;
672}
673def A2_paddifnew : HInst<
674(outs IntRegs:$Rd32),
675(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
676"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
677tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
678let Inst{13-13} = 0b1;
679let Inst{31-23} = 0b011101001;
680let isPredicated = 1;
681let isPredicatedFalse = 1;
682let hasNewValue = 1;
683let opNewValue = 0;
684let isPredicatedNew = 1;
685let CextOpcode = "A2_add";
686let InputType = "imm";
687let BaseOpcode = "A2_addi";
688let isExtendable = 1;
689let opExtendable = 3;
690let isExtentSigned = 1;
691let opExtentBits = 8;
692let opExtentAlign = 0;
693}
694def A2_paddit : HInst<
695(outs IntRegs:$Rd32),
696(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
697"if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
698tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
699let Inst{13-13} = 0b0;
700let Inst{31-23} = 0b011101000;
701let isPredicated = 1;
702let hasNewValue = 1;
703let opNewValue = 0;
704let CextOpcode = "A2_add";
705let InputType = "imm";
706let BaseOpcode = "A2_addi";
707let isExtendable = 1;
708let opExtendable = 3;
709let isExtentSigned = 1;
710let opExtentBits = 8;
711let opExtentAlign = 0;
712}
713def A2_padditnew : HInst<
714(outs IntRegs:$Rd32),
715(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
716"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
717tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
718let Inst{13-13} = 0b1;
719let Inst{31-23} = 0b011101000;
720let isPredicated = 1;
721let hasNewValue = 1;
722let opNewValue = 0;
723let isPredicatedNew = 1;
724let CextOpcode = "A2_add";
725let InputType = "imm";
726let BaseOpcode = "A2_addi";
727let isExtendable = 1;
728let opExtendable = 3;
729let isExtentSigned = 1;
730let opExtentBits = 8;
731let opExtentAlign = 0;
732}
733def A2_paddt : HInst<
734(outs IntRegs:$Rd32),
735(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
736"if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
737tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
738let Inst{7-7} = 0b0;
739let Inst{13-13} = 0b0;
740let Inst{31-21} = 0b11111011000;
741let isPredicated = 1;
742let hasNewValue = 1;
743let opNewValue = 0;
744let CextOpcode = "A2_add";
745let InputType = "reg";
746let BaseOpcode = "A2_add";
747}
748def A2_paddtnew : HInst<
749(outs IntRegs:$Rd32),
750(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
751"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
752tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
753let Inst{7-7} = 0b0;
754let Inst{13-13} = 0b1;
755let Inst{31-21} = 0b11111011000;
756let isPredicated = 1;
757let hasNewValue = 1;
758let opNewValue = 0;
759let isPredicatedNew = 1;
760let CextOpcode = "A2_add";
761let InputType = "reg";
762let BaseOpcode = "A2_add";
763}
764def A2_pandf : HInst<
765(outs IntRegs:$Rd32),
766(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
767"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
768tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
769let Inst{7-7} = 0b1;
770let Inst{13-13} = 0b0;
771let Inst{31-21} = 0b11111001000;
772let isPredicated = 1;
773let isPredicatedFalse = 1;
774let hasNewValue = 1;
775let opNewValue = 0;
776let BaseOpcode = "A2_and";
777}
778def A2_pandfnew : HInst<
779(outs IntRegs:$Rd32),
780(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
781"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
782tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
783let Inst{7-7} = 0b1;
784let Inst{13-13} = 0b1;
785let Inst{31-21} = 0b11111001000;
786let isPredicated = 1;
787let isPredicatedFalse = 1;
788let hasNewValue = 1;
789let opNewValue = 0;
790let isPredicatedNew = 1;
791let BaseOpcode = "A2_and";
792}
793def A2_pandt : HInst<
794(outs IntRegs:$Rd32),
795(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
796"if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
797tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
798let Inst{7-7} = 0b0;
799let Inst{13-13} = 0b0;
800let Inst{31-21} = 0b11111001000;
801let isPredicated = 1;
802let hasNewValue = 1;
803let opNewValue = 0;
804let BaseOpcode = "A2_and";
805}
806def A2_pandtnew : HInst<
807(outs IntRegs:$Rd32),
808(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
809"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
810tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
811let Inst{7-7} = 0b0;
812let Inst{13-13} = 0b1;
813let Inst{31-21} = 0b11111001000;
814let isPredicated = 1;
815let hasNewValue = 1;
816let opNewValue = 0;
817let isPredicatedNew = 1;
818let BaseOpcode = "A2_and";
819}
820def A2_porf : HInst<
821(outs IntRegs:$Rd32),
822(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
823"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
824tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
825let Inst{7-7} = 0b1;
826let Inst{13-13} = 0b0;
827let Inst{31-21} = 0b11111001001;
828let isPredicated = 1;
829let isPredicatedFalse = 1;
830let hasNewValue = 1;
831let opNewValue = 0;
832let BaseOpcode = "A2_or";
833}
834def A2_porfnew : HInst<
835(outs IntRegs:$Rd32),
836(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
837"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
838tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
839let Inst{7-7} = 0b1;
840let Inst{13-13} = 0b1;
841let Inst{31-21} = 0b11111001001;
842let isPredicated = 1;
843let isPredicatedFalse = 1;
844let hasNewValue = 1;
845let opNewValue = 0;
846let isPredicatedNew = 1;
847let BaseOpcode = "A2_or";
848}
849def A2_port : HInst<
850(outs IntRegs:$Rd32),
851(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
852"if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
853tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
854let Inst{7-7} = 0b0;
855let Inst{13-13} = 0b0;
856let Inst{31-21} = 0b11111001001;
857let isPredicated = 1;
858let hasNewValue = 1;
859let opNewValue = 0;
860let BaseOpcode = "A2_or";
861}
862def A2_portnew : HInst<
863(outs IntRegs:$Rd32),
864(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
865"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
866tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
867let Inst{7-7} = 0b0;
868let Inst{13-13} = 0b1;
869let Inst{31-21} = 0b11111001001;
870let isPredicated = 1;
871let hasNewValue = 1;
872let opNewValue = 0;
873let isPredicatedNew = 1;
874let BaseOpcode = "A2_or";
875}
876def A2_psubf : HInst<
877(outs IntRegs:$Rd32),
878(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
879"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
880tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
881let Inst{7-7} = 0b1;
882let Inst{13-13} = 0b0;
883let Inst{31-21} = 0b11111011001;
884let isPredicated = 1;
885let isPredicatedFalse = 1;
886let hasNewValue = 1;
887let opNewValue = 0;
888let BaseOpcode = "A2_sub";
889}
890def A2_psubfnew : HInst<
891(outs IntRegs:$Rd32),
892(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
893"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
894tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
895let Inst{7-7} = 0b1;
896let Inst{13-13} = 0b1;
897let Inst{31-21} = 0b11111011001;
898let isPredicated = 1;
899let isPredicatedFalse = 1;
900let hasNewValue = 1;
901let opNewValue = 0;
902let isPredicatedNew = 1;
903let BaseOpcode = "A2_sub";
904}
905def A2_psubt : HInst<
906(outs IntRegs:$Rd32),
907(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
908"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
909tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
910let Inst{7-7} = 0b0;
911let Inst{13-13} = 0b0;
912let Inst{31-21} = 0b11111011001;
913let isPredicated = 1;
914let hasNewValue = 1;
915let opNewValue = 0;
916let BaseOpcode = "A2_sub";
917}
918def A2_psubtnew : HInst<
919(outs IntRegs:$Rd32),
920(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
921"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
922tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
923let Inst{7-7} = 0b0;
924let Inst{13-13} = 0b1;
925let Inst{31-21} = 0b11111011001;
926let isPredicated = 1;
927let hasNewValue = 1;
928let opNewValue = 0;
929let isPredicatedNew = 1;
930let BaseOpcode = "A2_sub";
931}
932def A2_pxorf : HInst<
933(outs IntRegs:$Rd32),
934(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
935"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
936tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
937let Inst{7-7} = 0b1;
938let Inst{13-13} = 0b0;
939let Inst{31-21} = 0b11111001011;
940let isPredicated = 1;
941let isPredicatedFalse = 1;
942let hasNewValue = 1;
943let opNewValue = 0;
944let BaseOpcode = "A2_xor";
945}
946def A2_pxorfnew : HInst<
947(outs IntRegs:$Rd32),
948(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
949"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
950tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
951let Inst{7-7} = 0b1;
952let Inst{13-13} = 0b1;
953let Inst{31-21} = 0b11111001011;
954let isPredicated = 1;
955let isPredicatedFalse = 1;
956let hasNewValue = 1;
957let opNewValue = 0;
958let isPredicatedNew = 1;
959let BaseOpcode = "A2_xor";
960}
961def A2_pxort : HInst<
962(outs IntRegs:$Rd32),
963(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
964"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
965tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
966let Inst{7-7} = 0b0;
967let Inst{13-13} = 0b0;
968let Inst{31-21} = 0b11111001011;
969let isPredicated = 1;
970let hasNewValue = 1;
971let opNewValue = 0;
972let BaseOpcode = "A2_xor";
973}
974def A2_pxortnew : HInst<
975(outs IntRegs:$Rd32),
976(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
977"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
978tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
979let Inst{7-7} = 0b0;
980let Inst{13-13} = 0b1;
981let Inst{31-21} = 0b11111001011;
982let isPredicated = 1;
983let hasNewValue = 1;
984let opNewValue = 0;
985let isPredicatedNew = 1;
986let BaseOpcode = "A2_xor";
987}
988def A2_roundsat : HInst<
989(outs IntRegs:$Rd32),
990(ins DoubleRegs:$Rss32),
991"$Rd32 = round($Rss32):sat",
992tc_cf8126ae, TypeS_2op>, Enc_90cd8b {
993let Inst{13-5} = 0b000000001;
994let Inst{31-21} = 0b10001000110;
995let hasNewValue = 1;
996let opNewValue = 0;
997let prefersSlot3 = 1;
998let Defs = [USR_OVF];
999}
1000def A2_sat : HInst<
1001(outs IntRegs:$Rd32),
1002(ins DoubleRegs:$Rss32),
1003"$Rd32 = sat($Rss32)",
1004tc_0ae0825c, TypeS_2op>, Enc_90cd8b {
1005let Inst{13-5} = 0b000000000;
1006let Inst{31-21} = 0b10001000110;
1007let hasNewValue = 1;
1008let opNewValue = 0;
1009let Defs = [USR_OVF];
1010}
1011def A2_satb : HInst<
1012(outs IntRegs:$Rd32),
1013(ins IntRegs:$Rs32),
1014"$Rd32 = satb($Rs32)",
1015tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
1016let Inst{13-5} = 0b000000111;
1017let Inst{31-21} = 0b10001100110;
1018let hasNewValue = 1;
1019let opNewValue = 0;
1020let Defs = [USR_OVF];
1021}
1022def A2_sath : HInst<
1023(outs IntRegs:$Rd32),
1024(ins IntRegs:$Rs32),
1025"$Rd32 = sath($Rs32)",
1026tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
1027let Inst{13-5} = 0b000000100;
1028let Inst{31-21} = 0b10001100110;
1029let hasNewValue = 1;
1030let opNewValue = 0;
1031let Defs = [USR_OVF];
1032}
1033def A2_satub : HInst<
1034(outs IntRegs:$Rd32),
1035(ins IntRegs:$Rs32),
1036"$Rd32 = satub($Rs32)",
1037tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
1038let Inst{13-5} = 0b000000110;
1039let Inst{31-21} = 0b10001100110;
1040let hasNewValue = 1;
1041let opNewValue = 0;
1042let Defs = [USR_OVF];
1043}
1044def A2_satuh : HInst<
1045(outs IntRegs:$Rd32),
1046(ins IntRegs:$Rs32),
1047"$Rd32 = satuh($Rs32)",
1048tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
1049let Inst{13-5} = 0b000000101;
1050let Inst{31-21} = 0b10001100110;
1051let hasNewValue = 1;
1052let opNewValue = 0;
1053let Defs = [USR_OVF];
1054}
1055def A2_sub : HInst<
1056(outs IntRegs:$Rd32),
1057(ins IntRegs:$Rt32, IntRegs:$Rs32),
1058"$Rd32 = sub($Rt32,$Rs32)",
1059tc_5a2711e5, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
1060let Inst{7-5} = 0b000;
1061let Inst{13-13} = 0b0;
1062let Inst{31-21} = 0b11110011001;
1063let hasNewValue = 1;
1064let opNewValue = 0;
1065let CextOpcode = "A2_sub";
1066let InputType = "reg";
1067let BaseOpcode = "A2_sub";
1068let isPredicable = 1;
1069}
1070def A2_subh_h16_hh : HInst<
1071(outs IntRegs:$Rd32),
1072(ins IntRegs:$Rt32, IntRegs:$Rs32),
1073"$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
1074tc_679309b8, TypeALU64>, Enc_bd6011 {
1075let Inst{7-5} = 0b011;
1076let Inst{13-13} = 0b0;
1077let Inst{31-21} = 0b11010101011;
1078let hasNewValue = 1;
1079let opNewValue = 0;
1080let prefersSlot3 = 1;
1081}
1082def A2_subh_h16_hl : HInst<
1083(outs IntRegs:$Rd32),
1084(ins IntRegs:$Rt32, IntRegs:$Rs32),
1085"$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
1086tc_679309b8, TypeALU64>, Enc_bd6011 {
1087let Inst{7-5} = 0b010;
1088let Inst{13-13} = 0b0;
1089let Inst{31-21} = 0b11010101011;
1090let hasNewValue = 1;
1091let opNewValue = 0;
1092let prefersSlot3 = 1;
1093}
1094def A2_subh_h16_lh : HInst<
1095(outs IntRegs:$Rd32),
1096(ins IntRegs:$Rt32, IntRegs:$Rs32),
1097"$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
1098tc_679309b8, TypeALU64>, Enc_bd6011 {
1099let Inst{7-5} = 0b001;
1100let Inst{13-13} = 0b0;
1101let Inst{31-21} = 0b11010101011;
1102let hasNewValue = 1;
1103let opNewValue = 0;
1104let prefersSlot3 = 1;
1105}
1106def A2_subh_h16_ll : HInst<
1107(outs IntRegs:$Rd32),
1108(ins IntRegs:$Rt32, IntRegs:$Rs32),
1109"$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
1110tc_679309b8, TypeALU64>, Enc_bd6011 {
1111let Inst{7-5} = 0b000;
1112let Inst{13-13} = 0b0;
1113let Inst{31-21} = 0b11010101011;
1114let hasNewValue = 1;
1115let opNewValue = 0;
1116let prefersSlot3 = 1;
1117}
1118def A2_subh_h16_sat_hh : HInst<
1119(outs IntRegs:$Rd32),
1120(ins IntRegs:$Rt32, IntRegs:$Rs32),
1121"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
1122tc_779080bf, TypeALU64>, Enc_bd6011 {
1123let Inst{7-5} = 0b111;
1124let Inst{13-13} = 0b0;
1125let Inst{31-21} = 0b11010101011;
1126let hasNewValue = 1;
1127let opNewValue = 0;
1128let prefersSlot3 = 1;
1129let Defs = [USR_OVF];
1130}
1131def A2_subh_h16_sat_hl : HInst<
1132(outs IntRegs:$Rd32),
1133(ins IntRegs:$Rt32, IntRegs:$Rs32),
1134"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
1135tc_779080bf, TypeALU64>, Enc_bd6011 {
1136let Inst{7-5} = 0b110;
1137let Inst{13-13} = 0b0;
1138let Inst{31-21} = 0b11010101011;
1139let hasNewValue = 1;
1140let opNewValue = 0;
1141let prefersSlot3 = 1;
1142let Defs = [USR_OVF];
1143}
1144def A2_subh_h16_sat_lh : HInst<
1145(outs IntRegs:$Rd32),
1146(ins IntRegs:$Rt32, IntRegs:$Rs32),
1147"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
1148tc_779080bf, TypeALU64>, Enc_bd6011 {
1149let Inst{7-5} = 0b101;
1150let Inst{13-13} = 0b0;
1151let Inst{31-21} = 0b11010101011;
1152let hasNewValue = 1;
1153let opNewValue = 0;
1154let prefersSlot3 = 1;
1155let Defs = [USR_OVF];
1156}
1157def A2_subh_h16_sat_ll : HInst<
1158(outs IntRegs:$Rd32),
1159(ins IntRegs:$Rt32, IntRegs:$Rs32),
1160"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
1161tc_779080bf, TypeALU64>, Enc_bd6011 {
1162let Inst{7-5} = 0b100;
1163let Inst{13-13} = 0b0;
1164let Inst{31-21} = 0b11010101011;
1165let hasNewValue = 1;
1166let opNewValue = 0;
1167let prefersSlot3 = 1;
1168let Defs = [USR_OVF];
1169}
1170def A2_subh_l16_hl : HInst<
1171(outs IntRegs:$Rd32),
1172(ins IntRegs:$Rt32, IntRegs:$Rs32),
1173"$Rd32 = sub($Rt32.l,$Rs32.h)",
1174tc_4414d8b1, TypeALU64>, Enc_bd6011 {
1175let Inst{7-5} = 0b010;
1176let Inst{13-13} = 0b0;
1177let Inst{31-21} = 0b11010101001;
1178let hasNewValue = 1;
1179let opNewValue = 0;
1180let prefersSlot3 = 1;
1181}
1182def A2_subh_l16_ll : HInst<
1183(outs IntRegs:$Rd32),
1184(ins IntRegs:$Rt32, IntRegs:$Rs32),
1185"$Rd32 = sub($Rt32.l,$Rs32.l)",
1186tc_4414d8b1, TypeALU64>, Enc_bd6011 {
1187let Inst{7-5} = 0b000;
1188let Inst{13-13} = 0b0;
1189let Inst{31-21} = 0b11010101001;
1190let hasNewValue = 1;
1191let opNewValue = 0;
1192let prefersSlot3 = 1;
1193}
1194def A2_subh_l16_sat_hl : HInst<
1195(outs IntRegs:$Rd32),
1196(ins IntRegs:$Rt32, IntRegs:$Rs32),
1197"$Rd32 = sub($Rt32.l,$Rs32.h):sat",
1198tc_779080bf, TypeALU64>, Enc_bd6011 {
1199let Inst{7-5} = 0b110;
1200let Inst{13-13} = 0b0;
1201let Inst{31-21} = 0b11010101001;
1202let hasNewValue = 1;
1203let opNewValue = 0;
1204let prefersSlot3 = 1;
1205let Defs = [USR_OVF];
1206}
1207def A2_subh_l16_sat_ll : HInst<
1208(outs IntRegs:$Rd32),
1209(ins IntRegs:$Rt32, IntRegs:$Rs32),
1210"$Rd32 = sub($Rt32.l,$Rs32.l):sat",
1211tc_779080bf, TypeALU64>, Enc_bd6011 {
1212let Inst{7-5} = 0b100;
1213let Inst{13-13} = 0b0;
1214let Inst{31-21} = 0b11010101001;
1215let hasNewValue = 1;
1216let opNewValue = 0;
1217let prefersSlot3 = 1;
1218let Defs = [USR_OVF];
1219}
1220def A2_subp : HInst<
1221(outs DoubleRegs:$Rdd32),
1222(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1223"$Rdd32 = sub($Rtt32,$Rss32)",
1224tc_946df596, TypeALU64>, Enc_ea23e4 {
1225let Inst{7-5} = 0b111;
1226let Inst{13-13} = 0b0;
1227let Inst{31-21} = 0b11010011001;
1228}
1229def A2_subri : HInst<
1230(outs IntRegs:$Rd32),
1231(ins s32_0Imm:$Ii, IntRegs:$Rs32),
1232"$Rd32 = sub(#$Ii,$Rs32)",
1233tc_5a2711e5, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
1234let Inst{31-22} = 0b0111011001;
1235let hasNewValue = 1;
1236let opNewValue = 0;
1237let CextOpcode = "A2_sub";
1238let InputType = "imm";
1239let isExtendable = 1;
1240let opExtendable = 1;
1241let isExtentSigned = 1;
1242let opExtentBits = 10;
1243let opExtentAlign = 0;
1244}
1245def A2_subsat : HInst<
1246(outs IntRegs:$Rd32),
1247(ins IntRegs:$Rt32, IntRegs:$Rs32),
1248"$Rd32 = sub($Rt32,$Rs32):sat",
1249tc_61830035, TypeALU32_3op>, Enc_bd6011 {
1250let Inst{7-5} = 0b000;
1251let Inst{13-13} = 0b0;
1252let Inst{31-21} = 0b11110110110;
1253let hasNewValue = 1;
1254let opNewValue = 0;
1255let prefersSlot3 = 1;
1256let Defs = [USR_OVF];
1257let InputType = "reg";
1258}
1259def A2_svaddh : HInst<
1260(outs IntRegs:$Rd32),
1261(ins IntRegs:$Rs32, IntRegs:$Rt32),
1262"$Rd32 = vaddh($Rs32,$Rt32)",
1263tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be {
1264let Inst{7-5} = 0b000;
1265let Inst{13-13} = 0b0;
1266let Inst{31-21} = 0b11110110000;
1267let hasNewValue = 1;
1268let opNewValue = 0;
1269let InputType = "reg";
1270let isCommutable = 1;
1271}
1272def A2_svaddhs : HInst<
1273(outs IntRegs:$Rd32),
1274(ins IntRegs:$Rs32, IntRegs:$Rt32),
1275"$Rd32 = vaddh($Rs32,$Rt32):sat",
1276tc_61830035, TypeALU32_3op>, Enc_5ab2be {
1277let Inst{7-5} = 0b000;
1278let Inst{13-13} = 0b0;
1279let Inst{31-21} = 0b11110110001;
1280let hasNewValue = 1;
1281let opNewValue = 0;
1282let prefersSlot3 = 1;
1283let Defs = [USR_OVF];
1284let InputType = "reg";
1285let isCommutable = 1;
1286}
1287def A2_svadduhs : HInst<
1288(outs IntRegs:$Rd32),
1289(ins IntRegs:$Rs32, IntRegs:$Rt32),
1290"$Rd32 = vadduh($Rs32,$Rt32):sat",
1291tc_61830035, TypeALU32_3op>, Enc_5ab2be {
1292let Inst{7-5} = 0b000;
1293let Inst{13-13} = 0b0;
1294let Inst{31-21} = 0b11110110011;
1295let hasNewValue = 1;
1296let opNewValue = 0;
1297let prefersSlot3 = 1;
1298let Defs = [USR_OVF];
1299let InputType = "reg";
1300let isCommutable = 1;
1301}
1302def A2_svavgh : HInst<
1303(outs IntRegs:$Rd32),
1304(ins IntRegs:$Rs32, IntRegs:$Rt32),
1305"$Rd32 = vavgh($Rs32,$Rt32)",
1306tc_1c80410a, TypeALU32_3op>, Enc_5ab2be {
1307let Inst{7-5} = 0b000;
1308let Inst{13-13} = 0b0;
1309let Inst{31-21} = 0b11110111000;
1310let hasNewValue = 1;
1311let opNewValue = 0;
1312let prefersSlot3 = 1;
1313let InputType = "reg";
1314let isCommutable = 1;
1315}
1316def A2_svavghs : HInst<
1317(outs IntRegs:$Rd32),
1318(ins IntRegs:$Rs32, IntRegs:$Rt32),
1319"$Rd32 = vavgh($Rs32,$Rt32):rnd",
1320tc_d08ee0f4, TypeALU32_3op>, Enc_5ab2be {
1321let Inst{7-5} = 0b000;
1322let Inst{13-13} = 0b0;
1323let Inst{31-21} = 0b11110111001;
1324let hasNewValue = 1;
1325let opNewValue = 0;
1326let prefersSlot3 = 1;
1327let InputType = "reg";
1328let isCommutable = 1;
1329}
1330def A2_svnavgh : HInst<
1331(outs IntRegs:$Rd32),
1332(ins IntRegs:$Rt32, IntRegs:$Rs32),
1333"$Rd32 = vnavgh($Rt32,$Rs32)",
1334tc_1c80410a, TypeALU32_3op>, Enc_bd6011 {
1335let Inst{7-5} = 0b000;
1336let Inst{13-13} = 0b0;
1337let Inst{31-21} = 0b11110111011;
1338let hasNewValue = 1;
1339let opNewValue = 0;
1340let prefersSlot3 = 1;
1341let InputType = "reg";
1342}
1343def A2_svsubh : HInst<
1344(outs IntRegs:$Rd32),
1345(ins IntRegs:$Rt32, IntRegs:$Rs32),
1346"$Rd32 = vsubh($Rt32,$Rs32)",
1347tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 {
1348let Inst{7-5} = 0b000;
1349let Inst{13-13} = 0b0;
1350let Inst{31-21} = 0b11110110100;
1351let hasNewValue = 1;
1352let opNewValue = 0;
1353let InputType = "reg";
1354}
1355def A2_svsubhs : HInst<
1356(outs IntRegs:$Rd32),
1357(ins IntRegs:$Rt32, IntRegs:$Rs32),
1358"$Rd32 = vsubh($Rt32,$Rs32):sat",
1359tc_61830035, TypeALU32_3op>, Enc_bd6011 {
1360let Inst{7-5} = 0b000;
1361let Inst{13-13} = 0b0;
1362let Inst{31-21} = 0b11110110101;
1363let hasNewValue = 1;
1364let opNewValue = 0;
1365let prefersSlot3 = 1;
1366let Defs = [USR_OVF];
1367let InputType = "reg";
1368}
1369def A2_svsubuhs : HInst<
1370(outs IntRegs:$Rd32),
1371(ins IntRegs:$Rt32, IntRegs:$Rs32),
1372"$Rd32 = vsubuh($Rt32,$Rs32):sat",
1373tc_61830035, TypeALU32_3op>, Enc_bd6011 {
1374let Inst{7-5} = 0b000;
1375let Inst{13-13} = 0b0;
1376let Inst{31-21} = 0b11110110111;
1377let hasNewValue = 1;
1378let opNewValue = 0;
1379let prefersSlot3 = 1;
1380let Defs = [USR_OVF];
1381let InputType = "reg";
1382}
1383def A2_swiz : HInst<
1384(outs IntRegs:$Rd32),
1385(ins IntRegs:$Rs32),
1386"$Rd32 = swiz($Rs32)",
1387tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
1388let Inst{13-5} = 0b000000111;
1389let Inst{31-21} = 0b10001100100;
1390let hasNewValue = 1;
1391let opNewValue = 0;
1392}
1393def A2_sxtb : HInst<
1394(outs IntRegs:$Rd32),
1395(ins IntRegs:$Rs32),
1396"$Rd32 = sxtb($Rs32)",
1397tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1398let Inst{13-5} = 0b000000000;
1399let Inst{31-21} = 0b01110000101;
1400let hasNewValue = 1;
1401let opNewValue = 0;
1402let BaseOpcode = "A2_sxtb";
1403let isPredicable = 1;
1404}
1405def A2_sxth : HInst<
1406(outs IntRegs:$Rd32),
1407(ins IntRegs:$Rs32),
1408"$Rd32 = sxth($Rs32)",
1409tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1410let Inst{13-5} = 0b000000000;
1411let Inst{31-21} = 0b01110000111;
1412let hasNewValue = 1;
1413let opNewValue = 0;
1414let BaseOpcode = "A2_sxth";
1415let isPredicable = 1;
1416}
1417def A2_sxtw : HInst<
1418(outs DoubleRegs:$Rdd32),
1419(ins IntRegs:$Rs32),
1420"$Rdd32 = sxtw($Rs32)",
1421tc_0ae0825c, TypeS_2op>, Enc_3a3d62 {
1422let Inst{13-5} = 0b000000000;
1423let Inst{31-21} = 0b10000100010;
1424}
1425def A2_tfr : HInst<
1426(outs IntRegs:$Rd32),
1427(ins IntRegs:$Rs32),
1428"$Rd32 = $Rs32",
1429tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1430let Inst{13-5} = 0b000000000;
1431let Inst{31-21} = 0b01110000011;
1432let hasNewValue = 1;
1433let opNewValue = 0;
1434let InputType = "reg";
1435let BaseOpcode = "A2_tfr";
1436let isPredicable = 1;
1437}
1438def A2_tfrcrr : HInst<
1439(outs IntRegs:$Rd32),
1440(ins CtrRegs:$Cs32),
1441"$Rd32 = $Cs32",
1442tc_b9272d6c, TypeCR>, Enc_0cb018 {
1443let Inst{13-5} = 0b000000000;
1444let Inst{31-21} = 0b01101010000;
1445let hasNewValue = 1;
1446let opNewValue = 0;
1447}
1448def A2_tfrf : HInst<
1449(outs IntRegs:$Rd32),
1450(ins PredRegs:$Pu4, IntRegs:$Rs32),
1451"if (!$Pu4) $Rd32 = $Rs32",
1452tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel {
1453let isPredicated = 1;
1454let isPredicatedFalse = 1;
1455let hasNewValue = 1;
1456let opNewValue = 0;
1457let CextOpcode = "A2_tfr";
1458let InputType = "reg";
1459let BaseOpcode = "A2_tfr";
1460let isPseudo = 1;
1461let isCodeGenOnly = 1;
1462}
1463def A2_tfrfnew : HInst<
1464(outs IntRegs:$Rd32),
1465(ins PredRegs:$Pu4, IntRegs:$Rs32),
1466"if (!$Pu4.new) $Rd32 = $Rs32",
1467tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel {
1468let isPredicated = 1;
1469let isPredicatedFalse = 1;
1470let hasNewValue = 1;
1471let opNewValue = 0;
1472let isPredicatedNew = 1;
1473let CextOpcode = "A2_tfr";
1474let InputType = "reg";
1475let BaseOpcode = "A2_tfr";
1476let isPseudo = 1;
1477let isCodeGenOnly = 1;
1478}
1479def A2_tfrih : HInst<
1480(outs IntRegs:$Rx32),
1481(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1482"$Rx32.h = #$Ii",
1483tc_5a2711e5, TypeALU32_2op>, Enc_51436c {
1484let Inst{21-21} = 0b1;
1485let Inst{31-24} = 0b01110010;
1486let hasNewValue = 1;
1487let opNewValue = 0;
1488let Constraints = "$Rx32 = $Rx32in";
1489}
1490def A2_tfril : HInst<
1491(outs IntRegs:$Rx32),
1492(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1493"$Rx32.l = #$Ii",
1494tc_5a2711e5, TypeALU32_2op>, Enc_51436c {
1495let Inst{21-21} = 0b1;
1496let Inst{31-24} = 0b01110001;
1497let hasNewValue = 1;
1498let opNewValue = 0;
1499let Constraints = "$Rx32 = $Rx32in";
1500}
1501def A2_tfrp : HInst<
1502(outs DoubleRegs:$Rdd32),
1503(ins DoubleRegs:$Rss32),
1504"$Rdd32 = $Rss32",
1505tc_5a2711e5, TypeALU32_2op>, PredNewRel {
1506let BaseOpcode = "A2_tfrp";
1507let isPredicable = 1;
1508let isPseudo = 1;
1509}
1510def A2_tfrpf : HInst<
1511(outs DoubleRegs:$Rdd32),
1512(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1513"if (!$Pu4) $Rdd32 = $Rss32",
1514tc_5a2711e5, TypeALU32_2op>, PredNewRel {
1515let isPredicated = 1;
1516let isPredicatedFalse = 1;
1517let BaseOpcode = "A2_tfrp";
1518let isPseudo = 1;
1519}
1520def A2_tfrpfnew : HInst<
1521(outs DoubleRegs:$Rdd32),
1522(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1523"if (!$Pu4.new) $Rdd32 = $Rss32",
1524tc_1ae57e39, TypeALU32_2op>, PredNewRel {
1525let isPredicated = 1;
1526let isPredicatedFalse = 1;
1527let isPredicatedNew = 1;
1528let BaseOpcode = "A2_tfrp";
1529let isPseudo = 1;
1530}
1531def A2_tfrpi : HInst<
1532(outs DoubleRegs:$Rdd32),
1533(ins s8_0Imm:$Ii),
1534"$Rdd32 = #$Ii",
1535tc_5a2711e5, TypeALU64> {
1536let isReMaterializable = 1;
1537let isAsCheapAsAMove = 1;
1538let isMoveImm = 1;
1539let isPseudo = 1;
1540}
1541def A2_tfrpt : HInst<
1542(outs DoubleRegs:$Rdd32),
1543(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1544"if ($Pu4) $Rdd32 = $Rss32",
1545tc_5a2711e5, TypeALU32_2op>, PredNewRel {
1546let isPredicated = 1;
1547let BaseOpcode = "A2_tfrp";
1548let isPseudo = 1;
1549}
1550def A2_tfrptnew : HInst<
1551(outs DoubleRegs:$Rdd32),
1552(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1553"if ($Pu4.new) $Rdd32 = $Rss32",
1554tc_1ae57e39, TypeALU32_2op>, PredNewRel {
1555let isPredicated = 1;
1556let isPredicatedNew = 1;
1557let BaseOpcode = "A2_tfrp";
1558let isPseudo = 1;
1559}
1560def A2_tfrrcr : HInst<
1561(outs CtrRegs:$Cd32),
1562(ins IntRegs:$Rs32),
1563"$Cd32 = $Rs32",
1564tc_434c8e1e, TypeCR>, Enc_bd811a {
1565let Inst{13-5} = 0b000000000;
1566let Inst{31-21} = 0b01100010001;
1567let hasNewValue = 1;
1568let opNewValue = 0;
1569}
1570def A2_tfrsi : HInst<
1571(outs IntRegs:$Rd32),
1572(ins s32_0Imm:$Ii),
1573"$Rd32 = #$Ii",
1574tc_57890846, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
1575let Inst{21-21} = 0b0;
1576let Inst{31-24} = 0b01111000;
1577let hasNewValue = 1;
1578let opNewValue = 0;
1579let CextOpcode = "A2_tfr";
1580let InputType = "imm";
1581let BaseOpcode = "A2_tfrsi";
1582let isPredicable = 1;
1583let isReMaterializable = 1;
1584let isAsCheapAsAMove = 1;
1585let isMoveImm = 1;
1586let isExtendable = 1;
1587let opExtendable = 1;
1588let isExtentSigned = 1;
1589let opExtentBits = 16;
1590let opExtentAlign = 0;
1591}
1592def A2_tfrt : HInst<
1593(outs IntRegs:$Rd32),
1594(ins PredRegs:$Pu4, IntRegs:$Rs32),
1595"if ($Pu4) $Rd32 = $Rs32",
1596tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel {
1597let isPredicated = 1;
1598let hasNewValue = 1;
1599let opNewValue = 0;
1600let CextOpcode = "A2_tfr";
1601let InputType = "reg";
1602let BaseOpcode = "A2_tfr";
1603let isPseudo = 1;
1604let isCodeGenOnly = 1;
1605}
1606def A2_tfrtnew : HInst<
1607(outs IntRegs:$Rd32),
1608(ins PredRegs:$Pu4, IntRegs:$Rs32),
1609"if ($Pu4.new) $Rd32 = $Rs32",
1610tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel {
1611let isPredicated = 1;
1612let hasNewValue = 1;
1613let opNewValue = 0;
1614let isPredicatedNew = 1;
1615let CextOpcode = "A2_tfr";
1616let InputType = "reg";
1617let BaseOpcode = "A2_tfr";
1618let isPseudo = 1;
1619let isCodeGenOnly = 1;
1620}
1621def A2_vabsh : HInst<
1622(outs DoubleRegs:$Rdd32),
1623(ins DoubleRegs:$Rss32),
1624"$Rdd32 = vabsh($Rss32)",
1625tc_cf8126ae, TypeS_2op>, Enc_b9c5fb {
1626let Inst{13-5} = 0b000000100;
1627let Inst{31-21} = 0b10000000010;
1628let prefersSlot3 = 1;
1629}
1630def A2_vabshsat : HInst<
1631(outs DoubleRegs:$Rdd32),
1632(ins DoubleRegs:$Rss32),
1633"$Rdd32 = vabsh($Rss32):sat",
1634tc_cf8126ae, TypeS_2op>, Enc_b9c5fb {
1635let Inst{13-5} = 0b000000101;
1636let Inst{31-21} = 0b10000000010;
1637let prefersSlot3 = 1;
1638let Defs = [USR_OVF];
1639}
1640def A2_vabsw : HInst<
1641(outs DoubleRegs:$Rdd32),
1642(ins DoubleRegs:$Rss32),
1643"$Rdd32 = vabsw($Rss32)",
1644tc_cf8126ae, TypeS_2op>, Enc_b9c5fb {
1645let Inst{13-5} = 0b000000110;
1646let Inst{31-21} = 0b10000000010;
1647let prefersSlot3 = 1;
1648}
1649def A2_vabswsat : HInst<
1650(outs DoubleRegs:$Rdd32),
1651(ins DoubleRegs:$Rss32),
1652"$Rdd32 = vabsw($Rss32):sat",
1653tc_cf8126ae, TypeS_2op>, Enc_b9c5fb {
1654let Inst{13-5} = 0b000000111;
1655let Inst{31-21} = 0b10000000010;
1656let prefersSlot3 = 1;
1657let Defs = [USR_OVF];
1658}
1659def A2_vaddb_map : HInst<
1660(outs DoubleRegs:$Rdd32),
1661(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1662"$Rdd32 = vaddb($Rss32,$Rtt32)",
1663tc_946df596, TypeMAPPING> {
1664let isPseudo = 1;
1665let isCodeGenOnly = 1;
1666}
1667def A2_vaddh : HInst<
1668(outs DoubleRegs:$Rdd32),
1669(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1670"$Rdd32 = vaddh($Rss32,$Rtt32)",
1671tc_946df596, TypeALU64>, Enc_a56825 {
1672let Inst{7-5} = 0b010;
1673let Inst{13-13} = 0b0;
1674let Inst{31-21} = 0b11010011000;
1675}
1676def A2_vaddhs : HInst<
1677(outs DoubleRegs:$Rdd32),
1678(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1679"$Rdd32 = vaddh($Rss32,$Rtt32):sat",
1680tc_779080bf, TypeALU64>, Enc_a56825 {
1681let Inst{7-5} = 0b011;
1682let Inst{13-13} = 0b0;
1683let Inst{31-21} = 0b11010011000;
1684let prefersSlot3 = 1;
1685let Defs = [USR_OVF];
1686}
1687def A2_vaddub : HInst<
1688(outs DoubleRegs:$Rdd32),
1689(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1690"$Rdd32 = vaddub($Rss32,$Rtt32)",
1691tc_946df596, TypeALU64>, Enc_a56825 {
1692let Inst{7-5} = 0b000;
1693let Inst{13-13} = 0b0;
1694let Inst{31-21} = 0b11010011000;
1695}
1696def A2_vaddubs : HInst<
1697(outs DoubleRegs:$Rdd32),
1698(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1699"$Rdd32 = vaddub($Rss32,$Rtt32):sat",
1700tc_779080bf, TypeALU64>, Enc_a56825 {
1701let Inst{7-5} = 0b001;
1702let Inst{13-13} = 0b0;
1703let Inst{31-21} = 0b11010011000;
1704let prefersSlot3 = 1;
1705let Defs = [USR_OVF];
1706}
1707def A2_vadduhs : HInst<
1708(outs DoubleRegs:$Rdd32),
1709(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1710"$Rdd32 = vadduh($Rss32,$Rtt32):sat",
1711tc_779080bf, TypeALU64>, Enc_a56825 {
1712let Inst{7-5} = 0b100;
1713let Inst{13-13} = 0b0;
1714let Inst{31-21} = 0b11010011000;
1715let prefersSlot3 = 1;
1716let Defs = [USR_OVF];
1717}
1718def A2_vaddw : HInst<
1719(outs DoubleRegs:$Rdd32),
1720(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1721"$Rdd32 = vaddw($Rss32,$Rtt32)",
1722tc_946df596, TypeALU64>, Enc_a56825 {
1723let Inst{7-5} = 0b101;
1724let Inst{13-13} = 0b0;
1725let Inst{31-21} = 0b11010011000;
1726}
1727def A2_vaddws : HInst<
1728(outs DoubleRegs:$Rdd32),
1729(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1730"$Rdd32 = vaddw($Rss32,$Rtt32):sat",
1731tc_779080bf, TypeALU64>, Enc_a56825 {
1732let Inst{7-5} = 0b110;
1733let Inst{13-13} = 0b0;
1734let Inst{31-21} = 0b11010011000;
1735let prefersSlot3 = 1;
1736let Defs = [USR_OVF];
1737}
1738def A2_vavgh : HInst<
1739(outs DoubleRegs:$Rdd32),
1740(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1741"$Rdd32 = vavgh($Rss32,$Rtt32)",
1742tc_6132ba3d, TypeALU64>, Enc_a56825 {
1743let Inst{7-5} = 0b010;
1744let Inst{13-13} = 0b0;
1745let Inst{31-21} = 0b11010011010;
1746let prefersSlot3 = 1;
1747}
1748def A2_vavghcr : HInst<
1749(outs DoubleRegs:$Rdd32),
1750(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1751"$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
1752tc_002cb246, TypeALU64>, Enc_a56825 {
1753let Inst{7-5} = 0b100;
1754let Inst{13-13} = 0b0;
1755let Inst{31-21} = 0b11010011010;
1756let prefersSlot3 = 1;
1757}
1758def A2_vavghr : HInst<
1759(outs DoubleRegs:$Rdd32),
1760(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1761"$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
1762tc_e4a7f9f0, TypeALU64>, Enc_a56825 {
1763let Inst{7-5} = 0b011;
1764let Inst{13-13} = 0b0;
1765let Inst{31-21} = 0b11010011010;
1766let prefersSlot3 = 1;
1767}
1768def A2_vavgub : HInst<
1769(outs DoubleRegs:$Rdd32),
1770(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1771"$Rdd32 = vavgub($Rss32,$Rtt32)",
1772tc_6132ba3d, TypeALU64>, Enc_a56825 {
1773let Inst{7-5} = 0b000;
1774let Inst{13-13} = 0b0;
1775let Inst{31-21} = 0b11010011010;
1776let prefersSlot3 = 1;
1777}
1778def A2_vavgubr : HInst<
1779(outs DoubleRegs:$Rdd32),
1780(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1781"$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
1782tc_e4a7f9f0, TypeALU64>, Enc_a56825 {
1783let Inst{7-5} = 0b001;
1784let Inst{13-13} = 0b0;
1785let Inst{31-21} = 0b11010011010;
1786let prefersSlot3 = 1;
1787}
1788def A2_vavguh : HInst<
1789(outs DoubleRegs:$Rdd32),
1790(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1791"$Rdd32 = vavguh($Rss32,$Rtt32)",
1792tc_6132ba3d, TypeALU64>, Enc_a56825 {
1793let Inst{7-5} = 0b101;
1794let Inst{13-13} = 0b0;
1795let Inst{31-21} = 0b11010011010;
1796let prefersSlot3 = 1;
1797}
1798def A2_vavguhr : HInst<
1799(outs DoubleRegs:$Rdd32),
1800(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1801"$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
1802tc_e4a7f9f0, TypeALU64>, Enc_a56825 {
1803let Inst{7-5} = 0b110;
1804let Inst{13-13} = 0b0;
1805let Inst{31-21} = 0b11010011010;
1806let prefersSlot3 = 1;
1807}
1808def A2_vavguw : HInst<
1809(outs DoubleRegs:$Rdd32),
1810(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1811"$Rdd32 = vavguw($Rss32,$Rtt32)",
1812tc_6132ba3d, TypeALU64>, Enc_a56825 {
1813let Inst{7-5} = 0b011;
1814let Inst{13-13} = 0b0;
1815let Inst{31-21} = 0b11010011011;
1816let prefersSlot3 = 1;
1817}
1818def A2_vavguwr : HInst<
1819(outs DoubleRegs:$Rdd32),
1820(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1821"$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
1822tc_e4a7f9f0, TypeALU64>, Enc_a56825 {
1823let Inst{7-5} = 0b100;
1824let Inst{13-13} = 0b0;
1825let Inst{31-21} = 0b11010011011;
1826let prefersSlot3 = 1;
1827}
1828def A2_vavgw : HInst<
1829(outs DoubleRegs:$Rdd32),
1830(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1831"$Rdd32 = vavgw($Rss32,$Rtt32)",
1832tc_6132ba3d, TypeALU64>, Enc_a56825 {
1833let Inst{7-5} = 0b000;
1834let Inst{13-13} = 0b0;
1835let Inst{31-21} = 0b11010011011;
1836let prefersSlot3 = 1;
1837}
1838def A2_vavgwcr : HInst<
1839(outs DoubleRegs:$Rdd32),
1840(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1841"$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
1842tc_002cb246, TypeALU64>, Enc_a56825 {
1843let Inst{7-5} = 0b010;
1844let Inst{13-13} = 0b0;
1845let Inst{31-21} = 0b11010011011;
1846let prefersSlot3 = 1;
1847}
1848def A2_vavgwr : HInst<
1849(outs DoubleRegs:$Rdd32),
1850(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1851"$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
1852tc_e4a7f9f0, TypeALU64>, Enc_a56825 {
1853let Inst{7-5} = 0b001;
1854let Inst{13-13} = 0b0;
1855let Inst{31-21} = 0b11010011011;
1856let prefersSlot3 = 1;
1857}
1858def A2_vcmpbeq : HInst<
1859(outs PredRegs:$Pd4),
1860(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1861"$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
1862tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1863let Inst{7-2} = 0b110000;
1864let Inst{13-13} = 0b0;
1865let Inst{31-21} = 0b11010010000;
1866}
1867def A2_vcmpbgtu : HInst<
1868(outs PredRegs:$Pd4),
1869(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1870"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
1871tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1872let Inst{7-2} = 0b111000;
1873let Inst{13-13} = 0b0;
1874let Inst{31-21} = 0b11010010000;
1875}
1876def A2_vcmpheq : HInst<
1877(outs PredRegs:$Pd4),
1878(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1879"$Pd4 = vcmph.eq($Rss32,$Rtt32)",
1880tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1881let Inst{7-2} = 0b011000;
1882let Inst{13-13} = 0b0;
1883let Inst{31-21} = 0b11010010000;
1884}
1885def A2_vcmphgt : HInst<
1886(outs PredRegs:$Pd4),
1887(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1888"$Pd4 = vcmph.gt($Rss32,$Rtt32)",
1889tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1890let Inst{7-2} = 0b100000;
1891let Inst{13-13} = 0b0;
1892let Inst{31-21} = 0b11010010000;
1893}
1894def A2_vcmphgtu : HInst<
1895(outs PredRegs:$Pd4),
1896(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1897"$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
1898tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1899let Inst{7-2} = 0b101000;
1900let Inst{13-13} = 0b0;
1901let Inst{31-21} = 0b11010010000;
1902}
1903def A2_vcmpweq : HInst<
1904(outs PredRegs:$Pd4),
1905(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1906"$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
1907tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1908let Inst{7-2} = 0b000000;
1909let Inst{13-13} = 0b0;
1910let Inst{31-21} = 0b11010010000;
1911}
1912def A2_vcmpwgt : HInst<
1913(outs PredRegs:$Pd4),
1914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1915"$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
1916tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1917let Inst{7-2} = 0b001000;
1918let Inst{13-13} = 0b0;
1919let Inst{31-21} = 0b11010010000;
1920}
1921def A2_vcmpwgtu : HInst<
1922(outs PredRegs:$Pd4),
1923(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1924"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
1925tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
1926let Inst{7-2} = 0b010000;
1927let Inst{13-13} = 0b0;
1928let Inst{31-21} = 0b11010010000;
1929}
1930def A2_vconj : HInst<
1931(outs DoubleRegs:$Rdd32),
1932(ins DoubleRegs:$Rss32),
1933"$Rdd32 = vconj($Rss32):sat",
1934tc_cf8126ae, TypeS_2op>, Enc_b9c5fb {
1935let Inst{13-5} = 0b000000111;
1936let Inst{31-21} = 0b10000000100;
1937let prefersSlot3 = 1;
1938let Defs = [USR_OVF];
1939}
1940def A2_vmaxb : HInst<
1941(outs DoubleRegs:$Rdd32),
1942(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1943"$Rdd32 = vmaxb($Rtt32,$Rss32)",
1944tc_779080bf, TypeALU64>, Enc_ea23e4 {
1945let Inst{7-5} = 0b110;
1946let Inst{13-13} = 0b0;
1947let Inst{31-21} = 0b11010011110;
1948let prefersSlot3 = 1;
1949}
1950def A2_vmaxh : HInst<
1951(outs DoubleRegs:$Rdd32),
1952(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1953"$Rdd32 = vmaxh($Rtt32,$Rss32)",
1954tc_779080bf, TypeALU64>, Enc_ea23e4 {
1955let Inst{7-5} = 0b001;
1956let Inst{13-13} = 0b0;
1957let Inst{31-21} = 0b11010011110;
1958let prefersSlot3 = 1;
1959}
1960def A2_vmaxub : HInst<
1961(outs DoubleRegs:$Rdd32),
1962(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1963"$Rdd32 = vmaxub($Rtt32,$Rss32)",
1964tc_779080bf, TypeALU64>, Enc_ea23e4 {
1965let Inst{7-5} = 0b000;
1966let Inst{13-13} = 0b0;
1967let Inst{31-21} = 0b11010011110;
1968let prefersSlot3 = 1;
1969}
1970def A2_vmaxuh : HInst<
1971(outs DoubleRegs:$Rdd32),
1972(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1973"$Rdd32 = vmaxuh($Rtt32,$Rss32)",
1974tc_779080bf, TypeALU64>, Enc_ea23e4 {
1975let Inst{7-5} = 0b010;
1976let Inst{13-13} = 0b0;
1977let Inst{31-21} = 0b11010011110;
1978let prefersSlot3 = 1;
1979}
1980def A2_vmaxuw : HInst<
1981(outs DoubleRegs:$Rdd32),
1982(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1983"$Rdd32 = vmaxuw($Rtt32,$Rss32)",
1984tc_779080bf, TypeALU64>, Enc_ea23e4 {
1985let Inst{7-5} = 0b101;
1986let Inst{13-13} = 0b0;
1987let Inst{31-21} = 0b11010011101;
1988let prefersSlot3 = 1;
1989}
1990def A2_vmaxw : HInst<
1991(outs DoubleRegs:$Rdd32),
1992(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1993"$Rdd32 = vmaxw($Rtt32,$Rss32)",
1994tc_779080bf, TypeALU64>, Enc_ea23e4 {
1995let Inst{7-5} = 0b011;
1996let Inst{13-13} = 0b0;
1997let Inst{31-21} = 0b11010011110;
1998let prefersSlot3 = 1;
1999}
2000def A2_vminb : HInst<
2001(outs DoubleRegs:$Rdd32),
2002(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2003"$Rdd32 = vminb($Rtt32,$Rss32)",
2004tc_779080bf, TypeALU64>, Enc_ea23e4 {
2005let Inst{7-5} = 0b111;
2006let Inst{13-13} = 0b0;
2007let Inst{31-21} = 0b11010011110;
2008let prefersSlot3 = 1;
2009}
2010def A2_vminh : HInst<
2011(outs DoubleRegs:$Rdd32),
2012(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2013"$Rdd32 = vminh($Rtt32,$Rss32)",
2014tc_779080bf, TypeALU64>, Enc_ea23e4 {
2015let Inst{7-5} = 0b001;
2016let Inst{13-13} = 0b0;
2017let Inst{31-21} = 0b11010011101;
2018let prefersSlot3 = 1;
2019}
2020def A2_vminub : HInst<
2021(outs DoubleRegs:$Rdd32),
2022(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2023"$Rdd32 = vminub($Rtt32,$Rss32)",
2024tc_779080bf, TypeALU64>, Enc_ea23e4 {
2025let Inst{7-5} = 0b000;
2026let Inst{13-13} = 0b0;
2027let Inst{31-21} = 0b11010011101;
2028let prefersSlot3 = 1;
2029}
2030def A2_vminuh : HInst<
2031(outs DoubleRegs:$Rdd32),
2032(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2033"$Rdd32 = vminuh($Rtt32,$Rss32)",
2034tc_779080bf, TypeALU64>, Enc_ea23e4 {
2035let Inst{7-5} = 0b010;
2036let Inst{13-13} = 0b0;
2037let Inst{31-21} = 0b11010011101;
2038let prefersSlot3 = 1;
2039}
2040def A2_vminuw : HInst<
2041(outs DoubleRegs:$Rdd32),
2042(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2043"$Rdd32 = vminuw($Rtt32,$Rss32)",
2044tc_779080bf, TypeALU64>, Enc_ea23e4 {
2045let Inst{7-5} = 0b100;
2046let Inst{13-13} = 0b0;
2047let Inst{31-21} = 0b11010011101;
2048let prefersSlot3 = 1;
2049}
2050def A2_vminw : HInst<
2051(outs DoubleRegs:$Rdd32),
2052(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2053"$Rdd32 = vminw($Rtt32,$Rss32)",
2054tc_779080bf, TypeALU64>, Enc_ea23e4 {
2055let Inst{7-5} = 0b011;
2056let Inst{13-13} = 0b0;
2057let Inst{31-21} = 0b11010011101;
2058let prefersSlot3 = 1;
2059}
2060def A2_vnavgh : HInst<
2061(outs DoubleRegs:$Rdd32),
2062(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2063"$Rdd32 = vnavgh($Rtt32,$Rss32)",
2064tc_6132ba3d, TypeALU64>, Enc_ea23e4 {
2065let Inst{7-5} = 0b000;
2066let Inst{13-13} = 0b0;
2067let Inst{31-21} = 0b11010011100;
2068let prefersSlot3 = 1;
2069}
2070def A2_vnavghcr : HInst<
2071(outs DoubleRegs:$Rdd32),
2072(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2073"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
2074tc_002cb246, TypeALU64>, Enc_ea23e4 {
2075let Inst{7-5} = 0b010;
2076let Inst{13-13} = 0b0;
2077let Inst{31-21} = 0b11010011100;
2078let prefersSlot3 = 1;
2079let Defs = [USR_OVF];
2080}
2081def A2_vnavghr : HInst<
2082(outs DoubleRegs:$Rdd32),
2083(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2084"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
2085tc_002cb246, TypeALU64>, Enc_ea23e4 {
2086let Inst{7-5} = 0b001;
2087let Inst{13-13} = 0b0;
2088let Inst{31-21} = 0b11010011100;
2089let prefersSlot3 = 1;
2090let Defs = [USR_OVF];
2091}
2092def A2_vnavgw : HInst<
2093(outs DoubleRegs:$Rdd32),
2094(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2095"$Rdd32 = vnavgw($Rtt32,$Rss32)",
2096tc_6132ba3d, TypeALU64>, Enc_ea23e4 {
2097let Inst{7-5} = 0b011;
2098let Inst{13-13} = 0b0;
2099let Inst{31-21} = 0b11010011100;
2100let prefersSlot3 = 1;
2101}
2102def A2_vnavgwcr : HInst<
2103(outs DoubleRegs:$Rdd32),
2104(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2105"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
2106tc_002cb246, TypeALU64>, Enc_ea23e4 {
2107let Inst{7-5} = 0b110;
2108let Inst{13-13} = 0b0;
2109let Inst{31-21} = 0b11010011100;
2110let prefersSlot3 = 1;
2111let Defs = [USR_OVF];
2112}
2113def A2_vnavgwr : HInst<
2114(outs DoubleRegs:$Rdd32),
2115(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2116"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
2117tc_002cb246, TypeALU64>, Enc_ea23e4 {
2118let Inst{7-5} = 0b100;
2119let Inst{13-13} = 0b0;
2120let Inst{31-21} = 0b11010011100;
2121let prefersSlot3 = 1;
2122let Defs = [USR_OVF];
2123}
2124def A2_vraddub : HInst<
2125(outs DoubleRegs:$Rdd32),
2126(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2127"$Rdd32 = vraddub($Rss32,$Rtt32)",
2128tc_bafaade3, TypeM>, Enc_a56825 {
2129let Inst{7-5} = 0b001;
2130let Inst{13-13} = 0b0;
2131let Inst{31-21} = 0b11101000010;
2132let prefersSlot3 = 1;
2133}
2134def A2_vraddub_acc : HInst<
2135(outs DoubleRegs:$Rxx32),
2136(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2137"$Rxx32 += vraddub($Rss32,$Rtt32)",
2138tc_d773585a, TypeM>, Enc_88c16c {
2139let Inst{7-5} = 0b001;
2140let Inst{13-13} = 0b0;
2141let Inst{31-21} = 0b11101010010;
2142let prefersSlot3 = 1;
2143let Constraints = "$Rxx32 = $Rxx32in";
2144}
2145def A2_vrsadub : HInst<
2146(outs DoubleRegs:$Rdd32),
2147(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2148"$Rdd32 = vrsadub($Rss32,$Rtt32)",
2149tc_bafaade3, TypeM>, Enc_a56825 {
2150let Inst{7-5} = 0b010;
2151let Inst{13-13} = 0b0;
2152let Inst{31-21} = 0b11101000010;
2153let prefersSlot3 = 1;
2154}
2155def A2_vrsadub_acc : HInst<
2156(outs DoubleRegs:$Rxx32),
2157(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2158"$Rxx32 += vrsadub($Rss32,$Rtt32)",
2159tc_d773585a, TypeM>, Enc_88c16c {
2160let Inst{7-5} = 0b010;
2161let Inst{13-13} = 0b0;
2162let Inst{31-21} = 0b11101010010;
2163let prefersSlot3 = 1;
2164let Constraints = "$Rxx32 = $Rxx32in";
2165}
2166def A2_vsubb_map : HInst<
2167(outs DoubleRegs:$Rdd32),
2168(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2169"$Rdd32 = vsubb($Rss32,$Rtt32)",
2170tc_946df596, TypeMAPPING> {
2171let isPseudo = 1;
2172let isCodeGenOnly = 1;
2173}
2174def A2_vsubh : HInst<
2175(outs DoubleRegs:$Rdd32),
2176(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2177"$Rdd32 = vsubh($Rtt32,$Rss32)",
2178tc_946df596, TypeALU64>, Enc_ea23e4 {
2179let Inst{7-5} = 0b010;
2180let Inst{13-13} = 0b0;
2181let Inst{31-21} = 0b11010011001;
2182}
2183def A2_vsubhs : HInst<
2184(outs DoubleRegs:$Rdd32),
2185(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2186"$Rdd32 = vsubh($Rtt32,$Rss32):sat",
2187tc_779080bf, TypeALU64>, Enc_ea23e4 {
2188let Inst{7-5} = 0b011;
2189let Inst{13-13} = 0b0;
2190let Inst{31-21} = 0b11010011001;
2191let prefersSlot3 = 1;
2192let Defs = [USR_OVF];
2193}
2194def A2_vsubub : HInst<
2195(outs DoubleRegs:$Rdd32),
2196(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2197"$Rdd32 = vsubub($Rtt32,$Rss32)",
2198tc_946df596, TypeALU64>, Enc_ea23e4 {
2199let Inst{7-5} = 0b000;
2200let Inst{13-13} = 0b0;
2201let Inst{31-21} = 0b11010011001;
2202}
2203def A2_vsububs : HInst<
2204(outs DoubleRegs:$Rdd32),
2205(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2206"$Rdd32 = vsubub($Rtt32,$Rss32):sat",
2207tc_779080bf, TypeALU64>, Enc_ea23e4 {
2208let Inst{7-5} = 0b001;
2209let Inst{13-13} = 0b0;
2210let Inst{31-21} = 0b11010011001;
2211let prefersSlot3 = 1;
2212let Defs = [USR_OVF];
2213}
2214def A2_vsubuhs : HInst<
2215(outs DoubleRegs:$Rdd32),
2216(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2217"$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
2218tc_779080bf, TypeALU64>, Enc_ea23e4 {
2219let Inst{7-5} = 0b100;
2220let Inst{13-13} = 0b0;
2221let Inst{31-21} = 0b11010011001;
2222let prefersSlot3 = 1;
2223let Defs = [USR_OVF];
2224}
2225def A2_vsubw : HInst<
2226(outs DoubleRegs:$Rdd32),
2227(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2228"$Rdd32 = vsubw($Rtt32,$Rss32)",
2229tc_946df596, TypeALU64>, Enc_ea23e4 {
2230let Inst{7-5} = 0b101;
2231let Inst{13-13} = 0b0;
2232let Inst{31-21} = 0b11010011001;
2233}
2234def A2_vsubws : HInst<
2235(outs DoubleRegs:$Rdd32),
2236(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2237"$Rdd32 = vsubw($Rtt32,$Rss32):sat",
2238tc_779080bf, TypeALU64>, Enc_ea23e4 {
2239let Inst{7-5} = 0b110;
2240let Inst{13-13} = 0b0;
2241let Inst{31-21} = 0b11010011001;
2242let prefersSlot3 = 1;
2243let Defs = [USR_OVF];
2244}
2245def A2_xor : HInst<
2246(outs IntRegs:$Rd32),
2247(ins IntRegs:$Rs32, IntRegs:$Rt32),
2248"$Rd32 = xor($Rs32,$Rt32)",
2249tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
2250let Inst{7-5} = 0b000;
2251let Inst{13-13} = 0b0;
2252let Inst{31-21} = 0b11110001011;
2253let hasNewValue = 1;
2254let opNewValue = 0;
2255let InputType = "reg";
2256let BaseOpcode = "A2_xor";
2257let isCommutable = 1;
2258let isPredicable = 1;
2259}
2260def A2_xorp : HInst<
2261(outs DoubleRegs:$Rdd32),
2262(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2263"$Rdd32 = xor($Rss32,$Rtt32)",
2264tc_946df596, TypeALU64>, Enc_a56825 {
2265let Inst{7-5} = 0b100;
2266let Inst{13-13} = 0b0;
2267let Inst{31-21} = 0b11010011111;
2268let isCommutable = 1;
2269}
2270def A2_zxtb : HInst<
2271(outs IntRegs:$Rd32),
2272(ins IntRegs:$Rs32),
2273"$Rd32 = zxtb($Rs32)",
2274tc_5a2711e5, TypeALU32_2op>, PredNewRel {
2275let hasNewValue = 1;
2276let opNewValue = 0;
2277let BaseOpcode = "A2_zxtb";
2278let isPredicable = 1;
2279let isPseudo = 1;
2280let isCodeGenOnly = 1;
2281}
2282def A2_zxth : HInst<
2283(outs IntRegs:$Rd32),
2284(ins IntRegs:$Rs32),
2285"$Rd32 = zxth($Rs32)",
2286tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel {
2287let Inst{13-5} = 0b000000000;
2288let Inst{31-21} = 0b01110000110;
2289let hasNewValue = 1;
2290let opNewValue = 0;
2291let BaseOpcode = "A2_zxth";
2292let isPredicable = 1;
2293}
2294def A4_addp_c : HInst<
2295(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
2296(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
2297"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
2298tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 {
2299let Inst{7-7} = 0b0;
2300let Inst{13-13} = 0b0;
2301let Inst{31-21} = 0b11000010110;
2302let isPredicateLate = 1;
2303let Constraints = "$Px4 = $Px4in";
2304}
2305def A4_andn : HInst<
2306(outs IntRegs:$Rd32),
2307(ins IntRegs:$Rt32, IntRegs:$Rs32),
2308"$Rd32 = and($Rt32,~$Rs32)",
2309tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 {
2310let Inst{7-5} = 0b000;
2311let Inst{13-13} = 0b0;
2312let Inst{31-21} = 0b11110001100;
2313let hasNewValue = 1;
2314let opNewValue = 0;
2315let InputType = "reg";
2316}
2317def A4_andnp : HInst<
2318(outs DoubleRegs:$Rdd32),
2319(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2320"$Rdd32 = and($Rtt32,~$Rss32)",
2321tc_946df596, TypeALU64>, Enc_ea23e4 {
2322let Inst{7-5} = 0b001;
2323let Inst{13-13} = 0b0;
2324let Inst{31-21} = 0b11010011111;
2325}
2326def A4_bitsplit : HInst<
2327(outs DoubleRegs:$Rdd32),
2328(ins IntRegs:$Rs32, IntRegs:$Rt32),
2329"$Rdd32 = bitsplit($Rs32,$Rt32)",
2330tc_4414d8b1, TypeALU64>, Enc_be32a5 {
2331let Inst{7-5} = 0b000;
2332let Inst{13-13} = 0b0;
2333let Inst{31-21} = 0b11010100001;
2334let prefersSlot3 = 1;
2335}
2336def A4_bitspliti : HInst<
2337(outs DoubleRegs:$Rdd32),
2338(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2339"$Rdd32 = bitsplit($Rs32,#$Ii)",
2340tc_4414d8b1, TypeS_2op>, Enc_311abd {
2341let Inst{7-5} = 0b100;
2342let Inst{13-13} = 0b0;
2343let Inst{31-21} = 0b10001000110;
2344let prefersSlot3 = 1;
2345}
2346def A4_boundscheck : HInst<
2347(outs PredRegs:$Pd4),
2348(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
2349"$Pd4 = boundscheck($Rs32,$Rtt32)",
2350tc_85d5d03f, TypeALU64> {
2351let isPseudo = 1;
2352}
2353def A4_boundscheck_hi : HInst<
2354(outs PredRegs:$Pd4),
2355(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2356"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
2357tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
2358let Inst{7-2} = 0b101000;
2359let Inst{13-13} = 0b1;
2360let Inst{31-21} = 0b11010010000;
2361}
2362def A4_boundscheck_lo : HInst<
2363(outs PredRegs:$Pd4),
2364(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2365"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
2366tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
2367let Inst{7-2} = 0b100000;
2368let Inst{13-13} = 0b1;
2369let Inst{31-21} = 0b11010010000;
2370}
2371def A4_cmpbeq : HInst<
2372(outs PredRegs:$Pd4),
2373(ins IntRegs:$Rs32, IntRegs:$Rt32),
2374"$Pd4 = cmpb.eq($Rs32,$Rt32)",
2375tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2376let Inst{7-2} = 0b110000;
2377let Inst{13-13} = 0b0;
2378let Inst{31-21} = 0b11000111110;
2379let CextOpcode = "A4_cmpbeq";
2380let InputType = "reg";
2381let isCommutable = 1;
2382let isCompare = 1;
2383}
2384def A4_cmpbeqi : HInst<
2385(outs PredRegs:$Pd4),
2386(ins IntRegs:$Rs32, u8_0Imm:$Ii),
2387"$Pd4 = cmpb.eq($Rs32,#$Ii)",
2388tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel {
2389let Inst{4-2} = 0b000;
2390let Inst{13-13} = 0b0;
2391let Inst{31-21} = 0b11011101000;
2392let CextOpcode = "A4_cmpbeq";
2393let InputType = "imm";
2394let isCommutable = 1;
2395let isCompare = 1;
2396}
2397def A4_cmpbgt : HInst<
2398(outs PredRegs:$Pd4),
2399(ins IntRegs:$Rs32, IntRegs:$Rt32),
2400"$Pd4 = cmpb.gt($Rs32,$Rt32)",
2401tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2402let Inst{7-2} = 0b010000;
2403let Inst{13-13} = 0b0;
2404let Inst{31-21} = 0b11000111110;
2405let CextOpcode = "A4_cmpbgt";
2406let InputType = "reg";
2407let isCompare = 1;
2408}
2409def A4_cmpbgti : HInst<
2410(outs PredRegs:$Pd4),
2411(ins IntRegs:$Rs32, s8_0Imm:$Ii),
2412"$Pd4 = cmpb.gt($Rs32,#$Ii)",
2413tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel {
2414let Inst{4-2} = 0b000;
2415let Inst{13-13} = 0b0;
2416let Inst{31-21} = 0b11011101001;
2417let CextOpcode = "A4_cmpbgt";
2418let InputType = "imm";
2419let isCompare = 1;
2420}
2421def A4_cmpbgtu : HInst<
2422(outs PredRegs:$Pd4),
2423(ins IntRegs:$Rs32, IntRegs:$Rt32),
2424"$Pd4 = cmpb.gtu($Rs32,$Rt32)",
2425tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2426let Inst{7-2} = 0b111000;
2427let Inst{13-13} = 0b0;
2428let Inst{31-21} = 0b11000111110;
2429let CextOpcode = "A4_cmpbgtu";
2430let InputType = "reg";
2431let isCompare = 1;
2432}
2433def A4_cmpbgtui : HInst<
2434(outs PredRegs:$Pd4),
2435(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2436"$Pd4 = cmpb.gtu($Rs32,#$Ii)",
2437tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel {
2438let Inst{4-2} = 0b000;
2439let Inst{13-12} = 0b00;
2440let Inst{31-21} = 0b11011101010;
2441let CextOpcode = "A4_cmpbgtu";
2442let InputType = "imm";
2443let isCompare = 1;
2444let isExtendable = 1;
2445let opExtendable = 2;
2446let isExtentSigned = 0;
2447let opExtentBits = 7;
2448let opExtentAlign = 0;
2449}
2450def A4_cmpheq : HInst<
2451(outs PredRegs:$Pd4),
2452(ins IntRegs:$Rs32, IntRegs:$Rt32),
2453"$Pd4 = cmph.eq($Rs32,$Rt32)",
2454tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2455let Inst{7-2} = 0b011000;
2456let Inst{13-13} = 0b0;
2457let Inst{31-21} = 0b11000111110;
2458let CextOpcode = "A4_cmpheq";
2459let InputType = "reg";
2460let isCommutable = 1;
2461let isCompare = 1;
2462}
2463def A4_cmpheqi : HInst<
2464(outs PredRegs:$Pd4),
2465(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2466"$Pd4 = cmph.eq($Rs32,#$Ii)",
2467tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel {
2468let Inst{4-2} = 0b010;
2469let Inst{13-13} = 0b0;
2470let Inst{31-21} = 0b11011101000;
2471let CextOpcode = "A4_cmpheq";
2472let InputType = "imm";
2473let isCommutable = 1;
2474let isCompare = 1;
2475let isExtendable = 1;
2476let opExtendable = 2;
2477let isExtentSigned = 1;
2478let opExtentBits = 8;
2479let opExtentAlign = 0;
2480}
2481def A4_cmphgt : HInst<
2482(outs PredRegs:$Pd4),
2483(ins IntRegs:$Rs32, IntRegs:$Rt32),
2484"$Pd4 = cmph.gt($Rs32,$Rt32)",
2485tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2486let Inst{7-2} = 0b100000;
2487let Inst{13-13} = 0b0;
2488let Inst{31-21} = 0b11000111110;
2489let CextOpcode = "A4_cmphgt";
2490let InputType = "reg";
2491let isCompare = 1;
2492}
2493def A4_cmphgti : HInst<
2494(outs PredRegs:$Pd4),
2495(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2496"$Pd4 = cmph.gt($Rs32,#$Ii)",
2497tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel {
2498let Inst{4-2} = 0b010;
2499let Inst{13-13} = 0b0;
2500let Inst{31-21} = 0b11011101001;
2501let CextOpcode = "A4_cmphgt";
2502let InputType = "imm";
2503let isCompare = 1;
2504let isExtendable = 1;
2505let opExtendable = 2;
2506let isExtentSigned = 1;
2507let opExtentBits = 8;
2508let opExtentAlign = 0;
2509}
2510def A4_cmphgtu : HInst<
2511(outs PredRegs:$Pd4),
2512(ins IntRegs:$Rs32, IntRegs:$Rt32),
2513"$Pd4 = cmph.gtu($Rs32,$Rt32)",
2514tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2515let Inst{7-2} = 0b101000;
2516let Inst{13-13} = 0b0;
2517let Inst{31-21} = 0b11000111110;
2518let CextOpcode = "A4_cmphgtu";
2519let InputType = "reg";
2520let isCompare = 1;
2521}
2522def A4_cmphgtui : HInst<
2523(outs PredRegs:$Pd4),
2524(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2525"$Pd4 = cmph.gtu($Rs32,#$Ii)",
2526tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel {
2527let Inst{4-2} = 0b010;
2528let Inst{13-12} = 0b00;
2529let Inst{31-21} = 0b11011101010;
2530let CextOpcode = "A4_cmphgtu";
2531let InputType = "imm";
2532let isCompare = 1;
2533let isExtendable = 1;
2534let opExtendable = 2;
2535let isExtentSigned = 0;
2536let opExtentBits = 7;
2537let opExtentAlign = 0;
2538}
2539def A4_combineii : HInst<
2540(outs DoubleRegs:$Rdd32),
2541(ins s8_0Imm:$Ii, u32_0Imm:$II),
2542"$Rdd32 = combine(#$Ii,#$II)",
2543tc_5a2711e5, TypeALU32_2op>, Enc_f0cca7 {
2544let Inst{31-21} = 0b01111100100;
2545let isExtendable = 1;
2546let opExtendable = 2;
2547let isExtentSigned = 0;
2548let opExtentBits = 6;
2549let opExtentAlign = 0;
2550}
2551def A4_combineir : HInst<
2552(outs DoubleRegs:$Rdd32),
2553(ins s32_0Imm:$Ii, IntRegs:$Rs32),
2554"$Rdd32 = combine(#$Ii,$Rs32)",
2555tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 {
2556let Inst{13-13} = 0b1;
2557let Inst{31-21} = 0b01110011001;
2558let isExtendable = 1;
2559let opExtendable = 1;
2560let isExtentSigned = 1;
2561let opExtentBits = 8;
2562let opExtentAlign = 0;
2563}
2564def A4_combineri : HInst<
2565(outs DoubleRegs:$Rdd32),
2566(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2567"$Rdd32 = combine($Rs32,#$Ii)",
2568tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 {
2569let Inst{13-13} = 0b1;
2570let Inst{31-21} = 0b01110011000;
2571let isExtendable = 1;
2572let opExtendable = 2;
2573let isExtentSigned = 1;
2574let opExtentBits = 8;
2575let opExtentAlign = 0;
2576}
2577def A4_cround_ri : HInst<
2578(outs IntRegs:$Rd32),
2579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2580"$Rd32 = cround($Rs32,#$Ii)",
2581tc_002cb246, TypeS_2op>, Enc_a05677 {
2582let Inst{7-5} = 0b000;
2583let Inst{13-13} = 0b0;
2584let Inst{31-21} = 0b10001100111;
2585let hasNewValue = 1;
2586let opNewValue = 0;
2587let prefersSlot3 = 1;
2588}
2589def A4_cround_rr : HInst<
2590(outs IntRegs:$Rd32),
2591(ins IntRegs:$Rs32, IntRegs:$Rt32),
2592"$Rd32 = cround($Rs32,$Rt32)",
2593tc_002cb246, TypeS_3op>, Enc_5ab2be {
2594let Inst{7-5} = 0b000;
2595let Inst{13-13} = 0b0;
2596let Inst{31-21} = 0b11000110110;
2597let hasNewValue = 1;
2598let opNewValue = 0;
2599let prefersSlot3 = 1;
2600}
2601def A4_ext : HInst<
2602(outs),
2603(ins u26_6Imm:$Ii),
2604"immext(#$Ii)",
2605tc_862b3e70, TypeEXTENDER>, Enc_2b518f {
2606let Inst{31-28} = 0b0000;
2607}
2608def A4_modwrapu : HInst<
2609(outs IntRegs:$Rd32),
2610(ins IntRegs:$Rs32, IntRegs:$Rt32),
2611"$Rd32 = modwrap($Rs32,$Rt32)",
2612tc_779080bf, TypeALU64>, Enc_5ab2be {
2613let Inst{7-5} = 0b111;
2614let Inst{13-13} = 0b0;
2615let Inst{31-21} = 0b11010011111;
2616let hasNewValue = 1;
2617let opNewValue = 0;
2618let prefersSlot3 = 1;
2619}
2620def A4_orn : HInst<
2621(outs IntRegs:$Rd32),
2622(ins IntRegs:$Rt32, IntRegs:$Rs32),
2623"$Rd32 = or($Rt32,~$Rs32)",
2624tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 {
2625let Inst{7-5} = 0b000;
2626let Inst{13-13} = 0b0;
2627let Inst{31-21} = 0b11110001101;
2628let hasNewValue = 1;
2629let opNewValue = 0;
2630let InputType = "reg";
2631}
2632def A4_ornp : HInst<
2633(outs DoubleRegs:$Rdd32),
2634(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2635"$Rdd32 = or($Rtt32,~$Rss32)",
2636tc_946df596, TypeALU64>, Enc_ea23e4 {
2637let Inst{7-5} = 0b011;
2638let Inst{13-13} = 0b0;
2639let Inst{31-21} = 0b11010011111;
2640}
2641def A4_paslhf : HInst<
2642(outs IntRegs:$Rd32),
2643(ins PredRegs:$Pu4, IntRegs:$Rs32),
2644"if (!$Pu4) $Rd32 = aslh($Rs32)",
2645tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2646let Inst{7-5} = 0b000;
2647let Inst{13-10} = 0b1010;
2648let Inst{31-21} = 0b01110000000;
2649let isPredicated = 1;
2650let isPredicatedFalse = 1;
2651let hasNewValue = 1;
2652let opNewValue = 0;
2653let BaseOpcode = "A2_aslh";
2654}
2655def A4_paslhfnew : HInst<
2656(outs IntRegs:$Rd32),
2657(ins PredRegs:$Pu4, IntRegs:$Rs32),
2658"if (!$Pu4.new) $Rd32 = aslh($Rs32)",
2659tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2660let Inst{7-5} = 0b000;
2661let Inst{13-10} = 0b1011;
2662let Inst{31-21} = 0b01110000000;
2663let isPredicated = 1;
2664let isPredicatedFalse = 1;
2665let hasNewValue = 1;
2666let opNewValue = 0;
2667let isPredicatedNew = 1;
2668let BaseOpcode = "A2_aslh";
2669}
2670def A4_paslht : HInst<
2671(outs IntRegs:$Rd32),
2672(ins PredRegs:$Pu4, IntRegs:$Rs32),
2673"if ($Pu4) $Rd32 = aslh($Rs32)",
2674tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2675let Inst{7-5} = 0b000;
2676let Inst{13-10} = 0b1000;
2677let Inst{31-21} = 0b01110000000;
2678let isPredicated = 1;
2679let hasNewValue = 1;
2680let opNewValue = 0;
2681let BaseOpcode = "A2_aslh";
2682}
2683def A4_paslhtnew : HInst<
2684(outs IntRegs:$Rd32),
2685(ins PredRegs:$Pu4, IntRegs:$Rs32),
2686"if ($Pu4.new) $Rd32 = aslh($Rs32)",
2687tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2688let Inst{7-5} = 0b000;
2689let Inst{13-10} = 0b1001;
2690let Inst{31-21} = 0b01110000000;
2691let isPredicated = 1;
2692let hasNewValue = 1;
2693let opNewValue = 0;
2694let isPredicatedNew = 1;
2695let BaseOpcode = "A2_aslh";
2696}
2697def A4_pasrhf : HInst<
2698(outs IntRegs:$Rd32),
2699(ins PredRegs:$Pu4, IntRegs:$Rs32),
2700"if (!$Pu4) $Rd32 = asrh($Rs32)",
2701tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2702let Inst{7-5} = 0b000;
2703let Inst{13-10} = 0b1010;
2704let Inst{31-21} = 0b01110000001;
2705let isPredicated = 1;
2706let isPredicatedFalse = 1;
2707let hasNewValue = 1;
2708let opNewValue = 0;
2709let BaseOpcode = "A2_asrh";
2710}
2711def A4_pasrhfnew : HInst<
2712(outs IntRegs:$Rd32),
2713(ins PredRegs:$Pu4, IntRegs:$Rs32),
2714"if (!$Pu4.new) $Rd32 = asrh($Rs32)",
2715tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2716let Inst{7-5} = 0b000;
2717let Inst{13-10} = 0b1011;
2718let Inst{31-21} = 0b01110000001;
2719let isPredicated = 1;
2720let isPredicatedFalse = 1;
2721let hasNewValue = 1;
2722let opNewValue = 0;
2723let isPredicatedNew = 1;
2724let BaseOpcode = "A2_asrh";
2725}
2726def A4_pasrht : HInst<
2727(outs IntRegs:$Rd32),
2728(ins PredRegs:$Pu4, IntRegs:$Rs32),
2729"if ($Pu4) $Rd32 = asrh($Rs32)",
2730tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2731let Inst{7-5} = 0b000;
2732let Inst{13-10} = 0b1000;
2733let Inst{31-21} = 0b01110000001;
2734let isPredicated = 1;
2735let hasNewValue = 1;
2736let opNewValue = 0;
2737let BaseOpcode = "A2_asrh";
2738}
2739def A4_pasrhtnew : HInst<
2740(outs IntRegs:$Rd32),
2741(ins PredRegs:$Pu4, IntRegs:$Rs32),
2742"if ($Pu4.new) $Rd32 = asrh($Rs32)",
2743tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2744let Inst{7-5} = 0b000;
2745let Inst{13-10} = 0b1001;
2746let Inst{31-21} = 0b01110000001;
2747let isPredicated = 1;
2748let hasNewValue = 1;
2749let opNewValue = 0;
2750let isPredicatedNew = 1;
2751let BaseOpcode = "A2_asrh";
2752}
2753def A4_psxtbf : HInst<
2754(outs IntRegs:$Rd32),
2755(ins PredRegs:$Pu4, IntRegs:$Rs32),
2756"if (!$Pu4) $Rd32 = sxtb($Rs32)",
2757tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2758let Inst{7-5} = 0b000;
2759let Inst{13-10} = 0b1010;
2760let Inst{31-21} = 0b01110000101;
2761let isPredicated = 1;
2762let isPredicatedFalse = 1;
2763let hasNewValue = 1;
2764let opNewValue = 0;
2765let BaseOpcode = "A2_sxtb";
2766}
2767def A4_psxtbfnew : HInst<
2768(outs IntRegs:$Rd32),
2769(ins PredRegs:$Pu4, IntRegs:$Rs32),
2770"if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
2771tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2772let Inst{7-5} = 0b000;
2773let Inst{13-10} = 0b1011;
2774let Inst{31-21} = 0b01110000101;
2775let isPredicated = 1;
2776let isPredicatedFalse = 1;
2777let hasNewValue = 1;
2778let opNewValue = 0;
2779let isPredicatedNew = 1;
2780let BaseOpcode = "A2_sxtb";
2781}
2782def A4_psxtbt : HInst<
2783(outs IntRegs:$Rd32),
2784(ins PredRegs:$Pu4, IntRegs:$Rs32),
2785"if ($Pu4) $Rd32 = sxtb($Rs32)",
2786tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2787let Inst{7-5} = 0b000;
2788let Inst{13-10} = 0b1000;
2789let Inst{31-21} = 0b01110000101;
2790let isPredicated = 1;
2791let hasNewValue = 1;
2792let opNewValue = 0;
2793let BaseOpcode = "A2_sxtb";
2794}
2795def A4_psxtbtnew : HInst<
2796(outs IntRegs:$Rd32),
2797(ins PredRegs:$Pu4, IntRegs:$Rs32),
2798"if ($Pu4.new) $Rd32 = sxtb($Rs32)",
2799tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2800let Inst{7-5} = 0b000;
2801let Inst{13-10} = 0b1001;
2802let Inst{31-21} = 0b01110000101;
2803let isPredicated = 1;
2804let hasNewValue = 1;
2805let opNewValue = 0;
2806let isPredicatedNew = 1;
2807let BaseOpcode = "A2_sxtb";
2808}
2809def A4_psxthf : HInst<
2810(outs IntRegs:$Rd32),
2811(ins PredRegs:$Pu4, IntRegs:$Rs32),
2812"if (!$Pu4) $Rd32 = sxth($Rs32)",
2813tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2814let Inst{7-5} = 0b000;
2815let Inst{13-10} = 0b1010;
2816let Inst{31-21} = 0b01110000111;
2817let isPredicated = 1;
2818let isPredicatedFalse = 1;
2819let hasNewValue = 1;
2820let opNewValue = 0;
2821let BaseOpcode = "A2_sxth";
2822}
2823def A4_psxthfnew : HInst<
2824(outs IntRegs:$Rd32),
2825(ins PredRegs:$Pu4, IntRegs:$Rs32),
2826"if (!$Pu4.new) $Rd32 = sxth($Rs32)",
2827tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2828let Inst{7-5} = 0b000;
2829let Inst{13-10} = 0b1011;
2830let Inst{31-21} = 0b01110000111;
2831let isPredicated = 1;
2832let isPredicatedFalse = 1;
2833let hasNewValue = 1;
2834let opNewValue = 0;
2835let isPredicatedNew = 1;
2836let BaseOpcode = "A2_sxth";
2837}
2838def A4_psxtht : HInst<
2839(outs IntRegs:$Rd32),
2840(ins PredRegs:$Pu4, IntRegs:$Rs32),
2841"if ($Pu4) $Rd32 = sxth($Rs32)",
2842tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2843let Inst{7-5} = 0b000;
2844let Inst{13-10} = 0b1000;
2845let Inst{31-21} = 0b01110000111;
2846let isPredicated = 1;
2847let hasNewValue = 1;
2848let opNewValue = 0;
2849let BaseOpcode = "A2_sxth";
2850}
2851def A4_psxthtnew : HInst<
2852(outs IntRegs:$Rd32),
2853(ins PredRegs:$Pu4, IntRegs:$Rs32),
2854"if ($Pu4.new) $Rd32 = sxth($Rs32)",
2855tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2856let Inst{7-5} = 0b000;
2857let Inst{13-10} = 0b1001;
2858let Inst{31-21} = 0b01110000111;
2859let isPredicated = 1;
2860let hasNewValue = 1;
2861let opNewValue = 0;
2862let isPredicatedNew = 1;
2863let BaseOpcode = "A2_sxth";
2864}
2865def A4_pzxtbf : HInst<
2866(outs IntRegs:$Rd32),
2867(ins PredRegs:$Pu4, IntRegs:$Rs32),
2868"if (!$Pu4) $Rd32 = zxtb($Rs32)",
2869tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2870let Inst{7-5} = 0b000;
2871let Inst{13-10} = 0b1010;
2872let Inst{31-21} = 0b01110000100;
2873let isPredicated = 1;
2874let isPredicatedFalse = 1;
2875let hasNewValue = 1;
2876let opNewValue = 0;
2877let BaseOpcode = "A2_zxtb";
2878}
2879def A4_pzxtbfnew : HInst<
2880(outs IntRegs:$Rd32),
2881(ins PredRegs:$Pu4, IntRegs:$Rs32),
2882"if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
2883tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2884let Inst{7-5} = 0b000;
2885let Inst{13-10} = 0b1011;
2886let Inst{31-21} = 0b01110000100;
2887let isPredicated = 1;
2888let isPredicatedFalse = 1;
2889let hasNewValue = 1;
2890let opNewValue = 0;
2891let isPredicatedNew = 1;
2892let BaseOpcode = "A2_zxtb";
2893}
2894def A4_pzxtbt : HInst<
2895(outs IntRegs:$Rd32),
2896(ins PredRegs:$Pu4, IntRegs:$Rs32),
2897"if ($Pu4) $Rd32 = zxtb($Rs32)",
2898tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2899let Inst{7-5} = 0b000;
2900let Inst{13-10} = 0b1000;
2901let Inst{31-21} = 0b01110000100;
2902let isPredicated = 1;
2903let hasNewValue = 1;
2904let opNewValue = 0;
2905let BaseOpcode = "A2_zxtb";
2906}
2907def A4_pzxtbtnew : HInst<
2908(outs IntRegs:$Rd32),
2909(ins PredRegs:$Pu4, IntRegs:$Rs32),
2910"if ($Pu4.new) $Rd32 = zxtb($Rs32)",
2911tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2912let Inst{7-5} = 0b000;
2913let Inst{13-10} = 0b1001;
2914let Inst{31-21} = 0b01110000100;
2915let isPredicated = 1;
2916let hasNewValue = 1;
2917let opNewValue = 0;
2918let isPredicatedNew = 1;
2919let BaseOpcode = "A2_zxtb";
2920}
2921def A4_pzxthf : HInst<
2922(outs IntRegs:$Rd32),
2923(ins PredRegs:$Pu4, IntRegs:$Rs32),
2924"if (!$Pu4) $Rd32 = zxth($Rs32)",
2925tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2926let Inst{7-5} = 0b000;
2927let Inst{13-10} = 0b1010;
2928let Inst{31-21} = 0b01110000110;
2929let isPredicated = 1;
2930let isPredicatedFalse = 1;
2931let hasNewValue = 1;
2932let opNewValue = 0;
2933let BaseOpcode = "A2_zxth";
2934}
2935def A4_pzxthfnew : HInst<
2936(outs IntRegs:$Rd32),
2937(ins PredRegs:$Pu4, IntRegs:$Rs32),
2938"if (!$Pu4.new) $Rd32 = zxth($Rs32)",
2939tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2940let Inst{7-5} = 0b000;
2941let Inst{13-10} = 0b1011;
2942let Inst{31-21} = 0b01110000110;
2943let isPredicated = 1;
2944let isPredicatedFalse = 1;
2945let hasNewValue = 1;
2946let opNewValue = 0;
2947let isPredicatedNew = 1;
2948let BaseOpcode = "A2_zxth";
2949}
2950def A4_pzxtht : HInst<
2951(outs IntRegs:$Rd32),
2952(ins PredRegs:$Pu4, IntRegs:$Rs32),
2953"if ($Pu4) $Rd32 = zxth($Rs32)",
2954tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2955let Inst{7-5} = 0b000;
2956let Inst{13-10} = 0b1000;
2957let Inst{31-21} = 0b01110000110;
2958let isPredicated = 1;
2959let hasNewValue = 1;
2960let opNewValue = 0;
2961let BaseOpcode = "A2_zxth";
2962}
2963def A4_pzxthtnew : HInst<
2964(outs IntRegs:$Rd32),
2965(ins PredRegs:$Pu4, IntRegs:$Rs32),
2966"if ($Pu4.new) $Rd32 = zxth($Rs32)",
2967tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2968let Inst{7-5} = 0b000;
2969let Inst{13-10} = 0b1001;
2970let Inst{31-21} = 0b01110000110;
2971let isPredicated = 1;
2972let hasNewValue = 1;
2973let opNewValue = 0;
2974let isPredicatedNew = 1;
2975let BaseOpcode = "A2_zxth";
2976}
2977def A4_rcmpeq : HInst<
2978(outs IntRegs:$Rd32),
2979(ins IntRegs:$Rs32, IntRegs:$Rt32),
2980"$Rd32 = cmp.eq($Rs32,$Rt32)",
2981tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
2982let Inst{7-5} = 0b000;
2983let Inst{13-13} = 0b0;
2984let Inst{31-21} = 0b11110011010;
2985let hasNewValue = 1;
2986let opNewValue = 0;
2987let CextOpcode = "A4_rcmpeq";
2988let InputType = "reg";
2989let isCommutable = 1;
2990}
2991def A4_rcmpeqi : HInst<
2992(outs IntRegs:$Rd32),
2993(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2994"$Rd32 = cmp.eq($Rs32,#$Ii)",
2995tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
2996let Inst{13-13} = 0b1;
2997let Inst{31-21} = 0b01110011010;
2998let hasNewValue = 1;
2999let opNewValue = 0;
3000let CextOpcode = "A4_rcmpeqi";
3001let InputType = "imm";
3002let isExtendable = 1;
3003let opExtendable = 2;
3004let isExtentSigned = 1;
3005let opExtentBits = 8;
3006let opExtentAlign = 0;
3007}
3008def A4_rcmpneq : HInst<
3009(outs IntRegs:$Rd32),
3010(ins IntRegs:$Rs32, IntRegs:$Rt32),
3011"$Rd32 = !cmp.eq($Rs32,$Rt32)",
3012tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
3013let Inst{7-5} = 0b000;
3014let Inst{13-13} = 0b0;
3015let Inst{31-21} = 0b11110011011;
3016let hasNewValue = 1;
3017let opNewValue = 0;
3018let CextOpcode = "A4_rcmpneq";
3019let InputType = "reg";
3020let isCommutable = 1;
3021}
3022def A4_rcmpneqi : HInst<
3023(outs IntRegs:$Rd32),
3024(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3025"$Rd32 = !cmp.eq($Rs32,#$Ii)",
3026tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
3027let Inst{13-13} = 0b1;
3028let Inst{31-21} = 0b01110011011;
3029let hasNewValue = 1;
3030let opNewValue = 0;
3031let CextOpcode = "A4_rcmpeqi";
3032let InputType = "imm";
3033let isExtendable = 1;
3034let opExtendable = 2;
3035let isExtentSigned = 1;
3036let opExtentBits = 8;
3037let opExtentAlign = 0;
3038}
3039def A4_round_ri : HInst<
3040(outs IntRegs:$Rd32),
3041(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3042"$Rd32 = round($Rs32,#$Ii)",
3043tc_002cb246, TypeS_2op>, Enc_a05677 {
3044let Inst{7-5} = 0b100;
3045let Inst{13-13} = 0b0;
3046let Inst{31-21} = 0b10001100111;
3047let hasNewValue = 1;
3048let opNewValue = 0;
3049let prefersSlot3 = 1;
3050}
3051def A4_round_ri_sat : HInst<
3052(outs IntRegs:$Rd32),
3053(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3054"$Rd32 = round($Rs32,#$Ii):sat",
3055tc_002cb246, TypeS_2op>, Enc_a05677 {
3056let Inst{7-5} = 0b110;
3057let Inst{13-13} = 0b0;
3058let Inst{31-21} = 0b10001100111;
3059let hasNewValue = 1;
3060let opNewValue = 0;
3061let prefersSlot3 = 1;
3062let Defs = [USR_OVF];
3063}
3064def A4_round_rr : HInst<
3065(outs IntRegs:$Rd32),
3066(ins IntRegs:$Rs32, IntRegs:$Rt32),
3067"$Rd32 = round($Rs32,$Rt32)",
3068tc_002cb246, TypeS_3op>, Enc_5ab2be {
3069let Inst{7-5} = 0b100;
3070let Inst{13-13} = 0b0;
3071let Inst{31-21} = 0b11000110110;
3072let hasNewValue = 1;
3073let opNewValue = 0;
3074let prefersSlot3 = 1;
3075}
3076def A4_round_rr_sat : HInst<
3077(outs IntRegs:$Rd32),
3078(ins IntRegs:$Rs32, IntRegs:$Rt32),
3079"$Rd32 = round($Rs32,$Rt32):sat",
3080tc_002cb246, TypeS_3op>, Enc_5ab2be {
3081let Inst{7-5} = 0b110;
3082let Inst{13-13} = 0b0;
3083let Inst{31-21} = 0b11000110110;
3084let hasNewValue = 1;
3085let opNewValue = 0;
3086let prefersSlot3 = 1;
3087let Defs = [USR_OVF];
3088}
3089def A4_subp_c : HInst<
3090(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
3091(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
3092"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
3093tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 {
3094let Inst{7-7} = 0b0;
3095let Inst{13-13} = 0b0;
3096let Inst{31-21} = 0b11000010111;
3097let isPredicateLate = 1;
3098let Constraints = "$Px4 = $Px4in";
3099}
3100def A4_tfrcpp : HInst<
3101(outs DoubleRegs:$Rdd32),
3102(ins CtrRegs64:$Css32),
3103"$Rdd32 = $Css32",
3104tc_b9272d6c, TypeCR>, Enc_667b39 {
3105let Inst{13-5} = 0b000000000;
3106let Inst{31-21} = 0b01101000000;
3107}
3108def A4_tfrpcp : HInst<
3109(outs CtrRegs64:$Cdd32),
3110(ins DoubleRegs:$Rss32),
3111"$Cdd32 = $Rss32",
3112tc_434c8e1e, TypeCR>, Enc_0ed752 {
3113let Inst{13-5} = 0b000000000;
3114let Inst{31-21} = 0b01100011001;
3115}
3116def A4_tlbmatch : HInst<
3117(outs PredRegs:$Pd4),
3118(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3119"$Pd4 = tlbmatch($Rss32,$Rt32)",
3120tc_4837eefb, TypeALU64>, Enc_03833b {
3121let Inst{7-2} = 0b011000;
3122let Inst{13-13} = 0b1;
3123let Inst{31-21} = 0b11010010000;
3124let isPredicateLate = 1;
3125}
3126def A4_vcmpbeq_any : HInst<
3127(outs PredRegs:$Pd4),
3128(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3129"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
3130tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
3131let Inst{7-2} = 0b000000;
3132let Inst{13-13} = 0b1;
3133let Inst{31-21} = 0b11010010000;
3134}
3135def A4_vcmpbeqi : HInst<
3136(outs PredRegs:$Pd4),
3137(ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
3138"$Pd4 = vcmpb.eq($Rss32,#$Ii)",
3139tc_643b4717, TypeALU64>, Enc_0d8adb {
3140let Inst{4-2} = 0b000;
3141let Inst{13-13} = 0b0;
3142let Inst{31-21} = 0b11011100000;
3143}
3144def A4_vcmpbgt : HInst<
3145(outs PredRegs:$Pd4),
3146(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3147"$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
3148tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
3149let Inst{7-2} = 0b010000;
3150let Inst{13-13} = 0b1;
3151let Inst{31-21} = 0b11010010000;
3152}
3153def A4_vcmpbgti : HInst<
3154(outs PredRegs:$Pd4),
3155(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3156"$Pd4 = vcmpb.gt($Rss32,#$Ii)",
3157tc_643b4717, TypeALU64>, Enc_0d8adb {
3158let Inst{4-2} = 0b000;
3159let Inst{13-13} = 0b0;
3160let Inst{31-21} = 0b11011100001;
3161}
3162def A4_vcmpbgtui : HInst<
3163(outs PredRegs:$Pd4),
3164(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3165"$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
3166tc_643b4717, TypeALU64>, Enc_3680c2 {
3167let Inst{4-2} = 0b000;
3168let Inst{13-12} = 0b00;
3169let Inst{31-21} = 0b11011100010;
3170}
3171def A4_vcmpheqi : HInst<
3172(outs PredRegs:$Pd4),
3173(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3174"$Pd4 = vcmph.eq($Rss32,#$Ii)",
3175tc_643b4717, TypeALU64>, Enc_0d8adb {
3176let Inst{4-2} = 0b010;
3177let Inst{13-13} = 0b0;
3178let Inst{31-21} = 0b11011100000;
3179}
3180def A4_vcmphgti : HInst<
3181(outs PredRegs:$Pd4),
3182(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3183"$Pd4 = vcmph.gt($Rss32,#$Ii)",
3184tc_643b4717, TypeALU64>, Enc_0d8adb {
3185let Inst{4-2} = 0b010;
3186let Inst{13-13} = 0b0;
3187let Inst{31-21} = 0b11011100001;
3188}
3189def A4_vcmphgtui : HInst<
3190(outs PredRegs:$Pd4),
3191(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3192"$Pd4 = vcmph.gtu($Rss32,#$Ii)",
3193tc_643b4717, TypeALU64>, Enc_3680c2 {
3194let Inst{4-2} = 0b010;
3195let Inst{13-12} = 0b00;
3196let Inst{31-21} = 0b11011100010;
3197}
3198def A4_vcmpweqi : HInst<
3199(outs PredRegs:$Pd4),
3200(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3201"$Pd4 = vcmpw.eq($Rss32,#$Ii)",
3202tc_643b4717, TypeALU64>, Enc_0d8adb {
3203let Inst{4-2} = 0b100;
3204let Inst{13-13} = 0b0;
3205let Inst{31-21} = 0b11011100000;
3206}
3207def A4_vcmpwgti : HInst<
3208(outs PredRegs:$Pd4),
3209(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3210"$Pd4 = vcmpw.gt($Rss32,#$Ii)",
3211tc_643b4717, TypeALU64>, Enc_0d8adb {
3212let Inst{4-2} = 0b100;
3213let Inst{13-13} = 0b0;
3214let Inst{31-21} = 0b11011100001;
3215}
3216def A4_vcmpwgtui : HInst<
3217(outs PredRegs:$Pd4),
3218(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3219"$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
3220tc_643b4717, TypeALU64>, Enc_3680c2 {
3221let Inst{4-2} = 0b100;
3222let Inst{13-12} = 0b00;
3223let Inst{31-21} = 0b11011100010;
3224}
3225def A4_vrmaxh : HInst<
3226(outs DoubleRegs:$Rxx32),
3227(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3228"$Rxx32 = vrmaxh($Rss32,$Ru32)",
3229tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3230let Inst{7-5} = 0b001;
3231let Inst{13-13} = 0b0;
3232let Inst{31-21} = 0b11001011001;
3233let prefersSlot3 = 1;
3234let Constraints = "$Rxx32 = $Rxx32in";
3235}
3236def A4_vrmaxuh : HInst<
3237(outs DoubleRegs:$Rxx32),
3238(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3239"$Rxx32 = vrmaxuh($Rss32,$Ru32)",
3240tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3241let Inst{7-5} = 0b001;
3242let Inst{13-13} = 0b1;
3243let Inst{31-21} = 0b11001011001;
3244let prefersSlot3 = 1;
3245let Constraints = "$Rxx32 = $Rxx32in";
3246}
3247def A4_vrmaxuw : HInst<
3248(outs DoubleRegs:$Rxx32),
3249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3250"$Rxx32 = vrmaxuw($Rss32,$Ru32)",
3251tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3252let Inst{7-5} = 0b010;
3253let Inst{13-13} = 0b1;
3254let Inst{31-21} = 0b11001011001;
3255let prefersSlot3 = 1;
3256let Constraints = "$Rxx32 = $Rxx32in";
3257}
3258def A4_vrmaxw : HInst<
3259(outs DoubleRegs:$Rxx32),
3260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3261"$Rxx32 = vrmaxw($Rss32,$Ru32)",
3262tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3263let Inst{7-5} = 0b010;
3264let Inst{13-13} = 0b0;
3265let Inst{31-21} = 0b11001011001;
3266let prefersSlot3 = 1;
3267let Constraints = "$Rxx32 = $Rxx32in";
3268}
3269def A4_vrminh : HInst<
3270(outs DoubleRegs:$Rxx32),
3271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3272"$Rxx32 = vrminh($Rss32,$Ru32)",
3273tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3274let Inst{7-5} = 0b101;
3275let Inst{13-13} = 0b0;
3276let Inst{31-21} = 0b11001011001;
3277let prefersSlot3 = 1;
3278let Constraints = "$Rxx32 = $Rxx32in";
3279}
3280def A4_vrminuh : HInst<
3281(outs DoubleRegs:$Rxx32),
3282(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3283"$Rxx32 = vrminuh($Rss32,$Ru32)",
3284tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3285let Inst{7-5} = 0b101;
3286let Inst{13-13} = 0b1;
3287let Inst{31-21} = 0b11001011001;
3288let prefersSlot3 = 1;
3289let Constraints = "$Rxx32 = $Rxx32in";
3290}
3291def A4_vrminuw : HInst<
3292(outs DoubleRegs:$Rxx32),
3293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3294"$Rxx32 = vrminuw($Rss32,$Ru32)",
3295tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3296let Inst{7-5} = 0b110;
3297let Inst{13-13} = 0b1;
3298let Inst{31-21} = 0b11001011001;
3299let prefersSlot3 = 1;
3300let Constraints = "$Rxx32 = $Rxx32in";
3301}
3302def A4_vrminw : HInst<
3303(outs DoubleRegs:$Rxx32),
3304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3305"$Rxx32 = vrminw($Rss32,$Ru32)",
3306tc_5b54b33f, TypeS_3op>, Enc_412ff0 {
3307let Inst{7-5} = 0b110;
3308let Inst{13-13} = 0b0;
3309let Inst{31-21} = 0b11001011001;
3310let prefersSlot3 = 1;
3311let Constraints = "$Rxx32 = $Rxx32in";
3312}
3313def A5_ACS : HInst<
3314(outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
3315(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3316"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
3317tc_d1aa9eaa, TypeM>, Enc_831a7d, Requires<[HasV55]> {
3318let Inst{7-7} = 0b0;
3319let Inst{13-13} = 0b0;
3320let Inst{31-21} = 0b11101010101;
3321let isPredicateLate = 1;
3322let prefersSlot3 = 1;
3323let Defs = [USR_OVF];
3324let Constraints = "$Rxx32 = $Rxx32in";
3325}
3326def A5_vaddhubs : HInst<
3327(outs IntRegs:$Rd32),
3328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3329"$Rd32 = vaddhub($Rss32,$Rtt32):sat",
3330tc_002cb246, TypeS_3op>, Enc_d2216a {
3331let Inst{7-5} = 0b001;
3332let Inst{13-13} = 0b0;
3333let Inst{31-21} = 0b11000001010;
3334let hasNewValue = 1;
3335let opNewValue = 0;
3336let prefersSlot3 = 1;
3337let Defs = [USR_OVF];
3338}
3339def A6_vcmpbeq_notany : HInst<
3340(outs PredRegs:$Pd4),
3341(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3342"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
3343tc_1fc97744, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> {
3344let Inst{7-2} = 0b001000;
3345let Inst{13-13} = 0b1;
3346let Inst{31-21} = 0b11010010000;
3347}
3348def A6_vminub_RdP : HInst<
3349(outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
3350(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
3351"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
3352tc_f9058dd7, TypeM>, Enc_d2c7f1, Requires<[HasV62]> {
3353let Inst{7-7} = 0b0;
3354let Inst{13-13} = 0b0;
3355let Inst{31-21} = 0b11101010111;
3356let isPredicateLate = 1;
3357let prefersSlot3 = 1;
3358}
3359def C2_all8 : HInst<
3360(outs PredRegs:$Pd4),
3361(ins PredRegs:$Ps4),
3362"$Pd4 = all8($Ps4)",
3363tc_de554571, TypeCR>, Enc_65d691 {
3364let Inst{13-2} = 0b000000000000;
3365let Inst{31-18} = 0b01101011101000;
3366}
3367def C2_and : HInst<
3368(outs PredRegs:$Pd4),
3369(ins PredRegs:$Pt4, PredRegs:$Ps4),
3370"$Pd4 = and($Pt4,$Ps4)",
3371tc_640086b5, TypeCR>, Enc_454a26 {
3372let Inst{7-2} = 0b000000;
3373let Inst{13-10} = 0b0000;
3374let Inst{31-18} = 0b01101011000000;
3375}
3376def C2_andn : HInst<
3377(outs PredRegs:$Pd4),
3378(ins PredRegs:$Pt4, PredRegs:$Ps4),
3379"$Pd4 = and($Pt4,!$Ps4)",
3380tc_640086b5, TypeCR>, Enc_454a26 {
3381let Inst{7-2} = 0b000000;
3382let Inst{13-10} = 0b0000;
3383let Inst{31-18} = 0b01101011011000;
3384}
3385def C2_any8 : HInst<
3386(outs PredRegs:$Pd4),
3387(ins PredRegs:$Ps4),
3388"$Pd4 = any8($Ps4)",
3389tc_de554571, TypeCR>, Enc_65d691 {
3390let Inst{13-2} = 0b000000000000;
3391let Inst{31-18} = 0b01101011100000;
3392}
3393def C2_bitsclr : HInst<
3394(outs PredRegs:$Pd4),
3395(ins IntRegs:$Rs32, IntRegs:$Rt32),
3396"$Pd4 = bitsclr($Rs32,$Rt32)",
3397tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
3398let Inst{7-2} = 0b000000;
3399let Inst{13-13} = 0b0;
3400let Inst{31-21} = 0b11000111100;
3401}
3402def C2_bitsclri : HInst<
3403(outs PredRegs:$Pd4),
3404(ins IntRegs:$Rs32, u6_0Imm:$Ii),
3405"$Pd4 = bitsclr($Rs32,#$Ii)",
3406tc_643b4717, TypeS_2op>, Enc_5d6c34 {
3407let Inst{7-2} = 0b000000;
3408let Inst{31-21} = 0b10000101100;
3409}
3410def C2_bitsset : HInst<
3411(outs PredRegs:$Pd4),
3412(ins IntRegs:$Rs32, IntRegs:$Rt32),
3413"$Pd4 = bitsset($Rs32,$Rt32)",
3414tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
3415let Inst{7-2} = 0b000000;
3416let Inst{13-13} = 0b0;
3417let Inst{31-21} = 0b11000111010;
3418}
3419def C2_ccombinewf : HInst<
3420(outs DoubleRegs:$Rdd32),
3421(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3422"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3423tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3424let Inst{7-7} = 0b1;
3425let Inst{13-13} = 0b0;
3426let Inst{31-21} = 0b11111101000;
3427let isPredicated = 1;
3428let isPredicatedFalse = 1;
3429let BaseOpcode = "A2_combinew";
3430}
3431def C2_ccombinewnewf : HInst<
3432(outs DoubleRegs:$Rdd32),
3433(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3434"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3435tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3436let Inst{7-7} = 0b1;
3437let Inst{13-13} = 0b1;
3438let Inst{31-21} = 0b11111101000;
3439let isPredicated = 1;
3440let isPredicatedFalse = 1;
3441let isPredicatedNew = 1;
3442let BaseOpcode = "A2_combinew";
3443}
3444def C2_ccombinewnewt : HInst<
3445(outs DoubleRegs:$Rdd32),
3446(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3447"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3448tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3449let Inst{7-7} = 0b0;
3450let Inst{13-13} = 0b1;
3451let Inst{31-21} = 0b11111101000;
3452let isPredicated = 1;
3453let isPredicatedNew = 1;
3454let BaseOpcode = "A2_combinew";
3455}
3456def C2_ccombinewt : HInst<
3457(outs DoubleRegs:$Rdd32),
3458(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3459"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3460tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3461let Inst{7-7} = 0b0;
3462let Inst{13-13} = 0b0;
3463let Inst{31-21} = 0b11111101000;
3464let isPredicated = 1;
3465let BaseOpcode = "A2_combinew";
3466}
3467def C2_cmoveif : HInst<
3468(outs IntRegs:$Rd32),
3469(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3470"if (!$Pu4) $Rd32 = #$Ii",
3471tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3472let Inst{13-13} = 0b0;
3473let Inst{20-20} = 0b0;
3474let Inst{31-23} = 0b011111101;
3475let isPredicated = 1;
3476let isPredicatedFalse = 1;
3477let hasNewValue = 1;
3478let opNewValue = 0;
3479let CextOpcode = "A2_tfr";
3480let InputType = "imm";
3481let BaseOpcode = "A2_tfrsi";
3482let isMoveImm = 1;
3483let isExtendable = 1;
3484let opExtendable = 2;
3485let isExtentSigned = 1;
3486let opExtentBits = 12;
3487let opExtentAlign = 0;
3488}
3489def C2_cmoveit : HInst<
3490(outs IntRegs:$Rd32),
3491(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3492"if ($Pu4) $Rd32 = #$Ii",
3493tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3494let Inst{13-13} = 0b0;
3495let Inst{20-20} = 0b0;
3496let Inst{31-23} = 0b011111100;
3497let isPredicated = 1;
3498let hasNewValue = 1;
3499let opNewValue = 0;
3500let CextOpcode = "A2_tfr";
3501let InputType = "imm";
3502let BaseOpcode = "A2_tfrsi";
3503let isMoveImm = 1;
3504let isExtendable = 1;
3505let opExtendable = 2;
3506let isExtentSigned = 1;
3507let opExtentBits = 12;
3508let opExtentAlign = 0;
3509}
3510def C2_cmovenewif : HInst<
3511(outs IntRegs:$Rd32),
3512(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3513"if (!$Pu4.new) $Rd32 = #$Ii",
3514tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3515let Inst{13-13} = 0b1;
3516let Inst{20-20} = 0b0;
3517let Inst{31-23} = 0b011111101;
3518let isPredicated = 1;
3519let isPredicatedFalse = 1;
3520let hasNewValue = 1;
3521let opNewValue = 0;
3522let isPredicatedNew = 1;
3523let CextOpcode = "A2_tfr";
3524let InputType = "imm";
3525let BaseOpcode = "A2_tfrsi";
3526let isMoveImm = 1;
3527let isExtendable = 1;
3528let opExtendable = 2;
3529let isExtentSigned = 1;
3530let opExtentBits = 12;
3531let opExtentAlign = 0;
3532}
3533def C2_cmovenewit : HInst<
3534(outs IntRegs:$Rd32),
3535(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3536"if ($Pu4.new) $Rd32 = #$Ii",
3537tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3538let Inst{13-13} = 0b1;
3539let Inst{20-20} = 0b0;
3540let Inst{31-23} = 0b011111100;
3541let isPredicated = 1;
3542let hasNewValue = 1;
3543let opNewValue = 0;
3544let isPredicatedNew = 1;
3545let CextOpcode = "A2_tfr";
3546let InputType = "imm";
3547let BaseOpcode = "A2_tfrsi";
3548let isMoveImm = 1;
3549let isExtendable = 1;
3550let opExtendable = 2;
3551let isExtentSigned = 1;
3552let opExtentBits = 12;
3553let opExtentAlign = 0;
3554}
3555def C2_cmpeq : HInst<
3556(outs PredRegs:$Pd4),
3557(ins IntRegs:$Rs32, IntRegs:$Rt32),
3558"$Pd4 = cmp.eq($Rs32,$Rt32)",
3559tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3560let Inst{7-2} = 0b000000;
3561let Inst{13-13} = 0b0;
3562let Inst{31-21} = 0b11110010000;
3563let CextOpcode = "C2_cmpeq";
3564let InputType = "reg";
3565let isCommutable = 1;
3566let isCompare = 1;
3567}
3568def C2_cmpeqi : HInst<
3569(outs PredRegs:$Pd4),
3570(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3571"$Pd4 = cmp.eq($Rs32,#$Ii)",
3572tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3573let Inst{4-2} = 0b000;
3574let Inst{31-22} = 0b0111010100;
3575let CextOpcode = "C2_cmpeq";
3576let InputType = "imm";
3577let isCompare = 1;
3578let isExtendable = 1;
3579let opExtendable = 2;
3580let isExtentSigned = 1;
3581let opExtentBits = 10;
3582let opExtentAlign = 0;
3583}
3584def C2_cmpeqp : HInst<
3585(outs PredRegs:$Pd4),
3586(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3587"$Pd4 = cmp.eq($Rss32,$Rtt32)",
3588tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
3589let Inst{7-2} = 0b000000;
3590let Inst{13-13} = 0b0;
3591let Inst{31-21} = 0b11010010100;
3592let isCommutable = 1;
3593let isCompare = 1;
3594}
3595def C2_cmpgei : HInst<
3596(outs PredRegs:$Pd4),
3597(ins IntRegs:$Rs32, s8_0Imm:$Ii),
3598"$Pd4 = cmp.ge($Rs32,#$Ii)",
3599tc_56f114f4, TypeALU32_2op> {
3600let isCompare = 1;
3601let isPseudo = 1;
3602}
3603def C2_cmpgeui : HInst<
3604(outs PredRegs:$Pd4),
3605(ins IntRegs:$Rs32, u8_0Imm:$Ii),
3606"$Pd4 = cmp.geu($Rs32,#$Ii)",
3607tc_56f114f4, TypeALU32_2op> {
3608let isCompare = 1;
3609let isPseudo = 1;
3610}
3611def C2_cmpgt : HInst<
3612(outs PredRegs:$Pd4),
3613(ins IntRegs:$Rs32, IntRegs:$Rt32),
3614"$Pd4 = cmp.gt($Rs32,$Rt32)",
3615tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3616let Inst{7-2} = 0b000000;
3617let Inst{13-13} = 0b0;
3618let Inst{31-21} = 0b11110010010;
3619let CextOpcode = "C2_cmpgt";
3620let InputType = "reg";
3621let isCompare = 1;
3622}
3623def C2_cmpgti : HInst<
3624(outs PredRegs:$Pd4),
3625(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3626"$Pd4 = cmp.gt($Rs32,#$Ii)",
3627tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3628let Inst{4-2} = 0b000;
3629let Inst{31-22} = 0b0111010101;
3630let CextOpcode = "C2_cmpgt";
3631let InputType = "imm";
3632let isCompare = 1;
3633let isExtendable = 1;
3634let opExtendable = 2;
3635let isExtentSigned = 1;
3636let opExtentBits = 10;
3637let opExtentAlign = 0;
3638}
3639def C2_cmpgtp : HInst<
3640(outs PredRegs:$Pd4),
3641(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3642"$Pd4 = cmp.gt($Rss32,$Rtt32)",
3643tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
3644let Inst{7-2} = 0b010000;
3645let Inst{13-13} = 0b0;
3646let Inst{31-21} = 0b11010010100;
3647let isCompare = 1;
3648}
3649def C2_cmpgtu : HInst<
3650(outs PredRegs:$Pd4),
3651(ins IntRegs:$Rs32, IntRegs:$Rt32),
3652"$Pd4 = cmp.gtu($Rs32,$Rt32)",
3653tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3654let Inst{7-2} = 0b000000;
3655let Inst{13-13} = 0b0;
3656let Inst{31-21} = 0b11110010011;
3657let CextOpcode = "C2_cmpgtu";
3658let InputType = "reg";
3659let isCompare = 1;
3660}
3661def C2_cmpgtui : HInst<
3662(outs PredRegs:$Pd4),
3663(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3664"$Pd4 = cmp.gtu($Rs32,#$Ii)",
3665tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3666let Inst{4-2} = 0b000;
3667let Inst{31-21} = 0b01110101100;
3668let CextOpcode = "C2_cmpgtu";
3669let InputType = "imm";
3670let isCompare = 1;
3671let isExtendable = 1;
3672let opExtendable = 2;
3673let isExtentSigned = 0;
3674let opExtentBits = 9;
3675let opExtentAlign = 0;
3676}
3677def C2_cmpgtup : HInst<
3678(outs PredRegs:$Pd4),
3679(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3680"$Pd4 = cmp.gtu($Rss32,$Rtt32)",
3681tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
3682let Inst{7-2} = 0b100000;
3683let Inst{13-13} = 0b0;
3684let Inst{31-21} = 0b11010010100;
3685let isCompare = 1;
3686}
3687def C2_cmplt : HInst<
3688(outs PredRegs:$Pd4),
3689(ins IntRegs:$Rs32, IntRegs:$Rt32),
3690"$Pd4 = cmp.lt($Rs32,$Rt32)",
3691tc_56f114f4, TypeALU32_3op> {
3692let isCompare = 1;
3693let isPseudo = 1;
3694let isCodeGenOnly = 1;
3695}
3696def C2_cmpltu : HInst<
3697(outs PredRegs:$Pd4),
3698(ins IntRegs:$Rs32, IntRegs:$Rt32),
3699"$Pd4 = cmp.ltu($Rs32,$Rt32)",
3700tc_56f114f4, TypeALU32_3op> {
3701let isCompare = 1;
3702let isPseudo = 1;
3703let isCodeGenOnly = 1;
3704}
3705def C2_mask : HInst<
3706(outs DoubleRegs:$Rdd32),
3707(ins PredRegs:$Pt4),
3708"$Rdd32 = mask($Pt4)",
3709tc_0ae0825c, TypeS_2op>, Enc_78e566 {
3710let Inst{7-5} = 0b000;
3711let Inst{13-10} = 0b0000;
3712let Inst{31-16} = 0b1000011000000000;
3713}
3714def C2_mux : HInst<
3715(outs IntRegs:$Rd32),
3716(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3717"$Rd32 = mux($Pu4,$Rs32,$Rt32)",
3718tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54 {
3719let Inst{7-7} = 0b0;
3720let Inst{13-13} = 0b0;
3721let Inst{31-21} = 0b11110100000;
3722let hasNewValue = 1;
3723let opNewValue = 0;
3724let InputType = "reg";
3725}
3726def C2_muxii : HInst<
3727(outs IntRegs:$Rd32),
3728(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
3729"$Rd32 = mux($Pu4,#$Ii,#$II)",
3730tc_4c5ba658, TypeALU32_2op>, Enc_830e5d {
3731let Inst{31-25} = 0b0111101;
3732let hasNewValue = 1;
3733let opNewValue = 0;
3734let isExtendable = 1;
3735let opExtendable = 2;
3736let isExtentSigned = 1;
3737let opExtentBits = 8;
3738let opExtentAlign = 0;
3739}
3740def C2_muxir : HInst<
3741(outs IntRegs:$Rd32),
3742(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
3743"$Rd32 = mux($Pu4,$Rs32,#$Ii)",
3744tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f {
3745let Inst{13-13} = 0b0;
3746let Inst{31-23} = 0b011100110;
3747let hasNewValue = 1;
3748let opNewValue = 0;
3749let InputType = "imm";
3750let isExtendable = 1;
3751let opExtendable = 3;
3752let isExtentSigned = 1;
3753let opExtentBits = 8;
3754let opExtentAlign = 0;
3755}
3756def C2_muxri : HInst<
3757(outs IntRegs:$Rd32),
3758(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
3759"$Rd32 = mux($Pu4,#$Ii,$Rs32)",
3760tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f {
3761let Inst{13-13} = 0b0;
3762let Inst{31-23} = 0b011100111;
3763let hasNewValue = 1;
3764let opNewValue = 0;
3765let InputType = "imm";
3766let isExtendable = 1;
3767let opExtendable = 2;
3768let isExtentSigned = 1;
3769let opExtentBits = 8;
3770let opExtentAlign = 0;
3771}
3772def C2_not : HInst<
3773(outs PredRegs:$Pd4),
3774(ins PredRegs:$Ps4),
3775"$Pd4 = not($Ps4)",
3776tc_de554571, TypeCR>, Enc_65d691 {
3777let Inst{13-2} = 0b000000000000;
3778let Inst{31-18} = 0b01101011110000;
3779}
3780def C2_or : HInst<
3781(outs PredRegs:$Pd4),
3782(ins PredRegs:$Pt4, PredRegs:$Ps4),
3783"$Pd4 = or($Pt4,$Ps4)",
3784tc_640086b5, TypeCR>, Enc_454a26 {
3785let Inst{7-2} = 0b000000;
3786let Inst{13-10} = 0b0000;
3787let Inst{31-18} = 0b01101011001000;
3788}
3789def C2_orn : HInst<
3790(outs PredRegs:$Pd4),
3791(ins PredRegs:$Pt4, PredRegs:$Ps4),
3792"$Pd4 = or($Pt4,!$Ps4)",
3793tc_640086b5, TypeCR>, Enc_454a26 {
3794let Inst{7-2} = 0b000000;
3795let Inst{13-10} = 0b0000;
3796let Inst{31-18} = 0b01101011111000;
3797}
3798def C2_pxfer_map : HInst<
3799(outs PredRegs:$Pd4),
3800(ins PredRegs:$Ps4),
3801"$Pd4 = $Ps4",
3802tc_640086b5, TypeMAPPING> {
3803let isPseudo = 1;
3804let isCodeGenOnly = 1;
3805}
3806def C2_tfrpr : HInst<
3807(outs IntRegs:$Rd32),
3808(ins PredRegs:$Ps4),
3809"$Rd32 = $Ps4",
3810tc_0ae0825c, TypeS_2op>, Enc_f5e933 {
3811let Inst{13-5} = 0b000000000;
3812let Inst{31-18} = 0b10001001010000;
3813let hasNewValue = 1;
3814let opNewValue = 0;
3815}
3816def C2_tfrrp : HInst<
3817(outs PredRegs:$Pd4),
3818(ins IntRegs:$Rs32),
3819"$Pd4 = $Rs32",
3820tc_cfd8378a, TypeS_2op>, Enc_48b75f {
3821let Inst{13-2} = 0b000000000000;
3822let Inst{31-21} = 0b10000101010;
3823}
3824def C2_vitpack : HInst<
3825(outs IntRegs:$Rd32),
3826(ins PredRegs:$Ps4, PredRegs:$Pt4),
3827"$Rd32 = vitpack($Ps4,$Pt4)",
3828tc_4414d8b1, TypeS_2op>, Enc_527412 {
3829let Inst{7-5} = 0b000;
3830let Inst{13-10} = 0b0000;
3831let Inst{31-18} = 0b10001001000000;
3832let hasNewValue = 1;
3833let opNewValue = 0;
3834let prefersSlot3 = 1;
3835}
3836def C2_vmux : HInst<
3837(outs DoubleRegs:$Rdd32),
3838(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3839"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
3840tc_b4b5c03a, TypeALU64>, Enc_329361 {
3841let Inst{7-7} = 0b0;
3842let Inst{13-13} = 0b0;
3843let Inst{31-21} = 0b11010001000;
3844}
3845def C2_xor : HInst<
3846(outs PredRegs:$Pd4),
3847(ins PredRegs:$Ps4, PredRegs:$Pt4),
3848"$Pd4 = xor($Ps4,$Pt4)",
3849tc_640086b5, TypeCR>, Enc_284ebb {
3850let Inst{7-2} = 0b000000;
3851let Inst{13-10} = 0b0000;
3852let Inst{31-18} = 0b01101011010000;
3853}
3854def C4_addipc : HInst<
3855(outs IntRegs:$Rd32),
3856(ins u32_0Imm:$Ii),
3857"$Rd32 = add(pc,#$Ii)",
3858tc_a813cf9a, TypeCR>, Enc_607661 {
3859let Inst{6-5} = 0b00;
3860let Inst{13-13} = 0b0;
3861let Inst{31-16} = 0b0110101001001001;
3862let hasNewValue = 1;
3863let opNewValue = 0;
3864let isExtendable = 1;
3865let opExtendable = 1;
3866let isExtentSigned = 0;
3867let opExtentBits = 6;
3868let opExtentAlign = 0;
3869}
3870def C4_and_and : HInst<
3871(outs PredRegs:$Pd4),
3872(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3873"$Pd4 = and($Ps4,and($Pt4,$Pu4))",
3874tc_b31c2e97, TypeCR>, Enc_9ac432 {
3875let Inst{5-2} = 0b0000;
3876let Inst{13-10} = 0b0000;
3877let Inst{31-18} = 0b01101011000100;
3878}
3879def C4_and_andn : HInst<
3880(outs PredRegs:$Pd4),
3881(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3882"$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
3883tc_b31c2e97, TypeCR>, Enc_9ac432 {
3884let Inst{5-2} = 0b0000;
3885let Inst{13-10} = 0b0000;
3886let Inst{31-18} = 0b01101011100100;
3887}
3888def C4_and_or : HInst<
3889(outs PredRegs:$Pd4),
3890(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3891"$Pd4 = and($Ps4,or($Pt4,$Pu4))",
3892tc_b31c2e97, TypeCR>, Enc_9ac432 {
3893let Inst{5-2} = 0b0000;
3894let Inst{13-10} = 0b0000;
3895let Inst{31-18} = 0b01101011001100;
3896}
3897def C4_and_orn : HInst<
3898(outs PredRegs:$Pd4),
3899(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3900"$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
3901tc_b31c2e97, TypeCR>, Enc_9ac432 {
3902let Inst{5-2} = 0b0000;
3903let Inst{13-10} = 0b0000;
3904let Inst{31-18} = 0b01101011101100;
3905}
3906def C4_cmplte : HInst<
3907(outs PredRegs:$Pd4),
3908(ins IntRegs:$Rs32, IntRegs:$Rt32),
3909"$Pd4 = !cmp.gt($Rs32,$Rt32)",
3910tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3911let Inst{7-2} = 0b000100;
3912let Inst{13-13} = 0b0;
3913let Inst{31-21} = 0b11110010010;
3914let CextOpcode = "C4_cmplte";
3915let InputType = "reg";
3916let isCompare = 1;
3917}
3918def C4_cmpltei : HInst<
3919(outs PredRegs:$Pd4),
3920(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3921"$Pd4 = !cmp.gt($Rs32,#$Ii)",
3922tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3923let Inst{4-2} = 0b100;
3924let Inst{31-22} = 0b0111010101;
3925let CextOpcode = "C4_cmplte";
3926let InputType = "imm";
3927let isCompare = 1;
3928let isExtendable = 1;
3929let opExtendable = 2;
3930let isExtentSigned = 1;
3931let opExtentBits = 10;
3932let opExtentAlign = 0;
3933}
3934def C4_cmplteu : HInst<
3935(outs PredRegs:$Pd4),
3936(ins IntRegs:$Rs32, IntRegs:$Rt32),
3937"$Pd4 = !cmp.gtu($Rs32,$Rt32)",
3938tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3939let Inst{7-2} = 0b000100;
3940let Inst{13-13} = 0b0;
3941let Inst{31-21} = 0b11110010011;
3942let CextOpcode = "C4_cmplteu";
3943let InputType = "reg";
3944let isCompare = 1;
3945}
3946def C4_cmplteui : HInst<
3947(outs PredRegs:$Pd4),
3948(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3949"$Pd4 = !cmp.gtu($Rs32,#$Ii)",
3950tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3951let Inst{4-2} = 0b100;
3952let Inst{31-21} = 0b01110101100;
3953let CextOpcode = "C4_cmplteu";
3954let InputType = "imm";
3955let isCompare = 1;
3956let isExtendable = 1;
3957let opExtendable = 2;
3958let isExtentSigned = 0;
3959let opExtentBits = 9;
3960let opExtentAlign = 0;
3961}
3962def C4_cmpneq : HInst<
3963(outs PredRegs:$Pd4),
3964(ins IntRegs:$Rs32, IntRegs:$Rt32),
3965"$Pd4 = !cmp.eq($Rs32,$Rt32)",
3966tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3967let Inst{7-2} = 0b000100;
3968let Inst{13-13} = 0b0;
3969let Inst{31-21} = 0b11110010000;
3970let CextOpcode = "C4_cmpneq";
3971let InputType = "reg";
3972let isCommutable = 1;
3973let isCompare = 1;
3974}
3975def C4_cmpneqi : HInst<
3976(outs PredRegs:$Pd4),
3977(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3978"$Pd4 = !cmp.eq($Rs32,#$Ii)",
3979tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3980let Inst{4-2} = 0b100;
3981let Inst{31-22} = 0b0111010100;
3982let CextOpcode = "C4_cmpneq";
3983let InputType = "imm";
3984let isCompare = 1;
3985let isExtendable = 1;
3986let opExtendable = 2;
3987let isExtentSigned = 1;
3988let opExtentBits = 10;
3989let opExtentAlign = 0;
3990}
3991def C4_fastcorner9 : HInst<
3992(outs PredRegs:$Pd4),
3993(ins PredRegs:$Ps4, PredRegs:$Pt4),
3994"$Pd4 = fastcorner9($Ps4,$Pt4)",
3995tc_640086b5, TypeCR>, Enc_284ebb {
3996let Inst{7-2} = 0b100100;
3997let Inst{13-10} = 0b1000;
3998let Inst{31-18} = 0b01101011000000;
3999}
4000def C4_fastcorner9_not : HInst<
4001(outs PredRegs:$Pd4),
4002(ins PredRegs:$Ps4, PredRegs:$Pt4),
4003"$Pd4 = !fastcorner9($Ps4,$Pt4)",
4004tc_640086b5, TypeCR>, Enc_284ebb {
4005let Inst{7-2} = 0b100100;
4006let Inst{13-10} = 0b1000;
4007let Inst{31-18} = 0b01101011000100;
4008}
4009def C4_nbitsclr : HInst<
4010(outs PredRegs:$Pd4),
4011(ins IntRegs:$Rs32, IntRegs:$Rt32),
4012"$Pd4 = !bitsclr($Rs32,$Rt32)",
4013tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
4014let Inst{7-2} = 0b000000;
4015let Inst{13-13} = 0b0;
4016let Inst{31-21} = 0b11000111101;
4017}
4018def C4_nbitsclri : HInst<
4019(outs PredRegs:$Pd4),
4020(ins IntRegs:$Rs32, u6_0Imm:$Ii),
4021"$Pd4 = !bitsclr($Rs32,#$Ii)",
4022tc_643b4717, TypeS_2op>, Enc_5d6c34 {
4023let Inst{7-2} = 0b000000;
4024let Inst{31-21} = 0b10000101101;
4025}
4026def C4_nbitsset : HInst<
4027(outs PredRegs:$Pd4),
4028(ins IntRegs:$Rs32, IntRegs:$Rt32),
4029"$Pd4 = !bitsset($Rs32,$Rt32)",
4030tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
4031let Inst{7-2} = 0b000000;
4032let Inst{13-13} = 0b0;
4033let Inst{31-21} = 0b11000111011;
4034}
4035def C4_or_and : HInst<
4036(outs PredRegs:$Pd4),
4037(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4038"$Pd4 = or($Ps4,and($Pt4,$Pu4))",
4039tc_b31c2e97, TypeCR>, Enc_9ac432 {
4040let Inst{5-2} = 0b0000;
4041let Inst{13-10} = 0b0000;
4042let Inst{31-18} = 0b01101011010100;
4043}
4044def C4_or_andn : HInst<
4045(outs PredRegs:$Pd4),
4046(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4047"$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
4048tc_b31c2e97, TypeCR>, Enc_9ac432 {
4049let Inst{5-2} = 0b0000;
4050let Inst{13-10} = 0b0000;
4051let Inst{31-18} = 0b01101011110100;
4052}
4053def C4_or_or : HInst<
4054(outs PredRegs:$Pd4),
4055(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4056"$Pd4 = or($Ps4,or($Pt4,$Pu4))",
4057tc_b31c2e97, TypeCR>, Enc_9ac432 {
4058let Inst{5-2} = 0b0000;
4059let Inst{13-10} = 0b0000;
4060let Inst{31-18} = 0b01101011011100;
4061}
4062def C4_or_orn : HInst<
4063(outs PredRegs:$Pd4),
4064(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4065"$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
4066tc_b31c2e97, TypeCR>, Enc_9ac432 {
4067let Inst{5-2} = 0b0000;
4068let Inst{13-10} = 0b0000;
4069let Inst{31-18} = 0b01101011111100;
4070}
4071def F2_conv_d2df : HInst<
4072(outs DoubleRegs:$Rdd32),
4073(ins DoubleRegs:$Rss32),
4074"$Rdd32 = convert_d2df($Rss32)",
4075tc_3a867367, TypeS_2op>, Enc_b9c5fb {
4076let Inst{13-5} = 0b000000011;
4077let Inst{31-21} = 0b10000000111;
4078let isFP = 1;
4079let Uses = [USR];
4080}
4081def F2_conv_d2sf : HInst<
4082(outs IntRegs:$Rd32),
4083(ins DoubleRegs:$Rss32),
4084"$Rd32 = convert_d2sf($Rss32)",
4085tc_3a867367, TypeS_2op>, Enc_90cd8b {
4086let Inst{13-5} = 0b000000001;
4087let Inst{31-21} = 0b10001000010;
4088let hasNewValue = 1;
4089let opNewValue = 0;
4090let isFP = 1;
4091let Uses = [USR];
4092}
4093def F2_conv_df2d : HInst<
4094(outs DoubleRegs:$Rdd32),
4095(ins DoubleRegs:$Rss32),
4096"$Rdd32 = convert_df2d($Rss32)",
4097tc_3a867367, TypeS_2op>, Enc_b9c5fb {
4098let Inst{13-5} = 0b000000000;
4099let Inst{31-21} = 0b10000000111;
4100let isFP = 1;
4101let Uses = [USR];
4102}
4103def F2_conv_df2d_chop : HInst<
4104(outs DoubleRegs:$Rdd32),
4105(ins DoubleRegs:$Rss32),
4106"$Rdd32 = convert_df2d($Rss32):chop",
4107tc_3a867367, TypeS_2op>, Enc_b9c5fb {
4108let Inst{13-5} = 0b000000110;
4109let Inst{31-21} = 0b10000000111;
4110let isFP = 1;
4111let Uses = [USR];
4112}
4113def F2_conv_df2sf : HInst<
4114(outs IntRegs:$Rd32),
4115(ins DoubleRegs:$Rss32),
4116"$Rd32 = convert_df2sf($Rss32)",
4117tc_3a867367, TypeS_2op>, Enc_90cd8b {
4118let Inst{13-5} = 0b000000001;
4119let Inst{31-21} = 0b10001000000;
4120let hasNewValue = 1;
4121let opNewValue = 0;
4122let isFP = 1;
4123let Uses = [USR];
4124}
4125def F2_conv_df2ud : HInst<
4126(outs DoubleRegs:$Rdd32),
4127(ins DoubleRegs:$Rss32),
4128"$Rdd32 = convert_df2ud($Rss32)",
4129tc_3a867367, TypeS_2op>, Enc_b9c5fb {
4130let Inst{13-5} = 0b000000001;
4131let Inst{31-21} = 0b10000000111;
4132let isFP = 1;
4133let Uses = [USR];
4134}
4135def F2_conv_df2ud_chop : HInst<
4136(outs DoubleRegs:$Rdd32),
4137(ins DoubleRegs:$Rss32),
4138"$Rdd32 = convert_df2ud($Rss32):chop",
4139tc_3a867367, TypeS_2op>, Enc_b9c5fb {
4140let Inst{13-5} = 0b000000111;
4141let Inst{31-21} = 0b10000000111;
4142let isFP = 1;
4143let Uses = [USR];
4144}
4145def F2_conv_df2uw : HInst<
4146(outs IntRegs:$Rd32),
4147(ins DoubleRegs:$Rss32),
4148"$Rd32 = convert_df2uw($Rss32)",
4149tc_3a867367, TypeS_2op>, Enc_90cd8b {
4150let Inst{13-5} = 0b000000001;
4151let Inst{31-21} = 0b10001000011;
4152let hasNewValue = 1;
4153let opNewValue = 0;
4154let isFP = 1;
4155let Uses = [USR];
4156}
4157def F2_conv_df2uw_chop : HInst<
4158(outs IntRegs:$Rd32),
4159(ins DoubleRegs:$Rss32),
4160"$Rd32 = convert_df2uw($Rss32):chop",
4161tc_3a867367, TypeS_2op>, Enc_90cd8b {
4162let Inst{13-5} = 0b000000001;
4163let Inst{31-21} = 0b10001000101;
4164let hasNewValue = 1;
4165let opNewValue = 0;
4166let isFP = 1;
4167let Uses = [USR];
4168}
4169def F2_conv_df2w : HInst<
4170(outs IntRegs:$Rd32),
4171(ins DoubleRegs:$Rss32),
4172"$Rd32 = convert_df2w($Rss32)",
4173tc_3a867367, TypeS_2op>, Enc_90cd8b {
4174let Inst{13-5} = 0b000000001;
4175let Inst{31-21} = 0b10001000100;
4176let hasNewValue = 1;
4177let opNewValue = 0;
4178let isFP = 1;
4179let Uses = [USR];
4180}
4181def F2_conv_df2w_chop : HInst<
4182(outs IntRegs:$Rd32),
4183(ins DoubleRegs:$Rss32),
4184"$Rd32 = convert_df2w($Rss32):chop",
4185tc_3a867367, TypeS_2op>, Enc_90cd8b {
4186let Inst{13-5} = 0b000000001;
4187let Inst{31-21} = 0b10001000111;
4188let hasNewValue = 1;
4189let opNewValue = 0;
4190let isFP = 1;
4191let Uses = [USR];
4192}
4193def F2_conv_sf2d : HInst<
4194(outs DoubleRegs:$Rdd32),
4195(ins IntRegs:$Rs32),
4196"$Rdd32 = convert_sf2d($Rs32)",
4197tc_3a867367, TypeS_2op>, Enc_3a3d62 {
4198let Inst{13-5} = 0b000000100;
4199let Inst{31-21} = 0b10000100100;
4200let isFP = 1;
4201let Uses = [USR];
4202}
4203def F2_conv_sf2d_chop : HInst<
4204(outs DoubleRegs:$Rdd32),
4205(ins IntRegs:$Rs32),
4206"$Rdd32 = convert_sf2d($Rs32):chop",
4207tc_3a867367, TypeS_2op>, Enc_3a3d62 {
4208let Inst{13-5} = 0b000000110;
4209let Inst{31-21} = 0b10000100100;
4210let isFP = 1;
4211let Uses = [USR];
4212}
4213def F2_conv_sf2df : HInst<
4214(outs DoubleRegs:$Rdd32),
4215(ins IntRegs:$Rs32),
4216"$Rdd32 = convert_sf2df($Rs32)",
4217tc_3a867367, TypeS_2op>, Enc_3a3d62 {
4218let Inst{13-5} = 0b000000000;
4219let Inst{31-21} = 0b10000100100;
4220let isFP = 1;
4221let Uses = [USR];
4222}
4223def F2_conv_sf2ud : HInst<
4224(outs DoubleRegs:$Rdd32),
4225(ins IntRegs:$Rs32),
4226"$Rdd32 = convert_sf2ud($Rs32)",
4227tc_3a867367, TypeS_2op>, Enc_3a3d62 {
4228let Inst{13-5} = 0b000000011;
4229let Inst{31-21} = 0b10000100100;
4230let isFP = 1;
4231let Uses = [USR];
4232}
4233def F2_conv_sf2ud_chop : HInst<
4234(outs DoubleRegs:$Rdd32),
4235(ins IntRegs:$Rs32),
4236"$Rdd32 = convert_sf2ud($Rs32):chop",
4237tc_3a867367, TypeS_2op>, Enc_3a3d62 {
4238let Inst{13-5} = 0b000000101;
4239let Inst{31-21} = 0b10000100100;
4240let isFP = 1;
4241let Uses = [USR];
4242}
4243def F2_conv_sf2uw : HInst<
4244(outs IntRegs:$Rd32),
4245(ins IntRegs:$Rs32),
4246"$Rd32 = convert_sf2uw($Rs32)",
4247tc_3a867367, TypeS_2op>, Enc_5e2823 {
4248let Inst{13-5} = 0b000000000;
4249let Inst{31-21} = 0b10001011011;
4250let hasNewValue = 1;
4251let opNewValue = 0;
4252let isFP = 1;
4253let Uses = [USR];
4254}
4255def F2_conv_sf2uw_chop : HInst<
4256(outs IntRegs:$Rd32),
4257(ins IntRegs:$Rs32),
4258"$Rd32 = convert_sf2uw($Rs32):chop",
4259tc_3a867367, TypeS_2op>, Enc_5e2823 {
4260let Inst{13-5} = 0b000000001;
4261let Inst{31-21} = 0b10001011011;
4262let hasNewValue = 1;
4263let opNewValue = 0;
4264let isFP = 1;
4265let Uses = [USR];
4266}
4267def F2_conv_sf2w : HInst<
4268(outs IntRegs:$Rd32),
4269(ins IntRegs:$Rs32),
4270"$Rd32 = convert_sf2w($Rs32)",
4271tc_3a867367, TypeS_2op>, Enc_5e2823 {
4272let Inst{13-5} = 0b000000000;
4273let Inst{31-21} = 0b10001011100;
4274let hasNewValue = 1;
4275let opNewValue = 0;
4276let isFP = 1;
4277let Uses = [USR];
4278}
4279def F2_conv_sf2w_chop : HInst<
4280(outs IntRegs:$Rd32),
4281(ins IntRegs:$Rs32),
4282"$Rd32 = convert_sf2w($Rs32):chop",
4283tc_3a867367, TypeS_2op>, Enc_5e2823 {
4284let Inst{13-5} = 0b000000001;
4285let Inst{31-21} = 0b10001011100;
4286let hasNewValue = 1;
4287let opNewValue = 0;
4288let isFP = 1;
4289let Uses = [USR];
4290}
4291def F2_conv_ud2df : HInst<
4292(outs DoubleRegs:$Rdd32),
4293(ins DoubleRegs:$Rss32),
4294"$Rdd32 = convert_ud2df($Rss32)",
4295tc_3a867367, TypeS_2op>, Enc_b9c5fb {
4296let Inst{13-5} = 0b000000010;
4297let Inst{31-21} = 0b10000000111;
4298let isFP = 1;
4299let Uses = [USR];
4300}
4301def F2_conv_ud2sf : HInst<
4302(outs IntRegs:$Rd32),
4303(ins DoubleRegs:$Rss32),
4304"$Rd32 = convert_ud2sf($Rss32)",
4305tc_3a867367, TypeS_2op>, Enc_90cd8b {
4306let Inst{13-5} = 0b000000001;
4307let Inst{31-21} = 0b10001000001;
4308let hasNewValue = 1;
4309let opNewValue = 0;
4310let isFP = 1;
4311let Uses = [USR];
4312}
4313def F2_conv_uw2df : HInst<
4314(outs DoubleRegs:$Rdd32),
4315(ins IntRegs:$Rs32),
4316"$Rdd32 = convert_uw2df($Rs32)",
4317tc_3a867367, TypeS_2op>, Enc_3a3d62 {
4318let Inst{13-5} = 0b000000001;
4319let Inst{31-21} = 0b10000100100;
4320let isFP = 1;
4321let Uses = [USR];
4322}
4323def F2_conv_uw2sf : HInst<
4324(outs IntRegs:$Rd32),
4325(ins IntRegs:$Rs32),
4326"$Rd32 = convert_uw2sf($Rs32)",
4327tc_3a867367, TypeS_2op>, Enc_5e2823 {
4328let Inst{13-5} = 0b000000000;
4329let Inst{31-21} = 0b10001011001;
4330let hasNewValue = 1;
4331let opNewValue = 0;
4332let isFP = 1;
4333let Uses = [USR];
4334}
4335def F2_conv_w2df : HInst<
4336(outs DoubleRegs:$Rdd32),
4337(ins IntRegs:$Rs32),
4338"$Rdd32 = convert_w2df($Rs32)",
4339tc_3a867367, TypeS_2op>, Enc_3a3d62 {
4340let Inst{13-5} = 0b000000010;
4341let Inst{31-21} = 0b10000100100;
4342let isFP = 1;
4343let Uses = [USR];
4344}
4345def F2_conv_w2sf : HInst<
4346(outs IntRegs:$Rd32),
4347(ins IntRegs:$Rs32),
4348"$Rd32 = convert_w2sf($Rs32)",
4349tc_3a867367, TypeS_2op>, Enc_5e2823 {
4350let Inst{13-5} = 0b000000000;
4351let Inst{31-21} = 0b10001011010;
4352let hasNewValue = 1;
4353let opNewValue = 0;
4354let isFP = 1;
4355let Uses = [USR];
4356}
4357def F2_dfadd : HInst<
4358(outs DoubleRegs:$Rdd32),
4359(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4360"$Rdd32 = dfadd($Rss32,$Rtt32)",
4361tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> {
4362let Inst{7-5} = 0b011;
4363let Inst{13-13} = 0b0;
4364let Inst{31-21} = 0b11101000000;
4365let isFP = 1;
4366let Uses = [USR];
4367}
4368def F2_dfclass : HInst<
4369(outs PredRegs:$Pd4),
4370(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
4371"$Pd4 = dfclass($Rss32,#$Ii)",
4372tc_643b4717, TypeALU64>, Enc_1f19b5 {
4373let Inst{4-2} = 0b100;
4374let Inst{13-10} = 0b0000;
4375let Inst{31-21} = 0b11011100100;
4376let isFP = 1;
4377let Uses = [USR];
4378}
4379def F2_dfcmpeq : HInst<
4380(outs PredRegs:$Pd4),
4381(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4382"$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
4383tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
4384let Inst{7-2} = 0b000000;
4385let Inst{13-13} = 0b0;
4386let Inst{31-21} = 0b11010010111;
4387let isFP = 1;
4388let Uses = [USR];
4389let isCompare = 1;
4390}
4391def F2_dfcmpge : HInst<
4392(outs PredRegs:$Pd4),
4393(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4394"$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
4395tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
4396let Inst{7-2} = 0b010000;
4397let Inst{13-13} = 0b0;
4398let Inst{31-21} = 0b11010010111;
4399let isFP = 1;
4400let Uses = [USR];
4401let isCompare = 1;
4402}
4403def F2_dfcmpgt : HInst<
4404(outs PredRegs:$Pd4),
4405(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4406"$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
4407tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
4408let Inst{7-2} = 0b001000;
4409let Inst{13-13} = 0b0;
4410let Inst{31-21} = 0b11010010111;
4411let isFP = 1;
4412let Uses = [USR];
4413let isCompare = 1;
4414}
4415def F2_dfcmpuo : HInst<
4416(outs PredRegs:$Pd4),
4417(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4418"$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
4419tc_85d5d03f, TypeALU64>, Enc_fcf7a7 {
4420let Inst{7-2} = 0b011000;
4421let Inst{13-13} = 0b0;
4422let Inst{31-21} = 0b11010010111;
4423let isFP = 1;
4424let Uses = [USR];
4425let isCompare = 1;
4426}
4427def F2_dfimm_n : HInst<
4428(outs DoubleRegs:$Rdd32),
4429(ins u10_0Imm:$Ii),
4430"$Rdd32 = dfmake(#$Ii):neg",
4431tc_9e313203, TypeALU64>, Enc_e6c957 {
4432let Inst{20-16} = 0b00000;
4433let Inst{31-22} = 0b1101100101;
4434let prefersSlot3 = 1;
4435}
4436def F2_dfimm_p : HInst<
4437(outs DoubleRegs:$Rdd32),
4438(ins u10_0Imm:$Ii),
4439"$Rdd32 = dfmake(#$Ii):pos",
4440tc_9e313203, TypeALU64>, Enc_e6c957 {
4441let Inst{20-16} = 0b00000;
4442let Inst{31-22} = 0b1101100100;
4443let prefersSlot3 = 1;
4444}
4445def F2_dfsub : HInst<
4446(outs DoubleRegs:$Rdd32),
4447(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4448"$Rdd32 = dfsub($Rss32,$Rtt32)",
4449tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> {
4450let Inst{7-5} = 0b011;
4451let Inst{13-13} = 0b0;
4452let Inst{31-21} = 0b11101000100;
4453let isFP = 1;
4454let Uses = [USR];
4455}
4456def F2_sfadd : HInst<
4457(outs IntRegs:$Rd32),
4458(ins IntRegs:$Rs32, IntRegs:$Rt32),
4459"$Rd32 = sfadd($Rs32,$Rt32)",
4460tc_3b470976, TypeM>, Enc_5ab2be {
4461let Inst{7-5} = 0b000;
4462let Inst{13-13} = 0b0;
4463let Inst{31-21} = 0b11101011000;
4464let hasNewValue = 1;
4465let opNewValue = 0;
4466let isFP = 1;
4467let Uses = [USR];
4468let isCommutable = 1;
4469}
4470def F2_sfclass : HInst<
4471(outs PredRegs:$Pd4),
4472(ins IntRegs:$Rs32, u5_0Imm:$Ii),
4473"$Pd4 = sfclass($Rs32,#$Ii)",
4474tc_643b4717, TypeS_2op>, Enc_83ee64 {
4475let Inst{7-2} = 0b000000;
4476let Inst{13-13} = 0b0;
4477let Inst{31-21} = 0b10000101111;
4478let isFP = 1;
4479let Uses = [USR];
4480}
4481def F2_sfcmpeq : HInst<
4482(outs PredRegs:$Pd4),
4483(ins IntRegs:$Rs32, IntRegs:$Rt32),
4484"$Pd4 = sfcmp.eq($Rs32,$Rt32)",
4485tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
4486let Inst{7-2} = 0b011000;
4487let Inst{13-13} = 0b0;
4488let Inst{31-21} = 0b11000111111;
4489let isFP = 1;
4490let Uses = [USR];
4491let isCompare = 1;
4492}
4493def F2_sfcmpge : HInst<
4494(outs PredRegs:$Pd4),
4495(ins IntRegs:$Rs32, IntRegs:$Rt32),
4496"$Pd4 = sfcmp.ge($Rs32,$Rt32)",
4497tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
4498let Inst{7-2} = 0b000000;
4499let Inst{13-13} = 0b0;
4500let Inst{31-21} = 0b11000111111;
4501let isFP = 1;
4502let Uses = [USR];
4503let isCompare = 1;
4504}
4505def F2_sfcmpgt : HInst<
4506(outs PredRegs:$Pd4),
4507(ins IntRegs:$Rs32, IntRegs:$Rt32),
4508"$Pd4 = sfcmp.gt($Rs32,$Rt32)",
4509tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
4510let Inst{7-2} = 0b100000;
4511let Inst{13-13} = 0b0;
4512let Inst{31-21} = 0b11000111111;
4513let isFP = 1;
4514let Uses = [USR];
4515let isCompare = 1;
4516}
4517def F2_sfcmpuo : HInst<
4518(outs PredRegs:$Pd4),
4519(ins IntRegs:$Rs32, IntRegs:$Rt32),
4520"$Pd4 = sfcmp.uo($Rs32,$Rt32)",
4521tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
4522let Inst{7-2} = 0b001000;
4523let Inst{13-13} = 0b0;
4524let Inst{31-21} = 0b11000111111;
4525let isFP = 1;
4526let Uses = [USR];
4527let isCompare = 1;
4528}
4529def F2_sffixupd : HInst<
4530(outs IntRegs:$Rd32),
4531(ins IntRegs:$Rs32, IntRegs:$Rt32),
4532"$Rd32 = sffixupd($Rs32,$Rt32)",
4533tc_3b470976, TypeM>, Enc_5ab2be {
4534let Inst{7-5} = 0b001;
4535let Inst{13-13} = 0b0;
4536let Inst{31-21} = 0b11101011110;
4537let hasNewValue = 1;
4538let opNewValue = 0;
4539let isFP = 1;
4540}
4541def F2_sffixupn : HInst<
4542(outs IntRegs:$Rd32),
4543(ins IntRegs:$Rs32, IntRegs:$Rt32),
4544"$Rd32 = sffixupn($Rs32,$Rt32)",
4545tc_3b470976, TypeM>, Enc_5ab2be {
4546let Inst{7-5} = 0b000;
4547let Inst{13-13} = 0b0;
4548let Inst{31-21} = 0b11101011110;
4549let hasNewValue = 1;
4550let opNewValue = 0;
4551let isFP = 1;
4552}
4553def F2_sffixupr : HInst<
4554(outs IntRegs:$Rd32),
4555(ins IntRegs:$Rs32),
4556"$Rd32 = sffixupr($Rs32)",
4557tc_3a867367, TypeS_2op>, Enc_5e2823 {
4558let Inst{13-5} = 0b000000000;
4559let Inst{31-21} = 0b10001011101;
4560let hasNewValue = 1;
4561let opNewValue = 0;
4562let isFP = 1;
4563}
4564def F2_sffma : HInst<
4565(outs IntRegs:$Rx32),
4566(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4567"$Rx32 += sfmpy($Rs32,$Rt32)",
4568tc_a58fd5cc, TypeM>, Enc_2ae154 {
4569let Inst{7-5} = 0b100;
4570let Inst{13-13} = 0b0;
4571let Inst{31-21} = 0b11101111000;
4572let hasNewValue = 1;
4573let opNewValue = 0;
4574let isFP = 1;
4575let Uses = [USR];
4576let Constraints = "$Rx32 = $Rx32in";
4577}
4578def F2_sffma_lib : HInst<
4579(outs IntRegs:$Rx32),
4580(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4581"$Rx32 += sfmpy($Rs32,$Rt32):lib",
4582tc_a58fd5cc, TypeM>, Enc_2ae154 {
4583let Inst{7-5} = 0b110;
4584let Inst{13-13} = 0b0;
4585let Inst{31-21} = 0b11101111000;
4586let hasNewValue = 1;
4587let opNewValue = 0;
4588let isFP = 1;
4589let Uses = [USR];
4590let Constraints = "$Rx32 = $Rx32in";
4591}
4592def F2_sffma_sc : HInst<
4593(outs IntRegs:$Rx32),
4594(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
4595"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
4596tc_4560740b, TypeM>, Enc_437f33 {
4597let Inst{7-7} = 0b1;
4598let Inst{13-13} = 0b0;
4599let Inst{31-21} = 0b11101111011;
4600let hasNewValue = 1;
4601let opNewValue = 0;
4602let isFP = 1;
4603let Uses = [USR];
4604let Constraints = "$Rx32 = $Rx32in";
4605}
4606def F2_sffms : HInst<
4607(outs IntRegs:$Rx32),
4608(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4609"$Rx32 -= sfmpy($Rs32,$Rt32)",
4610tc_a58fd5cc, TypeM>, Enc_2ae154 {
4611let Inst{7-5} = 0b101;
4612let Inst{13-13} = 0b0;
4613let Inst{31-21} = 0b11101111000;
4614let hasNewValue = 1;
4615let opNewValue = 0;
4616let isFP = 1;
4617let Uses = [USR];
4618let Constraints = "$Rx32 = $Rx32in";
4619}
4620def F2_sffms_lib : HInst<
4621(outs IntRegs:$Rx32),
4622(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4623"$Rx32 -= sfmpy($Rs32,$Rt32):lib",
4624tc_a58fd5cc, TypeM>, Enc_2ae154 {
4625let Inst{7-5} = 0b111;
4626let Inst{13-13} = 0b0;
4627let Inst{31-21} = 0b11101111000;
4628let hasNewValue = 1;
4629let opNewValue = 0;
4630let isFP = 1;
4631let Uses = [USR];
4632let Constraints = "$Rx32 = $Rx32in";
4633}
4634def F2_sfimm_n : HInst<
4635(outs IntRegs:$Rd32),
4636(ins u10_0Imm:$Ii),
4637"$Rd32 = sfmake(#$Ii):neg",
4638tc_9e313203, TypeALU64>, Enc_6c9440 {
4639let Inst{20-16} = 0b00000;
4640let Inst{31-22} = 0b1101011001;
4641let hasNewValue = 1;
4642let opNewValue = 0;
4643let prefersSlot3 = 1;
4644}
4645def F2_sfimm_p : HInst<
4646(outs IntRegs:$Rd32),
4647(ins u10_0Imm:$Ii),
4648"$Rd32 = sfmake(#$Ii):pos",
4649tc_9e313203, TypeALU64>, Enc_6c9440 {
4650let Inst{20-16} = 0b00000;
4651let Inst{31-22} = 0b1101011000;
4652let hasNewValue = 1;
4653let opNewValue = 0;
4654let prefersSlot3 = 1;
4655}
4656def F2_sfinvsqrta : HInst<
4657(outs IntRegs:$Rd32, PredRegs:$Pe4),
4658(ins IntRegs:$Rs32),
4659"$Rd32,$Pe4 = sfinvsqrta($Rs32)",
4660tc_b8bffe55, TypeS_2op>, Enc_890909 {
4661let Inst{13-7} = 0b0000000;
4662let Inst{31-21} = 0b10001011111;
4663let hasNewValue = 1;
4664let opNewValue = 0;
4665let isFP = 1;
4666let isPredicateLate = 1;
4667}
4668def F2_sfmax : HInst<
4669(outs IntRegs:$Rd32),
4670(ins IntRegs:$Rs32, IntRegs:$Rt32),
4671"$Rd32 = sfmax($Rs32,$Rt32)",
4672tc_88b4f13d, TypeM>, Enc_5ab2be {
4673let Inst{7-5} = 0b000;
4674let Inst{13-13} = 0b0;
4675let Inst{31-21} = 0b11101011100;
4676let hasNewValue = 1;
4677let opNewValue = 0;
4678let isFP = 1;
4679let prefersSlot3 = 1;
4680let Uses = [USR];
4681}
4682def F2_sfmin : HInst<
4683(outs IntRegs:$Rd32),
4684(ins IntRegs:$Rs32, IntRegs:$Rt32),
4685"$Rd32 = sfmin($Rs32,$Rt32)",
4686tc_88b4f13d, TypeM>, Enc_5ab2be {
4687let Inst{7-5} = 0b001;
4688let Inst{13-13} = 0b0;
4689let Inst{31-21} = 0b11101011100;
4690let hasNewValue = 1;
4691let opNewValue = 0;
4692let isFP = 1;
4693let prefersSlot3 = 1;
4694let Uses = [USR];
4695}
4696def F2_sfmpy : HInst<
4697(outs IntRegs:$Rd32),
4698(ins IntRegs:$Rs32, IntRegs:$Rt32),
4699"$Rd32 = sfmpy($Rs32,$Rt32)",
4700tc_3b470976, TypeM>, Enc_5ab2be {
4701let Inst{7-5} = 0b000;
4702let Inst{13-13} = 0b0;
4703let Inst{31-21} = 0b11101011010;
4704let hasNewValue = 1;
4705let opNewValue = 0;
4706let isFP = 1;
4707let Uses = [USR];
4708let isCommutable = 1;
4709}
4710def F2_sfrecipa : HInst<
4711(outs IntRegs:$Rd32, PredRegs:$Pe4),
4712(ins IntRegs:$Rs32, IntRegs:$Rt32),
4713"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
4714tc_2ff964b4, TypeM>, Enc_a94f3b {
4715let Inst{7-7} = 0b1;
4716let Inst{13-13} = 0b0;
4717let Inst{31-21} = 0b11101011111;
4718let hasNewValue = 1;
4719let opNewValue = 0;
4720let isFP = 1;
4721let isPredicateLate = 1;
4722}
4723def F2_sfsub : HInst<
4724(outs IntRegs:$Rd32),
4725(ins IntRegs:$Rs32, IntRegs:$Rt32),
4726"$Rd32 = sfsub($Rs32,$Rt32)",
4727tc_3b470976, TypeM>, Enc_5ab2be {
4728let Inst{7-5} = 0b001;
4729let Inst{13-13} = 0b0;
4730let Inst{31-21} = 0b11101011000;
4731let hasNewValue = 1;
4732let opNewValue = 0;
4733let isFP = 1;
4734let Uses = [USR];
4735}
4736def G4_tfrgcpp : HInst<
4737(outs DoubleRegs:$Rdd32),
4738(ins GuestRegs64:$Gss32),
4739"$Rdd32 = $Gss32",
4740tc_0d8f5752, TypeCR>, Enc_0aa344 {
4741let Inst{13-5} = 0b000000000;
4742let Inst{31-21} = 0b01101000001;
4743}
4744def G4_tfrgcrr : HInst<
4745(outs IntRegs:$Rd32),
4746(ins GuestRegs:$Gs32),
4747"$Rd32 = $Gs32",
4748tc_0d8f5752, TypeCR>, Enc_44271f {
4749let Inst{13-5} = 0b000000000;
4750let Inst{31-21} = 0b01101010001;
4751let hasNewValue = 1;
4752let opNewValue = 0;
4753}
4754def G4_tfrgpcp : HInst<
4755(outs GuestRegs64:$Gdd32),
4756(ins DoubleRegs:$Rss32),
4757"$Gdd32 = $Rss32",
4758tc_bcf98408, TypeCR>, Enc_ed5027 {
4759let Inst{13-5} = 0b000000000;
4760let Inst{31-21} = 0b01100011000;
4761let hasNewValue = 1;
4762let opNewValue = 0;
4763}
4764def G4_tfrgrcr : HInst<
4765(outs GuestRegs:$Gd32),
4766(ins IntRegs:$Rs32),
4767"$Gd32 = $Rs32",
4768tc_bcf98408, TypeCR>, Enc_621fba {
4769let Inst{13-5} = 0b000000000;
4770let Inst{31-21} = 0b01100010000;
4771let hasNewValue = 1;
4772let opNewValue = 0;
4773}
4774def J2_call : HInst<
4775(outs),
4776(ins a30_2Imm:$Ii),
4777"call $Ii",
4778tc_4ae7b58b, TypeJ>, Enc_81ac1d, PredRel {
4779let Inst{0-0} = 0b0;
4780let Inst{31-25} = 0b0101101;
4781let isCall = 1;
4782let prefersSlot3 = 1;
4783let cofRelax2 = 1;
4784let cofMax1 = 1;
4785let Uses = [R29];
4786let Defs = [PC, R31];
4787let BaseOpcode = "J2_call";
4788let isPredicable = 1;
4789let hasSideEffects = 1;
4790let isExtendable = 1;
4791let opExtendable = 0;
4792let isExtentSigned = 1;
4793let opExtentBits = 24;
4794let opExtentAlign = 2;
4795}
4796def J2_callf : HInst<
4797(outs),
4798(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4799"if (!$Pu4) call $Ii",
4800tc_1d81e60e, TypeJ>, Enc_daea09, PredRel {
4801let Inst{0-0} = 0b0;
4802let Inst{12-10} = 0b000;
4803let Inst{21-21} = 0b1;
4804let Inst{31-24} = 0b01011101;
4805let isPredicated = 1;
4806let isPredicatedFalse = 1;
4807let isCall = 1;
4808let prefersSlot3 = 1;
4809let cofRelax1 = 1;
4810let cofRelax2 = 1;
4811let cofMax1 = 1;
4812let Uses = [R29];
4813let Defs = [PC, R31];
4814let BaseOpcode = "J2_call";
4815let hasSideEffects = 1;
4816let isTaken = Inst{12};
4817let isExtendable = 1;
4818let opExtendable = 1;
4819let isExtentSigned = 1;
4820let opExtentBits = 17;
4821let opExtentAlign = 2;
4822}
4823def J2_callr : HInst<
4824(outs),
4825(ins IntRegs:$Rs32),
4826"callr $Rs32",
4827tc_3bd75825, TypeJ>, Enc_ecbcc8 {
4828let Inst{13-0} = 0b00000000000000;
4829let Inst{31-21} = 0b01010000101;
4830let isCall = 1;
4831let prefersSlot3 = 1;
4832let cofMax1 = 1;
4833let Uses = [R29];
4834let Defs = [PC, R31];
4835let hasSideEffects = 1;
4836}
4837def J2_callrf : HInst<
4838(outs),
4839(ins PredRegs:$Pu4, IntRegs:$Rs32),
4840"if (!$Pu4) callr $Rs32",
4841tc_1ad90acd, TypeJ>, Enc_88d4d9 {
4842let Inst{7-0} = 0b00000000;
4843let Inst{13-10} = 0b0000;
4844let Inst{31-21} = 0b01010001001;
4845let isPredicated = 1;
4846let isPredicatedFalse = 1;
4847let isCall = 1;
4848let prefersSlot3 = 1;
4849let cofMax1 = 1;
4850let Uses = [R29];
4851let Defs = [PC, R31];
4852let hasSideEffects = 1;
4853let isTaken = Inst{12};
4854}
4855def J2_callrt : HInst<
4856(outs),
4857(ins PredRegs:$Pu4, IntRegs:$Rs32),
4858"if ($Pu4) callr $Rs32",
4859tc_1ad90acd, TypeJ>, Enc_88d4d9 {
4860let Inst{7-0} = 0b00000000;
4861let Inst{13-10} = 0b0000;
4862let Inst{31-21} = 0b01010001000;
4863let isPredicated = 1;
4864let isCall = 1;
4865let prefersSlot3 = 1;
4866let cofMax1 = 1;
4867let Uses = [R29];
4868let Defs = [PC, R31];
4869let hasSideEffects = 1;
4870let isTaken = Inst{12};
4871}
4872def J2_callt : HInst<
4873(outs),
4874(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4875"if ($Pu4) call $Ii",
4876tc_1d81e60e, TypeJ>, Enc_daea09, PredRel {
4877let Inst{0-0} = 0b0;
4878let Inst{12-10} = 0b000;
4879let Inst{21-21} = 0b0;
4880let Inst{31-24} = 0b01011101;
4881let isPredicated = 1;
4882let isCall = 1;
4883let prefersSlot3 = 1;
4884let cofRelax1 = 1;
4885let cofRelax2 = 1;
4886let cofMax1 = 1;
4887let Uses = [R29];
4888let Defs = [PC, R31];
4889let BaseOpcode = "J2_call";
4890let hasSideEffects = 1;
4891let isTaken = Inst{12};
4892let isExtendable = 1;
4893let opExtendable = 1;
4894let isExtentSigned = 1;
4895let opExtentBits = 17;
4896let opExtentAlign = 2;
4897}
4898def J2_endloop0 : HInst<
4899(outs),
4900(ins),
4901"endloop0",
4902tc_1b6f7cec, TypeJ> {
4903let Uses = [LC0, SA0];
4904let Defs = [LC0, P3, PC, USR];
4905let isBranch = 1;
4906let isTerminator = 1;
4907let isPseudo = 1;
4908}
4909def J2_endloop01 : HInst<
4910(outs),
4911(ins),
4912"endloop01",
4913tc_1b6f7cec, TypeJ> {
4914let Uses = [LC0, LC1, SA0, SA1];
4915let Defs = [LC0, LC1, P3, PC, USR];
4916let isPseudo = 1;
4917}
4918def J2_endloop1 : HInst<
4919(outs),
4920(ins),
4921"endloop1",
4922tc_1b6f7cec, TypeJ> {
4923let Uses = [LC1, SA1];
4924let Defs = [LC1, PC];
4925let isBranch = 1;
4926let isTerminator = 1;
4927let isPseudo = 1;
4928}
4929def J2_jump : HInst<
4930(outs),
4931(ins b30_2Imm:$Ii),
4932"jump $Ii",
4933tc_ae53734a, TypeJ>, Enc_81ac1d, PredNewRel {
4934let Inst{0-0} = 0b0;
4935let Inst{31-25} = 0b0101100;
4936let isTerminator = 1;
4937let isBranch = 1;
4938let cofRelax2 = 1;
4939let cofMax1 = 1;
4940let Defs = [PC];
4941let InputType = "imm";
4942let BaseOpcode = "J2_jump";
4943let isBarrier = 1;
4944let isPredicable = 1;
4945let isExtendable = 1;
4946let opExtendable = 0;
4947let isExtentSigned = 1;
4948let opExtentBits = 24;
4949let opExtentAlign = 2;
4950}
4951def J2_jumpf : HInst<
4952(outs),
4953(ins PredRegs:$Pu4, b30_2Imm:$Ii),
4954"if (!$Pu4) jump:nt $Ii",
4955tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel {
4956let Inst{0-0} = 0b0;
4957let Inst{12-10} = 0b000;
4958let Inst{21-21} = 0b1;
4959let Inst{31-24} = 0b01011100;
4960let isPredicated = 1;
4961let isPredicatedFalse = 1;
4962let isTerminator = 1;
4963let isBranch = 1;
4964let cofRelax1 = 1;
4965let cofRelax2 = 1;
4966let cofMax1 = 1;
4967let Defs = [PC];
4968let InputType = "imm";
4969let BaseOpcode = "J2_jump";
4970let isTaken = Inst{12};
4971let isExtendable = 1;
4972let opExtendable = 1;
4973let isExtentSigned = 1;
4974let opExtentBits = 17;
4975let opExtentAlign = 2;
4976}
4977def J2_jumpf_nopred_map : HInst<
4978(outs),
4979(ins PredRegs:$Pu4, b15_2Imm:$Ii),
4980"if (!$Pu4) jump $Ii",
4981tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> {
4982let isPseudo = 1;
4983let isCodeGenOnly = 1;
4984}
4985def J2_jumpfnew : HInst<
4986(outs),
4987(ins PredRegs:$Pu4, b30_2Imm:$Ii),
4988"if (!$Pu4.new) jump:nt $Ii",
4989tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel {
4990let Inst{0-0} = 0b0;
4991let Inst{12-10} = 0b010;
4992let Inst{21-21} = 0b1;
4993let Inst{31-24} = 0b01011100;
4994let isPredicated = 1;
4995let isPredicatedFalse = 1;
4996let isTerminator = 1;
4997let isBranch = 1;
4998let isPredicatedNew = 1;
4999let cofRelax1 = 1;
5000let cofRelax2 = 1;
5001let cofMax1 = 1;
5002let Defs = [PC];
5003let InputType = "imm";
5004let BaseOpcode = "J2_jump";
5005let isTaken = Inst{12};
5006let isExtendable = 1;
5007let opExtendable = 1;
5008let isExtentSigned = 1;
5009let opExtentBits = 17;
5010let opExtentAlign = 2;
5011}
5012def J2_jumpfnewpt : HInst<
5013(outs),
5014(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5015"if (!$Pu4.new) jump:t $Ii",
5016tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel {
5017let Inst{0-0} = 0b0;
5018let Inst{12-10} = 0b110;
5019let Inst{21-21} = 0b1;
5020let Inst{31-24} = 0b01011100;
5021let isPredicated = 1;
5022let isPredicatedFalse = 1;
5023let isTerminator = 1;
5024let isBranch = 1;
5025let isPredicatedNew = 1;
5026let cofRelax1 = 1;
5027let cofRelax2 = 1;
5028let cofMax1 = 1;
5029let Defs = [PC];
5030let InputType = "imm";
5031let BaseOpcode = "J2_jump";
5032let isTaken = Inst{12};
5033let isExtendable = 1;
5034let opExtendable = 1;
5035let isExtentSigned = 1;
5036let opExtentBits = 17;
5037let opExtentAlign = 2;
5038}
5039def J2_jumpfpt : HInst<
5040(outs),
5041(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5042"if (!$Pu4) jump:t $Ii",
5043tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5044let Inst{0-0} = 0b0;
5045let Inst{12-10} = 0b100;
5046let Inst{21-21} = 0b1;
5047let Inst{31-24} = 0b01011100;
5048let isPredicated = 1;
5049let isPredicatedFalse = 1;
5050let isTerminator = 1;
5051let isBranch = 1;
5052let cofRelax1 = 1;
5053let cofRelax2 = 1;
5054let cofMax1 = 1;
5055let Defs = [PC];
5056let InputType = "imm";
5057let BaseOpcode = "J2_jump";
5058let isTaken = Inst{12};
5059let isExtendable = 1;
5060let opExtendable = 1;
5061let isExtentSigned = 1;
5062let opExtentBits = 17;
5063let opExtentAlign = 2;
5064}
5065def J2_jumpr : HInst<
5066(outs),
5067(ins IntRegs:$Rs32),
5068"jumpr $Rs32",
5069tc_d5b7b0c1, TypeJ>, Enc_ecbcc8, PredNewRel {
5070let Inst{13-0} = 0b00000000000000;
5071let Inst{31-21} = 0b01010010100;
5072let isTerminator = 1;
5073let isIndirectBranch = 1;
5074let isBranch = 1;
5075let cofMax1 = 1;
5076let Defs = [PC];
5077let InputType = "reg";
5078let BaseOpcode = "J2_jumpr";
5079let isBarrier = 1;
5080let isPredicable = 1;
5081}
5082def J2_jumprf : HInst<
5083(outs),
5084(ins PredRegs:$Pu4, IntRegs:$Rs32),
5085"if (!$Pu4) jumpr:nt $Rs32",
5086tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel {
5087let Inst{7-0} = 0b00000000;
5088let Inst{13-10} = 0b0000;
5089let Inst{31-21} = 0b01010011011;
5090let isPredicated = 1;
5091let isPredicatedFalse = 1;
5092let isTerminator = 1;
5093let isIndirectBranch = 1;
5094let isBranch = 1;
5095let cofMax1 = 1;
5096let Defs = [PC];
5097let InputType = "reg";
5098let BaseOpcode = "J2_jumpr";
5099let isTaken = Inst{12};
5100}
5101def J2_jumprf_nopred_map : HInst<
5102(outs),
5103(ins PredRegs:$Pu4, IntRegs:$Rs32),
5104"if (!$Pu4) jumpr $Rs32",
5105tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> {
5106let isPseudo = 1;
5107let isCodeGenOnly = 1;
5108}
5109def J2_jumprfnew : HInst<
5110(outs),
5111(ins PredRegs:$Pu4, IntRegs:$Rs32),
5112"if (!$Pu4.new) jumpr:nt $Rs32",
5113tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel {
5114let Inst{7-0} = 0b00000000;
5115let Inst{13-10} = 0b0010;
5116let Inst{31-21} = 0b01010011011;
5117let isPredicated = 1;
5118let isPredicatedFalse = 1;
5119let isTerminator = 1;
5120let isIndirectBranch = 1;
5121let isBranch = 1;
5122let isPredicatedNew = 1;
5123let cofMax1 = 1;
5124let Defs = [PC];
5125let InputType = "reg";
5126let BaseOpcode = "J2_jumpr";
5127let isTaken = Inst{12};
5128}
5129def J2_jumprfnewpt : HInst<
5130(outs),
5131(ins PredRegs:$Pu4, IntRegs:$Rs32),
5132"if (!$Pu4.new) jumpr:t $Rs32",
5133tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel {
5134let Inst{7-0} = 0b00000000;
5135let Inst{13-10} = 0b0110;
5136let Inst{31-21} = 0b01010011011;
5137let isPredicated = 1;
5138let isPredicatedFalse = 1;
5139let isTerminator = 1;
5140let isIndirectBranch = 1;
5141let isBranch = 1;
5142let isPredicatedNew = 1;
5143let cofMax1 = 1;
5144let Defs = [PC];
5145let InputType = "reg";
5146let BaseOpcode = "J2_jumpr";
5147let isTaken = Inst{12};
5148}
5149def J2_jumprfpt : HInst<
5150(outs),
5151(ins PredRegs:$Pu4, IntRegs:$Rs32),
5152"if (!$Pu4) jumpr:t $Rs32",
5153tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5154let Inst{7-0} = 0b00000000;
5155let Inst{13-10} = 0b0100;
5156let Inst{31-21} = 0b01010011011;
5157let isPredicated = 1;
5158let isPredicatedFalse = 1;
5159let isTerminator = 1;
5160let isIndirectBranch = 1;
5161let isBranch = 1;
5162let cofMax1 = 1;
5163let Defs = [PC];
5164let InputType = "reg";
5165let BaseOpcode = "J2_jumpr";
5166let isTaken = Inst{12};
5167}
5168def J2_jumprgtez : HInst<
5169(outs),
5170(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5171"if ($Rs32>=#0) jump:nt $Ii",
5172tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5173let Inst{0-0} = 0b0;
5174let Inst{12-12} = 0b0;
5175let Inst{31-22} = 0b0110000101;
5176let isPredicated = 1;
5177let isTerminator = 1;
5178let isBranch = 1;
5179let isPredicatedNew = 1;
5180let cofRelax1 = 1;
5181let cofRelax2 = 1;
5182let cofMax1 = 1;
5183let Defs = [PC];
5184let isTaken = Inst{12};
5185}
5186def J2_jumprgtezpt : HInst<
5187(outs),
5188(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5189"if ($Rs32>=#0) jump:t $Ii",
5190tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5191let Inst{0-0} = 0b0;
5192let Inst{12-12} = 0b1;
5193let Inst{31-22} = 0b0110000101;
5194let isPredicated = 1;
5195let isTerminator = 1;
5196let isBranch = 1;
5197let isPredicatedNew = 1;
5198let cofRelax1 = 1;
5199let cofRelax2 = 1;
5200let cofMax1 = 1;
5201let Defs = [PC];
5202let isTaken = Inst{12};
5203}
5204def J2_jumprltez : HInst<
5205(outs),
5206(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5207"if ($Rs32<=#0) jump:nt $Ii",
5208tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5209let Inst{0-0} = 0b0;
5210let Inst{12-12} = 0b0;
5211let Inst{31-22} = 0b0110000111;
5212let isPredicated = 1;
5213let isTerminator = 1;
5214let isBranch = 1;
5215let isPredicatedNew = 1;
5216let cofRelax1 = 1;
5217let cofRelax2 = 1;
5218let cofMax1 = 1;
5219let Defs = [PC];
5220let isTaken = Inst{12};
5221}
5222def J2_jumprltezpt : HInst<
5223(outs),
5224(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5225"if ($Rs32<=#0) jump:t $Ii",
5226tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5227let Inst{0-0} = 0b0;
5228let Inst{12-12} = 0b1;
5229let Inst{31-22} = 0b0110000111;
5230let isPredicated = 1;
5231let isTerminator = 1;
5232let isBranch = 1;
5233let isPredicatedNew = 1;
5234let cofRelax1 = 1;
5235let cofRelax2 = 1;
5236let cofMax1 = 1;
5237let Defs = [PC];
5238let isTaken = Inst{12};
5239}
5240def J2_jumprnz : HInst<
5241(outs),
5242(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5243"if ($Rs32==#0) jump:nt $Ii",
5244tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5245let Inst{0-0} = 0b0;
5246let Inst{12-12} = 0b0;
5247let Inst{31-22} = 0b0110000110;
5248let isPredicated = 1;
5249let isTerminator = 1;
5250let isBranch = 1;
5251let isPredicatedNew = 1;
5252let cofRelax1 = 1;
5253let cofRelax2 = 1;
5254let cofMax1 = 1;
5255let Defs = [PC];
5256let isTaken = Inst{12};
5257}
5258def J2_jumprnzpt : HInst<
5259(outs),
5260(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5261"if ($Rs32==#0) jump:t $Ii",
5262tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5263let Inst{0-0} = 0b0;
5264let Inst{12-12} = 0b1;
5265let Inst{31-22} = 0b0110000110;
5266let isPredicated = 1;
5267let isTerminator = 1;
5268let isBranch = 1;
5269let isPredicatedNew = 1;
5270let cofRelax1 = 1;
5271let cofRelax2 = 1;
5272let cofMax1 = 1;
5273let Defs = [PC];
5274let isTaken = Inst{12};
5275}
5276def J2_jumprt : HInst<
5277(outs),
5278(ins PredRegs:$Pu4, IntRegs:$Rs32),
5279"if ($Pu4) jumpr:nt $Rs32",
5280tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel {
5281let Inst{7-0} = 0b00000000;
5282let Inst{13-10} = 0b0000;
5283let Inst{31-21} = 0b01010011010;
5284let isPredicated = 1;
5285let isTerminator = 1;
5286let isIndirectBranch = 1;
5287let isBranch = 1;
5288let cofMax1 = 1;
5289let Defs = [PC];
5290let InputType = "reg";
5291let BaseOpcode = "J2_jumpr";
5292let isTaken = Inst{12};
5293}
5294def J2_jumprt_nopred_map : HInst<
5295(outs),
5296(ins PredRegs:$Pu4, IntRegs:$Rs32),
5297"if ($Pu4) jumpr $Rs32",
5298tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> {
5299let isPseudo = 1;
5300let isCodeGenOnly = 1;
5301}
5302def J2_jumprtnew : HInst<
5303(outs),
5304(ins PredRegs:$Pu4, IntRegs:$Rs32),
5305"if ($Pu4.new) jumpr:nt $Rs32",
5306tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel {
5307let Inst{7-0} = 0b00000000;
5308let Inst{13-10} = 0b0010;
5309let Inst{31-21} = 0b01010011010;
5310let isPredicated = 1;
5311let isTerminator = 1;
5312let isIndirectBranch = 1;
5313let isBranch = 1;
5314let isPredicatedNew = 1;
5315let cofMax1 = 1;
5316let Defs = [PC];
5317let InputType = "reg";
5318let BaseOpcode = "J2_jumpr";
5319let isTaken = Inst{12};
5320}
5321def J2_jumprtnewpt : HInst<
5322(outs),
5323(ins PredRegs:$Pu4, IntRegs:$Rs32),
5324"if ($Pu4.new) jumpr:t $Rs32",
5325tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel {
5326let Inst{7-0} = 0b00000000;
5327let Inst{13-10} = 0b0110;
5328let Inst{31-21} = 0b01010011010;
5329let isPredicated = 1;
5330let isTerminator = 1;
5331let isIndirectBranch = 1;
5332let isBranch = 1;
5333let isPredicatedNew = 1;
5334let cofMax1 = 1;
5335let Defs = [PC];
5336let InputType = "reg";
5337let BaseOpcode = "J2_jumpr";
5338let isTaken = Inst{12};
5339}
5340def J2_jumprtpt : HInst<
5341(outs),
5342(ins PredRegs:$Pu4, IntRegs:$Rs32),
5343"if ($Pu4) jumpr:t $Rs32",
5344tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5345let Inst{7-0} = 0b00000000;
5346let Inst{13-10} = 0b0100;
5347let Inst{31-21} = 0b01010011010;
5348let isPredicated = 1;
5349let isTerminator = 1;
5350let isIndirectBranch = 1;
5351let isBranch = 1;
5352let cofMax1 = 1;
5353let Defs = [PC];
5354let InputType = "reg";
5355let BaseOpcode = "J2_jumpr";
5356let isTaken = Inst{12};
5357}
5358def J2_jumprz : HInst<
5359(outs),
5360(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5361"if ($Rs32!=#0) jump:nt $Ii",
5362tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5363let Inst{0-0} = 0b0;
5364let Inst{12-12} = 0b0;
5365let Inst{31-22} = 0b0110000100;
5366let isPredicated = 1;
5367let isTerminator = 1;
5368let isBranch = 1;
5369let isPredicatedNew = 1;
5370let cofRelax1 = 1;
5371let cofRelax2 = 1;
5372let cofMax1 = 1;
5373let Defs = [PC];
5374let isTaken = Inst{12};
5375}
5376def J2_jumprzpt : HInst<
5377(outs),
5378(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5379"if ($Rs32!=#0) jump:t $Ii",
5380tc_d9d43ecb, TypeCR>, Enc_0fa531 {
5381let Inst{0-0} = 0b0;
5382let Inst{12-12} = 0b1;
5383let Inst{31-22} = 0b0110000100;
5384let isPredicated = 1;
5385let isTerminator = 1;
5386let isBranch = 1;
5387let isPredicatedNew = 1;
5388let cofRelax1 = 1;
5389let cofRelax2 = 1;
5390let cofMax1 = 1;
5391let Defs = [PC];
5392let isTaken = Inst{12};
5393}
5394def J2_jumpt : HInst<
5395(outs),
5396(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5397"if ($Pu4) jump:nt $Ii",
5398tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel {
5399let Inst{0-0} = 0b0;
5400let Inst{12-10} = 0b000;
5401let Inst{21-21} = 0b0;
5402let Inst{31-24} = 0b01011100;
5403let isPredicated = 1;
5404let isTerminator = 1;
5405let isBranch = 1;
5406let cofRelax1 = 1;
5407let cofRelax2 = 1;
5408let cofMax1 = 1;
5409let Defs = [PC];
5410let InputType = "imm";
5411let BaseOpcode = "J2_jump";
5412let isTaken = Inst{12};
5413let isExtendable = 1;
5414let opExtendable = 1;
5415let isExtentSigned = 1;
5416let opExtentBits = 17;
5417let opExtentAlign = 2;
5418}
5419def J2_jumpt_nopred_map : HInst<
5420(outs),
5421(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5422"if ($Pu4) jump $Ii",
5423tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> {
5424let isPseudo = 1;
5425let isCodeGenOnly = 1;
5426}
5427def J2_jumptnew : HInst<
5428(outs),
5429(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5430"if ($Pu4.new) jump:nt $Ii",
5431tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel {
5432let Inst{0-0} = 0b0;
5433let Inst{12-10} = 0b010;
5434let Inst{21-21} = 0b0;
5435let Inst{31-24} = 0b01011100;
5436let isPredicated = 1;
5437let isTerminator = 1;
5438let isBranch = 1;
5439let isPredicatedNew = 1;
5440let cofRelax1 = 1;
5441let cofRelax2 = 1;
5442let cofMax1 = 1;
5443let Defs = [PC];
5444let InputType = "imm";
5445let BaseOpcode = "J2_jump";
5446let isTaken = Inst{12};
5447let isExtendable = 1;
5448let opExtendable = 1;
5449let isExtentSigned = 1;
5450let opExtentBits = 17;
5451let opExtentAlign = 2;
5452}
5453def J2_jumptnewpt : HInst<
5454(outs),
5455(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5456"if ($Pu4.new) jump:t $Ii",
5457tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel {
5458let Inst{0-0} = 0b0;
5459let Inst{12-10} = 0b110;
5460let Inst{21-21} = 0b0;
5461let Inst{31-24} = 0b01011100;
5462let isPredicated = 1;
5463let isTerminator = 1;
5464let isBranch = 1;
5465let isPredicatedNew = 1;
5466let cofRelax1 = 1;
5467let cofRelax2 = 1;
5468let cofMax1 = 1;
5469let Defs = [PC];
5470let InputType = "imm";
5471let BaseOpcode = "J2_jump";
5472let isTaken = Inst{12};
5473let isExtendable = 1;
5474let opExtendable = 1;
5475let isExtentSigned = 1;
5476let opExtentBits = 17;
5477let opExtentAlign = 2;
5478}
5479def J2_jumptpt : HInst<
5480(outs),
5481(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5482"if ($Pu4) jump:t $Ii",
5483tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5484let Inst{0-0} = 0b0;
5485let Inst{12-10} = 0b100;
5486let Inst{21-21} = 0b0;
5487let Inst{31-24} = 0b01011100;
5488let isPredicated = 1;
5489let isTerminator = 1;
5490let isBranch = 1;
5491let cofRelax1 = 1;
5492let cofRelax2 = 1;
5493let cofMax1 = 1;
5494let Defs = [PC];
5495let InputType = "imm";
5496let BaseOpcode = "J2_jump";
5497let isTaken = Inst{12};
5498let isExtendable = 1;
5499let opExtendable = 1;
5500let isExtentSigned = 1;
5501let opExtentBits = 17;
5502let opExtentAlign = 2;
5503}
5504def J2_loop0i : HInst<
5505(outs),
5506(ins b30_2Imm:$Ii, u10_0Imm:$II),
5507"loop0($Ii,#$II)",
5508tc_a9d88b22, TypeCR>, Enc_4dc228 {
5509let Inst{2-2} = 0b0;
5510let Inst{13-13} = 0b0;
5511let Inst{31-21} = 0b01101001000;
5512let cofRelax1 = 1;
5513let cofRelax2 = 1;
5514let Defs = [LC0, SA0, USR];
5515let isExtendable = 1;
5516let opExtendable = 0;
5517let isExtentSigned = 1;
5518let opExtentBits = 9;
5519let opExtentAlign = 2;
5520}
5521def J2_loop0r : HInst<
5522(outs),
5523(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5524"loop0($Ii,$Rs32)",
5525tc_df3319ed, TypeCR>, Enc_864a5a {
5526let Inst{2-0} = 0b000;
5527let Inst{7-5} = 0b000;
5528let Inst{13-13} = 0b0;
5529let Inst{31-21} = 0b01100000000;
5530let cofRelax1 = 1;
5531let cofRelax2 = 1;
5532let Defs = [LC0, SA0, USR];
5533let isExtendable = 1;
5534let opExtendable = 0;
5535let isExtentSigned = 1;
5536let opExtentBits = 9;
5537let opExtentAlign = 2;
5538}
5539def J2_loop1i : HInst<
5540(outs),
5541(ins b30_2Imm:$Ii, u10_0Imm:$II),
5542"loop1($Ii,#$II)",
5543tc_a9d88b22, TypeCR>, Enc_4dc228 {
5544let Inst{2-2} = 0b0;
5545let Inst{13-13} = 0b0;
5546let Inst{31-21} = 0b01101001001;
5547let cofRelax1 = 1;
5548let cofRelax2 = 1;
5549let Defs = [LC1, SA1];
5550let isExtendable = 1;
5551let opExtendable = 0;
5552let isExtentSigned = 1;
5553let opExtentBits = 9;
5554let opExtentAlign = 2;
5555}
5556def J2_loop1r : HInst<
5557(outs),
5558(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5559"loop1($Ii,$Rs32)",
5560tc_df3319ed, TypeCR>, Enc_864a5a {
5561let Inst{2-0} = 0b000;
5562let Inst{7-5} = 0b000;
5563let Inst{13-13} = 0b0;
5564let Inst{31-21} = 0b01100000001;
5565let cofRelax1 = 1;
5566let cofRelax2 = 1;
5567let Defs = [LC1, SA1];
5568let isExtendable = 1;
5569let opExtendable = 0;
5570let isExtentSigned = 1;
5571let opExtentBits = 9;
5572let opExtentAlign = 2;
5573}
5574def J2_pause : HInst<
5575(outs),
5576(ins u8_0Imm:$Ii),
5577"pause(#$Ii)",
5578tc_8d9d0154, TypeJ>, Enc_a51a9a {
5579let Inst{1-0} = 0b00;
5580let Inst{7-5} = 0b000;
5581let Inst{13-13} = 0b0;
5582let Inst{31-16} = 0b0101010001000000;
5583let isSolo = 1;
5584}
5585def J2_ploop1si : HInst<
5586(outs),
5587(ins b30_2Imm:$Ii, u10_0Imm:$II),
5588"p3 = sp1loop0($Ii,#$II)",
5589tc_1c4528a2, TypeCR>, Enc_4dc228 {
5590let Inst{2-2} = 0b0;
5591let Inst{13-13} = 0b0;
5592let Inst{31-21} = 0b01101001101;
5593let isPredicateLate = 1;
5594let cofRelax1 = 1;
5595let cofRelax2 = 1;
5596let Defs = [LC0, P3, SA0, USR];
5597let isExtendable = 1;
5598let opExtendable = 0;
5599let isExtentSigned = 1;
5600let opExtentBits = 9;
5601let opExtentAlign = 2;
5602}
5603def J2_ploop1sr : HInst<
5604(outs),
5605(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5606"p3 = sp1loop0($Ii,$Rs32)",
5607tc_32779c6f, TypeCR>, Enc_864a5a {
5608let Inst{2-0} = 0b000;
5609let Inst{7-5} = 0b000;
5610let Inst{13-13} = 0b0;
5611let Inst{31-21} = 0b01100000101;
5612let isPredicateLate = 1;
5613let cofRelax1 = 1;
5614let cofRelax2 = 1;
5615let Defs = [LC0, P3, SA0, USR];
5616let isExtendable = 1;
5617let opExtendable = 0;
5618let isExtentSigned = 1;
5619let opExtentBits = 9;
5620let opExtentAlign = 2;
5621}
5622def J2_ploop2si : HInst<
5623(outs),
5624(ins b30_2Imm:$Ii, u10_0Imm:$II),
5625"p3 = sp2loop0($Ii,#$II)",
5626tc_1c4528a2, TypeCR>, Enc_4dc228 {
5627let Inst{2-2} = 0b0;
5628let Inst{13-13} = 0b0;
5629let Inst{31-21} = 0b01101001110;
5630let isPredicateLate = 1;
5631let cofRelax1 = 1;
5632let cofRelax2 = 1;
5633let Defs = [LC0, P3, SA0, USR];
5634let isExtendable = 1;
5635let opExtendable = 0;
5636let isExtentSigned = 1;
5637let opExtentBits = 9;
5638let opExtentAlign = 2;
5639}
5640def J2_ploop2sr : HInst<
5641(outs),
5642(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5643"p3 = sp2loop0($Ii,$Rs32)",
5644tc_32779c6f, TypeCR>, Enc_864a5a {
5645let Inst{2-0} = 0b000;
5646let Inst{7-5} = 0b000;
5647let Inst{13-13} = 0b0;
5648let Inst{31-21} = 0b01100000110;
5649let isPredicateLate = 1;
5650let cofRelax1 = 1;
5651let cofRelax2 = 1;
5652let Defs = [LC0, P3, SA0, USR];
5653let isExtendable = 1;
5654let opExtendable = 0;
5655let isExtentSigned = 1;
5656let opExtentBits = 9;
5657let opExtentAlign = 2;
5658}
5659def J2_ploop3si : HInst<
5660(outs),
5661(ins b30_2Imm:$Ii, u10_0Imm:$II),
5662"p3 = sp3loop0($Ii,#$II)",
5663tc_1c4528a2, TypeCR>, Enc_4dc228 {
5664let Inst{2-2} = 0b0;
5665let Inst{13-13} = 0b0;
5666let Inst{31-21} = 0b01101001111;
5667let isPredicateLate = 1;
5668let cofRelax1 = 1;
5669let cofRelax2 = 1;
5670let Defs = [LC0, P3, SA0, USR];
5671let isExtendable = 1;
5672let opExtendable = 0;
5673let isExtentSigned = 1;
5674let opExtentBits = 9;
5675let opExtentAlign = 2;
5676}
5677def J2_ploop3sr : HInst<
5678(outs),
5679(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5680"p3 = sp3loop0($Ii,$Rs32)",
5681tc_32779c6f, TypeCR>, Enc_864a5a {
5682let Inst{2-0} = 0b000;
5683let Inst{7-5} = 0b000;
5684let Inst{13-13} = 0b0;
5685let Inst{31-21} = 0b01100000111;
5686let isPredicateLate = 1;
5687let cofRelax1 = 1;
5688let cofRelax2 = 1;
5689let Defs = [LC0, P3, SA0, USR];
5690let isExtendable = 1;
5691let opExtendable = 0;
5692let isExtentSigned = 1;
5693let opExtentBits = 9;
5694let opExtentAlign = 2;
5695}
5696def J2_trap0 : HInst<
5697(outs),
5698(ins u8_0Imm:$Ii),
5699"trap0(#$Ii)",
5700tc_fc3999b4, TypeJ>, Enc_a51a9a {
5701let Inst{1-0} = 0b00;
5702let Inst{7-5} = 0b000;
5703let Inst{13-13} = 0b0;
5704let Inst{31-16} = 0b0101010000000000;
5705let isSolo = 1;
5706let hasSideEffects = 1;
5707}
5708def J2_trap1 : HInst<
5709(outs IntRegs:$Rx32),
5710(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
5711"trap1($Rx32,#$Ii)",
5712tc_b9e09e03, TypeJ>, Enc_33f8ba {
5713let Inst{1-0} = 0b00;
5714let Inst{7-5} = 0b000;
5715let Inst{13-13} = 0b0;
5716let Inst{31-21} = 0b01010100100;
5717let hasNewValue = 1;
5718let opNewValue = 0;
5719let isSolo = 1;
5720let Uses = [GOSP];
5721let Defs = [GOSP, PC];
5722let hasSideEffects = 1;
5723let Constraints = "$Rx32 = $Rx32in";
5724}
5725def J2_trap1_noregmap : HInst<
5726(outs),
5727(ins u8_0Imm:$Ii),
5728"trap1(#$Ii)",
5729tc_b9e09e03, TypeMAPPING> {
5730let hasSideEffects = 1;
5731let isPseudo = 1;
5732let isCodeGenOnly = 1;
5733}
5734def J4_cmpeq_f_jumpnv_nt : HInst<
5735(outs),
5736(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5737"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5738tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
5739let Inst{0-0} = 0b0;
5740let Inst{13-13} = 0b0;
5741let Inst{19-19} = 0b0;
5742let Inst{31-22} = 0b0010000001;
5743let isPredicated = 1;
5744let isPredicatedFalse = 1;
5745let isTerminator = 1;
5746let isBranch = 1;
5747let isNewValue = 1;
5748let cofMax1 = 1;
5749let isRestrictNoSlot1Store = 1;
5750let Defs = [PC];
5751let BaseOpcode = "J4_cmpeqr";
5752let isTaken = Inst{13};
5753let isExtendable = 1;
5754let opExtendable = 2;
5755let isExtentSigned = 1;
5756let opExtentBits = 11;
5757let opExtentAlign = 2;
5758let opNewValue = 0;
5759}
5760def J4_cmpeq_f_jumpnv_t : HInst<
5761(outs),
5762(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5763"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5764tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
5765let Inst{0-0} = 0b0;
5766let Inst{13-13} = 0b1;
5767let Inst{19-19} = 0b0;
5768let Inst{31-22} = 0b0010000001;
5769let isPredicated = 1;
5770let isPredicatedFalse = 1;
5771let isTerminator = 1;
5772let isBranch = 1;
5773let isNewValue = 1;
5774let cofMax1 = 1;
5775let isRestrictNoSlot1Store = 1;
5776let Defs = [PC];
5777let BaseOpcode = "J4_cmpeqr";
5778let isTaken = Inst{13};
5779let isExtendable = 1;
5780let opExtendable = 2;
5781let isExtentSigned = 1;
5782let opExtentBits = 11;
5783let opExtentAlign = 2;
5784let opNewValue = 0;
5785}
5786def J4_cmpeq_fp0_jump_nt : HInst<
5787(outs),
5788(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5789"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
5790tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
5791let Inst{0-0} = 0b0;
5792let Inst{13-12} = 0b00;
5793let Inst{31-22} = 0b0001010001;
5794let isPredicated = 1;
5795let isPredicatedFalse = 1;
5796let isTerminator = 1;
5797let isBranch = 1;
5798let isPredicatedNew = 1;
5799let cofRelax1 = 1;
5800let cofRelax2 = 1;
5801let cofMax1 = 1;
5802let Uses = [P0];
5803let Defs = [P0, PC];
5804let BaseOpcode = "J4_cmpeqp0";
5805let isTaken = Inst{13};
5806let isExtendable = 1;
5807let opExtendable = 2;
5808let isExtentSigned = 1;
5809let opExtentBits = 11;
5810let opExtentAlign = 2;
5811}
5812def J4_cmpeq_fp0_jump_t : HInst<
5813(outs),
5814(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5815"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
5816tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
5817let Inst{0-0} = 0b0;
5818let Inst{13-12} = 0b10;
5819let Inst{31-22} = 0b0001010001;
5820let isPredicated = 1;
5821let isPredicatedFalse = 1;
5822let isTerminator = 1;
5823let isBranch = 1;
5824let isPredicatedNew = 1;
5825let cofRelax1 = 1;
5826let cofRelax2 = 1;
5827let cofMax1 = 1;
5828let Uses = [P0];
5829let Defs = [P0, PC];
5830let BaseOpcode = "J4_cmpeqp0";
5831let isTaken = Inst{13};
5832let isExtendable = 1;
5833let opExtendable = 2;
5834let isExtentSigned = 1;
5835let opExtentBits = 11;
5836let opExtentAlign = 2;
5837}
5838def J4_cmpeq_fp1_jump_nt : HInst<
5839(outs),
5840(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5841"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
5842tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
5843let Inst{0-0} = 0b0;
5844let Inst{13-12} = 0b01;
5845let Inst{31-22} = 0b0001010001;
5846let isPredicated = 1;
5847let isPredicatedFalse = 1;
5848let isTerminator = 1;
5849let isBranch = 1;
5850let isPredicatedNew = 1;
5851let cofRelax1 = 1;
5852let cofRelax2 = 1;
5853let cofMax1 = 1;
5854let Uses = [P1];
5855let Defs = [P1, PC];
5856let BaseOpcode = "J4_cmpeqp1";
5857let isTaken = Inst{13};
5858let isExtendable = 1;
5859let opExtendable = 2;
5860let isExtentSigned = 1;
5861let opExtentBits = 11;
5862let opExtentAlign = 2;
5863}
5864def J4_cmpeq_fp1_jump_t : HInst<
5865(outs),
5866(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5867"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
5868tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
5869let Inst{0-0} = 0b0;
5870let Inst{13-12} = 0b11;
5871let Inst{31-22} = 0b0001010001;
5872let isPredicated = 1;
5873let isPredicatedFalse = 1;
5874let isTerminator = 1;
5875let isBranch = 1;
5876let isPredicatedNew = 1;
5877let cofRelax1 = 1;
5878let cofRelax2 = 1;
5879let cofMax1 = 1;
5880let Uses = [P1];
5881let Defs = [P1, PC];
5882let BaseOpcode = "J4_cmpeqp1";
5883let isTaken = Inst{13};
5884let isExtendable = 1;
5885let opExtendable = 2;
5886let isExtentSigned = 1;
5887let opExtentBits = 11;
5888let opExtentAlign = 2;
5889}
5890def J4_cmpeq_t_jumpnv_nt : HInst<
5891(outs),
5892(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5893"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5894tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
5895let Inst{0-0} = 0b0;
5896let Inst{13-13} = 0b0;
5897let Inst{19-19} = 0b0;
5898let Inst{31-22} = 0b0010000000;
5899let isPredicated = 1;
5900let isTerminator = 1;
5901let isBranch = 1;
5902let isNewValue = 1;
5903let cofMax1 = 1;
5904let isRestrictNoSlot1Store = 1;
5905let Defs = [PC];
5906let BaseOpcode = "J4_cmpeqr";
5907let isTaken = Inst{13};
5908let isExtendable = 1;
5909let opExtendable = 2;
5910let isExtentSigned = 1;
5911let opExtentBits = 11;
5912let opExtentAlign = 2;
5913let opNewValue = 0;
5914}
5915def J4_cmpeq_t_jumpnv_t : HInst<
5916(outs),
5917(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5918"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5919tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
5920let Inst{0-0} = 0b0;
5921let Inst{13-13} = 0b1;
5922let Inst{19-19} = 0b0;
5923let Inst{31-22} = 0b0010000000;
5924let isPredicated = 1;
5925let isTerminator = 1;
5926let isBranch = 1;
5927let isNewValue = 1;
5928let cofMax1 = 1;
5929let isRestrictNoSlot1Store = 1;
5930let Defs = [PC];
5931let BaseOpcode = "J4_cmpeqr";
5932let isTaken = Inst{13};
5933let isExtendable = 1;
5934let opExtendable = 2;
5935let isExtentSigned = 1;
5936let opExtentBits = 11;
5937let opExtentAlign = 2;
5938let opNewValue = 0;
5939}
5940def J4_cmpeq_tp0_jump_nt : HInst<
5941(outs),
5942(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5943"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
5944tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
5945let Inst{0-0} = 0b0;
5946let Inst{13-12} = 0b00;
5947let Inst{31-22} = 0b0001010000;
5948let isPredicated = 1;
5949let isTerminator = 1;
5950let isBranch = 1;
5951let isPredicatedNew = 1;
5952let cofRelax1 = 1;
5953let cofRelax2 = 1;
5954let cofMax1 = 1;
5955let Uses = [P0];
5956let Defs = [P0, PC];
5957let BaseOpcode = "J4_cmpeqp0";
5958let isTaken = Inst{13};
5959let isExtendable = 1;
5960let opExtendable = 2;
5961let isExtentSigned = 1;
5962let opExtentBits = 11;
5963let opExtentAlign = 2;
5964}
5965def J4_cmpeq_tp0_jump_t : HInst<
5966(outs),
5967(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5968"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
5969tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
5970let Inst{0-0} = 0b0;
5971let Inst{13-12} = 0b10;
5972let Inst{31-22} = 0b0001010000;
5973let isPredicated = 1;
5974let isTerminator = 1;
5975let isBranch = 1;
5976let isPredicatedNew = 1;
5977let cofRelax1 = 1;
5978let cofRelax2 = 1;
5979let cofMax1 = 1;
5980let Uses = [P0];
5981let Defs = [P0, PC];
5982let BaseOpcode = "J4_cmpeqp0";
5983let isTaken = Inst{13};
5984let isExtendable = 1;
5985let opExtendable = 2;
5986let isExtentSigned = 1;
5987let opExtentBits = 11;
5988let opExtentAlign = 2;
5989}
5990def J4_cmpeq_tp1_jump_nt : HInst<
5991(outs),
5992(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5993"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
5994tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
5995let Inst{0-0} = 0b0;
5996let Inst{13-12} = 0b01;
5997let Inst{31-22} = 0b0001010000;
5998let isPredicated = 1;
5999let isTerminator = 1;
6000let isBranch = 1;
6001let isPredicatedNew = 1;
6002let cofRelax1 = 1;
6003let cofRelax2 = 1;
6004let cofMax1 = 1;
6005let Uses = [P1];
6006let Defs = [P1, PC];
6007let BaseOpcode = "J4_cmpeqp1";
6008let isTaken = Inst{13};
6009let isExtendable = 1;
6010let opExtendable = 2;
6011let isExtentSigned = 1;
6012let opExtentBits = 11;
6013let opExtentAlign = 2;
6014}
6015def J4_cmpeq_tp1_jump_t : HInst<
6016(outs),
6017(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6018"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6019tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6020let Inst{0-0} = 0b0;
6021let Inst{13-12} = 0b11;
6022let Inst{31-22} = 0b0001010000;
6023let isPredicated = 1;
6024let isTerminator = 1;
6025let isBranch = 1;
6026let isPredicatedNew = 1;
6027let cofRelax1 = 1;
6028let cofRelax2 = 1;
6029let cofMax1 = 1;
6030let Uses = [P1];
6031let Defs = [P1, PC];
6032let BaseOpcode = "J4_cmpeqp1";
6033let isTaken = Inst{13};
6034let isExtendable = 1;
6035let opExtendable = 2;
6036let isExtentSigned = 1;
6037let opExtentBits = 11;
6038let opExtentAlign = 2;
6039}
6040def J4_cmpeqi_f_jumpnv_nt : HInst<
6041(outs),
6042(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6043"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6044tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
6045let Inst{0-0} = 0b0;
6046let Inst{13-13} = 0b0;
6047let Inst{19-19} = 0b0;
6048let Inst{31-22} = 0b0010010001;
6049let isPredicated = 1;
6050let isPredicatedFalse = 1;
6051let isTerminator = 1;
6052let isBranch = 1;
6053let isNewValue = 1;
6054let cofMax1 = 1;
6055let isRestrictNoSlot1Store = 1;
6056let Defs = [PC];
6057let BaseOpcode = "J4_cmpeqi";
6058let isTaken = Inst{13};
6059let isExtendable = 1;
6060let opExtendable = 2;
6061let isExtentSigned = 1;
6062let opExtentBits = 11;
6063let opExtentAlign = 2;
6064let opNewValue = 0;
6065}
6066def J4_cmpeqi_f_jumpnv_t : HInst<
6067(outs),
6068(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6069"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6070tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
6071let Inst{0-0} = 0b0;
6072let Inst{13-13} = 0b1;
6073let Inst{19-19} = 0b0;
6074let Inst{31-22} = 0b0010010001;
6075let isPredicated = 1;
6076let isPredicatedFalse = 1;
6077let isTerminator = 1;
6078let isBranch = 1;
6079let isNewValue = 1;
6080let cofMax1 = 1;
6081let isRestrictNoSlot1Store = 1;
6082let Defs = [PC];
6083let BaseOpcode = "J4_cmpeqi";
6084let isTaken = Inst{13};
6085let isExtendable = 1;
6086let opExtendable = 2;
6087let isExtentSigned = 1;
6088let opExtentBits = 11;
6089let opExtentAlign = 2;
6090let opNewValue = 0;
6091}
6092def J4_cmpeqi_fp0_jump_nt : HInst<
6093(outs),
6094(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6095"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
6096tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6097let Inst{0-0} = 0b0;
6098let Inst{13-13} = 0b0;
6099let Inst{31-22} = 0b0001000001;
6100let isPredicated = 1;
6101let isPredicatedFalse = 1;
6102let isTerminator = 1;
6103let isBranch = 1;
6104let isPredicatedNew = 1;
6105let cofRelax1 = 1;
6106let cofRelax2 = 1;
6107let cofMax1 = 1;
6108let Uses = [P0];
6109let Defs = [P0, PC];
6110let BaseOpcode = "J4_cmpeqip0";
6111let isTaken = Inst{13};
6112let isExtendable = 1;
6113let opExtendable = 2;
6114let isExtentSigned = 1;
6115let opExtentBits = 11;
6116let opExtentAlign = 2;
6117}
6118def J4_cmpeqi_fp0_jump_t : HInst<
6119(outs),
6120(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6121"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
6122tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6123let Inst{0-0} = 0b0;
6124let Inst{13-13} = 0b1;
6125let Inst{31-22} = 0b0001000001;
6126let isPredicated = 1;
6127let isPredicatedFalse = 1;
6128let isTerminator = 1;
6129let isBranch = 1;
6130let isPredicatedNew = 1;
6131let cofRelax1 = 1;
6132let cofRelax2 = 1;
6133let cofMax1 = 1;
6134let Uses = [P0];
6135let Defs = [P0, PC];
6136let BaseOpcode = "J4_cmpeqip0";
6137let isTaken = Inst{13};
6138let isExtendable = 1;
6139let opExtendable = 2;
6140let isExtentSigned = 1;
6141let opExtentBits = 11;
6142let opExtentAlign = 2;
6143}
6144def J4_cmpeqi_fp1_jump_nt : HInst<
6145(outs),
6146(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6147"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6148tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6149let Inst{0-0} = 0b0;
6150let Inst{13-13} = 0b0;
6151let Inst{31-22} = 0b0001001001;
6152let isPredicated = 1;
6153let isPredicatedFalse = 1;
6154let isTerminator = 1;
6155let isBranch = 1;
6156let isPredicatedNew = 1;
6157let cofRelax1 = 1;
6158let cofRelax2 = 1;
6159let cofMax1 = 1;
6160let Uses = [P1];
6161let Defs = [P1, PC];
6162let BaseOpcode = "J4_cmpeqip1";
6163let isTaken = Inst{13};
6164let isExtendable = 1;
6165let opExtendable = 2;
6166let isExtentSigned = 1;
6167let opExtentBits = 11;
6168let opExtentAlign = 2;
6169}
6170def J4_cmpeqi_fp1_jump_t : HInst<
6171(outs),
6172(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6173"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
6174tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6175let Inst{0-0} = 0b0;
6176let Inst{13-13} = 0b1;
6177let Inst{31-22} = 0b0001001001;
6178let isPredicated = 1;
6179let isPredicatedFalse = 1;
6180let isTerminator = 1;
6181let isBranch = 1;
6182let isPredicatedNew = 1;
6183let cofRelax1 = 1;
6184let cofRelax2 = 1;
6185let cofMax1 = 1;
6186let Uses = [P1];
6187let Defs = [P1, PC];
6188let BaseOpcode = "J4_cmpeqip1";
6189let isTaken = Inst{13};
6190let isExtendable = 1;
6191let opExtendable = 2;
6192let isExtentSigned = 1;
6193let opExtentBits = 11;
6194let opExtentAlign = 2;
6195}
6196def J4_cmpeqi_t_jumpnv_nt : HInst<
6197(outs),
6198(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6199"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6200tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
6201let Inst{0-0} = 0b0;
6202let Inst{13-13} = 0b0;
6203let Inst{19-19} = 0b0;
6204let Inst{31-22} = 0b0010010000;
6205let isPredicated = 1;
6206let isTerminator = 1;
6207let isBranch = 1;
6208let isNewValue = 1;
6209let cofMax1 = 1;
6210let isRestrictNoSlot1Store = 1;
6211let Defs = [PC];
6212let BaseOpcode = "J4_cmpeqi";
6213let isTaken = Inst{13};
6214let isExtendable = 1;
6215let opExtendable = 2;
6216let isExtentSigned = 1;
6217let opExtentBits = 11;
6218let opExtentAlign = 2;
6219let opNewValue = 0;
6220}
6221def J4_cmpeqi_t_jumpnv_t : HInst<
6222(outs),
6223(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6224"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6225tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
6226let Inst{0-0} = 0b0;
6227let Inst{13-13} = 0b1;
6228let Inst{19-19} = 0b0;
6229let Inst{31-22} = 0b0010010000;
6230let isPredicated = 1;
6231let isTerminator = 1;
6232let isBranch = 1;
6233let isNewValue = 1;
6234let cofMax1 = 1;
6235let isRestrictNoSlot1Store = 1;
6236let Defs = [PC];
6237let BaseOpcode = "J4_cmpeqi";
6238let isTaken = Inst{13};
6239let isExtendable = 1;
6240let opExtendable = 2;
6241let isExtentSigned = 1;
6242let opExtentBits = 11;
6243let opExtentAlign = 2;
6244let opNewValue = 0;
6245}
6246def J4_cmpeqi_tp0_jump_nt : HInst<
6247(outs),
6248(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6249"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
6250tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6251let Inst{0-0} = 0b0;
6252let Inst{13-13} = 0b0;
6253let Inst{31-22} = 0b0001000000;
6254let isPredicated = 1;
6255let isTerminator = 1;
6256let isBranch = 1;
6257let isPredicatedNew = 1;
6258let cofRelax1 = 1;
6259let cofRelax2 = 1;
6260let cofMax1 = 1;
6261let Uses = [P0];
6262let Defs = [P0, PC];
6263let BaseOpcode = "J4_cmpeqip0";
6264let isTaken = Inst{13};
6265let isExtendable = 1;
6266let opExtendable = 2;
6267let isExtentSigned = 1;
6268let opExtentBits = 11;
6269let opExtentAlign = 2;
6270}
6271def J4_cmpeqi_tp0_jump_t : HInst<
6272(outs),
6273(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6274"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
6275tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6276let Inst{0-0} = 0b0;
6277let Inst{13-13} = 0b1;
6278let Inst{31-22} = 0b0001000000;
6279let isPredicated = 1;
6280let isTerminator = 1;
6281let isBranch = 1;
6282let isPredicatedNew = 1;
6283let cofRelax1 = 1;
6284let cofRelax2 = 1;
6285let cofMax1 = 1;
6286let Uses = [P0];
6287let Defs = [P0, PC];
6288let BaseOpcode = "J4_cmpeqip0";
6289let isTaken = Inst{13};
6290let isExtendable = 1;
6291let opExtendable = 2;
6292let isExtentSigned = 1;
6293let opExtentBits = 11;
6294let opExtentAlign = 2;
6295}
6296def J4_cmpeqi_tp1_jump_nt : HInst<
6297(outs),
6298(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6299"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
6300tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6301let Inst{0-0} = 0b0;
6302let Inst{13-13} = 0b0;
6303let Inst{31-22} = 0b0001001000;
6304let isPredicated = 1;
6305let isTerminator = 1;
6306let isBranch = 1;
6307let isPredicatedNew = 1;
6308let cofRelax1 = 1;
6309let cofRelax2 = 1;
6310let cofMax1 = 1;
6311let Uses = [P1];
6312let Defs = [P1, PC];
6313let BaseOpcode = "J4_cmpeqip1";
6314let isTaken = Inst{13};
6315let isExtendable = 1;
6316let opExtendable = 2;
6317let isExtentSigned = 1;
6318let opExtentBits = 11;
6319let opExtentAlign = 2;
6320}
6321def J4_cmpeqi_tp1_jump_t : HInst<
6322(outs),
6323(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6324"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
6325tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
6326let Inst{0-0} = 0b0;
6327let Inst{13-13} = 0b1;
6328let Inst{31-22} = 0b0001001000;
6329let isPredicated = 1;
6330let isTerminator = 1;
6331let isBranch = 1;
6332let isPredicatedNew = 1;
6333let cofRelax1 = 1;
6334let cofRelax2 = 1;
6335let cofMax1 = 1;
6336let Uses = [P1];
6337let Defs = [P1, PC];
6338let BaseOpcode = "J4_cmpeqip1";
6339let isTaken = Inst{13};
6340let isExtendable = 1;
6341let opExtendable = 2;
6342let isExtentSigned = 1;
6343let opExtentBits = 11;
6344let opExtentAlign = 2;
6345}
6346def J4_cmpeqn1_f_jumpnv_nt : HInst<
6347(outs),
6348(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6349"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6350tc_bd8382d1, TypeNCJ>, Enc_e90a15, PredRel {
6351let Inst{0-0} = 0b0;
6352let Inst{13-8} = 0b000000;
6353let Inst{19-19} = 0b0;
6354let Inst{31-22} = 0b0010011001;
6355let isPredicated = 1;
6356let isPredicatedFalse = 1;
6357let isTerminator = 1;
6358let isBranch = 1;
6359let isNewValue = 1;
6360let cofMax1 = 1;
6361let isRestrictNoSlot1Store = 1;
6362let Defs = [PC];
6363let BaseOpcode = "J4_cmpeqn1r";
6364let isTaken = Inst{13};
6365let isExtendable = 1;
6366let opExtendable = 2;
6367let isExtentSigned = 1;
6368let opExtentBits = 11;
6369let opExtentAlign = 2;
6370let opNewValue = 0;
6371}
6372def J4_cmpeqn1_f_jumpnv_t : HInst<
6373(outs),
6374(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6375"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6376tc_bd8382d1, TypeNCJ>, Enc_5a18b3, PredRel {
6377let Inst{0-0} = 0b0;
6378let Inst{13-8} = 0b100000;
6379let Inst{19-19} = 0b0;
6380let Inst{31-22} = 0b0010011001;
6381let isPredicated = 1;
6382let isPredicatedFalse = 1;
6383let isTerminator = 1;
6384let isBranch = 1;
6385let isNewValue = 1;
6386let cofMax1 = 1;
6387let isRestrictNoSlot1Store = 1;
6388let Defs = [PC];
6389let BaseOpcode = "J4_cmpeqn1r";
6390let isTaken = Inst{13};
6391let isExtendable = 1;
6392let opExtendable = 2;
6393let isExtentSigned = 1;
6394let opExtentBits = 11;
6395let opExtentAlign = 2;
6396let opNewValue = 0;
6397}
6398def J4_cmpeqn1_fp0_jump_nt : HInst<
6399(outs),
6400(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6401"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
6402tc_3d495a39, TypeCJ>, Enc_1de724, PredRel {
6403let Inst{0-0} = 0b0;
6404let Inst{13-8} = 0b000000;
6405let Inst{31-22} = 0b0001000111;
6406let isPredicated = 1;
6407let isPredicatedFalse = 1;
6408let isTerminator = 1;
6409let isBranch = 1;
6410let isPredicatedNew = 1;
6411let cofRelax1 = 1;
6412let cofRelax2 = 1;
6413let cofMax1 = 1;
6414let Uses = [P0];
6415let Defs = [P0, PC];
6416let BaseOpcode = "J4_cmpeqn1p0";
6417let isTaken = Inst{13};
6418let isExtendable = 1;
6419let opExtendable = 2;
6420let isExtentSigned = 1;
6421let opExtentBits = 11;
6422let opExtentAlign = 2;
6423}
6424def J4_cmpeqn1_fp0_jump_t : HInst<
6425(outs),
6426(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6427"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
6428tc_3d495a39, TypeCJ>, Enc_14640c, PredRel {
6429let Inst{0-0} = 0b0;
6430let Inst{13-8} = 0b100000;
6431let Inst{31-22} = 0b0001000111;
6432let isPredicated = 1;
6433let isPredicatedFalse = 1;
6434let isTerminator = 1;
6435let isBranch = 1;
6436let isPredicatedNew = 1;
6437let cofRelax1 = 1;
6438let cofRelax2 = 1;
6439let cofMax1 = 1;
6440let Uses = [P0];
6441let Defs = [P0, PC];
6442let BaseOpcode = "J4_cmpeqn1p0";
6443let isTaken = Inst{13};
6444let isExtendable = 1;
6445let opExtendable = 2;
6446let isExtentSigned = 1;
6447let opExtentBits = 11;
6448let opExtentAlign = 2;
6449}
6450def J4_cmpeqn1_fp1_jump_nt : HInst<
6451(outs),
6452(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6453"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
6454tc_3d495a39, TypeCJ>, Enc_668704, PredRel {
6455let Inst{0-0} = 0b0;
6456let Inst{13-8} = 0b000000;
6457let Inst{31-22} = 0b0001001111;
6458let isPredicated = 1;
6459let isPredicatedFalse = 1;
6460let isTerminator = 1;
6461let isBranch = 1;
6462let isPredicatedNew = 1;
6463let cofRelax1 = 1;
6464let cofRelax2 = 1;
6465let cofMax1 = 1;
6466let Uses = [P1];
6467let Defs = [P1, PC];
6468let BaseOpcode = "J4_cmpeqn1p1";
6469let isTaken = Inst{13};
6470let isExtendable = 1;
6471let opExtendable = 2;
6472let isExtentSigned = 1;
6473let opExtentBits = 11;
6474let opExtentAlign = 2;
6475}
6476def J4_cmpeqn1_fp1_jump_t : HInst<
6477(outs),
6478(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6479"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
6480tc_3d495a39, TypeCJ>, Enc_800e04, PredRel {
6481let Inst{0-0} = 0b0;
6482let Inst{13-8} = 0b100000;
6483let Inst{31-22} = 0b0001001111;
6484let isPredicated = 1;
6485let isPredicatedFalse = 1;
6486let isTerminator = 1;
6487let isBranch = 1;
6488let isPredicatedNew = 1;
6489let cofRelax1 = 1;
6490let cofRelax2 = 1;
6491let cofMax1 = 1;
6492let Uses = [P1];
6493let Defs = [P1, PC];
6494let BaseOpcode = "J4_cmpeqn1p1";
6495let isTaken = Inst{13};
6496let isExtendable = 1;
6497let opExtendable = 2;
6498let isExtentSigned = 1;
6499let opExtentBits = 11;
6500let opExtentAlign = 2;
6501}
6502def J4_cmpeqn1_t_jumpnv_nt : HInst<
6503(outs),
6504(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6505"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6506tc_bd8382d1, TypeNCJ>, Enc_4aca3a, PredRel {
6507let Inst{0-0} = 0b0;
6508let Inst{13-8} = 0b000000;
6509let Inst{19-19} = 0b0;
6510let Inst{31-22} = 0b0010011000;
6511let isPredicated = 1;
6512let isTerminator = 1;
6513let isBranch = 1;
6514let isNewValue = 1;
6515let cofMax1 = 1;
6516let isRestrictNoSlot1Store = 1;
6517let Defs = [PC];
6518let BaseOpcode = "J4_cmpeqn1r";
6519let isTaken = Inst{13};
6520let isExtendable = 1;
6521let opExtendable = 2;
6522let isExtentSigned = 1;
6523let opExtentBits = 11;
6524let opExtentAlign = 2;
6525let opNewValue = 0;
6526}
6527def J4_cmpeqn1_t_jumpnv_t : HInst<
6528(outs),
6529(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6530"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6531tc_bd8382d1, TypeNCJ>, Enc_f7ea77, PredRel {
6532let Inst{0-0} = 0b0;
6533let Inst{13-8} = 0b100000;
6534let Inst{19-19} = 0b0;
6535let Inst{31-22} = 0b0010011000;
6536let isPredicated = 1;
6537let isTerminator = 1;
6538let isBranch = 1;
6539let isNewValue = 1;
6540let cofMax1 = 1;
6541let isRestrictNoSlot1Store = 1;
6542let Defs = [PC];
6543let BaseOpcode = "J4_cmpeqn1r";
6544let isTaken = Inst{13};
6545let isExtendable = 1;
6546let opExtendable = 2;
6547let isExtentSigned = 1;
6548let opExtentBits = 11;
6549let opExtentAlign = 2;
6550let opNewValue = 0;
6551}
6552def J4_cmpeqn1_tp0_jump_nt : HInst<
6553(outs),
6554(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6555"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
6556tc_3d495a39, TypeCJ>, Enc_405228, PredRel {
6557let Inst{0-0} = 0b0;
6558let Inst{13-8} = 0b000000;
6559let Inst{31-22} = 0b0001000110;
6560let isPredicated = 1;
6561let isTerminator = 1;
6562let isBranch = 1;
6563let isPredicatedNew = 1;
6564let cofRelax1 = 1;
6565let cofRelax2 = 1;
6566let cofMax1 = 1;
6567let Uses = [P0];
6568let Defs = [P0, PC];
6569let BaseOpcode = "J4_cmpeqn1p0";
6570let isTaken = Inst{13};
6571let isExtendable = 1;
6572let opExtendable = 2;
6573let isExtentSigned = 1;
6574let opExtentBits = 11;
6575let opExtentAlign = 2;
6576}
6577def J4_cmpeqn1_tp0_jump_t : HInst<
6578(outs),
6579(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6580"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
6581tc_3d495a39, TypeCJ>, Enc_3a2484, PredRel {
6582let Inst{0-0} = 0b0;
6583let Inst{13-8} = 0b100000;
6584let Inst{31-22} = 0b0001000110;
6585let isPredicated = 1;
6586let isTerminator = 1;
6587let isBranch = 1;
6588let isPredicatedNew = 1;
6589let cofRelax1 = 1;
6590let cofRelax2 = 1;
6591let cofMax1 = 1;
6592let Uses = [P0];
6593let Defs = [P0, PC];
6594let BaseOpcode = "J4_cmpeqn1p0";
6595let isTaken = Inst{13};
6596let isExtendable = 1;
6597let opExtendable = 2;
6598let isExtentSigned = 1;
6599let opExtentBits = 11;
6600let opExtentAlign = 2;
6601}
6602def J4_cmpeqn1_tp1_jump_nt : HInst<
6603(outs),
6604(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6605"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
6606tc_3d495a39, TypeCJ>, Enc_736575, PredRel {
6607let Inst{0-0} = 0b0;
6608let Inst{13-8} = 0b000000;
6609let Inst{31-22} = 0b0001001110;
6610let isPredicated = 1;
6611let isTerminator = 1;
6612let isBranch = 1;
6613let isPredicatedNew = 1;
6614let cofRelax1 = 1;
6615let cofRelax2 = 1;
6616let cofMax1 = 1;
6617let Uses = [P1];
6618let Defs = [P1, PC];
6619let BaseOpcode = "J4_cmpeqn1p1";
6620let isTaken = Inst{13};
6621let isExtendable = 1;
6622let opExtendable = 2;
6623let isExtentSigned = 1;
6624let opExtentBits = 11;
6625let opExtentAlign = 2;
6626}
6627def J4_cmpeqn1_tp1_jump_t : HInst<
6628(outs),
6629(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6630"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
6631tc_3d495a39, TypeCJ>, Enc_8e583a, PredRel {
6632let Inst{0-0} = 0b0;
6633let Inst{13-8} = 0b100000;
6634let Inst{31-22} = 0b0001001110;
6635let isPredicated = 1;
6636let isTerminator = 1;
6637let isBranch = 1;
6638let isPredicatedNew = 1;
6639let cofRelax1 = 1;
6640let cofRelax2 = 1;
6641let cofMax1 = 1;
6642let Uses = [P1];
6643let Defs = [P1, PC];
6644let BaseOpcode = "J4_cmpeqn1p1";
6645let isTaken = Inst{13};
6646let isExtendable = 1;
6647let opExtendable = 2;
6648let isExtentSigned = 1;
6649let opExtentBits = 11;
6650let opExtentAlign = 2;
6651}
6652def J4_cmpgt_f_jumpnv_nt : HInst<
6653(outs),
6654(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6655"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6656tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
6657let Inst{0-0} = 0b0;
6658let Inst{13-13} = 0b0;
6659let Inst{19-19} = 0b0;
6660let Inst{31-22} = 0b0010000011;
6661let isPredicated = 1;
6662let isPredicatedFalse = 1;
6663let isTerminator = 1;
6664let isBranch = 1;
6665let isNewValue = 1;
6666let cofMax1 = 1;
6667let isRestrictNoSlot1Store = 1;
6668let Defs = [PC];
6669let BaseOpcode = "J4_cmpgtr";
6670let isTaken = Inst{13};
6671let isExtendable = 1;
6672let opExtendable = 2;
6673let isExtentSigned = 1;
6674let opExtentBits = 11;
6675let opExtentAlign = 2;
6676let opNewValue = 0;
6677}
6678def J4_cmpgt_f_jumpnv_t : HInst<
6679(outs),
6680(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6681"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6682tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
6683let Inst{0-0} = 0b0;
6684let Inst{13-13} = 0b1;
6685let Inst{19-19} = 0b0;
6686let Inst{31-22} = 0b0010000011;
6687let isPredicated = 1;
6688let isPredicatedFalse = 1;
6689let isTerminator = 1;
6690let isBranch = 1;
6691let isNewValue = 1;
6692let cofMax1 = 1;
6693let isRestrictNoSlot1Store = 1;
6694let Defs = [PC];
6695let BaseOpcode = "J4_cmpgtr";
6696let isTaken = Inst{13};
6697let isExtendable = 1;
6698let opExtendable = 2;
6699let isExtentSigned = 1;
6700let opExtentBits = 11;
6701let opExtentAlign = 2;
6702let opNewValue = 0;
6703}
6704def J4_cmpgt_fp0_jump_nt : HInst<
6705(outs),
6706(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6707"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
6708tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6709let Inst{0-0} = 0b0;
6710let Inst{13-12} = 0b00;
6711let Inst{31-22} = 0b0001010011;
6712let isPredicated = 1;
6713let isPredicatedFalse = 1;
6714let isTerminator = 1;
6715let isBranch = 1;
6716let isPredicatedNew = 1;
6717let cofRelax1 = 1;
6718let cofRelax2 = 1;
6719let cofMax1 = 1;
6720let Uses = [P0];
6721let Defs = [P0, PC];
6722let BaseOpcode = "J4_cmpgtp0";
6723let isTaken = Inst{13};
6724let isExtendable = 1;
6725let opExtendable = 2;
6726let isExtentSigned = 1;
6727let opExtentBits = 11;
6728let opExtentAlign = 2;
6729}
6730def J4_cmpgt_fp0_jump_t : HInst<
6731(outs),
6732(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6733"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
6734tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6735let Inst{0-0} = 0b0;
6736let Inst{13-12} = 0b10;
6737let Inst{31-22} = 0b0001010011;
6738let isPredicated = 1;
6739let isPredicatedFalse = 1;
6740let isTerminator = 1;
6741let isBranch = 1;
6742let isPredicatedNew = 1;
6743let cofRelax1 = 1;
6744let cofRelax2 = 1;
6745let cofMax1 = 1;
6746let Uses = [P0];
6747let Defs = [P0, PC];
6748let BaseOpcode = "J4_cmpgtp0";
6749let isTaken = Inst{13};
6750let isExtendable = 1;
6751let opExtendable = 2;
6752let isExtentSigned = 1;
6753let opExtentBits = 11;
6754let opExtentAlign = 2;
6755}
6756def J4_cmpgt_fp1_jump_nt : HInst<
6757(outs),
6758(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6759"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
6760tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6761let Inst{0-0} = 0b0;
6762let Inst{13-12} = 0b01;
6763let Inst{31-22} = 0b0001010011;
6764let isPredicated = 1;
6765let isPredicatedFalse = 1;
6766let isTerminator = 1;
6767let isBranch = 1;
6768let isPredicatedNew = 1;
6769let cofRelax1 = 1;
6770let cofRelax2 = 1;
6771let cofMax1 = 1;
6772let Uses = [P1];
6773let Defs = [P1, PC];
6774let BaseOpcode = "J4_cmpgtp1";
6775let isTaken = Inst{13};
6776let isExtendable = 1;
6777let opExtendable = 2;
6778let isExtentSigned = 1;
6779let opExtentBits = 11;
6780let opExtentAlign = 2;
6781}
6782def J4_cmpgt_fp1_jump_t : HInst<
6783(outs),
6784(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6785"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6786tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6787let Inst{0-0} = 0b0;
6788let Inst{13-12} = 0b11;
6789let Inst{31-22} = 0b0001010011;
6790let isPredicated = 1;
6791let isPredicatedFalse = 1;
6792let isTerminator = 1;
6793let isBranch = 1;
6794let isPredicatedNew = 1;
6795let cofRelax1 = 1;
6796let cofRelax2 = 1;
6797let cofMax1 = 1;
6798let Uses = [P1];
6799let Defs = [P1, PC];
6800let BaseOpcode = "J4_cmpgtp1";
6801let isTaken = Inst{13};
6802let isExtendable = 1;
6803let opExtendable = 2;
6804let isExtentSigned = 1;
6805let opExtentBits = 11;
6806let opExtentAlign = 2;
6807}
6808def J4_cmpgt_t_jumpnv_nt : HInst<
6809(outs),
6810(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6811"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6812tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
6813let Inst{0-0} = 0b0;
6814let Inst{13-13} = 0b0;
6815let Inst{19-19} = 0b0;
6816let Inst{31-22} = 0b0010000010;
6817let isPredicated = 1;
6818let isTerminator = 1;
6819let isBranch = 1;
6820let isNewValue = 1;
6821let cofMax1 = 1;
6822let isRestrictNoSlot1Store = 1;
6823let Defs = [PC];
6824let BaseOpcode = "J4_cmpgtr";
6825let isTaken = Inst{13};
6826let isExtendable = 1;
6827let opExtendable = 2;
6828let isExtentSigned = 1;
6829let opExtentBits = 11;
6830let opExtentAlign = 2;
6831let opNewValue = 0;
6832}
6833def J4_cmpgt_t_jumpnv_t : HInst<
6834(outs),
6835(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6836"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6837tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
6838let Inst{0-0} = 0b0;
6839let Inst{13-13} = 0b1;
6840let Inst{19-19} = 0b0;
6841let Inst{31-22} = 0b0010000010;
6842let isPredicated = 1;
6843let isTerminator = 1;
6844let isBranch = 1;
6845let isNewValue = 1;
6846let cofMax1 = 1;
6847let isRestrictNoSlot1Store = 1;
6848let Defs = [PC];
6849let BaseOpcode = "J4_cmpgtr";
6850let isTaken = Inst{13};
6851let isExtendable = 1;
6852let opExtendable = 2;
6853let isExtentSigned = 1;
6854let opExtentBits = 11;
6855let opExtentAlign = 2;
6856let opNewValue = 0;
6857}
6858def J4_cmpgt_tp0_jump_nt : HInst<
6859(outs),
6860(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6861"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6862tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6863let Inst{0-0} = 0b0;
6864let Inst{13-12} = 0b00;
6865let Inst{31-22} = 0b0001010010;
6866let isPredicated = 1;
6867let isTerminator = 1;
6868let isBranch = 1;
6869let isPredicatedNew = 1;
6870let cofRelax1 = 1;
6871let cofRelax2 = 1;
6872let cofMax1 = 1;
6873let Uses = [P0];
6874let Defs = [P0, PC];
6875let BaseOpcode = "J4_cmpgtp0";
6876let isTaken = Inst{13};
6877let isExtendable = 1;
6878let opExtendable = 2;
6879let isExtentSigned = 1;
6880let opExtentBits = 11;
6881let opExtentAlign = 2;
6882}
6883def J4_cmpgt_tp0_jump_t : HInst<
6884(outs),
6885(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6886"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6887tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6888let Inst{0-0} = 0b0;
6889let Inst{13-12} = 0b10;
6890let Inst{31-22} = 0b0001010010;
6891let isPredicated = 1;
6892let isTerminator = 1;
6893let isBranch = 1;
6894let isPredicatedNew = 1;
6895let cofRelax1 = 1;
6896let cofRelax2 = 1;
6897let cofMax1 = 1;
6898let Uses = [P0];
6899let Defs = [P0, PC];
6900let BaseOpcode = "J4_cmpgtp0";
6901let isTaken = Inst{13};
6902let isExtendable = 1;
6903let opExtendable = 2;
6904let isExtentSigned = 1;
6905let opExtentBits = 11;
6906let opExtentAlign = 2;
6907}
6908def J4_cmpgt_tp1_jump_nt : HInst<
6909(outs),
6910(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6911"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
6912tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6913let Inst{0-0} = 0b0;
6914let Inst{13-12} = 0b01;
6915let Inst{31-22} = 0b0001010010;
6916let isPredicated = 1;
6917let isTerminator = 1;
6918let isBranch = 1;
6919let isPredicatedNew = 1;
6920let cofRelax1 = 1;
6921let cofRelax2 = 1;
6922let cofMax1 = 1;
6923let Uses = [P1];
6924let Defs = [P1, PC];
6925let BaseOpcode = "J4_cmpgtp1";
6926let isTaken = Inst{13};
6927let isExtendable = 1;
6928let opExtendable = 2;
6929let isExtentSigned = 1;
6930let opExtentBits = 11;
6931let opExtentAlign = 2;
6932}
6933def J4_cmpgt_tp1_jump_t : HInst<
6934(outs),
6935(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6936"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6937tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
6938let Inst{0-0} = 0b0;
6939let Inst{13-12} = 0b11;
6940let Inst{31-22} = 0b0001010010;
6941let isPredicated = 1;
6942let isTerminator = 1;
6943let isBranch = 1;
6944let isPredicatedNew = 1;
6945let cofRelax1 = 1;
6946let cofRelax2 = 1;
6947let cofMax1 = 1;
6948let Uses = [P1];
6949let Defs = [P1, PC];
6950let BaseOpcode = "J4_cmpgtp1";
6951let isTaken = Inst{13};
6952let isExtendable = 1;
6953let opExtendable = 2;
6954let isExtentSigned = 1;
6955let opExtentBits = 11;
6956let opExtentAlign = 2;
6957}
6958def J4_cmpgti_f_jumpnv_nt : HInst<
6959(outs),
6960(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6961"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
6962tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
6963let Inst{0-0} = 0b0;
6964let Inst{13-13} = 0b0;
6965let Inst{19-19} = 0b0;
6966let Inst{31-22} = 0b0010010011;
6967let isPredicated = 1;
6968let isPredicatedFalse = 1;
6969let isTerminator = 1;
6970let isBranch = 1;
6971let isNewValue = 1;
6972let cofMax1 = 1;
6973let isRestrictNoSlot1Store = 1;
6974let Defs = [PC];
6975let BaseOpcode = "J4_cmpgtir";
6976let isTaken = Inst{13};
6977let isExtendable = 1;
6978let opExtendable = 2;
6979let isExtentSigned = 1;
6980let opExtentBits = 11;
6981let opExtentAlign = 2;
6982let opNewValue = 0;
6983}
6984def J4_cmpgti_f_jumpnv_t : HInst<
6985(outs),
6986(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6987"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
6988tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
6989let Inst{0-0} = 0b0;
6990let Inst{13-13} = 0b1;
6991let Inst{19-19} = 0b0;
6992let Inst{31-22} = 0b0010010011;
6993let isPredicated = 1;
6994let isPredicatedFalse = 1;
6995let isTerminator = 1;
6996let isBranch = 1;
6997let isNewValue = 1;
6998let cofMax1 = 1;
6999let isRestrictNoSlot1Store = 1;
7000let Defs = [PC];
7001let BaseOpcode = "J4_cmpgtir";
7002let isTaken = Inst{13};
7003let isExtendable = 1;
7004let opExtendable = 2;
7005let isExtentSigned = 1;
7006let opExtentBits = 11;
7007let opExtentAlign = 2;
7008let opNewValue = 0;
7009}
7010def J4_cmpgti_fp0_jump_nt : HInst<
7011(outs),
7012(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7013"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7014tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7015let Inst{0-0} = 0b0;
7016let Inst{13-13} = 0b0;
7017let Inst{31-22} = 0b0001000011;
7018let isPredicated = 1;
7019let isPredicatedFalse = 1;
7020let isTerminator = 1;
7021let isBranch = 1;
7022let isPredicatedNew = 1;
7023let cofRelax1 = 1;
7024let cofRelax2 = 1;
7025let cofMax1 = 1;
7026let Uses = [P0];
7027let Defs = [P0, PC];
7028let BaseOpcode = "J4_cmpgtip0";
7029let isTaken = Inst{13};
7030let isExtendable = 1;
7031let opExtendable = 2;
7032let isExtentSigned = 1;
7033let opExtentBits = 11;
7034let opExtentAlign = 2;
7035}
7036def J4_cmpgti_fp0_jump_t : HInst<
7037(outs),
7038(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7039"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
7040tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7041let Inst{0-0} = 0b0;
7042let Inst{13-13} = 0b1;
7043let Inst{31-22} = 0b0001000011;
7044let isPredicated = 1;
7045let isPredicatedFalse = 1;
7046let isTerminator = 1;
7047let isBranch = 1;
7048let isPredicatedNew = 1;
7049let cofRelax1 = 1;
7050let cofRelax2 = 1;
7051let cofMax1 = 1;
7052let Uses = [P0];
7053let Defs = [P0, PC];
7054let BaseOpcode = "J4_cmpgtip0";
7055let isTaken = Inst{13};
7056let isExtendable = 1;
7057let opExtendable = 2;
7058let isExtentSigned = 1;
7059let opExtentBits = 11;
7060let opExtentAlign = 2;
7061}
7062def J4_cmpgti_fp1_jump_nt : HInst<
7063(outs),
7064(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7065"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7066tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7067let Inst{0-0} = 0b0;
7068let Inst{13-13} = 0b0;
7069let Inst{31-22} = 0b0001001011;
7070let isPredicated = 1;
7071let isPredicatedFalse = 1;
7072let isTerminator = 1;
7073let isBranch = 1;
7074let isPredicatedNew = 1;
7075let cofRelax1 = 1;
7076let cofRelax2 = 1;
7077let cofMax1 = 1;
7078let Uses = [P1];
7079let Defs = [P1, PC];
7080let BaseOpcode = "J4_cmpgtip1";
7081let isTaken = Inst{13};
7082let isExtendable = 1;
7083let opExtendable = 2;
7084let isExtentSigned = 1;
7085let opExtentBits = 11;
7086let opExtentAlign = 2;
7087}
7088def J4_cmpgti_fp1_jump_t : HInst<
7089(outs),
7090(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7091"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
7092tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7093let Inst{0-0} = 0b0;
7094let Inst{13-13} = 0b1;
7095let Inst{31-22} = 0b0001001011;
7096let isPredicated = 1;
7097let isPredicatedFalse = 1;
7098let isTerminator = 1;
7099let isBranch = 1;
7100let isPredicatedNew = 1;
7101let cofRelax1 = 1;
7102let cofRelax2 = 1;
7103let cofMax1 = 1;
7104let Uses = [P1];
7105let Defs = [P1, PC];
7106let BaseOpcode = "J4_cmpgtip1";
7107let isTaken = Inst{13};
7108let isExtendable = 1;
7109let opExtendable = 2;
7110let isExtentSigned = 1;
7111let opExtentBits = 11;
7112let opExtentAlign = 2;
7113}
7114def J4_cmpgti_t_jumpnv_nt : HInst<
7115(outs),
7116(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7117"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7118tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
7119let Inst{0-0} = 0b0;
7120let Inst{13-13} = 0b0;
7121let Inst{19-19} = 0b0;
7122let Inst{31-22} = 0b0010010010;
7123let isPredicated = 1;
7124let isTerminator = 1;
7125let isBranch = 1;
7126let isNewValue = 1;
7127let cofMax1 = 1;
7128let isRestrictNoSlot1Store = 1;
7129let Defs = [PC];
7130let BaseOpcode = "J4_cmpgtir";
7131let isTaken = Inst{13};
7132let isExtendable = 1;
7133let opExtendable = 2;
7134let isExtentSigned = 1;
7135let opExtentBits = 11;
7136let opExtentAlign = 2;
7137let opNewValue = 0;
7138}
7139def J4_cmpgti_t_jumpnv_t : HInst<
7140(outs),
7141(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7142"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7143tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
7144let Inst{0-0} = 0b0;
7145let Inst{13-13} = 0b1;
7146let Inst{19-19} = 0b0;
7147let Inst{31-22} = 0b0010010010;
7148let isPredicated = 1;
7149let isTerminator = 1;
7150let isBranch = 1;
7151let isNewValue = 1;
7152let cofMax1 = 1;
7153let isRestrictNoSlot1Store = 1;
7154let Defs = [PC];
7155let BaseOpcode = "J4_cmpgtir";
7156let isTaken = Inst{13};
7157let isExtendable = 1;
7158let opExtendable = 2;
7159let isExtentSigned = 1;
7160let opExtentBits = 11;
7161let opExtentAlign = 2;
7162let opNewValue = 0;
7163}
7164def J4_cmpgti_tp0_jump_nt : HInst<
7165(outs),
7166(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7167"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
7168tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7169let Inst{0-0} = 0b0;
7170let Inst{13-13} = 0b0;
7171let Inst{31-22} = 0b0001000010;
7172let isPredicated = 1;
7173let isTerminator = 1;
7174let isBranch = 1;
7175let isPredicatedNew = 1;
7176let cofRelax1 = 1;
7177let cofRelax2 = 1;
7178let cofMax1 = 1;
7179let Uses = [P0];
7180let Defs = [P0, PC];
7181let BaseOpcode = "J4_cmpgtip0";
7182let isTaken = Inst{13};
7183let isExtendable = 1;
7184let opExtendable = 2;
7185let isExtentSigned = 1;
7186let opExtentBits = 11;
7187let opExtentAlign = 2;
7188}
7189def J4_cmpgti_tp0_jump_t : HInst<
7190(outs),
7191(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7192"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
7193tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7194let Inst{0-0} = 0b0;
7195let Inst{13-13} = 0b1;
7196let Inst{31-22} = 0b0001000010;
7197let isPredicated = 1;
7198let isTerminator = 1;
7199let isBranch = 1;
7200let isPredicatedNew = 1;
7201let cofRelax1 = 1;
7202let cofRelax2 = 1;
7203let cofMax1 = 1;
7204let Uses = [P0];
7205let Defs = [P0, PC];
7206let BaseOpcode = "J4_cmpgtip0";
7207let isTaken = Inst{13};
7208let isExtendable = 1;
7209let opExtendable = 2;
7210let isExtentSigned = 1;
7211let opExtentBits = 11;
7212let opExtentAlign = 2;
7213}
7214def J4_cmpgti_tp1_jump_nt : HInst<
7215(outs),
7216(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7217"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
7218tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7219let Inst{0-0} = 0b0;
7220let Inst{13-13} = 0b0;
7221let Inst{31-22} = 0b0001001010;
7222let isPredicated = 1;
7223let isTerminator = 1;
7224let isBranch = 1;
7225let isPredicatedNew = 1;
7226let cofRelax1 = 1;
7227let cofRelax2 = 1;
7228let cofMax1 = 1;
7229let Uses = [P1];
7230let Defs = [P1, PC];
7231let BaseOpcode = "J4_cmpgtip1";
7232let isTaken = Inst{13};
7233let isExtendable = 1;
7234let opExtendable = 2;
7235let isExtentSigned = 1;
7236let opExtentBits = 11;
7237let opExtentAlign = 2;
7238}
7239def J4_cmpgti_tp1_jump_t : HInst<
7240(outs),
7241(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7242"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
7243tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7244let Inst{0-0} = 0b0;
7245let Inst{13-13} = 0b1;
7246let Inst{31-22} = 0b0001001010;
7247let isPredicated = 1;
7248let isTerminator = 1;
7249let isBranch = 1;
7250let isPredicatedNew = 1;
7251let cofRelax1 = 1;
7252let cofRelax2 = 1;
7253let cofMax1 = 1;
7254let Uses = [P1];
7255let Defs = [P1, PC];
7256let BaseOpcode = "J4_cmpgtip1";
7257let isTaken = Inst{13};
7258let isExtendable = 1;
7259let opExtendable = 2;
7260let isExtentSigned = 1;
7261let opExtentBits = 11;
7262let opExtentAlign = 2;
7263}
7264def J4_cmpgtn1_f_jumpnv_nt : HInst<
7265(outs),
7266(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7267"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7268tc_bd8382d1, TypeNCJ>, Enc_3694bd, PredRel {
7269let Inst{0-0} = 0b0;
7270let Inst{13-8} = 0b000000;
7271let Inst{19-19} = 0b0;
7272let Inst{31-22} = 0b0010011011;
7273let isPredicated = 1;
7274let isPredicatedFalse = 1;
7275let isTerminator = 1;
7276let isBranch = 1;
7277let isNewValue = 1;
7278let cofMax1 = 1;
7279let isRestrictNoSlot1Store = 1;
7280let Defs = [PC];
7281let BaseOpcode = "J4_cmpgtn1r";
7282let isTaken = Inst{13};
7283let isExtendable = 1;
7284let opExtendable = 2;
7285let isExtentSigned = 1;
7286let opExtentBits = 11;
7287let opExtentAlign = 2;
7288let opNewValue = 0;
7289}
7290def J4_cmpgtn1_f_jumpnv_t : HInst<
7291(outs),
7292(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7293"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7294tc_bd8382d1, TypeNCJ>, Enc_a6853f, PredRel {
7295let Inst{0-0} = 0b0;
7296let Inst{13-8} = 0b100000;
7297let Inst{19-19} = 0b0;
7298let Inst{31-22} = 0b0010011011;
7299let isPredicated = 1;
7300let isPredicatedFalse = 1;
7301let isTerminator = 1;
7302let isBranch = 1;
7303let isNewValue = 1;
7304let cofMax1 = 1;
7305let isRestrictNoSlot1Store = 1;
7306let Defs = [PC];
7307let BaseOpcode = "J4_cmpgtn1r";
7308let isTaken = Inst{13};
7309let isExtendable = 1;
7310let opExtendable = 2;
7311let isExtentSigned = 1;
7312let opExtentBits = 11;
7313let opExtentAlign = 2;
7314let opNewValue = 0;
7315}
7316def J4_cmpgtn1_fp0_jump_nt : HInst<
7317(outs),
7318(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7319"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
7320tc_3d495a39, TypeCJ>, Enc_a42857, PredRel {
7321let Inst{0-0} = 0b0;
7322let Inst{13-8} = 0b000001;
7323let Inst{31-22} = 0b0001000111;
7324let isPredicated = 1;
7325let isPredicatedFalse = 1;
7326let isTerminator = 1;
7327let isBranch = 1;
7328let isPredicatedNew = 1;
7329let cofRelax1 = 1;
7330let cofRelax2 = 1;
7331let cofMax1 = 1;
7332let Uses = [P0];
7333let Defs = [P0, PC];
7334let BaseOpcode = "J4_cmpgtn1p0";
7335let isTaken = Inst{13};
7336let isExtendable = 1;
7337let opExtendable = 2;
7338let isExtentSigned = 1;
7339let opExtentBits = 11;
7340let opExtentAlign = 2;
7341}
7342def J4_cmpgtn1_fp0_jump_t : HInst<
7343(outs),
7344(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7345"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
7346tc_3d495a39, TypeCJ>, Enc_f6fe0b, PredRel {
7347let Inst{0-0} = 0b0;
7348let Inst{13-8} = 0b100001;
7349let Inst{31-22} = 0b0001000111;
7350let isPredicated = 1;
7351let isPredicatedFalse = 1;
7352let isTerminator = 1;
7353let isBranch = 1;
7354let isPredicatedNew = 1;
7355let cofRelax1 = 1;
7356let cofRelax2 = 1;
7357let cofMax1 = 1;
7358let Uses = [P0];
7359let Defs = [P0, PC];
7360let BaseOpcode = "J4_cmpgtn1p0";
7361let isTaken = Inst{13};
7362let isExtendable = 1;
7363let opExtendable = 2;
7364let isExtentSigned = 1;
7365let opExtentBits = 11;
7366let opExtentAlign = 2;
7367}
7368def J4_cmpgtn1_fp1_jump_nt : HInst<
7369(outs),
7370(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7371"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
7372tc_3d495a39, TypeCJ>, Enc_3e3989, PredRel {
7373let Inst{0-0} = 0b0;
7374let Inst{13-8} = 0b000001;
7375let Inst{31-22} = 0b0001001111;
7376let isPredicated = 1;
7377let isPredicatedFalse = 1;
7378let isTerminator = 1;
7379let isBranch = 1;
7380let isPredicatedNew = 1;
7381let cofRelax1 = 1;
7382let cofRelax2 = 1;
7383let cofMax1 = 1;
7384let Uses = [P1];
7385let Defs = [P1, PC];
7386let BaseOpcode = "J4_cmpgtn1p1";
7387let isTaken = Inst{13};
7388let isExtendable = 1;
7389let opExtendable = 2;
7390let isExtentSigned = 1;
7391let opExtentBits = 11;
7392let opExtentAlign = 2;
7393}
7394def J4_cmpgtn1_fp1_jump_t : HInst<
7395(outs),
7396(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7397"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
7398tc_3d495a39, TypeCJ>, Enc_b909d2, PredRel {
7399let Inst{0-0} = 0b0;
7400let Inst{13-8} = 0b100001;
7401let Inst{31-22} = 0b0001001111;
7402let isPredicated = 1;
7403let isPredicatedFalse = 1;
7404let isTerminator = 1;
7405let isBranch = 1;
7406let isPredicatedNew = 1;
7407let cofRelax1 = 1;
7408let cofRelax2 = 1;
7409let cofMax1 = 1;
7410let Uses = [P1];
7411let Defs = [P1, PC];
7412let BaseOpcode = "J4_cmpgtn1p1";
7413let isTaken = Inst{13};
7414let isExtendable = 1;
7415let opExtendable = 2;
7416let isExtentSigned = 1;
7417let opExtentBits = 11;
7418let opExtentAlign = 2;
7419}
7420def J4_cmpgtn1_t_jumpnv_nt : HInst<
7421(outs),
7422(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7423"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7424tc_bd8382d1, TypeNCJ>, Enc_f82302, PredRel {
7425let Inst{0-0} = 0b0;
7426let Inst{13-8} = 0b000000;
7427let Inst{19-19} = 0b0;
7428let Inst{31-22} = 0b0010011010;
7429let isPredicated = 1;
7430let isTerminator = 1;
7431let isBranch = 1;
7432let isNewValue = 1;
7433let cofMax1 = 1;
7434let isRestrictNoSlot1Store = 1;
7435let Defs = [PC];
7436let BaseOpcode = "J4_cmpgtn1r";
7437let isTaken = Inst{13};
7438let isExtendable = 1;
7439let opExtendable = 2;
7440let isExtentSigned = 1;
7441let opExtentBits = 11;
7442let opExtentAlign = 2;
7443let opNewValue = 0;
7444}
7445def J4_cmpgtn1_t_jumpnv_t : HInst<
7446(outs),
7447(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7448"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7449tc_bd8382d1, TypeNCJ>, Enc_6413b6, PredRel {
7450let Inst{0-0} = 0b0;
7451let Inst{13-8} = 0b100000;
7452let Inst{19-19} = 0b0;
7453let Inst{31-22} = 0b0010011010;
7454let isPredicated = 1;
7455let isTerminator = 1;
7456let isBranch = 1;
7457let isNewValue = 1;
7458let cofMax1 = 1;
7459let isRestrictNoSlot1Store = 1;
7460let Defs = [PC];
7461let BaseOpcode = "J4_cmpgtn1r";
7462let isTaken = Inst{13};
7463let isExtendable = 1;
7464let opExtendable = 2;
7465let isExtentSigned = 1;
7466let opExtentBits = 11;
7467let opExtentAlign = 2;
7468let opNewValue = 0;
7469}
7470def J4_cmpgtn1_tp0_jump_nt : HInst<
7471(outs),
7472(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7473"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
7474tc_3d495a39, TypeCJ>, Enc_b78edd, PredRel {
7475let Inst{0-0} = 0b0;
7476let Inst{13-8} = 0b000001;
7477let Inst{31-22} = 0b0001000110;
7478let isPredicated = 1;
7479let isTerminator = 1;
7480let isBranch = 1;
7481let isPredicatedNew = 1;
7482let cofRelax1 = 1;
7483let cofRelax2 = 1;
7484let cofMax1 = 1;
7485let Uses = [P0];
7486let Defs = [P0, PC];
7487let BaseOpcode = "J4_cmpgtn1p0";
7488let isTaken = Inst{13};
7489let isExtendable = 1;
7490let opExtendable = 2;
7491let isExtentSigned = 1;
7492let opExtentBits = 11;
7493let opExtentAlign = 2;
7494}
7495def J4_cmpgtn1_tp0_jump_t : HInst<
7496(outs),
7497(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7498"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
7499tc_3d495a39, TypeCJ>, Enc_041d7b, PredRel {
7500let Inst{0-0} = 0b0;
7501let Inst{13-8} = 0b100001;
7502let Inst{31-22} = 0b0001000110;
7503let isPredicated = 1;
7504let isTerminator = 1;
7505let isBranch = 1;
7506let isPredicatedNew = 1;
7507let cofRelax1 = 1;
7508let cofRelax2 = 1;
7509let cofMax1 = 1;
7510let Uses = [P0];
7511let Defs = [P0, PC];
7512let BaseOpcode = "J4_cmpgtn1p0";
7513let isTaken = Inst{13};
7514let isExtendable = 1;
7515let opExtendable = 2;
7516let isExtentSigned = 1;
7517let opExtentBits = 11;
7518let opExtentAlign = 2;
7519}
7520def J4_cmpgtn1_tp1_jump_nt : HInst<
7521(outs),
7522(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7523"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
7524tc_3d495a39, TypeCJ>, Enc_b1e1fb, PredRel {
7525let Inst{0-0} = 0b0;
7526let Inst{13-8} = 0b000001;
7527let Inst{31-22} = 0b0001001110;
7528let isPredicated = 1;
7529let isTerminator = 1;
7530let isBranch = 1;
7531let isPredicatedNew = 1;
7532let cofRelax1 = 1;
7533let cofRelax2 = 1;
7534let cofMax1 = 1;
7535let Uses = [P1];
7536let Defs = [P1, PC];
7537let BaseOpcode = "J4_cmpgtn1p1";
7538let isTaken = Inst{13};
7539let isExtendable = 1;
7540let opExtendable = 2;
7541let isExtentSigned = 1;
7542let opExtentBits = 11;
7543let opExtentAlign = 2;
7544}
7545def J4_cmpgtn1_tp1_jump_t : HInst<
7546(outs),
7547(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7548"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
7549tc_3d495a39, TypeCJ>, Enc_178717, PredRel {
7550let Inst{0-0} = 0b0;
7551let Inst{13-8} = 0b100001;
7552let Inst{31-22} = 0b0001001110;
7553let isPredicated = 1;
7554let isTerminator = 1;
7555let isBranch = 1;
7556let isPredicatedNew = 1;
7557let cofRelax1 = 1;
7558let cofRelax2 = 1;
7559let cofMax1 = 1;
7560let Uses = [P1];
7561let Defs = [P1, PC];
7562let BaseOpcode = "J4_cmpgtn1p1";
7563let isTaken = Inst{13};
7564let isExtendable = 1;
7565let opExtendable = 2;
7566let isExtentSigned = 1;
7567let opExtentBits = 11;
7568let opExtentAlign = 2;
7569}
7570def J4_cmpgtu_f_jumpnv_nt : HInst<
7571(outs),
7572(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7573"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7574tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
7575let Inst{0-0} = 0b0;
7576let Inst{13-13} = 0b0;
7577let Inst{19-19} = 0b0;
7578let Inst{31-22} = 0b0010000101;
7579let isPredicated = 1;
7580let isPredicatedFalse = 1;
7581let isTerminator = 1;
7582let isBranch = 1;
7583let isNewValue = 1;
7584let cofMax1 = 1;
7585let isRestrictNoSlot1Store = 1;
7586let Defs = [PC];
7587let BaseOpcode = "J4_cmpgtur";
7588let isTaken = Inst{13};
7589let isExtendable = 1;
7590let opExtendable = 2;
7591let isExtentSigned = 1;
7592let opExtentBits = 11;
7593let opExtentAlign = 2;
7594let opNewValue = 0;
7595}
7596def J4_cmpgtu_f_jumpnv_t : HInst<
7597(outs),
7598(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7599"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7600tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
7601let Inst{0-0} = 0b0;
7602let Inst{13-13} = 0b1;
7603let Inst{19-19} = 0b0;
7604let Inst{31-22} = 0b0010000101;
7605let isPredicated = 1;
7606let isPredicatedFalse = 1;
7607let isTerminator = 1;
7608let isBranch = 1;
7609let isNewValue = 1;
7610let cofMax1 = 1;
7611let isRestrictNoSlot1Store = 1;
7612let Defs = [PC];
7613let BaseOpcode = "J4_cmpgtur";
7614let isTaken = Inst{13};
7615let isExtendable = 1;
7616let opExtendable = 2;
7617let isExtentSigned = 1;
7618let opExtentBits = 11;
7619let opExtentAlign = 2;
7620let opNewValue = 0;
7621}
7622def J4_cmpgtu_fp0_jump_nt : HInst<
7623(outs),
7624(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7625"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
7626tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7627let Inst{0-0} = 0b0;
7628let Inst{13-12} = 0b00;
7629let Inst{31-22} = 0b0001010101;
7630let isPredicated = 1;
7631let isPredicatedFalse = 1;
7632let isTerminator = 1;
7633let isBranch = 1;
7634let isPredicatedNew = 1;
7635let cofRelax1 = 1;
7636let cofRelax2 = 1;
7637let cofMax1 = 1;
7638let Uses = [P0];
7639let Defs = [P0, PC];
7640let BaseOpcode = "J4_cmpgtup0";
7641let isTaken = Inst{13};
7642let isExtendable = 1;
7643let opExtendable = 2;
7644let isExtentSigned = 1;
7645let opExtentBits = 11;
7646let opExtentAlign = 2;
7647}
7648def J4_cmpgtu_fp0_jump_t : HInst<
7649(outs),
7650(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7651"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
7652tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7653let Inst{0-0} = 0b0;
7654let Inst{13-12} = 0b10;
7655let Inst{31-22} = 0b0001010101;
7656let isPredicated = 1;
7657let isPredicatedFalse = 1;
7658let isTerminator = 1;
7659let isBranch = 1;
7660let isPredicatedNew = 1;
7661let cofRelax1 = 1;
7662let cofRelax2 = 1;
7663let cofMax1 = 1;
7664let Uses = [P0];
7665let Defs = [P0, PC];
7666let BaseOpcode = "J4_cmpgtup0";
7667let isTaken = Inst{13};
7668let isExtendable = 1;
7669let opExtendable = 2;
7670let isExtentSigned = 1;
7671let opExtentBits = 11;
7672let opExtentAlign = 2;
7673}
7674def J4_cmpgtu_fp1_jump_nt : HInst<
7675(outs),
7676(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7677"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
7678tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7679let Inst{0-0} = 0b0;
7680let Inst{13-12} = 0b01;
7681let Inst{31-22} = 0b0001010101;
7682let isPredicated = 1;
7683let isPredicatedFalse = 1;
7684let isTerminator = 1;
7685let isBranch = 1;
7686let isPredicatedNew = 1;
7687let cofRelax1 = 1;
7688let cofRelax2 = 1;
7689let cofMax1 = 1;
7690let Uses = [P1];
7691let Defs = [P1, PC];
7692let BaseOpcode = "J4_cmpgtup1";
7693let isTaken = Inst{13};
7694let isExtendable = 1;
7695let opExtendable = 2;
7696let isExtentSigned = 1;
7697let opExtentBits = 11;
7698let opExtentAlign = 2;
7699}
7700def J4_cmpgtu_fp1_jump_t : HInst<
7701(outs),
7702(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7703"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
7704tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7705let Inst{0-0} = 0b0;
7706let Inst{13-12} = 0b11;
7707let Inst{31-22} = 0b0001010101;
7708let isPredicated = 1;
7709let isPredicatedFalse = 1;
7710let isTerminator = 1;
7711let isBranch = 1;
7712let isPredicatedNew = 1;
7713let cofRelax1 = 1;
7714let cofRelax2 = 1;
7715let cofMax1 = 1;
7716let Uses = [P1];
7717let Defs = [P1, PC];
7718let BaseOpcode = "J4_cmpgtup1";
7719let isTaken = Inst{13};
7720let isExtendable = 1;
7721let opExtendable = 2;
7722let isExtentSigned = 1;
7723let opExtentBits = 11;
7724let opExtentAlign = 2;
7725}
7726def J4_cmpgtu_t_jumpnv_nt : HInst<
7727(outs),
7728(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7729"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7730tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
7731let Inst{0-0} = 0b0;
7732let Inst{13-13} = 0b0;
7733let Inst{19-19} = 0b0;
7734let Inst{31-22} = 0b0010000100;
7735let isPredicated = 1;
7736let isTerminator = 1;
7737let isBranch = 1;
7738let isNewValue = 1;
7739let cofMax1 = 1;
7740let isRestrictNoSlot1Store = 1;
7741let Defs = [PC];
7742let BaseOpcode = "J4_cmpgtur";
7743let isTaken = Inst{13};
7744let isExtendable = 1;
7745let opExtendable = 2;
7746let isExtentSigned = 1;
7747let opExtentBits = 11;
7748let opExtentAlign = 2;
7749let opNewValue = 0;
7750}
7751def J4_cmpgtu_t_jumpnv_t : HInst<
7752(outs),
7753(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7754"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7755tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel {
7756let Inst{0-0} = 0b0;
7757let Inst{13-13} = 0b1;
7758let Inst{19-19} = 0b0;
7759let Inst{31-22} = 0b0010000100;
7760let isPredicated = 1;
7761let isTerminator = 1;
7762let isBranch = 1;
7763let isNewValue = 1;
7764let cofMax1 = 1;
7765let isRestrictNoSlot1Store = 1;
7766let Defs = [PC];
7767let BaseOpcode = "J4_cmpgtur";
7768let isTaken = Inst{13};
7769let isExtendable = 1;
7770let opExtendable = 2;
7771let isExtentSigned = 1;
7772let opExtentBits = 11;
7773let opExtentAlign = 2;
7774let opNewValue = 0;
7775}
7776def J4_cmpgtu_tp0_jump_nt : HInst<
7777(outs),
7778(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7779"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7780tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7781let Inst{0-0} = 0b0;
7782let Inst{13-12} = 0b00;
7783let Inst{31-22} = 0b0001010100;
7784let isPredicated = 1;
7785let isTerminator = 1;
7786let isBranch = 1;
7787let isPredicatedNew = 1;
7788let cofRelax1 = 1;
7789let cofRelax2 = 1;
7790let cofMax1 = 1;
7791let Uses = [P0];
7792let Defs = [P0, PC];
7793let BaseOpcode = "J4_cmpgtup0";
7794let isTaken = Inst{13};
7795let isExtendable = 1;
7796let opExtendable = 2;
7797let isExtentSigned = 1;
7798let opExtentBits = 11;
7799let opExtentAlign = 2;
7800}
7801def J4_cmpgtu_tp0_jump_t : HInst<
7802(outs),
7803(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7804"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7805tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7806let Inst{0-0} = 0b0;
7807let Inst{13-12} = 0b10;
7808let Inst{31-22} = 0b0001010100;
7809let isPredicated = 1;
7810let isTerminator = 1;
7811let isBranch = 1;
7812let isPredicatedNew = 1;
7813let cofRelax1 = 1;
7814let cofRelax2 = 1;
7815let cofMax1 = 1;
7816let Uses = [P0];
7817let Defs = [P0, PC];
7818let BaseOpcode = "J4_cmpgtup0";
7819let isTaken = Inst{13};
7820let isExtendable = 1;
7821let opExtendable = 2;
7822let isExtentSigned = 1;
7823let opExtentBits = 11;
7824let opExtentAlign = 2;
7825}
7826def J4_cmpgtu_tp1_jump_nt : HInst<
7827(outs),
7828(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7829"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7830tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7831let Inst{0-0} = 0b0;
7832let Inst{13-12} = 0b01;
7833let Inst{31-22} = 0b0001010100;
7834let isPredicated = 1;
7835let isTerminator = 1;
7836let isBranch = 1;
7837let isPredicatedNew = 1;
7838let cofRelax1 = 1;
7839let cofRelax2 = 1;
7840let cofMax1 = 1;
7841let Uses = [P1];
7842let Defs = [P1, PC];
7843let BaseOpcode = "J4_cmpgtup1";
7844let isTaken = Inst{13};
7845let isExtendable = 1;
7846let opExtendable = 2;
7847let isExtentSigned = 1;
7848let opExtentBits = 11;
7849let opExtentAlign = 2;
7850}
7851def J4_cmpgtu_tp1_jump_t : HInst<
7852(outs),
7853(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7854"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7855tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel {
7856let Inst{0-0} = 0b0;
7857let Inst{13-12} = 0b11;
7858let Inst{31-22} = 0b0001010100;
7859let isPredicated = 1;
7860let isTerminator = 1;
7861let isBranch = 1;
7862let isPredicatedNew = 1;
7863let cofRelax1 = 1;
7864let cofRelax2 = 1;
7865let cofMax1 = 1;
7866let Uses = [P1];
7867let Defs = [P1, PC];
7868let BaseOpcode = "J4_cmpgtup1";
7869let isTaken = Inst{13};
7870let isExtendable = 1;
7871let opExtendable = 2;
7872let isExtentSigned = 1;
7873let opExtentBits = 11;
7874let opExtentAlign = 2;
7875}
7876def J4_cmpgtui_f_jumpnv_nt : HInst<
7877(outs),
7878(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7879"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
7880tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
7881let Inst{0-0} = 0b0;
7882let Inst{13-13} = 0b0;
7883let Inst{19-19} = 0b0;
7884let Inst{31-22} = 0b0010010101;
7885let isPredicated = 1;
7886let isPredicatedFalse = 1;
7887let isTerminator = 1;
7888let isBranch = 1;
7889let isNewValue = 1;
7890let cofMax1 = 1;
7891let isRestrictNoSlot1Store = 1;
7892let Defs = [PC];
7893let BaseOpcode = "J4_cmpgtuir";
7894let isTaken = Inst{13};
7895let isExtendable = 1;
7896let opExtendable = 2;
7897let isExtentSigned = 1;
7898let opExtentBits = 11;
7899let opExtentAlign = 2;
7900let opNewValue = 0;
7901}
7902def J4_cmpgtui_f_jumpnv_t : HInst<
7903(outs),
7904(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7905"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
7906tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
7907let Inst{0-0} = 0b0;
7908let Inst{13-13} = 0b1;
7909let Inst{19-19} = 0b0;
7910let Inst{31-22} = 0b0010010101;
7911let isPredicated = 1;
7912let isPredicatedFalse = 1;
7913let isTerminator = 1;
7914let isBranch = 1;
7915let isNewValue = 1;
7916let cofMax1 = 1;
7917let isRestrictNoSlot1Store = 1;
7918let Defs = [PC];
7919let BaseOpcode = "J4_cmpgtuir";
7920let isTaken = Inst{13};
7921let isExtendable = 1;
7922let opExtendable = 2;
7923let isExtentSigned = 1;
7924let opExtentBits = 11;
7925let opExtentAlign = 2;
7926let opNewValue = 0;
7927}
7928def J4_cmpgtui_fp0_jump_nt : HInst<
7929(outs),
7930(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7931"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7932tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7933let Inst{0-0} = 0b0;
7934let Inst{13-13} = 0b0;
7935let Inst{31-22} = 0b0001000101;
7936let isPredicated = 1;
7937let isPredicatedFalse = 1;
7938let isTerminator = 1;
7939let isBranch = 1;
7940let isPredicatedNew = 1;
7941let cofRelax1 = 1;
7942let cofRelax2 = 1;
7943let cofMax1 = 1;
7944let Uses = [P0];
7945let Defs = [P0, PC];
7946let BaseOpcode = "J4_cmpgtuip0";
7947let isTaken = Inst{13};
7948let isExtendable = 1;
7949let opExtendable = 2;
7950let isExtentSigned = 1;
7951let opExtentBits = 11;
7952let opExtentAlign = 2;
7953}
7954def J4_cmpgtui_fp0_jump_t : HInst<
7955(outs),
7956(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7957"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
7958tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7959let Inst{0-0} = 0b0;
7960let Inst{13-13} = 0b1;
7961let Inst{31-22} = 0b0001000101;
7962let isPredicated = 1;
7963let isPredicatedFalse = 1;
7964let isTerminator = 1;
7965let isBranch = 1;
7966let isPredicatedNew = 1;
7967let cofRelax1 = 1;
7968let cofRelax2 = 1;
7969let cofMax1 = 1;
7970let Uses = [P0];
7971let Defs = [P0, PC];
7972let BaseOpcode = "J4_cmpgtuip0";
7973let isTaken = Inst{13};
7974let isExtendable = 1;
7975let opExtendable = 2;
7976let isExtentSigned = 1;
7977let opExtentBits = 11;
7978let opExtentAlign = 2;
7979}
7980def J4_cmpgtui_fp1_jump_nt : HInst<
7981(outs),
7982(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7983"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7984tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
7985let Inst{0-0} = 0b0;
7986let Inst{13-13} = 0b0;
7987let Inst{31-22} = 0b0001001101;
7988let isPredicated = 1;
7989let isPredicatedFalse = 1;
7990let isTerminator = 1;
7991let isBranch = 1;
7992let isPredicatedNew = 1;
7993let cofRelax1 = 1;
7994let cofRelax2 = 1;
7995let cofMax1 = 1;
7996let Uses = [P1];
7997let Defs = [P1, PC];
7998let BaseOpcode = "J4_cmpgtuip1";
7999let isTaken = Inst{13};
8000let isExtendable = 1;
8001let opExtendable = 2;
8002let isExtentSigned = 1;
8003let opExtentBits = 11;
8004let opExtentAlign = 2;
8005}
8006def J4_cmpgtui_fp1_jump_t : HInst<
8007(outs),
8008(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8009"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
8010tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
8011let Inst{0-0} = 0b0;
8012let Inst{13-13} = 0b1;
8013let Inst{31-22} = 0b0001001101;
8014let isPredicated = 1;
8015let isPredicatedFalse = 1;
8016let isTerminator = 1;
8017let isBranch = 1;
8018let isPredicatedNew = 1;
8019let cofRelax1 = 1;
8020let cofRelax2 = 1;
8021let cofMax1 = 1;
8022let Uses = [P1];
8023let Defs = [P1, PC];
8024let BaseOpcode = "J4_cmpgtuip1";
8025let isTaken = Inst{13};
8026let isExtendable = 1;
8027let opExtendable = 2;
8028let isExtentSigned = 1;
8029let opExtentBits = 11;
8030let opExtentAlign = 2;
8031}
8032def J4_cmpgtui_t_jumpnv_nt : HInst<
8033(outs),
8034(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8035"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8036tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
8037let Inst{0-0} = 0b0;
8038let Inst{13-13} = 0b0;
8039let Inst{19-19} = 0b0;
8040let Inst{31-22} = 0b0010010100;
8041let isPredicated = 1;
8042let isTerminator = 1;
8043let isBranch = 1;
8044let isNewValue = 1;
8045let cofMax1 = 1;
8046let isRestrictNoSlot1Store = 1;
8047let Defs = [PC];
8048let BaseOpcode = "J4_cmpgtuir";
8049let isTaken = Inst{13};
8050let isExtendable = 1;
8051let opExtendable = 2;
8052let isExtentSigned = 1;
8053let opExtentBits = 11;
8054let opExtentAlign = 2;
8055let opNewValue = 0;
8056}
8057def J4_cmpgtui_t_jumpnv_t : HInst<
8058(outs),
8059(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8060"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8061tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel {
8062let Inst{0-0} = 0b0;
8063let Inst{13-13} = 0b1;
8064let Inst{19-19} = 0b0;
8065let Inst{31-22} = 0b0010010100;
8066let isPredicated = 1;
8067let isTerminator = 1;
8068let isBranch = 1;
8069let isNewValue = 1;
8070let cofMax1 = 1;
8071let isRestrictNoSlot1Store = 1;
8072let Defs = [PC];
8073let BaseOpcode = "J4_cmpgtuir";
8074let isTaken = Inst{13};
8075let isExtendable = 1;
8076let opExtendable = 2;
8077let isExtentSigned = 1;
8078let opExtentBits = 11;
8079let opExtentAlign = 2;
8080let opNewValue = 0;
8081}
8082def J4_cmpgtui_tp0_jump_nt : HInst<
8083(outs),
8084(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8085"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
8086tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
8087let Inst{0-0} = 0b0;
8088let Inst{13-13} = 0b0;
8089let Inst{31-22} = 0b0001000100;
8090let isPredicated = 1;
8091let isTerminator = 1;
8092let isBranch = 1;
8093let isPredicatedNew = 1;
8094let cofRelax1 = 1;
8095let cofRelax2 = 1;
8096let cofMax1 = 1;
8097let Uses = [P0];
8098let Defs = [P0, PC];
8099let BaseOpcode = "J4_cmpgtuip0";
8100let isTaken = Inst{13};
8101let isExtendable = 1;
8102let opExtendable = 2;
8103let isExtentSigned = 1;
8104let opExtentBits = 11;
8105let opExtentAlign = 2;
8106}
8107def J4_cmpgtui_tp0_jump_t : HInst<
8108(outs),
8109(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8110"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
8111tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
8112let Inst{0-0} = 0b0;
8113let Inst{13-13} = 0b1;
8114let Inst{31-22} = 0b0001000100;
8115let isPredicated = 1;
8116let isTerminator = 1;
8117let isBranch = 1;
8118let isPredicatedNew = 1;
8119let cofRelax1 = 1;
8120let cofRelax2 = 1;
8121let cofMax1 = 1;
8122let Uses = [P0];
8123let Defs = [P0, PC];
8124let BaseOpcode = "J4_cmpgtuip0";
8125let isTaken = Inst{13};
8126let isExtendable = 1;
8127let opExtendable = 2;
8128let isExtentSigned = 1;
8129let opExtentBits = 11;
8130let opExtentAlign = 2;
8131}
8132def J4_cmpgtui_tp1_jump_nt : HInst<
8133(outs),
8134(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8135"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
8136tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
8137let Inst{0-0} = 0b0;
8138let Inst{13-13} = 0b0;
8139let Inst{31-22} = 0b0001001100;
8140let isPredicated = 1;
8141let isTerminator = 1;
8142let isBranch = 1;
8143let isPredicatedNew = 1;
8144let cofRelax1 = 1;
8145let cofRelax2 = 1;
8146let cofMax1 = 1;
8147let Uses = [P1];
8148let Defs = [P1, PC];
8149let BaseOpcode = "J4_cmpgtuip1";
8150let isTaken = Inst{13};
8151let isExtendable = 1;
8152let opExtendable = 2;
8153let isExtentSigned = 1;
8154let opExtentBits = 11;
8155let opExtentAlign = 2;
8156}
8157def J4_cmpgtui_tp1_jump_t : HInst<
8158(outs),
8159(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8160"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
8161tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel {
8162let Inst{0-0} = 0b0;
8163let Inst{13-13} = 0b1;
8164let Inst{31-22} = 0b0001001100;
8165let isPredicated = 1;
8166let isTerminator = 1;
8167let isBranch = 1;
8168let isPredicatedNew = 1;
8169let cofRelax1 = 1;
8170let cofRelax2 = 1;
8171let cofMax1 = 1;
8172let Uses = [P1];
8173let Defs = [P1, PC];
8174let BaseOpcode = "J4_cmpgtuip1";
8175let isTaken = Inst{13};
8176let isExtendable = 1;
8177let opExtendable = 2;
8178let isExtentSigned = 1;
8179let opExtentBits = 11;
8180let opExtentAlign = 2;
8181}
8182def J4_cmplt_f_jumpnv_nt : HInst<
8183(outs),
8184(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8185"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8186tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8187let Inst{0-0} = 0b0;
8188let Inst{13-13} = 0b0;
8189let Inst{19-19} = 0b0;
8190let Inst{31-22} = 0b0010000111;
8191let isPredicated = 1;
8192let isPredicatedFalse = 1;
8193let isTerminator = 1;
8194let isBranch = 1;
8195let isNewValue = 1;
8196let cofMax1 = 1;
8197let isRestrictNoSlot1Store = 1;
8198let Defs = [PC];
8199let BaseOpcode = "J4_cmpltr";
8200let isTaken = Inst{13};
8201let isExtendable = 1;
8202let opExtendable = 2;
8203let isExtentSigned = 1;
8204let opExtentBits = 11;
8205let opExtentAlign = 2;
8206let opNewValue = 1;
8207}
8208def J4_cmplt_f_jumpnv_t : HInst<
8209(outs),
8210(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8211"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8212tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8213let Inst{0-0} = 0b0;
8214let Inst{13-13} = 0b1;
8215let Inst{19-19} = 0b0;
8216let Inst{31-22} = 0b0010000111;
8217let isPredicated = 1;
8218let isPredicatedFalse = 1;
8219let isTerminator = 1;
8220let isBranch = 1;
8221let isNewValue = 1;
8222let cofMax1 = 1;
8223let isRestrictNoSlot1Store = 1;
8224let Defs = [PC];
8225let BaseOpcode = "J4_cmpltr";
8226let isTaken = Inst{13};
8227let isExtendable = 1;
8228let opExtendable = 2;
8229let isExtentSigned = 1;
8230let opExtentBits = 11;
8231let opExtentAlign = 2;
8232let opNewValue = 1;
8233}
8234def J4_cmplt_t_jumpnv_nt : HInst<
8235(outs),
8236(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8237"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8238tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8239let Inst{0-0} = 0b0;
8240let Inst{13-13} = 0b0;
8241let Inst{19-19} = 0b0;
8242let Inst{31-22} = 0b0010000110;
8243let isPredicated = 1;
8244let isTerminator = 1;
8245let isBranch = 1;
8246let isNewValue = 1;
8247let cofMax1 = 1;
8248let isRestrictNoSlot1Store = 1;
8249let Defs = [PC];
8250let BaseOpcode = "J4_cmpltr";
8251let isTaken = Inst{13};
8252let isExtendable = 1;
8253let opExtendable = 2;
8254let isExtentSigned = 1;
8255let opExtentBits = 11;
8256let opExtentAlign = 2;
8257let opNewValue = 1;
8258}
8259def J4_cmplt_t_jumpnv_t : HInst<
8260(outs),
8261(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8262"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8263tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8264let Inst{0-0} = 0b0;
8265let Inst{13-13} = 0b1;
8266let Inst{19-19} = 0b0;
8267let Inst{31-22} = 0b0010000110;
8268let isPredicated = 1;
8269let isTerminator = 1;
8270let isBranch = 1;
8271let isNewValue = 1;
8272let cofMax1 = 1;
8273let isRestrictNoSlot1Store = 1;
8274let Defs = [PC];
8275let BaseOpcode = "J4_cmpltr";
8276let isTaken = Inst{13};
8277let isExtendable = 1;
8278let opExtendable = 2;
8279let isExtentSigned = 1;
8280let opExtentBits = 11;
8281let opExtentAlign = 2;
8282let opNewValue = 1;
8283}
8284def J4_cmpltu_f_jumpnv_nt : HInst<
8285(outs),
8286(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8287"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8288tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8289let Inst{0-0} = 0b0;
8290let Inst{13-13} = 0b0;
8291let Inst{19-19} = 0b0;
8292let Inst{31-22} = 0b0010001001;
8293let isPredicated = 1;
8294let isPredicatedFalse = 1;
8295let isTerminator = 1;
8296let isBranch = 1;
8297let isNewValue = 1;
8298let cofMax1 = 1;
8299let isRestrictNoSlot1Store = 1;
8300let Defs = [PC];
8301let BaseOpcode = "J4_cmpltur";
8302let isTaken = Inst{13};
8303let isExtendable = 1;
8304let opExtendable = 2;
8305let isExtentSigned = 1;
8306let opExtentBits = 11;
8307let opExtentAlign = 2;
8308let opNewValue = 1;
8309}
8310def J4_cmpltu_f_jumpnv_t : HInst<
8311(outs),
8312(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8313"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8314tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8315let Inst{0-0} = 0b0;
8316let Inst{13-13} = 0b1;
8317let Inst{19-19} = 0b0;
8318let Inst{31-22} = 0b0010001001;
8319let isPredicated = 1;
8320let isPredicatedFalse = 1;
8321let isTerminator = 1;
8322let isBranch = 1;
8323let isNewValue = 1;
8324let cofMax1 = 1;
8325let isRestrictNoSlot1Store = 1;
8326let Defs = [PC];
8327let BaseOpcode = "J4_cmpltur";
8328let isTaken = Inst{13};
8329let isExtendable = 1;
8330let opExtendable = 2;
8331let isExtentSigned = 1;
8332let opExtentBits = 11;
8333let opExtentAlign = 2;
8334let opNewValue = 1;
8335}
8336def J4_cmpltu_t_jumpnv_nt : HInst<
8337(outs),
8338(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8339"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8340tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8341let Inst{0-0} = 0b0;
8342let Inst{13-13} = 0b0;
8343let Inst{19-19} = 0b0;
8344let Inst{31-22} = 0b0010001000;
8345let isPredicated = 1;
8346let isTerminator = 1;
8347let isBranch = 1;
8348let isNewValue = 1;
8349let cofMax1 = 1;
8350let isRestrictNoSlot1Store = 1;
8351let Defs = [PC];
8352let BaseOpcode = "J4_cmpltur";
8353let isTaken = Inst{13};
8354let isExtendable = 1;
8355let opExtendable = 2;
8356let isExtentSigned = 1;
8357let opExtentBits = 11;
8358let opExtentAlign = 2;
8359let opNewValue = 1;
8360}
8361def J4_cmpltu_t_jumpnv_t : HInst<
8362(outs),
8363(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8364"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8365tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel {
8366let Inst{0-0} = 0b0;
8367let Inst{13-13} = 0b1;
8368let Inst{19-19} = 0b0;
8369let Inst{31-22} = 0b0010001000;
8370let isPredicated = 1;
8371let isTerminator = 1;
8372let isBranch = 1;
8373let isNewValue = 1;
8374let cofMax1 = 1;
8375let isRestrictNoSlot1Store = 1;
8376let Defs = [PC];
8377let BaseOpcode = "J4_cmpltur";
8378let isTaken = Inst{13};
8379let isExtendable = 1;
8380let opExtendable = 2;
8381let isExtentSigned = 1;
8382let opExtentBits = 11;
8383let opExtentAlign = 2;
8384let opNewValue = 1;
8385}
8386def J4_hintjumpr : HInst<
8387(outs),
8388(ins IntRegs:$Rs32),
8389"hintjr($Rs32)",
8390tc_d5b7b0c1, TypeJ>, Enc_ecbcc8 {
8391let Inst{13-0} = 0b00000000000000;
8392let Inst{31-21} = 0b01010010101;
8393let isTerminator = 1;
8394let isIndirectBranch = 1;
8395let isBranch = 1;
8396let cofMax1 = 1;
8397}
8398def J4_jumpseti : HInst<
8399(outs GeneralSubRegs:$Rd16),
8400(ins u6_0Imm:$II, b30_2Imm:$Ii),
8401"$Rd16 = #$II ; jump $Ii",
8402tc_0663f615, TypeCJ>, Enc_9e4c3f {
8403let Inst{0-0} = 0b0;
8404let Inst{31-22} = 0b0001011000;
8405let hasNewValue = 1;
8406let opNewValue = 0;
8407let isTerminator = 1;
8408let isBranch = 1;
8409let cofRelax2 = 1;
8410let cofMax1 = 1;
8411let Defs = [PC];
8412let isExtendable = 1;
8413let opExtendable = 2;
8414let isExtentSigned = 1;
8415let opExtentBits = 11;
8416let opExtentAlign = 2;
8417}
8418def J4_jumpsetr : HInst<
8419(outs GeneralSubRegs:$Rd16),
8420(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8421"$Rd16 = $Rs16 ; jump $Ii",
8422tc_0663f615, TypeCJ>, Enc_66bce1 {
8423let Inst{0-0} = 0b0;
8424let Inst{13-12} = 0b00;
8425let Inst{31-22} = 0b0001011100;
8426let hasNewValue = 1;
8427let opNewValue = 0;
8428let isTerminator = 1;
8429let isBranch = 1;
8430let cofRelax2 = 1;
8431let cofMax1 = 1;
8432let Defs = [PC];
8433let isExtendable = 1;
8434let opExtendable = 2;
8435let isExtentSigned = 1;
8436let opExtentBits = 11;
8437let opExtentAlign = 2;
8438}
8439def J4_tstbit0_f_jumpnv_nt : HInst<
8440(outs),
8441(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8442"if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
8443tc_8c945be0, TypeNCJ>, Enc_69d63b {
8444let Inst{0-0} = 0b0;
8445let Inst{13-8} = 0b000000;
8446let Inst{19-19} = 0b0;
8447let Inst{31-22} = 0b0010010111;
8448let isPredicated = 1;
8449let isPredicatedFalse = 1;
8450let isTerminator = 1;
8451let isBranch = 1;
8452let isNewValue = 1;
8453let cofMax1 = 1;
8454let isRestrictNoSlot1Store = 1;
8455let Defs = [PC];
8456let isTaken = Inst{13};
8457let isExtendable = 1;
8458let opExtendable = 1;
8459let isExtentSigned = 1;
8460let opExtentBits = 11;
8461let opExtentAlign = 2;
8462let opNewValue = 0;
8463}
8464def J4_tstbit0_f_jumpnv_t : HInst<
8465(outs),
8466(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8467"if (!tstbit($Ns8.new,#0)) jump:t $Ii",
8468tc_8c945be0, TypeNCJ>, Enc_69d63b {
8469let Inst{0-0} = 0b0;
8470let Inst{13-8} = 0b100000;
8471let Inst{19-19} = 0b0;
8472let Inst{31-22} = 0b0010010111;
8473let isPredicated = 1;
8474let isPredicatedFalse = 1;
8475let isTerminator = 1;
8476let isBranch = 1;
8477let isNewValue = 1;
8478let cofMax1 = 1;
8479let isRestrictNoSlot1Store = 1;
8480let Defs = [PC];
8481let isTaken = Inst{13};
8482let isExtendable = 1;
8483let opExtendable = 1;
8484let isExtentSigned = 1;
8485let opExtentBits = 11;
8486let opExtentAlign = 2;
8487let opNewValue = 0;
8488}
8489def J4_tstbit0_fp0_jump_nt : HInst<
8490(outs),
8491(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8492"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
8493tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8494let Inst{0-0} = 0b0;
8495let Inst{13-8} = 0b000011;
8496let Inst{31-22} = 0b0001000111;
8497let isPredicated = 1;
8498let isPredicatedFalse = 1;
8499let isTerminator = 1;
8500let isBranch = 1;
8501let isPredicatedNew = 1;
8502let cofRelax1 = 1;
8503let cofRelax2 = 1;
8504let cofMax1 = 1;
8505let Uses = [P0];
8506let Defs = [P0, PC];
8507let isTaken = Inst{13};
8508let isExtendable = 1;
8509let opExtendable = 1;
8510let isExtentSigned = 1;
8511let opExtentBits = 11;
8512let opExtentAlign = 2;
8513}
8514def J4_tstbit0_fp0_jump_t : HInst<
8515(outs),
8516(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8517"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
8518tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8519let Inst{0-0} = 0b0;
8520let Inst{13-8} = 0b100011;
8521let Inst{31-22} = 0b0001000111;
8522let isPredicated = 1;
8523let isPredicatedFalse = 1;
8524let isTerminator = 1;
8525let isBranch = 1;
8526let isPredicatedNew = 1;
8527let cofRelax1 = 1;
8528let cofRelax2 = 1;
8529let cofMax1 = 1;
8530let Uses = [P0];
8531let Defs = [P0, PC];
8532let isTaken = Inst{13};
8533let isExtendable = 1;
8534let opExtendable = 1;
8535let isExtentSigned = 1;
8536let opExtentBits = 11;
8537let opExtentAlign = 2;
8538}
8539def J4_tstbit0_fp1_jump_nt : HInst<
8540(outs),
8541(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8542"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
8543tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8544let Inst{0-0} = 0b0;
8545let Inst{13-8} = 0b000011;
8546let Inst{31-22} = 0b0001001111;
8547let isPredicated = 1;
8548let isPredicatedFalse = 1;
8549let isTerminator = 1;
8550let isBranch = 1;
8551let isPredicatedNew = 1;
8552let cofRelax1 = 1;
8553let cofRelax2 = 1;
8554let cofMax1 = 1;
8555let Uses = [P1];
8556let Defs = [P1, PC];
8557let isTaken = Inst{13};
8558let isExtendable = 1;
8559let opExtendable = 1;
8560let isExtentSigned = 1;
8561let opExtentBits = 11;
8562let opExtentAlign = 2;
8563}
8564def J4_tstbit0_fp1_jump_t : HInst<
8565(outs),
8566(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8567"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
8568tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8569let Inst{0-0} = 0b0;
8570let Inst{13-8} = 0b100011;
8571let Inst{31-22} = 0b0001001111;
8572let isPredicated = 1;
8573let isPredicatedFalse = 1;
8574let isTerminator = 1;
8575let isBranch = 1;
8576let isPredicatedNew = 1;
8577let cofRelax1 = 1;
8578let cofRelax2 = 1;
8579let cofMax1 = 1;
8580let Uses = [P1];
8581let Defs = [P1, PC];
8582let isTaken = Inst{13};
8583let isExtendable = 1;
8584let opExtendable = 1;
8585let isExtentSigned = 1;
8586let opExtentBits = 11;
8587let opExtentAlign = 2;
8588}
8589def J4_tstbit0_t_jumpnv_nt : HInst<
8590(outs),
8591(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8592"if (tstbit($Ns8.new,#0)) jump:nt $Ii",
8593tc_8c945be0, TypeNCJ>, Enc_69d63b {
8594let Inst{0-0} = 0b0;
8595let Inst{13-8} = 0b000000;
8596let Inst{19-19} = 0b0;
8597let Inst{31-22} = 0b0010010110;
8598let isPredicated = 1;
8599let isTerminator = 1;
8600let isBranch = 1;
8601let isNewValue = 1;
8602let cofMax1 = 1;
8603let isRestrictNoSlot1Store = 1;
8604let Defs = [PC];
8605let isTaken = Inst{13};
8606let isExtendable = 1;
8607let opExtendable = 1;
8608let isExtentSigned = 1;
8609let opExtentBits = 11;
8610let opExtentAlign = 2;
8611let opNewValue = 0;
8612}
8613def J4_tstbit0_t_jumpnv_t : HInst<
8614(outs),
8615(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8616"if (tstbit($Ns8.new,#0)) jump:t $Ii",
8617tc_8c945be0, TypeNCJ>, Enc_69d63b {
8618let Inst{0-0} = 0b0;
8619let Inst{13-8} = 0b100000;
8620let Inst{19-19} = 0b0;
8621let Inst{31-22} = 0b0010010110;
8622let isPredicated = 1;
8623let isTerminator = 1;
8624let isBranch = 1;
8625let isNewValue = 1;
8626let cofMax1 = 1;
8627let isRestrictNoSlot1Store = 1;
8628let Defs = [PC];
8629let isTaken = Inst{13};
8630let isExtendable = 1;
8631let opExtendable = 1;
8632let isExtentSigned = 1;
8633let opExtentBits = 11;
8634let opExtentAlign = 2;
8635let opNewValue = 0;
8636}
8637def J4_tstbit0_tp0_jump_nt : HInst<
8638(outs),
8639(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8640"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
8641tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8642let Inst{0-0} = 0b0;
8643let Inst{13-8} = 0b000011;
8644let Inst{31-22} = 0b0001000110;
8645let isPredicated = 1;
8646let isTerminator = 1;
8647let isBranch = 1;
8648let isPredicatedNew = 1;
8649let cofRelax1 = 1;
8650let cofRelax2 = 1;
8651let cofMax1 = 1;
8652let Uses = [P0];
8653let Defs = [P0, PC];
8654let isTaken = Inst{13};
8655let isExtendable = 1;
8656let opExtendable = 1;
8657let isExtentSigned = 1;
8658let opExtentBits = 11;
8659let opExtentAlign = 2;
8660}
8661def J4_tstbit0_tp0_jump_t : HInst<
8662(outs),
8663(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8664"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
8665tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8666let Inst{0-0} = 0b0;
8667let Inst{13-8} = 0b100011;
8668let Inst{31-22} = 0b0001000110;
8669let isPredicated = 1;
8670let isTerminator = 1;
8671let isBranch = 1;
8672let isPredicatedNew = 1;
8673let cofRelax1 = 1;
8674let cofRelax2 = 1;
8675let cofMax1 = 1;
8676let Uses = [P0];
8677let Defs = [P0, PC];
8678let isTaken = Inst{13};
8679let isExtendable = 1;
8680let opExtendable = 1;
8681let isExtentSigned = 1;
8682let opExtentBits = 11;
8683let opExtentAlign = 2;
8684}
8685def J4_tstbit0_tp1_jump_nt : HInst<
8686(outs),
8687(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8688"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
8689tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8690let Inst{0-0} = 0b0;
8691let Inst{13-8} = 0b000011;
8692let Inst{31-22} = 0b0001001110;
8693let isPredicated = 1;
8694let isTerminator = 1;
8695let isBranch = 1;
8696let isPredicatedNew = 1;
8697let cofRelax1 = 1;
8698let cofRelax2 = 1;
8699let cofMax1 = 1;
8700let Uses = [P1];
8701let Defs = [P1, PC];
8702let isTaken = Inst{13};
8703let isExtendable = 1;
8704let opExtendable = 1;
8705let isExtentSigned = 1;
8706let opExtentBits = 11;
8707let opExtentAlign = 2;
8708}
8709def J4_tstbit0_tp1_jump_t : HInst<
8710(outs),
8711(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8712"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
8713tc_2332b92e, TypeCJ>, Enc_ad1c74 {
8714let Inst{0-0} = 0b0;
8715let Inst{13-8} = 0b100011;
8716let Inst{31-22} = 0b0001001110;
8717let isPredicated = 1;
8718let isTerminator = 1;
8719let isBranch = 1;
8720let isPredicatedNew = 1;
8721let cofRelax1 = 1;
8722let cofRelax2 = 1;
8723let cofMax1 = 1;
8724let Uses = [P1];
8725let Defs = [P1, PC];
8726let isTaken = Inst{13};
8727let isExtendable = 1;
8728let opExtendable = 1;
8729let isExtentSigned = 1;
8730let opExtentBits = 11;
8731let opExtentAlign = 2;
8732}
8733def L2_deallocframe : HInst<
8734(outs DoubleRegs:$Rdd32),
8735(ins IntRegs:$Rs32),
8736"$Rdd32 = deallocframe($Rs32):raw",
8737tc_15aa71c5, TypeLD>, Enc_3a3d62 {
8738let Inst{13-5} = 0b000000000;
8739let Inst{31-21} = 0b10010000000;
8740let accessSize = DoubleWordAccess;
8741let mayLoad = 1;
8742let Uses = [FRAMEKEY];
8743let Defs = [R29];
8744}
8745def L2_loadalignb_io : HInst<
8746(outs DoubleRegs:$Ryy32),
8747(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
8748"$Ryy32 = memb_fifo($Rs32+#$Ii)",
8749tc_5ef37dc4, TypeLD>, Enc_a27588 {
8750let Inst{24-21} = 0b0100;
8751let Inst{31-27} = 0b10010;
8752let addrMode = BaseImmOffset;
8753let accessSize = ByteAccess;
8754let mayLoad = 1;
8755let isExtendable = 1;
8756let opExtendable = 3;
8757let isExtentSigned = 1;
8758let opExtentBits = 11;
8759let opExtentAlign = 0;
8760let Constraints = "$Ryy32 = $Ryy32in";
8761}
8762def L2_loadalignb_pbr : HInst<
8763(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8764(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8765"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
8766tc_3c76b0ff, TypeLD>, Enc_1f5d8f {
8767let Inst{12-5} = 0b00000000;
8768let Inst{31-21} = 0b10011110100;
8769let addrMode = PostInc;
8770let accessSize = ByteAccess;
8771let mayLoad = 1;
8772let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8773}
8774def L2_loadalignb_pci : HInst<
8775(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8776(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
8777"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
8778tc_785f65a7, TypeLD>, Enc_74aef2 {
8779let Inst{12-9} = 0b0000;
8780let Inst{31-21} = 0b10011000100;
8781let addrMode = PostInc;
8782let accessSize = ByteAccess;
8783let mayLoad = 1;
8784let Uses = [CS];
8785let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8786}
8787def L2_loadalignb_pcr : HInst<
8788(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8789(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8790"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
8791tc_3c76b0ff, TypeLD>, Enc_1f5d8f {
8792let Inst{12-5} = 0b00010000;
8793let Inst{31-21} = 0b10011000100;
8794let addrMode = PostInc;
8795let accessSize = ByteAccess;
8796let mayLoad = 1;
8797let Uses = [CS];
8798let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8799}
8800def L2_loadalignb_pi : HInst<
8801(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8802(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
8803"$Ryy32 = memb_fifo($Rx32++#$Ii)",
8804tc_3c76b0ff, TypeLD>, Enc_6b197f {
8805let Inst{13-9} = 0b00000;
8806let Inst{31-21} = 0b10011010100;
8807let addrMode = PostInc;
8808let accessSize = ByteAccess;
8809let mayLoad = 1;
8810let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8811}
8812def L2_loadalignb_pr : HInst<
8813(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8814(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8815"$Ryy32 = memb_fifo($Rx32++$Mu2)",
8816tc_3c76b0ff, TypeLD>, Enc_1f5d8f {
8817let Inst{12-5} = 0b00000000;
8818let Inst{31-21} = 0b10011100100;
8819let addrMode = PostInc;
8820let accessSize = ByteAccess;
8821let mayLoad = 1;
8822let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8823}
8824def L2_loadalignb_zomap : HInst<
8825(outs DoubleRegs:$Ryy32),
8826(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8827"$Ryy32 = memb_fifo($Rs32)",
8828tc_5ef37dc4, TypeMAPPING> {
8829let isPseudo = 1;
8830let isCodeGenOnly = 1;
8831let Constraints = "$Ryy32 = $Ryy32in";
8832}
8833def L2_loadalignh_io : HInst<
8834(outs DoubleRegs:$Ryy32),
8835(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
8836"$Ryy32 = memh_fifo($Rs32+#$Ii)",
8837tc_5ef37dc4, TypeLD>, Enc_5cd7e9 {
8838let Inst{24-21} = 0b0010;
8839let Inst{31-27} = 0b10010;
8840let addrMode = BaseImmOffset;
8841let accessSize = HalfWordAccess;
8842let mayLoad = 1;
8843let isExtendable = 1;
8844let opExtendable = 3;
8845let isExtentSigned = 1;
8846let opExtentBits = 12;
8847let opExtentAlign = 1;
8848let Constraints = "$Ryy32 = $Ryy32in";
8849}
8850def L2_loadalignh_pbr : HInst<
8851(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8852(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8853"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
8854tc_3c76b0ff, TypeLD>, Enc_1f5d8f {
8855let Inst{12-5} = 0b00000000;
8856let Inst{31-21} = 0b10011110010;
8857let addrMode = PostInc;
8858let accessSize = HalfWordAccess;
8859let mayLoad = 1;
8860let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8861}
8862def L2_loadalignh_pci : HInst<
8863(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8864(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
8865"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
8866tc_785f65a7, TypeLD>, Enc_9e2e1c {
8867let Inst{12-9} = 0b0000;
8868let Inst{31-21} = 0b10011000010;
8869let addrMode = PostInc;
8870let accessSize = HalfWordAccess;
8871let mayLoad = 1;
8872let Uses = [CS];
8873let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8874}
8875def L2_loadalignh_pcr : HInst<
8876(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8877(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8878"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
8879tc_3c76b0ff, TypeLD>, Enc_1f5d8f {
8880let Inst{12-5} = 0b00010000;
8881let Inst{31-21} = 0b10011000010;
8882let addrMode = PostInc;
8883let accessSize = HalfWordAccess;
8884let mayLoad = 1;
8885let Uses = [CS];
8886let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8887}
8888def L2_loadalignh_pi : HInst<
8889(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8890(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
8891"$Ryy32 = memh_fifo($Rx32++#$Ii)",
8892tc_3c76b0ff, TypeLD>, Enc_bd1cbc {
8893let Inst{13-9} = 0b00000;
8894let Inst{31-21} = 0b10011010010;
8895let addrMode = PostInc;
8896let accessSize = HalfWordAccess;
8897let mayLoad = 1;
8898let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8899}
8900def L2_loadalignh_pr : HInst<
8901(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8902(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8903"$Ryy32 = memh_fifo($Rx32++$Mu2)",
8904tc_3c76b0ff, TypeLD>, Enc_1f5d8f {
8905let Inst{12-5} = 0b00000000;
8906let Inst{31-21} = 0b10011100010;
8907let addrMode = PostInc;
8908let accessSize = HalfWordAccess;
8909let mayLoad = 1;
8910let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8911}
8912def L2_loadalignh_zomap : HInst<
8913(outs DoubleRegs:$Ryy32),
8914(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8915"$Ryy32 = memh_fifo($Rs32)",
8916tc_5ef37dc4, TypeMAPPING> {
8917let isPseudo = 1;
8918let isCodeGenOnly = 1;
8919let Constraints = "$Ryy32 = $Ryy32in";
8920}
8921def L2_loadbsw2_io : HInst<
8922(outs IntRegs:$Rd32),
8923(ins IntRegs:$Rs32, s31_1Imm:$Ii),
8924"$Rd32 = membh($Rs32+#$Ii)",
8925tc_17e0d2cd, TypeLD>, Enc_de0214 {
8926let Inst{24-21} = 0b0001;
8927let Inst{31-27} = 0b10010;
8928let hasNewValue = 1;
8929let opNewValue = 0;
8930let addrMode = BaseImmOffset;
8931let accessSize = HalfWordAccess;
8932let mayLoad = 1;
8933let isExtendable = 1;
8934let opExtendable = 2;
8935let isExtentSigned = 1;
8936let opExtentBits = 12;
8937let opExtentAlign = 1;
8938}
8939def L2_loadbsw2_pbr : HInst<
8940(outs IntRegs:$Rd32, IntRegs:$Rx32),
8941(ins IntRegs:$Rx32in, ModRegs:$Mu2),
8942"$Rd32 = membh($Rx32++$Mu2:brev)",
8943tc_44d3da28, TypeLD>, Enc_74d4e5 {
8944let Inst{12-5} = 0b00000000;
8945let Inst{31-21} = 0b10011110001;
8946let hasNewValue = 1;
8947let opNewValue = 0;
8948let addrMode = PostInc;
8949let accessSize = HalfWordAccess;
8950let mayLoad = 1;
8951let Constraints = "$Rx32 = $Rx32in";
8952}
8953def L2_loadbsw2_pci : HInst<
8954(outs IntRegs:$Rd32, IntRegs:$Rx32),
8955(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
8956"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
8957tc_e93a3d71, TypeLD>, Enc_e83554 {
8958let Inst{12-9} = 0b0000;
8959let Inst{31-21} = 0b10011000001;
8960let hasNewValue = 1;
8961let opNewValue = 0;
8962let addrMode = PostInc;
8963let accessSize = HalfWordAccess;
8964let mayLoad = 1;
8965let Uses = [CS];
8966let Constraints = "$Rx32 = $Rx32in";
8967}
8968def L2_loadbsw2_pcr : HInst<
8969(outs IntRegs:$Rd32, IntRegs:$Rx32),
8970(ins IntRegs:$Rx32in, ModRegs:$Mu2),
8971"$Rd32 = membh($Rx32++I:circ($Mu2))",
8972tc_44d3da28, TypeLD>, Enc_74d4e5 {
8973let Inst{12-5} = 0b00010000;
8974let Inst{31-21} = 0b10011000001;
8975let hasNewValue = 1;
8976let opNewValue = 0;
8977let addrMode = PostInc;
8978let accessSize = HalfWordAccess;
8979let mayLoad = 1;
8980let Uses = [CS];
8981let Constraints = "$Rx32 = $Rx32in";
8982}
8983def L2_loadbsw2_pi : HInst<
8984(outs IntRegs:$Rd32, IntRegs:$Rx32),
8985(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
8986"$Rd32 = membh($Rx32++#$Ii)",
8987tc_44d3da28, TypeLD>, Enc_152467 {
8988let Inst{13-9} = 0b00000;
8989let Inst{31-21} = 0b10011010001;
8990let hasNewValue = 1;
8991let opNewValue = 0;
8992let addrMode = PostInc;
8993let accessSize = HalfWordAccess;
8994let mayLoad = 1;
8995let Constraints = "$Rx32 = $Rx32in";
8996}
8997def L2_loadbsw2_pr : HInst<
8998(outs IntRegs:$Rd32, IntRegs:$Rx32),
8999(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9000"$Rd32 = membh($Rx32++$Mu2)",
9001tc_44d3da28, TypeLD>, Enc_74d4e5 {
9002let Inst{12-5} = 0b00000000;
9003let Inst{31-21} = 0b10011100001;
9004let hasNewValue = 1;
9005let opNewValue = 0;
9006let addrMode = PostInc;
9007let accessSize = HalfWordAccess;
9008let mayLoad = 1;
9009let Constraints = "$Rx32 = $Rx32in";
9010}
9011def L2_loadbsw2_zomap : HInst<
9012(outs IntRegs:$Rd32),
9013(ins IntRegs:$Rs32),
9014"$Rd32 = membh($Rs32)",
9015tc_17e0d2cd, TypeMAPPING> {
9016let hasNewValue = 1;
9017let opNewValue = 0;
9018let isPseudo = 1;
9019let isCodeGenOnly = 1;
9020}
9021def L2_loadbsw4_io : HInst<
9022(outs DoubleRegs:$Rdd32),
9023(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9024"$Rdd32 = membh($Rs32+#$Ii)",
9025tc_17e0d2cd, TypeLD>, Enc_2d7491 {
9026let Inst{24-21} = 0b0111;
9027let Inst{31-27} = 0b10010;
9028let addrMode = BaseImmOffset;
9029let accessSize = WordAccess;
9030let mayLoad = 1;
9031let isExtendable = 1;
9032let opExtendable = 2;
9033let isExtentSigned = 1;
9034let opExtentBits = 13;
9035let opExtentAlign = 2;
9036}
9037def L2_loadbsw4_pbr : HInst<
9038(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9039(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9040"$Rdd32 = membh($Rx32++$Mu2:brev)",
9041tc_44d3da28, TypeLD>, Enc_7eee72 {
9042let Inst{12-5} = 0b00000000;
9043let Inst{31-21} = 0b10011110111;
9044let addrMode = PostInc;
9045let accessSize = WordAccess;
9046let mayLoad = 1;
9047let Constraints = "$Rx32 = $Rx32in";
9048}
9049def L2_loadbsw4_pci : HInst<
9050(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9051(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9052"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
9053tc_e93a3d71, TypeLD>, Enc_70b24b {
9054let Inst{12-9} = 0b0000;
9055let Inst{31-21} = 0b10011000111;
9056let addrMode = PostInc;
9057let accessSize = WordAccess;
9058let mayLoad = 1;
9059let Uses = [CS];
9060let Constraints = "$Rx32 = $Rx32in";
9061}
9062def L2_loadbsw4_pcr : HInst<
9063(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9064(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9065"$Rdd32 = membh($Rx32++I:circ($Mu2))",
9066tc_44d3da28, TypeLD>, Enc_7eee72 {
9067let Inst{12-5} = 0b00010000;
9068let Inst{31-21} = 0b10011000111;
9069let addrMode = PostInc;
9070let accessSize = WordAccess;
9071let mayLoad = 1;
9072let Uses = [CS];
9073let Constraints = "$Rx32 = $Rx32in";
9074}
9075def L2_loadbsw4_pi : HInst<
9076(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9077(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9078"$Rdd32 = membh($Rx32++#$Ii)",
9079tc_44d3da28, TypeLD>, Enc_71f1b4 {
9080let Inst{13-9} = 0b00000;
9081let Inst{31-21} = 0b10011010111;
9082let addrMode = PostInc;
9083let accessSize = WordAccess;
9084let mayLoad = 1;
9085let Constraints = "$Rx32 = $Rx32in";
9086}
9087def L2_loadbsw4_pr : HInst<
9088(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9089(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9090"$Rdd32 = membh($Rx32++$Mu2)",
9091tc_44d3da28, TypeLD>, Enc_7eee72 {
9092let Inst{12-5} = 0b00000000;
9093let Inst{31-21} = 0b10011100111;
9094let addrMode = PostInc;
9095let accessSize = WordAccess;
9096let mayLoad = 1;
9097let Constraints = "$Rx32 = $Rx32in";
9098}
9099def L2_loadbsw4_zomap : HInst<
9100(outs DoubleRegs:$Rdd32),
9101(ins IntRegs:$Rs32),
9102"$Rdd32 = membh($Rs32)",
9103tc_17e0d2cd, TypeMAPPING> {
9104let isPseudo = 1;
9105let isCodeGenOnly = 1;
9106}
9107def L2_loadbzw2_io : HInst<
9108(outs IntRegs:$Rd32),
9109(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9110"$Rd32 = memubh($Rs32+#$Ii)",
9111tc_17e0d2cd, TypeLD>, Enc_de0214 {
9112let Inst{24-21} = 0b0011;
9113let Inst{31-27} = 0b10010;
9114let hasNewValue = 1;
9115let opNewValue = 0;
9116let addrMode = BaseImmOffset;
9117let accessSize = HalfWordAccess;
9118let mayLoad = 1;
9119let isExtendable = 1;
9120let opExtendable = 2;
9121let isExtentSigned = 1;
9122let opExtentBits = 12;
9123let opExtentAlign = 1;
9124}
9125def L2_loadbzw2_pbr : HInst<
9126(outs IntRegs:$Rd32, IntRegs:$Rx32),
9127(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9128"$Rd32 = memubh($Rx32++$Mu2:brev)",
9129tc_44d3da28, TypeLD>, Enc_74d4e5 {
9130let Inst{12-5} = 0b00000000;
9131let Inst{31-21} = 0b10011110011;
9132let hasNewValue = 1;
9133let opNewValue = 0;
9134let addrMode = PostInc;
9135let accessSize = HalfWordAccess;
9136let mayLoad = 1;
9137let Constraints = "$Rx32 = $Rx32in";
9138}
9139def L2_loadbzw2_pci : HInst<
9140(outs IntRegs:$Rd32, IntRegs:$Rx32),
9141(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9142"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9143tc_e93a3d71, TypeLD>, Enc_e83554 {
9144let Inst{12-9} = 0b0000;
9145let Inst{31-21} = 0b10011000011;
9146let hasNewValue = 1;
9147let opNewValue = 0;
9148let addrMode = PostInc;
9149let accessSize = HalfWordAccess;
9150let mayLoad = 1;
9151let Uses = [CS];
9152let Constraints = "$Rx32 = $Rx32in";
9153}
9154def L2_loadbzw2_pcr : HInst<
9155(outs IntRegs:$Rd32, IntRegs:$Rx32),
9156(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9157"$Rd32 = memubh($Rx32++I:circ($Mu2))",
9158tc_44d3da28, TypeLD>, Enc_74d4e5 {
9159let Inst{12-5} = 0b00010000;
9160let Inst{31-21} = 0b10011000011;
9161let hasNewValue = 1;
9162let opNewValue = 0;
9163let addrMode = PostInc;
9164let accessSize = HalfWordAccess;
9165let mayLoad = 1;
9166let Uses = [CS];
9167let Constraints = "$Rx32 = $Rx32in";
9168}
9169def L2_loadbzw2_pi : HInst<
9170(outs IntRegs:$Rd32, IntRegs:$Rx32),
9171(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9172"$Rd32 = memubh($Rx32++#$Ii)",
9173tc_44d3da28, TypeLD>, Enc_152467 {
9174let Inst{13-9} = 0b00000;
9175let Inst{31-21} = 0b10011010011;
9176let hasNewValue = 1;
9177let opNewValue = 0;
9178let addrMode = PostInc;
9179let accessSize = HalfWordAccess;
9180let mayLoad = 1;
9181let Constraints = "$Rx32 = $Rx32in";
9182}
9183def L2_loadbzw2_pr : HInst<
9184(outs IntRegs:$Rd32, IntRegs:$Rx32),
9185(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9186"$Rd32 = memubh($Rx32++$Mu2)",
9187tc_44d3da28, TypeLD>, Enc_74d4e5 {
9188let Inst{12-5} = 0b00000000;
9189let Inst{31-21} = 0b10011100011;
9190let hasNewValue = 1;
9191let opNewValue = 0;
9192let addrMode = PostInc;
9193let accessSize = HalfWordAccess;
9194let mayLoad = 1;
9195let Constraints = "$Rx32 = $Rx32in";
9196}
9197def L2_loadbzw2_zomap : HInst<
9198(outs IntRegs:$Rd32),
9199(ins IntRegs:$Rs32),
9200"$Rd32 = memubh($Rs32)",
9201tc_17e0d2cd, TypeMAPPING> {
9202let hasNewValue = 1;
9203let opNewValue = 0;
9204let isPseudo = 1;
9205let isCodeGenOnly = 1;
9206}
9207def L2_loadbzw4_io : HInst<
9208(outs DoubleRegs:$Rdd32),
9209(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9210"$Rdd32 = memubh($Rs32+#$Ii)",
9211tc_17e0d2cd, TypeLD>, Enc_2d7491 {
9212let Inst{24-21} = 0b0101;
9213let Inst{31-27} = 0b10010;
9214let addrMode = BaseImmOffset;
9215let accessSize = WordAccess;
9216let mayLoad = 1;
9217let isExtendable = 1;
9218let opExtendable = 2;
9219let isExtentSigned = 1;
9220let opExtentBits = 13;
9221let opExtentAlign = 2;
9222}
9223def L2_loadbzw4_pbr : HInst<
9224(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9225(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9226"$Rdd32 = memubh($Rx32++$Mu2:brev)",
9227tc_44d3da28, TypeLD>, Enc_7eee72 {
9228let Inst{12-5} = 0b00000000;
9229let Inst{31-21} = 0b10011110101;
9230let addrMode = PostInc;
9231let accessSize = WordAccess;
9232let mayLoad = 1;
9233let Constraints = "$Rx32 = $Rx32in";
9234}
9235def L2_loadbzw4_pci : HInst<
9236(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9237(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9238"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9239tc_e93a3d71, TypeLD>, Enc_70b24b {
9240let Inst{12-9} = 0b0000;
9241let Inst{31-21} = 0b10011000101;
9242let addrMode = PostInc;
9243let accessSize = WordAccess;
9244let mayLoad = 1;
9245let Uses = [CS];
9246let Constraints = "$Rx32 = $Rx32in";
9247}
9248def L2_loadbzw4_pcr : HInst<
9249(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9250(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9251"$Rdd32 = memubh($Rx32++I:circ($Mu2))",
9252tc_44d3da28, TypeLD>, Enc_7eee72 {
9253let Inst{12-5} = 0b00010000;
9254let Inst{31-21} = 0b10011000101;
9255let addrMode = PostInc;
9256let accessSize = WordAccess;
9257let mayLoad = 1;
9258let Uses = [CS];
9259let Constraints = "$Rx32 = $Rx32in";
9260}
9261def L2_loadbzw4_pi : HInst<
9262(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9263(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9264"$Rdd32 = memubh($Rx32++#$Ii)",
9265tc_44d3da28, TypeLD>, Enc_71f1b4 {
9266let Inst{13-9} = 0b00000;
9267let Inst{31-21} = 0b10011010101;
9268let addrMode = PostInc;
9269let accessSize = WordAccess;
9270let mayLoad = 1;
9271let Constraints = "$Rx32 = $Rx32in";
9272}
9273def L2_loadbzw4_pr : HInst<
9274(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9275(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9276"$Rdd32 = memubh($Rx32++$Mu2)",
9277tc_44d3da28, TypeLD>, Enc_7eee72 {
9278let Inst{12-5} = 0b00000000;
9279let Inst{31-21} = 0b10011100101;
9280let addrMode = PostInc;
9281let accessSize = WordAccess;
9282let mayLoad = 1;
9283let Constraints = "$Rx32 = $Rx32in";
9284}
9285def L2_loadbzw4_zomap : HInst<
9286(outs DoubleRegs:$Rdd32),
9287(ins IntRegs:$Rs32),
9288"$Rdd32 = memubh($Rs32)",
9289tc_17e0d2cd, TypeMAPPING> {
9290let isPseudo = 1;
9291let isCodeGenOnly = 1;
9292}
9293def L2_loadrb_io : HInst<
9294(outs IntRegs:$Rd32),
9295(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9296"$Rd32 = memb($Rs32+#$Ii)",
9297tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9298let Inst{24-21} = 0b1000;
9299let Inst{31-27} = 0b10010;
9300let hasNewValue = 1;
9301let opNewValue = 0;
9302let addrMode = BaseImmOffset;
9303let accessSize = ByteAccess;
9304let mayLoad = 1;
9305let CextOpcode = "L2_loadrb";
9306let BaseOpcode = "L2_loadrb_io";
9307let isPredicable = 1;
9308let isExtendable = 1;
9309let opExtendable = 2;
9310let isExtentSigned = 1;
9311let opExtentBits = 11;
9312let opExtentAlign = 0;
9313}
9314def L2_loadrb_pbr : HInst<
9315(outs IntRegs:$Rd32, IntRegs:$Rx32),
9316(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9317"$Rd32 = memb($Rx32++$Mu2:brev)",
9318tc_44d3da28, TypeLD>, Enc_74d4e5 {
9319let Inst{12-5} = 0b00000000;
9320let Inst{31-21} = 0b10011111000;
9321let hasNewValue = 1;
9322let opNewValue = 0;
9323let addrMode = PostInc;
9324let accessSize = ByteAccess;
9325let mayLoad = 1;
9326let Constraints = "$Rx32 = $Rx32in";
9327}
9328def L2_loadrb_pci : HInst<
9329(outs IntRegs:$Rd32, IntRegs:$Rx32),
9330(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9331"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
9332tc_e93a3d71, TypeLD>, Enc_e0a47a {
9333let Inst{12-9} = 0b0000;
9334let Inst{31-21} = 0b10011001000;
9335let hasNewValue = 1;
9336let opNewValue = 0;
9337let addrMode = PostInc;
9338let accessSize = ByteAccess;
9339let mayLoad = 1;
9340let Uses = [CS];
9341let Constraints = "$Rx32 = $Rx32in";
9342}
9343def L2_loadrb_pcr : HInst<
9344(outs IntRegs:$Rd32, IntRegs:$Rx32),
9345(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9346"$Rd32 = memb($Rx32++I:circ($Mu2))",
9347tc_44d3da28, TypeLD>, Enc_74d4e5 {
9348let Inst{12-5} = 0b00010000;
9349let Inst{31-21} = 0b10011001000;
9350let hasNewValue = 1;
9351let opNewValue = 0;
9352let addrMode = PostInc;
9353let accessSize = ByteAccess;
9354let mayLoad = 1;
9355let Uses = [CS];
9356let Constraints = "$Rx32 = $Rx32in";
9357}
9358def L2_loadrb_pi : HInst<
9359(outs IntRegs:$Rd32, IntRegs:$Rx32),
9360(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9361"$Rd32 = memb($Rx32++#$Ii)",
9362tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9363let Inst{13-9} = 0b00000;
9364let Inst{31-21} = 0b10011011000;
9365let hasNewValue = 1;
9366let opNewValue = 0;
9367let addrMode = PostInc;
9368let accessSize = ByteAccess;
9369let mayLoad = 1;
9370let CextOpcode = "L2_loadrb";
9371let BaseOpcode = "L2_loadrb_pi";
9372let isPredicable = 1;
9373let Constraints = "$Rx32 = $Rx32in";
9374}
9375def L2_loadrb_pr : HInst<
9376(outs IntRegs:$Rd32, IntRegs:$Rx32),
9377(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9378"$Rd32 = memb($Rx32++$Mu2)",
9379tc_44d3da28, TypeLD>, Enc_74d4e5 {
9380let Inst{12-5} = 0b00000000;
9381let Inst{31-21} = 0b10011101000;
9382let hasNewValue = 1;
9383let opNewValue = 0;
9384let addrMode = PostInc;
9385let accessSize = ByteAccess;
9386let mayLoad = 1;
9387let Constraints = "$Rx32 = $Rx32in";
9388}
9389def L2_loadrb_zomap : HInst<
9390(outs IntRegs:$Rd32),
9391(ins IntRegs:$Rs32),
9392"$Rd32 = memb($Rs32)",
9393tc_17e0d2cd, TypeMAPPING> {
9394let hasNewValue = 1;
9395let opNewValue = 0;
9396let isPseudo = 1;
9397let isCodeGenOnly = 1;
9398}
9399def L2_loadrbgp : HInst<
9400(outs IntRegs:$Rd32),
9401(ins u32_0Imm:$Ii),
9402"$Rd32 = memb(gp+#$Ii)",
9403tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9404let Inst{24-21} = 0b1000;
9405let Inst{31-27} = 0b01001;
9406let hasNewValue = 1;
9407let opNewValue = 0;
9408let accessSize = ByteAccess;
9409let mayLoad = 1;
9410let Uses = [GP];
9411let BaseOpcode = "L4_loadrb_abs";
9412let isPredicable = 1;
9413let opExtendable = 1;
9414let isExtentSigned = 0;
9415let opExtentBits = 16;
9416let opExtentAlign = 0;
9417}
9418def L2_loadrd_io : HInst<
9419(outs DoubleRegs:$Rdd32),
9420(ins IntRegs:$Rs32, s29_3Imm:$Ii),
9421"$Rdd32 = memd($Rs32+#$Ii)",
9422tc_17e0d2cd, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
9423let Inst{24-21} = 0b1110;
9424let Inst{31-27} = 0b10010;
9425let addrMode = BaseImmOffset;
9426let accessSize = DoubleWordAccess;
9427let mayLoad = 1;
9428let CextOpcode = "L2_loadrd";
9429let BaseOpcode = "L2_loadrd_io";
9430let isPredicable = 1;
9431let isExtendable = 1;
9432let opExtendable = 2;
9433let isExtentSigned = 1;
9434let opExtentBits = 14;
9435let opExtentAlign = 3;
9436}
9437def L2_loadrd_pbr : HInst<
9438(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9439(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9440"$Rdd32 = memd($Rx32++$Mu2:brev)",
9441tc_44d3da28, TypeLD>, Enc_7eee72 {
9442let Inst{12-5} = 0b00000000;
9443let Inst{31-21} = 0b10011111110;
9444let addrMode = PostInc;
9445let accessSize = DoubleWordAccess;
9446let mayLoad = 1;
9447let Constraints = "$Rx32 = $Rx32in";
9448}
9449def L2_loadrd_pci : HInst<
9450(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9451(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
9452"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
9453tc_e93a3d71, TypeLD>, Enc_b05839 {
9454let Inst{12-9} = 0b0000;
9455let Inst{31-21} = 0b10011001110;
9456let addrMode = PostInc;
9457let accessSize = DoubleWordAccess;
9458let mayLoad = 1;
9459let Uses = [CS];
9460let Constraints = "$Rx32 = $Rx32in";
9461}
9462def L2_loadrd_pcr : HInst<
9463(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9464(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9465"$Rdd32 = memd($Rx32++I:circ($Mu2))",
9466tc_44d3da28, TypeLD>, Enc_7eee72 {
9467let Inst{12-5} = 0b00010000;
9468let Inst{31-21} = 0b10011001110;
9469let addrMode = PostInc;
9470let accessSize = DoubleWordAccess;
9471let mayLoad = 1;
9472let Uses = [CS];
9473let Constraints = "$Rx32 = $Rx32in";
9474}
9475def L2_loadrd_pi : HInst<
9476(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9477(ins IntRegs:$Rx32in, s4_3Imm:$Ii),
9478"$Rdd32 = memd($Rx32++#$Ii)",
9479tc_44d3da28, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
9480let Inst{13-9} = 0b00000;
9481let Inst{31-21} = 0b10011011110;
9482let addrMode = PostInc;
9483let accessSize = DoubleWordAccess;
9484let mayLoad = 1;
9485let CextOpcode = "L2_loadrd";
9486let BaseOpcode = "L2_loadrd_pi";
9487let isPredicable = 1;
9488let Constraints = "$Rx32 = $Rx32in";
9489}
9490def L2_loadrd_pr : HInst<
9491(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9492(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9493"$Rdd32 = memd($Rx32++$Mu2)",
9494tc_44d3da28, TypeLD>, Enc_7eee72 {
9495let Inst{12-5} = 0b00000000;
9496let Inst{31-21} = 0b10011101110;
9497let addrMode = PostInc;
9498let accessSize = DoubleWordAccess;
9499let mayLoad = 1;
9500let Constraints = "$Rx32 = $Rx32in";
9501}
9502def L2_loadrd_zomap : HInst<
9503(outs DoubleRegs:$Rdd32),
9504(ins IntRegs:$Rs32),
9505"$Rdd32 = memd($Rs32)",
9506tc_17e0d2cd, TypeMAPPING> {
9507let isPseudo = 1;
9508let isCodeGenOnly = 1;
9509}
9510def L2_loadrdgp : HInst<
9511(outs DoubleRegs:$Rdd32),
9512(ins u29_3Imm:$Ii),
9513"$Rdd32 = memd(gp+#$Ii)",
9514tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel {
9515let Inst{24-21} = 0b1110;
9516let Inst{31-27} = 0b01001;
9517let accessSize = DoubleWordAccess;
9518let mayLoad = 1;
9519let Uses = [GP];
9520let BaseOpcode = "L4_loadrd_abs";
9521let isPredicable = 1;
9522let opExtendable = 1;
9523let isExtentSigned = 0;
9524let opExtentBits = 19;
9525let opExtentAlign = 3;
9526}
9527def L2_loadrh_io : HInst<
9528(outs IntRegs:$Rd32),
9529(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9530"$Rd32 = memh($Rs32+#$Ii)",
9531tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9532let Inst{24-21} = 0b1010;
9533let Inst{31-27} = 0b10010;
9534let hasNewValue = 1;
9535let opNewValue = 0;
9536let addrMode = BaseImmOffset;
9537let accessSize = HalfWordAccess;
9538let mayLoad = 1;
9539let CextOpcode = "L2_loadrh";
9540let BaseOpcode = "L2_loadrh_io";
9541let isPredicable = 1;
9542let isExtendable = 1;
9543let opExtendable = 2;
9544let isExtentSigned = 1;
9545let opExtentBits = 12;
9546let opExtentAlign = 1;
9547}
9548def L2_loadrh_pbr : HInst<
9549(outs IntRegs:$Rd32, IntRegs:$Rx32),
9550(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9551"$Rd32 = memh($Rx32++$Mu2:brev)",
9552tc_44d3da28, TypeLD>, Enc_74d4e5 {
9553let Inst{12-5} = 0b00000000;
9554let Inst{31-21} = 0b10011111010;
9555let hasNewValue = 1;
9556let opNewValue = 0;
9557let addrMode = PostInc;
9558let accessSize = HalfWordAccess;
9559let mayLoad = 1;
9560let Constraints = "$Rx32 = $Rx32in";
9561}
9562def L2_loadrh_pci : HInst<
9563(outs IntRegs:$Rd32, IntRegs:$Rx32),
9564(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9565"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
9566tc_e93a3d71, TypeLD>, Enc_e83554 {
9567let Inst{12-9} = 0b0000;
9568let Inst{31-21} = 0b10011001010;
9569let hasNewValue = 1;
9570let opNewValue = 0;
9571let addrMode = PostInc;
9572let accessSize = HalfWordAccess;
9573let mayLoad = 1;
9574let Uses = [CS];
9575let Constraints = "$Rx32 = $Rx32in";
9576}
9577def L2_loadrh_pcr : HInst<
9578(outs IntRegs:$Rd32, IntRegs:$Rx32),
9579(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9580"$Rd32 = memh($Rx32++I:circ($Mu2))",
9581tc_44d3da28, TypeLD>, Enc_74d4e5 {
9582let Inst{12-5} = 0b00010000;
9583let Inst{31-21} = 0b10011001010;
9584let hasNewValue = 1;
9585let opNewValue = 0;
9586let addrMode = PostInc;
9587let accessSize = HalfWordAccess;
9588let mayLoad = 1;
9589let Uses = [CS];
9590let Constraints = "$Rx32 = $Rx32in";
9591}
9592def L2_loadrh_pi : HInst<
9593(outs IntRegs:$Rd32, IntRegs:$Rx32),
9594(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9595"$Rd32 = memh($Rx32++#$Ii)",
9596tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9597let Inst{13-9} = 0b00000;
9598let Inst{31-21} = 0b10011011010;
9599let hasNewValue = 1;
9600let opNewValue = 0;
9601let addrMode = PostInc;
9602let accessSize = HalfWordAccess;
9603let mayLoad = 1;
9604let CextOpcode = "L2_loadrh";
9605let BaseOpcode = "L2_loadrh_pi";
9606let isPredicable = 1;
9607let Constraints = "$Rx32 = $Rx32in";
9608}
9609def L2_loadrh_pr : HInst<
9610(outs IntRegs:$Rd32, IntRegs:$Rx32),
9611(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9612"$Rd32 = memh($Rx32++$Mu2)",
9613tc_44d3da28, TypeLD>, Enc_74d4e5 {
9614let Inst{12-5} = 0b00000000;
9615let Inst{31-21} = 0b10011101010;
9616let hasNewValue = 1;
9617let opNewValue = 0;
9618let addrMode = PostInc;
9619let accessSize = HalfWordAccess;
9620let mayLoad = 1;
9621let Constraints = "$Rx32 = $Rx32in";
9622}
9623def L2_loadrh_zomap : HInst<
9624(outs IntRegs:$Rd32),
9625(ins IntRegs:$Rs32),
9626"$Rd32 = memh($Rs32)",
9627tc_17e0d2cd, TypeMAPPING> {
9628let hasNewValue = 1;
9629let opNewValue = 0;
9630let isPseudo = 1;
9631let isCodeGenOnly = 1;
9632}
9633def L2_loadrhgp : HInst<
9634(outs IntRegs:$Rd32),
9635(ins u31_1Imm:$Ii),
9636"$Rd32 = memh(gp+#$Ii)",
9637tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9638let Inst{24-21} = 0b1010;
9639let Inst{31-27} = 0b01001;
9640let hasNewValue = 1;
9641let opNewValue = 0;
9642let accessSize = HalfWordAccess;
9643let mayLoad = 1;
9644let Uses = [GP];
9645let BaseOpcode = "L4_loadrh_abs";
9646let isPredicable = 1;
9647let opExtendable = 1;
9648let isExtentSigned = 0;
9649let opExtentBits = 17;
9650let opExtentAlign = 1;
9651}
9652def L2_loadri_io : HInst<
9653(outs IntRegs:$Rd32),
9654(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9655"$Rd32 = memw($Rs32+#$Ii)",
9656tc_17e0d2cd, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
9657let Inst{24-21} = 0b1100;
9658let Inst{31-27} = 0b10010;
9659let hasNewValue = 1;
9660let opNewValue = 0;
9661let addrMode = BaseImmOffset;
9662let accessSize = WordAccess;
9663let mayLoad = 1;
9664let CextOpcode = "L2_loadri";
9665let BaseOpcode = "L2_loadri_io";
9666let isPredicable = 1;
9667let isExtendable = 1;
9668let opExtendable = 2;
9669let isExtentSigned = 1;
9670let opExtentBits = 13;
9671let opExtentAlign = 2;
9672}
9673def L2_loadri_pbr : HInst<
9674(outs IntRegs:$Rd32, IntRegs:$Rx32),
9675(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9676"$Rd32 = memw($Rx32++$Mu2:brev)",
9677tc_44d3da28, TypeLD>, Enc_74d4e5 {
9678let Inst{12-5} = 0b00000000;
9679let Inst{31-21} = 0b10011111100;
9680let hasNewValue = 1;
9681let opNewValue = 0;
9682let addrMode = PostInc;
9683let accessSize = WordAccess;
9684let mayLoad = 1;
9685let Constraints = "$Rx32 = $Rx32in";
9686}
9687def L2_loadri_pci : HInst<
9688(outs IntRegs:$Rd32, IntRegs:$Rx32),
9689(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9690"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
9691tc_e93a3d71, TypeLD>, Enc_27fd0e {
9692let Inst{12-9} = 0b0000;
9693let Inst{31-21} = 0b10011001100;
9694let hasNewValue = 1;
9695let opNewValue = 0;
9696let addrMode = PostInc;
9697let accessSize = WordAccess;
9698let mayLoad = 1;
9699let Uses = [CS];
9700let Constraints = "$Rx32 = $Rx32in";
9701}
9702def L2_loadri_pcr : HInst<
9703(outs IntRegs:$Rd32, IntRegs:$Rx32),
9704(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9705"$Rd32 = memw($Rx32++I:circ($Mu2))",
9706tc_44d3da28, TypeLD>, Enc_74d4e5 {
9707let Inst{12-5} = 0b00010000;
9708let Inst{31-21} = 0b10011001100;
9709let hasNewValue = 1;
9710let opNewValue = 0;
9711let addrMode = PostInc;
9712let accessSize = WordAccess;
9713let mayLoad = 1;
9714let Uses = [CS];
9715let Constraints = "$Rx32 = $Rx32in";
9716}
9717def L2_loadri_pi : HInst<
9718(outs IntRegs:$Rd32, IntRegs:$Rx32),
9719(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9720"$Rd32 = memw($Rx32++#$Ii)",
9721tc_44d3da28, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
9722let Inst{13-9} = 0b00000;
9723let Inst{31-21} = 0b10011011100;
9724let hasNewValue = 1;
9725let opNewValue = 0;
9726let addrMode = PostInc;
9727let accessSize = WordAccess;
9728let mayLoad = 1;
9729let CextOpcode = "L2_loadri";
9730let BaseOpcode = "L2_loadri_pi";
9731let isPredicable = 1;
9732let Constraints = "$Rx32 = $Rx32in";
9733}
9734def L2_loadri_pr : HInst<
9735(outs IntRegs:$Rd32, IntRegs:$Rx32),
9736(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9737"$Rd32 = memw($Rx32++$Mu2)",
9738tc_44d3da28, TypeLD>, Enc_74d4e5 {
9739let Inst{12-5} = 0b00000000;
9740let Inst{31-21} = 0b10011101100;
9741let hasNewValue = 1;
9742let opNewValue = 0;
9743let addrMode = PostInc;
9744let accessSize = WordAccess;
9745let mayLoad = 1;
9746let Constraints = "$Rx32 = $Rx32in";
9747}
9748def L2_loadri_zomap : HInst<
9749(outs IntRegs:$Rd32),
9750(ins IntRegs:$Rs32),
9751"$Rd32 = memw($Rs32)",
9752tc_17e0d2cd, TypeMAPPING> {
9753let hasNewValue = 1;
9754let opNewValue = 0;
9755let isPseudo = 1;
9756let isCodeGenOnly = 1;
9757}
9758def L2_loadrigp : HInst<
9759(outs IntRegs:$Rd32),
9760(ins u30_2Imm:$Ii),
9761"$Rd32 = memw(gp+#$Ii)",
9762tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
9763let Inst{24-21} = 0b1100;
9764let Inst{31-27} = 0b01001;
9765let hasNewValue = 1;
9766let opNewValue = 0;
9767let accessSize = WordAccess;
9768let mayLoad = 1;
9769let Uses = [GP];
9770let BaseOpcode = "L4_loadri_abs";
9771let isPredicable = 1;
9772let opExtendable = 1;
9773let isExtentSigned = 0;
9774let opExtentBits = 18;
9775let opExtentAlign = 2;
9776}
9777def L2_loadrub_io : HInst<
9778(outs IntRegs:$Rd32),
9779(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9780"$Rd32 = memub($Rs32+#$Ii)",
9781tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9782let Inst{24-21} = 0b1001;
9783let Inst{31-27} = 0b10010;
9784let hasNewValue = 1;
9785let opNewValue = 0;
9786let addrMode = BaseImmOffset;
9787let accessSize = ByteAccess;
9788let mayLoad = 1;
9789let CextOpcode = "L2_loadrub";
9790let BaseOpcode = "L2_loadrub_io";
9791let isPredicable = 1;
9792let isExtendable = 1;
9793let opExtendable = 2;
9794let isExtentSigned = 1;
9795let opExtentBits = 11;
9796let opExtentAlign = 0;
9797}
9798def L2_loadrub_pbr : HInst<
9799(outs IntRegs:$Rd32, IntRegs:$Rx32),
9800(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9801"$Rd32 = memub($Rx32++$Mu2:brev)",
9802tc_44d3da28, TypeLD>, Enc_74d4e5 {
9803let Inst{12-5} = 0b00000000;
9804let Inst{31-21} = 0b10011111001;
9805let hasNewValue = 1;
9806let opNewValue = 0;
9807let addrMode = PostInc;
9808let accessSize = ByteAccess;
9809let mayLoad = 1;
9810let Constraints = "$Rx32 = $Rx32in";
9811}
9812def L2_loadrub_pci : HInst<
9813(outs IntRegs:$Rd32, IntRegs:$Rx32),
9814(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9815"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
9816tc_e93a3d71, TypeLD>, Enc_e0a47a {
9817let Inst{12-9} = 0b0000;
9818let Inst{31-21} = 0b10011001001;
9819let hasNewValue = 1;
9820let opNewValue = 0;
9821let addrMode = PostInc;
9822let accessSize = ByteAccess;
9823let mayLoad = 1;
9824let Uses = [CS];
9825let Constraints = "$Rx32 = $Rx32in";
9826}
9827def L2_loadrub_pcr : HInst<
9828(outs IntRegs:$Rd32, IntRegs:$Rx32),
9829(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9830"$Rd32 = memub($Rx32++I:circ($Mu2))",
9831tc_44d3da28, TypeLD>, Enc_74d4e5 {
9832let Inst{12-5} = 0b00010000;
9833let Inst{31-21} = 0b10011001001;
9834let hasNewValue = 1;
9835let opNewValue = 0;
9836let addrMode = PostInc;
9837let accessSize = ByteAccess;
9838let mayLoad = 1;
9839let Uses = [CS];
9840let Constraints = "$Rx32 = $Rx32in";
9841}
9842def L2_loadrub_pi : HInst<
9843(outs IntRegs:$Rd32, IntRegs:$Rx32),
9844(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9845"$Rd32 = memub($Rx32++#$Ii)",
9846tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9847let Inst{13-9} = 0b00000;
9848let Inst{31-21} = 0b10011011001;
9849let hasNewValue = 1;
9850let opNewValue = 0;
9851let addrMode = PostInc;
9852let accessSize = ByteAccess;
9853let mayLoad = 1;
9854let CextOpcode = "L2_loadrub";
9855let BaseOpcode = "L2_loadrub_pi";
9856let isPredicable = 1;
9857let Constraints = "$Rx32 = $Rx32in";
9858}
9859def L2_loadrub_pr : HInst<
9860(outs IntRegs:$Rd32, IntRegs:$Rx32),
9861(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9862"$Rd32 = memub($Rx32++$Mu2)",
9863tc_44d3da28, TypeLD>, Enc_74d4e5 {
9864let Inst{12-5} = 0b00000000;
9865let Inst{31-21} = 0b10011101001;
9866let hasNewValue = 1;
9867let opNewValue = 0;
9868let addrMode = PostInc;
9869let accessSize = ByteAccess;
9870let mayLoad = 1;
9871let Constraints = "$Rx32 = $Rx32in";
9872}
9873def L2_loadrub_zomap : HInst<
9874(outs IntRegs:$Rd32),
9875(ins IntRegs:$Rs32),
9876"$Rd32 = memub($Rs32)",
9877tc_17e0d2cd, TypeMAPPING> {
9878let hasNewValue = 1;
9879let opNewValue = 0;
9880let isPseudo = 1;
9881let isCodeGenOnly = 1;
9882}
9883def L2_loadrubgp : HInst<
9884(outs IntRegs:$Rd32),
9885(ins u32_0Imm:$Ii),
9886"$Rd32 = memub(gp+#$Ii)",
9887tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9888let Inst{24-21} = 0b1001;
9889let Inst{31-27} = 0b01001;
9890let hasNewValue = 1;
9891let opNewValue = 0;
9892let accessSize = ByteAccess;
9893let mayLoad = 1;
9894let Uses = [GP];
9895let BaseOpcode = "L4_loadrub_abs";
9896let isPredicable = 1;
9897let opExtendable = 1;
9898let isExtentSigned = 0;
9899let opExtentBits = 16;
9900let opExtentAlign = 0;
9901}
9902def L2_loadruh_io : HInst<
9903(outs IntRegs:$Rd32),
9904(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9905"$Rd32 = memuh($Rs32+#$Ii)",
9906tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9907let Inst{24-21} = 0b1011;
9908let Inst{31-27} = 0b10010;
9909let hasNewValue = 1;
9910let opNewValue = 0;
9911let addrMode = BaseImmOffset;
9912let accessSize = HalfWordAccess;
9913let mayLoad = 1;
9914let CextOpcode = "L2_loadruh";
9915let BaseOpcode = "L2_loadruh_io";
9916let isPredicable = 1;
9917let isExtendable = 1;
9918let opExtendable = 2;
9919let isExtentSigned = 1;
9920let opExtentBits = 12;
9921let opExtentAlign = 1;
9922}
9923def L2_loadruh_pbr : HInst<
9924(outs IntRegs:$Rd32, IntRegs:$Rx32),
9925(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9926"$Rd32 = memuh($Rx32++$Mu2:brev)",
9927tc_44d3da28, TypeLD>, Enc_74d4e5 {
9928let Inst{12-5} = 0b00000000;
9929let Inst{31-21} = 0b10011111011;
9930let hasNewValue = 1;
9931let opNewValue = 0;
9932let addrMode = PostInc;
9933let accessSize = HalfWordAccess;
9934let mayLoad = 1;
9935let Constraints = "$Rx32 = $Rx32in";
9936}
9937def L2_loadruh_pci : HInst<
9938(outs IntRegs:$Rd32, IntRegs:$Rx32),
9939(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9940"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
9941tc_e93a3d71, TypeLD>, Enc_e83554 {
9942let Inst{12-9} = 0b0000;
9943let Inst{31-21} = 0b10011001011;
9944let hasNewValue = 1;
9945let opNewValue = 0;
9946let addrMode = PostInc;
9947let accessSize = HalfWordAccess;
9948let mayLoad = 1;
9949let Uses = [CS];
9950let Constraints = "$Rx32 = $Rx32in";
9951}
9952def L2_loadruh_pcr : HInst<
9953(outs IntRegs:$Rd32, IntRegs:$Rx32),
9954(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9955"$Rd32 = memuh($Rx32++I:circ($Mu2))",
9956tc_44d3da28, TypeLD>, Enc_74d4e5 {
9957let Inst{12-5} = 0b00010000;
9958let Inst{31-21} = 0b10011001011;
9959let hasNewValue = 1;
9960let opNewValue = 0;
9961let addrMode = PostInc;
9962let accessSize = HalfWordAccess;
9963let mayLoad = 1;
9964let Uses = [CS];
9965let Constraints = "$Rx32 = $Rx32in";
9966}
9967def L2_loadruh_pi : HInst<
9968(outs IntRegs:$Rd32, IntRegs:$Rx32),
9969(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9970"$Rd32 = memuh($Rx32++#$Ii)",
9971tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9972let Inst{13-9} = 0b00000;
9973let Inst{31-21} = 0b10011011011;
9974let hasNewValue = 1;
9975let opNewValue = 0;
9976let addrMode = PostInc;
9977let accessSize = HalfWordAccess;
9978let mayLoad = 1;
9979let CextOpcode = "L2_loadruh";
9980let BaseOpcode = "L2_loadruh_pi";
9981let isPredicable = 1;
9982let Constraints = "$Rx32 = $Rx32in";
9983}
9984def L2_loadruh_pr : HInst<
9985(outs IntRegs:$Rd32, IntRegs:$Rx32),
9986(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9987"$Rd32 = memuh($Rx32++$Mu2)",
9988tc_44d3da28, TypeLD>, Enc_74d4e5 {
9989let Inst{12-5} = 0b00000000;
9990let Inst{31-21} = 0b10011101011;
9991let hasNewValue = 1;
9992let opNewValue = 0;
9993let addrMode = PostInc;
9994let accessSize = HalfWordAccess;
9995let mayLoad = 1;
9996let Constraints = "$Rx32 = $Rx32in";
9997}
9998def L2_loadruh_zomap : HInst<
9999(outs IntRegs:$Rd32),
10000(ins IntRegs:$Rs32),
10001"$Rd32 = memuh($Rs32)",
10002tc_17e0d2cd, TypeMAPPING> {
10003let hasNewValue = 1;
10004let opNewValue = 0;
10005let isPseudo = 1;
10006let isCodeGenOnly = 1;
10007}
10008def L2_loadruhgp : HInst<
10009(outs IntRegs:$Rd32),
10010(ins u31_1Imm:$Ii),
10011"$Rd32 = memuh(gp+#$Ii)",
10012tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel {
10013let Inst{24-21} = 0b1011;
10014let Inst{31-27} = 0b01001;
10015let hasNewValue = 1;
10016let opNewValue = 0;
10017let accessSize = HalfWordAccess;
10018let mayLoad = 1;
10019let Uses = [GP];
10020let BaseOpcode = "L4_loadruh_abs";
10021let isPredicable = 1;
10022let opExtendable = 1;
10023let isExtentSigned = 0;
10024let opExtentBits = 17;
10025let opExtentAlign = 1;
10026}
10027def L2_loadw_locked : HInst<
10028(outs IntRegs:$Rd32),
10029(ins IntRegs:$Rs32),
10030"$Rd32 = memw_locked($Rs32)",
10031tc_b43e7930, TypeLD>, Enc_5e2823 {
10032let Inst{13-5} = 0b000000000;
10033let Inst{31-21} = 0b10010010000;
10034let hasNewValue = 1;
10035let opNewValue = 0;
10036let accessSize = WordAccess;
10037let mayLoad = 1;
10038let isSoloAX = 1;
10039}
10040def L2_ploadrbf_io : HInst<
10041(outs IntRegs:$Rd32),
10042(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10043"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
10044tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10045let Inst{13-13} = 0b0;
10046let Inst{31-21} = 0b01000101000;
10047let isPredicated = 1;
10048let isPredicatedFalse = 1;
10049let hasNewValue = 1;
10050let opNewValue = 0;
10051let addrMode = BaseImmOffset;
10052let accessSize = ByteAccess;
10053let mayLoad = 1;
10054let CextOpcode = "L2_loadrb";
10055let BaseOpcode = "L2_loadrb_io";
10056let isExtendable = 1;
10057let opExtendable = 3;
10058let isExtentSigned = 0;
10059let opExtentBits = 6;
10060let opExtentAlign = 0;
10061}
10062def L2_ploadrbf_pi : HInst<
10063(outs IntRegs:$Rd32, IntRegs:$Rx32),
10064(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10065"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
10066tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel {
10067let Inst{13-11} = 0b101;
10068let Inst{31-21} = 0b10011011000;
10069let isPredicated = 1;
10070let isPredicatedFalse = 1;
10071let hasNewValue = 1;
10072let opNewValue = 0;
10073let addrMode = PostInc;
10074let accessSize = ByteAccess;
10075let mayLoad = 1;
10076let BaseOpcode = "L2_loadrb_pi";
10077let Constraints = "$Rx32 = $Rx32in";
10078}
10079def L2_ploadrbf_zomap : HInst<
10080(outs IntRegs:$Rd32),
10081(ins PredRegs:$Pt4, IntRegs:$Rs32),
10082"if (!$Pt4) $Rd32 = memb($Rs32)",
10083tc_5ef37dc4, TypeMAPPING> {
10084let hasNewValue = 1;
10085let opNewValue = 0;
10086let isPseudo = 1;
10087let isCodeGenOnly = 1;
10088}
10089def L2_ploadrbfnew_io : HInst<
10090(outs IntRegs:$Rd32),
10091(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10092"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10093tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10094let Inst{13-13} = 0b0;
10095let Inst{31-21} = 0b01000111000;
10096let isPredicated = 1;
10097let isPredicatedFalse = 1;
10098let hasNewValue = 1;
10099let opNewValue = 0;
10100let addrMode = BaseImmOffset;
10101let accessSize = ByteAccess;
10102let isPredicatedNew = 1;
10103let mayLoad = 1;
10104let CextOpcode = "L2_loadrb";
10105let BaseOpcode = "L2_loadrb_io";
10106let isExtendable = 1;
10107let opExtendable = 3;
10108let isExtentSigned = 0;
10109let opExtentBits = 6;
10110let opExtentAlign = 0;
10111}
10112def L2_ploadrbfnew_pi : HInst<
10113(outs IntRegs:$Rd32, IntRegs:$Rx32),
10114(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10115"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10116tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel {
10117let Inst{13-11} = 0b111;
10118let Inst{31-21} = 0b10011011000;
10119let isPredicated = 1;
10120let isPredicatedFalse = 1;
10121let hasNewValue = 1;
10122let opNewValue = 0;
10123let addrMode = PostInc;
10124let accessSize = ByteAccess;
10125let isPredicatedNew = 1;
10126let mayLoad = 1;
10127let BaseOpcode = "L2_loadrb_pi";
10128let Constraints = "$Rx32 = $Rx32in";
10129}
10130def L2_ploadrbfnew_zomap : HInst<
10131(outs IntRegs:$Rd32),
10132(ins PredRegs:$Pt4, IntRegs:$Rs32),
10133"if (!$Pt4.new) $Rd32 = memb($Rs32)",
10134tc_44d3da28, TypeMAPPING> {
10135let hasNewValue = 1;
10136let opNewValue = 0;
10137let isPseudo = 1;
10138let isCodeGenOnly = 1;
10139}
10140def L2_ploadrbt_io : HInst<
10141(outs IntRegs:$Rd32),
10142(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10143"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
10144tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10145let Inst{13-13} = 0b0;
10146let Inst{31-21} = 0b01000001000;
10147let isPredicated = 1;
10148let hasNewValue = 1;
10149let opNewValue = 0;
10150let addrMode = BaseImmOffset;
10151let accessSize = ByteAccess;
10152let mayLoad = 1;
10153let CextOpcode = "L2_loadrb";
10154let BaseOpcode = "L2_loadrb_io";
10155let isExtendable = 1;
10156let opExtendable = 3;
10157let isExtentSigned = 0;
10158let opExtentBits = 6;
10159let opExtentAlign = 0;
10160}
10161def L2_ploadrbt_pi : HInst<
10162(outs IntRegs:$Rd32, IntRegs:$Rx32),
10163(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10164"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
10165tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel {
10166let Inst{13-11} = 0b100;
10167let Inst{31-21} = 0b10011011000;
10168let isPredicated = 1;
10169let hasNewValue = 1;
10170let opNewValue = 0;
10171let addrMode = PostInc;
10172let accessSize = ByteAccess;
10173let mayLoad = 1;
10174let BaseOpcode = "L2_loadrb_pi";
10175let Constraints = "$Rx32 = $Rx32in";
10176}
10177def L2_ploadrbt_zomap : HInst<
10178(outs IntRegs:$Rd32),
10179(ins PredRegs:$Pt4, IntRegs:$Rs32),
10180"if ($Pt4) $Rd32 = memb($Rs32)",
10181tc_5ef37dc4, TypeMAPPING> {
10182let hasNewValue = 1;
10183let opNewValue = 0;
10184let isPseudo = 1;
10185let isCodeGenOnly = 1;
10186}
10187def L2_ploadrbtnew_io : HInst<
10188(outs IntRegs:$Rd32),
10189(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10190"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10191tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10192let Inst{13-13} = 0b0;
10193let Inst{31-21} = 0b01000011000;
10194let isPredicated = 1;
10195let hasNewValue = 1;
10196let opNewValue = 0;
10197let addrMode = BaseImmOffset;
10198let accessSize = ByteAccess;
10199let isPredicatedNew = 1;
10200let mayLoad = 1;
10201let CextOpcode = "L2_loadrb";
10202let BaseOpcode = "L2_loadrb_io";
10203let isExtendable = 1;
10204let opExtendable = 3;
10205let isExtentSigned = 0;
10206let opExtentBits = 6;
10207let opExtentAlign = 0;
10208}
10209def L2_ploadrbtnew_pi : HInst<
10210(outs IntRegs:$Rd32, IntRegs:$Rx32),
10211(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10212"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10213tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel {
10214let Inst{13-11} = 0b110;
10215let Inst{31-21} = 0b10011011000;
10216let isPredicated = 1;
10217let hasNewValue = 1;
10218let opNewValue = 0;
10219let addrMode = PostInc;
10220let accessSize = ByteAccess;
10221let isPredicatedNew = 1;
10222let mayLoad = 1;
10223let BaseOpcode = "L2_loadrb_pi";
10224let Constraints = "$Rx32 = $Rx32in";
10225}
10226def L2_ploadrbtnew_zomap : HInst<
10227(outs IntRegs:$Rd32),
10228(ins PredRegs:$Pt4, IntRegs:$Rs32),
10229"if ($Pt4.new) $Rd32 = memb($Rs32)",
10230tc_44d3da28, TypeMAPPING> {
10231let hasNewValue = 1;
10232let opNewValue = 0;
10233let isPseudo = 1;
10234let isCodeGenOnly = 1;
10235}
10236def L2_ploadrdf_io : HInst<
10237(outs DoubleRegs:$Rdd32),
10238(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10239"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10240tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10241let Inst{13-13} = 0b0;
10242let Inst{31-21} = 0b01000101110;
10243let isPredicated = 1;
10244let isPredicatedFalse = 1;
10245let addrMode = BaseImmOffset;
10246let accessSize = DoubleWordAccess;
10247let mayLoad = 1;
10248let CextOpcode = "L2_loadrd";
10249let BaseOpcode = "L2_loadrd_io";
10250let isExtendable = 1;
10251let opExtendable = 3;
10252let isExtentSigned = 0;
10253let opExtentBits = 9;
10254let opExtentAlign = 3;
10255}
10256def L2_ploadrdf_pi : HInst<
10257(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10258(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10259"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10260tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel {
10261let Inst{13-11} = 0b101;
10262let Inst{31-21} = 0b10011011110;
10263let isPredicated = 1;
10264let isPredicatedFalse = 1;
10265let addrMode = PostInc;
10266let accessSize = DoubleWordAccess;
10267let mayLoad = 1;
10268let BaseOpcode = "L2_loadrd_pi";
10269let Constraints = "$Rx32 = $Rx32in";
10270}
10271def L2_ploadrdf_zomap : HInst<
10272(outs DoubleRegs:$Rdd32),
10273(ins PredRegs:$Pt4, IntRegs:$Rs32),
10274"if (!$Pt4) $Rdd32 = memd($Rs32)",
10275tc_5ef37dc4, TypeMAPPING> {
10276let isPseudo = 1;
10277let isCodeGenOnly = 1;
10278}
10279def L2_ploadrdfnew_io : HInst<
10280(outs DoubleRegs:$Rdd32),
10281(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10282"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10283tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10284let Inst{13-13} = 0b0;
10285let Inst{31-21} = 0b01000111110;
10286let isPredicated = 1;
10287let isPredicatedFalse = 1;
10288let addrMode = BaseImmOffset;
10289let accessSize = DoubleWordAccess;
10290let isPredicatedNew = 1;
10291let mayLoad = 1;
10292let CextOpcode = "L2_loadrd";
10293let BaseOpcode = "L2_loadrd_io";
10294let isExtendable = 1;
10295let opExtendable = 3;
10296let isExtentSigned = 0;
10297let opExtentBits = 9;
10298let opExtentAlign = 3;
10299}
10300def L2_ploadrdfnew_pi : HInst<
10301(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10302(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10303"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10304tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel {
10305let Inst{13-11} = 0b111;
10306let Inst{31-21} = 0b10011011110;
10307let isPredicated = 1;
10308let isPredicatedFalse = 1;
10309let addrMode = PostInc;
10310let accessSize = DoubleWordAccess;
10311let isPredicatedNew = 1;
10312let mayLoad = 1;
10313let BaseOpcode = "L2_loadrd_pi";
10314let Constraints = "$Rx32 = $Rx32in";
10315}
10316def L2_ploadrdfnew_zomap : HInst<
10317(outs DoubleRegs:$Rdd32),
10318(ins PredRegs:$Pt4, IntRegs:$Rs32),
10319"if (!$Pt4.new) $Rdd32 = memd($Rs32)",
10320tc_44d3da28, TypeMAPPING> {
10321let isPseudo = 1;
10322let isCodeGenOnly = 1;
10323}
10324def L2_ploadrdt_io : HInst<
10325(outs DoubleRegs:$Rdd32),
10326(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10327"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10328tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10329let Inst{13-13} = 0b0;
10330let Inst{31-21} = 0b01000001110;
10331let isPredicated = 1;
10332let addrMode = BaseImmOffset;
10333let accessSize = DoubleWordAccess;
10334let mayLoad = 1;
10335let CextOpcode = "L2_loadrd";
10336let BaseOpcode = "L2_loadrd_io";
10337let isExtendable = 1;
10338let opExtendable = 3;
10339let isExtentSigned = 0;
10340let opExtentBits = 9;
10341let opExtentAlign = 3;
10342}
10343def L2_ploadrdt_pi : HInst<
10344(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10345(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10346"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10347tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel {
10348let Inst{13-11} = 0b100;
10349let Inst{31-21} = 0b10011011110;
10350let isPredicated = 1;
10351let addrMode = PostInc;
10352let accessSize = DoubleWordAccess;
10353let mayLoad = 1;
10354let BaseOpcode = "L2_loadrd_pi";
10355let Constraints = "$Rx32 = $Rx32in";
10356}
10357def L2_ploadrdt_zomap : HInst<
10358(outs DoubleRegs:$Rdd32),
10359(ins PredRegs:$Pt4, IntRegs:$Rs32),
10360"if ($Pt4) $Rdd32 = memd($Rs32)",
10361tc_5ef37dc4, TypeMAPPING> {
10362let isPseudo = 1;
10363let isCodeGenOnly = 1;
10364}
10365def L2_ploadrdtnew_io : HInst<
10366(outs DoubleRegs:$Rdd32),
10367(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10368"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10369tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10370let Inst{13-13} = 0b0;
10371let Inst{31-21} = 0b01000011110;
10372let isPredicated = 1;
10373let addrMode = BaseImmOffset;
10374let accessSize = DoubleWordAccess;
10375let isPredicatedNew = 1;
10376let mayLoad = 1;
10377let CextOpcode = "L2_loadrd";
10378let BaseOpcode = "L2_loadrd_io";
10379let isExtendable = 1;
10380let opExtendable = 3;
10381let isExtentSigned = 0;
10382let opExtentBits = 9;
10383let opExtentAlign = 3;
10384}
10385def L2_ploadrdtnew_pi : HInst<
10386(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10387(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10388"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10389tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel {
10390let Inst{13-11} = 0b110;
10391let Inst{31-21} = 0b10011011110;
10392let isPredicated = 1;
10393let addrMode = PostInc;
10394let accessSize = DoubleWordAccess;
10395let isPredicatedNew = 1;
10396let mayLoad = 1;
10397let BaseOpcode = "L2_loadrd_pi";
10398let Constraints = "$Rx32 = $Rx32in";
10399}
10400def L2_ploadrdtnew_zomap : HInst<
10401(outs DoubleRegs:$Rdd32),
10402(ins PredRegs:$Pt4, IntRegs:$Rs32),
10403"if ($Pt4.new) $Rdd32 = memd($Rs32)",
10404tc_44d3da28, TypeMAPPING> {
10405let isPseudo = 1;
10406let isCodeGenOnly = 1;
10407}
10408def L2_ploadrhf_io : HInst<
10409(outs IntRegs:$Rd32),
10410(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10411"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
10412tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10413let Inst{13-13} = 0b0;
10414let Inst{31-21} = 0b01000101010;
10415let isPredicated = 1;
10416let isPredicatedFalse = 1;
10417let hasNewValue = 1;
10418let opNewValue = 0;
10419let addrMode = BaseImmOffset;
10420let accessSize = HalfWordAccess;
10421let mayLoad = 1;
10422let CextOpcode = "L2_loadrh";
10423let BaseOpcode = "L2_loadrh_io";
10424let isExtendable = 1;
10425let opExtendable = 3;
10426let isExtentSigned = 0;
10427let opExtentBits = 7;
10428let opExtentAlign = 1;
10429}
10430def L2_ploadrhf_pi : HInst<
10431(outs IntRegs:$Rd32, IntRegs:$Rx32),
10432(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10433"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
10434tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel {
10435let Inst{13-11} = 0b101;
10436let Inst{31-21} = 0b10011011010;
10437let isPredicated = 1;
10438let isPredicatedFalse = 1;
10439let hasNewValue = 1;
10440let opNewValue = 0;
10441let addrMode = PostInc;
10442let accessSize = HalfWordAccess;
10443let mayLoad = 1;
10444let BaseOpcode = "L2_loadrh_pi";
10445let Constraints = "$Rx32 = $Rx32in";
10446}
10447def L2_ploadrhf_zomap : HInst<
10448(outs IntRegs:$Rd32),
10449(ins PredRegs:$Pt4, IntRegs:$Rs32),
10450"if (!$Pt4) $Rd32 = memh($Rs32)",
10451tc_5ef37dc4, TypeMAPPING> {
10452let hasNewValue = 1;
10453let opNewValue = 0;
10454let isPseudo = 1;
10455let isCodeGenOnly = 1;
10456}
10457def L2_ploadrhfnew_io : HInst<
10458(outs IntRegs:$Rd32),
10459(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10460"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10461tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10462let Inst{13-13} = 0b0;
10463let Inst{31-21} = 0b01000111010;
10464let isPredicated = 1;
10465let isPredicatedFalse = 1;
10466let hasNewValue = 1;
10467let opNewValue = 0;
10468let addrMode = BaseImmOffset;
10469let accessSize = HalfWordAccess;
10470let isPredicatedNew = 1;
10471let mayLoad = 1;
10472let CextOpcode = "L2_loadrh";
10473let BaseOpcode = "L2_loadrh_io";
10474let isExtendable = 1;
10475let opExtendable = 3;
10476let isExtentSigned = 0;
10477let opExtentBits = 7;
10478let opExtentAlign = 1;
10479}
10480def L2_ploadrhfnew_pi : HInst<
10481(outs IntRegs:$Rd32, IntRegs:$Rx32),
10482(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10483"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10484tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel {
10485let Inst{13-11} = 0b111;
10486let Inst{31-21} = 0b10011011010;
10487let isPredicated = 1;
10488let isPredicatedFalse = 1;
10489let hasNewValue = 1;
10490let opNewValue = 0;
10491let addrMode = PostInc;
10492let accessSize = HalfWordAccess;
10493let isPredicatedNew = 1;
10494let mayLoad = 1;
10495let BaseOpcode = "L2_loadrh_pi";
10496let Constraints = "$Rx32 = $Rx32in";
10497}
10498def L2_ploadrhfnew_zomap : HInst<
10499(outs IntRegs:$Rd32),
10500(ins PredRegs:$Pt4, IntRegs:$Rs32),
10501"if (!$Pt4.new) $Rd32 = memh($Rs32)",
10502tc_44d3da28, TypeMAPPING> {
10503let hasNewValue = 1;
10504let opNewValue = 0;
10505let isPseudo = 1;
10506let isCodeGenOnly = 1;
10507}
10508def L2_ploadrht_io : HInst<
10509(outs IntRegs:$Rd32),
10510(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10511"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
10512tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10513let Inst{13-13} = 0b0;
10514let Inst{31-21} = 0b01000001010;
10515let isPredicated = 1;
10516let hasNewValue = 1;
10517let opNewValue = 0;
10518let addrMode = BaseImmOffset;
10519let accessSize = HalfWordAccess;
10520let mayLoad = 1;
10521let CextOpcode = "L2_loadrh";
10522let BaseOpcode = "L2_loadrh_io";
10523let isExtendable = 1;
10524let opExtendable = 3;
10525let isExtentSigned = 0;
10526let opExtentBits = 7;
10527let opExtentAlign = 1;
10528}
10529def L2_ploadrht_pi : HInst<
10530(outs IntRegs:$Rd32, IntRegs:$Rx32),
10531(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10532"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
10533tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel {
10534let Inst{13-11} = 0b100;
10535let Inst{31-21} = 0b10011011010;
10536let isPredicated = 1;
10537let hasNewValue = 1;
10538let opNewValue = 0;
10539let addrMode = PostInc;
10540let accessSize = HalfWordAccess;
10541let mayLoad = 1;
10542let BaseOpcode = "L2_loadrh_pi";
10543let Constraints = "$Rx32 = $Rx32in";
10544}
10545def L2_ploadrht_zomap : HInst<
10546(outs IntRegs:$Rd32),
10547(ins PredRegs:$Pt4, IntRegs:$Rs32),
10548"if ($Pt4) $Rd32 = memh($Rs32)",
10549tc_5ef37dc4, TypeMAPPING> {
10550let hasNewValue = 1;
10551let opNewValue = 0;
10552let isPseudo = 1;
10553let isCodeGenOnly = 1;
10554}
10555def L2_ploadrhtnew_io : HInst<
10556(outs IntRegs:$Rd32),
10557(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10558"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10559tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10560let Inst{13-13} = 0b0;
10561let Inst{31-21} = 0b01000011010;
10562let isPredicated = 1;
10563let hasNewValue = 1;
10564let opNewValue = 0;
10565let addrMode = BaseImmOffset;
10566let accessSize = HalfWordAccess;
10567let isPredicatedNew = 1;
10568let mayLoad = 1;
10569let CextOpcode = "L2_loadrh";
10570let BaseOpcode = "L2_loadrh_io";
10571let isExtendable = 1;
10572let opExtendable = 3;
10573let isExtentSigned = 0;
10574let opExtentBits = 7;
10575let opExtentAlign = 1;
10576}
10577def L2_ploadrhtnew_pi : HInst<
10578(outs IntRegs:$Rd32, IntRegs:$Rx32),
10579(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10580"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10581tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel {
10582let Inst{13-11} = 0b110;
10583let Inst{31-21} = 0b10011011010;
10584let isPredicated = 1;
10585let hasNewValue = 1;
10586let opNewValue = 0;
10587let addrMode = PostInc;
10588let accessSize = HalfWordAccess;
10589let isPredicatedNew = 1;
10590let mayLoad = 1;
10591let BaseOpcode = "L2_loadrh_pi";
10592let Constraints = "$Rx32 = $Rx32in";
10593}
10594def L2_ploadrhtnew_zomap : HInst<
10595(outs IntRegs:$Rd32),
10596(ins PredRegs:$Pt4, IntRegs:$Rs32),
10597"if ($Pt4.new) $Rd32 = memh($Rs32)",
10598tc_44d3da28, TypeMAPPING> {
10599let hasNewValue = 1;
10600let opNewValue = 0;
10601let isPseudo = 1;
10602let isCodeGenOnly = 1;
10603}
10604def L2_ploadrif_io : HInst<
10605(outs IntRegs:$Rd32),
10606(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10607"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
10608tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10609let Inst{13-13} = 0b0;
10610let Inst{31-21} = 0b01000101100;
10611let isPredicated = 1;
10612let isPredicatedFalse = 1;
10613let hasNewValue = 1;
10614let opNewValue = 0;
10615let addrMode = BaseImmOffset;
10616let accessSize = WordAccess;
10617let mayLoad = 1;
10618let CextOpcode = "L2_loadri";
10619let BaseOpcode = "L2_loadri_io";
10620let isExtendable = 1;
10621let opExtendable = 3;
10622let isExtentSigned = 0;
10623let opExtentBits = 8;
10624let opExtentAlign = 2;
10625}
10626def L2_ploadrif_pi : HInst<
10627(outs IntRegs:$Rd32, IntRegs:$Rx32),
10628(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10629"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
10630tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel {
10631let Inst{13-11} = 0b101;
10632let Inst{31-21} = 0b10011011100;
10633let isPredicated = 1;
10634let isPredicatedFalse = 1;
10635let hasNewValue = 1;
10636let opNewValue = 0;
10637let addrMode = PostInc;
10638let accessSize = WordAccess;
10639let mayLoad = 1;
10640let BaseOpcode = "L2_loadri_pi";
10641let Constraints = "$Rx32 = $Rx32in";
10642}
10643def L2_ploadrif_zomap : HInst<
10644(outs IntRegs:$Rd32),
10645(ins PredRegs:$Pt4, IntRegs:$Rs32),
10646"if (!$Pt4) $Rd32 = memw($Rs32)",
10647tc_5ef37dc4, TypeMAPPING> {
10648let hasNewValue = 1;
10649let opNewValue = 0;
10650let isPseudo = 1;
10651let isCodeGenOnly = 1;
10652}
10653def L2_ploadrifnew_io : HInst<
10654(outs IntRegs:$Rd32),
10655(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10656"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10657tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10658let Inst{13-13} = 0b0;
10659let Inst{31-21} = 0b01000111100;
10660let isPredicated = 1;
10661let isPredicatedFalse = 1;
10662let hasNewValue = 1;
10663let opNewValue = 0;
10664let addrMode = BaseImmOffset;
10665let accessSize = WordAccess;
10666let isPredicatedNew = 1;
10667let mayLoad = 1;
10668let CextOpcode = "L2_loadri";
10669let BaseOpcode = "L2_loadri_io";
10670let isExtendable = 1;
10671let opExtendable = 3;
10672let isExtentSigned = 0;
10673let opExtentBits = 8;
10674let opExtentAlign = 2;
10675}
10676def L2_ploadrifnew_pi : HInst<
10677(outs IntRegs:$Rd32, IntRegs:$Rx32),
10678(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10679"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10680tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel {
10681let Inst{13-11} = 0b111;
10682let Inst{31-21} = 0b10011011100;
10683let isPredicated = 1;
10684let isPredicatedFalse = 1;
10685let hasNewValue = 1;
10686let opNewValue = 0;
10687let addrMode = PostInc;
10688let accessSize = WordAccess;
10689let isPredicatedNew = 1;
10690let mayLoad = 1;
10691let BaseOpcode = "L2_loadri_pi";
10692let Constraints = "$Rx32 = $Rx32in";
10693}
10694def L2_ploadrifnew_zomap : HInst<
10695(outs IntRegs:$Rd32),
10696(ins PredRegs:$Pt4, IntRegs:$Rs32),
10697"if (!$Pt4.new) $Rd32 = memw($Rs32)",
10698tc_44d3da28, TypeMAPPING> {
10699let hasNewValue = 1;
10700let opNewValue = 0;
10701let isPseudo = 1;
10702let isCodeGenOnly = 1;
10703}
10704def L2_ploadrit_io : HInst<
10705(outs IntRegs:$Rd32),
10706(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10707"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
10708tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10709let Inst{13-13} = 0b0;
10710let Inst{31-21} = 0b01000001100;
10711let isPredicated = 1;
10712let hasNewValue = 1;
10713let opNewValue = 0;
10714let addrMode = BaseImmOffset;
10715let accessSize = WordAccess;
10716let mayLoad = 1;
10717let CextOpcode = "L2_loadri";
10718let BaseOpcode = "L2_loadri_io";
10719let isExtendable = 1;
10720let opExtendable = 3;
10721let isExtentSigned = 0;
10722let opExtentBits = 8;
10723let opExtentAlign = 2;
10724}
10725def L2_ploadrit_pi : HInst<
10726(outs IntRegs:$Rd32, IntRegs:$Rx32),
10727(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10728"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
10729tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel {
10730let Inst{13-11} = 0b100;
10731let Inst{31-21} = 0b10011011100;
10732let isPredicated = 1;
10733let hasNewValue = 1;
10734let opNewValue = 0;
10735let addrMode = PostInc;
10736let accessSize = WordAccess;
10737let mayLoad = 1;
10738let BaseOpcode = "L2_loadri_pi";
10739let Constraints = "$Rx32 = $Rx32in";
10740}
10741def L2_ploadrit_zomap : HInst<
10742(outs IntRegs:$Rd32),
10743(ins PredRegs:$Pt4, IntRegs:$Rs32),
10744"if ($Pt4) $Rd32 = memw($Rs32)",
10745tc_5ef37dc4, TypeMAPPING> {
10746let hasNewValue = 1;
10747let opNewValue = 0;
10748let isPseudo = 1;
10749let isCodeGenOnly = 1;
10750}
10751def L2_ploadritnew_io : HInst<
10752(outs IntRegs:$Rd32),
10753(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10754"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10755tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10756let Inst{13-13} = 0b0;
10757let Inst{31-21} = 0b01000011100;
10758let isPredicated = 1;
10759let hasNewValue = 1;
10760let opNewValue = 0;
10761let addrMode = BaseImmOffset;
10762let accessSize = WordAccess;
10763let isPredicatedNew = 1;
10764let mayLoad = 1;
10765let CextOpcode = "L2_loadri";
10766let BaseOpcode = "L2_loadri_io";
10767let isExtendable = 1;
10768let opExtendable = 3;
10769let isExtentSigned = 0;
10770let opExtentBits = 8;
10771let opExtentAlign = 2;
10772}
10773def L2_ploadritnew_pi : HInst<
10774(outs IntRegs:$Rd32, IntRegs:$Rx32),
10775(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10776"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10777tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel {
10778let Inst{13-11} = 0b110;
10779let Inst{31-21} = 0b10011011100;
10780let isPredicated = 1;
10781let hasNewValue = 1;
10782let opNewValue = 0;
10783let addrMode = PostInc;
10784let accessSize = WordAccess;
10785let isPredicatedNew = 1;
10786let mayLoad = 1;
10787let BaseOpcode = "L2_loadri_pi";
10788let Constraints = "$Rx32 = $Rx32in";
10789}
10790def L2_ploadritnew_zomap : HInst<
10791(outs IntRegs:$Rd32),
10792(ins PredRegs:$Pt4, IntRegs:$Rs32),
10793"if ($Pt4.new) $Rd32 = memw($Rs32)",
10794tc_44d3da28, TypeMAPPING> {
10795let hasNewValue = 1;
10796let opNewValue = 0;
10797let isPseudo = 1;
10798let isCodeGenOnly = 1;
10799}
10800def L2_ploadrubf_io : HInst<
10801(outs IntRegs:$Rd32),
10802(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10803"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
10804tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10805let Inst{13-13} = 0b0;
10806let Inst{31-21} = 0b01000101001;
10807let isPredicated = 1;
10808let isPredicatedFalse = 1;
10809let hasNewValue = 1;
10810let opNewValue = 0;
10811let addrMode = BaseImmOffset;
10812let accessSize = ByteAccess;
10813let mayLoad = 1;
10814let CextOpcode = "L2_loadrub";
10815let BaseOpcode = "L2_loadrub_io";
10816let isExtendable = 1;
10817let opExtendable = 3;
10818let isExtentSigned = 0;
10819let opExtentBits = 6;
10820let opExtentAlign = 0;
10821}
10822def L2_ploadrubf_pi : HInst<
10823(outs IntRegs:$Rd32, IntRegs:$Rx32),
10824(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10825"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
10826tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel {
10827let Inst{13-11} = 0b101;
10828let Inst{31-21} = 0b10011011001;
10829let isPredicated = 1;
10830let isPredicatedFalse = 1;
10831let hasNewValue = 1;
10832let opNewValue = 0;
10833let addrMode = PostInc;
10834let accessSize = ByteAccess;
10835let mayLoad = 1;
10836let BaseOpcode = "L2_loadrub_pi";
10837let Constraints = "$Rx32 = $Rx32in";
10838}
10839def L2_ploadrubf_zomap : HInst<
10840(outs IntRegs:$Rd32),
10841(ins PredRegs:$Pt4, IntRegs:$Rs32),
10842"if (!$Pt4) $Rd32 = memub($Rs32)",
10843tc_5ef37dc4, TypeMAPPING> {
10844let hasNewValue = 1;
10845let opNewValue = 0;
10846let isPseudo = 1;
10847let isCodeGenOnly = 1;
10848}
10849def L2_ploadrubfnew_io : HInst<
10850(outs IntRegs:$Rd32),
10851(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10852"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
10853tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10854let Inst{13-13} = 0b0;
10855let Inst{31-21} = 0b01000111001;
10856let isPredicated = 1;
10857let isPredicatedFalse = 1;
10858let hasNewValue = 1;
10859let opNewValue = 0;
10860let addrMode = BaseImmOffset;
10861let accessSize = ByteAccess;
10862let isPredicatedNew = 1;
10863let mayLoad = 1;
10864let CextOpcode = "L2_loadrub";
10865let BaseOpcode = "L2_loadrub_io";
10866let isExtendable = 1;
10867let opExtendable = 3;
10868let isExtentSigned = 0;
10869let opExtentBits = 6;
10870let opExtentAlign = 0;
10871}
10872def L2_ploadrubfnew_pi : HInst<
10873(outs IntRegs:$Rd32, IntRegs:$Rx32),
10874(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10875"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
10876tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel {
10877let Inst{13-11} = 0b111;
10878let Inst{31-21} = 0b10011011001;
10879let isPredicated = 1;
10880let isPredicatedFalse = 1;
10881let hasNewValue = 1;
10882let opNewValue = 0;
10883let addrMode = PostInc;
10884let accessSize = ByteAccess;
10885let isPredicatedNew = 1;
10886let mayLoad = 1;
10887let BaseOpcode = "L2_loadrub_pi";
10888let Constraints = "$Rx32 = $Rx32in";
10889}
10890def L2_ploadrubfnew_zomap : HInst<
10891(outs IntRegs:$Rd32),
10892(ins PredRegs:$Pt4, IntRegs:$Rs32),
10893"if (!$Pt4.new) $Rd32 = memub($Rs32)",
10894tc_44d3da28, TypeMAPPING> {
10895let hasNewValue = 1;
10896let opNewValue = 0;
10897let isPseudo = 1;
10898let isCodeGenOnly = 1;
10899}
10900def L2_ploadrubt_io : HInst<
10901(outs IntRegs:$Rd32),
10902(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10903"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
10904tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10905let Inst{13-13} = 0b0;
10906let Inst{31-21} = 0b01000001001;
10907let isPredicated = 1;
10908let hasNewValue = 1;
10909let opNewValue = 0;
10910let addrMode = BaseImmOffset;
10911let accessSize = ByteAccess;
10912let mayLoad = 1;
10913let CextOpcode = "L2_loadrub";
10914let BaseOpcode = "L2_loadrub_io";
10915let isExtendable = 1;
10916let opExtendable = 3;
10917let isExtentSigned = 0;
10918let opExtentBits = 6;
10919let opExtentAlign = 0;
10920}
10921def L2_ploadrubt_pi : HInst<
10922(outs IntRegs:$Rd32, IntRegs:$Rx32),
10923(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10924"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
10925tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel {
10926let Inst{13-11} = 0b100;
10927let Inst{31-21} = 0b10011011001;
10928let isPredicated = 1;
10929let hasNewValue = 1;
10930let opNewValue = 0;
10931let addrMode = PostInc;
10932let accessSize = ByteAccess;
10933let mayLoad = 1;
10934let BaseOpcode = "L2_loadrub_pi";
10935let Constraints = "$Rx32 = $Rx32in";
10936}
10937def L2_ploadrubt_zomap : HInst<
10938(outs IntRegs:$Rd32),
10939(ins PredRegs:$Pt4, IntRegs:$Rs32),
10940"if ($Pt4) $Rd32 = memub($Rs32)",
10941tc_5ef37dc4, TypeMAPPING> {
10942let hasNewValue = 1;
10943let opNewValue = 0;
10944let isPseudo = 1;
10945let isCodeGenOnly = 1;
10946}
10947def L2_ploadrubtnew_io : HInst<
10948(outs IntRegs:$Rd32),
10949(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10950"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
10951tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10952let Inst{13-13} = 0b0;
10953let Inst{31-21} = 0b01000011001;
10954let isPredicated = 1;
10955let hasNewValue = 1;
10956let opNewValue = 0;
10957let addrMode = BaseImmOffset;
10958let accessSize = ByteAccess;
10959let isPredicatedNew = 1;
10960let mayLoad = 1;
10961let CextOpcode = "L2_loadrub";
10962let BaseOpcode = "L2_loadrub_io";
10963let isExtendable = 1;
10964let opExtendable = 3;
10965let isExtentSigned = 0;
10966let opExtentBits = 6;
10967let opExtentAlign = 0;
10968}
10969def L2_ploadrubtnew_pi : HInst<
10970(outs IntRegs:$Rd32, IntRegs:$Rx32),
10971(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10972"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
10973tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel {
10974let Inst{13-11} = 0b110;
10975let Inst{31-21} = 0b10011011001;
10976let isPredicated = 1;
10977let hasNewValue = 1;
10978let opNewValue = 0;
10979let addrMode = PostInc;
10980let accessSize = ByteAccess;
10981let isPredicatedNew = 1;
10982let mayLoad = 1;
10983let BaseOpcode = "L2_loadrub_pi";
10984let Constraints = "$Rx32 = $Rx32in";
10985}
10986def L2_ploadrubtnew_zomap : HInst<
10987(outs IntRegs:$Rd32),
10988(ins PredRegs:$Pt4, IntRegs:$Rs32),
10989"if ($Pt4.new) $Rd32 = memub($Rs32)",
10990tc_44d3da28, TypeMAPPING> {
10991let hasNewValue = 1;
10992let opNewValue = 0;
10993let isPseudo = 1;
10994let isCodeGenOnly = 1;
10995}
10996def L2_ploadruhf_io : HInst<
10997(outs IntRegs:$Rd32),
10998(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10999"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11000tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11001let Inst{13-13} = 0b0;
11002let Inst{31-21} = 0b01000101011;
11003let isPredicated = 1;
11004let isPredicatedFalse = 1;
11005let hasNewValue = 1;
11006let opNewValue = 0;
11007let addrMode = BaseImmOffset;
11008let accessSize = HalfWordAccess;
11009let mayLoad = 1;
11010let CextOpcode = "L2_loadruh";
11011let BaseOpcode = "L2_loadruh_io";
11012let isExtendable = 1;
11013let opExtendable = 3;
11014let isExtentSigned = 0;
11015let opExtentBits = 7;
11016let opExtentAlign = 1;
11017}
11018def L2_ploadruhf_pi : HInst<
11019(outs IntRegs:$Rd32, IntRegs:$Rx32),
11020(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11021"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11022tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel {
11023let Inst{13-11} = 0b101;
11024let Inst{31-21} = 0b10011011011;
11025let isPredicated = 1;
11026let isPredicatedFalse = 1;
11027let hasNewValue = 1;
11028let opNewValue = 0;
11029let addrMode = PostInc;
11030let accessSize = HalfWordAccess;
11031let mayLoad = 1;
11032let BaseOpcode = "L2_loadruh_pi";
11033let Constraints = "$Rx32 = $Rx32in";
11034}
11035def L2_ploadruhf_zomap : HInst<
11036(outs IntRegs:$Rd32),
11037(ins PredRegs:$Pt4, IntRegs:$Rs32),
11038"if (!$Pt4) $Rd32 = memuh($Rs32)",
11039tc_5ef37dc4, TypeMAPPING> {
11040let hasNewValue = 1;
11041let opNewValue = 0;
11042let isPseudo = 1;
11043let isCodeGenOnly = 1;
11044}
11045def L2_ploadruhfnew_io : HInst<
11046(outs IntRegs:$Rd32),
11047(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11048"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11049tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11050let Inst{13-13} = 0b0;
11051let Inst{31-21} = 0b01000111011;
11052let isPredicated = 1;
11053let isPredicatedFalse = 1;
11054let hasNewValue = 1;
11055let opNewValue = 0;
11056let addrMode = BaseImmOffset;
11057let accessSize = HalfWordAccess;
11058let isPredicatedNew = 1;
11059let mayLoad = 1;
11060let CextOpcode = "L2_loadruh";
11061let BaseOpcode = "L2_loadruh_io";
11062let isExtendable = 1;
11063let opExtendable = 3;
11064let isExtentSigned = 0;
11065let opExtentBits = 7;
11066let opExtentAlign = 1;
11067}
11068def L2_ploadruhfnew_pi : HInst<
11069(outs IntRegs:$Rd32, IntRegs:$Rx32),
11070(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11071"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11072tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel {
11073let Inst{13-11} = 0b111;
11074let Inst{31-21} = 0b10011011011;
11075let isPredicated = 1;
11076let isPredicatedFalse = 1;
11077let hasNewValue = 1;
11078let opNewValue = 0;
11079let addrMode = PostInc;
11080let accessSize = HalfWordAccess;
11081let isPredicatedNew = 1;
11082let mayLoad = 1;
11083let BaseOpcode = "L2_loadruh_pi";
11084let Constraints = "$Rx32 = $Rx32in";
11085}
11086def L2_ploadruhfnew_zomap : HInst<
11087(outs IntRegs:$Rd32),
11088(ins PredRegs:$Pt4, IntRegs:$Rs32),
11089"if (!$Pt4.new) $Rd32 = memuh($Rs32)",
11090tc_44d3da28, TypeMAPPING> {
11091let hasNewValue = 1;
11092let opNewValue = 0;
11093let isPseudo = 1;
11094let isCodeGenOnly = 1;
11095}
11096def L2_ploadruht_io : HInst<
11097(outs IntRegs:$Rd32),
11098(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11099"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11100tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11101let Inst{13-13} = 0b0;
11102let Inst{31-21} = 0b01000001011;
11103let isPredicated = 1;
11104let hasNewValue = 1;
11105let opNewValue = 0;
11106let addrMode = BaseImmOffset;
11107let accessSize = HalfWordAccess;
11108let mayLoad = 1;
11109let CextOpcode = "L2_loadruh";
11110let BaseOpcode = "L2_loadruh_io";
11111let isExtendable = 1;
11112let opExtendable = 3;
11113let isExtentSigned = 0;
11114let opExtentBits = 7;
11115let opExtentAlign = 1;
11116}
11117def L2_ploadruht_pi : HInst<
11118(outs IntRegs:$Rd32, IntRegs:$Rx32),
11119(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11120"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11121tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel {
11122let Inst{13-11} = 0b100;
11123let Inst{31-21} = 0b10011011011;
11124let isPredicated = 1;
11125let hasNewValue = 1;
11126let opNewValue = 0;
11127let addrMode = PostInc;
11128let accessSize = HalfWordAccess;
11129let mayLoad = 1;
11130let BaseOpcode = "L2_loadruh_pi";
11131let Constraints = "$Rx32 = $Rx32in";
11132}
11133def L2_ploadruht_zomap : HInst<
11134(outs IntRegs:$Rd32),
11135(ins PredRegs:$Pt4, IntRegs:$Rs32),
11136"if ($Pt4) $Rd32 = memuh($Rs32)",
11137tc_5ef37dc4, TypeMAPPING> {
11138let hasNewValue = 1;
11139let opNewValue = 0;
11140let isPseudo = 1;
11141let isCodeGenOnly = 1;
11142}
11143def L2_ploadruhtnew_io : HInst<
11144(outs IntRegs:$Rd32),
11145(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11146"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11147tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11148let Inst{13-13} = 0b0;
11149let Inst{31-21} = 0b01000011011;
11150let isPredicated = 1;
11151let hasNewValue = 1;
11152let opNewValue = 0;
11153let addrMode = BaseImmOffset;
11154let accessSize = HalfWordAccess;
11155let isPredicatedNew = 1;
11156let mayLoad = 1;
11157let CextOpcode = "L2_loadruh";
11158let BaseOpcode = "L2_loadruh_io";
11159let isExtendable = 1;
11160let opExtendable = 3;
11161let isExtentSigned = 0;
11162let opExtentBits = 7;
11163let opExtentAlign = 1;
11164}
11165def L2_ploadruhtnew_pi : HInst<
11166(outs IntRegs:$Rd32, IntRegs:$Rx32),
11167(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11168"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11169tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel {
11170let Inst{13-11} = 0b110;
11171let Inst{31-21} = 0b10011011011;
11172let isPredicated = 1;
11173let hasNewValue = 1;
11174let opNewValue = 0;
11175let addrMode = PostInc;
11176let accessSize = HalfWordAccess;
11177let isPredicatedNew = 1;
11178let mayLoad = 1;
11179let BaseOpcode = "L2_loadruh_pi";
11180let Constraints = "$Rx32 = $Rx32in";
11181}
11182def L2_ploadruhtnew_zomap : HInst<
11183(outs IntRegs:$Rd32),
11184(ins PredRegs:$Pt4, IntRegs:$Rs32),
11185"if ($Pt4.new) $Rd32 = memuh($Rs32)",
11186tc_44d3da28, TypeMAPPING> {
11187let hasNewValue = 1;
11188let opNewValue = 0;
11189let isPseudo = 1;
11190let isCodeGenOnly = 1;
11191}
11192def L4_add_memopb_io : HInst<
11193(outs),
11194(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11195"memb($Rs32+#$Ii) += $Rt32",
11196tc_7186d325, TypeV4LDST>, Enc_d44e31 {
11197let Inst{6-5} = 0b00;
11198let Inst{13-13} = 0b0;
11199let Inst{31-21} = 0b00111110000;
11200let addrMode = BaseImmOffset;
11201let accessSize = ByteAccess;
11202let mayLoad = 1;
11203let isRestrictNoSlot1Store = 1;
11204let mayStore = 1;
11205let isExtendable = 1;
11206let opExtendable = 1;
11207let isExtentSigned = 0;
11208let opExtentBits = 6;
11209let opExtentAlign = 0;
11210}
11211def L4_add_memopb_zomap : HInst<
11212(outs),
11213(ins IntRegs:$Rs32, IntRegs:$Rt32),
11214"memb($Rs32) += $Rt32",
11215tc_7186d325, TypeMAPPING> {
11216let isPseudo = 1;
11217let isCodeGenOnly = 1;
11218}
11219def L4_add_memoph_io : HInst<
11220(outs),
11221(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11222"memh($Rs32+#$Ii) += $Rt32",
11223tc_7186d325, TypeV4LDST>, Enc_163a3c {
11224let Inst{6-5} = 0b00;
11225let Inst{13-13} = 0b0;
11226let Inst{31-21} = 0b00111110001;
11227let addrMode = BaseImmOffset;
11228let accessSize = HalfWordAccess;
11229let mayLoad = 1;
11230let isRestrictNoSlot1Store = 1;
11231let mayStore = 1;
11232let isExtendable = 1;
11233let opExtendable = 1;
11234let isExtentSigned = 0;
11235let opExtentBits = 7;
11236let opExtentAlign = 1;
11237}
11238def L4_add_memoph_zomap : HInst<
11239(outs),
11240(ins IntRegs:$Rs32, IntRegs:$Rt32),
11241"memh($Rs32) += $Rt32",
11242tc_7186d325, TypeMAPPING> {
11243let isPseudo = 1;
11244let isCodeGenOnly = 1;
11245}
11246def L4_add_memopw_io : HInst<
11247(outs),
11248(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11249"memw($Rs32+#$Ii) += $Rt32",
11250tc_7186d325, TypeV4LDST>, Enc_226535 {
11251let Inst{6-5} = 0b00;
11252let Inst{13-13} = 0b0;
11253let Inst{31-21} = 0b00111110010;
11254let addrMode = BaseImmOffset;
11255let accessSize = WordAccess;
11256let mayLoad = 1;
11257let isRestrictNoSlot1Store = 1;
11258let mayStore = 1;
11259let isExtendable = 1;
11260let opExtendable = 1;
11261let isExtentSigned = 0;
11262let opExtentBits = 8;
11263let opExtentAlign = 2;
11264}
11265def L4_add_memopw_zomap : HInst<
11266(outs),
11267(ins IntRegs:$Rs32, IntRegs:$Rt32),
11268"memw($Rs32) += $Rt32",
11269tc_7186d325, TypeMAPPING> {
11270let isPseudo = 1;
11271let isCodeGenOnly = 1;
11272}
11273def L4_and_memopb_io : HInst<
11274(outs),
11275(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11276"memb($Rs32+#$Ii) &= $Rt32",
11277tc_7186d325, TypeV4LDST>, Enc_d44e31 {
11278let Inst{6-5} = 0b10;
11279let Inst{13-13} = 0b0;
11280let Inst{31-21} = 0b00111110000;
11281let addrMode = BaseImmOffset;
11282let accessSize = ByteAccess;
11283let mayLoad = 1;
11284let isRestrictNoSlot1Store = 1;
11285let mayStore = 1;
11286let isExtendable = 1;
11287let opExtendable = 1;
11288let isExtentSigned = 0;
11289let opExtentBits = 6;
11290let opExtentAlign = 0;
11291}
11292def L4_and_memopb_zomap : HInst<
11293(outs),
11294(ins IntRegs:$Rs32, IntRegs:$Rt32),
11295"memb($Rs32) &= $Rt32",
11296tc_7186d325, TypeMAPPING> {
11297let isPseudo = 1;
11298let isCodeGenOnly = 1;
11299}
11300def L4_and_memoph_io : HInst<
11301(outs),
11302(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11303"memh($Rs32+#$Ii) &= $Rt32",
11304tc_7186d325, TypeV4LDST>, Enc_163a3c {
11305let Inst{6-5} = 0b10;
11306let Inst{13-13} = 0b0;
11307let Inst{31-21} = 0b00111110001;
11308let addrMode = BaseImmOffset;
11309let accessSize = HalfWordAccess;
11310let mayLoad = 1;
11311let isRestrictNoSlot1Store = 1;
11312let mayStore = 1;
11313let isExtendable = 1;
11314let opExtendable = 1;
11315let isExtentSigned = 0;
11316let opExtentBits = 7;
11317let opExtentAlign = 1;
11318}
11319def L4_and_memoph_zomap : HInst<
11320(outs),
11321(ins IntRegs:$Rs32, IntRegs:$Rt32),
11322"memh($Rs32) &= $Rt32",
11323tc_7186d325, TypeMAPPING> {
11324let isPseudo = 1;
11325let isCodeGenOnly = 1;
11326}
11327def L4_and_memopw_io : HInst<
11328(outs),
11329(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11330"memw($Rs32+#$Ii) &= $Rt32",
11331tc_7186d325, TypeV4LDST>, Enc_226535 {
11332let Inst{6-5} = 0b10;
11333let Inst{13-13} = 0b0;
11334let Inst{31-21} = 0b00111110010;
11335let addrMode = BaseImmOffset;
11336let accessSize = WordAccess;
11337let mayLoad = 1;
11338let isRestrictNoSlot1Store = 1;
11339let mayStore = 1;
11340let isExtendable = 1;
11341let opExtendable = 1;
11342let isExtentSigned = 0;
11343let opExtentBits = 8;
11344let opExtentAlign = 2;
11345}
11346def L4_and_memopw_zomap : HInst<
11347(outs),
11348(ins IntRegs:$Rs32, IntRegs:$Rt32),
11349"memw($Rs32) &= $Rt32",
11350tc_7186d325, TypeMAPPING> {
11351let isPseudo = 1;
11352let isCodeGenOnly = 1;
11353}
11354def L4_iadd_memopb_io : HInst<
11355(outs),
11356(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11357"memb($Rs32+#$Ii) += #$II",
11358tc_096199d3, TypeV4LDST>, Enc_46c951 {
11359let Inst{6-5} = 0b00;
11360let Inst{13-13} = 0b0;
11361let Inst{31-21} = 0b00111111000;
11362let addrMode = BaseImmOffset;
11363let accessSize = ByteAccess;
11364let mayLoad = 1;
11365let isRestrictNoSlot1Store = 1;
11366let mayStore = 1;
11367let isExtendable = 1;
11368let opExtendable = 1;
11369let isExtentSigned = 0;
11370let opExtentBits = 6;
11371let opExtentAlign = 0;
11372}
11373def L4_iadd_memopb_zomap : HInst<
11374(outs),
11375(ins IntRegs:$Rs32, u5_0Imm:$II),
11376"memb($Rs32) += #$II",
11377tc_096199d3, TypeMAPPING> {
11378let isPseudo = 1;
11379let isCodeGenOnly = 1;
11380}
11381def L4_iadd_memoph_io : HInst<
11382(outs),
11383(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11384"memh($Rs32+#$Ii) += #$II",
11385tc_096199d3, TypeV4LDST>, Enc_e66a97 {
11386let Inst{6-5} = 0b00;
11387let Inst{13-13} = 0b0;
11388let Inst{31-21} = 0b00111111001;
11389let addrMode = BaseImmOffset;
11390let accessSize = HalfWordAccess;
11391let mayLoad = 1;
11392let isRestrictNoSlot1Store = 1;
11393let mayStore = 1;
11394let isExtendable = 1;
11395let opExtendable = 1;
11396let isExtentSigned = 0;
11397let opExtentBits = 7;
11398let opExtentAlign = 1;
11399}
11400def L4_iadd_memoph_zomap : HInst<
11401(outs),
11402(ins IntRegs:$Rs32, u5_0Imm:$II),
11403"memh($Rs32) += #$II",
11404tc_096199d3, TypeMAPPING> {
11405let isPseudo = 1;
11406let isCodeGenOnly = 1;
11407}
11408def L4_iadd_memopw_io : HInst<
11409(outs),
11410(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11411"memw($Rs32+#$Ii) += #$II",
11412tc_096199d3, TypeV4LDST>, Enc_84b2cd {
11413let Inst{6-5} = 0b00;
11414let Inst{13-13} = 0b0;
11415let Inst{31-21} = 0b00111111010;
11416let addrMode = BaseImmOffset;
11417let accessSize = WordAccess;
11418let mayLoad = 1;
11419let isRestrictNoSlot1Store = 1;
11420let mayStore = 1;
11421let isExtendable = 1;
11422let opExtendable = 1;
11423let isExtentSigned = 0;
11424let opExtentBits = 8;
11425let opExtentAlign = 2;
11426}
11427def L4_iadd_memopw_zomap : HInst<
11428(outs),
11429(ins IntRegs:$Rs32, u5_0Imm:$II),
11430"memw($Rs32) += #$II",
11431tc_096199d3, TypeMAPPING> {
11432let isPseudo = 1;
11433let isCodeGenOnly = 1;
11434}
11435def L4_iand_memopb_io : HInst<
11436(outs),
11437(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11438"memb($Rs32+#$Ii) = clrbit(#$II)",
11439tc_096199d3, TypeV4LDST>, Enc_46c951 {
11440let Inst{6-5} = 0b10;
11441let Inst{13-13} = 0b0;
11442let Inst{31-21} = 0b00111111000;
11443let addrMode = BaseImmOffset;
11444let accessSize = ByteAccess;
11445let mayLoad = 1;
11446let isRestrictNoSlot1Store = 1;
11447let mayStore = 1;
11448let isExtendable = 1;
11449let opExtendable = 1;
11450let isExtentSigned = 0;
11451let opExtentBits = 6;
11452let opExtentAlign = 0;
11453}
11454def L4_iand_memopb_zomap : HInst<
11455(outs),
11456(ins IntRegs:$Rs32, u5_0Imm:$II),
11457"memb($Rs32) = clrbit(#$II)",
11458tc_096199d3, TypeMAPPING> {
11459let isPseudo = 1;
11460let isCodeGenOnly = 1;
11461}
11462def L4_iand_memoph_io : HInst<
11463(outs),
11464(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11465"memh($Rs32+#$Ii) = clrbit(#$II)",
11466tc_096199d3, TypeV4LDST>, Enc_e66a97 {
11467let Inst{6-5} = 0b10;
11468let Inst{13-13} = 0b0;
11469let Inst{31-21} = 0b00111111001;
11470let addrMode = BaseImmOffset;
11471let accessSize = HalfWordAccess;
11472let mayLoad = 1;
11473let isRestrictNoSlot1Store = 1;
11474let mayStore = 1;
11475let isExtendable = 1;
11476let opExtendable = 1;
11477let isExtentSigned = 0;
11478let opExtentBits = 7;
11479let opExtentAlign = 1;
11480}
11481def L4_iand_memoph_zomap : HInst<
11482(outs),
11483(ins IntRegs:$Rs32, u5_0Imm:$II),
11484"memh($Rs32) = clrbit(#$II)",
11485tc_096199d3, TypeMAPPING> {
11486let isPseudo = 1;
11487let isCodeGenOnly = 1;
11488}
11489def L4_iand_memopw_io : HInst<
11490(outs),
11491(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11492"memw($Rs32+#$Ii) = clrbit(#$II)",
11493tc_096199d3, TypeV4LDST>, Enc_84b2cd {
11494let Inst{6-5} = 0b10;
11495let Inst{13-13} = 0b0;
11496let Inst{31-21} = 0b00111111010;
11497let addrMode = BaseImmOffset;
11498let accessSize = WordAccess;
11499let mayLoad = 1;
11500let isRestrictNoSlot1Store = 1;
11501let mayStore = 1;
11502let isExtendable = 1;
11503let opExtendable = 1;
11504let isExtentSigned = 0;
11505let opExtentBits = 8;
11506let opExtentAlign = 2;
11507}
11508def L4_iand_memopw_zomap : HInst<
11509(outs),
11510(ins IntRegs:$Rs32, u5_0Imm:$II),
11511"memw($Rs32) = clrbit(#$II)",
11512tc_096199d3, TypeMAPPING> {
11513let isPseudo = 1;
11514let isCodeGenOnly = 1;
11515}
11516def L4_ior_memopb_io : HInst<
11517(outs),
11518(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11519"memb($Rs32+#$Ii) = setbit(#$II)",
11520tc_096199d3, TypeV4LDST>, Enc_46c951 {
11521let Inst{6-5} = 0b11;
11522let Inst{13-13} = 0b0;
11523let Inst{31-21} = 0b00111111000;
11524let addrMode = BaseImmOffset;
11525let accessSize = ByteAccess;
11526let mayLoad = 1;
11527let isRestrictNoSlot1Store = 1;
11528let mayStore = 1;
11529let isExtendable = 1;
11530let opExtendable = 1;
11531let isExtentSigned = 0;
11532let opExtentBits = 6;
11533let opExtentAlign = 0;
11534}
11535def L4_ior_memopb_zomap : HInst<
11536(outs),
11537(ins IntRegs:$Rs32, u5_0Imm:$II),
11538"memb($Rs32) = setbit(#$II)",
11539tc_096199d3, TypeMAPPING> {
11540let isPseudo = 1;
11541let isCodeGenOnly = 1;
11542}
11543def L4_ior_memoph_io : HInst<
11544(outs),
11545(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11546"memh($Rs32+#$Ii) = setbit(#$II)",
11547tc_096199d3, TypeV4LDST>, Enc_e66a97 {
11548let Inst{6-5} = 0b11;
11549let Inst{13-13} = 0b0;
11550let Inst{31-21} = 0b00111111001;
11551let addrMode = BaseImmOffset;
11552let accessSize = HalfWordAccess;
11553let mayLoad = 1;
11554let isRestrictNoSlot1Store = 1;
11555let mayStore = 1;
11556let isExtendable = 1;
11557let opExtendable = 1;
11558let isExtentSigned = 0;
11559let opExtentBits = 7;
11560let opExtentAlign = 1;
11561}
11562def L4_ior_memoph_zomap : HInst<
11563(outs),
11564(ins IntRegs:$Rs32, u5_0Imm:$II),
11565"memh($Rs32) = setbit(#$II)",
11566tc_096199d3, TypeMAPPING> {
11567let isPseudo = 1;
11568let isCodeGenOnly = 1;
11569}
11570def L4_ior_memopw_io : HInst<
11571(outs),
11572(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11573"memw($Rs32+#$Ii) = setbit(#$II)",
11574tc_096199d3, TypeV4LDST>, Enc_84b2cd {
11575let Inst{6-5} = 0b11;
11576let Inst{13-13} = 0b0;
11577let Inst{31-21} = 0b00111111010;
11578let addrMode = BaseImmOffset;
11579let accessSize = WordAccess;
11580let mayLoad = 1;
11581let isRestrictNoSlot1Store = 1;
11582let mayStore = 1;
11583let isExtendable = 1;
11584let opExtendable = 1;
11585let isExtentSigned = 0;
11586let opExtentBits = 8;
11587let opExtentAlign = 2;
11588}
11589def L4_ior_memopw_zomap : HInst<
11590(outs),
11591(ins IntRegs:$Rs32, u5_0Imm:$II),
11592"memw($Rs32) = setbit(#$II)",
11593tc_096199d3, TypeMAPPING> {
11594let isPseudo = 1;
11595let isCodeGenOnly = 1;
11596}
11597def L4_isub_memopb_io : HInst<
11598(outs),
11599(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11600"memb($Rs32+#$Ii) -= #$II",
11601tc_096199d3, TypeV4LDST>, Enc_46c951 {
11602let Inst{6-5} = 0b01;
11603let Inst{13-13} = 0b0;
11604let Inst{31-21} = 0b00111111000;
11605let addrMode = BaseImmOffset;
11606let accessSize = ByteAccess;
11607let mayLoad = 1;
11608let isRestrictNoSlot1Store = 1;
11609let mayStore = 1;
11610let isExtendable = 1;
11611let opExtendable = 1;
11612let isExtentSigned = 0;
11613let opExtentBits = 6;
11614let opExtentAlign = 0;
11615}
11616def L4_isub_memopb_zomap : HInst<
11617(outs),
11618(ins IntRegs:$Rs32, u5_0Imm:$II),
11619"memb($Rs32) -= #$II",
11620tc_096199d3, TypeMAPPING> {
11621let isPseudo = 1;
11622let isCodeGenOnly = 1;
11623}
11624def L4_isub_memoph_io : HInst<
11625(outs),
11626(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11627"memh($Rs32+#$Ii) -= #$II",
11628tc_096199d3, TypeV4LDST>, Enc_e66a97 {
11629let Inst{6-5} = 0b01;
11630let Inst{13-13} = 0b0;
11631let Inst{31-21} = 0b00111111001;
11632let addrMode = BaseImmOffset;
11633let accessSize = HalfWordAccess;
11634let mayLoad = 1;
11635let isRestrictNoSlot1Store = 1;
11636let mayStore = 1;
11637let isExtendable = 1;
11638let opExtendable = 1;
11639let isExtentSigned = 0;
11640let opExtentBits = 7;
11641let opExtentAlign = 1;
11642}
11643def L4_isub_memoph_zomap : HInst<
11644(outs),
11645(ins IntRegs:$Rs32, u5_0Imm:$II),
11646"memh($Rs32) -= #$II",
11647tc_096199d3, TypeMAPPING> {
11648let isPseudo = 1;
11649let isCodeGenOnly = 1;
11650}
11651def L4_isub_memopw_io : HInst<
11652(outs),
11653(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11654"memw($Rs32+#$Ii) -= #$II",
11655tc_096199d3, TypeV4LDST>, Enc_84b2cd {
11656let Inst{6-5} = 0b01;
11657let Inst{13-13} = 0b0;
11658let Inst{31-21} = 0b00111111010;
11659let addrMode = BaseImmOffset;
11660let accessSize = WordAccess;
11661let mayLoad = 1;
11662let isRestrictNoSlot1Store = 1;
11663let mayStore = 1;
11664let isExtendable = 1;
11665let opExtendable = 1;
11666let isExtentSigned = 0;
11667let opExtentBits = 8;
11668let opExtentAlign = 2;
11669}
11670def L4_isub_memopw_zomap : HInst<
11671(outs),
11672(ins IntRegs:$Rs32, u5_0Imm:$II),
11673"memw($Rs32) -= #$II",
11674tc_096199d3, TypeMAPPING> {
11675let isPseudo = 1;
11676let isCodeGenOnly = 1;
11677}
11678def L4_loadalignb_ap : HInst<
11679(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11680(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11681"$Ryy32 = memb_fifo($Re32=#$II)",
11682tc_7a91e76a, TypeLD>, Enc_f394d3 {
11683let Inst{7-7} = 0b0;
11684let Inst{13-12} = 0b01;
11685let Inst{31-21} = 0b10011010100;
11686let addrMode = AbsoluteSet;
11687let accessSize = ByteAccess;
11688let mayLoad = 1;
11689let isExtended = 1;
11690let DecoderNamespace = "MustExtend";
11691let isExtendable = 1;
11692let opExtendable = 3;
11693let isExtentSigned = 0;
11694let opExtentBits = 6;
11695let opExtentAlign = 0;
11696let Constraints = "$Ryy32 = $Ryy32in";
11697}
11698def L4_loadalignb_ur : HInst<
11699(outs DoubleRegs:$Ryy32),
11700(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11701"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
11702tc_a5d4aeec, TypeLD>, Enc_04c959 {
11703let Inst{12-12} = 0b1;
11704let Inst{31-21} = 0b10011100100;
11705let addrMode = BaseLongOffset;
11706let accessSize = ByteAccess;
11707let mayLoad = 1;
11708let isExtended = 1;
11709let InputType = "imm";
11710let DecoderNamespace = "MustExtend";
11711let isExtendable = 1;
11712let opExtendable = 4;
11713let isExtentSigned = 0;
11714let opExtentBits = 6;
11715let opExtentAlign = 0;
11716let Constraints = "$Ryy32 = $Ryy32in";
11717}
11718def L4_loadalignh_ap : HInst<
11719(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11720(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11721"$Ryy32 = memh_fifo($Re32=#$II)",
11722tc_7a91e76a, TypeLD>, Enc_f394d3 {
11723let Inst{7-7} = 0b0;
11724let Inst{13-12} = 0b01;
11725let Inst{31-21} = 0b10011010010;
11726let addrMode = AbsoluteSet;
11727let accessSize = HalfWordAccess;
11728let mayLoad = 1;
11729let isExtended = 1;
11730let DecoderNamespace = "MustExtend";
11731let isExtendable = 1;
11732let opExtendable = 3;
11733let isExtentSigned = 0;
11734let opExtentBits = 6;
11735let opExtentAlign = 0;
11736let Constraints = "$Ryy32 = $Ryy32in";
11737}
11738def L4_loadalignh_ur : HInst<
11739(outs DoubleRegs:$Ryy32),
11740(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11741"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
11742tc_a5d4aeec, TypeLD>, Enc_04c959 {
11743let Inst{12-12} = 0b1;
11744let Inst{31-21} = 0b10011100010;
11745let addrMode = BaseLongOffset;
11746let accessSize = HalfWordAccess;
11747let mayLoad = 1;
11748let isExtended = 1;
11749let InputType = "imm";
11750let DecoderNamespace = "MustExtend";
11751let isExtendable = 1;
11752let opExtendable = 4;
11753let isExtentSigned = 0;
11754let opExtentBits = 6;
11755let opExtentAlign = 0;
11756let Constraints = "$Ryy32 = $Ryy32in";
11757}
11758def L4_loadbsw2_ap : HInst<
11759(outs IntRegs:$Rd32, IntRegs:$Re32),
11760(ins u32_0Imm:$II),
11761"$Rd32 = membh($Re32=#$II)",
11762tc_3b5b7ef9, TypeLD>, Enc_323f2d {
11763let Inst{7-7} = 0b0;
11764let Inst{13-12} = 0b01;
11765let Inst{31-21} = 0b10011010001;
11766let hasNewValue = 1;
11767let opNewValue = 0;
11768let addrMode = AbsoluteSet;
11769let accessSize = HalfWordAccess;
11770let mayLoad = 1;
11771let isExtended = 1;
11772let DecoderNamespace = "MustExtend";
11773let isExtendable = 1;
11774let opExtendable = 2;
11775let isExtentSigned = 0;
11776let opExtentBits = 6;
11777let opExtentAlign = 0;
11778}
11779def L4_loadbsw2_ur : HInst<
11780(outs IntRegs:$Rd32),
11781(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11782"$Rd32 = membh($Rt32<<#$Ii+#$II)",
11783tc_bab0eed9, TypeLD>, Enc_4f677b {
11784let Inst{12-12} = 0b1;
11785let Inst{31-21} = 0b10011100001;
11786let hasNewValue = 1;
11787let opNewValue = 0;
11788let addrMode = BaseLongOffset;
11789let accessSize = HalfWordAccess;
11790let mayLoad = 1;
11791let isExtended = 1;
11792let InputType = "imm";
11793let DecoderNamespace = "MustExtend";
11794let isExtendable = 1;
11795let opExtendable = 3;
11796let isExtentSigned = 0;
11797let opExtentBits = 6;
11798let opExtentAlign = 0;
11799}
11800def L4_loadbsw4_ap : HInst<
11801(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11802(ins u32_0Imm:$II),
11803"$Rdd32 = membh($Re32=#$II)",
11804tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 {
11805let Inst{7-7} = 0b0;
11806let Inst{13-12} = 0b01;
11807let Inst{31-21} = 0b10011010111;
11808let addrMode = AbsoluteSet;
11809let accessSize = WordAccess;
11810let mayLoad = 1;
11811let isExtended = 1;
11812let DecoderNamespace = "MustExtend";
11813let isExtendable = 1;
11814let opExtendable = 2;
11815let isExtentSigned = 0;
11816let opExtentBits = 6;
11817let opExtentAlign = 0;
11818}
11819def L4_loadbsw4_ur : HInst<
11820(outs DoubleRegs:$Rdd32),
11821(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11822"$Rdd32 = membh($Rt32<<#$Ii+#$II)",
11823tc_bab0eed9, TypeLD>, Enc_6185fe {
11824let Inst{12-12} = 0b1;
11825let Inst{31-21} = 0b10011100111;
11826let addrMode = BaseLongOffset;
11827let accessSize = WordAccess;
11828let mayLoad = 1;
11829let isExtended = 1;
11830let InputType = "imm";
11831let DecoderNamespace = "MustExtend";
11832let isExtendable = 1;
11833let opExtendable = 3;
11834let isExtentSigned = 0;
11835let opExtentBits = 6;
11836let opExtentAlign = 0;
11837}
11838def L4_loadbzw2_ap : HInst<
11839(outs IntRegs:$Rd32, IntRegs:$Re32),
11840(ins u32_0Imm:$II),
11841"$Rd32 = memubh($Re32=#$II)",
11842tc_3b5b7ef9, TypeLD>, Enc_323f2d {
11843let Inst{7-7} = 0b0;
11844let Inst{13-12} = 0b01;
11845let Inst{31-21} = 0b10011010011;
11846let hasNewValue = 1;
11847let opNewValue = 0;
11848let addrMode = AbsoluteSet;
11849let accessSize = HalfWordAccess;
11850let mayLoad = 1;
11851let isExtended = 1;
11852let DecoderNamespace = "MustExtend";
11853let isExtendable = 1;
11854let opExtendable = 2;
11855let isExtentSigned = 0;
11856let opExtentBits = 6;
11857let opExtentAlign = 0;
11858}
11859def L4_loadbzw2_ur : HInst<
11860(outs IntRegs:$Rd32),
11861(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11862"$Rd32 = memubh($Rt32<<#$Ii+#$II)",
11863tc_bab0eed9, TypeLD>, Enc_4f677b {
11864let Inst{12-12} = 0b1;
11865let Inst{31-21} = 0b10011100011;
11866let hasNewValue = 1;
11867let opNewValue = 0;
11868let addrMode = BaseLongOffset;
11869let accessSize = HalfWordAccess;
11870let mayLoad = 1;
11871let isExtended = 1;
11872let InputType = "imm";
11873let DecoderNamespace = "MustExtend";
11874let isExtendable = 1;
11875let opExtendable = 3;
11876let isExtentSigned = 0;
11877let opExtentBits = 6;
11878let opExtentAlign = 0;
11879}
11880def L4_loadbzw4_ap : HInst<
11881(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11882(ins u32_0Imm:$II),
11883"$Rdd32 = memubh($Re32=#$II)",
11884tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 {
11885let Inst{7-7} = 0b0;
11886let Inst{13-12} = 0b01;
11887let Inst{31-21} = 0b10011010101;
11888let addrMode = AbsoluteSet;
11889let accessSize = WordAccess;
11890let mayLoad = 1;
11891let isExtended = 1;
11892let DecoderNamespace = "MustExtend";
11893let isExtendable = 1;
11894let opExtendable = 2;
11895let isExtentSigned = 0;
11896let opExtentBits = 6;
11897let opExtentAlign = 0;
11898}
11899def L4_loadbzw4_ur : HInst<
11900(outs DoubleRegs:$Rdd32),
11901(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11902"$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
11903tc_bab0eed9, TypeLD>, Enc_6185fe {
11904let Inst{12-12} = 0b1;
11905let Inst{31-21} = 0b10011100101;
11906let addrMode = BaseLongOffset;
11907let accessSize = WordAccess;
11908let mayLoad = 1;
11909let isExtended = 1;
11910let InputType = "imm";
11911let DecoderNamespace = "MustExtend";
11912let isExtendable = 1;
11913let opExtendable = 3;
11914let isExtentSigned = 0;
11915let opExtentBits = 6;
11916let opExtentAlign = 0;
11917}
11918def L4_loadd_locked : HInst<
11919(outs DoubleRegs:$Rdd32),
11920(ins IntRegs:$Rs32),
11921"$Rdd32 = memd_locked($Rs32)",
11922tc_b43e7930, TypeLD>, Enc_3a3d62 {
11923let Inst{13-5} = 0b010000000;
11924let Inst{31-21} = 0b10010010000;
11925let accessSize = DoubleWordAccess;
11926let mayLoad = 1;
11927let isSoloAX = 1;
11928}
11929def L4_loadrb_ap : HInst<
11930(outs IntRegs:$Rd32, IntRegs:$Re32),
11931(ins u32_0Imm:$II),
11932"$Rd32 = memb($Re32=#$II)",
11933tc_3b5b7ef9, TypeLD>, Enc_323f2d {
11934let Inst{7-7} = 0b0;
11935let Inst{13-12} = 0b01;
11936let Inst{31-21} = 0b10011011000;
11937let hasNewValue = 1;
11938let opNewValue = 0;
11939let addrMode = AbsoluteSet;
11940let accessSize = ByteAccess;
11941let mayLoad = 1;
11942let isExtended = 1;
11943let DecoderNamespace = "MustExtend";
11944let isExtendable = 1;
11945let opExtendable = 2;
11946let isExtentSigned = 0;
11947let opExtentBits = 6;
11948let opExtentAlign = 0;
11949}
11950def L4_loadrb_rr : HInst<
11951(outs IntRegs:$Rd32),
11952(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
11953"$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
11954tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
11955let Inst{6-5} = 0b00;
11956let Inst{31-21} = 0b00111010000;
11957let hasNewValue = 1;
11958let opNewValue = 0;
11959let addrMode = BaseRegOffset;
11960let accessSize = ByteAccess;
11961let mayLoad = 1;
11962let CextOpcode = "L2_loadrb";
11963let InputType = "reg";
11964let BaseOpcode = "L4_loadrb_rr";
11965let isPredicable = 1;
11966}
11967def L4_loadrb_ur : HInst<
11968(outs IntRegs:$Rd32),
11969(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11970"$Rd32 = memb($Rt32<<#$Ii+#$II)",
11971tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
11972let Inst{12-12} = 0b1;
11973let Inst{31-21} = 0b10011101000;
11974let hasNewValue = 1;
11975let opNewValue = 0;
11976let addrMode = BaseLongOffset;
11977let accessSize = ByteAccess;
11978let mayLoad = 1;
11979let isExtended = 1;
11980let CextOpcode = "L2_loadrb";
11981let InputType = "imm";
11982let DecoderNamespace = "MustExtend";
11983let isExtendable = 1;
11984let opExtendable = 3;
11985let isExtentSigned = 0;
11986let opExtentBits = 6;
11987let opExtentAlign = 0;
11988}
11989def L4_loadrd_ap : HInst<
11990(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11991(ins u32_0Imm:$II),
11992"$Rdd32 = memd($Re32=#$II)",
11993tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 {
11994let Inst{7-7} = 0b0;
11995let Inst{13-12} = 0b01;
11996let Inst{31-21} = 0b10011011110;
11997let addrMode = AbsoluteSet;
11998let accessSize = DoubleWordAccess;
11999let mayLoad = 1;
12000let isExtended = 1;
12001let DecoderNamespace = "MustExtend";
12002let isExtendable = 1;
12003let opExtendable = 2;
12004let isExtentSigned = 0;
12005let opExtentBits = 6;
12006let opExtentAlign = 0;
12007}
12008def L4_loadrd_rr : HInst<
12009(outs DoubleRegs:$Rdd32),
12010(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12011"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12012tc_bf061958, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
12013let Inst{6-5} = 0b00;
12014let Inst{31-21} = 0b00111010110;
12015let addrMode = BaseRegOffset;
12016let accessSize = DoubleWordAccess;
12017let mayLoad = 1;
12018let CextOpcode = "L2_loadrd";
12019let InputType = "reg";
12020let BaseOpcode = "L4_loadrd_rr";
12021let isPredicable = 1;
12022}
12023def L4_loadrd_ur : HInst<
12024(outs DoubleRegs:$Rdd32),
12025(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12026"$Rdd32 = memd($Rt32<<#$Ii+#$II)",
12027tc_bab0eed9, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
12028let Inst{12-12} = 0b1;
12029let Inst{31-21} = 0b10011101110;
12030let addrMode = BaseLongOffset;
12031let accessSize = DoubleWordAccess;
12032let mayLoad = 1;
12033let isExtended = 1;
12034let CextOpcode = "L2_loadrd";
12035let InputType = "imm";
12036let DecoderNamespace = "MustExtend";
12037let isExtendable = 1;
12038let opExtendable = 3;
12039let isExtentSigned = 0;
12040let opExtentBits = 6;
12041let opExtentAlign = 0;
12042}
12043def L4_loadrh_ap : HInst<
12044(outs IntRegs:$Rd32, IntRegs:$Re32),
12045(ins u32_0Imm:$II),
12046"$Rd32 = memh($Re32=#$II)",
12047tc_3b5b7ef9, TypeLD>, Enc_323f2d {
12048let Inst{7-7} = 0b0;
12049let Inst{13-12} = 0b01;
12050let Inst{31-21} = 0b10011011010;
12051let hasNewValue = 1;
12052let opNewValue = 0;
12053let addrMode = AbsoluteSet;
12054let accessSize = HalfWordAccess;
12055let mayLoad = 1;
12056let isExtended = 1;
12057let DecoderNamespace = "MustExtend";
12058let isExtendable = 1;
12059let opExtendable = 2;
12060let isExtentSigned = 0;
12061let opExtentBits = 6;
12062let opExtentAlign = 0;
12063}
12064def L4_loadrh_rr : HInst<
12065(outs IntRegs:$Rd32),
12066(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12067"$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12068tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12069let Inst{6-5} = 0b00;
12070let Inst{31-21} = 0b00111010010;
12071let hasNewValue = 1;
12072let opNewValue = 0;
12073let addrMode = BaseRegOffset;
12074let accessSize = HalfWordAccess;
12075let mayLoad = 1;
12076let CextOpcode = "L2_loadrh";
12077let InputType = "reg";
12078let BaseOpcode = "L4_loadrh_rr";
12079let isPredicable = 1;
12080}
12081def L4_loadrh_ur : HInst<
12082(outs IntRegs:$Rd32),
12083(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12084"$Rd32 = memh($Rt32<<#$Ii+#$II)",
12085tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12086let Inst{12-12} = 0b1;
12087let Inst{31-21} = 0b10011101010;
12088let hasNewValue = 1;
12089let opNewValue = 0;
12090let addrMode = BaseLongOffset;
12091let accessSize = HalfWordAccess;
12092let mayLoad = 1;
12093let isExtended = 1;
12094let CextOpcode = "L2_loadrh";
12095let InputType = "imm";
12096let DecoderNamespace = "MustExtend";
12097let isExtendable = 1;
12098let opExtendable = 3;
12099let isExtentSigned = 0;
12100let opExtentBits = 6;
12101let opExtentAlign = 0;
12102}
12103def L4_loadri_ap : HInst<
12104(outs IntRegs:$Rd32, IntRegs:$Re32),
12105(ins u32_0Imm:$II),
12106"$Rd32 = memw($Re32=#$II)",
12107tc_3b5b7ef9, TypeLD>, Enc_323f2d {
12108let Inst{7-7} = 0b0;
12109let Inst{13-12} = 0b01;
12110let Inst{31-21} = 0b10011011100;
12111let hasNewValue = 1;
12112let opNewValue = 0;
12113let addrMode = AbsoluteSet;
12114let accessSize = WordAccess;
12115let mayLoad = 1;
12116let isExtended = 1;
12117let DecoderNamespace = "MustExtend";
12118let isExtendable = 1;
12119let opExtendable = 2;
12120let isExtentSigned = 0;
12121let opExtentBits = 6;
12122let opExtentAlign = 0;
12123}
12124def L4_loadri_rr : HInst<
12125(outs IntRegs:$Rd32),
12126(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12127"$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12128tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12129let Inst{6-5} = 0b00;
12130let Inst{31-21} = 0b00111010100;
12131let hasNewValue = 1;
12132let opNewValue = 0;
12133let addrMode = BaseRegOffset;
12134let accessSize = WordAccess;
12135let mayLoad = 1;
12136let CextOpcode = "L2_loadri";
12137let InputType = "reg";
12138let BaseOpcode = "L4_loadri_rr";
12139let isPredicable = 1;
12140}
12141def L4_loadri_ur : HInst<
12142(outs IntRegs:$Rd32),
12143(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12144"$Rd32 = memw($Rt32<<#$Ii+#$II)",
12145tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12146let Inst{12-12} = 0b1;
12147let Inst{31-21} = 0b10011101100;
12148let hasNewValue = 1;
12149let opNewValue = 0;
12150let addrMode = BaseLongOffset;
12151let accessSize = WordAccess;
12152let mayLoad = 1;
12153let isExtended = 1;
12154let CextOpcode = "L2_loadri";
12155let InputType = "imm";
12156let DecoderNamespace = "MustExtend";
12157let isExtendable = 1;
12158let opExtendable = 3;
12159let isExtentSigned = 0;
12160let opExtentBits = 6;
12161let opExtentAlign = 0;
12162}
12163def L4_loadrub_ap : HInst<
12164(outs IntRegs:$Rd32, IntRegs:$Re32),
12165(ins u32_0Imm:$II),
12166"$Rd32 = memub($Re32=#$II)",
12167tc_3b5b7ef9, TypeLD>, Enc_323f2d {
12168let Inst{7-7} = 0b0;
12169let Inst{13-12} = 0b01;
12170let Inst{31-21} = 0b10011011001;
12171let hasNewValue = 1;
12172let opNewValue = 0;
12173let addrMode = AbsoluteSet;
12174let accessSize = ByteAccess;
12175let mayLoad = 1;
12176let isExtended = 1;
12177let DecoderNamespace = "MustExtend";
12178let isExtendable = 1;
12179let opExtendable = 2;
12180let isExtentSigned = 0;
12181let opExtentBits = 6;
12182let opExtentAlign = 0;
12183}
12184def L4_loadrub_rr : HInst<
12185(outs IntRegs:$Rd32),
12186(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12187"$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12188tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12189let Inst{6-5} = 0b00;
12190let Inst{31-21} = 0b00111010001;
12191let hasNewValue = 1;
12192let opNewValue = 0;
12193let addrMode = BaseRegOffset;
12194let accessSize = ByteAccess;
12195let mayLoad = 1;
12196let CextOpcode = "L2_loadrub";
12197let InputType = "reg";
12198let BaseOpcode = "L4_loadrub_rr";
12199let isPredicable = 1;
12200}
12201def L4_loadrub_ur : HInst<
12202(outs IntRegs:$Rd32),
12203(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12204"$Rd32 = memub($Rt32<<#$Ii+#$II)",
12205tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12206let Inst{12-12} = 0b1;
12207let Inst{31-21} = 0b10011101001;
12208let hasNewValue = 1;
12209let opNewValue = 0;
12210let addrMode = BaseLongOffset;
12211let accessSize = ByteAccess;
12212let mayLoad = 1;
12213let isExtended = 1;
12214let CextOpcode = "L2_loadrub";
12215let InputType = "imm";
12216let DecoderNamespace = "MustExtend";
12217let isExtendable = 1;
12218let opExtendable = 3;
12219let isExtentSigned = 0;
12220let opExtentBits = 6;
12221let opExtentAlign = 0;
12222}
12223def L4_loadruh_ap : HInst<
12224(outs IntRegs:$Rd32, IntRegs:$Re32),
12225(ins u32_0Imm:$II),
12226"$Rd32 = memuh($Re32=#$II)",
12227tc_3b5b7ef9, TypeLD>, Enc_323f2d {
12228let Inst{7-7} = 0b0;
12229let Inst{13-12} = 0b01;
12230let Inst{31-21} = 0b10011011011;
12231let hasNewValue = 1;
12232let opNewValue = 0;
12233let addrMode = AbsoluteSet;
12234let accessSize = HalfWordAccess;
12235let mayLoad = 1;
12236let isExtended = 1;
12237let DecoderNamespace = "MustExtend";
12238let isExtendable = 1;
12239let opExtendable = 2;
12240let isExtentSigned = 0;
12241let opExtentBits = 6;
12242let opExtentAlign = 0;
12243}
12244def L4_loadruh_rr : HInst<
12245(outs IntRegs:$Rd32),
12246(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12247"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
12248tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12249let Inst{6-5} = 0b00;
12250let Inst{31-21} = 0b00111010011;
12251let hasNewValue = 1;
12252let opNewValue = 0;
12253let addrMode = BaseRegOffset;
12254let accessSize = HalfWordAccess;
12255let mayLoad = 1;
12256let CextOpcode = "L2_loadruh";
12257let InputType = "reg";
12258let BaseOpcode = "L4_loadruh_rr";
12259let isPredicable = 1;
12260}
12261def L4_loadruh_ur : HInst<
12262(outs IntRegs:$Rd32),
12263(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12264"$Rd32 = memuh($Rt32<<#$Ii+#$II)",
12265tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12266let Inst{12-12} = 0b1;
12267let Inst{31-21} = 0b10011101011;
12268let hasNewValue = 1;
12269let opNewValue = 0;
12270let addrMode = BaseLongOffset;
12271let accessSize = HalfWordAccess;
12272let mayLoad = 1;
12273let isExtended = 1;
12274let CextOpcode = "L2_loadruh";
12275let InputType = "imm";
12276let DecoderNamespace = "MustExtend";
12277let isExtendable = 1;
12278let opExtendable = 3;
12279let isExtentSigned = 0;
12280let opExtentBits = 6;
12281let opExtentAlign = 0;
12282}
12283def L4_or_memopb_io : HInst<
12284(outs),
12285(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
12286"memb($Rs32+#$Ii) |= $Rt32",
12287tc_7186d325, TypeV4LDST>, Enc_d44e31 {
12288let Inst{6-5} = 0b11;
12289let Inst{13-13} = 0b0;
12290let Inst{31-21} = 0b00111110000;
12291let addrMode = BaseImmOffset;
12292let accessSize = ByteAccess;
12293let mayLoad = 1;
12294let isRestrictNoSlot1Store = 1;
12295let mayStore = 1;
12296let isExtendable = 1;
12297let opExtendable = 1;
12298let isExtentSigned = 0;
12299let opExtentBits = 6;
12300let opExtentAlign = 0;
12301}
12302def L4_or_memopb_zomap : HInst<
12303(outs),
12304(ins IntRegs:$Rs32, IntRegs:$Rt32),
12305"memb($Rs32) |= $Rt32",
12306tc_7186d325, TypeMAPPING> {
12307let isPseudo = 1;
12308let isCodeGenOnly = 1;
12309}
12310def L4_or_memoph_io : HInst<
12311(outs),
12312(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
12313"memh($Rs32+#$Ii) |= $Rt32",
12314tc_7186d325, TypeV4LDST>, Enc_163a3c {
12315let Inst{6-5} = 0b11;
12316let Inst{13-13} = 0b0;
12317let Inst{31-21} = 0b00111110001;
12318let addrMode = BaseImmOffset;
12319let accessSize = HalfWordAccess;
12320let mayLoad = 1;
12321let isRestrictNoSlot1Store = 1;
12322let mayStore = 1;
12323let isExtendable = 1;
12324let opExtendable = 1;
12325let isExtentSigned = 0;
12326let opExtentBits = 7;
12327let opExtentAlign = 1;
12328}
12329def L4_or_memoph_zomap : HInst<
12330(outs),
12331(ins IntRegs:$Rs32, IntRegs:$Rt32),
12332"memh($Rs32) |= $Rt32",
12333tc_7186d325, TypeMAPPING> {
12334let isPseudo = 1;
12335let isCodeGenOnly = 1;
12336}
12337def L4_or_memopw_io : HInst<
12338(outs),
12339(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
12340"memw($Rs32+#$Ii) |= $Rt32",
12341tc_7186d325, TypeV4LDST>, Enc_226535 {
12342let Inst{6-5} = 0b11;
12343let Inst{13-13} = 0b0;
12344let Inst{31-21} = 0b00111110010;
12345let addrMode = BaseImmOffset;
12346let accessSize = WordAccess;
12347let mayLoad = 1;
12348let isRestrictNoSlot1Store = 1;
12349let mayStore = 1;
12350let isExtendable = 1;
12351let opExtendable = 1;
12352let isExtentSigned = 0;
12353let opExtentBits = 8;
12354let opExtentAlign = 2;
12355}
12356def L4_or_memopw_zomap : HInst<
12357(outs),
12358(ins IntRegs:$Rs32, IntRegs:$Rt32),
12359"memw($Rs32) |= $Rt32",
12360tc_7186d325, TypeMAPPING> {
12361let isPseudo = 1;
12362let isCodeGenOnly = 1;
12363}
12364def L4_ploadrbf_abs : HInst<
12365(outs IntRegs:$Rd32),
12366(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12367"if (!$Pt4) $Rd32 = memb(#$Ii)",
12368tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
12369let Inst{7-5} = 0b100;
12370let Inst{13-11} = 0b101;
12371let Inst{31-21} = 0b10011111000;
12372let isPredicated = 1;
12373let isPredicatedFalse = 1;
12374let hasNewValue = 1;
12375let opNewValue = 0;
12376let addrMode = Absolute;
12377let accessSize = ByteAccess;
12378let mayLoad = 1;
12379let isExtended = 1;
12380let CextOpcode = "L2_loadrb";
12381let BaseOpcode = "L4_loadrb_abs";
12382let DecoderNamespace = "MustExtend";
12383let isExtendable = 1;
12384let opExtendable = 2;
12385let isExtentSigned = 0;
12386let opExtentBits = 6;
12387let opExtentAlign = 0;
12388}
12389def L4_ploadrbf_rr : HInst<
12390(outs IntRegs:$Rd32),
12391(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12392"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12393tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
12394let Inst{31-21} = 0b00110001000;
12395let isPredicated = 1;
12396let isPredicatedFalse = 1;
12397let hasNewValue = 1;
12398let opNewValue = 0;
12399let addrMode = BaseRegOffset;
12400let accessSize = ByteAccess;
12401let mayLoad = 1;
12402let CextOpcode = "L2_loadrb";
12403let InputType = "reg";
12404let BaseOpcode = "L4_loadrb_rr";
12405}
12406def L4_ploadrbfnew_abs : HInst<
12407(outs IntRegs:$Rd32),
12408(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12409"if (!$Pt4.new) $Rd32 = memb(#$Ii)",
12410tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
12411let Inst{7-5} = 0b100;
12412let Inst{13-11} = 0b111;
12413let Inst{31-21} = 0b10011111000;
12414let isPredicated = 1;
12415let isPredicatedFalse = 1;
12416let hasNewValue = 1;
12417let opNewValue = 0;
12418let addrMode = Absolute;
12419let accessSize = ByteAccess;
12420let isPredicatedNew = 1;
12421let mayLoad = 1;
12422let isExtended = 1;
12423let CextOpcode = "L2_loadrb";
12424let BaseOpcode = "L4_loadrb_abs";
12425let DecoderNamespace = "MustExtend";
12426let isExtendable = 1;
12427let opExtendable = 2;
12428let isExtentSigned = 0;
12429let opExtentBits = 6;
12430let opExtentAlign = 0;
12431}
12432def L4_ploadrbfnew_rr : HInst<
12433(outs IntRegs:$Rd32),
12434(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12435"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12436tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
12437let Inst{31-21} = 0b00110011000;
12438let isPredicated = 1;
12439let isPredicatedFalse = 1;
12440let hasNewValue = 1;
12441let opNewValue = 0;
12442let addrMode = BaseRegOffset;
12443let accessSize = ByteAccess;
12444let isPredicatedNew = 1;
12445let mayLoad = 1;
12446let CextOpcode = "L2_loadrb";
12447let InputType = "reg";
12448let BaseOpcode = "L4_loadrb_rr";
12449}
12450def L4_ploadrbt_abs : HInst<
12451(outs IntRegs:$Rd32),
12452(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12453"if ($Pt4) $Rd32 = memb(#$Ii)",
12454tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
12455let Inst{7-5} = 0b100;
12456let Inst{13-11} = 0b100;
12457let Inst{31-21} = 0b10011111000;
12458let isPredicated = 1;
12459let hasNewValue = 1;
12460let opNewValue = 0;
12461let addrMode = Absolute;
12462let accessSize = ByteAccess;
12463let mayLoad = 1;
12464let isExtended = 1;
12465let CextOpcode = "L2_loadrb";
12466let BaseOpcode = "L4_loadrb_abs";
12467let DecoderNamespace = "MustExtend";
12468let isExtendable = 1;
12469let opExtendable = 2;
12470let isExtentSigned = 0;
12471let opExtentBits = 6;
12472let opExtentAlign = 0;
12473}
12474def L4_ploadrbt_rr : HInst<
12475(outs IntRegs:$Rd32),
12476(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12477"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12478tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
12479let Inst{31-21} = 0b00110000000;
12480let isPredicated = 1;
12481let hasNewValue = 1;
12482let opNewValue = 0;
12483let addrMode = BaseRegOffset;
12484let accessSize = ByteAccess;
12485let mayLoad = 1;
12486let CextOpcode = "L2_loadrb";
12487let InputType = "reg";
12488let BaseOpcode = "L4_loadrb_rr";
12489}
12490def L4_ploadrbtnew_abs : HInst<
12491(outs IntRegs:$Rd32),
12492(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12493"if ($Pt4.new) $Rd32 = memb(#$Ii)",
12494tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
12495let Inst{7-5} = 0b100;
12496let Inst{13-11} = 0b110;
12497let Inst{31-21} = 0b10011111000;
12498let isPredicated = 1;
12499let hasNewValue = 1;
12500let opNewValue = 0;
12501let addrMode = Absolute;
12502let accessSize = ByteAccess;
12503let isPredicatedNew = 1;
12504let mayLoad = 1;
12505let isExtended = 1;
12506let CextOpcode = "L2_loadrb";
12507let BaseOpcode = "L4_loadrb_abs";
12508let DecoderNamespace = "MustExtend";
12509let isExtendable = 1;
12510let opExtendable = 2;
12511let isExtentSigned = 0;
12512let opExtentBits = 6;
12513let opExtentAlign = 0;
12514}
12515def L4_ploadrbtnew_rr : HInst<
12516(outs IntRegs:$Rd32),
12517(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12518"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12519tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
12520let Inst{31-21} = 0b00110010000;
12521let isPredicated = 1;
12522let hasNewValue = 1;
12523let opNewValue = 0;
12524let addrMode = BaseRegOffset;
12525let accessSize = ByteAccess;
12526let isPredicatedNew = 1;
12527let mayLoad = 1;
12528let CextOpcode = "L2_loadrb";
12529let InputType = "reg";
12530let BaseOpcode = "L4_loadrb_rr";
12531}
12532def L4_ploadrdf_abs : HInst<
12533(outs DoubleRegs:$Rdd32),
12534(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12535"if (!$Pt4) $Rdd32 = memd(#$Ii)",
12536tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel {
12537let Inst{7-5} = 0b100;
12538let Inst{13-11} = 0b101;
12539let Inst{31-21} = 0b10011111110;
12540let isPredicated = 1;
12541let isPredicatedFalse = 1;
12542let addrMode = Absolute;
12543let accessSize = DoubleWordAccess;
12544let mayLoad = 1;
12545let isExtended = 1;
12546let CextOpcode = "L2_loadrd";
12547let BaseOpcode = "L4_loadrd_abs";
12548let DecoderNamespace = "MustExtend";
12549let isExtendable = 1;
12550let opExtendable = 2;
12551let isExtentSigned = 0;
12552let opExtentBits = 6;
12553let opExtentAlign = 0;
12554}
12555def L4_ploadrdf_rr : HInst<
12556(outs DoubleRegs:$Rdd32),
12557(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12558"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12559tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel {
12560let Inst{31-21} = 0b00110001110;
12561let isPredicated = 1;
12562let isPredicatedFalse = 1;
12563let addrMode = BaseRegOffset;
12564let accessSize = DoubleWordAccess;
12565let mayLoad = 1;
12566let CextOpcode = "L2_loadrd";
12567let InputType = "reg";
12568let BaseOpcode = "L4_loadrd_rr";
12569}
12570def L4_ploadrdfnew_abs : HInst<
12571(outs DoubleRegs:$Rdd32),
12572(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12573"if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
12574tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel {
12575let Inst{7-5} = 0b100;
12576let Inst{13-11} = 0b111;
12577let Inst{31-21} = 0b10011111110;
12578let isPredicated = 1;
12579let isPredicatedFalse = 1;
12580let addrMode = Absolute;
12581let accessSize = DoubleWordAccess;
12582let isPredicatedNew = 1;
12583let mayLoad = 1;
12584let isExtended = 1;
12585let CextOpcode = "L2_loadrd";
12586let BaseOpcode = "L4_loadrd_abs";
12587let DecoderNamespace = "MustExtend";
12588let isExtendable = 1;
12589let opExtendable = 2;
12590let isExtentSigned = 0;
12591let opExtentBits = 6;
12592let opExtentAlign = 0;
12593}
12594def L4_ploadrdfnew_rr : HInst<
12595(outs DoubleRegs:$Rdd32),
12596(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12597"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12598tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel {
12599let Inst{31-21} = 0b00110011110;
12600let isPredicated = 1;
12601let isPredicatedFalse = 1;
12602let addrMode = BaseRegOffset;
12603let accessSize = DoubleWordAccess;
12604let isPredicatedNew = 1;
12605let mayLoad = 1;
12606let CextOpcode = "L2_loadrd";
12607let InputType = "reg";
12608let BaseOpcode = "L4_loadrd_rr";
12609}
12610def L4_ploadrdt_abs : HInst<
12611(outs DoubleRegs:$Rdd32),
12612(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12613"if ($Pt4) $Rdd32 = memd(#$Ii)",
12614tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel {
12615let Inst{7-5} = 0b100;
12616let Inst{13-11} = 0b100;
12617let Inst{31-21} = 0b10011111110;
12618let isPredicated = 1;
12619let addrMode = Absolute;
12620let accessSize = DoubleWordAccess;
12621let mayLoad = 1;
12622let isExtended = 1;
12623let CextOpcode = "L2_loadrd";
12624let BaseOpcode = "L4_loadrd_abs";
12625let DecoderNamespace = "MustExtend";
12626let isExtendable = 1;
12627let opExtendable = 2;
12628let isExtentSigned = 0;
12629let opExtentBits = 6;
12630let opExtentAlign = 0;
12631}
12632def L4_ploadrdt_rr : HInst<
12633(outs DoubleRegs:$Rdd32),
12634(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12635"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12636tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel {
12637let Inst{31-21} = 0b00110000110;
12638let isPredicated = 1;
12639let addrMode = BaseRegOffset;
12640let accessSize = DoubleWordAccess;
12641let mayLoad = 1;
12642let CextOpcode = "L2_loadrd";
12643let InputType = "reg";
12644let BaseOpcode = "L4_loadrd_rr";
12645}
12646def L4_ploadrdtnew_abs : HInst<
12647(outs DoubleRegs:$Rdd32),
12648(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12649"if ($Pt4.new) $Rdd32 = memd(#$Ii)",
12650tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel {
12651let Inst{7-5} = 0b100;
12652let Inst{13-11} = 0b110;
12653let Inst{31-21} = 0b10011111110;
12654let isPredicated = 1;
12655let addrMode = Absolute;
12656let accessSize = DoubleWordAccess;
12657let isPredicatedNew = 1;
12658let mayLoad = 1;
12659let isExtended = 1;
12660let CextOpcode = "L2_loadrd";
12661let BaseOpcode = "L4_loadrd_abs";
12662let DecoderNamespace = "MustExtend";
12663let isExtendable = 1;
12664let opExtendable = 2;
12665let isExtentSigned = 0;
12666let opExtentBits = 6;
12667let opExtentAlign = 0;
12668}
12669def L4_ploadrdtnew_rr : HInst<
12670(outs DoubleRegs:$Rdd32),
12671(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12672"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12673tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel {
12674let Inst{31-21} = 0b00110010110;
12675let isPredicated = 1;
12676let addrMode = BaseRegOffset;
12677let accessSize = DoubleWordAccess;
12678let isPredicatedNew = 1;
12679let mayLoad = 1;
12680let CextOpcode = "L2_loadrd";
12681let InputType = "reg";
12682let BaseOpcode = "L4_loadrd_rr";
12683}
12684def L4_ploadrhf_abs : HInst<
12685(outs IntRegs:$Rd32),
12686(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12687"if (!$Pt4) $Rd32 = memh(#$Ii)",
12688tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
12689let Inst{7-5} = 0b100;
12690let Inst{13-11} = 0b101;
12691let Inst{31-21} = 0b10011111010;
12692let isPredicated = 1;
12693let isPredicatedFalse = 1;
12694let hasNewValue = 1;
12695let opNewValue = 0;
12696let addrMode = Absolute;
12697let accessSize = HalfWordAccess;
12698let mayLoad = 1;
12699let isExtended = 1;
12700let CextOpcode = "L2_loadrh";
12701let BaseOpcode = "L4_loadrh_abs";
12702let DecoderNamespace = "MustExtend";
12703let isExtendable = 1;
12704let opExtendable = 2;
12705let isExtentSigned = 0;
12706let opExtentBits = 6;
12707let opExtentAlign = 0;
12708}
12709def L4_ploadrhf_rr : HInst<
12710(outs IntRegs:$Rd32),
12711(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12712"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12713tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
12714let Inst{31-21} = 0b00110001010;
12715let isPredicated = 1;
12716let isPredicatedFalse = 1;
12717let hasNewValue = 1;
12718let opNewValue = 0;
12719let addrMode = BaseRegOffset;
12720let accessSize = HalfWordAccess;
12721let mayLoad = 1;
12722let CextOpcode = "L2_loadrh";
12723let InputType = "reg";
12724let BaseOpcode = "L4_loadrh_rr";
12725}
12726def L4_ploadrhfnew_abs : HInst<
12727(outs IntRegs:$Rd32),
12728(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12729"if (!$Pt4.new) $Rd32 = memh(#$Ii)",
12730tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
12731let Inst{7-5} = 0b100;
12732let Inst{13-11} = 0b111;
12733let Inst{31-21} = 0b10011111010;
12734let isPredicated = 1;
12735let isPredicatedFalse = 1;
12736let hasNewValue = 1;
12737let opNewValue = 0;
12738let addrMode = Absolute;
12739let accessSize = HalfWordAccess;
12740let isPredicatedNew = 1;
12741let mayLoad = 1;
12742let isExtended = 1;
12743let CextOpcode = "L2_loadrh";
12744let BaseOpcode = "L4_loadrh_abs";
12745let DecoderNamespace = "MustExtend";
12746let isExtendable = 1;
12747let opExtendable = 2;
12748let isExtentSigned = 0;
12749let opExtentBits = 6;
12750let opExtentAlign = 0;
12751}
12752def L4_ploadrhfnew_rr : HInst<
12753(outs IntRegs:$Rd32),
12754(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12755"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12756tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
12757let Inst{31-21} = 0b00110011010;
12758let isPredicated = 1;
12759let isPredicatedFalse = 1;
12760let hasNewValue = 1;
12761let opNewValue = 0;
12762let addrMode = BaseRegOffset;
12763let accessSize = HalfWordAccess;
12764let isPredicatedNew = 1;
12765let mayLoad = 1;
12766let CextOpcode = "L2_loadrh";
12767let InputType = "reg";
12768let BaseOpcode = "L4_loadrh_rr";
12769}
12770def L4_ploadrht_abs : HInst<
12771(outs IntRegs:$Rd32),
12772(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12773"if ($Pt4) $Rd32 = memh(#$Ii)",
12774tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
12775let Inst{7-5} = 0b100;
12776let Inst{13-11} = 0b100;
12777let Inst{31-21} = 0b10011111010;
12778let isPredicated = 1;
12779let hasNewValue = 1;
12780let opNewValue = 0;
12781let addrMode = Absolute;
12782let accessSize = HalfWordAccess;
12783let mayLoad = 1;
12784let isExtended = 1;
12785let CextOpcode = "L2_loadrh";
12786let BaseOpcode = "L4_loadrh_abs";
12787let DecoderNamespace = "MustExtend";
12788let isExtendable = 1;
12789let opExtendable = 2;
12790let isExtentSigned = 0;
12791let opExtentBits = 6;
12792let opExtentAlign = 0;
12793}
12794def L4_ploadrht_rr : HInst<
12795(outs IntRegs:$Rd32),
12796(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12797"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12798tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
12799let Inst{31-21} = 0b00110000010;
12800let isPredicated = 1;
12801let hasNewValue = 1;
12802let opNewValue = 0;
12803let addrMode = BaseRegOffset;
12804let accessSize = HalfWordAccess;
12805let mayLoad = 1;
12806let CextOpcode = "L2_loadrh";
12807let InputType = "reg";
12808let BaseOpcode = "L4_loadrh_rr";
12809}
12810def L4_ploadrhtnew_abs : HInst<
12811(outs IntRegs:$Rd32),
12812(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12813"if ($Pt4.new) $Rd32 = memh(#$Ii)",
12814tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
12815let Inst{7-5} = 0b100;
12816let Inst{13-11} = 0b110;
12817let Inst{31-21} = 0b10011111010;
12818let isPredicated = 1;
12819let hasNewValue = 1;
12820let opNewValue = 0;
12821let addrMode = Absolute;
12822let accessSize = HalfWordAccess;
12823let isPredicatedNew = 1;
12824let mayLoad = 1;
12825let isExtended = 1;
12826let CextOpcode = "L2_loadrh";
12827let BaseOpcode = "L4_loadrh_abs";
12828let DecoderNamespace = "MustExtend";
12829let isExtendable = 1;
12830let opExtendable = 2;
12831let isExtentSigned = 0;
12832let opExtentBits = 6;
12833let opExtentAlign = 0;
12834}
12835def L4_ploadrhtnew_rr : HInst<
12836(outs IntRegs:$Rd32),
12837(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12838"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12839tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
12840let Inst{31-21} = 0b00110010010;
12841let isPredicated = 1;
12842let hasNewValue = 1;
12843let opNewValue = 0;
12844let addrMode = BaseRegOffset;
12845let accessSize = HalfWordAccess;
12846let isPredicatedNew = 1;
12847let mayLoad = 1;
12848let CextOpcode = "L2_loadrh";
12849let InputType = "reg";
12850let BaseOpcode = "L4_loadrh_rr";
12851}
12852def L4_ploadrif_abs : HInst<
12853(outs IntRegs:$Rd32),
12854(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12855"if (!$Pt4) $Rd32 = memw(#$Ii)",
12856tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
12857let Inst{7-5} = 0b100;
12858let Inst{13-11} = 0b101;
12859let Inst{31-21} = 0b10011111100;
12860let isPredicated = 1;
12861let isPredicatedFalse = 1;
12862let hasNewValue = 1;
12863let opNewValue = 0;
12864let addrMode = Absolute;
12865let accessSize = WordAccess;
12866let mayLoad = 1;
12867let isExtended = 1;
12868let CextOpcode = "L2_loadri";
12869let BaseOpcode = "L4_loadri_abs";
12870let DecoderNamespace = "MustExtend";
12871let isExtendable = 1;
12872let opExtendable = 2;
12873let isExtentSigned = 0;
12874let opExtentBits = 6;
12875let opExtentAlign = 0;
12876}
12877def L4_ploadrif_rr : HInst<
12878(outs IntRegs:$Rd32),
12879(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12880"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12881tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
12882let Inst{31-21} = 0b00110001100;
12883let isPredicated = 1;
12884let isPredicatedFalse = 1;
12885let hasNewValue = 1;
12886let opNewValue = 0;
12887let addrMode = BaseRegOffset;
12888let accessSize = WordAccess;
12889let mayLoad = 1;
12890let CextOpcode = "L2_loadri";
12891let InputType = "reg";
12892let BaseOpcode = "L4_loadri_rr";
12893}
12894def L4_ploadrifnew_abs : HInst<
12895(outs IntRegs:$Rd32),
12896(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12897"if (!$Pt4.new) $Rd32 = memw(#$Ii)",
12898tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
12899let Inst{7-5} = 0b100;
12900let Inst{13-11} = 0b111;
12901let Inst{31-21} = 0b10011111100;
12902let isPredicated = 1;
12903let isPredicatedFalse = 1;
12904let hasNewValue = 1;
12905let opNewValue = 0;
12906let addrMode = Absolute;
12907let accessSize = WordAccess;
12908let isPredicatedNew = 1;
12909let mayLoad = 1;
12910let isExtended = 1;
12911let CextOpcode = "L2_loadri";
12912let BaseOpcode = "L4_loadri_abs";
12913let DecoderNamespace = "MustExtend";
12914let isExtendable = 1;
12915let opExtendable = 2;
12916let isExtentSigned = 0;
12917let opExtentBits = 6;
12918let opExtentAlign = 0;
12919}
12920def L4_ploadrifnew_rr : HInst<
12921(outs IntRegs:$Rd32),
12922(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12923"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12924tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
12925let Inst{31-21} = 0b00110011100;
12926let isPredicated = 1;
12927let isPredicatedFalse = 1;
12928let hasNewValue = 1;
12929let opNewValue = 0;
12930let addrMode = BaseRegOffset;
12931let accessSize = WordAccess;
12932let isPredicatedNew = 1;
12933let mayLoad = 1;
12934let CextOpcode = "L2_loadri";
12935let InputType = "reg";
12936let BaseOpcode = "L4_loadri_rr";
12937}
12938def L4_ploadrit_abs : HInst<
12939(outs IntRegs:$Rd32),
12940(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12941"if ($Pt4) $Rd32 = memw(#$Ii)",
12942tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
12943let Inst{7-5} = 0b100;
12944let Inst{13-11} = 0b100;
12945let Inst{31-21} = 0b10011111100;
12946let isPredicated = 1;
12947let hasNewValue = 1;
12948let opNewValue = 0;
12949let addrMode = Absolute;
12950let accessSize = WordAccess;
12951let mayLoad = 1;
12952let isExtended = 1;
12953let CextOpcode = "L2_loadri";
12954let BaseOpcode = "L4_loadri_abs";
12955let DecoderNamespace = "MustExtend";
12956let isExtendable = 1;
12957let opExtendable = 2;
12958let isExtentSigned = 0;
12959let opExtentBits = 6;
12960let opExtentAlign = 0;
12961}
12962def L4_ploadrit_rr : HInst<
12963(outs IntRegs:$Rd32),
12964(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12965"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12966tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
12967let Inst{31-21} = 0b00110000100;
12968let isPredicated = 1;
12969let hasNewValue = 1;
12970let opNewValue = 0;
12971let addrMode = BaseRegOffset;
12972let accessSize = WordAccess;
12973let mayLoad = 1;
12974let CextOpcode = "L2_loadri";
12975let InputType = "reg";
12976let BaseOpcode = "L4_loadri_rr";
12977}
12978def L4_ploadritnew_abs : HInst<
12979(outs IntRegs:$Rd32),
12980(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12981"if ($Pt4.new) $Rd32 = memw(#$Ii)",
12982tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
12983let Inst{7-5} = 0b100;
12984let Inst{13-11} = 0b110;
12985let Inst{31-21} = 0b10011111100;
12986let isPredicated = 1;
12987let hasNewValue = 1;
12988let opNewValue = 0;
12989let addrMode = Absolute;
12990let accessSize = WordAccess;
12991let isPredicatedNew = 1;
12992let mayLoad = 1;
12993let isExtended = 1;
12994let CextOpcode = "L2_loadri";
12995let BaseOpcode = "L4_loadri_abs";
12996let DecoderNamespace = "MustExtend";
12997let isExtendable = 1;
12998let opExtendable = 2;
12999let isExtentSigned = 0;
13000let opExtentBits = 6;
13001let opExtentAlign = 0;
13002}
13003def L4_ploadritnew_rr : HInst<
13004(outs IntRegs:$Rd32),
13005(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13006"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13007tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
13008let Inst{31-21} = 0b00110010100;
13009let isPredicated = 1;
13010let hasNewValue = 1;
13011let opNewValue = 0;
13012let addrMode = BaseRegOffset;
13013let accessSize = WordAccess;
13014let isPredicatedNew = 1;
13015let mayLoad = 1;
13016let CextOpcode = "L2_loadri";
13017let InputType = "reg";
13018let BaseOpcode = "L4_loadri_rr";
13019}
13020def L4_ploadrubf_abs : HInst<
13021(outs IntRegs:$Rd32),
13022(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13023"if (!$Pt4) $Rd32 = memub(#$Ii)",
13024tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
13025let Inst{7-5} = 0b100;
13026let Inst{13-11} = 0b101;
13027let Inst{31-21} = 0b10011111001;
13028let isPredicated = 1;
13029let isPredicatedFalse = 1;
13030let hasNewValue = 1;
13031let opNewValue = 0;
13032let addrMode = Absolute;
13033let accessSize = ByteAccess;
13034let mayLoad = 1;
13035let isExtended = 1;
13036let CextOpcode = "L2_loadrub";
13037let BaseOpcode = "L4_loadrub_abs";
13038let DecoderNamespace = "MustExtend";
13039let isExtendable = 1;
13040let opExtendable = 2;
13041let isExtentSigned = 0;
13042let opExtentBits = 6;
13043let opExtentAlign = 0;
13044}
13045def L4_ploadrubf_rr : HInst<
13046(outs IntRegs:$Rd32),
13047(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13048"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13049tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
13050let Inst{31-21} = 0b00110001001;
13051let isPredicated = 1;
13052let isPredicatedFalse = 1;
13053let hasNewValue = 1;
13054let opNewValue = 0;
13055let addrMode = BaseRegOffset;
13056let accessSize = ByteAccess;
13057let mayLoad = 1;
13058let CextOpcode = "L2_loadrub";
13059let InputType = "reg";
13060let BaseOpcode = "L4_loadrub_rr";
13061}
13062def L4_ploadrubfnew_abs : HInst<
13063(outs IntRegs:$Rd32),
13064(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13065"if (!$Pt4.new) $Rd32 = memub(#$Ii)",
13066tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
13067let Inst{7-5} = 0b100;
13068let Inst{13-11} = 0b111;
13069let Inst{31-21} = 0b10011111001;
13070let isPredicated = 1;
13071let isPredicatedFalse = 1;
13072let hasNewValue = 1;
13073let opNewValue = 0;
13074let addrMode = Absolute;
13075let accessSize = ByteAccess;
13076let isPredicatedNew = 1;
13077let mayLoad = 1;
13078let isExtended = 1;
13079let CextOpcode = "L2_loadrub";
13080let BaseOpcode = "L4_loadrub_abs";
13081let DecoderNamespace = "MustExtend";
13082let isExtendable = 1;
13083let opExtendable = 2;
13084let isExtentSigned = 0;
13085let opExtentBits = 6;
13086let opExtentAlign = 0;
13087}
13088def L4_ploadrubfnew_rr : HInst<
13089(outs IntRegs:$Rd32),
13090(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13091"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13092tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
13093let Inst{31-21} = 0b00110011001;
13094let isPredicated = 1;
13095let isPredicatedFalse = 1;
13096let hasNewValue = 1;
13097let opNewValue = 0;
13098let addrMode = BaseRegOffset;
13099let accessSize = ByteAccess;
13100let isPredicatedNew = 1;
13101let mayLoad = 1;
13102let CextOpcode = "L2_loadrub";
13103let InputType = "reg";
13104let BaseOpcode = "L4_loadrub_rr";
13105}
13106def L4_ploadrubt_abs : HInst<
13107(outs IntRegs:$Rd32),
13108(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13109"if ($Pt4) $Rd32 = memub(#$Ii)",
13110tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
13111let Inst{7-5} = 0b100;
13112let Inst{13-11} = 0b100;
13113let Inst{31-21} = 0b10011111001;
13114let isPredicated = 1;
13115let hasNewValue = 1;
13116let opNewValue = 0;
13117let addrMode = Absolute;
13118let accessSize = ByteAccess;
13119let mayLoad = 1;
13120let isExtended = 1;
13121let CextOpcode = "L2_loadrub";
13122let BaseOpcode = "L4_loadrub_abs";
13123let DecoderNamespace = "MustExtend";
13124let isExtendable = 1;
13125let opExtendable = 2;
13126let isExtentSigned = 0;
13127let opExtentBits = 6;
13128let opExtentAlign = 0;
13129}
13130def L4_ploadrubt_rr : HInst<
13131(outs IntRegs:$Rd32),
13132(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13133"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13134tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
13135let Inst{31-21} = 0b00110000001;
13136let isPredicated = 1;
13137let hasNewValue = 1;
13138let opNewValue = 0;
13139let addrMode = BaseRegOffset;
13140let accessSize = ByteAccess;
13141let mayLoad = 1;
13142let CextOpcode = "L2_loadrub";
13143let InputType = "reg";
13144let BaseOpcode = "L4_loadrub_rr";
13145}
13146def L4_ploadrubtnew_abs : HInst<
13147(outs IntRegs:$Rd32),
13148(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13149"if ($Pt4.new) $Rd32 = memub(#$Ii)",
13150tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
13151let Inst{7-5} = 0b100;
13152let Inst{13-11} = 0b110;
13153let Inst{31-21} = 0b10011111001;
13154let isPredicated = 1;
13155let hasNewValue = 1;
13156let opNewValue = 0;
13157let addrMode = Absolute;
13158let accessSize = ByteAccess;
13159let isPredicatedNew = 1;
13160let mayLoad = 1;
13161let isExtended = 1;
13162let CextOpcode = "L2_loadrub";
13163let BaseOpcode = "L4_loadrub_abs";
13164let DecoderNamespace = "MustExtend";
13165let isExtendable = 1;
13166let opExtendable = 2;
13167let isExtentSigned = 0;
13168let opExtentBits = 6;
13169let opExtentAlign = 0;
13170}
13171def L4_ploadrubtnew_rr : HInst<
13172(outs IntRegs:$Rd32),
13173(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13174"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13175tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
13176let Inst{31-21} = 0b00110010001;
13177let isPredicated = 1;
13178let hasNewValue = 1;
13179let opNewValue = 0;
13180let addrMode = BaseRegOffset;
13181let accessSize = ByteAccess;
13182let isPredicatedNew = 1;
13183let mayLoad = 1;
13184let CextOpcode = "L2_loadrub";
13185let InputType = "reg";
13186let BaseOpcode = "L4_loadrub_rr";
13187}
13188def L4_ploadruhf_abs : HInst<
13189(outs IntRegs:$Rd32),
13190(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13191"if (!$Pt4) $Rd32 = memuh(#$Ii)",
13192tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
13193let Inst{7-5} = 0b100;
13194let Inst{13-11} = 0b101;
13195let Inst{31-21} = 0b10011111011;
13196let isPredicated = 1;
13197let isPredicatedFalse = 1;
13198let hasNewValue = 1;
13199let opNewValue = 0;
13200let addrMode = Absolute;
13201let accessSize = HalfWordAccess;
13202let mayLoad = 1;
13203let isExtended = 1;
13204let CextOpcode = "L2_loadruh";
13205let BaseOpcode = "L4_loadruh_abs";
13206let DecoderNamespace = "MustExtend";
13207let isExtendable = 1;
13208let opExtendable = 2;
13209let isExtentSigned = 0;
13210let opExtentBits = 6;
13211let opExtentAlign = 0;
13212}
13213def L4_ploadruhf_rr : HInst<
13214(outs IntRegs:$Rd32),
13215(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13216"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13217tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
13218let Inst{31-21} = 0b00110001011;
13219let isPredicated = 1;
13220let isPredicatedFalse = 1;
13221let hasNewValue = 1;
13222let opNewValue = 0;
13223let addrMode = BaseRegOffset;
13224let accessSize = HalfWordAccess;
13225let mayLoad = 1;
13226let CextOpcode = "L2_loadruh";
13227let InputType = "reg";
13228let BaseOpcode = "L4_loadruh_rr";
13229}
13230def L4_ploadruhfnew_abs : HInst<
13231(outs IntRegs:$Rd32),
13232(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13233"if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
13234tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
13235let Inst{7-5} = 0b100;
13236let Inst{13-11} = 0b111;
13237let Inst{31-21} = 0b10011111011;
13238let isPredicated = 1;
13239let isPredicatedFalse = 1;
13240let hasNewValue = 1;
13241let opNewValue = 0;
13242let addrMode = Absolute;
13243let accessSize = HalfWordAccess;
13244let isPredicatedNew = 1;
13245let mayLoad = 1;
13246let isExtended = 1;
13247let CextOpcode = "L2_loadruh";
13248let BaseOpcode = "L4_loadruh_abs";
13249let DecoderNamespace = "MustExtend";
13250let isExtendable = 1;
13251let opExtendable = 2;
13252let isExtentSigned = 0;
13253let opExtentBits = 6;
13254let opExtentAlign = 0;
13255}
13256def L4_ploadruhfnew_rr : HInst<
13257(outs IntRegs:$Rd32),
13258(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13259"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13260tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
13261let Inst{31-21} = 0b00110011011;
13262let isPredicated = 1;
13263let isPredicatedFalse = 1;
13264let hasNewValue = 1;
13265let opNewValue = 0;
13266let addrMode = BaseRegOffset;
13267let accessSize = HalfWordAccess;
13268let isPredicatedNew = 1;
13269let mayLoad = 1;
13270let CextOpcode = "L2_loadruh";
13271let InputType = "reg";
13272let BaseOpcode = "L4_loadruh_rr";
13273}
13274def L4_ploadruht_abs : HInst<
13275(outs IntRegs:$Rd32),
13276(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13277"if ($Pt4) $Rd32 = memuh(#$Ii)",
13278tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel {
13279let Inst{7-5} = 0b100;
13280let Inst{13-11} = 0b100;
13281let Inst{31-21} = 0b10011111011;
13282let isPredicated = 1;
13283let hasNewValue = 1;
13284let opNewValue = 0;
13285let addrMode = Absolute;
13286let accessSize = HalfWordAccess;
13287let mayLoad = 1;
13288let isExtended = 1;
13289let CextOpcode = "L2_loadruh";
13290let BaseOpcode = "L4_loadruh_abs";
13291let DecoderNamespace = "MustExtend";
13292let isExtendable = 1;
13293let opExtendable = 2;
13294let isExtentSigned = 0;
13295let opExtentBits = 6;
13296let opExtentAlign = 0;
13297}
13298def L4_ploadruht_rr : HInst<
13299(outs IntRegs:$Rd32),
13300(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13301"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13302tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel {
13303let Inst{31-21} = 0b00110000011;
13304let isPredicated = 1;
13305let hasNewValue = 1;
13306let opNewValue = 0;
13307let addrMode = BaseRegOffset;
13308let accessSize = HalfWordAccess;
13309let mayLoad = 1;
13310let CextOpcode = "L2_loadruh";
13311let InputType = "reg";
13312let BaseOpcode = "L4_loadruh_rr";
13313}
13314def L4_ploadruhtnew_abs : HInst<
13315(outs IntRegs:$Rd32),
13316(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13317"if ($Pt4.new) $Rd32 = memuh(#$Ii)",
13318tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel {
13319let Inst{7-5} = 0b100;
13320let Inst{13-11} = 0b110;
13321let Inst{31-21} = 0b10011111011;
13322let isPredicated = 1;
13323let hasNewValue = 1;
13324let opNewValue = 0;
13325let addrMode = Absolute;
13326let accessSize = HalfWordAccess;
13327let isPredicatedNew = 1;
13328let mayLoad = 1;
13329let isExtended = 1;
13330let CextOpcode = "L2_loadruh";
13331let BaseOpcode = "L4_loadruh_abs";
13332let DecoderNamespace = "MustExtend";
13333let isExtendable = 1;
13334let opExtendable = 2;
13335let isExtentSigned = 0;
13336let opExtentBits = 6;
13337let opExtentAlign = 0;
13338}
13339def L4_ploadruhtnew_rr : HInst<
13340(outs IntRegs:$Rd32),
13341(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13342"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13343tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel {
13344let Inst{31-21} = 0b00110010011;
13345let isPredicated = 1;
13346let hasNewValue = 1;
13347let opNewValue = 0;
13348let addrMode = BaseRegOffset;
13349let accessSize = HalfWordAccess;
13350let isPredicatedNew = 1;
13351let mayLoad = 1;
13352let CextOpcode = "L2_loadruh";
13353let InputType = "reg";
13354let BaseOpcode = "L4_loadruh_rr";
13355}
13356def L4_return : HInst<
13357(outs DoubleRegs:$Rdd32),
13358(ins IntRegs:$Rs32),
13359"$Rdd32 = dealloc_return($Rs32):raw",
13360tc_675e4897, TypeLD>, Enc_3a3d62, PredNewRel {
13361let Inst{13-5} = 0b000000000;
13362let Inst{31-21} = 0b10010110000;
13363let isTerminator = 1;
13364let isIndirectBranch = 1;
13365let accessSize = DoubleWordAccess;
13366let mayLoad = 1;
13367let cofMax1 = 1;
13368let isRestrictNoSlot1Store = 1;
13369let isReturn = 1;
13370let Uses = [FRAMEKEY];
13371let Defs = [PC, R29];
13372let BaseOpcode = "L4_return";
13373let isBarrier = 1;
13374let isPredicable = 1;
13375let isTaken = 1;
13376}
13377def L4_return_f : HInst<
13378(outs DoubleRegs:$Rdd32),
13379(ins PredRegs:$Pv4, IntRegs:$Rs32),
13380"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13381tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel {
13382let Inst{7-5} = 0b000;
13383let Inst{13-10} = 0b1100;
13384let Inst{31-21} = 0b10010110000;
13385let isPredicated = 1;
13386let isPredicatedFalse = 1;
13387let isTerminator = 1;
13388let isIndirectBranch = 1;
13389let accessSize = DoubleWordAccess;
13390let mayLoad = 1;
13391let cofMax1 = 1;
13392let isRestrictNoSlot1Store = 1;
13393let isReturn = 1;
13394let Uses = [FRAMEKEY];
13395let Defs = [PC, R29];
13396let BaseOpcode = "L4_return";
13397let isTaken = Inst{12};
13398}
13399def L4_return_fnew_pnt : HInst<
13400(outs DoubleRegs:$Rdd32),
13401(ins PredRegs:$Pv4, IntRegs:$Rs32),
13402"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13403tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel {
13404let Inst{7-5} = 0b000;
13405let Inst{13-10} = 0b1010;
13406let Inst{31-21} = 0b10010110000;
13407let isPredicated = 1;
13408let isPredicatedFalse = 1;
13409let isTerminator = 1;
13410let isIndirectBranch = 1;
13411let accessSize = DoubleWordAccess;
13412let isPredicatedNew = 1;
13413let mayLoad = 1;
13414let cofMax1 = 1;
13415let isRestrictNoSlot1Store = 1;
13416let isReturn = 1;
13417let Uses = [FRAMEKEY];
13418let Defs = [PC, R29];
13419let BaseOpcode = "L4_return";
13420let isTaken = Inst{12};
13421}
13422def L4_return_fnew_pt : HInst<
13423(outs DoubleRegs:$Rdd32),
13424(ins PredRegs:$Pv4, IntRegs:$Rs32),
13425"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13426tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel {
13427let Inst{7-5} = 0b000;
13428let Inst{13-10} = 0b1110;
13429let Inst{31-21} = 0b10010110000;
13430let isPredicated = 1;
13431let isPredicatedFalse = 1;
13432let isTerminator = 1;
13433let isIndirectBranch = 1;
13434let accessSize = DoubleWordAccess;
13435let isPredicatedNew = 1;
13436let mayLoad = 1;
13437let cofMax1 = 1;
13438let isRestrictNoSlot1Store = 1;
13439let isReturn = 1;
13440let Uses = [FRAMEKEY];
13441let Defs = [PC, R29];
13442let BaseOpcode = "L4_return";
13443let isTaken = Inst{12};
13444}
13445def L4_return_map_to_raw_f : HInst<
13446(outs),
13447(ins PredRegs:$Pv4),
13448"if (!$Pv4) dealloc_return",
13449tc_2b8da4c2, TypeMAPPING>, Requires<[HasV65]> {
13450let isPseudo = 1;
13451let isCodeGenOnly = 1;
13452}
13453def L4_return_map_to_raw_fnew_pnt : HInst<
13454(outs),
13455(ins PredRegs:$Pv4),
13456"if (!$Pv4.new) dealloc_return:nt",
13457tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> {
13458let isPseudo = 1;
13459let isCodeGenOnly = 1;
13460}
13461def L4_return_map_to_raw_fnew_pt : HInst<
13462(outs),
13463(ins PredRegs:$Pv4),
13464"if (!$Pv4.new) dealloc_return:t",
13465tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> {
13466let isPseudo = 1;
13467let isCodeGenOnly = 1;
13468}
13469def L4_return_map_to_raw_t : HInst<
13470(outs),
13471(ins PredRegs:$Pv4),
13472"if ($Pv4) dealloc_return",
13473tc_4d5fa3a1, TypeMAPPING>, Requires<[HasV65]> {
13474let isPseudo = 1;
13475let isCodeGenOnly = 1;
13476}
13477def L4_return_map_to_raw_tnew_pnt : HInst<
13478(outs),
13479(ins PredRegs:$Pv4),
13480"if ($Pv4.new) dealloc_return:nt",
13481tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> {
13482let isPseudo = 1;
13483let isCodeGenOnly = 1;
13484}
13485def L4_return_map_to_raw_tnew_pt : HInst<
13486(outs),
13487(ins PredRegs:$Pv4),
13488"if ($Pv4.new) dealloc_return:t",
13489tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> {
13490let isPseudo = 1;
13491let isCodeGenOnly = 1;
13492}
13493def L4_return_t : HInst<
13494(outs DoubleRegs:$Rdd32),
13495(ins PredRegs:$Pv4, IntRegs:$Rs32),
13496"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13497tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel {
13498let Inst{7-5} = 0b000;
13499let Inst{13-10} = 0b0100;
13500let Inst{31-21} = 0b10010110000;
13501let isPredicated = 1;
13502let isTerminator = 1;
13503let isIndirectBranch = 1;
13504let accessSize = DoubleWordAccess;
13505let mayLoad = 1;
13506let cofMax1 = 1;
13507let isRestrictNoSlot1Store = 1;
13508let isReturn = 1;
13509let Uses = [FRAMEKEY];
13510let Defs = [PC, R29];
13511let BaseOpcode = "L4_return";
13512let isTaken = Inst{12};
13513}
13514def L4_return_tnew_pnt : HInst<
13515(outs DoubleRegs:$Rdd32),
13516(ins PredRegs:$Pv4, IntRegs:$Rs32),
13517"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13518tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel {
13519let Inst{7-5} = 0b000;
13520let Inst{13-10} = 0b0010;
13521let Inst{31-21} = 0b10010110000;
13522let isPredicated = 1;
13523let isTerminator = 1;
13524let isIndirectBranch = 1;
13525let accessSize = DoubleWordAccess;
13526let isPredicatedNew = 1;
13527let mayLoad = 1;
13528let cofMax1 = 1;
13529let isRestrictNoSlot1Store = 1;
13530let isReturn = 1;
13531let Uses = [FRAMEKEY];
13532let Defs = [PC, R29];
13533let BaseOpcode = "L4_return";
13534let isTaken = Inst{12};
13535}
13536def L4_return_tnew_pt : HInst<
13537(outs DoubleRegs:$Rdd32),
13538(ins PredRegs:$Pv4, IntRegs:$Rs32),
13539"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13540tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel {
13541let Inst{7-5} = 0b000;
13542let Inst{13-10} = 0b0110;
13543let Inst{31-21} = 0b10010110000;
13544let isPredicated = 1;
13545let isTerminator = 1;
13546let isIndirectBranch = 1;
13547let accessSize = DoubleWordAccess;
13548let isPredicatedNew = 1;
13549let mayLoad = 1;
13550let cofMax1 = 1;
13551let isRestrictNoSlot1Store = 1;
13552let isReturn = 1;
13553let Uses = [FRAMEKEY];
13554let Defs = [PC, R29];
13555let BaseOpcode = "L4_return";
13556let isTaken = Inst{12};
13557}
13558def L4_sub_memopb_io : HInst<
13559(outs),
13560(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
13561"memb($Rs32+#$Ii) -= $Rt32",
13562tc_7186d325, TypeV4LDST>, Enc_d44e31 {
13563let Inst{6-5} = 0b01;
13564let Inst{13-13} = 0b0;
13565let Inst{31-21} = 0b00111110000;
13566let addrMode = BaseImmOffset;
13567let accessSize = ByteAccess;
13568let mayLoad = 1;
13569let isRestrictNoSlot1Store = 1;
13570let mayStore = 1;
13571let isExtendable = 1;
13572let opExtendable = 1;
13573let isExtentSigned = 0;
13574let opExtentBits = 6;
13575let opExtentAlign = 0;
13576}
13577def L4_sub_memopb_zomap : HInst<
13578(outs),
13579(ins IntRegs:$Rs32, IntRegs:$Rt32),
13580"memb($Rs32) -= $Rt32",
13581tc_7186d325, TypeMAPPING> {
13582let isPseudo = 1;
13583let isCodeGenOnly = 1;
13584}
13585def L4_sub_memoph_io : HInst<
13586(outs),
13587(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
13588"memh($Rs32+#$Ii) -= $Rt32",
13589tc_7186d325, TypeV4LDST>, Enc_163a3c {
13590let Inst{6-5} = 0b01;
13591let Inst{13-13} = 0b0;
13592let Inst{31-21} = 0b00111110001;
13593let addrMode = BaseImmOffset;
13594let accessSize = HalfWordAccess;
13595let mayLoad = 1;
13596let isRestrictNoSlot1Store = 1;
13597let mayStore = 1;
13598let isExtendable = 1;
13599let opExtendable = 1;
13600let isExtentSigned = 0;
13601let opExtentBits = 7;
13602let opExtentAlign = 1;
13603}
13604def L4_sub_memoph_zomap : HInst<
13605(outs),
13606(ins IntRegs:$Rs32, IntRegs:$Rt32),
13607"memh($Rs32) -= $Rt32",
13608tc_7186d325, TypeMAPPING> {
13609let isPseudo = 1;
13610let isCodeGenOnly = 1;
13611}
13612def L4_sub_memopw_io : HInst<
13613(outs),
13614(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
13615"memw($Rs32+#$Ii) -= $Rt32",
13616tc_7186d325, TypeV4LDST>, Enc_226535 {
13617let Inst{6-5} = 0b01;
13618let Inst{13-13} = 0b0;
13619let Inst{31-21} = 0b00111110010;
13620let addrMode = BaseImmOffset;
13621let accessSize = WordAccess;
13622let mayLoad = 1;
13623let isRestrictNoSlot1Store = 1;
13624let mayStore = 1;
13625let isExtendable = 1;
13626let opExtendable = 1;
13627let isExtentSigned = 0;
13628let opExtentBits = 8;
13629let opExtentAlign = 2;
13630}
13631def L4_sub_memopw_zomap : HInst<
13632(outs),
13633(ins IntRegs:$Rs32, IntRegs:$Rt32),
13634"memw($Rs32) -= $Rt32",
13635tc_7186d325, TypeMAPPING> {
13636let isPseudo = 1;
13637let isCodeGenOnly = 1;
13638}
13639def L6_deallocframe_map_to_raw : HInst<
13640(outs),
13641(ins),
13642"deallocframe",
13643tc_15aa71c5, TypeMAPPING>, Requires<[HasV65]> {
13644let isPseudo = 1;
13645let isCodeGenOnly = 1;
13646}
13647def L6_memcpy : HInst<
13648(outs),
13649(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
13650"memcpy($Rs32,$Rt32,$Mu2)",
13651tc_a6b1eca9, TypeLD>, Enc_a75aa6, Requires<[HasV66]> {
13652let Inst{7-0} = 0b01000000;
13653let Inst{31-21} = 0b10010010000;
13654let mayLoad = 1;
13655let isSolo = 1;
13656let mayStore = 1;
13657}
13658def L6_return_map_to_raw : HInst<
13659(outs),
13660(ins),
13661"dealloc_return",
13662tc_675e4897, TypeMAPPING>, Requires<[HasV65]> {
13663let isPseudo = 1;
13664let isCodeGenOnly = 1;
13665}
13666def M2_acci : HInst<
13667(outs IntRegs:$Rx32),
13668(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13669"$Rx32 += add($Rs32,$Rt32)",
13670tc_f675fee8, TypeM>, Enc_2ae154, ImmRegRel {
13671let Inst{7-5} = 0b001;
13672let Inst{13-13} = 0b0;
13673let Inst{31-21} = 0b11101111000;
13674let hasNewValue = 1;
13675let opNewValue = 0;
13676let prefersSlot3 = 1;
13677let CextOpcode = "M2_acci";
13678let InputType = "reg";
13679let Constraints = "$Rx32 = $Rx32in";
13680}
13681def M2_accii : HInst<
13682(outs IntRegs:$Rx32),
13683(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
13684"$Rx32 += add($Rs32,#$Ii)",
13685tc_f675fee8, TypeM>, Enc_c90aca, ImmRegRel {
13686let Inst{13-13} = 0b0;
13687let Inst{31-21} = 0b11100010000;
13688let hasNewValue = 1;
13689let opNewValue = 0;
13690let prefersSlot3 = 1;
13691let CextOpcode = "M2_acci";
13692let InputType = "imm";
13693let isExtendable = 1;
13694let opExtendable = 3;
13695let isExtentSigned = 1;
13696let opExtentBits = 8;
13697let opExtentAlign = 0;
13698let Constraints = "$Rx32 = $Rx32in";
13699}
13700def M2_cmaci_s0 : HInst<
13701(outs DoubleRegs:$Rxx32),
13702(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13703"$Rxx32 += cmpyi($Rs32,$Rt32)",
13704tc_d773585a, TypeM>, Enc_61f0b0 {
13705let Inst{7-5} = 0b001;
13706let Inst{13-13} = 0b0;
13707let Inst{31-21} = 0b11100111000;
13708let prefersSlot3 = 1;
13709let Constraints = "$Rxx32 = $Rxx32in";
13710}
13711def M2_cmacr_s0 : HInst<
13712(outs DoubleRegs:$Rxx32),
13713(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13714"$Rxx32 += cmpyr($Rs32,$Rt32)",
13715tc_d773585a, TypeM>, Enc_61f0b0 {
13716let Inst{7-5} = 0b010;
13717let Inst{13-13} = 0b0;
13718let Inst{31-21} = 0b11100111000;
13719let prefersSlot3 = 1;
13720let Constraints = "$Rxx32 = $Rxx32in";
13721}
13722def M2_cmacs_s0 : HInst<
13723(outs DoubleRegs:$Rxx32),
13724(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13725"$Rxx32 += cmpy($Rs32,$Rt32):sat",
13726tc_d773585a, TypeM>, Enc_61f0b0 {
13727let Inst{7-5} = 0b110;
13728let Inst{13-13} = 0b0;
13729let Inst{31-21} = 0b11100111000;
13730let prefersSlot3 = 1;
13731let Defs = [USR_OVF];
13732let Constraints = "$Rxx32 = $Rxx32in";
13733}
13734def M2_cmacs_s1 : HInst<
13735(outs DoubleRegs:$Rxx32),
13736(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13737"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
13738tc_d773585a, TypeM>, Enc_61f0b0 {
13739let Inst{7-5} = 0b110;
13740let Inst{13-13} = 0b0;
13741let Inst{31-21} = 0b11100111100;
13742let prefersSlot3 = 1;
13743let Defs = [USR_OVF];
13744let Constraints = "$Rxx32 = $Rxx32in";
13745}
13746def M2_cmacsc_s0 : HInst<
13747(outs DoubleRegs:$Rxx32),
13748(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13749"$Rxx32 += cmpy($Rs32,$Rt32*):sat",
13750tc_d773585a, TypeM>, Enc_61f0b0 {
13751let Inst{7-5} = 0b110;
13752let Inst{13-13} = 0b0;
13753let Inst{31-21} = 0b11100111010;
13754let prefersSlot3 = 1;
13755let Defs = [USR_OVF];
13756let Constraints = "$Rxx32 = $Rxx32in";
13757}
13758def M2_cmacsc_s1 : HInst<
13759(outs DoubleRegs:$Rxx32),
13760(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13761"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
13762tc_d773585a, TypeM>, Enc_61f0b0 {
13763let Inst{7-5} = 0b110;
13764let Inst{13-13} = 0b0;
13765let Inst{31-21} = 0b11100111110;
13766let prefersSlot3 = 1;
13767let Defs = [USR_OVF];
13768let Constraints = "$Rxx32 = $Rxx32in";
13769}
13770def M2_cmpyi_s0 : HInst<
13771(outs DoubleRegs:$Rdd32),
13772(ins IntRegs:$Rs32, IntRegs:$Rt32),
13773"$Rdd32 = cmpyi($Rs32,$Rt32)",
13774tc_bafaade3, TypeM>, Enc_be32a5 {
13775let Inst{7-5} = 0b001;
13776let Inst{13-13} = 0b0;
13777let Inst{31-21} = 0b11100101000;
13778let prefersSlot3 = 1;
13779}
13780def M2_cmpyr_s0 : HInst<
13781(outs DoubleRegs:$Rdd32),
13782(ins IntRegs:$Rs32, IntRegs:$Rt32),
13783"$Rdd32 = cmpyr($Rs32,$Rt32)",
13784tc_bafaade3, TypeM>, Enc_be32a5 {
13785let Inst{7-5} = 0b010;
13786let Inst{13-13} = 0b0;
13787let Inst{31-21} = 0b11100101000;
13788let prefersSlot3 = 1;
13789}
13790def M2_cmpyrs_s0 : HInst<
13791(outs IntRegs:$Rd32),
13792(ins IntRegs:$Rs32, IntRegs:$Rt32),
13793"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
13794tc_bafaade3, TypeM>, Enc_5ab2be {
13795let Inst{7-5} = 0b110;
13796let Inst{13-13} = 0b0;
13797let Inst{31-21} = 0b11101101001;
13798let hasNewValue = 1;
13799let opNewValue = 0;
13800let prefersSlot3 = 1;
13801let Defs = [USR_OVF];
13802}
13803def M2_cmpyrs_s1 : HInst<
13804(outs IntRegs:$Rd32),
13805(ins IntRegs:$Rs32, IntRegs:$Rt32),
13806"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
13807tc_bafaade3, TypeM>, Enc_5ab2be {
13808let Inst{7-5} = 0b110;
13809let Inst{13-13} = 0b0;
13810let Inst{31-21} = 0b11101101101;
13811let hasNewValue = 1;
13812let opNewValue = 0;
13813let prefersSlot3 = 1;
13814let Defs = [USR_OVF];
13815}
13816def M2_cmpyrsc_s0 : HInst<
13817(outs IntRegs:$Rd32),
13818(ins IntRegs:$Rs32, IntRegs:$Rt32),
13819"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
13820tc_bafaade3, TypeM>, Enc_5ab2be {
13821let Inst{7-5} = 0b110;
13822let Inst{13-13} = 0b0;
13823let Inst{31-21} = 0b11101101011;
13824let hasNewValue = 1;
13825let opNewValue = 0;
13826let prefersSlot3 = 1;
13827let Defs = [USR_OVF];
13828}
13829def M2_cmpyrsc_s1 : HInst<
13830(outs IntRegs:$Rd32),
13831(ins IntRegs:$Rs32, IntRegs:$Rt32),
13832"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
13833tc_bafaade3, TypeM>, Enc_5ab2be {
13834let Inst{7-5} = 0b110;
13835let Inst{13-13} = 0b0;
13836let Inst{31-21} = 0b11101101111;
13837let hasNewValue = 1;
13838let opNewValue = 0;
13839let prefersSlot3 = 1;
13840let Defs = [USR_OVF];
13841}
13842def M2_cmpys_s0 : HInst<
13843(outs DoubleRegs:$Rdd32),
13844(ins IntRegs:$Rs32, IntRegs:$Rt32),
13845"$Rdd32 = cmpy($Rs32,$Rt32):sat",
13846tc_bafaade3, TypeM>, Enc_be32a5 {
13847let Inst{7-5} = 0b110;
13848let Inst{13-13} = 0b0;
13849let Inst{31-21} = 0b11100101000;
13850let prefersSlot3 = 1;
13851let Defs = [USR_OVF];
13852}
13853def M2_cmpys_s1 : HInst<
13854(outs DoubleRegs:$Rdd32),
13855(ins IntRegs:$Rs32, IntRegs:$Rt32),
13856"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
13857tc_bafaade3, TypeM>, Enc_be32a5 {
13858let Inst{7-5} = 0b110;
13859let Inst{13-13} = 0b0;
13860let Inst{31-21} = 0b11100101100;
13861let prefersSlot3 = 1;
13862let Defs = [USR_OVF];
13863}
13864def M2_cmpysc_s0 : HInst<
13865(outs DoubleRegs:$Rdd32),
13866(ins IntRegs:$Rs32, IntRegs:$Rt32),
13867"$Rdd32 = cmpy($Rs32,$Rt32*):sat",
13868tc_bafaade3, TypeM>, Enc_be32a5 {
13869let Inst{7-5} = 0b110;
13870let Inst{13-13} = 0b0;
13871let Inst{31-21} = 0b11100101010;
13872let prefersSlot3 = 1;
13873let Defs = [USR_OVF];
13874}
13875def M2_cmpysc_s1 : HInst<
13876(outs DoubleRegs:$Rdd32),
13877(ins IntRegs:$Rs32, IntRegs:$Rt32),
13878"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
13879tc_bafaade3, TypeM>, Enc_be32a5 {
13880let Inst{7-5} = 0b110;
13881let Inst{13-13} = 0b0;
13882let Inst{31-21} = 0b11100101110;
13883let prefersSlot3 = 1;
13884let Defs = [USR_OVF];
13885}
13886def M2_cnacs_s0 : HInst<
13887(outs DoubleRegs:$Rxx32),
13888(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13889"$Rxx32 -= cmpy($Rs32,$Rt32):sat",
13890tc_d773585a, TypeM>, Enc_61f0b0 {
13891let Inst{7-5} = 0b111;
13892let Inst{13-13} = 0b0;
13893let Inst{31-21} = 0b11100111000;
13894let prefersSlot3 = 1;
13895let Defs = [USR_OVF];
13896let Constraints = "$Rxx32 = $Rxx32in";
13897}
13898def M2_cnacs_s1 : HInst<
13899(outs DoubleRegs:$Rxx32),
13900(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13901"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
13902tc_d773585a, TypeM>, Enc_61f0b0 {
13903let Inst{7-5} = 0b111;
13904let Inst{13-13} = 0b0;
13905let Inst{31-21} = 0b11100111100;
13906let prefersSlot3 = 1;
13907let Defs = [USR_OVF];
13908let Constraints = "$Rxx32 = $Rxx32in";
13909}
13910def M2_cnacsc_s0 : HInst<
13911(outs DoubleRegs:$Rxx32),
13912(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13913"$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
13914tc_d773585a, TypeM>, Enc_61f0b0 {
13915let Inst{7-5} = 0b111;
13916let Inst{13-13} = 0b0;
13917let Inst{31-21} = 0b11100111010;
13918let prefersSlot3 = 1;
13919let Defs = [USR_OVF];
13920let Constraints = "$Rxx32 = $Rxx32in";
13921}
13922def M2_cnacsc_s1 : HInst<
13923(outs DoubleRegs:$Rxx32),
13924(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13925"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
13926tc_d773585a, TypeM>, Enc_61f0b0 {
13927let Inst{7-5} = 0b111;
13928let Inst{13-13} = 0b0;
13929let Inst{31-21} = 0b11100111110;
13930let prefersSlot3 = 1;
13931let Defs = [USR_OVF];
13932let Constraints = "$Rxx32 = $Rxx32in";
13933}
13934def M2_dpmpyss_acc_s0 : HInst<
13935(outs DoubleRegs:$Rxx32),
13936(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13937"$Rxx32 += mpy($Rs32,$Rt32)",
13938tc_d773585a, TypeM>, Enc_61f0b0 {
13939let Inst{7-5} = 0b000;
13940let Inst{13-13} = 0b0;
13941let Inst{31-21} = 0b11100111000;
13942let prefersSlot3 = 1;
13943let Constraints = "$Rxx32 = $Rxx32in";
13944}
13945def M2_dpmpyss_nac_s0 : HInst<
13946(outs DoubleRegs:$Rxx32),
13947(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13948"$Rxx32 -= mpy($Rs32,$Rt32)",
13949tc_d773585a, TypeM>, Enc_61f0b0 {
13950let Inst{7-5} = 0b000;
13951let Inst{13-13} = 0b0;
13952let Inst{31-21} = 0b11100111001;
13953let prefersSlot3 = 1;
13954let Constraints = "$Rxx32 = $Rxx32in";
13955}
13956def M2_dpmpyss_rnd_s0 : HInst<
13957(outs IntRegs:$Rd32),
13958(ins IntRegs:$Rs32, IntRegs:$Rt32),
13959"$Rd32 = mpy($Rs32,$Rt32):rnd",
13960tc_bafaade3, TypeM>, Enc_5ab2be {
13961let Inst{7-5} = 0b001;
13962let Inst{13-13} = 0b0;
13963let Inst{31-21} = 0b11101101001;
13964let hasNewValue = 1;
13965let opNewValue = 0;
13966let prefersSlot3 = 1;
13967}
13968def M2_dpmpyss_s0 : HInst<
13969(outs DoubleRegs:$Rdd32),
13970(ins IntRegs:$Rs32, IntRegs:$Rt32),
13971"$Rdd32 = mpy($Rs32,$Rt32)",
13972tc_bafaade3, TypeM>, Enc_be32a5 {
13973let Inst{7-5} = 0b000;
13974let Inst{13-13} = 0b0;
13975let Inst{31-21} = 0b11100101000;
13976let prefersSlot3 = 1;
13977}
13978def M2_dpmpyuu_acc_s0 : HInst<
13979(outs DoubleRegs:$Rxx32),
13980(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13981"$Rxx32 += mpyu($Rs32,$Rt32)",
13982tc_d773585a, TypeM>, Enc_61f0b0 {
13983let Inst{7-5} = 0b000;
13984let Inst{13-13} = 0b0;
13985let Inst{31-21} = 0b11100111010;
13986let prefersSlot3 = 1;
13987let Constraints = "$Rxx32 = $Rxx32in";
13988}
13989def M2_dpmpyuu_nac_s0 : HInst<
13990(outs DoubleRegs:$Rxx32),
13991(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13992"$Rxx32 -= mpyu($Rs32,$Rt32)",
13993tc_d773585a, TypeM>, Enc_61f0b0 {
13994let Inst{7-5} = 0b000;
13995let Inst{13-13} = 0b0;
13996let Inst{31-21} = 0b11100111011;
13997let prefersSlot3 = 1;
13998let Constraints = "$Rxx32 = $Rxx32in";
13999}
14000def M2_dpmpyuu_s0 : HInst<
14001(outs DoubleRegs:$Rdd32),
14002(ins IntRegs:$Rs32, IntRegs:$Rt32),
14003"$Rdd32 = mpyu($Rs32,$Rt32)",
14004tc_bafaade3, TypeM>, Enc_be32a5 {
14005let Inst{7-5} = 0b000;
14006let Inst{13-13} = 0b0;
14007let Inst{31-21} = 0b11100101010;
14008let prefersSlot3 = 1;
14009}
14010def M2_hmmpyh_rs1 : HInst<
14011(outs IntRegs:$Rd32),
14012(ins IntRegs:$Rs32, IntRegs:$Rt32),
14013"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
14014tc_bafaade3, TypeM>, Enc_5ab2be {
14015let Inst{7-5} = 0b100;
14016let Inst{13-13} = 0b0;
14017let Inst{31-21} = 0b11101101101;
14018let hasNewValue = 1;
14019let opNewValue = 0;
14020let prefersSlot3 = 1;
14021let Defs = [USR_OVF];
14022}
14023def M2_hmmpyh_s1 : HInst<
14024(outs IntRegs:$Rd32),
14025(ins IntRegs:$Rs32, IntRegs:$Rt32),
14026"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
14027tc_bafaade3, TypeM>, Enc_5ab2be {
14028let Inst{7-5} = 0b000;
14029let Inst{13-13} = 0b0;
14030let Inst{31-21} = 0b11101101101;
14031let hasNewValue = 1;
14032let opNewValue = 0;
14033let prefersSlot3 = 1;
14034let Defs = [USR_OVF];
14035}
14036def M2_hmmpyl_rs1 : HInst<
14037(outs IntRegs:$Rd32),
14038(ins IntRegs:$Rs32, IntRegs:$Rt32),
14039"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
14040tc_bafaade3, TypeM>, Enc_5ab2be {
14041let Inst{7-5} = 0b100;
14042let Inst{13-13} = 0b0;
14043let Inst{31-21} = 0b11101101111;
14044let hasNewValue = 1;
14045let opNewValue = 0;
14046let prefersSlot3 = 1;
14047let Defs = [USR_OVF];
14048}
14049def M2_hmmpyl_s1 : HInst<
14050(outs IntRegs:$Rd32),
14051(ins IntRegs:$Rs32, IntRegs:$Rt32),
14052"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
14053tc_bafaade3, TypeM>, Enc_5ab2be {
14054let Inst{7-5} = 0b001;
14055let Inst{13-13} = 0b0;
14056let Inst{31-21} = 0b11101101101;
14057let hasNewValue = 1;
14058let opNewValue = 0;
14059let prefersSlot3 = 1;
14060let Defs = [USR_OVF];
14061}
14062def M2_maci : HInst<
14063(outs IntRegs:$Rx32),
14064(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14065"$Rx32 += mpyi($Rs32,$Rt32)",
14066tc_d773585a, TypeM>, Enc_2ae154, ImmRegRel {
14067let Inst{7-5} = 0b000;
14068let Inst{13-13} = 0b0;
14069let Inst{31-21} = 0b11101111000;
14070let hasNewValue = 1;
14071let opNewValue = 0;
14072let prefersSlot3 = 1;
14073let CextOpcode = "M2_maci";
14074let InputType = "reg";
14075let Constraints = "$Rx32 = $Rx32in";
14076}
14077def M2_macsin : HInst<
14078(outs IntRegs:$Rx32),
14079(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14080"$Rx32 -= mpyi($Rs32,#$Ii)",
14081tc_05d3a09b, TypeM>, Enc_c90aca {
14082let Inst{13-13} = 0b0;
14083let Inst{31-21} = 0b11100001100;
14084let hasNewValue = 1;
14085let opNewValue = 0;
14086let prefersSlot3 = 1;
14087let InputType = "imm";
14088let isExtendable = 1;
14089let opExtendable = 3;
14090let isExtentSigned = 0;
14091let opExtentBits = 8;
14092let opExtentAlign = 0;
14093let Constraints = "$Rx32 = $Rx32in";
14094}
14095def M2_macsip : HInst<
14096(outs IntRegs:$Rx32),
14097(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14098"$Rx32 += mpyi($Rs32,#$Ii)",
14099tc_05d3a09b, TypeM>, Enc_c90aca, ImmRegRel {
14100let Inst{13-13} = 0b0;
14101let Inst{31-21} = 0b11100001000;
14102let hasNewValue = 1;
14103let opNewValue = 0;
14104let prefersSlot3 = 1;
14105let CextOpcode = "M2_maci";
14106let InputType = "imm";
14107let isExtendable = 1;
14108let opExtendable = 3;
14109let isExtentSigned = 0;
14110let opExtentBits = 8;
14111let opExtentAlign = 0;
14112let Constraints = "$Rx32 = $Rx32in";
14113}
14114def M2_mmachs_rs0 : HInst<
14115(outs DoubleRegs:$Rxx32),
14116(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14117"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
14118tc_d773585a, TypeM>, Enc_88c16c {
14119let Inst{7-5} = 0b111;
14120let Inst{13-13} = 0b0;
14121let Inst{31-21} = 0b11101010001;
14122let prefersSlot3 = 1;
14123let Defs = [USR_OVF];
14124let Constraints = "$Rxx32 = $Rxx32in";
14125}
14126def M2_mmachs_rs1 : HInst<
14127(outs DoubleRegs:$Rxx32),
14128(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14129"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14130tc_d773585a, TypeM>, Enc_88c16c {
14131let Inst{7-5} = 0b111;
14132let Inst{13-13} = 0b0;
14133let Inst{31-21} = 0b11101010101;
14134let prefersSlot3 = 1;
14135let Defs = [USR_OVF];
14136let Constraints = "$Rxx32 = $Rxx32in";
14137}
14138def M2_mmachs_s0 : HInst<
14139(outs DoubleRegs:$Rxx32),
14140(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14141"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
14142tc_d773585a, TypeM>, Enc_88c16c {
14143let Inst{7-5} = 0b111;
14144let Inst{13-13} = 0b0;
14145let Inst{31-21} = 0b11101010000;
14146let prefersSlot3 = 1;
14147let Defs = [USR_OVF];
14148let Constraints = "$Rxx32 = $Rxx32in";
14149}
14150def M2_mmachs_s1 : HInst<
14151(outs DoubleRegs:$Rxx32),
14152(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14153"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
14154tc_d773585a, TypeM>, Enc_88c16c {
14155let Inst{7-5} = 0b111;
14156let Inst{13-13} = 0b0;
14157let Inst{31-21} = 0b11101010100;
14158let prefersSlot3 = 1;
14159let Defs = [USR_OVF];
14160let Constraints = "$Rxx32 = $Rxx32in";
14161}
14162def M2_mmacls_rs0 : HInst<
14163(outs DoubleRegs:$Rxx32),
14164(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14165"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
14166tc_d773585a, TypeM>, Enc_88c16c {
14167let Inst{7-5} = 0b101;
14168let Inst{13-13} = 0b0;
14169let Inst{31-21} = 0b11101010001;
14170let prefersSlot3 = 1;
14171let Defs = [USR_OVF];
14172let Constraints = "$Rxx32 = $Rxx32in";
14173}
14174def M2_mmacls_rs1 : HInst<
14175(outs DoubleRegs:$Rxx32),
14176(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14177"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14178tc_d773585a, TypeM>, Enc_88c16c {
14179let Inst{7-5} = 0b101;
14180let Inst{13-13} = 0b0;
14181let Inst{31-21} = 0b11101010101;
14182let prefersSlot3 = 1;
14183let Defs = [USR_OVF];
14184let Constraints = "$Rxx32 = $Rxx32in";
14185}
14186def M2_mmacls_s0 : HInst<
14187(outs DoubleRegs:$Rxx32),
14188(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14189"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
14190tc_d773585a, TypeM>, Enc_88c16c {
14191let Inst{7-5} = 0b101;
14192let Inst{13-13} = 0b0;
14193let Inst{31-21} = 0b11101010000;
14194let prefersSlot3 = 1;
14195let Defs = [USR_OVF];
14196let Constraints = "$Rxx32 = $Rxx32in";
14197}
14198def M2_mmacls_s1 : HInst<
14199(outs DoubleRegs:$Rxx32),
14200(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14201"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
14202tc_d773585a, TypeM>, Enc_88c16c {
14203let Inst{7-5} = 0b101;
14204let Inst{13-13} = 0b0;
14205let Inst{31-21} = 0b11101010100;
14206let prefersSlot3 = 1;
14207let Defs = [USR_OVF];
14208let Constraints = "$Rxx32 = $Rxx32in";
14209}
14210def M2_mmacuhs_rs0 : HInst<
14211(outs DoubleRegs:$Rxx32),
14212(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14213"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
14214tc_d773585a, TypeM>, Enc_88c16c {
14215let Inst{7-5} = 0b111;
14216let Inst{13-13} = 0b0;
14217let Inst{31-21} = 0b11101010011;
14218let prefersSlot3 = 1;
14219let Defs = [USR_OVF];
14220let Constraints = "$Rxx32 = $Rxx32in";
14221}
14222def M2_mmacuhs_rs1 : HInst<
14223(outs DoubleRegs:$Rxx32),
14224(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14225"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14226tc_d773585a, TypeM>, Enc_88c16c {
14227let Inst{7-5} = 0b111;
14228let Inst{13-13} = 0b0;
14229let Inst{31-21} = 0b11101010111;
14230let prefersSlot3 = 1;
14231let Defs = [USR_OVF];
14232let Constraints = "$Rxx32 = $Rxx32in";
14233}
14234def M2_mmacuhs_s0 : HInst<
14235(outs DoubleRegs:$Rxx32),
14236(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14237"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
14238tc_d773585a, TypeM>, Enc_88c16c {
14239let Inst{7-5} = 0b111;
14240let Inst{13-13} = 0b0;
14241let Inst{31-21} = 0b11101010010;
14242let prefersSlot3 = 1;
14243let Defs = [USR_OVF];
14244let Constraints = "$Rxx32 = $Rxx32in";
14245}
14246def M2_mmacuhs_s1 : HInst<
14247(outs DoubleRegs:$Rxx32),
14248(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14249"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
14250tc_d773585a, TypeM>, Enc_88c16c {
14251let Inst{7-5} = 0b111;
14252let Inst{13-13} = 0b0;
14253let Inst{31-21} = 0b11101010110;
14254let prefersSlot3 = 1;
14255let Defs = [USR_OVF];
14256let Constraints = "$Rxx32 = $Rxx32in";
14257}
14258def M2_mmaculs_rs0 : HInst<
14259(outs DoubleRegs:$Rxx32),
14260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14261"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
14262tc_d773585a, TypeM>, Enc_88c16c {
14263let Inst{7-5} = 0b101;
14264let Inst{13-13} = 0b0;
14265let Inst{31-21} = 0b11101010011;
14266let prefersSlot3 = 1;
14267let Defs = [USR_OVF];
14268let Constraints = "$Rxx32 = $Rxx32in";
14269}
14270def M2_mmaculs_rs1 : HInst<
14271(outs DoubleRegs:$Rxx32),
14272(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14273"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14274tc_d773585a, TypeM>, Enc_88c16c {
14275let Inst{7-5} = 0b101;
14276let Inst{13-13} = 0b0;
14277let Inst{31-21} = 0b11101010111;
14278let prefersSlot3 = 1;
14279let Defs = [USR_OVF];
14280let Constraints = "$Rxx32 = $Rxx32in";
14281}
14282def M2_mmaculs_s0 : HInst<
14283(outs DoubleRegs:$Rxx32),
14284(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14285"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
14286tc_d773585a, TypeM>, Enc_88c16c {
14287let Inst{7-5} = 0b101;
14288let Inst{13-13} = 0b0;
14289let Inst{31-21} = 0b11101010010;
14290let prefersSlot3 = 1;
14291let Defs = [USR_OVF];
14292let Constraints = "$Rxx32 = $Rxx32in";
14293}
14294def M2_mmaculs_s1 : HInst<
14295(outs DoubleRegs:$Rxx32),
14296(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14297"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
14298tc_d773585a, TypeM>, Enc_88c16c {
14299let Inst{7-5} = 0b101;
14300let Inst{13-13} = 0b0;
14301let Inst{31-21} = 0b11101010110;
14302let prefersSlot3 = 1;
14303let Defs = [USR_OVF];
14304let Constraints = "$Rxx32 = $Rxx32in";
14305}
14306def M2_mmpyh_rs0 : HInst<
14307(outs DoubleRegs:$Rdd32),
14308(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14309"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
14310tc_bafaade3, TypeM>, Enc_a56825 {
14311let Inst{7-5} = 0b111;
14312let Inst{13-13} = 0b0;
14313let Inst{31-21} = 0b11101000001;
14314let prefersSlot3 = 1;
14315let Defs = [USR_OVF];
14316}
14317def M2_mmpyh_rs1 : HInst<
14318(outs DoubleRegs:$Rdd32),
14319(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14320"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14321tc_bafaade3, TypeM>, Enc_a56825 {
14322let Inst{7-5} = 0b111;
14323let Inst{13-13} = 0b0;
14324let Inst{31-21} = 0b11101000101;
14325let prefersSlot3 = 1;
14326let Defs = [USR_OVF];
14327}
14328def M2_mmpyh_s0 : HInst<
14329(outs DoubleRegs:$Rdd32),
14330(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14331"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
14332tc_bafaade3, TypeM>, Enc_a56825 {
14333let Inst{7-5} = 0b111;
14334let Inst{13-13} = 0b0;
14335let Inst{31-21} = 0b11101000000;
14336let prefersSlot3 = 1;
14337let Defs = [USR_OVF];
14338}
14339def M2_mmpyh_s1 : HInst<
14340(outs DoubleRegs:$Rdd32),
14341(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14342"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
14343tc_bafaade3, TypeM>, Enc_a56825 {
14344let Inst{7-5} = 0b111;
14345let Inst{13-13} = 0b0;
14346let Inst{31-21} = 0b11101000100;
14347let prefersSlot3 = 1;
14348let Defs = [USR_OVF];
14349}
14350def M2_mmpyl_rs0 : HInst<
14351(outs DoubleRegs:$Rdd32),
14352(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14353"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
14354tc_bafaade3, TypeM>, Enc_a56825 {
14355let Inst{7-5} = 0b101;
14356let Inst{13-13} = 0b0;
14357let Inst{31-21} = 0b11101000001;
14358let prefersSlot3 = 1;
14359let Defs = [USR_OVF];
14360}
14361def M2_mmpyl_rs1 : HInst<
14362(outs DoubleRegs:$Rdd32),
14363(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14364"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14365tc_bafaade3, TypeM>, Enc_a56825 {
14366let Inst{7-5} = 0b101;
14367let Inst{13-13} = 0b0;
14368let Inst{31-21} = 0b11101000101;
14369let prefersSlot3 = 1;
14370let Defs = [USR_OVF];
14371}
14372def M2_mmpyl_s0 : HInst<
14373(outs DoubleRegs:$Rdd32),
14374(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14375"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
14376tc_bafaade3, TypeM>, Enc_a56825 {
14377let Inst{7-5} = 0b101;
14378let Inst{13-13} = 0b0;
14379let Inst{31-21} = 0b11101000000;
14380let prefersSlot3 = 1;
14381let Defs = [USR_OVF];
14382}
14383def M2_mmpyl_s1 : HInst<
14384(outs DoubleRegs:$Rdd32),
14385(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14386"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
14387tc_bafaade3, TypeM>, Enc_a56825 {
14388let Inst{7-5} = 0b101;
14389let Inst{13-13} = 0b0;
14390let Inst{31-21} = 0b11101000100;
14391let prefersSlot3 = 1;
14392let Defs = [USR_OVF];
14393}
14394def M2_mmpyuh_rs0 : HInst<
14395(outs DoubleRegs:$Rdd32),
14396(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14397"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
14398tc_bafaade3, TypeM>, Enc_a56825 {
14399let Inst{7-5} = 0b111;
14400let Inst{13-13} = 0b0;
14401let Inst{31-21} = 0b11101000011;
14402let prefersSlot3 = 1;
14403let Defs = [USR_OVF];
14404}
14405def M2_mmpyuh_rs1 : HInst<
14406(outs DoubleRegs:$Rdd32),
14407(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14408"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14409tc_bafaade3, TypeM>, Enc_a56825 {
14410let Inst{7-5} = 0b111;
14411let Inst{13-13} = 0b0;
14412let Inst{31-21} = 0b11101000111;
14413let prefersSlot3 = 1;
14414let Defs = [USR_OVF];
14415}
14416def M2_mmpyuh_s0 : HInst<
14417(outs DoubleRegs:$Rdd32),
14418(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14419"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
14420tc_bafaade3, TypeM>, Enc_a56825 {
14421let Inst{7-5} = 0b111;
14422let Inst{13-13} = 0b0;
14423let Inst{31-21} = 0b11101000010;
14424let prefersSlot3 = 1;
14425let Defs = [USR_OVF];
14426}
14427def M2_mmpyuh_s1 : HInst<
14428(outs DoubleRegs:$Rdd32),
14429(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14430"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
14431tc_bafaade3, TypeM>, Enc_a56825 {
14432let Inst{7-5} = 0b111;
14433let Inst{13-13} = 0b0;
14434let Inst{31-21} = 0b11101000110;
14435let prefersSlot3 = 1;
14436let Defs = [USR_OVF];
14437}
14438def M2_mmpyul_rs0 : HInst<
14439(outs DoubleRegs:$Rdd32),
14440(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14441"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
14442tc_bafaade3, TypeM>, Enc_a56825 {
14443let Inst{7-5} = 0b101;
14444let Inst{13-13} = 0b0;
14445let Inst{31-21} = 0b11101000011;
14446let prefersSlot3 = 1;
14447let Defs = [USR_OVF];
14448}
14449def M2_mmpyul_rs1 : HInst<
14450(outs DoubleRegs:$Rdd32),
14451(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14452"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14453tc_bafaade3, TypeM>, Enc_a56825 {
14454let Inst{7-5} = 0b101;
14455let Inst{13-13} = 0b0;
14456let Inst{31-21} = 0b11101000111;
14457let prefersSlot3 = 1;
14458let Defs = [USR_OVF];
14459}
14460def M2_mmpyul_s0 : HInst<
14461(outs DoubleRegs:$Rdd32),
14462(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14463"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
14464tc_bafaade3, TypeM>, Enc_a56825 {
14465let Inst{7-5} = 0b101;
14466let Inst{13-13} = 0b0;
14467let Inst{31-21} = 0b11101000010;
14468let prefersSlot3 = 1;
14469let Defs = [USR_OVF];
14470}
14471def M2_mmpyul_s1 : HInst<
14472(outs DoubleRegs:$Rdd32),
14473(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14474"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
14475tc_bafaade3, TypeM>, Enc_a56825 {
14476let Inst{7-5} = 0b101;
14477let Inst{13-13} = 0b0;
14478let Inst{31-21} = 0b11101000110;
14479let prefersSlot3 = 1;
14480let Defs = [USR_OVF];
14481}
14482def M2_mnaci : HInst<
14483(outs IntRegs:$Rx32),
14484(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14485"$Rx32 -= mpyi($Rs32,$Rt32)",
14486tc_bdceeac1, TypeM>, Enc_2ae154, Requires<[HasV66]> {
14487let Inst{7-5} = 0b000;
14488let Inst{13-13} = 0b0;
14489let Inst{31-21} = 0b11101111100;
14490let hasNewValue = 1;
14491let opNewValue = 0;
14492let prefersSlot3 = 1;
14493let Constraints = "$Rx32 = $Rx32in";
14494}
14495def M2_mpy_acc_hh_s0 : HInst<
14496(outs IntRegs:$Rx32),
14497(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14498"$Rx32 += mpy($Rs32.h,$Rt32.h)",
14499tc_d773585a, TypeM>, Enc_2ae154 {
14500let Inst{7-5} = 0b011;
14501let Inst{13-13} = 0b0;
14502let Inst{31-21} = 0b11101110000;
14503let hasNewValue = 1;
14504let opNewValue = 0;
14505let prefersSlot3 = 1;
14506let Constraints = "$Rx32 = $Rx32in";
14507}
14508def M2_mpy_acc_hh_s1 : HInst<
14509(outs IntRegs:$Rx32),
14510(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14511"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
14512tc_d773585a, TypeM>, Enc_2ae154 {
14513let Inst{7-5} = 0b011;
14514let Inst{13-13} = 0b0;
14515let Inst{31-21} = 0b11101110100;
14516let hasNewValue = 1;
14517let opNewValue = 0;
14518let prefersSlot3 = 1;
14519let Constraints = "$Rx32 = $Rx32in";
14520}
14521def M2_mpy_acc_hl_s0 : HInst<
14522(outs IntRegs:$Rx32),
14523(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14524"$Rx32 += mpy($Rs32.h,$Rt32.l)",
14525tc_d773585a, TypeM>, Enc_2ae154 {
14526let Inst{7-5} = 0b010;
14527let Inst{13-13} = 0b0;
14528let Inst{31-21} = 0b11101110000;
14529let hasNewValue = 1;
14530let opNewValue = 0;
14531let prefersSlot3 = 1;
14532let Constraints = "$Rx32 = $Rx32in";
14533}
14534def M2_mpy_acc_hl_s1 : HInst<
14535(outs IntRegs:$Rx32),
14536(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14537"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
14538tc_d773585a, TypeM>, Enc_2ae154 {
14539let Inst{7-5} = 0b010;
14540let Inst{13-13} = 0b0;
14541let Inst{31-21} = 0b11101110100;
14542let hasNewValue = 1;
14543let opNewValue = 0;
14544let prefersSlot3 = 1;
14545let Constraints = "$Rx32 = $Rx32in";
14546}
14547def M2_mpy_acc_lh_s0 : HInst<
14548(outs IntRegs:$Rx32),
14549(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14550"$Rx32 += mpy($Rs32.l,$Rt32.h)",
14551tc_d773585a, TypeM>, Enc_2ae154 {
14552let Inst{7-5} = 0b001;
14553let Inst{13-13} = 0b0;
14554let Inst{31-21} = 0b11101110000;
14555let hasNewValue = 1;
14556let opNewValue = 0;
14557let prefersSlot3 = 1;
14558let Constraints = "$Rx32 = $Rx32in";
14559}
14560def M2_mpy_acc_lh_s1 : HInst<
14561(outs IntRegs:$Rx32),
14562(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14563"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
14564tc_d773585a, TypeM>, Enc_2ae154 {
14565let Inst{7-5} = 0b001;
14566let Inst{13-13} = 0b0;
14567let Inst{31-21} = 0b11101110100;
14568let hasNewValue = 1;
14569let opNewValue = 0;
14570let prefersSlot3 = 1;
14571let Constraints = "$Rx32 = $Rx32in";
14572}
14573def M2_mpy_acc_ll_s0 : HInst<
14574(outs IntRegs:$Rx32),
14575(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14576"$Rx32 += mpy($Rs32.l,$Rt32.l)",
14577tc_d773585a, TypeM>, Enc_2ae154 {
14578let Inst{7-5} = 0b000;
14579let Inst{13-13} = 0b0;
14580let Inst{31-21} = 0b11101110000;
14581let hasNewValue = 1;
14582let opNewValue = 0;
14583let prefersSlot3 = 1;
14584let Constraints = "$Rx32 = $Rx32in";
14585}
14586def M2_mpy_acc_ll_s1 : HInst<
14587(outs IntRegs:$Rx32),
14588(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14589"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
14590tc_d773585a, TypeM>, Enc_2ae154 {
14591let Inst{7-5} = 0b000;
14592let Inst{13-13} = 0b0;
14593let Inst{31-21} = 0b11101110100;
14594let hasNewValue = 1;
14595let opNewValue = 0;
14596let prefersSlot3 = 1;
14597let Constraints = "$Rx32 = $Rx32in";
14598}
14599def M2_mpy_acc_sat_hh_s0 : HInst<
14600(outs IntRegs:$Rx32),
14601(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14602"$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
14603tc_d773585a, TypeM>, Enc_2ae154 {
14604let Inst{7-5} = 0b111;
14605let Inst{13-13} = 0b0;
14606let Inst{31-21} = 0b11101110000;
14607let hasNewValue = 1;
14608let opNewValue = 0;
14609let prefersSlot3 = 1;
14610let Defs = [USR_OVF];
14611let Constraints = "$Rx32 = $Rx32in";
14612}
14613def M2_mpy_acc_sat_hh_s1 : HInst<
14614(outs IntRegs:$Rx32),
14615(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14616"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
14617tc_d773585a, TypeM>, Enc_2ae154 {
14618let Inst{7-5} = 0b111;
14619let Inst{13-13} = 0b0;
14620let Inst{31-21} = 0b11101110100;
14621let hasNewValue = 1;
14622let opNewValue = 0;
14623let prefersSlot3 = 1;
14624let Defs = [USR_OVF];
14625let Constraints = "$Rx32 = $Rx32in";
14626}
14627def M2_mpy_acc_sat_hl_s0 : HInst<
14628(outs IntRegs:$Rx32),
14629(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14630"$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
14631tc_d773585a, TypeM>, Enc_2ae154 {
14632let Inst{7-5} = 0b110;
14633let Inst{13-13} = 0b0;
14634let Inst{31-21} = 0b11101110000;
14635let hasNewValue = 1;
14636let opNewValue = 0;
14637let prefersSlot3 = 1;
14638let Defs = [USR_OVF];
14639let Constraints = "$Rx32 = $Rx32in";
14640}
14641def M2_mpy_acc_sat_hl_s1 : HInst<
14642(outs IntRegs:$Rx32),
14643(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14644"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
14645tc_d773585a, TypeM>, Enc_2ae154 {
14646let Inst{7-5} = 0b110;
14647let Inst{13-13} = 0b0;
14648let Inst{31-21} = 0b11101110100;
14649let hasNewValue = 1;
14650let opNewValue = 0;
14651let prefersSlot3 = 1;
14652let Defs = [USR_OVF];
14653let Constraints = "$Rx32 = $Rx32in";
14654}
14655def M2_mpy_acc_sat_lh_s0 : HInst<
14656(outs IntRegs:$Rx32),
14657(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14658"$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
14659tc_d773585a, TypeM>, Enc_2ae154 {
14660let Inst{7-5} = 0b101;
14661let Inst{13-13} = 0b0;
14662let Inst{31-21} = 0b11101110000;
14663let hasNewValue = 1;
14664let opNewValue = 0;
14665let prefersSlot3 = 1;
14666let Defs = [USR_OVF];
14667let Constraints = "$Rx32 = $Rx32in";
14668}
14669def M2_mpy_acc_sat_lh_s1 : HInst<
14670(outs IntRegs:$Rx32),
14671(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14672"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
14673tc_d773585a, TypeM>, Enc_2ae154 {
14674let Inst{7-5} = 0b101;
14675let Inst{13-13} = 0b0;
14676let Inst{31-21} = 0b11101110100;
14677let hasNewValue = 1;
14678let opNewValue = 0;
14679let prefersSlot3 = 1;
14680let Defs = [USR_OVF];
14681let Constraints = "$Rx32 = $Rx32in";
14682}
14683def M2_mpy_acc_sat_ll_s0 : HInst<
14684(outs IntRegs:$Rx32),
14685(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14686"$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
14687tc_d773585a, TypeM>, Enc_2ae154 {
14688let Inst{7-5} = 0b100;
14689let Inst{13-13} = 0b0;
14690let Inst{31-21} = 0b11101110000;
14691let hasNewValue = 1;
14692let opNewValue = 0;
14693let prefersSlot3 = 1;
14694let Defs = [USR_OVF];
14695let Constraints = "$Rx32 = $Rx32in";
14696}
14697def M2_mpy_acc_sat_ll_s1 : HInst<
14698(outs IntRegs:$Rx32),
14699(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14700"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
14701tc_d773585a, TypeM>, Enc_2ae154 {
14702let Inst{7-5} = 0b100;
14703let Inst{13-13} = 0b0;
14704let Inst{31-21} = 0b11101110100;
14705let hasNewValue = 1;
14706let opNewValue = 0;
14707let prefersSlot3 = 1;
14708let Defs = [USR_OVF];
14709let Constraints = "$Rx32 = $Rx32in";
14710}
14711def M2_mpy_hh_s0 : HInst<
14712(outs IntRegs:$Rd32),
14713(ins IntRegs:$Rs32, IntRegs:$Rt32),
14714"$Rd32 = mpy($Rs32.h,$Rt32.h)",
14715tc_bafaade3, TypeM>, Enc_5ab2be {
14716let Inst{7-5} = 0b011;
14717let Inst{13-13} = 0b0;
14718let Inst{31-21} = 0b11101100000;
14719let hasNewValue = 1;
14720let opNewValue = 0;
14721let prefersSlot3 = 1;
14722}
14723def M2_mpy_hh_s1 : HInst<
14724(outs IntRegs:$Rd32),
14725(ins IntRegs:$Rs32, IntRegs:$Rt32),
14726"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
14727tc_bafaade3, TypeM>, Enc_5ab2be {
14728let Inst{7-5} = 0b011;
14729let Inst{13-13} = 0b0;
14730let Inst{31-21} = 0b11101100100;
14731let hasNewValue = 1;
14732let opNewValue = 0;
14733let prefersSlot3 = 1;
14734}
14735def M2_mpy_hl_s0 : HInst<
14736(outs IntRegs:$Rd32),
14737(ins IntRegs:$Rs32, IntRegs:$Rt32),
14738"$Rd32 = mpy($Rs32.h,$Rt32.l)",
14739tc_bafaade3, TypeM>, Enc_5ab2be {
14740let Inst{7-5} = 0b010;
14741let Inst{13-13} = 0b0;
14742let Inst{31-21} = 0b11101100000;
14743let hasNewValue = 1;
14744let opNewValue = 0;
14745let prefersSlot3 = 1;
14746}
14747def M2_mpy_hl_s1 : HInst<
14748(outs IntRegs:$Rd32),
14749(ins IntRegs:$Rs32, IntRegs:$Rt32),
14750"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
14751tc_bafaade3, TypeM>, Enc_5ab2be {
14752let Inst{7-5} = 0b010;
14753let Inst{13-13} = 0b0;
14754let Inst{31-21} = 0b11101100100;
14755let hasNewValue = 1;
14756let opNewValue = 0;
14757let prefersSlot3 = 1;
14758}
14759def M2_mpy_lh_s0 : HInst<
14760(outs IntRegs:$Rd32),
14761(ins IntRegs:$Rs32, IntRegs:$Rt32),
14762"$Rd32 = mpy($Rs32.l,$Rt32.h)",
14763tc_bafaade3, TypeM>, Enc_5ab2be {
14764let Inst{7-5} = 0b001;
14765let Inst{13-13} = 0b0;
14766let Inst{31-21} = 0b11101100000;
14767let hasNewValue = 1;
14768let opNewValue = 0;
14769let prefersSlot3 = 1;
14770}
14771def M2_mpy_lh_s1 : HInst<
14772(outs IntRegs:$Rd32),
14773(ins IntRegs:$Rs32, IntRegs:$Rt32),
14774"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
14775tc_bafaade3, TypeM>, Enc_5ab2be {
14776let Inst{7-5} = 0b001;
14777let Inst{13-13} = 0b0;
14778let Inst{31-21} = 0b11101100100;
14779let hasNewValue = 1;
14780let opNewValue = 0;
14781let prefersSlot3 = 1;
14782}
14783def M2_mpy_ll_s0 : HInst<
14784(outs IntRegs:$Rd32),
14785(ins IntRegs:$Rs32, IntRegs:$Rt32),
14786"$Rd32 = mpy($Rs32.l,$Rt32.l)",
14787tc_bafaade3, TypeM>, Enc_5ab2be {
14788let Inst{7-5} = 0b000;
14789let Inst{13-13} = 0b0;
14790let Inst{31-21} = 0b11101100000;
14791let hasNewValue = 1;
14792let opNewValue = 0;
14793let prefersSlot3 = 1;
14794}
14795def M2_mpy_ll_s1 : HInst<
14796(outs IntRegs:$Rd32),
14797(ins IntRegs:$Rs32, IntRegs:$Rt32),
14798"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
14799tc_bafaade3, TypeM>, Enc_5ab2be {
14800let Inst{7-5} = 0b000;
14801let Inst{13-13} = 0b0;
14802let Inst{31-21} = 0b11101100100;
14803let hasNewValue = 1;
14804let opNewValue = 0;
14805let prefersSlot3 = 1;
14806}
14807def M2_mpy_nac_hh_s0 : HInst<
14808(outs IntRegs:$Rx32),
14809(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14810"$Rx32 -= mpy($Rs32.h,$Rt32.h)",
14811tc_d773585a, TypeM>, Enc_2ae154 {
14812let Inst{7-5} = 0b011;
14813let Inst{13-13} = 0b0;
14814let Inst{31-21} = 0b11101110001;
14815let hasNewValue = 1;
14816let opNewValue = 0;
14817let prefersSlot3 = 1;
14818let Constraints = "$Rx32 = $Rx32in";
14819}
14820def M2_mpy_nac_hh_s1 : HInst<
14821(outs IntRegs:$Rx32),
14822(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14823"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
14824tc_d773585a, TypeM>, Enc_2ae154 {
14825let Inst{7-5} = 0b011;
14826let Inst{13-13} = 0b0;
14827let Inst{31-21} = 0b11101110101;
14828let hasNewValue = 1;
14829let opNewValue = 0;
14830let prefersSlot3 = 1;
14831let Constraints = "$Rx32 = $Rx32in";
14832}
14833def M2_mpy_nac_hl_s0 : HInst<
14834(outs IntRegs:$Rx32),
14835(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14836"$Rx32 -= mpy($Rs32.h,$Rt32.l)",
14837tc_d773585a, TypeM>, Enc_2ae154 {
14838let Inst{7-5} = 0b010;
14839let Inst{13-13} = 0b0;
14840let Inst{31-21} = 0b11101110001;
14841let hasNewValue = 1;
14842let opNewValue = 0;
14843let prefersSlot3 = 1;
14844let Constraints = "$Rx32 = $Rx32in";
14845}
14846def M2_mpy_nac_hl_s1 : HInst<
14847(outs IntRegs:$Rx32),
14848(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14849"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
14850tc_d773585a, TypeM>, Enc_2ae154 {
14851let Inst{7-5} = 0b010;
14852let Inst{13-13} = 0b0;
14853let Inst{31-21} = 0b11101110101;
14854let hasNewValue = 1;
14855let opNewValue = 0;
14856let prefersSlot3 = 1;
14857let Constraints = "$Rx32 = $Rx32in";
14858}
14859def M2_mpy_nac_lh_s0 : HInst<
14860(outs IntRegs:$Rx32),
14861(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14862"$Rx32 -= mpy($Rs32.l,$Rt32.h)",
14863tc_d773585a, TypeM>, Enc_2ae154 {
14864let Inst{7-5} = 0b001;
14865let Inst{13-13} = 0b0;
14866let Inst{31-21} = 0b11101110001;
14867let hasNewValue = 1;
14868let opNewValue = 0;
14869let prefersSlot3 = 1;
14870let Constraints = "$Rx32 = $Rx32in";
14871}
14872def M2_mpy_nac_lh_s1 : HInst<
14873(outs IntRegs:$Rx32),
14874(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14875"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
14876tc_d773585a, TypeM>, Enc_2ae154 {
14877let Inst{7-5} = 0b001;
14878let Inst{13-13} = 0b0;
14879let Inst{31-21} = 0b11101110101;
14880let hasNewValue = 1;
14881let opNewValue = 0;
14882let prefersSlot3 = 1;
14883let Constraints = "$Rx32 = $Rx32in";
14884}
14885def M2_mpy_nac_ll_s0 : HInst<
14886(outs IntRegs:$Rx32),
14887(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14888"$Rx32 -= mpy($Rs32.l,$Rt32.l)",
14889tc_d773585a, TypeM>, Enc_2ae154 {
14890let Inst{7-5} = 0b000;
14891let Inst{13-13} = 0b0;
14892let Inst{31-21} = 0b11101110001;
14893let hasNewValue = 1;
14894let opNewValue = 0;
14895let prefersSlot3 = 1;
14896let Constraints = "$Rx32 = $Rx32in";
14897}
14898def M2_mpy_nac_ll_s1 : HInst<
14899(outs IntRegs:$Rx32),
14900(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14901"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
14902tc_d773585a, TypeM>, Enc_2ae154 {
14903let Inst{7-5} = 0b000;
14904let Inst{13-13} = 0b0;
14905let Inst{31-21} = 0b11101110101;
14906let hasNewValue = 1;
14907let opNewValue = 0;
14908let prefersSlot3 = 1;
14909let Constraints = "$Rx32 = $Rx32in";
14910}
14911def M2_mpy_nac_sat_hh_s0 : HInst<
14912(outs IntRegs:$Rx32),
14913(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14914"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
14915tc_d773585a, TypeM>, Enc_2ae154 {
14916let Inst{7-5} = 0b111;
14917let Inst{13-13} = 0b0;
14918let Inst{31-21} = 0b11101110001;
14919let hasNewValue = 1;
14920let opNewValue = 0;
14921let prefersSlot3 = 1;
14922let Defs = [USR_OVF];
14923let Constraints = "$Rx32 = $Rx32in";
14924}
14925def M2_mpy_nac_sat_hh_s1 : HInst<
14926(outs IntRegs:$Rx32),
14927(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14928"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
14929tc_d773585a, TypeM>, Enc_2ae154 {
14930let Inst{7-5} = 0b111;
14931let Inst{13-13} = 0b0;
14932let Inst{31-21} = 0b11101110101;
14933let hasNewValue = 1;
14934let opNewValue = 0;
14935let prefersSlot3 = 1;
14936let Defs = [USR_OVF];
14937let Constraints = "$Rx32 = $Rx32in";
14938}
14939def M2_mpy_nac_sat_hl_s0 : HInst<
14940(outs IntRegs:$Rx32),
14941(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14942"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
14943tc_d773585a, TypeM>, Enc_2ae154 {
14944let Inst{7-5} = 0b110;
14945let Inst{13-13} = 0b0;
14946let Inst{31-21} = 0b11101110001;
14947let hasNewValue = 1;
14948let opNewValue = 0;
14949let prefersSlot3 = 1;
14950let Defs = [USR_OVF];
14951let Constraints = "$Rx32 = $Rx32in";
14952}
14953def M2_mpy_nac_sat_hl_s1 : HInst<
14954(outs IntRegs:$Rx32),
14955(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14956"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
14957tc_d773585a, TypeM>, Enc_2ae154 {
14958let Inst{7-5} = 0b110;
14959let Inst{13-13} = 0b0;
14960let Inst{31-21} = 0b11101110101;
14961let hasNewValue = 1;
14962let opNewValue = 0;
14963let prefersSlot3 = 1;
14964let Defs = [USR_OVF];
14965let Constraints = "$Rx32 = $Rx32in";
14966}
14967def M2_mpy_nac_sat_lh_s0 : HInst<
14968(outs IntRegs:$Rx32),
14969(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14970"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
14971tc_d773585a, TypeM>, Enc_2ae154 {
14972let Inst{7-5} = 0b101;
14973let Inst{13-13} = 0b0;
14974let Inst{31-21} = 0b11101110001;
14975let hasNewValue = 1;
14976let opNewValue = 0;
14977let prefersSlot3 = 1;
14978let Defs = [USR_OVF];
14979let Constraints = "$Rx32 = $Rx32in";
14980}
14981def M2_mpy_nac_sat_lh_s1 : HInst<
14982(outs IntRegs:$Rx32),
14983(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14984"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
14985tc_d773585a, TypeM>, Enc_2ae154 {
14986let Inst{7-5} = 0b101;
14987let Inst{13-13} = 0b0;
14988let Inst{31-21} = 0b11101110101;
14989let hasNewValue = 1;
14990let opNewValue = 0;
14991let prefersSlot3 = 1;
14992let Defs = [USR_OVF];
14993let Constraints = "$Rx32 = $Rx32in";
14994}
14995def M2_mpy_nac_sat_ll_s0 : HInst<
14996(outs IntRegs:$Rx32),
14997(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14998"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
14999tc_d773585a, TypeM>, Enc_2ae154 {
15000let Inst{7-5} = 0b100;
15001let Inst{13-13} = 0b0;
15002let Inst{31-21} = 0b11101110001;
15003let hasNewValue = 1;
15004let opNewValue = 0;
15005let prefersSlot3 = 1;
15006let Defs = [USR_OVF];
15007let Constraints = "$Rx32 = $Rx32in";
15008}
15009def M2_mpy_nac_sat_ll_s1 : HInst<
15010(outs IntRegs:$Rx32),
15011(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15012"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
15013tc_d773585a, TypeM>, Enc_2ae154 {
15014let Inst{7-5} = 0b100;
15015let Inst{13-13} = 0b0;
15016let Inst{31-21} = 0b11101110101;
15017let hasNewValue = 1;
15018let opNewValue = 0;
15019let prefersSlot3 = 1;
15020let Defs = [USR_OVF];
15021let Constraints = "$Rx32 = $Rx32in";
15022}
15023def M2_mpy_rnd_hh_s0 : HInst<
15024(outs IntRegs:$Rd32),
15025(ins IntRegs:$Rs32, IntRegs:$Rt32),
15026"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
15027tc_bafaade3, TypeM>, Enc_5ab2be {
15028let Inst{7-5} = 0b011;
15029let Inst{13-13} = 0b0;
15030let Inst{31-21} = 0b11101100001;
15031let hasNewValue = 1;
15032let opNewValue = 0;
15033let prefersSlot3 = 1;
15034}
15035def M2_mpy_rnd_hh_s1 : HInst<
15036(outs IntRegs:$Rd32),
15037(ins IntRegs:$Rs32, IntRegs:$Rt32),
15038"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15039tc_bafaade3, TypeM>, Enc_5ab2be {
15040let Inst{7-5} = 0b011;
15041let Inst{13-13} = 0b0;
15042let Inst{31-21} = 0b11101100101;
15043let hasNewValue = 1;
15044let opNewValue = 0;
15045let prefersSlot3 = 1;
15046}
15047def M2_mpy_rnd_hl_s0 : HInst<
15048(outs IntRegs:$Rd32),
15049(ins IntRegs:$Rs32, IntRegs:$Rt32),
15050"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
15051tc_bafaade3, TypeM>, Enc_5ab2be {
15052let Inst{7-5} = 0b010;
15053let Inst{13-13} = 0b0;
15054let Inst{31-21} = 0b11101100001;
15055let hasNewValue = 1;
15056let opNewValue = 0;
15057let prefersSlot3 = 1;
15058}
15059def M2_mpy_rnd_hl_s1 : HInst<
15060(outs IntRegs:$Rd32),
15061(ins IntRegs:$Rs32, IntRegs:$Rt32),
15062"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15063tc_bafaade3, TypeM>, Enc_5ab2be {
15064let Inst{7-5} = 0b010;
15065let Inst{13-13} = 0b0;
15066let Inst{31-21} = 0b11101100101;
15067let hasNewValue = 1;
15068let opNewValue = 0;
15069let prefersSlot3 = 1;
15070}
15071def M2_mpy_rnd_lh_s0 : HInst<
15072(outs IntRegs:$Rd32),
15073(ins IntRegs:$Rs32, IntRegs:$Rt32),
15074"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
15075tc_bafaade3, TypeM>, Enc_5ab2be {
15076let Inst{7-5} = 0b001;
15077let Inst{13-13} = 0b0;
15078let Inst{31-21} = 0b11101100001;
15079let hasNewValue = 1;
15080let opNewValue = 0;
15081let prefersSlot3 = 1;
15082}
15083def M2_mpy_rnd_lh_s1 : HInst<
15084(outs IntRegs:$Rd32),
15085(ins IntRegs:$Rs32, IntRegs:$Rt32),
15086"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15087tc_bafaade3, TypeM>, Enc_5ab2be {
15088let Inst{7-5} = 0b001;
15089let Inst{13-13} = 0b0;
15090let Inst{31-21} = 0b11101100101;
15091let hasNewValue = 1;
15092let opNewValue = 0;
15093let prefersSlot3 = 1;
15094}
15095def M2_mpy_rnd_ll_s0 : HInst<
15096(outs IntRegs:$Rd32),
15097(ins IntRegs:$Rs32, IntRegs:$Rt32),
15098"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
15099tc_bafaade3, TypeM>, Enc_5ab2be {
15100let Inst{7-5} = 0b000;
15101let Inst{13-13} = 0b0;
15102let Inst{31-21} = 0b11101100001;
15103let hasNewValue = 1;
15104let opNewValue = 0;
15105let prefersSlot3 = 1;
15106}
15107def M2_mpy_rnd_ll_s1 : HInst<
15108(outs IntRegs:$Rd32),
15109(ins IntRegs:$Rs32, IntRegs:$Rt32),
15110"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15111tc_bafaade3, TypeM>, Enc_5ab2be {
15112let Inst{7-5} = 0b000;
15113let Inst{13-13} = 0b0;
15114let Inst{31-21} = 0b11101100101;
15115let hasNewValue = 1;
15116let opNewValue = 0;
15117let prefersSlot3 = 1;
15118}
15119def M2_mpy_sat_hh_s0 : HInst<
15120(outs IntRegs:$Rd32),
15121(ins IntRegs:$Rs32, IntRegs:$Rt32),
15122"$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
15123tc_bafaade3, TypeM>, Enc_5ab2be {
15124let Inst{7-5} = 0b111;
15125let Inst{13-13} = 0b0;
15126let Inst{31-21} = 0b11101100000;
15127let hasNewValue = 1;
15128let opNewValue = 0;
15129let prefersSlot3 = 1;
15130let Defs = [USR_OVF];
15131}
15132def M2_mpy_sat_hh_s1 : HInst<
15133(outs IntRegs:$Rd32),
15134(ins IntRegs:$Rs32, IntRegs:$Rt32),
15135"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
15136tc_bafaade3, TypeM>, Enc_5ab2be {
15137let Inst{7-5} = 0b111;
15138let Inst{13-13} = 0b0;
15139let Inst{31-21} = 0b11101100100;
15140let hasNewValue = 1;
15141let opNewValue = 0;
15142let prefersSlot3 = 1;
15143let Defs = [USR_OVF];
15144}
15145def M2_mpy_sat_hl_s0 : HInst<
15146(outs IntRegs:$Rd32),
15147(ins IntRegs:$Rs32, IntRegs:$Rt32),
15148"$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
15149tc_bafaade3, TypeM>, Enc_5ab2be {
15150let Inst{7-5} = 0b110;
15151let Inst{13-13} = 0b0;
15152let Inst{31-21} = 0b11101100000;
15153let hasNewValue = 1;
15154let opNewValue = 0;
15155let prefersSlot3 = 1;
15156let Defs = [USR_OVF];
15157}
15158def M2_mpy_sat_hl_s1 : HInst<
15159(outs IntRegs:$Rd32),
15160(ins IntRegs:$Rs32, IntRegs:$Rt32),
15161"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
15162tc_bafaade3, TypeM>, Enc_5ab2be {
15163let Inst{7-5} = 0b110;
15164let Inst{13-13} = 0b0;
15165let Inst{31-21} = 0b11101100100;
15166let hasNewValue = 1;
15167let opNewValue = 0;
15168let prefersSlot3 = 1;
15169let Defs = [USR_OVF];
15170}
15171def M2_mpy_sat_lh_s0 : HInst<
15172(outs IntRegs:$Rd32),
15173(ins IntRegs:$Rs32, IntRegs:$Rt32),
15174"$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
15175tc_bafaade3, TypeM>, Enc_5ab2be {
15176let Inst{7-5} = 0b101;
15177let Inst{13-13} = 0b0;
15178let Inst{31-21} = 0b11101100000;
15179let hasNewValue = 1;
15180let opNewValue = 0;
15181let prefersSlot3 = 1;
15182let Defs = [USR_OVF];
15183}
15184def M2_mpy_sat_lh_s1 : HInst<
15185(outs IntRegs:$Rd32),
15186(ins IntRegs:$Rs32, IntRegs:$Rt32),
15187"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
15188tc_bafaade3, TypeM>, Enc_5ab2be {
15189let Inst{7-5} = 0b101;
15190let Inst{13-13} = 0b0;
15191let Inst{31-21} = 0b11101100100;
15192let hasNewValue = 1;
15193let opNewValue = 0;
15194let prefersSlot3 = 1;
15195let Defs = [USR_OVF];
15196}
15197def M2_mpy_sat_ll_s0 : HInst<
15198(outs IntRegs:$Rd32),
15199(ins IntRegs:$Rs32, IntRegs:$Rt32),
15200"$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
15201tc_bafaade3, TypeM>, Enc_5ab2be {
15202let Inst{7-5} = 0b100;
15203let Inst{13-13} = 0b0;
15204let Inst{31-21} = 0b11101100000;
15205let hasNewValue = 1;
15206let opNewValue = 0;
15207let prefersSlot3 = 1;
15208let Defs = [USR_OVF];
15209}
15210def M2_mpy_sat_ll_s1 : HInst<
15211(outs IntRegs:$Rd32),
15212(ins IntRegs:$Rs32, IntRegs:$Rt32),
15213"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
15214tc_bafaade3, TypeM>, Enc_5ab2be {
15215let Inst{7-5} = 0b100;
15216let Inst{13-13} = 0b0;
15217let Inst{31-21} = 0b11101100100;
15218let hasNewValue = 1;
15219let opNewValue = 0;
15220let prefersSlot3 = 1;
15221let Defs = [USR_OVF];
15222}
15223def M2_mpy_sat_rnd_hh_s0 : HInst<
15224(outs IntRegs:$Rd32),
15225(ins IntRegs:$Rs32, IntRegs:$Rt32),
15226"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
15227tc_bafaade3, TypeM>, Enc_5ab2be {
15228let Inst{7-5} = 0b111;
15229let Inst{13-13} = 0b0;
15230let Inst{31-21} = 0b11101100001;
15231let hasNewValue = 1;
15232let opNewValue = 0;
15233let prefersSlot3 = 1;
15234let Defs = [USR_OVF];
15235}
15236def M2_mpy_sat_rnd_hh_s1 : HInst<
15237(outs IntRegs:$Rd32),
15238(ins IntRegs:$Rs32, IntRegs:$Rt32),
15239"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
15240tc_bafaade3, TypeM>, Enc_5ab2be {
15241let Inst{7-5} = 0b111;
15242let Inst{13-13} = 0b0;
15243let Inst{31-21} = 0b11101100101;
15244let hasNewValue = 1;
15245let opNewValue = 0;
15246let prefersSlot3 = 1;
15247let Defs = [USR_OVF];
15248}
15249def M2_mpy_sat_rnd_hl_s0 : HInst<
15250(outs IntRegs:$Rd32),
15251(ins IntRegs:$Rs32, IntRegs:$Rt32),
15252"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
15253tc_bafaade3, TypeM>, Enc_5ab2be {
15254let Inst{7-5} = 0b110;
15255let Inst{13-13} = 0b0;
15256let Inst{31-21} = 0b11101100001;
15257let hasNewValue = 1;
15258let opNewValue = 0;
15259let prefersSlot3 = 1;
15260let Defs = [USR_OVF];
15261}
15262def M2_mpy_sat_rnd_hl_s1 : HInst<
15263(outs IntRegs:$Rd32),
15264(ins IntRegs:$Rs32, IntRegs:$Rt32),
15265"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
15266tc_bafaade3, TypeM>, Enc_5ab2be {
15267let Inst{7-5} = 0b110;
15268let Inst{13-13} = 0b0;
15269let Inst{31-21} = 0b11101100101;
15270let hasNewValue = 1;
15271let opNewValue = 0;
15272let prefersSlot3 = 1;
15273let Defs = [USR_OVF];
15274}
15275def M2_mpy_sat_rnd_lh_s0 : HInst<
15276(outs IntRegs:$Rd32),
15277(ins IntRegs:$Rs32, IntRegs:$Rt32),
15278"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
15279tc_bafaade3, TypeM>, Enc_5ab2be {
15280let Inst{7-5} = 0b101;
15281let Inst{13-13} = 0b0;
15282let Inst{31-21} = 0b11101100001;
15283let hasNewValue = 1;
15284let opNewValue = 0;
15285let prefersSlot3 = 1;
15286let Defs = [USR_OVF];
15287}
15288def M2_mpy_sat_rnd_lh_s1 : HInst<
15289(outs IntRegs:$Rd32),
15290(ins IntRegs:$Rs32, IntRegs:$Rt32),
15291"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
15292tc_bafaade3, TypeM>, Enc_5ab2be {
15293let Inst{7-5} = 0b101;
15294let Inst{13-13} = 0b0;
15295let Inst{31-21} = 0b11101100101;
15296let hasNewValue = 1;
15297let opNewValue = 0;
15298let prefersSlot3 = 1;
15299let Defs = [USR_OVF];
15300}
15301def M2_mpy_sat_rnd_ll_s0 : HInst<
15302(outs IntRegs:$Rd32),
15303(ins IntRegs:$Rs32, IntRegs:$Rt32),
15304"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
15305tc_bafaade3, TypeM>, Enc_5ab2be {
15306let Inst{7-5} = 0b100;
15307let Inst{13-13} = 0b0;
15308let Inst{31-21} = 0b11101100001;
15309let hasNewValue = 1;
15310let opNewValue = 0;
15311let prefersSlot3 = 1;
15312let Defs = [USR_OVF];
15313}
15314def M2_mpy_sat_rnd_ll_s1 : HInst<
15315(outs IntRegs:$Rd32),
15316(ins IntRegs:$Rs32, IntRegs:$Rt32),
15317"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
15318tc_bafaade3, TypeM>, Enc_5ab2be {
15319let Inst{7-5} = 0b100;
15320let Inst{13-13} = 0b0;
15321let Inst{31-21} = 0b11101100101;
15322let hasNewValue = 1;
15323let opNewValue = 0;
15324let prefersSlot3 = 1;
15325let Defs = [USR_OVF];
15326}
15327def M2_mpy_up : HInst<
15328(outs IntRegs:$Rd32),
15329(ins IntRegs:$Rs32, IntRegs:$Rt32),
15330"$Rd32 = mpy($Rs32,$Rt32)",
15331tc_bafaade3, TypeM>, Enc_5ab2be {
15332let Inst{7-5} = 0b001;
15333let Inst{13-13} = 0b0;
15334let Inst{31-21} = 0b11101101000;
15335let hasNewValue = 1;
15336let opNewValue = 0;
15337let prefersSlot3 = 1;
15338}
15339def M2_mpy_up_s1 : HInst<
15340(outs IntRegs:$Rd32),
15341(ins IntRegs:$Rs32, IntRegs:$Rt32),
15342"$Rd32 = mpy($Rs32,$Rt32):<<1",
15343tc_bafaade3, TypeM>, Enc_5ab2be {
15344let Inst{7-5} = 0b010;
15345let Inst{13-13} = 0b0;
15346let Inst{31-21} = 0b11101101101;
15347let hasNewValue = 1;
15348let opNewValue = 0;
15349let prefersSlot3 = 1;
15350}
15351def M2_mpy_up_s1_sat : HInst<
15352(outs IntRegs:$Rd32),
15353(ins IntRegs:$Rs32, IntRegs:$Rt32),
15354"$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
15355tc_bafaade3, TypeM>, Enc_5ab2be {
15356let Inst{7-5} = 0b000;
15357let Inst{13-13} = 0b0;
15358let Inst{31-21} = 0b11101101111;
15359let hasNewValue = 1;
15360let opNewValue = 0;
15361let prefersSlot3 = 1;
15362let Defs = [USR_OVF];
15363}
15364def M2_mpyd_acc_hh_s0 : HInst<
15365(outs DoubleRegs:$Rxx32),
15366(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15367"$Rxx32 += mpy($Rs32.h,$Rt32.h)",
15368tc_d773585a, TypeM>, Enc_61f0b0 {
15369let Inst{7-5} = 0b011;
15370let Inst{13-13} = 0b0;
15371let Inst{31-21} = 0b11100110000;
15372let prefersSlot3 = 1;
15373let Constraints = "$Rxx32 = $Rxx32in";
15374}
15375def M2_mpyd_acc_hh_s1 : HInst<
15376(outs DoubleRegs:$Rxx32),
15377(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15378"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
15379tc_d773585a, TypeM>, Enc_61f0b0 {
15380let Inst{7-5} = 0b011;
15381let Inst{13-13} = 0b0;
15382let Inst{31-21} = 0b11100110100;
15383let prefersSlot3 = 1;
15384let Constraints = "$Rxx32 = $Rxx32in";
15385}
15386def M2_mpyd_acc_hl_s0 : HInst<
15387(outs DoubleRegs:$Rxx32),
15388(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15389"$Rxx32 += mpy($Rs32.h,$Rt32.l)",
15390tc_d773585a, TypeM>, Enc_61f0b0 {
15391let Inst{7-5} = 0b010;
15392let Inst{13-13} = 0b0;
15393let Inst{31-21} = 0b11100110000;
15394let prefersSlot3 = 1;
15395let Constraints = "$Rxx32 = $Rxx32in";
15396}
15397def M2_mpyd_acc_hl_s1 : HInst<
15398(outs DoubleRegs:$Rxx32),
15399(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15400"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
15401tc_d773585a, TypeM>, Enc_61f0b0 {
15402let Inst{7-5} = 0b010;
15403let Inst{13-13} = 0b0;
15404let Inst{31-21} = 0b11100110100;
15405let prefersSlot3 = 1;
15406let Constraints = "$Rxx32 = $Rxx32in";
15407}
15408def M2_mpyd_acc_lh_s0 : HInst<
15409(outs DoubleRegs:$Rxx32),
15410(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15411"$Rxx32 += mpy($Rs32.l,$Rt32.h)",
15412tc_d773585a, TypeM>, Enc_61f0b0 {
15413let Inst{7-5} = 0b001;
15414let Inst{13-13} = 0b0;
15415let Inst{31-21} = 0b11100110000;
15416let prefersSlot3 = 1;
15417let Constraints = "$Rxx32 = $Rxx32in";
15418}
15419def M2_mpyd_acc_lh_s1 : HInst<
15420(outs DoubleRegs:$Rxx32),
15421(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15422"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
15423tc_d773585a, TypeM>, Enc_61f0b0 {
15424let Inst{7-5} = 0b001;
15425let Inst{13-13} = 0b0;
15426let Inst{31-21} = 0b11100110100;
15427let prefersSlot3 = 1;
15428let Constraints = "$Rxx32 = $Rxx32in";
15429}
15430def M2_mpyd_acc_ll_s0 : HInst<
15431(outs DoubleRegs:$Rxx32),
15432(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15433"$Rxx32 += mpy($Rs32.l,$Rt32.l)",
15434tc_d773585a, TypeM>, Enc_61f0b0 {
15435let Inst{7-5} = 0b000;
15436let Inst{13-13} = 0b0;
15437let Inst{31-21} = 0b11100110000;
15438let prefersSlot3 = 1;
15439let Constraints = "$Rxx32 = $Rxx32in";
15440}
15441def M2_mpyd_acc_ll_s1 : HInst<
15442(outs DoubleRegs:$Rxx32),
15443(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15444"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
15445tc_d773585a, TypeM>, Enc_61f0b0 {
15446let Inst{7-5} = 0b000;
15447let Inst{13-13} = 0b0;
15448let Inst{31-21} = 0b11100110100;
15449let prefersSlot3 = 1;
15450let Constraints = "$Rxx32 = $Rxx32in";
15451}
15452def M2_mpyd_hh_s0 : HInst<
15453(outs DoubleRegs:$Rdd32),
15454(ins IntRegs:$Rs32, IntRegs:$Rt32),
15455"$Rdd32 = mpy($Rs32.h,$Rt32.h)",
15456tc_bafaade3, TypeM>, Enc_be32a5 {
15457let Inst{7-5} = 0b011;
15458let Inst{13-13} = 0b0;
15459let Inst{31-21} = 0b11100100000;
15460let prefersSlot3 = 1;
15461}
15462def M2_mpyd_hh_s1 : HInst<
15463(outs DoubleRegs:$Rdd32),
15464(ins IntRegs:$Rs32, IntRegs:$Rt32),
15465"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
15466tc_bafaade3, TypeM>, Enc_be32a5 {
15467let Inst{7-5} = 0b011;
15468let Inst{13-13} = 0b0;
15469let Inst{31-21} = 0b11100100100;
15470let prefersSlot3 = 1;
15471}
15472def M2_mpyd_hl_s0 : HInst<
15473(outs DoubleRegs:$Rdd32),
15474(ins IntRegs:$Rs32, IntRegs:$Rt32),
15475"$Rdd32 = mpy($Rs32.h,$Rt32.l)",
15476tc_bafaade3, TypeM>, Enc_be32a5 {
15477let Inst{7-5} = 0b010;
15478let Inst{13-13} = 0b0;
15479let Inst{31-21} = 0b11100100000;
15480let prefersSlot3 = 1;
15481}
15482def M2_mpyd_hl_s1 : HInst<
15483(outs DoubleRegs:$Rdd32),
15484(ins IntRegs:$Rs32, IntRegs:$Rt32),
15485"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
15486tc_bafaade3, TypeM>, Enc_be32a5 {
15487let Inst{7-5} = 0b010;
15488let Inst{13-13} = 0b0;
15489let Inst{31-21} = 0b11100100100;
15490let prefersSlot3 = 1;
15491}
15492def M2_mpyd_lh_s0 : HInst<
15493(outs DoubleRegs:$Rdd32),
15494(ins IntRegs:$Rs32, IntRegs:$Rt32),
15495"$Rdd32 = mpy($Rs32.l,$Rt32.h)",
15496tc_bafaade3, TypeM>, Enc_be32a5 {
15497let Inst{7-5} = 0b001;
15498let Inst{13-13} = 0b0;
15499let Inst{31-21} = 0b11100100000;
15500let prefersSlot3 = 1;
15501}
15502def M2_mpyd_lh_s1 : HInst<
15503(outs DoubleRegs:$Rdd32),
15504(ins IntRegs:$Rs32, IntRegs:$Rt32),
15505"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
15506tc_bafaade3, TypeM>, Enc_be32a5 {
15507let Inst{7-5} = 0b001;
15508let Inst{13-13} = 0b0;
15509let Inst{31-21} = 0b11100100100;
15510let prefersSlot3 = 1;
15511}
15512def M2_mpyd_ll_s0 : HInst<
15513(outs DoubleRegs:$Rdd32),
15514(ins IntRegs:$Rs32, IntRegs:$Rt32),
15515"$Rdd32 = mpy($Rs32.l,$Rt32.l)",
15516tc_bafaade3, TypeM>, Enc_be32a5 {
15517let Inst{7-5} = 0b000;
15518let Inst{13-13} = 0b0;
15519let Inst{31-21} = 0b11100100000;
15520let prefersSlot3 = 1;
15521}
15522def M2_mpyd_ll_s1 : HInst<
15523(outs DoubleRegs:$Rdd32),
15524(ins IntRegs:$Rs32, IntRegs:$Rt32),
15525"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
15526tc_bafaade3, TypeM>, Enc_be32a5 {
15527let Inst{7-5} = 0b000;
15528let Inst{13-13} = 0b0;
15529let Inst{31-21} = 0b11100100100;
15530let prefersSlot3 = 1;
15531}
15532def M2_mpyd_nac_hh_s0 : HInst<
15533(outs DoubleRegs:$Rxx32),
15534(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15535"$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
15536tc_d773585a, TypeM>, Enc_61f0b0 {
15537let Inst{7-5} = 0b011;
15538let Inst{13-13} = 0b0;
15539let Inst{31-21} = 0b11100110001;
15540let prefersSlot3 = 1;
15541let Constraints = "$Rxx32 = $Rxx32in";
15542}
15543def M2_mpyd_nac_hh_s1 : HInst<
15544(outs DoubleRegs:$Rxx32),
15545(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15546"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15547tc_d773585a, TypeM>, Enc_61f0b0 {
15548let Inst{7-5} = 0b011;
15549let Inst{13-13} = 0b0;
15550let Inst{31-21} = 0b11100110101;
15551let prefersSlot3 = 1;
15552let Constraints = "$Rxx32 = $Rxx32in";
15553}
15554def M2_mpyd_nac_hl_s0 : HInst<
15555(outs DoubleRegs:$Rxx32),
15556(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15557"$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
15558tc_d773585a, TypeM>, Enc_61f0b0 {
15559let Inst{7-5} = 0b010;
15560let Inst{13-13} = 0b0;
15561let Inst{31-21} = 0b11100110001;
15562let prefersSlot3 = 1;
15563let Constraints = "$Rxx32 = $Rxx32in";
15564}
15565def M2_mpyd_nac_hl_s1 : HInst<
15566(outs DoubleRegs:$Rxx32),
15567(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15568"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15569tc_d773585a, TypeM>, Enc_61f0b0 {
15570let Inst{7-5} = 0b010;
15571let Inst{13-13} = 0b0;
15572let Inst{31-21} = 0b11100110101;
15573let prefersSlot3 = 1;
15574let Constraints = "$Rxx32 = $Rxx32in";
15575}
15576def M2_mpyd_nac_lh_s0 : HInst<
15577(outs DoubleRegs:$Rxx32),
15578(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15579"$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
15580tc_d773585a, TypeM>, Enc_61f0b0 {
15581let Inst{7-5} = 0b001;
15582let Inst{13-13} = 0b0;
15583let Inst{31-21} = 0b11100110001;
15584let prefersSlot3 = 1;
15585let Constraints = "$Rxx32 = $Rxx32in";
15586}
15587def M2_mpyd_nac_lh_s1 : HInst<
15588(outs DoubleRegs:$Rxx32),
15589(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15590"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15591tc_d773585a, TypeM>, Enc_61f0b0 {
15592let Inst{7-5} = 0b001;
15593let Inst{13-13} = 0b0;
15594let Inst{31-21} = 0b11100110101;
15595let prefersSlot3 = 1;
15596let Constraints = "$Rxx32 = $Rxx32in";
15597}
15598def M2_mpyd_nac_ll_s0 : HInst<
15599(outs DoubleRegs:$Rxx32),
15600(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15601"$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
15602tc_d773585a, TypeM>, Enc_61f0b0 {
15603let Inst{7-5} = 0b000;
15604let Inst{13-13} = 0b0;
15605let Inst{31-21} = 0b11100110001;
15606let prefersSlot3 = 1;
15607let Constraints = "$Rxx32 = $Rxx32in";
15608}
15609def M2_mpyd_nac_ll_s1 : HInst<
15610(outs DoubleRegs:$Rxx32),
15611(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15612"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15613tc_d773585a, TypeM>, Enc_61f0b0 {
15614let Inst{7-5} = 0b000;
15615let Inst{13-13} = 0b0;
15616let Inst{31-21} = 0b11100110101;
15617let prefersSlot3 = 1;
15618let Constraints = "$Rxx32 = $Rxx32in";
15619}
15620def M2_mpyd_rnd_hh_s0 : HInst<
15621(outs DoubleRegs:$Rdd32),
15622(ins IntRegs:$Rs32, IntRegs:$Rt32),
15623"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
15624tc_bafaade3, TypeM>, Enc_be32a5 {
15625let Inst{7-5} = 0b011;
15626let Inst{13-13} = 0b0;
15627let Inst{31-21} = 0b11100100001;
15628let prefersSlot3 = 1;
15629}
15630def M2_mpyd_rnd_hh_s1 : HInst<
15631(outs DoubleRegs:$Rdd32),
15632(ins IntRegs:$Rs32, IntRegs:$Rt32),
15633"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15634tc_bafaade3, TypeM>, Enc_be32a5 {
15635let Inst{7-5} = 0b011;
15636let Inst{13-13} = 0b0;
15637let Inst{31-21} = 0b11100100101;
15638let prefersSlot3 = 1;
15639}
15640def M2_mpyd_rnd_hl_s0 : HInst<
15641(outs DoubleRegs:$Rdd32),
15642(ins IntRegs:$Rs32, IntRegs:$Rt32),
15643"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
15644tc_bafaade3, TypeM>, Enc_be32a5 {
15645let Inst{7-5} = 0b010;
15646let Inst{13-13} = 0b0;
15647let Inst{31-21} = 0b11100100001;
15648let prefersSlot3 = 1;
15649}
15650def M2_mpyd_rnd_hl_s1 : HInst<
15651(outs DoubleRegs:$Rdd32),
15652(ins IntRegs:$Rs32, IntRegs:$Rt32),
15653"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15654tc_bafaade3, TypeM>, Enc_be32a5 {
15655let Inst{7-5} = 0b010;
15656let Inst{13-13} = 0b0;
15657let Inst{31-21} = 0b11100100101;
15658let prefersSlot3 = 1;
15659}
15660def M2_mpyd_rnd_lh_s0 : HInst<
15661(outs DoubleRegs:$Rdd32),
15662(ins IntRegs:$Rs32, IntRegs:$Rt32),
15663"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
15664tc_bafaade3, TypeM>, Enc_be32a5 {
15665let Inst{7-5} = 0b001;
15666let Inst{13-13} = 0b0;
15667let Inst{31-21} = 0b11100100001;
15668let prefersSlot3 = 1;
15669}
15670def M2_mpyd_rnd_lh_s1 : HInst<
15671(outs DoubleRegs:$Rdd32),
15672(ins IntRegs:$Rs32, IntRegs:$Rt32),
15673"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15674tc_bafaade3, TypeM>, Enc_be32a5 {
15675let Inst{7-5} = 0b001;
15676let Inst{13-13} = 0b0;
15677let Inst{31-21} = 0b11100100101;
15678let prefersSlot3 = 1;
15679}
15680def M2_mpyd_rnd_ll_s0 : HInst<
15681(outs DoubleRegs:$Rdd32),
15682(ins IntRegs:$Rs32, IntRegs:$Rt32),
15683"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
15684tc_bafaade3, TypeM>, Enc_be32a5 {
15685let Inst{7-5} = 0b000;
15686let Inst{13-13} = 0b0;
15687let Inst{31-21} = 0b11100100001;
15688let prefersSlot3 = 1;
15689}
15690def M2_mpyd_rnd_ll_s1 : HInst<
15691(outs DoubleRegs:$Rdd32),
15692(ins IntRegs:$Rs32, IntRegs:$Rt32),
15693"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15694tc_bafaade3, TypeM>, Enc_be32a5 {
15695let Inst{7-5} = 0b000;
15696let Inst{13-13} = 0b0;
15697let Inst{31-21} = 0b11100100101;
15698let prefersSlot3 = 1;
15699}
15700def M2_mpyi : HInst<
15701(outs IntRegs:$Rd32),
15702(ins IntRegs:$Rs32, IntRegs:$Rt32),
15703"$Rd32 = mpyi($Rs32,$Rt32)",
15704tc_bafaade3, TypeM>, Enc_5ab2be, ImmRegRel {
15705let Inst{7-5} = 0b000;
15706let Inst{13-13} = 0b0;
15707let Inst{31-21} = 0b11101101000;
15708let hasNewValue = 1;
15709let opNewValue = 0;
15710let prefersSlot3 = 1;
15711let CextOpcode = "M2_mpyi";
15712let InputType = "reg";
15713}
15714def M2_mpysin : HInst<
15715(outs IntRegs:$Rd32),
15716(ins IntRegs:$Rs32, u8_0Imm:$Ii),
15717"$Rd32 = -mpyi($Rs32,#$Ii)",
15718tc_c8ce0b5c, TypeM>, Enc_b8c967 {
15719let Inst{13-13} = 0b0;
15720let Inst{31-21} = 0b11100000100;
15721let hasNewValue = 1;
15722let opNewValue = 0;
15723let prefersSlot3 = 1;
15724}
15725def M2_mpysip : HInst<
15726(outs IntRegs:$Rd32),
15727(ins IntRegs:$Rs32, u32_0Imm:$Ii),
15728"$Rd32 = +mpyi($Rs32,#$Ii)",
15729tc_c8ce0b5c, TypeM>, Enc_b8c967 {
15730let Inst{13-13} = 0b0;
15731let Inst{31-21} = 0b11100000000;
15732let hasNewValue = 1;
15733let opNewValue = 0;
15734let prefersSlot3 = 1;
15735let isExtendable = 1;
15736let opExtendable = 2;
15737let isExtentSigned = 0;
15738let opExtentBits = 8;
15739let opExtentAlign = 0;
15740}
15741def M2_mpysmi : HInst<
15742(outs IntRegs:$Rd32),
15743(ins IntRegs:$Rs32, m32_0Imm:$Ii),
15744"$Rd32 = mpyi($Rs32,#$Ii)",
15745tc_c8ce0b5c, TypeM>, ImmRegRel {
15746let hasNewValue = 1;
15747let opNewValue = 0;
15748let CextOpcode = "M2_mpyi";
15749let InputType = "imm";
15750let isPseudo = 1;
15751let isExtendable = 1;
15752let opExtendable = 2;
15753let isExtentSigned = 1;
15754let opExtentBits = 9;
15755let opExtentAlign = 0;
15756}
15757def M2_mpysu_up : HInst<
15758(outs IntRegs:$Rd32),
15759(ins IntRegs:$Rs32, IntRegs:$Rt32),
15760"$Rd32 = mpysu($Rs32,$Rt32)",
15761tc_bafaade3, TypeM>, Enc_5ab2be {
15762let Inst{7-5} = 0b001;
15763let Inst{13-13} = 0b0;
15764let Inst{31-21} = 0b11101101011;
15765let hasNewValue = 1;
15766let opNewValue = 0;
15767let prefersSlot3 = 1;
15768}
15769def M2_mpyu_acc_hh_s0 : HInst<
15770(outs IntRegs:$Rx32),
15771(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15772"$Rx32 += mpyu($Rs32.h,$Rt32.h)",
15773tc_d773585a, TypeM>, Enc_2ae154 {
15774let Inst{7-5} = 0b011;
15775let Inst{13-13} = 0b0;
15776let Inst{31-21} = 0b11101110010;
15777let hasNewValue = 1;
15778let opNewValue = 0;
15779let prefersSlot3 = 1;
15780let Constraints = "$Rx32 = $Rx32in";
15781}
15782def M2_mpyu_acc_hh_s1 : HInst<
15783(outs IntRegs:$Rx32),
15784(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15785"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15786tc_d773585a, TypeM>, Enc_2ae154 {
15787let Inst{7-5} = 0b011;
15788let Inst{13-13} = 0b0;
15789let Inst{31-21} = 0b11101110110;
15790let hasNewValue = 1;
15791let opNewValue = 0;
15792let prefersSlot3 = 1;
15793let Constraints = "$Rx32 = $Rx32in";
15794}
15795def M2_mpyu_acc_hl_s0 : HInst<
15796(outs IntRegs:$Rx32),
15797(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15798"$Rx32 += mpyu($Rs32.h,$Rt32.l)",
15799tc_d773585a, TypeM>, Enc_2ae154 {
15800let Inst{7-5} = 0b010;
15801let Inst{13-13} = 0b0;
15802let Inst{31-21} = 0b11101110010;
15803let hasNewValue = 1;
15804let opNewValue = 0;
15805let prefersSlot3 = 1;
15806let Constraints = "$Rx32 = $Rx32in";
15807}
15808def M2_mpyu_acc_hl_s1 : HInst<
15809(outs IntRegs:$Rx32),
15810(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15811"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
15812tc_d773585a, TypeM>, Enc_2ae154 {
15813let Inst{7-5} = 0b010;
15814let Inst{13-13} = 0b0;
15815let Inst{31-21} = 0b11101110110;
15816let hasNewValue = 1;
15817let opNewValue = 0;
15818let prefersSlot3 = 1;
15819let Constraints = "$Rx32 = $Rx32in";
15820}
15821def M2_mpyu_acc_lh_s0 : HInst<
15822(outs IntRegs:$Rx32),
15823(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15824"$Rx32 += mpyu($Rs32.l,$Rt32.h)",
15825tc_d773585a, TypeM>, Enc_2ae154 {
15826let Inst{7-5} = 0b001;
15827let Inst{13-13} = 0b0;
15828let Inst{31-21} = 0b11101110010;
15829let hasNewValue = 1;
15830let opNewValue = 0;
15831let prefersSlot3 = 1;
15832let Constraints = "$Rx32 = $Rx32in";
15833}
15834def M2_mpyu_acc_lh_s1 : HInst<
15835(outs IntRegs:$Rx32),
15836(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15837"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
15838tc_d773585a, TypeM>, Enc_2ae154 {
15839let Inst{7-5} = 0b001;
15840let Inst{13-13} = 0b0;
15841let Inst{31-21} = 0b11101110110;
15842let hasNewValue = 1;
15843let opNewValue = 0;
15844let prefersSlot3 = 1;
15845let Constraints = "$Rx32 = $Rx32in";
15846}
15847def M2_mpyu_acc_ll_s0 : HInst<
15848(outs IntRegs:$Rx32),
15849(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15850"$Rx32 += mpyu($Rs32.l,$Rt32.l)",
15851tc_d773585a, TypeM>, Enc_2ae154 {
15852let Inst{7-5} = 0b000;
15853let Inst{13-13} = 0b0;
15854let Inst{31-21} = 0b11101110010;
15855let hasNewValue = 1;
15856let opNewValue = 0;
15857let prefersSlot3 = 1;
15858let Constraints = "$Rx32 = $Rx32in";
15859}
15860def M2_mpyu_acc_ll_s1 : HInst<
15861(outs IntRegs:$Rx32),
15862(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15863"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
15864tc_d773585a, TypeM>, Enc_2ae154 {
15865let Inst{7-5} = 0b000;
15866let Inst{13-13} = 0b0;
15867let Inst{31-21} = 0b11101110110;
15868let hasNewValue = 1;
15869let opNewValue = 0;
15870let prefersSlot3 = 1;
15871let Constraints = "$Rx32 = $Rx32in";
15872}
15873def M2_mpyu_hh_s0 : HInst<
15874(outs IntRegs:$Rd32),
15875(ins IntRegs:$Rs32, IntRegs:$Rt32),
15876"$Rd32 = mpyu($Rs32.h,$Rt32.h)",
15877tc_bafaade3, TypeM>, Enc_5ab2be {
15878let Inst{7-5} = 0b011;
15879let Inst{13-13} = 0b0;
15880let Inst{31-21} = 0b11101100010;
15881let hasNewValue = 1;
15882let opNewValue = 0;
15883let prefersSlot3 = 1;
15884}
15885def M2_mpyu_hh_s1 : HInst<
15886(outs IntRegs:$Rd32),
15887(ins IntRegs:$Rs32, IntRegs:$Rt32),
15888"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
15889tc_bafaade3, TypeM>, Enc_5ab2be {
15890let Inst{7-5} = 0b011;
15891let Inst{13-13} = 0b0;
15892let Inst{31-21} = 0b11101100110;
15893let hasNewValue = 1;
15894let opNewValue = 0;
15895let prefersSlot3 = 1;
15896}
15897def M2_mpyu_hl_s0 : HInst<
15898(outs IntRegs:$Rd32),
15899(ins IntRegs:$Rs32, IntRegs:$Rt32),
15900"$Rd32 = mpyu($Rs32.h,$Rt32.l)",
15901tc_bafaade3, TypeM>, Enc_5ab2be {
15902let Inst{7-5} = 0b010;
15903let Inst{13-13} = 0b0;
15904let Inst{31-21} = 0b11101100010;
15905let hasNewValue = 1;
15906let opNewValue = 0;
15907let prefersSlot3 = 1;
15908}
15909def M2_mpyu_hl_s1 : HInst<
15910(outs IntRegs:$Rd32),
15911(ins IntRegs:$Rs32, IntRegs:$Rt32),
15912"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
15913tc_bafaade3, TypeM>, Enc_5ab2be {
15914let Inst{7-5} = 0b010;
15915let Inst{13-13} = 0b0;
15916let Inst{31-21} = 0b11101100110;
15917let hasNewValue = 1;
15918let opNewValue = 0;
15919let prefersSlot3 = 1;
15920}
15921def M2_mpyu_lh_s0 : HInst<
15922(outs IntRegs:$Rd32),
15923(ins IntRegs:$Rs32, IntRegs:$Rt32),
15924"$Rd32 = mpyu($Rs32.l,$Rt32.h)",
15925tc_bafaade3, TypeM>, Enc_5ab2be {
15926let Inst{7-5} = 0b001;
15927let Inst{13-13} = 0b0;
15928let Inst{31-21} = 0b11101100010;
15929let hasNewValue = 1;
15930let opNewValue = 0;
15931let prefersSlot3 = 1;
15932}
15933def M2_mpyu_lh_s1 : HInst<
15934(outs IntRegs:$Rd32),
15935(ins IntRegs:$Rs32, IntRegs:$Rt32),
15936"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
15937tc_bafaade3, TypeM>, Enc_5ab2be {
15938let Inst{7-5} = 0b001;
15939let Inst{13-13} = 0b0;
15940let Inst{31-21} = 0b11101100110;
15941let hasNewValue = 1;
15942let opNewValue = 0;
15943let prefersSlot3 = 1;
15944}
15945def M2_mpyu_ll_s0 : HInst<
15946(outs IntRegs:$Rd32),
15947(ins IntRegs:$Rs32, IntRegs:$Rt32),
15948"$Rd32 = mpyu($Rs32.l,$Rt32.l)",
15949tc_bafaade3, TypeM>, Enc_5ab2be {
15950let Inst{7-5} = 0b000;
15951let Inst{13-13} = 0b0;
15952let Inst{31-21} = 0b11101100010;
15953let hasNewValue = 1;
15954let opNewValue = 0;
15955let prefersSlot3 = 1;
15956}
15957def M2_mpyu_ll_s1 : HInst<
15958(outs IntRegs:$Rd32),
15959(ins IntRegs:$Rs32, IntRegs:$Rt32),
15960"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
15961tc_bafaade3, TypeM>, Enc_5ab2be {
15962let Inst{7-5} = 0b000;
15963let Inst{13-13} = 0b0;
15964let Inst{31-21} = 0b11101100110;
15965let hasNewValue = 1;
15966let opNewValue = 0;
15967let prefersSlot3 = 1;
15968}
15969def M2_mpyu_nac_hh_s0 : HInst<
15970(outs IntRegs:$Rx32),
15971(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15972"$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
15973tc_d773585a, TypeM>, Enc_2ae154 {
15974let Inst{7-5} = 0b011;
15975let Inst{13-13} = 0b0;
15976let Inst{31-21} = 0b11101110011;
15977let hasNewValue = 1;
15978let opNewValue = 0;
15979let prefersSlot3 = 1;
15980let Constraints = "$Rx32 = $Rx32in";
15981}
15982def M2_mpyu_nac_hh_s1 : HInst<
15983(outs IntRegs:$Rx32),
15984(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15985"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
15986tc_d773585a, TypeM>, Enc_2ae154 {
15987let Inst{7-5} = 0b011;
15988let Inst{13-13} = 0b0;
15989let Inst{31-21} = 0b11101110111;
15990let hasNewValue = 1;
15991let opNewValue = 0;
15992let prefersSlot3 = 1;
15993let Constraints = "$Rx32 = $Rx32in";
15994}
15995def M2_mpyu_nac_hl_s0 : HInst<
15996(outs IntRegs:$Rx32),
15997(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15998"$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
15999tc_d773585a, TypeM>, Enc_2ae154 {
16000let Inst{7-5} = 0b010;
16001let Inst{13-13} = 0b0;
16002let Inst{31-21} = 0b11101110011;
16003let hasNewValue = 1;
16004let opNewValue = 0;
16005let prefersSlot3 = 1;
16006let Constraints = "$Rx32 = $Rx32in";
16007}
16008def M2_mpyu_nac_hl_s1 : HInst<
16009(outs IntRegs:$Rx32),
16010(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16011"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16012tc_d773585a, TypeM>, Enc_2ae154 {
16013let Inst{7-5} = 0b010;
16014let Inst{13-13} = 0b0;
16015let Inst{31-21} = 0b11101110111;
16016let hasNewValue = 1;
16017let opNewValue = 0;
16018let prefersSlot3 = 1;
16019let Constraints = "$Rx32 = $Rx32in";
16020}
16021def M2_mpyu_nac_lh_s0 : HInst<
16022(outs IntRegs:$Rx32),
16023(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16024"$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
16025tc_d773585a, TypeM>, Enc_2ae154 {
16026let Inst{7-5} = 0b001;
16027let Inst{13-13} = 0b0;
16028let Inst{31-21} = 0b11101110011;
16029let hasNewValue = 1;
16030let opNewValue = 0;
16031let prefersSlot3 = 1;
16032let Constraints = "$Rx32 = $Rx32in";
16033}
16034def M2_mpyu_nac_lh_s1 : HInst<
16035(outs IntRegs:$Rx32),
16036(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16037"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16038tc_d773585a, TypeM>, Enc_2ae154 {
16039let Inst{7-5} = 0b001;
16040let Inst{13-13} = 0b0;
16041let Inst{31-21} = 0b11101110111;
16042let hasNewValue = 1;
16043let opNewValue = 0;
16044let prefersSlot3 = 1;
16045let Constraints = "$Rx32 = $Rx32in";
16046}
16047def M2_mpyu_nac_ll_s0 : HInst<
16048(outs IntRegs:$Rx32),
16049(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16050"$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
16051tc_d773585a, TypeM>, Enc_2ae154 {
16052let Inst{7-5} = 0b000;
16053let Inst{13-13} = 0b0;
16054let Inst{31-21} = 0b11101110011;
16055let hasNewValue = 1;
16056let opNewValue = 0;
16057let prefersSlot3 = 1;
16058let Constraints = "$Rx32 = $Rx32in";
16059}
16060def M2_mpyu_nac_ll_s1 : HInst<
16061(outs IntRegs:$Rx32),
16062(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16063"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16064tc_d773585a, TypeM>, Enc_2ae154 {
16065let Inst{7-5} = 0b000;
16066let Inst{13-13} = 0b0;
16067let Inst{31-21} = 0b11101110111;
16068let hasNewValue = 1;
16069let opNewValue = 0;
16070let prefersSlot3 = 1;
16071let Constraints = "$Rx32 = $Rx32in";
16072}
16073def M2_mpyu_up : HInst<
16074(outs IntRegs:$Rd32),
16075(ins IntRegs:$Rs32, IntRegs:$Rt32),
16076"$Rd32 = mpyu($Rs32,$Rt32)",
16077tc_bafaade3, TypeM>, Enc_5ab2be {
16078let Inst{7-5} = 0b001;
16079let Inst{13-13} = 0b0;
16080let Inst{31-21} = 0b11101101010;
16081let hasNewValue = 1;
16082let opNewValue = 0;
16083let prefersSlot3 = 1;
16084}
16085def M2_mpyud_acc_hh_s0 : HInst<
16086(outs DoubleRegs:$Rxx32),
16087(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16088"$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
16089tc_d773585a, TypeM>, Enc_61f0b0 {
16090let Inst{7-5} = 0b011;
16091let Inst{13-13} = 0b0;
16092let Inst{31-21} = 0b11100110010;
16093let prefersSlot3 = 1;
16094let Constraints = "$Rxx32 = $Rxx32in";
16095}
16096def M2_mpyud_acc_hh_s1 : HInst<
16097(outs DoubleRegs:$Rxx32),
16098(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16099"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
16100tc_d773585a, TypeM>, Enc_61f0b0 {
16101let Inst{7-5} = 0b011;
16102let Inst{13-13} = 0b0;
16103let Inst{31-21} = 0b11100110110;
16104let prefersSlot3 = 1;
16105let Constraints = "$Rxx32 = $Rxx32in";
16106}
16107def M2_mpyud_acc_hl_s0 : HInst<
16108(outs DoubleRegs:$Rxx32),
16109(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16110"$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
16111tc_d773585a, TypeM>, Enc_61f0b0 {
16112let Inst{7-5} = 0b010;
16113let Inst{13-13} = 0b0;
16114let Inst{31-21} = 0b11100110010;
16115let prefersSlot3 = 1;
16116let Constraints = "$Rxx32 = $Rxx32in";
16117}
16118def M2_mpyud_acc_hl_s1 : HInst<
16119(outs DoubleRegs:$Rxx32),
16120(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16121"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
16122tc_d773585a, TypeM>, Enc_61f0b0 {
16123let Inst{7-5} = 0b010;
16124let Inst{13-13} = 0b0;
16125let Inst{31-21} = 0b11100110110;
16126let prefersSlot3 = 1;
16127let Constraints = "$Rxx32 = $Rxx32in";
16128}
16129def M2_mpyud_acc_lh_s0 : HInst<
16130(outs DoubleRegs:$Rxx32),
16131(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16132"$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
16133tc_d773585a, TypeM>, Enc_61f0b0 {
16134let Inst{7-5} = 0b001;
16135let Inst{13-13} = 0b0;
16136let Inst{31-21} = 0b11100110010;
16137let prefersSlot3 = 1;
16138let Constraints = "$Rxx32 = $Rxx32in";
16139}
16140def M2_mpyud_acc_lh_s1 : HInst<
16141(outs DoubleRegs:$Rxx32),
16142(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16143"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16144tc_d773585a, TypeM>, Enc_61f0b0 {
16145let Inst{7-5} = 0b001;
16146let Inst{13-13} = 0b0;
16147let Inst{31-21} = 0b11100110110;
16148let prefersSlot3 = 1;
16149let Constraints = "$Rxx32 = $Rxx32in";
16150}
16151def M2_mpyud_acc_ll_s0 : HInst<
16152(outs DoubleRegs:$Rxx32),
16153(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16154"$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
16155tc_d773585a, TypeM>, Enc_61f0b0 {
16156let Inst{7-5} = 0b000;
16157let Inst{13-13} = 0b0;
16158let Inst{31-21} = 0b11100110010;
16159let prefersSlot3 = 1;
16160let Constraints = "$Rxx32 = $Rxx32in";
16161}
16162def M2_mpyud_acc_ll_s1 : HInst<
16163(outs DoubleRegs:$Rxx32),
16164(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16165"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16166tc_d773585a, TypeM>, Enc_61f0b0 {
16167let Inst{7-5} = 0b000;
16168let Inst{13-13} = 0b0;
16169let Inst{31-21} = 0b11100110110;
16170let prefersSlot3 = 1;
16171let Constraints = "$Rxx32 = $Rxx32in";
16172}
16173def M2_mpyud_hh_s0 : HInst<
16174(outs DoubleRegs:$Rdd32),
16175(ins IntRegs:$Rs32, IntRegs:$Rt32),
16176"$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
16177tc_bafaade3, TypeM>, Enc_be32a5 {
16178let Inst{7-5} = 0b011;
16179let Inst{13-13} = 0b0;
16180let Inst{31-21} = 0b11100100010;
16181let prefersSlot3 = 1;
16182}
16183def M2_mpyud_hh_s1 : HInst<
16184(outs DoubleRegs:$Rdd32),
16185(ins IntRegs:$Rs32, IntRegs:$Rt32),
16186"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16187tc_bafaade3, TypeM>, Enc_be32a5 {
16188let Inst{7-5} = 0b011;
16189let Inst{13-13} = 0b0;
16190let Inst{31-21} = 0b11100100110;
16191let prefersSlot3 = 1;
16192}
16193def M2_mpyud_hl_s0 : HInst<
16194(outs DoubleRegs:$Rdd32),
16195(ins IntRegs:$Rs32, IntRegs:$Rt32),
16196"$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
16197tc_bafaade3, TypeM>, Enc_be32a5 {
16198let Inst{7-5} = 0b010;
16199let Inst{13-13} = 0b0;
16200let Inst{31-21} = 0b11100100010;
16201let prefersSlot3 = 1;
16202}
16203def M2_mpyud_hl_s1 : HInst<
16204(outs DoubleRegs:$Rdd32),
16205(ins IntRegs:$Rs32, IntRegs:$Rt32),
16206"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16207tc_bafaade3, TypeM>, Enc_be32a5 {
16208let Inst{7-5} = 0b010;
16209let Inst{13-13} = 0b0;
16210let Inst{31-21} = 0b11100100110;
16211let prefersSlot3 = 1;
16212}
16213def M2_mpyud_lh_s0 : HInst<
16214(outs DoubleRegs:$Rdd32),
16215(ins IntRegs:$Rs32, IntRegs:$Rt32),
16216"$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
16217tc_bafaade3, TypeM>, Enc_be32a5 {
16218let Inst{7-5} = 0b001;
16219let Inst{13-13} = 0b0;
16220let Inst{31-21} = 0b11100100010;
16221let prefersSlot3 = 1;
16222}
16223def M2_mpyud_lh_s1 : HInst<
16224(outs DoubleRegs:$Rdd32),
16225(ins IntRegs:$Rs32, IntRegs:$Rt32),
16226"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16227tc_bafaade3, TypeM>, Enc_be32a5 {
16228let Inst{7-5} = 0b001;
16229let Inst{13-13} = 0b0;
16230let Inst{31-21} = 0b11100100110;
16231let prefersSlot3 = 1;
16232}
16233def M2_mpyud_ll_s0 : HInst<
16234(outs DoubleRegs:$Rdd32),
16235(ins IntRegs:$Rs32, IntRegs:$Rt32),
16236"$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
16237tc_bafaade3, TypeM>, Enc_be32a5 {
16238let Inst{7-5} = 0b000;
16239let Inst{13-13} = 0b0;
16240let Inst{31-21} = 0b11100100010;
16241let prefersSlot3 = 1;
16242}
16243def M2_mpyud_ll_s1 : HInst<
16244(outs DoubleRegs:$Rdd32),
16245(ins IntRegs:$Rs32, IntRegs:$Rt32),
16246"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16247tc_bafaade3, TypeM>, Enc_be32a5 {
16248let Inst{7-5} = 0b000;
16249let Inst{13-13} = 0b0;
16250let Inst{31-21} = 0b11100100110;
16251let prefersSlot3 = 1;
16252}
16253def M2_mpyud_nac_hh_s0 : HInst<
16254(outs DoubleRegs:$Rxx32),
16255(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16256"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
16257tc_d773585a, TypeM>, Enc_61f0b0 {
16258let Inst{7-5} = 0b011;
16259let Inst{13-13} = 0b0;
16260let Inst{31-21} = 0b11100110011;
16261let prefersSlot3 = 1;
16262let Constraints = "$Rxx32 = $Rxx32in";
16263}
16264def M2_mpyud_nac_hh_s1 : HInst<
16265(outs DoubleRegs:$Rxx32),
16266(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16267"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16268tc_d773585a, TypeM>, Enc_61f0b0 {
16269let Inst{7-5} = 0b011;
16270let Inst{13-13} = 0b0;
16271let Inst{31-21} = 0b11100110111;
16272let prefersSlot3 = 1;
16273let Constraints = "$Rxx32 = $Rxx32in";
16274}
16275def M2_mpyud_nac_hl_s0 : HInst<
16276(outs DoubleRegs:$Rxx32),
16277(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16278"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
16279tc_d773585a, TypeM>, Enc_61f0b0 {
16280let Inst{7-5} = 0b010;
16281let Inst{13-13} = 0b0;
16282let Inst{31-21} = 0b11100110011;
16283let prefersSlot3 = 1;
16284let Constraints = "$Rxx32 = $Rxx32in";
16285}
16286def M2_mpyud_nac_hl_s1 : HInst<
16287(outs DoubleRegs:$Rxx32),
16288(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16289"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16290tc_d773585a, TypeM>, Enc_61f0b0 {
16291let Inst{7-5} = 0b010;
16292let Inst{13-13} = 0b0;
16293let Inst{31-21} = 0b11100110111;
16294let prefersSlot3 = 1;
16295let Constraints = "$Rxx32 = $Rxx32in";
16296}
16297def M2_mpyud_nac_lh_s0 : HInst<
16298(outs DoubleRegs:$Rxx32),
16299(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16300"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
16301tc_d773585a, TypeM>, Enc_61f0b0 {
16302let Inst{7-5} = 0b001;
16303let Inst{13-13} = 0b0;
16304let Inst{31-21} = 0b11100110011;
16305let prefersSlot3 = 1;
16306let Constraints = "$Rxx32 = $Rxx32in";
16307}
16308def M2_mpyud_nac_lh_s1 : HInst<
16309(outs DoubleRegs:$Rxx32),
16310(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16311"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16312tc_d773585a, TypeM>, Enc_61f0b0 {
16313let Inst{7-5} = 0b001;
16314let Inst{13-13} = 0b0;
16315let Inst{31-21} = 0b11100110111;
16316let prefersSlot3 = 1;
16317let Constraints = "$Rxx32 = $Rxx32in";
16318}
16319def M2_mpyud_nac_ll_s0 : HInst<
16320(outs DoubleRegs:$Rxx32),
16321(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16322"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
16323tc_d773585a, TypeM>, Enc_61f0b0 {
16324let Inst{7-5} = 0b000;
16325let Inst{13-13} = 0b0;
16326let Inst{31-21} = 0b11100110011;
16327let prefersSlot3 = 1;
16328let Constraints = "$Rxx32 = $Rxx32in";
16329}
16330def M2_mpyud_nac_ll_s1 : HInst<
16331(outs DoubleRegs:$Rxx32),
16332(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16333"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16334tc_d773585a, TypeM>, Enc_61f0b0 {
16335let Inst{7-5} = 0b000;
16336let Inst{13-13} = 0b0;
16337let Inst{31-21} = 0b11100110111;
16338let prefersSlot3 = 1;
16339let Constraints = "$Rxx32 = $Rxx32in";
16340}
16341def M2_mpyui : HInst<
16342(outs IntRegs:$Rd32),
16343(ins IntRegs:$Rs32, IntRegs:$Rt32),
16344"$Rd32 = mpyui($Rs32,$Rt32)",
16345tc_bafaade3, TypeM> {
16346let hasNewValue = 1;
16347let opNewValue = 0;
16348let isPseudo = 1;
16349let isCodeGenOnly = 1;
16350}
16351def M2_nacci : HInst<
16352(outs IntRegs:$Rx32),
16353(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16354"$Rx32 -= add($Rs32,$Rt32)",
16355tc_f675fee8, TypeM>, Enc_2ae154 {
16356let Inst{7-5} = 0b001;
16357let Inst{13-13} = 0b0;
16358let Inst{31-21} = 0b11101111100;
16359let hasNewValue = 1;
16360let opNewValue = 0;
16361let prefersSlot3 = 1;
16362let InputType = "reg";
16363let Constraints = "$Rx32 = $Rx32in";
16364}
16365def M2_naccii : HInst<
16366(outs IntRegs:$Rx32),
16367(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
16368"$Rx32 -= add($Rs32,#$Ii)",
16369tc_f675fee8, TypeM>, Enc_c90aca {
16370let Inst{13-13} = 0b0;
16371let Inst{31-21} = 0b11100010100;
16372let hasNewValue = 1;
16373let opNewValue = 0;
16374let prefersSlot3 = 1;
16375let InputType = "imm";
16376let isExtendable = 1;
16377let opExtendable = 3;
16378let isExtentSigned = 1;
16379let opExtentBits = 8;
16380let opExtentAlign = 0;
16381let Constraints = "$Rx32 = $Rx32in";
16382}
16383def M2_subacc : HInst<
16384(outs IntRegs:$Rx32),
16385(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
16386"$Rx32 += sub($Rt32,$Rs32)",
16387tc_f675fee8, TypeM>, Enc_a568d4 {
16388let Inst{7-5} = 0b011;
16389let Inst{13-13} = 0b0;
16390let Inst{31-21} = 0b11101111000;
16391let hasNewValue = 1;
16392let opNewValue = 0;
16393let prefersSlot3 = 1;
16394let InputType = "reg";
16395let Constraints = "$Rx32 = $Rx32in";
16396}
16397def M2_vabsdiffh : HInst<
16398(outs DoubleRegs:$Rdd32),
16399(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16400"$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
16401tc_002cb246, TypeM>, Enc_ea23e4 {
16402let Inst{7-5} = 0b000;
16403let Inst{13-13} = 0b0;
16404let Inst{31-21} = 0b11101000011;
16405let prefersSlot3 = 1;
16406}
16407def M2_vabsdiffw : HInst<
16408(outs DoubleRegs:$Rdd32),
16409(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16410"$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
16411tc_002cb246, TypeM>, Enc_ea23e4 {
16412let Inst{7-5} = 0b000;
16413let Inst{13-13} = 0b0;
16414let Inst{31-21} = 0b11101000001;
16415let prefersSlot3 = 1;
16416}
16417def M2_vcmac_s0_sat_i : HInst<
16418(outs DoubleRegs:$Rxx32),
16419(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16420"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
16421tc_d773585a, TypeM>, Enc_88c16c {
16422let Inst{7-5} = 0b100;
16423let Inst{13-13} = 0b0;
16424let Inst{31-21} = 0b11101010010;
16425let prefersSlot3 = 1;
16426let Defs = [USR_OVF];
16427let Constraints = "$Rxx32 = $Rxx32in";
16428}
16429def M2_vcmac_s0_sat_r : HInst<
16430(outs DoubleRegs:$Rxx32),
16431(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16432"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
16433tc_d773585a, TypeM>, Enc_88c16c {
16434let Inst{7-5} = 0b100;
16435let Inst{13-13} = 0b0;
16436let Inst{31-21} = 0b11101010001;
16437let prefersSlot3 = 1;
16438let Defs = [USR_OVF];
16439let Constraints = "$Rxx32 = $Rxx32in";
16440}
16441def M2_vcmpy_s0_sat_i : HInst<
16442(outs DoubleRegs:$Rdd32),
16443(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16444"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
16445tc_bafaade3, TypeM>, Enc_a56825 {
16446let Inst{7-5} = 0b110;
16447let Inst{13-13} = 0b0;
16448let Inst{31-21} = 0b11101000010;
16449let prefersSlot3 = 1;
16450let Defs = [USR_OVF];
16451}
16452def M2_vcmpy_s0_sat_r : HInst<
16453(outs DoubleRegs:$Rdd32),
16454(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16455"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
16456tc_bafaade3, TypeM>, Enc_a56825 {
16457let Inst{7-5} = 0b110;
16458let Inst{13-13} = 0b0;
16459let Inst{31-21} = 0b11101000001;
16460let prefersSlot3 = 1;
16461let Defs = [USR_OVF];
16462}
16463def M2_vcmpy_s1_sat_i : HInst<
16464(outs DoubleRegs:$Rdd32),
16465(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16466"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
16467tc_bafaade3, TypeM>, Enc_a56825 {
16468let Inst{7-5} = 0b110;
16469let Inst{13-13} = 0b0;
16470let Inst{31-21} = 0b11101000110;
16471let prefersSlot3 = 1;
16472let Defs = [USR_OVF];
16473}
16474def M2_vcmpy_s1_sat_r : HInst<
16475(outs DoubleRegs:$Rdd32),
16476(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16477"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
16478tc_bafaade3, TypeM>, Enc_a56825 {
16479let Inst{7-5} = 0b110;
16480let Inst{13-13} = 0b0;
16481let Inst{31-21} = 0b11101000101;
16482let prefersSlot3 = 1;
16483let Defs = [USR_OVF];
16484}
16485def M2_vdmacs_s0 : HInst<
16486(outs DoubleRegs:$Rxx32),
16487(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16488"$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
16489tc_d773585a, TypeM>, Enc_88c16c {
16490let Inst{7-5} = 0b100;
16491let Inst{13-13} = 0b0;
16492let Inst{31-21} = 0b11101010000;
16493let prefersSlot3 = 1;
16494let Defs = [USR_OVF];
16495let Constraints = "$Rxx32 = $Rxx32in";
16496}
16497def M2_vdmacs_s1 : HInst<
16498(outs DoubleRegs:$Rxx32),
16499(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16500"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
16501tc_d773585a, TypeM>, Enc_88c16c {
16502let Inst{7-5} = 0b100;
16503let Inst{13-13} = 0b0;
16504let Inst{31-21} = 0b11101010100;
16505let prefersSlot3 = 1;
16506let Defs = [USR_OVF];
16507let Constraints = "$Rxx32 = $Rxx32in";
16508}
16509def M2_vdmpyrs_s0 : HInst<
16510(outs IntRegs:$Rd32),
16511(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16512"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
16513tc_bafaade3, TypeM>, Enc_d2216a {
16514let Inst{7-5} = 0b000;
16515let Inst{13-13} = 0b0;
16516let Inst{31-21} = 0b11101001000;
16517let hasNewValue = 1;
16518let opNewValue = 0;
16519let prefersSlot3 = 1;
16520let Defs = [USR_OVF];
16521}
16522def M2_vdmpyrs_s1 : HInst<
16523(outs IntRegs:$Rd32),
16524(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16525"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
16526tc_bafaade3, TypeM>, Enc_d2216a {
16527let Inst{7-5} = 0b000;
16528let Inst{13-13} = 0b0;
16529let Inst{31-21} = 0b11101001100;
16530let hasNewValue = 1;
16531let opNewValue = 0;
16532let prefersSlot3 = 1;
16533let Defs = [USR_OVF];
16534}
16535def M2_vdmpys_s0 : HInst<
16536(outs DoubleRegs:$Rdd32),
16537(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16538"$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
16539tc_bafaade3, TypeM>, Enc_a56825 {
16540let Inst{7-5} = 0b100;
16541let Inst{13-13} = 0b0;
16542let Inst{31-21} = 0b11101000000;
16543let prefersSlot3 = 1;
16544let Defs = [USR_OVF];
16545}
16546def M2_vdmpys_s1 : HInst<
16547(outs DoubleRegs:$Rdd32),
16548(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16549"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
16550tc_bafaade3, TypeM>, Enc_a56825 {
16551let Inst{7-5} = 0b100;
16552let Inst{13-13} = 0b0;
16553let Inst{31-21} = 0b11101000100;
16554let prefersSlot3 = 1;
16555let Defs = [USR_OVF];
16556}
16557def M2_vmac2 : HInst<
16558(outs DoubleRegs:$Rxx32),
16559(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16560"$Rxx32 += vmpyh($Rs32,$Rt32)",
16561tc_d773585a, TypeM>, Enc_61f0b0 {
16562let Inst{7-5} = 0b001;
16563let Inst{13-13} = 0b0;
16564let Inst{31-21} = 0b11100111001;
16565let prefersSlot3 = 1;
16566let Constraints = "$Rxx32 = $Rxx32in";
16567}
16568def M2_vmac2es : HInst<
16569(outs DoubleRegs:$Rxx32),
16570(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16571"$Rxx32 += vmpyeh($Rss32,$Rtt32)",
16572tc_d773585a, TypeM>, Enc_88c16c {
16573let Inst{7-5} = 0b010;
16574let Inst{13-13} = 0b0;
16575let Inst{31-21} = 0b11101010001;
16576let prefersSlot3 = 1;
16577let Constraints = "$Rxx32 = $Rxx32in";
16578}
16579def M2_vmac2es_s0 : HInst<
16580(outs DoubleRegs:$Rxx32),
16581(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16582"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
16583tc_d773585a, TypeM>, Enc_88c16c {
16584let Inst{7-5} = 0b110;
16585let Inst{13-13} = 0b0;
16586let Inst{31-21} = 0b11101010000;
16587let prefersSlot3 = 1;
16588let Defs = [USR_OVF];
16589let Constraints = "$Rxx32 = $Rxx32in";
16590}
16591def M2_vmac2es_s1 : HInst<
16592(outs DoubleRegs:$Rxx32),
16593(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16594"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
16595tc_d773585a, TypeM>, Enc_88c16c {
16596let Inst{7-5} = 0b110;
16597let Inst{13-13} = 0b0;
16598let Inst{31-21} = 0b11101010100;
16599let prefersSlot3 = 1;
16600let Defs = [USR_OVF];
16601let Constraints = "$Rxx32 = $Rxx32in";
16602}
16603def M2_vmac2s_s0 : HInst<
16604(outs DoubleRegs:$Rxx32),
16605(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16606"$Rxx32 += vmpyh($Rs32,$Rt32):sat",
16607tc_d773585a, TypeM>, Enc_61f0b0 {
16608let Inst{7-5} = 0b101;
16609let Inst{13-13} = 0b0;
16610let Inst{31-21} = 0b11100111000;
16611let prefersSlot3 = 1;
16612let Defs = [USR_OVF];
16613let Constraints = "$Rxx32 = $Rxx32in";
16614}
16615def M2_vmac2s_s1 : HInst<
16616(outs DoubleRegs:$Rxx32),
16617(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16618"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
16619tc_d773585a, TypeM>, Enc_61f0b0 {
16620let Inst{7-5} = 0b101;
16621let Inst{13-13} = 0b0;
16622let Inst{31-21} = 0b11100111100;
16623let prefersSlot3 = 1;
16624let Defs = [USR_OVF];
16625let Constraints = "$Rxx32 = $Rxx32in";
16626}
16627def M2_vmac2su_s0 : HInst<
16628(outs DoubleRegs:$Rxx32),
16629(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16630"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
16631tc_d773585a, TypeM>, Enc_61f0b0 {
16632let Inst{7-5} = 0b101;
16633let Inst{13-13} = 0b0;
16634let Inst{31-21} = 0b11100111011;
16635let prefersSlot3 = 1;
16636let Defs = [USR_OVF];
16637let Constraints = "$Rxx32 = $Rxx32in";
16638}
16639def M2_vmac2su_s1 : HInst<
16640(outs DoubleRegs:$Rxx32),
16641(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16642"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
16643tc_d773585a, TypeM>, Enc_61f0b0 {
16644let Inst{7-5} = 0b101;
16645let Inst{13-13} = 0b0;
16646let Inst{31-21} = 0b11100111111;
16647let prefersSlot3 = 1;
16648let Defs = [USR_OVF];
16649let Constraints = "$Rxx32 = $Rxx32in";
16650}
16651def M2_vmpy2es_s0 : HInst<
16652(outs DoubleRegs:$Rdd32),
16653(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16654"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
16655tc_bafaade3, TypeM>, Enc_a56825 {
16656let Inst{7-5} = 0b110;
16657let Inst{13-13} = 0b0;
16658let Inst{31-21} = 0b11101000000;
16659let prefersSlot3 = 1;
16660let Defs = [USR_OVF];
16661}
16662def M2_vmpy2es_s1 : HInst<
16663(outs DoubleRegs:$Rdd32),
16664(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16665"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
16666tc_bafaade3, TypeM>, Enc_a56825 {
16667let Inst{7-5} = 0b110;
16668let Inst{13-13} = 0b0;
16669let Inst{31-21} = 0b11101000100;
16670let prefersSlot3 = 1;
16671let Defs = [USR_OVF];
16672}
16673def M2_vmpy2s_s0 : HInst<
16674(outs DoubleRegs:$Rdd32),
16675(ins IntRegs:$Rs32, IntRegs:$Rt32),
16676"$Rdd32 = vmpyh($Rs32,$Rt32):sat",
16677tc_bafaade3, TypeM>, Enc_be32a5 {
16678let Inst{7-5} = 0b101;
16679let Inst{13-13} = 0b0;
16680let Inst{31-21} = 0b11100101000;
16681let prefersSlot3 = 1;
16682let Defs = [USR_OVF];
16683}
16684def M2_vmpy2s_s0pack : HInst<
16685(outs IntRegs:$Rd32),
16686(ins IntRegs:$Rs32, IntRegs:$Rt32),
16687"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
16688tc_bafaade3, TypeM>, Enc_5ab2be {
16689let Inst{7-5} = 0b111;
16690let Inst{13-13} = 0b0;
16691let Inst{31-21} = 0b11101101001;
16692let hasNewValue = 1;
16693let opNewValue = 0;
16694let prefersSlot3 = 1;
16695let Defs = [USR_OVF];
16696}
16697def M2_vmpy2s_s1 : HInst<
16698(outs DoubleRegs:$Rdd32),
16699(ins IntRegs:$Rs32, IntRegs:$Rt32),
16700"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
16701tc_bafaade3, TypeM>, Enc_be32a5 {
16702let Inst{7-5} = 0b101;
16703let Inst{13-13} = 0b0;
16704let Inst{31-21} = 0b11100101100;
16705let prefersSlot3 = 1;
16706let Defs = [USR_OVF];
16707}
16708def M2_vmpy2s_s1pack : HInst<
16709(outs IntRegs:$Rd32),
16710(ins IntRegs:$Rs32, IntRegs:$Rt32),
16711"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
16712tc_bafaade3, TypeM>, Enc_5ab2be {
16713let Inst{7-5} = 0b111;
16714let Inst{13-13} = 0b0;
16715let Inst{31-21} = 0b11101101101;
16716let hasNewValue = 1;
16717let opNewValue = 0;
16718let prefersSlot3 = 1;
16719let Defs = [USR_OVF];
16720}
16721def M2_vmpy2su_s0 : HInst<
16722(outs DoubleRegs:$Rdd32),
16723(ins IntRegs:$Rs32, IntRegs:$Rt32),
16724"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
16725tc_bafaade3, TypeM>, Enc_be32a5 {
16726let Inst{7-5} = 0b111;
16727let Inst{13-13} = 0b0;
16728let Inst{31-21} = 0b11100101000;
16729let prefersSlot3 = 1;
16730let Defs = [USR_OVF];
16731}
16732def M2_vmpy2su_s1 : HInst<
16733(outs DoubleRegs:$Rdd32),
16734(ins IntRegs:$Rs32, IntRegs:$Rt32),
16735"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
16736tc_bafaade3, TypeM>, Enc_be32a5 {
16737let Inst{7-5} = 0b111;
16738let Inst{13-13} = 0b0;
16739let Inst{31-21} = 0b11100101100;
16740let prefersSlot3 = 1;
16741let Defs = [USR_OVF];
16742}
16743def M2_vraddh : HInst<
16744(outs IntRegs:$Rd32),
16745(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16746"$Rd32 = vraddh($Rss32,$Rtt32)",
16747tc_bafaade3, TypeM>, Enc_d2216a {
16748let Inst{7-5} = 0b111;
16749let Inst{13-13} = 0b0;
16750let Inst{31-21} = 0b11101001001;
16751let hasNewValue = 1;
16752let opNewValue = 0;
16753let prefersSlot3 = 1;
16754}
16755def M2_vradduh : HInst<
16756(outs IntRegs:$Rd32),
16757(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16758"$Rd32 = vradduh($Rss32,$Rtt32)",
16759tc_bafaade3, TypeM>, Enc_d2216a {
16760let Inst{7-5} = 0b001;
16761let Inst{13-13} = 0b0;
16762let Inst{31-21} = 0b11101001000;
16763let hasNewValue = 1;
16764let opNewValue = 0;
16765let prefersSlot3 = 1;
16766}
16767def M2_vrcmaci_s0 : HInst<
16768(outs DoubleRegs:$Rxx32),
16769(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16770"$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
16771tc_d773585a, TypeM>, Enc_88c16c {
16772let Inst{7-5} = 0b000;
16773let Inst{13-13} = 0b0;
16774let Inst{31-21} = 0b11101010000;
16775let prefersSlot3 = 1;
16776let Constraints = "$Rxx32 = $Rxx32in";
16777}
16778def M2_vrcmaci_s0c : HInst<
16779(outs DoubleRegs:$Rxx32),
16780(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16781"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
16782tc_d773585a, TypeM>, Enc_88c16c {
16783let Inst{7-5} = 0b000;
16784let Inst{13-13} = 0b0;
16785let Inst{31-21} = 0b11101010010;
16786let prefersSlot3 = 1;
16787let Constraints = "$Rxx32 = $Rxx32in";
16788}
16789def M2_vrcmacr_s0 : HInst<
16790(outs DoubleRegs:$Rxx32),
16791(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16792"$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
16793tc_d773585a, TypeM>, Enc_88c16c {
16794let Inst{7-5} = 0b001;
16795let Inst{13-13} = 0b0;
16796let Inst{31-21} = 0b11101010000;
16797let prefersSlot3 = 1;
16798let Constraints = "$Rxx32 = $Rxx32in";
16799}
16800def M2_vrcmacr_s0c : HInst<
16801(outs DoubleRegs:$Rxx32),
16802(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16803"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
16804tc_d773585a, TypeM>, Enc_88c16c {
16805let Inst{7-5} = 0b001;
16806let Inst{13-13} = 0b0;
16807let Inst{31-21} = 0b11101010011;
16808let prefersSlot3 = 1;
16809let Constraints = "$Rxx32 = $Rxx32in";
16810}
16811def M2_vrcmpyi_s0 : HInst<
16812(outs DoubleRegs:$Rdd32),
16813(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16814"$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
16815tc_bafaade3, TypeM>, Enc_a56825 {
16816let Inst{7-5} = 0b000;
16817let Inst{13-13} = 0b0;
16818let Inst{31-21} = 0b11101000000;
16819let prefersSlot3 = 1;
16820}
16821def M2_vrcmpyi_s0c : HInst<
16822(outs DoubleRegs:$Rdd32),
16823(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16824"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
16825tc_bafaade3, TypeM>, Enc_a56825 {
16826let Inst{7-5} = 0b000;
16827let Inst{13-13} = 0b0;
16828let Inst{31-21} = 0b11101000010;
16829let prefersSlot3 = 1;
16830}
16831def M2_vrcmpyr_s0 : HInst<
16832(outs DoubleRegs:$Rdd32),
16833(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16834"$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
16835tc_bafaade3, TypeM>, Enc_a56825 {
16836let Inst{7-5} = 0b001;
16837let Inst{13-13} = 0b0;
16838let Inst{31-21} = 0b11101000000;
16839let prefersSlot3 = 1;
16840}
16841def M2_vrcmpyr_s0c : HInst<
16842(outs DoubleRegs:$Rdd32),
16843(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16844"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
16845tc_bafaade3, TypeM>, Enc_a56825 {
16846let Inst{7-5} = 0b001;
16847let Inst{13-13} = 0b0;
16848let Inst{31-21} = 0b11101000011;
16849let prefersSlot3 = 1;
16850}
16851def M2_vrcmpys_acc_s1 : HInst<
16852(outs DoubleRegs:$Rxx32),
16853(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
16854"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
16855tc_d773585a, TypeM> {
16856let isPseudo = 1;
16857let Constraints = "$Rxx32 = $Rxx32in";
16858}
16859def M2_vrcmpys_acc_s1_h : HInst<
16860(outs DoubleRegs:$Rxx32),
16861(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16862"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
16863tc_d773585a, TypeM>, Enc_88c16c {
16864let Inst{7-5} = 0b100;
16865let Inst{13-13} = 0b0;
16866let Inst{31-21} = 0b11101010101;
16867let prefersSlot3 = 1;
16868let Defs = [USR_OVF];
16869let Constraints = "$Rxx32 = $Rxx32in";
16870}
16871def M2_vrcmpys_acc_s1_l : HInst<
16872(outs DoubleRegs:$Rxx32),
16873(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16874"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
16875tc_d773585a, TypeM>, Enc_88c16c {
16876let Inst{7-5} = 0b100;
16877let Inst{13-13} = 0b0;
16878let Inst{31-21} = 0b11101010111;
16879let prefersSlot3 = 1;
16880let Defs = [USR_OVF];
16881let Constraints = "$Rxx32 = $Rxx32in";
16882}
16883def M2_vrcmpys_s1 : HInst<
16884(outs DoubleRegs:$Rdd32),
16885(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16886"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
16887tc_bafaade3, TypeM> {
16888let isPseudo = 1;
16889}
16890def M2_vrcmpys_s1_h : HInst<
16891(outs DoubleRegs:$Rdd32),
16892(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16893"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
16894tc_bafaade3, TypeM>, Enc_a56825 {
16895let Inst{7-5} = 0b100;
16896let Inst{13-13} = 0b0;
16897let Inst{31-21} = 0b11101000101;
16898let prefersSlot3 = 1;
16899let Defs = [USR_OVF];
16900}
16901def M2_vrcmpys_s1_l : HInst<
16902(outs DoubleRegs:$Rdd32),
16903(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16904"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
16905tc_bafaade3, TypeM>, Enc_a56825 {
16906let Inst{7-5} = 0b100;
16907let Inst{13-13} = 0b0;
16908let Inst{31-21} = 0b11101000111;
16909let prefersSlot3 = 1;
16910let Defs = [USR_OVF];
16911}
16912def M2_vrcmpys_s1rp : HInst<
16913(outs IntRegs:$Rd32),
16914(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
16915"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
16916tc_bafaade3, TypeM> {
16917let hasNewValue = 1;
16918let opNewValue = 0;
16919let isPseudo = 1;
16920}
16921def M2_vrcmpys_s1rp_h : HInst<
16922(outs IntRegs:$Rd32),
16923(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16924"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
16925tc_bafaade3, TypeM>, Enc_d2216a {
16926let Inst{7-5} = 0b110;
16927let Inst{13-13} = 0b0;
16928let Inst{31-21} = 0b11101001101;
16929let hasNewValue = 1;
16930let opNewValue = 0;
16931let prefersSlot3 = 1;
16932let Defs = [USR_OVF];
16933}
16934def M2_vrcmpys_s1rp_l : HInst<
16935(outs IntRegs:$Rd32),
16936(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16937"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
16938tc_bafaade3, TypeM>, Enc_d2216a {
16939let Inst{7-5} = 0b111;
16940let Inst{13-13} = 0b0;
16941let Inst{31-21} = 0b11101001101;
16942let hasNewValue = 1;
16943let opNewValue = 0;
16944let prefersSlot3 = 1;
16945let Defs = [USR_OVF];
16946}
16947def M2_vrmac_s0 : HInst<
16948(outs DoubleRegs:$Rxx32),
16949(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16950"$Rxx32 += vrmpyh($Rss32,$Rtt32)",
16951tc_d773585a, TypeM>, Enc_88c16c {
16952let Inst{7-5} = 0b010;
16953let Inst{13-13} = 0b0;
16954let Inst{31-21} = 0b11101010000;
16955let prefersSlot3 = 1;
16956let Constraints = "$Rxx32 = $Rxx32in";
16957}
16958def M2_vrmpy_s0 : HInst<
16959(outs DoubleRegs:$Rdd32),
16960(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16961"$Rdd32 = vrmpyh($Rss32,$Rtt32)",
16962tc_bafaade3, TypeM>, Enc_a56825 {
16963let Inst{7-5} = 0b010;
16964let Inst{13-13} = 0b0;
16965let Inst{31-21} = 0b11101000000;
16966let prefersSlot3 = 1;
16967}
16968def M2_xor_xacc : HInst<
16969(outs IntRegs:$Rx32),
16970(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16971"$Rx32 ^= xor($Rs32,$Rt32)",
16972tc_f429765c, TypeM>, Enc_2ae154 {
16973let Inst{7-5} = 0b011;
16974let Inst{13-13} = 0b0;
16975let Inst{31-21} = 0b11101111100;
16976let hasNewValue = 1;
16977let opNewValue = 0;
16978let prefersSlot3 = 1;
16979let InputType = "reg";
16980let Constraints = "$Rx32 = $Rx32in";
16981}
16982def M4_and_and : HInst<
16983(outs IntRegs:$Rx32),
16984(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16985"$Rx32 &= and($Rs32,$Rt32)",
16986tc_f429765c, TypeM>, Enc_2ae154 {
16987let Inst{7-5} = 0b000;
16988let Inst{13-13} = 0b0;
16989let Inst{31-21} = 0b11101111010;
16990let hasNewValue = 1;
16991let opNewValue = 0;
16992let prefersSlot3 = 1;
16993let InputType = "reg";
16994let Constraints = "$Rx32 = $Rx32in";
16995}
16996def M4_and_andn : HInst<
16997(outs IntRegs:$Rx32),
16998(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16999"$Rx32 &= and($Rs32,~$Rt32)",
17000tc_f429765c, TypeM>, Enc_2ae154 {
17001let Inst{7-5} = 0b001;
17002let Inst{13-13} = 0b0;
17003let Inst{31-21} = 0b11101111001;
17004let hasNewValue = 1;
17005let opNewValue = 0;
17006let prefersSlot3 = 1;
17007let InputType = "reg";
17008let Constraints = "$Rx32 = $Rx32in";
17009}
17010def M4_and_or : HInst<
17011(outs IntRegs:$Rx32),
17012(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17013"$Rx32 &= or($Rs32,$Rt32)",
17014tc_f429765c, TypeM>, Enc_2ae154 {
17015let Inst{7-5} = 0b001;
17016let Inst{13-13} = 0b0;
17017let Inst{31-21} = 0b11101111010;
17018let hasNewValue = 1;
17019let opNewValue = 0;
17020let prefersSlot3 = 1;
17021let InputType = "reg";
17022let Constraints = "$Rx32 = $Rx32in";
17023}
17024def M4_and_xor : HInst<
17025(outs IntRegs:$Rx32),
17026(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17027"$Rx32 &= xor($Rs32,$Rt32)",
17028tc_f429765c, TypeM>, Enc_2ae154 {
17029let Inst{7-5} = 0b010;
17030let Inst{13-13} = 0b0;
17031let Inst{31-21} = 0b11101111010;
17032let hasNewValue = 1;
17033let opNewValue = 0;
17034let prefersSlot3 = 1;
17035let InputType = "reg";
17036let Constraints = "$Rx32 = $Rx32in";
17037}
17038def M4_cmpyi_wh : HInst<
17039(outs IntRegs:$Rd32),
17040(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17041"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
17042tc_bafaade3, TypeS_3op>, Enc_3d5b28 {
17043let Inst{7-5} = 0b100;
17044let Inst{13-13} = 0b0;
17045let Inst{31-21} = 0b11000101000;
17046let hasNewValue = 1;
17047let opNewValue = 0;
17048let prefersSlot3 = 1;
17049let Defs = [USR_OVF];
17050}
17051def M4_cmpyi_whc : HInst<
17052(outs IntRegs:$Rd32),
17053(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17054"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
17055tc_bafaade3, TypeS_3op>, Enc_3d5b28 {
17056let Inst{7-5} = 0b101;
17057let Inst{13-13} = 0b0;
17058let Inst{31-21} = 0b11000101000;
17059let hasNewValue = 1;
17060let opNewValue = 0;
17061let prefersSlot3 = 1;
17062let Defs = [USR_OVF];
17063}
17064def M4_cmpyr_wh : HInst<
17065(outs IntRegs:$Rd32),
17066(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17067"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
17068tc_bafaade3, TypeS_3op>, Enc_3d5b28 {
17069let Inst{7-5} = 0b110;
17070let Inst{13-13} = 0b0;
17071let Inst{31-21} = 0b11000101000;
17072let hasNewValue = 1;
17073let opNewValue = 0;
17074let prefersSlot3 = 1;
17075let Defs = [USR_OVF];
17076}
17077def M4_cmpyr_whc : HInst<
17078(outs IntRegs:$Rd32),
17079(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17080"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
17081tc_bafaade3, TypeS_3op>, Enc_3d5b28 {
17082let Inst{7-5} = 0b111;
17083let Inst{13-13} = 0b0;
17084let Inst{31-21} = 0b11000101000;
17085let hasNewValue = 1;
17086let opNewValue = 0;
17087let prefersSlot3 = 1;
17088let Defs = [USR_OVF];
17089}
17090def M4_mac_up_s1_sat : HInst<
17091(outs IntRegs:$Rx32),
17092(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17093"$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
17094tc_d773585a, TypeM>, Enc_2ae154 {
17095let Inst{7-5} = 0b000;
17096let Inst{13-13} = 0b0;
17097let Inst{31-21} = 0b11101111011;
17098let hasNewValue = 1;
17099let opNewValue = 0;
17100let prefersSlot3 = 1;
17101let Defs = [USR_OVF];
17102let InputType = "reg";
17103let Constraints = "$Rx32 = $Rx32in";
17104}
17105def M4_mpyri_addi : HInst<
17106(outs IntRegs:$Rd32),
17107(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
17108"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
17109tc_05d3a09b, TypeALU64>, Enc_322e1b, ImmRegRel {
17110let Inst{31-24} = 0b11011000;
17111let hasNewValue = 1;
17112let opNewValue = 0;
17113let prefersSlot3 = 1;
17114let CextOpcode = "M4_mpyri_addr";
17115let isExtendable = 1;
17116let opExtendable = 1;
17117let isExtentSigned = 0;
17118let opExtentBits = 6;
17119let opExtentAlign = 0;
17120}
17121def M4_mpyri_addr : HInst<
17122(outs IntRegs:$Rd32),
17123(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
17124"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
17125tc_05d3a09b, TypeALU64>, Enc_420cf3, ImmRegRel {
17126let Inst{31-23} = 0b110111111;
17127let hasNewValue = 1;
17128let opNewValue = 0;
17129let prefersSlot3 = 1;
17130let CextOpcode = "M4_mpyri_addr";
17131let InputType = "imm";
17132let isExtendable = 1;
17133let opExtendable = 3;
17134let isExtentSigned = 0;
17135let opExtentBits = 6;
17136let opExtentAlign = 0;
17137}
17138def M4_mpyri_addr_u2 : HInst<
17139(outs IntRegs:$Rd32),
17140(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
17141"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17142tc_1a2fd869, TypeALU64>, Enc_277737 {
17143let Inst{31-23} = 0b110111110;
17144let hasNewValue = 1;
17145let opNewValue = 0;
17146let prefersSlot3 = 1;
17147}
17148def M4_mpyrr_addi : HInst<
17149(outs IntRegs:$Rd32),
17150(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
17151"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17152tc_d773585a, TypeALU64>, Enc_a7b8e8, ImmRegRel {
17153let Inst{31-23} = 0b110101110;
17154let hasNewValue = 1;
17155let opNewValue = 0;
17156let prefersSlot3 = 1;
17157let CextOpcode = "M4_mpyrr_addr";
17158let InputType = "imm";
17159let isExtendable = 1;
17160let opExtendable = 1;
17161let isExtentSigned = 0;
17162let opExtentBits = 6;
17163let opExtentAlign = 0;
17164}
17165def M4_mpyrr_addr : HInst<
17166(outs IntRegs:$Ry32),
17167(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
17168"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17169tc_d773585a, TypeM>, Enc_7f1a05, ImmRegRel {
17170let Inst{7-5} = 0b000;
17171let Inst{13-13} = 0b0;
17172let Inst{31-21} = 0b11100011000;
17173let hasNewValue = 1;
17174let opNewValue = 0;
17175let prefersSlot3 = 1;
17176let CextOpcode = "M4_mpyrr_addr";
17177let InputType = "reg";
17178let Constraints = "$Ry32 = $Ry32in";
17179}
17180def M4_nac_up_s1_sat : HInst<
17181(outs IntRegs:$Rx32),
17182(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17183"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
17184tc_d773585a, TypeM>, Enc_2ae154 {
17185let Inst{7-5} = 0b001;
17186let Inst{13-13} = 0b0;
17187let Inst{31-21} = 0b11101111011;
17188let hasNewValue = 1;
17189let opNewValue = 0;
17190let prefersSlot3 = 1;
17191let Defs = [USR_OVF];
17192let InputType = "reg";
17193let Constraints = "$Rx32 = $Rx32in";
17194}
17195def M4_or_and : HInst<
17196(outs IntRegs:$Rx32),
17197(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17198"$Rx32 |= and($Rs32,$Rt32)",
17199tc_f429765c, TypeM>, Enc_2ae154 {
17200let Inst{7-5} = 0b011;
17201let Inst{13-13} = 0b0;
17202let Inst{31-21} = 0b11101111010;
17203let hasNewValue = 1;
17204let opNewValue = 0;
17205let prefersSlot3 = 1;
17206let InputType = "reg";
17207let Constraints = "$Rx32 = $Rx32in";
17208}
17209def M4_or_andn : HInst<
17210(outs IntRegs:$Rx32),
17211(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17212"$Rx32 |= and($Rs32,~$Rt32)",
17213tc_f429765c, TypeM>, Enc_2ae154 {
17214let Inst{7-5} = 0b000;
17215let Inst{13-13} = 0b0;
17216let Inst{31-21} = 0b11101111001;
17217let hasNewValue = 1;
17218let opNewValue = 0;
17219let prefersSlot3 = 1;
17220let InputType = "reg";
17221let Constraints = "$Rx32 = $Rx32in";
17222}
17223def M4_or_or : HInst<
17224(outs IntRegs:$Rx32),
17225(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17226"$Rx32 |= or($Rs32,$Rt32)",
17227tc_f429765c, TypeM>, Enc_2ae154 {
17228let Inst{7-5} = 0b000;
17229let Inst{13-13} = 0b0;
17230let Inst{31-21} = 0b11101111110;
17231let hasNewValue = 1;
17232let opNewValue = 0;
17233let prefersSlot3 = 1;
17234let InputType = "reg";
17235let Constraints = "$Rx32 = $Rx32in";
17236}
17237def M4_or_xor : HInst<
17238(outs IntRegs:$Rx32),
17239(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17240"$Rx32 |= xor($Rs32,$Rt32)",
17241tc_f429765c, TypeM>, Enc_2ae154 {
17242let Inst{7-5} = 0b001;
17243let Inst{13-13} = 0b0;
17244let Inst{31-21} = 0b11101111110;
17245let hasNewValue = 1;
17246let opNewValue = 0;
17247let prefersSlot3 = 1;
17248let InputType = "reg";
17249let Constraints = "$Rx32 = $Rx32in";
17250}
17251def M4_pmpyw : HInst<
17252(outs DoubleRegs:$Rdd32),
17253(ins IntRegs:$Rs32, IntRegs:$Rt32),
17254"$Rdd32 = pmpyw($Rs32,$Rt32)",
17255tc_bafaade3, TypeM>, Enc_be32a5 {
17256let Inst{7-5} = 0b111;
17257let Inst{13-13} = 0b0;
17258let Inst{31-21} = 0b11100101010;
17259let prefersSlot3 = 1;
17260}
17261def M4_pmpyw_acc : HInst<
17262(outs DoubleRegs:$Rxx32),
17263(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17264"$Rxx32 ^= pmpyw($Rs32,$Rt32)",
17265tc_d773585a, TypeM>, Enc_61f0b0 {
17266let Inst{7-5} = 0b111;
17267let Inst{13-13} = 0b0;
17268let Inst{31-21} = 0b11100111001;
17269let prefersSlot3 = 1;
17270let Constraints = "$Rxx32 = $Rxx32in";
17271}
17272def M4_vpmpyh : HInst<
17273(outs DoubleRegs:$Rdd32),
17274(ins IntRegs:$Rs32, IntRegs:$Rt32),
17275"$Rdd32 = vpmpyh($Rs32,$Rt32)",
17276tc_bafaade3, TypeM>, Enc_be32a5 {
17277let Inst{7-5} = 0b111;
17278let Inst{13-13} = 0b0;
17279let Inst{31-21} = 0b11100101110;
17280let prefersSlot3 = 1;
17281}
17282def M4_vpmpyh_acc : HInst<
17283(outs DoubleRegs:$Rxx32),
17284(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17285"$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
17286tc_d773585a, TypeM>, Enc_61f0b0 {
17287let Inst{7-5} = 0b111;
17288let Inst{13-13} = 0b0;
17289let Inst{31-21} = 0b11100111101;
17290let prefersSlot3 = 1;
17291let Constraints = "$Rxx32 = $Rxx32in";
17292}
17293def M4_vrmpyeh_acc_s0 : HInst<
17294(outs DoubleRegs:$Rxx32),
17295(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17296"$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
17297tc_d773585a, TypeM>, Enc_88c16c {
17298let Inst{7-5} = 0b110;
17299let Inst{13-13} = 0b0;
17300let Inst{31-21} = 0b11101010001;
17301let prefersSlot3 = 1;
17302let Constraints = "$Rxx32 = $Rxx32in";
17303}
17304def M4_vrmpyeh_acc_s1 : HInst<
17305(outs DoubleRegs:$Rxx32),
17306(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17307"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
17308tc_d773585a, TypeM>, Enc_88c16c {
17309let Inst{7-5} = 0b110;
17310let Inst{13-13} = 0b0;
17311let Inst{31-21} = 0b11101010101;
17312let prefersSlot3 = 1;
17313let Constraints = "$Rxx32 = $Rxx32in";
17314}
17315def M4_vrmpyeh_s0 : HInst<
17316(outs DoubleRegs:$Rdd32),
17317(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17318"$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
17319tc_bafaade3, TypeM>, Enc_a56825 {
17320let Inst{7-5} = 0b100;
17321let Inst{13-13} = 0b0;
17322let Inst{31-21} = 0b11101000010;
17323let prefersSlot3 = 1;
17324}
17325def M4_vrmpyeh_s1 : HInst<
17326(outs DoubleRegs:$Rdd32),
17327(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17328"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
17329tc_bafaade3, TypeM>, Enc_a56825 {
17330let Inst{7-5} = 0b100;
17331let Inst{13-13} = 0b0;
17332let Inst{31-21} = 0b11101000110;
17333let prefersSlot3 = 1;
17334}
17335def M4_vrmpyoh_acc_s0 : HInst<
17336(outs DoubleRegs:$Rxx32),
17337(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17338"$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
17339tc_d773585a, TypeM>, Enc_88c16c {
17340let Inst{7-5} = 0b110;
17341let Inst{13-13} = 0b0;
17342let Inst{31-21} = 0b11101010011;
17343let prefersSlot3 = 1;
17344let Constraints = "$Rxx32 = $Rxx32in";
17345}
17346def M4_vrmpyoh_acc_s1 : HInst<
17347(outs DoubleRegs:$Rxx32),
17348(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17349"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
17350tc_d773585a, TypeM>, Enc_88c16c {
17351let Inst{7-5} = 0b110;
17352let Inst{13-13} = 0b0;
17353let Inst{31-21} = 0b11101010111;
17354let prefersSlot3 = 1;
17355let Constraints = "$Rxx32 = $Rxx32in";
17356}
17357def M4_vrmpyoh_s0 : HInst<
17358(outs DoubleRegs:$Rdd32),
17359(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17360"$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
17361tc_bafaade3, TypeM>, Enc_a56825 {
17362let Inst{7-5} = 0b010;
17363let Inst{13-13} = 0b0;
17364let Inst{31-21} = 0b11101000001;
17365let prefersSlot3 = 1;
17366}
17367def M4_vrmpyoh_s1 : HInst<
17368(outs DoubleRegs:$Rdd32),
17369(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17370"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
17371tc_bafaade3, TypeM>, Enc_a56825 {
17372let Inst{7-5} = 0b010;
17373let Inst{13-13} = 0b0;
17374let Inst{31-21} = 0b11101000101;
17375let prefersSlot3 = 1;
17376}
17377def M4_xor_and : HInst<
17378(outs IntRegs:$Rx32),
17379(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17380"$Rx32 ^= and($Rs32,$Rt32)",
17381tc_f429765c, TypeM>, Enc_2ae154 {
17382let Inst{7-5} = 0b010;
17383let Inst{13-13} = 0b0;
17384let Inst{31-21} = 0b11101111110;
17385let hasNewValue = 1;
17386let opNewValue = 0;
17387let prefersSlot3 = 1;
17388let InputType = "reg";
17389let Constraints = "$Rx32 = $Rx32in";
17390}
17391def M4_xor_andn : HInst<
17392(outs IntRegs:$Rx32),
17393(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17394"$Rx32 ^= and($Rs32,~$Rt32)",
17395tc_f429765c, TypeM>, Enc_2ae154 {
17396let Inst{7-5} = 0b010;
17397let Inst{13-13} = 0b0;
17398let Inst{31-21} = 0b11101111001;
17399let hasNewValue = 1;
17400let opNewValue = 0;
17401let prefersSlot3 = 1;
17402let InputType = "reg";
17403let Constraints = "$Rx32 = $Rx32in";
17404}
17405def M4_xor_or : HInst<
17406(outs IntRegs:$Rx32),
17407(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17408"$Rx32 ^= or($Rs32,$Rt32)",
17409tc_f429765c, TypeM>, Enc_2ae154 {
17410let Inst{7-5} = 0b011;
17411let Inst{13-13} = 0b0;
17412let Inst{31-21} = 0b11101111110;
17413let hasNewValue = 1;
17414let opNewValue = 0;
17415let prefersSlot3 = 1;
17416let InputType = "reg";
17417let Constraints = "$Rx32 = $Rx32in";
17418}
17419def M4_xor_xacc : HInst<
17420(outs DoubleRegs:$Rxx32),
17421(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17422"$Rxx32 ^= xor($Rss32,$Rtt32)",
17423tc_f429765c, TypeS_3op>, Enc_88c16c {
17424let Inst{7-5} = 0b000;
17425let Inst{13-13} = 0b0;
17426let Inst{31-21} = 0b11001010100;
17427let prefersSlot3 = 1;
17428let Constraints = "$Rxx32 = $Rxx32in";
17429}
17430def M5_vdmacbsu : HInst<
17431(outs DoubleRegs:$Rxx32),
17432(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17433"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
17434tc_d773585a, TypeM>, Enc_88c16c {
17435let Inst{7-5} = 0b001;
17436let Inst{13-13} = 0b0;
17437let Inst{31-21} = 0b11101010001;
17438let prefersSlot3 = 1;
17439let Defs = [USR_OVF];
17440let Constraints = "$Rxx32 = $Rxx32in";
17441}
17442def M5_vdmpybsu : HInst<
17443(outs DoubleRegs:$Rdd32),
17444(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17445"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
17446tc_bafaade3, TypeM>, Enc_a56825 {
17447let Inst{7-5} = 0b001;
17448let Inst{13-13} = 0b0;
17449let Inst{31-21} = 0b11101000101;
17450let prefersSlot3 = 1;
17451let Defs = [USR_OVF];
17452}
17453def M5_vmacbsu : HInst<
17454(outs DoubleRegs:$Rxx32),
17455(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17456"$Rxx32 += vmpybsu($Rs32,$Rt32)",
17457tc_d773585a, TypeM>, Enc_61f0b0 {
17458let Inst{7-5} = 0b001;
17459let Inst{13-13} = 0b0;
17460let Inst{31-21} = 0b11100111110;
17461let prefersSlot3 = 1;
17462let Constraints = "$Rxx32 = $Rxx32in";
17463}
17464def M5_vmacbuu : HInst<
17465(outs DoubleRegs:$Rxx32),
17466(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17467"$Rxx32 += vmpybu($Rs32,$Rt32)",
17468tc_d773585a, TypeM>, Enc_61f0b0 {
17469let Inst{7-5} = 0b001;
17470let Inst{13-13} = 0b0;
17471let Inst{31-21} = 0b11100111100;
17472let prefersSlot3 = 1;
17473let Constraints = "$Rxx32 = $Rxx32in";
17474}
17475def M5_vmpybsu : HInst<
17476(outs DoubleRegs:$Rdd32),
17477(ins IntRegs:$Rs32, IntRegs:$Rt32),
17478"$Rdd32 = vmpybsu($Rs32,$Rt32)",
17479tc_bafaade3, TypeM>, Enc_be32a5 {
17480let Inst{7-5} = 0b001;
17481let Inst{13-13} = 0b0;
17482let Inst{31-21} = 0b11100101010;
17483let prefersSlot3 = 1;
17484}
17485def M5_vmpybuu : HInst<
17486(outs DoubleRegs:$Rdd32),
17487(ins IntRegs:$Rs32, IntRegs:$Rt32),
17488"$Rdd32 = vmpybu($Rs32,$Rt32)",
17489tc_bafaade3, TypeM>, Enc_be32a5 {
17490let Inst{7-5} = 0b001;
17491let Inst{13-13} = 0b0;
17492let Inst{31-21} = 0b11100101100;
17493let prefersSlot3 = 1;
17494}
17495def M5_vrmacbsu : HInst<
17496(outs DoubleRegs:$Rxx32),
17497(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17498"$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
17499tc_d773585a, TypeM>, Enc_88c16c {
17500let Inst{7-5} = 0b001;
17501let Inst{13-13} = 0b0;
17502let Inst{31-21} = 0b11101010110;
17503let prefersSlot3 = 1;
17504let Constraints = "$Rxx32 = $Rxx32in";
17505}
17506def M5_vrmacbuu : HInst<
17507(outs DoubleRegs:$Rxx32),
17508(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17509"$Rxx32 += vrmpybu($Rss32,$Rtt32)",
17510tc_d773585a, TypeM>, Enc_88c16c {
17511let Inst{7-5} = 0b001;
17512let Inst{13-13} = 0b0;
17513let Inst{31-21} = 0b11101010100;
17514let prefersSlot3 = 1;
17515let Constraints = "$Rxx32 = $Rxx32in";
17516}
17517def M5_vrmpybsu : HInst<
17518(outs DoubleRegs:$Rdd32),
17519(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17520"$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
17521tc_bafaade3, TypeM>, Enc_a56825 {
17522let Inst{7-5} = 0b001;
17523let Inst{13-13} = 0b0;
17524let Inst{31-21} = 0b11101000110;
17525let prefersSlot3 = 1;
17526}
17527def M5_vrmpybuu : HInst<
17528(outs DoubleRegs:$Rdd32),
17529(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17530"$Rdd32 = vrmpybu($Rss32,$Rtt32)",
17531tc_bafaade3, TypeM>, Enc_a56825 {
17532let Inst{7-5} = 0b001;
17533let Inst{13-13} = 0b0;
17534let Inst{31-21} = 0b11101000100;
17535let prefersSlot3 = 1;
17536}
17537def M6_vabsdiffb : HInst<
17538(outs DoubleRegs:$Rdd32),
17539(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17540"$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
17541tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17542let Inst{7-5} = 0b000;
17543let Inst{13-13} = 0b0;
17544let Inst{31-21} = 0b11101000111;
17545let prefersSlot3 = 1;
17546}
17547def M6_vabsdiffub : HInst<
17548(outs DoubleRegs:$Rdd32),
17549(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17550"$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
17551tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17552let Inst{7-5} = 0b000;
17553let Inst{13-13} = 0b0;
17554let Inst{31-21} = 0b11101000101;
17555let prefersSlot3 = 1;
17556}
17557def PS_loadrbabs : HInst<
17558(outs IntRegs:$Rd32),
17559(ins u32_0Imm:$Ii),
17560"$Rd32 = memb(#$Ii)",
17561tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17562let Inst{24-21} = 0b1000;
17563let Inst{31-27} = 0b01001;
17564let hasNewValue = 1;
17565let opNewValue = 0;
17566let addrMode = Absolute;
17567let accessSize = ByteAccess;
17568let mayLoad = 1;
17569let isExtended = 1;
17570let CextOpcode = "L2_loadrb";
17571let BaseOpcode = "L4_loadrb_abs";
17572let isPredicable = 1;
17573let DecoderNamespace = "MustExtend";
17574let isExtended = 1;
17575let opExtendable = 1;
17576let isExtentSigned = 0;
17577let opExtentBits = 16;
17578let opExtentAlign = 0;
17579}
17580def PS_loadrdabs : HInst<
17581(outs DoubleRegs:$Rdd32),
17582(ins u29_3Imm:$Ii),
17583"$Rdd32 = memd(#$Ii)",
17584tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel {
17585let Inst{24-21} = 0b1110;
17586let Inst{31-27} = 0b01001;
17587let addrMode = Absolute;
17588let accessSize = DoubleWordAccess;
17589let mayLoad = 1;
17590let isExtended = 1;
17591let CextOpcode = "L2_loadrd";
17592let BaseOpcode = "L4_loadrd_abs";
17593let isPredicable = 1;
17594let DecoderNamespace = "MustExtend";
17595let isExtended = 1;
17596let opExtendable = 1;
17597let isExtentSigned = 0;
17598let opExtentBits = 19;
17599let opExtentAlign = 3;
17600}
17601def PS_loadrhabs : HInst<
17602(outs IntRegs:$Rd32),
17603(ins u31_1Imm:$Ii),
17604"$Rd32 = memh(#$Ii)",
17605tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17606let Inst{24-21} = 0b1010;
17607let Inst{31-27} = 0b01001;
17608let hasNewValue = 1;
17609let opNewValue = 0;
17610let addrMode = Absolute;
17611let accessSize = HalfWordAccess;
17612let mayLoad = 1;
17613let isExtended = 1;
17614let CextOpcode = "L2_loadrh";
17615let BaseOpcode = "L4_loadrh_abs";
17616let isPredicable = 1;
17617let DecoderNamespace = "MustExtend";
17618let isExtended = 1;
17619let opExtendable = 1;
17620let isExtentSigned = 0;
17621let opExtentBits = 17;
17622let opExtentAlign = 1;
17623}
17624def PS_loadriabs : HInst<
17625(outs IntRegs:$Rd32),
17626(ins u30_2Imm:$Ii),
17627"$Rd32 = memw(#$Ii)",
17628tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
17629let Inst{24-21} = 0b1100;
17630let Inst{31-27} = 0b01001;
17631let hasNewValue = 1;
17632let opNewValue = 0;
17633let addrMode = Absolute;
17634let accessSize = WordAccess;
17635let mayLoad = 1;
17636let isExtended = 1;
17637let CextOpcode = "L2_loadri";
17638let BaseOpcode = "L4_loadri_abs";
17639let isPredicable = 1;
17640let DecoderNamespace = "MustExtend";
17641let isExtended = 1;
17642let opExtendable = 1;
17643let isExtentSigned = 0;
17644let opExtentBits = 18;
17645let opExtentAlign = 2;
17646}
17647def PS_loadrubabs : HInst<
17648(outs IntRegs:$Rd32),
17649(ins u32_0Imm:$Ii),
17650"$Rd32 = memub(#$Ii)",
17651tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17652let Inst{24-21} = 0b1001;
17653let Inst{31-27} = 0b01001;
17654let hasNewValue = 1;
17655let opNewValue = 0;
17656let addrMode = Absolute;
17657let accessSize = ByteAccess;
17658let mayLoad = 1;
17659let isExtended = 1;
17660let CextOpcode = "L2_loadrub";
17661let BaseOpcode = "L4_loadrub_abs";
17662let isPredicable = 1;
17663let DecoderNamespace = "MustExtend";
17664let isExtended = 1;
17665let opExtendable = 1;
17666let isExtentSigned = 0;
17667let opExtentBits = 16;
17668let opExtentAlign = 0;
17669}
17670def PS_loadruhabs : HInst<
17671(outs IntRegs:$Rd32),
17672(ins u31_1Imm:$Ii),
17673"$Rd32 = memuh(#$Ii)",
17674tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17675let Inst{24-21} = 0b1011;
17676let Inst{31-27} = 0b01001;
17677let hasNewValue = 1;
17678let opNewValue = 0;
17679let addrMode = Absolute;
17680let accessSize = HalfWordAccess;
17681let mayLoad = 1;
17682let isExtended = 1;
17683let CextOpcode = "L2_loadruh";
17684let BaseOpcode = "L4_loadruh_abs";
17685let isPredicable = 1;
17686let DecoderNamespace = "MustExtend";
17687let isExtended = 1;
17688let opExtendable = 1;
17689let isExtentSigned = 0;
17690let opExtentBits = 17;
17691let opExtentAlign = 1;
17692}
17693def PS_storerbabs : HInst<
17694(outs),
17695(ins u32_0Imm:$Ii, IntRegs:$Rt32),
17696"memb(#$Ii) = $Rt32",
17697tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
17698let Inst{24-21} = 0b0000;
17699let Inst{31-27} = 0b01001;
17700let addrMode = Absolute;
17701let accessSize = ByteAccess;
17702let isExtended = 1;
17703let mayStore = 1;
17704let CextOpcode = "S2_storerb";
17705let BaseOpcode = "S2_storerbabs";
17706let isPredicable = 1;
17707let isNVStorable = 1;
17708let DecoderNamespace = "MustExtend";
17709let isExtended = 1;
17710let opExtendable = 0;
17711let isExtentSigned = 0;
17712let opExtentBits = 16;
17713let opExtentAlign = 0;
17714}
17715def PS_storerbnewabs : HInst<
17716(outs),
17717(ins u32_0Imm:$Ii, IntRegs:$Nt8),
17718"memb(#$Ii) = $Nt8.new",
17719tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel {
17720let Inst{12-11} = 0b00;
17721let Inst{24-21} = 0b0101;
17722let Inst{31-27} = 0b01001;
17723let addrMode = Absolute;
17724let accessSize = ByteAccess;
17725let isNVStore = 1;
17726let isNewValue = 1;
17727let isExtended = 1;
17728let isRestrictNoSlot1Store = 1;
17729let mayStore = 1;
17730let CextOpcode = "S2_storerb";
17731let BaseOpcode = "S2_storerbabs";
17732let isPredicable = 1;
17733let DecoderNamespace = "MustExtend";
17734let isExtended = 1;
17735let opExtendable = 0;
17736let isExtentSigned = 0;
17737let opExtentBits = 16;
17738let opExtentAlign = 0;
17739let opNewValue = 1;
17740}
17741def PS_storerdabs : HInst<
17742(outs),
17743(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
17744"memd(#$Ii) = $Rtt32",
17745tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel {
17746let Inst{24-21} = 0b0110;
17747let Inst{31-27} = 0b01001;
17748let addrMode = Absolute;
17749let accessSize = DoubleWordAccess;
17750let isExtended = 1;
17751let mayStore = 1;
17752let CextOpcode = "S2_storerd";
17753let BaseOpcode = "S2_storerdabs";
17754let isPredicable = 1;
17755let DecoderNamespace = "MustExtend";
17756let isExtended = 1;
17757let opExtendable = 0;
17758let isExtentSigned = 0;
17759let opExtentBits = 19;
17760let opExtentAlign = 3;
17761}
17762def PS_storerfabs : HInst<
17763(outs),
17764(ins u31_1Imm:$Ii, IntRegs:$Rt32),
17765"memh(#$Ii) = $Rt32.h",
17766tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel {
17767let Inst{24-21} = 0b0011;
17768let Inst{31-27} = 0b01001;
17769let addrMode = Absolute;
17770let accessSize = HalfWordAccess;
17771let isExtended = 1;
17772let mayStore = 1;
17773let CextOpcode = "S2_storerf";
17774let BaseOpcode = "S2_storerfabs";
17775let isPredicable = 1;
17776let DecoderNamespace = "MustExtend";
17777let isExtended = 1;
17778let opExtendable = 0;
17779let isExtentSigned = 0;
17780let opExtentBits = 17;
17781let opExtentAlign = 1;
17782}
17783def PS_storerhabs : HInst<
17784(outs),
17785(ins u31_1Imm:$Ii, IntRegs:$Rt32),
17786"memh(#$Ii) = $Rt32",
17787tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel {
17788let Inst{24-21} = 0b0010;
17789let Inst{31-27} = 0b01001;
17790let addrMode = Absolute;
17791let accessSize = HalfWordAccess;
17792let isExtended = 1;
17793let mayStore = 1;
17794let CextOpcode = "S2_storerh";
17795let BaseOpcode = "S2_storerhabs";
17796let isPredicable = 1;
17797let isNVStorable = 1;
17798let DecoderNamespace = "MustExtend";
17799let isExtended = 1;
17800let opExtendable = 0;
17801let isExtentSigned = 0;
17802let opExtentBits = 17;
17803let opExtentAlign = 1;
17804}
17805def PS_storerhnewabs : HInst<
17806(outs),
17807(ins u31_1Imm:$Ii, IntRegs:$Nt8),
17808"memh(#$Ii) = $Nt8.new",
17809tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
17810let Inst{12-11} = 0b01;
17811let Inst{24-21} = 0b0101;
17812let Inst{31-27} = 0b01001;
17813let addrMode = Absolute;
17814let accessSize = HalfWordAccess;
17815let isNVStore = 1;
17816let isNewValue = 1;
17817let isExtended = 1;
17818let isRestrictNoSlot1Store = 1;
17819let mayStore = 1;
17820let CextOpcode = "S2_storerh";
17821let BaseOpcode = "S2_storerhabs";
17822let isPredicable = 1;
17823let DecoderNamespace = "MustExtend";
17824let isExtended = 1;
17825let opExtendable = 0;
17826let isExtentSigned = 0;
17827let opExtentBits = 17;
17828let opExtentAlign = 1;
17829let opNewValue = 1;
17830}
17831def PS_storeriabs : HInst<
17832(outs),
17833(ins u30_2Imm:$Ii, IntRegs:$Rt32),
17834"memw(#$Ii) = $Rt32",
17835tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel {
17836let Inst{24-21} = 0b0100;
17837let Inst{31-27} = 0b01001;
17838let addrMode = Absolute;
17839let accessSize = WordAccess;
17840let isExtended = 1;
17841let mayStore = 1;
17842let CextOpcode = "S2_storeri";
17843let BaseOpcode = "S2_storeriabs";
17844let isPredicable = 1;
17845let isNVStorable = 1;
17846let DecoderNamespace = "MustExtend";
17847let isExtended = 1;
17848let opExtendable = 0;
17849let isExtentSigned = 0;
17850let opExtentBits = 18;
17851let opExtentAlign = 2;
17852}
17853def PS_storerinewabs : HInst<
17854(outs),
17855(ins u30_2Imm:$Ii, IntRegs:$Nt8),
17856"memw(#$Ii) = $Nt8.new",
17857tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
17858let Inst{12-11} = 0b10;
17859let Inst{24-21} = 0b0101;
17860let Inst{31-27} = 0b01001;
17861let addrMode = Absolute;
17862let accessSize = WordAccess;
17863let isNVStore = 1;
17864let isNewValue = 1;
17865let isExtended = 1;
17866let isRestrictNoSlot1Store = 1;
17867let mayStore = 1;
17868let CextOpcode = "S2_storeri";
17869let BaseOpcode = "S2_storeriabs";
17870let isPredicable = 1;
17871let DecoderNamespace = "MustExtend";
17872let isExtended = 1;
17873let opExtendable = 0;
17874let isExtentSigned = 0;
17875let opExtentBits = 18;
17876let opExtentAlign = 2;
17877let opNewValue = 1;
17878}
17879def S2_addasl_rrri : HInst<
17880(outs IntRegs:$Rd32),
17881(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
17882"$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
17883tc_f675fee8, TypeS_3op>, Enc_47ef61 {
17884let Inst{13-13} = 0b0;
17885let Inst{31-21} = 0b11000100000;
17886let hasNewValue = 1;
17887let opNewValue = 0;
17888let prefersSlot3 = 1;
17889}
17890def S2_allocframe : HInst<
17891(outs IntRegs:$Rx32),
17892(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
17893"allocframe($Rx32,#$Ii):raw",
17894tc_b44ecf75, TypeST>, Enc_22c845 {
17895let Inst{13-11} = 0b000;
17896let Inst{31-21} = 0b10100000100;
17897let hasNewValue = 1;
17898let opNewValue = 0;
17899let addrMode = BaseImmOffset;
17900let accessSize = DoubleWordAccess;
17901let mayStore = 1;
17902let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
17903let Defs = [R30];
17904let Constraints = "$Rx32 = $Rx32in";
17905}
17906def S2_asl_i_p : HInst<
17907(outs DoubleRegs:$Rdd32),
17908(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
17909"$Rdd32 = asl($Rss32,#$Ii)",
17910tc_946df596, TypeS_2op>, Enc_5eac98 {
17911let Inst{7-5} = 0b010;
17912let Inst{31-21} = 0b10000000000;
17913}
17914def S2_asl_i_p_acc : HInst<
17915(outs DoubleRegs:$Rxx32),
17916(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17917"$Rxx32 += asl($Rss32,#$Ii)",
17918tc_f675fee8, TypeS_2op>, Enc_70fb07 {
17919let Inst{7-5} = 0b110;
17920let Inst{31-21} = 0b10000010000;
17921let prefersSlot3 = 1;
17922let Constraints = "$Rxx32 = $Rxx32in";
17923}
17924def S2_asl_i_p_and : HInst<
17925(outs DoubleRegs:$Rxx32),
17926(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17927"$Rxx32 &= asl($Rss32,#$Ii)",
17928tc_f429765c, TypeS_2op>, Enc_70fb07 {
17929let Inst{7-5} = 0b010;
17930let Inst{31-21} = 0b10000010010;
17931let prefersSlot3 = 1;
17932let Constraints = "$Rxx32 = $Rxx32in";
17933}
17934def S2_asl_i_p_nac : HInst<
17935(outs DoubleRegs:$Rxx32),
17936(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17937"$Rxx32 -= asl($Rss32,#$Ii)",
17938tc_f675fee8, TypeS_2op>, Enc_70fb07 {
17939let Inst{7-5} = 0b010;
17940let Inst{31-21} = 0b10000010000;
17941let prefersSlot3 = 1;
17942let Constraints = "$Rxx32 = $Rxx32in";
17943}
17944def S2_asl_i_p_or : HInst<
17945(outs DoubleRegs:$Rxx32),
17946(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17947"$Rxx32 |= asl($Rss32,#$Ii)",
17948tc_f429765c, TypeS_2op>, Enc_70fb07 {
17949let Inst{7-5} = 0b110;
17950let Inst{31-21} = 0b10000010010;
17951let prefersSlot3 = 1;
17952let Constraints = "$Rxx32 = $Rxx32in";
17953}
17954def S2_asl_i_p_xacc : HInst<
17955(outs DoubleRegs:$Rxx32),
17956(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
17957"$Rxx32 ^= asl($Rss32,#$Ii)",
17958tc_f429765c, TypeS_2op>, Enc_70fb07 {
17959let Inst{7-5} = 0b010;
17960let Inst{31-21} = 0b10000010100;
17961let prefersSlot3 = 1;
17962let Constraints = "$Rxx32 = $Rxx32in";
17963}
17964def S2_asl_i_r : HInst<
17965(outs IntRegs:$Rd32),
17966(ins IntRegs:$Rs32, u5_0Imm:$Ii),
17967"$Rd32 = asl($Rs32,#$Ii)",
17968tc_946df596, TypeS_2op>, Enc_a05677 {
17969let Inst{7-5} = 0b010;
17970let Inst{13-13} = 0b0;
17971let Inst{31-21} = 0b10001100000;
17972let hasNewValue = 1;
17973let opNewValue = 0;
17974}
17975def S2_asl_i_r_acc : HInst<
17976(outs IntRegs:$Rx32),
17977(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
17978"$Rx32 += asl($Rs32,#$Ii)",
17979tc_f675fee8, TypeS_2op>, Enc_28a2dc {
17980let Inst{7-5} = 0b110;
17981let Inst{13-13} = 0b0;
17982let Inst{31-21} = 0b10001110000;
17983let hasNewValue = 1;
17984let opNewValue = 0;
17985let prefersSlot3 = 1;
17986let Constraints = "$Rx32 = $Rx32in";
17987}
17988def S2_asl_i_r_and : HInst<
17989(outs IntRegs:$Rx32),
17990(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
17991"$Rx32 &= asl($Rs32,#$Ii)",
17992tc_f429765c, TypeS_2op>, Enc_28a2dc {
17993let Inst{7-5} = 0b010;
17994let Inst{13-13} = 0b0;
17995let Inst{31-21} = 0b10001110010;
17996let hasNewValue = 1;
17997let opNewValue = 0;
17998let prefersSlot3 = 1;
17999let Constraints = "$Rx32 = $Rx32in";
18000}
18001def S2_asl_i_r_nac : HInst<
18002(outs IntRegs:$Rx32),
18003(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18004"$Rx32 -= asl($Rs32,#$Ii)",
18005tc_f675fee8, TypeS_2op>, Enc_28a2dc {
18006let Inst{7-5} = 0b010;
18007let Inst{13-13} = 0b0;
18008let Inst{31-21} = 0b10001110000;
18009let hasNewValue = 1;
18010let opNewValue = 0;
18011let prefersSlot3 = 1;
18012let Constraints = "$Rx32 = $Rx32in";
18013}
18014def S2_asl_i_r_or : HInst<
18015(outs IntRegs:$Rx32),
18016(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18017"$Rx32 |= asl($Rs32,#$Ii)",
18018tc_f429765c, TypeS_2op>, Enc_28a2dc {
18019let Inst{7-5} = 0b110;
18020let Inst{13-13} = 0b0;
18021let Inst{31-21} = 0b10001110010;
18022let hasNewValue = 1;
18023let opNewValue = 0;
18024let prefersSlot3 = 1;
18025let Constraints = "$Rx32 = $Rx32in";
18026}
18027def S2_asl_i_r_sat : HInst<
18028(outs IntRegs:$Rd32),
18029(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18030"$Rd32 = asl($Rs32,#$Ii):sat",
18031tc_779080bf, TypeS_2op>, Enc_a05677 {
18032let Inst{7-5} = 0b010;
18033let Inst{13-13} = 0b0;
18034let Inst{31-21} = 0b10001100010;
18035let hasNewValue = 1;
18036let opNewValue = 0;
18037let prefersSlot3 = 1;
18038let Defs = [USR_OVF];
18039}
18040def S2_asl_i_r_xacc : HInst<
18041(outs IntRegs:$Rx32),
18042(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18043"$Rx32 ^= asl($Rs32,#$Ii)",
18044tc_f429765c, TypeS_2op>, Enc_28a2dc {
18045let Inst{7-5} = 0b010;
18046let Inst{13-13} = 0b0;
18047let Inst{31-21} = 0b10001110100;
18048let hasNewValue = 1;
18049let opNewValue = 0;
18050let prefersSlot3 = 1;
18051let Constraints = "$Rx32 = $Rx32in";
18052}
18053def S2_asl_i_vh : HInst<
18054(outs DoubleRegs:$Rdd32),
18055(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18056"$Rdd32 = vaslh($Rss32,#$Ii)",
18057tc_946df596, TypeS_2op>, Enc_12b6e9 {
18058let Inst{7-5} = 0b010;
18059let Inst{13-12} = 0b00;
18060let Inst{31-21} = 0b10000000100;
18061}
18062def S2_asl_i_vw : HInst<
18063(outs DoubleRegs:$Rdd32),
18064(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18065"$Rdd32 = vaslw($Rss32,#$Ii)",
18066tc_946df596, TypeS_2op>, Enc_7e5a82 {
18067let Inst{7-5} = 0b010;
18068let Inst{13-13} = 0b0;
18069let Inst{31-21} = 0b10000000010;
18070}
18071def S2_asl_r_p : HInst<
18072(outs DoubleRegs:$Rdd32),
18073(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18074"$Rdd32 = asl($Rss32,$Rt32)",
18075tc_946df596, TypeS_3op>, Enc_927852 {
18076let Inst{7-5} = 0b100;
18077let Inst{13-13} = 0b0;
18078let Inst{31-21} = 0b11000011100;
18079}
18080def S2_asl_r_p_acc : HInst<
18081(outs DoubleRegs:$Rxx32),
18082(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18083"$Rxx32 += asl($Rss32,$Rt32)",
18084tc_f675fee8, TypeS_3op>, Enc_1aa186 {
18085let Inst{7-5} = 0b100;
18086let Inst{13-13} = 0b0;
18087let Inst{31-21} = 0b11001011110;
18088let prefersSlot3 = 1;
18089let Constraints = "$Rxx32 = $Rxx32in";
18090}
18091def S2_asl_r_p_and : HInst<
18092(outs DoubleRegs:$Rxx32),
18093(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18094"$Rxx32 &= asl($Rss32,$Rt32)",
18095tc_f429765c, TypeS_3op>, Enc_1aa186 {
18096let Inst{7-5} = 0b100;
18097let Inst{13-13} = 0b0;
18098let Inst{31-21} = 0b11001011010;
18099let prefersSlot3 = 1;
18100let Constraints = "$Rxx32 = $Rxx32in";
18101}
18102def S2_asl_r_p_nac : HInst<
18103(outs DoubleRegs:$Rxx32),
18104(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18105"$Rxx32 -= asl($Rss32,$Rt32)",
18106tc_f675fee8, TypeS_3op>, Enc_1aa186 {
18107let Inst{7-5} = 0b100;
18108let Inst{13-13} = 0b0;
18109let Inst{31-21} = 0b11001011100;
18110let prefersSlot3 = 1;
18111let Constraints = "$Rxx32 = $Rxx32in";
18112}
18113def S2_asl_r_p_or : HInst<
18114(outs DoubleRegs:$Rxx32),
18115(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18116"$Rxx32 |= asl($Rss32,$Rt32)",
18117tc_f429765c, TypeS_3op>, Enc_1aa186 {
18118let Inst{7-5} = 0b100;
18119let Inst{13-13} = 0b0;
18120let Inst{31-21} = 0b11001011000;
18121let prefersSlot3 = 1;
18122let Constraints = "$Rxx32 = $Rxx32in";
18123}
18124def S2_asl_r_p_xor : HInst<
18125(outs DoubleRegs:$Rxx32),
18126(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18127"$Rxx32 ^= asl($Rss32,$Rt32)",
18128tc_f429765c, TypeS_3op>, Enc_1aa186 {
18129let Inst{7-5} = 0b100;
18130let Inst{13-13} = 0b0;
18131let Inst{31-21} = 0b11001011011;
18132let prefersSlot3 = 1;
18133let Constraints = "$Rxx32 = $Rxx32in";
18134}
18135def S2_asl_r_r : HInst<
18136(outs IntRegs:$Rd32),
18137(ins IntRegs:$Rs32, IntRegs:$Rt32),
18138"$Rd32 = asl($Rs32,$Rt32)",
18139tc_946df596, TypeS_3op>, Enc_5ab2be {
18140let Inst{7-5} = 0b100;
18141let Inst{13-13} = 0b0;
18142let Inst{31-21} = 0b11000110010;
18143let hasNewValue = 1;
18144let opNewValue = 0;
18145}
18146def S2_asl_r_r_acc : HInst<
18147(outs IntRegs:$Rx32),
18148(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18149"$Rx32 += asl($Rs32,$Rt32)",
18150tc_f675fee8, TypeS_3op>, Enc_2ae154 {
18151let Inst{7-5} = 0b100;
18152let Inst{13-13} = 0b0;
18153let Inst{31-21} = 0b11001100110;
18154let hasNewValue = 1;
18155let opNewValue = 0;
18156let prefersSlot3 = 1;
18157let Constraints = "$Rx32 = $Rx32in";
18158}
18159def S2_asl_r_r_and : HInst<
18160(outs IntRegs:$Rx32),
18161(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18162"$Rx32 &= asl($Rs32,$Rt32)",
18163tc_f429765c, TypeS_3op>, Enc_2ae154 {
18164let Inst{7-5} = 0b100;
18165let Inst{13-13} = 0b0;
18166let Inst{31-21} = 0b11001100010;
18167let hasNewValue = 1;
18168let opNewValue = 0;
18169let prefersSlot3 = 1;
18170let Constraints = "$Rx32 = $Rx32in";
18171}
18172def S2_asl_r_r_nac : HInst<
18173(outs IntRegs:$Rx32),
18174(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18175"$Rx32 -= asl($Rs32,$Rt32)",
18176tc_f675fee8, TypeS_3op>, Enc_2ae154 {
18177let Inst{7-5} = 0b100;
18178let Inst{13-13} = 0b0;
18179let Inst{31-21} = 0b11001100100;
18180let hasNewValue = 1;
18181let opNewValue = 0;
18182let prefersSlot3 = 1;
18183let Constraints = "$Rx32 = $Rx32in";
18184}
18185def S2_asl_r_r_or : HInst<
18186(outs IntRegs:$Rx32),
18187(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18188"$Rx32 |= asl($Rs32,$Rt32)",
18189tc_f429765c, TypeS_3op>, Enc_2ae154 {
18190let Inst{7-5} = 0b100;
18191let Inst{13-13} = 0b0;
18192let Inst{31-21} = 0b11001100000;
18193let hasNewValue = 1;
18194let opNewValue = 0;
18195let prefersSlot3 = 1;
18196let Constraints = "$Rx32 = $Rx32in";
18197}
18198def S2_asl_r_r_sat : HInst<
18199(outs IntRegs:$Rd32),
18200(ins IntRegs:$Rs32, IntRegs:$Rt32),
18201"$Rd32 = asl($Rs32,$Rt32):sat",
18202tc_779080bf, TypeS_3op>, Enc_5ab2be {
18203let Inst{7-5} = 0b100;
18204let Inst{13-13} = 0b0;
18205let Inst{31-21} = 0b11000110000;
18206let hasNewValue = 1;
18207let opNewValue = 0;
18208let prefersSlot3 = 1;
18209let Defs = [USR_OVF];
18210}
18211def S2_asl_r_vh : HInst<
18212(outs DoubleRegs:$Rdd32),
18213(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18214"$Rdd32 = vaslh($Rss32,$Rt32)",
18215tc_946df596, TypeS_3op>, Enc_927852 {
18216let Inst{7-5} = 0b100;
18217let Inst{13-13} = 0b0;
18218let Inst{31-21} = 0b11000011010;
18219}
18220def S2_asl_r_vw : HInst<
18221(outs DoubleRegs:$Rdd32),
18222(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18223"$Rdd32 = vaslw($Rss32,$Rt32)",
18224tc_946df596, TypeS_3op>, Enc_927852 {
18225let Inst{7-5} = 0b100;
18226let Inst{13-13} = 0b0;
18227let Inst{31-21} = 0b11000011000;
18228}
18229def S2_asr_i_p : HInst<
18230(outs DoubleRegs:$Rdd32),
18231(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18232"$Rdd32 = asr($Rss32,#$Ii)",
18233tc_946df596, TypeS_2op>, Enc_5eac98 {
18234let Inst{7-5} = 0b000;
18235let Inst{31-21} = 0b10000000000;
18236}
18237def S2_asr_i_p_acc : HInst<
18238(outs DoubleRegs:$Rxx32),
18239(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18240"$Rxx32 += asr($Rss32,#$Ii)",
18241tc_f675fee8, TypeS_2op>, Enc_70fb07 {
18242let Inst{7-5} = 0b100;
18243let Inst{31-21} = 0b10000010000;
18244let prefersSlot3 = 1;
18245let Constraints = "$Rxx32 = $Rxx32in";
18246}
18247def S2_asr_i_p_and : HInst<
18248(outs DoubleRegs:$Rxx32),
18249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18250"$Rxx32 &= asr($Rss32,#$Ii)",
18251tc_f429765c, TypeS_2op>, Enc_70fb07 {
18252let Inst{7-5} = 0b000;
18253let Inst{31-21} = 0b10000010010;
18254let prefersSlot3 = 1;
18255let Constraints = "$Rxx32 = $Rxx32in";
18256}
18257def S2_asr_i_p_nac : HInst<
18258(outs DoubleRegs:$Rxx32),
18259(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18260"$Rxx32 -= asr($Rss32,#$Ii)",
18261tc_f675fee8, TypeS_2op>, Enc_70fb07 {
18262let Inst{7-5} = 0b000;
18263let Inst{31-21} = 0b10000010000;
18264let prefersSlot3 = 1;
18265let Constraints = "$Rxx32 = $Rxx32in";
18266}
18267def S2_asr_i_p_or : HInst<
18268(outs DoubleRegs:$Rxx32),
18269(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18270"$Rxx32 |= asr($Rss32,#$Ii)",
18271tc_f429765c, TypeS_2op>, Enc_70fb07 {
18272let Inst{7-5} = 0b100;
18273let Inst{31-21} = 0b10000010010;
18274let prefersSlot3 = 1;
18275let Constraints = "$Rxx32 = $Rxx32in";
18276}
18277def S2_asr_i_p_rnd : HInst<
18278(outs DoubleRegs:$Rdd32),
18279(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18280"$Rdd32 = asr($Rss32,#$Ii):rnd",
18281tc_002cb246, TypeS_2op>, Enc_5eac98 {
18282let Inst{7-5} = 0b111;
18283let Inst{31-21} = 0b10000000110;
18284let prefersSlot3 = 1;
18285}
18286def S2_asr_i_p_rnd_goodsyntax : HInst<
18287(outs DoubleRegs:$Rdd32),
18288(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18289"$Rdd32 = asrrnd($Rss32,#$Ii)",
18290tc_002cb246, TypeS_2op> {
18291let isPseudo = 1;
18292}
18293def S2_asr_i_r : HInst<
18294(outs IntRegs:$Rd32),
18295(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18296"$Rd32 = asr($Rs32,#$Ii)",
18297tc_946df596, TypeS_2op>, Enc_a05677 {
18298let Inst{7-5} = 0b000;
18299let Inst{13-13} = 0b0;
18300let Inst{31-21} = 0b10001100000;
18301let hasNewValue = 1;
18302let opNewValue = 0;
18303}
18304def S2_asr_i_r_acc : HInst<
18305(outs IntRegs:$Rx32),
18306(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18307"$Rx32 += asr($Rs32,#$Ii)",
18308tc_f675fee8, TypeS_2op>, Enc_28a2dc {
18309let Inst{7-5} = 0b100;
18310let Inst{13-13} = 0b0;
18311let Inst{31-21} = 0b10001110000;
18312let hasNewValue = 1;
18313let opNewValue = 0;
18314let prefersSlot3 = 1;
18315let Constraints = "$Rx32 = $Rx32in";
18316}
18317def S2_asr_i_r_and : HInst<
18318(outs IntRegs:$Rx32),
18319(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18320"$Rx32 &= asr($Rs32,#$Ii)",
18321tc_f429765c, TypeS_2op>, Enc_28a2dc {
18322let Inst{7-5} = 0b000;
18323let Inst{13-13} = 0b0;
18324let Inst{31-21} = 0b10001110010;
18325let hasNewValue = 1;
18326let opNewValue = 0;
18327let prefersSlot3 = 1;
18328let Constraints = "$Rx32 = $Rx32in";
18329}
18330def S2_asr_i_r_nac : HInst<
18331(outs IntRegs:$Rx32),
18332(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18333"$Rx32 -= asr($Rs32,#$Ii)",
18334tc_f675fee8, TypeS_2op>, Enc_28a2dc {
18335let Inst{7-5} = 0b000;
18336let Inst{13-13} = 0b0;
18337let Inst{31-21} = 0b10001110000;
18338let hasNewValue = 1;
18339let opNewValue = 0;
18340let prefersSlot3 = 1;
18341let Constraints = "$Rx32 = $Rx32in";
18342}
18343def S2_asr_i_r_or : HInst<
18344(outs IntRegs:$Rx32),
18345(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18346"$Rx32 |= asr($Rs32,#$Ii)",
18347tc_f429765c, TypeS_2op>, Enc_28a2dc {
18348let Inst{7-5} = 0b100;
18349let Inst{13-13} = 0b0;
18350let Inst{31-21} = 0b10001110010;
18351let hasNewValue = 1;
18352let opNewValue = 0;
18353let prefersSlot3 = 1;
18354let Constraints = "$Rx32 = $Rx32in";
18355}
18356def S2_asr_i_r_rnd : HInst<
18357(outs IntRegs:$Rd32),
18358(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18359"$Rd32 = asr($Rs32,#$Ii):rnd",
18360tc_002cb246, TypeS_2op>, Enc_a05677 {
18361let Inst{7-5} = 0b000;
18362let Inst{13-13} = 0b0;
18363let Inst{31-21} = 0b10001100010;
18364let hasNewValue = 1;
18365let opNewValue = 0;
18366let prefersSlot3 = 1;
18367}
18368def S2_asr_i_r_rnd_goodsyntax : HInst<
18369(outs IntRegs:$Rd32),
18370(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18371"$Rd32 = asrrnd($Rs32,#$Ii)",
18372tc_002cb246, TypeS_2op> {
18373let hasNewValue = 1;
18374let opNewValue = 0;
18375let isPseudo = 1;
18376}
18377def S2_asr_i_svw_trun : HInst<
18378(outs IntRegs:$Rd32),
18379(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18380"$Rd32 = vasrw($Rss32,#$Ii)",
18381tc_4414d8b1, TypeS_2op>, Enc_8dec2e {
18382let Inst{7-5} = 0b010;
18383let Inst{13-13} = 0b0;
18384let Inst{31-21} = 0b10001000110;
18385let hasNewValue = 1;
18386let opNewValue = 0;
18387let prefersSlot3 = 1;
18388}
18389def S2_asr_i_vh : HInst<
18390(outs DoubleRegs:$Rdd32),
18391(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18392"$Rdd32 = vasrh($Rss32,#$Ii)",
18393tc_946df596, TypeS_2op>, Enc_12b6e9 {
18394let Inst{7-5} = 0b000;
18395let Inst{13-12} = 0b00;
18396let Inst{31-21} = 0b10000000100;
18397}
18398def S2_asr_i_vw : HInst<
18399(outs DoubleRegs:$Rdd32),
18400(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18401"$Rdd32 = vasrw($Rss32,#$Ii)",
18402tc_946df596, TypeS_2op>, Enc_7e5a82 {
18403let Inst{7-5} = 0b000;
18404let Inst{13-13} = 0b0;
18405let Inst{31-21} = 0b10000000010;
18406}
18407def S2_asr_r_p : HInst<
18408(outs DoubleRegs:$Rdd32),
18409(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18410"$Rdd32 = asr($Rss32,$Rt32)",
18411tc_946df596, TypeS_3op>, Enc_927852 {
18412let Inst{7-5} = 0b000;
18413let Inst{13-13} = 0b0;
18414let Inst{31-21} = 0b11000011100;
18415}
18416def S2_asr_r_p_acc : HInst<
18417(outs DoubleRegs:$Rxx32),
18418(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18419"$Rxx32 += asr($Rss32,$Rt32)",
18420tc_f675fee8, TypeS_3op>, Enc_1aa186 {
18421let Inst{7-5} = 0b000;
18422let Inst{13-13} = 0b0;
18423let Inst{31-21} = 0b11001011110;
18424let prefersSlot3 = 1;
18425let Constraints = "$Rxx32 = $Rxx32in";
18426}
18427def S2_asr_r_p_and : HInst<
18428(outs DoubleRegs:$Rxx32),
18429(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18430"$Rxx32 &= asr($Rss32,$Rt32)",
18431tc_f429765c, TypeS_3op>, Enc_1aa186 {
18432let Inst{7-5} = 0b000;
18433let Inst{13-13} = 0b0;
18434let Inst{31-21} = 0b11001011010;
18435let prefersSlot3 = 1;
18436let Constraints = "$Rxx32 = $Rxx32in";
18437}
18438def S2_asr_r_p_nac : HInst<
18439(outs DoubleRegs:$Rxx32),
18440(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18441"$Rxx32 -= asr($Rss32,$Rt32)",
18442tc_f675fee8, TypeS_3op>, Enc_1aa186 {
18443let Inst{7-5} = 0b000;
18444let Inst{13-13} = 0b0;
18445let Inst{31-21} = 0b11001011100;
18446let prefersSlot3 = 1;
18447let Constraints = "$Rxx32 = $Rxx32in";
18448}
18449def S2_asr_r_p_or : HInst<
18450(outs DoubleRegs:$Rxx32),
18451(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18452"$Rxx32 |= asr($Rss32,$Rt32)",
18453tc_f429765c, TypeS_3op>, Enc_1aa186 {
18454let Inst{7-5} = 0b000;
18455let Inst{13-13} = 0b0;
18456let Inst{31-21} = 0b11001011000;
18457let prefersSlot3 = 1;
18458let Constraints = "$Rxx32 = $Rxx32in";
18459}
18460def S2_asr_r_p_xor : HInst<
18461(outs DoubleRegs:$Rxx32),
18462(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18463"$Rxx32 ^= asr($Rss32,$Rt32)",
18464tc_f429765c, TypeS_3op>, Enc_1aa186 {
18465let Inst{7-5} = 0b000;
18466let Inst{13-13} = 0b0;
18467let Inst{31-21} = 0b11001011011;
18468let prefersSlot3 = 1;
18469let Constraints = "$Rxx32 = $Rxx32in";
18470}
18471def S2_asr_r_r : HInst<
18472(outs IntRegs:$Rd32),
18473(ins IntRegs:$Rs32, IntRegs:$Rt32),
18474"$Rd32 = asr($Rs32,$Rt32)",
18475tc_946df596, TypeS_3op>, Enc_5ab2be {
18476let Inst{7-5} = 0b000;
18477let Inst{13-13} = 0b0;
18478let Inst{31-21} = 0b11000110010;
18479let hasNewValue = 1;
18480let opNewValue = 0;
18481}
18482def S2_asr_r_r_acc : HInst<
18483(outs IntRegs:$Rx32),
18484(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18485"$Rx32 += asr($Rs32,$Rt32)",
18486tc_f675fee8, TypeS_3op>, Enc_2ae154 {
18487let Inst{7-5} = 0b000;
18488let Inst{13-13} = 0b0;
18489let Inst{31-21} = 0b11001100110;
18490let hasNewValue = 1;
18491let opNewValue = 0;
18492let prefersSlot3 = 1;
18493let Constraints = "$Rx32 = $Rx32in";
18494}
18495def S2_asr_r_r_and : HInst<
18496(outs IntRegs:$Rx32),
18497(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18498"$Rx32 &= asr($Rs32,$Rt32)",
18499tc_f429765c, TypeS_3op>, Enc_2ae154 {
18500let Inst{7-5} = 0b000;
18501let Inst{13-13} = 0b0;
18502let Inst{31-21} = 0b11001100010;
18503let hasNewValue = 1;
18504let opNewValue = 0;
18505let prefersSlot3 = 1;
18506let Constraints = "$Rx32 = $Rx32in";
18507}
18508def S2_asr_r_r_nac : HInst<
18509(outs IntRegs:$Rx32),
18510(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18511"$Rx32 -= asr($Rs32,$Rt32)",
18512tc_f675fee8, TypeS_3op>, Enc_2ae154 {
18513let Inst{7-5} = 0b000;
18514let Inst{13-13} = 0b0;
18515let Inst{31-21} = 0b11001100100;
18516let hasNewValue = 1;
18517let opNewValue = 0;
18518let prefersSlot3 = 1;
18519let Constraints = "$Rx32 = $Rx32in";
18520}
18521def S2_asr_r_r_or : HInst<
18522(outs IntRegs:$Rx32),
18523(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18524"$Rx32 |= asr($Rs32,$Rt32)",
18525tc_f429765c, TypeS_3op>, Enc_2ae154 {
18526let Inst{7-5} = 0b000;
18527let Inst{13-13} = 0b0;
18528let Inst{31-21} = 0b11001100000;
18529let hasNewValue = 1;
18530let opNewValue = 0;
18531let prefersSlot3 = 1;
18532let Constraints = "$Rx32 = $Rx32in";
18533}
18534def S2_asr_r_r_sat : HInst<
18535(outs IntRegs:$Rd32),
18536(ins IntRegs:$Rs32, IntRegs:$Rt32),
18537"$Rd32 = asr($Rs32,$Rt32):sat",
18538tc_779080bf, TypeS_3op>, Enc_5ab2be {
18539let Inst{7-5} = 0b000;
18540let Inst{13-13} = 0b0;
18541let Inst{31-21} = 0b11000110000;
18542let hasNewValue = 1;
18543let opNewValue = 0;
18544let prefersSlot3 = 1;
18545let Defs = [USR_OVF];
18546}
18547def S2_asr_r_svw_trun : HInst<
18548(outs IntRegs:$Rd32),
18549(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18550"$Rd32 = vasrw($Rss32,$Rt32)",
18551tc_4414d8b1, TypeS_3op>, Enc_3d5b28 {
18552let Inst{7-5} = 0b010;
18553let Inst{13-13} = 0b0;
18554let Inst{31-21} = 0b11000101000;
18555let hasNewValue = 1;
18556let opNewValue = 0;
18557let prefersSlot3 = 1;
18558}
18559def S2_asr_r_vh : HInst<
18560(outs DoubleRegs:$Rdd32),
18561(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18562"$Rdd32 = vasrh($Rss32,$Rt32)",
18563tc_946df596, TypeS_3op>, Enc_927852 {
18564let Inst{7-5} = 0b000;
18565let Inst{13-13} = 0b0;
18566let Inst{31-21} = 0b11000011010;
18567}
18568def S2_asr_r_vw : HInst<
18569(outs DoubleRegs:$Rdd32),
18570(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18571"$Rdd32 = vasrw($Rss32,$Rt32)",
18572tc_946df596, TypeS_3op>, Enc_927852 {
18573let Inst{7-5} = 0b000;
18574let Inst{13-13} = 0b0;
18575let Inst{31-21} = 0b11000011000;
18576}
18577def S2_brev : HInst<
18578(outs IntRegs:$Rd32),
18579(ins IntRegs:$Rs32),
18580"$Rd32 = brev($Rs32)",
18581tc_14b5c689, TypeS_2op>, Enc_5e2823 {
18582let Inst{13-5} = 0b000000110;
18583let Inst{31-21} = 0b10001100010;
18584let hasNewValue = 1;
18585let opNewValue = 0;
18586let prefersSlot3 = 1;
18587}
18588def S2_brevp : HInst<
18589(outs DoubleRegs:$Rdd32),
18590(ins DoubleRegs:$Rss32),
18591"$Rdd32 = brev($Rss32)",
18592tc_14b5c689, TypeS_2op>, Enc_b9c5fb {
18593let Inst{13-5} = 0b000000110;
18594let Inst{31-21} = 0b10000000110;
18595let prefersSlot3 = 1;
18596}
18597def S2_cabacdecbin : HInst<
18598(outs DoubleRegs:$Rdd32),
18599(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18600"$Rdd32 = decbin($Rss32,$Rtt32)",
18601tc_76851da1, TypeS_3op>, Enc_a56825 {
18602let Inst{7-5} = 0b110;
18603let Inst{13-13} = 0b0;
18604let Inst{31-21} = 0b11000001110;
18605let isPredicateLate = 1;
18606let prefersSlot3 = 1;
18607let Defs = [P0];
18608}
18609def S2_cl0 : HInst<
18610(outs IntRegs:$Rd32),
18611(ins IntRegs:$Rs32),
18612"$Rd32 = cl0($Rs32)",
18613tc_14b5c689, TypeS_2op>, Enc_5e2823 {
18614let Inst{13-5} = 0b000000101;
18615let Inst{31-21} = 0b10001100000;
18616let hasNewValue = 1;
18617let opNewValue = 0;
18618let prefersSlot3 = 1;
18619}
18620def S2_cl0p : HInst<
18621(outs IntRegs:$Rd32),
18622(ins DoubleRegs:$Rss32),
18623"$Rd32 = cl0($Rss32)",
18624tc_14b5c689, TypeS_2op>, Enc_90cd8b {
18625let Inst{13-5} = 0b000000010;
18626let Inst{31-21} = 0b10001000010;
18627let hasNewValue = 1;
18628let opNewValue = 0;
18629let prefersSlot3 = 1;
18630}
18631def S2_cl1 : HInst<
18632(outs IntRegs:$Rd32),
18633(ins IntRegs:$Rs32),
18634"$Rd32 = cl1($Rs32)",
18635tc_14b5c689, TypeS_2op>, Enc_5e2823 {
18636let Inst{13-5} = 0b000000110;
18637let Inst{31-21} = 0b10001100000;
18638let hasNewValue = 1;
18639let opNewValue = 0;
18640let prefersSlot3 = 1;
18641}
18642def S2_cl1p : HInst<
18643(outs IntRegs:$Rd32),
18644(ins DoubleRegs:$Rss32),
18645"$Rd32 = cl1($Rss32)",
18646tc_14b5c689, TypeS_2op>, Enc_90cd8b {
18647let Inst{13-5} = 0b000000100;
18648let Inst{31-21} = 0b10001000010;
18649let hasNewValue = 1;
18650let opNewValue = 0;
18651let prefersSlot3 = 1;
18652}
18653def S2_clb : HInst<
18654(outs IntRegs:$Rd32),
18655(ins IntRegs:$Rs32),
18656"$Rd32 = clb($Rs32)",
18657tc_14b5c689, TypeS_2op>, Enc_5e2823 {
18658let Inst{13-5} = 0b000000100;
18659let Inst{31-21} = 0b10001100000;
18660let hasNewValue = 1;
18661let opNewValue = 0;
18662let prefersSlot3 = 1;
18663}
18664def S2_clbnorm : HInst<
18665(outs IntRegs:$Rd32),
18666(ins IntRegs:$Rs32),
18667"$Rd32 = normamt($Rs32)",
18668tc_14b5c689, TypeS_2op>, Enc_5e2823 {
18669let Inst{13-5} = 0b000000111;
18670let Inst{31-21} = 0b10001100000;
18671let hasNewValue = 1;
18672let opNewValue = 0;
18673let prefersSlot3 = 1;
18674}
18675def S2_clbp : HInst<
18676(outs IntRegs:$Rd32),
18677(ins DoubleRegs:$Rss32),
18678"$Rd32 = clb($Rss32)",
18679tc_14b5c689, TypeS_2op>, Enc_90cd8b {
18680let Inst{13-5} = 0b000000000;
18681let Inst{31-21} = 0b10001000010;
18682let hasNewValue = 1;
18683let opNewValue = 0;
18684let prefersSlot3 = 1;
18685}
18686def S2_clrbit_i : HInst<
18687(outs IntRegs:$Rd32),
18688(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18689"$Rd32 = clrbit($Rs32,#$Ii)",
18690tc_946df596, TypeS_2op>, Enc_a05677 {
18691let Inst{7-5} = 0b001;
18692let Inst{13-13} = 0b0;
18693let Inst{31-21} = 0b10001100110;
18694let hasNewValue = 1;
18695let opNewValue = 0;
18696}
18697def S2_clrbit_r : HInst<
18698(outs IntRegs:$Rd32),
18699(ins IntRegs:$Rs32, IntRegs:$Rt32),
18700"$Rd32 = clrbit($Rs32,$Rt32)",
18701tc_946df596, TypeS_3op>, Enc_5ab2be {
18702let Inst{7-5} = 0b010;
18703let Inst{13-13} = 0b0;
18704let Inst{31-21} = 0b11000110100;
18705let hasNewValue = 1;
18706let opNewValue = 0;
18707}
18708def S2_ct0 : HInst<
18709(outs IntRegs:$Rd32),
18710(ins IntRegs:$Rs32),
18711"$Rd32 = ct0($Rs32)",
18712tc_14b5c689, TypeS_2op>, Enc_5e2823 {
18713let Inst{13-5} = 0b000000100;
18714let Inst{31-21} = 0b10001100010;
18715let hasNewValue = 1;
18716let opNewValue = 0;
18717let prefersSlot3 = 1;
18718}
18719def S2_ct0p : HInst<
18720(outs IntRegs:$Rd32),
18721(ins DoubleRegs:$Rss32),
18722"$Rd32 = ct0($Rss32)",
18723tc_14b5c689, TypeS_2op>, Enc_90cd8b {
18724let Inst{13-5} = 0b000000010;
18725let Inst{31-21} = 0b10001000111;
18726let hasNewValue = 1;
18727let opNewValue = 0;
18728let prefersSlot3 = 1;
18729}
18730def S2_ct1 : HInst<
18731(outs IntRegs:$Rd32),
18732(ins IntRegs:$Rs32),
18733"$Rd32 = ct1($Rs32)",
18734tc_14b5c689, TypeS_2op>, Enc_5e2823 {
18735let Inst{13-5} = 0b000000101;
18736let Inst{31-21} = 0b10001100010;
18737let hasNewValue = 1;
18738let opNewValue = 0;
18739let prefersSlot3 = 1;
18740}
18741def S2_ct1p : HInst<
18742(outs IntRegs:$Rd32),
18743(ins DoubleRegs:$Rss32),
18744"$Rd32 = ct1($Rss32)",
18745tc_14b5c689, TypeS_2op>, Enc_90cd8b {
18746let Inst{13-5} = 0b000000100;
18747let Inst{31-21} = 0b10001000111;
18748let hasNewValue = 1;
18749let opNewValue = 0;
18750let prefersSlot3 = 1;
18751}
18752def S2_deinterleave : HInst<
18753(outs DoubleRegs:$Rdd32),
18754(ins DoubleRegs:$Rss32),
18755"$Rdd32 = deinterleave($Rss32)",
18756tc_14b5c689, TypeS_2op>, Enc_b9c5fb {
18757let Inst{13-5} = 0b000000100;
18758let Inst{31-21} = 0b10000000110;
18759let prefersSlot3 = 1;
18760}
18761def S2_extractu : HInst<
18762(outs IntRegs:$Rd32),
18763(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
18764"$Rd32 = extractu($Rs32,#$Ii,#$II)",
18765tc_f675fee8, TypeS_2op>, Enc_b388cf {
18766let Inst{13-13} = 0b0;
18767let Inst{31-23} = 0b100011010;
18768let hasNewValue = 1;
18769let opNewValue = 0;
18770let prefersSlot3 = 1;
18771}
18772def S2_extractu_rp : HInst<
18773(outs IntRegs:$Rd32),
18774(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
18775"$Rd32 = extractu($Rs32,$Rtt32)",
18776tc_002cb246, TypeS_3op>, Enc_e07374 {
18777let Inst{7-5} = 0b000;
18778let Inst{13-13} = 0b0;
18779let Inst{31-21} = 0b11001001000;
18780let hasNewValue = 1;
18781let opNewValue = 0;
18782let prefersSlot3 = 1;
18783}
18784def S2_extractup : HInst<
18785(outs DoubleRegs:$Rdd32),
18786(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
18787"$Rdd32 = extractu($Rss32,#$Ii,#$II)",
18788tc_f675fee8, TypeS_2op>, Enc_b84c4c {
18789let Inst{31-24} = 0b10000001;
18790let prefersSlot3 = 1;
18791}
18792def S2_extractup_rp : HInst<
18793(outs DoubleRegs:$Rdd32),
18794(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18795"$Rdd32 = extractu($Rss32,$Rtt32)",
18796tc_002cb246, TypeS_3op>, Enc_a56825 {
18797let Inst{7-5} = 0b000;
18798let Inst{13-13} = 0b0;
18799let Inst{31-21} = 0b11000001000;
18800let prefersSlot3 = 1;
18801}
18802def S2_insert : HInst<
18803(outs IntRegs:$Rx32),
18804(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
18805"$Rx32 = insert($Rs32,#$Ii,#$II)",
18806tc_bfec0f01, TypeS_2op>, Enc_a1e29d {
18807let Inst{13-13} = 0b0;
18808let Inst{31-23} = 0b100011110;
18809let hasNewValue = 1;
18810let opNewValue = 0;
18811let prefersSlot3 = 1;
18812let Constraints = "$Rx32 = $Rx32in";
18813}
18814def S2_insert_rp : HInst<
18815(outs IntRegs:$Rx32),
18816(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
18817"$Rx32 = insert($Rs32,$Rtt32)",
18818tc_f429765c, TypeS_3op>, Enc_179b35 {
18819let Inst{7-5} = 0b000;
18820let Inst{13-13} = 0b0;
18821let Inst{31-21} = 0b11001000000;
18822let hasNewValue = 1;
18823let opNewValue = 0;
18824let prefersSlot3 = 1;
18825let Constraints = "$Rx32 = $Rx32in";
18826}
18827def S2_insertp : HInst<
18828(outs DoubleRegs:$Rxx32),
18829(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
18830"$Rxx32 = insert($Rss32,#$Ii,#$II)",
18831tc_bfec0f01, TypeS_2op>, Enc_143a3c {
18832let Inst{31-24} = 0b10000011;
18833let prefersSlot3 = 1;
18834let Constraints = "$Rxx32 = $Rxx32in";
18835}
18836def S2_insertp_rp : HInst<
18837(outs DoubleRegs:$Rxx32),
18838(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18839"$Rxx32 = insert($Rss32,$Rtt32)",
18840tc_f429765c, TypeS_3op>, Enc_88c16c {
18841let Inst{7-5} = 0b000;
18842let Inst{13-13} = 0b0;
18843let Inst{31-21} = 0b11001010000;
18844let prefersSlot3 = 1;
18845let Constraints = "$Rxx32 = $Rxx32in";
18846}
18847def S2_interleave : HInst<
18848(outs DoubleRegs:$Rdd32),
18849(ins DoubleRegs:$Rss32),
18850"$Rdd32 = interleave($Rss32)",
18851tc_14b5c689, TypeS_2op>, Enc_b9c5fb {
18852let Inst{13-5} = 0b000000101;
18853let Inst{31-21} = 0b10000000110;
18854let prefersSlot3 = 1;
18855}
18856def S2_lfsp : HInst<
18857(outs DoubleRegs:$Rdd32),
18858(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18859"$Rdd32 = lfs($Rss32,$Rtt32)",
18860tc_002cb246, TypeS_3op>, Enc_a56825 {
18861let Inst{7-5} = 0b110;
18862let Inst{13-13} = 0b0;
18863let Inst{31-21} = 0b11000001100;
18864let prefersSlot3 = 1;
18865}
18866def S2_lsl_r_p : HInst<
18867(outs DoubleRegs:$Rdd32),
18868(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18869"$Rdd32 = lsl($Rss32,$Rt32)",
18870tc_946df596, TypeS_3op>, Enc_927852 {
18871let Inst{7-5} = 0b110;
18872let Inst{13-13} = 0b0;
18873let Inst{31-21} = 0b11000011100;
18874}
18875def S2_lsl_r_p_acc : HInst<
18876(outs DoubleRegs:$Rxx32),
18877(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18878"$Rxx32 += lsl($Rss32,$Rt32)",
18879tc_f675fee8, TypeS_3op>, Enc_1aa186 {
18880let Inst{7-5} = 0b110;
18881let Inst{13-13} = 0b0;
18882let Inst{31-21} = 0b11001011110;
18883let prefersSlot3 = 1;
18884let Constraints = "$Rxx32 = $Rxx32in";
18885}
18886def S2_lsl_r_p_and : HInst<
18887(outs DoubleRegs:$Rxx32),
18888(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18889"$Rxx32 &= lsl($Rss32,$Rt32)",
18890tc_f429765c, TypeS_3op>, Enc_1aa186 {
18891let Inst{7-5} = 0b110;
18892let Inst{13-13} = 0b0;
18893let Inst{31-21} = 0b11001011010;
18894let prefersSlot3 = 1;
18895let Constraints = "$Rxx32 = $Rxx32in";
18896}
18897def S2_lsl_r_p_nac : HInst<
18898(outs DoubleRegs:$Rxx32),
18899(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18900"$Rxx32 -= lsl($Rss32,$Rt32)",
18901tc_f675fee8, TypeS_3op>, Enc_1aa186 {
18902let Inst{7-5} = 0b110;
18903let Inst{13-13} = 0b0;
18904let Inst{31-21} = 0b11001011100;
18905let prefersSlot3 = 1;
18906let Constraints = "$Rxx32 = $Rxx32in";
18907}
18908def S2_lsl_r_p_or : HInst<
18909(outs DoubleRegs:$Rxx32),
18910(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18911"$Rxx32 |= lsl($Rss32,$Rt32)",
18912tc_f429765c, TypeS_3op>, Enc_1aa186 {
18913let Inst{7-5} = 0b110;
18914let Inst{13-13} = 0b0;
18915let Inst{31-21} = 0b11001011000;
18916let prefersSlot3 = 1;
18917let Constraints = "$Rxx32 = $Rxx32in";
18918}
18919def S2_lsl_r_p_xor : HInst<
18920(outs DoubleRegs:$Rxx32),
18921(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18922"$Rxx32 ^= lsl($Rss32,$Rt32)",
18923tc_f429765c, TypeS_3op>, Enc_1aa186 {
18924let Inst{7-5} = 0b110;
18925let Inst{13-13} = 0b0;
18926let Inst{31-21} = 0b11001011011;
18927let prefersSlot3 = 1;
18928let Constraints = "$Rxx32 = $Rxx32in";
18929}
18930def S2_lsl_r_r : HInst<
18931(outs IntRegs:$Rd32),
18932(ins IntRegs:$Rs32, IntRegs:$Rt32),
18933"$Rd32 = lsl($Rs32,$Rt32)",
18934tc_946df596, TypeS_3op>, Enc_5ab2be {
18935let Inst{7-5} = 0b110;
18936let Inst{13-13} = 0b0;
18937let Inst{31-21} = 0b11000110010;
18938let hasNewValue = 1;
18939let opNewValue = 0;
18940}
18941def S2_lsl_r_r_acc : HInst<
18942(outs IntRegs:$Rx32),
18943(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18944"$Rx32 += lsl($Rs32,$Rt32)",
18945tc_f675fee8, TypeS_3op>, Enc_2ae154 {
18946let Inst{7-5} = 0b110;
18947let Inst{13-13} = 0b0;
18948let Inst{31-21} = 0b11001100110;
18949let hasNewValue = 1;
18950let opNewValue = 0;
18951let prefersSlot3 = 1;
18952let Constraints = "$Rx32 = $Rx32in";
18953}
18954def S2_lsl_r_r_and : HInst<
18955(outs IntRegs:$Rx32),
18956(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18957"$Rx32 &= lsl($Rs32,$Rt32)",
18958tc_f429765c, TypeS_3op>, Enc_2ae154 {
18959let Inst{7-5} = 0b110;
18960let Inst{13-13} = 0b0;
18961let Inst{31-21} = 0b11001100010;
18962let hasNewValue = 1;
18963let opNewValue = 0;
18964let prefersSlot3 = 1;
18965let Constraints = "$Rx32 = $Rx32in";
18966}
18967def S2_lsl_r_r_nac : HInst<
18968(outs IntRegs:$Rx32),
18969(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18970"$Rx32 -= lsl($Rs32,$Rt32)",
18971tc_f675fee8, TypeS_3op>, Enc_2ae154 {
18972let Inst{7-5} = 0b110;
18973let Inst{13-13} = 0b0;
18974let Inst{31-21} = 0b11001100100;
18975let hasNewValue = 1;
18976let opNewValue = 0;
18977let prefersSlot3 = 1;
18978let Constraints = "$Rx32 = $Rx32in";
18979}
18980def S2_lsl_r_r_or : HInst<
18981(outs IntRegs:$Rx32),
18982(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18983"$Rx32 |= lsl($Rs32,$Rt32)",
18984tc_f429765c, TypeS_3op>, Enc_2ae154 {
18985let Inst{7-5} = 0b110;
18986let Inst{13-13} = 0b0;
18987let Inst{31-21} = 0b11001100000;
18988let hasNewValue = 1;
18989let opNewValue = 0;
18990let prefersSlot3 = 1;
18991let Constraints = "$Rx32 = $Rx32in";
18992}
18993def S2_lsl_r_vh : HInst<
18994(outs DoubleRegs:$Rdd32),
18995(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18996"$Rdd32 = vlslh($Rss32,$Rt32)",
18997tc_946df596, TypeS_3op>, Enc_927852 {
18998let Inst{7-5} = 0b110;
18999let Inst{13-13} = 0b0;
19000let Inst{31-21} = 0b11000011010;
19001}
19002def S2_lsl_r_vw : HInst<
19003(outs DoubleRegs:$Rdd32),
19004(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19005"$Rdd32 = vlslw($Rss32,$Rt32)",
19006tc_946df596, TypeS_3op>, Enc_927852 {
19007let Inst{7-5} = 0b110;
19008let Inst{13-13} = 0b0;
19009let Inst{31-21} = 0b11000011000;
19010}
19011def S2_lsr_i_p : HInst<
19012(outs DoubleRegs:$Rdd32),
19013(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
19014"$Rdd32 = lsr($Rss32,#$Ii)",
19015tc_946df596, TypeS_2op>, Enc_5eac98 {
19016let Inst{7-5} = 0b001;
19017let Inst{31-21} = 0b10000000000;
19018}
19019def S2_lsr_i_p_acc : HInst<
19020(outs DoubleRegs:$Rxx32),
19021(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19022"$Rxx32 += lsr($Rss32,#$Ii)",
19023tc_f675fee8, TypeS_2op>, Enc_70fb07 {
19024let Inst{7-5} = 0b101;
19025let Inst{31-21} = 0b10000010000;
19026let prefersSlot3 = 1;
19027let Constraints = "$Rxx32 = $Rxx32in";
19028}
19029def S2_lsr_i_p_and : HInst<
19030(outs DoubleRegs:$Rxx32),
19031(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19032"$Rxx32 &= lsr($Rss32,#$Ii)",
19033tc_f429765c, TypeS_2op>, Enc_70fb07 {
19034let Inst{7-5} = 0b001;
19035let Inst{31-21} = 0b10000010010;
19036let prefersSlot3 = 1;
19037let Constraints = "$Rxx32 = $Rxx32in";
19038}
19039def S2_lsr_i_p_nac : HInst<
19040(outs DoubleRegs:$Rxx32),
19041(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19042"$Rxx32 -= lsr($Rss32,#$Ii)",
19043tc_f675fee8, TypeS_2op>, Enc_70fb07 {
19044let Inst{7-5} = 0b001;
19045let Inst{31-21} = 0b10000010000;
19046let prefersSlot3 = 1;
19047let Constraints = "$Rxx32 = $Rxx32in";
19048}
19049def S2_lsr_i_p_or : HInst<
19050(outs DoubleRegs:$Rxx32),
19051(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19052"$Rxx32 |= lsr($Rss32,#$Ii)",
19053tc_f429765c, TypeS_2op>, Enc_70fb07 {
19054let Inst{7-5} = 0b101;
19055let Inst{31-21} = 0b10000010010;
19056let prefersSlot3 = 1;
19057let Constraints = "$Rxx32 = $Rxx32in";
19058}
19059def S2_lsr_i_p_xacc : HInst<
19060(outs DoubleRegs:$Rxx32),
19061(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19062"$Rxx32 ^= lsr($Rss32,#$Ii)",
19063tc_f429765c, TypeS_2op>, Enc_70fb07 {
19064let Inst{7-5} = 0b001;
19065let Inst{31-21} = 0b10000010100;
19066let prefersSlot3 = 1;
19067let Constraints = "$Rxx32 = $Rxx32in";
19068}
19069def S2_lsr_i_r : HInst<
19070(outs IntRegs:$Rd32),
19071(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19072"$Rd32 = lsr($Rs32,#$Ii)",
19073tc_946df596, TypeS_2op>, Enc_a05677 {
19074let Inst{7-5} = 0b001;
19075let Inst{13-13} = 0b0;
19076let Inst{31-21} = 0b10001100000;
19077let hasNewValue = 1;
19078let opNewValue = 0;
19079}
19080def S2_lsr_i_r_acc : HInst<
19081(outs IntRegs:$Rx32),
19082(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19083"$Rx32 += lsr($Rs32,#$Ii)",
19084tc_f675fee8, TypeS_2op>, Enc_28a2dc {
19085let Inst{7-5} = 0b101;
19086let Inst{13-13} = 0b0;
19087let Inst{31-21} = 0b10001110000;
19088let hasNewValue = 1;
19089let opNewValue = 0;
19090let prefersSlot3 = 1;
19091let Constraints = "$Rx32 = $Rx32in";
19092}
19093def S2_lsr_i_r_and : HInst<
19094(outs IntRegs:$Rx32),
19095(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19096"$Rx32 &= lsr($Rs32,#$Ii)",
19097tc_f429765c, TypeS_2op>, Enc_28a2dc {
19098let Inst{7-5} = 0b001;
19099let Inst{13-13} = 0b0;
19100let Inst{31-21} = 0b10001110010;
19101let hasNewValue = 1;
19102let opNewValue = 0;
19103let prefersSlot3 = 1;
19104let Constraints = "$Rx32 = $Rx32in";
19105}
19106def S2_lsr_i_r_nac : HInst<
19107(outs IntRegs:$Rx32),
19108(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19109"$Rx32 -= lsr($Rs32,#$Ii)",
19110tc_f675fee8, TypeS_2op>, Enc_28a2dc {
19111let Inst{7-5} = 0b001;
19112let Inst{13-13} = 0b0;
19113let Inst{31-21} = 0b10001110000;
19114let hasNewValue = 1;
19115let opNewValue = 0;
19116let prefersSlot3 = 1;
19117let Constraints = "$Rx32 = $Rx32in";
19118}
19119def S2_lsr_i_r_or : HInst<
19120(outs IntRegs:$Rx32),
19121(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19122"$Rx32 |= lsr($Rs32,#$Ii)",
19123tc_f429765c, TypeS_2op>, Enc_28a2dc {
19124let Inst{7-5} = 0b101;
19125let Inst{13-13} = 0b0;
19126let Inst{31-21} = 0b10001110010;
19127let hasNewValue = 1;
19128let opNewValue = 0;
19129let prefersSlot3 = 1;
19130let Constraints = "$Rx32 = $Rx32in";
19131}
19132def S2_lsr_i_r_xacc : HInst<
19133(outs IntRegs:$Rx32),
19134(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19135"$Rx32 ^= lsr($Rs32,#$Ii)",
19136tc_f429765c, TypeS_2op>, Enc_28a2dc {
19137let Inst{7-5} = 0b001;
19138let Inst{13-13} = 0b0;
19139let Inst{31-21} = 0b10001110100;
19140let hasNewValue = 1;
19141let opNewValue = 0;
19142let prefersSlot3 = 1;
19143let Constraints = "$Rx32 = $Rx32in";
19144}
19145def S2_lsr_i_vh : HInst<
19146(outs DoubleRegs:$Rdd32),
19147(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
19148"$Rdd32 = vlsrh($Rss32,#$Ii)",
19149tc_946df596, TypeS_2op>, Enc_12b6e9 {
19150let Inst{7-5} = 0b001;
19151let Inst{13-12} = 0b00;
19152let Inst{31-21} = 0b10000000100;
19153}
19154def S2_lsr_i_vw : HInst<
19155(outs DoubleRegs:$Rdd32),
19156(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
19157"$Rdd32 = vlsrw($Rss32,#$Ii)",
19158tc_946df596, TypeS_2op>, Enc_7e5a82 {
19159let Inst{7-5} = 0b001;
19160let Inst{13-13} = 0b0;
19161let Inst{31-21} = 0b10000000010;
19162}
19163def S2_lsr_r_p : HInst<
19164(outs DoubleRegs:$Rdd32),
19165(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19166"$Rdd32 = lsr($Rss32,$Rt32)",
19167tc_946df596, TypeS_3op>, Enc_927852 {
19168let Inst{7-5} = 0b010;
19169let Inst{13-13} = 0b0;
19170let Inst{31-21} = 0b11000011100;
19171}
19172def S2_lsr_r_p_acc : HInst<
19173(outs DoubleRegs:$Rxx32),
19174(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19175"$Rxx32 += lsr($Rss32,$Rt32)",
19176tc_f675fee8, TypeS_3op>, Enc_1aa186 {
19177let Inst{7-5} = 0b010;
19178let Inst{13-13} = 0b0;
19179let Inst{31-21} = 0b11001011110;
19180let prefersSlot3 = 1;
19181let Constraints = "$Rxx32 = $Rxx32in";
19182}
19183def S2_lsr_r_p_and : HInst<
19184(outs DoubleRegs:$Rxx32),
19185(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19186"$Rxx32 &= lsr($Rss32,$Rt32)",
19187tc_f429765c, TypeS_3op>, Enc_1aa186 {
19188let Inst{7-5} = 0b010;
19189let Inst{13-13} = 0b0;
19190let Inst{31-21} = 0b11001011010;
19191let prefersSlot3 = 1;
19192let Constraints = "$Rxx32 = $Rxx32in";
19193}
19194def S2_lsr_r_p_nac : HInst<
19195(outs DoubleRegs:$Rxx32),
19196(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19197"$Rxx32 -= lsr($Rss32,$Rt32)",
19198tc_f675fee8, TypeS_3op>, Enc_1aa186 {
19199let Inst{7-5} = 0b010;
19200let Inst{13-13} = 0b0;
19201let Inst{31-21} = 0b11001011100;
19202let prefersSlot3 = 1;
19203let Constraints = "$Rxx32 = $Rxx32in";
19204}
19205def S2_lsr_r_p_or : HInst<
19206(outs DoubleRegs:$Rxx32),
19207(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19208"$Rxx32 |= lsr($Rss32,$Rt32)",
19209tc_f429765c, TypeS_3op>, Enc_1aa186 {
19210let Inst{7-5} = 0b010;
19211let Inst{13-13} = 0b0;
19212let Inst{31-21} = 0b11001011000;
19213let prefersSlot3 = 1;
19214let Constraints = "$Rxx32 = $Rxx32in";
19215}
19216def S2_lsr_r_p_xor : HInst<
19217(outs DoubleRegs:$Rxx32),
19218(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19219"$Rxx32 ^= lsr($Rss32,$Rt32)",
19220tc_f429765c, TypeS_3op>, Enc_1aa186 {
19221let Inst{7-5} = 0b010;
19222let Inst{13-13} = 0b0;
19223let Inst{31-21} = 0b11001011011;
19224let prefersSlot3 = 1;
19225let Constraints = "$Rxx32 = $Rxx32in";
19226}
19227def S2_lsr_r_r : HInst<
19228(outs IntRegs:$Rd32),
19229(ins IntRegs:$Rs32, IntRegs:$Rt32),
19230"$Rd32 = lsr($Rs32,$Rt32)",
19231tc_946df596, TypeS_3op>, Enc_5ab2be {
19232let Inst{7-5} = 0b010;
19233let Inst{13-13} = 0b0;
19234let Inst{31-21} = 0b11000110010;
19235let hasNewValue = 1;
19236let opNewValue = 0;
19237}
19238def S2_lsr_r_r_acc : HInst<
19239(outs IntRegs:$Rx32),
19240(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19241"$Rx32 += lsr($Rs32,$Rt32)",
19242tc_f675fee8, TypeS_3op>, Enc_2ae154 {
19243let Inst{7-5} = 0b010;
19244let Inst{13-13} = 0b0;
19245let Inst{31-21} = 0b11001100110;
19246let hasNewValue = 1;
19247let opNewValue = 0;
19248let prefersSlot3 = 1;
19249let Constraints = "$Rx32 = $Rx32in";
19250}
19251def S2_lsr_r_r_and : HInst<
19252(outs IntRegs:$Rx32),
19253(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19254"$Rx32 &= lsr($Rs32,$Rt32)",
19255tc_f429765c, TypeS_3op>, Enc_2ae154 {
19256let Inst{7-5} = 0b010;
19257let Inst{13-13} = 0b0;
19258let Inst{31-21} = 0b11001100010;
19259let hasNewValue = 1;
19260let opNewValue = 0;
19261let prefersSlot3 = 1;
19262let Constraints = "$Rx32 = $Rx32in";
19263}
19264def S2_lsr_r_r_nac : HInst<
19265(outs IntRegs:$Rx32),
19266(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19267"$Rx32 -= lsr($Rs32,$Rt32)",
19268tc_f675fee8, TypeS_3op>, Enc_2ae154 {
19269let Inst{7-5} = 0b010;
19270let Inst{13-13} = 0b0;
19271let Inst{31-21} = 0b11001100100;
19272let hasNewValue = 1;
19273let opNewValue = 0;
19274let prefersSlot3 = 1;
19275let Constraints = "$Rx32 = $Rx32in";
19276}
19277def S2_lsr_r_r_or : HInst<
19278(outs IntRegs:$Rx32),
19279(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19280"$Rx32 |= lsr($Rs32,$Rt32)",
19281tc_f429765c, TypeS_3op>, Enc_2ae154 {
19282let Inst{7-5} = 0b010;
19283let Inst{13-13} = 0b0;
19284let Inst{31-21} = 0b11001100000;
19285let hasNewValue = 1;
19286let opNewValue = 0;
19287let prefersSlot3 = 1;
19288let Constraints = "$Rx32 = $Rx32in";
19289}
19290def S2_lsr_r_vh : HInst<
19291(outs DoubleRegs:$Rdd32),
19292(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19293"$Rdd32 = vlsrh($Rss32,$Rt32)",
19294tc_946df596, TypeS_3op>, Enc_927852 {
19295let Inst{7-5} = 0b010;
19296let Inst{13-13} = 0b0;
19297let Inst{31-21} = 0b11000011010;
19298}
19299def S2_lsr_r_vw : HInst<
19300(outs DoubleRegs:$Rdd32),
19301(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19302"$Rdd32 = vlsrw($Rss32,$Rt32)",
19303tc_946df596, TypeS_3op>, Enc_927852 {
19304let Inst{7-5} = 0b010;
19305let Inst{13-13} = 0b0;
19306let Inst{31-21} = 0b11000011000;
19307}
19308def S2_mask : HInst<
19309(outs IntRegs:$Rd32),
19310(ins u5_0Imm:$Ii, u5_0Imm:$II),
19311"$Rd32 = mask(#$Ii,#$II)",
19312tc_9461ff31, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> {
19313let Inst{13-13} = 0b1;
19314let Inst{20-16} = 0b00000;
19315let Inst{31-23} = 0b100011010;
19316let hasNewValue = 1;
19317let opNewValue = 0;
19318let prefersSlot3 = 1;
19319}
19320def S2_packhl : HInst<
19321(outs DoubleRegs:$Rdd32),
19322(ins IntRegs:$Rs32, IntRegs:$Rt32),
19323"$Rdd32 = packhl($Rs32,$Rt32)",
19324tc_5a2711e5, TypeALU32_3op>, Enc_be32a5 {
19325let Inst{7-5} = 0b000;
19326let Inst{13-13} = 0b0;
19327let Inst{31-21} = 0b11110101100;
19328let InputType = "reg";
19329}
19330def S2_parityp : HInst<
19331(outs IntRegs:$Rd32),
19332(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19333"$Rd32 = parity($Rss32,$Rtt32)",
19334tc_002cb246, TypeALU64>, Enc_d2216a {
19335let Inst{7-5} = 0b000;
19336let Inst{13-13} = 0b0;
19337let Inst{31-21} = 0b11010000000;
19338let hasNewValue = 1;
19339let opNewValue = 0;
19340let prefersSlot3 = 1;
19341}
19342def S2_pstorerbf_io : HInst<
19343(outs),
19344(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19345"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
19346tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19347let Inst{2-2} = 0b0;
19348let Inst{31-21} = 0b01000100000;
19349let isPredicated = 1;
19350let isPredicatedFalse = 1;
19351let addrMode = BaseImmOffset;
19352let accessSize = ByteAccess;
19353let mayStore = 1;
19354let CextOpcode = "S2_storerb";
19355let InputType = "imm";
19356let BaseOpcode = "S2_storerb_io";
19357let isNVStorable = 1;
19358let isExtendable = 1;
19359let opExtendable = 2;
19360let isExtentSigned = 0;
19361let opExtentBits = 6;
19362let opExtentAlign = 0;
19363}
19364def S2_pstorerbf_pi : HInst<
19365(outs IntRegs:$Rx32),
19366(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19367"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
19368tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel {
19369let Inst{2-2} = 0b1;
19370let Inst{7-7} = 0b0;
19371let Inst{13-13} = 0b1;
19372let Inst{31-21} = 0b10101011000;
19373let isPredicated = 1;
19374let isPredicatedFalse = 1;
19375let addrMode = PostInc;
19376let accessSize = ByteAccess;
19377let mayStore = 1;
19378let BaseOpcode = "S2_storerb_pi";
19379let isNVStorable = 1;
19380let Constraints = "$Rx32 = $Rx32in";
19381}
19382def S2_pstorerbf_zomap : HInst<
19383(outs),
19384(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19385"if (!$Pv4) memb($Rs32) = $Rt32",
19386tc_f8e23f0b, TypeMAPPING> {
19387let isPseudo = 1;
19388let isCodeGenOnly = 1;
19389}
19390def S2_pstorerbfnew_pi : HInst<
19391(outs IntRegs:$Rx32),
19392(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19393"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19394tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel {
19395let Inst{2-2} = 0b1;
19396let Inst{7-7} = 0b1;
19397let Inst{13-13} = 0b1;
19398let Inst{31-21} = 0b10101011000;
19399let isPredicated = 1;
19400let isPredicatedFalse = 1;
19401let addrMode = PostInc;
19402let accessSize = ByteAccess;
19403let isPredicatedNew = 1;
19404let mayStore = 1;
19405let BaseOpcode = "S2_storerb_pi";
19406let isNVStorable = 1;
19407let Constraints = "$Rx32 = $Rx32in";
19408}
19409def S2_pstorerbnewf_io : HInst<
19410(outs),
19411(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19412"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19413tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel {
19414let Inst{2-2} = 0b0;
19415let Inst{12-11} = 0b00;
19416let Inst{31-21} = 0b01000100101;
19417let isPredicated = 1;
19418let isPredicatedFalse = 1;
19419let addrMode = BaseImmOffset;
19420let accessSize = ByteAccess;
19421let isNVStore = 1;
19422let isNewValue = 1;
19423let isRestrictNoSlot1Store = 1;
19424let mayStore = 1;
19425let CextOpcode = "S2_storerb";
19426let InputType = "imm";
19427let BaseOpcode = "S2_storerb_io";
19428let isExtendable = 1;
19429let opExtendable = 2;
19430let isExtentSigned = 0;
19431let opExtentBits = 6;
19432let opExtentAlign = 0;
19433let opNewValue = 3;
19434}
19435def S2_pstorerbnewf_pi : HInst<
19436(outs IntRegs:$Rx32),
19437(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19438"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19439tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel {
19440let Inst{2-2} = 0b1;
19441let Inst{7-7} = 0b0;
19442let Inst{13-11} = 0b100;
19443let Inst{31-21} = 0b10101011101;
19444let isPredicated = 1;
19445let isPredicatedFalse = 1;
19446let addrMode = PostInc;
19447let accessSize = ByteAccess;
19448let isNVStore = 1;
19449let isNewValue = 1;
19450let isRestrictNoSlot1Store = 1;
19451let mayStore = 1;
19452let CextOpcode = "S2_storerb";
19453let BaseOpcode = "S2_storerb_pi";
19454let opNewValue = 4;
19455let Constraints = "$Rx32 = $Rx32in";
19456}
19457def S2_pstorerbnewf_zomap : HInst<
19458(outs),
19459(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19460"if (!$Pv4) memb($Rs32) = $Nt8.new",
19461tc_8fb7ab1b, TypeMAPPING> {
19462let isPseudo = 1;
19463let isCodeGenOnly = 1;
19464let opNewValue = 2;
19465}
19466def S2_pstorerbnewfnew_pi : HInst<
19467(outs IntRegs:$Rx32),
19468(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19469"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19470tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel {
19471let Inst{2-2} = 0b1;
19472let Inst{7-7} = 0b1;
19473let Inst{13-11} = 0b100;
19474let Inst{31-21} = 0b10101011101;
19475let isPredicated = 1;
19476let isPredicatedFalse = 1;
19477let addrMode = PostInc;
19478let accessSize = ByteAccess;
19479let isNVStore = 1;
19480let isPredicatedNew = 1;
19481let isNewValue = 1;
19482let isRestrictNoSlot1Store = 1;
19483let mayStore = 1;
19484let CextOpcode = "S2_storerb";
19485let BaseOpcode = "S2_storerb_pi";
19486let opNewValue = 4;
19487let Constraints = "$Rx32 = $Rx32in";
19488}
19489def S2_pstorerbnewt_io : HInst<
19490(outs),
19491(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19492"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19493tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel {
19494let Inst{2-2} = 0b0;
19495let Inst{12-11} = 0b00;
19496let Inst{31-21} = 0b01000000101;
19497let isPredicated = 1;
19498let addrMode = BaseImmOffset;
19499let accessSize = ByteAccess;
19500let isNVStore = 1;
19501let isNewValue = 1;
19502let isRestrictNoSlot1Store = 1;
19503let mayStore = 1;
19504let CextOpcode = "S2_storerb";
19505let InputType = "imm";
19506let BaseOpcode = "S2_storerb_io";
19507let isExtendable = 1;
19508let opExtendable = 2;
19509let isExtentSigned = 0;
19510let opExtentBits = 6;
19511let opExtentAlign = 0;
19512let opNewValue = 3;
19513}
19514def S2_pstorerbnewt_pi : HInst<
19515(outs IntRegs:$Rx32),
19516(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19517"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19518tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel {
19519let Inst{2-2} = 0b0;
19520let Inst{7-7} = 0b0;
19521let Inst{13-11} = 0b100;
19522let Inst{31-21} = 0b10101011101;
19523let isPredicated = 1;
19524let addrMode = PostInc;
19525let accessSize = ByteAccess;
19526let isNVStore = 1;
19527let isNewValue = 1;
19528let isRestrictNoSlot1Store = 1;
19529let mayStore = 1;
19530let CextOpcode = "S2_storerb";
19531let BaseOpcode = "S2_storerb_pi";
19532let opNewValue = 4;
19533let Constraints = "$Rx32 = $Rx32in";
19534}
19535def S2_pstorerbnewt_zomap : HInst<
19536(outs),
19537(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19538"if ($Pv4) memb($Rs32) = $Nt8.new",
19539tc_8fb7ab1b, TypeMAPPING> {
19540let isPseudo = 1;
19541let isCodeGenOnly = 1;
19542let opNewValue = 2;
19543}
19544def S2_pstorerbnewtnew_pi : HInst<
19545(outs IntRegs:$Rx32),
19546(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19547"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19548tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel {
19549let Inst{2-2} = 0b0;
19550let Inst{7-7} = 0b1;
19551let Inst{13-11} = 0b100;
19552let Inst{31-21} = 0b10101011101;
19553let isPredicated = 1;
19554let addrMode = PostInc;
19555let accessSize = ByteAccess;
19556let isNVStore = 1;
19557let isPredicatedNew = 1;
19558let isNewValue = 1;
19559let isRestrictNoSlot1Store = 1;
19560let mayStore = 1;
19561let CextOpcode = "S2_storerb";
19562let BaseOpcode = "S2_storerb_pi";
19563let opNewValue = 4;
19564let Constraints = "$Rx32 = $Rx32in";
19565}
19566def S2_pstorerbt_io : HInst<
19567(outs),
19568(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19569"if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
19570tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19571let Inst{2-2} = 0b0;
19572let Inst{31-21} = 0b01000000000;
19573let isPredicated = 1;
19574let addrMode = BaseImmOffset;
19575let accessSize = ByteAccess;
19576let mayStore = 1;
19577let CextOpcode = "S2_storerb";
19578let InputType = "imm";
19579let BaseOpcode = "S2_storerb_io";
19580let isNVStorable = 1;
19581let isExtendable = 1;
19582let opExtendable = 2;
19583let isExtentSigned = 0;
19584let opExtentBits = 6;
19585let opExtentAlign = 0;
19586}
19587def S2_pstorerbt_pi : HInst<
19588(outs IntRegs:$Rx32),
19589(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19590"if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
19591tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel {
19592let Inst{2-2} = 0b0;
19593let Inst{7-7} = 0b0;
19594let Inst{13-13} = 0b1;
19595let Inst{31-21} = 0b10101011000;
19596let isPredicated = 1;
19597let addrMode = PostInc;
19598let accessSize = ByteAccess;
19599let mayStore = 1;
19600let BaseOpcode = "S2_storerb_pi";
19601let isNVStorable = 1;
19602let Constraints = "$Rx32 = $Rx32in";
19603}
19604def S2_pstorerbt_zomap : HInst<
19605(outs),
19606(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19607"if ($Pv4) memb($Rs32) = $Rt32",
19608tc_f8e23f0b, TypeMAPPING> {
19609let isPseudo = 1;
19610let isCodeGenOnly = 1;
19611}
19612def S2_pstorerbtnew_pi : HInst<
19613(outs IntRegs:$Rx32),
19614(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19615"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19616tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel {
19617let Inst{2-2} = 0b0;
19618let Inst{7-7} = 0b1;
19619let Inst{13-13} = 0b1;
19620let Inst{31-21} = 0b10101011000;
19621let isPredicated = 1;
19622let addrMode = PostInc;
19623let accessSize = ByteAccess;
19624let isPredicatedNew = 1;
19625let mayStore = 1;
19626let BaseOpcode = "S2_storerb_pi";
19627let isNVStorable = 1;
19628let Constraints = "$Rx32 = $Rx32in";
19629}
19630def S2_pstorerdf_io : HInst<
19631(outs),
19632(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
19633"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
19634tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel {
19635let Inst{2-2} = 0b0;
19636let Inst{31-21} = 0b01000100110;
19637let isPredicated = 1;
19638let isPredicatedFalse = 1;
19639let addrMode = BaseImmOffset;
19640let accessSize = DoubleWordAccess;
19641let mayStore = 1;
19642let CextOpcode = "S2_storerd";
19643let InputType = "imm";
19644let BaseOpcode = "S2_storerd_io";
19645let isExtendable = 1;
19646let opExtendable = 2;
19647let isExtentSigned = 0;
19648let opExtentBits = 9;
19649let opExtentAlign = 3;
19650}
19651def S2_pstorerdf_pi : HInst<
19652(outs IntRegs:$Rx32),
19653(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19654"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
19655tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel {
19656let Inst{2-2} = 0b1;
19657let Inst{7-7} = 0b0;
19658let Inst{13-13} = 0b1;
19659let Inst{31-21} = 0b10101011110;
19660let isPredicated = 1;
19661let isPredicatedFalse = 1;
19662let addrMode = PostInc;
19663let accessSize = DoubleWordAccess;
19664let mayStore = 1;
19665let CextOpcode = "S2_storerd";
19666let BaseOpcode = "S2_storerd_pi";
19667let Constraints = "$Rx32 = $Rx32in";
19668}
19669def S2_pstorerdf_zomap : HInst<
19670(outs),
19671(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19672"if (!$Pv4) memd($Rs32) = $Rtt32",
19673tc_f8e23f0b, TypeMAPPING> {
19674let isPseudo = 1;
19675let isCodeGenOnly = 1;
19676}
19677def S2_pstorerdfnew_pi : HInst<
19678(outs IntRegs:$Rx32),
19679(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19680"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
19681tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel {
19682let Inst{2-2} = 0b1;
19683let Inst{7-7} = 0b1;
19684let Inst{13-13} = 0b1;
19685let Inst{31-21} = 0b10101011110;
19686let isPredicated = 1;
19687let isPredicatedFalse = 1;
19688let addrMode = PostInc;
19689let accessSize = DoubleWordAccess;
19690let isPredicatedNew = 1;
19691let mayStore = 1;
19692let CextOpcode = "S2_storerd";
19693let BaseOpcode = "S2_storerd_pi";
19694let Constraints = "$Rx32 = $Rx32in";
19695}
19696def S2_pstorerdt_io : HInst<
19697(outs),
19698(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
19699"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
19700tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel {
19701let Inst{2-2} = 0b0;
19702let Inst{31-21} = 0b01000000110;
19703let isPredicated = 1;
19704let addrMode = BaseImmOffset;
19705let accessSize = DoubleWordAccess;
19706let mayStore = 1;
19707let CextOpcode = "S2_storerd";
19708let InputType = "imm";
19709let BaseOpcode = "S2_storerd_io";
19710let isExtendable = 1;
19711let opExtendable = 2;
19712let isExtentSigned = 0;
19713let opExtentBits = 9;
19714let opExtentAlign = 3;
19715}
19716def S2_pstorerdt_pi : HInst<
19717(outs IntRegs:$Rx32),
19718(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19719"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
19720tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel {
19721let Inst{2-2} = 0b0;
19722let Inst{7-7} = 0b0;
19723let Inst{13-13} = 0b1;
19724let Inst{31-21} = 0b10101011110;
19725let isPredicated = 1;
19726let addrMode = PostInc;
19727let accessSize = DoubleWordAccess;
19728let mayStore = 1;
19729let CextOpcode = "S2_storerd";
19730let BaseOpcode = "S2_storerd_pi";
19731let Constraints = "$Rx32 = $Rx32in";
19732}
19733def S2_pstorerdt_zomap : HInst<
19734(outs),
19735(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19736"if ($Pv4) memd($Rs32) = $Rtt32",
19737tc_f8e23f0b, TypeMAPPING> {
19738let isPseudo = 1;
19739let isCodeGenOnly = 1;
19740}
19741def S2_pstorerdtnew_pi : HInst<
19742(outs IntRegs:$Rx32),
19743(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
19744"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
19745tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel {
19746let Inst{2-2} = 0b0;
19747let Inst{7-7} = 0b1;
19748let Inst{13-13} = 0b1;
19749let Inst{31-21} = 0b10101011110;
19750let isPredicated = 1;
19751let addrMode = PostInc;
19752let accessSize = DoubleWordAccess;
19753let isPredicatedNew = 1;
19754let mayStore = 1;
19755let CextOpcode = "S2_storerd";
19756let BaseOpcode = "S2_storerd_pi";
19757let Constraints = "$Rx32 = $Rx32in";
19758}
19759def S2_pstorerff_io : HInst<
19760(outs),
19761(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
19762"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
19763tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
19764let Inst{2-2} = 0b0;
19765let Inst{31-21} = 0b01000100011;
19766let isPredicated = 1;
19767let isPredicatedFalse = 1;
19768let addrMode = BaseImmOffset;
19769let accessSize = HalfWordAccess;
19770let mayStore = 1;
19771let CextOpcode = "S2_storerf";
19772let InputType = "imm";
19773let BaseOpcode = "S2_storerf_io";
19774let isExtendable = 1;
19775let opExtendable = 2;
19776let isExtentSigned = 0;
19777let opExtentBits = 7;
19778let opExtentAlign = 1;
19779}
19780def S2_pstorerff_pi : HInst<
19781(outs IntRegs:$Rx32),
19782(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19783"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
19784tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel {
19785let Inst{2-2} = 0b1;
19786let Inst{7-7} = 0b0;
19787let Inst{13-13} = 0b1;
19788let Inst{31-21} = 0b10101011011;
19789let isPredicated = 1;
19790let isPredicatedFalse = 1;
19791let addrMode = PostInc;
19792let accessSize = HalfWordAccess;
19793let mayStore = 1;
19794let CextOpcode = "S2_storerf";
19795let BaseOpcode = "S2_storerf_pi";
19796let Constraints = "$Rx32 = $Rx32in";
19797}
19798def S2_pstorerff_zomap : HInst<
19799(outs),
19800(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19801"if (!$Pv4) memh($Rs32) = $Rt32.h",
19802tc_f8e23f0b, TypeMAPPING> {
19803let isPseudo = 1;
19804let isCodeGenOnly = 1;
19805}
19806def S2_pstorerffnew_pi : HInst<
19807(outs IntRegs:$Rx32),
19808(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19809"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
19810tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel {
19811let Inst{2-2} = 0b1;
19812let Inst{7-7} = 0b1;
19813let Inst{13-13} = 0b1;
19814let Inst{31-21} = 0b10101011011;
19815let isPredicated = 1;
19816let isPredicatedFalse = 1;
19817let addrMode = PostInc;
19818let accessSize = HalfWordAccess;
19819let isPredicatedNew = 1;
19820let mayStore = 1;
19821let CextOpcode = "S2_storerf";
19822let BaseOpcode = "S2_storerf_pi";
19823let Constraints = "$Rx32 = $Rx32in";
19824}
19825def S2_pstorerft_io : HInst<
19826(outs),
19827(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
19828"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
19829tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
19830let Inst{2-2} = 0b0;
19831let Inst{31-21} = 0b01000000011;
19832let isPredicated = 1;
19833let addrMode = BaseImmOffset;
19834let accessSize = HalfWordAccess;
19835let mayStore = 1;
19836let CextOpcode = "S2_storerf";
19837let InputType = "imm";
19838let BaseOpcode = "S2_storerf_io";
19839let isExtendable = 1;
19840let opExtendable = 2;
19841let isExtentSigned = 0;
19842let opExtentBits = 7;
19843let opExtentAlign = 1;
19844}
19845def S2_pstorerft_pi : HInst<
19846(outs IntRegs:$Rx32),
19847(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19848"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
19849tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel {
19850let Inst{2-2} = 0b0;
19851let Inst{7-7} = 0b0;
19852let Inst{13-13} = 0b1;
19853let Inst{31-21} = 0b10101011011;
19854let isPredicated = 1;
19855let addrMode = PostInc;
19856let accessSize = HalfWordAccess;
19857let mayStore = 1;
19858let CextOpcode = "S2_storerf";
19859let BaseOpcode = "S2_storerf_pi";
19860let Constraints = "$Rx32 = $Rx32in";
19861}
19862def S2_pstorerft_zomap : HInst<
19863(outs),
19864(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19865"if ($Pv4) memh($Rs32) = $Rt32.h",
19866tc_f8e23f0b, TypeMAPPING> {
19867let isPseudo = 1;
19868let isCodeGenOnly = 1;
19869}
19870def S2_pstorerftnew_pi : HInst<
19871(outs IntRegs:$Rx32),
19872(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19873"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
19874tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel {
19875let Inst{2-2} = 0b0;
19876let Inst{7-7} = 0b1;
19877let Inst{13-13} = 0b1;
19878let Inst{31-21} = 0b10101011011;
19879let isPredicated = 1;
19880let addrMode = PostInc;
19881let accessSize = HalfWordAccess;
19882let isPredicatedNew = 1;
19883let mayStore = 1;
19884let CextOpcode = "S2_storerf";
19885let BaseOpcode = "S2_storerf_pi";
19886let Constraints = "$Rx32 = $Rx32in";
19887}
19888def S2_pstorerhf_io : HInst<
19889(outs),
19890(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
19891"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
19892tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
19893let Inst{2-2} = 0b0;
19894let Inst{31-21} = 0b01000100010;
19895let isPredicated = 1;
19896let isPredicatedFalse = 1;
19897let addrMode = BaseImmOffset;
19898let accessSize = HalfWordAccess;
19899let mayStore = 1;
19900let CextOpcode = "S2_storerh";
19901let InputType = "imm";
19902let BaseOpcode = "S2_storerh_io";
19903let isNVStorable = 1;
19904let isExtendable = 1;
19905let opExtendable = 2;
19906let isExtentSigned = 0;
19907let opExtentBits = 7;
19908let opExtentAlign = 1;
19909}
19910def S2_pstorerhf_pi : HInst<
19911(outs IntRegs:$Rx32),
19912(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19913"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
19914tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel {
19915let Inst{2-2} = 0b1;
19916let Inst{7-7} = 0b0;
19917let Inst{13-13} = 0b1;
19918let Inst{31-21} = 0b10101011010;
19919let isPredicated = 1;
19920let isPredicatedFalse = 1;
19921let addrMode = PostInc;
19922let accessSize = HalfWordAccess;
19923let mayStore = 1;
19924let BaseOpcode = "S2_storerh_pi";
19925let isNVStorable = 1;
19926let Constraints = "$Rx32 = $Rx32in";
19927}
19928def S2_pstorerhf_zomap : HInst<
19929(outs),
19930(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19931"if (!$Pv4) memh($Rs32) = $Rt32",
19932tc_f8e23f0b, TypeMAPPING> {
19933let isPseudo = 1;
19934let isCodeGenOnly = 1;
19935}
19936def S2_pstorerhfnew_pi : HInst<
19937(outs IntRegs:$Rx32),
19938(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
19939"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
19940tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel {
19941let Inst{2-2} = 0b1;
19942let Inst{7-7} = 0b1;
19943let Inst{13-13} = 0b1;
19944let Inst{31-21} = 0b10101011010;
19945let isPredicated = 1;
19946let isPredicatedFalse = 1;
19947let addrMode = PostInc;
19948let accessSize = HalfWordAccess;
19949let isPredicatedNew = 1;
19950let mayStore = 1;
19951let BaseOpcode = "S2_storerh_pi";
19952let isNVStorable = 1;
19953let Constraints = "$Rx32 = $Rx32in";
19954}
19955def S2_pstorerhnewf_io : HInst<
19956(outs),
19957(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
19958"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
19959tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel {
19960let Inst{2-2} = 0b0;
19961let Inst{12-11} = 0b01;
19962let Inst{31-21} = 0b01000100101;
19963let isPredicated = 1;
19964let isPredicatedFalse = 1;
19965let addrMode = BaseImmOffset;
19966let accessSize = HalfWordAccess;
19967let isNVStore = 1;
19968let isNewValue = 1;
19969let isRestrictNoSlot1Store = 1;
19970let mayStore = 1;
19971let CextOpcode = "S2_storerh";
19972let InputType = "imm";
19973let BaseOpcode = "S2_storerh_io";
19974let isExtendable = 1;
19975let opExtendable = 2;
19976let isExtentSigned = 0;
19977let opExtentBits = 7;
19978let opExtentAlign = 1;
19979let opNewValue = 3;
19980}
19981def S2_pstorerhnewf_pi : HInst<
19982(outs IntRegs:$Rx32),
19983(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
19984"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
19985tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel {
19986let Inst{2-2} = 0b1;
19987let Inst{7-7} = 0b0;
19988let Inst{13-11} = 0b101;
19989let Inst{31-21} = 0b10101011101;
19990let isPredicated = 1;
19991let isPredicatedFalse = 1;
19992let addrMode = PostInc;
19993let accessSize = HalfWordAccess;
19994let isNVStore = 1;
19995let isNewValue = 1;
19996let isRestrictNoSlot1Store = 1;
19997let mayStore = 1;
19998let CextOpcode = "S2_storerh";
19999let BaseOpcode = "S2_storerh_pi";
20000let opNewValue = 4;
20001let Constraints = "$Rx32 = $Rx32in";
20002}
20003def S2_pstorerhnewf_zomap : HInst<
20004(outs),
20005(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20006"if (!$Pv4) memh($Rs32) = $Nt8.new",
20007tc_8fb7ab1b, TypeMAPPING> {
20008let isPseudo = 1;
20009let isCodeGenOnly = 1;
20010let opNewValue = 2;
20011}
20012def S2_pstorerhnewfnew_pi : HInst<
20013(outs IntRegs:$Rx32),
20014(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20015"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20016tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel {
20017let Inst{2-2} = 0b1;
20018let Inst{7-7} = 0b1;
20019let Inst{13-11} = 0b101;
20020let Inst{31-21} = 0b10101011101;
20021let isPredicated = 1;
20022let isPredicatedFalse = 1;
20023let addrMode = PostInc;
20024let accessSize = HalfWordAccess;
20025let isNVStore = 1;
20026let isPredicatedNew = 1;
20027let isNewValue = 1;
20028let isRestrictNoSlot1Store = 1;
20029let mayStore = 1;
20030let CextOpcode = "S2_storerh";
20031let BaseOpcode = "S2_storerh_pi";
20032let opNewValue = 4;
20033let Constraints = "$Rx32 = $Rx32in";
20034}
20035def S2_pstorerhnewt_io : HInst<
20036(outs),
20037(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20038"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20039tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel {
20040let Inst{2-2} = 0b0;
20041let Inst{12-11} = 0b01;
20042let Inst{31-21} = 0b01000000101;
20043let isPredicated = 1;
20044let addrMode = BaseImmOffset;
20045let accessSize = HalfWordAccess;
20046let isNVStore = 1;
20047let isNewValue = 1;
20048let isRestrictNoSlot1Store = 1;
20049let mayStore = 1;
20050let CextOpcode = "S2_storerh";
20051let InputType = "imm";
20052let BaseOpcode = "S2_storerh_io";
20053let isExtendable = 1;
20054let opExtendable = 2;
20055let isExtentSigned = 0;
20056let opExtentBits = 7;
20057let opExtentAlign = 1;
20058let opNewValue = 3;
20059}
20060def S2_pstorerhnewt_pi : HInst<
20061(outs IntRegs:$Rx32),
20062(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20063"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20064tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel {
20065let Inst{2-2} = 0b0;
20066let Inst{7-7} = 0b0;
20067let Inst{13-11} = 0b101;
20068let Inst{31-21} = 0b10101011101;
20069let isPredicated = 1;
20070let addrMode = PostInc;
20071let accessSize = HalfWordAccess;
20072let isNVStore = 1;
20073let isNewValue = 1;
20074let isRestrictNoSlot1Store = 1;
20075let mayStore = 1;
20076let CextOpcode = "S2_storerh";
20077let BaseOpcode = "S2_storerh_pi";
20078let opNewValue = 4;
20079let Constraints = "$Rx32 = $Rx32in";
20080}
20081def S2_pstorerhnewt_zomap : HInst<
20082(outs),
20083(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20084"if ($Pv4) memh($Rs32) = $Nt8.new",
20085tc_8fb7ab1b, TypeMAPPING> {
20086let isPseudo = 1;
20087let isCodeGenOnly = 1;
20088let opNewValue = 2;
20089}
20090def S2_pstorerhnewtnew_pi : HInst<
20091(outs IntRegs:$Rx32),
20092(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20093"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20094tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel {
20095let Inst{2-2} = 0b0;
20096let Inst{7-7} = 0b1;
20097let Inst{13-11} = 0b101;
20098let Inst{31-21} = 0b10101011101;
20099let isPredicated = 1;
20100let addrMode = PostInc;
20101let accessSize = HalfWordAccess;
20102let isNVStore = 1;
20103let isPredicatedNew = 1;
20104let isNewValue = 1;
20105let isRestrictNoSlot1Store = 1;
20106let mayStore = 1;
20107let CextOpcode = "S2_storerh";
20108let BaseOpcode = "S2_storerh_pi";
20109let opNewValue = 4;
20110let Constraints = "$Rx32 = $Rx32in";
20111}
20112def S2_pstorerht_io : HInst<
20113(outs),
20114(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20115"if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
20116tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20117let Inst{2-2} = 0b0;
20118let Inst{31-21} = 0b01000000010;
20119let isPredicated = 1;
20120let addrMode = BaseImmOffset;
20121let accessSize = HalfWordAccess;
20122let mayStore = 1;
20123let CextOpcode = "S2_storerh";
20124let InputType = "imm";
20125let BaseOpcode = "S2_storerh_io";
20126let isNVStorable = 1;
20127let isExtendable = 1;
20128let opExtendable = 2;
20129let isExtentSigned = 0;
20130let opExtentBits = 7;
20131let opExtentAlign = 1;
20132}
20133def S2_pstorerht_pi : HInst<
20134(outs IntRegs:$Rx32),
20135(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20136"if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
20137tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel {
20138let Inst{2-2} = 0b0;
20139let Inst{7-7} = 0b0;
20140let Inst{13-13} = 0b1;
20141let Inst{31-21} = 0b10101011010;
20142let isPredicated = 1;
20143let addrMode = PostInc;
20144let accessSize = HalfWordAccess;
20145let mayStore = 1;
20146let BaseOpcode = "S2_storerh_pi";
20147let isNVStorable = 1;
20148let Constraints = "$Rx32 = $Rx32in";
20149}
20150def S2_pstorerht_zomap : HInst<
20151(outs),
20152(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20153"if ($Pv4) memh($Rs32) = $Rt32",
20154tc_f8e23f0b, TypeMAPPING> {
20155let isPseudo = 1;
20156let isCodeGenOnly = 1;
20157}
20158def S2_pstorerhtnew_pi : HInst<
20159(outs IntRegs:$Rx32),
20160(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20161"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20162tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel {
20163let Inst{2-2} = 0b0;
20164let Inst{7-7} = 0b1;
20165let Inst{13-13} = 0b1;
20166let Inst{31-21} = 0b10101011010;
20167let isPredicated = 1;
20168let addrMode = PostInc;
20169let accessSize = HalfWordAccess;
20170let isPredicatedNew = 1;
20171let mayStore = 1;
20172let BaseOpcode = "S2_storerh_pi";
20173let isNVStorable = 1;
20174let Constraints = "$Rx32 = $Rx32in";
20175}
20176def S2_pstorerif_io : HInst<
20177(outs),
20178(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20179"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
20180tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel {
20181let Inst{2-2} = 0b0;
20182let Inst{31-21} = 0b01000100100;
20183let isPredicated = 1;
20184let isPredicatedFalse = 1;
20185let addrMode = BaseImmOffset;
20186let accessSize = WordAccess;
20187let mayStore = 1;
20188let CextOpcode = "S2_storeri";
20189let InputType = "imm";
20190let BaseOpcode = "S2_storeri_io";
20191let isNVStorable = 1;
20192let isExtendable = 1;
20193let opExtendable = 2;
20194let isExtentSigned = 0;
20195let opExtentBits = 8;
20196let opExtentAlign = 2;
20197}
20198def S2_pstorerif_pi : HInst<
20199(outs IntRegs:$Rx32),
20200(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20201"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
20202tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel {
20203let Inst{2-2} = 0b1;
20204let Inst{7-7} = 0b0;
20205let Inst{13-13} = 0b1;
20206let Inst{31-21} = 0b10101011100;
20207let isPredicated = 1;
20208let isPredicatedFalse = 1;
20209let addrMode = PostInc;
20210let accessSize = WordAccess;
20211let mayStore = 1;
20212let BaseOpcode = "S2_storeri_pi";
20213let isNVStorable = 1;
20214let Constraints = "$Rx32 = $Rx32in";
20215}
20216def S2_pstorerif_zomap : HInst<
20217(outs),
20218(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20219"if (!$Pv4) memw($Rs32) = $Rt32",
20220tc_f8e23f0b, TypeMAPPING> {
20221let isPseudo = 1;
20222let isCodeGenOnly = 1;
20223}
20224def S2_pstorerifnew_pi : HInst<
20225(outs IntRegs:$Rx32),
20226(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20227"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20228tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel {
20229let Inst{2-2} = 0b1;
20230let Inst{7-7} = 0b1;
20231let Inst{13-13} = 0b1;
20232let Inst{31-21} = 0b10101011100;
20233let isPredicated = 1;
20234let isPredicatedFalse = 1;
20235let addrMode = PostInc;
20236let accessSize = WordAccess;
20237let isPredicatedNew = 1;
20238let mayStore = 1;
20239let CextOpcode = "S2_storeri";
20240let BaseOpcode = "S2_storeri_pi";
20241let isNVStorable = 1;
20242let Constraints = "$Rx32 = $Rx32in";
20243}
20244def S2_pstorerinewf_io : HInst<
20245(outs),
20246(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20247"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20248tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20249let Inst{2-2} = 0b0;
20250let Inst{12-11} = 0b10;
20251let Inst{31-21} = 0b01000100101;
20252let isPredicated = 1;
20253let isPredicatedFalse = 1;
20254let addrMode = BaseImmOffset;
20255let accessSize = WordAccess;
20256let isNVStore = 1;
20257let isNewValue = 1;
20258let isRestrictNoSlot1Store = 1;
20259let mayStore = 1;
20260let CextOpcode = "S2_storeri";
20261let InputType = "imm";
20262let BaseOpcode = "S2_storeri_io";
20263let isExtendable = 1;
20264let opExtendable = 2;
20265let isExtentSigned = 0;
20266let opExtentBits = 8;
20267let opExtentAlign = 2;
20268let opNewValue = 3;
20269}
20270def S2_pstorerinewf_pi : HInst<
20271(outs IntRegs:$Rx32),
20272(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20273"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20274tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel {
20275let Inst{2-2} = 0b1;
20276let Inst{7-7} = 0b0;
20277let Inst{13-11} = 0b110;
20278let Inst{31-21} = 0b10101011101;
20279let isPredicated = 1;
20280let isPredicatedFalse = 1;
20281let addrMode = PostInc;
20282let accessSize = WordAccess;
20283let isNVStore = 1;
20284let isNewValue = 1;
20285let isRestrictNoSlot1Store = 1;
20286let mayStore = 1;
20287let CextOpcode = "S2_storeri";
20288let BaseOpcode = "S2_storeri_pi";
20289let opNewValue = 4;
20290let Constraints = "$Rx32 = $Rx32in";
20291}
20292def S2_pstorerinewf_zomap : HInst<
20293(outs),
20294(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20295"if (!$Pv4) memw($Rs32) = $Nt8.new",
20296tc_8fb7ab1b, TypeMAPPING> {
20297let isPseudo = 1;
20298let isCodeGenOnly = 1;
20299let opNewValue = 2;
20300}
20301def S2_pstorerinewfnew_pi : HInst<
20302(outs IntRegs:$Rx32),
20303(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20304"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20305tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel {
20306let Inst{2-2} = 0b1;
20307let Inst{7-7} = 0b1;
20308let Inst{13-11} = 0b110;
20309let Inst{31-21} = 0b10101011101;
20310let isPredicated = 1;
20311let isPredicatedFalse = 1;
20312let addrMode = PostInc;
20313let accessSize = WordAccess;
20314let isNVStore = 1;
20315let isPredicatedNew = 1;
20316let isNewValue = 1;
20317let isRestrictNoSlot1Store = 1;
20318let mayStore = 1;
20319let CextOpcode = "S2_storeri";
20320let BaseOpcode = "S2_storeri_pi";
20321let opNewValue = 4;
20322let Constraints = "$Rx32 = $Rx32in";
20323}
20324def S2_pstorerinewt_io : HInst<
20325(outs),
20326(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20327"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20328tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20329let Inst{2-2} = 0b0;
20330let Inst{12-11} = 0b10;
20331let Inst{31-21} = 0b01000000101;
20332let isPredicated = 1;
20333let addrMode = BaseImmOffset;
20334let accessSize = WordAccess;
20335let isNVStore = 1;
20336let isNewValue = 1;
20337let isRestrictNoSlot1Store = 1;
20338let mayStore = 1;
20339let CextOpcode = "S2_storeri";
20340let InputType = "imm";
20341let BaseOpcode = "S2_storeri_io";
20342let isExtendable = 1;
20343let opExtendable = 2;
20344let isExtentSigned = 0;
20345let opExtentBits = 8;
20346let opExtentAlign = 2;
20347let opNewValue = 3;
20348}
20349def S2_pstorerinewt_pi : HInst<
20350(outs IntRegs:$Rx32),
20351(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20352"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20353tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel {
20354let Inst{2-2} = 0b0;
20355let Inst{7-7} = 0b0;
20356let Inst{13-11} = 0b110;
20357let Inst{31-21} = 0b10101011101;
20358let isPredicated = 1;
20359let addrMode = PostInc;
20360let accessSize = WordAccess;
20361let isNVStore = 1;
20362let isNewValue = 1;
20363let isRestrictNoSlot1Store = 1;
20364let mayStore = 1;
20365let CextOpcode = "S2_storeri";
20366let BaseOpcode = "S2_storeri_pi";
20367let opNewValue = 4;
20368let Constraints = "$Rx32 = $Rx32in";
20369}
20370def S2_pstorerinewt_zomap : HInst<
20371(outs),
20372(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20373"if ($Pv4) memw($Rs32) = $Nt8.new",
20374tc_8fb7ab1b, TypeMAPPING> {
20375let isPseudo = 1;
20376let isCodeGenOnly = 1;
20377let opNewValue = 2;
20378}
20379def S2_pstorerinewtnew_pi : HInst<
20380(outs IntRegs:$Rx32),
20381(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20382"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20383tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel {
20384let Inst{2-2} = 0b0;
20385let Inst{7-7} = 0b1;
20386let Inst{13-11} = 0b110;
20387let Inst{31-21} = 0b10101011101;
20388let isPredicated = 1;
20389let addrMode = PostInc;
20390let accessSize = WordAccess;
20391let isNVStore = 1;
20392let isPredicatedNew = 1;
20393let isNewValue = 1;
20394let isRestrictNoSlot1Store = 1;
20395let mayStore = 1;
20396let CextOpcode = "S2_storeri";
20397let BaseOpcode = "S2_storeri_pi";
20398let opNewValue = 4;
20399let Constraints = "$Rx32 = $Rx32in";
20400}
20401def S2_pstorerit_io : HInst<
20402(outs),
20403(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20404"if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
20405tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel {
20406let Inst{2-2} = 0b0;
20407let Inst{31-21} = 0b01000000100;
20408let isPredicated = 1;
20409let addrMode = BaseImmOffset;
20410let accessSize = WordAccess;
20411let mayStore = 1;
20412let CextOpcode = "S2_storeri";
20413let InputType = "imm";
20414let BaseOpcode = "S2_storeri_io";
20415let isNVStorable = 1;
20416let isExtendable = 1;
20417let opExtendable = 2;
20418let isExtentSigned = 0;
20419let opExtentBits = 8;
20420let opExtentAlign = 2;
20421}
20422def S2_pstorerit_pi : HInst<
20423(outs IntRegs:$Rx32),
20424(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20425"if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
20426tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel {
20427let Inst{2-2} = 0b0;
20428let Inst{7-7} = 0b0;
20429let Inst{13-13} = 0b1;
20430let Inst{31-21} = 0b10101011100;
20431let isPredicated = 1;
20432let addrMode = PostInc;
20433let accessSize = WordAccess;
20434let mayStore = 1;
20435let BaseOpcode = "S2_storeri_pi";
20436let isNVStorable = 1;
20437let Constraints = "$Rx32 = $Rx32in";
20438}
20439def S2_pstorerit_zomap : HInst<
20440(outs),
20441(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20442"if ($Pv4) memw($Rs32) = $Rt32",
20443tc_f8e23f0b, TypeMAPPING> {
20444let isPseudo = 1;
20445let isCodeGenOnly = 1;
20446}
20447def S2_pstoreritnew_pi : HInst<
20448(outs IntRegs:$Rx32),
20449(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20450"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20451tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel {
20452let Inst{2-2} = 0b0;
20453let Inst{7-7} = 0b1;
20454let Inst{13-13} = 0b1;
20455let Inst{31-21} = 0b10101011100;
20456let isPredicated = 1;
20457let addrMode = PostInc;
20458let accessSize = WordAccess;
20459let isPredicatedNew = 1;
20460let mayStore = 1;
20461let BaseOpcode = "S2_storeri_pi";
20462let isNVStorable = 1;
20463let Constraints = "$Rx32 = $Rx32in";
20464}
20465def S2_setbit_i : HInst<
20466(outs IntRegs:$Rd32),
20467(ins IntRegs:$Rs32, u5_0Imm:$Ii),
20468"$Rd32 = setbit($Rs32,#$Ii)",
20469tc_946df596, TypeS_2op>, Enc_a05677 {
20470let Inst{7-5} = 0b000;
20471let Inst{13-13} = 0b0;
20472let Inst{31-21} = 0b10001100110;
20473let hasNewValue = 1;
20474let opNewValue = 0;
20475}
20476def S2_setbit_r : HInst<
20477(outs IntRegs:$Rd32),
20478(ins IntRegs:$Rs32, IntRegs:$Rt32),
20479"$Rd32 = setbit($Rs32,$Rt32)",
20480tc_946df596, TypeS_3op>, Enc_5ab2be {
20481let Inst{7-5} = 0b000;
20482let Inst{13-13} = 0b0;
20483let Inst{31-21} = 0b11000110100;
20484let hasNewValue = 1;
20485let opNewValue = 0;
20486}
20487def S2_shuffeb : HInst<
20488(outs DoubleRegs:$Rdd32),
20489(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20490"$Rdd32 = shuffeb($Rss32,$Rtt32)",
20491tc_946df596, TypeS_3op>, Enc_a56825 {
20492let Inst{7-5} = 0b010;
20493let Inst{13-13} = 0b0;
20494let Inst{31-21} = 0b11000001000;
20495}
20496def S2_shuffeh : HInst<
20497(outs DoubleRegs:$Rdd32),
20498(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20499"$Rdd32 = shuffeh($Rss32,$Rtt32)",
20500tc_946df596, TypeS_3op>, Enc_a56825 {
20501let Inst{7-5} = 0b110;
20502let Inst{13-13} = 0b0;
20503let Inst{31-21} = 0b11000001000;
20504}
20505def S2_shuffob : HInst<
20506(outs DoubleRegs:$Rdd32),
20507(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20508"$Rdd32 = shuffob($Rtt32,$Rss32)",
20509tc_946df596, TypeS_3op>, Enc_ea23e4 {
20510let Inst{7-5} = 0b100;
20511let Inst{13-13} = 0b0;
20512let Inst{31-21} = 0b11000001000;
20513}
20514def S2_shuffoh : HInst<
20515(outs DoubleRegs:$Rdd32),
20516(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20517"$Rdd32 = shuffoh($Rtt32,$Rss32)",
20518tc_946df596, TypeS_3op>, Enc_ea23e4 {
20519let Inst{7-5} = 0b000;
20520let Inst{13-13} = 0b0;
20521let Inst{31-21} = 0b11000001100;
20522}
20523def S2_storerb_io : HInst<
20524(outs),
20525(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
20526"memb($Rs32+#$Ii) = $Rt32",
20527tc_30b9bb4a, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
20528let Inst{24-21} = 0b1000;
20529let Inst{31-27} = 0b10100;
20530let addrMode = BaseImmOffset;
20531let accessSize = ByteAccess;
20532let mayStore = 1;
20533let CextOpcode = "S2_storerb";
20534let InputType = "imm";
20535let BaseOpcode = "S2_storerb_io";
20536let isPredicable = 1;
20537let isNVStorable = 1;
20538let isExtendable = 1;
20539let opExtendable = 1;
20540let isExtentSigned = 1;
20541let opExtentBits = 11;
20542let opExtentAlign = 0;
20543}
20544def S2_storerb_pbr : HInst<
20545(outs IntRegs:$Rx32),
20546(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20547"memb($Rx32++$Mu2:brev) = $Rt32",
20548tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel {
20549let Inst{7-0} = 0b00000000;
20550let Inst{31-21} = 0b10101111000;
20551let addrMode = PostInc;
20552let accessSize = ByteAccess;
20553let mayStore = 1;
20554let BaseOpcode = "S2_storerb_pbr";
20555let isNVStorable = 1;
20556let Constraints = "$Rx32 = $Rx32in";
20557}
20558def S2_storerb_pci : HInst<
20559(outs IntRegs:$Rx32),
20560(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20561"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20562tc_e86aa961, TypeST>, Enc_b15941, AddrModeRel {
20563let Inst{2-0} = 0b000;
20564let Inst{7-7} = 0b0;
20565let Inst{31-21} = 0b10101001000;
20566let addrMode = PostInc;
20567let accessSize = ByteAccess;
20568let mayStore = 1;
20569let Uses = [CS];
20570let BaseOpcode = "S2_storerb_pci";
20571let isNVStorable = 1;
20572let Constraints = "$Rx32 = $Rx32in";
20573}
20574def S2_storerb_pcr : HInst<
20575(outs IntRegs:$Rx32),
20576(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20577"memb($Rx32++I:circ($Mu2)) = $Rt32",
20578tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel {
20579let Inst{7-0} = 0b00000010;
20580let Inst{31-21} = 0b10101001000;
20581let addrMode = PostInc;
20582let accessSize = ByteAccess;
20583let mayStore = 1;
20584let Uses = [CS];
20585let BaseOpcode = "S2_storerb_pcr";
20586let isNVStorable = 1;
20587let Constraints = "$Rx32 = $Rx32in";
20588}
20589def S2_storerb_pi : HInst<
20590(outs IntRegs:$Rx32),
20591(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20592"memb($Rx32++#$Ii) = $Rt32",
20593tc_da97ee82, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
20594let Inst{2-0} = 0b000;
20595let Inst{7-7} = 0b0;
20596let Inst{13-13} = 0b0;
20597let Inst{31-21} = 0b10101011000;
20598let addrMode = PostInc;
20599let accessSize = ByteAccess;
20600let mayStore = 1;
20601let CextOpcode = "S2_storerb";
20602let BaseOpcode = "S2_storerb_pi";
20603let isPredicable = 1;
20604let isNVStorable = 1;
20605let Constraints = "$Rx32 = $Rx32in";
20606}
20607def S2_storerb_pr : HInst<
20608(outs IntRegs:$Rx32),
20609(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20610"memb($Rx32++$Mu2) = $Rt32",
20611tc_da97ee82, TypeST>, Enc_d5c73f {
20612let Inst{7-0} = 0b00000000;
20613let Inst{31-21} = 0b10101101000;
20614let addrMode = PostInc;
20615let accessSize = ByteAccess;
20616let mayStore = 1;
20617let isNVStorable = 1;
20618let Constraints = "$Rx32 = $Rx32in";
20619}
20620def S2_storerb_zomap : HInst<
20621(outs),
20622(ins IntRegs:$Rs32, IntRegs:$Rt32),
20623"memb($Rs32) = $Rt32",
20624tc_30b9bb4a, TypeMAPPING> {
20625let isPseudo = 1;
20626let isCodeGenOnly = 1;
20627}
20628def S2_storerbgp : HInst<
20629(outs),
20630(ins u32_0Imm:$Ii, IntRegs:$Rt32),
20631"memb(gp+#$Ii) = $Rt32",
20632tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
20633let Inst{24-21} = 0b0000;
20634let Inst{31-27} = 0b01001;
20635let accessSize = ByteAccess;
20636let mayStore = 1;
20637let Uses = [GP];
20638let BaseOpcode = "S2_storerbabs";
20639let isPredicable = 1;
20640let isNVStorable = 1;
20641let opExtendable = 0;
20642let isExtentSigned = 0;
20643let opExtentBits = 16;
20644let opExtentAlign = 0;
20645}
20646def S2_storerbnew_io : HInst<
20647(outs),
20648(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
20649"memb($Rs32+#$Ii) = $Nt8.new",
20650tc_be9602ff, TypeST>, Enc_4df4e9, AddrModeRel {
20651let Inst{12-11} = 0b00;
20652let Inst{24-21} = 0b1101;
20653let Inst{31-27} = 0b10100;
20654let addrMode = BaseImmOffset;
20655let accessSize = ByteAccess;
20656let isNVStore = 1;
20657let isNewValue = 1;
20658let isRestrictNoSlot1Store = 1;
20659let mayStore = 1;
20660let CextOpcode = "S2_storerb";
20661let InputType = "imm";
20662let BaseOpcode = "S2_storerb_io";
20663let isPredicable = 1;
20664let isExtendable = 1;
20665let opExtendable = 1;
20666let isExtentSigned = 1;
20667let opExtentBits = 11;
20668let opExtentAlign = 0;
20669let opNewValue = 2;
20670}
20671def S2_storerbnew_pbr : HInst<
20672(outs IntRegs:$Rx32),
20673(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
20674"memb($Rx32++$Mu2:brev) = $Nt8.new",
20675tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel {
20676let Inst{7-0} = 0b00000000;
20677let Inst{12-11} = 0b00;
20678let Inst{31-21} = 0b10101111101;
20679let addrMode = PostInc;
20680let accessSize = ByteAccess;
20681let isNVStore = 1;
20682let isNewValue = 1;
20683let isRestrictNoSlot1Store = 1;
20684let mayStore = 1;
20685let BaseOpcode = "S2_storerb_pbr";
20686let opNewValue = 3;
20687let Constraints = "$Rx32 = $Rx32in";
20688}
20689def S2_storerbnew_pci : HInst<
20690(outs IntRegs:$Rx32),
20691(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
20692"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
20693tc_d5c0729a, TypeST>, Enc_96ce4f, AddrModeRel {
20694let Inst{2-0} = 0b000;
20695let Inst{7-7} = 0b0;
20696let Inst{12-11} = 0b00;
20697let Inst{31-21} = 0b10101001101;
20698let addrMode = PostInc;
20699let accessSize = ByteAccess;
20700let isNVStore = 1;
20701let isNewValue = 1;
20702let isRestrictNoSlot1Store = 1;
20703let mayStore = 1;
20704let Uses = [CS];
20705let BaseOpcode = "S2_storerb_pci";
20706let opNewValue = 4;
20707let Constraints = "$Rx32 = $Rx32in";
20708}
20709def S2_storerbnew_pcr : HInst<
20710(outs IntRegs:$Rx32),
20711(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
20712"memb($Rx32++I:circ($Mu2)) = $Nt8.new",
20713tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel {
20714let Inst{7-0} = 0b00000010;
20715let Inst{12-11} = 0b00;
20716let Inst{31-21} = 0b10101001101;
20717let addrMode = PostInc;
20718let accessSize = ByteAccess;
20719let isNVStore = 1;
20720let isNewValue = 1;
20721let isRestrictNoSlot1Store = 1;
20722let mayStore = 1;
20723let Uses = [CS];
20724let BaseOpcode = "S2_storerb_pcr";
20725let opNewValue = 3;
20726let Constraints = "$Rx32 = $Rx32in";
20727}
20728def S2_storerbnew_pi : HInst<
20729(outs IntRegs:$Rx32),
20730(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
20731"memb($Rx32++#$Ii) = $Nt8.new",
20732tc_c79a189f, TypeST>, Enc_c7cd90, AddrModeRel {
20733let Inst{2-0} = 0b000;
20734let Inst{7-7} = 0b0;
20735let Inst{13-11} = 0b000;
20736let Inst{31-21} = 0b10101011101;
20737let addrMode = PostInc;
20738let accessSize = ByteAccess;
20739let isNVStore = 1;
20740let isNewValue = 1;
20741let isRestrictNoSlot1Store = 1;
20742let mayStore = 1;
20743let BaseOpcode = "S2_storerb_pi";
20744let isPredicable = 1;
20745let isNVStorable = 1;
20746let opNewValue = 3;
20747let Constraints = "$Rx32 = $Rx32in";
20748}
20749def S2_storerbnew_pr : HInst<
20750(outs IntRegs:$Rx32),
20751(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
20752"memb($Rx32++$Mu2) = $Nt8.new",
20753tc_c79a189f, TypeST>, Enc_8dbe85 {
20754let Inst{7-0} = 0b00000000;
20755let Inst{12-11} = 0b00;
20756let Inst{31-21} = 0b10101101101;
20757let addrMode = PostInc;
20758let accessSize = ByteAccess;
20759let isNVStore = 1;
20760let isNewValue = 1;
20761let isRestrictNoSlot1Store = 1;
20762let mayStore = 1;
20763let opNewValue = 3;
20764let Constraints = "$Rx32 = $Rx32in";
20765}
20766def S2_storerbnew_zomap : HInst<
20767(outs),
20768(ins IntRegs:$Rs32, IntRegs:$Nt8),
20769"memb($Rs32) = $Nt8.new",
20770tc_be9602ff, TypeMAPPING> {
20771let isPseudo = 1;
20772let isCodeGenOnly = 1;
20773let opNewValue = 1;
20774}
20775def S2_storerbnewgp : HInst<
20776(outs),
20777(ins u32_0Imm:$Ii, IntRegs:$Nt8),
20778"memb(gp+#$Ii) = $Nt8.new",
20779tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel {
20780let Inst{12-11} = 0b00;
20781let Inst{24-21} = 0b0101;
20782let Inst{31-27} = 0b01001;
20783let accessSize = ByteAccess;
20784let isNVStore = 1;
20785let isNewValue = 1;
20786let isRestrictNoSlot1Store = 1;
20787let mayStore = 1;
20788let Uses = [GP];
20789let BaseOpcode = "S2_storerbabs";
20790let isPredicable = 1;
20791let opExtendable = 0;
20792let isExtentSigned = 0;
20793let opExtentBits = 16;
20794let opExtentAlign = 0;
20795let opNewValue = 1;
20796}
20797def S2_storerd_io : HInst<
20798(outs),
20799(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
20800"memd($Rs32+#$Ii) = $Rtt32",
20801tc_30b9bb4a, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
20802let Inst{24-21} = 0b1110;
20803let Inst{31-27} = 0b10100;
20804let addrMode = BaseImmOffset;
20805let accessSize = DoubleWordAccess;
20806let mayStore = 1;
20807let CextOpcode = "S2_storerd";
20808let InputType = "imm";
20809let BaseOpcode = "S2_storerd_io";
20810let isPredicable = 1;
20811let isExtendable = 1;
20812let opExtendable = 1;
20813let isExtentSigned = 1;
20814let opExtentBits = 14;
20815let opExtentAlign = 3;
20816}
20817def S2_storerd_pbr : HInst<
20818(outs IntRegs:$Rx32),
20819(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20820"memd($Rx32++$Mu2:brev) = $Rtt32",
20821tc_da97ee82, TypeST>, Enc_928ca1 {
20822let Inst{7-0} = 0b00000000;
20823let Inst{31-21} = 0b10101111110;
20824let addrMode = PostInc;
20825let accessSize = DoubleWordAccess;
20826let mayStore = 1;
20827let Constraints = "$Rx32 = $Rx32in";
20828}
20829def S2_storerd_pci : HInst<
20830(outs IntRegs:$Rx32),
20831(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20832"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
20833tc_e86aa961, TypeST>, Enc_395cc4 {
20834let Inst{2-0} = 0b000;
20835let Inst{7-7} = 0b0;
20836let Inst{31-21} = 0b10101001110;
20837let addrMode = PostInc;
20838let accessSize = DoubleWordAccess;
20839let mayStore = 1;
20840let Uses = [CS];
20841let Constraints = "$Rx32 = $Rx32in";
20842}
20843def S2_storerd_pcr : HInst<
20844(outs IntRegs:$Rx32),
20845(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20846"memd($Rx32++I:circ($Mu2)) = $Rtt32",
20847tc_da97ee82, TypeST>, Enc_928ca1 {
20848let Inst{7-0} = 0b00000010;
20849let Inst{31-21} = 0b10101001110;
20850let addrMode = PostInc;
20851let accessSize = DoubleWordAccess;
20852let mayStore = 1;
20853let Uses = [CS];
20854let Constraints = "$Rx32 = $Rx32in";
20855}
20856def S2_storerd_pi : HInst<
20857(outs IntRegs:$Rx32),
20858(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20859"memd($Rx32++#$Ii) = $Rtt32",
20860tc_da97ee82, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
20861let Inst{2-0} = 0b000;
20862let Inst{7-7} = 0b0;
20863let Inst{13-13} = 0b0;
20864let Inst{31-21} = 0b10101011110;
20865let addrMode = PostInc;
20866let accessSize = DoubleWordAccess;
20867let mayStore = 1;
20868let CextOpcode = "S2_storerd";
20869let BaseOpcode = "S2_storerd_pi";
20870let isPredicable = 1;
20871let Constraints = "$Rx32 = $Rx32in";
20872}
20873def S2_storerd_pr : HInst<
20874(outs IntRegs:$Rx32),
20875(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
20876"memd($Rx32++$Mu2) = $Rtt32",
20877tc_da97ee82, TypeST>, Enc_928ca1 {
20878let Inst{7-0} = 0b00000000;
20879let Inst{31-21} = 0b10101101110;
20880let addrMode = PostInc;
20881let accessSize = DoubleWordAccess;
20882let mayStore = 1;
20883let Constraints = "$Rx32 = $Rx32in";
20884}
20885def S2_storerd_zomap : HInst<
20886(outs),
20887(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
20888"memd($Rs32) = $Rtt32",
20889tc_30b9bb4a, TypeMAPPING> {
20890let isPseudo = 1;
20891let isCodeGenOnly = 1;
20892}
20893def S2_storerdgp : HInst<
20894(outs),
20895(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20896"memd(gp+#$Ii) = $Rtt32",
20897tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel {
20898let Inst{24-21} = 0b0110;
20899let Inst{31-27} = 0b01001;
20900let accessSize = DoubleWordAccess;
20901let mayStore = 1;
20902let Uses = [GP];
20903let BaseOpcode = "S2_storerdabs";
20904let isPredicable = 1;
20905let opExtendable = 0;
20906let isExtentSigned = 0;
20907let opExtentBits = 19;
20908let opExtentAlign = 3;
20909}
20910def S2_storerf_io : HInst<
20911(outs),
20912(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
20913"memh($Rs32+#$Ii) = $Rt32.h",
20914tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
20915let Inst{24-21} = 0b1011;
20916let Inst{31-27} = 0b10100;
20917let addrMode = BaseImmOffset;
20918let accessSize = HalfWordAccess;
20919let mayStore = 1;
20920let CextOpcode = "S2_storerf";
20921let InputType = "imm";
20922let BaseOpcode = "S2_storerf_io";
20923let isPredicable = 1;
20924let isExtendable = 1;
20925let opExtendable = 1;
20926let isExtentSigned = 1;
20927let opExtentBits = 12;
20928let opExtentAlign = 1;
20929}
20930def S2_storerf_pbr : HInst<
20931(outs IntRegs:$Rx32),
20932(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20933"memh($Rx32++$Mu2:brev) = $Rt32.h",
20934tc_da97ee82, TypeST>, Enc_d5c73f {
20935let Inst{7-0} = 0b00000000;
20936let Inst{31-21} = 0b10101111011;
20937let addrMode = PostInc;
20938let accessSize = HalfWordAccess;
20939let mayStore = 1;
20940let Constraints = "$Rx32 = $Rx32in";
20941}
20942def S2_storerf_pci : HInst<
20943(outs IntRegs:$Rx32),
20944(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20945"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
20946tc_e86aa961, TypeST>, Enc_935d9b {
20947let Inst{2-0} = 0b000;
20948let Inst{7-7} = 0b0;
20949let Inst{31-21} = 0b10101001011;
20950let addrMode = PostInc;
20951let accessSize = HalfWordAccess;
20952let mayStore = 1;
20953let Uses = [CS];
20954let Constraints = "$Rx32 = $Rx32in";
20955}
20956def S2_storerf_pcr : HInst<
20957(outs IntRegs:$Rx32),
20958(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20959"memh($Rx32++I:circ($Mu2)) = $Rt32.h",
20960tc_da97ee82, TypeST>, Enc_d5c73f {
20961let Inst{7-0} = 0b00000010;
20962let Inst{31-21} = 0b10101001011;
20963let addrMode = PostInc;
20964let accessSize = HalfWordAccess;
20965let mayStore = 1;
20966let Uses = [CS];
20967let Constraints = "$Rx32 = $Rx32in";
20968}
20969def S2_storerf_pi : HInst<
20970(outs IntRegs:$Rx32),
20971(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20972"memh($Rx32++#$Ii) = $Rt32.h",
20973tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
20974let Inst{2-0} = 0b000;
20975let Inst{7-7} = 0b0;
20976let Inst{13-13} = 0b0;
20977let Inst{31-21} = 0b10101011011;
20978let addrMode = PostInc;
20979let accessSize = HalfWordAccess;
20980let mayStore = 1;
20981let CextOpcode = "S2_storerf";
20982let BaseOpcode = "S2_storerf_pi";
20983let isPredicable = 1;
20984let Constraints = "$Rx32 = $Rx32in";
20985}
20986def S2_storerf_pr : HInst<
20987(outs IntRegs:$Rx32),
20988(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20989"memh($Rx32++$Mu2) = $Rt32.h",
20990tc_da97ee82, TypeST>, Enc_d5c73f {
20991let Inst{7-0} = 0b00000000;
20992let Inst{31-21} = 0b10101101011;
20993let addrMode = PostInc;
20994let accessSize = HalfWordAccess;
20995let mayStore = 1;
20996let Constraints = "$Rx32 = $Rx32in";
20997}
20998def S2_storerf_zomap : HInst<
20999(outs),
21000(ins IntRegs:$Rs32, IntRegs:$Rt32),
21001"memh($Rs32) = $Rt32.h",
21002tc_30b9bb4a, TypeMAPPING> {
21003let isPseudo = 1;
21004let isCodeGenOnly = 1;
21005}
21006def S2_storerfgp : HInst<
21007(outs),
21008(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21009"memh(gp+#$Ii) = $Rt32.h",
21010tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21011let Inst{24-21} = 0b0011;
21012let Inst{31-27} = 0b01001;
21013let accessSize = HalfWordAccess;
21014let mayStore = 1;
21015let Uses = [GP];
21016let BaseOpcode = "S2_storerfabs";
21017let isPredicable = 1;
21018let opExtendable = 0;
21019let isExtentSigned = 0;
21020let opExtentBits = 17;
21021let opExtentAlign = 1;
21022}
21023def S2_storerh_io : HInst<
21024(outs),
21025(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21026"memh($Rs32+#$Ii) = $Rt32",
21027tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21028let Inst{24-21} = 0b1010;
21029let Inst{31-27} = 0b10100;
21030let addrMode = BaseImmOffset;
21031let accessSize = HalfWordAccess;
21032let mayStore = 1;
21033let CextOpcode = "S2_storerh";
21034let InputType = "imm";
21035let BaseOpcode = "S2_storerh_io";
21036let isPredicable = 1;
21037let isNVStorable = 1;
21038let isExtendable = 1;
21039let opExtendable = 1;
21040let isExtentSigned = 1;
21041let opExtentBits = 12;
21042let opExtentAlign = 1;
21043}
21044def S2_storerh_pbr : HInst<
21045(outs IntRegs:$Rx32),
21046(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21047"memh($Rx32++$Mu2:brev) = $Rt32",
21048tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel {
21049let Inst{7-0} = 0b00000000;
21050let Inst{31-21} = 0b10101111010;
21051let addrMode = PostInc;
21052let accessSize = HalfWordAccess;
21053let mayStore = 1;
21054let BaseOpcode = "S2_storerh_pbr";
21055let isNVStorable = 1;
21056let Constraints = "$Rx32 = $Rx32in";
21057}
21058def S2_storerh_pci : HInst<
21059(outs IntRegs:$Rx32),
21060(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21061"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21062tc_e86aa961, TypeST>, Enc_935d9b, AddrModeRel {
21063let Inst{2-0} = 0b000;
21064let Inst{7-7} = 0b0;
21065let Inst{31-21} = 0b10101001010;
21066let addrMode = PostInc;
21067let accessSize = HalfWordAccess;
21068let mayStore = 1;
21069let Uses = [CS];
21070let BaseOpcode = "S2_storerh_pci";
21071let isNVStorable = 1;
21072let Constraints = "$Rx32 = $Rx32in";
21073}
21074def S2_storerh_pcr : HInst<
21075(outs IntRegs:$Rx32),
21076(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21077"memh($Rx32++I:circ($Mu2)) = $Rt32",
21078tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel {
21079let Inst{7-0} = 0b00000010;
21080let Inst{31-21} = 0b10101001010;
21081let addrMode = PostInc;
21082let accessSize = HalfWordAccess;
21083let mayStore = 1;
21084let Uses = [CS];
21085let BaseOpcode = "S2_storerh_pcr";
21086let isNVStorable = 1;
21087let Constraints = "$Rx32 = $Rx32in";
21088}
21089def S2_storerh_pi : HInst<
21090(outs IntRegs:$Rx32),
21091(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21092"memh($Rx32++#$Ii) = $Rt32",
21093tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21094let Inst{2-0} = 0b000;
21095let Inst{7-7} = 0b0;
21096let Inst{13-13} = 0b0;
21097let Inst{31-21} = 0b10101011010;
21098let addrMode = PostInc;
21099let accessSize = HalfWordAccess;
21100let mayStore = 1;
21101let CextOpcode = "S2_storerh";
21102let BaseOpcode = "S2_storerh_pi";
21103let isPredicable = 1;
21104let isNVStorable = 1;
21105let Constraints = "$Rx32 = $Rx32in";
21106}
21107def S2_storerh_pr : HInst<
21108(outs IntRegs:$Rx32),
21109(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21110"memh($Rx32++$Mu2) = $Rt32",
21111tc_da97ee82, TypeST>, Enc_d5c73f {
21112let Inst{7-0} = 0b00000000;
21113let Inst{31-21} = 0b10101101010;
21114let addrMode = PostInc;
21115let accessSize = HalfWordAccess;
21116let mayStore = 1;
21117let isNVStorable = 1;
21118let Constraints = "$Rx32 = $Rx32in";
21119}
21120def S2_storerh_zomap : HInst<
21121(outs),
21122(ins IntRegs:$Rs32, IntRegs:$Rt32),
21123"memh($Rs32) = $Rt32",
21124tc_30b9bb4a, TypeMAPPING> {
21125let isPseudo = 1;
21126let isCodeGenOnly = 1;
21127}
21128def S2_storerhgp : HInst<
21129(outs),
21130(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21131"memh(gp+#$Ii) = $Rt32",
21132tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21133let Inst{24-21} = 0b0010;
21134let Inst{31-27} = 0b01001;
21135let accessSize = HalfWordAccess;
21136let mayStore = 1;
21137let Uses = [GP];
21138let BaseOpcode = "S2_storerhabs";
21139let isPredicable = 1;
21140let isNVStorable = 1;
21141let opExtendable = 0;
21142let isExtentSigned = 0;
21143let opExtentBits = 17;
21144let opExtentAlign = 1;
21145}
21146def S2_storerhnew_io : HInst<
21147(outs),
21148(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
21149"memh($Rs32+#$Ii) = $Nt8.new",
21150tc_be9602ff, TypeST>, Enc_0d8870, AddrModeRel {
21151let Inst{12-11} = 0b01;
21152let Inst{24-21} = 0b1101;
21153let Inst{31-27} = 0b10100;
21154let addrMode = BaseImmOffset;
21155let accessSize = HalfWordAccess;
21156let isNVStore = 1;
21157let isNewValue = 1;
21158let isRestrictNoSlot1Store = 1;
21159let mayStore = 1;
21160let CextOpcode = "S2_storerh";
21161let InputType = "imm";
21162let BaseOpcode = "S2_storerh_io";
21163let isPredicable = 1;
21164let isExtendable = 1;
21165let opExtendable = 1;
21166let isExtentSigned = 1;
21167let opExtentBits = 12;
21168let opExtentAlign = 1;
21169let opNewValue = 2;
21170}
21171def S2_storerhnew_pbr : HInst<
21172(outs IntRegs:$Rx32),
21173(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21174"memh($Rx32++$Mu2:brev) = $Nt8.new",
21175tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel {
21176let Inst{7-0} = 0b00000000;
21177let Inst{12-11} = 0b01;
21178let Inst{31-21} = 0b10101111101;
21179let addrMode = PostInc;
21180let accessSize = HalfWordAccess;
21181let isNVStore = 1;
21182let isNewValue = 1;
21183let isRestrictNoSlot1Store = 1;
21184let mayStore = 1;
21185let BaseOpcode = "S2_storerh_pbr";
21186let opNewValue = 3;
21187let Constraints = "$Rx32 = $Rx32in";
21188}
21189def S2_storerhnew_pci : HInst<
21190(outs IntRegs:$Rx32),
21191(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21192"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21193tc_d5c0729a, TypeST>, Enc_91b9fe, AddrModeRel {
21194let Inst{2-0} = 0b000;
21195let Inst{7-7} = 0b0;
21196let Inst{12-11} = 0b01;
21197let Inst{31-21} = 0b10101001101;
21198let addrMode = PostInc;
21199let accessSize = HalfWordAccess;
21200let isNVStore = 1;
21201let isNewValue = 1;
21202let isRestrictNoSlot1Store = 1;
21203let mayStore = 1;
21204let Uses = [CS];
21205let BaseOpcode = "S2_storerh_pci";
21206let opNewValue = 4;
21207let Constraints = "$Rx32 = $Rx32in";
21208}
21209def S2_storerhnew_pcr : HInst<
21210(outs IntRegs:$Rx32),
21211(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21212"memh($Rx32++I:circ($Mu2)) = $Nt8.new",
21213tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel {
21214let Inst{7-0} = 0b00000010;
21215let Inst{12-11} = 0b01;
21216let Inst{31-21} = 0b10101001101;
21217let addrMode = PostInc;
21218let accessSize = HalfWordAccess;
21219let isNVStore = 1;
21220let isNewValue = 1;
21221let isRestrictNoSlot1Store = 1;
21222let mayStore = 1;
21223let Uses = [CS];
21224let BaseOpcode = "S2_storerh_pcr";
21225let opNewValue = 3;
21226let Constraints = "$Rx32 = $Rx32in";
21227}
21228def S2_storerhnew_pi : HInst<
21229(outs IntRegs:$Rx32),
21230(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
21231"memh($Rx32++#$Ii) = $Nt8.new",
21232tc_c79a189f, TypeST>, Enc_e26546, AddrModeRel {
21233let Inst{2-0} = 0b000;
21234let Inst{7-7} = 0b0;
21235let Inst{13-11} = 0b001;
21236let Inst{31-21} = 0b10101011101;
21237let addrMode = PostInc;
21238let accessSize = HalfWordAccess;
21239let isNVStore = 1;
21240let isNewValue = 1;
21241let isRestrictNoSlot1Store = 1;
21242let mayStore = 1;
21243let BaseOpcode = "S2_storerh_pi";
21244let isNVStorable = 1;
21245let isPredicable = 1;
21246let opNewValue = 3;
21247let Constraints = "$Rx32 = $Rx32in";
21248}
21249def S2_storerhnew_pr : HInst<
21250(outs IntRegs:$Rx32),
21251(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21252"memh($Rx32++$Mu2) = $Nt8.new",
21253tc_c79a189f, TypeST>, Enc_8dbe85 {
21254let Inst{7-0} = 0b00000000;
21255let Inst{12-11} = 0b01;
21256let Inst{31-21} = 0b10101101101;
21257let addrMode = PostInc;
21258let accessSize = HalfWordAccess;
21259let isNVStore = 1;
21260let isNewValue = 1;
21261let isRestrictNoSlot1Store = 1;
21262let mayStore = 1;
21263let opNewValue = 3;
21264let Constraints = "$Rx32 = $Rx32in";
21265}
21266def S2_storerhnew_zomap : HInst<
21267(outs),
21268(ins IntRegs:$Rs32, IntRegs:$Nt8),
21269"memh($Rs32) = $Nt8.new",
21270tc_be9602ff, TypeMAPPING> {
21271let isPseudo = 1;
21272let isCodeGenOnly = 1;
21273let opNewValue = 1;
21274}
21275def S2_storerhnewgp : HInst<
21276(outs),
21277(ins u31_1Imm:$Ii, IntRegs:$Nt8),
21278"memh(gp+#$Ii) = $Nt8.new",
21279tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
21280let Inst{12-11} = 0b01;
21281let Inst{24-21} = 0b0101;
21282let Inst{31-27} = 0b01001;
21283let accessSize = HalfWordAccess;
21284let isNVStore = 1;
21285let isNewValue = 1;
21286let isRestrictNoSlot1Store = 1;
21287let mayStore = 1;
21288let Uses = [GP];
21289let BaseOpcode = "S2_storerhabs";
21290let isPredicable = 1;
21291let opExtendable = 0;
21292let isExtentSigned = 0;
21293let opExtentBits = 17;
21294let opExtentAlign = 1;
21295let opNewValue = 1;
21296}
21297def S2_storeri_io : HInst<
21298(outs),
21299(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
21300"memw($Rs32+#$Ii) = $Rt32",
21301tc_30b9bb4a, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
21302let Inst{24-21} = 0b1100;
21303let Inst{31-27} = 0b10100;
21304let addrMode = BaseImmOffset;
21305let accessSize = WordAccess;
21306let mayStore = 1;
21307let CextOpcode = "S2_storeri";
21308let InputType = "imm";
21309let BaseOpcode = "S2_storeri_io";
21310let isPredicable = 1;
21311let isNVStorable = 1;
21312let isExtendable = 1;
21313let opExtendable = 1;
21314let isExtentSigned = 1;
21315let opExtentBits = 13;
21316let opExtentAlign = 2;
21317}
21318def S2_storeri_pbr : HInst<
21319(outs IntRegs:$Rx32),
21320(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21321"memw($Rx32++$Mu2:brev) = $Rt32",
21322tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel {
21323let Inst{7-0} = 0b00000000;
21324let Inst{31-21} = 0b10101111100;
21325let addrMode = PostInc;
21326let accessSize = WordAccess;
21327let mayStore = 1;
21328let BaseOpcode = "S2_storeri_pbr";
21329let isNVStorable = 1;
21330let Constraints = "$Rx32 = $Rx32in";
21331}
21332def S2_storeri_pci : HInst<
21333(outs IntRegs:$Rx32),
21334(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21335"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21336tc_e86aa961, TypeST>, Enc_79b8c8, AddrModeRel {
21337let Inst{2-0} = 0b000;
21338let Inst{7-7} = 0b0;
21339let Inst{31-21} = 0b10101001100;
21340let addrMode = PostInc;
21341let accessSize = WordAccess;
21342let mayStore = 1;
21343let Uses = [CS];
21344let BaseOpcode = "S2_storeri_pci";
21345let isNVStorable = 1;
21346let Constraints = "$Rx32 = $Rx32in";
21347}
21348def S2_storeri_pcr : HInst<
21349(outs IntRegs:$Rx32),
21350(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21351"memw($Rx32++I:circ($Mu2)) = $Rt32",
21352tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel {
21353let Inst{7-0} = 0b00000010;
21354let Inst{31-21} = 0b10101001100;
21355let addrMode = PostInc;
21356let accessSize = WordAccess;
21357let mayStore = 1;
21358let Uses = [CS];
21359let BaseOpcode = "S2_storeri_pcr";
21360let isNVStorable = 1;
21361let Constraints = "$Rx32 = $Rx32in";
21362}
21363def S2_storeri_pi : HInst<
21364(outs IntRegs:$Rx32),
21365(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
21366"memw($Rx32++#$Ii) = $Rt32",
21367tc_da97ee82, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
21368let Inst{2-0} = 0b000;
21369let Inst{7-7} = 0b0;
21370let Inst{13-13} = 0b0;
21371let Inst{31-21} = 0b10101011100;
21372let addrMode = PostInc;
21373let accessSize = WordAccess;
21374let mayStore = 1;
21375let CextOpcode = "S2_storeri";
21376let BaseOpcode = "S2_storeri_pi";
21377let isPredicable = 1;
21378let isNVStorable = 1;
21379let Constraints = "$Rx32 = $Rx32in";
21380}
21381def S2_storeri_pr : HInst<
21382(outs IntRegs:$Rx32),
21383(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21384"memw($Rx32++$Mu2) = $Rt32",
21385tc_da97ee82, TypeST>, Enc_d5c73f {
21386let Inst{7-0} = 0b00000000;
21387let Inst{31-21} = 0b10101101100;
21388let addrMode = PostInc;
21389let accessSize = WordAccess;
21390let mayStore = 1;
21391let isNVStorable = 1;
21392let Constraints = "$Rx32 = $Rx32in";
21393}
21394def S2_storeri_zomap : HInst<
21395(outs),
21396(ins IntRegs:$Rs32, IntRegs:$Rt32),
21397"memw($Rs32) = $Rt32",
21398tc_30b9bb4a, TypeMAPPING> {
21399let isPseudo = 1;
21400let isCodeGenOnly = 1;
21401}
21402def S2_storerigp : HInst<
21403(outs),
21404(ins u30_2Imm:$Ii, IntRegs:$Rt32),
21405"memw(gp+#$Ii) = $Rt32",
21406tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel {
21407let Inst{24-21} = 0b0100;
21408let Inst{31-27} = 0b01001;
21409let accessSize = WordAccess;
21410let mayStore = 1;
21411let Uses = [GP];
21412let BaseOpcode = "S2_storeriabs";
21413let isPredicable = 1;
21414let isNVStorable = 1;
21415let opExtendable = 0;
21416let isExtentSigned = 0;
21417let opExtentBits = 18;
21418let opExtentAlign = 2;
21419}
21420def S2_storerinew_io : HInst<
21421(outs),
21422(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
21423"memw($Rs32+#$Ii) = $Nt8.new",
21424tc_be9602ff, TypeST>, Enc_690862, AddrModeRel {
21425let Inst{12-11} = 0b10;
21426let Inst{24-21} = 0b1101;
21427let Inst{31-27} = 0b10100;
21428let addrMode = BaseImmOffset;
21429let accessSize = WordAccess;
21430let isNVStore = 1;
21431let isNewValue = 1;
21432let isRestrictNoSlot1Store = 1;
21433let mayStore = 1;
21434let CextOpcode = "S2_storeri";
21435let InputType = "imm";
21436let BaseOpcode = "S2_storeri_io";
21437let isPredicable = 1;
21438let isExtendable = 1;
21439let opExtendable = 1;
21440let isExtentSigned = 1;
21441let opExtentBits = 13;
21442let opExtentAlign = 2;
21443let opNewValue = 2;
21444}
21445def S2_storerinew_pbr : HInst<
21446(outs IntRegs:$Rx32),
21447(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21448"memw($Rx32++$Mu2:brev) = $Nt8.new",
21449tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel {
21450let Inst{7-0} = 0b00000000;
21451let Inst{12-11} = 0b10;
21452let Inst{31-21} = 0b10101111101;
21453let addrMode = PostInc;
21454let accessSize = WordAccess;
21455let isNVStore = 1;
21456let isNewValue = 1;
21457let isRestrictNoSlot1Store = 1;
21458let mayStore = 1;
21459let BaseOpcode = "S2_storeri_pbr";
21460let opNewValue = 3;
21461let Constraints = "$Rx32 = $Rx32in";
21462}
21463def S2_storerinew_pci : HInst<
21464(outs IntRegs:$Rx32),
21465(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21466"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21467tc_d5c0729a, TypeST>, Enc_3f97c8, AddrModeRel {
21468let Inst{2-0} = 0b000;
21469let Inst{7-7} = 0b0;
21470let Inst{12-11} = 0b10;
21471let Inst{31-21} = 0b10101001101;
21472let addrMode = PostInc;
21473let accessSize = WordAccess;
21474let isNVStore = 1;
21475let isNewValue = 1;
21476let isRestrictNoSlot1Store = 1;
21477let mayStore = 1;
21478let Uses = [CS];
21479let BaseOpcode = "S2_storeri_pci";
21480let opNewValue = 4;
21481let Constraints = "$Rx32 = $Rx32in";
21482}
21483def S2_storerinew_pcr : HInst<
21484(outs IntRegs:$Rx32),
21485(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21486"memw($Rx32++I:circ($Mu2)) = $Nt8.new",
21487tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel {
21488let Inst{7-0} = 0b00000010;
21489let Inst{12-11} = 0b10;
21490let Inst{31-21} = 0b10101001101;
21491let addrMode = PostInc;
21492let accessSize = WordAccess;
21493let isNVStore = 1;
21494let isNewValue = 1;
21495let isRestrictNoSlot1Store = 1;
21496let mayStore = 1;
21497let Uses = [CS];
21498let BaseOpcode = "S2_storeri_pcr";
21499let opNewValue = 3;
21500let Constraints = "$Rx32 = $Rx32in";
21501}
21502def S2_storerinew_pi : HInst<
21503(outs IntRegs:$Rx32),
21504(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
21505"memw($Rx32++#$Ii) = $Nt8.new",
21506tc_c79a189f, TypeST>, Enc_223005, AddrModeRel {
21507let Inst{2-0} = 0b000;
21508let Inst{7-7} = 0b0;
21509let Inst{13-11} = 0b010;
21510let Inst{31-21} = 0b10101011101;
21511let addrMode = PostInc;
21512let accessSize = WordAccess;
21513let isNVStore = 1;
21514let isNewValue = 1;
21515let isRestrictNoSlot1Store = 1;
21516let mayStore = 1;
21517let BaseOpcode = "S2_storeri_pi";
21518let isPredicable = 1;
21519let opNewValue = 3;
21520let Constraints = "$Rx32 = $Rx32in";
21521}
21522def S2_storerinew_pr : HInst<
21523(outs IntRegs:$Rx32),
21524(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21525"memw($Rx32++$Mu2) = $Nt8.new",
21526tc_c79a189f, TypeST>, Enc_8dbe85 {
21527let Inst{7-0} = 0b00000000;
21528let Inst{12-11} = 0b10;
21529let Inst{31-21} = 0b10101101101;
21530let addrMode = PostInc;
21531let accessSize = WordAccess;
21532let isNVStore = 1;
21533let isNewValue = 1;
21534let isRestrictNoSlot1Store = 1;
21535let mayStore = 1;
21536let opNewValue = 3;
21537let Constraints = "$Rx32 = $Rx32in";
21538}
21539def S2_storerinew_zomap : HInst<
21540(outs),
21541(ins IntRegs:$Rs32, IntRegs:$Nt8),
21542"memw($Rs32) = $Nt8.new",
21543tc_be9602ff, TypeMAPPING> {
21544let isPseudo = 1;
21545let isCodeGenOnly = 1;
21546let opNewValue = 1;
21547}
21548def S2_storerinewgp : HInst<
21549(outs),
21550(ins u30_2Imm:$Ii, IntRegs:$Nt8),
21551"memw(gp+#$Ii) = $Nt8.new",
21552tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
21553let Inst{12-11} = 0b10;
21554let Inst{24-21} = 0b0101;
21555let Inst{31-27} = 0b01001;
21556let accessSize = WordAccess;
21557let isNVStore = 1;
21558let isNewValue = 1;
21559let isRestrictNoSlot1Store = 1;
21560let mayStore = 1;
21561let Uses = [GP];
21562let BaseOpcode = "S2_storeriabs";
21563let isPredicable = 1;
21564let opExtendable = 0;
21565let isExtentSigned = 0;
21566let opExtentBits = 18;
21567let opExtentAlign = 2;
21568let opNewValue = 1;
21569}
21570def S2_storew_locked : HInst<
21571(outs PredRegs:$Pd4),
21572(ins IntRegs:$Rs32, IntRegs:$Rt32),
21573"memw_locked($Rs32,$Pd4) = $Rt32",
21574tc_5abb5e3f, TypeST>, Enc_c2b48e {
21575let Inst{7-2} = 0b000000;
21576let Inst{13-13} = 0b0;
21577let Inst{31-21} = 0b10100000101;
21578let accessSize = WordAccess;
21579let isPredicateLate = 1;
21580let isSoloAX = 1;
21581let mayStore = 1;
21582}
21583def S2_svsathb : HInst<
21584(outs IntRegs:$Rd32),
21585(ins IntRegs:$Rs32),
21586"$Rd32 = vsathb($Rs32)",
21587tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
21588let Inst{13-5} = 0b000000000;
21589let Inst{31-21} = 0b10001100100;
21590let hasNewValue = 1;
21591let opNewValue = 0;
21592let Defs = [USR_OVF];
21593}
21594def S2_svsathub : HInst<
21595(outs IntRegs:$Rd32),
21596(ins IntRegs:$Rs32),
21597"$Rd32 = vsathub($Rs32)",
21598tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
21599let Inst{13-5} = 0b000000010;
21600let Inst{31-21} = 0b10001100100;
21601let hasNewValue = 1;
21602let opNewValue = 0;
21603let Defs = [USR_OVF];
21604}
21605def S2_tableidxb : HInst<
21606(outs IntRegs:$Rx32),
21607(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21608"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
21609tc_bfec0f01, TypeS_2op>, Enc_cd82bc {
21610let Inst{31-22} = 0b1000011100;
21611let hasNewValue = 1;
21612let opNewValue = 0;
21613let prefersSlot3 = 1;
21614let Constraints = "$Rx32 = $Rx32in";
21615}
21616def S2_tableidxb_goodsyntax : HInst<
21617(outs IntRegs:$Rx32),
21618(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21619"$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
21620tc_bfec0f01, TypeS_2op> {
21621let hasNewValue = 1;
21622let opNewValue = 0;
21623let isPseudo = 1;
21624let isCodeGenOnly = 1;
21625let Constraints = "$Rx32 = $Rx32in";
21626}
21627def S2_tableidxd : HInst<
21628(outs IntRegs:$Rx32),
21629(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21630"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
21631tc_bfec0f01, TypeS_2op>, Enc_cd82bc {
21632let Inst{31-22} = 0b1000011111;
21633let hasNewValue = 1;
21634let opNewValue = 0;
21635let prefersSlot3 = 1;
21636let Constraints = "$Rx32 = $Rx32in";
21637}
21638def S2_tableidxd_goodsyntax : HInst<
21639(outs IntRegs:$Rx32),
21640(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21641"$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
21642tc_bfec0f01, TypeS_2op> {
21643let hasNewValue = 1;
21644let opNewValue = 0;
21645let isPseudo = 1;
21646let Constraints = "$Rx32 = $Rx32in";
21647}
21648def S2_tableidxh : HInst<
21649(outs IntRegs:$Rx32),
21650(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21651"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
21652tc_bfec0f01, TypeS_2op>, Enc_cd82bc {
21653let Inst{31-22} = 0b1000011101;
21654let hasNewValue = 1;
21655let opNewValue = 0;
21656let prefersSlot3 = 1;
21657let Constraints = "$Rx32 = $Rx32in";
21658}
21659def S2_tableidxh_goodsyntax : HInst<
21660(outs IntRegs:$Rx32),
21661(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21662"$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
21663tc_bfec0f01, TypeS_2op> {
21664let hasNewValue = 1;
21665let opNewValue = 0;
21666let isPseudo = 1;
21667let Constraints = "$Rx32 = $Rx32in";
21668}
21669def S2_tableidxw : HInst<
21670(outs IntRegs:$Rx32),
21671(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
21672"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
21673tc_bfec0f01, TypeS_2op>, Enc_cd82bc {
21674let Inst{31-22} = 0b1000011110;
21675let hasNewValue = 1;
21676let opNewValue = 0;
21677let prefersSlot3 = 1;
21678let Constraints = "$Rx32 = $Rx32in";
21679}
21680def S2_tableidxw_goodsyntax : HInst<
21681(outs IntRegs:$Rx32),
21682(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
21683"$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
21684tc_bfec0f01, TypeS_2op> {
21685let hasNewValue = 1;
21686let opNewValue = 0;
21687let isPseudo = 1;
21688let Constraints = "$Rx32 = $Rx32in";
21689}
21690def S2_togglebit_i : HInst<
21691(outs IntRegs:$Rd32),
21692(ins IntRegs:$Rs32, u5_0Imm:$Ii),
21693"$Rd32 = togglebit($Rs32,#$Ii)",
21694tc_946df596, TypeS_2op>, Enc_a05677 {
21695let Inst{7-5} = 0b010;
21696let Inst{13-13} = 0b0;
21697let Inst{31-21} = 0b10001100110;
21698let hasNewValue = 1;
21699let opNewValue = 0;
21700}
21701def S2_togglebit_r : HInst<
21702(outs IntRegs:$Rd32),
21703(ins IntRegs:$Rs32, IntRegs:$Rt32),
21704"$Rd32 = togglebit($Rs32,$Rt32)",
21705tc_946df596, TypeS_3op>, Enc_5ab2be {
21706let Inst{7-5} = 0b100;
21707let Inst{13-13} = 0b0;
21708let Inst{31-21} = 0b11000110100;
21709let hasNewValue = 1;
21710let opNewValue = 0;
21711}
21712def S2_tstbit_i : HInst<
21713(outs PredRegs:$Pd4),
21714(ins IntRegs:$Rs32, u5_0Imm:$Ii),
21715"$Pd4 = tstbit($Rs32,#$Ii)",
21716tc_643b4717, TypeS_2op>, Enc_83ee64 {
21717let Inst{7-2} = 0b000000;
21718let Inst{13-13} = 0b0;
21719let Inst{31-21} = 0b10000101000;
21720}
21721def S2_tstbit_r : HInst<
21722(outs PredRegs:$Pd4),
21723(ins IntRegs:$Rs32, IntRegs:$Rt32),
21724"$Pd4 = tstbit($Rs32,$Rt32)",
21725tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
21726let Inst{7-2} = 0b000000;
21727let Inst{13-13} = 0b0;
21728let Inst{31-21} = 0b11000111000;
21729}
21730def S2_valignib : HInst<
21731(outs DoubleRegs:$Rdd32),
21732(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
21733"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
21734tc_b4b5c03a, TypeS_3op>, Enc_729ff7 {
21735let Inst{13-13} = 0b0;
21736let Inst{31-21} = 0b11000000000;
21737}
21738def S2_valignrb : HInst<
21739(outs DoubleRegs:$Rdd32),
21740(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
21741"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
21742tc_b4b5c03a, TypeS_3op>, Enc_8c6530 {
21743let Inst{7-7} = 0b0;
21744let Inst{13-13} = 0b0;
21745let Inst{31-21} = 0b11000010000;
21746}
21747def S2_vcnegh : HInst<
21748(outs DoubleRegs:$Rdd32),
21749(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
21750"$Rdd32 = vcnegh($Rss32,$Rt32)",
21751tc_779080bf, TypeS_3op>, Enc_927852 {
21752let Inst{7-5} = 0b010;
21753let Inst{13-13} = 0b0;
21754let Inst{31-21} = 0b11000011110;
21755let prefersSlot3 = 1;
21756let Defs = [USR_OVF];
21757}
21758def S2_vcrotate : HInst<
21759(outs DoubleRegs:$Rdd32),
21760(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
21761"$Rdd32 = vcrotate($Rss32,$Rt32)",
21762tc_002cb246, TypeS_3op>, Enc_927852 {
21763let Inst{7-5} = 0b000;
21764let Inst{13-13} = 0b0;
21765let Inst{31-21} = 0b11000011110;
21766let prefersSlot3 = 1;
21767let Defs = [USR_OVF];
21768}
21769def S2_vrcnegh : HInst<
21770(outs DoubleRegs:$Rxx32),
21771(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
21772"$Rxx32 += vrcnegh($Rss32,$Rt32)",
21773tc_d773585a, TypeS_3op>, Enc_1aa186 {
21774let Inst{7-5} = 0b111;
21775let Inst{13-13} = 0b1;
21776let Inst{31-21} = 0b11001011001;
21777let prefersSlot3 = 1;
21778let Constraints = "$Rxx32 = $Rxx32in";
21779}
21780def S2_vrndpackwh : HInst<
21781(outs IntRegs:$Rd32),
21782(ins DoubleRegs:$Rss32),
21783"$Rd32 = vrndwh($Rss32)",
21784tc_14b5c689, TypeS_2op>, Enc_90cd8b {
21785let Inst{13-5} = 0b000000100;
21786let Inst{31-21} = 0b10001000100;
21787let hasNewValue = 1;
21788let opNewValue = 0;
21789let prefersSlot3 = 1;
21790}
21791def S2_vrndpackwhs : HInst<
21792(outs IntRegs:$Rd32),
21793(ins DoubleRegs:$Rss32),
21794"$Rd32 = vrndwh($Rss32):sat",
21795tc_cf8126ae, TypeS_2op>, Enc_90cd8b {
21796let Inst{13-5} = 0b000000110;
21797let Inst{31-21} = 0b10001000100;
21798let hasNewValue = 1;
21799let opNewValue = 0;
21800let prefersSlot3 = 1;
21801let Defs = [USR_OVF];
21802}
21803def S2_vsathb : HInst<
21804(outs IntRegs:$Rd32),
21805(ins DoubleRegs:$Rss32),
21806"$Rd32 = vsathb($Rss32)",
21807tc_0ae0825c, TypeS_2op>, Enc_90cd8b {
21808let Inst{13-5} = 0b000000110;
21809let Inst{31-21} = 0b10001000000;
21810let hasNewValue = 1;
21811let opNewValue = 0;
21812let Defs = [USR_OVF];
21813}
21814def S2_vsathb_nopack : HInst<
21815(outs DoubleRegs:$Rdd32),
21816(ins DoubleRegs:$Rss32),
21817"$Rdd32 = vsathb($Rss32)",
21818tc_0ae0825c, TypeS_2op>, Enc_b9c5fb {
21819let Inst{13-5} = 0b000000111;
21820let Inst{31-21} = 0b10000000000;
21821let Defs = [USR_OVF];
21822}
21823def S2_vsathub : HInst<
21824(outs IntRegs:$Rd32),
21825(ins DoubleRegs:$Rss32),
21826"$Rd32 = vsathub($Rss32)",
21827tc_0ae0825c, TypeS_2op>, Enc_90cd8b {
21828let Inst{13-5} = 0b000000000;
21829let Inst{31-21} = 0b10001000000;
21830let hasNewValue = 1;
21831let opNewValue = 0;
21832let Defs = [USR_OVF];
21833}
21834def S2_vsathub_nopack : HInst<
21835(outs DoubleRegs:$Rdd32),
21836(ins DoubleRegs:$Rss32),
21837"$Rdd32 = vsathub($Rss32)",
21838tc_0ae0825c, TypeS_2op>, Enc_b9c5fb {
21839let Inst{13-5} = 0b000000100;
21840let Inst{31-21} = 0b10000000000;
21841let Defs = [USR_OVF];
21842}
21843def S2_vsatwh : HInst<
21844(outs IntRegs:$Rd32),
21845(ins DoubleRegs:$Rss32),
21846"$Rd32 = vsatwh($Rss32)",
21847tc_0ae0825c, TypeS_2op>, Enc_90cd8b {
21848let Inst{13-5} = 0b000000010;
21849let Inst{31-21} = 0b10001000000;
21850let hasNewValue = 1;
21851let opNewValue = 0;
21852let Defs = [USR_OVF];
21853}
21854def S2_vsatwh_nopack : HInst<
21855(outs DoubleRegs:$Rdd32),
21856(ins DoubleRegs:$Rss32),
21857"$Rdd32 = vsatwh($Rss32)",
21858tc_0ae0825c, TypeS_2op>, Enc_b9c5fb {
21859let Inst{13-5} = 0b000000110;
21860let Inst{31-21} = 0b10000000000;
21861let Defs = [USR_OVF];
21862}
21863def S2_vsatwuh : HInst<
21864(outs IntRegs:$Rd32),
21865(ins DoubleRegs:$Rss32),
21866"$Rd32 = vsatwuh($Rss32)",
21867tc_0ae0825c, TypeS_2op>, Enc_90cd8b {
21868let Inst{13-5} = 0b000000100;
21869let Inst{31-21} = 0b10001000000;
21870let hasNewValue = 1;
21871let opNewValue = 0;
21872let Defs = [USR_OVF];
21873}
21874def S2_vsatwuh_nopack : HInst<
21875(outs DoubleRegs:$Rdd32),
21876(ins DoubleRegs:$Rss32),
21877"$Rdd32 = vsatwuh($Rss32)",
21878tc_0ae0825c, TypeS_2op>, Enc_b9c5fb {
21879let Inst{13-5} = 0b000000101;
21880let Inst{31-21} = 0b10000000000;
21881let Defs = [USR_OVF];
21882}
21883def S2_vsplatrb : HInst<
21884(outs IntRegs:$Rd32),
21885(ins IntRegs:$Rs32),
21886"$Rd32 = vsplatb($Rs32)",
21887tc_0ae0825c, TypeS_2op>, Enc_5e2823 {
21888let Inst{13-5} = 0b000000111;
21889let Inst{31-21} = 0b10001100010;
21890let hasNewValue = 1;
21891let opNewValue = 0;
21892let isReMaterializable = 1;
21893let isAsCheapAsAMove = 1;
21894}
21895def S2_vsplatrh : HInst<
21896(outs DoubleRegs:$Rdd32),
21897(ins IntRegs:$Rs32),
21898"$Rdd32 = vsplath($Rs32)",
21899tc_0ae0825c, TypeS_2op>, Enc_3a3d62 {
21900let Inst{13-5} = 0b000000010;
21901let Inst{31-21} = 0b10000100010;
21902let isReMaterializable = 1;
21903let isAsCheapAsAMove = 1;
21904}
21905def S2_vspliceib : HInst<
21906(outs DoubleRegs:$Rdd32),
21907(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
21908"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
21909tc_b4b5c03a, TypeS_3op>, Enc_d50cd3 {
21910let Inst{13-13} = 0b0;
21911let Inst{31-21} = 0b11000000100;
21912}
21913def S2_vsplicerb : HInst<
21914(outs DoubleRegs:$Rdd32),
21915(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
21916"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
21917tc_b4b5c03a, TypeS_3op>, Enc_dbd70c {
21918let Inst{7-7} = 0b0;
21919let Inst{13-13} = 0b0;
21920let Inst{31-21} = 0b11000010100;
21921}
21922def S2_vsxtbh : HInst<
21923(outs DoubleRegs:$Rdd32),
21924(ins IntRegs:$Rs32),
21925"$Rdd32 = vsxtbh($Rs32)",
21926tc_0ae0825c, TypeS_2op>, Enc_3a3d62 {
21927let Inst{13-5} = 0b000000000;
21928let Inst{31-21} = 0b10000100000;
21929let isReMaterializable = 1;
21930let isAsCheapAsAMove = 1;
21931}
21932def S2_vsxthw : HInst<
21933(outs DoubleRegs:$Rdd32),
21934(ins IntRegs:$Rs32),
21935"$Rdd32 = vsxthw($Rs32)",
21936tc_0ae0825c, TypeS_2op>, Enc_3a3d62 {
21937let Inst{13-5} = 0b000000100;
21938let Inst{31-21} = 0b10000100000;
21939let isReMaterializable = 1;
21940let isAsCheapAsAMove = 1;
21941}
21942def S2_vtrunehb : HInst<
21943(outs IntRegs:$Rd32),
21944(ins DoubleRegs:$Rss32),
21945"$Rd32 = vtrunehb($Rss32)",
21946tc_0ae0825c, TypeS_2op>, Enc_90cd8b {
21947let Inst{13-5} = 0b000000010;
21948let Inst{31-21} = 0b10001000100;
21949let hasNewValue = 1;
21950let opNewValue = 0;
21951}
21952def S2_vtrunewh : HInst<
21953(outs DoubleRegs:$Rdd32),
21954(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
21955"$Rdd32 = vtrunewh($Rss32,$Rtt32)",
21956tc_946df596, TypeS_3op>, Enc_a56825 {
21957let Inst{7-5} = 0b010;
21958let Inst{13-13} = 0b0;
21959let Inst{31-21} = 0b11000001100;
21960}
21961def S2_vtrunohb : HInst<
21962(outs IntRegs:$Rd32),
21963(ins DoubleRegs:$Rss32),
21964"$Rd32 = vtrunohb($Rss32)",
21965tc_0ae0825c, TypeS_2op>, Enc_90cd8b {
21966let Inst{13-5} = 0b000000000;
21967let Inst{31-21} = 0b10001000100;
21968let hasNewValue = 1;
21969let opNewValue = 0;
21970}
21971def S2_vtrunowh : HInst<
21972(outs DoubleRegs:$Rdd32),
21973(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
21974"$Rdd32 = vtrunowh($Rss32,$Rtt32)",
21975tc_946df596, TypeS_3op>, Enc_a56825 {
21976let Inst{7-5} = 0b100;
21977let Inst{13-13} = 0b0;
21978let Inst{31-21} = 0b11000001100;
21979}
21980def S2_vzxtbh : HInst<
21981(outs DoubleRegs:$Rdd32),
21982(ins IntRegs:$Rs32),
21983"$Rdd32 = vzxtbh($Rs32)",
21984tc_0ae0825c, TypeS_2op>, Enc_3a3d62 {
21985let Inst{13-5} = 0b000000010;
21986let Inst{31-21} = 0b10000100000;
21987let isReMaterializable = 1;
21988let isAsCheapAsAMove = 1;
21989}
21990def S2_vzxthw : HInst<
21991(outs DoubleRegs:$Rdd32),
21992(ins IntRegs:$Rs32),
21993"$Rdd32 = vzxthw($Rs32)",
21994tc_0ae0825c, TypeS_2op>, Enc_3a3d62 {
21995let Inst{13-5} = 0b000000110;
21996let Inst{31-21} = 0b10000100000;
21997let isReMaterializable = 1;
21998let isAsCheapAsAMove = 1;
21999}
22000def S4_addaddi : HInst<
22001(outs IntRegs:$Rd32),
22002(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
22003"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
22004tc_f675fee8, TypeALU64>, Enc_8b8d61 {
22005let Inst{31-23} = 0b110110110;
22006let hasNewValue = 1;
22007let opNewValue = 0;
22008let prefersSlot3 = 1;
22009let isExtendable = 1;
22010let opExtendable = 3;
22011let isExtentSigned = 1;
22012let opExtentBits = 6;
22013let opExtentAlign = 0;
22014}
22015def S4_addi_asl_ri : HInst<
22016(outs IntRegs:$Rx32),
22017(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22018"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
22019tc_f675fee8, TypeALU64>, Enc_c31910 {
22020let Inst{2-0} = 0b100;
22021let Inst{4-4} = 0b0;
22022let Inst{31-24} = 0b11011110;
22023let hasNewValue = 1;
22024let opNewValue = 0;
22025let prefersSlot3 = 1;
22026let isExtendable = 1;
22027let opExtendable = 1;
22028let isExtentSigned = 0;
22029let opExtentBits = 8;
22030let opExtentAlign = 0;
22031let Constraints = "$Rx32 = $Rx32in";
22032}
22033def S4_addi_lsr_ri : HInst<
22034(outs IntRegs:$Rx32),
22035(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22036"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
22037tc_f675fee8, TypeALU64>, Enc_c31910 {
22038let Inst{2-0} = 0b100;
22039let Inst{4-4} = 0b1;
22040let Inst{31-24} = 0b11011110;
22041let hasNewValue = 1;
22042let opNewValue = 0;
22043let prefersSlot3 = 1;
22044let isExtendable = 1;
22045let opExtendable = 1;
22046let isExtentSigned = 0;
22047let opExtentBits = 8;
22048let opExtentAlign = 0;
22049let Constraints = "$Rx32 = $Rx32in";
22050}
22051def S4_andi_asl_ri : HInst<
22052(outs IntRegs:$Rx32),
22053(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22054"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
22055tc_f429765c, TypeALU64>, Enc_c31910 {
22056let Inst{2-0} = 0b000;
22057let Inst{4-4} = 0b0;
22058let Inst{31-24} = 0b11011110;
22059let hasNewValue = 1;
22060let opNewValue = 0;
22061let prefersSlot3 = 1;
22062let isExtendable = 1;
22063let opExtendable = 1;
22064let isExtentSigned = 0;
22065let opExtentBits = 8;
22066let opExtentAlign = 0;
22067let Constraints = "$Rx32 = $Rx32in";
22068}
22069def S4_andi_lsr_ri : HInst<
22070(outs IntRegs:$Rx32),
22071(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22072"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
22073tc_f429765c, TypeALU64>, Enc_c31910 {
22074let Inst{2-0} = 0b000;
22075let Inst{4-4} = 0b1;
22076let Inst{31-24} = 0b11011110;
22077let hasNewValue = 1;
22078let opNewValue = 0;
22079let prefersSlot3 = 1;
22080let isExtendable = 1;
22081let opExtendable = 1;
22082let isExtentSigned = 0;
22083let opExtentBits = 8;
22084let opExtentAlign = 0;
22085let Constraints = "$Rx32 = $Rx32in";
22086}
22087def S4_clbaddi : HInst<
22088(outs IntRegs:$Rd32),
22089(ins IntRegs:$Rs32, s6_0Imm:$Ii),
22090"$Rd32 = add(clb($Rs32),#$Ii)",
22091tc_002cb246, TypeS_2op>, Enc_9fae8a {
22092let Inst{7-5} = 0b000;
22093let Inst{31-21} = 0b10001100001;
22094let hasNewValue = 1;
22095let opNewValue = 0;
22096let prefersSlot3 = 1;
22097}
22098def S4_clbpaddi : HInst<
22099(outs IntRegs:$Rd32),
22100(ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
22101"$Rd32 = add(clb($Rss32),#$Ii)",
22102tc_002cb246, TypeS_2op>, Enc_a1640c {
22103let Inst{7-5} = 0b010;
22104let Inst{31-21} = 0b10001000011;
22105let hasNewValue = 1;
22106let opNewValue = 0;
22107let prefersSlot3 = 1;
22108}
22109def S4_clbpnorm : HInst<
22110(outs IntRegs:$Rd32),
22111(ins DoubleRegs:$Rss32),
22112"$Rd32 = normamt($Rss32)",
22113tc_14b5c689, TypeS_2op>, Enc_90cd8b {
22114let Inst{13-5} = 0b000000000;
22115let Inst{31-21} = 0b10001000011;
22116let hasNewValue = 1;
22117let opNewValue = 0;
22118let prefersSlot3 = 1;
22119}
22120def S4_extract : HInst<
22121(outs IntRegs:$Rd32),
22122(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
22123"$Rd32 = extract($Rs32,#$Ii,#$II)",
22124tc_f675fee8, TypeS_2op>, Enc_b388cf {
22125let Inst{13-13} = 0b0;
22126let Inst{31-23} = 0b100011011;
22127let hasNewValue = 1;
22128let opNewValue = 0;
22129let prefersSlot3 = 1;
22130}
22131def S4_extract_rp : HInst<
22132(outs IntRegs:$Rd32),
22133(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
22134"$Rd32 = extract($Rs32,$Rtt32)",
22135tc_002cb246, TypeS_3op>, Enc_e07374 {
22136let Inst{7-5} = 0b010;
22137let Inst{13-13} = 0b0;
22138let Inst{31-21} = 0b11001001000;
22139let hasNewValue = 1;
22140let opNewValue = 0;
22141let prefersSlot3 = 1;
22142}
22143def S4_extractp : HInst<
22144(outs DoubleRegs:$Rdd32),
22145(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
22146"$Rdd32 = extract($Rss32,#$Ii,#$II)",
22147tc_f675fee8, TypeS_2op>, Enc_b84c4c {
22148let Inst{31-24} = 0b10001010;
22149let prefersSlot3 = 1;
22150}
22151def S4_extractp_rp : HInst<
22152(outs DoubleRegs:$Rdd32),
22153(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22154"$Rdd32 = extract($Rss32,$Rtt32)",
22155tc_002cb246, TypeS_3op>, Enc_a56825 {
22156let Inst{7-5} = 0b100;
22157let Inst{13-13} = 0b0;
22158let Inst{31-21} = 0b11000001110;
22159let prefersSlot3 = 1;
22160}
22161def S4_lsli : HInst<
22162(outs IntRegs:$Rd32),
22163(ins s6_0Imm:$Ii, IntRegs:$Rt32),
22164"$Rd32 = lsl(#$Ii,$Rt32)",
22165tc_946df596, TypeS_3op>, Enc_fef969 {
22166let Inst{7-6} = 0b11;
22167let Inst{13-13} = 0b0;
22168let Inst{31-21} = 0b11000110100;
22169let hasNewValue = 1;
22170let opNewValue = 0;
22171}
22172def S4_ntstbit_i : HInst<
22173(outs PredRegs:$Pd4),
22174(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22175"$Pd4 = !tstbit($Rs32,#$Ii)",
22176tc_643b4717, TypeS_2op>, Enc_83ee64 {
22177let Inst{7-2} = 0b000000;
22178let Inst{13-13} = 0b0;
22179let Inst{31-21} = 0b10000101001;
22180}
22181def S4_ntstbit_r : HInst<
22182(outs PredRegs:$Pd4),
22183(ins IntRegs:$Rs32, IntRegs:$Rt32),
22184"$Pd4 = !tstbit($Rs32,$Rt32)",
22185tc_85d5d03f, TypeS_3op>, Enc_c2b48e {
22186let Inst{7-2} = 0b000000;
22187let Inst{13-13} = 0b0;
22188let Inst{31-21} = 0b11000111001;
22189}
22190def S4_or_andi : HInst<
22191(outs IntRegs:$Rx32),
22192(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22193"$Rx32 |= and($Rs32,#$Ii)",
22194tc_f429765c, TypeALU64>, Enc_b0e9d8 {
22195let Inst{31-22} = 0b1101101000;
22196let hasNewValue = 1;
22197let opNewValue = 0;
22198let prefersSlot3 = 1;
22199let InputType = "imm";
22200let isExtendable = 1;
22201let opExtendable = 3;
22202let isExtentSigned = 1;
22203let opExtentBits = 10;
22204let opExtentAlign = 0;
22205let Constraints = "$Rx32 = $Rx32in";
22206}
22207def S4_or_andix : HInst<
22208(outs IntRegs:$Rx32),
22209(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
22210"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22211tc_f429765c, TypeALU64>, Enc_b4e6cf {
22212let Inst{31-22} = 0b1101101001;
22213let hasNewValue = 1;
22214let opNewValue = 0;
22215let prefersSlot3 = 1;
22216let isExtendable = 1;
22217let opExtendable = 3;
22218let isExtentSigned = 1;
22219let opExtentBits = 10;
22220let opExtentAlign = 0;
22221let Constraints = "$Rx32 = $Rx32in";
22222}
22223def S4_or_ori : HInst<
22224(outs IntRegs:$Rx32),
22225(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22226"$Rx32 |= or($Rs32,#$Ii)",
22227tc_f429765c, TypeALU64>, Enc_b0e9d8 {
22228let Inst{31-22} = 0b1101101010;
22229let hasNewValue = 1;
22230let opNewValue = 0;
22231let prefersSlot3 = 1;
22232let InputType = "imm";
22233let isExtendable = 1;
22234let opExtendable = 3;
22235let isExtentSigned = 1;
22236let opExtentBits = 10;
22237let opExtentAlign = 0;
22238let Constraints = "$Rx32 = $Rx32in";
22239}
22240def S4_ori_asl_ri : HInst<
22241(outs IntRegs:$Rx32),
22242(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22243"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22244tc_f429765c, TypeALU64>, Enc_c31910 {
22245let Inst{2-0} = 0b010;
22246let Inst{4-4} = 0b0;
22247let Inst{31-24} = 0b11011110;
22248let hasNewValue = 1;
22249let opNewValue = 0;
22250let prefersSlot3 = 1;
22251let isExtendable = 1;
22252let opExtendable = 1;
22253let isExtentSigned = 0;
22254let opExtentBits = 8;
22255let opExtentAlign = 0;
22256let Constraints = "$Rx32 = $Rx32in";
22257}
22258def S4_ori_lsr_ri : HInst<
22259(outs IntRegs:$Rx32),
22260(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22261"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22262tc_f429765c, TypeALU64>, Enc_c31910 {
22263let Inst{2-0} = 0b010;
22264let Inst{4-4} = 0b1;
22265let Inst{31-24} = 0b11011110;
22266let hasNewValue = 1;
22267let opNewValue = 0;
22268let prefersSlot3 = 1;
22269let isExtendable = 1;
22270let opExtendable = 1;
22271let isExtentSigned = 0;
22272let opExtentBits = 8;
22273let opExtentAlign = 0;
22274let Constraints = "$Rx32 = $Rx32in";
22275}
22276def S4_parity : HInst<
22277(outs IntRegs:$Rd32),
22278(ins IntRegs:$Rs32, IntRegs:$Rt32),
22279"$Rd32 = parity($Rs32,$Rt32)",
22280tc_002cb246, TypeALU64>, Enc_5ab2be {
22281let Inst{7-5} = 0b000;
22282let Inst{13-13} = 0b0;
22283let Inst{31-21} = 0b11010101111;
22284let hasNewValue = 1;
22285let opNewValue = 0;
22286let prefersSlot3 = 1;
22287}
22288def S4_pstorerbf_abs : HInst<
22289(outs),
22290(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22291"if (!$Pv4) memb(#$Ii) = $Rt32",
22292tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
22293let Inst{2-2} = 0b1;
22294let Inst{7-7} = 0b1;
22295let Inst{13-13} = 0b0;
22296let Inst{31-18} = 0b10101111000000;
22297let isPredicated = 1;
22298let isPredicatedFalse = 1;
22299let addrMode = Absolute;
22300let accessSize = ByteAccess;
22301let isExtended = 1;
22302let mayStore = 1;
22303let CextOpcode = "S2_storerb";
22304let BaseOpcode = "S2_storerbabs";
22305let isNVStorable = 1;
22306let DecoderNamespace = "MustExtend";
22307let isExtendable = 1;
22308let opExtendable = 1;
22309let isExtentSigned = 0;
22310let opExtentBits = 6;
22311let opExtentAlign = 0;
22312}
22313def S4_pstorerbf_rr : HInst<
22314(outs),
22315(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22316"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22317tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
22318let Inst{31-21} = 0b00110101000;
22319let isPredicated = 1;
22320let isPredicatedFalse = 1;
22321let addrMode = BaseRegOffset;
22322let accessSize = ByteAccess;
22323let mayStore = 1;
22324let CextOpcode = "S2_storerb";
22325let InputType = "reg";
22326let BaseOpcode = "S4_storerb_rr";
22327let isNVStorable = 1;
22328}
22329def S4_pstorerbfnew_abs : HInst<
22330(outs),
22331(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22332"if (!$Pv4.new) memb(#$Ii) = $Rt32",
22333tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
22334let Inst{2-2} = 0b1;
22335let Inst{7-7} = 0b1;
22336let Inst{13-13} = 0b1;
22337let Inst{31-18} = 0b10101111000000;
22338let isPredicated = 1;
22339let isPredicatedFalse = 1;
22340let addrMode = Absolute;
22341let accessSize = ByteAccess;
22342let isPredicatedNew = 1;
22343let isExtended = 1;
22344let mayStore = 1;
22345let CextOpcode = "S2_storerb";
22346let BaseOpcode = "S2_storerbabs";
22347let isNVStorable = 1;
22348let DecoderNamespace = "MustExtend";
22349let isExtendable = 1;
22350let opExtendable = 1;
22351let isExtentSigned = 0;
22352let opExtentBits = 6;
22353let opExtentAlign = 0;
22354}
22355def S4_pstorerbfnew_io : HInst<
22356(outs),
22357(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22358"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22359tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22360let Inst{2-2} = 0b0;
22361let Inst{31-21} = 0b01000110000;
22362let isPredicated = 1;
22363let isPredicatedFalse = 1;
22364let addrMode = BaseImmOffset;
22365let accessSize = ByteAccess;
22366let isPredicatedNew = 1;
22367let mayStore = 1;
22368let CextOpcode = "S2_storerb";
22369let InputType = "imm";
22370let BaseOpcode = "S2_storerb_io";
22371let isNVStorable = 1;
22372let isExtendable = 1;
22373let opExtendable = 2;
22374let isExtentSigned = 0;
22375let opExtentBits = 6;
22376let opExtentAlign = 0;
22377}
22378def S4_pstorerbfnew_rr : HInst<
22379(outs),
22380(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22381"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22382tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
22383let Inst{31-21} = 0b00110111000;
22384let isPredicated = 1;
22385let isPredicatedFalse = 1;
22386let addrMode = BaseRegOffset;
22387let accessSize = ByteAccess;
22388let isPredicatedNew = 1;
22389let mayStore = 1;
22390let CextOpcode = "S2_storerb";
22391let InputType = "reg";
22392let BaseOpcode = "S4_storerb_rr";
22393let isNVStorable = 1;
22394}
22395def S4_pstorerbfnew_zomap : HInst<
22396(outs),
22397(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22398"if (!$Pv4.new) memb($Rs32) = $Rt32",
22399tc_da97ee82, TypeMAPPING> {
22400let isPseudo = 1;
22401let isCodeGenOnly = 1;
22402}
22403def S4_pstorerbnewf_abs : HInst<
22404(outs),
22405(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22406"if (!$Pv4) memb(#$Ii) = $Nt8.new",
22407tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel {
22408let Inst{2-2} = 0b1;
22409let Inst{7-7} = 0b1;
22410let Inst{13-11} = 0b000;
22411let Inst{31-18} = 0b10101111101000;
22412let isPredicated = 1;
22413let isPredicatedFalse = 1;
22414let addrMode = Absolute;
22415let accessSize = ByteAccess;
22416let isNVStore = 1;
22417let isNewValue = 1;
22418let isExtended = 1;
22419let isRestrictNoSlot1Store = 1;
22420let mayStore = 1;
22421let CextOpcode = "S2_storerb";
22422let BaseOpcode = "S2_storerbabs";
22423let DecoderNamespace = "MustExtend";
22424let isExtendable = 1;
22425let opExtendable = 1;
22426let isExtentSigned = 0;
22427let opExtentBits = 6;
22428let opExtentAlign = 0;
22429let opNewValue = 2;
22430}
22431def S4_pstorerbnewf_rr : HInst<
22432(outs),
22433(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22434"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22435tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel {
22436let Inst{4-3} = 0b00;
22437let Inst{31-21} = 0b00110101101;
22438let isPredicated = 1;
22439let isPredicatedFalse = 1;
22440let addrMode = BaseRegOffset;
22441let accessSize = ByteAccess;
22442let isNVStore = 1;
22443let isNewValue = 1;
22444let isRestrictNoSlot1Store = 1;
22445let mayStore = 1;
22446let CextOpcode = "S2_storerb";
22447let InputType = "reg";
22448let BaseOpcode = "S4_storerb_rr";
22449let opNewValue = 4;
22450}
22451def S4_pstorerbnewfnew_abs : HInst<
22452(outs),
22453(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22454"if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
22455tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel {
22456let Inst{2-2} = 0b1;
22457let Inst{7-7} = 0b1;
22458let Inst{13-11} = 0b100;
22459let Inst{31-18} = 0b10101111101000;
22460let isPredicated = 1;
22461let isPredicatedFalse = 1;
22462let addrMode = Absolute;
22463let accessSize = ByteAccess;
22464let isNVStore = 1;
22465let isPredicatedNew = 1;
22466let isNewValue = 1;
22467let isExtended = 1;
22468let isRestrictNoSlot1Store = 1;
22469let mayStore = 1;
22470let CextOpcode = "S2_storerb";
22471let BaseOpcode = "S2_storerbabs";
22472let DecoderNamespace = "MustExtend";
22473let isExtendable = 1;
22474let opExtendable = 1;
22475let isExtentSigned = 0;
22476let opExtentBits = 6;
22477let opExtentAlign = 0;
22478let opNewValue = 2;
22479}
22480def S4_pstorerbnewfnew_io : HInst<
22481(outs),
22482(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22483"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22484tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel {
22485let Inst{2-2} = 0b0;
22486let Inst{12-11} = 0b00;
22487let Inst{31-21} = 0b01000110101;
22488let isPredicated = 1;
22489let isPredicatedFalse = 1;
22490let addrMode = BaseImmOffset;
22491let accessSize = ByteAccess;
22492let isNVStore = 1;
22493let isPredicatedNew = 1;
22494let isNewValue = 1;
22495let isRestrictNoSlot1Store = 1;
22496let mayStore = 1;
22497let CextOpcode = "S2_storerb";
22498let InputType = "imm";
22499let BaseOpcode = "S2_storerb_io";
22500let isExtendable = 1;
22501let opExtendable = 2;
22502let isExtentSigned = 0;
22503let opExtentBits = 6;
22504let opExtentAlign = 0;
22505let opNewValue = 3;
22506}
22507def S4_pstorerbnewfnew_rr : HInst<
22508(outs),
22509(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22510"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22511tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel {
22512let Inst{4-3} = 0b00;
22513let Inst{31-21} = 0b00110111101;
22514let isPredicated = 1;
22515let isPredicatedFalse = 1;
22516let addrMode = BaseRegOffset;
22517let accessSize = ByteAccess;
22518let isNVStore = 1;
22519let isPredicatedNew = 1;
22520let isNewValue = 1;
22521let isRestrictNoSlot1Store = 1;
22522let mayStore = 1;
22523let CextOpcode = "S2_storerb";
22524let InputType = "reg";
22525let BaseOpcode = "S4_storerb_rr";
22526let opNewValue = 4;
22527}
22528def S4_pstorerbnewfnew_zomap : HInst<
22529(outs),
22530(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22531"if (!$Pv4.new) memb($Rs32) = $Nt8.new",
22532tc_c79a189f, TypeMAPPING> {
22533let isPseudo = 1;
22534let isCodeGenOnly = 1;
22535let opNewValue = 2;
22536}
22537def S4_pstorerbnewt_abs : HInst<
22538(outs),
22539(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22540"if ($Pv4) memb(#$Ii) = $Nt8.new",
22541tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel {
22542let Inst{2-2} = 0b0;
22543let Inst{7-7} = 0b1;
22544let Inst{13-11} = 0b000;
22545let Inst{31-18} = 0b10101111101000;
22546let isPredicated = 1;
22547let addrMode = Absolute;
22548let accessSize = ByteAccess;
22549let isNVStore = 1;
22550let isNewValue = 1;
22551let isExtended = 1;
22552let isRestrictNoSlot1Store = 1;
22553let mayStore = 1;
22554let CextOpcode = "S2_storerb";
22555let BaseOpcode = "S2_storerbabs";
22556let DecoderNamespace = "MustExtend";
22557let isExtendable = 1;
22558let opExtendable = 1;
22559let isExtentSigned = 0;
22560let opExtentBits = 6;
22561let opExtentAlign = 0;
22562let opNewValue = 2;
22563}
22564def S4_pstorerbnewt_rr : HInst<
22565(outs),
22566(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22567"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22568tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel {
22569let Inst{4-3} = 0b00;
22570let Inst{31-21} = 0b00110100101;
22571let isPredicated = 1;
22572let addrMode = BaseRegOffset;
22573let accessSize = ByteAccess;
22574let isNVStore = 1;
22575let isNewValue = 1;
22576let isRestrictNoSlot1Store = 1;
22577let mayStore = 1;
22578let CextOpcode = "S2_storerb";
22579let InputType = "reg";
22580let BaseOpcode = "S4_storerb_rr";
22581let opNewValue = 4;
22582}
22583def S4_pstorerbnewtnew_abs : HInst<
22584(outs),
22585(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22586"if ($Pv4.new) memb(#$Ii) = $Nt8.new",
22587tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel {
22588let Inst{2-2} = 0b0;
22589let Inst{7-7} = 0b1;
22590let Inst{13-11} = 0b100;
22591let Inst{31-18} = 0b10101111101000;
22592let isPredicated = 1;
22593let addrMode = Absolute;
22594let accessSize = ByteAccess;
22595let isNVStore = 1;
22596let isPredicatedNew = 1;
22597let isNewValue = 1;
22598let isExtended = 1;
22599let isRestrictNoSlot1Store = 1;
22600let mayStore = 1;
22601let CextOpcode = "S2_storerb";
22602let BaseOpcode = "S2_storerbabs";
22603let DecoderNamespace = "MustExtend";
22604let isExtendable = 1;
22605let opExtendable = 1;
22606let isExtentSigned = 0;
22607let opExtentBits = 6;
22608let opExtentAlign = 0;
22609let opNewValue = 2;
22610}
22611def S4_pstorerbnewtnew_io : HInst<
22612(outs),
22613(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22614"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22615tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel {
22616let Inst{2-2} = 0b0;
22617let Inst{12-11} = 0b00;
22618let Inst{31-21} = 0b01000010101;
22619let isPredicated = 1;
22620let addrMode = BaseImmOffset;
22621let accessSize = ByteAccess;
22622let isNVStore = 1;
22623let isPredicatedNew = 1;
22624let isNewValue = 1;
22625let isRestrictNoSlot1Store = 1;
22626let mayStore = 1;
22627let CextOpcode = "S2_storerb";
22628let InputType = "imm";
22629let BaseOpcode = "S2_storerb_io";
22630let isExtendable = 1;
22631let opExtendable = 2;
22632let isExtentSigned = 0;
22633let opExtentBits = 6;
22634let opExtentAlign = 0;
22635let opNewValue = 3;
22636}
22637def S4_pstorerbnewtnew_rr : HInst<
22638(outs),
22639(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22640"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22641tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel {
22642let Inst{4-3} = 0b00;
22643let Inst{31-21} = 0b00110110101;
22644let isPredicated = 1;
22645let addrMode = BaseRegOffset;
22646let accessSize = ByteAccess;
22647let isNVStore = 1;
22648let isPredicatedNew = 1;
22649let isNewValue = 1;
22650let isRestrictNoSlot1Store = 1;
22651let mayStore = 1;
22652let CextOpcode = "S2_storerb";
22653let InputType = "reg";
22654let BaseOpcode = "S4_storerb_rr";
22655let opNewValue = 4;
22656}
22657def S4_pstorerbnewtnew_zomap : HInst<
22658(outs),
22659(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22660"if ($Pv4.new) memb($Rs32) = $Nt8.new",
22661tc_c79a189f, TypeMAPPING> {
22662let isPseudo = 1;
22663let isCodeGenOnly = 1;
22664let opNewValue = 2;
22665}
22666def S4_pstorerbt_abs : HInst<
22667(outs),
22668(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22669"if ($Pv4) memb(#$Ii) = $Rt32",
22670tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
22671let Inst{2-2} = 0b0;
22672let Inst{7-7} = 0b1;
22673let Inst{13-13} = 0b0;
22674let Inst{31-18} = 0b10101111000000;
22675let isPredicated = 1;
22676let addrMode = Absolute;
22677let accessSize = ByteAccess;
22678let isExtended = 1;
22679let mayStore = 1;
22680let CextOpcode = "S2_storerb";
22681let BaseOpcode = "S2_storerbabs";
22682let isNVStorable = 1;
22683let DecoderNamespace = "MustExtend";
22684let isExtendable = 1;
22685let opExtendable = 1;
22686let isExtentSigned = 0;
22687let opExtentBits = 6;
22688let opExtentAlign = 0;
22689}
22690def S4_pstorerbt_rr : HInst<
22691(outs),
22692(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22693"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22694tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
22695let Inst{31-21} = 0b00110100000;
22696let isPredicated = 1;
22697let addrMode = BaseRegOffset;
22698let accessSize = ByteAccess;
22699let mayStore = 1;
22700let CextOpcode = "S2_storerb";
22701let InputType = "reg";
22702let BaseOpcode = "S4_storerb_rr";
22703let isNVStorable = 1;
22704}
22705def S4_pstorerbtnew_abs : HInst<
22706(outs),
22707(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22708"if ($Pv4.new) memb(#$Ii) = $Rt32",
22709tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
22710let Inst{2-2} = 0b0;
22711let Inst{7-7} = 0b1;
22712let Inst{13-13} = 0b1;
22713let Inst{31-18} = 0b10101111000000;
22714let isPredicated = 1;
22715let addrMode = Absolute;
22716let accessSize = ByteAccess;
22717let isPredicatedNew = 1;
22718let isExtended = 1;
22719let mayStore = 1;
22720let CextOpcode = "S2_storerb";
22721let BaseOpcode = "S2_storerbabs";
22722let isNVStorable = 1;
22723let DecoderNamespace = "MustExtend";
22724let isExtendable = 1;
22725let opExtendable = 1;
22726let isExtentSigned = 0;
22727let opExtentBits = 6;
22728let opExtentAlign = 0;
22729}
22730def S4_pstorerbtnew_io : HInst<
22731(outs),
22732(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22733"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22734tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22735let Inst{2-2} = 0b0;
22736let Inst{31-21} = 0b01000010000;
22737let isPredicated = 1;
22738let addrMode = BaseImmOffset;
22739let accessSize = ByteAccess;
22740let isPredicatedNew = 1;
22741let mayStore = 1;
22742let CextOpcode = "S2_storerb";
22743let InputType = "imm";
22744let BaseOpcode = "S2_storerb_io";
22745let isNVStorable = 1;
22746let isExtendable = 1;
22747let opExtendable = 2;
22748let isExtentSigned = 0;
22749let opExtentBits = 6;
22750let opExtentAlign = 0;
22751}
22752def S4_pstorerbtnew_rr : HInst<
22753(outs),
22754(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22755"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22756tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
22757let Inst{31-21} = 0b00110110000;
22758let isPredicated = 1;
22759let addrMode = BaseRegOffset;
22760let accessSize = ByteAccess;
22761let isPredicatedNew = 1;
22762let mayStore = 1;
22763let CextOpcode = "S2_storerb";
22764let InputType = "reg";
22765let BaseOpcode = "S4_storerb_rr";
22766let isNVStorable = 1;
22767}
22768def S4_pstorerbtnew_zomap : HInst<
22769(outs),
22770(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22771"if ($Pv4.new) memb($Rs32) = $Rt32",
22772tc_da97ee82, TypeMAPPING> {
22773let isPseudo = 1;
22774let isCodeGenOnly = 1;
22775}
22776def S4_pstorerdf_abs : HInst<
22777(outs),
22778(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22779"if (!$Pv4) memd(#$Ii) = $Rtt32",
22780tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel {
22781let Inst{2-2} = 0b1;
22782let Inst{7-7} = 0b1;
22783let Inst{13-13} = 0b0;
22784let Inst{31-18} = 0b10101111110000;
22785let isPredicated = 1;
22786let isPredicatedFalse = 1;
22787let addrMode = Absolute;
22788let accessSize = DoubleWordAccess;
22789let isExtended = 1;
22790let mayStore = 1;
22791let CextOpcode = "S2_storerd";
22792let BaseOpcode = "S2_storerdabs";
22793let DecoderNamespace = "MustExtend";
22794let isExtendable = 1;
22795let opExtendable = 1;
22796let isExtentSigned = 0;
22797let opExtentBits = 6;
22798let opExtentAlign = 0;
22799}
22800def S4_pstorerdf_rr : HInst<
22801(outs),
22802(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22803"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22804tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel {
22805let Inst{31-21} = 0b00110101110;
22806let isPredicated = 1;
22807let isPredicatedFalse = 1;
22808let addrMode = BaseRegOffset;
22809let accessSize = DoubleWordAccess;
22810let mayStore = 1;
22811let CextOpcode = "S2_storerd";
22812let InputType = "reg";
22813let BaseOpcode = "S2_storerd_rr";
22814}
22815def S4_pstorerdfnew_abs : HInst<
22816(outs),
22817(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22818"if (!$Pv4.new) memd(#$Ii) = $Rtt32",
22819tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel {
22820let Inst{2-2} = 0b1;
22821let Inst{7-7} = 0b1;
22822let Inst{13-13} = 0b1;
22823let Inst{31-18} = 0b10101111110000;
22824let isPredicated = 1;
22825let isPredicatedFalse = 1;
22826let addrMode = Absolute;
22827let accessSize = DoubleWordAccess;
22828let isPredicatedNew = 1;
22829let isExtended = 1;
22830let mayStore = 1;
22831let CextOpcode = "S2_storerd";
22832let BaseOpcode = "S2_storerdabs";
22833let DecoderNamespace = "MustExtend";
22834let isExtendable = 1;
22835let opExtendable = 1;
22836let isExtentSigned = 0;
22837let opExtentBits = 6;
22838let opExtentAlign = 0;
22839}
22840def S4_pstorerdfnew_io : HInst<
22841(outs),
22842(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
22843"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
22844tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel {
22845let Inst{2-2} = 0b0;
22846let Inst{31-21} = 0b01000110110;
22847let isPredicated = 1;
22848let isPredicatedFalse = 1;
22849let addrMode = BaseImmOffset;
22850let accessSize = DoubleWordAccess;
22851let isPredicatedNew = 1;
22852let mayStore = 1;
22853let CextOpcode = "S2_storerd";
22854let InputType = "imm";
22855let BaseOpcode = "S2_storerd_io";
22856let isExtendable = 1;
22857let opExtendable = 2;
22858let isExtentSigned = 0;
22859let opExtentBits = 9;
22860let opExtentAlign = 3;
22861}
22862def S4_pstorerdfnew_rr : HInst<
22863(outs),
22864(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22865"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22866tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel {
22867let Inst{31-21} = 0b00110111110;
22868let isPredicated = 1;
22869let isPredicatedFalse = 1;
22870let addrMode = BaseRegOffset;
22871let accessSize = DoubleWordAccess;
22872let isPredicatedNew = 1;
22873let mayStore = 1;
22874let CextOpcode = "S2_storerd";
22875let InputType = "reg";
22876let BaseOpcode = "S2_storerd_rr";
22877}
22878def S4_pstorerdfnew_zomap : HInst<
22879(outs),
22880(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
22881"if (!$Pv4.new) memd($Rs32) = $Rtt32",
22882tc_da97ee82, TypeMAPPING> {
22883let isPseudo = 1;
22884let isCodeGenOnly = 1;
22885}
22886def S4_pstorerdt_abs : HInst<
22887(outs),
22888(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22889"if ($Pv4) memd(#$Ii) = $Rtt32",
22890tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel {
22891let Inst{2-2} = 0b0;
22892let Inst{7-7} = 0b1;
22893let Inst{13-13} = 0b0;
22894let Inst{31-18} = 0b10101111110000;
22895let isPredicated = 1;
22896let addrMode = Absolute;
22897let accessSize = DoubleWordAccess;
22898let isExtended = 1;
22899let mayStore = 1;
22900let CextOpcode = "S2_storerd";
22901let BaseOpcode = "S2_storerdabs";
22902let DecoderNamespace = "MustExtend";
22903let isExtendable = 1;
22904let opExtendable = 1;
22905let isExtentSigned = 0;
22906let opExtentBits = 6;
22907let opExtentAlign = 0;
22908}
22909def S4_pstorerdt_rr : HInst<
22910(outs),
22911(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22912"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22913tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel {
22914let Inst{31-21} = 0b00110100110;
22915let isPredicated = 1;
22916let addrMode = BaseRegOffset;
22917let accessSize = DoubleWordAccess;
22918let mayStore = 1;
22919let CextOpcode = "S2_storerd";
22920let InputType = "reg";
22921let BaseOpcode = "S2_storerd_rr";
22922}
22923def S4_pstorerdtnew_abs : HInst<
22924(outs),
22925(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
22926"if ($Pv4.new) memd(#$Ii) = $Rtt32",
22927tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel {
22928let Inst{2-2} = 0b0;
22929let Inst{7-7} = 0b1;
22930let Inst{13-13} = 0b1;
22931let Inst{31-18} = 0b10101111110000;
22932let isPredicated = 1;
22933let addrMode = Absolute;
22934let accessSize = DoubleWordAccess;
22935let isPredicatedNew = 1;
22936let isExtended = 1;
22937let mayStore = 1;
22938let CextOpcode = "S2_storerd";
22939let BaseOpcode = "S2_storerdabs";
22940let DecoderNamespace = "MustExtend";
22941let isExtendable = 1;
22942let opExtendable = 1;
22943let isExtentSigned = 0;
22944let opExtentBits = 6;
22945let opExtentAlign = 0;
22946}
22947def S4_pstorerdtnew_io : HInst<
22948(outs),
22949(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
22950"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
22951tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel {
22952let Inst{2-2} = 0b0;
22953let Inst{31-21} = 0b01000010110;
22954let isPredicated = 1;
22955let addrMode = BaseImmOffset;
22956let accessSize = DoubleWordAccess;
22957let isPredicatedNew = 1;
22958let mayStore = 1;
22959let CextOpcode = "S2_storerd";
22960let InputType = "imm";
22961let BaseOpcode = "S2_storerd_io";
22962let isExtendable = 1;
22963let opExtendable = 2;
22964let isExtentSigned = 0;
22965let opExtentBits = 9;
22966let opExtentAlign = 3;
22967}
22968def S4_pstorerdtnew_rr : HInst<
22969(outs),
22970(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
22971"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
22972tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel {
22973let Inst{31-21} = 0b00110110110;
22974let isPredicated = 1;
22975let addrMode = BaseRegOffset;
22976let accessSize = DoubleWordAccess;
22977let isPredicatedNew = 1;
22978let mayStore = 1;
22979let CextOpcode = "S2_storerd";
22980let InputType = "reg";
22981let BaseOpcode = "S2_storerd_rr";
22982}
22983def S4_pstorerdtnew_zomap : HInst<
22984(outs),
22985(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
22986"if ($Pv4.new) memd($Rs32) = $Rtt32",
22987tc_da97ee82, TypeMAPPING> {
22988let isPseudo = 1;
22989let isCodeGenOnly = 1;
22990}
22991def S4_pstorerff_abs : HInst<
22992(outs),
22993(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22994"if (!$Pv4) memh(#$Ii) = $Rt32.h",
22995tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
22996let Inst{2-2} = 0b1;
22997let Inst{7-7} = 0b1;
22998let Inst{13-13} = 0b0;
22999let Inst{31-18} = 0b10101111011000;
23000let isPredicated = 1;
23001let isPredicatedFalse = 1;
23002let addrMode = Absolute;
23003let accessSize = HalfWordAccess;
23004let isExtended = 1;
23005let mayStore = 1;
23006let CextOpcode = "S2_storerf";
23007let BaseOpcode = "S2_storerfabs";
23008let DecoderNamespace = "MustExtend";
23009let isExtendable = 1;
23010let opExtendable = 1;
23011let isExtentSigned = 0;
23012let opExtentBits = 6;
23013let opExtentAlign = 0;
23014}
23015def S4_pstorerff_rr : HInst<
23016(outs),
23017(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23018"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23019tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
23020let Inst{31-21} = 0b00110101011;
23021let isPredicated = 1;
23022let isPredicatedFalse = 1;
23023let addrMode = BaseRegOffset;
23024let accessSize = HalfWordAccess;
23025let mayStore = 1;
23026let CextOpcode = "S2_storerf";
23027let InputType = "reg";
23028let BaseOpcode = "S4_storerf_rr";
23029}
23030def S4_pstorerffnew_abs : HInst<
23031(outs),
23032(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23033"if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
23034tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
23035let Inst{2-2} = 0b1;
23036let Inst{7-7} = 0b1;
23037let Inst{13-13} = 0b1;
23038let Inst{31-18} = 0b10101111011000;
23039let isPredicated = 1;
23040let isPredicatedFalse = 1;
23041let addrMode = Absolute;
23042let accessSize = HalfWordAccess;
23043let isPredicatedNew = 1;
23044let isExtended = 1;
23045let mayStore = 1;
23046let CextOpcode = "S2_storerf";
23047let BaseOpcode = "S2_storerfabs";
23048let DecoderNamespace = "MustExtend";
23049let isExtendable = 1;
23050let opExtendable = 1;
23051let isExtentSigned = 0;
23052let opExtentBits = 6;
23053let opExtentAlign = 0;
23054}
23055def S4_pstorerffnew_io : HInst<
23056(outs),
23057(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23058"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23059tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23060let Inst{2-2} = 0b0;
23061let Inst{31-21} = 0b01000110011;
23062let isPredicated = 1;
23063let isPredicatedFalse = 1;
23064let addrMode = BaseImmOffset;
23065let accessSize = HalfWordAccess;
23066let isPredicatedNew = 1;
23067let mayStore = 1;
23068let CextOpcode = "S2_storerf";
23069let InputType = "imm";
23070let BaseOpcode = "S2_storerf_io";
23071let isExtendable = 1;
23072let opExtendable = 2;
23073let isExtentSigned = 0;
23074let opExtentBits = 7;
23075let opExtentAlign = 1;
23076}
23077def S4_pstorerffnew_rr : HInst<
23078(outs),
23079(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23080"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23081tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
23082let Inst{31-21} = 0b00110111011;
23083let isPredicated = 1;
23084let isPredicatedFalse = 1;
23085let addrMode = BaseRegOffset;
23086let accessSize = HalfWordAccess;
23087let isPredicatedNew = 1;
23088let mayStore = 1;
23089let CextOpcode = "S2_storerf";
23090let InputType = "reg";
23091let BaseOpcode = "S4_storerf_rr";
23092}
23093def S4_pstorerffnew_zomap : HInst<
23094(outs),
23095(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23096"if (!$Pv4.new) memh($Rs32) = $Rt32.h",
23097tc_da97ee82, TypeMAPPING> {
23098let isPseudo = 1;
23099let isCodeGenOnly = 1;
23100}
23101def S4_pstorerft_abs : HInst<
23102(outs),
23103(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23104"if ($Pv4) memh(#$Ii) = $Rt32.h",
23105tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
23106let Inst{2-2} = 0b0;
23107let Inst{7-7} = 0b1;
23108let Inst{13-13} = 0b0;
23109let Inst{31-18} = 0b10101111011000;
23110let isPredicated = 1;
23111let addrMode = Absolute;
23112let accessSize = HalfWordAccess;
23113let isExtended = 1;
23114let mayStore = 1;
23115let CextOpcode = "S2_storerf";
23116let BaseOpcode = "S2_storerfabs";
23117let DecoderNamespace = "MustExtend";
23118let isExtendable = 1;
23119let opExtendable = 1;
23120let isExtentSigned = 0;
23121let opExtentBits = 6;
23122let opExtentAlign = 0;
23123}
23124def S4_pstorerft_rr : HInst<
23125(outs),
23126(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23127"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23128tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
23129let Inst{31-21} = 0b00110100011;
23130let isPredicated = 1;
23131let addrMode = BaseRegOffset;
23132let accessSize = HalfWordAccess;
23133let mayStore = 1;
23134let CextOpcode = "S2_storerf";
23135let InputType = "reg";
23136let BaseOpcode = "S4_storerf_rr";
23137}
23138def S4_pstorerftnew_abs : HInst<
23139(outs),
23140(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23141"if ($Pv4.new) memh(#$Ii) = $Rt32.h",
23142tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
23143let Inst{2-2} = 0b0;
23144let Inst{7-7} = 0b1;
23145let Inst{13-13} = 0b1;
23146let Inst{31-18} = 0b10101111011000;
23147let isPredicated = 1;
23148let addrMode = Absolute;
23149let accessSize = HalfWordAccess;
23150let isPredicatedNew = 1;
23151let isExtended = 1;
23152let mayStore = 1;
23153let CextOpcode = "S2_storerf";
23154let BaseOpcode = "S2_storerfabs";
23155let DecoderNamespace = "MustExtend";
23156let isExtendable = 1;
23157let opExtendable = 1;
23158let isExtentSigned = 0;
23159let opExtentBits = 6;
23160let opExtentAlign = 0;
23161}
23162def S4_pstorerftnew_io : HInst<
23163(outs),
23164(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23165"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23166tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23167let Inst{2-2} = 0b0;
23168let Inst{31-21} = 0b01000010011;
23169let isPredicated = 1;
23170let addrMode = BaseImmOffset;
23171let accessSize = HalfWordAccess;
23172let isPredicatedNew = 1;
23173let mayStore = 1;
23174let CextOpcode = "S2_storerf";
23175let InputType = "imm";
23176let BaseOpcode = "S2_storerf_io";
23177let isExtendable = 1;
23178let opExtendable = 2;
23179let isExtentSigned = 0;
23180let opExtentBits = 7;
23181let opExtentAlign = 1;
23182}
23183def S4_pstorerftnew_rr : HInst<
23184(outs),
23185(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23186"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23187tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
23188let Inst{31-21} = 0b00110110011;
23189let isPredicated = 1;
23190let addrMode = BaseRegOffset;
23191let accessSize = HalfWordAccess;
23192let isPredicatedNew = 1;
23193let mayStore = 1;
23194let CextOpcode = "S2_storerf";
23195let InputType = "reg";
23196let BaseOpcode = "S4_storerf_rr";
23197}
23198def S4_pstorerftnew_zomap : HInst<
23199(outs),
23200(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23201"if ($Pv4.new) memh($Rs32) = $Rt32.h",
23202tc_da97ee82, TypeMAPPING> {
23203let isPseudo = 1;
23204let isCodeGenOnly = 1;
23205}
23206def S4_pstorerhf_abs : HInst<
23207(outs),
23208(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23209"if (!$Pv4) memh(#$Ii) = $Rt32",
23210tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
23211let Inst{2-2} = 0b1;
23212let Inst{7-7} = 0b1;
23213let Inst{13-13} = 0b0;
23214let Inst{31-18} = 0b10101111010000;
23215let isPredicated = 1;
23216let isPredicatedFalse = 1;
23217let addrMode = Absolute;
23218let accessSize = HalfWordAccess;
23219let isExtended = 1;
23220let mayStore = 1;
23221let CextOpcode = "S2_storerh";
23222let BaseOpcode = "S2_storerhabs";
23223let isNVStorable = 1;
23224let DecoderNamespace = "MustExtend";
23225let isExtendable = 1;
23226let opExtendable = 1;
23227let isExtentSigned = 0;
23228let opExtentBits = 6;
23229let opExtentAlign = 0;
23230}
23231def S4_pstorerhf_rr : HInst<
23232(outs),
23233(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23234"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23235tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
23236let Inst{31-21} = 0b00110101010;
23237let isPredicated = 1;
23238let isPredicatedFalse = 1;
23239let addrMode = BaseRegOffset;
23240let accessSize = HalfWordAccess;
23241let mayStore = 1;
23242let CextOpcode = "S2_storerh";
23243let InputType = "reg";
23244let BaseOpcode = "S2_storerh_rr";
23245let isNVStorable = 1;
23246}
23247def S4_pstorerhfnew_abs : HInst<
23248(outs),
23249(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23250"if (!$Pv4.new) memh(#$Ii) = $Rt32",
23251tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
23252let Inst{2-2} = 0b1;
23253let Inst{7-7} = 0b1;
23254let Inst{13-13} = 0b1;
23255let Inst{31-18} = 0b10101111010000;
23256let isPredicated = 1;
23257let isPredicatedFalse = 1;
23258let addrMode = Absolute;
23259let accessSize = HalfWordAccess;
23260let isPredicatedNew = 1;
23261let isExtended = 1;
23262let mayStore = 1;
23263let CextOpcode = "S2_storerh";
23264let BaseOpcode = "S2_storerhabs";
23265let isNVStorable = 1;
23266let DecoderNamespace = "MustExtend";
23267let isExtendable = 1;
23268let opExtendable = 1;
23269let isExtentSigned = 0;
23270let opExtentBits = 6;
23271let opExtentAlign = 0;
23272}
23273def S4_pstorerhfnew_io : HInst<
23274(outs),
23275(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23276"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23277tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23278let Inst{2-2} = 0b0;
23279let Inst{31-21} = 0b01000110010;
23280let isPredicated = 1;
23281let isPredicatedFalse = 1;
23282let addrMode = BaseImmOffset;
23283let accessSize = HalfWordAccess;
23284let isPredicatedNew = 1;
23285let mayStore = 1;
23286let CextOpcode = "S2_storerh";
23287let InputType = "imm";
23288let BaseOpcode = "S2_storerh_io";
23289let isNVStorable = 1;
23290let isExtendable = 1;
23291let opExtendable = 2;
23292let isExtentSigned = 0;
23293let opExtentBits = 7;
23294let opExtentAlign = 1;
23295}
23296def S4_pstorerhfnew_rr : HInst<
23297(outs),
23298(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23299"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23300tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
23301let Inst{31-21} = 0b00110111010;
23302let isPredicated = 1;
23303let isPredicatedFalse = 1;
23304let addrMode = BaseRegOffset;
23305let accessSize = HalfWordAccess;
23306let isPredicatedNew = 1;
23307let mayStore = 1;
23308let CextOpcode = "S2_storerh";
23309let InputType = "reg";
23310let BaseOpcode = "S2_storerh_rr";
23311let isNVStorable = 1;
23312}
23313def S4_pstorerhfnew_zomap : HInst<
23314(outs),
23315(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23316"if (!$Pv4.new) memh($Rs32) = $Rt32",
23317tc_da97ee82, TypeMAPPING> {
23318let isPseudo = 1;
23319let isCodeGenOnly = 1;
23320}
23321def S4_pstorerhnewf_abs : HInst<
23322(outs),
23323(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23324"if (!$Pv4) memh(#$Ii) = $Nt8.new",
23325tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel {
23326let Inst{2-2} = 0b1;
23327let Inst{7-7} = 0b1;
23328let Inst{13-11} = 0b001;
23329let Inst{31-18} = 0b10101111101000;
23330let isPredicated = 1;
23331let isPredicatedFalse = 1;
23332let addrMode = Absolute;
23333let accessSize = HalfWordAccess;
23334let isNVStore = 1;
23335let isNewValue = 1;
23336let isExtended = 1;
23337let isRestrictNoSlot1Store = 1;
23338let mayStore = 1;
23339let CextOpcode = "S2_storerh";
23340let BaseOpcode = "S2_storerhabs";
23341let DecoderNamespace = "MustExtend";
23342let isExtendable = 1;
23343let opExtendable = 1;
23344let isExtentSigned = 0;
23345let opExtentBits = 6;
23346let opExtentAlign = 0;
23347let opNewValue = 2;
23348}
23349def S4_pstorerhnewf_rr : HInst<
23350(outs),
23351(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23352"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23353tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel {
23354let Inst{4-3} = 0b01;
23355let Inst{31-21} = 0b00110101101;
23356let isPredicated = 1;
23357let isPredicatedFalse = 1;
23358let addrMode = BaseRegOffset;
23359let accessSize = HalfWordAccess;
23360let isNVStore = 1;
23361let isNewValue = 1;
23362let isRestrictNoSlot1Store = 1;
23363let mayStore = 1;
23364let CextOpcode = "S2_storerh";
23365let InputType = "reg";
23366let BaseOpcode = "S2_storerh_rr";
23367let opNewValue = 4;
23368}
23369def S4_pstorerhnewfnew_abs : HInst<
23370(outs),
23371(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23372"if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
23373tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel {
23374let Inst{2-2} = 0b1;
23375let Inst{7-7} = 0b1;
23376let Inst{13-11} = 0b101;
23377let Inst{31-18} = 0b10101111101000;
23378let isPredicated = 1;
23379let isPredicatedFalse = 1;
23380let addrMode = Absolute;
23381let accessSize = HalfWordAccess;
23382let isNVStore = 1;
23383let isPredicatedNew = 1;
23384let isNewValue = 1;
23385let isExtended = 1;
23386let isRestrictNoSlot1Store = 1;
23387let mayStore = 1;
23388let CextOpcode = "S2_storerh";
23389let BaseOpcode = "S2_storerhabs";
23390let DecoderNamespace = "MustExtend";
23391let isExtendable = 1;
23392let opExtendable = 1;
23393let isExtentSigned = 0;
23394let opExtentBits = 6;
23395let opExtentAlign = 0;
23396let opNewValue = 2;
23397}
23398def S4_pstorerhnewfnew_io : HInst<
23399(outs),
23400(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23401"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23402tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel {
23403let Inst{2-2} = 0b0;
23404let Inst{12-11} = 0b01;
23405let Inst{31-21} = 0b01000110101;
23406let isPredicated = 1;
23407let isPredicatedFalse = 1;
23408let addrMode = BaseImmOffset;
23409let accessSize = HalfWordAccess;
23410let isNVStore = 1;
23411let isPredicatedNew = 1;
23412let isNewValue = 1;
23413let isRestrictNoSlot1Store = 1;
23414let mayStore = 1;
23415let CextOpcode = "S2_storerh";
23416let InputType = "imm";
23417let BaseOpcode = "S2_storerh_io";
23418let isExtendable = 1;
23419let opExtendable = 2;
23420let isExtentSigned = 0;
23421let opExtentBits = 7;
23422let opExtentAlign = 1;
23423let opNewValue = 3;
23424}
23425def S4_pstorerhnewfnew_rr : HInst<
23426(outs),
23427(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23428"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23429tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel {
23430let Inst{4-3} = 0b01;
23431let Inst{31-21} = 0b00110111101;
23432let isPredicated = 1;
23433let isPredicatedFalse = 1;
23434let addrMode = BaseRegOffset;
23435let accessSize = HalfWordAccess;
23436let isNVStore = 1;
23437let isPredicatedNew = 1;
23438let isNewValue = 1;
23439let isRestrictNoSlot1Store = 1;
23440let mayStore = 1;
23441let CextOpcode = "S2_storerh";
23442let InputType = "reg";
23443let BaseOpcode = "S2_storerh_rr";
23444let opNewValue = 4;
23445}
23446def S4_pstorerhnewfnew_zomap : HInst<
23447(outs),
23448(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23449"if (!$Pv4.new) memh($Rs32) = $Nt8.new",
23450tc_c79a189f, TypeMAPPING> {
23451let isPseudo = 1;
23452let isCodeGenOnly = 1;
23453let opNewValue = 2;
23454}
23455def S4_pstorerhnewt_abs : HInst<
23456(outs),
23457(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23458"if ($Pv4) memh(#$Ii) = $Nt8.new",
23459tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel {
23460let Inst{2-2} = 0b0;
23461let Inst{7-7} = 0b1;
23462let Inst{13-11} = 0b001;
23463let Inst{31-18} = 0b10101111101000;
23464let isPredicated = 1;
23465let addrMode = Absolute;
23466let accessSize = HalfWordAccess;
23467let isNVStore = 1;
23468let isNewValue = 1;
23469let isExtended = 1;
23470let isRestrictNoSlot1Store = 1;
23471let mayStore = 1;
23472let CextOpcode = "S2_storerh";
23473let BaseOpcode = "S2_storerhabs";
23474let DecoderNamespace = "MustExtend";
23475let isExtendable = 1;
23476let opExtendable = 1;
23477let isExtentSigned = 0;
23478let opExtentBits = 6;
23479let opExtentAlign = 0;
23480let opNewValue = 2;
23481}
23482def S4_pstorerhnewt_rr : HInst<
23483(outs),
23484(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23485"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23486tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel {
23487let Inst{4-3} = 0b01;
23488let Inst{31-21} = 0b00110100101;
23489let isPredicated = 1;
23490let addrMode = BaseRegOffset;
23491let accessSize = HalfWordAccess;
23492let isNVStore = 1;
23493let isNewValue = 1;
23494let isRestrictNoSlot1Store = 1;
23495let mayStore = 1;
23496let CextOpcode = "S2_storerh";
23497let InputType = "reg";
23498let BaseOpcode = "S2_storerh_rr";
23499let opNewValue = 4;
23500}
23501def S4_pstorerhnewtnew_abs : HInst<
23502(outs),
23503(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23504"if ($Pv4.new) memh(#$Ii) = $Nt8.new",
23505tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel {
23506let Inst{2-2} = 0b0;
23507let Inst{7-7} = 0b1;
23508let Inst{13-11} = 0b101;
23509let Inst{31-18} = 0b10101111101000;
23510let isPredicated = 1;
23511let addrMode = Absolute;
23512let accessSize = HalfWordAccess;
23513let isNVStore = 1;
23514let isPredicatedNew = 1;
23515let isNewValue = 1;
23516let isExtended = 1;
23517let isRestrictNoSlot1Store = 1;
23518let mayStore = 1;
23519let CextOpcode = "S2_storerh";
23520let BaseOpcode = "S2_storerhabs";
23521let DecoderNamespace = "MustExtend";
23522let isExtendable = 1;
23523let opExtendable = 1;
23524let isExtentSigned = 0;
23525let opExtentBits = 6;
23526let opExtentAlign = 0;
23527let opNewValue = 2;
23528}
23529def S4_pstorerhnewtnew_io : HInst<
23530(outs),
23531(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23532"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23533tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel {
23534let Inst{2-2} = 0b0;
23535let Inst{12-11} = 0b01;
23536let Inst{31-21} = 0b01000010101;
23537let isPredicated = 1;
23538let addrMode = BaseImmOffset;
23539let accessSize = HalfWordAccess;
23540let isNVStore = 1;
23541let isPredicatedNew = 1;
23542let isNewValue = 1;
23543let isRestrictNoSlot1Store = 1;
23544let mayStore = 1;
23545let CextOpcode = "S2_storerh";
23546let InputType = "imm";
23547let BaseOpcode = "S2_storerh_io";
23548let isExtendable = 1;
23549let opExtendable = 2;
23550let isExtentSigned = 0;
23551let opExtentBits = 7;
23552let opExtentAlign = 1;
23553let opNewValue = 3;
23554}
23555def S4_pstorerhnewtnew_rr : HInst<
23556(outs),
23557(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23558"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23559tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel {
23560let Inst{4-3} = 0b01;
23561let Inst{31-21} = 0b00110110101;
23562let isPredicated = 1;
23563let addrMode = BaseRegOffset;
23564let accessSize = HalfWordAccess;
23565let isNVStore = 1;
23566let isPredicatedNew = 1;
23567let isNewValue = 1;
23568let isRestrictNoSlot1Store = 1;
23569let mayStore = 1;
23570let CextOpcode = "S2_storerh";
23571let InputType = "reg";
23572let BaseOpcode = "S2_storerh_rr";
23573let opNewValue = 4;
23574}
23575def S4_pstorerhnewtnew_zomap : HInst<
23576(outs),
23577(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23578"if ($Pv4.new) memh($Rs32) = $Nt8.new",
23579tc_c79a189f, TypeMAPPING> {
23580let isPseudo = 1;
23581let isCodeGenOnly = 1;
23582let opNewValue = 2;
23583}
23584def S4_pstorerht_abs : HInst<
23585(outs),
23586(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23587"if ($Pv4) memh(#$Ii) = $Rt32",
23588tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
23589let Inst{2-2} = 0b0;
23590let Inst{7-7} = 0b1;
23591let Inst{13-13} = 0b0;
23592let Inst{31-18} = 0b10101111010000;
23593let isPredicated = 1;
23594let addrMode = Absolute;
23595let accessSize = HalfWordAccess;
23596let isExtended = 1;
23597let mayStore = 1;
23598let CextOpcode = "S2_storerh";
23599let BaseOpcode = "S2_storerhabs";
23600let isNVStorable = 1;
23601let DecoderNamespace = "MustExtend";
23602let isExtendable = 1;
23603let opExtendable = 1;
23604let isExtentSigned = 0;
23605let opExtentBits = 6;
23606let opExtentAlign = 0;
23607}
23608def S4_pstorerht_rr : HInst<
23609(outs),
23610(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23611"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23612tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
23613let Inst{31-21} = 0b00110100010;
23614let isPredicated = 1;
23615let addrMode = BaseRegOffset;
23616let accessSize = HalfWordAccess;
23617let mayStore = 1;
23618let CextOpcode = "S2_storerh";
23619let InputType = "reg";
23620let BaseOpcode = "S2_storerh_rr";
23621let isNVStorable = 1;
23622}
23623def S4_pstorerhtnew_abs : HInst<
23624(outs),
23625(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23626"if ($Pv4.new) memh(#$Ii) = $Rt32",
23627tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
23628let Inst{2-2} = 0b0;
23629let Inst{7-7} = 0b1;
23630let Inst{13-13} = 0b1;
23631let Inst{31-18} = 0b10101111010000;
23632let isPredicated = 1;
23633let addrMode = Absolute;
23634let accessSize = HalfWordAccess;
23635let isPredicatedNew = 1;
23636let isExtended = 1;
23637let mayStore = 1;
23638let CextOpcode = "S2_storerh";
23639let BaseOpcode = "S2_storerhabs";
23640let isNVStorable = 1;
23641let DecoderNamespace = "MustExtend";
23642let isExtendable = 1;
23643let opExtendable = 1;
23644let isExtentSigned = 0;
23645let opExtentBits = 6;
23646let opExtentAlign = 0;
23647}
23648def S4_pstorerhtnew_io : HInst<
23649(outs),
23650(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23651"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23652tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23653let Inst{2-2} = 0b0;
23654let Inst{31-21} = 0b01000010010;
23655let isPredicated = 1;
23656let addrMode = BaseImmOffset;
23657let accessSize = HalfWordAccess;
23658let isPredicatedNew = 1;
23659let mayStore = 1;
23660let CextOpcode = "S2_storerh";
23661let InputType = "imm";
23662let BaseOpcode = "S2_storerh_io";
23663let isNVStorable = 1;
23664let isExtendable = 1;
23665let opExtendable = 2;
23666let isExtentSigned = 0;
23667let opExtentBits = 7;
23668let opExtentAlign = 1;
23669}
23670def S4_pstorerhtnew_rr : HInst<
23671(outs),
23672(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23673"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23674tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
23675let Inst{31-21} = 0b00110110010;
23676let isPredicated = 1;
23677let addrMode = BaseRegOffset;
23678let accessSize = HalfWordAccess;
23679let isPredicatedNew = 1;
23680let mayStore = 1;
23681let CextOpcode = "S2_storerh";
23682let InputType = "reg";
23683let BaseOpcode = "S2_storerh_rr";
23684let isNVStorable = 1;
23685}
23686def S4_pstorerhtnew_zomap : HInst<
23687(outs),
23688(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23689"if ($Pv4.new) memh($Rs32) = $Rt32",
23690tc_da97ee82, TypeMAPPING> {
23691let isPseudo = 1;
23692let isCodeGenOnly = 1;
23693}
23694def S4_pstorerif_abs : HInst<
23695(outs),
23696(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23697"if (!$Pv4) memw(#$Ii) = $Rt32",
23698tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
23699let Inst{2-2} = 0b1;
23700let Inst{7-7} = 0b1;
23701let Inst{13-13} = 0b0;
23702let Inst{31-18} = 0b10101111100000;
23703let isPredicated = 1;
23704let isPredicatedFalse = 1;
23705let addrMode = Absolute;
23706let accessSize = WordAccess;
23707let isExtended = 1;
23708let mayStore = 1;
23709let CextOpcode = "S2_storeri";
23710let BaseOpcode = "S2_storeriabs";
23711let isNVStorable = 1;
23712let DecoderNamespace = "MustExtend";
23713let isExtendable = 1;
23714let opExtendable = 1;
23715let isExtentSigned = 0;
23716let opExtentBits = 6;
23717let opExtentAlign = 0;
23718}
23719def S4_pstorerif_rr : HInst<
23720(outs),
23721(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23722"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
23723tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
23724let Inst{31-21} = 0b00110101100;
23725let isPredicated = 1;
23726let isPredicatedFalse = 1;
23727let addrMode = BaseRegOffset;
23728let accessSize = WordAccess;
23729let mayStore = 1;
23730let CextOpcode = "S2_storeri";
23731let InputType = "reg";
23732let BaseOpcode = "S2_storeri_rr";
23733let isNVStorable = 1;
23734}
23735def S4_pstorerifnew_abs : HInst<
23736(outs),
23737(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23738"if (!$Pv4.new) memw(#$Ii) = $Rt32",
23739tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
23740let Inst{2-2} = 0b1;
23741let Inst{7-7} = 0b1;
23742let Inst{13-13} = 0b1;
23743let Inst{31-18} = 0b10101111100000;
23744let isPredicated = 1;
23745let isPredicatedFalse = 1;
23746let addrMode = Absolute;
23747let accessSize = WordAccess;
23748let isPredicatedNew = 1;
23749let isExtended = 1;
23750let mayStore = 1;
23751let CextOpcode = "S2_storeri";
23752let BaseOpcode = "S2_storeriabs";
23753let isNVStorable = 1;
23754let DecoderNamespace = "MustExtend";
23755let isExtendable = 1;
23756let opExtendable = 1;
23757let isExtentSigned = 0;
23758let opExtentBits = 6;
23759let opExtentAlign = 0;
23760}
23761def S4_pstorerifnew_io : HInst<
23762(outs),
23763(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
23764"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
23765tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel {
23766let Inst{2-2} = 0b0;
23767let Inst{31-21} = 0b01000110100;
23768let isPredicated = 1;
23769let isPredicatedFalse = 1;
23770let addrMode = BaseImmOffset;
23771let accessSize = WordAccess;
23772let isPredicatedNew = 1;
23773let mayStore = 1;
23774let CextOpcode = "S2_storeri";
23775let InputType = "imm";
23776let BaseOpcode = "S2_storeri_io";
23777let isNVStorable = 1;
23778let isExtendable = 1;
23779let opExtendable = 2;
23780let isExtentSigned = 0;
23781let opExtentBits = 8;
23782let opExtentAlign = 2;
23783}
23784def S4_pstorerifnew_rr : HInst<
23785(outs),
23786(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23787"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
23788tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
23789let Inst{31-21} = 0b00110111100;
23790let isPredicated = 1;
23791let isPredicatedFalse = 1;
23792let addrMode = BaseRegOffset;
23793let accessSize = WordAccess;
23794let isPredicatedNew = 1;
23795let mayStore = 1;
23796let CextOpcode = "S2_storeri";
23797let InputType = "reg";
23798let BaseOpcode = "S2_storeri_rr";
23799let isNVStorable = 1;
23800}
23801def S4_pstorerifnew_zomap : HInst<
23802(outs),
23803(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23804"if (!$Pv4.new) memw($Rs32) = $Rt32",
23805tc_da97ee82, TypeMAPPING> {
23806let isPseudo = 1;
23807let isCodeGenOnly = 1;
23808}
23809def S4_pstorerinewf_abs : HInst<
23810(outs),
23811(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23812"if (!$Pv4) memw(#$Ii) = $Nt8.new",
23813tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel {
23814let Inst{2-2} = 0b1;
23815let Inst{7-7} = 0b1;
23816let Inst{13-11} = 0b010;
23817let Inst{31-18} = 0b10101111101000;
23818let isPredicated = 1;
23819let isPredicatedFalse = 1;
23820let addrMode = Absolute;
23821let accessSize = WordAccess;
23822let isNVStore = 1;
23823let isNewValue = 1;
23824let isExtended = 1;
23825let isRestrictNoSlot1Store = 1;
23826let mayStore = 1;
23827let CextOpcode = "S2_storeri";
23828let BaseOpcode = "S2_storeriabs";
23829let DecoderNamespace = "MustExtend";
23830let isExtendable = 1;
23831let opExtendable = 1;
23832let isExtentSigned = 0;
23833let opExtentBits = 6;
23834let opExtentAlign = 0;
23835let opNewValue = 2;
23836}
23837def S4_pstorerinewf_rr : HInst<
23838(outs),
23839(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23840"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23841tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel {
23842let Inst{4-3} = 0b10;
23843let Inst{31-21} = 0b00110101101;
23844let isPredicated = 1;
23845let isPredicatedFalse = 1;
23846let addrMode = BaseRegOffset;
23847let accessSize = WordAccess;
23848let isNVStore = 1;
23849let isNewValue = 1;
23850let isRestrictNoSlot1Store = 1;
23851let mayStore = 1;
23852let CextOpcode = "S2_storeri";
23853let InputType = "reg";
23854let BaseOpcode = "S2_storeri_rr";
23855let opNewValue = 4;
23856}
23857def S4_pstorerinewfnew_abs : HInst<
23858(outs),
23859(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23860"if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
23861tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel {
23862let Inst{2-2} = 0b1;
23863let Inst{7-7} = 0b1;
23864let Inst{13-11} = 0b110;
23865let Inst{31-18} = 0b10101111101000;
23866let isPredicated = 1;
23867let isPredicatedFalse = 1;
23868let addrMode = Absolute;
23869let accessSize = WordAccess;
23870let isNVStore = 1;
23871let isPredicatedNew = 1;
23872let isNewValue = 1;
23873let isExtended = 1;
23874let isRestrictNoSlot1Store = 1;
23875let mayStore = 1;
23876let CextOpcode = "S2_storeri";
23877let BaseOpcode = "S2_storeriabs";
23878let DecoderNamespace = "MustExtend";
23879let isExtendable = 1;
23880let opExtendable = 1;
23881let isExtentSigned = 0;
23882let opExtentBits = 6;
23883let opExtentAlign = 0;
23884let opNewValue = 2;
23885}
23886def S4_pstorerinewfnew_io : HInst<
23887(outs),
23888(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
23889"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
23890tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
23891let Inst{2-2} = 0b0;
23892let Inst{12-11} = 0b10;
23893let Inst{31-21} = 0b01000110101;
23894let isPredicated = 1;
23895let isPredicatedFalse = 1;
23896let addrMode = BaseImmOffset;
23897let accessSize = WordAccess;
23898let isNVStore = 1;
23899let isPredicatedNew = 1;
23900let isNewValue = 1;
23901let isRestrictNoSlot1Store = 1;
23902let mayStore = 1;
23903let CextOpcode = "S2_storeri";
23904let InputType = "imm";
23905let BaseOpcode = "S2_storeri_io";
23906let isExtendable = 1;
23907let opExtendable = 2;
23908let isExtentSigned = 0;
23909let opExtentBits = 8;
23910let opExtentAlign = 2;
23911let opNewValue = 3;
23912}
23913def S4_pstorerinewfnew_rr : HInst<
23914(outs),
23915(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23916"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23917tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel {
23918let Inst{4-3} = 0b10;
23919let Inst{31-21} = 0b00110111101;
23920let isPredicated = 1;
23921let isPredicatedFalse = 1;
23922let addrMode = BaseRegOffset;
23923let accessSize = WordAccess;
23924let isNVStore = 1;
23925let isPredicatedNew = 1;
23926let isNewValue = 1;
23927let isRestrictNoSlot1Store = 1;
23928let mayStore = 1;
23929let CextOpcode = "S2_storeri";
23930let InputType = "reg";
23931let BaseOpcode = "S2_storeri_rr";
23932let opNewValue = 4;
23933}
23934def S4_pstorerinewfnew_zomap : HInst<
23935(outs),
23936(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23937"if (!$Pv4.new) memw($Rs32) = $Nt8.new",
23938tc_c79a189f, TypeMAPPING> {
23939let isPseudo = 1;
23940let isCodeGenOnly = 1;
23941let opNewValue = 2;
23942}
23943def S4_pstorerinewt_abs : HInst<
23944(outs),
23945(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23946"if ($Pv4) memw(#$Ii) = $Nt8.new",
23947tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel {
23948let Inst{2-2} = 0b0;
23949let Inst{7-7} = 0b1;
23950let Inst{13-11} = 0b010;
23951let Inst{31-18} = 0b10101111101000;
23952let isPredicated = 1;
23953let addrMode = Absolute;
23954let accessSize = WordAccess;
23955let isNVStore = 1;
23956let isNewValue = 1;
23957let isExtended = 1;
23958let isRestrictNoSlot1Store = 1;
23959let mayStore = 1;
23960let CextOpcode = "S2_storeri";
23961let BaseOpcode = "S2_storeriabs";
23962let DecoderNamespace = "MustExtend";
23963let isExtendable = 1;
23964let opExtendable = 1;
23965let isExtentSigned = 0;
23966let opExtentBits = 6;
23967let opExtentAlign = 0;
23968let opNewValue = 2;
23969}
23970def S4_pstorerinewt_rr : HInst<
23971(outs),
23972(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23973"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23974tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel {
23975let Inst{4-3} = 0b10;
23976let Inst{31-21} = 0b00110100101;
23977let isPredicated = 1;
23978let addrMode = BaseRegOffset;
23979let accessSize = WordAccess;
23980let isNVStore = 1;
23981let isNewValue = 1;
23982let isRestrictNoSlot1Store = 1;
23983let mayStore = 1;
23984let CextOpcode = "S2_storeri";
23985let InputType = "reg";
23986let BaseOpcode = "S2_storeri_rr";
23987let opNewValue = 4;
23988}
23989def S4_pstorerinewtnew_abs : HInst<
23990(outs),
23991(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23992"if ($Pv4.new) memw(#$Ii) = $Nt8.new",
23993tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel {
23994let Inst{2-2} = 0b0;
23995let Inst{7-7} = 0b1;
23996let Inst{13-11} = 0b110;
23997let Inst{31-18} = 0b10101111101000;
23998let isPredicated = 1;
23999let addrMode = Absolute;
24000let accessSize = WordAccess;
24001let isNVStore = 1;
24002let isPredicatedNew = 1;
24003let isNewValue = 1;
24004let isExtended = 1;
24005let isRestrictNoSlot1Store = 1;
24006let mayStore = 1;
24007let CextOpcode = "S2_storeri";
24008let BaseOpcode = "S2_storeriabs";
24009let DecoderNamespace = "MustExtend";
24010let isExtendable = 1;
24011let opExtendable = 1;
24012let isExtentSigned = 0;
24013let opExtentBits = 6;
24014let opExtentAlign = 0;
24015let opNewValue = 2;
24016}
24017def S4_pstorerinewtnew_io : HInst<
24018(outs),
24019(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24020"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24021tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24022let Inst{2-2} = 0b0;
24023let Inst{12-11} = 0b10;
24024let Inst{31-21} = 0b01000010101;
24025let isPredicated = 1;
24026let addrMode = BaseImmOffset;
24027let accessSize = WordAccess;
24028let isNVStore = 1;
24029let isPredicatedNew = 1;
24030let isNewValue = 1;
24031let isRestrictNoSlot1Store = 1;
24032let mayStore = 1;
24033let CextOpcode = "S2_storeri";
24034let InputType = "imm";
24035let BaseOpcode = "S2_storeri_io";
24036let isExtendable = 1;
24037let opExtendable = 2;
24038let isExtentSigned = 0;
24039let opExtentBits = 8;
24040let opExtentAlign = 2;
24041let opNewValue = 3;
24042}
24043def S4_pstorerinewtnew_rr : HInst<
24044(outs),
24045(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24046"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24047tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel {
24048let Inst{4-3} = 0b10;
24049let Inst{31-21} = 0b00110110101;
24050let isPredicated = 1;
24051let addrMode = BaseRegOffset;
24052let accessSize = WordAccess;
24053let isNVStore = 1;
24054let isPredicatedNew = 1;
24055let isNewValue = 1;
24056let isRestrictNoSlot1Store = 1;
24057let mayStore = 1;
24058let CextOpcode = "S2_storeri";
24059let InputType = "reg";
24060let BaseOpcode = "S2_storeri_rr";
24061let opNewValue = 4;
24062}
24063def S4_pstorerinewtnew_zomap : HInst<
24064(outs),
24065(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24066"if ($Pv4.new) memw($Rs32) = $Nt8.new",
24067tc_c79a189f, TypeMAPPING> {
24068let isPseudo = 1;
24069let isCodeGenOnly = 1;
24070let opNewValue = 2;
24071}
24072def S4_pstorerit_abs : HInst<
24073(outs),
24074(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24075"if ($Pv4) memw(#$Ii) = $Rt32",
24076tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel {
24077let Inst{2-2} = 0b0;
24078let Inst{7-7} = 0b1;
24079let Inst{13-13} = 0b0;
24080let Inst{31-18} = 0b10101111100000;
24081let isPredicated = 1;
24082let addrMode = Absolute;
24083let accessSize = WordAccess;
24084let isExtended = 1;
24085let mayStore = 1;
24086let CextOpcode = "S2_storeri";
24087let BaseOpcode = "S2_storeriabs";
24088let isNVStorable = 1;
24089let DecoderNamespace = "MustExtend";
24090let isExtendable = 1;
24091let opExtendable = 1;
24092let isExtentSigned = 0;
24093let opExtentBits = 6;
24094let opExtentAlign = 0;
24095}
24096def S4_pstorerit_rr : HInst<
24097(outs),
24098(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24099"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24100tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel {
24101let Inst{31-21} = 0b00110100100;
24102let isPredicated = 1;
24103let addrMode = BaseRegOffset;
24104let accessSize = WordAccess;
24105let mayStore = 1;
24106let CextOpcode = "S2_storeri";
24107let InputType = "reg";
24108let BaseOpcode = "S2_storeri_rr";
24109let isNVStorable = 1;
24110}
24111def S4_pstoreritnew_abs : HInst<
24112(outs),
24113(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24114"if ($Pv4.new) memw(#$Ii) = $Rt32",
24115tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel {
24116let Inst{2-2} = 0b0;
24117let Inst{7-7} = 0b1;
24118let Inst{13-13} = 0b1;
24119let Inst{31-18} = 0b10101111100000;
24120let isPredicated = 1;
24121let addrMode = Absolute;
24122let accessSize = WordAccess;
24123let isPredicatedNew = 1;
24124let isExtended = 1;
24125let mayStore = 1;
24126let CextOpcode = "S2_storeri";
24127let BaseOpcode = "S2_storeriabs";
24128let isNVStorable = 1;
24129let DecoderNamespace = "MustExtend";
24130let isExtendable = 1;
24131let opExtendable = 1;
24132let isExtentSigned = 0;
24133let opExtentBits = 6;
24134let opExtentAlign = 0;
24135}
24136def S4_pstoreritnew_io : HInst<
24137(outs),
24138(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24139"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24140tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel {
24141let Inst{2-2} = 0b0;
24142let Inst{31-21} = 0b01000010100;
24143let isPredicated = 1;
24144let addrMode = BaseImmOffset;
24145let accessSize = WordAccess;
24146let isPredicatedNew = 1;
24147let mayStore = 1;
24148let CextOpcode = "S2_storeri";
24149let InputType = "imm";
24150let BaseOpcode = "S2_storeri_io";
24151let isNVStorable = 1;
24152let isExtendable = 1;
24153let opExtendable = 2;
24154let isExtentSigned = 0;
24155let opExtentBits = 8;
24156let opExtentAlign = 2;
24157}
24158def S4_pstoreritnew_rr : HInst<
24159(outs),
24160(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24161"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24162tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel {
24163let Inst{31-21} = 0b00110110100;
24164let isPredicated = 1;
24165let addrMode = BaseRegOffset;
24166let accessSize = WordAccess;
24167let isPredicatedNew = 1;
24168let mayStore = 1;
24169let CextOpcode = "S2_storeri";
24170let InputType = "reg";
24171let BaseOpcode = "S2_storeri_rr";
24172let isNVStorable = 1;
24173}
24174def S4_pstoreritnew_zomap : HInst<
24175(outs),
24176(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24177"if ($Pv4.new) memw($Rs32) = $Rt32",
24178tc_da97ee82, TypeMAPPING> {
24179let isPseudo = 1;
24180let isCodeGenOnly = 1;
24181}
24182def S4_stored_locked : HInst<
24183(outs PredRegs:$Pd4),
24184(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24185"memd_locked($Rs32,$Pd4) = $Rtt32",
24186tc_5abb5e3f, TypeST>, Enc_d7dc10 {
24187let Inst{7-2} = 0b000000;
24188let Inst{13-13} = 0b0;
24189let Inst{31-21} = 0b10100000111;
24190let accessSize = DoubleWordAccess;
24191let isPredicateLate = 1;
24192let isSoloAX = 1;
24193let mayStore = 1;
24194}
24195def S4_storeirb_io : HInst<
24196(outs),
24197(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24198"memb($Rs32+#$Ii) = #$II",
24199tc_b83e6d73, TypeST>, Enc_8203bb, PredNewRel {
24200let Inst{31-21} = 0b00111100000;
24201let addrMode = BaseImmOffset;
24202let accessSize = ByteAccess;
24203let mayStore = 1;
24204let CextOpcode = "S2_storerb";
24205let InputType = "imm";
24206let BaseOpcode = "S4_storeirb_io";
24207let isPredicable = 1;
24208let isExtendable = 1;
24209let opExtendable = 2;
24210let isExtentSigned = 1;
24211let opExtentBits = 8;
24212let opExtentAlign = 0;
24213}
24214def S4_storeirb_zomap : HInst<
24215(outs),
24216(ins IntRegs:$Rs32, s8_0Imm:$II),
24217"memb($Rs32) = #$II",
24218tc_b83e6d73, TypeMAPPING> {
24219let isPseudo = 1;
24220let isCodeGenOnly = 1;
24221}
24222def S4_storeirbf_io : HInst<
24223(outs),
24224(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24225"if (!$Pv4) memb($Rs32+#$Ii) = #$II",
24226tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel {
24227let Inst{31-21} = 0b00111000100;
24228let isPredicated = 1;
24229let isPredicatedFalse = 1;
24230let addrMode = BaseImmOffset;
24231let accessSize = ByteAccess;
24232let mayStore = 1;
24233let CextOpcode = "S2_storerb";
24234let InputType = "imm";
24235let BaseOpcode = "S4_storeirb_io";
24236let isExtendable = 1;
24237let opExtendable = 3;
24238let isExtentSigned = 1;
24239let opExtentBits = 6;
24240let opExtentAlign = 0;
24241}
24242def S4_storeirbf_zomap : HInst<
24243(outs),
24244(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24245"if (!$Pv4) memb($Rs32) = #$II",
24246tc_0b2be201, TypeMAPPING> {
24247let isPseudo = 1;
24248let isCodeGenOnly = 1;
24249}
24250def S4_storeirbfnew_io : HInst<
24251(outs),
24252(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24253"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
24254tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel {
24255let Inst{31-21} = 0b00111001100;
24256let isPredicated = 1;
24257let isPredicatedFalse = 1;
24258let addrMode = BaseImmOffset;
24259let accessSize = ByteAccess;
24260let isPredicatedNew = 1;
24261let mayStore = 1;
24262let CextOpcode = "S2_storerb";
24263let InputType = "imm";
24264let BaseOpcode = "S4_storeirb_io";
24265let isExtendable = 1;
24266let opExtendable = 3;
24267let isExtentSigned = 1;
24268let opExtentBits = 6;
24269let opExtentAlign = 0;
24270}
24271def S4_storeirbfnew_zomap : HInst<
24272(outs),
24273(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24274"if (!$Pv4.new) memb($Rs32) = #$II",
24275tc_c4f596e3, TypeMAPPING> {
24276let isPseudo = 1;
24277let isCodeGenOnly = 1;
24278}
24279def S4_storeirbt_io : HInst<
24280(outs),
24281(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24282"if ($Pv4) memb($Rs32+#$Ii) = #$II",
24283tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel {
24284let Inst{31-21} = 0b00111000000;
24285let isPredicated = 1;
24286let addrMode = BaseImmOffset;
24287let accessSize = ByteAccess;
24288let mayStore = 1;
24289let CextOpcode = "S2_storerb";
24290let InputType = "imm";
24291let BaseOpcode = "S4_storeirb_io";
24292let isExtendable = 1;
24293let opExtendable = 3;
24294let isExtentSigned = 1;
24295let opExtentBits = 6;
24296let opExtentAlign = 0;
24297}
24298def S4_storeirbt_zomap : HInst<
24299(outs),
24300(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24301"if ($Pv4) memb($Rs32) = #$II",
24302tc_0b2be201, TypeMAPPING> {
24303let isPseudo = 1;
24304let isCodeGenOnly = 1;
24305}
24306def S4_storeirbtnew_io : HInst<
24307(outs),
24308(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24309"if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
24310tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel {
24311let Inst{31-21} = 0b00111001000;
24312let isPredicated = 1;
24313let addrMode = BaseImmOffset;
24314let accessSize = ByteAccess;
24315let isPredicatedNew = 1;
24316let mayStore = 1;
24317let CextOpcode = "S2_storerb";
24318let InputType = "imm";
24319let BaseOpcode = "S4_storeirb_io";
24320let isExtendable = 1;
24321let opExtendable = 3;
24322let isExtentSigned = 1;
24323let opExtentBits = 6;
24324let opExtentAlign = 0;
24325}
24326def S4_storeirbtnew_zomap : HInst<
24327(outs),
24328(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24329"if ($Pv4.new) memb($Rs32) = #$II",
24330tc_c4f596e3, TypeMAPPING> {
24331let isPseudo = 1;
24332let isCodeGenOnly = 1;
24333}
24334def S4_storeirh_io : HInst<
24335(outs),
24336(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24337"memh($Rs32+#$Ii) = #$II",
24338tc_b83e6d73, TypeST>, Enc_a803e0, PredNewRel {
24339let Inst{31-21} = 0b00111100001;
24340let addrMode = BaseImmOffset;
24341let accessSize = HalfWordAccess;
24342let mayStore = 1;
24343let CextOpcode = "S2_storerh";
24344let InputType = "imm";
24345let BaseOpcode = "S4_storeirh_io";
24346let isPredicable = 1;
24347let isExtendable = 1;
24348let opExtendable = 2;
24349let isExtentSigned = 1;
24350let opExtentBits = 8;
24351let opExtentAlign = 0;
24352}
24353def S4_storeirh_zomap : HInst<
24354(outs),
24355(ins IntRegs:$Rs32, s8_0Imm:$II),
24356"memh($Rs32) = #$II",
24357tc_b83e6d73, TypeMAPPING> {
24358let isPseudo = 1;
24359let isCodeGenOnly = 1;
24360}
24361def S4_storeirhf_io : HInst<
24362(outs),
24363(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24364"if (!$Pv4) memh($Rs32+#$Ii) = #$II",
24365tc_0b2be201, TypeST>, Enc_f20719, PredNewRel {
24366let Inst{31-21} = 0b00111000101;
24367let isPredicated = 1;
24368let isPredicatedFalse = 1;
24369let addrMode = BaseImmOffset;
24370let accessSize = HalfWordAccess;
24371let mayStore = 1;
24372let CextOpcode = "S2_storerh";
24373let InputType = "imm";
24374let BaseOpcode = "S4_storeirh_io";
24375let isExtendable = 1;
24376let opExtendable = 3;
24377let isExtentSigned = 1;
24378let opExtentBits = 6;
24379let opExtentAlign = 0;
24380}
24381def S4_storeirhf_zomap : HInst<
24382(outs),
24383(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24384"if (!$Pv4) memh($Rs32) = #$II",
24385tc_0b2be201, TypeMAPPING> {
24386let isPseudo = 1;
24387let isCodeGenOnly = 1;
24388}
24389def S4_storeirhfnew_io : HInst<
24390(outs),
24391(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24392"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
24393tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel {
24394let Inst{31-21} = 0b00111001101;
24395let isPredicated = 1;
24396let isPredicatedFalse = 1;
24397let addrMode = BaseImmOffset;
24398let accessSize = HalfWordAccess;
24399let isPredicatedNew = 1;
24400let mayStore = 1;
24401let CextOpcode = "S2_storerh";
24402let InputType = "imm";
24403let BaseOpcode = "S4_storeirh_io";
24404let isExtendable = 1;
24405let opExtendable = 3;
24406let isExtentSigned = 1;
24407let opExtentBits = 6;
24408let opExtentAlign = 0;
24409}
24410def S4_storeirhfnew_zomap : HInst<
24411(outs),
24412(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24413"if (!$Pv4.new) memh($Rs32) = #$II",
24414tc_c4f596e3, TypeMAPPING> {
24415let isPseudo = 1;
24416let isCodeGenOnly = 1;
24417}
24418def S4_storeirht_io : HInst<
24419(outs),
24420(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24421"if ($Pv4) memh($Rs32+#$Ii) = #$II",
24422tc_0b2be201, TypeST>, Enc_f20719, PredNewRel {
24423let Inst{31-21} = 0b00111000001;
24424let isPredicated = 1;
24425let addrMode = BaseImmOffset;
24426let accessSize = HalfWordAccess;
24427let mayStore = 1;
24428let CextOpcode = "S2_storerh";
24429let InputType = "imm";
24430let BaseOpcode = "S4_storeirh_io";
24431let isExtendable = 1;
24432let opExtendable = 3;
24433let isExtentSigned = 1;
24434let opExtentBits = 6;
24435let opExtentAlign = 0;
24436}
24437def S4_storeirht_zomap : HInst<
24438(outs),
24439(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24440"if ($Pv4) memh($Rs32) = #$II",
24441tc_0b2be201, TypeMAPPING> {
24442let isPseudo = 1;
24443let isCodeGenOnly = 1;
24444}
24445def S4_storeirhtnew_io : HInst<
24446(outs),
24447(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24448"if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
24449tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel {
24450let Inst{31-21} = 0b00111001001;
24451let isPredicated = 1;
24452let addrMode = BaseImmOffset;
24453let accessSize = HalfWordAccess;
24454let isPredicatedNew = 1;
24455let mayStore = 1;
24456let CextOpcode = "S2_storerh";
24457let InputType = "imm";
24458let BaseOpcode = "S4_storeirh_io";
24459let isExtendable = 1;
24460let opExtendable = 3;
24461let isExtentSigned = 1;
24462let opExtentBits = 6;
24463let opExtentAlign = 0;
24464}
24465def S4_storeirhtnew_zomap : HInst<
24466(outs),
24467(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24468"if ($Pv4.new) memh($Rs32) = #$II",
24469tc_c4f596e3, TypeMAPPING> {
24470let isPseudo = 1;
24471let isCodeGenOnly = 1;
24472}
24473def S4_storeiri_io : HInst<
24474(outs),
24475(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24476"memw($Rs32+#$Ii) = #$II",
24477tc_b83e6d73, TypeST>, Enc_f37377, PredNewRel {
24478let Inst{31-21} = 0b00111100010;
24479let addrMode = BaseImmOffset;
24480let accessSize = WordAccess;
24481let mayStore = 1;
24482let CextOpcode = "S2_storeri";
24483let InputType = "imm";
24484let BaseOpcode = "S4_storeiri_io";
24485let isPredicable = 1;
24486let isExtendable = 1;
24487let opExtendable = 2;
24488let isExtentSigned = 1;
24489let opExtentBits = 8;
24490let opExtentAlign = 0;
24491}
24492def S4_storeiri_zomap : HInst<
24493(outs),
24494(ins IntRegs:$Rs32, s8_0Imm:$II),
24495"memw($Rs32) = #$II",
24496tc_b83e6d73, TypeMAPPING> {
24497let isPseudo = 1;
24498let isCodeGenOnly = 1;
24499}
24500def S4_storeirif_io : HInst<
24501(outs),
24502(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24503"if (!$Pv4) memw($Rs32+#$Ii) = #$II",
24504tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel {
24505let Inst{31-21} = 0b00111000110;
24506let isPredicated = 1;
24507let isPredicatedFalse = 1;
24508let addrMode = BaseImmOffset;
24509let accessSize = WordAccess;
24510let mayStore = 1;
24511let CextOpcode = "S2_storeri";
24512let InputType = "imm";
24513let BaseOpcode = "S4_storeiri_io";
24514let isExtendable = 1;
24515let opExtendable = 3;
24516let isExtentSigned = 1;
24517let opExtentBits = 6;
24518let opExtentAlign = 0;
24519}
24520def S4_storeirif_zomap : HInst<
24521(outs),
24522(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24523"if (!$Pv4) memw($Rs32) = #$II",
24524tc_0b2be201, TypeMAPPING> {
24525let isPseudo = 1;
24526let isCodeGenOnly = 1;
24527}
24528def S4_storeirifnew_io : HInst<
24529(outs),
24530(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24531"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
24532tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel {
24533let Inst{31-21} = 0b00111001110;
24534let isPredicated = 1;
24535let isPredicatedFalse = 1;
24536let addrMode = BaseImmOffset;
24537let accessSize = WordAccess;
24538let isPredicatedNew = 1;
24539let mayStore = 1;
24540let CextOpcode = "S2_storeri";
24541let InputType = "imm";
24542let BaseOpcode = "S4_storeiri_io";
24543let isExtendable = 1;
24544let opExtendable = 3;
24545let isExtentSigned = 1;
24546let opExtentBits = 6;
24547let opExtentAlign = 0;
24548}
24549def S4_storeirifnew_zomap : HInst<
24550(outs),
24551(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24552"if (!$Pv4.new) memw($Rs32) = #$II",
24553tc_c4f596e3, TypeMAPPING> {
24554let isPseudo = 1;
24555let isCodeGenOnly = 1;
24556}
24557def S4_storeirit_io : HInst<
24558(outs),
24559(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24560"if ($Pv4) memw($Rs32+#$Ii) = #$II",
24561tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel {
24562let Inst{31-21} = 0b00111000010;
24563let isPredicated = 1;
24564let addrMode = BaseImmOffset;
24565let accessSize = WordAccess;
24566let mayStore = 1;
24567let CextOpcode = "S2_storeri";
24568let InputType = "imm";
24569let BaseOpcode = "S4_storeiri_io";
24570let isExtendable = 1;
24571let opExtendable = 3;
24572let isExtentSigned = 1;
24573let opExtentBits = 6;
24574let opExtentAlign = 0;
24575}
24576def S4_storeirit_zomap : HInst<
24577(outs),
24578(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24579"if ($Pv4) memw($Rs32) = #$II",
24580tc_0b2be201, TypeMAPPING> {
24581let isPseudo = 1;
24582let isCodeGenOnly = 1;
24583}
24584def S4_storeiritnew_io : HInst<
24585(outs),
24586(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24587"if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
24588tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel {
24589let Inst{31-21} = 0b00111001010;
24590let isPredicated = 1;
24591let addrMode = BaseImmOffset;
24592let accessSize = WordAccess;
24593let isPredicatedNew = 1;
24594let mayStore = 1;
24595let CextOpcode = "S2_storeri";
24596let InputType = "imm";
24597let BaseOpcode = "S4_storeiri_io";
24598let isExtendable = 1;
24599let opExtendable = 3;
24600let isExtentSigned = 1;
24601let opExtentBits = 6;
24602let opExtentAlign = 0;
24603}
24604def S4_storeiritnew_zomap : HInst<
24605(outs),
24606(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24607"if ($Pv4.new) memw($Rs32) = #$II",
24608tc_c4f596e3, TypeMAPPING> {
24609let isPseudo = 1;
24610let isCodeGenOnly = 1;
24611}
24612def S4_storerb_ap : HInst<
24613(outs IntRegs:$Re32),
24614(ins u32_0Imm:$II, IntRegs:$Rt32),
24615"memb($Re32=#$II) = $Rt32",
24616tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel {
24617let Inst{7-6} = 0b10;
24618let Inst{13-13} = 0b0;
24619let Inst{31-21} = 0b10101011000;
24620let addrMode = AbsoluteSet;
24621let accessSize = ByteAccess;
24622let isExtended = 1;
24623let mayStore = 1;
24624let BaseOpcode = "S2_storerb_ap";
24625let isNVStorable = 1;
24626let DecoderNamespace = "MustExtend";
24627let isExtendable = 1;
24628let opExtendable = 1;
24629let isExtentSigned = 0;
24630let opExtentBits = 6;
24631let opExtentAlign = 0;
24632}
24633def S4_storerb_rr : HInst<
24634(outs),
24635(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24636"memb($Rs32+$Ru32<<#$Ii) = $Rt32",
24637tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24638let Inst{6-5} = 0b00;
24639let Inst{31-21} = 0b00111011000;
24640let addrMode = BaseRegOffset;
24641let accessSize = ByteAccess;
24642let mayStore = 1;
24643let CextOpcode = "S2_storerb";
24644let InputType = "reg";
24645let BaseOpcode = "S4_storerb_rr";
24646let isNVStorable = 1;
24647let isPredicable = 1;
24648}
24649def S4_storerb_ur : HInst<
24650(outs),
24651(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24652"memb($Ru32<<#$Ii+#$II) = $Rt32",
24653tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24654let Inst{7-7} = 0b1;
24655let Inst{31-21} = 0b10101101000;
24656let addrMode = BaseLongOffset;
24657let accessSize = ByteAccess;
24658let isExtended = 1;
24659let mayStore = 1;
24660let CextOpcode = "S2_storerb";
24661let InputType = "imm";
24662let BaseOpcode = "S4_storerb_ur";
24663let isNVStorable = 1;
24664let DecoderNamespace = "MustExtend";
24665let isExtendable = 1;
24666let opExtendable = 2;
24667let isExtentSigned = 0;
24668let opExtentBits = 6;
24669let opExtentAlign = 0;
24670}
24671def S4_storerbnew_ap : HInst<
24672(outs IntRegs:$Re32),
24673(ins u32_0Imm:$II, IntRegs:$Nt8),
24674"memb($Re32=#$II) = $Nt8.new",
24675tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel {
24676let Inst{7-6} = 0b10;
24677let Inst{13-11} = 0b000;
24678let Inst{31-21} = 0b10101011101;
24679let addrMode = AbsoluteSet;
24680let accessSize = ByteAccess;
24681let isNVStore = 1;
24682let isNewValue = 1;
24683let isExtended = 1;
24684let isRestrictNoSlot1Store = 1;
24685let mayStore = 1;
24686let BaseOpcode = "S2_storerb_ap";
24687let DecoderNamespace = "MustExtend";
24688let isExtendable = 1;
24689let opExtendable = 1;
24690let isExtentSigned = 0;
24691let opExtentBits = 6;
24692let opExtentAlign = 0;
24693let opNewValue = 2;
24694}
24695def S4_storerbnew_rr : HInst<
24696(outs),
24697(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24698"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24699tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel {
24700let Inst{6-3} = 0b0000;
24701let Inst{31-21} = 0b00111011101;
24702let addrMode = BaseRegOffset;
24703let accessSize = ByteAccess;
24704let isNVStore = 1;
24705let isNewValue = 1;
24706let isRestrictNoSlot1Store = 1;
24707let mayStore = 1;
24708let CextOpcode = "S2_storerb";
24709let InputType = "reg";
24710let BaseOpcode = "S4_storerb_rr";
24711let isPredicable = 1;
24712let opNewValue = 3;
24713}
24714def S4_storerbnew_ur : HInst<
24715(outs),
24716(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
24717"memb($Ru32<<#$Ii+#$II) = $Nt8.new",
24718tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel {
24719let Inst{7-7} = 0b1;
24720let Inst{12-11} = 0b00;
24721let Inst{31-21} = 0b10101101101;
24722let addrMode = BaseLongOffset;
24723let accessSize = ByteAccess;
24724let isNVStore = 1;
24725let isNewValue = 1;
24726let isExtended = 1;
24727let isRestrictNoSlot1Store = 1;
24728let mayStore = 1;
24729let CextOpcode = "S2_storerb";
24730let BaseOpcode = "S4_storerb_ur";
24731let DecoderNamespace = "MustExtend";
24732let isExtendable = 1;
24733let opExtendable = 2;
24734let isExtentSigned = 0;
24735let opExtentBits = 6;
24736let opExtentAlign = 0;
24737let opNewValue = 3;
24738}
24739def S4_storerd_ap : HInst<
24740(outs IntRegs:$Re32),
24741(ins u32_0Imm:$II, DoubleRegs:$Rtt32),
24742"memd($Re32=#$II) = $Rtt32",
24743tc_da4a37ed, TypeST>, Enc_c7a204 {
24744let Inst{7-6} = 0b10;
24745let Inst{13-13} = 0b0;
24746let Inst{31-21} = 0b10101011110;
24747let addrMode = AbsoluteSet;
24748let accessSize = DoubleWordAccess;
24749let isExtended = 1;
24750let mayStore = 1;
24751let BaseOpcode = "S4_storerd_ap";
24752let DecoderNamespace = "MustExtend";
24753let isExtendable = 1;
24754let opExtendable = 1;
24755let isExtentSigned = 0;
24756let opExtentBits = 6;
24757let opExtentAlign = 0;
24758}
24759def S4_storerd_rr : HInst<
24760(outs),
24761(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
24762"memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
24763tc_5aee39f7, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
24764let Inst{6-5} = 0b00;
24765let Inst{31-21} = 0b00111011110;
24766let addrMode = BaseRegOffset;
24767let accessSize = DoubleWordAccess;
24768let mayStore = 1;
24769let CextOpcode = "S2_storerd";
24770let InputType = "reg";
24771let BaseOpcode = "S2_storerd_rr";
24772let isPredicable = 1;
24773}
24774def S4_storerd_ur : HInst<
24775(outs),
24776(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
24777"memd($Ru32<<#$Ii+#$II) = $Rtt32",
24778tc_14b272fa, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
24779let Inst{7-7} = 0b1;
24780let Inst{31-21} = 0b10101101110;
24781let addrMode = BaseLongOffset;
24782let accessSize = DoubleWordAccess;
24783let isExtended = 1;
24784let mayStore = 1;
24785let CextOpcode = "S2_storerd";
24786let InputType = "imm";
24787let BaseOpcode = "S2_storerd_ur";
24788let DecoderNamespace = "MustExtend";
24789let isExtendable = 1;
24790let opExtendable = 2;
24791let isExtentSigned = 0;
24792let opExtentBits = 6;
24793let opExtentAlign = 0;
24794}
24795def S4_storerf_ap : HInst<
24796(outs IntRegs:$Re32),
24797(ins u32_0Imm:$II, IntRegs:$Rt32),
24798"memh($Re32=#$II) = $Rt32.h",
24799tc_da4a37ed, TypeST>, Enc_8bcba4 {
24800let Inst{7-6} = 0b10;
24801let Inst{13-13} = 0b0;
24802let Inst{31-21} = 0b10101011011;
24803let addrMode = AbsoluteSet;
24804let accessSize = HalfWordAccess;
24805let isExtended = 1;
24806let mayStore = 1;
24807let BaseOpcode = "S4_storerf_ap";
24808let DecoderNamespace = "MustExtend";
24809let isExtendable = 1;
24810let opExtendable = 1;
24811let isExtentSigned = 0;
24812let opExtentBits = 6;
24813let opExtentAlign = 0;
24814}
24815def S4_storerf_rr : HInst<
24816(outs),
24817(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24818"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
24819tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24820let Inst{6-5} = 0b00;
24821let Inst{31-21} = 0b00111011011;
24822let addrMode = BaseRegOffset;
24823let accessSize = HalfWordAccess;
24824let mayStore = 1;
24825let CextOpcode = "S2_storerf";
24826let InputType = "reg";
24827let BaseOpcode = "S4_storerf_rr";
24828let isPredicable = 1;
24829}
24830def S4_storerf_ur : HInst<
24831(outs),
24832(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24833"memh($Ru32<<#$Ii+#$II) = $Rt32.h",
24834tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24835let Inst{7-7} = 0b1;
24836let Inst{31-21} = 0b10101101011;
24837let addrMode = BaseLongOffset;
24838let accessSize = HalfWordAccess;
24839let isExtended = 1;
24840let mayStore = 1;
24841let CextOpcode = "S2_storerf";
24842let InputType = "imm";
24843let BaseOpcode = "S4_storerf_rr";
24844let DecoderNamespace = "MustExtend";
24845let isExtendable = 1;
24846let opExtendable = 2;
24847let isExtentSigned = 0;
24848let opExtentBits = 6;
24849let opExtentAlign = 0;
24850}
24851def S4_storerh_ap : HInst<
24852(outs IntRegs:$Re32),
24853(ins u32_0Imm:$II, IntRegs:$Rt32),
24854"memh($Re32=#$II) = $Rt32",
24855tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel {
24856let Inst{7-6} = 0b10;
24857let Inst{13-13} = 0b0;
24858let Inst{31-21} = 0b10101011010;
24859let addrMode = AbsoluteSet;
24860let accessSize = HalfWordAccess;
24861let isExtended = 1;
24862let mayStore = 1;
24863let BaseOpcode = "S2_storerh_ap";
24864let isNVStorable = 1;
24865let DecoderNamespace = "MustExtend";
24866let isExtendable = 1;
24867let opExtendable = 1;
24868let isExtentSigned = 0;
24869let opExtentBits = 6;
24870let opExtentAlign = 0;
24871}
24872def S4_storerh_rr : HInst<
24873(outs),
24874(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24875"memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24876tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
24877let Inst{6-5} = 0b00;
24878let Inst{31-21} = 0b00111011010;
24879let addrMode = BaseRegOffset;
24880let accessSize = HalfWordAccess;
24881let mayStore = 1;
24882let CextOpcode = "S2_storerh";
24883let InputType = "reg";
24884let BaseOpcode = "S2_storerh_rr";
24885let isNVStorable = 1;
24886let isPredicable = 1;
24887}
24888def S4_storerh_ur : HInst<
24889(outs),
24890(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
24891"memh($Ru32<<#$Ii+#$II) = $Rt32",
24892tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
24893let Inst{7-7} = 0b1;
24894let Inst{31-21} = 0b10101101010;
24895let addrMode = BaseLongOffset;
24896let accessSize = HalfWordAccess;
24897let isExtended = 1;
24898let mayStore = 1;
24899let CextOpcode = "S2_storerh";
24900let InputType = "imm";
24901let BaseOpcode = "S2_storerh_ur";
24902let isNVStorable = 1;
24903let DecoderNamespace = "MustExtend";
24904let isExtendable = 1;
24905let opExtendable = 2;
24906let isExtentSigned = 0;
24907let opExtentBits = 6;
24908let opExtentAlign = 0;
24909}
24910def S4_storerhnew_ap : HInst<
24911(outs IntRegs:$Re32),
24912(ins u32_0Imm:$II, IntRegs:$Nt8),
24913"memh($Re32=#$II) = $Nt8.new",
24914tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel {
24915let Inst{7-6} = 0b10;
24916let Inst{13-11} = 0b001;
24917let Inst{31-21} = 0b10101011101;
24918let addrMode = AbsoluteSet;
24919let accessSize = HalfWordAccess;
24920let isNVStore = 1;
24921let isNewValue = 1;
24922let isExtended = 1;
24923let isRestrictNoSlot1Store = 1;
24924let mayStore = 1;
24925let BaseOpcode = "S2_storerh_ap";
24926let DecoderNamespace = "MustExtend";
24927let isExtendable = 1;
24928let opExtendable = 1;
24929let isExtentSigned = 0;
24930let opExtentBits = 6;
24931let opExtentAlign = 0;
24932let opNewValue = 2;
24933}
24934def S4_storerhnew_rr : HInst<
24935(outs),
24936(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24937"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24938tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel {
24939let Inst{6-3} = 0b0001;
24940let Inst{31-21} = 0b00111011101;
24941let addrMode = BaseRegOffset;
24942let accessSize = HalfWordAccess;
24943let isNVStore = 1;
24944let isNewValue = 1;
24945let isRestrictNoSlot1Store = 1;
24946let mayStore = 1;
24947let CextOpcode = "S2_storerh";
24948let InputType = "reg";
24949let BaseOpcode = "S2_storerh_rr";
24950let isPredicable = 1;
24951let opNewValue = 3;
24952}
24953def S4_storerhnew_ur : HInst<
24954(outs),
24955(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
24956"memh($Ru32<<#$Ii+#$II) = $Nt8.new",
24957tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel {
24958let Inst{7-7} = 0b1;
24959let Inst{12-11} = 0b01;
24960let Inst{31-21} = 0b10101101101;
24961let addrMode = BaseLongOffset;
24962let accessSize = HalfWordAccess;
24963let isNVStore = 1;
24964let isNewValue = 1;
24965let isExtended = 1;
24966let isRestrictNoSlot1Store = 1;
24967let mayStore = 1;
24968let CextOpcode = "S2_storerh";
24969let BaseOpcode = "S2_storerh_ur";
24970let DecoderNamespace = "MustExtend";
24971let isExtendable = 1;
24972let opExtendable = 2;
24973let isExtentSigned = 0;
24974let opExtentBits = 6;
24975let opExtentAlign = 0;
24976let opNewValue = 3;
24977}
24978def S4_storeri_ap : HInst<
24979(outs IntRegs:$Re32),
24980(ins u32_0Imm:$II, IntRegs:$Rt32),
24981"memw($Re32=#$II) = $Rt32",
24982tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel {
24983let Inst{7-6} = 0b10;
24984let Inst{13-13} = 0b0;
24985let Inst{31-21} = 0b10101011100;
24986let addrMode = AbsoluteSet;
24987let accessSize = WordAccess;
24988let isExtended = 1;
24989let mayStore = 1;
24990let BaseOpcode = "S2_storeri_ap";
24991let isNVStorable = 1;
24992let DecoderNamespace = "MustExtend";
24993let isExtendable = 1;
24994let opExtendable = 1;
24995let isExtentSigned = 0;
24996let opExtentBits = 6;
24997let opExtentAlign = 0;
24998}
24999def S4_storeri_rr : HInst<
25000(outs),
25001(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25002"memw($Rs32+$Ru32<<#$Ii) = $Rt32",
25003tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25004let Inst{6-5} = 0b00;
25005let Inst{31-21} = 0b00111011100;
25006let addrMode = BaseRegOffset;
25007let accessSize = WordAccess;
25008let mayStore = 1;
25009let CextOpcode = "S2_storeri";
25010let InputType = "reg";
25011let BaseOpcode = "S2_storeri_rr";
25012let isNVStorable = 1;
25013let isPredicable = 1;
25014}
25015def S4_storeri_ur : HInst<
25016(outs),
25017(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25018"memw($Ru32<<#$Ii+#$II) = $Rt32",
25019tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25020let Inst{7-7} = 0b1;
25021let Inst{31-21} = 0b10101101100;
25022let addrMode = BaseLongOffset;
25023let accessSize = WordAccess;
25024let isExtended = 1;
25025let mayStore = 1;
25026let CextOpcode = "S2_storeri";
25027let InputType = "imm";
25028let BaseOpcode = "S2_storeri_ur";
25029let isNVStorable = 1;
25030let DecoderNamespace = "MustExtend";
25031let isExtendable = 1;
25032let opExtendable = 2;
25033let isExtentSigned = 0;
25034let opExtentBits = 6;
25035let opExtentAlign = 0;
25036}
25037def S4_storerinew_ap : HInst<
25038(outs IntRegs:$Re32),
25039(ins u32_0Imm:$II, IntRegs:$Nt8),
25040"memw($Re32=#$II) = $Nt8.new",
25041tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel {
25042let Inst{7-6} = 0b10;
25043let Inst{13-11} = 0b010;
25044let Inst{31-21} = 0b10101011101;
25045let addrMode = AbsoluteSet;
25046let accessSize = WordAccess;
25047let isNVStore = 1;
25048let isNewValue = 1;
25049let isExtended = 1;
25050let isRestrictNoSlot1Store = 1;
25051let mayStore = 1;
25052let BaseOpcode = "S2_storeri_ap";
25053let DecoderNamespace = "MustExtend";
25054let isExtendable = 1;
25055let opExtendable = 1;
25056let isExtentSigned = 0;
25057let opExtentBits = 6;
25058let opExtentAlign = 0;
25059let opNewValue = 2;
25060}
25061def S4_storerinew_rr : HInst<
25062(outs),
25063(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25064"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25065tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel {
25066let Inst{6-3} = 0b0010;
25067let Inst{31-21} = 0b00111011101;
25068let addrMode = BaseRegOffset;
25069let accessSize = WordAccess;
25070let isNVStore = 1;
25071let isNewValue = 1;
25072let isRestrictNoSlot1Store = 1;
25073let mayStore = 1;
25074let CextOpcode = "S2_storeri";
25075let InputType = "reg";
25076let BaseOpcode = "S2_storeri_rr";
25077let isPredicable = 1;
25078let opNewValue = 3;
25079}
25080def S4_storerinew_ur : HInst<
25081(outs),
25082(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25083"memw($Ru32<<#$Ii+#$II) = $Nt8.new",
25084tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel {
25085let Inst{7-7} = 0b1;
25086let Inst{12-11} = 0b10;
25087let Inst{31-21} = 0b10101101101;
25088let addrMode = BaseLongOffset;
25089let accessSize = WordAccess;
25090let isNVStore = 1;
25091let isNewValue = 1;
25092let isExtended = 1;
25093let isRestrictNoSlot1Store = 1;
25094let mayStore = 1;
25095let CextOpcode = "S2_storeri";
25096let BaseOpcode = "S2_storeri_ur";
25097let DecoderNamespace = "MustExtend";
25098let isExtendable = 1;
25099let opExtendable = 2;
25100let isExtentSigned = 0;
25101let opExtentBits = 6;
25102let opExtentAlign = 0;
25103let opNewValue = 3;
25104}
25105def S4_subaddi : HInst<
25106(outs IntRegs:$Rd32),
25107(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
25108"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
25109tc_f675fee8, TypeALU64>, Enc_8b8d61 {
25110let Inst{31-23} = 0b110110111;
25111let hasNewValue = 1;
25112let opNewValue = 0;
25113let prefersSlot3 = 1;
25114let isExtendable = 1;
25115let opExtendable = 2;
25116let isExtentSigned = 1;
25117let opExtentBits = 6;
25118let opExtentAlign = 0;
25119}
25120def S4_subi_asl_ri : HInst<
25121(outs IntRegs:$Rx32),
25122(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25123"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
25124tc_f675fee8, TypeALU64>, Enc_c31910 {
25125let Inst{2-0} = 0b110;
25126let Inst{4-4} = 0b0;
25127let Inst{31-24} = 0b11011110;
25128let hasNewValue = 1;
25129let opNewValue = 0;
25130let prefersSlot3 = 1;
25131let isExtendable = 1;
25132let opExtendable = 1;
25133let isExtentSigned = 0;
25134let opExtentBits = 8;
25135let opExtentAlign = 0;
25136let Constraints = "$Rx32 = $Rx32in";
25137}
25138def S4_subi_lsr_ri : HInst<
25139(outs IntRegs:$Rx32),
25140(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25141"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
25142tc_f675fee8, TypeALU64>, Enc_c31910 {
25143let Inst{2-0} = 0b110;
25144let Inst{4-4} = 0b1;
25145let Inst{31-24} = 0b11011110;
25146let hasNewValue = 1;
25147let opNewValue = 0;
25148let prefersSlot3 = 1;
25149let isExtendable = 1;
25150let opExtendable = 1;
25151let isExtentSigned = 0;
25152let opExtentBits = 8;
25153let opExtentAlign = 0;
25154let Constraints = "$Rx32 = $Rx32in";
25155}
25156def S4_vrcrotate : HInst<
25157(outs DoubleRegs:$Rdd32),
25158(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25159"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
25160tc_13bfbcf9, TypeS_3op>, Enc_645d54 {
25161let Inst{7-6} = 0b11;
25162let Inst{31-21} = 0b11000011110;
25163let prefersSlot3 = 1;
25164}
25165def S4_vrcrotate_acc : HInst<
25166(outs DoubleRegs:$Rxx32),
25167(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25168"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
25169tc_9debc299, TypeS_3op>, Enc_b72622 {
25170let Inst{7-6} = 0b00;
25171let Inst{31-21} = 0b11001011101;
25172let prefersSlot3 = 1;
25173let Constraints = "$Rxx32 = $Rxx32in";
25174}
25175def S4_vxaddsubh : HInst<
25176(outs DoubleRegs:$Rdd32),
25177(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25178"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
25179tc_779080bf, TypeS_3op>, Enc_a56825 {
25180let Inst{7-5} = 0b100;
25181let Inst{13-13} = 0b0;
25182let Inst{31-21} = 0b11000001010;
25183let prefersSlot3 = 1;
25184let Defs = [USR_OVF];
25185}
25186def S4_vxaddsubhr : HInst<
25187(outs DoubleRegs:$Rdd32),
25188(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25189"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
25190tc_002cb246, TypeS_3op>, Enc_a56825 {
25191let Inst{7-5} = 0b000;
25192let Inst{13-13} = 0b0;
25193let Inst{31-21} = 0b11000001110;
25194let prefersSlot3 = 1;
25195let Defs = [USR_OVF];
25196}
25197def S4_vxaddsubw : HInst<
25198(outs DoubleRegs:$Rdd32),
25199(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25200"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
25201tc_779080bf, TypeS_3op>, Enc_a56825 {
25202let Inst{7-5} = 0b000;
25203let Inst{13-13} = 0b0;
25204let Inst{31-21} = 0b11000001010;
25205let prefersSlot3 = 1;
25206let Defs = [USR_OVF];
25207}
25208def S4_vxsubaddh : HInst<
25209(outs DoubleRegs:$Rdd32),
25210(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25211"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
25212tc_779080bf, TypeS_3op>, Enc_a56825 {
25213let Inst{7-5} = 0b110;
25214let Inst{13-13} = 0b0;
25215let Inst{31-21} = 0b11000001010;
25216let prefersSlot3 = 1;
25217let Defs = [USR_OVF];
25218}
25219def S4_vxsubaddhr : HInst<
25220(outs DoubleRegs:$Rdd32),
25221(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25222"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
25223tc_002cb246, TypeS_3op>, Enc_a56825 {
25224let Inst{7-5} = 0b010;
25225let Inst{13-13} = 0b0;
25226let Inst{31-21} = 0b11000001110;
25227let prefersSlot3 = 1;
25228let Defs = [USR_OVF];
25229}
25230def S4_vxsubaddw : HInst<
25231(outs DoubleRegs:$Rdd32),
25232(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25233"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
25234tc_779080bf, TypeS_3op>, Enc_a56825 {
25235let Inst{7-5} = 0b010;
25236let Inst{13-13} = 0b0;
25237let Inst{31-21} = 0b11000001010;
25238let prefersSlot3 = 1;
25239let Defs = [USR_OVF];
25240}
25241def S5_asrhub_rnd_sat : HInst<
25242(outs IntRegs:$Rd32),
25243(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25244"$Rd32 = vasrhub($Rss32,#$Ii):raw",
25245tc_002cb246, TypeS_2op>, Enc_11a146 {
25246let Inst{7-5} = 0b100;
25247let Inst{13-12} = 0b00;
25248let Inst{31-21} = 0b10001000011;
25249let hasNewValue = 1;
25250let opNewValue = 0;
25251let prefersSlot3 = 1;
25252let Defs = [USR_OVF];
25253}
25254def S5_asrhub_rnd_sat_goodsyntax : HInst<
25255(outs IntRegs:$Rd32),
25256(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25257"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
25258tc_002cb246, TypeS_2op> {
25259let hasNewValue = 1;
25260let opNewValue = 0;
25261let isPseudo = 1;
25262}
25263def S5_asrhub_sat : HInst<
25264(outs IntRegs:$Rd32),
25265(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25266"$Rd32 = vasrhub($Rss32,#$Ii):sat",
25267tc_002cb246, TypeS_2op>, Enc_11a146 {
25268let Inst{7-5} = 0b101;
25269let Inst{13-12} = 0b00;
25270let Inst{31-21} = 0b10001000011;
25271let hasNewValue = 1;
25272let opNewValue = 0;
25273let prefersSlot3 = 1;
25274let Defs = [USR_OVF];
25275}
25276def S5_popcountp : HInst<
25277(outs IntRegs:$Rd32),
25278(ins DoubleRegs:$Rss32),
25279"$Rd32 = popcount($Rss32)",
25280tc_703e822c, TypeS_2op>, Enc_90cd8b {
25281let Inst{13-5} = 0b000000011;
25282let Inst{31-21} = 0b10001000011;
25283let hasNewValue = 1;
25284let opNewValue = 0;
25285let prefersSlot3 = 1;
25286}
25287def S5_vasrhrnd : HInst<
25288(outs DoubleRegs:$Rdd32),
25289(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25290"$Rdd32 = vasrh($Rss32,#$Ii):raw",
25291tc_002cb246, TypeS_2op>, Enc_12b6e9 {
25292let Inst{7-5} = 0b000;
25293let Inst{13-12} = 0b00;
25294let Inst{31-21} = 0b10000000001;
25295let prefersSlot3 = 1;
25296}
25297def S5_vasrhrnd_goodsyntax : HInst<
25298(outs DoubleRegs:$Rdd32),
25299(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25300"$Rdd32 = vasrh($Rss32,#$Ii):rnd",
25301tc_002cb246, TypeS_2op> {
25302let isPseudo = 1;
25303}
25304def S6_allocframe_to_raw : HInst<
25305(outs),
25306(ins u11_3Imm:$Ii),
25307"allocframe(#$Ii)",
25308tc_b44ecf75, TypeMAPPING>, Requires<[HasV65]> {
25309let isPseudo = 1;
25310let isCodeGenOnly = 1;
25311}
25312def S6_rol_i_p : HInst<
25313(outs DoubleRegs:$Rdd32),
25314(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
25315"$Rdd32 = rol($Rss32,#$Ii)",
25316tc_1fc97744, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> {
25317let Inst{7-5} = 0b011;
25318let Inst{31-21} = 0b10000000000;
25319}
25320def S6_rol_i_p_acc : HInst<
25321(outs DoubleRegs:$Rxx32),
25322(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25323"$Rxx32 += rol($Rss32,#$Ii)",
25324tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25325let Inst{7-5} = 0b111;
25326let Inst{31-21} = 0b10000010000;
25327let prefersSlot3 = 1;
25328let Constraints = "$Rxx32 = $Rxx32in";
25329}
25330def S6_rol_i_p_and : HInst<
25331(outs DoubleRegs:$Rxx32),
25332(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25333"$Rxx32 &= rol($Rss32,#$Ii)",
25334tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25335let Inst{7-5} = 0b011;
25336let Inst{31-21} = 0b10000010010;
25337let prefersSlot3 = 1;
25338let Constraints = "$Rxx32 = $Rxx32in";
25339}
25340def S6_rol_i_p_nac : HInst<
25341(outs DoubleRegs:$Rxx32),
25342(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25343"$Rxx32 -= rol($Rss32,#$Ii)",
25344tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25345let Inst{7-5} = 0b011;
25346let Inst{31-21} = 0b10000010000;
25347let prefersSlot3 = 1;
25348let Constraints = "$Rxx32 = $Rxx32in";
25349}
25350def S6_rol_i_p_or : HInst<
25351(outs DoubleRegs:$Rxx32),
25352(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25353"$Rxx32 |= rol($Rss32,#$Ii)",
25354tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25355let Inst{7-5} = 0b111;
25356let Inst{31-21} = 0b10000010010;
25357let prefersSlot3 = 1;
25358let Constraints = "$Rxx32 = $Rxx32in";
25359}
25360def S6_rol_i_p_xacc : HInst<
25361(outs DoubleRegs:$Rxx32),
25362(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25363"$Rxx32 ^= rol($Rss32,#$Ii)",
25364tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25365let Inst{7-5} = 0b011;
25366let Inst{31-21} = 0b10000010100;
25367let prefersSlot3 = 1;
25368let Constraints = "$Rxx32 = $Rxx32in";
25369}
25370def S6_rol_i_r : HInst<
25371(outs IntRegs:$Rd32),
25372(ins IntRegs:$Rs32, u5_0Imm:$Ii),
25373"$Rd32 = rol($Rs32,#$Ii)",
25374tc_1fc97744, TypeS_2op>, Enc_a05677, Requires<[HasV60]> {
25375let Inst{7-5} = 0b011;
25376let Inst{13-13} = 0b0;
25377let Inst{31-21} = 0b10001100000;
25378let hasNewValue = 1;
25379let opNewValue = 0;
25380}
25381def S6_rol_i_r_acc : HInst<
25382(outs IntRegs:$Rx32),
25383(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25384"$Rx32 += rol($Rs32,#$Ii)",
25385tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25386let Inst{7-5} = 0b111;
25387let Inst{13-13} = 0b0;
25388let Inst{31-21} = 0b10001110000;
25389let hasNewValue = 1;
25390let opNewValue = 0;
25391let prefersSlot3 = 1;
25392let Constraints = "$Rx32 = $Rx32in";
25393}
25394def S6_rol_i_r_and : HInst<
25395(outs IntRegs:$Rx32),
25396(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25397"$Rx32 &= rol($Rs32,#$Ii)",
25398tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25399let Inst{7-5} = 0b011;
25400let Inst{13-13} = 0b0;
25401let Inst{31-21} = 0b10001110010;
25402let hasNewValue = 1;
25403let opNewValue = 0;
25404let prefersSlot3 = 1;
25405let Constraints = "$Rx32 = $Rx32in";
25406}
25407def S6_rol_i_r_nac : HInst<
25408(outs IntRegs:$Rx32),
25409(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25410"$Rx32 -= rol($Rs32,#$Ii)",
25411tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25412let Inst{7-5} = 0b011;
25413let Inst{13-13} = 0b0;
25414let Inst{31-21} = 0b10001110000;
25415let hasNewValue = 1;
25416let opNewValue = 0;
25417let prefersSlot3 = 1;
25418let Constraints = "$Rx32 = $Rx32in";
25419}
25420def S6_rol_i_r_or : HInst<
25421(outs IntRegs:$Rx32),
25422(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25423"$Rx32 |= rol($Rs32,#$Ii)",
25424tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25425let Inst{7-5} = 0b111;
25426let Inst{13-13} = 0b0;
25427let Inst{31-21} = 0b10001110010;
25428let hasNewValue = 1;
25429let opNewValue = 0;
25430let prefersSlot3 = 1;
25431let Constraints = "$Rx32 = $Rx32in";
25432}
25433def S6_rol_i_r_xacc : HInst<
25434(outs IntRegs:$Rx32),
25435(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25436"$Rx32 ^= rol($Rs32,#$Ii)",
25437tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25438let Inst{7-5} = 0b011;
25439let Inst{13-13} = 0b0;
25440let Inst{31-21} = 0b10001110100;
25441let hasNewValue = 1;
25442let opNewValue = 0;
25443let prefersSlot3 = 1;
25444let Constraints = "$Rx32 = $Rx32in";
25445}
25446def S6_vsplatrbp : HInst<
25447(outs DoubleRegs:$Rdd32),
25448(ins IntRegs:$Rs32),
25449"$Rdd32 = vsplatb($Rs32)",
25450tc_a1c00888, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> {
25451let Inst{13-5} = 0b000000100;
25452let Inst{31-21} = 0b10000100010;
25453}
25454def S6_vtrunehb_ppp : HInst<
25455(outs DoubleRegs:$Rdd32),
25456(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25457"$Rdd32 = vtrunehb($Rss32,$Rtt32)",
25458tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25459let Inst{7-5} = 0b011;
25460let Inst{13-13} = 0b0;
25461let Inst{31-21} = 0b11000001100;
25462}
25463def S6_vtrunohb_ppp : HInst<
25464(outs DoubleRegs:$Rdd32),
25465(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25466"$Rdd32 = vtrunohb($Rss32,$Rtt32)",
25467tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25468let Inst{7-5} = 0b101;
25469let Inst{13-13} = 0b0;
25470let Inst{31-21} = 0b11000001100;
25471}
25472def SA1_addi : HInst<
25473(outs GeneralSubRegs:$Rx16),
25474(ins IntRegs:$Rx16in, s32_0Imm:$Ii),
25475"$Rx16 = add($Rx16in,#$Ii)",
25476tc_0a705168, TypeSUBINSN>, Enc_93af4c {
25477let Inst{12-11} = 0b00;
25478let hasNewValue = 1;
25479let opNewValue = 0;
25480let AsmVariantName = "NonParsable";
25481let DecoderNamespace = "SUBINSN_A";
25482let isExtendable = 1;
25483let opExtendable = 2;
25484let isExtentSigned = 1;
25485let opExtentBits = 7;
25486let opExtentAlign = 0;
25487let Constraints = "$Rx16 = $Rx16in";
25488}
25489def SA1_addrx : HInst<
25490(outs GeneralSubRegs:$Rx16),
25491(ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16),
25492"$Rx16 = add($Rx16in,$Rs16)",
25493tc_0a705168, TypeSUBINSN>, Enc_0527db {
25494let Inst{12-8} = 0b11000;
25495let hasNewValue = 1;
25496let opNewValue = 0;
25497let AsmVariantName = "NonParsable";
25498let DecoderNamespace = "SUBINSN_A";
25499let Constraints = "$Rx16 = $Rx16in";
25500}
25501def SA1_addsp : HInst<
25502(outs GeneralSubRegs:$Rd16),
25503(ins u6_2Imm:$Ii),
25504"$Rd16 = add(r29,#$Ii)",
25505tc_9fc3dae0, TypeSUBINSN>, Enc_2df31d {
25506let Inst{12-10} = 0b011;
25507let hasNewValue = 1;
25508let opNewValue = 0;
25509let AsmVariantName = "NonParsable";
25510let Uses = [R29];
25511let DecoderNamespace = "SUBINSN_A";
25512}
25513def SA1_and1 : HInst<
25514(outs GeneralSubRegs:$Rd16),
25515(ins GeneralSubRegs:$Rs16),
25516"$Rd16 = and($Rs16,#1)",
25517tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 {
25518let Inst{12-8} = 0b10010;
25519let hasNewValue = 1;
25520let opNewValue = 0;
25521let AsmVariantName = "NonParsable";
25522let DecoderNamespace = "SUBINSN_A";
25523}
25524def SA1_clrf : HInst<
25525(outs GeneralSubRegs:$Rd16),
25526(ins),
25527"if (!p0) $Rd16 = #0",
25528tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 {
25529let Inst{12-4} = 0b110100111;
25530let isPredicated = 1;
25531let isPredicatedFalse = 1;
25532let hasNewValue = 1;
25533let opNewValue = 0;
25534let AsmVariantName = "NonParsable";
25535let Uses = [P0];
25536let DecoderNamespace = "SUBINSN_A";
25537}
25538def SA1_clrfnew : HInst<
25539(outs GeneralSubRegs:$Rd16),
25540(ins),
25541"if (!p0.new) $Rd16 = #0",
25542tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 {
25543let Inst{12-4} = 0b110100101;
25544let isPredicated = 1;
25545let isPredicatedFalse = 1;
25546let hasNewValue = 1;
25547let opNewValue = 0;
25548let AsmVariantName = "NonParsable";
25549let isPredicatedNew = 1;
25550let Uses = [P0];
25551let DecoderNamespace = "SUBINSN_A";
25552}
25553def SA1_clrt : HInst<
25554(outs GeneralSubRegs:$Rd16),
25555(ins),
25556"if (p0) $Rd16 = #0",
25557tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 {
25558let Inst{12-4} = 0b110100110;
25559let isPredicated = 1;
25560let hasNewValue = 1;
25561let opNewValue = 0;
25562let AsmVariantName = "NonParsable";
25563let Uses = [P0];
25564let DecoderNamespace = "SUBINSN_A";
25565}
25566def SA1_clrtnew : HInst<
25567(outs GeneralSubRegs:$Rd16),
25568(ins),
25569"if (p0.new) $Rd16 = #0",
25570tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 {
25571let Inst{12-4} = 0b110100100;
25572let isPredicated = 1;
25573let hasNewValue = 1;
25574let opNewValue = 0;
25575let AsmVariantName = "NonParsable";
25576let isPredicatedNew = 1;
25577let Uses = [P0];
25578let DecoderNamespace = "SUBINSN_A";
25579}
25580def SA1_cmpeqi : HInst<
25581(outs),
25582(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
25583"p0 = cmp.eq($Rs16,#$Ii)",
25584tc_5b7c0967, TypeSUBINSN>, Enc_63eaeb {
25585let Inst{3-2} = 0b00;
25586let Inst{12-8} = 0b11001;
25587let AsmVariantName = "NonParsable";
25588let Defs = [P0];
25589let DecoderNamespace = "SUBINSN_A";
25590}
25591def SA1_combine0i : HInst<
25592(outs GeneralDoubleLow8Regs:$Rdd8),
25593(ins u2_0Imm:$Ii),
25594"$Rdd8 = combine(#0,#$Ii)",
25595tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be {
25596let Inst{4-3} = 0b00;
25597let Inst{12-7} = 0b111000;
25598let hasNewValue = 1;
25599let opNewValue = 0;
25600let AsmVariantName = "NonParsable";
25601let DecoderNamespace = "SUBINSN_A";
25602}
25603def SA1_combine1i : HInst<
25604(outs GeneralDoubleLow8Regs:$Rdd8),
25605(ins u2_0Imm:$Ii),
25606"$Rdd8 = combine(#1,#$Ii)",
25607tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be {
25608let Inst{4-3} = 0b01;
25609let Inst{12-7} = 0b111000;
25610let hasNewValue = 1;
25611let opNewValue = 0;
25612let AsmVariantName = "NonParsable";
25613let DecoderNamespace = "SUBINSN_A";
25614}
25615def SA1_combine2i : HInst<
25616(outs GeneralDoubleLow8Regs:$Rdd8),
25617(ins u2_0Imm:$Ii),
25618"$Rdd8 = combine(#2,#$Ii)",
25619tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be {
25620let Inst{4-3} = 0b10;
25621let Inst{12-7} = 0b111000;
25622let hasNewValue = 1;
25623let opNewValue = 0;
25624let AsmVariantName = "NonParsable";
25625let DecoderNamespace = "SUBINSN_A";
25626}
25627def SA1_combine3i : HInst<
25628(outs GeneralDoubleLow8Regs:$Rdd8),
25629(ins u2_0Imm:$Ii),
25630"$Rdd8 = combine(#3,#$Ii)",
25631tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be {
25632let Inst{4-3} = 0b11;
25633let Inst{12-7} = 0b111000;
25634let hasNewValue = 1;
25635let opNewValue = 0;
25636let AsmVariantName = "NonParsable";
25637let DecoderNamespace = "SUBINSN_A";
25638}
25639def SA1_combinerz : HInst<
25640(outs GeneralDoubleLow8Regs:$Rdd8),
25641(ins GeneralSubRegs:$Rs16),
25642"$Rdd8 = combine($Rs16,#0)",
25643tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 {
25644let Inst{3-3} = 0b1;
25645let Inst{12-8} = 0b11101;
25646let hasNewValue = 1;
25647let opNewValue = 0;
25648let AsmVariantName = "NonParsable";
25649let DecoderNamespace = "SUBINSN_A";
25650}
25651def SA1_combinezr : HInst<
25652(outs GeneralDoubleLow8Regs:$Rdd8),
25653(ins GeneralSubRegs:$Rs16),
25654"$Rdd8 = combine(#0,$Rs16)",
25655tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 {
25656let Inst{3-3} = 0b0;
25657let Inst{12-8} = 0b11101;
25658let hasNewValue = 1;
25659let opNewValue = 0;
25660let AsmVariantName = "NonParsable";
25661let DecoderNamespace = "SUBINSN_A";
25662}
25663def SA1_dec : HInst<
25664(outs GeneralSubRegs:$Rd16),
25665(ins GeneralSubRegs:$Rs16, n1Const:$n1),
25666"$Rd16 = add($Rs16,#$n1)",
25667tc_0a705168, TypeSUBINSN>, Enc_ee5ed0 {
25668let Inst{12-8} = 0b10011;
25669let hasNewValue = 1;
25670let opNewValue = 0;
25671let AsmVariantName = "NonParsable";
25672let DecoderNamespace = "SUBINSN_A";
25673}
25674def SA1_inc : HInst<
25675(outs GeneralSubRegs:$Rd16),
25676(ins GeneralSubRegs:$Rs16),
25677"$Rd16 = add($Rs16,#1)",
25678tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 {
25679let Inst{12-8} = 0b10001;
25680let hasNewValue = 1;
25681let opNewValue = 0;
25682let AsmVariantName = "NonParsable";
25683let DecoderNamespace = "SUBINSN_A";
25684}
25685def SA1_seti : HInst<
25686(outs GeneralSubRegs:$Rd16),
25687(ins u32_0Imm:$Ii),
25688"$Rd16 = #$Ii",
25689tc_9fc3dae0, TypeSUBINSN>, Enc_e39bb2 {
25690let Inst{12-10} = 0b010;
25691let hasNewValue = 1;
25692let opNewValue = 0;
25693let AsmVariantName = "NonParsable";
25694let DecoderNamespace = "SUBINSN_A";
25695let isExtendable = 1;
25696let opExtendable = 1;
25697let isExtentSigned = 0;
25698let opExtentBits = 6;
25699let opExtentAlign = 0;
25700}
25701def SA1_setin1 : HInst<
25702(outs GeneralSubRegs:$Rd16),
25703(ins n1Const:$n1),
25704"$Rd16 = #$n1",
25705tc_9fc3dae0, TypeSUBINSN>, Enc_7a0ea6 {
25706let Inst{12-4} = 0b110100000;
25707let hasNewValue = 1;
25708let opNewValue = 0;
25709let AsmVariantName = "NonParsable";
25710let DecoderNamespace = "SUBINSN_A";
25711}
25712def SA1_sxtb : HInst<
25713(outs GeneralSubRegs:$Rd16),
25714(ins GeneralSubRegs:$Rs16),
25715"$Rd16 = sxtb($Rs16)",
25716tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 {
25717let Inst{12-8} = 0b10101;
25718let hasNewValue = 1;
25719let opNewValue = 0;
25720let AsmVariantName = "NonParsable";
25721let DecoderNamespace = "SUBINSN_A";
25722}
25723def SA1_sxth : HInst<
25724(outs GeneralSubRegs:$Rd16),
25725(ins GeneralSubRegs:$Rs16),
25726"$Rd16 = sxth($Rs16)",
25727tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 {
25728let Inst{12-8} = 0b10100;
25729let hasNewValue = 1;
25730let opNewValue = 0;
25731let AsmVariantName = "NonParsable";
25732let DecoderNamespace = "SUBINSN_A";
25733}
25734def SA1_tfr : HInst<
25735(outs GeneralSubRegs:$Rd16),
25736(ins GeneralSubRegs:$Rs16),
25737"$Rd16 = $Rs16",
25738tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 {
25739let Inst{12-8} = 0b10000;
25740let hasNewValue = 1;
25741let opNewValue = 0;
25742let AsmVariantName = "NonParsable";
25743let DecoderNamespace = "SUBINSN_A";
25744}
25745def SA1_zxtb : HInst<
25746(outs GeneralSubRegs:$Rd16),
25747(ins GeneralSubRegs:$Rs16),
25748"$Rd16 = and($Rs16,#255)",
25749tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 {
25750let Inst{12-8} = 0b10111;
25751let hasNewValue = 1;
25752let opNewValue = 0;
25753let AsmVariantName = "NonParsable";
25754let DecoderNamespace = "SUBINSN_A";
25755}
25756def SA1_zxth : HInst<
25757(outs GeneralSubRegs:$Rd16),
25758(ins GeneralSubRegs:$Rs16),
25759"$Rd16 = zxth($Rs16)",
25760tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 {
25761let Inst{12-8} = 0b10110;
25762let hasNewValue = 1;
25763let opNewValue = 0;
25764let AsmVariantName = "NonParsable";
25765let DecoderNamespace = "SUBINSN_A";
25766}
25767def SL1_loadri_io : HInst<
25768(outs GeneralSubRegs:$Rd16),
25769(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
25770"$Rd16 = memw($Rs16+#$Ii)",
25771tc_17e0d2cd, TypeSUBINSN>, Enc_53dca9 {
25772let Inst{12-12} = 0b0;
25773let hasNewValue = 1;
25774let opNewValue = 0;
25775let addrMode = BaseImmOffset;
25776let accessSize = WordAccess;
25777let AsmVariantName = "NonParsable";
25778let mayLoad = 1;
25779let DecoderNamespace = "SUBINSN_L1";
25780}
25781def SL1_loadrub_io : HInst<
25782(outs GeneralSubRegs:$Rd16),
25783(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
25784"$Rd16 = memub($Rs16+#$Ii)",
25785tc_17e0d2cd, TypeSUBINSN>, Enc_c175d0 {
25786let Inst{12-12} = 0b1;
25787let hasNewValue = 1;
25788let opNewValue = 0;
25789let addrMode = BaseImmOffset;
25790let accessSize = ByteAccess;
25791let AsmVariantName = "NonParsable";
25792let mayLoad = 1;
25793let DecoderNamespace = "SUBINSN_L1";
25794}
25795def SL2_deallocframe : HInst<
25796(outs),
25797(ins),
25798"deallocframe",
25799tc_39dfefe8, TypeSUBINSN>, Enc_e3b0c4 {
25800let Inst{12-0} = 0b1111100000000;
25801let accessSize = DoubleWordAccess;
25802let AsmVariantName = "NonParsable";
25803let mayLoad = 1;
25804let Uses = [FRAMEKEY, R30];
25805let Defs = [R30, R29, R31];
25806let DecoderNamespace = "SUBINSN_L2";
25807}
25808def SL2_jumpr31 : HInst<
25809(outs),
25810(ins),
25811"jumpr r31",
25812tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 {
25813let Inst{12-0} = 0b1111111000000;
25814let isTerminator = 1;
25815let isIndirectBranch = 1;
25816let AsmVariantName = "NonParsable";
25817let cofMax1 = 1;
25818let isReturn = 1;
25819let Uses = [R31];
25820let Defs = [PC];
25821let DecoderNamespace = "SUBINSN_L2";
25822}
25823def SL2_jumpr31_f : HInst<
25824(outs),
25825(ins),
25826"if (!p0) jumpr r31",
25827tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 {
25828let Inst{12-0} = 0b1111111000101;
25829let isPredicated = 1;
25830let isPredicatedFalse = 1;
25831let isTerminator = 1;
25832let isIndirectBranch = 1;
25833let AsmVariantName = "NonParsable";
25834let cofMax1 = 1;
25835let isReturn = 1;
25836let Uses = [P0, R31];
25837let Defs = [PC];
25838let isTaken = Inst{4};
25839let DecoderNamespace = "SUBINSN_L2";
25840}
25841def SL2_jumpr31_fnew : HInst<
25842(outs),
25843(ins),
25844"if (!p0.new) jumpr:nt r31",
25845tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 {
25846let Inst{12-0} = 0b1111111000111;
25847let isPredicated = 1;
25848let isPredicatedFalse = 1;
25849let isTerminator = 1;
25850let isIndirectBranch = 1;
25851let AsmVariantName = "NonParsable";
25852let isPredicatedNew = 1;
25853let cofMax1 = 1;
25854let isReturn = 1;
25855let Uses = [P0, R31];
25856let Defs = [PC];
25857let isTaken = Inst{4};
25858let DecoderNamespace = "SUBINSN_L2";
25859}
25860def SL2_jumpr31_t : HInst<
25861(outs),
25862(ins),
25863"if (p0) jumpr r31",
25864tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 {
25865let Inst{12-0} = 0b1111111000100;
25866let isPredicated = 1;
25867let isTerminator = 1;
25868let isIndirectBranch = 1;
25869let AsmVariantName = "NonParsable";
25870let cofMax1 = 1;
25871let isReturn = 1;
25872let Uses = [P0, R31];
25873let Defs = [PC];
25874let isTaken = Inst{4};
25875let DecoderNamespace = "SUBINSN_L2";
25876}
25877def SL2_jumpr31_tnew : HInst<
25878(outs),
25879(ins),
25880"if (p0.new) jumpr:nt r31",
25881tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 {
25882let Inst{12-0} = 0b1111111000110;
25883let isPredicated = 1;
25884let isTerminator = 1;
25885let isIndirectBranch = 1;
25886let AsmVariantName = "NonParsable";
25887let isPredicatedNew = 1;
25888let cofMax1 = 1;
25889let isReturn = 1;
25890let Uses = [P0, R31];
25891let Defs = [PC];
25892let isTaken = Inst{4};
25893let DecoderNamespace = "SUBINSN_L2";
25894}
25895def SL2_loadrb_io : HInst<
25896(outs GeneralSubRegs:$Rd16),
25897(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
25898"$Rd16 = memb($Rs16+#$Ii)",
25899tc_17e0d2cd, TypeSUBINSN>, Enc_2fbf3c {
25900let Inst{12-11} = 0b10;
25901let hasNewValue = 1;
25902let opNewValue = 0;
25903let addrMode = BaseImmOffset;
25904let accessSize = ByteAccess;
25905let AsmVariantName = "NonParsable";
25906let mayLoad = 1;
25907let DecoderNamespace = "SUBINSN_L2";
25908}
25909def SL2_loadrd_sp : HInst<
25910(outs GeneralDoubleLow8Regs:$Rdd8),
25911(ins u5_3Imm:$Ii),
25912"$Rdd8 = memd(r29+#$Ii)",
25913tc_c4db48cb, TypeSUBINSN>, Enc_86a14b {
25914let Inst{12-8} = 0b11110;
25915let hasNewValue = 1;
25916let opNewValue = 0;
25917let addrMode = BaseImmOffset;
25918let accessSize = DoubleWordAccess;
25919let AsmVariantName = "NonParsable";
25920let mayLoad = 1;
25921let Uses = [R29];
25922let DecoderNamespace = "SUBINSN_L2";
25923}
25924def SL2_loadrh_io : HInst<
25925(outs GeneralSubRegs:$Rd16),
25926(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
25927"$Rd16 = memh($Rs16+#$Ii)",
25928tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 {
25929let Inst{12-11} = 0b00;
25930let hasNewValue = 1;
25931let opNewValue = 0;
25932let addrMode = BaseImmOffset;
25933let accessSize = HalfWordAccess;
25934let AsmVariantName = "NonParsable";
25935let mayLoad = 1;
25936let DecoderNamespace = "SUBINSN_L2";
25937}
25938def SL2_loadri_sp : HInst<
25939(outs GeneralSubRegs:$Rd16),
25940(ins u5_2Imm:$Ii),
25941"$Rd16 = memw(r29+#$Ii)",
25942tc_c4db48cb, TypeSUBINSN>, Enc_51635c {
25943let Inst{12-9} = 0b1110;
25944let hasNewValue = 1;
25945let opNewValue = 0;
25946let addrMode = BaseImmOffset;
25947let accessSize = WordAccess;
25948let AsmVariantName = "NonParsable";
25949let mayLoad = 1;
25950let Uses = [R29];
25951let DecoderNamespace = "SUBINSN_L2";
25952}
25953def SL2_loadruh_io : HInst<
25954(outs GeneralSubRegs:$Rd16),
25955(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
25956"$Rd16 = memuh($Rs16+#$Ii)",
25957tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 {
25958let Inst{12-11} = 0b01;
25959let hasNewValue = 1;
25960let opNewValue = 0;
25961let addrMode = BaseImmOffset;
25962let accessSize = HalfWordAccess;
25963let AsmVariantName = "NonParsable";
25964let mayLoad = 1;
25965let DecoderNamespace = "SUBINSN_L2";
25966}
25967def SL2_return : HInst<
25968(outs),
25969(ins),
25970"dealloc_return",
25971tc_36153880, TypeSUBINSN>, Enc_e3b0c4 {
25972let Inst{12-0} = 0b1111101000000;
25973let isTerminator = 1;
25974let isIndirectBranch = 1;
25975let accessSize = DoubleWordAccess;
25976let AsmVariantName = "NonParsable";
25977let mayLoad = 1;
25978let cofMax1 = 1;
25979let isRestrictNoSlot1Store = 1;
25980let isReturn = 1;
25981let Uses = [FRAMEKEY, R30];
25982let Defs = [PC, R30, R29, R31];
25983let DecoderNamespace = "SUBINSN_L2";
25984}
25985def SL2_return_f : HInst<
25986(outs),
25987(ins),
25988"if (!p0) dealloc_return",
25989tc_36153880, TypeSUBINSN>, Enc_e3b0c4 {
25990let Inst{12-0} = 0b1111101000101;
25991let isPredicated = 1;
25992let isPredicatedFalse = 1;
25993let isTerminator = 1;
25994let isIndirectBranch = 1;
25995let accessSize = DoubleWordAccess;
25996let AsmVariantName = "NonParsable";
25997let mayLoad = 1;
25998let cofMax1 = 1;
25999let isRestrictNoSlot1Store = 1;
26000let isReturn = 1;
26001let Uses = [FRAMEKEY, P0, R30];
26002let Defs = [PC, R30, R29, R31];
26003let isTaken = Inst{4};
26004let DecoderNamespace = "SUBINSN_L2";
26005}
26006def SL2_return_fnew : HInst<
26007(outs),
26008(ins),
26009"if (!p0.new) dealloc_return:nt",
26010tc_36153880, TypeSUBINSN>, Enc_e3b0c4 {
26011let Inst{12-0} = 0b1111101000111;
26012let isPredicated = 1;
26013let isPredicatedFalse = 1;
26014let isTerminator = 1;
26015let isIndirectBranch = 1;
26016let accessSize = DoubleWordAccess;
26017let AsmVariantName = "NonParsable";
26018let isPredicatedNew = 1;
26019let mayLoad = 1;
26020let cofMax1 = 1;
26021let isRestrictNoSlot1Store = 1;
26022let isReturn = 1;
26023let Uses = [FRAMEKEY, P0, R30];
26024let Defs = [PC, R30, R29, R31];
26025let isTaken = Inst{4};
26026let DecoderNamespace = "SUBINSN_L2";
26027}
26028def SL2_return_t : HInst<
26029(outs),
26030(ins),
26031"if (p0) dealloc_return",
26032tc_36153880, TypeSUBINSN>, Enc_e3b0c4 {
26033let Inst{12-0} = 0b1111101000100;
26034let isPredicated = 1;
26035let isTerminator = 1;
26036let isIndirectBranch = 1;
26037let accessSize = DoubleWordAccess;
26038let AsmVariantName = "NonParsable";
26039let mayLoad = 1;
26040let cofMax1 = 1;
26041let isRestrictNoSlot1Store = 1;
26042let isReturn = 1;
26043let Uses = [FRAMEKEY, P0, R30];
26044let Defs = [PC, R30, R29, R31];
26045let isTaken = Inst{4};
26046let DecoderNamespace = "SUBINSN_L2";
26047}
26048def SL2_return_tnew : HInst<
26049(outs),
26050(ins),
26051"if (p0.new) dealloc_return:nt",
26052tc_36153880, TypeSUBINSN>, Enc_e3b0c4 {
26053let Inst{12-0} = 0b1111101000110;
26054let isPredicated = 1;
26055let isTerminator = 1;
26056let isIndirectBranch = 1;
26057let accessSize = DoubleWordAccess;
26058let AsmVariantName = "NonParsable";
26059let isPredicatedNew = 1;
26060let mayLoad = 1;
26061let cofMax1 = 1;
26062let isRestrictNoSlot1Store = 1;
26063let isReturn = 1;
26064let Uses = [FRAMEKEY, P0, R30];
26065let Defs = [PC, R30, R29, R31];
26066let isTaken = Inst{4};
26067let DecoderNamespace = "SUBINSN_L2";
26068}
26069def SS1_storeb_io : HInst<
26070(outs),
26071(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
26072"memb($Rs16+#$Ii) = $Rt16",
26073tc_30b9bb4a, TypeSUBINSN>, Enc_b38ffc {
26074let Inst{12-12} = 0b1;
26075let addrMode = BaseImmOffset;
26076let accessSize = ByteAccess;
26077let AsmVariantName = "NonParsable";
26078let mayStore = 1;
26079let DecoderNamespace = "SUBINSN_S1";
26080}
26081def SS1_storew_io : HInst<
26082(outs),
26083(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
26084"memw($Rs16+#$Ii) = $Rt16",
26085tc_30b9bb4a, TypeSUBINSN>, Enc_f55a0c {
26086let Inst{12-12} = 0b0;
26087let addrMode = BaseImmOffset;
26088let accessSize = WordAccess;
26089let AsmVariantName = "NonParsable";
26090let mayStore = 1;
26091let DecoderNamespace = "SUBINSN_S1";
26092}
26093def SS2_allocframe : HInst<
26094(outs),
26095(ins u5_3Imm:$Ii),
26096"allocframe(#$Ii)",
26097tc_49a8207d, TypeSUBINSN>, Enc_6f70ca {
26098let Inst{3-0} = 0b0000;
26099let Inst{12-9} = 0b1110;
26100let addrMode = BaseImmOffset;
26101let accessSize = DoubleWordAccess;
26102let AsmVariantName = "NonParsable";
26103let mayStore = 1;
26104let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31];
26105let Defs = [R30, R29];
26106let DecoderNamespace = "SUBINSN_S2";
26107}
26108def SS2_storebi0 : HInst<
26109(outs),
26110(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26111"memb($Rs16+#$Ii) = #0",
26112tc_89e94ad3, TypeSUBINSN>, Enc_84d359 {
26113let Inst{12-8} = 0b10010;
26114let addrMode = BaseImmOffset;
26115let accessSize = ByteAccess;
26116let AsmVariantName = "NonParsable";
26117let mayStore = 1;
26118let DecoderNamespace = "SUBINSN_S2";
26119}
26120def SS2_storebi1 : HInst<
26121(outs),
26122(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26123"memb($Rs16+#$Ii) = #1",
26124tc_89e94ad3, TypeSUBINSN>, Enc_84d359 {
26125let Inst{12-8} = 0b10011;
26126let addrMode = BaseImmOffset;
26127let accessSize = ByteAccess;
26128let AsmVariantName = "NonParsable";
26129let mayStore = 1;
26130let DecoderNamespace = "SUBINSN_S2";
26131}
26132def SS2_stored_sp : HInst<
26133(outs),
26134(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
26135"memd(r29+#$Ii) = $Rtt8",
26136tc_0371abea, TypeSUBINSN>, Enc_b8309d {
26137let Inst{12-9} = 0b0101;
26138let addrMode = BaseImmOffset;
26139let accessSize = DoubleWordAccess;
26140let AsmVariantName = "NonParsable";
26141let mayStore = 1;
26142let Uses = [R29];
26143let DecoderNamespace = "SUBINSN_S2";
26144}
26145def SS2_storeh_io : HInst<
26146(outs),
26147(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
26148"memh($Rs16+#$Ii) = $Rt16",
26149tc_30b9bb4a, TypeSUBINSN>, Enc_625deb {
26150let Inst{12-11} = 0b00;
26151let addrMode = BaseImmOffset;
26152let accessSize = HalfWordAccess;
26153let AsmVariantName = "NonParsable";
26154let mayStore = 1;
26155let DecoderNamespace = "SUBINSN_S2";
26156}
26157def SS2_storew_sp : HInst<
26158(outs),
26159(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
26160"memw(r29+#$Ii) = $Rt16",
26161tc_0371abea, TypeSUBINSN>, Enc_87c142 {
26162let Inst{12-9} = 0b0100;
26163let addrMode = BaseImmOffset;
26164let accessSize = WordAccess;
26165let AsmVariantName = "NonParsable";
26166let mayStore = 1;
26167let Uses = [R29];
26168let DecoderNamespace = "SUBINSN_S2";
26169}
26170def SS2_storewi0 : HInst<
26171(outs),
26172(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26173"memw($Rs16+#$Ii) = #0",
26174tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c {
26175let Inst{12-8} = 0b10000;
26176let addrMode = BaseImmOffset;
26177let accessSize = WordAccess;
26178let AsmVariantName = "NonParsable";
26179let mayStore = 1;
26180let DecoderNamespace = "SUBINSN_S2";
26181}
26182def SS2_storewi1 : HInst<
26183(outs),
26184(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26185"memw($Rs16+#$Ii) = #1",
26186tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c {
26187let Inst{12-8} = 0b10001;
26188let addrMode = BaseImmOffset;
26189let accessSize = WordAccess;
26190let AsmVariantName = "NonParsable";
26191let mayStore = 1;
26192let DecoderNamespace = "SUBINSN_S2";
26193}
26194def V6_MAP_equb : HInst<
26195(outs HvxQR:$Qd4),
26196(ins HvxVR:$Vu32, HvxVR:$Vv32),
26197"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
26198PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26199let hasNewValue = 1;
26200let opNewValue = 0;
26201let isPseudo = 1;
26202let isCodeGenOnly = 1;
26203let DecoderNamespace = "EXT_mmvec";
26204}
26205def V6_MAP_equb_and : HInst<
26206(outs HvxQR:$Qx4),
26207(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26208"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
26209PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26210let isPseudo = 1;
26211let isCodeGenOnly = 1;
26212let DecoderNamespace = "EXT_mmvec";
26213let Constraints = "$Qx4 = $Qx4in";
26214}
26215def V6_MAP_equb_ior : HInst<
26216(outs HvxQR:$Qx4),
26217(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26218"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
26219PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26220let isAccumulator = 1;
26221let isPseudo = 1;
26222let isCodeGenOnly = 1;
26223let DecoderNamespace = "EXT_mmvec";
26224let Constraints = "$Qx4 = $Qx4in";
26225}
26226def V6_MAP_equb_xor : HInst<
26227(outs HvxQR:$Qx4),
26228(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26229"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
26230PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26231let isPseudo = 1;
26232let isCodeGenOnly = 1;
26233let DecoderNamespace = "EXT_mmvec";
26234let Constraints = "$Qx4 = $Qx4in";
26235}
26236def V6_MAP_equh : HInst<
26237(outs HvxQR:$Qd4),
26238(ins HvxVR:$Vu32, HvxVR:$Vv32),
26239"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
26240PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26241let hasNewValue = 1;
26242let opNewValue = 0;
26243let isPseudo = 1;
26244let isCodeGenOnly = 1;
26245let DecoderNamespace = "EXT_mmvec";
26246}
26247def V6_MAP_equh_and : HInst<
26248(outs HvxQR:$Qx4),
26249(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26250"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
26251PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26252let isPseudo = 1;
26253let isCodeGenOnly = 1;
26254let DecoderNamespace = "EXT_mmvec";
26255let Constraints = "$Qx4 = $Qx4in";
26256}
26257def V6_MAP_equh_ior : HInst<
26258(outs HvxQR:$Qx4),
26259(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26260"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
26261PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26262let isAccumulator = 1;
26263let isPseudo = 1;
26264let isCodeGenOnly = 1;
26265let DecoderNamespace = "EXT_mmvec";
26266let Constraints = "$Qx4 = $Qx4in";
26267}
26268def V6_MAP_equh_xor : HInst<
26269(outs HvxQR:$Qx4),
26270(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26271"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
26272PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26273let isPseudo = 1;
26274let isCodeGenOnly = 1;
26275let DecoderNamespace = "EXT_mmvec";
26276let Constraints = "$Qx4 = $Qx4in";
26277}
26278def V6_MAP_equw : HInst<
26279(outs HvxQR:$Qd4),
26280(ins HvxVR:$Vu32, HvxVR:$Vv32),
26281"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
26282PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26283let hasNewValue = 1;
26284let opNewValue = 0;
26285let isPseudo = 1;
26286let isCodeGenOnly = 1;
26287let DecoderNamespace = "EXT_mmvec";
26288}
26289def V6_MAP_equw_and : HInst<
26290(outs HvxQR:$Qx4),
26291(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26292"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
26293PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26294let isPseudo = 1;
26295let isCodeGenOnly = 1;
26296let DecoderNamespace = "EXT_mmvec";
26297let Constraints = "$Qx4 = $Qx4in";
26298}
26299def V6_MAP_equw_ior : HInst<
26300(outs HvxQR:$Qx4),
26301(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26302"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
26303PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26304let isAccumulator = 1;
26305let isPseudo = 1;
26306let isCodeGenOnly = 1;
26307let DecoderNamespace = "EXT_mmvec";
26308let Constraints = "$Qx4 = $Qx4in";
26309}
26310def V6_MAP_equw_xor : HInst<
26311(outs HvxQR:$Qx4),
26312(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26313"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
26314PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26315let isPseudo = 1;
26316let isCodeGenOnly = 1;
26317let DecoderNamespace = "EXT_mmvec";
26318let Constraints = "$Qx4 = $Qx4in";
26319}
26320def V6_extractw : HInst<
26321(outs IntRegs:$Rd32),
26322(ins HvxVR:$Vu32, IntRegs:$Rs32),
26323"$Rd32 = vextract($Vu32,$Rs32)",
26324tc_540c3da3, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
26325let Inst{7-5} = 0b001;
26326let Inst{13-13} = 0b0;
26327let Inst{31-21} = 0b10010010000;
26328let hasNewValue = 1;
26329let opNewValue = 0;
26330let isSolo = 1;
26331let mayLoad = 1;
26332let DecoderNamespace = "EXT_mmvec";
26333}
26334def V6_extractw_alt : HInst<
26335(outs IntRegs:$Rd32),
26336(ins HvxVR:$Vu32, IntRegs:$Rs32),
26337"$Rd32.w = vextract($Vu32,$Rs32)",
26338PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26339let hasNewValue = 1;
26340let opNewValue = 0;
26341let isPseudo = 1;
26342let isCodeGenOnly = 1;
26343let DecoderNamespace = "EXT_mmvec";
26344}
26345def V6_hi : HInst<
26346(outs HvxVR:$Vd32),
26347(ins HvxWR:$Vss32),
26348"$Vd32 = hi($Vss32)",
26349CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26350let hasNewValue = 1;
26351let opNewValue = 0;
26352let isPseudo = 1;
26353let DecoderNamespace = "EXT_mmvec";
26354}
26355def V6_ld0 : HInst<
26356(outs HvxVR:$Vd32),
26357(ins IntRegs:$Rt32),
26358"$Vd32 = vmem($Rt32)",
26359PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26360let hasNewValue = 1;
26361let opNewValue = 0;
26362let isPseudo = 1;
26363let isCodeGenOnly = 1;
26364let DecoderNamespace = "EXT_mmvec";
26365}
26366def V6_ldcnp0 : HInst<
26367(outs HvxVR:$Vd32),
26368(ins PredRegs:$Pv4, IntRegs:$Rt32),
26369"if (!$Pv4) $Vd32.cur = vmem($Rt32)",
26370PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26371let hasNewValue = 1;
26372let opNewValue = 0;
26373let isPseudo = 1;
26374let isCodeGenOnly = 1;
26375let DecoderNamespace = "EXT_mmvec";
26376}
26377def V6_ldcnpnt0 : HInst<
26378(outs HvxVR:$Vd32),
26379(ins PredRegs:$Pv4, IntRegs:$Rt32),
26380"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
26381PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26382let hasNewValue = 1;
26383let opNewValue = 0;
26384let isPseudo = 1;
26385let isCodeGenOnly = 1;
26386let DecoderNamespace = "EXT_mmvec";
26387}
26388def V6_ldcp0 : HInst<
26389(outs HvxVR:$Vd32),
26390(ins PredRegs:$Pv4, IntRegs:$Rt32),
26391"if ($Pv4) $Vd32.cur = vmem($Rt32)",
26392PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26393let hasNewValue = 1;
26394let opNewValue = 0;
26395let isPseudo = 1;
26396let isCodeGenOnly = 1;
26397let DecoderNamespace = "EXT_mmvec";
26398}
26399def V6_ldcpnt0 : HInst<
26400(outs HvxVR:$Vd32),
26401(ins PredRegs:$Pv4, IntRegs:$Rt32),
26402"if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
26403PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26404let hasNewValue = 1;
26405let opNewValue = 0;
26406let isPseudo = 1;
26407let isCodeGenOnly = 1;
26408let DecoderNamespace = "EXT_mmvec";
26409}
26410def V6_ldnp0 : HInst<
26411(outs HvxVR:$Vd32),
26412(ins PredRegs:$Pv4, IntRegs:$Rt32),
26413"if (!$Pv4) $Vd32 = vmem($Rt32)",
26414PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26415let hasNewValue = 1;
26416let opNewValue = 0;
26417let isPseudo = 1;
26418let isCodeGenOnly = 1;
26419let DecoderNamespace = "EXT_mmvec";
26420}
26421def V6_ldnpnt0 : HInst<
26422(outs HvxVR:$Vd32),
26423(ins PredRegs:$Pv4, IntRegs:$Rt32),
26424"if (!$Pv4) $Vd32 = vmem($Rt32):nt",
26425PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26426let hasNewValue = 1;
26427let opNewValue = 0;
26428let isPseudo = 1;
26429let isCodeGenOnly = 1;
26430let DecoderNamespace = "EXT_mmvec";
26431}
26432def V6_ldnt0 : HInst<
26433(outs HvxVR:$Vd32),
26434(ins IntRegs:$Rt32),
26435"$Vd32 = vmem($Rt32):nt",
26436PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26437let hasNewValue = 1;
26438let opNewValue = 0;
26439let isPseudo = 1;
26440let isCodeGenOnly = 1;
26441let DecoderNamespace = "EXT_mmvec";
26442}
26443def V6_ldntnt0 : HInst<
26444(outs HvxVR:$Vd32),
26445(ins IntRegs:$Rt32),
26446"$Vd32 = vmem($Rt32):nt",
26447PSEUDO, TypeMAPPING>, Requires<[HasV62]> {
26448let hasNewValue = 1;
26449let opNewValue = 0;
26450let isPseudo = 1;
26451let isCodeGenOnly = 1;
26452let DecoderNamespace = "EXT_mmvec";
26453}
26454def V6_ldp0 : HInst<
26455(outs HvxVR:$Vd32),
26456(ins PredRegs:$Pv4, IntRegs:$Rt32),
26457"if ($Pv4) $Vd32 = vmem($Rt32)",
26458PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26459let hasNewValue = 1;
26460let opNewValue = 0;
26461let isPseudo = 1;
26462let isCodeGenOnly = 1;
26463let DecoderNamespace = "EXT_mmvec";
26464}
26465def V6_ldpnt0 : HInst<
26466(outs HvxVR:$Vd32),
26467(ins PredRegs:$Pv4, IntRegs:$Rt32),
26468"if ($Pv4) $Vd32 = vmem($Rt32):nt",
26469PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26470let hasNewValue = 1;
26471let opNewValue = 0;
26472let isPseudo = 1;
26473let isCodeGenOnly = 1;
26474let DecoderNamespace = "EXT_mmvec";
26475}
26476def V6_ldtnp0 : HInst<
26477(outs HvxVR:$Vd32),
26478(ins PredRegs:$Pv4, IntRegs:$Rt32),
26479"if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
26480PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26481let hasNewValue = 1;
26482let opNewValue = 0;
26483let isPseudo = 1;
26484let isCodeGenOnly = 1;
26485let DecoderNamespace = "EXT_mmvec";
26486}
26487def V6_ldtnpnt0 : HInst<
26488(outs HvxVR:$Vd32),
26489(ins PredRegs:$Pv4, IntRegs:$Rt32),
26490"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
26491PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26492let hasNewValue = 1;
26493let opNewValue = 0;
26494let isPseudo = 1;
26495let isCodeGenOnly = 1;
26496let DecoderNamespace = "EXT_mmvec";
26497}
26498def V6_ldtp0 : HInst<
26499(outs HvxVR:$Vd32),
26500(ins PredRegs:$Pv4, IntRegs:$Rt32),
26501"if ($Pv4) $Vd32.tmp = vmem($Rt32)",
26502PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26503let hasNewValue = 1;
26504let opNewValue = 0;
26505let isPseudo = 1;
26506let isCodeGenOnly = 1;
26507let DecoderNamespace = "EXT_mmvec";
26508}
26509def V6_ldtpnt0 : HInst<
26510(outs HvxVR:$Vd32),
26511(ins PredRegs:$Pv4, IntRegs:$Rt32),
26512"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
26513PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26514let hasNewValue = 1;
26515let opNewValue = 0;
26516let isPseudo = 1;
26517let isCodeGenOnly = 1;
26518let DecoderNamespace = "EXT_mmvec";
26519}
26520def V6_ldu0 : HInst<
26521(outs HvxVR:$Vd32),
26522(ins IntRegs:$Rt32),
26523"$Vd32 = vmemu($Rt32)",
26524PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26525let hasNewValue = 1;
26526let opNewValue = 0;
26527let isPseudo = 1;
26528let isCodeGenOnly = 1;
26529let DecoderNamespace = "EXT_mmvec";
26530}
26531def V6_lo : HInst<
26532(outs HvxVR:$Vd32),
26533(ins HvxWR:$Vss32),
26534"$Vd32 = lo($Vss32)",
26535CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26536let hasNewValue = 1;
26537let opNewValue = 0;
26538let isPseudo = 1;
26539let DecoderNamespace = "EXT_mmvec";
26540}
26541def V6_lvsplatb : HInst<
26542(outs HvxVR:$Vd32),
26543(ins IntRegs:$Rt32),
26544"$Vd32.b = vsplat($Rt32)",
26545tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26546let Inst{13-5} = 0b000000010;
26547let Inst{31-21} = 0b00011001110;
26548let hasNewValue = 1;
26549let opNewValue = 0;
26550let DecoderNamespace = "EXT_mmvec";
26551}
26552def V6_lvsplath : HInst<
26553(outs HvxVR:$Vd32),
26554(ins IntRegs:$Rt32),
26555"$Vd32.h = vsplat($Rt32)",
26556tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26557let Inst{13-5} = 0b000000001;
26558let Inst{31-21} = 0b00011001110;
26559let hasNewValue = 1;
26560let opNewValue = 0;
26561let DecoderNamespace = "EXT_mmvec";
26562}
26563def V6_lvsplatw : HInst<
26564(outs HvxVR:$Vd32),
26565(ins IntRegs:$Rt32),
26566"$Vd32 = vsplat($Rt32)",
26567tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
26568let Inst{13-5} = 0b000000001;
26569let Inst{31-21} = 0b00011001101;
26570let hasNewValue = 1;
26571let opNewValue = 0;
26572let DecoderNamespace = "EXT_mmvec";
26573}
26574def V6_pred_and : HInst<
26575(outs HvxQR:$Qd4),
26576(ins HvxQR:$Qs4, HvxQR:$Qt4),
26577"$Qd4 = and($Qs4,$Qt4)",
26578tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26579let Inst{7-2} = 0b000000;
26580let Inst{13-10} = 0b0000;
26581let Inst{21-16} = 0b000011;
26582let Inst{31-24} = 0b00011110;
26583let hasNewValue = 1;
26584let opNewValue = 0;
26585let DecoderNamespace = "EXT_mmvec";
26586}
26587def V6_pred_and_n : HInst<
26588(outs HvxQR:$Qd4),
26589(ins HvxQR:$Qs4, HvxQR:$Qt4),
26590"$Qd4 = and($Qs4,!$Qt4)",
26591tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26592let Inst{7-2} = 0b000101;
26593let Inst{13-10} = 0b0000;
26594let Inst{21-16} = 0b000011;
26595let Inst{31-24} = 0b00011110;
26596let hasNewValue = 1;
26597let opNewValue = 0;
26598let DecoderNamespace = "EXT_mmvec";
26599}
26600def V6_pred_not : HInst<
26601(outs HvxQR:$Qd4),
26602(ins HvxQR:$Qs4),
26603"$Qd4 = not($Qs4)",
26604tc_0ec46cf9, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
26605let Inst{7-2} = 0b000010;
26606let Inst{13-10} = 0b0000;
26607let Inst{31-16} = 0b0001111000000011;
26608let hasNewValue = 1;
26609let opNewValue = 0;
26610let DecoderNamespace = "EXT_mmvec";
26611}
26612def V6_pred_or : HInst<
26613(outs HvxQR:$Qd4),
26614(ins HvxQR:$Qs4, HvxQR:$Qt4),
26615"$Qd4 = or($Qs4,$Qt4)",
26616tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26617let Inst{7-2} = 0b000001;
26618let Inst{13-10} = 0b0000;
26619let Inst{21-16} = 0b000011;
26620let Inst{31-24} = 0b00011110;
26621let hasNewValue = 1;
26622let opNewValue = 0;
26623let DecoderNamespace = "EXT_mmvec";
26624}
26625def V6_pred_or_n : HInst<
26626(outs HvxQR:$Qd4),
26627(ins HvxQR:$Qs4, HvxQR:$Qt4),
26628"$Qd4 = or($Qs4,!$Qt4)",
26629tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26630let Inst{7-2} = 0b000100;
26631let Inst{13-10} = 0b0000;
26632let Inst{21-16} = 0b000011;
26633let Inst{31-24} = 0b00011110;
26634let hasNewValue = 1;
26635let opNewValue = 0;
26636let DecoderNamespace = "EXT_mmvec";
26637}
26638def V6_pred_scalar2 : HInst<
26639(outs HvxQR:$Qd4),
26640(ins IntRegs:$Rt32),
26641"$Qd4 = vsetq($Rt32)",
26642tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
26643let Inst{13-2} = 0b000000010001;
26644let Inst{31-21} = 0b00011001101;
26645let hasNewValue = 1;
26646let opNewValue = 0;
26647let DecoderNamespace = "EXT_mmvec";
26648}
26649def V6_pred_scalar2v2 : HInst<
26650(outs HvxQR:$Qd4),
26651(ins IntRegs:$Rt32),
26652"$Qd4 = vsetq2($Rt32)",
26653tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
26654let Inst{13-2} = 0b000000010011;
26655let Inst{31-21} = 0b00011001101;
26656let hasNewValue = 1;
26657let opNewValue = 0;
26658let DecoderNamespace = "EXT_mmvec";
26659}
26660def V6_pred_xor : HInst<
26661(outs HvxQR:$Qd4),
26662(ins HvxQR:$Qs4, HvxQR:$Qt4),
26663"$Qd4 = xor($Qs4,$Qt4)",
26664tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
26665let Inst{7-2} = 0b000011;
26666let Inst{13-10} = 0b0000;
26667let Inst{21-16} = 0b000011;
26668let Inst{31-24} = 0b00011110;
26669let hasNewValue = 1;
26670let opNewValue = 0;
26671let DecoderNamespace = "EXT_mmvec";
26672}
26673def V6_shuffeqh : HInst<
26674(outs HvxQR:$Qd4),
26675(ins HvxQR:$Qs4, HvxQR:$Qt4),
26676"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
26677tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
26678let Inst{7-2} = 0b000110;
26679let Inst{13-10} = 0b0000;
26680let Inst{21-16} = 0b000011;
26681let Inst{31-24} = 0b00011110;
26682let hasNewValue = 1;
26683let opNewValue = 0;
26684let DecoderNamespace = "EXT_mmvec";
26685}
26686def V6_shuffeqw : HInst<
26687(outs HvxQR:$Qd4),
26688(ins HvxQR:$Qs4, HvxQR:$Qt4),
26689"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
26690tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
26691let Inst{7-2} = 0b000111;
26692let Inst{13-10} = 0b0000;
26693let Inst{21-16} = 0b000011;
26694let Inst{31-24} = 0b00011110;
26695let hasNewValue = 1;
26696let opNewValue = 0;
26697let DecoderNamespace = "EXT_mmvec";
26698}
26699def V6_st0 : HInst<
26700(outs),
26701(ins IntRegs:$Rt32, HvxVR:$Vs32),
26702"vmem($Rt32) = $Vs32",
26703PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26704let isPseudo = 1;
26705let isCodeGenOnly = 1;
26706let DecoderNamespace = "EXT_mmvec";
26707}
26708def V6_stn0 : HInst<
26709(outs),
26710(ins IntRegs:$Rt32, HvxVR:$Os8),
26711"vmem($Rt32) = $Os8.new",
26712PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26713let isPseudo = 1;
26714let isCodeGenOnly = 1;
26715let DecoderNamespace = "EXT_mmvec";
26716let opNewValue = 1;
26717}
26718def V6_stnnt0 : HInst<
26719(outs),
26720(ins IntRegs:$Rt32, HvxVR:$Os8),
26721"vmem($Rt32):nt = $Os8.new",
26722PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26723let isPseudo = 1;
26724let isCodeGenOnly = 1;
26725let DecoderNamespace = "EXT_mmvec";
26726let opNewValue = 1;
26727}
26728def V6_stnp0 : HInst<
26729(outs),
26730(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26731"if (!$Pv4) vmem($Rt32) = $Vs32",
26732PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26733let isPseudo = 1;
26734let isCodeGenOnly = 1;
26735let DecoderNamespace = "EXT_mmvec";
26736}
26737def V6_stnpnt0 : HInst<
26738(outs),
26739(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26740"if (!$Pv4) vmem($Rt32):nt = $Vs32",
26741PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26742let isPseudo = 1;
26743let isCodeGenOnly = 1;
26744let DecoderNamespace = "EXT_mmvec";
26745}
26746def V6_stnq0 : HInst<
26747(outs),
26748(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26749"if (!$Qv4) vmem($Rt32) = $Vs32",
26750PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26751let isPseudo = 1;
26752let isCodeGenOnly = 1;
26753let DecoderNamespace = "EXT_mmvec";
26754}
26755def V6_stnqnt0 : HInst<
26756(outs),
26757(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26758"if (!$Qv4) vmem($Rt32):nt = $Vs32",
26759PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26760let isPseudo = 1;
26761let isCodeGenOnly = 1;
26762let DecoderNamespace = "EXT_mmvec";
26763}
26764def V6_stnt0 : HInst<
26765(outs),
26766(ins IntRegs:$Rt32, HvxVR:$Vs32),
26767"vmem($Rt32):nt = $Vs32",
26768PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26769let isPseudo = 1;
26770let isCodeGenOnly = 1;
26771let DecoderNamespace = "EXT_mmvec";
26772}
26773def V6_stp0 : HInst<
26774(outs),
26775(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26776"if ($Pv4) vmem($Rt32) = $Vs32",
26777PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26778let isPseudo = 1;
26779let isCodeGenOnly = 1;
26780let DecoderNamespace = "EXT_mmvec";
26781}
26782def V6_stpnt0 : HInst<
26783(outs),
26784(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26785"if ($Pv4) vmem($Rt32):nt = $Vs32",
26786PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26787let isPseudo = 1;
26788let isCodeGenOnly = 1;
26789let DecoderNamespace = "EXT_mmvec";
26790}
26791def V6_stq0 : HInst<
26792(outs),
26793(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26794"if ($Qv4) vmem($Rt32) = $Vs32",
26795PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26796let isPseudo = 1;
26797let isCodeGenOnly = 1;
26798let DecoderNamespace = "EXT_mmvec";
26799}
26800def V6_stqnt0 : HInst<
26801(outs),
26802(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
26803"if ($Qv4) vmem($Rt32):nt = $Vs32",
26804PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26805let isPseudo = 1;
26806let isCodeGenOnly = 1;
26807let DecoderNamespace = "EXT_mmvec";
26808}
26809def V6_stu0 : HInst<
26810(outs),
26811(ins IntRegs:$Rt32, HvxVR:$Vs32),
26812"vmemu($Rt32) = $Vs32",
26813PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26814let isPseudo = 1;
26815let isCodeGenOnly = 1;
26816let DecoderNamespace = "EXT_mmvec";
26817}
26818def V6_stunp0 : HInst<
26819(outs),
26820(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26821"if (!$Pv4) vmemu($Rt32) = $Vs32",
26822PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26823let isPseudo = 1;
26824let isCodeGenOnly = 1;
26825let DecoderNamespace = "EXT_mmvec";
26826}
26827def V6_stup0 : HInst<
26828(outs),
26829(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
26830"if ($Pv4) vmemu($Rt32) = $Vs32",
26831PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
26832let isPseudo = 1;
26833let isCodeGenOnly = 1;
26834let DecoderNamespace = "EXT_mmvec";
26835}
26836def V6_vL32Ub_ai : HInst<
26837(outs HvxVR:$Vd32),
26838(ins IntRegs:$Rt32, s4_0Imm:$Ii),
26839"$Vd32 = vmemu($Rt32+#$Ii)",
26840tc_a7e6707d, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> {
26841let Inst{7-5} = 0b111;
26842let Inst{12-11} = 0b00;
26843let Inst{31-21} = 0b00101000000;
26844let hasNewValue = 1;
26845let opNewValue = 0;
26846let addrMode = BaseImmOffset;
26847let accessSize = HVXVectorAccess;
26848let isCVLoad = 1;
26849let mayLoad = 1;
26850let isRestrictNoSlot1Store = 1;
26851let DecoderNamespace = "EXT_mmvec";
26852}
26853def V6_vL32Ub_pi : HInst<
26854(outs HvxVR:$Vd32, IntRegs:$Rx32),
26855(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
26856"$Vd32 = vmemu($Rx32++#$Ii)",
26857tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> {
26858let Inst{7-5} = 0b111;
26859let Inst{13-11} = 0b000;
26860let Inst{31-21} = 0b00101001000;
26861let hasNewValue = 1;
26862let opNewValue = 0;
26863let addrMode = PostInc;
26864let accessSize = HVXVectorAccess;
26865let isCVLoad = 1;
26866let mayLoad = 1;
26867let isRestrictNoSlot1Store = 1;
26868let BaseOpcode = "V6_vL32b_pi";
26869let DecoderNamespace = "EXT_mmvec";
26870let Constraints = "$Rx32 = $Rx32in";
26871}
26872def V6_vL32Ub_ppu : HInst<
26873(outs HvxVR:$Vd32, IntRegs:$Rx32),
26874(ins IntRegs:$Rx32in, ModRegs:$Mu2),
26875"$Vd32 = vmemu($Rx32++$Mu2)",
26876tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
26877let Inst{12-5} = 0b00000111;
26878let Inst{31-21} = 0b00101011000;
26879let hasNewValue = 1;
26880let opNewValue = 0;
26881let addrMode = PostInc;
26882let accessSize = HVXVectorAccess;
26883let isCVLoad = 1;
26884let mayLoad = 1;
26885let isRestrictNoSlot1Store = 1;
26886let DecoderNamespace = "EXT_mmvec";
26887let Constraints = "$Rx32 = $Rx32in";
26888}
26889def V6_vL32b_ai : HInst<
26890(outs HvxVR:$Vd32),
26891(ins IntRegs:$Rt32, s4_0Imm:$Ii),
26892"$Vd32 = vmem($Rt32+#$Ii)",
26893tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
26894let Inst{7-5} = 0b000;
26895let Inst{12-11} = 0b00;
26896let Inst{31-21} = 0b00101000000;
26897let hasNewValue = 1;
26898let opNewValue = 0;
26899let addrMode = BaseImmOffset;
26900let accessSize = HVXVectorAccess;
26901let isCVLoad = 1;
26902let mayLoad = 1;
26903let isRestrictNoSlot1Store = 1;
26904let BaseOpcode = "V6_vL32b_ai";
26905let isCVLoadable = 1;
26906let isPredicable = 1;
26907let DecoderNamespace = "EXT_mmvec";
26908}
26909def V6_vL32b_cur_ai : HInst<
26910(outs HvxVR:$Vd32),
26911(ins IntRegs:$Rt32, s4_0Imm:$Ii),
26912"$Vd32.cur = vmem($Rt32+#$Ii)",
26913tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
26914let Inst{7-5} = 0b001;
26915let Inst{12-11} = 0b00;
26916let Inst{31-21} = 0b00101000000;
26917let hasNewValue = 1;
26918let opNewValue = 0;
26919let addrMode = BaseImmOffset;
26920let accessSize = HVXVectorAccess;
26921let isCVLoad = 1;
26922let CVINew = 1;
26923let mayLoad = 1;
26924let isRestrictNoSlot1Store = 1;
26925let BaseOpcode = "V6_vL32b_cur_ai";
26926let isPredicable = 1;
26927let DecoderNamespace = "EXT_mmvec";
26928}
26929def V6_vL32b_cur_npred_ai : HInst<
26930(outs HvxVR:$Vd32),
26931(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
26932"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
26933tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
26934let Inst{7-5} = 0b101;
26935let Inst{31-21} = 0b00101000100;
26936let isPredicated = 1;
26937let isPredicatedFalse = 1;
26938let hasNewValue = 1;
26939let opNewValue = 0;
26940let addrMode = BaseImmOffset;
26941let accessSize = HVXVectorAccess;
26942let isCVLoad = 1;
26943let CVINew = 1;
26944let mayLoad = 1;
26945let isRestrictNoSlot1Store = 1;
26946let BaseOpcode = "V6_vL32b_cur_ai";
26947let DecoderNamespace = "EXT_mmvec";
26948}
26949def V6_vL32b_cur_npred_pi : HInst<
26950(outs HvxVR:$Vd32, IntRegs:$Rx32),
26951(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
26952"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
26953tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
26954let Inst{7-5} = 0b101;
26955let Inst{13-13} = 0b0;
26956let Inst{31-21} = 0b00101001100;
26957let isPredicated = 1;
26958let isPredicatedFalse = 1;
26959let hasNewValue = 1;
26960let opNewValue = 0;
26961let addrMode = PostInc;
26962let accessSize = HVXVectorAccess;
26963let isCVLoad = 1;
26964let CVINew = 1;
26965let mayLoad = 1;
26966let isRestrictNoSlot1Store = 1;
26967let BaseOpcode = "V6_vL32b_cur_pi";
26968let DecoderNamespace = "EXT_mmvec";
26969let Constraints = "$Rx32 = $Rx32in";
26970}
26971def V6_vL32b_cur_npred_ppu : HInst<
26972(outs HvxVR:$Vd32, IntRegs:$Rx32),
26973(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
26974"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
26975tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
26976let Inst{10-5} = 0b000101;
26977let Inst{31-21} = 0b00101011100;
26978let isPredicated = 1;
26979let isPredicatedFalse = 1;
26980let hasNewValue = 1;
26981let opNewValue = 0;
26982let addrMode = PostInc;
26983let accessSize = HVXVectorAccess;
26984let isCVLoad = 1;
26985let CVINew = 1;
26986let mayLoad = 1;
26987let isRestrictNoSlot1Store = 1;
26988let BaseOpcode = "V6_vL32b_cur_ppu";
26989let DecoderNamespace = "EXT_mmvec";
26990let Constraints = "$Rx32 = $Rx32in";
26991}
26992def V6_vL32b_cur_pi : HInst<
26993(outs HvxVR:$Vd32, IntRegs:$Rx32),
26994(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
26995"$Vd32.cur = vmem($Rx32++#$Ii)",
26996tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
26997let Inst{7-5} = 0b001;
26998let Inst{13-11} = 0b000;
26999let Inst{31-21} = 0b00101001000;
27000let hasNewValue = 1;
27001let opNewValue = 0;
27002let addrMode = PostInc;
27003let accessSize = HVXVectorAccess;
27004let isCVLoad = 1;
27005let CVINew = 1;
27006let mayLoad = 1;
27007let isRestrictNoSlot1Store = 1;
27008let BaseOpcode = "V6_vL32b_cur_pi";
27009let isPredicable = 1;
27010let DecoderNamespace = "EXT_mmvec";
27011let Constraints = "$Rx32 = $Rx32in";
27012}
27013def V6_vL32b_cur_ppu : HInst<
27014(outs HvxVR:$Vd32, IntRegs:$Rx32),
27015(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27016"$Vd32.cur = vmem($Rx32++$Mu2)",
27017tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27018let Inst{12-5} = 0b00000001;
27019let Inst{31-21} = 0b00101011000;
27020let hasNewValue = 1;
27021let opNewValue = 0;
27022let addrMode = PostInc;
27023let accessSize = HVXVectorAccess;
27024let isCVLoad = 1;
27025let CVINew = 1;
27026let mayLoad = 1;
27027let isRestrictNoSlot1Store = 1;
27028let BaseOpcode = "V6_vL32b_cur_ppu";
27029let isPredicable = 1;
27030let DecoderNamespace = "EXT_mmvec";
27031let Constraints = "$Rx32 = $Rx32in";
27032}
27033def V6_vL32b_cur_pred_ai : HInst<
27034(outs HvxVR:$Vd32),
27035(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27036"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27037tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27038let Inst{7-5} = 0b100;
27039let Inst{31-21} = 0b00101000100;
27040let isPredicated = 1;
27041let hasNewValue = 1;
27042let opNewValue = 0;
27043let addrMode = BaseImmOffset;
27044let accessSize = HVXVectorAccess;
27045let isCVLoad = 1;
27046let CVINew = 1;
27047let mayLoad = 1;
27048let isRestrictNoSlot1Store = 1;
27049let BaseOpcode = "V6_vL32b_cur_ai";
27050let DecoderNamespace = "EXT_mmvec";
27051}
27052def V6_vL32b_cur_pred_pi : HInst<
27053(outs HvxVR:$Vd32, IntRegs:$Rx32),
27054(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27055"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27056tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27057let Inst{7-5} = 0b100;
27058let Inst{13-13} = 0b0;
27059let Inst{31-21} = 0b00101001100;
27060let isPredicated = 1;
27061let hasNewValue = 1;
27062let opNewValue = 0;
27063let addrMode = PostInc;
27064let accessSize = HVXVectorAccess;
27065let isCVLoad = 1;
27066let CVINew = 1;
27067let mayLoad = 1;
27068let isRestrictNoSlot1Store = 1;
27069let BaseOpcode = "V6_vL32b_cur_pi";
27070let DecoderNamespace = "EXT_mmvec";
27071let Constraints = "$Rx32 = $Rx32in";
27072}
27073def V6_vL32b_cur_pred_ppu : HInst<
27074(outs HvxVR:$Vd32, IntRegs:$Rx32),
27075(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27076"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27077tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27078let Inst{10-5} = 0b000100;
27079let Inst{31-21} = 0b00101011100;
27080let isPredicated = 1;
27081let hasNewValue = 1;
27082let opNewValue = 0;
27083let addrMode = PostInc;
27084let accessSize = HVXVectorAccess;
27085let isCVLoad = 1;
27086let CVINew = 1;
27087let mayLoad = 1;
27088let isRestrictNoSlot1Store = 1;
27089let BaseOpcode = "V6_vL32b_cur_ppu";
27090let DecoderNamespace = "EXT_mmvec";
27091let Constraints = "$Rx32 = $Rx32in";
27092}
27093def V6_vL32b_npred_ai : HInst<
27094(outs HvxVR:$Vd32),
27095(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27096"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27097tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27098let Inst{7-5} = 0b011;
27099let Inst{31-21} = 0b00101000100;
27100let isPredicated = 1;
27101let isPredicatedFalse = 1;
27102let hasNewValue = 1;
27103let opNewValue = 0;
27104let addrMode = BaseImmOffset;
27105let accessSize = HVXVectorAccess;
27106let isCVLoad = 1;
27107let mayLoad = 1;
27108let isRestrictNoSlot1Store = 1;
27109let BaseOpcode = "V6_vL32b_ai";
27110let DecoderNamespace = "EXT_mmvec";
27111}
27112def V6_vL32b_npred_pi : HInst<
27113(outs HvxVR:$Vd32, IntRegs:$Rx32),
27114(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27115"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27116tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27117let Inst{7-5} = 0b011;
27118let Inst{13-13} = 0b0;
27119let Inst{31-21} = 0b00101001100;
27120let isPredicated = 1;
27121let isPredicatedFalse = 1;
27122let hasNewValue = 1;
27123let opNewValue = 0;
27124let addrMode = PostInc;
27125let accessSize = HVXVectorAccess;
27126let isCVLoad = 1;
27127let mayLoad = 1;
27128let isRestrictNoSlot1Store = 1;
27129let BaseOpcode = "V6_vL32b_pi";
27130let DecoderNamespace = "EXT_mmvec";
27131let Constraints = "$Rx32 = $Rx32in";
27132}
27133def V6_vL32b_npred_ppu : HInst<
27134(outs HvxVR:$Vd32, IntRegs:$Rx32),
27135(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27136"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27137tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27138let Inst{10-5} = 0b000011;
27139let Inst{31-21} = 0b00101011100;
27140let isPredicated = 1;
27141let isPredicatedFalse = 1;
27142let hasNewValue = 1;
27143let opNewValue = 0;
27144let addrMode = PostInc;
27145let accessSize = HVXVectorAccess;
27146let isCVLoad = 1;
27147let mayLoad = 1;
27148let isRestrictNoSlot1Store = 1;
27149let BaseOpcode = "V6_vL32b_ppu";
27150let DecoderNamespace = "EXT_mmvec";
27151let Constraints = "$Rx32 = $Rx32in";
27152}
27153def V6_vL32b_nt_ai : HInst<
27154(outs HvxVR:$Vd32),
27155(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27156"$Vd32 = vmem($Rt32+#$Ii):nt",
27157tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27158let Inst{7-5} = 0b000;
27159let Inst{12-11} = 0b00;
27160let Inst{31-21} = 0b00101000010;
27161let hasNewValue = 1;
27162let opNewValue = 0;
27163let addrMode = BaseImmOffset;
27164let accessSize = HVXVectorAccess;
27165let isCVLoad = 1;
27166let mayLoad = 1;
27167let isNonTemporal = 1;
27168let isRestrictNoSlot1Store = 1;
27169let BaseOpcode = "V6_vL32b_nt_ai";
27170let isCVLoadable = 1;
27171let isPredicable = 1;
27172let DecoderNamespace = "EXT_mmvec";
27173}
27174def V6_vL32b_nt_cur_ai : HInst<
27175(outs HvxVR:$Vd32),
27176(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27177"$Vd32.cur = vmem($Rt32+#$Ii):nt",
27178tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27179let Inst{7-5} = 0b001;
27180let Inst{12-11} = 0b00;
27181let Inst{31-21} = 0b00101000010;
27182let hasNewValue = 1;
27183let opNewValue = 0;
27184let addrMode = BaseImmOffset;
27185let accessSize = HVXVectorAccess;
27186let isCVLoad = 1;
27187let CVINew = 1;
27188let mayLoad = 1;
27189let isNonTemporal = 1;
27190let isRestrictNoSlot1Store = 1;
27191let BaseOpcode = "V6_vL32b_nt_cur_ai";
27192let isPredicable = 1;
27193let DecoderNamespace = "EXT_mmvec";
27194}
27195def V6_vL32b_nt_cur_npred_ai : HInst<
27196(outs HvxVR:$Vd32),
27197(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27198"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27199tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27200let Inst{7-5} = 0b101;
27201let Inst{31-21} = 0b00101000110;
27202let isPredicated = 1;
27203let isPredicatedFalse = 1;
27204let hasNewValue = 1;
27205let opNewValue = 0;
27206let addrMode = BaseImmOffset;
27207let accessSize = HVXVectorAccess;
27208let isCVLoad = 1;
27209let CVINew = 1;
27210let mayLoad = 1;
27211let isNonTemporal = 1;
27212let isRestrictNoSlot1Store = 1;
27213let BaseOpcode = "V6_vL32b_nt_cur_ai";
27214let DecoderNamespace = "EXT_mmvec";
27215}
27216def V6_vL32b_nt_cur_npred_pi : HInst<
27217(outs HvxVR:$Vd32, IntRegs:$Rx32),
27218(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27219"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27220tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27221let Inst{7-5} = 0b101;
27222let Inst{13-13} = 0b0;
27223let Inst{31-21} = 0b00101001110;
27224let isPredicated = 1;
27225let isPredicatedFalse = 1;
27226let hasNewValue = 1;
27227let opNewValue = 0;
27228let addrMode = PostInc;
27229let accessSize = HVXVectorAccess;
27230let isCVLoad = 1;
27231let CVINew = 1;
27232let mayLoad = 1;
27233let isNonTemporal = 1;
27234let isRestrictNoSlot1Store = 1;
27235let BaseOpcode = "V6_vL32b_nt_cur_pi";
27236let DecoderNamespace = "EXT_mmvec";
27237let Constraints = "$Rx32 = $Rx32in";
27238}
27239def V6_vL32b_nt_cur_npred_ppu : HInst<
27240(outs HvxVR:$Vd32, IntRegs:$Rx32),
27241(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27242"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27243tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27244let Inst{10-5} = 0b000101;
27245let Inst{31-21} = 0b00101011110;
27246let isPredicated = 1;
27247let isPredicatedFalse = 1;
27248let hasNewValue = 1;
27249let opNewValue = 0;
27250let addrMode = PostInc;
27251let accessSize = HVXVectorAccess;
27252let isCVLoad = 1;
27253let CVINew = 1;
27254let mayLoad = 1;
27255let isNonTemporal = 1;
27256let isRestrictNoSlot1Store = 1;
27257let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27258let DecoderNamespace = "EXT_mmvec";
27259let Constraints = "$Rx32 = $Rx32in";
27260}
27261def V6_vL32b_nt_cur_pi : HInst<
27262(outs HvxVR:$Vd32, IntRegs:$Rx32),
27263(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27264"$Vd32.cur = vmem($Rx32++#$Ii):nt",
27265tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27266let Inst{7-5} = 0b001;
27267let Inst{13-11} = 0b000;
27268let Inst{31-21} = 0b00101001010;
27269let hasNewValue = 1;
27270let opNewValue = 0;
27271let addrMode = PostInc;
27272let accessSize = HVXVectorAccess;
27273let isCVLoad = 1;
27274let CVINew = 1;
27275let mayLoad = 1;
27276let isNonTemporal = 1;
27277let isRestrictNoSlot1Store = 1;
27278let BaseOpcode = "V6_vL32b_nt_cur_pi";
27279let isPredicable = 1;
27280let DecoderNamespace = "EXT_mmvec";
27281let Constraints = "$Rx32 = $Rx32in";
27282}
27283def V6_vL32b_nt_cur_ppu : HInst<
27284(outs HvxVR:$Vd32, IntRegs:$Rx32),
27285(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27286"$Vd32.cur = vmem($Rx32++$Mu2):nt",
27287tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27288let Inst{12-5} = 0b00000001;
27289let Inst{31-21} = 0b00101011010;
27290let hasNewValue = 1;
27291let opNewValue = 0;
27292let addrMode = PostInc;
27293let accessSize = HVXVectorAccess;
27294let isCVLoad = 1;
27295let CVINew = 1;
27296let mayLoad = 1;
27297let isNonTemporal = 1;
27298let isRestrictNoSlot1Store = 1;
27299let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27300let isPredicable = 1;
27301let DecoderNamespace = "EXT_mmvec";
27302let Constraints = "$Rx32 = $Rx32in";
27303}
27304def V6_vL32b_nt_cur_pred_ai : HInst<
27305(outs HvxVR:$Vd32),
27306(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27307"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27308tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27309let Inst{7-5} = 0b100;
27310let Inst{31-21} = 0b00101000110;
27311let isPredicated = 1;
27312let hasNewValue = 1;
27313let opNewValue = 0;
27314let addrMode = BaseImmOffset;
27315let accessSize = HVXVectorAccess;
27316let isCVLoad = 1;
27317let CVINew = 1;
27318let mayLoad = 1;
27319let isNonTemporal = 1;
27320let isRestrictNoSlot1Store = 1;
27321let BaseOpcode = "V6_vL32b_nt_cur_ai";
27322let DecoderNamespace = "EXT_mmvec";
27323}
27324def V6_vL32b_nt_cur_pred_pi : HInst<
27325(outs HvxVR:$Vd32, IntRegs:$Rx32),
27326(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27327"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27328tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27329let Inst{7-5} = 0b100;
27330let Inst{13-13} = 0b0;
27331let Inst{31-21} = 0b00101001110;
27332let isPredicated = 1;
27333let hasNewValue = 1;
27334let opNewValue = 0;
27335let addrMode = PostInc;
27336let accessSize = HVXVectorAccess;
27337let isCVLoad = 1;
27338let CVINew = 1;
27339let mayLoad = 1;
27340let isNonTemporal = 1;
27341let isRestrictNoSlot1Store = 1;
27342let BaseOpcode = "V6_vL32b_nt_cur_pi";
27343let DecoderNamespace = "EXT_mmvec";
27344let Constraints = "$Rx32 = $Rx32in";
27345}
27346def V6_vL32b_nt_cur_pred_ppu : HInst<
27347(outs HvxVR:$Vd32, IntRegs:$Rx32),
27348(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27349"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27350tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27351let Inst{10-5} = 0b000100;
27352let Inst{31-21} = 0b00101011110;
27353let isPredicated = 1;
27354let hasNewValue = 1;
27355let opNewValue = 0;
27356let addrMode = PostInc;
27357let accessSize = HVXVectorAccess;
27358let isCVLoad = 1;
27359let CVINew = 1;
27360let mayLoad = 1;
27361let isNonTemporal = 1;
27362let isRestrictNoSlot1Store = 1;
27363let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27364let DecoderNamespace = "EXT_mmvec";
27365let Constraints = "$Rx32 = $Rx32in";
27366}
27367def V6_vL32b_nt_npred_ai : HInst<
27368(outs HvxVR:$Vd32),
27369(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27370"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27371tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27372let Inst{7-5} = 0b011;
27373let Inst{31-21} = 0b00101000110;
27374let isPredicated = 1;
27375let isPredicatedFalse = 1;
27376let hasNewValue = 1;
27377let opNewValue = 0;
27378let addrMode = BaseImmOffset;
27379let accessSize = HVXVectorAccess;
27380let isCVLoad = 1;
27381let mayLoad = 1;
27382let isNonTemporal = 1;
27383let isRestrictNoSlot1Store = 1;
27384let BaseOpcode = "V6_vL32b_nt_ai";
27385let DecoderNamespace = "EXT_mmvec";
27386}
27387def V6_vL32b_nt_npred_pi : HInst<
27388(outs HvxVR:$Vd32, IntRegs:$Rx32),
27389(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27390"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27391tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27392let Inst{7-5} = 0b011;
27393let Inst{13-13} = 0b0;
27394let Inst{31-21} = 0b00101001110;
27395let isPredicated = 1;
27396let isPredicatedFalse = 1;
27397let hasNewValue = 1;
27398let opNewValue = 0;
27399let addrMode = PostInc;
27400let accessSize = HVXVectorAccess;
27401let isCVLoad = 1;
27402let mayLoad = 1;
27403let isNonTemporal = 1;
27404let isRestrictNoSlot1Store = 1;
27405let BaseOpcode = "V6_vL32b_nt_pi";
27406let DecoderNamespace = "EXT_mmvec";
27407let Constraints = "$Rx32 = $Rx32in";
27408}
27409def V6_vL32b_nt_npred_ppu : HInst<
27410(outs HvxVR:$Vd32, IntRegs:$Rx32),
27411(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27412"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
27413tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27414let Inst{10-5} = 0b000011;
27415let Inst{31-21} = 0b00101011110;
27416let isPredicated = 1;
27417let isPredicatedFalse = 1;
27418let hasNewValue = 1;
27419let opNewValue = 0;
27420let addrMode = PostInc;
27421let accessSize = HVXVectorAccess;
27422let isCVLoad = 1;
27423let mayLoad = 1;
27424let isNonTemporal = 1;
27425let isRestrictNoSlot1Store = 1;
27426let BaseOpcode = "V6_vL32b_nt_ppu";
27427let DecoderNamespace = "EXT_mmvec";
27428let Constraints = "$Rx32 = $Rx32in";
27429}
27430def V6_vL32b_nt_pi : HInst<
27431(outs HvxVR:$Vd32, IntRegs:$Rx32),
27432(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27433"$Vd32 = vmem($Rx32++#$Ii):nt",
27434tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27435let Inst{7-5} = 0b000;
27436let Inst{13-11} = 0b000;
27437let Inst{31-21} = 0b00101001010;
27438let hasNewValue = 1;
27439let opNewValue = 0;
27440let addrMode = PostInc;
27441let accessSize = HVXVectorAccess;
27442let isCVLoad = 1;
27443let mayLoad = 1;
27444let isNonTemporal = 1;
27445let isRestrictNoSlot1Store = 1;
27446let BaseOpcode = "V6_vL32b_nt_pi";
27447let isCVLoadable = 1;
27448let isPredicable = 1;
27449let DecoderNamespace = "EXT_mmvec";
27450let Constraints = "$Rx32 = $Rx32in";
27451}
27452def V6_vL32b_nt_ppu : HInst<
27453(outs HvxVR:$Vd32, IntRegs:$Rx32),
27454(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27455"$Vd32 = vmem($Rx32++$Mu2):nt",
27456tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27457let Inst{12-5} = 0b00000000;
27458let Inst{31-21} = 0b00101011010;
27459let hasNewValue = 1;
27460let opNewValue = 0;
27461let addrMode = PostInc;
27462let accessSize = HVXVectorAccess;
27463let isCVLoad = 1;
27464let mayLoad = 1;
27465let isNonTemporal = 1;
27466let isRestrictNoSlot1Store = 1;
27467let BaseOpcode = "V6_vL32b_nt_ppu";
27468let isCVLoadable = 1;
27469let isPredicable = 1;
27470let DecoderNamespace = "EXT_mmvec";
27471let Constraints = "$Rx32 = $Rx32in";
27472}
27473def V6_vL32b_nt_pred_ai : HInst<
27474(outs HvxVR:$Vd32),
27475(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27476"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27477tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27478let Inst{7-5} = 0b010;
27479let Inst{31-21} = 0b00101000110;
27480let isPredicated = 1;
27481let hasNewValue = 1;
27482let opNewValue = 0;
27483let addrMode = BaseImmOffset;
27484let accessSize = HVXVectorAccess;
27485let isCVLoad = 1;
27486let mayLoad = 1;
27487let isNonTemporal = 1;
27488let isRestrictNoSlot1Store = 1;
27489let BaseOpcode = "V6_vL32b_nt_ai";
27490let DecoderNamespace = "EXT_mmvec";
27491}
27492def V6_vL32b_nt_pred_pi : HInst<
27493(outs HvxVR:$Vd32, IntRegs:$Rx32),
27494(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27495"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27496tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27497let Inst{7-5} = 0b010;
27498let Inst{13-13} = 0b0;
27499let Inst{31-21} = 0b00101001110;
27500let isPredicated = 1;
27501let hasNewValue = 1;
27502let opNewValue = 0;
27503let addrMode = PostInc;
27504let accessSize = HVXVectorAccess;
27505let isCVLoad = 1;
27506let mayLoad = 1;
27507let isNonTemporal = 1;
27508let isRestrictNoSlot1Store = 1;
27509let BaseOpcode = "V6_vL32b_nt_pi";
27510let DecoderNamespace = "EXT_mmvec";
27511let Constraints = "$Rx32 = $Rx32in";
27512}
27513def V6_vL32b_nt_pred_ppu : HInst<
27514(outs HvxVR:$Vd32, IntRegs:$Rx32),
27515(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27516"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
27517tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27518let Inst{10-5} = 0b000010;
27519let Inst{31-21} = 0b00101011110;
27520let isPredicated = 1;
27521let hasNewValue = 1;
27522let opNewValue = 0;
27523let addrMode = PostInc;
27524let accessSize = HVXVectorAccess;
27525let isCVLoad = 1;
27526let mayLoad = 1;
27527let isNonTemporal = 1;
27528let isRestrictNoSlot1Store = 1;
27529let BaseOpcode = "V6_vL32b_nt_ppu";
27530let DecoderNamespace = "EXT_mmvec";
27531let Constraints = "$Rx32 = $Rx32in";
27532}
27533def V6_vL32b_nt_tmp_ai : HInst<
27534(outs HvxVR:$Vd32),
27535(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27536"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
27537tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27538let Inst{7-5} = 0b010;
27539let Inst{12-11} = 0b00;
27540let Inst{31-21} = 0b00101000010;
27541let hasNewValue = 1;
27542let opNewValue = 0;
27543let addrMode = BaseImmOffset;
27544let accessSize = HVXVectorAccess;
27545let isCVLoad = 1;
27546let mayLoad = 1;
27547let isNonTemporal = 1;
27548let isRestrictNoSlot1Store = 1;
27549let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27550let isPredicable = 1;
27551let DecoderNamespace = "EXT_mmvec";
27552}
27553def V6_vL32b_nt_tmp_npred_ai : HInst<
27554(outs HvxVR:$Vd32),
27555(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27556"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
27557tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27558let Inst{7-5} = 0b111;
27559let Inst{31-21} = 0b00101000110;
27560let isPredicated = 1;
27561let isPredicatedFalse = 1;
27562let hasNewValue = 1;
27563let opNewValue = 0;
27564let addrMode = BaseImmOffset;
27565let accessSize = HVXVectorAccess;
27566let isCVLoad = 1;
27567let mayLoad = 1;
27568let isNonTemporal = 1;
27569let isRestrictNoSlot1Store = 1;
27570let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27571let DecoderNamespace = "EXT_mmvec";
27572}
27573def V6_vL32b_nt_tmp_npred_pi : HInst<
27574(outs HvxVR:$Vd32, IntRegs:$Rx32),
27575(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27576"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
27577tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27578let Inst{7-5} = 0b111;
27579let Inst{13-13} = 0b0;
27580let Inst{31-21} = 0b00101001110;
27581let isPredicated = 1;
27582let isPredicatedFalse = 1;
27583let hasNewValue = 1;
27584let opNewValue = 0;
27585let addrMode = PostInc;
27586let accessSize = HVXVectorAccess;
27587let isCVLoad = 1;
27588let mayLoad = 1;
27589let isNonTemporal = 1;
27590let isRestrictNoSlot1Store = 1;
27591let BaseOpcode = "V6_vL32b_nt_tmp_pi";
27592let DecoderNamespace = "EXT_mmvec";
27593let Constraints = "$Rx32 = $Rx32in";
27594}
27595def V6_vL32b_nt_tmp_npred_ppu : HInst<
27596(outs HvxVR:$Vd32, IntRegs:$Rx32),
27597(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27598"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
27599tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27600let Inst{10-5} = 0b000111;
27601let Inst{31-21} = 0b00101011110;
27602let isPredicated = 1;
27603let isPredicatedFalse = 1;
27604let hasNewValue = 1;
27605let opNewValue = 0;
27606let addrMode = PostInc;
27607let accessSize = HVXVectorAccess;
27608let isCVLoad = 1;
27609let mayLoad = 1;
27610let isNonTemporal = 1;
27611let isRestrictNoSlot1Store = 1;
27612let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
27613let DecoderNamespace = "EXT_mmvec";
27614let Constraints = "$Rx32 = $Rx32in";
27615}
27616def V6_vL32b_nt_tmp_pi : HInst<
27617(outs HvxVR:$Vd32, IntRegs:$Rx32),
27618(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27619"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
27620tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27621let Inst{7-5} = 0b010;
27622let Inst{13-11} = 0b000;
27623let Inst{31-21} = 0b00101001010;
27624let hasNewValue = 1;
27625let opNewValue = 0;
27626let addrMode = PostInc;
27627let accessSize = HVXVectorAccess;
27628let isCVLoad = 1;
27629let mayLoad = 1;
27630let isNonTemporal = 1;
27631let isRestrictNoSlot1Store = 1;
27632let BaseOpcode = "V6_vL32b_nt_tmp_pi";
27633let isPredicable = 1;
27634let DecoderNamespace = "EXT_mmvec";
27635let Constraints = "$Rx32 = $Rx32in";
27636}
27637def V6_vL32b_nt_tmp_ppu : HInst<
27638(outs HvxVR:$Vd32, IntRegs:$Rx32),
27639(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27640"$Vd32.tmp = vmem($Rx32++$Mu2):nt",
27641tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27642let Inst{12-5} = 0b00000010;
27643let Inst{31-21} = 0b00101011010;
27644let hasNewValue = 1;
27645let opNewValue = 0;
27646let addrMode = PostInc;
27647let accessSize = HVXVectorAccess;
27648let isCVLoad = 1;
27649let mayLoad = 1;
27650let isNonTemporal = 1;
27651let isRestrictNoSlot1Store = 1;
27652let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
27653let isPredicable = 1;
27654let DecoderNamespace = "EXT_mmvec";
27655let Constraints = "$Rx32 = $Rx32in";
27656}
27657def V6_vL32b_nt_tmp_pred_ai : HInst<
27658(outs HvxVR:$Vd32),
27659(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27660"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
27661tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27662let Inst{7-5} = 0b110;
27663let Inst{31-21} = 0b00101000110;
27664let isPredicated = 1;
27665let hasNewValue = 1;
27666let opNewValue = 0;
27667let addrMode = BaseImmOffset;
27668let accessSize = HVXVectorAccess;
27669let isCVLoad = 1;
27670let mayLoad = 1;
27671let isNonTemporal = 1;
27672let isRestrictNoSlot1Store = 1;
27673let BaseOpcode = "V6_vL32b_nt_tmp_ai";
27674let DecoderNamespace = "EXT_mmvec";
27675}
27676def V6_vL32b_nt_tmp_pred_pi : HInst<
27677(outs HvxVR:$Vd32, IntRegs:$Rx32),
27678(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27679"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
27680tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27681let Inst{7-5} = 0b110;
27682let Inst{13-13} = 0b0;
27683let Inst{31-21} = 0b00101001110;
27684let isPredicated = 1;
27685let hasNewValue = 1;
27686let opNewValue = 0;
27687let addrMode = PostInc;
27688let accessSize = HVXVectorAccess;
27689let isCVLoad = 1;
27690let mayLoad = 1;
27691let isNonTemporal = 1;
27692let isRestrictNoSlot1Store = 1;
27693let BaseOpcode = "V6_vL32b_nt_tmp_pi";
27694let DecoderNamespace = "EXT_mmvec";
27695let Constraints = "$Rx32 = $Rx32in";
27696}
27697def V6_vL32b_nt_tmp_pred_ppu : HInst<
27698(outs HvxVR:$Vd32, IntRegs:$Rx32),
27699(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27700"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
27701tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27702let Inst{10-5} = 0b000110;
27703let Inst{31-21} = 0b00101011110;
27704let isPredicated = 1;
27705let hasNewValue = 1;
27706let opNewValue = 0;
27707let addrMode = PostInc;
27708let accessSize = HVXVectorAccess;
27709let isCVLoad = 1;
27710let mayLoad = 1;
27711let isNonTemporal = 1;
27712let isRestrictNoSlot1Store = 1;
27713let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
27714let DecoderNamespace = "EXT_mmvec";
27715let Constraints = "$Rx32 = $Rx32in";
27716}
27717def V6_vL32b_pi : HInst<
27718(outs HvxVR:$Vd32, IntRegs:$Rx32),
27719(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27720"$Vd32 = vmem($Rx32++#$Ii)",
27721tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27722let Inst{7-5} = 0b000;
27723let Inst{13-11} = 0b000;
27724let Inst{31-21} = 0b00101001000;
27725let hasNewValue = 1;
27726let opNewValue = 0;
27727let addrMode = PostInc;
27728let accessSize = HVXVectorAccess;
27729let isCVLoad = 1;
27730let mayLoad = 1;
27731let isRestrictNoSlot1Store = 1;
27732let BaseOpcode = "V6_vL32b_pi";
27733let isCVLoadable = 1;
27734let isPredicable = 1;
27735let DecoderNamespace = "EXT_mmvec";
27736let Constraints = "$Rx32 = $Rx32in";
27737}
27738def V6_vL32b_ppu : HInst<
27739(outs HvxVR:$Vd32, IntRegs:$Rx32),
27740(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27741"$Vd32 = vmem($Rx32++$Mu2)",
27742tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27743let Inst{12-5} = 0b00000000;
27744let Inst{31-21} = 0b00101011000;
27745let hasNewValue = 1;
27746let opNewValue = 0;
27747let addrMode = PostInc;
27748let accessSize = HVXVectorAccess;
27749let isCVLoad = 1;
27750let mayLoad = 1;
27751let isRestrictNoSlot1Store = 1;
27752let BaseOpcode = "V6_vL32b_ppu";
27753let isCVLoadable = 1;
27754let isPredicable = 1;
27755let DecoderNamespace = "EXT_mmvec";
27756let Constraints = "$Rx32 = $Rx32in";
27757}
27758def V6_vL32b_pred_ai : HInst<
27759(outs HvxVR:$Vd32),
27760(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27761"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27762tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27763let Inst{7-5} = 0b010;
27764let Inst{31-21} = 0b00101000100;
27765let isPredicated = 1;
27766let hasNewValue = 1;
27767let opNewValue = 0;
27768let addrMode = BaseImmOffset;
27769let accessSize = HVXVectorAccess;
27770let isCVLoad = 1;
27771let mayLoad = 1;
27772let isRestrictNoSlot1Store = 1;
27773let BaseOpcode = "V6_vL32b_ai";
27774let DecoderNamespace = "EXT_mmvec";
27775}
27776def V6_vL32b_pred_pi : HInst<
27777(outs HvxVR:$Vd32, IntRegs:$Rx32),
27778(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27779"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27780tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27781let Inst{7-5} = 0b010;
27782let Inst{13-13} = 0b0;
27783let Inst{31-21} = 0b00101001100;
27784let isPredicated = 1;
27785let hasNewValue = 1;
27786let opNewValue = 0;
27787let addrMode = PostInc;
27788let accessSize = HVXVectorAccess;
27789let isCVLoad = 1;
27790let mayLoad = 1;
27791let isRestrictNoSlot1Store = 1;
27792let BaseOpcode = "V6_vL32b_pi";
27793let DecoderNamespace = "EXT_mmvec";
27794let Constraints = "$Rx32 = $Rx32in";
27795}
27796def V6_vL32b_pred_ppu : HInst<
27797(outs HvxVR:$Vd32, IntRegs:$Rx32),
27798(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27799"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27800tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27801let Inst{10-5} = 0b000010;
27802let Inst{31-21} = 0b00101011100;
27803let isPredicated = 1;
27804let hasNewValue = 1;
27805let opNewValue = 0;
27806let addrMode = PostInc;
27807let accessSize = HVXVectorAccess;
27808let isCVLoad = 1;
27809let mayLoad = 1;
27810let isRestrictNoSlot1Store = 1;
27811let BaseOpcode = "V6_vL32b_ppu";
27812let DecoderNamespace = "EXT_mmvec";
27813let Constraints = "$Rx32 = $Rx32in";
27814}
27815def V6_vL32b_tmp_ai : HInst<
27816(outs HvxVR:$Vd32),
27817(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27818"$Vd32.tmp = vmem($Rt32+#$Ii)",
27819tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27820let Inst{7-5} = 0b010;
27821let Inst{12-11} = 0b00;
27822let Inst{31-21} = 0b00101000000;
27823let hasNewValue = 1;
27824let opNewValue = 0;
27825let addrMode = BaseImmOffset;
27826let accessSize = HVXVectorAccess;
27827let isCVLoad = 1;
27828let mayLoad = 1;
27829let isRestrictNoSlot1Store = 1;
27830let BaseOpcode = "V6_vL32b_tmp_ai";
27831let isPredicable = 1;
27832let DecoderNamespace = "EXT_mmvec";
27833}
27834def V6_vL32b_tmp_npred_ai : HInst<
27835(outs HvxVR:$Vd32),
27836(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27837"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
27838tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27839let Inst{7-5} = 0b111;
27840let Inst{31-21} = 0b00101000100;
27841let isPredicated = 1;
27842let isPredicatedFalse = 1;
27843let hasNewValue = 1;
27844let opNewValue = 0;
27845let addrMode = BaseImmOffset;
27846let accessSize = HVXVectorAccess;
27847let isCVLoad = 1;
27848let mayLoad = 1;
27849let isRestrictNoSlot1Store = 1;
27850let BaseOpcode = "V6_vL32b_tmp_ai";
27851let DecoderNamespace = "EXT_mmvec";
27852}
27853def V6_vL32b_tmp_npred_pi : HInst<
27854(outs HvxVR:$Vd32, IntRegs:$Rx32),
27855(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27856"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
27857tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27858let Inst{7-5} = 0b111;
27859let Inst{13-13} = 0b0;
27860let Inst{31-21} = 0b00101001100;
27861let isPredicated = 1;
27862let isPredicatedFalse = 1;
27863let hasNewValue = 1;
27864let opNewValue = 0;
27865let addrMode = PostInc;
27866let accessSize = HVXVectorAccess;
27867let isCVLoad = 1;
27868let mayLoad = 1;
27869let isRestrictNoSlot1Store = 1;
27870let BaseOpcode = "V6_vL32b_tmp_pi";
27871let DecoderNamespace = "EXT_mmvec";
27872let Constraints = "$Rx32 = $Rx32in";
27873}
27874def V6_vL32b_tmp_npred_ppu : HInst<
27875(outs HvxVR:$Vd32, IntRegs:$Rx32),
27876(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27877"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
27878tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27879let Inst{10-5} = 0b000111;
27880let Inst{31-21} = 0b00101011100;
27881let isPredicated = 1;
27882let isPredicatedFalse = 1;
27883let hasNewValue = 1;
27884let opNewValue = 0;
27885let addrMode = PostInc;
27886let accessSize = HVXVectorAccess;
27887let isCVLoad = 1;
27888let mayLoad = 1;
27889let isRestrictNoSlot1Store = 1;
27890let BaseOpcode = "V6_vL32b_tmp_ppu";
27891let DecoderNamespace = "EXT_mmvec";
27892let Constraints = "$Rx32 = $Rx32in";
27893}
27894def V6_vL32b_tmp_pi : HInst<
27895(outs HvxVR:$Vd32, IntRegs:$Rx32),
27896(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27897"$Vd32.tmp = vmem($Rx32++#$Ii)",
27898tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27899let Inst{7-5} = 0b010;
27900let Inst{13-11} = 0b000;
27901let Inst{31-21} = 0b00101001000;
27902let hasNewValue = 1;
27903let opNewValue = 0;
27904let addrMode = PostInc;
27905let accessSize = HVXVectorAccess;
27906let isCVLoad = 1;
27907let mayLoad = 1;
27908let isRestrictNoSlot1Store = 1;
27909let BaseOpcode = "V6_vL32b_tmp_pi";
27910let isPredicable = 1;
27911let DecoderNamespace = "EXT_mmvec";
27912let Constraints = "$Rx32 = $Rx32in";
27913}
27914def V6_vL32b_tmp_ppu : HInst<
27915(outs HvxVR:$Vd32, IntRegs:$Rx32),
27916(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27917"$Vd32.tmp = vmem($Rx32++$Mu2)",
27918tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27919let Inst{12-5} = 0b00000010;
27920let Inst{31-21} = 0b00101011000;
27921let hasNewValue = 1;
27922let opNewValue = 0;
27923let addrMode = PostInc;
27924let accessSize = HVXVectorAccess;
27925let isCVLoad = 1;
27926let mayLoad = 1;
27927let isRestrictNoSlot1Store = 1;
27928let BaseOpcode = "V6_vL32b_tmp_ppu";
27929let isPredicable = 1;
27930let DecoderNamespace = "EXT_mmvec";
27931let Constraints = "$Rx32 = $Rx32in";
27932}
27933def V6_vL32b_tmp_pred_ai : HInst<
27934(outs HvxVR:$Vd32),
27935(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27936"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
27937tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27938let Inst{7-5} = 0b110;
27939let Inst{31-21} = 0b00101000100;
27940let isPredicated = 1;
27941let hasNewValue = 1;
27942let opNewValue = 0;
27943let addrMode = BaseImmOffset;
27944let accessSize = HVXVectorAccess;
27945let isCVLoad = 1;
27946let mayLoad = 1;
27947let isRestrictNoSlot1Store = 1;
27948let BaseOpcode = "V6_vL32b_tmp_ai";
27949let DecoderNamespace = "EXT_mmvec";
27950}
27951def V6_vL32b_tmp_pred_pi : HInst<
27952(outs HvxVR:$Vd32, IntRegs:$Rx32),
27953(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27954"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
27955tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27956let Inst{7-5} = 0b110;
27957let Inst{13-13} = 0b0;
27958let Inst{31-21} = 0b00101001100;
27959let isPredicated = 1;
27960let hasNewValue = 1;
27961let opNewValue = 0;
27962let addrMode = PostInc;
27963let accessSize = HVXVectorAccess;
27964let isCVLoad = 1;
27965let mayLoad = 1;
27966let isRestrictNoSlot1Store = 1;
27967let BaseOpcode = "V6_vL32b_tmp_pi";
27968let DecoderNamespace = "EXT_mmvec";
27969let Constraints = "$Rx32 = $Rx32in";
27970}
27971def V6_vL32b_tmp_pred_ppu : HInst<
27972(outs HvxVR:$Vd32, IntRegs:$Rx32),
27973(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27974"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
27975tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27976let Inst{10-5} = 0b000110;
27977let Inst{31-21} = 0b00101011100;
27978let isPredicated = 1;
27979let hasNewValue = 1;
27980let opNewValue = 0;
27981let addrMode = PostInc;
27982let accessSize = HVXVectorAccess;
27983let isCVLoad = 1;
27984let mayLoad = 1;
27985let isRestrictNoSlot1Store = 1;
27986let BaseOpcode = "V6_vL32b_tmp_ppu";
27987let DecoderNamespace = "EXT_mmvec";
27988let Constraints = "$Rx32 = $Rx32in";
27989}
27990def V6_vS32Ub_ai : HInst<
27991(outs),
27992(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
27993"vmemu($Rt32+#$Ii) = $Vs32",
27994tc_f21e8abb, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
27995let Inst{7-5} = 0b111;
27996let Inst{12-11} = 0b00;
27997let Inst{31-21} = 0b00101000001;
27998let addrMode = BaseImmOffset;
27999let accessSize = HVXVectorAccess;
28000let mayStore = 1;
28001let BaseOpcode = "V6_vS32Ub_ai";
28002let isPredicable = 1;
28003let DecoderNamespace = "EXT_mmvec";
28004}
28005def V6_vS32Ub_npred_ai : HInst<
28006(outs),
28007(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28008"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28009tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28010let Inst{7-5} = 0b111;
28011let Inst{31-21} = 0b00101000101;
28012let isPredicated = 1;
28013let isPredicatedFalse = 1;
28014let addrMode = BaseImmOffset;
28015let accessSize = HVXVectorAccess;
28016let mayStore = 1;
28017let BaseOpcode = "V6_vS32Ub_ai";
28018let DecoderNamespace = "EXT_mmvec";
28019}
28020def V6_vS32Ub_npred_pi : HInst<
28021(outs IntRegs:$Rx32),
28022(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28023"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28024tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28025let Inst{7-5} = 0b111;
28026let Inst{13-13} = 0b0;
28027let Inst{31-21} = 0b00101001101;
28028let isPredicated = 1;
28029let isPredicatedFalse = 1;
28030let addrMode = PostInc;
28031let accessSize = HVXVectorAccess;
28032let mayStore = 1;
28033let BaseOpcode = "V6_vS32Ub_pi";
28034let DecoderNamespace = "EXT_mmvec";
28035let Constraints = "$Rx32 = $Rx32in";
28036}
28037def V6_vS32Ub_npred_ppu : HInst<
28038(outs IntRegs:$Rx32),
28039(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28040"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28041tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28042let Inst{10-5} = 0b000111;
28043let Inst{31-21} = 0b00101011101;
28044let isPredicated = 1;
28045let isPredicatedFalse = 1;
28046let addrMode = PostInc;
28047let accessSize = HVXVectorAccess;
28048let mayStore = 1;
28049let BaseOpcode = "V6_vS32Ub_ppu";
28050let DecoderNamespace = "EXT_mmvec";
28051let Constraints = "$Rx32 = $Rx32in";
28052}
28053def V6_vS32Ub_pi : HInst<
28054(outs IntRegs:$Rx32),
28055(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28056"vmemu($Rx32++#$Ii) = $Vs32",
28057tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
28058let Inst{7-5} = 0b111;
28059let Inst{13-11} = 0b000;
28060let Inst{31-21} = 0b00101001001;
28061let addrMode = PostInc;
28062let accessSize = HVXVectorAccess;
28063let mayStore = 1;
28064let BaseOpcode = "V6_vS32Ub_pi";
28065let isPredicable = 1;
28066let DecoderNamespace = "EXT_mmvec";
28067let Constraints = "$Rx32 = $Rx32in";
28068}
28069def V6_vS32Ub_ppu : HInst<
28070(outs IntRegs:$Rx32),
28071(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28072"vmemu($Rx32++$Mu2) = $Vs32",
28073tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28074let Inst{12-5} = 0b00000111;
28075let Inst{31-21} = 0b00101011001;
28076let addrMode = PostInc;
28077let accessSize = HVXVectorAccess;
28078let mayStore = 1;
28079let BaseOpcode = "V6_vS32Ub_ppu";
28080let isPredicable = 1;
28081let DecoderNamespace = "EXT_mmvec";
28082let Constraints = "$Rx32 = $Rx32in";
28083}
28084def V6_vS32Ub_pred_ai : HInst<
28085(outs),
28086(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28087"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28088tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28089let Inst{7-5} = 0b110;
28090let Inst{31-21} = 0b00101000101;
28091let isPredicated = 1;
28092let addrMode = BaseImmOffset;
28093let accessSize = HVXVectorAccess;
28094let mayStore = 1;
28095let BaseOpcode = "V6_vS32Ub_ai";
28096let DecoderNamespace = "EXT_mmvec";
28097}
28098def V6_vS32Ub_pred_pi : HInst<
28099(outs IntRegs:$Rx32),
28100(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28101"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28102tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28103let Inst{7-5} = 0b110;
28104let Inst{13-13} = 0b0;
28105let Inst{31-21} = 0b00101001101;
28106let isPredicated = 1;
28107let addrMode = PostInc;
28108let accessSize = HVXVectorAccess;
28109let mayStore = 1;
28110let BaseOpcode = "V6_vS32Ub_pi";
28111let DecoderNamespace = "EXT_mmvec";
28112let Constraints = "$Rx32 = $Rx32in";
28113}
28114def V6_vS32Ub_pred_ppu : HInst<
28115(outs IntRegs:$Rx32),
28116(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28117"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28118tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28119let Inst{10-5} = 0b000110;
28120let Inst{31-21} = 0b00101011101;
28121let isPredicated = 1;
28122let addrMode = PostInc;
28123let accessSize = HVXVectorAccess;
28124let mayStore = 1;
28125let BaseOpcode = "V6_vS32Ub_ppu";
28126let DecoderNamespace = "EXT_mmvec";
28127let Constraints = "$Rx32 = $Rx32in";
28128}
28129def V6_vS32b_ai : HInst<
28130(outs),
28131(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28132"vmem($Rt32+#$Ii) = $Vs32",
28133tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28134let Inst{7-5} = 0b000;
28135let Inst{12-11} = 0b00;
28136let Inst{31-21} = 0b00101000001;
28137let addrMode = BaseImmOffset;
28138let accessSize = HVXVectorAccess;
28139let mayStore = 1;
28140let BaseOpcode = "V6_vS32b_ai";
28141let isNVStorable = 1;
28142let isPredicable = 1;
28143let DecoderNamespace = "EXT_mmvec";
28144}
28145def V6_vS32b_new_ai : HInst<
28146(outs),
28147(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28148"vmem($Rt32+#$Ii) = $Os8.new",
28149tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
28150let Inst{7-3} = 0b00100;
28151let Inst{12-11} = 0b00;
28152let Inst{31-21} = 0b00101000001;
28153let addrMode = BaseImmOffset;
28154let accessSize = HVXVectorAccess;
28155let isNVStore = 1;
28156let CVINew = 1;
28157let isNewValue = 1;
28158let mayStore = 1;
28159let BaseOpcode = "V6_vS32b_ai";
28160let isPredicable = 1;
28161let DecoderNamespace = "EXT_mmvec";
28162let opNewValue = 2;
28163}
28164def V6_vS32b_new_npred_ai : HInst<
28165(outs),
28166(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28167"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28168tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28169let Inst{7-3} = 0b01101;
28170let Inst{31-21} = 0b00101000101;
28171let isPredicated = 1;
28172let isPredicatedFalse = 1;
28173let addrMode = BaseImmOffset;
28174let accessSize = HVXVectorAccess;
28175let isNVStore = 1;
28176let CVINew = 1;
28177let isNewValue = 1;
28178let mayStore = 1;
28179let BaseOpcode = "V6_vS32b_ai";
28180let DecoderNamespace = "EXT_mmvec";
28181let opNewValue = 3;
28182}
28183def V6_vS32b_new_npred_pi : HInst<
28184(outs IntRegs:$Rx32),
28185(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28186"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28187tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28188let Inst{7-3} = 0b01101;
28189let Inst{13-13} = 0b0;
28190let Inst{31-21} = 0b00101001101;
28191let isPredicated = 1;
28192let isPredicatedFalse = 1;
28193let addrMode = PostInc;
28194let accessSize = HVXVectorAccess;
28195let isNVStore = 1;
28196let CVINew = 1;
28197let isNewValue = 1;
28198let mayStore = 1;
28199let BaseOpcode = "V6_vS32b_pi";
28200let DecoderNamespace = "EXT_mmvec";
28201let opNewValue = 4;
28202let Constraints = "$Rx32 = $Rx32in";
28203}
28204def V6_vS32b_new_npred_ppu : HInst<
28205(outs IntRegs:$Rx32),
28206(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28207"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28208tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28209let Inst{10-3} = 0b00001101;
28210let Inst{31-21} = 0b00101011101;
28211let isPredicated = 1;
28212let isPredicatedFalse = 1;
28213let addrMode = PostInc;
28214let accessSize = HVXVectorAccess;
28215let isNVStore = 1;
28216let CVINew = 1;
28217let isNewValue = 1;
28218let mayStore = 1;
28219let BaseOpcode = "V6_vS32b_ppu";
28220let DecoderNamespace = "EXT_mmvec";
28221let opNewValue = 4;
28222let Constraints = "$Rx32 = $Rx32in";
28223}
28224def V6_vS32b_new_pi : HInst<
28225(outs IntRegs:$Rx32),
28226(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28227"vmem($Rx32++#$Ii) = $Os8.new",
28228tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
28229let Inst{7-3} = 0b00100;
28230let Inst{13-11} = 0b000;
28231let Inst{31-21} = 0b00101001001;
28232let addrMode = PostInc;
28233let accessSize = HVXVectorAccess;
28234let isNVStore = 1;
28235let CVINew = 1;
28236let isNewValue = 1;
28237let mayStore = 1;
28238let BaseOpcode = "V6_vS32b_pi";
28239let isPredicable = 1;
28240let DecoderNamespace = "EXT_mmvec";
28241let opNewValue = 3;
28242let Constraints = "$Rx32 = $Rx32in";
28243}
28244def V6_vS32b_new_ppu : HInst<
28245(outs IntRegs:$Rx32),
28246(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28247"vmem($Rx32++$Mu2) = $Os8.new",
28248tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
28249let Inst{12-3} = 0b0000000100;
28250let Inst{31-21} = 0b00101011001;
28251let addrMode = PostInc;
28252let accessSize = HVXVectorAccess;
28253let isNVStore = 1;
28254let CVINew = 1;
28255let isNewValue = 1;
28256let mayStore = 1;
28257let BaseOpcode = "V6_vS32b_ppu";
28258let isPredicable = 1;
28259let DecoderNamespace = "EXT_mmvec";
28260let opNewValue = 3;
28261let Constraints = "$Rx32 = $Rx32in";
28262}
28263def V6_vS32b_new_pred_ai : HInst<
28264(outs),
28265(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28266"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28267tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28268let Inst{7-3} = 0b01000;
28269let Inst{31-21} = 0b00101000101;
28270let isPredicated = 1;
28271let addrMode = BaseImmOffset;
28272let accessSize = HVXVectorAccess;
28273let isNVStore = 1;
28274let CVINew = 1;
28275let isNewValue = 1;
28276let mayStore = 1;
28277let BaseOpcode = "V6_vS32b_ai";
28278let DecoderNamespace = "EXT_mmvec";
28279let opNewValue = 3;
28280}
28281def V6_vS32b_new_pred_pi : HInst<
28282(outs IntRegs:$Rx32),
28283(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28284"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28285tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28286let Inst{7-3} = 0b01000;
28287let Inst{13-13} = 0b0;
28288let Inst{31-21} = 0b00101001101;
28289let isPredicated = 1;
28290let addrMode = PostInc;
28291let accessSize = HVXVectorAccess;
28292let isNVStore = 1;
28293let CVINew = 1;
28294let isNewValue = 1;
28295let mayStore = 1;
28296let BaseOpcode = "V6_vS32b_pi";
28297let DecoderNamespace = "EXT_mmvec";
28298let opNewValue = 4;
28299let Constraints = "$Rx32 = $Rx32in";
28300}
28301def V6_vS32b_new_pred_ppu : HInst<
28302(outs IntRegs:$Rx32),
28303(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28304"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28305tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28306let Inst{10-3} = 0b00001000;
28307let Inst{31-21} = 0b00101011101;
28308let isPredicated = 1;
28309let addrMode = PostInc;
28310let accessSize = HVXVectorAccess;
28311let isNVStore = 1;
28312let CVINew = 1;
28313let isNewValue = 1;
28314let mayStore = 1;
28315let BaseOpcode = "V6_vS32b_ppu";
28316let DecoderNamespace = "EXT_mmvec";
28317let opNewValue = 4;
28318let Constraints = "$Rx32 = $Rx32in";
28319}
28320def V6_vS32b_npred_ai : HInst<
28321(outs),
28322(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28323"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
28324tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28325let Inst{7-5} = 0b001;
28326let Inst{31-21} = 0b00101000101;
28327let isPredicated = 1;
28328let isPredicatedFalse = 1;
28329let addrMode = BaseImmOffset;
28330let accessSize = HVXVectorAccess;
28331let mayStore = 1;
28332let BaseOpcode = "V6_vS32b_ai";
28333let isNVStorable = 1;
28334let DecoderNamespace = "EXT_mmvec";
28335}
28336def V6_vS32b_npred_pi : HInst<
28337(outs IntRegs:$Rx32),
28338(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28339"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
28340tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28341let Inst{7-5} = 0b001;
28342let Inst{13-13} = 0b0;
28343let Inst{31-21} = 0b00101001101;
28344let isPredicated = 1;
28345let isPredicatedFalse = 1;
28346let addrMode = PostInc;
28347let accessSize = HVXVectorAccess;
28348let mayStore = 1;
28349let BaseOpcode = "V6_vS32b_pi";
28350let isNVStorable = 1;
28351let DecoderNamespace = "EXT_mmvec";
28352let Constraints = "$Rx32 = $Rx32in";
28353}
28354def V6_vS32b_npred_ppu : HInst<
28355(outs IntRegs:$Rx32),
28356(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28357"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
28358tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28359let Inst{10-5} = 0b000001;
28360let Inst{31-21} = 0b00101011101;
28361let isPredicated = 1;
28362let isPredicatedFalse = 1;
28363let addrMode = PostInc;
28364let accessSize = HVXVectorAccess;
28365let mayStore = 1;
28366let BaseOpcode = "V6_vS32b_ppu";
28367let isNVStorable = 1;
28368let DecoderNamespace = "EXT_mmvec";
28369let Constraints = "$Rx32 = $Rx32in";
28370}
28371def V6_vS32b_nqpred_ai : HInst<
28372(outs),
28373(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28374"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
28375tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28376let Inst{7-5} = 0b001;
28377let Inst{31-21} = 0b00101000100;
28378let addrMode = BaseImmOffset;
28379let accessSize = HVXVectorAccess;
28380let mayStore = 1;
28381let DecoderNamespace = "EXT_mmvec";
28382}
28383def V6_vS32b_nqpred_pi : HInst<
28384(outs IntRegs:$Rx32),
28385(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28386"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
28387tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28388let Inst{7-5} = 0b001;
28389let Inst{13-13} = 0b0;
28390let Inst{31-21} = 0b00101001100;
28391let addrMode = PostInc;
28392let accessSize = HVXVectorAccess;
28393let mayStore = 1;
28394let DecoderNamespace = "EXT_mmvec";
28395let Constraints = "$Rx32 = $Rx32in";
28396}
28397def V6_vS32b_nqpred_ppu : HInst<
28398(outs IntRegs:$Rx32),
28399(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28400"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
28401tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28402let Inst{10-5} = 0b000001;
28403let Inst{31-21} = 0b00101011100;
28404let addrMode = PostInc;
28405let accessSize = HVXVectorAccess;
28406let mayStore = 1;
28407let DecoderNamespace = "EXT_mmvec";
28408let Constraints = "$Rx32 = $Rx32in";
28409}
28410def V6_vS32b_nt_ai : HInst<
28411(outs),
28412(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28413"vmem($Rt32+#$Ii):nt = $Vs32",
28414tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28415let Inst{7-5} = 0b000;
28416let Inst{12-11} = 0b00;
28417let Inst{31-21} = 0b00101000011;
28418let addrMode = BaseImmOffset;
28419let accessSize = HVXVectorAccess;
28420let isNonTemporal = 1;
28421let mayStore = 1;
28422let BaseOpcode = "V6_vS32b_ai";
28423let isNVStorable = 1;
28424let isPredicable = 1;
28425let DecoderNamespace = "EXT_mmvec";
28426}
28427def V6_vS32b_nt_new_ai : HInst<
28428(outs),
28429(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28430"vmem($Rt32+#$Ii):nt = $Os8.new",
28431tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
28432let Inst{7-3} = 0b00100;
28433let Inst{12-11} = 0b00;
28434let Inst{31-21} = 0b00101000011;
28435let addrMode = BaseImmOffset;
28436let accessSize = HVXVectorAccess;
28437let isNVStore = 1;
28438let CVINew = 1;
28439let isNewValue = 1;
28440let isNonTemporal = 1;
28441let mayStore = 1;
28442let BaseOpcode = "V6_vS32b_ai";
28443let isPredicable = 1;
28444let DecoderNamespace = "EXT_mmvec";
28445let opNewValue = 2;
28446}
28447def V6_vS32b_nt_new_npred_ai : HInst<
28448(outs),
28449(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28450"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
28451tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28452let Inst{7-3} = 0b01111;
28453let Inst{31-21} = 0b00101000111;
28454let isPredicated = 1;
28455let isPredicatedFalse = 1;
28456let addrMode = BaseImmOffset;
28457let accessSize = HVXVectorAccess;
28458let isNVStore = 1;
28459let CVINew = 1;
28460let isNewValue = 1;
28461let isNonTemporal = 1;
28462let mayStore = 1;
28463let BaseOpcode = "V6_vS32b_ai";
28464let DecoderNamespace = "EXT_mmvec";
28465let opNewValue = 3;
28466}
28467def V6_vS32b_nt_new_npred_pi : HInst<
28468(outs IntRegs:$Rx32),
28469(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28470"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
28471tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28472let Inst{7-3} = 0b01111;
28473let Inst{13-13} = 0b0;
28474let Inst{31-21} = 0b00101001111;
28475let isPredicated = 1;
28476let isPredicatedFalse = 1;
28477let addrMode = PostInc;
28478let accessSize = HVXVectorAccess;
28479let isNVStore = 1;
28480let CVINew = 1;
28481let isNewValue = 1;
28482let isNonTemporal = 1;
28483let mayStore = 1;
28484let BaseOpcode = "V6_vS32b_pi";
28485let DecoderNamespace = "EXT_mmvec";
28486let opNewValue = 4;
28487let Constraints = "$Rx32 = $Rx32in";
28488}
28489def V6_vS32b_nt_new_npred_ppu : HInst<
28490(outs IntRegs:$Rx32),
28491(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28492"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
28493tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28494let Inst{10-3} = 0b00001111;
28495let Inst{31-21} = 0b00101011111;
28496let isPredicated = 1;
28497let isPredicatedFalse = 1;
28498let addrMode = PostInc;
28499let accessSize = HVXVectorAccess;
28500let isNVStore = 1;
28501let CVINew = 1;
28502let isNewValue = 1;
28503let isNonTemporal = 1;
28504let mayStore = 1;
28505let BaseOpcode = "V6_vS32b_ppu";
28506let DecoderNamespace = "EXT_mmvec";
28507let opNewValue = 4;
28508let Constraints = "$Rx32 = $Rx32in";
28509}
28510def V6_vS32b_nt_new_pi : HInst<
28511(outs IntRegs:$Rx32),
28512(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28513"vmem($Rx32++#$Ii):nt = $Os8.new",
28514tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
28515let Inst{7-3} = 0b00100;
28516let Inst{13-11} = 0b000;
28517let Inst{31-21} = 0b00101001011;
28518let addrMode = PostInc;
28519let accessSize = HVXVectorAccess;
28520let isNVStore = 1;
28521let CVINew = 1;
28522let isNewValue = 1;
28523let isNonTemporal = 1;
28524let mayStore = 1;
28525let BaseOpcode = "V6_vS32b_pi";
28526let isPredicable = 1;
28527let DecoderNamespace = "EXT_mmvec";
28528let opNewValue = 3;
28529let Constraints = "$Rx32 = $Rx32in";
28530}
28531def V6_vS32b_nt_new_ppu : HInst<
28532(outs IntRegs:$Rx32),
28533(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28534"vmem($Rx32++$Mu2):nt = $Os8.new",
28535tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
28536let Inst{12-3} = 0b0000000100;
28537let Inst{31-21} = 0b00101011011;
28538let addrMode = PostInc;
28539let accessSize = HVXVectorAccess;
28540let isNVStore = 1;
28541let CVINew = 1;
28542let isNewValue = 1;
28543let isNonTemporal = 1;
28544let mayStore = 1;
28545let BaseOpcode = "V6_vS32b_ppu";
28546let isPredicable = 1;
28547let DecoderNamespace = "EXT_mmvec";
28548let opNewValue = 3;
28549let Constraints = "$Rx32 = $Rx32in";
28550}
28551def V6_vS32b_nt_new_pred_ai : HInst<
28552(outs),
28553(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28554"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
28555tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28556let Inst{7-3} = 0b01010;
28557let Inst{31-21} = 0b00101000111;
28558let isPredicated = 1;
28559let addrMode = BaseImmOffset;
28560let accessSize = HVXVectorAccess;
28561let isNVStore = 1;
28562let CVINew = 1;
28563let isNewValue = 1;
28564let isNonTemporal = 1;
28565let mayStore = 1;
28566let BaseOpcode = "V6_vS32b_ai";
28567let DecoderNamespace = "EXT_mmvec";
28568let opNewValue = 3;
28569}
28570def V6_vS32b_nt_new_pred_pi : HInst<
28571(outs IntRegs:$Rx32),
28572(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28573"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
28574tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28575let Inst{7-3} = 0b01010;
28576let Inst{13-13} = 0b0;
28577let Inst{31-21} = 0b00101001111;
28578let isPredicated = 1;
28579let addrMode = PostInc;
28580let accessSize = HVXVectorAccess;
28581let isNVStore = 1;
28582let CVINew = 1;
28583let isNewValue = 1;
28584let isNonTemporal = 1;
28585let mayStore = 1;
28586let BaseOpcode = "V6_vS32b_pi";
28587let DecoderNamespace = "EXT_mmvec";
28588let opNewValue = 4;
28589let Constraints = "$Rx32 = $Rx32in";
28590}
28591def V6_vS32b_nt_new_pred_ppu : HInst<
28592(outs IntRegs:$Rx32),
28593(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28594"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
28595tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28596let Inst{10-3} = 0b00001010;
28597let Inst{31-21} = 0b00101011111;
28598let isPredicated = 1;
28599let addrMode = PostInc;
28600let accessSize = HVXVectorAccess;
28601let isNVStore = 1;
28602let CVINew = 1;
28603let isNewValue = 1;
28604let isNonTemporal = 1;
28605let mayStore = 1;
28606let BaseOpcode = "V6_vS32b_ppu";
28607let DecoderNamespace = "EXT_mmvec";
28608let opNewValue = 4;
28609let Constraints = "$Rx32 = $Rx32in";
28610}
28611def V6_vS32b_nt_npred_ai : HInst<
28612(outs),
28613(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28614"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
28615tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28616let Inst{7-5} = 0b001;
28617let Inst{31-21} = 0b00101000111;
28618let isPredicated = 1;
28619let isPredicatedFalse = 1;
28620let addrMode = BaseImmOffset;
28621let accessSize = HVXVectorAccess;
28622let isNonTemporal = 1;
28623let mayStore = 1;
28624let BaseOpcode = "V6_vS32b_ai";
28625let isNVStorable = 1;
28626let DecoderNamespace = "EXT_mmvec";
28627}
28628def V6_vS32b_nt_npred_pi : HInst<
28629(outs IntRegs:$Rx32),
28630(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28631"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
28632tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28633let Inst{7-5} = 0b001;
28634let Inst{13-13} = 0b0;
28635let Inst{31-21} = 0b00101001111;
28636let isPredicated = 1;
28637let isPredicatedFalse = 1;
28638let addrMode = PostInc;
28639let accessSize = HVXVectorAccess;
28640let isNonTemporal = 1;
28641let mayStore = 1;
28642let BaseOpcode = "V6_vS32b_pi";
28643let isNVStorable = 1;
28644let DecoderNamespace = "EXT_mmvec";
28645let Constraints = "$Rx32 = $Rx32in";
28646}
28647def V6_vS32b_nt_npred_ppu : HInst<
28648(outs IntRegs:$Rx32),
28649(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28650"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
28651tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28652let Inst{10-5} = 0b000001;
28653let Inst{31-21} = 0b00101011111;
28654let isPredicated = 1;
28655let isPredicatedFalse = 1;
28656let addrMode = PostInc;
28657let accessSize = HVXVectorAccess;
28658let isNonTemporal = 1;
28659let mayStore = 1;
28660let BaseOpcode = "V6_vS32b_ppu";
28661let isNVStorable = 1;
28662let DecoderNamespace = "EXT_mmvec";
28663let Constraints = "$Rx32 = $Rx32in";
28664}
28665def V6_vS32b_nt_nqpred_ai : HInst<
28666(outs),
28667(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28668"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
28669tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28670let Inst{7-5} = 0b001;
28671let Inst{31-21} = 0b00101000110;
28672let addrMode = BaseImmOffset;
28673let accessSize = HVXVectorAccess;
28674let isNonTemporal = 1;
28675let mayStore = 1;
28676let DecoderNamespace = "EXT_mmvec";
28677}
28678def V6_vS32b_nt_nqpred_pi : HInst<
28679(outs IntRegs:$Rx32),
28680(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28681"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
28682tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28683let Inst{7-5} = 0b001;
28684let Inst{13-13} = 0b0;
28685let Inst{31-21} = 0b00101001110;
28686let addrMode = PostInc;
28687let accessSize = HVXVectorAccess;
28688let isNonTemporal = 1;
28689let mayStore = 1;
28690let DecoderNamespace = "EXT_mmvec";
28691let Constraints = "$Rx32 = $Rx32in";
28692}
28693def V6_vS32b_nt_nqpred_ppu : HInst<
28694(outs IntRegs:$Rx32),
28695(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28696"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
28697tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28698let Inst{10-5} = 0b000001;
28699let Inst{31-21} = 0b00101011110;
28700let addrMode = PostInc;
28701let accessSize = HVXVectorAccess;
28702let isNonTemporal = 1;
28703let mayStore = 1;
28704let DecoderNamespace = "EXT_mmvec";
28705let Constraints = "$Rx32 = $Rx32in";
28706}
28707def V6_vS32b_nt_pi : HInst<
28708(outs IntRegs:$Rx32),
28709(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28710"vmem($Rx32++#$Ii):nt = $Vs32",
28711tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
28712let Inst{7-5} = 0b000;
28713let Inst{13-11} = 0b000;
28714let Inst{31-21} = 0b00101001011;
28715let addrMode = PostInc;
28716let accessSize = HVXVectorAccess;
28717let isNonTemporal = 1;
28718let mayStore = 1;
28719let BaseOpcode = "V6_vS32b_pi";
28720let isNVStorable = 1;
28721let isPredicable = 1;
28722let DecoderNamespace = "EXT_mmvec";
28723let Constraints = "$Rx32 = $Rx32in";
28724}
28725def V6_vS32b_nt_ppu : HInst<
28726(outs IntRegs:$Rx32),
28727(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28728"vmem($Rx32++$Mu2):nt = $Vs32",
28729tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28730let Inst{12-5} = 0b00000000;
28731let Inst{31-21} = 0b00101011011;
28732let addrMode = PostInc;
28733let accessSize = HVXVectorAccess;
28734let isNonTemporal = 1;
28735let mayStore = 1;
28736let BaseOpcode = "V6_vS32b_ppu";
28737let isNVStorable = 1;
28738let isPredicable = 1;
28739let DecoderNamespace = "EXT_mmvec";
28740let Constraints = "$Rx32 = $Rx32in";
28741}
28742def V6_vS32b_nt_pred_ai : HInst<
28743(outs),
28744(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28745"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
28746tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28747let Inst{7-5} = 0b000;
28748let Inst{31-21} = 0b00101000111;
28749let isPredicated = 1;
28750let addrMode = BaseImmOffset;
28751let accessSize = HVXVectorAccess;
28752let isNonTemporal = 1;
28753let mayStore = 1;
28754let BaseOpcode = "V6_vS32b_ai";
28755let isNVStorable = 1;
28756let DecoderNamespace = "EXT_mmvec";
28757}
28758def V6_vS32b_nt_pred_pi : HInst<
28759(outs IntRegs:$Rx32),
28760(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28761"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
28762tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28763let Inst{7-5} = 0b000;
28764let Inst{13-13} = 0b0;
28765let Inst{31-21} = 0b00101001111;
28766let isPredicated = 1;
28767let addrMode = PostInc;
28768let accessSize = HVXVectorAccess;
28769let isNonTemporal = 1;
28770let mayStore = 1;
28771let BaseOpcode = "V6_vS32b_pi";
28772let isNVStorable = 1;
28773let DecoderNamespace = "EXT_mmvec";
28774let Constraints = "$Rx32 = $Rx32in";
28775}
28776def V6_vS32b_nt_pred_ppu : HInst<
28777(outs IntRegs:$Rx32),
28778(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28779"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
28780tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28781let Inst{10-5} = 0b000000;
28782let Inst{31-21} = 0b00101011111;
28783let isPredicated = 1;
28784let addrMode = PostInc;
28785let accessSize = HVXVectorAccess;
28786let isNonTemporal = 1;
28787let mayStore = 1;
28788let BaseOpcode = "V6_vS32b_ppu";
28789let isNVStorable = 1;
28790let DecoderNamespace = "EXT_mmvec";
28791let Constraints = "$Rx32 = $Rx32in";
28792}
28793def V6_vS32b_nt_qpred_ai : HInst<
28794(outs),
28795(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28796"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
28797tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28798let Inst{7-5} = 0b000;
28799let Inst{31-21} = 0b00101000110;
28800let addrMode = BaseImmOffset;
28801let accessSize = HVXVectorAccess;
28802let isNonTemporal = 1;
28803let mayStore = 1;
28804let DecoderNamespace = "EXT_mmvec";
28805}
28806def V6_vS32b_nt_qpred_pi : HInst<
28807(outs IntRegs:$Rx32),
28808(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28809"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
28810tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28811let Inst{7-5} = 0b000;
28812let Inst{13-13} = 0b0;
28813let Inst{31-21} = 0b00101001110;
28814let addrMode = PostInc;
28815let accessSize = HVXVectorAccess;
28816let isNonTemporal = 1;
28817let mayStore = 1;
28818let DecoderNamespace = "EXT_mmvec";
28819let Constraints = "$Rx32 = $Rx32in";
28820}
28821def V6_vS32b_nt_qpred_ppu : HInst<
28822(outs IntRegs:$Rx32),
28823(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28824"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
28825tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28826let Inst{10-5} = 0b000000;
28827let Inst{31-21} = 0b00101011110;
28828let addrMode = PostInc;
28829let accessSize = HVXVectorAccess;
28830let isNonTemporal = 1;
28831let mayStore = 1;
28832let DecoderNamespace = "EXT_mmvec";
28833let Constraints = "$Rx32 = $Rx32in";
28834}
28835def V6_vS32b_pi : HInst<
28836(outs IntRegs:$Rx32),
28837(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28838"vmem($Rx32++#$Ii) = $Vs32",
28839tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
28840let Inst{7-5} = 0b000;
28841let Inst{13-11} = 0b000;
28842let Inst{31-21} = 0b00101001001;
28843let addrMode = PostInc;
28844let accessSize = HVXVectorAccess;
28845let mayStore = 1;
28846let BaseOpcode = "V6_vS32b_pi";
28847let isNVStorable = 1;
28848let isPredicable = 1;
28849let DecoderNamespace = "EXT_mmvec";
28850let Constraints = "$Rx32 = $Rx32in";
28851}
28852def V6_vS32b_ppu : HInst<
28853(outs IntRegs:$Rx32),
28854(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28855"vmem($Rx32++$Mu2) = $Vs32",
28856tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28857let Inst{12-5} = 0b00000000;
28858let Inst{31-21} = 0b00101011001;
28859let addrMode = PostInc;
28860let accessSize = HVXVectorAccess;
28861let mayStore = 1;
28862let isNVStorable = 1;
28863let isPredicable = 1;
28864let DecoderNamespace = "EXT_mmvec";
28865let Constraints = "$Rx32 = $Rx32in";
28866}
28867def V6_vS32b_pred_ai : HInst<
28868(outs),
28869(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28870"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
28871tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28872let Inst{7-5} = 0b000;
28873let Inst{31-21} = 0b00101000101;
28874let isPredicated = 1;
28875let addrMode = BaseImmOffset;
28876let accessSize = HVXVectorAccess;
28877let mayStore = 1;
28878let BaseOpcode = "V6_vS32b_ai";
28879let isNVStorable = 1;
28880let DecoderNamespace = "EXT_mmvec";
28881}
28882def V6_vS32b_pred_pi : HInst<
28883(outs IntRegs:$Rx32),
28884(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28885"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
28886tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28887let Inst{7-5} = 0b000;
28888let Inst{13-13} = 0b0;
28889let Inst{31-21} = 0b00101001101;
28890let isPredicated = 1;
28891let addrMode = PostInc;
28892let accessSize = HVXVectorAccess;
28893let mayStore = 1;
28894let BaseOpcode = "V6_vS32b_pi";
28895let isNVStorable = 1;
28896let DecoderNamespace = "EXT_mmvec";
28897let Constraints = "$Rx32 = $Rx32in";
28898}
28899def V6_vS32b_pred_ppu : HInst<
28900(outs IntRegs:$Rx32),
28901(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28902"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
28903tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28904let Inst{10-5} = 0b000000;
28905let Inst{31-21} = 0b00101011101;
28906let isPredicated = 1;
28907let addrMode = PostInc;
28908let accessSize = HVXVectorAccess;
28909let mayStore = 1;
28910let BaseOpcode = "V6_vS32b_ppu";
28911let isNVStorable = 1;
28912let DecoderNamespace = "EXT_mmvec";
28913let Constraints = "$Rx32 = $Rx32in";
28914}
28915def V6_vS32b_qpred_ai : HInst<
28916(outs),
28917(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28918"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
28919tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
28920let Inst{7-5} = 0b000;
28921let Inst{31-21} = 0b00101000100;
28922let addrMode = BaseImmOffset;
28923let accessSize = HVXVectorAccess;
28924let mayStore = 1;
28925let DecoderNamespace = "EXT_mmvec";
28926}
28927def V6_vS32b_qpred_pi : HInst<
28928(outs IntRegs:$Rx32),
28929(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28930"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
28931tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
28932let Inst{7-5} = 0b000;
28933let Inst{13-13} = 0b0;
28934let Inst{31-21} = 0b00101001100;
28935let addrMode = PostInc;
28936let accessSize = HVXVectorAccess;
28937let mayStore = 1;
28938let DecoderNamespace = "EXT_mmvec";
28939let Constraints = "$Rx32 = $Rx32in";
28940}
28941def V6_vS32b_qpred_ppu : HInst<
28942(outs IntRegs:$Rx32),
28943(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28944"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
28945tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
28946let Inst{10-5} = 0b000000;
28947let Inst{31-21} = 0b00101011100;
28948let addrMode = PostInc;
28949let accessSize = HVXVectorAccess;
28950let mayStore = 1;
28951let DecoderNamespace = "EXT_mmvec";
28952let Constraints = "$Rx32 = $Rx32in";
28953}
28954def V6_vS32b_srls_ai : HInst<
28955(outs),
28956(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28957"vmem($Rt32+#$Ii):scatter_release",
28958tc_3ce09744, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
28959let Inst{7-0} = 0b00101000;
28960let Inst{12-11} = 0b00;
28961let Inst{31-21} = 0b00101000001;
28962let addrMode = BaseImmOffset;
28963let accessSize = HVXVectorAccess;
28964let CVINew = 1;
28965let mayStore = 1;
28966let DecoderNamespace = "EXT_mmvec";
28967}
28968def V6_vS32b_srls_pi : HInst<
28969(outs IntRegs:$Rx32),
28970(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28971"vmem($Rx32++#$Ii):scatter_release",
28972tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
28973let Inst{7-0} = 0b00101000;
28974let Inst{13-11} = 0b000;
28975let Inst{31-21} = 0b00101001001;
28976let addrMode = PostInc;
28977let accessSize = HVXVectorAccess;
28978let CVINew = 1;
28979let mayStore = 1;
28980let DecoderNamespace = "EXT_mmvec";
28981let Constraints = "$Rx32 = $Rx32in";
28982}
28983def V6_vS32b_srls_ppu : HInst<
28984(outs IntRegs:$Rx32),
28985(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28986"vmem($Rx32++$Mu2):scatter_release",
28987tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
28988let Inst{12-0} = 0b0000000101000;
28989let Inst{31-21} = 0b00101011001;
28990let addrMode = PostInc;
28991let accessSize = HVXVectorAccess;
28992let CVINew = 1;
28993let mayStore = 1;
28994let DecoderNamespace = "EXT_mmvec";
28995let Constraints = "$Rx32 = $Rx32in";
28996}
28997def V6_vabsb : HInst<
28998(outs HvxVR:$Vd32),
28999(ins HvxVR:$Vu32),
29000"$Vd32.b = vabs($Vu32.b)",
29001tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29002let Inst{7-5} = 0b100;
29003let Inst{13-13} = 0b0;
29004let Inst{31-16} = 0b0001111000000001;
29005let hasNewValue = 1;
29006let opNewValue = 0;
29007let DecoderNamespace = "EXT_mmvec";
29008}
29009def V6_vabsb_alt : HInst<
29010(outs HvxVR:$Vd32),
29011(ins HvxVR:$Vu32),
29012"$Vd32 = vabsb($Vu32)",
29013PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29014let hasNewValue = 1;
29015let opNewValue = 0;
29016let isPseudo = 1;
29017let isCodeGenOnly = 1;
29018let DecoderNamespace = "EXT_mmvec";
29019}
29020def V6_vabsb_sat : HInst<
29021(outs HvxVR:$Vd32),
29022(ins HvxVR:$Vu32),
29023"$Vd32.b = vabs($Vu32.b):sat",
29024tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29025let Inst{7-5} = 0b101;
29026let Inst{13-13} = 0b0;
29027let Inst{31-16} = 0b0001111000000001;
29028let hasNewValue = 1;
29029let opNewValue = 0;
29030let DecoderNamespace = "EXT_mmvec";
29031}
29032def V6_vabsb_sat_alt : HInst<
29033(outs HvxVR:$Vd32),
29034(ins HvxVR:$Vu32),
29035"$Vd32 = vabsb($Vu32):sat",
29036PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29037let hasNewValue = 1;
29038let opNewValue = 0;
29039let isPseudo = 1;
29040let isCodeGenOnly = 1;
29041let DecoderNamespace = "EXT_mmvec";
29042}
29043def V6_vabsdiffh : HInst<
29044(outs HvxVR:$Vd32),
29045(ins HvxVR:$Vu32, HvxVR:$Vv32),
29046"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
29047tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29048let Inst{7-5} = 0b001;
29049let Inst{13-13} = 0b0;
29050let Inst{31-21} = 0b00011100110;
29051let hasNewValue = 1;
29052let opNewValue = 0;
29053let DecoderNamespace = "EXT_mmvec";
29054}
29055def V6_vabsdiffh_alt : HInst<
29056(outs HvxVR:$Vd32),
29057(ins HvxVR:$Vu32, HvxVR:$Vv32),
29058"$Vd32 = vabsdiffh($Vu32,$Vv32)",
29059PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29060let hasNewValue = 1;
29061let opNewValue = 0;
29062let isPseudo = 1;
29063let isCodeGenOnly = 1;
29064let DecoderNamespace = "EXT_mmvec";
29065}
29066def V6_vabsdiffub : HInst<
29067(outs HvxVR:$Vd32),
29068(ins HvxVR:$Vu32, HvxVR:$Vv32),
29069"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
29070tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29071let Inst{7-5} = 0b000;
29072let Inst{13-13} = 0b0;
29073let Inst{31-21} = 0b00011100110;
29074let hasNewValue = 1;
29075let opNewValue = 0;
29076let DecoderNamespace = "EXT_mmvec";
29077}
29078def V6_vabsdiffub_alt : HInst<
29079(outs HvxVR:$Vd32),
29080(ins HvxVR:$Vu32, HvxVR:$Vv32),
29081"$Vd32 = vabsdiffub($Vu32,$Vv32)",
29082PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29083let hasNewValue = 1;
29084let opNewValue = 0;
29085let isPseudo = 1;
29086let isCodeGenOnly = 1;
29087let DecoderNamespace = "EXT_mmvec";
29088}
29089def V6_vabsdiffuh : HInst<
29090(outs HvxVR:$Vd32),
29091(ins HvxVR:$Vu32, HvxVR:$Vv32),
29092"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
29093tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29094let Inst{7-5} = 0b010;
29095let Inst{13-13} = 0b0;
29096let Inst{31-21} = 0b00011100110;
29097let hasNewValue = 1;
29098let opNewValue = 0;
29099let DecoderNamespace = "EXT_mmvec";
29100}
29101def V6_vabsdiffuh_alt : HInst<
29102(outs HvxVR:$Vd32),
29103(ins HvxVR:$Vu32, HvxVR:$Vv32),
29104"$Vd32 = vabsdiffuh($Vu32,$Vv32)",
29105PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29106let hasNewValue = 1;
29107let opNewValue = 0;
29108let isPseudo = 1;
29109let isCodeGenOnly = 1;
29110let DecoderNamespace = "EXT_mmvec";
29111}
29112def V6_vabsdiffw : HInst<
29113(outs HvxVR:$Vd32),
29114(ins HvxVR:$Vu32, HvxVR:$Vv32),
29115"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
29116tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29117let Inst{7-5} = 0b011;
29118let Inst{13-13} = 0b0;
29119let Inst{31-21} = 0b00011100110;
29120let hasNewValue = 1;
29121let opNewValue = 0;
29122let DecoderNamespace = "EXT_mmvec";
29123}
29124def V6_vabsdiffw_alt : HInst<
29125(outs HvxVR:$Vd32),
29126(ins HvxVR:$Vu32, HvxVR:$Vv32),
29127"$Vd32 = vabsdiffw($Vu32,$Vv32)",
29128PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29129let hasNewValue = 1;
29130let opNewValue = 0;
29131let isPseudo = 1;
29132let isCodeGenOnly = 1;
29133let DecoderNamespace = "EXT_mmvec";
29134}
29135def V6_vabsh : HInst<
29136(outs HvxVR:$Vd32),
29137(ins HvxVR:$Vu32),
29138"$Vd32.h = vabs($Vu32.h)",
29139tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29140let Inst{7-5} = 0b000;
29141let Inst{13-13} = 0b0;
29142let Inst{31-16} = 0b0001111000000000;
29143let hasNewValue = 1;
29144let opNewValue = 0;
29145let DecoderNamespace = "EXT_mmvec";
29146}
29147def V6_vabsh_alt : HInst<
29148(outs HvxVR:$Vd32),
29149(ins HvxVR:$Vu32),
29150"$Vd32 = vabsh($Vu32)",
29151PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29152let hasNewValue = 1;
29153let opNewValue = 0;
29154let isPseudo = 1;
29155let isCodeGenOnly = 1;
29156let DecoderNamespace = "EXT_mmvec";
29157}
29158def V6_vabsh_sat : HInst<
29159(outs HvxVR:$Vd32),
29160(ins HvxVR:$Vu32),
29161"$Vd32.h = vabs($Vu32.h):sat",
29162tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29163let Inst{7-5} = 0b001;
29164let Inst{13-13} = 0b0;
29165let Inst{31-16} = 0b0001111000000000;
29166let hasNewValue = 1;
29167let opNewValue = 0;
29168let DecoderNamespace = "EXT_mmvec";
29169}
29170def V6_vabsh_sat_alt : HInst<
29171(outs HvxVR:$Vd32),
29172(ins HvxVR:$Vu32),
29173"$Vd32 = vabsh($Vu32):sat",
29174PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29175let hasNewValue = 1;
29176let opNewValue = 0;
29177let isPseudo = 1;
29178let isCodeGenOnly = 1;
29179let DecoderNamespace = "EXT_mmvec";
29180}
29181def V6_vabsub_alt : HInst<
29182(outs HvxVR:$Vd32),
29183(ins HvxVR:$Vu32),
29184"$Vd32.ub = vabs($Vu32.b)",
29185tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29186let hasNewValue = 1;
29187let opNewValue = 0;
29188let isPseudo = 1;
29189let isCodeGenOnly = 1;
29190let DecoderNamespace = "EXT_mmvec";
29191}
29192def V6_vabsuh_alt : HInst<
29193(outs HvxVR:$Vd32),
29194(ins HvxVR:$Vu32),
29195"$Vd32.uh = vabs($Vu32.h)",
29196tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29197let hasNewValue = 1;
29198let opNewValue = 0;
29199let isPseudo = 1;
29200let isCodeGenOnly = 1;
29201let DecoderNamespace = "EXT_mmvec";
29202}
29203def V6_vabsuw_alt : HInst<
29204(outs HvxVR:$Vd32),
29205(ins HvxVR:$Vu32),
29206"$Vd32.uw = vabs($Vu32.w)",
29207tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29208let hasNewValue = 1;
29209let opNewValue = 0;
29210let isPseudo = 1;
29211let isCodeGenOnly = 1;
29212let DecoderNamespace = "EXT_mmvec";
29213}
29214def V6_vabsw : HInst<
29215(outs HvxVR:$Vd32),
29216(ins HvxVR:$Vu32),
29217"$Vd32.w = vabs($Vu32.w)",
29218tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29219let Inst{7-5} = 0b010;
29220let Inst{13-13} = 0b0;
29221let Inst{31-16} = 0b0001111000000000;
29222let hasNewValue = 1;
29223let opNewValue = 0;
29224let DecoderNamespace = "EXT_mmvec";
29225}
29226def V6_vabsw_alt : HInst<
29227(outs HvxVR:$Vd32),
29228(ins HvxVR:$Vu32),
29229"$Vd32 = vabsw($Vu32)",
29230PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29231let hasNewValue = 1;
29232let opNewValue = 0;
29233let isPseudo = 1;
29234let isCodeGenOnly = 1;
29235let DecoderNamespace = "EXT_mmvec";
29236}
29237def V6_vabsw_sat : HInst<
29238(outs HvxVR:$Vd32),
29239(ins HvxVR:$Vu32),
29240"$Vd32.w = vabs($Vu32.w):sat",
29241tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29242let Inst{7-5} = 0b011;
29243let Inst{13-13} = 0b0;
29244let Inst{31-16} = 0b0001111000000000;
29245let hasNewValue = 1;
29246let opNewValue = 0;
29247let DecoderNamespace = "EXT_mmvec";
29248}
29249def V6_vabsw_sat_alt : HInst<
29250(outs HvxVR:$Vd32),
29251(ins HvxVR:$Vu32),
29252"$Vd32 = vabsw($Vu32):sat",
29253PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29254let hasNewValue = 1;
29255let opNewValue = 0;
29256let isPseudo = 1;
29257let isCodeGenOnly = 1;
29258let DecoderNamespace = "EXT_mmvec";
29259}
29260def V6_vaddb : HInst<
29261(outs HvxVR:$Vd32),
29262(ins HvxVR:$Vu32, HvxVR:$Vv32),
29263"$Vd32.b = vadd($Vu32.b,$Vv32.b)",
29264tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29265let Inst{7-5} = 0b110;
29266let Inst{13-13} = 0b0;
29267let Inst{31-21} = 0b00011111101;
29268let hasNewValue = 1;
29269let opNewValue = 0;
29270let DecoderNamespace = "EXT_mmvec";
29271}
29272def V6_vaddb_alt : HInst<
29273(outs HvxVR:$Vd32),
29274(ins HvxVR:$Vu32, HvxVR:$Vv32),
29275"$Vd32 = vaddb($Vu32,$Vv32)",
29276PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29277let hasNewValue = 1;
29278let opNewValue = 0;
29279let isPseudo = 1;
29280let isCodeGenOnly = 1;
29281let DecoderNamespace = "EXT_mmvec";
29282}
29283def V6_vaddb_dv : HInst<
29284(outs HvxWR:$Vdd32),
29285(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29286"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
29287tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29288let Inst{7-5} = 0b100;
29289let Inst{13-13} = 0b0;
29290let Inst{31-21} = 0b00011100011;
29291let hasNewValue = 1;
29292let opNewValue = 0;
29293let DecoderNamespace = "EXT_mmvec";
29294}
29295def V6_vaddb_dv_alt : HInst<
29296(outs HvxWR:$Vdd32),
29297(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29298"$Vdd32 = vaddb($Vuu32,$Vvv32)",
29299PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29300let hasNewValue = 1;
29301let opNewValue = 0;
29302let isPseudo = 1;
29303let isCodeGenOnly = 1;
29304let DecoderNamespace = "EXT_mmvec";
29305}
29306def V6_vaddbnq : HInst<
29307(outs HvxVR:$Vx32),
29308(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29309"if (!$Qv4) $Vx32.b += $Vu32.b",
29310tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29311let Inst{7-5} = 0b011;
29312let Inst{13-13} = 0b1;
29313let Inst{21-16} = 0b000001;
29314let Inst{31-24} = 0b00011110;
29315let hasNewValue = 1;
29316let opNewValue = 0;
29317let isAccumulator = 1;
29318let DecoderNamespace = "EXT_mmvec";
29319let Constraints = "$Vx32 = $Vx32in";
29320}
29321def V6_vaddbnq_alt : HInst<
29322(outs HvxVR:$Vx32),
29323(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29324"if (!$Qv4.b) $Vx32.b += $Vu32.b",
29325PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29326let hasNewValue = 1;
29327let opNewValue = 0;
29328let isAccumulator = 1;
29329let isPseudo = 1;
29330let isCodeGenOnly = 1;
29331let DecoderNamespace = "EXT_mmvec";
29332let Constraints = "$Vx32 = $Vx32in";
29333}
29334def V6_vaddbq : HInst<
29335(outs HvxVR:$Vx32),
29336(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29337"if ($Qv4) $Vx32.b += $Vu32.b",
29338tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29339let Inst{7-5} = 0b000;
29340let Inst{13-13} = 0b1;
29341let Inst{21-16} = 0b000001;
29342let Inst{31-24} = 0b00011110;
29343let hasNewValue = 1;
29344let opNewValue = 0;
29345let isAccumulator = 1;
29346let DecoderNamespace = "EXT_mmvec";
29347let Constraints = "$Vx32 = $Vx32in";
29348}
29349def V6_vaddbq_alt : HInst<
29350(outs HvxVR:$Vx32),
29351(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29352"if ($Qv4.b) $Vx32.b += $Vu32.b",
29353PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29354let hasNewValue = 1;
29355let opNewValue = 0;
29356let isAccumulator = 1;
29357let isPseudo = 1;
29358let isCodeGenOnly = 1;
29359let DecoderNamespace = "EXT_mmvec";
29360let Constraints = "$Vx32 = $Vx32in";
29361}
29362def V6_vaddbsat : HInst<
29363(outs HvxVR:$Vd32),
29364(ins HvxVR:$Vu32, HvxVR:$Vv32),
29365"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
29366tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
29367let Inst{7-5} = 0b000;
29368let Inst{13-13} = 0b0;
29369let Inst{31-21} = 0b00011111000;
29370let hasNewValue = 1;
29371let opNewValue = 0;
29372let DecoderNamespace = "EXT_mmvec";
29373}
29374def V6_vaddbsat_alt : HInst<
29375(outs HvxVR:$Vd32),
29376(ins HvxVR:$Vu32, HvxVR:$Vv32),
29377"$Vd32 = vaddb($Vu32,$Vv32):sat",
29378PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29379let hasNewValue = 1;
29380let opNewValue = 0;
29381let isPseudo = 1;
29382let isCodeGenOnly = 1;
29383let DecoderNamespace = "EXT_mmvec";
29384}
29385def V6_vaddbsat_dv : HInst<
29386(outs HvxWR:$Vdd32),
29387(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29388"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
29389tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
29390let Inst{7-5} = 0b000;
29391let Inst{13-13} = 0b0;
29392let Inst{31-21} = 0b00011110101;
29393let hasNewValue = 1;
29394let opNewValue = 0;
29395let DecoderNamespace = "EXT_mmvec";
29396}
29397def V6_vaddbsat_dv_alt : HInst<
29398(outs HvxWR:$Vdd32),
29399(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29400"$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
29401PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29402let hasNewValue = 1;
29403let opNewValue = 0;
29404let isPseudo = 1;
29405let isCodeGenOnly = 1;
29406let DecoderNamespace = "EXT_mmvec";
29407}
29408def V6_vaddcarry : HInst<
29409(outs HvxVR:$Vd32, HvxQR:$Qx4),
29410(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
29411"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
29412tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
29413let Inst{7-7} = 0b0;
29414let Inst{13-13} = 0b1;
29415let Inst{31-21} = 0b00011100101;
29416let hasNewValue = 1;
29417let opNewValue = 0;
29418let DecoderNamespace = "EXT_mmvec";
29419let Constraints = "$Qx4 = $Qx4in";
29420}
29421def V6_vaddcarryo : HInst<
29422(outs HvxVR:$Vd32, HvxQR:$Qe4),
29423(ins HvxVR:$Vu32, HvxVR:$Vv32),
29424"$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry",
29425tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> {
29426let Inst{7-7} = 0b0;
29427let Inst{13-13} = 0b1;
29428let Inst{31-21} = 0b00011101101;
29429let hasNewValue = 1;
29430let opNewValue = 0;
29431let hasNewValue2 = 1;
29432let opNewValue2 = 1;
29433let DecoderNamespace = "EXT_mmvec";
29434}
29435def V6_vaddcarrysat : HInst<
29436(outs HvxVR:$Vd32),
29437(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qs4),
29438"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qs4):carry:sat",
29439tc_257f6f7c, TypeCVI_VA>, Enc_e0820b, Requires<[UseHVXV66]> {
29440let Inst{7-7} = 0b0;
29441let Inst{13-13} = 0b1;
29442let Inst{31-21} = 0b00011101100;
29443let hasNewValue = 1;
29444let opNewValue = 0;
29445let DecoderNamespace = "EXT_mmvec";
29446}
29447def V6_vaddclbh : HInst<
29448(outs HvxVR:$Vd32),
29449(ins HvxVR:$Vu32, HvxVR:$Vv32),
29450"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
29451tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
29452let Inst{7-5} = 0b000;
29453let Inst{13-13} = 0b1;
29454let Inst{31-21} = 0b00011111000;
29455let hasNewValue = 1;
29456let opNewValue = 0;
29457let DecoderNamespace = "EXT_mmvec";
29458}
29459def V6_vaddclbw : HInst<
29460(outs HvxVR:$Vd32),
29461(ins HvxVR:$Vu32, HvxVR:$Vv32),
29462"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
29463tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
29464let Inst{7-5} = 0b001;
29465let Inst{13-13} = 0b1;
29466let Inst{31-21} = 0b00011111000;
29467let hasNewValue = 1;
29468let opNewValue = 0;
29469let DecoderNamespace = "EXT_mmvec";
29470}
29471def V6_vaddh : HInst<
29472(outs HvxVR:$Vd32),
29473(ins HvxVR:$Vu32, HvxVR:$Vv32),
29474"$Vd32.h = vadd($Vu32.h,$Vv32.h)",
29475tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29476let Inst{7-5} = 0b111;
29477let Inst{13-13} = 0b0;
29478let Inst{31-21} = 0b00011111101;
29479let hasNewValue = 1;
29480let opNewValue = 0;
29481let DecoderNamespace = "EXT_mmvec";
29482}
29483def V6_vaddh_alt : HInst<
29484(outs HvxVR:$Vd32),
29485(ins HvxVR:$Vu32, HvxVR:$Vv32),
29486"$Vd32 = vaddh($Vu32,$Vv32)",
29487PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29488let hasNewValue = 1;
29489let opNewValue = 0;
29490let isPseudo = 1;
29491let isCodeGenOnly = 1;
29492let DecoderNamespace = "EXT_mmvec";
29493}
29494def V6_vaddh_dv : HInst<
29495(outs HvxWR:$Vdd32),
29496(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29497"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
29498tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29499let Inst{7-5} = 0b101;
29500let Inst{13-13} = 0b0;
29501let Inst{31-21} = 0b00011100011;
29502let hasNewValue = 1;
29503let opNewValue = 0;
29504let DecoderNamespace = "EXT_mmvec";
29505}
29506def V6_vaddh_dv_alt : HInst<
29507(outs HvxWR:$Vdd32),
29508(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29509"$Vdd32 = vaddh($Vuu32,$Vvv32)",
29510PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29511let hasNewValue = 1;
29512let opNewValue = 0;
29513let isPseudo = 1;
29514let isCodeGenOnly = 1;
29515let DecoderNamespace = "EXT_mmvec";
29516}
29517def V6_vaddhnq : HInst<
29518(outs HvxVR:$Vx32),
29519(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29520"if (!$Qv4) $Vx32.h += $Vu32.h",
29521tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29522let Inst{7-5} = 0b100;
29523let Inst{13-13} = 0b1;
29524let Inst{21-16} = 0b000001;
29525let Inst{31-24} = 0b00011110;
29526let hasNewValue = 1;
29527let opNewValue = 0;
29528let isAccumulator = 1;
29529let DecoderNamespace = "EXT_mmvec";
29530let Constraints = "$Vx32 = $Vx32in";
29531}
29532def V6_vaddhnq_alt : HInst<
29533(outs HvxVR:$Vx32),
29534(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29535"if (!$Qv4.h) $Vx32.h += $Vu32.h",
29536PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29537let hasNewValue = 1;
29538let opNewValue = 0;
29539let isAccumulator = 1;
29540let isPseudo = 1;
29541let isCodeGenOnly = 1;
29542let DecoderNamespace = "EXT_mmvec";
29543let Constraints = "$Vx32 = $Vx32in";
29544}
29545def V6_vaddhq : HInst<
29546(outs HvxVR:$Vx32),
29547(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29548"if ($Qv4) $Vx32.h += $Vu32.h",
29549tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29550let Inst{7-5} = 0b001;
29551let Inst{13-13} = 0b1;
29552let Inst{21-16} = 0b000001;
29553let Inst{31-24} = 0b00011110;
29554let hasNewValue = 1;
29555let opNewValue = 0;
29556let isAccumulator = 1;
29557let DecoderNamespace = "EXT_mmvec";
29558let Constraints = "$Vx32 = $Vx32in";
29559}
29560def V6_vaddhq_alt : HInst<
29561(outs HvxVR:$Vx32),
29562(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29563"if ($Qv4.h) $Vx32.h += $Vu32.h",
29564PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29565let hasNewValue = 1;
29566let opNewValue = 0;
29567let isAccumulator = 1;
29568let isPseudo = 1;
29569let isCodeGenOnly = 1;
29570let DecoderNamespace = "EXT_mmvec";
29571let Constraints = "$Vx32 = $Vx32in";
29572}
29573def V6_vaddhsat : HInst<
29574(outs HvxVR:$Vd32),
29575(ins HvxVR:$Vu32, HvxVR:$Vv32),
29576"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
29577tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29578let Inst{7-5} = 0b011;
29579let Inst{13-13} = 0b0;
29580let Inst{31-21} = 0b00011100010;
29581let hasNewValue = 1;
29582let opNewValue = 0;
29583let DecoderNamespace = "EXT_mmvec";
29584}
29585def V6_vaddhsat_alt : HInst<
29586(outs HvxVR:$Vd32),
29587(ins HvxVR:$Vu32, HvxVR:$Vv32),
29588"$Vd32 = vaddh($Vu32,$Vv32):sat",
29589PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29590let hasNewValue = 1;
29591let opNewValue = 0;
29592let isPseudo = 1;
29593let isCodeGenOnly = 1;
29594let DecoderNamespace = "EXT_mmvec";
29595}
29596def V6_vaddhsat_dv : HInst<
29597(outs HvxWR:$Vdd32),
29598(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29599"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
29600tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29601let Inst{7-5} = 0b001;
29602let Inst{13-13} = 0b0;
29603let Inst{31-21} = 0b00011100100;
29604let hasNewValue = 1;
29605let opNewValue = 0;
29606let DecoderNamespace = "EXT_mmvec";
29607}
29608def V6_vaddhsat_dv_alt : HInst<
29609(outs HvxWR:$Vdd32),
29610(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29611"$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
29612PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29613let hasNewValue = 1;
29614let opNewValue = 0;
29615let isPseudo = 1;
29616let isCodeGenOnly = 1;
29617let DecoderNamespace = "EXT_mmvec";
29618}
29619def V6_vaddhw : HInst<
29620(outs HvxWR:$Vdd32),
29621(ins HvxVR:$Vu32, HvxVR:$Vv32),
29622"$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
29623tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
29624let Inst{7-5} = 0b100;
29625let Inst{13-13} = 0b0;
29626let Inst{31-21} = 0b00011100101;
29627let hasNewValue = 1;
29628let opNewValue = 0;
29629let DecoderNamespace = "EXT_mmvec";
29630}
29631def V6_vaddhw_acc : HInst<
29632(outs HvxWR:$Vxx32),
29633(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29634"$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
29635tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
29636let Inst{7-5} = 0b010;
29637let Inst{13-13} = 0b1;
29638let Inst{31-21} = 0b00011100001;
29639let hasNewValue = 1;
29640let opNewValue = 0;
29641let isAccumulator = 1;
29642let DecoderNamespace = "EXT_mmvec";
29643let Constraints = "$Vxx32 = $Vxx32in";
29644}
29645def V6_vaddhw_acc_alt : HInst<
29646(outs HvxWR:$Vxx32),
29647(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29648"$Vxx32 += vaddh($Vu32,$Vv32)",
29649PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29650let hasNewValue = 1;
29651let opNewValue = 0;
29652let isAccumulator = 1;
29653let isPseudo = 1;
29654let isCodeGenOnly = 1;
29655let DecoderNamespace = "EXT_mmvec";
29656let Constraints = "$Vxx32 = $Vxx32in";
29657}
29658def V6_vaddhw_alt : HInst<
29659(outs HvxWR:$Vdd32),
29660(ins HvxVR:$Vu32, HvxVR:$Vv32),
29661"$Vdd32 = vaddh($Vu32,$Vv32)",
29662PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29663let hasNewValue = 1;
29664let opNewValue = 0;
29665let isPseudo = 1;
29666let isCodeGenOnly = 1;
29667let DecoderNamespace = "EXT_mmvec";
29668}
29669def V6_vaddubh : HInst<
29670(outs HvxWR:$Vdd32),
29671(ins HvxVR:$Vu32, HvxVR:$Vv32),
29672"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
29673tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
29674let Inst{7-5} = 0b010;
29675let Inst{13-13} = 0b0;
29676let Inst{31-21} = 0b00011100101;
29677let hasNewValue = 1;
29678let opNewValue = 0;
29679let DecoderNamespace = "EXT_mmvec";
29680}
29681def V6_vaddubh_acc : HInst<
29682(outs HvxWR:$Vxx32),
29683(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29684"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
29685tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
29686let Inst{7-5} = 0b101;
29687let Inst{13-13} = 0b1;
29688let Inst{31-21} = 0b00011100010;
29689let hasNewValue = 1;
29690let opNewValue = 0;
29691let isAccumulator = 1;
29692let DecoderNamespace = "EXT_mmvec";
29693let Constraints = "$Vxx32 = $Vxx32in";
29694}
29695def V6_vaddubh_acc_alt : HInst<
29696(outs HvxWR:$Vxx32),
29697(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29698"$Vxx32 += vaddub($Vu32,$Vv32)",
29699PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29700let hasNewValue = 1;
29701let opNewValue = 0;
29702let isAccumulator = 1;
29703let isPseudo = 1;
29704let isCodeGenOnly = 1;
29705let DecoderNamespace = "EXT_mmvec";
29706let Constraints = "$Vxx32 = $Vxx32in";
29707}
29708def V6_vaddubh_alt : HInst<
29709(outs HvxWR:$Vdd32),
29710(ins HvxVR:$Vu32, HvxVR:$Vv32),
29711"$Vdd32 = vaddub($Vu32,$Vv32)",
29712PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29713let hasNewValue = 1;
29714let opNewValue = 0;
29715let isPseudo = 1;
29716let isCodeGenOnly = 1;
29717let DecoderNamespace = "EXT_mmvec";
29718}
29719def V6_vaddubsat : HInst<
29720(outs HvxVR:$Vd32),
29721(ins HvxVR:$Vu32, HvxVR:$Vv32),
29722"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
29723tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29724let Inst{7-5} = 0b001;
29725let Inst{13-13} = 0b0;
29726let Inst{31-21} = 0b00011100010;
29727let hasNewValue = 1;
29728let opNewValue = 0;
29729let DecoderNamespace = "EXT_mmvec";
29730}
29731def V6_vaddubsat_alt : HInst<
29732(outs HvxVR:$Vd32),
29733(ins HvxVR:$Vu32, HvxVR:$Vv32),
29734"$Vd32 = vaddub($Vu32,$Vv32):sat",
29735PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29736let hasNewValue = 1;
29737let opNewValue = 0;
29738let isPseudo = 1;
29739let isCodeGenOnly = 1;
29740let DecoderNamespace = "EXT_mmvec";
29741}
29742def V6_vaddubsat_dv : HInst<
29743(outs HvxWR:$Vdd32),
29744(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29745"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
29746tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29747let Inst{7-5} = 0b111;
29748let Inst{13-13} = 0b0;
29749let Inst{31-21} = 0b00011100011;
29750let hasNewValue = 1;
29751let opNewValue = 0;
29752let DecoderNamespace = "EXT_mmvec";
29753}
29754def V6_vaddubsat_dv_alt : HInst<
29755(outs HvxWR:$Vdd32),
29756(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29757"$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
29758PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29759let hasNewValue = 1;
29760let opNewValue = 0;
29761let isPseudo = 1;
29762let isCodeGenOnly = 1;
29763let DecoderNamespace = "EXT_mmvec";
29764}
29765def V6_vaddububb_sat : HInst<
29766(outs HvxVR:$Vd32),
29767(ins HvxVR:$Vu32, HvxVR:$Vv32),
29768"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
29769tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
29770let Inst{7-5} = 0b100;
29771let Inst{13-13} = 0b0;
29772let Inst{31-21} = 0b00011110101;
29773let hasNewValue = 1;
29774let opNewValue = 0;
29775let DecoderNamespace = "EXT_mmvec";
29776}
29777def V6_vadduhsat : HInst<
29778(outs HvxVR:$Vd32),
29779(ins HvxVR:$Vu32, HvxVR:$Vv32),
29780"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
29781tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29782let Inst{7-5} = 0b010;
29783let Inst{13-13} = 0b0;
29784let Inst{31-21} = 0b00011100010;
29785let hasNewValue = 1;
29786let opNewValue = 0;
29787let DecoderNamespace = "EXT_mmvec";
29788}
29789def V6_vadduhsat_alt : HInst<
29790(outs HvxVR:$Vd32),
29791(ins HvxVR:$Vu32, HvxVR:$Vv32),
29792"$Vd32 = vadduh($Vu32,$Vv32):sat",
29793PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29794let hasNewValue = 1;
29795let opNewValue = 0;
29796let isPseudo = 1;
29797let isCodeGenOnly = 1;
29798let DecoderNamespace = "EXT_mmvec";
29799}
29800def V6_vadduhsat_dv : HInst<
29801(outs HvxWR:$Vdd32),
29802(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29803"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
29804tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29805let Inst{7-5} = 0b000;
29806let Inst{13-13} = 0b0;
29807let Inst{31-21} = 0b00011100100;
29808let hasNewValue = 1;
29809let opNewValue = 0;
29810let DecoderNamespace = "EXT_mmvec";
29811}
29812def V6_vadduhsat_dv_alt : HInst<
29813(outs HvxWR:$Vdd32),
29814(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29815"$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
29816PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29817let hasNewValue = 1;
29818let opNewValue = 0;
29819let isPseudo = 1;
29820let isCodeGenOnly = 1;
29821let DecoderNamespace = "EXT_mmvec";
29822}
29823def V6_vadduhw : HInst<
29824(outs HvxWR:$Vdd32),
29825(ins HvxVR:$Vu32, HvxVR:$Vv32),
29826"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
29827tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
29828let Inst{7-5} = 0b011;
29829let Inst{13-13} = 0b0;
29830let Inst{31-21} = 0b00011100101;
29831let hasNewValue = 1;
29832let opNewValue = 0;
29833let DecoderNamespace = "EXT_mmvec";
29834}
29835def V6_vadduhw_acc : HInst<
29836(outs HvxWR:$Vxx32),
29837(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29838"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
29839tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
29840let Inst{7-5} = 0b100;
29841let Inst{13-13} = 0b1;
29842let Inst{31-21} = 0b00011100010;
29843let hasNewValue = 1;
29844let opNewValue = 0;
29845let isAccumulator = 1;
29846let DecoderNamespace = "EXT_mmvec";
29847let Constraints = "$Vxx32 = $Vxx32in";
29848}
29849def V6_vadduhw_acc_alt : HInst<
29850(outs HvxWR:$Vxx32),
29851(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
29852"$Vxx32 += vadduh($Vu32,$Vv32)",
29853PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29854let hasNewValue = 1;
29855let opNewValue = 0;
29856let isAccumulator = 1;
29857let isPseudo = 1;
29858let isCodeGenOnly = 1;
29859let DecoderNamespace = "EXT_mmvec";
29860let Constraints = "$Vxx32 = $Vxx32in";
29861}
29862def V6_vadduhw_alt : HInst<
29863(outs HvxWR:$Vdd32),
29864(ins HvxVR:$Vu32, HvxVR:$Vv32),
29865"$Vdd32 = vadduh($Vu32,$Vv32)",
29866PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29867let hasNewValue = 1;
29868let opNewValue = 0;
29869let isPseudo = 1;
29870let isCodeGenOnly = 1;
29871let DecoderNamespace = "EXT_mmvec";
29872}
29873def V6_vadduwsat : HInst<
29874(outs HvxVR:$Vd32),
29875(ins HvxVR:$Vu32, HvxVR:$Vv32),
29876"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
29877tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
29878let Inst{7-5} = 0b001;
29879let Inst{13-13} = 0b0;
29880let Inst{31-21} = 0b00011111011;
29881let hasNewValue = 1;
29882let opNewValue = 0;
29883let DecoderNamespace = "EXT_mmvec";
29884}
29885def V6_vadduwsat_alt : HInst<
29886(outs HvxVR:$Vd32),
29887(ins HvxVR:$Vu32, HvxVR:$Vv32),
29888"$Vd32 = vadduw($Vu32,$Vv32):sat",
29889PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29890let hasNewValue = 1;
29891let opNewValue = 0;
29892let isPseudo = 1;
29893let isCodeGenOnly = 1;
29894let DecoderNamespace = "EXT_mmvec";
29895}
29896def V6_vadduwsat_dv : HInst<
29897(outs HvxWR:$Vdd32),
29898(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29899"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
29900tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
29901let Inst{7-5} = 0b010;
29902let Inst{13-13} = 0b0;
29903let Inst{31-21} = 0b00011110101;
29904let hasNewValue = 1;
29905let opNewValue = 0;
29906let DecoderNamespace = "EXT_mmvec";
29907}
29908def V6_vadduwsat_dv_alt : HInst<
29909(outs HvxWR:$Vdd32),
29910(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29911"$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
29912PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
29913let hasNewValue = 1;
29914let opNewValue = 0;
29915let isPseudo = 1;
29916let isCodeGenOnly = 1;
29917let DecoderNamespace = "EXT_mmvec";
29918}
29919def V6_vaddw : HInst<
29920(outs HvxVR:$Vd32),
29921(ins HvxVR:$Vu32, HvxVR:$Vv32),
29922"$Vd32.w = vadd($Vu32.w,$Vv32.w)",
29923tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29924let Inst{7-5} = 0b000;
29925let Inst{13-13} = 0b0;
29926let Inst{31-21} = 0b00011100010;
29927let hasNewValue = 1;
29928let opNewValue = 0;
29929let DecoderNamespace = "EXT_mmvec";
29930}
29931def V6_vaddw_alt : HInst<
29932(outs HvxVR:$Vd32),
29933(ins HvxVR:$Vu32, HvxVR:$Vv32),
29934"$Vd32 = vaddw($Vu32,$Vv32)",
29935PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29936let hasNewValue = 1;
29937let opNewValue = 0;
29938let isPseudo = 1;
29939let isCodeGenOnly = 1;
29940let DecoderNamespace = "EXT_mmvec";
29941}
29942def V6_vaddw_dv : HInst<
29943(outs HvxWR:$Vdd32),
29944(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29945"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
29946tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
29947let Inst{7-5} = 0b110;
29948let Inst{13-13} = 0b0;
29949let Inst{31-21} = 0b00011100011;
29950let hasNewValue = 1;
29951let opNewValue = 0;
29952let DecoderNamespace = "EXT_mmvec";
29953}
29954def V6_vaddw_dv_alt : HInst<
29955(outs HvxWR:$Vdd32),
29956(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
29957"$Vdd32 = vaddw($Vuu32,$Vvv32)",
29958PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29959let hasNewValue = 1;
29960let opNewValue = 0;
29961let isPseudo = 1;
29962let isCodeGenOnly = 1;
29963let DecoderNamespace = "EXT_mmvec";
29964}
29965def V6_vaddwnq : HInst<
29966(outs HvxVR:$Vx32),
29967(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29968"if (!$Qv4) $Vx32.w += $Vu32.w",
29969tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29970let Inst{7-5} = 0b101;
29971let Inst{13-13} = 0b1;
29972let Inst{21-16} = 0b000001;
29973let Inst{31-24} = 0b00011110;
29974let hasNewValue = 1;
29975let opNewValue = 0;
29976let isAccumulator = 1;
29977let DecoderNamespace = "EXT_mmvec";
29978let Constraints = "$Vx32 = $Vx32in";
29979}
29980def V6_vaddwnq_alt : HInst<
29981(outs HvxVR:$Vx32),
29982(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29983"if (!$Qv4.w) $Vx32.w += $Vu32.w",
29984PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29985let hasNewValue = 1;
29986let opNewValue = 0;
29987let isAccumulator = 1;
29988let isPseudo = 1;
29989let isCodeGenOnly = 1;
29990let DecoderNamespace = "EXT_mmvec";
29991let Constraints = "$Vx32 = $Vx32in";
29992}
29993def V6_vaddwq : HInst<
29994(outs HvxVR:$Vx32),
29995(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
29996"if ($Qv4) $Vx32.w += $Vu32.w",
29997tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
29998let Inst{7-5} = 0b010;
29999let Inst{13-13} = 0b1;
30000let Inst{21-16} = 0b000001;
30001let Inst{31-24} = 0b00011110;
30002let hasNewValue = 1;
30003let opNewValue = 0;
30004let isAccumulator = 1;
30005let DecoderNamespace = "EXT_mmvec";
30006let Constraints = "$Vx32 = $Vx32in";
30007}
30008def V6_vaddwq_alt : HInst<
30009(outs HvxVR:$Vx32),
30010(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30011"if ($Qv4.w) $Vx32.w += $Vu32.w",
30012PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30013let hasNewValue = 1;
30014let opNewValue = 0;
30015let isAccumulator = 1;
30016let isPseudo = 1;
30017let isCodeGenOnly = 1;
30018let DecoderNamespace = "EXT_mmvec";
30019let Constraints = "$Vx32 = $Vx32in";
30020}
30021def V6_vaddwsat : HInst<
30022(outs HvxVR:$Vd32),
30023(ins HvxVR:$Vu32, HvxVR:$Vv32),
30024"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
30025tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30026let Inst{7-5} = 0b100;
30027let Inst{13-13} = 0b0;
30028let Inst{31-21} = 0b00011100010;
30029let hasNewValue = 1;
30030let opNewValue = 0;
30031let DecoderNamespace = "EXT_mmvec";
30032}
30033def V6_vaddwsat_alt : HInst<
30034(outs HvxVR:$Vd32),
30035(ins HvxVR:$Vu32, HvxVR:$Vv32),
30036"$Vd32 = vaddw($Vu32,$Vv32):sat",
30037PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30038let hasNewValue = 1;
30039let opNewValue = 0;
30040let isPseudo = 1;
30041let isCodeGenOnly = 1;
30042let DecoderNamespace = "EXT_mmvec";
30043}
30044def V6_vaddwsat_dv : HInst<
30045(outs HvxWR:$Vdd32),
30046(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30047"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
30048tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30049let Inst{7-5} = 0b010;
30050let Inst{13-13} = 0b0;
30051let Inst{31-21} = 0b00011100100;
30052let hasNewValue = 1;
30053let opNewValue = 0;
30054let DecoderNamespace = "EXT_mmvec";
30055}
30056def V6_vaddwsat_dv_alt : HInst<
30057(outs HvxWR:$Vdd32),
30058(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30059"$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
30060PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30061let hasNewValue = 1;
30062let opNewValue = 0;
30063let isPseudo = 1;
30064let isCodeGenOnly = 1;
30065let DecoderNamespace = "EXT_mmvec";
30066}
30067def V6_valignb : HInst<
30068(outs HvxVR:$Vd32),
30069(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30070"$Vd32 = valign($Vu32,$Vv32,$Rt8)",
30071tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
30072let Inst{7-5} = 0b000;
30073let Inst{13-13} = 0b0;
30074let Inst{31-24} = 0b00011011;
30075let hasNewValue = 1;
30076let opNewValue = 0;
30077let DecoderNamespace = "EXT_mmvec";
30078}
30079def V6_valignbi : HInst<
30080(outs HvxVR:$Vd32),
30081(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
30082"$Vd32 = valign($Vu32,$Vv32,#$Ii)",
30083tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
30084let Inst{13-13} = 0b1;
30085let Inst{31-21} = 0b00011110001;
30086let hasNewValue = 1;
30087let opNewValue = 0;
30088let DecoderNamespace = "EXT_mmvec";
30089}
30090def V6_vand : HInst<
30091(outs HvxVR:$Vd32),
30092(ins HvxVR:$Vu32, HvxVR:$Vv32),
30093"$Vd32 = vand($Vu32,$Vv32)",
30094tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30095let Inst{7-5} = 0b101;
30096let Inst{13-13} = 0b0;
30097let Inst{31-21} = 0b00011100001;
30098let hasNewValue = 1;
30099let opNewValue = 0;
30100let DecoderNamespace = "EXT_mmvec";
30101}
30102def V6_vandnqrt : HInst<
30103(outs HvxVR:$Vd32),
30104(ins HvxQR:$Qu4, IntRegs:$Rt32),
30105"$Vd32 = vand(!$Qu4,$Rt32)",
30106tc_ac4046bc, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> {
30107let Inst{7-5} = 0b101;
30108let Inst{13-10} = 0b0001;
30109let Inst{31-21} = 0b00011001101;
30110let hasNewValue = 1;
30111let opNewValue = 0;
30112let DecoderNamespace = "EXT_mmvec";
30113}
30114def V6_vandnqrt_acc : HInst<
30115(outs HvxVR:$Vx32),
30116(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30117"$Vx32 |= vand(!$Qu4,$Rt32)",
30118tc_2e8f5f6e, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> {
30119let Inst{7-5} = 0b011;
30120let Inst{13-10} = 0b1001;
30121let Inst{31-21} = 0b00011001011;
30122let hasNewValue = 1;
30123let opNewValue = 0;
30124let isAccumulator = 1;
30125let DecoderNamespace = "EXT_mmvec";
30126let Constraints = "$Vx32 = $Vx32in";
30127}
30128def V6_vandnqrt_acc_alt : HInst<
30129(outs HvxVR:$Vx32),
30130(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30131"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
30132PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30133let hasNewValue = 1;
30134let opNewValue = 0;
30135let isAccumulator = 1;
30136let isPseudo = 1;
30137let isCodeGenOnly = 1;
30138let DecoderNamespace = "EXT_mmvec";
30139let Constraints = "$Vx32 = $Vx32in";
30140}
30141def V6_vandnqrt_alt : HInst<
30142(outs HvxVR:$Vd32),
30143(ins HvxQR:$Qu4, IntRegs:$Rt32),
30144"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
30145PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30146let hasNewValue = 1;
30147let opNewValue = 0;
30148let isPseudo = 1;
30149let isCodeGenOnly = 1;
30150let DecoderNamespace = "EXT_mmvec";
30151}
30152def V6_vandqrt : HInst<
30153(outs HvxVR:$Vd32),
30154(ins HvxQR:$Qu4, IntRegs:$Rt32),
30155"$Vd32 = vand($Qu4,$Rt32)",
30156tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
30157let Inst{7-5} = 0b101;
30158let Inst{13-10} = 0b0000;
30159let Inst{31-21} = 0b00011001101;
30160let hasNewValue = 1;
30161let opNewValue = 0;
30162let DecoderNamespace = "EXT_mmvec";
30163}
30164def V6_vandqrt_acc : HInst<
30165(outs HvxVR:$Vx32),
30166(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30167"$Vx32 |= vand($Qu4,$Rt32)",
30168tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
30169let Inst{7-5} = 0b011;
30170let Inst{13-10} = 0b1000;
30171let Inst{31-21} = 0b00011001011;
30172let hasNewValue = 1;
30173let opNewValue = 0;
30174let isAccumulator = 1;
30175let DecoderNamespace = "EXT_mmvec";
30176let Constraints = "$Vx32 = $Vx32in";
30177}
30178def V6_vandqrt_acc_alt : HInst<
30179(outs HvxVR:$Vx32),
30180(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30181"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
30182PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30183let hasNewValue = 1;
30184let opNewValue = 0;
30185let isAccumulator = 1;
30186let isPseudo = 1;
30187let isCodeGenOnly = 1;
30188let DecoderNamespace = "EXT_mmvec";
30189let Constraints = "$Vx32 = $Vx32in";
30190}
30191def V6_vandqrt_alt : HInst<
30192(outs HvxVR:$Vd32),
30193(ins HvxQR:$Qu4, IntRegs:$Rt32),
30194"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
30195PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30196let hasNewValue = 1;
30197let opNewValue = 0;
30198let isPseudo = 1;
30199let isCodeGenOnly = 1;
30200let DecoderNamespace = "EXT_mmvec";
30201}
30202def V6_vandvnqv : HInst<
30203(outs HvxVR:$Vd32),
30204(ins HvxQR:$Qv4, HvxVR:$Vu32),
30205"$Vd32 = vand(!$Qv4,$Vu32)",
30206tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
30207let Inst{7-5} = 0b001;
30208let Inst{13-13} = 0b1;
30209let Inst{21-16} = 0b000011;
30210let Inst{31-24} = 0b00011110;
30211let hasNewValue = 1;
30212let opNewValue = 0;
30213let DecoderNamespace = "EXT_mmvec";
30214}
30215def V6_vandvqv : HInst<
30216(outs HvxVR:$Vd32),
30217(ins HvxQR:$Qv4, HvxVR:$Vu32),
30218"$Vd32 = vand($Qv4,$Vu32)",
30219tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
30220let Inst{7-5} = 0b000;
30221let Inst{13-13} = 0b1;
30222let Inst{21-16} = 0b000011;
30223let Inst{31-24} = 0b00011110;
30224let hasNewValue = 1;
30225let opNewValue = 0;
30226let DecoderNamespace = "EXT_mmvec";
30227}
30228def V6_vandvrt : HInst<
30229(outs HvxQR:$Qd4),
30230(ins HvxVR:$Vu32, IntRegs:$Rt32),
30231"$Qd4 = vand($Vu32,$Rt32)",
30232tc_ac4046bc, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
30233let Inst{7-2} = 0b010010;
30234let Inst{13-13} = 0b0;
30235let Inst{31-21} = 0b00011001101;
30236let hasNewValue = 1;
30237let opNewValue = 0;
30238let DecoderNamespace = "EXT_mmvec";
30239}
30240def V6_vandvrt_acc : HInst<
30241(outs HvxQR:$Qx4),
30242(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
30243"$Qx4 |= vand($Vu32,$Rt32)",
30244tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
30245let Inst{7-2} = 0b100000;
30246let Inst{13-13} = 0b1;
30247let Inst{31-21} = 0b00011001011;
30248let isAccumulator = 1;
30249let DecoderNamespace = "EXT_mmvec";
30250let Constraints = "$Qx4 = $Qx4in";
30251}
30252def V6_vandvrt_acc_alt : HInst<
30253(outs HvxQR:$Qx4),
30254(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
30255"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
30256PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30257let isAccumulator = 1;
30258let isPseudo = 1;
30259let isCodeGenOnly = 1;
30260let DecoderNamespace = "EXT_mmvec";
30261let Constraints = "$Qx4 = $Qx4in";
30262}
30263def V6_vandvrt_alt : HInst<
30264(outs HvxQR:$Qd4),
30265(ins HvxVR:$Vu32, IntRegs:$Rt32),
30266"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
30267PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30268let hasNewValue = 1;
30269let opNewValue = 0;
30270let isPseudo = 1;
30271let isCodeGenOnly = 1;
30272let DecoderNamespace = "EXT_mmvec";
30273}
30274def V6_vaslh : HInst<
30275(outs HvxVR:$Vd32),
30276(ins HvxVR:$Vu32, IntRegs:$Rt32),
30277"$Vd32.h = vasl($Vu32.h,$Rt32)",
30278tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30279let Inst{7-5} = 0b000;
30280let Inst{13-13} = 0b0;
30281let Inst{31-21} = 0b00011001100;
30282let hasNewValue = 1;
30283let opNewValue = 0;
30284let DecoderNamespace = "EXT_mmvec";
30285}
30286def V6_vaslh_acc : HInst<
30287(outs HvxVR:$Vx32),
30288(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30289"$Vx32.h += vasl($Vu32.h,$Rt32)",
30290tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
30291let Inst{7-5} = 0b101;
30292let Inst{13-13} = 0b1;
30293let Inst{31-21} = 0b00011001101;
30294let hasNewValue = 1;
30295let opNewValue = 0;
30296let isAccumulator = 1;
30297let DecoderNamespace = "EXT_mmvec";
30298let Constraints = "$Vx32 = $Vx32in";
30299}
30300def V6_vaslh_acc_alt : HInst<
30301(outs HvxVR:$Vx32),
30302(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30303"$Vx32 += vaslh($Vu32,$Rt32)",
30304PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30305let hasNewValue = 1;
30306let opNewValue = 0;
30307let isAccumulator = 1;
30308let isPseudo = 1;
30309let isCodeGenOnly = 1;
30310let DecoderNamespace = "EXT_mmvec";
30311let Constraints = "$Vx32 = $Vx32in";
30312}
30313def V6_vaslh_alt : HInst<
30314(outs HvxVR:$Vd32),
30315(ins HvxVR:$Vu32, IntRegs:$Rt32),
30316"$Vd32 = vaslh($Vu32,$Rt32)",
30317PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30318let hasNewValue = 1;
30319let opNewValue = 0;
30320let isPseudo = 1;
30321let isCodeGenOnly = 1;
30322let DecoderNamespace = "EXT_mmvec";
30323}
30324def V6_vaslhv : HInst<
30325(outs HvxVR:$Vd32),
30326(ins HvxVR:$Vu32, HvxVR:$Vv32),
30327"$Vd32.h = vasl($Vu32.h,$Vv32.h)",
30328tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30329let Inst{7-5} = 0b101;
30330let Inst{13-13} = 0b0;
30331let Inst{31-21} = 0b00011111101;
30332let hasNewValue = 1;
30333let opNewValue = 0;
30334let DecoderNamespace = "EXT_mmvec";
30335}
30336def V6_vaslhv_alt : HInst<
30337(outs HvxVR:$Vd32),
30338(ins HvxVR:$Vu32, HvxVR:$Vv32),
30339"$Vd32 = vaslh($Vu32,$Vv32)",
30340PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30341let hasNewValue = 1;
30342let opNewValue = 0;
30343let isPseudo = 1;
30344let isCodeGenOnly = 1;
30345let DecoderNamespace = "EXT_mmvec";
30346}
30347def V6_vaslw : HInst<
30348(outs HvxVR:$Vd32),
30349(ins HvxVR:$Vu32, IntRegs:$Rt32),
30350"$Vd32.w = vasl($Vu32.w,$Rt32)",
30351tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30352let Inst{7-5} = 0b111;
30353let Inst{13-13} = 0b0;
30354let Inst{31-21} = 0b00011001011;
30355let hasNewValue = 1;
30356let opNewValue = 0;
30357let DecoderNamespace = "EXT_mmvec";
30358}
30359def V6_vaslw_acc : HInst<
30360(outs HvxVR:$Vx32),
30361(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30362"$Vx32.w += vasl($Vu32.w,$Rt32)",
30363tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
30364let Inst{7-5} = 0b010;
30365let Inst{13-13} = 0b1;
30366let Inst{31-21} = 0b00011001011;
30367let hasNewValue = 1;
30368let opNewValue = 0;
30369let isAccumulator = 1;
30370let DecoderNamespace = "EXT_mmvec";
30371let Constraints = "$Vx32 = $Vx32in";
30372}
30373def V6_vaslw_acc_alt : HInst<
30374(outs HvxVR:$Vx32),
30375(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30376"$Vx32 += vaslw($Vu32,$Rt32)",
30377PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30378let hasNewValue = 1;
30379let opNewValue = 0;
30380let isAccumulator = 1;
30381let isPseudo = 1;
30382let isCodeGenOnly = 1;
30383let DecoderNamespace = "EXT_mmvec";
30384let Constraints = "$Vx32 = $Vx32in";
30385}
30386def V6_vaslw_alt : HInst<
30387(outs HvxVR:$Vd32),
30388(ins HvxVR:$Vu32, IntRegs:$Rt32),
30389"$Vd32 = vaslw($Vu32,$Rt32)",
30390PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30391let hasNewValue = 1;
30392let opNewValue = 0;
30393let isPseudo = 1;
30394let isCodeGenOnly = 1;
30395let DecoderNamespace = "EXT_mmvec";
30396}
30397def V6_vaslwv : HInst<
30398(outs HvxVR:$Vd32),
30399(ins HvxVR:$Vu32, HvxVR:$Vv32),
30400"$Vd32.w = vasl($Vu32.w,$Vv32.w)",
30401tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30402let Inst{7-5} = 0b100;
30403let Inst{13-13} = 0b0;
30404let Inst{31-21} = 0b00011111101;
30405let hasNewValue = 1;
30406let opNewValue = 0;
30407let DecoderNamespace = "EXT_mmvec";
30408}
30409def V6_vaslwv_alt : HInst<
30410(outs HvxVR:$Vd32),
30411(ins HvxVR:$Vu32, HvxVR:$Vv32),
30412"$Vd32 = vaslw($Vu32,$Vv32)",
30413PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30414let hasNewValue = 1;
30415let opNewValue = 0;
30416let isPseudo = 1;
30417let isCodeGenOnly = 1;
30418let DecoderNamespace = "EXT_mmvec";
30419}
30420def V6_vasr_into : HInst<
30421(outs HvxWR:$Vxx32),
30422(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30423"$Vxx32.w = vasrinto($Vu32.w,$Vv32.w)",
30424tc_df80eeb0, TypeCVI_VP_VS>, Enc_3fc427, Requires<[UseHVXV66]> {
30425let Inst{7-5} = 0b111;
30426let Inst{13-13} = 0b1;
30427let Inst{31-21} = 0b00011010101;
30428let hasNewValue = 1;
30429let opNewValue = 0;
30430let DecoderNamespace = "EXT_mmvec";
30431let Constraints = "$Vxx32 = $Vxx32in";
30432}
30433def V6_vasr_into_alt : HInst<
30434(outs HvxWR:$Vxx32),
30435(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30436"$Vxx32 = vasrinto($Vu32,$Vv32)",
30437PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
30438let hasNewValue = 1;
30439let opNewValue = 0;
30440let isPseudo = 1;
30441let isCodeGenOnly = 1;
30442let DecoderNamespace = "EXT_mmvec";
30443let Constraints = "$Vxx32 = $Vxx32in";
30444}
30445def V6_vasrh : HInst<
30446(outs HvxVR:$Vd32),
30447(ins HvxVR:$Vu32, IntRegs:$Rt32),
30448"$Vd32.h = vasr($Vu32.h,$Rt32)",
30449tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30450let Inst{7-5} = 0b110;
30451let Inst{13-13} = 0b0;
30452let Inst{31-21} = 0b00011001011;
30453let hasNewValue = 1;
30454let opNewValue = 0;
30455let DecoderNamespace = "EXT_mmvec";
30456}
30457def V6_vasrh_acc : HInst<
30458(outs HvxVR:$Vx32),
30459(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30460"$Vx32.h += vasr($Vu32.h,$Rt32)",
30461tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
30462let Inst{7-5} = 0b111;
30463let Inst{13-13} = 0b1;
30464let Inst{31-21} = 0b00011001100;
30465let hasNewValue = 1;
30466let opNewValue = 0;
30467let isAccumulator = 1;
30468let DecoderNamespace = "EXT_mmvec";
30469let Constraints = "$Vx32 = $Vx32in";
30470}
30471def V6_vasrh_acc_alt : HInst<
30472(outs HvxVR:$Vx32),
30473(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30474"$Vx32 += vasrh($Vu32,$Rt32)",
30475PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30476let hasNewValue = 1;
30477let opNewValue = 0;
30478let isAccumulator = 1;
30479let isPseudo = 1;
30480let isCodeGenOnly = 1;
30481let DecoderNamespace = "EXT_mmvec";
30482let Constraints = "$Vx32 = $Vx32in";
30483}
30484def V6_vasrh_alt : HInst<
30485(outs HvxVR:$Vd32),
30486(ins HvxVR:$Vu32, IntRegs:$Rt32),
30487"$Vd32 = vasrh($Vu32,$Rt32)",
30488PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30489let hasNewValue = 1;
30490let opNewValue = 0;
30491let isPseudo = 1;
30492let isCodeGenOnly = 1;
30493let DecoderNamespace = "EXT_mmvec";
30494}
30495def V6_vasrhbrndsat : HInst<
30496(outs HvxVR:$Vd32),
30497(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30498"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
30499tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30500let Inst{7-5} = 0b000;
30501let Inst{13-13} = 0b1;
30502let Inst{31-24} = 0b00011011;
30503let hasNewValue = 1;
30504let opNewValue = 0;
30505let DecoderNamespace = "EXT_mmvec";
30506}
30507def V6_vasrhbrndsat_alt : HInst<
30508(outs HvxVR:$Vd32),
30509(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30510"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat",
30511tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> {
30512let hasNewValue = 1;
30513let opNewValue = 0;
30514let isPseudo = 1;
30515let isCodeGenOnly = 1;
30516}
30517def V6_vasrhbsat : HInst<
30518(outs HvxVR:$Vd32),
30519(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30520"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
30521tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
30522let Inst{7-5} = 0b000;
30523let Inst{13-13} = 0b0;
30524let Inst{31-24} = 0b00011000;
30525let hasNewValue = 1;
30526let opNewValue = 0;
30527let DecoderNamespace = "EXT_mmvec";
30528}
30529def V6_vasrhubrndsat : HInst<
30530(outs HvxVR:$Vd32),
30531(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30532"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
30533tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30534let Inst{7-5} = 0b111;
30535let Inst{13-13} = 0b0;
30536let Inst{31-24} = 0b00011011;
30537let hasNewValue = 1;
30538let opNewValue = 0;
30539let DecoderNamespace = "EXT_mmvec";
30540}
30541def V6_vasrhubrndsat_alt : HInst<
30542(outs HvxVR:$Vd32),
30543(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30544"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat",
30545tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> {
30546let hasNewValue = 1;
30547let opNewValue = 0;
30548let isPseudo = 1;
30549let isCodeGenOnly = 1;
30550}
30551def V6_vasrhubsat : HInst<
30552(outs HvxVR:$Vd32),
30553(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30554"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
30555tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30556let Inst{7-5} = 0b110;
30557let Inst{13-13} = 0b0;
30558let Inst{31-24} = 0b00011011;
30559let hasNewValue = 1;
30560let opNewValue = 0;
30561let DecoderNamespace = "EXT_mmvec";
30562}
30563def V6_vasrhubsat_alt : HInst<
30564(outs HvxVR:$Vd32),
30565(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30566"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat",
30567tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> {
30568let hasNewValue = 1;
30569let opNewValue = 0;
30570let isPseudo = 1;
30571let isCodeGenOnly = 1;
30572}
30573def V6_vasrhv : HInst<
30574(outs HvxVR:$Vd32),
30575(ins HvxVR:$Vu32, HvxVR:$Vv32),
30576"$Vd32.h = vasr($Vu32.h,$Vv32.h)",
30577tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30578let Inst{7-5} = 0b011;
30579let Inst{13-13} = 0b0;
30580let Inst{31-21} = 0b00011111101;
30581let hasNewValue = 1;
30582let opNewValue = 0;
30583let DecoderNamespace = "EXT_mmvec";
30584}
30585def V6_vasrhv_alt : HInst<
30586(outs HvxVR:$Vd32),
30587(ins HvxVR:$Vu32, HvxVR:$Vv32),
30588"$Vd32 = vasrh($Vu32,$Vv32)",
30589PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30590let hasNewValue = 1;
30591let opNewValue = 0;
30592let isPseudo = 1;
30593let isCodeGenOnly = 1;
30594let DecoderNamespace = "EXT_mmvec";
30595}
30596def V6_vasruhubrndsat : HInst<
30597(outs HvxVR:$Vd32),
30598(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30599"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
30600tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
30601let Inst{7-5} = 0b111;
30602let Inst{13-13} = 0b0;
30603let Inst{31-24} = 0b00011000;
30604let hasNewValue = 1;
30605let opNewValue = 0;
30606let DecoderNamespace = "EXT_mmvec";
30607}
30608def V6_vasruhubsat : HInst<
30609(outs HvxVR:$Vd32),
30610(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30611"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
30612tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
30613let Inst{7-5} = 0b101;
30614let Inst{13-13} = 0b1;
30615let Inst{31-24} = 0b00011000;
30616let hasNewValue = 1;
30617let opNewValue = 0;
30618let DecoderNamespace = "EXT_mmvec";
30619}
30620def V6_vasruwuhrndsat : HInst<
30621(outs HvxVR:$Vd32),
30622(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30623"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
30624tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
30625let Inst{7-5} = 0b001;
30626let Inst{13-13} = 0b0;
30627let Inst{31-24} = 0b00011000;
30628let hasNewValue = 1;
30629let opNewValue = 0;
30630let DecoderNamespace = "EXT_mmvec";
30631}
30632def V6_vasruwuhsat : HInst<
30633(outs HvxVR:$Vd32),
30634(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30635"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
30636tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
30637let Inst{7-5} = 0b100;
30638let Inst{13-13} = 0b1;
30639let Inst{31-24} = 0b00011000;
30640let hasNewValue = 1;
30641let opNewValue = 0;
30642let DecoderNamespace = "EXT_mmvec";
30643}
30644def V6_vasrw : HInst<
30645(outs HvxVR:$Vd32),
30646(ins HvxVR:$Vu32, IntRegs:$Rt32),
30647"$Vd32.w = vasr($Vu32.w,$Rt32)",
30648tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
30649let Inst{7-5} = 0b101;
30650let Inst{13-13} = 0b0;
30651let Inst{31-21} = 0b00011001011;
30652let hasNewValue = 1;
30653let opNewValue = 0;
30654let DecoderNamespace = "EXT_mmvec";
30655}
30656def V6_vasrw_acc : HInst<
30657(outs HvxVR:$Vx32),
30658(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30659"$Vx32.w += vasr($Vu32.w,$Rt32)",
30660tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
30661let Inst{7-5} = 0b101;
30662let Inst{13-13} = 0b1;
30663let Inst{31-21} = 0b00011001011;
30664let hasNewValue = 1;
30665let opNewValue = 0;
30666let isAccumulator = 1;
30667let DecoderNamespace = "EXT_mmvec";
30668let Constraints = "$Vx32 = $Vx32in";
30669}
30670def V6_vasrw_acc_alt : HInst<
30671(outs HvxVR:$Vx32),
30672(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
30673"$Vx32 += vasrw($Vu32,$Rt32)",
30674PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30675let hasNewValue = 1;
30676let opNewValue = 0;
30677let isAccumulator = 1;
30678let isPseudo = 1;
30679let isCodeGenOnly = 1;
30680let DecoderNamespace = "EXT_mmvec";
30681let Constraints = "$Vx32 = $Vx32in";
30682}
30683def V6_vasrw_alt : HInst<
30684(outs HvxVR:$Vd32),
30685(ins HvxVR:$Vu32, IntRegs:$Rt32),
30686"$Vd32 = vasrw($Vu32,$Rt32)",
30687PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30688let hasNewValue = 1;
30689let opNewValue = 0;
30690let isPseudo = 1;
30691let isCodeGenOnly = 1;
30692let DecoderNamespace = "EXT_mmvec";
30693}
30694def V6_vasrwh : HInst<
30695(outs HvxVR:$Vd32),
30696(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30697"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
30698tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30699let Inst{7-5} = 0b010;
30700let Inst{13-13} = 0b0;
30701let Inst{31-24} = 0b00011011;
30702let hasNewValue = 1;
30703let opNewValue = 0;
30704let DecoderNamespace = "EXT_mmvec";
30705}
30706def V6_vasrwh_alt : HInst<
30707(outs HvxVR:$Vd32),
30708(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30709"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)",
30710tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> {
30711let hasNewValue = 1;
30712let opNewValue = 0;
30713let isPseudo = 1;
30714let isCodeGenOnly = 1;
30715}
30716def V6_vasrwhrndsat : HInst<
30717(outs HvxVR:$Vd32),
30718(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30719"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
30720tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30721let Inst{7-5} = 0b100;
30722let Inst{13-13} = 0b0;
30723let Inst{31-24} = 0b00011011;
30724let hasNewValue = 1;
30725let opNewValue = 0;
30726let DecoderNamespace = "EXT_mmvec";
30727}
30728def V6_vasrwhrndsat_alt : HInst<
30729(outs HvxVR:$Vd32),
30730(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30731"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat",
30732tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> {
30733let hasNewValue = 1;
30734let opNewValue = 0;
30735let isPseudo = 1;
30736let isCodeGenOnly = 1;
30737}
30738def V6_vasrwhsat : HInst<
30739(outs HvxVR:$Vd32),
30740(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30741"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
30742tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30743let Inst{7-5} = 0b011;
30744let Inst{13-13} = 0b0;
30745let Inst{31-24} = 0b00011011;
30746let hasNewValue = 1;
30747let opNewValue = 0;
30748let DecoderNamespace = "EXT_mmvec";
30749}
30750def V6_vasrwhsat_alt : HInst<
30751(outs HvxVR:$Vd32),
30752(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30753"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat",
30754tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> {
30755let hasNewValue = 1;
30756let opNewValue = 0;
30757let isPseudo = 1;
30758let isCodeGenOnly = 1;
30759}
30760def V6_vasrwuhrndsat : HInst<
30761(outs HvxVR:$Vd32),
30762(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30763"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
30764tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
30765let Inst{7-5} = 0b010;
30766let Inst{13-13} = 0b0;
30767let Inst{31-24} = 0b00011000;
30768let hasNewValue = 1;
30769let opNewValue = 0;
30770let DecoderNamespace = "EXT_mmvec";
30771}
30772def V6_vasrwuhsat : HInst<
30773(outs HvxVR:$Vd32),
30774(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30775"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
30776tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
30777let Inst{7-5} = 0b101;
30778let Inst{13-13} = 0b0;
30779let Inst{31-24} = 0b00011011;
30780let hasNewValue = 1;
30781let opNewValue = 0;
30782let DecoderNamespace = "EXT_mmvec";
30783}
30784def V6_vasrwuhsat_alt : HInst<
30785(outs HvxVR:$Vd32),
30786(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30787"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat",
30788tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> {
30789let hasNewValue = 1;
30790let opNewValue = 0;
30791let isPseudo = 1;
30792let isCodeGenOnly = 1;
30793}
30794def V6_vasrwv : HInst<
30795(outs HvxVR:$Vd32),
30796(ins HvxVR:$Vu32, HvxVR:$Vv32),
30797"$Vd32.w = vasr($Vu32.w,$Vv32.w)",
30798tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
30799let Inst{7-5} = 0b000;
30800let Inst{13-13} = 0b0;
30801let Inst{31-21} = 0b00011111101;
30802let hasNewValue = 1;
30803let opNewValue = 0;
30804let DecoderNamespace = "EXT_mmvec";
30805}
30806def V6_vasrwv_alt : HInst<
30807(outs HvxVR:$Vd32),
30808(ins HvxVR:$Vu32, HvxVR:$Vv32),
30809"$Vd32 = vasrw($Vu32,$Vv32)",
30810PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30811let hasNewValue = 1;
30812let opNewValue = 0;
30813let isPseudo = 1;
30814let isCodeGenOnly = 1;
30815let DecoderNamespace = "EXT_mmvec";
30816}
30817def V6_vassign : HInst<
30818(outs HvxVR:$Vd32),
30819(ins HvxVR:$Vu32),
30820"$Vd32 = $Vu32",
30821tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30822let Inst{7-5} = 0b111;
30823let Inst{13-13} = 0b1;
30824let Inst{31-16} = 0b0001111000000011;
30825let hasNewValue = 1;
30826let opNewValue = 0;
30827let DecoderNamespace = "EXT_mmvec";
30828}
30829def V6_vassignp : HInst<
30830(outs HvxWR:$Vdd32),
30831(ins HvxWR:$Vuu32),
30832"$Vdd32 = $Vuu32",
30833CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
30834let hasNewValue = 1;
30835let opNewValue = 0;
30836let isPseudo = 1;
30837let DecoderNamespace = "EXT_mmvec";
30838}
30839def V6_vavgb : HInst<
30840(outs HvxVR:$Vd32),
30841(ins HvxVR:$Vu32, HvxVR:$Vv32),
30842"$Vd32.b = vavg($Vu32.b,$Vv32.b)",
30843tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
30844let Inst{7-5} = 0b100;
30845let Inst{13-13} = 0b1;
30846let Inst{31-21} = 0b00011111000;
30847let hasNewValue = 1;
30848let opNewValue = 0;
30849let DecoderNamespace = "EXT_mmvec";
30850}
30851def V6_vavgb_alt : HInst<
30852(outs HvxVR:$Vd32),
30853(ins HvxVR:$Vu32, HvxVR:$Vv32),
30854"$Vd32 = vavgb($Vu32,$Vv32)",
30855PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30856let hasNewValue = 1;
30857let opNewValue = 0;
30858let isPseudo = 1;
30859let isCodeGenOnly = 1;
30860let DecoderNamespace = "EXT_mmvec";
30861}
30862def V6_vavgbrnd : HInst<
30863(outs HvxVR:$Vd32),
30864(ins HvxVR:$Vu32, HvxVR:$Vv32),
30865"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
30866tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
30867let Inst{7-5} = 0b101;
30868let Inst{13-13} = 0b1;
30869let Inst{31-21} = 0b00011111000;
30870let hasNewValue = 1;
30871let opNewValue = 0;
30872let DecoderNamespace = "EXT_mmvec";
30873}
30874def V6_vavgbrnd_alt : HInst<
30875(outs HvxVR:$Vd32),
30876(ins HvxVR:$Vu32, HvxVR:$Vv32),
30877"$Vd32 = vavgb($Vu32,$Vv32):rnd",
30878PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
30879let hasNewValue = 1;
30880let opNewValue = 0;
30881let isPseudo = 1;
30882let isCodeGenOnly = 1;
30883let DecoderNamespace = "EXT_mmvec";
30884}
30885def V6_vavgh : HInst<
30886(outs HvxVR:$Vd32),
30887(ins HvxVR:$Vu32, HvxVR:$Vv32),
30888"$Vd32.h = vavg($Vu32.h,$Vv32.h)",
30889tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30890let Inst{7-5} = 0b110;
30891let Inst{13-13} = 0b0;
30892let Inst{31-21} = 0b00011100110;
30893let hasNewValue = 1;
30894let opNewValue = 0;
30895let DecoderNamespace = "EXT_mmvec";
30896}
30897def V6_vavgh_alt : HInst<
30898(outs HvxVR:$Vd32),
30899(ins HvxVR:$Vu32, HvxVR:$Vv32),
30900"$Vd32 = vavgh($Vu32,$Vv32)",
30901PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30902let hasNewValue = 1;
30903let opNewValue = 0;
30904let isPseudo = 1;
30905let isCodeGenOnly = 1;
30906let DecoderNamespace = "EXT_mmvec";
30907}
30908def V6_vavghrnd : HInst<
30909(outs HvxVR:$Vd32),
30910(ins HvxVR:$Vu32, HvxVR:$Vv32),
30911"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
30912tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30913let Inst{7-5} = 0b101;
30914let Inst{13-13} = 0b0;
30915let Inst{31-21} = 0b00011100111;
30916let hasNewValue = 1;
30917let opNewValue = 0;
30918let DecoderNamespace = "EXT_mmvec";
30919}
30920def V6_vavghrnd_alt : HInst<
30921(outs HvxVR:$Vd32),
30922(ins HvxVR:$Vu32, HvxVR:$Vv32),
30923"$Vd32 = vavgh($Vu32,$Vv32):rnd",
30924PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30925let hasNewValue = 1;
30926let opNewValue = 0;
30927let isPseudo = 1;
30928let isCodeGenOnly = 1;
30929let DecoderNamespace = "EXT_mmvec";
30930}
30931def V6_vavgub : HInst<
30932(outs HvxVR:$Vd32),
30933(ins HvxVR:$Vu32, HvxVR:$Vv32),
30934"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
30935tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30936let Inst{7-5} = 0b100;
30937let Inst{13-13} = 0b0;
30938let Inst{31-21} = 0b00011100110;
30939let hasNewValue = 1;
30940let opNewValue = 0;
30941let DecoderNamespace = "EXT_mmvec";
30942}
30943def V6_vavgub_alt : HInst<
30944(outs HvxVR:$Vd32),
30945(ins HvxVR:$Vu32, HvxVR:$Vv32),
30946"$Vd32 = vavgub($Vu32,$Vv32)",
30947PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30948let hasNewValue = 1;
30949let opNewValue = 0;
30950let isPseudo = 1;
30951let isCodeGenOnly = 1;
30952let DecoderNamespace = "EXT_mmvec";
30953}
30954def V6_vavgubrnd : HInst<
30955(outs HvxVR:$Vd32),
30956(ins HvxVR:$Vu32, HvxVR:$Vv32),
30957"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
30958tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30959let Inst{7-5} = 0b011;
30960let Inst{13-13} = 0b0;
30961let Inst{31-21} = 0b00011100111;
30962let hasNewValue = 1;
30963let opNewValue = 0;
30964let DecoderNamespace = "EXT_mmvec";
30965}
30966def V6_vavgubrnd_alt : HInst<
30967(outs HvxVR:$Vd32),
30968(ins HvxVR:$Vu32, HvxVR:$Vv32),
30969"$Vd32 = vavgub($Vu32,$Vv32):rnd",
30970PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30971let hasNewValue = 1;
30972let opNewValue = 0;
30973let isPseudo = 1;
30974let isCodeGenOnly = 1;
30975let DecoderNamespace = "EXT_mmvec";
30976}
30977def V6_vavguh : HInst<
30978(outs HvxVR:$Vd32),
30979(ins HvxVR:$Vu32, HvxVR:$Vv32),
30980"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
30981tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30982let Inst{7-5} = 0b101;
30983let Inst{13-13} = 0b0;
30984let Inst{31-21} = 0b00011100110;
30985let hasNewValue = 1;
30986let opNewValue = 0;
30987let DecoderNamespace = "EXT_mmvec";
30988}
30989def V6_vavguh_alt : HInst<
30990(outs HvxVR:$Vd32),
30991(ins HvxVR:$Vu32, HvxVR:$Vv32),
30992"$Vd32 = vavguh($Vu32,$Vv32)",
30993PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30994let hasNewValue = 1;
30995let opNewValue = 0;
30996let isPseudo = 1;
30997let isCodeGenOnly = 1;
30998let DecoderNamespace = "EXT_mmvec";
30999}
31000def V6_vavguhrnd : HInst<
31001(outs HvxVR:$Vd32),
31002(ins HvxVR:$Vu32, HvxVR:$Vv32),
31003"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
31004tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31005let Inst{7-5} = 0b100;
31006let Inst{13-13} = 0b0;
31007let Inst{31-21} = 0b00011100111;
31008let hasNewValue = 1;
31009let opNewValue = 0;
31010let DecoderNamespace = "EXT_mmvec";
31011}
31012def V6_vavguhrnd_alt : HInst<
31013(outs HvxVR:$Vd32),
31014(ins HvxVR:$Vu32, HvxVR:$Vv32),
31015"$Vd32 = vavguh($Vu32,$Vv32):rnd",
31016PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31017let hasNewValue = 1;
31018let opNewValue = 0;
31019let isPseudo = 1;
31020let isCodeGenOnly = 1;
31021let DecoderNamespace = "EXT_mmvec";
31022}
31023def V6_vavguw : HInst<
31024(outs HvxVR:$Vd32),
31025(ins HvxVR:$Vu32, HvxVR:$Vv32),
31026"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
31027tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31028let Inst{7-5} = 0b010;
31029let Inst{13-13} = 0b1;
31030let Inst{31-21} = 0b00011111000;
31031let hasNewValue = 1;
31032let opNewValue = 0;
31033let DecoderNamespace = "EXT_mmvec";
31034}
31035def V6_vavguw_alt : HInst<
31036(outs HvxVR:$Vd32),
31037(ins HvxVR:$Vu32, HvxVR:$Vv32),
31038"$Vd32 = vavguw($Vu32,$Vv32)",
31039PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31040let hasNewValue = 1;
31041let opNewValue = 0;
31042let isPseudo = 1;
31043let isCodeGenOnly = 1;
31044let DecoderNamespace = "EXT_mmvec";
31045}
31046def V6_vavguwrnd : HInst<
31047(outs HvxVR:$Vd32),
31048(ins HvxVR:$Vu32, HvxVR:$Vv32),
31049"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
31050tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31051let Inst{7-5} = 0b011;
31052let Inst{13-13} = 0b1;
31053let Inst{31-21} = 0b00011111000;
31054let hasNewValue = 1;
31055let opNewValue = 0;
31056let DecoderNamespace = "EXT_mmvec";
31057}
31058def V6_vavguwrnd_alt : HInst<
31059(outs HvxVR:$Vd32),
31060(ins HvxVR:$Vu32, HvxVR:$Vv32),
31061"$Vd32 = vavguw($Vu32,$Vv32):rnd",
31062PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31063let hasNewValue = 1;
31064let opNewValue = 0;
31065let isPseudo = 1;
31066let isCodeGenOnly = 1;
31067let DecoderNamespace = "EXT_mmvec";
31068}
31069def V6_vavgw : HInst<
31070(outs HvxVR:$Vd32),
31071(ins HvxVR:$Vu32, HvxVR:$Vv32),
31072"$Vd32.w = vavg($Vu32.w,$Vv32.w)",
31073tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31074let Inst{7-5} = 0b111;
31075let Inst{13-13} = 0b0;
31076let Inst{31-21} = 0b00011100110;
31077let hasNewValue = 1;
31078let opNewValue = 0;
31079let DecoderNamespace = "EXT_mmvec";
31080}
31081def V6_vavgw_alt : HInst<
31082(outs HvxVR:$Vd32),
31083(ins HvxVR:$Vu32, HvxVR:$Vv32),
31084"$Vd32 = vavgw($Vu32,$Vv32)",
31085PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31086let hasNewValue = 1;
31087let opNewValue = 0;
31088let isPseudo = 1;
31089let isCodeGenOnly = 1;
31090let DecoderNamespace = "EXT_mmvec";
31091}
31092def V6_vavgwrnd : HInst<
31093(outs HvxVR:$Vd32),
31094(ins HvxVR:$Vu32, HvxVR:$Vv32),
31095"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
31096tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31097let Inst{7-5} = 0b110;
31098let Inst{13-13} = 0b0;
31099let Inst{31-21} = 0b00011100111;
31100let hasNewValue = 1;
31101let opNewValue = 0;
31102let DecoderNamespace = "EXT_mmvec";
31103}
31104def V6_vavgwrnd_alt : HInst<
31105(outs HvxVR:$Vd32),
31106(ins HvxVR:$Vu32, HvxVR:$Vv32),
31107"$Vd32 = vavgw($Vu32,$Vv32):rnd",
31108PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31109let hasNewValue = 1;
31110let opNewValue = 0;
31111let isPseudo = 1;
31112let isCodeGenOnly = 1;
31113let DecoderNamespace = "EXT_mmvec";
31114}
31115def V6_vccombine : HInst<
31116(outs HvxWR:$Vdd32),
31117(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
31118"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
31119tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
31120let Inst{7-7} = 0b0;
31121let Inst{13-13} = 0b0;
31122let Inst{31-21} = 0b00011010011;
31123let isPredicated = 1;
31124let hasNewValue = 1;
31125let opNewValue = 0;
31126let DecoderNamespace = "EXT_mmvec";
31127}
31128def V6_vcl0h : HInst<
31129(outs HvxVR:$Vd32),
31130(ins HvxVR:$Vu32),
31131"$Vd32.uh = vcl0($Vu32.uh)",
31132tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
31133let Inst{7-5} = 0b111;
31134let Inst{13-13} = 0b0;
31135let Inst{31-16} = 0b0001111000000010;
31136let hasNewValue = 1;
31137let opNewValue = 0;
31138let DecoderNamespace = "EXT_mmvec";
31139}
31140def V6_vcl0h_alt : HInst<
31141(outs HvxVR:$Vd32),
31142(ins HvxVR:$Vu32),
31143"$Vd32 = vcl0h($Vu32)",
31144PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31145let hasNewValue = 1;
31146let opNewValue = 0;
31147let isPseudo = 1;
31148let isCodeGenOnly = 1;
31149let DecoderNamespace = "EXT_mmvec";
31150}
31151def V6_vcl0w : HInst<
31152(outs HvxVR:$Vd32),
31153(ins HvxVR:$Vu32),
31154"$Vd32.uw = vcl0($Vu32.uw)",
31155tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
31156let Inst{7-5} = 0b101;
31157let Inst{13-13} = 0b0;
31158let Inst{31-16} = 0b0001111000000010;
31159let hasNewValue = 1;
31160let opNewValue = 0;
31161let DecoderNamespace = "EXT_mmvec";
31162}
31163def V6_vcl0w_alt : HInst<
31164(outs HvxVR:$Vd32),
31165(ins HvxVR:$Vu32),
31166"$Vd32 = vcl0w($Vu32)",
31167PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31168let hasNewValue = 1;
31169let opNewValue = 0;
31170let isPseudo = 1;
31171let isCodeGenOnly = 1;
31172let DecoderNamespace = "EXT_mmvec";
31173}
31174def V6_vcmov : HInst<
31175(outs HvxVR:$Vd32),
31176(ins PredRegs:$Ps4, HvxVR:$Vu32),
31177"if ($Ps4) $Vd32 = $Vu32",
31178tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
31179let Inst{7-7} = 0b0;
31180let Inst{13-13} = 0b0;
31181let Inst{31-16} = 0b0001101000000000;
31182let isPredicated = 1;
31183let hasNewValue = 1;
31184let opNewValue = 0;
31185let DecoderNamespace = "EXT_mmvec";
31186}
31187def V6_vcombine : HInst<
31188(outs HvxWR:$Vdd32),
31189(ins HvxVR:$Vu32, HvxVR:$Vv32),
31190"$Vdd32 = vcombine($Vu32,$Vv32)",
31191tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
31192let Inst{7-5} = 0b111;
31193let Inst{13-13} = 0b0;
31194let Inst{31-21} = 0b00011111010;
31195let hasNewValue = 1;
31196let opNewValue = 0;
31197let isRegSequence = 1;
31198let DecoderNamespace = "EXT_mmvec";
31199}
31200def V6_vd0 : HInst<
31201(outs HvxVR:$Vd32),
31202(ins),
31203"$Vd32 = #0",
31204CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
31205let hasNewValue = 1;
31206let opNewValue = 0;
31207let isPseudo = 1;
31208let isCodeGenOnly = 1;
31209let DecoderNamespace = "EXT_mmvec";
31210}
31211def V6_vdd0 : HInst<
31212(outs HvxWR:$Vdd32),
31213(ins),
31214"$Vdd32 = #0",
31215tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> {
31216let hasNewValue = 1;
31217let opNewValue = 0;
31218let isPseudo = 1;
31219let isCodeGenOnly = 1;
31220let DecoderNamespace = "EXT_mmvec";
31221}
31222def V6_vdeal : HInst<
31223(outs HvxVR:$Vy32, HvxVR:$Vx32),
31224(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
31225"vdeal($Vy32,$Vx32,$Rt32)",
31226tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
31227let Inst{7-5} = 0b010;
31228let Inst{13-13} = 0b1;
31229let Inst{31-21} = 0b00011001111;
31230let hasNewValue = 1;
31231let opNewValue = 0;
31232let hasNewValue2 = 1;
31233let opNewValue2 = 1;
31234let DecoderNamespace = "EXT_mmvec";
31235let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
31236}
31237def V6_vdealb : HInst<
31238(outs HvxVR:$Vd32),
31239(ins HvxVR:$Vu32),
31240"$Vd32.b = vdeal($Vu32.b)",
31241tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
31242let Inst{7-5} = 0b111;
31243let Inst{13-13} = 0b0;
31244let Inst{31-16} = 0b0001111000000000;
31245let hasNewValue = 1;
31246let opNewValue = 0;
31247let DecoderNamespace = "EXT_mmvec";
31248}
31249def V6_vdealb4w : HInst<
31250(outs HvxVR:$Vd32),
31251(ins HvxVR:$Vu32, HvxVR:$Vv32),
31252"$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
31253tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
31254let Inst{7-5} = 0b111;
31255let Inst{13-13} = 0b0;
31256let Inst{31-21} = 0b00011111001;
31257let hasNewValue = 1;
31258let opNewValue = 0;
31259let DecoderNamespace = "EXT_mmvec";
31260}
31261def V6_vdealb4w_alt : HInst<
31262(outs HvxVR:$Vd32),
31263(ins HvxVR:$Vu32, HvxVR:$Vv32),
31264"$Vd32 = vdealb4w($Vu32,$Vv32)",
31265PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31266let hasNewValue = 1;
31267let opNewValue = 0;
31268let isPseudo = 1;
31269let isCodeGenOnly = 1;
31270let DecoderNamespace = "EXT_mmvec";
31271}
31272def V6_vdealb_alt : HInst<
31273(outs HvxVR:$Vd32),
31274(ins HvxVR:$Vu32),
31275"$Vd32 = vdealb($Vu32)",
31276PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31277let hasNewValue = 1;
31278let opNewValue = 0;
31279let isPseudo = 1;
31280let isCodeGenOnly = 1;
31281let DecoderNamespace = "EXT_mmvec";
31282}
31283def V6_vdealh : HInst<
31284(outs HvxVR:$Vd32),
31285(ins HvxVR:$Vu32),
31286"$Vd32.h = vdeal($Vu32.h)",
31287tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
31288let Inst{7-5} = 0b110;
31289let Inst{13-13} = 0b0;
31290let Inst{31-16} = 0b0001111000000000;
31291let hasNewValue = 1;
31292let opNewValue = 0;
31293let DecoderNamespace = "EXT_mmvec";
31294}
31295def V6_vdealh_alt : HInst<
31296(outs HvxVR:$Vd32),
31297(ins HvxVR:$Vu32),
31298"$Vd32 = vdealh($Vu32)",
31299PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31300let hasNewValue = 1;
31301let opNewValue = 0;
31302let isPseudo = 1;
31303let isCodeGenOnly = 1;
31304let DecoderNamespace = "EXT_mmvec";
31305}
31306def V6_vdealvdd : HInst<
31307(outs HvxWR:$Vdd32),
31308(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31309"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
31310tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
31311let Inst{7-5} = 0b100;
31312let Inst{13-13} = 0b1;
31313let Inst{31-24} = 0b00011011;
31314let hasNewValue = 1;
31315let opNewValue = 0;
31316let DecoderNamespace = "EXT_mmvec";
31317}
31318def V6_vdelta : HInst<
31319(outs HvxVR:$Vd32),
31320(ins HvxVR:$Vu32, HvxVR:$Vv32),
31321"$Vd32 = vdelta($Vu32,$Vv32)",
31322tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
31323let Inst{7-5} = 0b001;
31324let Inst{13-13} = 0b0;
31325let Inst{31-21} = 0b00011111001;
31326let hasNewValue = 1;
31327let opNewValue = 0;
31328let DecoderNamespace = "EXT_mmvec";
31329}
31330def V6_vdmpybus : HInst<
31331(outs HvxVR:$Vd32),
31332(ins HvxVR:$Vu32, IntRegs:$Rt32),
31333"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
31334tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
31335let Inst{7-5} = 0b110;
31336let Inst{13-13} = 0b0;
31337let Inst{31-21} = 0b00011001000;
31338let hasNewValue = 1;
31339let opNewValue = 0;
31340let DecoderNamespace = "EXT_mmvec";
31341}
31342def V6_vdmpybus_acc : HInst<
31343(outs HvxVR:$Vx32),
31344(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31345"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
31346tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
31347let Inst{7-5} = 0b110;
31348let Inst{13-13} = 0b1;
31349let Inst{31-21} = 0b00011001000;
31350let hasNewValue = 1;
31351let opNewValue = 0;
31352let isAccumulator = 1;
31353let DecoderNamespace = "EXT_mmvec";
31354let Constraints = "$Vx32 = $Vx32in";
31355}
31356def V6_vdmpybus_acc_alt : HInst<
31357(outs HvxVR:$Vx32),
31358(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31359"$Vx32 += vdmpybus($Vu32,$Rt32)",
31360PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31361let hasNewValue = 1;
31362let opNewValue = 0;
31363let isAccumulator = 1;
31364let isPseudo = 1;
31365let isCodeGenOnly = 1;
31366let DecoderNamespace = "EXT_mmvec";
31367let Constraints = "$Vx32 = $Vx32in";
31368}
31369def V6_vdmpybus_alt : HInst<
31370(outs HvxVR:$Vd32),
31371(ins HvxVR:$Vu32, IntRegs:$Rt32),
31372"$Vd32 = vdmpybus($Vu32,$Rt32)",
31373PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31374let hasNewValue = 1;
31375let opNewValue = 0;
31376let isPseudo = 1;
31377let isCodeGenOnly = 1;
31378let DecoderNamespace = "EXT_mmvec";
31379}
31380def V6_vdmpybus_dv : HInst<
31381(outs HvxWR:$Vdd32),
31382(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31383"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
31384tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
31385let Inst{7-5} = 0b111;
31386let Inst{13-13} = 0b0;
31387let Inst{31-21} = 0b00011001000;
31388let hasNewValue = 1;
31389let opNewValue = 0;
31390let DecoderNamespace = "EXT_mmvec";
31391}
31392def V6_vdmpybus_dv_acc : HInst<
31393(outs HvxWR:$Vxx32),
31394(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31395"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
31396tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
31397let Inst{7-5} = 0b111;
31398let Inst{13-13} = 0b1;
31399let Inst{31-21} = 0b00011001000;
31400let hasNewValue = 1;
31401let opNewValue = 0;
31402let isAccumulator = 1;
31403let DecoderNamespace = "EXT_mmvec";
31404let Constraints = "$Vxx32 = $Vxx32in";
31405}
31406def V6_vdmpybus_dv_acc_alt : HInst<
31407(outs HvxWR:$Vxx32),
31408(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31409"$Vxx32 += vdmpybus($Vuu32,$Rt32)",
31410PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31411let hasNewValue = 1;
31412let opNewValue = 0;
31413let isAccumulator = 1;
31414let isPseudo = 1;
31415let isCodeGenOnly = 1;
31416let DecoderNamespace = "EXT_mmvec";
31417let Constraints = "$Vxx32 = $Vxx32in";
31418}
31419def V6_vdmpybus_dv_alt : HInst<
31420(outs HvxWR:$Vdd32),
31421(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31422"$Vdd32 = vdmpybus($Vuu32,$Rt32)",
31423PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31424let hasNewValue = 1;
31425let opNewValue = 0;
31426let isPseudo = 1;
31427let isCodeGenOnly = 1;
31428let DecoderNamespace = "EXT_mmvec";
31429}
31430def V6_vdmpyhb : HInst<
31431(outs HvxVR:$Vd32),
31432(ins HvxVR:$Vu32, IntRegs:$Rt32),
31433"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
31434tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
31435let Inst{7-5} = 0b010;
31436let Inst{13-13} = 0b0;
31437let Inst{31-21} = 0b00011001000;
31438let hasNewValue = 1;
31439let opNewValue = 0;
31440let DecoderNamespace = "EXT_mmvec";
31441}
31442def V6_vdmpyhb_acc : HInst<
31443(outs HvxVR:$Vx32),
31444(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31445"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
31446tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
31447let Inst{7-5} = 0b011;
31448let Inst{13-13} = 0b1;
31449let Inst{31-21} = 0b00011001000;
31450let hasNewValue = 1;
31451let opNewValue = 0;
31452let isAccumulator = 1;
31453let DecoderNamespace = "EXT_mmvec";
31454let Constraints = "$Vx32 = $Vx32in";
31455}
31456def V6_vdmpyhb_acc_alt : HInst<
31457(outs HvxVR:$Vx32),
31458(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31459"$Vx32 += vdmpyhb($Vu32,$Rt32)",
31460PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31461let hasNewValue = 1;
31462let opNewValue = 0;
31463let isAccumulator = 1;
31464let isPseudo = 1;
31465let isCodeGenOnly = 1;
31466let DecoderNamespace = "EXT_mmvec";
31467let Constraints = "$Vx32 = $Vx32in";
31468}
31469def V6_vdmpyhb_alt : HInst<
31470(outs HvxVR:$Vd32),
31471(ins HvxVR:$Vu32, IntRegs:$Rt32),
31472"$Vd32 = vdmpyhb($Vu32,$Rt32)",
31473PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31474let hasNewValue = 1;
31475let opNewValue = 0;
31476let isPseudo = 1;
31477let isCodeGenOnly = 1;
31478let DecoderNamespace = "EXT_mmvec";
31479}
31480def V6_vdmpyhb_dv : HInst<
31481(outs HvxWR:$Vdd32),
31482(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31483"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
31484tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
31485let Inst{7-5} = 0b100;
31486let Inst{13-13} = 0b0;
31487let Inst{31-21} = 0b00011001001;
31488let hasNewValue = 1;
31489let opNewValue = 0;
31490let DecoderNamespace = "EXT_mmvec";
31491}
31492def V6_vdmpyhb_dv_acc : HInst<
31493(outs HvxWR:$Vxx32),
31494(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31495"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
31496tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
31497let Inst{7-5} = 0b100;
31498let Inst{13-13} = 0b1;
31499let Inst{31-21} = 0b00011001001;
31500let hasNewValue = 1;
31501let opNewValue = 0;
31502let isAccumulator = 1;
31503let DecoderNamespace = "EXT_mmvec";
31504let Constraints = "$Vxx32 = $Vxx32in";
31505}
31506def V6_vdmpyhb_dv_acc_alt : HInst<
31507(outs HvxWR:$Vxx32),
31508(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31509"$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
31510PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31511let hasNewValue = 1;
31512let opNewValue = 0;
31513let isAccumulator = 1;
31514let isPseudo = 1;
31515let isCodeGenOnly = 1;
31516let DecoderNamespace = "EXT_mmvec";
31517let Constraints = "$Vxx32 = $Vxx32in";
31518}
31519def V6_vdmpyhb_dv_alt : HInst<
31520(outs HvxWR:$Vdd32),
31521(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31522"$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
31523PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31524let hasNewValue = 1;
31525let opNewValue = 0;
31526let isPseudo = 1;
31527let isCodeGenOnly = 1;
31528let DecoderNamespace = "EXT_mmvec";
31529}
31530def V6_vdmpyhisat : HInst<
31531(outs HvxVR:$Vd32),
31532(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31533"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
31534tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
31535let Inst{7-5} = 0b011;
31536let Inst{13-13} = 0b0;
31537let Inst{31-21} = 0b00011001001;
31538let hasNewValue = 1;
31539let opNewValue = 0;
31540let DecoderNamespace = "EXT_mmvec";
31541}
31542def V6_vdmpyhisat_acc : HInst<
31543(outs HvxVR:$Vx32),
31544(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31545"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
31546tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
31547let Inst{7-5} = 0b010;
31548let Inst{13-13} = 0b1;
31549let Inst{31-21} = 0b00011001001;
31550let hasNewValue = 1;
31551let opNewValue = 0;
31552let isAccumulator = 1;
31553let DecoderNamespace = "EXT_mmvec";
31554let Constraints = "$Vx32 = $Vx32in";
31555}
31556def V6_vdmpyhisat_acc_alt : HInst<
31557(outs HvxVR:$Vx32),
31558(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31559"$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
31560PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31561let hasNewValue = 1;
31562let opNewValue = 0;
31563let isAccumulator = 1;
31564let isPseudo = 1;
31565let isCodeGenOnly = 1;
31566let DecoderNamespace = "EXT_mmvec";
31567let Constraints = "$Vx32 = $Vx32in";
31568}
31569def V6_vdmpyhisat_alt : HInst<
31570(outs HvxVR:$Vd32),
31571(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31572"$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
31573PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31574let hasNewValue = 1;
31575let opNewValue = 0;
31576let isPseudo = 1;
31577let isCodeGenOnly = 1;
31578let DecoderNamespace = "EXT_mmvec";
31579}
31580def V6_vdmpyhsat : HInst<
31581(outs HvxVR:$Vd32),
31582(ins HvxVR:$Vu32, IntRegs:$Rt32),
31583"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
31584tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
31585let Inst{7-5} = 0b010;
31586let Inst{13-13} = 0b0;
31587let Inst{31-21} = 0b00011001001;
31588let hasNewValue = 1;
31589let opNewValue = 0;
31590let DecoderNamespace = "EXT_mmvec";
31591}
31592def V6_vdmpyhsat_acc : HInst<
31593(outs HvxVR:$Vx32),
31594(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31595"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
31596tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
31597let Inst{7-5} = 0b011;
31598let Inst{13-13} = 0b1;
31599let Inst{31-21} = 0b00011001001;
31600let hasNewValue = 1;
31601let opNewValue = 0;
31602let isAccumulator = 1;
31603let DecoderNamespace = "EXT_mmvec";
31604let Constraints = "$Vx32 = $Vx32in";
31605}
31606def V6_vdmpyhsat_acc_alt : HInst<
31607(outs HvxVR:$Vx32),
31608(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31609"$Vx32 += vdmpyh($Vu32,$Rt32):sat",
31610PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31611let hasNewValue = 1;
31612let opNewValue = 0;
31613let isAccumulator = 1;
31614let isPseudo = 1;
31615let isCodeGenOnly = 1;
31616let DecoderNamespace = "EXT_mmvec";
31617let Constraints = "$Vx32 = $Vx32in";
31618}
31619def V6_vdmpyhsat_alt : HInst<
31620(outs HvxVR:$Vd32),
31621(ins HvxVR:$Vu32, IntRegs:$Rt32),
31622"$Vd32 = vdmpyh($Vu32,$Rt32):sat",
31623PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31624let hasNewValue = 1;
31625let opNewValue = 0;
31626let isPseudo = 1;
31627let isCodeGenOnly = 1;
31628let DecoderNamespace = "EXT_mmvec";
31629}
31630def V6_vdmpyhsuisat : HInst<
31631(outs HvxVR:$Vd32),
31632(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31633"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
31634tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
31635let Inst{7-5} = 0b001;
31636let Inst{13-13} = 0b0;
31637let Inst{31-21} = 0b00011001001;
31638let hasNewValue = 1;
31639let opNewValue = 0;
31640let DecoderNamespace = "EXT_mmvec";
31641}
31642def V6_vdmpyhsuisat_acc : HInst<
31643(outs HvxVR:$Vx32),
31644(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31645"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
31646tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
31647let Inst{7-5} = 0b001;
31648let Inst{13-13} = 0b1;
31649let Inst{31-21} = 0b00011001001;
31650let hasNewValue = 1;
31651let opNewValue = 0;
31652let isAccumulator = 1;
31653let DecoderNamespace = "EXT_mmvec";
31654let Constraints = "$Vx32 = $Vx32in";
31655}
31656def V6_vdmpyhsuisat_acc_alt : HInst<
31657(outs HvxVR:$Vx32),
31658(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31659"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
31660PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31661let hasNewValue = 1;
31662let opNewValue = 0;
31663let isAccumulator = 1;
31664let isPseudo = 1;
31665let isCodeGenOnly = 1;
31666let DecoderNamespace = "EXT_mmvec";
31667let Constraints = "$Vx32 = $Vx32in";
31668}
31669def V6_vdmpyhsuisat_alt : HInst<
31670(outs HvxVR:$Vd32),
31671(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31672"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
31673PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31674let hasNewValue = 1;
31675let opNewValue = 0;
31676let isPseudo = 1;
31677let isCodeGenOnly = 1;
31678let DecoderNamespace = "EXT_mmvec";
31679}
31680def V6_vdmpyhsusat : HInst<
31681(outs HvxVR:$Vd32),
31682(ins HvxVR:$Vu32, IntRegs:$Rt32),
31683"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
31684tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
31685let Inst{7-5} = 0b000;
31686let Inst{13-13} = 0b0;
31687let Inst{31-21} = 0b00011001001;
31688let hasNewValue = 1;
31689let opNewValue = 0;
31690let DecoderNamespace = "EXT_mmvec";
31691}
31692def V6_vdmpyhsusat_acc : HInst<
31693(outs HvxVR:$Vx32),
31694(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31695"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
31696tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
31697let Inst{7-5} = 0b000;
31698let Inst{13-13} = 0b1;
31699let Inst{31-21} = 0b00011001001;
31700let hasNewValue = 1;
31701let opNewValue = 0;
31702let isAccumulator = 1;
31703let DecoderNamespace = "EXT_mmvec";
31704let Constraints = "$Vx32 = $Vx32in";
31705}
31706def V6_vdmpyhsusat_acc_alt : HInst<
31707(outs HvxVR:$Vx32),
31708(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31709"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
31710PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31711let hasNewValue = 1;
31712let opNewValue = 0;
31713let isAccumulator = 1;
31714let isPseudo = 1;
31715let isCodeGenOnly = 1;
31716let DecoderNamespace = "EXT_mmvec";
31717let Constraints = "$Vx32 = $Vx32in";
31718}
31719def V6_vdmpyhsusat_alt : HInst<
31720(outs HvxVR:$Vd32),
31721(ins HvxVR:$Vu32, IntRegs:$Rt32),
31722"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
31723PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31724let hasNewValue = 1;
31725let opNewValue = 0;
31726let isPseudo = 1;
31727let isCodeGenOnly = 1;
31728let DecoderNamespace = "EXT_mmvec";
31729}
31730def V6_vdmpyhvsat : HInst<
31731(outs HvxVR:$Vd32),
31732(ins HvxVR:$Vu32, HvxVR:$Vv32),
31733"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
31734tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
31735let Inst{7-5} = 0b011;
31736let Inst{13-13} = 0b0;
31737let Inst{31-21} = 0b00011100000;
31738let hasNewValue = 1;
31739let opNewValue = 0;
31740let DecoderNamespace = "EXT_mmvec";
31741}
31742def V6_vdmpyhvsat_acc : HInst<
31743(outs HvxVR:$Vx32),
31744(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31745"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
31746tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
31747let Inst{7-5} = 0b011;
31748let Inst{13-13} = 0b1;
31749let Inst{31-21} = 0b00011100000;
31750let hasNewValue = 1;
31751let opNewValue = 0;
31752let isAccumulator = 1;
31753let DecoderNamespace = "EXT_mmvec";
31754let Constraints = "$Vx32 = $Vx32in";
31755}
31756def V6_vdmpyhvsat_acc_alt : HInst<
31757(outs HvxVR:$Vx32),
31758(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31759"$Vx32 += vdmpyh($Vu32,$Vv32):sat",
31760PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31761let hasNewValue = 1;
31762let opNewValue = 0;
31763let isAccumulator = 1;
31764let isPseudo = 1;
31765let isCodeGenOnly = 1;
31766let DecoderNamespace = "EXT_mmvec";
31767let Constraints = "$Vx32 = $Vx32in";
31768}
31769def V6_vdmpyhvsat_alt : HInst<
31770(outs HvxVR:$Vd32),
31771(ins HvxVR:$Vu32, HvxVR:$Vv32),
31772"$Vd32 = vdmpyh($Vu32,$Vv32):sat",
31773PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31774let hasNewValue = 1;
31775let opNewValue = 0;
31776let isPseudo = 1;
31777let isCodeGenOnly = 1;
31778let DecoderNamespace = "EXT_mmvec";
31779}
31780def V6_vdsaduh : HInst<
31781(outs HvxWR:$Vdd32),
31782(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31783"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
31784tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
31785let Inst{7-5} = 0b101;
31786let Inst{13-13} = 0b0;
31787let Inst{31-21} = 0b00011001000;
31788let hasNewValue = 1;
31789let opNewValue = 0;
31790let DecoderNamespace = "EXT_mmvec";
31791}
31792def V6_vdsaduh_acc : HInst<
31793(outs HvxWR:$Vxx32),
31794(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31795"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
31796tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
31797let Inst{7-5} = 0b000;
31798let Inst{13-13} = 0b1;
31799let Inst{31-21} = 0b00011001011;
31800let hasNewValue = 1;
31801let opNewValue = 0;
31802let isAccumulator = 1;
31803let DecoderNamespace = "EXT_mmvec";
31804let Constraints = "$Vxx32 = $Vxx32in";
31805}
31806def V6_vdsaduh_acc_alt : HInst<
31807(outs HvxWR:$Vxx32),
31808(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
31809"$Vxx32 += vdsaduh($Vuu32,$Rt32)",
31810PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31811let hasNewValue = 1;
31812let opNewValue = 0;
31813let isAccumulator = 1;
31814let isPseudo = 1;
31815let isCodeGenOnly = 1;
31816let DecoderNamespace = "EXT_mmvec";
31817let Constraints = "$Vxx32 = $Vxx32in";
31818}
31819def V6_vdsaduh_alt : HInst<
31820(outs HvxWR:$Vdd32),
31821(ins HvxWR:$Vuu32, IntRegs:$Rt32),
31822"$Vdd32 = vdsaduh($Vuu32,$Rt32)",
31823PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31824let hasNewValue = 1;
31825let opNewValue = 0;
31826let isPseudo = 1;
31827let isCodeGenOnly = 1;
31828let DecoderNamespace = "EXT_mmvec";
31829}
31830def V6_veqb : HInst<
31831(outs HvxQR:$Qd4),
31832(ins HvxVR:$Vu32, HvxVR:$Vv32),
31833"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
31834tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31835let Inst{7-2} = 0b000000;
31836let Inst{13-13} = 0b0;
31837let Inst{31-21} = 0b00011111100;
31838let hasNewValue = 1;
31839let opNewValue = 0;
31840let DecoderNamespace = "EXT_mmvec";
31841}
31842def V6_veqb_and : HInst<
31843(outs HvxQR:$Qx4),
31844(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31845"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
31846tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31847let Inst{7-2} = 0b000000;
31848let Inst{13-13} = 0b1;
31849let Inst{31-21} = 0b00011100100;
31850let DecoderNamespace = "EXT_mmvec";
31851let Constraints = "$Qx4 = $Qx4in";
31852}
31853def V6_veqb_or : HInst<
31854(outs HvxQR:$Qx4),
31855(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31856"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
31857tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31858let Inst{7-2} = 0b010000;
31859let Inst{13-13} = 0b1;
31860let Inst{31-21} = 0b00011100100;
31861let isAccumulator = 1;
31862let DecoderNamespace = "EXT_mmvec";
31863let Constraints = "$Qx4 = $Qx4in";
31864}
31865def V6_veqb_xor : HInst<
31866(outs HvxQR:$Qx4),
31867(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31868"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
31869tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31870let Inst{7-2} = 0b100000;
31871let Inst{13-13} = 0b1;
31872let Inst{31-21} = 0b00011100100;
31873let DecoderNamespace = "EXT_mmvec";
31874let Constraints = "$Qx4 = $Qx4in";
31875}
31876def V6_veqh : HInst<
31877(outs HvxQR:$Qd4),
31878(ins HvxVR:$Vu32, HvxVR:$Vv32),
31879"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
31880tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31881let Inst{7-2} = 0b000001;
31882let Inst{13-13} = 0b0;
31883let Inst{31-21} = 0b00011111100;
31884let hasNewValue = 1;
31885let opNewValue = 0;
31886let DecoderNamespace = "EXT_mmvec";
31887}
31888def V6_veqh_and : HInst<
31889(outs HvxQR:$Qx4),
31890(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31891"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
31892tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31893let Inst{7-2} = 0b000001;
31894let Inst{13-13} = 0b1;
31895let Inst{31-21} = 0b00011100100;
31896let DecoderNamespace = "EXT_mmvec";
31897let Constraints = "$Qx4 = $Qx4in";
31898}
31899def V6_veqh_or : HInst<
31900(outs HvxQR:$Qx4),
31901(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31902"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
31903tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31904let Inst{7-2} = 0b010001;
31905let Inst{13-13} = 0b1;
31906let Inst{31-21} = 0b00011100100;
31907let isAccumulator = 1;
31908let DecoderNamespace = "EXT_mmvec";
31909let Constraints = "$Qx4 = $Qx4in";
31910}
31911def V6_veqh_xor : HInst<
31912(outs HvxQR:$Qx4),
31913(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31914"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
31915tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31916let Inst{7-2} = 0b100001;
31917let Inst{13-13} = 0b1;
31918let Inst{31-21} = 0b00011100100;
31919let DecoderNamespace = "EXT_mmvec";
31920let Constraints = "$Qx4 = $Qx4in";
31921}
31922def V6_veqw : HInst<
31923(outs HvxQR:$Qd4),
31924(ins HvxVR:$Vu32, HvxVR:$Vv32),
31925"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
31926tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
31927let Inst{7-2} = 0b000010;
31928let Inst{13-13} = 0b0;
31929let Inst{31-21} = 0b00011111100;
31930let hasNewValue = 1;
31931let opNewValue = 0;
31932let DecoderNamespace = "EXT_mmvec";
31933}
31934def V6_veqw_and : HInst<
31935(outs HvxQR:$Qx4),
31936(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31937"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
31938tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31939let Inst{7-2} = 0b000010;
31940let Inst{13-13} = 0b1;
31941let Inst{31-21} = 0b00011100100;
31942let DecoderNamespace = "EXT_mmvec";
31943let Constraints = "$Qx4 = $Qx4in";
31944}
31945def V6_veqw_or : HInst<
31946(outs HvxQR:$Qx4),
31947(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31948"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
31949tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31950let Inst{7-2} = 0b010010;
31951let Inst{13-13} = 0b1;
31952let Inst{31-21} = 0b00011100100;
31953let isAccumulator = 1;
31954let DecoderNamespace = "EXT_mmvec";
31955let Constraints = "$Qx4 = $Qx4in";
31956}
31957def V6_veqw_xor : HInst<
31958(outs HvxQR:$Qx4),
31959(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
31960"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
31961tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
31962let Inst{7-2} = 0b100010;
31963let Inst{13-13} = 0b1;
31964let Inst{31-21} = 0b00011100100;
31965let DecoderNamespace = "EXT_mmvec";
31966let Constraints = "$Qx4 = $Qx4in";
31967}
31968def V6_vgathermh : HInst<
31969(outs),
31970(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
31971"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
31972tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
31973let Inst{12-5} = 0b00001000;
31974let Inst{31-21} = 0b00101111000;
31975let hasNewValue = 1;
31976let opNewValue = 0;
31977let accessSize = HalfWordAccess;
31978let isCVLoad = 1;
31979let hasTmpDst = 1;
31980let mayLoad = 1;
31981let Defs = [VTMP];
31982let DecoderNamespace = "EXT_mmvec";
31983}
31984def V6_vgathermhq : HInst<
31985(outs),
31986(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
31987"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
31988tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
31989let Inst{12-7} = 0b001010;
31990let Inst{31-21} = 0b00101111000;
31991let hasNewValue = 1;
31992let opNewValue = 0;
31993let accessSize = HalfWordAccess;
31994let isCVLoad = 1;
31995let hasTmpDst = 1;
31996let mayLoad = 1;
31997let Defs = [VTMP];
31998let DecoderNamespace = "EXT_mmvec";
31999}
32000def V6_vgathermhw : HInst<
32001(outs),
32002(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
32003"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
32004tc_05058f6f, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> {
32005let Inst{12-5} = 0b00010000;
32006let Inst{31-21} = 0b00101111000;
32007let hasNewValue = 1;
32008let opNewValue = 0;
32009let accessSize = HalfWordAccess;
32010let isCVLoad = 1;
32011let hasTmpDst = 1;
32012let mayLoad = 1;
32013let Defs = [VTMP];
32014let DecoderNamespace = "EXT_mmvec";
32015}
32016def V6_vgathermhwq : HInst<
32017(outs),
32018(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
32019"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
32020tc_fd7610da, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> {
32021let Inst{12-7} = 0b001100;
32022let Inst{31-21} = 0b00101111000;
32023let hasNewValue = 1;
32024let opNewValue = 0;
32025let accessSize = HalfWordAccess;
32026let isCVLoad = 1;
32027let hasTmpDst = 1;
32028let mayLoad = 1;
32029let Defs = [VTMP];
32030let DecoderNamespace = "EXT_mmvec";
32031}
32032def V6_vgathermw : HInst<
32033(outs),
32034(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32035"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
32036tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
32037let Inst{12-5} = 0b00000000;
32038let Inst{31-21} = 0b00101111000;
32039let hasNewValue = 1;
32040let opNewValue = 0;
32041let accessSize = WordAccess;
32042let isCVLoad = 1;
32043let hasTmpDst = 1;
32044let mayLoad = 1;
32045let Defs = [VTMP];
32046let DecoderNamespace = "EXT_mmvec";
32047}
32048def V6_vgathermwq : HInst<
32049(outs),
32050(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32051"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
32052tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
32053let Inst{12-7} = 0b001000;
32054let Inst{31-21} = 0b00101111000;
32055let hasNewValue = 1;
32056let opNewValue = 0;
32057let accessSize = WordAccess;
32058let isCVLoad = 1;
32059let hasTmpDst = 1;
32060let mayLoad = 1;
32061let Defs = [VTMP];
32062let DecoderNamespace = "EXT_mmvec";
32063}
32064def V6_vgtb : HInst<
32065(outs HvxQR:$Qd4),
32066(ins HvxVR:$Vu32, HvxVR:$Vv32),
32067"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
32068tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32069let Inst{7-2} = 0b000100;
32070let Inst{13-13} = 0b0;
32071let Inst{31-21} = 0b00011111100;
32072let hasNewValue = 1;
32073let opNewValue = 0;
32074let DecoderNamespace = "EXT_mmvec";
32075}
32076def V6_vgtb_and : HInst<
32077(outs HvxQR:$Qx4),
32078(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32079"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
32080tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32081let Inst{7-2} = 0b000100;
32082let Inst{13-13} = 0b1;
32083let Inst{31-21} = 0b00011100100;
32084let DecoderNamespace = "EXT_mmvec";
32085let Constraints = "$Qx4 = $Qx4in";
32086}
32087def V6_vgtb_or : HInst<
32088(outs HvxQR:$Qx4),
32089(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32090"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
32091tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32092let Inst{7-2} = 0b010100;
32093let Inst{13-13} = 0b1;
32094let Inst{31-21} = 0b00011100100;
32095let isAccumulator = 1;
32096let DecoderNamespace = "EXT_mmvec";
32097let Constraints = "$Qx4 = $Qx4in";
32098}
32099def V6_vgtb_xor : HInst<
32100(outs HvxQR:$Qx4),
32101(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32102"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
32103tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32104let Inst{7-2} = 0b100100;
32105let Inst{13-13} = 0b1;
32106let Inst{31-21} = 0b00011100100;
32107let DecoderNamespace = "EXT_mmvec";
32108let Constraints = "$Qx4 = $Qx4in";
32109}
32110def V6_vgth : HInst<
32111(outs HvxQR:$Qd4),
32112(ins HvxVR:$Vu32, HvxVR:$Vv32),
32113"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
32114tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32115let Inst{7-2} = 0b000101;
32116let Inst{13-13} = 0b0;
32117let Inst{31-21} = 0b00011111100;
32118let hasNewValue = 1;
32119let opNewValue = 0;
32120let DecoderNamespace = "EXT_mmvec";
32121}
32122def V6_vgth_and : HInst<
32123(outs HvxQR:$Qx4),
32124(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32125"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
32126tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32127let Inst{7-2} = 0b000101;
32128let Inst{13-13} = 0b1;
32129let Inst{31-21} = 0b00011100100;
32130let DecoderNamespace = "EXT_mmvec";
32131let Constraints = "$Qx4 = $Qx4in";
32132}
32133def V6_vgth_or : HInst<
32134(outs HvxQR:$Qx4),
32135(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32136"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
32137tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32138let Inst{7-2} = 0b010101;
32139let Inst{13-13} = 0b1;
32140let Inst{31-21} = 0b00011100100;
32141let isAccumulator = 1;
32142let DecoderNamespace = "EXT_mmvec";
32143let Constraints = "$Qx4 = $Qx4in";
32144}
32145def V6_vgth_xor : HInst<
32146(outs HvxQR:$Qx4),
32147(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32148"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
32149tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32150let Inst{7-2} = 0b100101;
32151let Inst{13-13} = 0b1;
32152let Inst{31-21} = 0b00011100100;
32153let DecoderNamespace = "EXT_mmvec";
32154let Constraints = "$Qx4 = $Qx4in";
32155}
32156def V6_vgtub : HInst<
32157(outs HvxQR:$Qd4),
32158(ins HvxVR:$Vu32, HvxVR:$Vv32),
32159"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
32160tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32161let Inst{7-2} = 0b001000;
32162let Inst{13-13} = 0b0;
32163let Inst{31-21} = 0b00011111100;
32164let hasNewValue = 1;
32165let opNewValue = 0;
32166let DecoderNamespace = "EXT_mmvec";
32167}
32168def V6_vgtub_and : HInst<
32169(outs HvxQR:$Qx4),
32170(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32171"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
32172tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32173let Inst{7-2} = 0b001000;
32174let Inst{13-13} = 0b1;
32175let Inst{31-21} = 0b00011100100;
32176let DecoderNamespace = "EXT_mmvec";
32177let Constraints = "$Qx4 = $Qx4in";
32178}
32179def V6_vgtub_or : HInst<
32180(outs HvxQR:$Qx4),
32181(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32182"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
32183tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32184let Inst{7-2} = 0b011000;
32185let Inst{13-13} = 0b1;
32186let Inst{31-21} = 0b00011100100;
32187let isAccumulator = 1;
32188let DecoderNamespace = "EXT_mmvec";
32189let Constraints = "$Qx4 = $Qx4in";
32190}
32191def V6_vgtub_xor : HInst<
32192(outs HvxQR:$Qx4),
32193(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32194"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
32195tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32196let Inst{7-2} = 0b101000;
32197let Inst{13-13} = 0b1;
32198let Inst{31-21} = 0b00011100100;
32199let DecoderNamespace = "EXT_mmvec";
32200let Constraints = "$Qx4 = $Qx4in";
32201}
32202def V6_vgtuh : HInst<
32203(outs HvxQR:$Qd4),
32204(ins HvxVR:$Vu32, HvxVR:$Vv32),
32205"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
32206tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32207let Inst{7-2} = 0b001001;
32208let Inst{13-13} = 0b0;
32209let Inst{31-21} = 0b00011111100;
32210let hasNewValue = 1;
32211let opNewValue = 0;
32212let DecoderNamespace = "EXT_mmvec";
32213}
32214def V6_vgtuh_and : HInst<
32215(outs HvxQR:$Qx4),
32216(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32217"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
32218tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32219let Inst{7-2} = 0b001001;
32220let Inst{13-13} = 0b1;
32221let Inst{31-21} = 0b00011100100;
32222let DecoderNamespace = "EXT_mmvec";
32223let Constraints = "$Qx4 = $Qx4in";
32224}
32225def V6_vgtuh_or : HInst<
32226(outs HvxQR:$Qx4),
32227(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32228"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
32229tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32230let Inst{7-2} = 0b011001;
32231let Inst{13-13} = 0b1;
32232let Inst{31-21} = 0b00011100100;
32233let isAccumulator = 1;
32234let DecoderNamespace = "EXT_mmvec";
32235let Constraints = "$Qx4 = $Qx4in";
32236}
32237def V6_vgtuh_xor : HInst<
32238(outs HvxQR:$Qx4),
32239(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32240"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
32241tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32242let Inst{7-2} = 0b101001;
32243let Inst{13-13} = 0b1;
32244let Inst{31-21} = 0b00011100100;
32245let DecoderNamespace = "EXT_mmvec";
32246let Constraints = "$Qx4 = $Qx4in";
32247}
32248def V6_vgtuw : HInst<
32249(outs HvxQR:$Qd4),
32250(ins HvxVR:$Vu32, HvxVR:$Vv32),
32251"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
32252tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32253let Inst{7-2} = 0b001010;
32254let Inst{13-13} = 0b0;
32255let Inst{31-21} = 0b00011111100;
32256let hasNewValue = 1;
32257let opNewValue = 0;
32258let DecoderNamespace = "EXT_mmvec";
32259}
32260def V6_vgtuw_and : HInst<
32261(outs HvxQR:$Qx4),
32262(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32263"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
32264tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32265let Inst{7-2} = 0b001010;
32266let Inst{13-13} = 0b1;
32267let Inst{31-21} = 0b00011100100;
32268let DecoderNamespace = "EXT_mmvec";
32269let Constraints = "$Qx4 = $Qx4in";
32270}
32271def V6_vgtuw_or : HInst<
32272(outs HvxQR:$Qx4),
32273(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32274"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
32275tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32276let Inst{7-2} = 0b011010;
32277let Inst{13-13} = 0b1;
32278let Inst{31-21} = 0b00011100100;
32279let isAccumulator = 1;
32280let DecoderNamespace = "EXT_mmvec";
32281let Constraints = "$Qx4 = $Qx4in";
32282}
32283def V6_vgtuw_xor : HInst<
32284(outs HvxQR:$Qx4),
32285(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32286"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
32287tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32288let Inst{7-2} = 0b101010;
32289let Inst{13-13} = 0b1;
32290let Inst{31-21} = 0b00011100100;
32291let DecoderNamespace = "EXT_mmvec";
32292let Constraints = "$Qx4 = $Qx4in";
32293}
32294def V6_vgtw : HInst<
32295(outs HvxQR:$Qd4),
32296(ins HvxVR:$Vu32, HvxVR:$Vv32),
32297"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
32298tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32299let Inst{7-2} = 0b000110;
32300let Inst{13-13} = 0b0;
32301let Inst{31-21} = 0b00011111100;
32302let hasNewValue = 1;
32303let opNewValue = 0;
32304let DecoderNamespace = "EXT_mmvec";
32305}
32306def V6_vgtw_and : HInst<
32307(outs HvxQR:$Qx4),
32308(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32309"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
32310tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32311let Inst{7-2} = 0b000110;
32312let Inst{13-13} = 0b1;
32313let Inst{31-21} = 0b00011100100;
32314let DecoderNamespace = "EXT_mmvec";
32315let Constraints = "$Qx4 = $Qx4in";
32316}
32317def V6_vgtw_or : HInst<
32318(outs HvxQR:$Qx4),
32319(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32320"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
32321tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32322let Inst{7-2} = 0b010110;
32323let Inst{13-13} = 0b1;
32324let Inst{31-21} = 0b00011100100;
32325let isAccumulator = 1;
32326let DecoderNamespace = "EXT_mmvec";
32327let Constraints = "$Qx4 = $Qx4in";
32328}
32329def V6_vgtw_xor : HInst<
32330(outs HvxQR:$Qx4),
32331(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32332"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
32333tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32334let Inst{7-2} = 0b100110;
32335let Inst{13-13} = 0b1;
32336let Inst{31-21} = 0b00011100100;
32337let DecoderNamespace = "EXT_mmvec";
32338let Constraints = "$Qx4 = $Qx4in";
32339}
32340def V6_vhist : HInst<
32341(outs),
32342(ins),
32343"vhist",
32344tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
32345let Inst{13-0} = 0b10000010000000;
32346let Inst{31-16} = 0b0001111000000000;
32347let DecoderNamespace = "EXT_mmvec";
32348}
32349def V6_vhistq : HInst<
32350(outs),
32351(ins HvxQR:$Qv4),
32352"vhist($Qv4)",
32353tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
32354let Inst{13-0} = 0b10000010000000;
32355let Inst{21-16} = 0b000010;
32356let Inst{31-24} = 0b00011110;
32357let DecoderNamespace = "EXT_mmvec";
32358}
32359def V6_vinsertwr : HInst<
32360(outs HvxVR:$Vx32),
32361(ins HvxVR:$Vx32in, IntRegs:$Rt32),
32362"$Vx32.w = vinsert($Rt32)",
32363tc_ac4046bc, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
32364let Inst{13-5} = 0b100000001;
32365let Inst{31-21} = 0b00011001101;
32366let hasNewValue = 1;
32367let opNewValue = 0;
32368let DecoderNamespace = "EXT_mmvec";
32369let Constraints = "$Vx32 = $Vx32in";
32370}
32371def V6_vlalignb : HInst<
32372(outs HvxVR:$Vd32),
32373(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32374"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
32375tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
32376let Inst{7-5} = 0b001;
32377let Inst{13-13} = 0b0;
32378let Inst{31-24} = 0b00011011;
32379let hasNewValue = 1;
32380let opNewValue = 0;
32381let DecoderNamespace = "EXT_mmvec";
32382}
32383def V6_vlalignbi : HInst<
32384(outs HvxVR:$Vd32),
32385(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32386"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
32387tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
32388let Inst{13-13} = 0b1;
32389let Inst{31-21} = 0b00011110011;
32390let hasNewValue = 1;
32391let opNewValue = 0;
32392let DecoderNamespace = "EXT_mmvec";
32393}
32394def V6_vlsrb : HInst<
32395(outs HvxVR:$Vd32),
32396(ins HvxVR:$Vu32, IntRegs:$Rt32),
32397"$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
32398tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
32399let Inst{7-5} = 0b011;
32400let Inst{13-13} = 0b0;
32401let Inst{31-21} = 0b00011001100;
32402let hasNewValue = 1;
32403let opNewValue = 0;
32404let DecoderNamespace = "EXT_mmvec";
32405}
32406def V6_vlsrh : HInst<
32407(outs HvxVR:$Vd32),
32408(ins HvxVR:$Vu32, IntRegs:$Rt32),
32409"$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
32410tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
32411let Inst{7-5} = 0b010;
32412let Inst{13-13} = 0b0;
32413let Inst{31-21} = 0b00011001100;
32414let hasNewValue = 1;
32415let opNewValue = 0;
32416let DecoderNamespace = "EXT_mmvec";
32417}
32418def V6_vlsrh_alt : HInst<
32419(outs HvxVR:$Vd32),
32420(ins HvxVR:$Vu32, IntRegs:$Rt32),
32421"$Vd32 = vlsrh($Vu32,$Rt32)",
32422PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32423let hasNewValue = 1;
32424let opNewValue = 0;
32425let isPseudo = 1;
32426let isCodeGenOnly = 1;
32427let DecoderNamespace = "EXT_mmvec";
32428}
32429def V6_vlsrhv : HInst<
32430(outs HvxVR:$Vd32),
32431(ins HvxVR:$Vu32, HvxVR:$Vv32),
32432"$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
32433tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
32434let Inst{7-5} = 0b010;
32435let Inst{13-13} = 0b0;
32436let Inst{31-21} = 0b00011111101;
32437let hasNewValue = 1;
32438let opNewValue = 0;
32439let DecoderNamespace = "EXT_mmvec";
32440}
32441def V6_vlsrhv_alt : HInst<
32442(outs HvxVR:$Vd32),
32443(ins HvxVR:$Vu32, HvxVR:$Vv32),
32444"$Vd32 = vlsrh($Vu32,$Vv32)",
32445PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32446let hasNewValue = 1;
32447let opNewValue = 0;
32448let isPseudo = 1;
32449let isCodeGenOnly = 1;
32450let DecoderNamespace = "EXT_mmvec";
32451}
32452def V6_vlsrw : HInst<
32453(outs HvxVR:$Vd32),
32454(ins HvxVR:$Vu32, IntRegs:$Rt32),
32455"$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
32456tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
32457let Inst{7-5} = 0b001;
32458let Inst{13-13} = 0b0;
32459let Inst{31-21} = 0b00011001100;
32460let hasNewValue = 1;
32461let opNewValue = 0;
32462let DecoderNamespace = "EXT_mmvec";
32463}
32464def V6_vlsrw_alt : HInst<
32465(outs HvxVR:$Vd32),
32466(ins HvxVR:$Vu32, IntRegs:$Rt32),
32467"$Vd32 = vlsrw($Vu32,$Rt32)",
32468PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32469let hasNewValue = 1;
32470let opNewValue = 0;
32471let isPseudo = 1;
32472let isCodeGenOnly = 1;
32473let DecoderNamespace = "EXT_mmvec";
32474}
32475def V6_vlsrwv : HInst<
32476(outs HvxVR:$Vd32),
32477(ins HvxVR:$Vu32, HvxVR:$Vv32),
32478"$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
32479tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
32480let Inst{7-5} = 0b001;
32481let Inst{13-13} = 0b0;
32482let Inst{31-21} = 0b00011111101;
32483let hasNewValue = 1;
32484let opNewValue = 0;
32485let DecoderNamespace = "EXT_mmvec";
32486}
32487def V6_vlsrwv_alt : HInst<
32488(outs HvxVR:$Vd32),
32489(ins HvxVR:$Vu32, HvxVR:$Vv32),
32490"$Vd32 = vlsrw($Vu32,$Vv32)",
32491PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32492let hasNewValue = 1;
32493let opNewValue = 0;
32494let isPseudo = 1;
32495let isCodeGenOnly = 1;
32496let DecoderNamespace = "EXT_mmvec";
32497}
32498def V6_vlut4 : HInst<
32499(outs HvxVR:$Vd32),
32500(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
32501"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
32502tc_f1de44ef, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
32503let Inst{7-5} = 0b100;
32504let Inst{13-13} = 0b0;
32505let Inst{31-21} = 0b00011001011;
32506let hasNewValue = 1;
32507let opNewValue = 0;
32508let DecoderNamespace = "EXT_mmvec";
32509}
32510def V6_vlutvvb : HInst<
32511(outs HvxVR:$Vd32),
32512(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32513"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
32514tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
32515let Inst{7-5} = 0b001;
32516let Inst{13-13} = 0b1;
32517let Inst{31-24} = 0b00011011;
32518let hasNewValue = 1;
32519let opNewValue = 0;
32520let DecoderNamespace = "EXT_mmvec";
32521}
32522def V6_vlutvvb_nm : HInst<
32523(outs HvxVR:$Vd32),
32524(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32525"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
32526tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
32527let Inst{7-5} = 0b011;
32528let Inst{13-13} = 0b0;
32529let Inst{31-24} = 0b00011000;
32530let hasNewValue = 1;
32531let opNewValue = 0;
32532let DecoderNamespace = "EXT_mmvec";
32533}
32534def V6_vlutvvb_oracc : HInst<
32535(outs HvxVR:$Vx32),
32536(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32537"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
32538tc_9d1dc972, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
32539let Inst{7-5} = 0b101;
32540let Inst{13-13} = 0b1;
32541let Inst{31-24} = 0b00011011;
32542let hasNewValue = 1;
32543let opNewValue = 0;
32544let isAccumulator = 1;
32545let DecoderNamespace = "EXT_mmvec";
32546let Constraints = "$Vx32 = $Vx32in";
32547}
32548def V6_vlutvvb_oracci : HInst<
32549(outs HvxVR:$Vx32),
32550(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32551"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
32552tc_9d1dc972, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
32553let Inst{13-13} = 0b1;
32554let Inst{31-21} = 0b00011100110;
32555let hasNewValue = 1;
32556let opNewValue = 0;
32557let isAccumulator = 1;
32558let DecoderNamespace = "EXT_mmvec";
32559let Constraints = "$Vx32 = $Vx32in";
32560}
32561def V6_vlutvvbi : HInst<
32562(outs HvxVR:$Vd32),
32563(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32564"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
32565tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
32566let Inst{13-13} = 0b0;
32567let Inst{31-21} = 0b00011110001;
32568let hasNewValue = 1;
32569let opNewValue = 0;
32570let DecoderNamespace = "EXT_mmvec";
32571}
32572def V6_vlutvwh : HInst<
32573(outs HvxWR:$Vdd32),
32574(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32575"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
32576tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
32577let Inst{7-5} = 0b110;
32578let Inst{13-13} = 0b1;
32579let Inst{31-24} = 0b00011011;
32580let hasNewValue = 1;
32581let opNewValue = 0;
32582let DecoderNamespace = "EXT_mmvec";
32583}
32584def V6_vlutvwh_nm : HInst<
32585(outs HvxWR:$Vdd32),
32586(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32587"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
32588tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
32589let Inst{7-5} = 0b100;
32590let Inst{13-13} = 0b0;
32591let Inst{31-24} = 0b00011000;
32592let hasNewValue = 1;
32593let opNewValue = 0;
32594let DecoderNamespace = "EXT_mmvec";
32595}
32596def V6_vlutvwh_oracc : HInst<
32597(outs HvxWR:$Vxx32),
32598(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32599"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
32600tc_9d1dc972, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
32601let Inst{7-5} = 0b111;
32602let Inst{13-13} = 0b1;
32603let Inst{31-24} = 0b00011011;
32604let hasNewValue = 1;
32605let opNewValue = 0;
32606let isAccumulator = 1;
32607let DecoderNamespace = "EXT_mmvec";
32608let Constraints = "$Vxx32 = $Vxx32in";
32609}
32610def V6_vlutvwh_oracci : HInst<
32611(outs HvxWR:$Vxx32),
32612(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32613"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
32614tc_9d1dc972, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
32615let Inst{13-13} = 0b1;
32616let Inst{31-21} = 0b00011100111;
32617let hasNewValue = 1;
32618let opNewValue = 0;
32619let isAccumulator = 1;
32620let DecoderNamespace = "EXT_mmvec";
32621let Constraints = "$Vxx32 = $Vxx32in";
32622}
32623def V6_vlutvwhi : HInst<
32624(outs HvxWR:$Vdd32),
32625(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
32626"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
32627tc_87adc037, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
32628let Inst{13-13} = 0b0;
32629let Inst{31-21} = 0b00011110011;
32630let hasNewValue = 1;
32631let opNewValue = 0;
32632let DecoderNamespace = "EXT_mmvec";
32633}
32634def V6_vmaxb : HInst<
32635(outs HvxVR:$Vd32),
32636(ins HvxVR:$Vu32, HvxVR:$Vv32),
32637"$Vd32.b = vmax($Vu32.b,$Vv32.b)",
32638tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
32639let Inst{7-5} = 0b101;
32640let Inst{13-13} = 0b0;
32641let Inst{31-21} = 0b00011111001;
32642let hasNewValue = 1;
32643let opNewValue = 0;
32644let DecoderNamespace = "EXT_mmvec";
32645}
32646def V6_vmaxb_alt : HInst<
32647(outs HvxVR:$Vd32),
32648(ins HvxVR:$Vu32, HvxVR:$Vv32),
32649"$Vd32 = vmaxb($Vu32,$Vv32)",
32650PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
32651let hasNewValue = 1;
32652let opNewValue = 0;
32653let isPseudo = 1;
32654let isCodeGenOnly = 1;
32655let DecoderNamespace = "EXT_mmvec";
32656}
32657def V6_vmaxh : HInst<
32658(outs HvxVR:$Vd32),
32659(ins HvxVR:$Vu32, HvxVR:$Vv32),
32660"$Vd32.h = vmax($Vu32.h,$Vv32.h)",
32661tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32662let Inst{7-5} = 0b111;
32663let Inst{13-13} = 0b0;
32664let Inst{31-21} = 0b00011111000;
32665let hasNewValue = 1;
32666let opNewValue = 0;
32667let DecoderNamespace = "EXT_mmvec";
32668}
32669def V6_vmaxh_alt : HInst<
32670(outs HvxVR:$Vd32),
32671(ins HvxVR:$Vu32, HvxVR:$Vv32),
32672"$Vd32 = vmaxh($Vu32,$Vv32)",
32673PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32674let hasNewValue = 1;
32675let opNewValue = 0;
32676let isPseudo = 1;
32677let isCodeGenOnly = 1;
32678let DecoderNamespace = "EXT_mmvec";
32679}
32680def V6_vmaxub : HInst<
32681(outs HvxVR:$Vd32),
32682(ins HvxVR:$Vu32, HvxVR:$Vv32),
32683"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
32684tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32685let Inst{7-5} = 0b101;
32686let Inst{13-13} = 0b0;
32687let Inst{31-21} = 0b00011111000;
32688let hasNewValue = 1;
32689let opNewValue = 0;
32690let DecoderNamespace = "EXT_mmvec";
32691}
32692def V6_vmaxub_alt : HInst<
32693(outs HvxVR:$Vd32),
32694(ins HvxVR:$Vu32, HvxVR:$Vv32),
32695"$Vd32 = vmaxub($Vu32,$Vv32)",
32696PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32697let hasNewValue = 1;
32698let opNewValue = 0;
32699let isPseudo = 1;
32700let isCodeGenOnly = 1;
32701let DecoderNamespace = "EXT_mmvec";
32702}
32703def V6_vmaxuh : HInst<
32704(outs HvxVR:$Vd32),
32705(ins HvxVR:$Vu32, HvxVR:$Vv32),
32706"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
32707tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32708let Inst{7-5} = 0b110;
32709let Inst{13-13} = 0b0;
32710let Inst{31-21} = 0b00011111000;
32711let hasNewValue = 1;
32712let opNewValue = 0;
32713let DecoderNamespace = "EXT_mmvec";
32714}
32715def V6_vmaxuh_alt : HInst<
32716(outs HvxVR:$Vd32),
32717(ins HvxVR:$Vu32, HvxVR:$Vv32),
32718"$Vd32 = vmaxuh($Vu32,$Vv32)",
32719PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32720let hasNewValue = 1;
32721let opNewValue = 0;
32722let isPseudo = 1;
32723let isCodeGenOnly = 1;
32724let DecoderNamespace = "EXT_mmvec";
32725}
32726def V6_vmaxw : HInst<
32727(outs HvxVR:$Vd32),
32728(ins HvxVR:$Vu32, HvxVR:$Vv32),
32729"$Vd32.w = vmax($Vu32.w,$Vv32.w)",
32730tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32731let Inst{7-5} = 0b000;
32732let Inst{13-13} = 0b0;
32733let Inst{31-21} = 0b00011111001;
32734let hasNewValue = 1;
32735let opNewValue = 0;
32736let DecoderNamespace = "EXT_mmvec";
32737}
32738def V6_vmaxw_alt : HInst<
32739(outs HvxVR:$Vd32),
32740(ins HvxVR:$Vu32, HvxVR:$Vv32),
32741"$Vd32 = vmaxw($Vu32,$Vv32)",
32742PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32743let hasNewValue = 1;
32744let opNewValue = 0;
32745let isPseudo = 1;
32746let isCodeGenOnly = 1;
32747let DecoderNamespace = "EXT_mmvec";
32748}
32749def V6_vminb : HInst<
32750(outs HvxVR:$Vd32),
32751(ins HvxVR:$Vu32, HvxVR:$Vv32),
32752"$Vd32.b = vmin($Vu32.b,$Vv32.b)",
32753tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
32754let Inst{7-5} = 0b100;
32755let Inst{13-13} = 0b0;
32756let Inst{31-21} = 0b00011111001;
32757let hasNewValue = 1;
32758let opNewValue = 0;
32759let DecoderNamespace = "EXT_mmvec";
32760}
32761def V6_vminb_alt : HInst<
32762(outs HvxVR:$Vd32),
32763(ins HvxVR:$Vu32, HvxVR:$Vv32),
32764"$Vd32 = vminb($Vu32,$Vv32)",
32765PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
32766let hasNewValue = 1;
32767let opNewValue = 0;
32768let isPseudo = 1;
32769let isCodeGenOnly = 1;
32770let DecoderNamespace = "EXT_mmvec";
32771}
32772def V6_vminh : HInst<
32773(outs HvxVR:$Vd32),
32774(ins HvxVR:$Vu32, HvxVR:$Vv32),
32775"$Vd32.h = vmin($Vu32.h,$Vv32.h)",
32776tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32777let Inst{7-5} = 0b011;
32778let Inst{13-13} = 0b0;
32779let Inst{31-21} = 0b00011111000;
32780let hasNewValue = 1;
32781let opNewValue = 0;
32782let DecoderNamespace = "EXT_mmvec";
32783}
32784def V6_vminh_alt : HInst<
32785(outs HvxVR:$Vd32),
32786(ins HvxVR:$Vu32, HvxVR:$Vv32),
32787"$Vd32 = vminh($Vu32,$Vv32)",
32788PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32789let hasNewValue = 1;
32790let opNewValue = 0;
32791let isPseudo = 1;
32792let isCodeGenOnly = 1;
32793let DecoderNamespace = "EXT_mmvec";
32794}
32795def V6_vminub : HInst<
32796(outs HvxVR:$Vd32),
32797(ins HvxVR:$Vu32, HvxVR:$Vv32),
32798"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
32799tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32800let Inst{7-5} = 0b001;
32801let Inst{13-13} = 0b0;
32802let Inst{31-21} = 0b00011111000;
32803let hasNewValue = 1;
32804let opNewValue = 0;
32805let DecoderNamespace = "EXT_mmvec";
32806}
32807def V6_vminub_alt : HInst<
32808(outs HvxVR:$Vd32),
32809(ins HvxVR:$Vu32, HvxVR:$Vv32),
32810"$Vd32 = vminub($Vu32,$Vv32)",
32811PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32812let hasNewValue = 1;
32813let opNewValue = 0;
32814let isPseudo = 1;
32815let isCodeGenOnly = 1;
32816let DecoderNamespace = "EXT_mmvec";
32817}
32818def V6_vminuh : HInst<
32819(outs HvxVR:$Vd32),
32820(ins HvxVR:$Vu32, HvxVR:$Vv32),
32821"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
32822tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32823let Inst{7-5} = 0b010;
32824let Inst{13-13} = 0b0;
32825let Inst{31-21} = 0b00011111000;
32826let hasNewValue = 1;
32827let opNewValue = 0;
32828let DecoderNamespace = "EXT_mmvec";
32829}
32830def V6_vminuh_alt : HInst<
32831(outs HvxVR:$Vd32),
32832(ins HvxVR:$Vu32, HvxVR:$Vv32),
32833"$Vd32 = vminuh($Vu32,$Vv32)",
32834PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32835let hasNewValue = 1;
32836let opNewValue = 0;
32837let isPseudo = 1;
32838let isCodeGenOnly = 1;
32839let DecoderNamespace = "EXT_mmvec";
32840}
32841def V6_vminw : HInst<
32842(outs HvxVR:$Vd32),
32843(ins HvxVR:$Vu32, HvxVR:$Vv32),
32844"$Vd32.w = vmin($Vu32.w,$Vv32.w)",
32845tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32846let Inst{7-5} = 0b100;
32847let Inst{13-13} = 0b0;
32848let Inst{31-21} = 0b00011111000;
32849let hasNewValue = 1;
32850let opNewValue = 0;
32851let DecoderNamespace = "EXT_mmvec";
32852}
32853def V6_vminw_alt : HInst<
32854(outs HvxVR:$Vd32),
32855(ins HvxVR:$Vu32, HvxVR:$Vv32),
32856"$Vd32 = vminw($Vu32,$Vv32)",
32857PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32858let hasNewValue = 1;
32859let opNewValue = 0;
32860let isPseudo = 1;
32861let isCodeGenOnly = 1;
32862let DecoderNamespace = "EXT_mmvec";
32863}
32864def V6_vmpabus : HInst<
32865(outs HvxWR:$Vdd32),
32866(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32867"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
32868tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32869let Inst{7-5} = 0b110;
32870let Inst{13-13} = 0b0;
32871let Inst{31-21} = 0b00011001001;
32872let hasNewValue = 1;
32873let opNewValue = 0;
32874let DecoderNamespace = "EXT_mmvec";
32875}
32876def V6_vmpabus_acc : HInst<
32877(outs HvxWR:$Vxx32),
32878(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32879"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
32880tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32881let Inst{7-5} = 0b110;
32882let Inst{13-13} = 0b1;
32883let Inst{31-21} = 0b00011001001;
32884let hasNewValue = 1;
32885let opNewValue = 0;
32886let isAccumulator = 1;
32887let DecoderNamespace = "EXT_mmvec";
32888let Constraints = "$Vxx32 = $Vxx32in";
32889}
32890def V6_vmpabus_acc_alt : HInst<
32891(outs HvxWR:$Vxx32),
32892(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32893"$Vxx32 += vmpabus($Vuu32,$Rt32)",
32894PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32895let hasNewValue = 1;
32896let opNewValue = 0;
32897let isAccumulator = 1;
32898let isPseudo = 1;
32899let isCodeGenOnly = 1;
32900let DecoderNamespace = "EXT_mmvec";
32901let Constraints = "$Vxx32 = $Vxx32in";
32902}
32903def V6_vmpabus_alt : HInst<
32904(outs HvxWR:$Vdd32),
32905(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32906"$Vdd32 = vmpabus($Vuu32,$Rt32)",
32907PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32908let hasNewValue = 1;
32909let opNewValue = 0;
32910let isPseudo = 1;
32911let isCodeGenOnly = 1;
32912let DecoderNamespace = "EXT_mmvec";
32913}
32914def V6_vmpabusv : HInst<
32915(outs HvxWR:$Vdd32),
32916(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
32917"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
32918tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
32919let Inst{7-5} = 0b011;
32920let Inst{13-13} = 0b0;
32921let Inst{31-21} = 0b00011100001;
32922let hasNewValue = 1;
32923let opNewValue = 0;
32924let DecoderNamespace = "EXT_mmvec";
32925}
32926def V6_vmpabusv_alt : HInst<
32927(outs HvxWR:$Vdd32),
32928(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
32929"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
32930PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32931let hasNewValue = 1;
32932let opNewValue = 0;
32933let isPseudo = 1;
32934let isCodeGenOnly = 1;
32935let DecoderNamespace = "EXT_mmvec";
32936}
32937def V6_vmpabuu : HInst<
32938(outs HvxWR:$Vdd32),
32939(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32940"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
32941tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
32942let Inst{7-5} = 0b011;
32943let Inst{13-13} = 0b0;
32944let Inst{31-21} = 0b00011001011;
32945let hasNewValue = 1;
32946let opNewValue = 0;
32947let DecoderNamespace = "EXT_mmvec";
32948}
32949def V6_vmpabuu_acc : HInst<
32950(outs HvxWR:$Vxx32),
32951(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32952"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
32953tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
32954let Inst{7-5} = 0b100;
32955let Inst{13-13} = 0b1;
32956let Inst{31-21} = 0b00011001101;
32957let hasNewValue = 1;
32958let opNewValue = 0;
32959let isAccumulator = 1;
32960let DecoderNamespace = "EXT_mmvec";
32961let Constraints = "$Vxx32 = $Vxx32in";
32962}
32963def V6_vmpabuu_acc_alt : HInst<
32964(outs HvxWR:$Vxx32),
32965(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32966"$Vxx32 += vmpabuu($Vuu32,$Rt32)",
32967PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32968let hasNewValue = 1;
32969let opNewValue = 0;
32970let isAccumulator = 1;
32971let isPseudo = 1;
32972let isCodeGenOnly = 1;
32973let DecoderNamespace = "EXT_mmvec";
32974let Constraints = "$Vxx32 = $Vxx32in";
32975}
32976def V6_vmpabuu_alt : HInst<
32977(outs HvxWR:$Vdd32),
32978(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32979"$Vdd32 = vmpabuu($Vuu32,$Rt32)",
32980PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32981let hasNewValue = 1;
32982let opNewValue = 0;
32983let isPseudo = 1;
32984let isCodeGenOnly = 1;
32985let DecoderNamespace = "EXT_mmvec";
32986}
32987def V6_vmpabuuv : HInst<
32988(outs HvxWR:$Vdd32),
32989(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
32990"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
32991tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
32992let Inst{7-5} = 0b111;
32993let Inst{13-13} = 0b0;
32994let Inst{31-21} = 0b00011100111;
32995let hasNewValue = 1;
32996let opNewValue = 0;
32997let DecoderNamespace = "EXT_mmvec";
32998}
32999def V6_vmpabuuv_alt : HInst<
33000(outs HvxWR:$Vdd32),
33001(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33002"$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
33003PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33004let hasNewValue = 1;
33005let opNewValue = 0;
33006let isPseudo = 1;
33007let isCodeGenOnly = 1;
33008let DecoderNamespace = "EXT_mmvec";
33009}
33010def V6_vmpahb : HInst<
33011(outs HvxWR:$Vdd32),
33012(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33013"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
33014tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33015let Inst{7-5} = 0b111;
33016let Inst{13-13} = 0b0;
33017let Inst{31-21} = 0b00011001001;
33018let hasNewValue = 1;
33019let opNewValue = 0;
33020let DecoderNamespace = "EXT_mmvec";
33021}
33022def V6_vmpahb_acc : HInst<
33023(outs HvxWR:$Vxx32),
33024(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33025"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
33026tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33027let Inst{7-5} = 0b111;
33028let Inst{13-13} = 0b1;
33029let Inst{31-21} = 0b00011001001;
33030let hasNewValue = 1;
33031let opNewValue = 0;
33032let isAccumulator = 1;
33033let DecoderNamespace = "EXT_mmvec";
33034let Constraints = "$Vxx32 = $Vxx32in";
33035}
33036def V6_vmpahb_acc_alt : HInst<
33037(outs HvxWR:$Vxx32),
33038(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33039"$Vxx32 += vmpahb($Vuu32,$Rt32)",
33040PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33041let hasNewValue = 1;
33042let opNewValue = 0;
33043let isAccumulator = 1;
33044let isPseudo = 1;
33045let isCodeGenOnly = 1;
33046let DecoderNamespace = "EXT_mmvec";
33047let Constraints = "$Vxx32 = $Vxx32in";
33048}
33049def V6_vmpahb_alt : HInst<
33050(outs HvxWR:$Vdd32),
33051(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33052"$Vdd32 = vmpahb($Vuu32,$Rt32)",
33053PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33054let hasNewValue = 1;
33055let opNewValue = 0;
33056let isPseudo = 1;
33057let isCodeGenOnly = 1;
33058let DecoderNamespace = "EXT_mmvec";
33059}
33060def V6_vmpahhsat : HInst<
33061(outs HvxVR:$Vx32),
33062(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
33063"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
33064tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
33065let Inst{7-5} = 0b100;
33066let Inst{13-13} = 0b1;
33067let Inst{31-21} = 0b00011001100;
33068let hasNewValue = 1;
33069let opNewValue = 0;
33070let DecoderNamespace = "EXT_mmvec";
33071let Constraints = "$Vx32 = $Vx32in";
33072}
33073def V6_vmpauhb : HInst<
33074(outs HvxWR:$Vdd32),
33075(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33076"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
33077tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
33078let Inst{7-5} = 0b101;
33079let Inst{13-13} = 0b0;
33080let Inst{31-21} = 0b00011001100;
33081let hasNewValue = 1;
33082let opNewValue = 0;
33083let DecoderNamespace = "EXT_mmvec";
33084}
33085def V6_vmpauhb_acc : HInst<
33086(outs HvxWR:$Vxx32),
33087(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33088"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
33089tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
33090let Inst{7-5} = 0b010;
33091let Inst{13-13} = 0b1;
33092let Inst{31-21} = 0b00011001100;
33093let hasNewValue = 1;
33094let opNewValue = 0;
33095let isAccumulator = 1;
33096let DecoderNamespace = "EXT_mmvec";
33097let Constraints = "$Vxx32 = $Vxx32in";
33098}
33099def V6_vmpauhb_acc_alt : HInst<
33100(outs HvxWR:$Vxx32),
33101(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33102"$Vxx32 += vmpauhb($Vuu32,$Rt32)",
33103PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33104let hasNewValue = 1;
33105let opNewValue = 0;
33106let isAccumulator = 1;
33107let isPseudo = 1;
33108let isCodeGenOnly = 1;
33109let DecoderNamespace = "EXT_mmvec";
33110let Constraints = "$Vxx32 = $Vxx32in";
33111}
33112def V6_vmpauhb_alt : HInst<
33113(outs HvxWR:$Vdd32),
33114(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33115"$Vdd32 = vmpauhb($Vuu32,$Rt32)",
33116PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33117let hasNewValue = 1;
33118let opNewValue = 0;
33119let isPseudo = 1;
33120let isCodeGenOnly = 1;
33121let DecoderNamespace = "EXT_mmvec";
33122}
33123def V6_vmpauhuhsat : HInst<
33124(outs HvxVR:$Vx32),
33125(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
33126"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
33127tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
33128let Inst{7-5} = 0b101;
33129let Inst{13-13} = 0b1;
33130let Inst{31-21} = 0b00011001100;
33131let hasNewValue = 1;
33132let opNewValue = 0;
33133let DecoderNamespace = "EXT_mmvec";
33134let Constraints = "$Vx32 = $Vx32in";
33135}
33136def V6_vmpsuhuhsat : HInst<
33137(outs HvxVR:$Vx32),
33138(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
33139"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
33140tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
33141let Inst{7-5} = 0b110;
33142let Inst{13-13} = 0b1;
33143let Inst{31-21} = 0b00011001100;
33144let hasNewValue = 1;
33145let opNewValue = 0;
33146let DecoderNamespace = "EXT_mmvec";
33147let Constraints = "$Vx32 = $Vx32in";
33148}
33149def V6_vmpybus : HInst<
33150(outs HvxWR:$Vdd32),
33151(ins HvxVR:$Vu32, IntRegs:$Rt32),
33152"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
33153tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
33154let Inst{7-5} = 0b101;
33155let Inst{13-13} = 0b0;
33156let Inst{31-21} = 0b00011001001;
33157let hasNewValue = 1;
33158let opNewValue = 0;
33159let DecoderNamespace = "EXT_mmvec";
33160}
33161def V6_vmpybus_acc : HInst<
33162(outs HvxWR:$Vxx32),
33163(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33164"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
33165tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
33166let Inst{7-5} = 0b101;
33167let Inst{13-13} = 0b1;
33168let Inst{31-21} = 0b00011001001;
33169let hasNewValue = 1;
33170let opNewValue = 0;
33171let isAccumulator = 1;
33172let DecoderNamespace = "EXT_mmvec";
33173let Constraints = "$Vxx32 = $Vxx32in";
33174}
33175def V6_vmpybus_acc_alt : HInst<
33176(outs HvxWR:$Vxx32),
33177(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33178"$Vxx32 += vmpybus($Vu32,$Rt32)",
33179PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33180let hasNewValue = 1;
33181let opNewValue = 0;
33182let isAccumulator = 1;
33183let isPseudo = 1;
33184let isCodeGenOnly = 1;
33185let DecoderNamespace = "EXT_mmvec";
33186let Constraints = "$Vxx32 = $Vxx32in";
33187}
33188def V6_vmpybus_alt : HInst<
33189(outs HvxWR:$Vdd32),
33190(ins HvxVR:$Vu32, IntRegs:$Rt32),
33191"$Vdd32 = vmpybus($Vu32,$Rt32)",
33192PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33193let hasNewValue = 1;
33194let opNewValue = 0;
33195let isPseudo = 1;
33196let isCodeGenOnly = 1;
33197let DecoderNamespace = "EXT_mmvec";
33198}
33199def V6_vmpybusv : HInst<
33200(outs HvxWR:$Vdd32),
33201(ins HvxVR:$Vu32, HvxVR:$Vv32),
33202"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
33203tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33204let Inst{7-5} = 0b110;
33205let Inst{13-13} = 0b0;
33206let Inst{31-21} = 0b00011100000;
33207let hasNewValue = 1;
33208let opNewValue = 0;
33209let DecoderNamespace = "EXT_mmvec";
33210}
33211def V6_vmpybusv_acc : HInst<
33212(outs HvxWR:$Vxx32),
33213(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33214"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
33215tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33216let Inst{7-5} = 0b110;
33217let Inst{13-13} = 0b1;
33218let Inst{31-21} = 0b00011100000;
33219let hasNewValue = 1;
33220let opNewValue = 0;
33221let isAccumulator = 1;
33222let DecoderNamespace = "EXT_mmvec";
33223let Constraints = "$Vxx32 = $Vxx32in";
33224}
33225def V6_vmpybusv_acc_alt : HInst<
33226(outs HvxWR:$Vxx32),
33227(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33228"$Vxx32 += vmpybus($Vu32,$Vv32)",
33229PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33230let hasNewValue = 1;
33231let opNewValue = 0;
33232let isAccumulator = 1;
33233let isPseudo = 1;
33234let isCodeGenOnly = 1;
33235let DecoderNamespace = "EXT_mmvec";
33236let Constraints = "$Vxx32 = $Vxx32in";
33237}
33238def V6_vmpybusv_alt : HInst<
33239(outs HvxWR:$Vdd32),
33240(ins HvxVR:$Vu32, HvxVR:$Vv32),
33241"$Vdd32 = vmpybus($Vu32,$Vv32)",
33242PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33243let hasNewValue = 1;
33244let opNewValue = 0;
33245let isPseudo = 1;
33246let isCodeGenOnly = 1;
33247let DecoderNamespace = "EXT_mmvec";
33248}
33249def V6_vmpybv : HInst<
33250(outs HvxWR:$Vdd32),
33251(ins HvxVR:$Vu32, HvxVR:$Vv32),
33252"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
33253tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33254let Inst{7-5} = 0b100;
33255let Inst{13-13} = 0b0;
33256let Inst{31-21} = 0b00011100000;
33257let hasNewValue = 1;
33258let opNewValue = 0;
33259let DecoderNamespace = "EXT_mmvec";
33260}
33261def V6_vmpybv_acc : HInst<
33262(outs HvxWR:$Vxx32),
33263(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33264"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
33265tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33266let Inst{7-5} = 0b100;
33267let Inst{13-13} = 0b1;
33268let Inst{31-21} = 0b00011100000;
33269let hasNewValue = 1;
33270let opNewValue = 0;
33271let isAccumulator = 1;
33272let DecoderNamespace = "EXT_mmvec";
33273let Constraints = "$Vxx32 = $Vxx32in";
33274}
33275def V6_vmpybv_acc_alt : HInst<
33276(outs HvxWR:$Vxx32),
33277(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33278"$Vxx32 += vmpyb($Vu32,$Vv32)",
33279PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33280let hasNewValue = 1;
33281let opNewValue = 0;
33282let isAccumulator = 1;
33283let isPseudo = 1;
33284let isCodeGenOnly = 1;
33285let DecoderNamespace = "EXT_mmvec";
33286let Constraints = "$Vxx32 = $Vxx32in";
33287}
33288def V6_vmpybv_alt : HInst<
33289(outs HvxWR:$Vdd32),
33290(ins HvxVR:$Vu32, HvxVR:$Vv32),
33291"$Vdd32 = vmpyb($Vu32,$Vv32)",
33292PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33293let hasNewValue = 1;
33294let opNewValue = 0;
33295let isPseudo = 1;
33296let isCodeGenOnly = 1;
33297let DecoderNamespace = "EXT_mmvec";
33298}
33299def V6_vmpyewuh : HInst<
33300(outs HvxVR:$Vd32),
33301(ins HvxVR:$Vu32, HvxVR:$Vv32),
33302"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
33303tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33304let Inst{7-5} = 0b101;
33305let Inst{13-13} = 0b0;
33306let Inst{31-21} = 0b00011111111;
33307let hasNewValue = 1;
33308let opNewValue = 0;
33309let DecoderNamespace = "EXT_mmvec";
33310}
33311def V6_vmpyewuh_64 : HInst<
33312(outs HvxWR:$Vdd32),
33313(ins HvxVR:$Vu32, HvxVR:$Vv32),
33314"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
33315tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
33316let Inst{7-5} = 0b110;
33317let Inst{13-13} = 0b0;
33318let Inst{31-21} = 0b00011110101;
33319let hasNewValue = 1;
33320let opNewValue = 0;
33321let DecoderNamespace = "EXT_mmvec";
33322}
33323def V6_vmpyewuh_alt : HInst<
33324(outs HvxVR:$Vd32),
33325(ins HvxVR:$Vu32, HvxVR:$Vv32),
33326"$Vd32 = vmpyewuh($Vu32,$Vv32)",
33327PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33328let hasNewValue = 1;
33329let opNewValue = 0;
33330let isPseudo = 1;
33331let isCodeGenOnly = 1;
33332let DecoderNamespace = "EXT_mmvec";
33333}
33334def V6_vmpyh : HInst<
33335(outs HvxWR:$Vdd32),
33336(ins HvxVR:$Vu32, IntRegs:$Rt32),
33337"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
33338tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
33339let Inst{7-5} = 0b000;
33340let Inst{13-13} = 0b0;
33341let Inst{31-21} = 0b00011001010;
33342let hasNewValue = 1;
33343let opNewValue = 0;
33344let DecoderNamespace = "EXT_mmvec";
33345}
33346def V6_vmpyh_acc : HInst<
33347(outs HvxWR:$Vxx32),
33348(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33349"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
33350tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
33351let Inst{7-5} = 0b110;
33352let Inst{13-13} = 0b1;
33353let Inst{31-21} = 0b00011001101;
33354let hasNewValue = 1;
33355let opNewValue = 0;
33356let isAccumulator = 1;
33357let DecoderNamespace = "EXT_mmvec";
33358let Constraints = "$Vxx32 = $Vxx32in";
33359}
33360def V6_vmpyh_acc_alt : HInst<
33361(outs HvxWR:$Vxx32),
33362(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33363"$Vxx32 += vmpyh($Vu32,$Rt32)",
33364PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
33365let hasNewValue = 1;
33366let opNewValue = 0;
33367let isAccumulator = 1;
33368let isPseudo = 1;
33369let isCodeGenOnly = 1;
33370let DecoderNamespace = "EXT_mmvec";
33371let Constraints = "$Vxx32 = $Vxx32in";
33372}
33373def V6_vmpyh_alt : HInst<
33374(outs HvxWR:$Vdd32),
33375(ins HvxVR:$Vu32, IntRegs:$Rt32),
33376"$Vdd32 = vmpyh($Vu32,$Rt32)",
33377PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33378let hasNewValue = 1;
33379let opNewValue = 0;
33380let isPseudo = 1;
33381let isCodeGenOnly = 1;
33382let DecoderNamespace = "EXT_mmvec";
33383}
33384def V6_vmpyhsat_acc : HInst<
33385(outs HvxWR:$Vxx32),
33386(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33387"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
33388tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
33389let Inst{7-5} = 0b000;
33390let Inst{13-13} = 0b1;
33391let Inst{31-21} = 0b00011001010;
33392let hasNewValue = 1;
33393let opNewValue = 0;
33394let isAccumulator = 1;
33395let DecoderNamespace = "EXT_mmvec";
33396let Constraints = "$Vxx32 = $Vxx32in";
33397}
33398def V6_vmpyhsat_acc_alt : HInst<
33399(outs HvxWR:$Vxx32),
33400(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33401"$Vxx32 += vmpyh($Vu32,$Rt32):sat",
33402PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33403let hasNewValue = 1;
33404let opNewValue = 0;
33405let isAccumulator = 1;
33406let isPseudo = 1;
33407let isCodeGenOnly = 1;
33408let DecoderNamespace = "EXT_mmvec";
33409let Constraints = "$Vxx32 = $Vxx32in";
33410}
33411def V6_vmpyhsrs : HInst<
33412(outs HvxVR:$Vd32),
33413(ins HvxVR:$Vu32, IntRegs:$Rt32),
33414"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
33415tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
33416let Inst{7-5} = 0b010;
33417let Inst{13-13} = 0b0;
33418let Inst{31-21} = 0b00011001010;
33419let hasNewValue = 1;
33420let opNewValue = 0;
33421let DecoderNamespace = "EXT_mmvec";
33422}
33423def V6_vmpyhsrs_alt : HInst<
33424(outs HvxVR:$Vd32),
33425(ins HvxVR:$Vu32, IntRegs:$Rt32),
33426"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
33427PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33428let hasNewValue = 1;
33429let opNewValue = 0;
33430let isPseudo = 1;
33431let isCodeGenOnly = 1;
33432let DecoderNamespace = "EXT_mmvec";
33433}
33434def V6_vmpyhss : HInst<
33435(outs HvxVR:$Vd32),
33436(ins HvxVR:$Vu32, IntRegs:$Rt32),
33437"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
33438tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
33439let Inst{7-5} = 0b001;
33440let Inst{13-13} = 0b0;
33441let Inst{31-21} = 0b00011001010;
33442let hasNewValue = 1;
33443let opNewValue = 0;
33444let DecoderNamespace = "EXT_mmvec";
33445}
33446def V6_vmpyhss_alt : HInst<
33447(outs HvxVR:$Vd32),
33448(ins HvxVR:$Vu32, IntRegs:$Rt32),
33449"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
33450PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33451let hasNewValue = 1;
33452let opNewValue = 0;
33453let isPseudo = 1;
33454let isCodeGenOnly = 1;
33455let DecoderNamespace = "EXT_mmvec";
33456}
33457def V6_vmpyhus : HInst<
33458(outs HvxWR:$Vdd32),
33459(ins HvxVR:$Vu32, HvxVR:$Vv32),
33460"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
33461tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33462let Inst{7-5} = 0b010;
33463let Inst{13-13} = 0b0;
33464let Inst{31-21} = 0b00011100001;
33465let hasNewValue = 1;
33466let opNewValue = 0;
33467let DecoderNamespace = "EXT_mmvec";
33468}
33469def V6_vmpyhus_acc : HInst<
33470(outs HvxWR:$Vxx32),
33471(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33472"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
33473tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33474let Inst{7-5} = 0b001;
33475let Inst{13-13} = 0b1;
33476let Inst{31-21} = 0b00011100001;
33477let hasNewValue = 1;
33478let opNewValue = 0;
33479let isAccumulator = 1;
33480let DecoderNamespace = "EXT_mmvec";
33481let Constraints = "$Vxx32 = $Vxx32in";
33482}
33483def V6_vmpyhus_acc_alt : HInst<
33484(outs HvxWR:$Vxx32),
33485(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33486"$Vxx32 += vmpyhus($Vu32,$Vv32)",
33487PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33488let hasNewValue = 1;
33489let opNewValue = 0;
33490let isAccumulator = 1;
33491let isPseudo = 1;
33492let isCodeGenOnly = 1;
33493let DecoderNamespace = "EXT_mmvec";
33494let Constraints = "$Vxx32 = $Vxx32in";
33495}
33496def V6_vmpyhus_alt : HInst<
33497(outs HvxWR:$Vdd32),
33498(ins HvxVR:$Vu32, HvxVR:$Vv32),
33499"$Vdd32 = vmpyhus($Vu32,$Vv32)",
33500PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33501let hasNewValue = 1;
33502let opNewValue = 0;
33503let isPseudo = 1;
33504let isCodeGenOnly = 1;
33505let DecoderNamespace = "EXT_mmvec";
33506}
33507def V6_vmpyhv : HInst<
33508(outs HvxWR:$Vdd32),
33509(ins HvxVR:$Vu32, HvxVR:$Vv32),
33510"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
33511tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
33512let Inst{7-5} = 0b111;
33513let Inst{13-13} = 0b0;
33514let Inst{31-21} = 0b00011100000;
33515let hasNewValue = 1;
33516let opNewValue = 0;
33517let DecoderNamespace = "EXT_mmvec";
33518}
33519def V6_vmpyhv_acc : HInst<
33520(outs HvxWR:$Vxx32),
33521(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33522"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
33523tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
33524let Inst{7-5} = 0b111;
33525let Inst{13-13} = 0b1;
33526let Inst{31-21} = 0b00011100000;
33527let hasNewValue = 1;
33528let opNewValue = 0;
33529let isAccumulator = 1;
33530let DecoderNamespace = "EXT_mmvec";
33531let Constraints = "$Vxx32 = $Vxx32in";
33532}
33533def V6_vmpyhv_acc_alt : HInst<
33534(outs HvxWR:$Vxx32),
33535(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33536"$Vxx32 += vmpyh($Vu32,$Vv32)",
33537PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33538let hasNewValue = 1;
33539let opNewValue = 0;
33540let isAccumulator = 1;
33541let isPseudo = 1;
33542let isCodeGenOnly = 1;
33543let DecoderNamespace = "EXT_mmvec";
33544let Constraints = "$Vxx32 = $Vxx32in";
33545}
33546def V6_vmpyhv_alt : HInst<
33547(outs HvxWR:$Vdd32),
33548(ins HvxVR:$Vu32, HvxVR:$Vv32),
33549"$Vdd32 = vmpyh($Vu32,$Vv32)",
33550PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33551let hasNewValue = 1;
33552let opNewValue = 0;
33553let isPseudo = 1;
33554let isCodeGenOnly = 1;
33555let DecoderNamespace = "EXT_mmvec";
33556}
33557def V6_vmpyhvsrs : HInst<
33558(outs HvxVR:$Vd32),
33559(ins HvxVR:$Vu32, HvxVR:$Vv32),
33560"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
33561tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33562let Inst{7-5} = 0b001;
33563let Inst{13-13} = 0b0;
33564let Inst{31-21} = 0b00011100001;
33565let hasNewValue = 1;
33566let opNewValue = 0;
33567let DecoderNamespace = "EXT_mmvec";
33568}
33569def V6_vmpyhvsrs_alt : HInst<
33570(outs HvxVR:$Vd32),
33571(ins HvxVR:$Vu32, HvxVR:$Vv32),
33572"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
33573PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33574let hasNewValue = 1;
33575let opNewValue = 0;
33576let isPseudo = 1;
33577let isCodeGenOnly = 1;
33578let DecoderNamespace = "EXT_mmvec";
33579}
33580def V6_vmpyieoh : HInst<
33581(outs HvxVR:$Vd32),
33582(ins HvxVR:$Vu32, HvxVR:$Vv32),
33583"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
33584tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
33585let Inst{7-5} = 0b000;
33586let Inst{13-13} = 0b0;
33587let Inst{31-21} = 0b00011111011;
33588let hasNewValue = 1;
33589let opNewValue = 0;
33590let DecoderNamespace = "EXT_mmvec";
33591}
33592def V6_vmpyiewh_acc : HInst<
33593(outs HvxVR:$Vx32),
33594(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33595"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
33596tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33597let Inst{7-5} = 0b000;
33598let Inst{13-13} = 0b1;
33599let Inst{31-21} = 0b00011100010;
33600let hasNewValue = 1;
33601let opNewValue = 0;
33602let isAccumulator = 1;
33603let DecoderNamespace = "EXT_mmvec";
33604let Constraints = "$Vx32 = $Vx32in";
33605}
33606def V6_vmpyiewh_acc_alt : HInst<
33607(outs HvxVR:$Vx32),
33608(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33609"$Vx32 += vmpyiewh($Vu32,$Vv32)",
33610PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33611let hasNewValue = 1;
33612let opNewValue = 0;
33613let isAccumulator = 1;
33614let isPseudo = 1;
33615let isCodeGenOnly = 1;
33616let DecoderNamespace = "EXT_mmvec";
33617let Constraints = "$Vx32 = $Vx32in";
33618}
33619def V6_vmpyiewuh : HInst<
33620(outs HvxVR:$Vd32),
33621(ins HvxVR:$Vu32, HvxVR:$Vv32),
33622"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
33623tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33624let Inst{7-5} = 0b000;
33625let Inst{13-13} = 0b0;
33626let Inst{31-21} = 0b00011111110;
33627let hasNewValue = 1;
33628let opNewValue = 0;
33629let DecoderNamespace = "EXT_mmvec";
33630}
33631def V6_vmpyiewuh_acc : HInst<
33632(outs HvxVR:$Vx32),
33633(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33634"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
33635tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33636let Inst{7-5} = 0b101;
33637let Inst{13-13} = 0b1;
33638let Inst{31-21} = 0b00011100001;
33639let hasNewValue = 1;
33640let opNewValue = 0;
33641let isAccumulator = 1;
33642let DecoderNamespace = "EXT_mmvec";
33643let Constraints = "$Vx32 = $Vx32in";
33644}
33645def V6_vmpyiewuh_acc_alt : HInst<
33646(outs HvxVR:$Vx32),
33647(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33648"$Vx32 += vmpyiewuh($Vu32,$Vv32)",
33649PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33650let hasNewValue = 1;
33651let opNewValue = 0;
33652let isAccumulator = 1;
33653let isPseudo = 1;
33654let isCodeGenOnly = 1;
33655let DecoderNamespace = "EXT_mmvec";
33656let Constraints = "$Vx32 = $Vx32in";
33657}
33658def V6_vmpyiewuh_alt : HInst<
33659(outs HvxVR:$Vd32),
33660(ins HvxVR:$Vu32, HvxVR:$Vv32),
33661"$Vd32 = vmpyiewuh($Vu32,$Vv32)",
33662PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33663let hasNewValue = 1;
33664let opNewValue = 0;
33665let isPseudo = 1;
33666let isCodeGenOnly = 1;
33667let DecoderNamespace = "EXT_mmvec";
33668}
33669def V6_vmpyih : HInst<
33670(outs HvxVR:$Vd32),
33671(ins HvxVR:$Vu32, HvxVR:$Vv32),
33672"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
33673tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33674let Inst{7-5} = 0b100;
33675let Inst{13-13} = 0b0;
33676let Inst{31-21} = 0b00011100001;
33677let hasNewValue = 1;
33678let opNewValue = 0;
33679let DecoderNamespace = "EXT_mmvec";
33680}
33681def V6_vmpyih_acc : HInst<
33682(outs HvxVR:$Vx32),
33683(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33684"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
33685tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33686let Inst{7-5} = 0b100;
33687let Inst{13-13} = 0b1;
33688let Inst{31-21} = 0b00011100001;
33689let hasNewValue = 1;
33690let opNewValue = 0;
33691let isAccumulator = 1;
33692let DecoderNamespace = "EXT_mmvec";
33693let Constraints = "$Vx32 = $Vx32in";
33694}
33695def V6_vmpyih_acc_alt : HInst<
33696(outs HvxVR:$Vx32),
33697(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33698"$Vx32 += vmpyih($Vu32,$Vv32)",
33699PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33700let hasNewValue = 1;
33701let opNewValue = 0;
33702let isAccumulator = 1;
33703let isPseudo = 1;
33704let isCodeGenOnly = 1;
33705let DecoderNamespace = "EXT_mmvec";
33706let Constraints = "$Vx32 = $Vx32in";
33707}
33708def V6_vmpyih_alt : HInst<
33709(outs HvxVR:$Vd32),
33710(ins HvxVR:$Vu32, HvxVR:$Vv32),
33711"$Vd32 = vmpyih($Vu32,$Vv32)",
33712PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33713let hasNewValue = 1;
33714let opNewValue = 0;
33715let isPseudo = 1;
33716let isCodeGenOnly = 1;
33717let DecoderNamespace = "EXT_mmvec";
33718}
33719def V6_vmpyihb : HInst<
33720(outs HvxVR:$Vd32),
33721(ins HvxVR:$Vu32, IntRegs:$Rt32),
33722"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
33723tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33724let Inst{7-5} = 0b000;
33725let Inst{13-13} = 0b0;
33726let Inst{31-21} = 0b00011001011;
33727let hasNewValue = 1;
33728let opNewValue = 0;
33729let DecoderNamespace = "EXT_mmvec";
33730}
33731def V6_vmpyihb_acc : HInst<
33732(outs HvxVR:$Vx32),
33733(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33734"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
33735tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33736let Inst{7-5} = 0b001;
33737let Inst{13-13} = 0b1;
33738let Inst{31-21} = 0b00011001011;
33739let hasNewValue = 1;
33740let opNewValue = 0;
33741let isAccumulator = 1;
33742let DecoderNamespace = "EXT_mmvec";
33743let Constraints = "$Vx32 = $Vx32in";
33744}
33745def V6_vmpyihb_acc_alt : HInst<
33746(outs HvxVR:$Vx32),
33747(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33748"$Vx32 += vmpyihb($Vu32,$Rt32)",
33749PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33750let hasNewValue = 1;
33751let opNewValue = 0;
33752let isAccumulator = 1;
33753let isPseudo = 1;
33754let isCodeGenOnly = 1;
33755let DecoderNamespace = "EXT_mmvec";
33756let Constraints = "$Vx32 = $Vx32in";
33757}
33758def V6_vmpyihb_alt : HInst<
33759(outs HvxVR:$Vd32),
33760(ins HvxVR:$Vu32, IntRegs:$Rt32),
33761"$Vd32 = vmpyihb($Vu32,$Rt32)",
33762PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33763let hasNewValue = 1;
33764let opNewValue = 0;
33765let isPseudo = 1;
33766let isCodeGenOnly = 1;
33767let DecoderNamespace = "EXT_mmvec";
33768}
33769def V6_vmpyiowh : HInst<
33770(outs HvxVR:$Vd32),
33771(ins HvxVR:$Vu32, HvxVR:$Vv32),
33772"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
33773tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33774let Inst{7-5} = 0b001;
33775let Inst{13-13} = 0b0;
33776let Inst{31-21} = 0b00011111110;
33777let hasNewValue = 1;
33778let opNewValue = 0;
33779let DecoderNamespace = "EXT_mmvec";
33780}
33781def V6_vmpyiowh_alt : HInst<
33782(outs HvxVR:$Vd32),
33783(ins HvxVR:$Vu32, HvxVR:$Vv32),
33784"$Vd32 = vmpyiowh($Vu32,$Vv32)",
33785PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33786let hasNewValue = 1;
33787let opNewValue = 0;
33788let isPseudo = 1;
33789let isCodeGenOnly = 1;
33790let DecoderNamespace = "EXT_mmvec";
33791}
33792def V6_vmpyiwb : HInst<
33793(outs HvxVR:$Vd32),
33794(ins HvxVR:$Vu32, IntRegs:$Rt32),
33795"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
33796tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33797let Inst{7-5} = 0b000;
33798let Inst{13-13} = 0b0;
33799let Inst{31-21} = 0b00011001101;
33800let hasNewValue = 1;
33801let opNewValue = 0;
33802let DecoderNamespace = "EXT_mmvec";
33803}
33804def V6_vmpyiwb_acc : HInst<
33805(outs HvxVR:$Vx32),
33806(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33807"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
33808tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33809let Inst{7-5} = 0b010;
33810let Inst{13-13} = 0b1;
33811let Inst{31-21} = 0b00011001010;
33812let hasNewValue = 1;
33813let opNewValue = 0;
33814let isAccumulator = 1;
33815let DecoderNamespace = "EXT_mmvec";
33816let Constraints = "$Vx32 = $Vx32in";
33817}
33818def V6_vmpyiwb_acc_alt : HInst<
33819(outs HvxVR:$Vx32),
33820(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33821"$Vx32 += vmpyiwb($Vu32,$Rt32)",
33822PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33823let hasNewValue = 1;
33824let opNewValue = 0;
33825let isAccumulator = 1;
33826let isPseudo = 1;
33827let isCodeGenOnly = 1;
33828let DecoderNamespace = "EXT_mmvec";
33829let Constraints = "$Vx32 = $Vx32in";
33830}
33831def V6_vmpyiwb_alt : HInst<
33832(outs HvxVR:$Vd32),
33833(ins HvxVR:$Vu32, IntRegs:$Rt32),
33834"$Vd32 = vmpyiwb($Vu32,$Rt32)",
33835PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33836let hasNewValue = 1;
33837let opNewValue = 0;
33838let isPseudo = 1;
33839let isCodeGenOnly = 1;
33840let DecoderNamespace = "EXT_mmvec";
33841}
33842def V6_vmpyiwh : HInst<
33843(outs HvxVR:$Vd32),
33844(ins HvxVR:$Vu32, IntRegs:$Rt32),
33845"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
33846tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
33847let Inst{7-5} = 0b111;
33848let Inst{13-13} = 0b0;
33849let Inst{31-21} = 0b00011001100;
33850let hasNewValue = 1;
33851let opNewValue = 0;
33852let DecoderNamespace = "EXT_mmvec";
33853}
33854def V6_vmpyiwh_acc : HInst<
33855(outs HvxVR:$Vx32),
33856(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33857"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
33858tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
33859let Inst{7-5} = 0b011;
33860let Inst{13-13} = 0b1;
33861let Inst{31-21} = 0b00011001010;
33862let hasNewValue = 1;
33863let opNewValue = 0;
33864let isAccumulator = 1;
33865let DecoderNamespace = "EXT_mmvec";
33866let Constraints = "$Vx32 = $Vx32in";
33867}
33868def V6_vmpyiwh_acc_alt : HInst<
33869(outs HvxVR:$Vx32),
33870(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33871"$Vx32 += vmpyiwh($Vu32,$Rt32)",
33872PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33873let hasNewValue = 1;
33874let opNewValue = 0;
33875let isAccumulator = 1;
33876let isPseudo = 1;
33877let isCodeGenOnly = 1;
33878let DecoderNamespace = "EXT_mmvec";
33879let Constraints = "$Vx32 = $Vx32in";
33880}
33881def V6_vmpyiwh_alt : HInst<
33882(outs HvxVR:$Vd32),
33883(ins HvxVR:$Vu32, IntRegs:$Rt32),
33884"$Vd32 = vmpyiwh($Vu32,$Rt32)",
33885PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33886let hasNewValue = 1;
33887let opNewValue = 0;
33888let isPseudo = 1;
33889let isCodeGenOnly = 1;
33890let DecoderNamespace = "EXT_mmvec";
33891}
33892def V6_vmpyiwub : HInst<
33893(outs HvxVR:$Vd32),
33894(ins HvxVR:$Vu32, IntRegs:$Rt32),
33895"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
33896tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
33897let Inst{7-5} = 0b110;
33898let Inst{13-13} = 0b0;
33899let Inst{31-21} = 0b00011001100;
33900let hasNewValue = 1;
33901let opNewValue = 0;
33902let DecoderNamespace = "EXT_mmvec";
33903}
33904def V6_vmpyiwub_acc : HInst<
33905(outs HvxVR:$Vx32),
33906(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33907"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
33908tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
33909let Inst{7-5} = 0b001;
33910let Inst{13-13} = 0b1;
33911let Inst{31-21} = 0b00011001100;
33912let hasNewValue = 1;
33913let opNewValue = 0;
33914let isAccumulator = 1;
33915let DecoderNamespace = "EXT_mmvec";
33916let Constraints = "$Vx32 = $Vx32in";
33917}
33918def V6_vmpyiwub_acc_alt : HInst<
33919(outs HvxVR:$Vx32),
33920(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33921"$Vx32 += vmpyiwub($Vu32,$Rt32)",
33922PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33923let hasNewValue = 1;
33924let opNewValue = 0;
33925let isAccumulator = 1;
33926let isPseudo = 1;
33927let isCodeGenOnly = 1;
33928let DecoderNamespace = "EXT_mmvec";
33929let Constraints = "$Vx32 = $Vx32in";
33930}
33931def V6_vmpyiwub_alt : HInst<
33932(outs HvxVR:$Vd32),
33933(ins HvxVR:$Vu32, IntRegs:$Rt32),
33934"$Vd32 = vmpyiwub($Vu32,$Rt32)",
33935PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33936let hasNewValue = 1;
33937let opNewValue = 0;
33938let isPseudo = 1;
33939let isCodeGenOnly = 1;
33940let DecoderNamespace = "EXT_mmvec";
33941}
33942def V6_vmpyowh : HInst<
33943(outs HvxVR:$Vd32),
33944(ins HvxVR:$Vu32, HvxVR:$Vv32),
33945"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
33946tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33947let Inst{7-5} = 0b111;
33948let Inst{13-13} = 0b0;
33949let Inst{31-21} = 0b00011111111;
33950let hasNewValue = 1;
33951let opNewValue = 0;
33952let DecoderNamespace = "EXT_mmvec";
33953}
33954def V6_vmpyowh_64_acc : HInst<
33955(outs HvxWR:$Vxx32),
33956(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33957"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
33958tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
33959let Inst{7-5} = 0b011;
33960let Inst{13-13} = 0b1;
33961let Inst{31-21} = 0b00011100001;
33962let hasNewValue = 1;
33963let opNewValue = 0;
33964let isAccumulator = 1;
33965let DecoderNamespace = "EXT_mmvec";
33966let Constraints = "$Vxx32 = $Vxx32in";
33967}
33968def V6_vmpyowh_alt : HInst<
33969(outs HvxVR:$Vd32),
33970(ins HvxVR:$Vu32, HvxVR:$Vv32),
33971"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
33972PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33973let hasNewValue = 1;
33974let opNewValue = 0;
33975let isPseudo = 1;
33976let isCodeGenOnly = 1;
33977let DecoderNamespace = "EXT_mmvec";
33978}
33979def V6_vmpyowh_rnd : HInst<
33980(outs HvxVR:$Vd32),
33981(ins HvxVR:$Vu32, HvxVR:$Vv32),
33982"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
33983tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
33984let Inst{7-5} = 0b000;
33985let Inst{13-13} = 0b0;
33986let Inst{31-21} = 0b00011111010;
33987let hasNewValue = 1;
33988let opNewValue = 0;
33989let DecoderNamespace = "EXT_mmvec";
33990}
33991def V6_vmpyowh_rnd_alt : HInst<
33992(outs HvxVR:$Vd32),
33993(ins HvxVR:$Vu32, HvxVR:$Vv32),
33994"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
33995PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33996let hasNewValue = 1;
33997let opNewValue = 0;
33998let isPseudo = 1;
33999let isCodeGenOnly = 1;
34000let DecoderNamespace = "EXT_mmvec";
34001}
34002def V6_vmpyowh_rnd_sacc : HInst<
34003(outs HvxVR:$Vx32),
34004(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34005"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
34006tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34007let Inst{7-5} = 0b111;
34008let Inst{13-13} = 0b1;
34009let Inst{31-21} = 0b00011100001;
34010let hasNewValue = 1;
34011let opNewValue = 0;
34012let isAccumulator = 1;
34013let DecoderNamespace = "EXT_mmvec";
34014let Constraints = "$Vx32 = $Vx32in";
34015}
34016def V6_vmpyowh_rnd_sacc_alt : HInst<
34017(outs HvxVR:$Vx32),
34018(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34019"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
34020PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34021let hasNewValue = 1;
34022let opNewValue = 0;
34023let isAccumulator = 1;
34024let isPseudo = 1;
34025let DecoderNamespace = "EXT_mmvec";
34026let Constraints = "$Vx32 = $Vx32in";
34027}
34028def V6_vmpyowh_sacc : HInst<
34029(outs HvxVR:$Vx32),
34030(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34031"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
34032tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34033let Inst{7-5} = 0b110;
34034let Inst{13-13} = 0b1;
34035let Inst{31-21} = 0b00011100001;
34036let hasNewValue = 1;
34037let opNewValue = 0;
34038let isAccumulator = 1;
34039let DecoderNamespace = "EXT_mmvec";
34040let Constraints = "$Vx32 = $Vx32in";
34041}
34042def V6_vmpyowh_sacc_alt : HInst<
34043(outs HvxVR:$Vx32),
34044(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34045"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
34046PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34047let hasNewValue = 1;
34048let opNewValue = 0;
34049let isAccumulator = 1;
34050let isPseudo = 1;
34051let DecoderNamespace = "EXT_mmvec";
34052let Constraints = "$Vx32 = $Vx32in";
34053}
34054def V6_vmpyub : HInst<
34055(outs HvxWR:$Vdd32),
34056(ins HvxVR:$Vu32, IntRegs:$Rt32),
34057"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
34058tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
34059let Inst{7-5} = 0b000;
34060let Inst{13-13} = 0b0;
34061let Inst{31-21} = 0b00011001110;
34062let hasNewValue = 1;
34063let opNewValue = 0;
34064let DecoderNamespace = "EXT_mmvec";
34065}
34066def V6_vmpyub_acc : HInst<
34067(outs HvxWR:$Vxx32),
34068(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34069"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
34070tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
34071let Inst{7-5} = 0b000;
34072let Inst{13-13} = 0b1;
34073let Inst{31-21} = 0b00011001100;
34074let hasNewValue = 1;
34075let opNewValue = 0;
34076let isAccumulator = 1;
34077let DecoderNamespace = "EXT_mmvec";
34078let Constraints = "$Vxx32 = $Vxx32in";
34079}
34080def V6_vmpyub_acc_alt : HInst<
34081(outs HvxWR:$Vxx32),
34082(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34083"$Vxx32 += vmpyub($Vu32,$Rt32)",
34084PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34085let hasNewValue = 1;
34086let opNewValue = 0;
34087let isAccumulator = 1;
34088let isPseudo = 1;
34089let isCodeGenOnly = 1;
34090let DecoderNamespace = "EXT_mmvec";
34091let Constraints = "$Vxx32 = $Vxx32in";
34092}
34093def V6_vmpyub_alt : HInst<
34094(outs HvxWR:$Vdd32),
34095(ins HvxVR:$Vu32, IntRegs:$Rt32),
34096"$Vdd32 = vmpyub($Vu32,$Rt32)",
34097PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34098let hasNewValue = 1;
34099let opNewValue = 0;
34100let isPseudo = 1;
34101let isCodeGenOnly = 1;
34102let DecoderNamespace = "EXT_mmvec";
34103}
34104def V6_vmpyubv : HInst<
34105(outs HvxWR:$Vdd32),
34106(ins HvxVR:$Vu32, HvxVR:$Vv32),
34107"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
34108tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34109let Inst{7-5} = 0b101;
34110let Inst{13-13} = 0b0;
34111let Inst{31-21} = 0b00011100000;
34112let hasNewValue = 1;
34113let opNewValue = 0;
34114let DecoderNamespace = "EXT_mmvec";
34115}
34116def V6_vmpyubv_acc : HInst<
34117(outs HvxWR:$Vxx32),
34118(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34119"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
34120tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34121let Inst{7-5} = 0b101;
34122let Inst{13-13} = 0b1;
34123let Inst{31-21} = 0b00011100000;
34124let hasNewValue = 1;
34125let opNewValue = 0;
34126let isAccumulator = 1;
34127let DecoderNamespace = "EXT_mmvec";
34128let Constraints = "$Vxx32 = $Vxx32in";
34129}
34130def V6_vmpyubv_acc_alt : HInst<
34131(outs HvxWR:$Vxx32),
34132(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34133"$Vxx32 += vmpyub($Vu32,$Vv32)",
34134PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34135let hasNewValue = 1;
34136let opNewValue = 0;
34137let isAccumulator = 1;
34138let isPseudo = 1;
34139let isCodeGenOnly = 1;
34140let DecoderNamespace = "EXT_mmvec";
34141let Constraints = "$Vxx32 = $Vxx32in";
34142}
34143def V6_vmpyubv_alt : HInst<
34144(outs HvxWR:$Vdd32),
34145(ins HvxVR:$Vu32, HvxVR:$Vv32),
34146"$Vdd32 = vmpyub($Vu32,$Vv32)",
34147PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34148let hasNewValue = 1;
34149let opNewValue = 0;
34150let isPseudo = 1;
34151let isCodeGenOnly = 1;
34152let DecoderNamespace = "EXT_mmvec";
34153}
34154def V6_vmpyuh : HInst<
34155(outs HvxWR:$Vdd32),
34156(ins HvxVR:$Vu32, IntRegs:$Rt32),
34157"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
34158tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
34159let Inst{7-5} = 0b011;
34160let Inst{13-13} = 0b0;
34161let Inst{31-21} = 0b00011001010;
34162let hasNewValue = 1;
34163let opNewValue = 0;
34164let DecoderNamespace = "EXT_mmvec";
34165}
34166def V6_vmpyuh_acc : HInst<
34167(outs HvxWR:$Vxx32),
34168(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34169"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
34170tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
34171let Inst{7-5} = 0b001;
34172let Inst{13-13} = 0b1;
34173let Inst{31-21} = 0b00011001010;
34174let hasNewValue = 1;
34175let opNewValue = 0;
34176let isAccumulator = 1;
34177let DecoderNamespace = "EXT_mmvec";
34178let Constraints = "$Vxx32 = $Vxx32in";
34179}
34180def V6_vmpyuh_acc_alt : HInst<
34181(outs HvxWR:$Vxx32),
34182(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34183"$Vxx32 += vmpyuh($Vu32,$Rt32)",
34184PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34185let hasNewValue = 1;
34186let opNewValue = 0;
34187let isAccumulator = 1;
34188let isPseudo = 1;
34189let isCodeGenOnly = 1;
34190let DecoderNamespace = "EXT_mmvec";
34191let Constraints = "$Vxx32 = $Vxx32in";
34192}
34193def V6_vmpyuh_alt : HInst<
34194(outs HvxWR:$Vdd32),
34195(ins HvxVR:$Vu32, IntRegs:$Rt32),
34196"$Vdd32 = vmpyuh($Vu32,$Rt32)",
34197PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34198let hasNewValue = 1;
34199let opNewValue = 0;
34200let isPseudo = 1;
34201let isCodeGenOnly = 1;
34202let DecoderNamespace = "EXT_mmvec";
34203}
34204def V6_vmpyuhe : HInst<
34205(outs HvxVR:$Vd32),
34206(ins HvxVR:$Vu32, IntRegs:$Rt32),
34207"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
34208tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
34209let Inst{7-5} = 0b010;
34210let Inst{13-13} = 0b0;
34211let Inst{31-21} = 0b00011001011;
34212let hasNewValue = 1;
34213let opNewValue = 0;
34214let DecoderNamespace = "EXT_mmvec";
34215}
34216def V6_vmpyuhe_acc : HInst<
34217(outs HvxVR:$Vx32),
34218(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34219"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
34220tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
34221let Inst{7-5} = 0b011;
34222let Inst{13-13} = 0b1;
34223let Inst{31-21} = 0b00011001100;
34224let hasNewValue = 1;
34225let opNewValue = 0;
34226let isAccumulator = 1;
34227let DecoderNamespace = "EXT_mmvec";
34228let Constraints = "$Vx32 = $Vx32in";
34229}
34230def V6_vmpyuhv : HInst<
34231(outs HvxWR:$Vdd32),
34232(ins HvxVR:$Vu32, HvxVR:$Vv32),
34233"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
34234tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34235let Inst{7-5} = 0b000;
34236let Inst{13-13} = 0b0;
34237let Inst{31-21} = 0b00011100001;
34238let hasNewValue = 1;
34239let opNewValue = 0;
34240let DecoderNamespace = "EXT_mmvec";
34241}
34242def V6_vmpyuhv_acc : HInst<
34243(outs HvxWR:$Vxx32),
34244(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34245"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
34246tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34247let Inst{7-5} = 0b000;
34248let Inst{13-13} = 0b1;
34249let Inst{31-21} = 0b00011100001;
34250let hasNewValue = 1;
34251let opNewValue = 0;
34252let isAccumulator = 1;
34253let DecoderNamespace = "EXT_mmvec";
34254let Constraints = "$Vxx32 = $Vxx32in";
34255}
34256def V6_vmpyuhv_acc_alt : HInst<
34257(outs HvxWR:$Vxx32),
34258(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34259"$Vxx32 += vmpyuh($Vu32,$Vv32)",
34260PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34261let hasNewValue = 1;
34262let opNewValue = 0;
34263let isAccumulator = 1;
34264let isPseudo = 1;
34265let isCodeGenOnly = 1;
34266let DecoderNamespace = "EXT_mmvec";
34267let Constraints = "$Vxx32 = $Vxx32in";
34268}
34269def V6_vmpyuhv_alt : HInst<
34270(outs HvxWR:$Vdd32),
34271(ins HvxVR:$Vu32, HvxVR:$Vv32),
34272"$Vdd32 = vmpyuh($Vu32,$Vv32)",
34273PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34274let hasNewValue = 1;
34275let opNewValue = 0;
34276let isPseudo = 1;
34277let isCodeGenOnly = 1;
34278let DecoderNamespace = "EXT_mmvec";
34279}
34280def V6_vmux : HInst<
34281(outs HvxVR:$Vd32),
34282(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
34283"$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
34284tc_257f6f7c, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
34285let Inst{7-7} = 0b0;
34286let Inst{13-13} = 0b1;
34287let Inst{31-21} = 0b00011110111;
34288let hasNewValue = 1;
34289let opNewValue = 0;
34290let DecoderNamespace = "EXT_mmvec";
34291}
34292def V6_vnavgb : HInst<
34293(outs HvxVR:$Vd32),
34294(ins HvxVR:$Vu32, HvxVR:$Vv32),
34295"$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
34296tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
34297let Inst{7-5} = 0b110;
34298let Inst{13-13} = 0b1;
34299let Inst{31-21} = 0b00011111000;
34300let hasNewValue = 1;
34301let opNewValue = 0;
34302let DecoderNamespace = "EXT_mmvec";
34303}
34304def V6_vnavgb_alt : HInst<
34305(outs HvxVR:$Vd32),
34306(ins HvxVR:$Vu32, HvxVR:$Vv32),
34307"$Vd32 = vnavgb($Vu32,$Vv32)",
34308PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34309let hasNewValue = 1;
34310let opNewValue = 0;
34311let isPseudo = 1;
34312let isCodeGenOnly = 1;
34313let DecoderNamespace = "EXT_mmvec";
34314}
34315def V6_vnavgh : HInst<
34316(outs HvxVR:$Vd32),
34317(ins HvxVR:$Vu32, HvxVR:$Vv32),
34318"$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
34319tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34320let Inst{7-5} = 0b001;
34321let Inst{13-13} = 0b0;
34322let Inst{31-21} = 0b00011100111;
34323let hasNewValue = 1;
34324let opNewValue = 0;
34325let DecoderNamespace = "EXT_mmvec";
34326}
34327def V6_vnavgh_alt : HInst<
34328(outs HvxVR:$Vd32),
34329(ins HvxVR:$Vu32, HvxVR:$Vv32),
34330"$Vd32 = vnavgh($Vu32,$Vv32)",
34331PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34332let hasNewValue = 1;
34333let opNewValue = 0;
34334let isPseudo = 1;
34335let isCodeGenOnly = 1;
34336let DecoderNamespace = "EXT_mmvec";
34337}
34338def V6_vnavgub : HInst<
34339(outs HvxVR:$Vd32),
34340(ins HvxVR:$Vu32, HvxVR:$Vv32),
34341"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
34342tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34343let Inst{7-5} = 0b000;
34344let Inst{13-13} = 0b0;
34345let Inst{31-21} = 0b00011100111;
34346let hasNewValue = 1;
34347let opNewValue = 0;
34348let DecoderNamespace = "EXT_mmvec";
34349}
34350def V6_vnavgub_alt : HInst<
34351(outs HvxVR:$Vd32),
34352(ins HvxVR:$Vu32, HvxVR:$Vv32),
34353"$Vd32 = vnavgub($Vu32,$Vv32)",
34354PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34355let hasNewValue = 1;
34356let opNewValue = 0;
34357let isPseudo = 1;
34358let isCodeGenOnly = 1;
34359let DecoderNamespace = "EXT_mmvec";
34360}
34361def V6_vnavgw : HInst<
34362(outs HvxVR:$Vd32),
34363(ins HvxVR:$Vu32, HvxVR:$Vv32),
34364"$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
34365tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34366let Inst{7-5} = 0b010;
34367let Inst{13-13} = 0b0;
34368let Inst{31-21} = 0b00011100111;
34369let hasNewValue = 1;
34370let opNewValue = 0;
34371let DecoderNamespace = "EXT_mmvec";
34372}
34373def V6_vnavgw_alt : HInst<
34374(outs HvxVR:$Vd32),
34375(ins HvxVR:$Vu32, HvxVR:$Vv32),
34376"$Vd32 = vnavgw($Vu32,$Vv32)",
34377PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34378let hasNewValue = 1;
34379let opNewValue = 0;
34380let isPseudo = 1;
34381let isCodeGenOnly = 1;
34382let DecoderNamespace = "EXT_mmvec";
34383}
34384def V6_vnccombine : HInst<
34385(outs HvxWR:$Vdd32),
34386(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
34387"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
34388tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
34389let Inst{7-7} = 0b0;
34390let Inst{13-13} = 0b0;
34391let Inst{31-21} = 0b00011010010;
34392let isPredicated = 1;
34393let isPredicatedFalse = 1;
34394let hasNewValue = 1;
34395let opNewValue = 0;
34396let DecoderNamespace = "EXT_mmvec";
34397}
34398def V6_vncmov : HInst<
34399(outs HvxVR:$Vd32),
34400(ins PredRegs:$Ps4, HvxVR:$Vu32),
34401"if (!$Ps4) $Vd32 = $Vu32",
34402tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
34403let Inst{7-7} = 0b0;
34404let Inst{13-13} = 0b0;
34405let Inst{31-16} = 0b0001101000100000;
34406let isPredicated = 1;
34407let isPredicatedFalse = 1;
34408let hasNewValue = 1;
34409let opNewValue = 0;
34410let DecoderNamespace = "EXT_mmvec";
34411}
34412def V6_vnormamth : HInst<
34413(outs HvxVR:$Vd32),
34414(ins HvxVR:$Vu32),
34415"$Vd32.h = vnormamt($Vu32.h)",
34416tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
34417let Inst{7-5} = 0b101;
34418let Inst{13-13} = 0b0;
34419let Inst{31-16} = 0b0001111000000011;
34420let hasNewValue = 1;
34421let opNewValue = 0;
34422let DecoderNamespace = "EXT_mmvec";
34423}
34424def V6_vnormamth_alt : HInst<
34425(outs HvxVR:$Vd32),
34426(ins HvxVR:$Vu32),
34427"$Vd32 = vnormamth($Vu32)",
34428PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34429let hasNewValue = 1;
34430let opNewValue = 0;
34431let isPseudo = 1;
34432let isCodeGenOnly = 1;
34433let DecoderNamespace = "EXT_mmvec";
34434}
34435def V6_vnormamtw : HInst<
34436(outs HvxVR:$Vd32),
34437(ins HvxVR:$Vu32),
34438"$Vd32.w = vnormamt($Vu32.w)",
34439tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
34440let Inst{7-5} = 0b100;
34441let Inst{13-13} = 0b0;
34442let Inst{31-16} = 0b0001111000000011;
34443let hasNewValue = 1;
34444let opNewValue = 0;
34445let DecoderNamespace = "EXT_mmvec";
34446}
34447def V6_vnormamtw_alt : HInst<
34448(outs HvxVR:$Vd32),
34449(ins HvxVR:$Vu32),
34450"$Vd32 = vnormamtw($Vu32)",
34451PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34452let hasNewValue = 1;
34453let opNewValue = 0;
34454let isPseudo = 1;
34455let isCodeGenOnly = 1;
34456let DecoderNamespace = "EXT_mmvec";
34457}
34458def V6_vnot : HInst<
34459(outs HvxVR:$Vd32),
34460(ins HvxVR:$Vu32),
34461"$Vd32 = vnot($Vu32)",
34462tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
34463let Inst{7-5} = 0b100;
34464let Inst{13-13} = 0b0;
34465let Inst{31-16} = 0b0001111000000000;
34466let hasNewValue = 1;
34467let opNewValue = 0;
34468let DecoderNamespace = "EXT_mmvec";
34469}
34470def V6_vor : HInst<
34471(outs HvxVR:$Vd32),
34472(ins HvxVR:$Vu32, HvxVR:$Vv32),
34473"$Vd32 = vor($Vu32,$Vv32)",
34474tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34475let Inst{7-5} = 0b110;
34476let Inst{13-13} = 0b0;
34477let Inst{31-21} = 0b00011100001;
34478let hasNewValue = 1;
34479let opNewValue = 0;
34480let DecoderNamespace = "EXT_mmvec";
34481}
34482def V6_vpackeb : HInst<
34483(outs HvxVR:$Vd32),
34484(ins HvxVR:$Vu32, HvxVR:$Vv32),
34485"$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
34486tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34487let Inst{7-5} = 0b010;
34488let Inst{13-13} = 0b0;
34489let Inst{31-21} = 0b00011111110;
34490let hasNewValue = 1;
34491let opNewValue = 0;
34492let DecoderNamespace = "EXT_mmvec";
34493}
34494def V6_vpackeb_alt : HInst<
34495(outs HvxVR:$Vd32),
34496(ins HvxVR:$Vu32, HvxVR:$Vv32),
34497"$Vd32 = vpackeb($Vu32,$Vv32)",
34498PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34499let hasNewValue = 1;
34500let opNewValue = 0;
34501let isPseudo = 1;
34502let isCodeGenOnly = 1;
34503let DecoderNamespace = "EXT_mmvec";
34504}
34505def V6_vpackeh : HInst<
34506(outs HvxVR:$Vd32),
34507(ins HvxVR:$Vu32, HvxVR:$Vv32),
34508"$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
34509tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34510let Inst{7-5} = 0b011;
34511let Inst{13-13} = 0b0;
34512let Inst{31-21} = 0b00011111110;
34513let hasNewValue = 1;
34514let opNewValue = 0;
34515let DecoderNamespace = "EXT_mmvec";
34516}
34517def V6_vpackeh_alt : HInst<
34518(outs HvxVR:$Vd32),
34519(ins HvxVR:$Vu32, HvxVR:$Vv32),
34520"$Vd32 = vpackeh($Vu32,$Vv32)",
34521PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34522let hasNewValue = 1;
34523let opNewValue = 0;
34524let isPseudo = 1;
34525let isCodeGenOnly = 1;
34526let DecoderNamespace = "EXT_mmvec";
34527}
34528def V6_vpackhb_sat : HInst<
34529(outs HvxVR:$Vd32),
34530(ins HvxVR:$Vu32, HvxVR:$Vv32),
34531"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
34532tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34533let Inst{7-5} = 0b110;
34534let Inst{13-13} = 0b0;
34535let Inst{31-21} = 0b00011111110;
34536let hasNewValue = 1;
34537let opNewValue = 0;
34538let DecoderNamespace = "EXT_mmvec";
34539}
34540def V6_vpackhb_sat_alt : HInst<
34541(outs HvxVR:$Vd32),
34542(ins HvxVR:$Vu32, HvxVR:$Vv32),
34543"$Vd32 = vpackhb($Vu32,$Vv32):sat",
34544PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34545let hasNewValue = 1;
34546let opNewValue = 0;
34547let isPseudo = 1;
34548let isCodeGenOnly = 1;
34549let DecoderNamespace = "EXT_mmvec";
34550}
34551def V6_vpackhub_sat : HInst<
34552(outs HvxVR:$Vd32),
34553(ins HvxVR:$Vu32, HvxVR:$Vv32),
34554"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
34555tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34556let Inst{7-5} = 0b101;
34557let Inst{13-13} = 0b0;
34558let Inst{31-21} = 0b00011111110;
34559let hasNewValue = 1;
34560let opNewValue = 0;
34561let DecoderNamespace = "EXT_mmvec";
34562}
34563def V6_vpackhub_sat_alt : HInst<
34564(outs HvxVR:$Vd32),
34565(ins HvxVR:$Vu32, HvxVR:$Vv32),
34566"$Vd32 = vpackhub($Vu32,$Vv32):sat",
34567PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34568let hasNewValue = 1;
34569let opNewValue = 0;
34570let isPseudo = 1;
34571let isCodeGenOnly = 1;
34572let DecoderNamespace = "EXT_mmvec";
34573}
34574def V6_vpackob : HInst<
34575(outs HvxVR:$Vd32),
34576(ins HvxVR:$Vu32, HvxVR:$Vv32),
34577"$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
34578tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34579let Inst{7-5} = 0b001;
34580let Inst{13-13} = 0b0;
34581let Inst{31-21} = 0b00011111111;
34582let hasNewValue = 1;
34583let opNewValue = 0;
34584let DecoderNamespace = "EXT_mmvec";
34585}
34586def V6_vpackob_alt : HInst<
34587(outs HvxVR:$Vd32),
34588(ins HvxVR:$Vu32, HvxVR:$Vv32),
34589"$Vd32 = vpackob($Vu32,$Vv32)",
34590PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34591let hasNewValue = 1;
34592let opNewValue = 0;
34593let isPseudo = 1;
34594let isCodeGenOnly = 1;
34595let DecoderNamespace = "EXT_mmvec";
34596}
34597def V6_vpackoh : HInst<
34598(outs HvxVR:$Vd32),
34599(ins HvxVR:$Vu32, HvxVR:$Vv32),
34600"$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
34601tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34602let Inst{7-5} = 0b010;
34603let Inst{13-13} = 0b0;
34604let Inst{31-21} = 0b00011111111;
34605let hasNewValue = 1;
34606let opNewValue = 0;
34607let DecoderNamespace = "EXT_mmvec";
34608}
34609def V6_vpackoh_alt : HInst<
34610(outs HvxVR:$Vd32),
34611(ins HvxVR:$Vu32, HvxVR:$Vv32),
34612"$Vd32 = vpackoh($Vu32,$Vv32)",
34613PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34614let hasNewValue = 1;
34615let opNewValue = 0;
34616let isPseudo = 1;
34617let isCodeGenOnly = 1;
34618let DecoderNamespace = "EXT_mmvec";
34619}
34620def V6_vpackwh_sat : HInst<
34621(outs HvxVR:$Vd32),
34622(ins HvxVR:$Vu32, HvxVR:$Vv32),
34623"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
34624tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34625let Inst{7-5} = 0b000;
34626let Inst{13-13} = 0b0;
34627let Inst{31-21} = 0b00011111111;
34628let hasNewValue = 1;
34629let opNewValue = 0;
34630let DecoderNamespace = "EXT_mmvec";
34631}
34632def V6_vpackwh_sat_alt : HInst<
34633(outs HvxVR:$Vd32),
34634(ins HvxVR:$Vu32, HvxVR:$Vv32),
34635"$Vd32 = vpackwh($Vu32,$Vv32):sat",
34636PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34637let hasNewValue = 1;
34638let opNewValue = 0;
34639let isPseudo = 1;
34640let isCodeGenOnly = 1;
34641let DecoderNamespace = "EXT_mmvec";
34642}
34643def V6_vpackwuh_sat : HInst<
34644(outs HvxVR:$Vd32),
34645(ins HvxVR:$Vu32, HvxVR:$Vv32),
34646"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
34647tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34648let Inst{7-5} = 0b111;
34649let Inst{13-13} = 0b0;
34650let Inst{31-21} = 0b00011111110;
34651let hasNewValue = 1;
34652let opNewValue = 0;
34653let DecoderNamespace = "EXT_mmvec";
34654}
34655def V6_vpackwuh_sat_alt : HInst<
34656(outs HvxVR:$Vd32),
34657(ins HvxVR:$Vu32, HvxVR:$Vv32),
34658"$Vd32 = vpackwuh($Vu32,$Vv32):sat",
34659PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34660let hasNewValue = 1;
34661let opNewValue = 0;
34662let isPseudo = 1;
34663let isCodeGenOnly = 1;
34664let DecoderNamespace = "EXT_mmvec";
34665}
34666def V6_vpopcounth : HInst<
34667(outs HvxVR:$Vd32),
34668(ins HvxVR:$Vu32),
34669"$Vd32.h = vpopcount($Vu32.h)",
34670tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
34671let Inst{7-5} = 0b110;
34672let Inst{13-13} = 0b0;
34673let Inst{31-16} = 0b0001111000000010;
34674let hasNewValue = 1;
34675let opNewValue = 0;
34676let DecoderNamespace = "EXT_mmvec";
34677}
34678def V6_vpopcounth_alt : HInst<
34679(outs HvxVR:$Vd32),
34680(ins HvxVR:$Vu32),
34681"$Vd32 = vpopcounth($Vu32)",
34682PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34683let hasNewValue = 1;
34684let opNewValue = 0;
34685let isPseudo = 1;
34686let isCodeGenOnly = 1;
34687let DecoderNamespace = "EXT_mmvec";
34688}
34689def V6_vprefixqb : HInst<
34690(outs HvxVR:$Vd32),
34691(ins HvxQR:$Qv4),
34692"$Vd32.b = prefixsum($Qv4)",
34693tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
34694let Inst{13-5} = 0b100000010;
34695let Inst{21-16} = 0b000011;
34696let Inst{31-24} = 0b00011110;
34697let hasNewValue = 1;
34698let opNewValue = 0;
34699let DecoderNamespace = "EXT_mmvec";
34700}
34701def V6_vprefixqh : HInst<
34702(outs HvxVR:$Vd32),
34703(ins HvxQR:$Qv4),
34704"$Vd32.h = prefixsum($Qv4)",
34705tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
34706let Inst{13-5} = 0b100001010;
34707let Inst{21-16} = 0b000011;
34708let Inst{31-24} = 0b00011110;
34709let hasNewValue = 1;
34710let opNewValue = 0;
34711let DecoderNamespace = "EXT_mmvec";
34712}
34713def V6_vprefixqw : HInst<
34714(outs HvxVR:$Vd32),
34715(ins HvxQR:$Qv4),
34716"$Vd32.w = prefixsum($Qv4)",
34717tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
34718let Inst{13-5} = 0b100010010;
34719let Inst{21-16} = 0b000011;
34720let Inst{31-24} = 0b00011110;
34721let hasNewValue = 1;
34722let opNewValue = 0;
34723let DecoderNamespace = "EXT_mmvec";
34724}
34725def V6_vrdelta : HInst<
34726(outs HvxVR:$Vd32),
34727(ins HvxVR:$Vu32, HvxVR:$Vv32),
34728"$Vd32 = vrdelta($Vu32,$Vv32)",
34729tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
34730let Inst{7-5} = 0b011;
34731let Inst{13-13} = 0b0;
34732let Inst{31-21} = 0b00011111001;
34733let hasNewValue = 1;
34734let opNewValue = 0;
34735let DecoderNamespace = "EXT_mmvec";
34736}
34737def V6_vrmpybub_rtt : HInst<
34738(outs HvxWR:$Vdd32),
34739(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34740"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
34741tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
34742let Inst{7-5} = 0b101;
34743let Inst{13-13} = 0b0;
34744let Inst{31-21} = 0b00011001110;
34745let hasNewValue = 1;
34746let opNewValue = 0;
34747let DecoderNamespace = "EXT_mmvec";
34748}
34749def V6_vrmpybub_rtt_acc : HInst<
34750(outs HvxWR:$Vxx32),
34751(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34752"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
34753tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
34754let Inst{7-5} = 0b000;
34755let Inst{13-13} = 0b1;
34756let Inst{31-21} = 0b00011001101;
34757let hasNewValue = 1;
34758let opNewValue = 0;
34759let isAccumulator = 1;
34760let DecoderNamespace = "EXT_mmvec";
34761let Constraints = "$Vxx32 = $Vxx32in";
34762}
34763def V6_vrmpybub_rtt_acc_alt : HInst<
34764(outs HvxWR:$Vxx32),
34765(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34766"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
34767PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34768let hasNewValue = 1;
34769let opNewValue = 0;
34770let isAccumulator = 1;
34771let isPseudo = 1;
34772let isCodeGenOnly = 1;
34773let DecoderNamespace = "EXT_mmvec";
34774let Constraints = "$Vxx32 = $Vxx32in";
34775}
34776def V6_vrmpybub_rtt_alt : HInst<
34777(outs HvxWR:$Vdd32),
34778(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34779"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
34780PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34781let hasNewValue = 1;
34782let opNewValue = 0;
34783let isPseudo = 1;
34784let isCodeGenOnly = 1;
34785let DecoderNamespace = "EXT_mmvec";
34786}
34787def V6_vrmpybus : HInst<
34788(outs HvxVR:$Vd32),
34789(ins HvxVR:$Vu32, IntRegs:$Rt32),
34790"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
34791tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34792let Inst{7-5} = 0b100;
34793let Inst{13-13} = 0b0;
34794let Inst{31-21} = 0b00011001000;
34795let hasNewValue = 1;
34796let opNewValue = 0;
34797let DecoderNamespace = "EXT_mmvec";
34798}
34799def V6_vrmpybus_acc : HInst<
34800(outs HvxVR:$Vx32),
34801(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34802"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
34803tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
34804let Inst{7-5} = 0b101;
34805let Inst{13-13} = 0b1;
34806let Inst{31-21} = 0b00011001000;
34807let hasNewValue = 1;
34808let opNewValue = 0;
34809let isAccumulator = 1;
34810let DecoderNamespace = "EXT_mmvec";
34811let Constraints = "$Vx32 = $Vx32in";
34812}
34813def V6_vrmpybus_acc_alt : HInst<
34814(outs HvxVR:$Vx32),
34815(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34816"$Vx32 += vrmpybus($Vu32,$Rt32)",
34817PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34818let hasNewValue = 1;
34819let opNewValue = 0;
34820let isAccumulator = 1;
34821let isPseudo = 1;
34822let isCodeGenOnly = 1;
34823let DecoderNamespace = "EXT_mmvec";
34824let Constraints = "$Vx32 = $Vx32in";
34825}
34826def V6_vrmpybus_alt : HInst<
34827(outs HvxVR:$Vd32),
34828(ins HvxVR:$Vu32, IntRegs:$Rt32),
34829"$Vd32 = vrmpybus($Vu32,$Rt32)",
34830PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34831let hasNewValue = 1;
34832let opNewValue = 0;
34833let isPseudo = 1;
34834let isCodeGenOnly = 1;
34835let DecoderNamespace = "EXT_mmvec";
34836}
34837def V6_vrmpybusi : HInst<
34838(outs HvxWR:$Vdd32),
34839(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34840"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
34841tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
34842let Inst{7-6} = 0b10;
34843let Inst{13-13} = 0b0;
34844let Inst{31-21} = 0b00011001010;
34845let hasNewValue = 1;
34846let opNewValue = 0;
34847let DecoderNamespace = "EXT_mmvec";
34848}
34849def V6_vrmpybusi_acc : HInst<
34850(outs HvxWR:$Vxx32),
34851(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34852"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
34853tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
34854let Inst{7-6} = 0b10;
34855let Inst{13-13} = 0b1;
34856let Inst{31-21} = 0b00011001010;
34857let hasNewValue = 1;
34858let opNewValue = 0;
34859let isAccumulator = 1;
34860let DecoderNamespace = "EXT_mmvec";
34861let Constraints = "$Vxx32 = $Vxx32in";
34862}
34863def V6_vrmpybusi_acc_alt : HInst<
34864(outs HvxWR:$Vxx32),
34865(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34866"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
34867PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34868let hasNewValue = 1;
34869let opNewValue = 0;
34870let isAccumulator = 1;
34871let isPseudo = 1;
34872let isCodeGenOnly = 1;
34873let DecoderNamespace = "EXT_mmvec";
34874let Constraints = "$Vxx32 = $Vxx32in";
34875}
34876def V6_vrmpybusi_alt : HInst<
34877(outs HvxWR:$Vdd32),
34878(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
34879"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
34880PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34881let hasNewValue = 1;
34882let opNewValue = 0;
34883let isPseudo = 1;
34884let isCodeGenOnly = 1;
34885let DecoderNamespace = "EXT_mmvec";
34886}
34887def V6_vrmpybusv : HInst<
34888(outs HvxVR:$Vd32),
34889(ins HvxVR:$Vu32, HvxVR:$Vv32),
34890"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
34891tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
34892let Inst{7-5} = 0b010;
34893let Inst{13-13} = 0b0;
34894let Inst{31-21} = 0b00011100000;
34895let hasNewValue = 1;
34896let opNewValue = 0;
34897let DecoderNamespace = "EXT_mmvec";
34898}
34899def V6_vrmpybusv_acc : HInst<
34900(outs HvxVR:$Vx32),
34901(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34902"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
34903tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34904let Inst{7-5} = 0b010;
34905let Inst{13-13} = 0b1;
34906let Inst{31-21} = 0b00011100000;
34907let hasNewValue = 1;
34908let opNewValue = 0;
34909let isAccumulator = 1;
34910let DecoderNamespace = "EXT_mmvec";
34911let Constraints = "$Vx32 = $Vx32in";
34912}
34913def V6_vrmpybusv_acc_alt : HInst<
34914(outs HvxVR:$Vx32),
34915(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34916"$Vx32 += vrmpybus($Vu32,$Vv32)",
34917PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34918let hasNewValue = 1;
34919let opNewValue = 0;
34920let isAccumulator = 1;
34921let isPseudo = 1;
34922let isCodeGenOnly = 1;
34923let DecoderNamespace = "EXT_mmvec";
34924let Constraints = "$Vx32 = $Vx32in";
34925}
34926def V6_vrmpybusv_alt : HInst<
34927(outs HvxVR:$Vd32),
34928(ins HvxVR:$Vu32, HvxVR:$Vv32),
34929"$Vd32 = vrmpybus($Vu32,$Vv32)",
34930PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34931let hasNewValue = 1;
34932let opNewValue = 0;
34933let isPseudo = 1;
34934let isCodeGenOnly = 1;
34935let DecoderNamespace = "EXT_mmvec";
34936}
34937def V6_vrmpybv : HInst<
34938(outs HvxVR:$Vd32),
34939(ins HvxVR:$Vu32, HvxVR:$Vv32),
34940"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
34941tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
34942let Inst{7-5} = 0b001;
34943let Inst{13-13} = 0b0;
34944let Inst{31-21} = 0b00011100000;
34945let hasNewValue = 1;
34946let opNewValue = 0;
34947let DecoderNamespace = "EXT_mmvec";
34948}
34949def V6_vrmpybv_acc : HInst<
34950(outs HvxVR:$Vx32),
34951(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34952"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
34953tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34954let Inst{7-5} = 0b001;
34955let Inst{13-13} = 0b1;
34956let Inst{31-21} = 0b00011100000;
34957let hasNewValue = 1;
34958let opNewValue = 0;
34959let isAccumulator = 1;
34960let DecoderNamespace = "EXT_mmvec";
34961let Constraints = "$Vx32 = $Vx32in";
34962}
34963def V6_vrmpybv_acc_alt : HInst<
34964(outs HvxVR:$Vx32),
34965(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34966"$Vx32 += vrmpyb($Vu32,$Vv32)",
34967PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34968let hasNewValue = 1;
34969let opNewValue = 0;
34970let isAccumulator = 1;
34971let isPseudo = 1;
34972let isCodeGenOnly = 1;
34973let DecoderNamespace = "EXT_mmvec";
34974let Constraints = "$Vx32 = $Vx32in";
34975}
34976def V6_vrmpybv_alt : HInst<
34977(outs HvxVR:$Vd32),
34978(ins HvxVR:$Vu32, HvxVR:$Vv32),
34979"$Vd32 = vrmpyb($Vu32,$Vv32)",
34980PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34981let hasNewValue = 1;
34982let opNewValue = 0;
34983let isPseudo = 1;
34984let isCodeGenOnly = 1;
34985let DecoderNamespace = "EXT_mmvec";
34986}
34987def V6_vrmpyub : HInst<
34988(outs HvxVR:$Vd32),
34989(ins HvxVR:$Vu32, IntRegs:$Rt32),
34990"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
34991tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34992let Inst{7-5} = 0b011;
34993let Inst{13-13} = 0b0;
34994let Inst{31-21} = 0b00011001000;
34995let hasNewValue = 1;
34996let opNewValue = 0;
34997let DecoderNamespace = "EXT_mmvec";
34998}
34999def V6_vrmpyub_acc : HInst<
35000(outs HvxVR:$Vx32),
35001(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35002"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
35003tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
35004let Inst{7-5} = 0b100;
35005let Inst{13-13} = 0b1;
35006let Inst{31-21} = 0b00011001000;
35007let hasNewValue = 1;
35008let opNewValue = 0;
35009let isAccumulator = 1;
35010let DecoderNamespace = "EXT_mmvec";
35011let Constraints = "$Vx32 = $Vx32in";
35012}
35013def V6_vrmpyub_acc_alt : HInst<
35014(outs HvxVR:$Vx32),
35015(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35016"$Vx32 += vrmpyub($Vu32,$Rt32)",
35017PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35018let hasNewValue = 1;
35019let opNewValue = 0;
35020let isAccumulator = 1;
35021let isPseudo = 1;
35022let isCodeGenOnly = 1;
35023let DecoderNamespace = "EXT_mmvec";
35024let Constraints = "$Vx32 = $Vx32in";
35025}
35026def V6_vrmpyub_alt : HInst<
35027(outs HvxVR:$Vd32),
35028(ins HvxVR:$Vu32, IntRegs:$Rt32),
35029"$Vd32 = vrmpyub($Vu32,$Rt32)",
35030PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35031let hasNewValue = 1;
35032let opNewValue = 0;
35033let isPseudo = 1;
35034let isCodeGenOnly = 1;
35035let DecoderNamespace = "EXT_mmvec";
35036}
35037def V6_vrmpyub_rtt : HInst<
35038(outs HvxWR:$Vdd32),
35039(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
35040"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
35041tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
35042let Inst{7-5} = 0b100;
35043let Inst{13-13} = 0b0;
35044let Inst{31-21} = 0b00011001110;
35045let hasNewValue = 1;
35046let opNewValue = 0;
35047let DecoderNamespace = "EXT_mmvec";
35048}
35049def V6_vrmpyub_rtt_acc : HInst<
35050(outs HvxWR:$Vxx32),
35051(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35052"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
35053tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
35054let Inst{7-5} = 0b111;
35055let Inst{13-13} = 0b1;
35056let Inst{31-21} = 0b00011001101;
35057let hasNewValue = 1;
35058let opNewValue = 0;
35059let isAccumulator = 1;
35060let DecoderNamespace = "EXT_mmvec";
35061let Constraints = "$Vxx32 = $Vxx32in";
35062}
35063def V6_vrmpyub_rtt_acc_alt : HInst<
35064(outs HvxWR:$Vxx32),
35065(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35066"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
35067PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35068let hasNewValue = 1;
35069let opNewValue = 0;
35070let isAccumulator = 1;
35071let isPseudo = 1;
35072let isCodeGenOnly = 1;
35073let DecoderNamespace = "EXT_mmvec";
35074let Constraints = "$Vxx32 = $Vxx32in";
35075}
35076def V6_vrmpyub_rtt_alt : HInst<
35077(outs HvxWR:$Vdd32),
35078(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
35079"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
35080PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35081let hasNewValue = 1;
35082let opNewValue = 0;
35083let isPseudo = 1;
35084let isCodeGenOnly = 1;
35085let DecoderNamespace = "EXT_mmvec";
35086}
35087def V6_vrmpyubi : HInst<
35088(outs HvxWR:$Vdd32),
35089(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35090"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
35091tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
35092let Inst{7-6} = 0b11;
35093let Inst{13-13} = 0b0;
35094let Inst{31-21} = 0b00011001101;
35095let hasNewValue = 1;
35096let opNewValue = 0;
35097let DecoderNamespace = "EXT_mmvec";
35098}
35099def V6_vrmpyubi_acc : HInst<
35100(outs HvxWR:$Vxx32),
35101(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35102"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
35103tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
35104let Inst{7-6} = 0b11;
35105let Inst{13-13} = 0b1;
35106let Inst{31-21} = 0b00011001011;
35107let hasNewValue = 1;
35108let opNewValue = 0;
35109let isAccumulator = 1;
35110let DecoderNamespace = "EXT_mmvec";
35111let Constraints = "$Vxx32 = $Vxx32in";
35112}
35113def V6_vrmpyubi_acc_alt : HInst<
35114(outs HvxWR:$Vxx32),
35115(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35116"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
35117PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35118let hasNewValue = 1;
35119let opNewValue = 0;
35120let isAccumulator = 1;
35121let isPseudo = 1;
35122let isCodeGenOnly = 1;
35123let DecoderNamespace = "EXT_mmvec";
35124let Constraints = "$Vxx32 = $Vxx32in";
35125}
35126def V6_vrmpyubi_alt : HInst<
35127(outs HvxWR:$Vdd32),
35128(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35129"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
35130PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35131let hasNewValue = 1;
35132let opNewValue = 0;
35133let isPseudo = 1;
35134let isCodeGenOnly = 1;
35135let DecoderNamespace = "EXT_mmvec";
35136}
35137def V6_vrmpyubv : HInst<
35138(outs HvxVR:$Vd32),
35139(ins HvxVR:$Vu32, HvxVR:$Vv32),
35140"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
35141tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35142let Inst{7-5} = 0b000;
35143let Inst{13-13} = 0b0;
35144let Inst{31-21} = 0b00011100000;
35145let hasNewValue = 1;
35146let opNewValue = 0;
35147let DecoderNamespace = "EXT_mmvec";
35148}
35149def V6_vrmpyubv_acc : HInst<
35150(outs HvxVR:$Vx32),
35151(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35152"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
35153tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35154let Inst{7-5} = 0b000;
35155let Inst{13-13} = 0b1;
35156let Inst{31-21} = 0b00011100000;
35157let hasNewValue = 1;
35158let opNewValue = 0;
35159let isAccumulator = 1;
35160let DecoderNamespace = "EXT_mmvec";
35161let Constraints = "$Vx32 = $Vx32in";
35162}
35163def V6_vrmpyubv_acc_alt : HInst<
35164(outs HvxVR:$Vx32),
35165(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35166"$Vx32 += vrmpyub($Vu32,$Vv32)",
35167PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35168let hasNewValue = 1;
35169let opNewValue = 0;
35170let isAccumulator = 1;
35171let isPseudo = 1;
35172let isCodeGenOnly = 1;
35173let DecoderNamespace = "EXT_mmvec";
35174let Constraints = "$Vx32 = $Vx32in";
35175}
35176def V6_vrmpyubv_alt : HInst<
35177(outs HvxVR:$Vd32),
35178(ins HvxVR:$Vu32, HvxVR:$Vv32),
35179"$Vd32 = vrmpyub($Vu32,$Vv32)",
35180PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35181let hasNewValue = 1;
35182let opNewValue = 0;
35183let isPseudo = 1;
35184let isCodeGenOnly = 1;
35185let DecoderNamespace = "EXT_mmvec";
35186}
35187def V6_vrmpyzbb_rt : HInst<
35188(outs HvxVQR:$Vdddd32),
35189(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
35190"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.b)",
35191tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
35192let Inst{7-5} = 0b000;
35193let Inst{13-13} = 0b0;
35194let Inst{31-19} = 0b0001100111101;
35195let hasNewValue = 1;
35196let opNewValue = 0;
35197let DecoderNamespace = "EXT_mmvec";
35198}
35199def V6_vrmpyzbb_rt_acc : HInst<
35200(outs HvxVQR:$Vyyyy32),
35201(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
35202"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.b)",
35203tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
35204let Inst{7-5} = 0b010;
35205let Inst{13-13} = 0b1;
35206let Inst{31-19} = 0b0001100111000;
35207let hasNewValue = 1;
35208let opNewValue = 0;
35209let isAccumulator = 1;
35210let DecoderNamespace = "EXT_mmvec";
35211let Constraints = "$Vyyyy32 = $Vyyyy32in";
35212}
35213def V6_vrmpyzbb_rx : HInst<
35214(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
35215(ins HvxVR:$Vu32, IntRegs:$Rx8in),
35216"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)",
35217tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
35218let Inst{7-5} = 0b000;
35219let Inst{13-13} = 0b0;
35220let Inst{31-19} = 0b0001100111100;
35221let hasNewValue = 1;
35222let opNewValue = 0;
35223let DecoderNamespace = "EXT_mmvec";
35224let Constraints = "$Rx8 = $Rx8in";
35225}
35226def V6_vrmpyzbb_rx_acc : HInst<
35227(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
35228(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
35229"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)",
35230tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
35231let Inst{7-5} = 0b010;
35232let Inst{13-13} = 0b1;
35233let Inst{31-19} = 0b0001100111001;
35234let hasNewValue = 1;
35235let opNewValue = 0;
35236let isAccumulator = 1;
35237let DecoderNamespace = "EXT_mmvec";
35238let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
35239}
35240def V6_vrmpyzbub_rt : HInst<
35241(outs HvxVQR:$Vdddd32),
35242(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
35243"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.ub)",
35244tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
35245let Inst{7-5} = 0b010;
35246let Inst{13-13} = 0b0;
35247let Inst{31-19} = 0b0001100111111;
35248let hasNewValue = 1;
35249let opNewValue = 0;
35250let DecoderNamespace = "EXT_mmvec";
35251}
35252def V6_vrmpyzbub_rt_acc : HInst<
35253(outs HvxVQR:$Vyyyy32),
35254(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
35255"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.ub)",
35256tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
35257let Inst{7-5} = 0b001;
35258let Inst{13-13} = 0b1;
35259let Inst{31-19} = 0b0001100111010;
35260let hasNewValue = 1;
35261let opNewValue = 0;
35262let isAccumulator = 1;
35263let DecoderNamespace = "EXT_mmvec";
35264let Constraints = "$Vyyyy32 = $Vyyyy32in";
35265}
35266def V6_vrmpyzbub_rx : HInst<
35267(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
35268(ins HvxVR:$Vu32, IntRegs:$Rx8in),
35269"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)",
35270tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
35271let Inst{7-5} = 0b010;
35272let Inst{13-13} = 0b0;
35273let Inst{31-19} = 0b0001100111110;
35274let hasNewValue = 1;
35275let opNewValue = 0;
35276let DecoderNamespace = "EXT_mmvec";
35277let Constraints = "$Rx8 = $Rx8in";
35278}
35279def V6_vrmpyzbub_rx_acc : HInst<
35280(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
35281(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
35282"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)",
35283tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
35284let Inst{7-5} = 0b001;
35285let Inst{13-13} = 0b1;
35286let Inst{31-19} = 0b0001100111011;
35287let hasNewValue = 1;
35288let opNewValue = 0;
35289let isAccumulator = 1;
35290let DecoderNamespace = "EXT_mmvec";
35291let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
35292}
35293def V6_vrmpyzcb_rt : HInst<
35294(outs HvxVQR:$Vdddd32),
35295(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
35296"$Vdddd32.w = vr16mpyz($Vu32.c,$Rt8.b)",
35297tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
35298let Inst{7-5} = 0b001;
35299let Inst{13-13} = 0b0;
35300let Inst{31-19} = 0b0001100111101;
35301let hasNewValue = 1;
35302let opNewValue = 0;
35303let DecoderNamespace = "EXT_mmvec";
35304}
35305def V6_vrmpyzcb_rt_acc : HInst<
35306(outs HvxVQR:$Vyyyy32),
35307(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
35308"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rt8.b)",
35309tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
35310let Inst{7-5} = 0b011;
35311let Inst{13-13} = 0b1;
35312let Inst{31-19} = 0b0001100111000;
35313let hasNewValue = 1;
35314let opNewValue = 0;
35315let isAccumulator = 1;
35316let DecoderNamespace = "EXT_mmvec";
35317let Constraints = "$Vyyyy32 = $Vyyyy32in";
35318}
35319def V6_vrmpyzcb_rx : HInst<
35320(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
35321(ins HvxVR:$Vu32, IntRegs:$Rx8in),
35322"$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)",
35323tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
35324let Inst{7-5} = 0b001;
35325let Inst{13-13} = 0b0;
35326let Inst{31-19} = 0b0001100111100;
35327let hasNewValue = 1;
35328let opNewValue = 0;
35329let DecoderNamespace = "EXT_mmvec";
35330let Constraints = "$Rx8 = $Rx8in";
35331}
35332def V6_vrmpyzcb_rx_acc : HInst<
35333(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
35334(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
35335"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)",
35336tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
35337let Inst{7-5} = 0b011;
35338let Inst{13-13} = 0b1;
35339let Inst{31-19} = 0b0001100111001;
35340let hasNewValue = 1;
35341let opNewValue = 0;
35342let isAccumulator = 1;
35343let DecoderNamespace = "EXT_mmvec";
35344let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
35345}
35346def V6_vrmpyzcbs_rt : HInst<
35347(outs HvxVQR:$Vdddd32),
35348(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
35349"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rt8.b)",
35350tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
35351let Inst{7-5} = 0b010;
35352let Inst{13-13} = 0b0;
35353let Inst{31-19} = 0b0001100111101;
35354let hasNewValue = 1;
35355let opNewValue = 0;
35356let DecoderNamespace = "EXT_mmvec";
35357}
35358def V6_vrmpyzcbs_rt_acc : HInst<
35359(outs HvxVQR:$Vyyyy32),
35360(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
35361"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rt8.b)",
35362tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
35363let Inst{7-5} = 0b001;
35364let Inst{13-13} = 0b1;
35365let Inst{31-19} = 0b0001100111000;
35366let hasNewValue = 1;
35367let opNewValue = 0;
35368let isAccumulator = 1;
35369let DecoderNamespace = "EXT_mmvec";
35370let Constraints = "$Vyyyy32 = $Vyyyy32in";
35371}
35372def V6_vrmpyzcbs_rx : HInst<
35373(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
35374(ins HvxVR:$Vu32, IntRegs:$Rx8in),
35375"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)",
35376tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
35377let Inst{7-5} = 0b010;
35378let Inst{13-13} = 0b0;
35379let Inst{31-19} = 0b0001100111100;
35380let hasNewValue = 1;
35381let opNewValue = 0;
35382let DecoderNamespace = "EXT_mmvec";
35383let Constraints = "$Rx8 = $Rx8in";
35384}
35385def V6_vrmpyzcbs_rx_acc : HInst<
35386(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
35387(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
35388"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)",
35389tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
35390let Inst{7-5} = 0b001;
35391let Inst{13-13} = 0b1;
35392let Inst{31-19} = 0b0001100111001;
35393let hasNewValue = 1;
35394let opNewValue = 0;
35395let isAccumulator = 1;
35396let DecoderNamespace = "EXT_mmvec";
35397let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
35398}
35399def V6_vrmpyznb_rt : HInst<
35400(outs HvxVQR:$Vdddd32),
35401(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
35402"$Vdddd32.w = vr8mpyz($Vu32.n,$Rt8.b)",
35403tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
35404let Inst{7-5} = 0b000;
35405let Inst{13-13} = 0b0;
35406let Inst{31-19} = 0b0001100111111;
35407let hasNewValue = 1;
35408let opNewValue = 0;
35409let DecoderNamespace = "EXT_mmvec";
35410}
35411def V6_vrmpyznb_rt_acc : HInst<
35412(outs HvxVQR:$Vyyyy32),
35413(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
35414"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rt8.b)",
35415tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
35416let Inst{7-5} = 0b010;
35417let Inst{13-13} = 0b1;
35418let Inst{31-19} = 0b0001100111010;
35419let hasNewValue = 1;
35420let opNewValue = 0;
35421let isAccumulator = 1;
35422let DecoderNamespace = "EXT_mmvec";
35423let Constraints = "$Vyyyy32 = $Vyyyy32in";
35424}
35425def V6_vrmpyznb_rx : HInst<
35426(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
35427(ins HvxVR:$Vu32, IntRegs:$Rx8in),
35428"$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)",
35429tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
35430let Inst{7-5} = 0b000;
35431let Inst{13-13} = 0b0;
35432let Inst{31-19} = 0b0001100111110;
35433let hasNewValue = 1;
35434let opNewValue = 0;
35435let DecoderNamespace = "EXT_mmvec";
35436let Constraints = "$Rx8 = $Rx8in";
35437}
35438def V6_vrmpyznb_rx_acc : HInst<
35439(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
35440(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in),
35441"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)",
35442tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
35443let Inst{7-5} = 0b010;
35444let Inst{13-13} = 0b1;
35445let Inst{31-19} = 0b0001100111011;
35446let hasNewValue = 1;
35447let opNewValue = 0;
35448let isAccumulator = 1;
35449let DecoderNamespace = "EXT_mmvec";
35450let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
35451}
35452def V6_vror : HInst<
35453(outs HvxVR:$Vd32),
35454(ins HvxVR:$Vu32, IntRegs:$Rt32),
35455"$Vd32 = vror($Vu32,$Rt32)",
35456tc_6e7fa133, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
35457let Inst{7-5} = 0b001;
35458let Inst{13-13} = 0b0;
35459let Inst{31-21} = 0b00011001011;
35460let hasNewValue = 1;
35461let opNewValue = 0;
35462let DecoderNamespace = "EXT_mmvec";
35463}
35464def V6_vrotr : HInst<
35465(outs HvxVR:$Vd32),
35466(ins HvxVR:$Vu32, HvxVR:$Vv32),
35467"$Vd32.uw = vrotr($Vu32.uw,$Vv32.uw)",
35468tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV66]> {
35469let Inst{7-5} = 0b111;
35470let Inst{13-13} = 0b1;
35471let Inst{31-21} = 0b00011010100;
35472let hasNewValue = 1;
35473let opNewValue = 0;
35474let DecoderNamespace = "EXT_mmvec";
35475}
35476def V6_vrotr_alt : HInst<
35477(outs HvxVR:$Vd32),
35478(ins HvxVR:$Vu32, HvxVR:$Vv32),
35479"$Vd32 = vrotr($Vu32,$Vv32)",
35480PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
35481let hasNewValue = 1;
35482let opNewValue = 0;
35483let isPseudo = 1;
35484let isCodeGenOnly = 1;
35485let DecoderNamespace = "EXT_mmvec";
35486}
35487def V6_vroundhb : HInst<
35488(outs HvxVR:$Vd32),
35489(ins HvxVR:$Vu32, HvxVR:$Vv32),
35490"$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
35491tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
35492let Inst{7-5} = 0b110;
35493let Inst{13-13} = 0b0;
35494let Inst{31-21} = 0b00011111011;
35495let hasNewValue = 1;
35496let opNewValue = 0;
35497let DecoderNamespace = "EXT_mmvec";
35498}
35499def V6_vroundhb_alt : HInst<
35500(outs HvxVR:$Vd32),
35501(ins HvxVR:$Vu32, HvxVR:$Vv32),
35502"$Vd32 = vroundhb($Vu32,$Vv32):sat",
35503PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35504let hasNewValue = 1;
35505let opNewValue = 0;
35506let isPseudo = 1;
35507let isCodeGenOnly = 1;
35508let DecoderNamespace = "EXT_mmvec";
35509}
35510def V6_vroundhub : HInst<
35511(outs HvxVR:$Vd32),
35512(ins HvxVR:$Vu32, HvxVR:$Vv32),
35513"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
35514tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
35515let Inst{7-5} = 0b111;
35516let Inst{13-13} = 0b0;
35517let Inst{31-21} = 0b00011111011;
35518let hasNewValue = 1;
35519let opNewValue = 0;
35520let DecoderNamespace = "EXT_mmvec";
35521}
35522def V6_vroundhub_alt : HInst<
35523(outs HvxVR:$Vd32),
35524(ins HvxVR:$Vu32, HvxVR:$Vv32),
35525"$Vd32 = vroundhub($Vu32,$Vv32):sat",
35526PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35527let hasNewValue = 1;
35528let opNewValue = 0;
35529let isPseudo = 1;
35530let isCodeGenOnly = 1;
35531let DecoderNamespace = "EXT_mmvec";
35532}
35533def V6_vrounduhub : HInst<
35534(outs HvxVR:$Vd32),
35535(ins HvxVR:$Vu32, HvxVR:$Vv32),
35536"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
35537tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
35538let Inst{7-5} = 0b011;
35539let Inst{13-13} = 0b0;
35540let Inst{31-21} = 0b00011111111;
35541let hasNewValue = 1;
35542let opNewValue = 0;
35543let DecoderNamespace = "EXT_mmvec";
35544}
35545def V6_vrounduhub_alt : HInst<
35546(outs HvxVR:$Vd32),
35547(ins HvxVR:$Vu32, HvxVR:$Vv32),
35548"$Vd32 = vrounduhub($Vu32,$Vv32):sat",
35549PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35550let hasNewValue = 1;
35551let opNewValue = 0;
35552let isPseudo = 1;
35553let isCodeGenOnly = 1;
35554let DecoderNamespace = "EXT_mmvec";
35555}
35556def V6_vrounduwuh : HInst<
35557(outs HvxVR:$Vd32),
35558(ins HvxVR:$Vu32, HvxVR:$Vv32),
35559"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
35560tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
35561let Inst{7-5} = 0b100;
35562let Inst{13-13} = 0b0;
35563let Inst{31-21} = 0b00011111111;
35564let hasNewValue = 1;
35565let opNewValue = 0;
35566let DecoderNamespace = "EXT_mmvec";
35567}
35568def V6_vrounduwuh_alt : HInst<
35569(outs HvxVR:$Vd32),
35570(ins HvxVR:$Vu32, HvxVR:$Vv32),
35571"$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
35572PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35573let hasNewValue = 1;
35574let opNewValue = 0;
35575let isPseudo = 1;
35576let isCodeGenOnly = 1;
35577let DecoderNamespace = "EXT_mmvec";
35578}
35579def V6_vroundwh : HInst<
35580(outs HvxVR:$Vd32),
35581(ins HvxVR:$Vu32, HvxVR:$Vv32),
35582"$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
35583tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
35584let Inst{7-5} = 0b100;
35585let Inst{13-13} = 0b0;
35586let Inst{31-21} = 0b00011111011;
35587let hasNewValue = 1;
35588let opNewValue = 0;
35589let DecoderNamespace = "EXT_mmvec";
35590}
35591def V6_vroundwh_alt : HInst<
35592(outs HvxVR:$Vd32),
35593(ins HvxVR:$Vu32, HvxVR:$Vv32),
35594"$Vd32 = vroundwh($Vu32,$Vv32):sat",
35595PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35596let hasNewValue = 1;
35597let opNewValue = 0;
35598let isPseudo = 1;
35599let isCodeGenOnly = 1;
35600let DecoderNamespace = "EXT_mmvec";
35601}
35602def V6_vroundwuh : HInst<
35603(outs HvxVR:$Vd32),
35604(ins HvxVR:$Vu32, HvxVR:$Vv32),
35605"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
35606tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
35607let Inst{7-5} = 0b101;
35608let Inst{13-13} = 0b0;
35609let Inst{31-21} = 0b00011111011;
35610let hasNewValue = 1;
35611let opNewValue = 0;
35612let DecoderNamespace = "EXT_mmvec";
35613}
35614def V6_vroundwuh_alt : HInst<
35615(outs HvxVR:$Vd32),
35616(ins HvxVR:$Vu32, HvxVR:$Vv32),
35617"$Vd32 = vroundwuh($Vu32,$Vv32):sat",
35618PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35619let hasNewValue = 1;
35620let opNewValue = 0;
35621let isPseudo = 1;
35622let isCodeGenOnly = 1;
35623let DecoderNamespace = "EXT_mmvec";
35624}
35625def V6_vrsadubi : HInst<
35626(outs HvxWR:$Vdd32),
35627(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35628"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
35629tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
35630let Inst{7-6} = 0b11;
35631let Inst{13-13} = 0b0;
35632let Inst{31-21} = 0b00011001010;
35633let hasNewValue = 1;
35634let opNewValue = 0;
35635let DecoderNamespace = "EXT_mmvec";
35636}
35637def V6_vrsadubi_acc : HInst<
35638(outs HvxWR:$Vxx32),
35639(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35640"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
35641tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
35642let Inst{7-6} = 0b11;
35643let Inst{13-13} = 0b1;
35644let Inst{31-21} = 0b00011001010;
35645let hasNewValue = 1;
35646let opNewValue = 0;
35647let isAccumulator = 1;
35648let DecoderNamespace = "EXT_mmvec";
35649let Constraints = "$Vxx32 = $Vxx32in";
35650}
35651def V6_vrsadubi_acc_alt : HInst<
35652(outs HvxWR:$Vxx32),
35653(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35654"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
35655PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35656let hasNewValue = 1;
35657let opNewValue = 0;
35658let isAccumulator = 1;
35659let isPseudo = 1;
35660let isCodeGenOnly = 1;
35661let DecoderNamespace = "EXT_mmvec";
35662let Constraints = "$Vxx32 = $Vxx32in";
35663}
35664def V6_vrsadubi_alt : HInst<
35665(outs HvxWR:$Vdd32),
35666(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35667"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
35668PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35669let hasNewValue = 1;
35670let opNewValue = 0;
35671let isPseudo = 1;
35672let isCodeGenOnly = 1;
35673let DecoderNamespace = "EXT_mmvec";
35674}
35675def V6_vsatdw : HInst<
35676(outs HvxVR:$Vd32),
35677(ins HvxVR:$Vu32, HvxVR:$Vv32),
35678"$Vd32.w = vsatdw($Vu32.w,$Vv32.w)",
35679tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV66]> {
35680let Inst{7-5} = 0b111;
35681let Inst{13-13} = 0b1;
35682let Inst{31-21} = 0b00011101100;
35683let hasNewValue = 1;
35684let opNewValue = 0;
35685let DecoderNamespace = "EXT_mmvec";
35686}
35687def V6_vsathub : HInst<
35688(outs HvxVR:$Vd32),
35689(ins HvxVR:$Vu32, HvxVR:$Vv32),
35690"$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
35691tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
35692let Inst{7-5} = 0b010;
35693let Inst{13-13} = 0b0;
35694let Inst{31-21} = 0b00011111011;
35695let hasNewValue = 1;
35696let opNewValue = 0;
35697let DecoderNamespace = "EXT_mmvec";
35698}
35699def V6_vsathub_alt : HInst<
35700(outs HvxVR:$Vd32),
35701(ins HvxVR:$Vu32, HvxVR:$Vv32),
35702"$Vd32 = vsathub($Vu32,$Vv32)",
35703PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35704let hasNewValue = 1;
35705let opNewValue = 0;
35706let isPseudo = 1;
35707let isCodeGenOnly = 1;
35708let DecoderNamespace = "EXT_mmvec";
35709}
35710def V6_vsatuwuh : HInst<
35711(outs HvxVR:$Vd32),
35712(ins HvxVR:$Vu32, HvxVR:$Vv32),
35713"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
35714tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
35715let Inst{7-5} = 0b110;
35716let Inst{13-13} = 0b0;
35717let Inst{31-21} = 0b00011111001;
35718let hasNewValue = 1;
35719let opNewValue = 0;
35720let DecoderNamespace = "EXT_mmvec";
35721}
35722def V6_vsatuwuh_alt : HInst<
35723(outs HvxVR:$Vd32),
35724(ins HvxVR:$Vu32, HvxVR:$Vv32),
35725"$Vd32 = vsatuwuh($Vu32,$Vv32)",
35726PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35727let hasNewValue = 1;
35728let opNewValue = 0;
35729let isPseudo = 1;
35730let isCodeGenOnly = 1;
35731let DecoderNamespace = "EXT_mmvec";
35732}
35733def V6_vsatwh : HInst<
35734(outs HvxVR:$Vd32),
35735(ins HvxVR:$Vu32, HvxVR:$Vv32),
35736"$Vd32.h = vsat($Vu32.w,$Vv32.w)",
35737tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> {
35738let Inst{7-5} = 0b011;
35739let Inst{13-13} = 0b0;
35740let Inst{31-21} = 0b00011111011;
35741let hasNewValue = 1;
35742let opNewValue = 0;
35743let DecoderNamespace = "EXT_mmvec";
35744}
35745def V6_vsatwh_alt : HInst<
35746(outs HvxVR:$Vd32),
35747(ins HvxVR:$Vu32, HvxVR:$Vv32),
35748"$Vd32 = vsatwh($Vu32,$Vv32)",
35749PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35750let hasNewValue = 1;
35751let opNewValue = 0;
35752let isPseudo = 1;
35753let isCodeGenOnly = 1;
35754let DecoderNamespace = "EXT_mmvec";
35755}
35756def V6_vsb : HInst<
35757(outs HvxWR:$Vdd32),
35758(ins HvxVR:$Vu32),
35759"$Vdd32.h = vsxt($Vu32.b)",
35760tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
35761let Inst{7-5} = 0b011;
35762let Inst{13-13} = 0b0;
35763let Inst{31-16} = 0b0001111000000010;
35764let hasNewValue = 1;
35765let opNewValue = 0;
35766let DecoderNamespace = "EXT_mmvec";
35767}
35768def V6_vsb_alt : HInst<
35769(outs HvxWR:$Vdd32),
35770(ins HvxVR:$Vu32),
35771"$Vdd32 = vsxtb($Vu32)",
35772PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35773let hasNewValue = 1;
35774let opNewValue = 0;
35775let isPseudo = 1;
35776let isCodeGenOnly = 1;
35777let DecoderNamespace = "EXT_mmvec";
35778}
35779def V6_vscattermh : HInst<
35780(outs),
35781(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35782"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
35783tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35784let Inst{7-5} = 0b001;
35785let Inst{31-21} = 0b00101111001;
35786let accessSize = HalfWordAccess;
35787let mayStore = 1;
35788let DecoderNamespace = "EXT_mmvec";
35789}
35790def V6_vscattermh_add : HInst<
35791(outs),
35792(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35793"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
35794tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35795let Inst{7-5} = 0b101;
35796let Inst{31-21} = 0b00101111001;
35797let accessSize = HalfWordAccess;
35798let isAccumulator = 1;
35799let mayStore = 1;
35800let DecoderNamespace = "EXT_mmvec";
35801}
35802def V6_vscattermh_add_alt : HInst<
35803(outs),
35804(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35805"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
35806PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35807let isAccumulator = 1;
35808let isPseudo = 1;
35809let isCodeGenOnly = 1;
35810let DecoderNamespace = "EXT_mmvec";
35811}
35812def V6_vscattermh_alt : HInst<
35813(outs),
35814(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35815"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
35816PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35817let isPseudo = 1;
35818let isCodeGenOnly = 1;
35819let DecoderNamespace = "EXT_mmvec";
35820}
35821def V6_vscattermhq : HInst<
35822(outs),
35823(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35824"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
35825tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
35826let Inst{7-7} = 0b1;
35827let Inst{31-21} = 0b00101111100;
35828let accessSize = HalfWordAccess;
35829let mayStore = 1;
35830let DecoderNamespace = "EXT_mmvec";
35831}
35832def V6_vscattermhq_alt : HInst<
35833(outs),
35834(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35835"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
35836PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35837let isPseudo = 1;
35838let isCodeGenOnly = 1;
35839let DecoderNamespace = "EXT_mmvec";
35840}
35841def V6_vscattermhw : HInst<
35842(outs),
35843(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35844"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
35845tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
35846let Inst{7-5} = 0b010;
35847let Inst{31-21} = 0b00101111001;
35848let accessSize = HalfWordAccess;
35849let mayStore = 1;
35850let DecoderNamespace = "EXT_mmvec";
35851}
35852def V6_vscattermhw_add : HInst<
35853(outs),
35854(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35855"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
35856tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
35857let Inst{7-5} = 0b110;
35858let Inst{31-21} = 0b00101111001;
35859let accessSize = HalfWordAccess;
35860let isAccumulator = 1;
35861let mayStore = 1;
35862let DecoderNamespace = "EXT_mmvec";
35863}
35864def V6_vscattermhwq : HInst<
35865(outs),
35866(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35867"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
35868tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
35869let Inst{7-7} = 0b0;
35870let Inst{31-21} = 0b00101111101;
35871let accessSize = HalfWordAccess;
35872let mayStore = 1;
35873let DecoderNamespace = "EXT_mmvec";
35874}
35875def V6_vscattermw : HInst<
35876(outs),
35877(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35878"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
35879tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35880let Inst{7-5} = 0b000;
35881let Inst{31-21} = 0b00101111001;
35882let accessSize = WordAccess;
35883let mayStore = 1;
35884let DecoderNamespace = "EXT_mmvec";
35885}
35886def V6_vscattermw_add : HInst<
35887(outs),
35888(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35889"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
35890tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
35891let Inst{7-5} = 0b100;
35892let Inst{31-21} = 0b00101111001;
35893let accessSize = WordAccess;
35894let isAccumulator = 1;
35895let mayStore = 1;
35896let DecoderNamespace = "EXT_mmvec";
35897}
35898def V6_vscattermw_add_alt : HInst<
35899(outs),
35900(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35901"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
35902PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35903let isAccumulator = 1;
35904let isPseudo = 1;
35905let isCodeGenOnly = 1;
35906let DecoderNamespace = "EXT_mmvec";
35907}
35908def V6_vscattermw_alt : HInst<
35909(outs),
35910(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35911"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
35912PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35913let isPseudo = 1;
35914let isCodeGenOnly = 1;
35915let DecoderNamespace = "EXT_mmvec";
35916}
35917def V6_vscattermwh_add_alt : HInst<
35918(outs),
35919(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35920"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
35921PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35922let isAccumulator = 1;
35923let isPseudo = 1;
35924let isCodeGenOnly = 1;
35925let DecoderNamespace = "EXT_mmvec";
35926}
35927def V6_vscattermwh_alt : HInst<
35928(outs),
35929(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35930"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
35931PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35932let isPseudo = 1;
35933let isCodeGenOnly = 1;
35934let DecoderNamespace = "EXT_mmvec";
35935}
35936def V6_vscattermwhq_alt : HInst<
35937(outs),
35938(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
35939"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
35940PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35941let isPseudo = 1;
35942let isCodeGenOnly = 1;
35943let DecoderNamespace = "EXT_mmvec";
35944}
35945def V6_vscattermwq : HInst<
35946(outs),
35947(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35948"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
35949tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
35950let Inst{7-7} = 0b0;
35951let Inst{31-21} = 0b00101111100;
35952let accessSize = WordAccess;
35953let mayStore = 1;
35954let DecoderNamespace = "EXT_mmvec";
35955}
35956def V6_vscattermwq_alt : HInst<
35957(outs),
35958(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
35959"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
35960PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35961let isPseudo = 1;
35962let isCodeGenOnly = 1;
35963let DecoderNamespace = "EXT_mmvec";
35964}
35965def V6_vsh : HInst<
35966(outs HvxWR:$Vdd32),
35967(ins HvxVR:$Vu32),
35968"$Vdd32.w = vsxt($Vu32.h)",
35969tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
35970let Inst{7-5} = 0b100;
35971let Inst{13-13} = 0b0;
35972let Inst{31-16} = 0b0001111000000010;
35973let hasNewValue = 1;
35974let opNewValue = 0;
35975let DecoderNamespace = "EXT_mmvec";
35976}
35977def V6_vsh_alt : HInst<
35978(outs HvxWR:$Vdd32),
35979(ins HvxVR:$Vu32),
35980"$Vdd32 = vsxth($Vu32)",
35981PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35982let hasNewValue = 1;
35983let opNewValue = 0;
35984let isPseudo = 1;
35985let isCodeGenOnly = 1;
35986let DecoderNamespace = "EXT_mmvec";
35987}
35988def V6_vshufeh : HInst<
35989(outs HvxVR:$Vd32),
35990(ins HvxVR:$Vu32, HvxVR:$Vv32),
35991"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
35992tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35993let Inst{7-5} = 0b011;
35994let Inst{13-13} = 0b0;
35995let Inst{31-21} = 0b00011111010;
35996let hasNewValue = 1;
35997let opNewValue = 0;
35998let DecoderNamespace = "EXT_mmvec";
35999}
36000def V6_vshufeh_alt : HInst<
36001(outs HvxVR:$Vd32),
36002(ins HvxVR:$Vu32, HvxVR:$Vv32),
36003"$Vd32 = vshuffeh($Vu32,$Vv32)",
36004PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36005let hasNewValue = 1;
36006let opNewValue = 0;
36007let isPseudo = 1;
36008let isCodeGenOnly = 1;
36009let DecoderNamespace = "EXT_mmvec";
36010}
36011def V6_vshuff : HInst<
36012(outs HvxVR:$Vy32, HvxVR:$Vx32),
36013(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
36014"vshuff($Vy32,$Vx32,$Rt32)",
36015tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
36016let Inst{7-5} = 0b001;
36017let Inst{13-13} = 0b1;
36018let Inst{31-21} = 0b00011001111;
36019let hasNewValue = 1;
36020let opNewValue = 0;
36021let hasNewValue2 = 1;
36022let opNewValue2 = 1;
36023let DecoderNamespace = "EXT_mmvec";
36024let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
36025}
36026def V6_vshuffb : HInst<
36027(outs HvxVR:$Vd32),
36028(ins HvxVR:$Vu32),
36029"$Vd32.b = vshuff($Vu32.b)",
36030tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
36031let Inst{7-5} = 0b000;
36032let Inst{13-13} = 0b0;
36033let Inst{31-16} = 0b0001111000000010;
36034let hasNewValue = 1;
36035let opNewValue = 0;
36036let DecoderNamespace = "EXT_mmvec";
36037}
36038def V6_vshuffb_alt : HInst<
36039(outs HvxVR:$Vd32),
36040(ins HvxVR:$Vu32),
36041"$Vd32 = vshuffb($Vu32)",
36042PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36043let hasNewValue = 1;
36044let opNewValue = 0;
36045let isPseudo = 1;
36046let isCodeGenOnly = 1;
36047let DecoderNamespace = "EXT_mmvec";
36048}
36049def V6_vshuffeb : HInst<
36050(outs HvxVR:$Vd32),
36051(ins HvxVR:$Vu32, HvxVR:$Vv32),
36052"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
36053tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36054let Inst{7-5} = 0b001;
36055let Inst{13-13} = 0b0;
36056let Inst{31-21} = 0b00011111010;
36057let hasNewValue = 1;
36058let opNewValue = 0;
36059let DecoderNamespace = "EXT_mmvec";
36060}
36061def V6_vshuffeb_alt : HInst<
36062(outs HvxVR:$Vd32),
36063(ins HvxVR:$Vu32, HvxVR:$Vv32),
36064"$Vd32 = vshuffeb($Vu32,$Vv32)",
36065PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36066let hasNewValue = 1;
36067let opNewValue = 0;
36068let isPseudo = 1;
36069let isCodeGenOnly = 1;
36070let DecoderNamespace = "EXT_mmvec";
36071}
36072def V6_vshuffh : HInst<
36073(outs HvxVR:$Vd32),
36074(ins HvxVR:$Vu32),
36075"$Vd32.h = vshuff($Vu32.h)",
36076tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
36077let Inst{7-5} = 0b111;
36078let Inst{13-13} = 0b0;
36079let Inst{31-16} = 0b0001111000000001;
36080let hasNewValue = 1;
36081let opNewValue = 0;
36082let DecoderNamespace = "EXT_mmvec";
36083}
36084def V6_vshuffh_alt : HInst<
36085(outs HvxVR:$Vd32),
36086(ins HvxVR:$Vu32),
36087"$Vd32 = vshuffh($Vu32)",
36088PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36089let hasNewValue = 1;
36090let opNewValue = 0;
36091let isPseudo = 1;
36092let isCodeGenOnly = 1;
36093let DecoderNamespace = "EXT_mmvec";
36094}
36095def V6_vshuffob : HInst<
36096(outs HvxVR:$Vd32),
36097(ins HvxVR:$Vu32, HvxVR:$Vv32),
36098"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
36099tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36100let Inst{7-5} = 0b010;
36101let Inst{13-13} = 0b0;
36102let Inst{31-21} = 0b00011111010;
36103let hasNewValue = 1;
36104let opNewValue = 0;
36105let DecoderNamespace = "EXT_mmvec";
36106}
36107def V6_vshuffob_alt : HInst<
36108(outs HvxVR:$Vd32),
36109(ins HvxVR:$Vu32, HvxVR:$Vv32),
36110"$Vd32 = vshuffob($Vu32,$Vv32)",
36111PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36112let hasNewValue = 1;
36113let opNewValue = 0;
36114let isPseudo = 1;
36115let isCodeGenOnly = 1;
36116let DecoderNamespace = "EXT_mmvec";
36117}
36118def V6_vshuffvdd : HInst<
36119(outs HvxWR:$Vdd32),
36120(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
36121"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
36122tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
36123let Inst{7-5} = 0b011;
36124let Inst{13-13} = 0b1;
36125let Inst{31-24} = 0b00011011;
36126let hasNewValue = 1;
36127let opNewValue = 0;
36128let DecoderNamespace = "EXT_mmvec";
36129}
36130def V6_vshufoeb : HInst<
36131(outs HvxWR:$Vdd32),
36132(ins HvxVR:$Vu32, HvxVR:$Vv32),
36133"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
36134tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36135let Inst{7-5} = 0b110;
36136let Inst{13-13} = 0b0;
36137let Inst{31-21} = 0b00011111010;
36138let hasNewValue = 1;
36139let opNewValue = 0;
36140let DecoderNamespace = "EXT_mmvec";
36141}
36142def V6_vshufoeb_alt : HInst<
36143(outs HvxWR:$Vdd32),
36144(ins HvxVR:$Vu32, HvxVR:$Vv32),
36145"$Vdd32 = vshuffoeb($Vu32,$Vv32)",
36146PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36147let hasNewValue = 1;
36148let opNewValue = 0;
36149let isPseudo = 1;
36150let isCodeGenOnly = 1;
36151let DecoderNamespace = "EXT_mmvec";
36152}
36153def V6_vshufoeh : HInst<
36154(outs HvxWR:$Vdd32),
36155(ins HvxVR:$Vu32, HvxVR:$Vv32),
36156"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
36157tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36158let Inst{7-5} = 0b101;
36159let Inst{13-13} = 0b0;
36160let Inst{31-21} = 0b00011111010;
36161let hasNewValue = 1;
36162let opNewValue = 0;
36163let DecoderNamespace = "EXT_mmvec";
36164}
36165def V6_vshufoeh_alt : HInst<
36166(outs HvxWR:$Vdd32),
36167(ins HvxVR:$Vu32, HvxVR:$Vv32),
36168"$Vdd32 = vshuffoeh($Vu32,$Vv32)",
36169PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36170let hasNewValue = 1;
36171let opNewValue = 0;
36172let isPseudo = 1;
36173let isCodeGenOnly = 1;
36174let DecoderNamespace = "EXT_mmvec";
36175}
36176def V6_vshufoh : HInst<
36177(outs HvxVR:$Vd32),
36178(ins HvxVR:$Vu32, HvxVR:$Vv32),
36179"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
36180tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36181let Inst{7-5} = 0b100;
36182let Inst{13-13} = 0b0;
36183let Inst{31-21} = 0b00011111010;
36184let hasNewValue = 1;
36185let opNewValue = 0;
36186let DecoderNamespace = "EXT_mmvec";
36187}
36188def V6_vshufoh_alt : HInst<
36189(outs HvxVR:$Vd32),
36190(ins HvxVR:$Vu32, HvxVR:$Vv32),
36191"$Vd32 = vshuffoh($Vu32,$Vv32)",
36192PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36193let hasNewValue = 1;
36194let opNewValue = 0;
36195let isPseudo = 1;
36196let isCodeGenOnly = 1;
36197let DecoderNamespace = "EXT_mmvec";
36198}
36199def V6_vsubb : HInst<
36200(outs HvxVR:$Vd32),
36201(ins HvxVR:$Vu32, HvxVR:$Vv32),
36202"$Vd32.b = vsub($Vu32.b,$Vv32.b)",
36203tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36204let Inst{7-5} = 0b101;
36205let Inst{13-13} = 0b0;
36206let Inst{31-21} = 0b00011100010;
36207let hasNewValue = 1;
36208let opNewValue = 0;
36209let DecoderNamespace = "EXT_mmvec";
36210}
36211def V6_vsubb_alt : HInst<
36212(outs HvxVR:$Vd32),
36213(ins HvxVR:$Vu32, HvxVR:$Vv32),
36214"$Vd32 = vsubb($Vu32,$Vv32)",
36215PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36216let hasNewValue = 1;
36217let opNewValue = 0;
36218let isPseudo = 1;
36219let isCodeGenOnly = 1;
36220let DecoderNamespace = "EXT_mmvec";
36221}
36222def V6_vsubb_dv : HInst<
36223(outs HvxWR:$Vdd32),
36224(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36225"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
36226tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36227let Inst{7-5} = 0b011;
36228let Inst{13-13} = 0b0;
36229let Inst{31-21} = 0b00011100100;
36230let hasNewValue = 1;
36231let opNewValue = 0;
36232let DecoderNamespace = "EXT_mmvec";
36233}
36234def V6_vsubb_dv_alt : HInst<
36235(outs HvxWR:$Vdd32),
36236(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36237"$Vdd32 = vsubb($Vuu32,$Vvv32)",
36238PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36239let hasNewValue = 1;
36240let opNewValue = 0;
36241let isPseudo = 1;
36242let isCodeGenOnly = 1;
36243let DecoderNamespace = "EXT_mmvec";
36244}
36245def V6_vsubbnq : HInst<
36246(outs HvxVR:$Vx32),
36247(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36248"if (!$Qv4) $Vx32.b -= $Vu32.b",
36249tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36250let Inst{7-5} = 0b001;
36251let Inst{13-13} = 0b1;
36252let Inst{21-16} = 0b000010;
36253let Inst{31-24} = 0b00011110;
36254let hasNewValue = 1;
36255let opNewValue = 0;
36256let DecoderNamespace = "EXT_mmvec";
36257let Constraints = "$Vx32 = $Vx32in";
36258}
36259def V6_vsubbnq_alt : HInst<
36260(outs HvxVR:$Vx32),
36261(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36262"if (!$Qv4.b) $Vx32.b -= $Vu32.b",
36263PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36264let hasNewValue = 1;
36265let opNewValue = 0;
36266let isPseudo = 1;
36267let isCodeGenOnly = 1;
36268let DecoderNamespace = "EXT_mmvec";
36269let Constraints = "$Vx32 = $Vx32in";
36270}
36271def V6_vsubbq : HInst<
36272(outs HvxVR:$Vx32),
36273(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36274"if ($Qv4) $Vx32.b -= $Vu32.b",
36275tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36276let Inst{7-5} = 0b110;
36277let Inst{13-13} = 0b1;
36278let Inst{21-16} = 0b000001;
36279let Inst{31-24} = 0b00011110;
36280let hasNewValue = 1;
36281let opNewValue = 0;
36282let DecoderNamespace = "EXT_mmvec";
36283let Constraints = "$Vx32 = $Vx32in";
36284}
36285def V6_vsubbq_alt : HInst<
36286(outs HvxVR:$Vx32),
36287(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36288"if ($Qv4.b) $Vx32.b -= $Vu32.b",
36289PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36290let hasNewValue = 1;
36291let opNewValue = 0;
36292let isPseudo = 1;
36293let isCodeGenOnly = 1;
36294let DecoderNamespace = "EXT_mmvec";
36295let Constraints = "$Vx32 = $Vx32in";
36296}
36297def V6_vsubbsat : HInst<
36298(outs HvxVR:$Vd32),
36299(ins HvxVR:$Vu32, HvxVR:$Vv32),
36300"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
36301tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
36302let Inst{7-5} = 0b010;
36303let Inst{13-13} = 0b0;
36304let Inst{31-21} = 0b00011111001;
36305let hasNewValue = 1;
36306let opNewValue = 0;
36307let DecoderNamespace = "EXT_mmvec";
36308}
36309def V6_vsubbsat_alt : HInst<
36310(outs HvxVR:$Vd32),
36311(ins HvxVR:$Vu32, HvxVR:$Vv32),
36312"$Vd32 = vsubb($Vu32,$Vv32):sat",
36313PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36314let hasNewValue = 1;
36315let opNewValue = 0;
36316let isPseudo = 1;
36317let isCodeGenOnly = 1;
36318let DecoderNamespace = "EXT_mmvec";
36319}
36320def V6_vsubbsat_dv : HInst<
36321(outs HvxWR:$Vdd32),
36322(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36323"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
36324tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
36325let Inst{7-5} = 0b001;
36326let Inst{13-13} = 0b0;
36327let Inst{31-21} = 0b00011110101;
36328let hasNewValue = 1;
36329let opNewValue = 0;
36330let DecoderNamespace = "EXT_mmvec";
36331}
36332def V6_vsubbsat_dv_alt : HInst<
36333(outs HvxWR:$Vdd32),
36334(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36335"$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
36336PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36337let hasNewValue = 1;
36338let opNewValue = 0;
36339let isPseudo = 1;
36340let isCodeGenOnly = 1;
36341let DecoderNamespace = "EXT_mmvec";
36342}
36343def V6_vsubcarry : HInst<
36344(outs HvxVR:$Vd32, HvxQR:$Qx4),
36345(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
36346"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
36347tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
36348let Inst{7-7} = 0b1;
36349let Inst{13-13} = 0b1;
36350let Inst{31-21} = 0b00011100101;
36351let hasNewValue = 1;
36352let opNewValue = 0;
36353let DecoderNamespace = "EXT_mmvec";
36354let Constraints = "$Qx4 = $Qx4in";
36355}
36356def V6_vsubcarryo : HInst<
36357(outs HvxVR:$Vd32, HvxQR:$Qe4),
36358(ins HvxVR:$Vu32, HvxVR:$Vv32),
36359"$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry",
36360tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> {
36361let Inst{7-7} = 0b1;
36362let Inst{13-13} = 0b1;
36363let Inst{31-21} = 0b00011101101;
36364let hasNewValue = 1;
36365let opNewValue = 0;
36366let hasNewValue2 = 1;
36367let opNewValue2 = 1;
36368let DecoderNamespace = "EXT_mmvec";
36369}
36370def V6_vsubh : HInst<
36371(outs HvxVR:$Vd32),
36372(ins HvxVR:$Vu32, HvxVR:$Vv32),
36373"$Vd32.h = vsub($Vu32.h,$Vv32.h)",
36374tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36375let Inst{7-5} = 0b110;
36376let Inst{13-13} = 0b0;
36377let Inst{31-21} = 0b00011100010;
36378let hasNewValue = 1;
36379let opNewValue = 0;
36380let DecoderNamespace = "EXT_mmvec";
36381}
36382def V6_vsubh_alt : HInst<
36383(outs HvxVR:$Vd32),
36384(ins HvxVR:$Vu32, HvxVR:$Vv32),
36385"$Vd32 = vsubh($Vu32,$Vv32)",
36386PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36387let hasNewValue = 1;
36388let opNewValue = 0;
36389let isPseudo = 1;
36390let isCodeGenOnly = 1;
36391let DecoderNamespace = "EXT_mmvec";
36392}
36393def V6_vsubh_dv : HInst<
36394(outs HvxWR:$Vdd32),
36395(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36396"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
36397tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36398let Inst{7-5} = 0b100;
36399let Inst{13-13} = 0b0;
36400let Inst{31-21} = 0b00011100100;
36401let hasNewValue = 1;
36402let opNewValue = 0;
36403let DecoderNamespace = "EXT_mmvec";
36404}
36405def V6_vsubh_dv_alt : HInst<
36406(outs HvxWR:$Vdd32),
36407(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36408"$Vdd32 = vsubh($Vuu32,$Vvv32)",
36409PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36410let hasNewValue = 1;
36411let opNewValue = 0;
36412let isPseudo = 1;
36413let isCodeGenOnly = 1;
36414let DecoderNamespace = "EXT_mmvec";
36415}
36416def V6_vsubhnq : HInst<
36417(outs HvxVR:$Vx32),
36418(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36419"if (!$Qv4) $Vx32.h -= $Vu32.h",
36420tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36421let Inst{7-5} = 0b010;
36422let Inst{13-13} = 0b1;
36423let Inst{21-16} = 0b000010;
36424let Inst{31-24} = 0b00011110;
36425let hasNewValue = 1;
36426let opNewValue = 0;
36427let DecoderNamespace = "EXT_mmvec";
36428let Constraints = "$Vx32 = $Vx32in";
36429}
36430def V6_vsubhnq_alt : HInst<
36431(outs HvxVR:$Vx32),
36432(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36433"if (!$Qv4.h) $Vx32.h -= $Vu32.h",
36434PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36435let hasNewValue = 1;
36436let opNewValue = 0;
36437let isPseudo = 1;
36438let isCodeGenOnly = 1;
36439let DecoderNamespace = "EXT_mmvec";
36440let Constraints = "$Vx32 = $Vx32in";
36441}
36442def V6_vsubhq : HInst<
36443(outs HvxVR:$Vx32),
36444(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36445"if ($Qv4) $Vx32.h -= $Vu32.h",
36446tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36447let Inst{7-5} = 0b111;
36448let Inst{13-13} = 0b1;
36449let Inst{21-16} = 0b000001;
36450let Inst{31-24} = 0b00011110;
36451let hasNewValue = 1;
36452let opNewValue = 0;
36453let DecoderNamespace = "EXT_mmvec";
36454let Constraints = "$Vx32 = $Vx32in";
36455}
36456def V6_vsubhq_alt : HInst<
36457(outs HvxVR:$Vx32),
36458(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36459"if ($Qv4.h) $Vx32.h -= $Vu32.h",
36460PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36461let hasNewValue = 1;
36462let opNewValue = 0;
36463let isPseudo = 1;
36464let isCodeGenOnly = 1;
36465let DecoderNamespace = "EXT_mmvec";
36466let Constraints = "$Vx32 = $Vx32in";
36467}
36468def V6_vsubhsat : HInst<
36469(outs HvxVR:$Vd32),
36470(ins HvxVR:$Vu32, HvxVR:$Vv32),
36471"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
36472tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36473let Inst{7-5} = 0b010;
36474let Inst{13-13} = 0b0;
36475let Inst{31-21} = 0b00011100011;
36476let hasNewValue = 1;
36477let opNewValue = 0;
36478let DecoderNamespace = "EXT_mmvec";
36479}
36480def V6_vsubhsat_alt : HInst<
36481(outs HvxVR:$Vd32),
36482(ins HvxVR:$Vu32, HvxVR:$Vv32),
36483"$Vd32 = vsubh($Vu32,$Vv32):sat",
36484PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36485let hasNewValue = 1;
36486let opNewValue = 0;
36487let isPseudo = 1;
36488let isCodeGenOnly = 1;
36489let DecoderNamespace = "EXT_mmvec";
36490}
36491def V6_vsubhsat_dv : HInst<
36492(outs HvxWR:$Vdd32),
36493(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36494"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
36495tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36496let Inst{7-5} = 0b000;
36497let Inst{13-13} = 0b0;
36498let Inst{31-21} = 0b00011100101;
36499let hasNewValue = 1;
36500let opNewValue = 0;
36501let DecoderNamespace = "EXT_mmvec";
36502}
36503def V6_vsubhsat_dv_alt : HInst<
36504(outs HvxWR:$Vdd32),
36505(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36506"$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
36507PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36508let hasNewValue = 1;
36509let opNewValue = 0;
36510let isPseudo = 1;
36511let isCodeGenOnly = 1;
36512let DecoderNamespace = "EXT_mmvec";
36513}
36514def V6_vsubhw : HInst<
36515(outs HvxWR:$Vdd32),
36516(ins HvxVR:$Vu32, HvxVR:$Vv32),
36517"$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
36518tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36519let Inst{7-5} = 0b111;
36520let Inst{13-13} = 0b0;
36521let Inst{31-21} = 0b00011100101;
36522let hasNewValue = 1;
36523let opNewValue = 0;
36524let DecoderNamespace = "EXT_mmvec";
36525}
36526def V6_vsubhw_alt : HInst<
36527(outs HvxWR:$Vdd32),
36528(ins HvxVR:$Vu32, HvxVR:$Vv32),
36529"$Vdd32 = vsubh($Vu32,$Vv32)",
36530PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36531let hasNewValue = 1;
36532let opNewValue = 0;
36533let isPseudo = 1;
36534let isCodeGenOnly = 1;
36535let DecoderNamespace = "EXT_mmvec";
36536}
36537def V6_vsububh : HInst<
36538(outs HvxWR:$Vdd32),
36539(ins HvxVR:$Vu32, HvxVR:$Vv32),
36540"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
36541tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36542let Inst{7-5} = 0b101;
36543let Inst{13-13} = 0b0;
36544let Inst{31-21} = 0b00011100101;
36545let hasNewValue = 1;
36546let opNewValue = 0;
36547let DecoderNamespace = "EXT_mmvec";
36548}
36549def V6_vsububh_alt : HInst<
36550(outs HvxWR:$Vdd32),
36551(ins HvxVR:$Vu32, HvxVR:$Vv32),
36552"$Vdd32 = vsubub($Vu32,$Vv32)",
36553PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36554let hasNewValue = 1;
36555let opNewValue = 0;
36556let isPseudo = 1;
36557let isCodeGenOnly = 1;
36558let DecoderNamespace = "EXT_mmvec";
36559}
36560def V6_vsububsat : HInst<
36561(outs HvxVR:$Vd32),
36562(ins HvxVR:$Vu32, HvxVR:$Vv32),
36563"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
36564tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36565let Inst{7-5} = 0b000;
36566let Inst{13-13} = 0b0;
36567let Inst{31-21} = 0b00011100011;
36568let hasNewValue = 1;
36569let opNewValue = 0;
36570let DecoderNamespace = "EXT_mmvec";
36571}
36572def V6_vsububsat_alt : HInst<
36573(outs HvxVR:$Vd32),
36574(ins HvxVR:$Vu32, HvxVR:$Vv32),
36575"$Vd32 = vsubub($Vu32,$Vv32):sat",
36576PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36577let hasNewValue = 1;
36578let opNewValue = 0;
36579let isPseudo = 1;
36580let isCodeGenOnly = 1;
36581let DecoderNamespace = "EXT_mmvec";
36582}
36583def V6_vsububsat_dv : HInst<
36584(outs HvxWR:$Vdd32),
36585(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36586"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
36587tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36588let Inst{7-5} = 0b110;
36589let Inst{13-13} = 0b0;
36590let Inst{31-21} = 0b00011100100;
36591let hasNewValue = 1;
36592let opNewValue = 0;
36593let DecoderNamespace = "EXT_mmvec";
36594}
36595def V6_vsububsat_dv_alt : HInst<
36596(outs HvxWR:$Vdd32),
36597(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36598"$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
36599PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36600let hasNewValue = 1;
36601let opNewValue = 0;
36602let isPseudo = 1;
36603let isCodeGenOnly = 1;
36604let DecoderNamespace = "EXT_mmvec";
36605}
36606def V6_vsubububb_sat : HInst<
36607(outs HvxVR:$Vd32),
36608(ins HvxVR:$Vu32, HvxVR:$Vv32),
36609"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
36610tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
36611let Inst{7-5} = 0b101;
36612let Inst{13-13} = 0b0;
36613let Inst{31-21} = 0b00011110101;
36614let hasNewValue = 1;
36615let opNewValue = 0;
36616let DecoderNamespace = "EXT_mmvec";
36617}
36618def V6_vsubuhsat : HInst<
36619(outs HvxVR:$Vd32),
36620(ins HvxVR:$Vu32, HvxVR:$Vv32),
36621"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
36622tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36623let Inst{7-5} = 0b001;
36624let Inst{13-13} = 0b0;
36625let Inst{31-21} = 0b00011100011;
36626let hasNewValue = 1;
36627let opNewValue = 0;
36628let DecoderNamespace = "EXT_mmvec";
36629}
36630def V6_vsubuhsat_alt : HInst<
36631(outs HvxVR:$Vd32),
36632(ins HvxVR:$Vu32, HvxVR:$Vv32),
36633"$Vd32 = vsubuh($Vu32,$Vv32):sat",
36634PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36635let hasNewValue = 1;
36636let opNewValue = 0;
36637let isPseudo = 1;
36638let isCodeGenOnly = 1;
36639let DecoderNamespace = "EXT_mmvec";
36640}
36641def V6_vsubuhsat_dv : HInst<
36642(outs HvxWR:$Vdd32),
36643(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36644"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
36645tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36646let Inst{7-5} = 0b111;
36647let Inst{13-13} = 0b0;
36648let Inst{31-21} = 0b00011100100;
36649let hasNewValue = 1;
36650let opNewValue = 0;
36651let DecoderNamespace = "EXT_mmvec";
36652}
36653def V6_vsubuhsat_dv_alt : HInst<
36654(outs HvxWR:$Vdd32),
36655(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36656"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
36657PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36658let hasNewValue = 1;
36659let opNewValue = 0;
36660let isPseudo = 1;
36661let isCodeGenOnly = 1;
36662let DecoderNamespace = "EXT_mmvec";
36663}
36664def V6_vsubuhw : HInst<
36665(outs HvxWR:$Vdd32),
36666(ins HvxVR:$Vu32, HvxVR:$Vv32),
36667"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
36668tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36669let Inst{7-5} = 0b110;
36670let Inst{13-13} = 0b0;
36671let Inst{31-21} = 0b00011100101;
36672let hasNewValue = 1;
36673let opNewValue = 0;
36674let DecoderNamespace = "EXT_mmvec";
36675}
36676def V6_vsubuhw_alt : HInst<
36677(outs HvxWR:$Vdd32),
36678(ins HvxVR:$Vu32, HvxVR:$Vv32),
36679"$Vdd32 = vsubuh($Vu32,$Vv32)",
36680PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36681let hasNewValue = 1;
36682let opNewValue = 0;
36683let isPseudo = 1;
36684let isCodeGenOnly = 1;
36685let DecoderNamespace = "EXT_mmvec";
36686}
36687def V6_vsubuwsat : HInst<
36688(outs HvxVR:$Vd32),
36689(ins HvxVR:$Vu32, HvxVR:$Vv32),
36690"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
36691tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
36692let Inst{7-5} = 0b100;
36693let Inst{13-13} = 0b0;
36694let Inst{31-21} = 0b00011111110;
36695let hasNewValue = 1;
36696let opNewValue = 0;
36697let DecoderNamespace = "EXT_mmvec";
36698}
36699def V6_vsubuwsat_alt : HInst<
36700(outs HvxVR:$Vd32),
36701(ins HvxVR:$Vu32, HvxVR:$Vv32),
36702"$Vd32 = vsubuw($Vu32,$Vv32):sat",
36703PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36704let hasNewValue = 1;
36705let opNewValue = 0;
36706let isPseudo = 1;
36707let isCodeGenOnly = 1;
36708let DecoderNamespace = "EXT_mmvec";
36709}
36710def V6_vsubuwsat_dv : HInst<
36711(outs HvxWR:$Vdd32),
36712(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36713"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
36714tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
36715let Inst{7-5} = 0b011;
36716let Inst{13-13} = 0b0;
36717let Inst{31-21} = 0b00011110101;
36718let hasNewValue = 1;
36719let opNewValue = 0;
36720let DecoderNamespace = "EXT_mmvec";
36721}
36722def V6_vsubuwsat_dv_alt : HInst<
36723(outs HvxWR:$Vdd32),
36724(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36725"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
36726PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36727let hasNewValue = 1;
36728let opNewValue = 0;
36729let isPseudo = 1;
36730let isCodeGenOnly = 1;
36731let DecoderNamespace = "EXT_mmvec";
36732}
36733def V6_vsubw : HInst<
36734(outs HvxVR:$Vd32),
36735(ins HvxVR:$Vu32, HvxVR:$Vv32),
36736"$Vd32.w = vsub($Vu32.w,$Vv32.w)",
36737tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36738let Inst{7-5} = 0b111;
36739let Inst{13-13} = 0b0;
36740let Inst{31-21} = 0b00011100010;
36741let hasNewValue = 1;
36742let opNewValue = 0;
36743let DecoderNamespace = "EXT_mmvec";
36744}
36745def V6_vsubw_alt : HInst<
36746(outs HvxVR:$Vd32),
36747(ins HvxVR:$Vu32, HvxVR:$Vv32),
36748"$Vd32 = vsubw($Vu32,$Vv32)",
36749PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36750let hasNewValue = 1;
36751let opNewValue = 0;
36752let isPseudo = 1;
36753let isCodeGenOnly = 1;
36754let DecoderNamespace = "EXT_mmvec";
36755}
36756def V6_vsubw_dv : HInst<
36757(outs HvxWR:$Vdd32),
36758(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36759"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
36760tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36761let Inst{7-5} = 0b101;
36762let Inst{13-13} = 0b0;
36763let Inst{31-21} = 0b00011100100;
36764let hasNewValue = 1;
36765let opNewValue = 0;
36766let DecoderNamespace = "EXT_mmvec";
36767}
36768def V6_vsubw_dv_alt : HInst<
36769(outs HvxWR:$Vdd32),
36770(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36771"$Vdd32 = vsubw($Vuu32,$Vvv32)",
36772PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36773let hasNewValue = 1;
36774let opNewValue = 0;
36775let isPseudo = 1;
36776let isCodeGenOnly = 1;
36777let DecoderNamespace = "EXT_mmvec";
36778}
36779def V6_vsubwnq : HInst<
36780(outs HvxVR:$Vx32),
36781(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36782"if (!$Qv4) $Vx32.w -= $Vu32.w",
36783tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36784let Inst{7-5} = 0b011;
36785let Inst{13-13} = 0b1;
36786let Inst{21-16} = 0b000010;
36787let Inst{31-24} = 0b00011110;
36788let hasNewValue = 1;
36789let opNewValue = 0;
36790let DecoderNamespace = "EXT_mmvec";
36791let Constraints = "$Vx32 = $Vx32in";
36792}
36793def V6_vsubwnq_alt : HInst<
36794(outs HvxVR:$Vx32),
36795(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36796"if (!$Qv4.w) $Vx32.w -= $Vu32.w",
36797PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36798let hasNewValue = 1;
36799let opNewValue = 0;
36800let isPseudo = 1;
36801let isCodeGenOnly = 1;
36802let DecoderNamespace = "EXT_mmvec";
36803let Constraints = "$Vx32 = $Vx32in";
36804}
36805def V6_vsubwq : HInst<
36806(outs HvxVR:$Vx32),
36807(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36808"if ($Qv4) $Vx32.w -= $Vu32.w",
36809tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
36810let Inst{7-5} = 0b000;
36811let Inst{13-13} = 0b1;
36812let Inst{21-16} = 0b000010;
36813let Inst{31-24} = 0b00011110;
36814let hasNewValue = 1;
36815let opNewValue = 0;
36816let DecoderNamespace = "EXT_mmvec";
36817let Constraints = "$Vx32 = $Vx32in";
36818}
36819def V6_vsubwq_alt : HInst<
36820(outs HvxVR:$Vx32),
36821(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
36822"if ($Qv4.w) $Vx32.w -= $Vu32.w",
36823PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36824let hasNewValue = 1;
36825let opNewValue = 0;
36826let isPseudo = 1;
36827let isCodeGenOnly = 1;
36828let DecoderNamespace = "EXT_mmvec";
36829let Constraints = "$Vx32 = $Vx32in";
36830}
36831def V6_vsubwsat : HInst<
36832(outs HvxVR:$Vd32),
36833(ins HvxVR:$Vu32, HvxVR:$Vv32),
36834"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
36835tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36836let Inst{7-5} = 0b011;
36837let Inst{13-13} = 0b0;
36838let Inst{31-21} = 0b00011100011;
36839let hasNewValue = 1;
36840let opNewValue = 0;
36841let DecoderNamespace = "EXT_mmvec";
36842}
36843def V6_vsubwsat_alt : HInst<
36844(outs HvxVR:$Vd32),
36845(ins HvxVR:$Vu32, HvxVR:$Vv32),
36846"$Vd32 = vsubw($Vu32,$Vv32):sat",
36847PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36848let hasNewValue = 1;
36849let opNewValue = 0;
36850let isPseudo = 1;
36851let isCodeGenOnly = 1;
36852let DecoderNamespace = "EXT_mmvec";
36853}
36854def V6_vsubwsat_dv : HInst<
36855(outs HvxWR:$Vdd32),
36856(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36857"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
36858tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
36859let Inst{7-5} = 0b001;
36860let Inst{13-13} = 0b0;
36861let Inst{31-21} = 0b00011100101;
36862let hasNewValue = 1;
36863let opNewValue = 0;
36864let DecoderNamespace = "EXT_mmvec";
36865}
36866def V6_vsubwsat_dv_alt : HInst<
36867(outs HvxWR:$Vdd32),
36868(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
36869"$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
36870PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36871let hasNewValue = 1;
36872let opNewValue = 0;
36873let isPseudo = 1;
36874let isCodeGenOnly = 1;
36875let DecoderNamespace = "EXT_mmvec";
36876}
36877def V6_vswap : HInst<
36878(outs HvxWR:$Vdd32),
36879(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
36880"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
36881tc_71646d06, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
36882let Inst{7-7} = 0b0;
36883let Inst{13-13} = 0b1;
36884let Inst{31-21} = 0b00011110101;
36885let hasNewValue = 1;
36886let opNewValue = 0;
36887let DecoderNamespace = "EXT_mmvec";
36888}
36889def V6_vtmpyb : HInst<
36890(outs HvxWR:$Vdd32),
36891(ins HvxWR:$Vuu32, IntRegs:$Rt32),
36892"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
36893tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
36894let Inst{7-5} = 0b000;
36895let Inst{13-13} = 0b0;
36896let Inst{31-21} = 0b00011001000;
36897let hasNewValue = 1;
36898let opNewValue = 0;
36899let DecoderNamespace = "EXT_mmvec";
36900}
36901def V6_vtmpyb_acc : HInst<
36902(outs HvxWR:$Vxx32),
36903(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36904"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
36905tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
36906let Inst{7-5} = 0b000;
36907let Inst{13-13} = 0b1;
36908let Inst{31-21} = 0b00011001000;
36909let hasNewValue = 1;
36910let opNewValue = 0;
36911let isAccumulator = 1;
36912let DecoderNamespace = "EXT_mmvec";
36913let Constraints = "$Vxx32 = $Vxx32in";
36914}
36915def V6_vtmpyb_acc_alt : HInst<
36916(outs HvxWR:$Vxx32),
36917(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36918"$Vxx32 += vtmpyb($Vuu32,$Rt32)",
36919PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36920let hasNewValue = 1;
36921let opNewValue = 0;
36922let isAccumulator = 1;
36923let isPseudo = 1;
36924let isCodeGenOnly = 1;
36925let DecoderNamespace = "EXT_mmvec";
36926let Constraints = "$Vxx32 = $Vxx32in";
36927}
36928def V6_vtmpyb_alt : HInst<
36929(outs HvxWR:$Vdd32),
36930(ins HvxWR:$Vuu32, IntRegs:$Rt32),
36931"$Vdd32 = vtmpyb($Vuu32,$Rt32)",
36932PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36933let hasNewValue = 1;
36934let opNewValue = 0;
36935let isPseudo = 1;
36936let isCodeGenOnly = 1;
36937let DecoderNamespace = "EXT_mmvec";
36938}
36939def V6_vtmpybus : HInst<
36940(outs HvxWR:$Vdd32),
36941(ins HvxWR:$Vuu32, IntRegs:$Rt32),
36942"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
36943tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
36944let Inst{7-5} = 0b001;
36945let Inst{13-13} = 0b0;
36946let Inst{31-21} = 0b00011001000;
36947let hasNewValue = 1;
36948let opNewValue = 0;
36949let DecoderNamespace = "EXT_mmvec";
36950}
36951def V6_vtmpybus_acc : HInst<
36952(outs HvxWR:$Vxx32),
36953(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36954"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
36955tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
36956let Inst{7-5} = 0b001;
36957let Inst{13-13} = 0b1;
36958let Inst{31-21} = 0b00011001000;
36959let hasNewValue = 1;
36960let opNewValue = 0;
36961let isAccumulator = 1;
36962let DecoderNamespace = "EXT_mmvec";
36963let Constraints = "$Vxx32 = $Vxx32in";
36964}
36965def V6_vtmpybus_acc_alt : HInst<
36966(outs HvxWR:$Vxx32),
36967(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
36968"$Vxx32 += vtmpybus($Vuu32,$Rt32)",
36969PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36970let hasNewValue = 1;
36971let opNewValue = 0;
36972let isAccumulator = 1;
36973let isPseudo = 1;
36974let isCodeGenOnly = 1;
36975let DecoderNamespace = "EXT_mmvec";
36976let Constraints = "$Vxx32 = $Vxx32in";
36977}
36978def V6_vtmpybus_alt : HInst<
36979(outs HvxWR:$Vdd32),
36980(ins HvxWR:$Vuu32, IntRegs:$Rt32),
36981"$Vdd32 = vtmpybus($Vuu32,$Rt32)",
36982PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36983let hasNewValue = 1;
36984let opNewValue = 0;
36985let isPseudo = 1;
36986let isCodeGenOnly = 1;
36987let DecoderNamespace = "EXT_mmvec";
36988}
36989def V6_vtmpyhb : HInst<
36990(outs HvxWR:$Vdd32),
36991(ins HvxWR:$Vuu32, IntRegs:$Rt32),
36992"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
36993tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
36994let Inst{7-5} = 0b100;
36995let Inst{13-13} = 0b0;
36996let Inst{31-21} = 0b00011001101;
36997let hasNewValue = 1;
36998let opNewValue = 0;
36999let DecoderNamespace = "EXT_mmvec";
37000}
37001def V6_vtmpyhb_acc : HInst<
37002(outs HvxWR:$Vxx32),
37003(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
37004"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
37005tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
37006let Inst{7-5} = 0b010;
37007let Inst{13-13} = 0b1;
37008let Inst{31-21} = 0b00011001000;
37009let hasNewValue = 1;
37010let opNewValue = 0;
37011let isAccumulator = 1;
37012let DecoderNamespace = "EXT_mmvec";
37013let Constraints = "$Vxx32 = $Vxx32in";
37014}
37015def V6_vtmpyhb_acc_alt : HInst<
37016(outs HvxWR:$Vxx32),
37017(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
37018"$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
37019PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37020let hasNewValue = 1;
37021let opNewValue = 0;
37022let isAccumulator = 1;
37023let isPseudo = 1;
37024let isCodeGenOnly = 1;
37025let DecoderNamespace = "EXT_mmvec";
37026let Constraints = "$Vxx32 = $Vxx32in";
37027}
37028def V6_vtmpyhb_alt : HInst<
37029(outs HvxWR:$Vdd32),
37030(ins HvxWR:$Vuu32, IntRegs:$Rt32),
37031"$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
37032PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37033let hasNewValue = 1;
37034let opNewValue = 0;
37035let isPseudo = 1;
37036let isCodeGenOnly = 1;
37037let DecoderNamespace = "EXT_mmvec";
37038}
37039def V6_vtran2x2_map : HInst<
37040(outs HvxVR:$Vy32, HvxVR:$Vx32),
37041(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
37042"vtrans2x2($Vy32,$Vx32,$Rt32)",
37043PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37044let hasNewValue = 1;
37045let opNewValue = 0;
37046let hasNewValue2 = 1;
37047let opNewValue2 = 1;
37048let isPseudo = 1;
37049let isCodeGenOnly = 1;
37050let DecoderNamespace = "EXT_mmvec";
37051let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
37052}
37053def V6_vunpackb : HInst<
37054(outs HvxWR:$Vdd32),
37055(ins HvxVR:$Vu32),
37056"$Vdd32.h = vunpack($Vu32.b)",
37057tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
37058let Inst{7-5} = 0b010;
37059let Inst{13-13} = 0b0;
37060let Inst{31-16} = 0b0001111000000001;
37061let hasNewValue = 1;
37062let opNewValue = 0;
37063let DecoderNamespace = "EXT_mmvec";
37064}
37065def V6_vunpackb_alt : HInst<
37066(outs HvxWR:$Vdd32),
37067(ins HvxVR:$Vu32),
37068"$Vdd32 = vunpackb($Vu32)",
37069PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37070let hasNewValue = 1;
37071let opNewValue = 0;
37072let isPseudo = 1;
37073let isCodeGenOnly = 1;
37074let DecoderNamespace = "EXT_mmvec";
37075}
37076def V6_vunpackh : HInst<
37077(outs HvxWR:$Vdd32),
37078(ins HvxVR:$Vu32),
37079"$Vdd32.w = vunpack($Vu32.h)",
37080tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
37081let Inst{7-5} = 0b011;
37082let Inst{13-13} = 0b0;
37083let Inst{31-16} = 0b0001111000000001;
37084let hasNewValue = 1;
37085let opNewValue = 0;
37086let DecoderNamespace = "EXT_mmvec";
37087}
37088def V6_vunpackh_alt : HInst<
37089(outs HvxWR:$Vdd32),
37090(ins HvxVR:$Vu32),
37091"$Vdd32 = vunpackh($Vu32)",
37092PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37093let hasNewValue = 1;
37094let opNewValue = 0;
37095let isPseudo = 1;
37096let isCodeGenOnly = 1;
37097let DecoderNamespace = "EXT_mmvec";
37098}
37099def V6_vunpackob : HInst<
37100(outs HvxWR:$Vxx32),
37101(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
37102"$Vxx32.h |= vunpacko($Vu32.b)",
37103tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
37104let Inst{7-5} = 0b000;
37105let Inst{13-13} = 0b1;
37106let Inst{31-16} = 0b0001111000000000;
37107let hasNewValue = 1;
37108let opNewValue = 0;
37109let isAccumulator = 1;
37110let DecoderNamespace = "EXT_mmvec";
37111let Constraints = "$Vxx32 = $Vxx32in";
37112}
37113def V6_vunpackob_alt : HInst<
37114(outs HvxWR:$Vxx32),
37115(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
37116"$Vxx32 |= vunpackob($Vu32)",
37117PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37118let hasNewValue = 1;
37119let opNewValue = 0;
37120let isAccumulator = 1;
37121let isPseudo = 1;
37122let DecoderNamespace = "EXT_mmvec";
37123let Constraints = "$Vxx32 = $Vxx32in";
37124}
37125def V6_vunpackoh : HInst<
37126(outs HvxWR:$Vxx32),
37127(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
37128"$Vxx32.w |= vunpacko($Vu32.h)",
37129tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
37130let Inst{7-5} = 0b001;
37131let Inst{13-13} = 0b1;
37132let Inst{31-16} = 0b0001111000000000;
37133let hasNewValue = 1;
37134let opNewValue = 0;
37135let isAccumulator = 1;
37136let DecoderNamespace = "EXT_mmvec";
37137let Constraints = "$Vxx32 = $Vxx32in";
37138}
37139def V6_vunpackoh_alt : HInst<
37140(outs HvxWR:$Vxx32),
37141(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
37142"$Vxx32 |= vunpackoh($Vu32)",
37143PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37144let hasNewValue = 1;
37145let opNewValue = 0;
37146let isAccumulator = 1;
37147let isPseudo = 1;
37148let isCodeGenOnly = 1;
37149let DecoderNamespace = "EXT_mmvec";
37150let Constraints = "$Vxx32 = $Vxx32in";
37151}
37152def V6_vunpackub : HInst<
37153(outs HvxWR:$Vdd32),
37154(ins HvxVR:$Vu32),
37155"$Vdd32.uh = vunpack($Vu32.ub)",
37156tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
37157let Inst{7-5} = 0b000;
37158let Inst{13-13} = 0b0;
37159let Inst{31-16} = 0b0001111000000001;
37160let hasNewValue = 1;
37161let opNewValue = 0;
37162let DecoderNamespace = "EXT_mmvec";
37163}
37164def V6_vunpackub_alt : HInst<
37165(outs HvxWR:$Vdd32),
37166(ins HvxVR:$Vu32),
37167"$Vdd32 = vunpackub($Vu32)",
37168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37169let hasNewValue = 1;
37170let opNewValue = 0;
37171let isPseudo = 1;
37172let isCodeGenOnly = 1;
37173let DecoderNamespace = "EXT_mmvec";
37174}
37175def V6_vunpackuh : HInst<
37176(outs HvxWR:$Vdd32),
37177(ins HvxVR:$Vu32),
37178"$Vdd32.uw = vunpack($Vu32.uh)",
37179tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
37180let Inst{7-5} = 0b001;
37181let Inst{13-13} = 0b0;
37182let Inst{31-16} = 0b0001111000000001;
37183let hasNewValue = 1;
37184let opNewValue = 0;
37185let DecoderNamespace = "EXT_mmvec";
37186}
37187def V6_vunpackuh_alt : HInst<
37188(outs HvxWR:$Vdd32),
37189(ins HvxVR:$Vu32),
37190"$Vdd32 = vunpackuh($Vu32)",
37191PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37192let hasNewValue = 1;
37193let opNewValue = 0;
37194let isPseudo = 1;
37195let isCodeGenOnly = 1;
37196let DecoderNamespace = "EXT_mmvec";
37197}
37198def V6_vwhist128 : HInst<
37199(outs),
37200(ins),
37201"vwhist128",
37202tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
37203let Inst{13-0} = 0b10010010000000;
37204let Inst{31-16} = 0b0001111000000000;
37205let DecoderNamespace = "EXT_mmvec";
37206}
37207def V6_vwhist128m : HInst<
37208(outs),
37209(ins u1_0Imm:$Ii),
37210"vwhist128(#$Ii)",
37211tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
37212let Inst{7-0} = 0b10000000;
37213let Inst{13-9} = 0b10011;
37214let Inst{31-16} = 0b0001111000000000;
37215let DecoderNamespace = "EXT_mmvec";
37216}
37217def V6_vwhist128q : HInst<
37218(outs),
37219(ins HvxQR:$Qv4),
37220"vwhist128($Qv4)",
37221tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
37222let Inst{13-0} = 0b10010010000000;
37223let Inst{21-16} = 0b000010;
37224let Inst{31-24} = 0b00011110;
37225let DecoderNamespace = "EXT_mmvec";
37226}
37227def V6_vwhist128qm : HInst<
37228(outs),
37229(ins HvxQR:$Qv4, u1_0Imm:$Ii),
37230"vwhist128($Qv4,#$Ii)",
37231tc_767c4e9d, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
37232let Inst{7-0} = 0b10000000;
37233let Inst{13-9} = 0b10011;
37234let Inst{21-16} = 0b000010;
37235let Inst{31-24} = 0b00011110;
37236let DecoderNamespace = "EXT_mmvec";
37237}
37238def V6_vwhist256 : HInst<
37239(outs),
37240(ins),
37241"vwhist256",
37242tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
37243let Inst{13-0} = 0b10001010000000;
37244let Inst{31-16} = 0b0001111000000000;
37245let DecoderNamespace = "EXT_mmvec";
37246}
37247def V6_vwhist256_sat : HInst<
37248(outs),
37249(ins),
37250"vwhist256:sat",
37251tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
37252let Inst{13-0} = 0b10001110000000;
37253let Inst{31-16} = 0b0001111000000000;
37254let DecoderNamespace = "EXT_mmvec";
37255}
37256def V6_vwhist256q : HInst<
37257(outs),
37258(ins HvxQR:$Qv4),
37259"vwhist256($Qv4)",
37260tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
37261let Inst{13-0} = 0b10001010000000;
37262let Inst{21-16} = 0b000010;
37263let Inst{31-24} = 0b00011110;
37264let DecoderNamespace = "EXT_mmvec";
37265}
37266def V6_vwhist256q_sat : HInst<
37267(outs),
37268(ins HvxQR:$Qv4),
37269"vwhist256($Qv4):sat",
37270tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
37271let Inst{13-0} = 0b10001110000000;
37272let Inst{21-16} = 0b000010;
37273let Inst{31-24} = 0b00011110;
37274let DecoderNamespace = "EXT_mmvec";
37275}
37276def V6_vxor : HInst<
37277(outs HvxVR:$Vd32),
37278(ins HvxVR:$Vu32, HvxVR:$Vv32),
37279"$Vd32 = vxor($Vu32,$Vv32)",
37280tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37281let Inst{7-5} = 0b111;
37282let Inst{13-13} = 0b0;
37283let Inst{31-21} = 0b00011100001;
37284let hasNewValue = 1;
37285let opNewValue = 0;
37286let DecoderNamespace = "EXT_mmvec";
37287}
37288def V6_vzb : HInst<
37289(outs HvxWR:$Vdd32),
37290(ins HvxVR:$Vu32),
37291"$Vdd32.uh = vzxt($Vu32.ub)",
37292tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
37293let Inst{7-5} = 0b001;
37294let Inst{13-13} = 0b0;
37295let Inst{31-16} = 0b0001111000000010;
37296let hasNewValue = 1;
37297let opNewValue = 0;
37298let DecoderNamespace = "EXT_mmvec";
37299}
37300def V6_vzb_alt : HInst<
37301(outs HvxWR:$Vdd32),
37302(ins HvxVR:$Vu32),
37303"$Vdd32 = vzxtb($Vu32)",
37304PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37305let hasNewValue = 1;
37306let opNewValue = 0;
37307let isPseudo = 1;
37308let isCodeGenOnly = 1;
37309let DecoderNamespace = "EXT_mmvec";
37310}
37311def V6_vzh : HInst<
37312(outs HvxWR:$Vdd32),
37313(ins HvxVR:$Vu32),
37314"$Vdd32.uw = vzxt($Vu32.uh)",
37315tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
37316let Inst{7-5} = 0b010;
37317let Inst{13-13} = 0b0;
37318let Inst{31-16} = 0b0001111000000010;
37319let hasNewValue = 1;
37320let opNewValue = 0;
37321let DecoderNamespace = "EXT_mmvec";
37322}
37323def V6_vzh_alt : HInst<
37324(outs HvxWR:$Vdd32),
37325(ins HvxVR:$Vu32),
37326"$Vdd32 = vzxth($Vu32)",
37327PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37328let hasNewValue = 1;
37329let opNewValue = 0;
37330let isPseudo = 1;
37331let isCodeGenOnly = 1;
37332let DecoderNamespace = "EXT_mmvec";
37333}
37334def V6_zLd_ai : HInst<
37335(outs),
37336(ins IntRegs:$Rt32, s4_0Imm:$Ii),
37337"z = vmem($Rt32+#$Ii)",
37338tc_e699ae41, TypeCVI_ZW>, Enc_ff3442, Requires<[UseHVXV66,UseZReg]> {
37339let Inst{7-0} = 0b00000000;
37340let Inst{12-11} = 0b00;
37341let Inst{31-21} = 0b00101100000;
37342let addrMode = BaseImmOffset;
37343let mayLoad = 1;
37344let isRestrictNoSlot1Store = 1;
37345let DecoderNamespace = "EXT_mmvec";
37346}
37347def V6_zLd_pi : HInst<
37348(outs IntRegs:$Rx32),
37349(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
37350"z = vmem($Rx32++#$Ii)",
37351tc_a0dbea28, TypeCVI_ZW>, Enc_6c9ee0, Requires<[UseHVXV66,UseZReg]> {
37352let Inst{7-0} = 0b00000000;
37353let Inst{13-11} = 0b000;
37354let Inst{31-21} = 0b00101101000;
37355let addrMode = PostInc;
37356let mayLoad = 1;
37357let isRestrictNoSlot1Store = 1;
37358let DecoderNamespace = "EXT_mmvec";
37359let Constraints = "$Rx32 = $Rx32in";
37360}
37361def V6_zLd_ppu : HInst<
37362(outs IntRegs:$Rx32),
37363(ins IntRegs:$Rx32in, ModRegs:$Mu2),
37364"z = vmem($Rx32++$Mu2)",
37365tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> {
37366let Inst{12-0} = 0b0000000000001;
37367let Inst{31-21} = 0b00101101000;
37368let addrMode = PostInc;
37369let mayLoad = 1;
37370let isRestrictNoSlot1Store = 1;
37371let DecoderNamespace = "EXT_mmvec";
37372let Constraints = "$Rx32 = $Rx32in";
37373}
37374def V6_zLd_pred_ai : HInst<
37375(outs),
37376(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
37377"if ($Pv4) z = vmem($Rt32+#$Ii)",
37378tc_dd5b0695, TypeCVI_ZW>, Enc_ef601b, Requires<[UseHVXV66,UseZReg]> {
37379let Inst{7-0} = 0b00000000;
37380let Inst{31-21} = 0b00101100100;
37381let isPredicated = 1;
37382let addrMode = BaseImmOffset;
37383let mayLoad = 1;
37384let isRestrictNoSlot1Store = 1;
37385let DecoderNamespace = "EXT_mmvec";
37386}
37387def V6_zLd_pred_pi : HInst<
37388(outs IntRegs:$Rx32),
37389(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
37390"if ($Pv4) z = vmem($Rx32++#$Ii)",
37391tc_3ad719fb, TypeCVI_ZW>, Enc_6baed4, Requires<[UseHVXV66,UseZReg]> {
37392let Inst{7-0} = 0b00000000;
37393let Inst{13-13} = 0b0;
37394let Inst{31-21} = 0b00101101100;
37395let isPredicated = 1;
37396let addrMode = PostInc;
37397let mayLoad = 1;
37398let isRestrictNoSlot1Store = 1;
37399let DecoderNamespace = "EXT_mmvec";
37400let Constraints = "$Rx32 = $Rx32in";
37401}
37402def V6_zLd_pred_ppu : HInst<
37403(outs IntRegs:$Rx32),
37404(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
37405"if ($Pv4) z = vmem($Rx32++$Mu2)",
37406tc_3ad719fb, TypeCVI_ZW>, Enc_691712, Requires<[UseHVXV66,UseZReg]> {
37407let Inst{10-0} = 0b00000000001;
37408let Inst{31-21} = 0b00101101100;
37409let isPredicated = 1;
37410let addrMode = PostInc;
37411let mayLoad = 1;
37412let isRestrictNoSlot1Store = 1;
37413let DecoderNamespace = "EXT_mmvec";
37414let Constraints = "$Rx32 = $Rx32in";
37415}
37416def V6_zextract : HInst<
37417(outs HvxVR:$Vd32),
37418(ins IntRegs:$Rt32),
37419"$Vd32 = zextract($Rt32)",
37420tc_5bf8afbb, TypeCVI_VP>, Enc_a5ed8a, Requires<[UseHVXV66,UseZReg]> {
37421let Inst{13-5} = 0b000001001;
37422let Inst{31-21} = 0b00011001101;
37423let hasNewValue = 1;
37424let opNewValue = 0;
37425let DecoderNamespace = "EXT_mmvec";
37426}
37427def V6_zld0 : HInst<
37428(outs),
37429(ins IntRegs:$Rt32),
37430"z = vmem($Rt32)",
37431PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
37432let isPseudo = 1;
37433let isCodeGenOnly = 1;
37434let DecoderNamespace = "EXT_mmvec";
37435}
37436def V6_zldp0 : HInst<
37437(outs),
37438(ins PredRegs:$Pv4, IntRegs:$Rt32),
37439"if ($Pv4) z = vmem($Rt32)",
37440PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
37441let isPseudo = 1;
37442let isCodeGenOnly = 1;
37443let DecoderNamespace = "EXT_mmvec";
37444}
37445def Y2_barrier : HInst<
37446(outs),
37447(ins),
37448"barrier",
37449tc_8c99de45, TypeST>, Enc_e3b0c4 {
37450let Inst{13-0} = 0b00000000000000;
37451let Inst{31-16} = 0b1010100000000000;
37452let isSoloAX = 1;
37453let hasSideEffects = 1;
37454}
37455def Y2_break : HInst<
37456(outs),
37457(ins),
37458"brkpt",
37459tc_9ad9998f, TypeCR>, Enc_e3b0c4 {
37460let Inst{13-0} = 0b00000000000000;
37461let Inst{31-16} = 0b0110110000100000;
37462let isSolo = 1;
37463}
37464def Y2_dccleana : HInst<
37465(outs),
37466(ins IntRegs:$Rs32),
37467"dccleana($Rs32)",
37468tc_b857bf4e, TypeST>, Enc_ecbcc8 {
37469let Inst{13-0} = 0b00000000000000;
37470let Inst{31-21} = 0b10100000000;
37471let isRestrictSlot1AOK = 1;
37472let hasSideEffects = 1;
37473}
37474def Y2_dccleaninva : HInst<
37475(outs),
37476(ins IntRegs:$Rs32),
37477"dccleaninva($Rs32)",
37478tc_b857bf4e, TypeST>, Enc_ecbcc8 {
37479let Inst{13-0} = 0b00000000000000;
37480let Inst{31-21} = 0b10100000010;
37481let isRestrictSlot1AOK = 1;
37482let hasSideEffects = 1;
37483}
37484def Y2_dcfetch : HInst<
37485(outs),
37486(ins IntRegs:$Rs32),
37487"dcfetch($Rs32)",
37488tc_d63f638c, TypeMAPPING> {
37489let hasSideEffects = 1;
37490let isPseudo = 1;
37491let isCodeGenOnly = 1;
37492}
37493def Y2_dcfetchbo : HInst<
37494(outs),
37495(ins IntRegs:$Rs32, u11_3Imm:$Ii),
37496"dcfetch($Rs32+#$Ii)",
37497tc_9ca930f7, TypeLD>, Enc_2d829e {
37498let Inst{13-11} = 0b000;
37499let Inst{31-21} = 0b10010100000;
37500let addrMode = BaseImmOffset;
37501let isRestrictNoSlot1Store = 1;
37502let hasSideEffects = 1;
37503}
37504def Y2_dcinva : HInst<
37505(outs),
37506(ins IntRegs:$Rs32),
37507"dcinva($Rs32)",
37508tc_b857bf4e, TypeST>, Enc_ecbcc8 {
37509let Inst{13-0} = 0b00000000000000;
37510let Inst{31-21} = 0b10100000001;
37511let isRestrictSlot1AOK = 1;
37512let hasSideEffects = 1;
37513}
37514def Y2_dczeroa : HInst<
37515(outs),
37516(ins IntRegs:$Rs32),
37517"dczeroa($Rs32)",
37518tc_b857bf4e, TypeST>, Enc_ecbcc8 {
37519let Inst{13-0} = 0b00000000000000;
37520let Inst{31-21} = 0b10100000110;
37521let isRestrictSlot1AOK = 1;
37522let mayStore = 1;
37523let hasSideEffects = 1;
37524}
37525def Y2_icinva : HInst<
37526(outs),
37527(ins IntRegs:$Rs32),
37528"icinva($Rs32)",
37529tc_5d7f5414, TypeJ>, Enc_ecbcc8 {
37530let Inst{13-0} = 0b00000000000000;
37531let Inst{31-21} = 0b01010110110;
37532let isSolo = 1;
37533}
37534def Y2_isync : HInst<
37535(outs),
37536(ins),
37537"isync",
37538tc_8b121f4a, TypeJ>, Enc_e3b0c4 {
37539let Inst{13-0} = 0b00000000000010;
37540let Inst{31-16} = 0b0101011111000000;
37541let isSolo = 1;
37542}
37543def Y2_syncht : HInst<
37544(outs),
37545(ins),
37546"syncht",
37547tc_8c99de45, TypeST>, Enc_e3b0c4 {
37548let Inst{13-0} = 0b00000000000000;
37549let Inst{31-16} = 0b1010100001000000;
37550let isSolo = 1;
37551}
37552def Y2_wait : HInst<
37553(outs),
37554(ins IntRegs:$Rs32),
37555"wait($Rs32)",
37556tc_174516e8, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> {
37557let Inst{13-0} = 0b00000000000000;
37558let Inst{31-21} = 0b01100100010;
37559let isSolo = 1;
37560}
37561def Y4_l2fetch : HInst<
37562(outs),
37563(ins IntRegs:$Rs32, IntRegs:$Rt32),
37564"l2fetch($Rs32,$Rt32)",
37565tc_fe211424, TypeST>, Enc_ca3887 {
37566let Inst{7-0} = 0b00000000;
37567let Inst{13-13} = 0b0;
37568let Inst{31-21} = 0b10100110000;
37569let isSoloAX = 1;
37570let mayStore = 1;
37571let hasSideEffects = 1;
37572}
37573def Y4_trace : HInst<
37574(outs),
37575(ins IntRegs:$Rs32),
37576"trace($Rs32)",
37577tc_6b25e783, TypeCR>, Enc_ecbcc8 {
37578let Inst{13-0} = 0b00000000000000;
37579let Inst{31-21} = 0b01100010010;
37580let isSoloAX = 1;
37581}
37582def Y5_l2fetch : HInst<
37583(outs),
37584(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
37585"l2fetch($Rs32,$Rtt32)",
37586tc_fe211424, TypeST>, Enc_e6abcf {
37587let Inst{7-0} = 0b00000000;
37588let Inst{13-13} = 0b0;
37589let Inst{31-21} = 0b10100110100;
37590let isSoloAX = 1;
37591let mayStore = 1;
37592let hasSideEffects = 1;
37593}
37594def dep_A2_addsat : HInst<
37595(outs IntRegs:$Rd32),
37596(ins IntRegs:$Rs32, IntRegs:$Rt32),
37597"$Rd32 = add($Rs32,$Rt32):sat:deprecated",
37598tc_779080bf, TypeALU64>, Enc_5ab2be {
37599let Inst{7-5} = 0b000;
37600let Inst{13-13} = 0b0;
37601let Inst{31-21} = 0b11010101100;
37602let hasNewValue = 1;
37603let opNewValue = 0;
37604let prefersSlot3 = 1;
37605let Defs = [USR_OVF];
37606}
37607def dep_A2_subsat : HInst<
37608(outs IntRegs:$Rd32),
37609(ins IntRegs:$Rt32, IntRegs:$Rs32),
37610"$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
37611tc_779080bf, TypeALU64>, Enc_bd6011 {
37612let Inst{7-5} = 0b100;
37613let Inst{13-13} = 0b0;
37614let Inst{31-21} = 0b11010101100;
37615let hasNewValue = 1;
37616let opNewValue = 0;
37617let prefersSlot3 = 1;
37618let Defs = [USR_OVF];
37619}
37620def dep_S2_packhl : HInst<
37621(outs DoubleRegs:$Rdd32),
37622(ins IntRegs:$Rs32, IntRegs:$Rt32),
37623"$Rdd32 = packhl($Rs32,$Rt32):deprecated",
37624tc_946df596, TypeALU64>, Enc_be32a5 {
37625let Inst{7-5} = 0b000;
37626let Inst{13-13} = 0b0;
37627let Inst{31-21} = 0b11010100000;
37628}
37629