xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (revision 5d6d6278979b9eab598a23c804d23e930d2f7268) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11def A2_abs : HInst<
12(outs IntRegs:$Rd32),
13(ins IntRegs:$Rs32),
14"$Rd32 = abs($Rs32)",
15tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
16let Inst{13-5} = 0b000000100;
17let Inst{31-21} = 0b10001100100;
18let hasNewValue = 1;
19let opNewValue = 0;
20let prefersSlot3 = 1;
21}
22def A2_absp : HInst<
23(outs DoubleRegs:$Rdd32),
24(ins DoubleRegs:$Rss32),
25"$Rdd32 = abs($Rss32)",
26tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
27let Inst{13-5} = 0b000000110;
28let Inst{31-21} = 0b10000000100;
29let prefersSlot3 = 1;
30}
31def A2_abssat : HInst<
32(outs IntRegs:$Rd32),
33(ins IntRegs:$Rs32),
34"$Rd32 = abs($Rs32):sat",
35tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
36let Inst{13-5} = 0b000000101;
37let Inst{31-21} = 0b10001100100;
38let hasNewValue = 1;
39let opNewValue = 0;
40let prefersSlot3 = 1;
41let Defs = [USR_OVF];
42}
43def A2_add : HInst<
44(outs IntRegs:$Rd32),
45(ins IntRegs:$Rs32, IntRegs:$Rt32),
46"$Rd32 = add($Rs32,$Rt32)",
47tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
48let Inst{7-5} = 0b000;
49let Inst{13-13} = 0b0;
50let Inst{31-21} = 0b11110011000;
51let hasNewValue = 1;
52let opNewValue = 0;
53let BaseOpcode = "A2_add";
54let CextOpcode = "A2_add";
55let InputType = "reg";
56let isCommutable = 1;
57let isPredicable = 1;
58}
59def A2_addh_h16_hh : HInst<
60(outs IntRegs:$Rd32),
61(ins IntRegs:$Rt32, IntRegs:$Rs32),
62"$Rd32 = add($Rt32.h,$Rs32.h):<<16",
63tc_01d44cb2, TypeALU64>, Enc_bd6011 {
64let Inst{7-5} = 0b011;
65let Inst{13-13} = 0b0;
66let Inst{31-21} = 0b11010101010;
67let hasNewValue = 1;
68let opNewValue = 0;
69let prefersSlot3 = 1;
70}
71def A2_addh_h16_hl : HInst<
72(outs IntRegs:$Rd32),
73(ins IntRegs:$Rt32, IntRegs:$Rs32),
74"$Rd32 = add($Rt32.h,$Rs32.l):<<16",
75tc_01d44cb2, TypeALU64>, Enc_bd6011 {
76let Inst{7-5} = 0b010;
77let Inst{13-13} = 0b0;
78let Inst{31-21} = 0b11010101010;
79let hasNewValue = 1;
80let opNewValue = 0;
81let prefersSlot3 = 1;
82}
83def A2_addh_h16_lh : HInst<
84(outs IntRegs:$Rd32),
85(ins IntRegs:$Rt32, IntRegs:$Rs32),
86"$Rd32 = add($Rt32.l,$Rs32.h):<<16",
87tc_01d44cb2, TypeALU64>, Enc_bd6011 {
88let Inst{7-5} = 0b001;
89let Inst{13-13} = 0b0;
90let Inst{31-21} = 0b11010101010;
91let hasNewValue = 1;
92let opNewValue = 0;
93let prefersSlot3 = 1;
94}
95def A2_addh_h16_ll : HInst<
96(outs IntRegs:$Rd32),
97(ins IntRegs:$Rt32, IntRegs:$Rs32),
98"$Rd32 = add($Rt32.l,$Rs32.l):<<16",
99tc_01d44cb2, TypeALU64>, Enc_bd6011 {
100let Inst{7-5} = 0b000;
101let Inst{13-13} = 0b0;
102let Inst{31-21} = 0b11010101010;
103let hasNewValue = 1;
104let opNewValue = 0;
105let prefersSlot3 = 1;
106}
107def A2_addh_h16_sat_hh : HInst<
108(outs IntRegs:$Rd32),
109(ins IntRegs:$Rt32, IntRegs:$Rs32),
110"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
111tc_8a825db2, TypeALU64>, Enc_bd6011 {
112let Inst{7-5} = 0b111;
113let Inst{13-13} = 0b0;
114let Inst{31-21} = 0b11010101010;
115let hasNewValue = 1;
116let opNewValue = 0;
117let prefersSlot3 = 1;
118let Defs = [USR_OVF];
119}
120def A2_addh_h16_sat_hl : HInst<
121(outs IntRegs:$Rd32),
122(ins IntRegs:$Rt32, IntRegs:$Rs32),
123"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
124tc_8a825db2, TypeALU64>, Enc_bd6011 {
125let Inst{7-5} = 0b110;
126let Inst{13-13} = 0b0;
127let Inst{31-21} = 0b11010101010;
128let hasNewValue = 1;
129let opNewValue = 0;
130let prefersSlot3 = 1;
131let Defs = [USR_OVF];
132}
133def A2_addh_h16_sat_lh : HInst<
134(outs IntRegs:$Rd32),
135(ins IntRegs:$Rt32, IntRegs:$Rs32),
136"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
137tc_8a825db2, TypeALU64>, Enc_bd6011 {
138let Inst{7-5} = 0b101;
139let Inst{13-13} = 0b0;
140let Inst{31-21} = 0b11010101010;
141let hasNewValue = 1;
142let opNewValue = 0;
143let prefersSlot3 = 1;
144let Defs = [USR_OVF];
145}
146def A2_addh_h16_sat_ll : HInst<
147(outs IntRegs:$Rd32),
148(ins IntRegs:$Rt32, IntRegs:$Rs32),
149"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
150tc_8a825db2, TypeALU64>, Enc_bd6011 {
151let Inst{7-5} = 0b100;
152let Inst{13-13} = 0b0;
153let Inst{31-21} = 0b11010101010;
154let hasNewValue = 1;
155let opNewValue = 0;
156let prefersSlot3 = 1;
157let Defs = [USR_OVF];
158}
159def A2_addh_l16_hl : HInst<
160(outs IntRegs:$Rd32),
161(ins IntRegs:$Rt32, IntRegs:$Rs32),
162"$Rd32 = add($Rt32.l,$Rs32.h)",
163tc_f34c1c21, TypeALU64>, Enc_bd6011 {
164let Inst{7-5} = 0b010;
165let Inst{13-13} = 0b0;
166let Inst{31-21} = 0b11010101000;
167let hasNewValue = 1;
168let opNewValue = 0;
169let prefersSlot3 = 1;
170}
171def A2_addh_l16_ll : HInst<
172(outs IntRegs:$Rd32),
173(ins IntRegs:$Rt32, IntRegs:$Rs32),
174"$Rd32 = add($Rt32.l,$Rs32.l)",
175tc_f34c1c21, TypeALU64>, Enc_bd6011 {
176let Inst{7-5} = 0b000;
177let Inst{13-13} = 0b0;
178let Inst{31-21} = 0b11010101000;
179let hasNewValue = 1;
180let opNewValue = 0;
181let prefersSlot3 = 1;
182}
183def A2_addh_l16_sat_hl : HInst<
184(outs IntRegs:$Rd32),
185(ins IntRegs:$Rt32, IntRegs:$Rs32),
186"$Rd32 = add($Rt32.l,$Rs32.h):sat",
187tc_8a825db2, TypeALU64>, Enc_bd6011 {
188let Inst{7-5} = 0b110;
189let Inst{13-13} = 0b0;
190let Inst{31-21} = 0b11010101000;
191let hasNewValue = 1;
192let opNewValue = 0;
193let prefersSlot3 = 1;
194let Defs = [USR_OVF];
195}
196def A2_addh_l16_sat_ll : HInst<
197(outs IntRegs:$Rd32),
198(ins IntRegs:$Rt32, IntRegs:$Rs32),
199"$Rd32 = add($Rt32.l,$Rs32.l):sat",
200tc_8a825db2, TypeALU64>, Enc_bd6011 {
201let Inst{7-5} = 0b100;
202let Inst{13-13} = 0b0;
203let Inst{31-21} = 0b11010101000;
204let hasNewValue = 1;
205let opNewValue = 0;
206let prefersSlot3 = 1;
207let Defs = [USR_OVF];
208}
209def A2_addi : HInst<
210(outs IntRegs:$Rd32),
211(ins IntRegs:$Rs32, s32_0Imm:$Ii),
212"$Rd32 = add($Rs32,#$Ii)",
213tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
214let Inst{31-28} = 0b1011;
215let hasNewValue = 1;
216let opNewValue = 0;
217let BaseOpcode = "A2_addi";
218let CextOpcode = "A2_add";
219let InputType = "imm";
220let isAdd = 1;
221let isPredicable = 1;
222let isExtendable = 1;
223let opExtendable = 2;
224let isExtentSigned = 1;
225let opExtentBits = 16;
226let opExtentAlign = 0;
227}
228def A2_addp : HInst<
229(outs DoubleRegs:$Rdd32),
230(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
231"$Rdd32 = add($Rss32,$Rtt32)",
232tc_5da50c4b, TypeALU64>, Enc_a56825 {
233let Inst{7-5} = 0b111;
234let Inst{13-13} = 0b0;
235let Inst{31-21} = 0b11010011000;
236let isAdd = 1;
237let isCommutable = 1;
238}
239def A2_addpsat : HInst<
240(outs DoubleRegs:$Rdd32),
241(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
242"$Rdd32 = add($Rss32,$Rtt32):sat",
243tc_8a825db2, TypeALU64>, Enc_a56825 {
244let Inst{7-5} = 0b101;
245let Inst{13-13} = 0b0;
246let Inst{31-21} = 0b11010011011;
247let prefersSlot3 = 1;
248let Defs = [USR_OVF];
249let isCommutable = 1;
250}
251def A2_addsat : HInst<
252(outs IntRegs:$Rd32),
253(ins IntRegs:$Rs32, IntRegs:$Rt32),
254"$Rd32 = add($Rs32,$Rt32):sat",
255tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
256let Inst{7-5} = 0b000;
257let Inst{13-13} = 0b0;
258let Inst{31-21} = 0b11110110010;
259let hasNewValue = 1;
260let opNewValue = 0;
261let prefersSlot3 = 1;
262let Defs = [USR_OVF];
263let InputType = "reg";
264let isCommutable = 1;
265}
266def A2_addsp : HInst<
267(outs DoubleRegs:$Rdd32),
268(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
269"$Rdd32 = add($Rs32,$Rtt32)",
270tc_01d44cb2, TypeALU64> {
271let isPseudo = 1;
272}
273def A2_addsph : HInst<
274(outs DoubleRegs:$Rdd32),
275(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
276"$Rdd32 = add($Rss32,$Rtt32):raw:hi",
277tc_01d44cb2, TypeALU64>, Enc_a56825 {
278let Inst{7-5} = 0b111;
279let Inst{13-13} = 0b0;
280let Inst{31-21} = 0b11010011011;
281let prefersSlot3 = 1;
282}
283def A2_addspl : HInst<
284(outs DoubleRegs:$Rdd32),
285(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
286"$Rdd32 = add($Rss32,$Rtt32):raw:lo",
287tc_01d44cb2, TypeALU64>, Enc_a56825 {
288let Inst{7-5} = 0b110;
289let Inst{13-13} = 0b0;
290let Inst{31-21} = 0b11010011011;
291let prefersSlot3 = 1;
292}
293def A2_and : HInst<
294(outs IntRegs:$Rd32),
295(ins IntRegs:$Rs32, IntRegs:$Rt32),
296"$Rd32 = and($Rs32,$Rt32)",
297tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
298let Inst{7-5} = 0b000;
299let Inst{13-13} = 0b0;
300let Inst{31-21} = 0b11110001000;
301let hasNewValue = 1;
302let opNewValue = 0;
303let BaseOpcode = "A2_and";
304let CextOpcode = "A2_and";
305let InputType = "reg";
306let isCommutable = 1;
307let isPredicable = 1;
308}
309def A2_andir : HInst<
310(outs IntRegs:$Rd32),
311(ins IntRegs:$Rs32, s32_0Imm:$Ii),
312"$Rd32 = and($Rs32,#$Ii)",
313tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
314let Inst{31-22} = 0b0111011000;
315let hasNewValue = 1;
316let opNewValue = 0;
317let CextOpcode = "A2_and";
318let InputType = "imm";
319let isExtendable = 1;
320let opExtendable = 2;
321let isExtentSigned = 1;
322let opExtentBits = 10;
323let opExtentAlign = 0;
324}
325def A2_andp : HInst<
326(outs DoubleRegs:$Rdd32),
327(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
328"$Rdd32 = and($Rss32,$Rtt32)",
329tc_5da50c4b, TypeALU64>, Enc_a56825 {
330let Inst{7-5} = 0b000;
331let Inst{13-13} = 0b0;
332let Inst{31-21} = 0b11010011111;
333let isCommutable = 1;
334}
335def A2_aslh : HInst<
336(outs IntRegs:$Rd32),
337(ins IntRegs:$Rs32),
338"$Rd32 = aslh($Rs32)",
339tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
340let Inst{13-5} = 0b000000000;
341let Inst{31-21} = 0b01110000000;
342let hasNewValue = 1;
343let opNewValue = 0;
344let BaseOpcode = "A2_aslh";
345let isPredicable = 1;
346}
347def A2_asrh : HInst<
348(outs IntRegs:$Rd32),
349(ins IntRegs:$Rs32),
350"$Rd32 = asrh($Rs32)",
351tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
352let Inst{13-5} = 0b000000000;
353let Inst{31-21} = 0b01110000001;
354let hasNewValue = 1;
355let opNewValue = 0;
356let BaseOpcode = "A2_asrh";
357let isPredicable = 1;
358}
359def A2_combine_hh : HInst<
360(outs IntRegs:$Rd32),
361(ins IntRegs:$Rt32, IntRegs:$Rs32),
362"$Rd32 = combine($Rt32.h,$Rs32.h)",
363tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
364let Inst{7-5} = 0b000;
365let Inst{13-13} = 0b0;
366let Inst{31-21} = 0b11110011100;
367let hasNewValue = 1;
368let opNewValue = 0;
369let InputType = "reg";
370}
371def A2_combine_hl : HInst<
372(outs IntRegs:$Rd32),
373(ins IntRegs:$Rt32, IntRegs:$Rs32),
374"$Rd32 = combine($Rt32.h,$Rs32.l)",
375tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
376let Inst{7-5} = 0b000;
377let Inst{13-13} = 0b0;
378let Inst{31-21} = 0b11110011101;
379let hasNewValue = 1;
380let opNewValue = 0;
381let InputType = "reg";
382}
383def A2_combine_lh : HInst<
384(outs IntRegs:$Rd32),
385(ins IntRegs:$Rt32, IntRegs:$Rs32),
386"$Rd32 = combine($Rt32.l,$Rs32.h)",
387tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
388let Inst{7-5} = 0b000;
389let Inst{13-13} = 0b0;
390let Inst{31-21} = 0b11110011110;
391let hasNewValue = 1;
392let opNewValue = 0;
393let InputType = "reg";
394}
395def A2_combine_ll : HInst<
396(outs IntRegs:$Rd32),
397(ins IntRegs:$Rt32, IntRegs:$Rs32),
398"$Rd32 = combine($Rt32.l,$Rs32.l)",
399tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
400let Inst{7-5} = 0b000;
401let Inst{13-13} = 0b0;
402let Inst{31-21} = 0b11110011111;
403let hasNewValue = 1;
404let opNewValue = 0;
405let InputType = "reg";
406}
407def A2_combineii : HInst<
408(outs DoubleRegs:$Rdd32),
409(ins s32_0Imm:$Ii, s8_0Imm:$II),
410"$Rdd32 = combine(#$Ii,#$II)",
411tc_713b66bf, TypeALU32_2op>, Enc_18c338 {
412let Inst{31-23} = 0b011111000;
413let isAsCheapAsAMove = 1;
414let isMoveImm = 1;
415let isReMaterializable = 1;
416let isExtendable = 1;
417let opExtendable = 1;
418let isExtentSigned = 1;
419let opExtentBits = 8;
420let opExtentAlign = 0;
421}
422def A2_combinew : HInst<
423(outs DoubleRegs:$Rdd32),
424(ins IntRegs:$Rs32, IntRegs:$Rt32),
425"$Rdd32 = combine($Rs32,$Rt32)",
426tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel {
427let Inst{7-5} = 0b000;
428let Inst{13-13} = 0b0;
429let Inst{31-21} = 0b11110101000;
430let BaseOpcode = "A2_combinew";
431let InputType = "reg";
432let isPredicable = 1;
433}
434def A2_max : HInst<
435(outs IntRegs:$Rd32),
436(ins IntRegs:$Rs32, IntRegs:$Rt32),
437"$Rd32 = max($Rs32,$Rt32)",
438tc_8a825db2, TypeALU64>, Enc_5ab2be {
439let Inst{7-5} = 0b000;
440let Inst{13-13} = 0b0;
441let Inst{31-21} = 0b11010101110;
442let hasNewValue = 1;
443let opNewValue = 0;
444let prefersSlot3 = 1;
445}
446def A2_maxp : HInst<
447(outs DoubleRegs:$Rdd32),
448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
449"$Rdd32 = max($Rss32,$Rtt32)",
450tc_8a825db2, TypeALU64>, Enc_a56825 {
451let Inst{7-5} = 0b100;
452let Inst{13-13} = 0b0;
453let Inst{31-21} = 0b11010011110;
454let prefersSlot3 = 1;
455}
456def A2_maxu : HInst<
457(outs IntRegs:$Rd32),
458(ins IntRegs:$Rs32, IntRegs:$Rt32),
459"$Rd32 = maxu($Rs32,$Rt32)",
460tc_8a825db2, TypeALU64>, Enc_5ab2be {
461let Inst{7-5} = 0b100;
462let Inst{13-13} = 0b0;
463let Inst{31-21} = 0b11010101110;
464let hasNewValue = 1;
465let opNewValue = 0;
466let prefersSlot3 = 1;
467}
468def A2_maxup : HInst<
469(outs DoubleRegs:$Rdd32),
470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
471"$Rdd32 = maxu($Rss32,$Rtt32)",
472tc_8a825db2, TypeALU64>, Enc_a56825 {
473let Inst{7-5} = 0b101;
474let Inst{13-13} = 0b0;
475let Inst{31-21} = 0b11010011110;
476let prefersSlot3 = 1;
477}
478def A2_min : HInst<
479(outs IntRegs:$Rd32),
480(ins IntRegs:$Rt32, IntRegs:$Rs32),
481"$Rd32 = min($Rt32,$Rs32)",
482tc_8a825db2, TypeALU64>, Enc_bd6011 {
483let Inst{7-5} = 0b000;
484let Inst{13-13} = 0b0;
485let Inst{31-21} = 0b11010101101;
486let hasNewValue = 1;
487let opNewValue = 0;
488let prefersSlot3 = 1;
489}
490def A2_minp : HInst<
491(outs DoubleRegs:$Rdd32),
492(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
493"$Rdd32 = min($Rtt32,$Rss32)",
494tc_8a825db2, TypeALU64>, Enc_ea23e4 {
495let Inst{7-5} = 0b110;
496let Inst{13-13} = 0b0;
497let Inst{31-21} = 0b11010011101;
498let prefersSlot3 = 1;
499}
500def A2_minu : HInst<
501(outs IntRegs:$Rd32),
502(ins IntRegs:$Rt32, IntRegs:$Rs32),
503"$Rd32 = minu($Rt32,$Rs32)",
504tc_8a825db2, TypeALU64>, Enc_bd6011 {
505let Inst{7-5} = 0b100;
506let Inst{13-13} = 0b0;
507let Inst{31-21} = 0b11010101101;
508let hasNewValue = 1;
509let opNewValue = 0;
510let prefersSlot3 = 1;
511}
512def A2_minup : HInst<
513(outs DoubleRegs:$Rdd32),
514(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
515"$Rdd32 = minu($Rtt32,$Rss32)",
516tc_8a825db2, TypeALU64>, Enc_ea23e4 {
517let Inst{7-5} = 0b111;
518let Inst{13-13} = 0b0;
519let Inst{31-21} = 0b11010011101;
520let prefersSlot3 = 1;
521}
522def A2_neg : HInst<
523(outs IntRegs:$Rd32),
524(ins IntRegs:$Rs32),
525"$Rd32 = neg($Rs32)",
526tc_c57d9f39, TypeALU32_2op> {
527let hasNewValue = 1;
528let opNewValue = 0;
529let isPseudo = 1;
530let isCodeGenOnly = 1;
531}
532def A2_negp : HInst<
533(outs DoubleRegs:$Rdd32),
534(ins DoubleRegs:$Rss32),
535"$Rdd32 = neg($Rss32)",
536tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
537let Inst{13-5} = 0b000000101;
538let Inst{31-21} = 0b10000000100;
539}
540def A2_negsat : HInst<
541(outs IntRegs:$Rd32),
542(ins IntRegs:$Rs32),
543"$Rd32 = neg($Rs32):sat",
544tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
545let Inst{13-5} = 0b000000110;
546let Inst{31-21} = 0b10001100100;
547let hasNewValue = 1;
548let opNewValue = 0;
549let prefersSlot3 = 1;
550let Defs = [USR_OVF];
551}
552def A2_nop : HInst<
553(outs),
554(ins),
555"nop",
556tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 {
557let Inst{13-0} = 0b00000000000000;
558let Inst{31-16} = 0b0111111100000000;
559}
560def A2_not : HInst<
561(outs IntRegs:$Rd32),
562(ins IntRegs:$Rs32),
563"$Rd32 = not($Rs32)",
564tc_c57d9f39, TypeALU32_2op> {
565let hasNewValue = 1;
566let opNewValue = 0;
567let isPseudo = 1;
568let isCodeGenOnly = 1;
569}
570def A2_notp : HInst<
571(outs DoubleRegs:$Rdd32),
572(ins DoubleRegs:$Rss32),
573"$Rdd32 = not($Rss32)",
574tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
575let Inst{13-5} = 0b000000100;
576let Inst{31-21} = 0b10000000100;
577}
578def A2_or : HInst<
579(outs IntRegs:$Rd32),
580(ins IntRegs:$Rs32, IntRegs:$Rt32),
581"$Rd32 = or($Rs32,$Rt32)",
582tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
583let Inst{7-5} = 0b000;
584let Inst{13-13} = 0b0;
585let Inst{31-21} = 0b11110001001;
586let hasNewValue = 1;
587let opNewValue = 0;
588let BaseOpcode = "A2_or";
589let CextOpcode = "A2_or";
590let InputType = "reg";
591let isCommutable = 1;
592let isPredicable = 1;
593}
594def A2_orir : HInst<
595(outs IntRegs:$Rd32),
596(ins IntRegs:$Rs32, s32_0Imm:$Ii),
597"$Rd32 = or($Rs32,#$Ii)",
598tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
599let Inst{31-22} = 0b0111011010;
600let hasNewValue = 1;
601let opNewValue = 0;
602let CextOpcode = "A2_or";
603let InputType = "imm";
604let isExtendable = 1;
605let opExtendable = 2;
606let isExtentSigned = 1;
607let opExtentBits = 10;
608let opExtentAlign = 0;
609}
610def A2_orp : HInst<
611(outs DoubleRegs:$Rdd32),
612(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
613"$Rdd32 = or($Rss32,$Rtt32)",
614tc_5da50c4b, TypeALU64>, Enc_a56825 {
615let Inst{7-5} = 0b010;
616let Inst{13-13} = 0b0;
617let Inst{31-21} = 0b11010011111;
618let isCommutable = 1;
619}
620def A2_paddf : HInst<
621(outs IntRegs:$Rd32),
622(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
623"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
624tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
625let Inst{7-7} = 0b1;
626let Inst{13-13} = 0b0;
627let Inst{31-21} = 0b11111011000;
628let isPredicated = 1;
629let isPredicatedFalse = 1;
630let hasNewValue = 1;
631let opNewValue = 0;
632let BaseOpcode = "A2_add";
633let CextOpcode = "A2_add";
634let InputType = "reg";
635}
636def A2_paddfnew : HInst<
637(outs IntRegs:$Rd32),
638(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
639"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
640tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
641let Inst{7-7} = 0b1;
642let Inst{13-13} = 0b1;
643let Inst{31-21} = 0b11111011000;
644let isPredicated = 1;
645let isPredicatedFalse = 1;
646let hasNewValue = 1;
647let opNewValue = 0;
648let isPredicatedNew = 1;
649let BaseOpcode = "A2_add";
650let CextOpcode = "A2_add";
651let InputType = "reg";
652}
653def A2_paddif : HInst<
654(outs IntRegs:$Rd32),
655(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
656"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
657tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
658let Inst{13-13} = 0b0;
659let Inst{31-23} = 0b011101001;
660let isPredicated = 1;
661let isPredicatedFalse = 1;
662let hasNewValue = 1;
663let opNewValue = 0;
664let BaseOpcode = "A2_addi";
665let CextOpcode = "A2_add";
666let InputType = "imm";
667let isExtendable = 1;
668let opExtendable = 3;
669let isExtentSigned = 1;
670let opExtentBits = 8;
671let opExtentAlign = 0;
672}
673def A2_paddifnew : HInst<
674(outs IntRegs:$Rd32),
675(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
676"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
677tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
678let Inst{13-13} = 0b1;
679let Inst{31-23} = 0b011101001;
680let isPredicated = 1;
681let isPredicatedFalse = 1;
682let hasNewValue = 1;
683let opNewValue = 0;
684let isPredicatedNew = 1;
685let BaseOpcode = "A2_addi";
686let CextOpcode = "A2_add";
687let InputType = "imm";
688let isExtendable = 1;
689let opExtendable = 3;
690let isExtentSigned = 1;
691let opExtentBits = 8;
692let opExtentAlign = 0;
693}
694def A2_paddit : HInst<
695(outs IntRegs:$Rd32),
696(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
697"if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
698tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
699let Inst{13-13} = 0b0;
700let Inst{31-23} = 0b011101000;
701let isPredicated = 1;
702let hasNewValue = 1;
703let opNewValue = 0;
704let BaseOpcode = "A2_addi";
705let CextOpcode = "A2_add";
706let InputType = "imm";
707let isExtendable = 1;
708let opExtendable = 3;
709let isExtentSigned = 1;
710let opExtentBits = 8;
711let opExtentAlign = 0;
712}
713def A2_padditnew : HInst<
714(outs IntRegs:$Rd32),
715(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
716"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
717tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
718let Inst{13-13} = 0b1;
719let Inst{31-23} = 0b011101000;
720let isPredicated = 1;
721let hasNewValue = 1;
722let opNewValue = 0;
723let isPredicatedNew = 1;
724let BaseOpcode = "A2_addi";
725let CextOpcode = "A2_add";
726let InputType = "imm";
727let isExtendable = 1;
728let opExtendable = 3;
729let isExtentSigned = 1;
730let opExtentBits = 8;
731let opExtentAlign = 0;
732}
733def A2_paddt : HInst<
734(outs IntRegs:$Rd32),
735(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
736"if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
737tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
738let Inst{7-7} = 0b0;
739let Inst{13-13} = 0b0;
740let Inst{31-21} = 0b11111011000;
741let isPredicated = 1;
742let hasNewValue = 1;
743let opNewValue = 0;
744let BaseOpcode = "A2_add";
745let CextOpcode = "A2_add";
746let InputType = "reg";
747}
748def A2_paddtnew : HInst<
749(outs IntRegs:$Rd32),
750(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
751"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
752tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
753let Inst{7-7} = 0b0;
754let Inst{13-13} = 0b1;
755let Inst{31-21} = 0b11111011000;
756let isPredicated = 1;
757let hasNewValue = 1;
758let opNewValue = 0;
759let isPredicatedNew = 1;
760let BaseOpcode = "A2_add";
761let CextOpcode = "A2_add";
762let InputType = "reg";
763}
764def A2_pandf : HInst<
765(outs IntRegs:$Rd32),
766(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
767"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
768tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
769let Inst{7-7} = 0b1;
770let Inst{13-13} = 0b0;
771let Inst{31-21} = 0b11111001000;
772let isPredicated = 1;
773let isPredicatedFalse = 1;
774let hasNewValue = 1;
775let opNewValue = 0;
776let BaseOpcode = "A2_and";
777}
778def A2_pandfnew : HInst<
779(outs IntRegs:$Rd32),
780(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
781"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
782tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
783let Inst{7-7} = 0b1;
784let Inst{13-13} = 0b1;
785let Inst{31-21} = 0b11111001000;
786let isPredicated = 1;
787let isPredicatedFalse = 1;
788let hasNewValue = 1;
789let opNewValue = 0;
790let isPredicatedNew = 1;
791let BaseOpcode = "A2_and";
792}
793def A2_pandt : HInst<
794(outs IntRegs:$Rd32),
795(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
796"if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
797tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
798let Inst{7-7} = 0b0;
799let Inst{13-13} = 0b0;
800let Inst{31-21} = 0b11111001000;
801let isPredicated = 1;
802let hasNewValue = 1;
803let opNewValue = 0;
804let BaseOpcode = "A2_and";
805}
806def A2_pandtnew : HInst<
807(outs IntRegs:$Rd32),
808(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
809"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
810tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
811let Inst{7-7} = 0b0;
812let Inst{13-13} = 0b1;
813let Inst{31-21} = 0b11111001000;
814let isPredicated = 1;
815let hasNewValue = 1;
816let opNewValue = 0;
817let isPredicatedNew = 1;
818let BaseOpcode = "A2_and";
819}
820def A2_porf : HInst<
821(outs IntRegs:$Rd32),
822(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
823"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
824tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
825let Inst{7-7} = 0b1;
826let Inst{13-13} = 0b0;
827let Inst{31-21} = 0b11111001001;
828let isPredicated = 1;
829let isPredicatedFalse = 1;
830let hasNewValue = 1;
831let opNewValue = 0;
832let BaseOpcode = "A2_or";
833}
834def A2_porfnew : HInst<
835(outs IntRegs:$Rd32),
836(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
837"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
838tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
839let Inst{7-7} = 0b1;
840let Inst{13-13} = 0b1;
841let Inst{31-21} = 0b11111001001;
842let isPredicated = 1;
843let isPredicatedFalse = 1;
844let hasNewValue = 1;
845let opNewValue = 0;
846let isPredicatedNew = 1;
847let BaseOpcode = "A2_or";
848}
849def A2_port : HInst<
850(outs IntRegs:$Rd32),
851(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
852"if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
853tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
854let Inst{7-7} = 0b0;
855let Inst{13-13} = 0b0;
856let Inst{31-21} = 0b11111001001;
857let isPredicated = 1;
858let hasNewValue = 1;
859let opNewValue = 0;
860let BaseOpcode = "A2_or";
861}
862def A2_portnew : HInst<
863(outs IntRegs:$Rd32),
864(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
865"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
866tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
867let Inst{7-7} = 0b0;
868let Inst{13-13} = 0b1;
869let Inst{31-21} = 0b11111001001;
870let isPredicated = 1;
871let hasNewValue = 1;
872let opNewValue = 0;
873let isPredicatedNew = 1;
874let BaseOpcode = "A2_or";
875}
876def A2_psubf : HInst<
877(outs IntRegs:$Rd32),
878(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
879"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
880tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
881let Inst{7-7} = 0b1;
882let Inst{13-13} = 0b0;
883let Inst{31-21} = 0b11111011001;
884let isPredicated = 1;
885let isPredicatedFalse = 1;
886let hasNewValue = 1;
887let opNewValue = 0;
888let BaseOpcode = "A2_sub";
889}
890def A2_psubfnew : HInst<
891(outs IntRegs:$Rd32),
892(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
893"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
894tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
895let Inst{7-7} = 0b1;
896let Inst{13-13} = 0b1;
897let Inst{31-21} = 0b11111011001;
898let isPredicated = 1;
899let isPredicatedFalse = 1;
900let hasNewValue = 1;
901let opNewValue = 0;
902let isPredicatedNew = 1;
903let BaseOpcode = "A2_sub";
904}
905def A2_psubt : HInst<
906(outs IntRegs:$Rd32),
907(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
908"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
909tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
910let Inst{7-7} = 0b0;
911let Inst{13-13} = 0b0;
912let Inst{31-21} = 0b11111011001;
913let isPredicated = 1;
914let hasNewValue = 1;
915let opNewValue = 0;
916let BaseOpcode = "A2_sub";
917}
918def A2_psubtnew : HInst<
919(outs IntRegs:$Rd32),
920(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
921"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
922tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
923let Inst{7-7} = 0b0;
924let Inst{13-13} = 0b1;
925let Inst{31-21} = 0b11111011001;
926let isPredicated = 1;
927let hasNewValue = 1;
928let opNewValue = 0;
929let isPredicatedNew = 1;
930let BaseOpcode = "A2_sub";
931}
932def A2_pxorf : HInst<
933(outs IntRegs:$Rd32),
934(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
935"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
936tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
937let Inst{7-7} = 0b1;
938let Inst{13-13} = 0b0;
939let Inst{31-21} = 0b11111001011;
940let isPredicated = 1;
941let isPredicatedFalse = 1;
942let hasNewValue = 1;
943let opNewValue = 0;
944let BaseOpcode = "A2_xor";
945}
946def A2_pxorfnew : HInst<
947(outs IntRegs:$Rd32),
948(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
949"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
950tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
951let Inst{7-7} = 0b1;
952let Inst{13-13} = 0b1;
953let Inst{31-21} = 0b11111001011;
954let isPredicated = 1;
955let isPredicatedFalse = 1;
956let hasNewValue = 1;
957let opNewValue = 0;
958let isPredicatedNew = 1;
959let BaseOpcode = "A2_xor";
960}
961def A2_pxort : HInst<
962(outs IntRegs:$Rd32),
963(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
964"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
965tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
966let Inst{7-7} = 0b0;
967let Inst{13-13} = 0b0;
968let Inst{31-21} = 0b11111001011;
969let isPredicated = 1;
970let hasNewValue = 1;
971let opNewValue = 0;
972let BaseOpcode = "A2_xor";
973}
974def A2_pxortnew : HInst<
975(outs IntRegs:$Rd32),
976(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
977"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
978tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
979let Inst{7-7} = 0b0;
980let Inst{13-13} = 0b1;
981let Inst{31-21} = 0b11111001011;
982let isPredicated = 1;
983let hasNewValue = 1;
984let opNewValue = 0;
985let isPredicatedNew = 1;
986let BaseOpcode = "A2_xor";
987}
988def A2_roundsat : HInst<
989(outs IntRegs:$Rd32),
990(ins DoubleRegs:$Rss32),
991"$Rd32 = round($Rss32):sat",
992tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
993let Inst{13-5} = 0b000000001;
994let Inst{31-21} = 0b10001000110;
995let hasNewValue = 1;
996let opNewValue = 0;
997let prefersSlot3 = 1;
998let Defs = [USR_OVF];
999}
1000def A2_sat : HInst<
1001(outs IntRegs:$Rd32),
1002(ins DoubleRegs:$Rss32),
1003"$Rd32 = sat($Rss32)",
1004tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
1005let Inst{13-5} = 0b000000000;
1006let Inst{31-21} = 0b10001000110;
1007let hasNewValue = 1;
1008let opNewValue = 0;
1009let Defs = [USR_OVF];
1010}
1011def A2_satb : HInst<
1012(outs IntRegs:$Rd32),
1013(ins IntRegs:$Rs32),
1014"$Rd32 = satb($Rs32)",
1015tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1016let Inst{13-5} = 0b000000111;
1017let Inst{31-21} = 0b10001100110;
1018let hasNewValue = 1;
1019let opNewValue = 0;
1020let Defs = [USR_OVF];
1021}
1022def A2_sath : HInst<
1023(outs IntRegs:$Rd32),
1024(ins IntRegs:$Rs32),
1025"$Rd32 = sath($Rs32)",
1026tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1027let Inst{13-5} = 0b000000100;
1028let Inst{31-21} = 0b10001100110;
1029let hasNewValue = 1;
1030let opNewValue = 0;
1031let Defs = [USR_OVF];
1032}
1033def A2_satub : HInst<
1034(outs IntRegs:$Rd32),
1035(ins IntRegs:$Rs32),
1036"$Rd32 = satub($Rs32)",
1037tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1038let Inst{13-5} = 0b000000110;
1039let Inst{31-21} = 0b10001100110;
1040let hasNewValue = 1;
1041let opNewValue = 0;
1042let Defs = [USR_OVF];
1043}
1044def A2_satuh : HInst<
1045(outs IntRegs:$Rd32),
1046(ins IntRegs:$Rs32),
1047"$Rd32 = satuh($Rs32)",
1048tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1049let Inst{13-5} = 0b000000101;
1050let Inst{31-21} = 0b10001100110;
1051let hasNewValue = 1;
1052let opNewValue = 0;
1053let Defs = [USR_OVF];
1054}
1055def A2_sub : HInst<
1056(outs IntRegs:$Rd32),
1057(ins IntRegs:$Rt32, IntRegs:$Rs32),
1058"$Rd32 = sub($Rt32,$Rs32)",
1059tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
1060let Inst{7-5} = 0b000;
1061let Inst{13-13} = 0b0;
1062let Inst{31-21} = 0b11110011001;
1063let hasNewValue = 1;
1064let opNewValue = 0;
1065let BaseOpcode = "A2_sub";
1066let CextOpcode = "A2_sub";
1067let InputType = "reg";
1068let isPredicable = 1;
1069}
1070def A2_subh_h16_hh : HInst<
1071(outs IntRegs:$Rd32),
1072(ins IntRegs:$Rt32, IntRegs:$Rs32),
1073"$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
1074tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1075let Inst{7-5} = 0b011;
1076let Inst{13-13} = 0b0;
1077let Inst{31-21} = 0b11010101011;
1078let hasNewValue = 1;
1079let opNewValue = 0;
1080let prefersSlot3 = 1;
1081}
1082def A2_subh_h16_hl : HInst<
1083(outs IntRegs:$Rd32),
1084(ins IntRegs:$Rt32, IntRegs:$Rs32),
1085"$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
1086tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1087let Inst{7-5} = 0b010;
1088let Inst{13-13} = 0b0;
1089let Inst{31-21} = 0b11010101011;
1090let hasNewValue = 1;
1091let opNewValue = 0;
1092let prefersSlot3 = 1;
1093}
1094def A2_subh_h16_lh : HInst<
1095(outs IntRegs:$Rd32),
1096(ins IntRegs:$Rt32, IntRegs:$Rs32),
1097"$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
1098tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1099let Inst{7-5} = 0b001;
1100let Inst{13-13} = 0b0;
1101let Inst{31-21} = 0b11010101011;
1102let hasNewValue = 1;
1103let opNewValue = 0;
1104let prefersSlot3 = 1;
1105}
1106def A2_subh_h16_ll : HInst<
1107(outs IntRegs:$Rd32),
1108(ins IntRegs:$Rt32, IntRegs:$Rs32),
1109"$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
1110tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1111let Inst{7-5} = 0b000;
1112let Inst{13-13} = 0b0;
1113let Inst{31-21} = 0b11010101011;
1114let hasNewValue = 1;
1115let opNewValue = 0;
1116let prefersSlot3 = 1;
1117}
1118def A2_subh_h16_sat_hh : HInst<
1119(outs IntRegs:$Rd32),
1120(ins IntRegs:$Rt32, IntRegs:$Rs32),
1121"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
1122tc_8a825db2, TypeALU64>, Enc_bd6011 {
1123let Inst{7-5} = 0b111;
1124let Inst{13-13} = 0b0;
1125let Inst{31-21} = 0b11010101011;
1126let hasNewValue = 1;
1127let opNewValue = 0;
1128let prefersSlot3 = 1;
1129let Defs = [USR_OVF];
1130}
1131def A2_subh_h16_sat_hl : HInst<
1132(outs IntRegs:$Rd32),
1133(ins IntRegs:$Rt32, IntRegs:$Rs32),
1134"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
1135tc_8a825db2, TypeALU64>, Enc_bd6011 {
1136let Inst{7-5} = 0b110;
1137let Inst{13-13} = 0b0;
1138let Inst{31-21} = 0b11010101011;
1139let hasNewValue = 1;
1140let opNewValue = 0;
1141let prefersSlot3 = 1;
1142let Defs = [USR_OVF];
1143}
1144def A2_subh_h16_sat_lh : HInst<
1145(outs IntRegs:$Rd32),
1146(ins IntRegs:$Rt32, IntRegs:$Rs32),
1147"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
1148tc_8a825db2, TypeALU64>, Enc_bd6011 {
1149let Inst{7-5} = 0b101;
1150let Inst{13-13} = 0b0;
1151let Inst{31-21} = 0b11010101011;
1152let hasNewValue = 1;
1153let opNewValue = 0;
1154let prefersSlot3 = 1;
1155let Defs = [USR_OVF];
1156}
1157def A2_subh_h16_sat_ll : HInst<
1158(outs IntRegs:$Rd32),
1159(ins IntRegs:$Rt32, IntRegs:$Rs32),
1160"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
1161tc_8a825db2, TypeALU64>, Enc_bd6011 {
1162let Inst{7-5} = 0b100;
1163let Inst{13-13} = 0b0;
1164let Inst{31-21} = 0b11010101011;
1165let hasNewValue = 1;
1166let opNewValue = 0;
1167let prefersSlot3 = 1;
1168let Defs = [USR_OVF];
1169}
1170def A2_subh_l16_hl : HInst<
1171(outs IntRegs:$Rd32),
1172(ins IntRegs:$Rt32, IntRegs:$Rs32),
1173"$Rd32 = sub($Rt32.l,$Rs32.h)",
1174tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1175let Inst{7-5} = 0b010;
1176let Inst{13-13} = 0b0;
1177let Inst{31-21} = 0b11010101001;
1178let hasNewValue = 1;
1179let opNewValue = 0;
1180let prefersSlot3 = 1;
1181}
1182def A2_subh_l16_ll : HInst<
1183(outs IntRegs:$Rd32),
1184(ins IntRegs:$Rt32, IntRegs:$Rs32),
1185"$Rd32 = sub($Rt32.l,$Rs32.l)",
1186tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1187let Inst{7-5} = 0b000;
1188let Inst{13-13} = 0b0;
1189let Inst{31-21} = 0b11010101001;
1190let hasNewValue = 1;
1191let opNewValue = 0;
1192let prefersSlot3 = 1;
1193}
1194def A2_subh_l16_sat_hl : HInst<
1195(outs IntRegs:$Rd32),
1196(ins IntRegs:$Rt32, IntRegs:$Rs32),
1197"$Rd32 = sub($Rt32.l,$Rs32.h):sat",
1198tc_8a825db2, TypeALU64>, Enc_bd6011 {
1199let Inst{7-5} = 0b110;
1200let Inst{13-13} = 0b0;
1201let Inst{31-21} = 0b11010101001;
1202let hasNewValue = 1;
1203let opNewValue = 0;
1204let prefersSlot3 = 1;
1205let Defs = [USR_OVF];
1206}
1207def A2_subh_l16_sat_ll : HInst<
1208(outs IntRegs:$Rd32),
1209(ins IntRegs:$Rt32, IntRegs:$Rs32),
1210"$Rd32 = sub($Rt32.l,$Rs32.l):sat",
1211tc_8a825db2, TypeALU64>, Enc_bd6011 {
1212let Inst{7-5} = 0b100;
1213let Inst{13-13} = 0b0;
1214let Inst{31-21} = 0b11010101001;
1215let hasNewValue = 1;
1216let opNewValue = 0;
1217let prefersSlot3 = 1;
1218let Defs = [USR_OVF];
1219}
1220def A2_subp : HInst<
1221(outs DoubleRegs:$Rdd32),
1222(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1223"$Rdd32 = sub($Rtt32,$Rss32)",
1224tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
1225let Inst{7-5} = 0b111;
1226let Inst{13-13} = 0b0;
1227let Inst{31-21} = 0b11010011001;
1228}
1229def A2_subri : HInst<
1230(outs IntRegs:$Rd32),
1231(ins s32_0Imm:$Ii, IntRegs:$Rs32),
1232"$Rd32 = sub(#$Ii,$Rs32)",
1233tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
1234let Inst{31-22} = 0b0111011001;
1235let hasNewValue = 1;
1236let opNewValue = 0;
1237let CextOpcode = "A2_sub";
1238let InputType = "imm";
1239let isExtendable = 1;
1240let opExtendable = 1;
1241let isExtentSigned = 1;
1242let opExtentBits = 10;
1243let opExtentAlign = 0;
1244}
1245def A2_subsat : HInst<
1246(outs IntRegs:$Rd32),
1247(ins IntRegs:$Rt32, IntRegs:$Rs32),
1248"$Rd32 = sub($Rt32,$Rs32):sat",
1249tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1250let Inst{7-5} = 0b000;
1251let Inst{13-13} = 0b0;
1252let Inst{31-21} = 0b11110110110;
1253let hasNewValue = 1;
1254let opNewValue = 0;
1255let prefersSlot3 = 1;
1256let Defs = [USR_OVF];
1257let InputType = "reg";
1258}
1259def A2_svaddh : HInst<
1260(outs IntRegs:$Rd32),
1261(ins IntRegs:$Rs32, IntRegs:$Rt32),
1262"$Rd32 = vaddh($Rs32,$Rt32)",
1263tc_713b66bf, TypeALU32_3op>, Enc_5ab2be {
1264let Inst{7-5} = 0b000;
1265let Inst{13-13} = 0b0;
1266let Inst{31-21} = 0b11110110000;
1267let hasNewValue = 1;
1268let opNewValue = 0;
1269let InputType = "reg";
1270let isCommutable = 1;
1271}
1272def A2_svaddhs : HInst<
1273(outs IntRegs:$Rd32),
1274(ins IntRegs:$Rs32, IntRegs:$Rt32),
1275"$Rd32 = vaddh($Rs32,$Rt32):sat",
1276tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1277let Inst{7-5} = 0b000;
1278let Inst{13-13} = 0b0;
1279let Inst{31-21} = 0b11110110001;
1280let hasNewValue = 1;
1281let opNewValue = 0;
1282let prefersSlot3 = 1;
1283let Defs = [USR_OVF];
1284let InputType = "reg";
1285let isCommutable = 1;
1286}
1287def A2_svadduhs : HInst<
1288(outs IntRegs:$Rd32),
1289(ins IntRegs:$Rs32, IntRegs:$Rt32),
1290"$Rd32 = vadduh($Rs32,$Rt32):sat",
1291tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1292let Inst{7-5} = 0b000;
1293let Inst{13-13} = 0b0;
1294let Inst{31-21} = 0b11110110011;
1295let hasNewValue = 1;
1296let opNewValue = 0;
1297let prefersSlot3 = 1;
1298let Defs = [USR_OVF];
1299let InputType = "reg";
1300let isCommutable = 1;
1301}
1302def A2_svavgh : HInst<
1303(outs IntRegs:$Rd32),
1304(ins IntRegs:$Rs32, IntRegs:$Rt32),
1305"$Rd32 = vavgh($Rs32,$Rt32)",
1306tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be {
1307let Inst{7-5} = 0b000;
1308let Inst{13-13} = 0b0;
1309let Inst{31-21} = 0b11110111000;
1310let hasNewValue = 1;
1311let opNewValue = 0;
1312let prefersSlot3 = 1;
1313let InputType = "reg";
1314let isCommutable = 1;
1315}
1316def A2_svavghs : HInst<
1317(outs IntRegs:$Rd32),
1318(ins IntRegs:$Rs32, IntRegs:$Rt32),
1319"$Rd32 = vavgh($Rs32,$Rt32):rnd",
1320tc_84a7500d, TypeALU32_3op>, Enc_5ab2be {
1321let Inst{7-5} = 0b000;
1322let Inst{13-13} = 0b0;
1323let Inst{31-21} = 0b11110111001;
1324let hasNewValue = 1;
1325let opNewValue = 0;
1326let prefersSlot3 = 1;
1327let InputType = "reg";
1328let isCommutable = 1;
1329}
1330def A2_svnavgh : HInst<
1331(outs IntRegs:$Rd32),
1332(ins IntRegs:$Rt32, IntRegs:$Rs32),
1333"$Rd32 = vnavgh($Rt32,$Rs32)",
1334tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 {
1335let Inst{7-5} = 0b000;
1336let Inst{13-13} = 0b0;
1337let Inst{31-21} = 0b11110111011;
1338let hasNewValue = 1;
1339let opNewValue = 0;
1340let prefersSlot3 = 1;
1341let InputType = "reg";
1342}
1343def A2_svsubh : HInst<
1344(outs IntRegs:$Rd32),
1345(ins IntRegs:$Rt32, IntRegs:$Rs32),
1346"$Rd32 = vsubh($Rt32,$Rs32)",
1347tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
1348let Inst{7-5} = 0b000;
1349let Inst{13-13} = 0b0;
1350let Inst{31-21} = 0b11110110100;
1351let hasNewValue = 1;
1352let opNewValue = 0;
1353let InputType = "reg";
1354}
1355def A2_svsubhs : HInst<
1356(outs IntRegs:$Rd32),
1357(ins IntRegs:$Rt32, IntRegs:$Rs32),
1358"$Rd32 = vsubh($Rt32,$Rs32):sat",
1359tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1360let Inst{7-5} = 0b000;
1361let Inst{13-13} = 0b0;
1362let Inst{31-21} = 0b11110110101;
1363let hasNewValue = 1;
1364let opNewValue = 0;
1365let prefersSlot3 = 1;
1366let Defs = [USR_OVF];
1367let InputType = "reg";
1368}
1369def A2_svsubuhs : HInst<
1370(outs IntRegs:$Rd32),
1371(ins IntRegs:$Rt32, IntRegs:$Rs32),
1372"$Rd32 = vsubuh($Rt32,$Rs32):sat",
1373tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1374let Inst{7-5} = 0b000;
1375let Inst{13-13} = 0b0;
1376let Inst{31-21} = 0b11110110111;
1377let hasNewValue = 1;
1378let opNewValue = 0;
1379let prefersSlot3 = 1;
1380let Defs = [USR_OVF];
1381let InputType = "reg";
1382}
1383def A2_swiz : HInst<
1384(outs IntRegs:$Rd32),
1385(ins IntRegs:$Rs32),
1386"$Rd32 = swiz($Rs32)",
1387tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1388let Inst{13-5} = 0b000000111;
1389let Inst{31-21} = 0b10001100100;
1390let hasNewValue = 1;
1391let opNewValue = 0;
1392}
1393def A2_sxtb : HInst<
1394(outs IntRegs:$Rd32),
1395(ins IntRegs:$Rs32),
1396"$Rd32 = sxtb($Rs32)",
1397tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1398let Inst{13-5} = 0b000000000;
1399let Inst{31-21} = 0b01110000101;
1400let hasNewValue = 1;
1401let opNewValue = 0;
1402let BaseOpcode = "A2_sxtb";
1403let isPredicable = 1;
1404}
1405def A2_sxth : HInst<
1406(outs IntRegs:$Rd32),
1407(ins IntRegs:$Rs32),
1408"$Rd32 = sxth($Rs32)",
1409tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1410let Inst{13-5} = 0b000000000;
1411let Inst{31-21} = 0b01110000111;
1412let hasNewValue = 1;
1413let opNewValue = 0;
1414let BaseOpcode = "A2_sxth";
1415let isPredicable = 1;
1416}
1417def A2_sxtw : HInst<
1418(outs DoubleRegs:$Rdd32),
1419(ins IntRegs:$Rs32),
1420"$Rdd32 = sxtw($Rs32)",
1421tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
1422let Inst{13-5} = 0b000000000;
1423let Inst{31-21} = 0b10000100010;
1424}
1425def A2_tfr : HInst<
1426(outs IntRegs:$Rd32),
1427(ins IntRegs:$Rs32),
1428"$Rd32 = $Rs32",
1429tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1430let Inst{13-5} = 0b000000000;
1431let Inst{31-21} = 0b01110000011;
1432let hasNewValue = 1;
1433let opNewValue = 0;
1434let BaseOpcode = "A2_tfr";
1435let InputType = "reg";
1436let isPredicable = 1;
1437}
1438def A2_tfrcrr : HInst<
1439(outs IntRegs:$Rd32),
1440(ins CtrRegs:$Cs32),
1441"$Rd32 = $Cs32",
1442tc_7476d766, TypeCR>, Enc_0cb018 {
1443let Inst{13-5} = 0b000000000;
1444let Inst{31-21} = 0b01101010000;
1445let hasNewValue = 1;
1446let opNewValue = 0;
1447}
1448def A2_tfrf : HInst<
1449(outs IntRegs:$Rd32),
1450(ins PredRegs:$Pu4, IntRegs:$Rs32),
1451"if (!$Pu4) $Rd32 = $Rs32",
1452tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1453let isPredicated = 1;
1454let isPredicatedFalse = 1;
1455let hasNewValue = 1;
1456let opNewValue = 0;
1457let BaseOpcode = "A2_tfr";
1458let CextOpcode = "A2_tfr";
1459let InputType = "reg";
1460let isPseudo = 1;
1461let isCodeGenOnly = 1;
1462}
1463def A2_tfrfnew : HInst<
1464(outs IntRegs:$Rd32),
1465(ins PredRegs:$Pu4, IntRegs:$Rs32),
1466"if (!$Pu4.new) $Rd32 = $Rs32",
1467tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1468let isPredicated = 1;
1469let isPredicatedFalse = 1;
1470let hasNewValue = 1;
1471let opNewValue = 0;
1472let isPredicatedNew = 1;
1473let BaseOpcode = "A2_tfr";
1474let CextOpcode = "A2_tfr";
1475let InputType = "reg";
1476let isPseudo = 1;
1477let isCodeGenOnly = 1;
1478}
1479def A2_tfrih : HInst<
1480(outs IntRegs:$Rx32),
1481(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1482"$Rx32.h = #$Ii",
1483tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1484let Inst{21-21} = 0b1;
1485let Inst{31-24} = 0b01110010;
1486let hasNewValue = 1;
1487let opNewValue = 0;
1488let Constraints = "$Rx32 = $Rx32in";
1489}
1490def A2_tfril : HInst<
1491(outs IntRegs:$Rx32),
1492(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1493"$Rx32.l = #$Ii",
1494tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1495let Inst{21-21} = 0b1;
1496let Inst{31-24} = 0b01110001;
1497let hasNewValue = 1;
1498let opNewValue = 0;
1499let Constraints = "$Rx32 = $Rx32in";
1500}
1501def A2_tfrp : HInst<
1502(outs DoubleRegs:$Rdd32),
1503(ins DoubleRegs:$Rss32),
1504"$Rdd32 = $Rss32",
1505tc_713b66bf, TypeALU32_2op>, PredNewRel {
1506let BaseOpcode = "A2_tfrp";
1507let isPredicable = 1;
1508let isPseudo = 1;
1509}
1510def A2_tfrpf : HInst<
1511(outs DoubleRegs:$Rdd32),
1512(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1513"if (!$Pu4) $Rdd32 = $Rss32",
1514tc_713b66bf, TypeALU32_2op>, PredNewRel {
1515let isPredicated = 1;
1516let isPredicatedFalse = 1;
1517let BaseOpcode = "A2_tfrp";
1518let isPseudo = 1;
1519}
1520def A2_tfrpfnew : HInst<
1521(outs DoubleRegs:$Rdd32),
1522(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1523"if (!$Pu4.new) $Rdd32 = $Rss32",
1524tc_86173609, TypeALU32_2op>, PredNewRel {
1525let isPredicated = 1;
1526let isPredicatedFalse = 1;
1527let isPredicatedNew = 1;
1528let BaseOpcode = "A2_tfrp";
1529let isPseudo = 1;
1530}
1531def A2_tfrpi : HInst<
1532(outs DoubleRegs:$Rdd32),
1533(ins s8_0Imm:$Ii),
1534"$Rdd32 = #$Ii",
1535tc_713b66bf, TypeALU64> {
1536let isAsCheapAsAMove = 1;
1537let isMoveImm = 1;
1538let isReMaterializable = 1;
1539let isPseudo = 1;
1540}
1541def A2_tfrpt : HInst<
1542(outs DoubleRegs:$Rdd32),
1543(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1544"if ($Pu4) $Rdd32 = $Rss32",
1545tc_713b66bf, TypeALU32_2op>, PredNewRel {
1546let isPredicated = 1;
1547let BaseOpcode = "A2_tfrp";
1548let isPseudo = 1;
1549}
1550def A2_tfrptnew : HInst<
1551(outs DoubleRegs:$Rdd32),
1552(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1553"if ($Pu4.new) $Rdd32 = $Rss32",
1554tc_86173609, TypeALU32_2op>, PredNewRel {
1555let isPredicated = 1;
1556let isPredicatedNew = 1;
1557let BaseOpcode = "A2_tfrp";
1558let isPseudo = 1;
1559}
1560def A2_tfrrcr : HInst<
1561(outs CtrRegs:$Cd32),
1562(ins IntRegs:$Rs32),
1563"$Cd32 = $Rs32",
1564tc_49fdfd4b, TypeCR>, Enc_bd811a {
1565let Inst{13-5} = 0b000000000;
1566let Inst{31-21} = 0b01100010001;
1567let hasNewValue = 1;
1568let opNewValue = 0;
1569}
1570def A2_tfrsi : HInst<
1571(outs IntRegs:$Rd32),
1572(ins s32_0Imm:$Ii),
1573"$Rd32 = #$Ii",
1574tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
1575let Inst{21-21} = 0b0;
1576let Inst{31-24} = 0b01111000;
1577let hasNewValue = 1;
1578let opNewValue = 0;
1579let BaseOpcode = "A2_tfrsi";
1580let CextOpcode = "A2_tfr";
1581let InputType = "imm";
1582let isAsCheapAsAMove = 1;
1583let isMoveImm = 1;
1584let isPredicable = 1;
1585let isReMaterializable = 1;
1586let isExtendable = 1;
1587let opExtendable = 1;
1588let isExtentSigned = 1;
1589let opExtentBits = 16;
1590let opExtentAlign = 0;
1591}
1592def A2_tfrt : HInst<
1593(outs IntRegs:$Rd32),
1594(ins PredRegs:$Pu4, IntRegs:$Rs32),
1595"if ($Pu4) $Rd32 = $Rs32",
1596tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1597let isPredicated = 1;
1598let hasNewValue = 1;
1599let opNewValue = 0;
1600let BaseOpcode = "A2_tfr";
1601let CextOpcode = "A2_tfr";
1602let InputType = "reg";
1603let isPseudo = 1;
1604let isCodeGenOnly = 1;
1605}
1606def A2_tfrtnew : HInst<
1607(outs IntRegs:$Rd32),
1608(ins PredRegs:$Pu4, IntRegs:$Rs32),
1609"if ($Pu4.new) $Rd32 = $Rs32",
1610tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1611let isPredicated = 1;
1612let hasNewValue = 1;
1613let opNewValue = 0;
1614let isPredicatedNew = 1;
1615let BaseOpcode = "A2_tfr";
1616let CextOpcode = "A2_tfr";
1617let InputType = "reg";
1618let isPseudo = 1;
1619let isCodeGenOnly = 1;
1620}
1621def A2_vabsh : HInst<
1622(outs DoubleRegs:$Rdd32),
1623(ins DoubleRegs:$Rss32),
1624"$Rdd32 = vabsh($Rss32)",
1625tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1626let Inst{13-5} = 0b000000100;
1627let Inst{31-21} = 0b10000000010;
1628let prefersSlot3 = 1;
1629}
1630def A2_vabshsat : HInst<
1631(outs DoubleRegs:$Rdd32),
1632(ins DoubleRegs:$Rss32),
1633"$Rdd32 = vabsh($Rss32):sat",
1634tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1635let Inst{13-5} = 0b000000101;
1636let Inst{31-21} = 0b10000000010;
1637let prefersSlot3 = 1;
1638let Defs = [USR_OVF];
1639}
1640def A2_vabsw : HInst<
1641(outs DoubleRegs:$Rdd32),
1642(ins DoubleRegs:$Rss32),
1643"$Rdd32 = vabsw($Rss32)",
1644tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1645let Inst{13-5} = 0b000000110;
1646let Inst{31-21} = 0b10000000010;
1647let prefersSlot3 = 1;
1648}
1649def A2_vabswsat : HInst<
1650(outs DoubleRegs:$Rdd32),
1651(ins DoubleRegs:$Rss32),
1652"$Rdd32 = vabsw($Rss32):sat",
1653tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1654let Inst{13-5} = 0b000000111;
1655let Inst{31-21} = 0b10000000010;
1656let prefersSlot3 = 1;
1657let Defs = [USR_OVF];
1658}
1659def A2_vaddb_map : HInst<
1660(outs DoubleRegs:$Rdd32),
1661(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1662"$Rdd32 = vaddb($Rss32,$Rtt32)",
1663tc_5da50c4b, TypeMAPPING> {
1664let isPseudo = 1;
1665let isCodeGenOnly = 1;
1666}
1667def A2_vaddh : HInst<
1668(outs DoubleRegs:$Rdd32),
1669(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1670"$Rdd32 = vaddh($Rss32,$Rtt32)",
1671tc_5da50c4b, TypeALU64>, Enc_a56825 {
1672let Inst{7-5} = 0b010;
1673let Inst{13-13} = 0b0;
1674let Inst{31-21} = 0b11010011000;
1675}
1676def A2_vaddhs : HInst<
1677(outs DoubleRegs:$Rdd32),
1678(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1679"$Rdd32 = vaddh($Rss32,$Rtt32):sat",
1680tc_8a825db2, TypeALU64>, Enc_a56825 {
1681let Inst{7-5} = 0b011;
1682let Inst{13-13} = 0b0;
1683let Inst{31-21} = 0b11010011000;
1684let prefersSlot3 = 1;
1685let Defs = [USR_OVF];
1686}
1687def A2_vaddub : HInst<
1688(outs DoubleRegs:$Rdd32),
1689(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1690"$Rdd32 = vaddub($Rss32,$Rtt32)",
1691tc_5da50c4b, TypeALU64>, Enc_a56825 {
1692let Inst{7-5} = 0b000;
1693let Inst{13-13} = 0b0;
1694let Inst{31-21} = 0b11010011000;
1695}
1696def A2_vaddubs : HInst<
1697(outs DoubleRegs:$Rdd32),
1698(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1699"$Rdd32 = vaddub($Rss32,$Rtt32):sat",
1700tc_8a825db2, TypeALU64>, Enc_a56825 {
1701let Inst{7-5} = 0b001;
1702let Inst{13-13} = 0b0;
1703let Inst{31-21} = 0b11010011000;
1704let prefersSlot3 = 1;
1705let Defs = [USR_OVF];
1706}
1707def A2_vadduhs : HInst<
1708(outs DoubleRegs:$Rdd32),
1709(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1710"$Rdd32 = vadduh($Rss32,$Rtt32):sat",
1711tc_8a825db2, TypeALU64>, Enc_a56825 {
1712let Inst{7-5} = 0b100;
1713let Inst{13-13} = 0b0;
1714let Inst{31-21} = 0b11010011000;
1715let prefersSlot3 = 1;
1716let Defs = [USR_OVF];
1717}
1718def A2_vaddw : HInst<
1719(outs DoubleRegs:$Rdd32),
1720(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1721"$Rdd32 = vaddw($Rss32,$Rtt32)",
1722tc_5da50c4b, TypeALU64>, Enc_a56825 {
1723let Inst{7-5} = 0b101;
1724let Inst{13-13} = 0b0;
1725let Inst{31-21} = 0b11010011000;
1726}
1727def A2_vaddws : HInst<
1728(outs DoubleRegs:$Rdd32),
1729(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1730"$Rdd32 = vaddw($Rss32,$Rtt32):sat",
1731tc_8a825db2, TypeALU64>, Enc_a56825 {
1732let Inst{7-5} = 0b110;
1733let Inst{13-13} = 0b0;
1734let Inst{31-21} = 0b11010011000;
1735let prefersSlot3 = 1;
1736let Defs = [USR_OVF];
1737}
1738def A2_vavgh : HInst<
1739(outs DoubleRegs:$Rdd32),
1740(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1741"$Rdd32 = vavgh($Rss32,$Rtt32)",
1742tc_f098b237, TypeALU64>, Enc_a56825 {
1743let Inst{7-5} = 0b010;
1744let Inst{13-13} = 0b0;
1745let Inst{31-21} = 0b11010011010;
1746let prefersSlot3 = 1;
1747}
1748def A2_vavghcr : HInst<
1749(outs DoubleRegs:$Rdd32),
1750(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1751"$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
1752tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1753let Inst{7-5} = 0b100;
1754let Inst{13-13} = 0b0;
1755let Inst{31-21} = 0b11010011010;
1756let prefersSlot3 = 1;
1757}
1758def A2_vavghr : HInst<
1759(outs DoubleRegs:$Rdd32),
1760(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1761"$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
1762tc_20131976, TypeALU64>, Enc_a56825 {
1763let Inst{7-5} = 0b011;
1764let Inst{13-13} = 0b0;
1765let Inst{31-21} = 0b11010011010;
1766let prefersSlot3 = 1;
1767}
1768def A2_vavgub : HInst<
1769(outs DoubleRegs:$Rdd32),
1770(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1771"$Rdd32 = vavgub($Rss32,$Rtt32)",
1772tc_f098b237, TypeALU64>, Enc_a56825 {
1773let Inst{7-5} = 0b000;
1774let Inst{13-13} = 0b0;
1775let Inst{31-21} = 0b11010011010;
1776let prefersSlot3 = 1;
1777}
1778def A2_vavgubr : HInst<
1779(outs DoubleRegs:$Rdd32),
1780(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1781"$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
1782tc_20131976, TypeALU64>, Enc_a56825 {
1783let Inst{7-5} = 0b001;
1784let Inst{13-13} = 0b0;
1785let Inst{31-21} = 0b11010011010;
1786let prefersSlot3 = 1;
1787}
1788def A2_vavguh : HInst<
1789(outs DoubleRegs:$Rdd32),
1790(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1791"$Rdd32 = vavguh($Rss32,$Rtt32)",
1792tc_f098b237, TypeALU64>, Enc_a56825 {
1793let Inst{7-5} = 0b101;
1794let Inst{13-13} = 0b0;
1795let Inst{31-21} = 0b11010011010;
1796let prefersSlot3 = 1;
1797}
1798def A2_vavguhr : HInst<
1799(outs DoubleRegs:$Rdd32),
1800(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1801"$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
1802tc_20131976, TypeALU64>, Enc_a56825 {
1803let Inst{7-5} = 0b110;
1804let Inst{13-13} = 0b0;
1805let Inst{31-21} = 0b11010011010;
1806let prefersSlot3 = 1;
1807}
1808def A2_vavguw : HInst<
1809(outs DoubleRegs:$Rdd32),
1810(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1811"$Rdd32 = vavguw($Rss32,$Rtt32)",
1812tc_f098b237, TypeALU64>, Enc_a56825 {
1813let Inst{7-5} = 0b011;
1814let Inst{13-13} = 0b0;
1815let Inst{31-21} = 0b11010011011;
1816let prefersSlot3 = 1;
1817}
1818def A2_vavguwr : HInst<
1819(outs DoubleRegs:$Rdd32),
1820(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1821"$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
1822tc_20131976, TypeALU64>, Enc_a56825 {
1823let Inst{7-5} = 0b100;
1824let Inst{13-13} = 0b0;
1825let Inst{31-21} = 0b11010011011;
1826let prefersSlot3 = 1;
1827}
1828def A2_vavgw : HInst<
1829(outs DoubleRegs:$Rdd32),
1830(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1831"$Rdd32 = vavgw($Rss32,$Rtt32)",
1832tc_f098b237, TypeALU64>, Enc_a56825 {
1833let Inst{7-5} = 0b000;
1834let Inst{13-13} = 0b0;
1835let Inst{31-21} = 0b11010011011;
1836let prefersSlot3 = 1;
1837}
1838def A2_vavgwcr : HInst<
1839(outs DoubleRegs:$Rdd32),
1840(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1841"$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
1842tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1843let Inst{7-5} = 0b010;
1844let Inst{13-13} = 0b0;
1845let Inst{31-21} = 0b11010011011;
1846let prefersSlot3 = 1;
1847}
1848def A2_vavgwr : HInst<
1849(outs DoubleRegs:$Rdd32),
1850(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1851"$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
1852tc_20131976, TypeALU64>, Enc_a56825 {
1853let Inst{7-5} = 0b001;
1854let Inst{13-13} = 0b0;
1855let Inst{31-21} = 0b11010011011;
1856let prefersSlot3 = 1;
1857}
1858def A2_vcmpbeq : HInst<
1859(outs PredRegs:$Pd4),
1860(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1861"$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
1862tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1863let Inst{7-2} = 0b110000;
1864let Inst{13-13} = 0b0;
1865let Inst{31-21} = 0b11010010000;
1866}
1867def A2_vcmpbgtu : HInst<
1868(outs PredRegs:$Pd4),
1869(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1870"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
1871tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1872let Inst{7-2} = 0b111000;
1873let Inst{13-13} = 0b0;
1874let Inst{31-21} = 0b11010010000;
1875}
1876def A2_vcmpheq : HInst<
1877(outs PredRegs:$Pd4),
1878(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1879"$Pd4 = vcmph.eq($Rss32,$Rtt32)",
1880tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1881let Inst{7-2} = 0b011000;
1882let Inst{13-13} = 0b0;
1883let Inst{31-21} = 0b11010010000;
1884}
1885def A2_vcmphgt : HInst<
1886(outs PredRegs:$Pd4),
1887(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1888"$Pd4 = vcmph.gt($Rss32,$Rtt32)",
1889tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1890let Inst{7-2} = 0b100000;
1891let Inst{13-13} = 0b0;
1892let Inst{31-21} = 0b11010010000;
1893}
1894def A2_vcmphgtu : HInst<
1895(outs PredRegs:$Pd4),
1896(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1897"$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
1898tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1899let Inst{7-2} = 0b101000;
1900let Inst{13-13} = 0b0;
1901let Inst{31-21} = 0b11010010000;
1902}
1903def A2_vcmpweq : HInst<
1904(outs PredRegs:$Pd4),
1905(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1906"$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
1907tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1908let Inst{7-2} = 0b000000;
1909let Inst{13-13} = 0b0;
1910let Inst{31-21} = 0b11010010000;
1911}
1912def A2_vcmpwgt : HInst<
1913(outs PredRegs:$Pd4),
1914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1915"$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
1916tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1917let Inst{7-2} = 0b001000;
1918let Inst{13-13} = 0b0;
1919let Inst{31-21} = 0b11010010000;
1920}
1921def A2_vcmpwgtu : HInst<
1922(outs PredRegs:$Pd4),
1923(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1924"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
1925tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1926let Inst{7-2} = 0b010000;
1927let Inst{13-13} = 0b0;
1928let Inst{31-21} = 0b11010010000;
1929}
1930def A2_vconj : HInst<
1931(outs DoubleRegs:$Rdd32),
1932(ins DoubleRegs:$Rss32),
1933"$Rdd32 = vconj($Rss32):sat",
1934tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1935let Inst{13-5} = 0b000000111;
1936let Inst{31-21} = 0b10000000100;
1937let prefersSlot3 = 1;
1938let Defs = [USR_OVF];
1939}
1940def A2_vmaxb : HInst<
1941(outs DoubleRegs:$Rdd32),
1942(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1943"$Rdd32 = vmaxb($Rtt32,$Rss32)",
1944tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1945let Inst{7-5} = 0b110;
1946let Inst{13-13} = 0b0;
1947let Inst{31-21} = 0b11010011110;
1948let prefersSlot3 = 1;
1949}
1950def A2_vmaxh : HInst<
1951(outs DoubleRegs:$Rdd32),
1952(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1953"$Rdd32 = vmaxh($Rtt32,$Rss32)",
1954tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1955let Inst{7-5} = 0b001;
1956let Inst{13-13} = 0b0;
1957let Inst{31-21} = 0b11010011110;
1958let prefersSlot3 = 1;
1959}
1960def A2_vmaxub : HInst<
1961(outs DoubleRegs:$Rdd32),
1962(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1963"$Rdd32 = vmaxub($Rtt32,$Rss32)",
1964tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1965let Inst{7-5} = 0b000;
1966let Inst{13-13} = 0b0;
1967let Inst{31-21} = 0b11010011110;
1968let prefersSlot3 = 1;
1969}
1970def A2_vmaxuh : HInst<
1971(outs DoubleRegs:$Rdd32),
1972(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1973"$Rdd32 = vmaxuh($Rtt32,$Rss32)",
1974tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1975let Inst{7-5} = 0b010;
1976let Inst{13-13} = 0b0;
1977let Inst{31-21} = 0b11010011110;
1978let prefersSlot3 = 1;
1979}
1980def A2_vmaxuw : HInst<
1981(outs DoubleRegs:$Rdd32),
1982(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1983"$Rdd32 = vmaxuw($Rtt32,$Rss32)",
1984tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1985let Inst{7-5} = 0b101;
1986let Inst{13-13} = 0b0;
1987let Inst{31-21} = 0b11010011101;
1988let prefersSlot3 = 1;
1989}
1990def A2_vmaxw : HInst<
1991(outs DoubleRegs:$Rdd32),
1992(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1993"$Rdd32 = vmaxw($Rtt32,$Rss32)",
1994tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1995let Inst{7-5} = 0b011;
1996let Inst{13-13} = 0b0;
1997let Inst{31-21} = 0b11010011110;
1998let prefersSlot3 = 1;
1999}
2000def A2_vminb : HInst<
2001(outs DoubleRegs:$Rdd32),
2002(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2003"$Rdd32 = vminb($Rtt32,$Rss32)",
2004tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2005let Inst{7-5} = 0b111;
2006let Inst{13-13} = 0b0;
2007let Inst{31-21} = 0b11010011110;
2008let prefersSlot3 = 1;
2009}
2010def A2_vminh : HInst<
2011(outs DoubleRegs:$Rdd32),
2012(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2013"$Rdd32 = vminh($Rtt32,$Rss32)",
2014tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2015let Inst{7-5} = 0b001;
2016let Inst{13-13} = 0b0;
2017let Inst{31-21} = 0b11010011101;
2018let prefersSlot3 = 1;
2019}
2020def A2_vminub : HInst<
2021(outs DoubleRegs:$Rdd32),
2022(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2023"$Rdd32 = vminub($Rtt32,$Rss32)",
2024tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2025let Inst{7-5} = 0b000;
2026let Inst{13-13} = 0b0;
2027let Inst{31-21} = 0b11010011101;
2028let prefersSlot3 = 1;
2029}
2030def A2_vminuh : HInst<
2031(outs DoubleRegs:$Rdd32),
2032(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2033"$Rdd32 = vminuh($Rtt32,$Rss32)",
2034tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2035let Inst{7-5} = 0b010;
2036let Inst{13-13} = 0b0;
2037let Inst{31-21} = 0b11010011101;
2038let prefersSlot3 = 1;
2039}
2040def A2_vminuw : HInst<
2041(outs DoubleRegs:$Rdd32),
2042(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2043"$Rdd32 = vminuw($Rtt32,$Rss32)",
2044tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2045let Inst{7-5} = 0b100;
2046let Inst{13-13} = 0b0;
2047let Inst{31-21} = 0b11010011101;
2048let prefersSlot3 = 1;
2049}
2050def A2_vminw : HInst<
2051(outs DoubleRegs:$Rdd32),
2052(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2053"$Rdd32 = vminw($Rtt32,$Rss32)",
2054tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2055let Inst{7-5} = 0b011;
2056let Inst{13-13} = 0b0;
2057let Inst{31-21} = 0b11010011101;
2058let prefersSlot3 = 1;
2059}
2060def A2_vnavgh : HInst<
2061(outs DoubleRegs:$Rdd32),
2062(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2063"$Rdd32 = vnavgh($Rtt32,$Rss32)",
2064tc_f098b237, TypeALU64>, Enc_ea23e4 {
2065let Inst{7-5} = 0b000;
2066let Inst{13-13} = 0b0;
2067let Inst{31-21} = 0b11010011100;
2068let prefersSlot3 = 1;
2069}
2070def A2_vnavghcr : HInst<
2071(outs DoubleRegs:$Rdd32),
2072(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2073"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
2074tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2075let Inst{7-5} = 0b010;
2076let Inst{13-13} = 0b0;
2077let Inst{31-21} = 0b11010011100;
2078let prefersSlot3 = 1;
2079let Defs = [USR_OVF];
2080}
2081def A2_vnavghr : HInst<
2082(outs DoubleRegs:$Rdd32),
2083(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2084"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
2085tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2086let Inst{7-5} = 0b001;
2087let Inst{13-13} = 0b0;
2088let Inst{31-21} = 0b11010011100;
2089let prefersSlot3 = 1;
2090let Defs = [USR_OVF];
2091}
2092def A2_vnavgw : HInst<
2093(outs DoubleRegs:$Rdd32),
2094(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2095"$Rdd32 = vnavgw($Rtt32,$Rss32)",
2096tc_f098b237, TypeALU64>, Enc_ea23e4 {
2097let Inst{7-5} = 0b011;
2098let Inst{13-13} = 0b0;
2099let Inst{31-21} = 0b11010011100;
2100let prefersSlot3 = 1;
2101}
2102def A2_vnavgwcr : HInst<
2103(outs DoubleRegs:$Rdd32),
2104(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2105"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
2106tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2107let Inst{7-5} = 0b110;
2108let Inst{13-13} = 0b0;
2109let Inst{31-21} = 0b11010011100;
2110let prefersSlot3 = 1;
2111let Defs = [USR_OVF];
2112}
2113def A2_vnavgwr : HInst<
2114(outs DoubleRegs:$Rdd32),
2115(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2116"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
2117tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2118let Inst{7-5} = 0b100;
2119let Inst{13-13} = 0b0;
2120let Inst{31-21} = 0b11010011100;
2121let prefersSlot3 = 1;
2122let Defs = [USR_OVF];
2123}
2124def A2_vraddub : HInst<
2125(outs DoubleRegs:$Rdd32),
2126(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2127"$Rdd32 = vraddub($Rss32,$Rtt32)",
2128tc_c21d7447, TypeM>, Enc_a56825 {
2129let Inst{7-5} = 0b001;
2130let Inst{13-13} = 0b0;
2131let Inst{31-21} = 0b11101000010;
2132let prefersSlot3 = 1;
2133}
2134def A2_vraddub_acc : HInst<
2135(outs DoubleRegs:$Rxx32),
2136(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2137"$Rxx32 += vraddub($Rss32,$Rtt32)",
2138tc_7f8ae742, TypeM>, Enc_88c16c {
2139let Inst{7-5} = 0b001;
2140let Inst{13-13} = 0b0;
2141let Inst{31-21} = 0b11101010010;
2142let prefersSlot3 = 1;
2143let Constraints = "$Rxx32 = $Rxx32in";
2144}
2145def A2_vrsadub : HInst<
2146(outs DoubleRegs:$Rdd32),
2147(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2148"$Rdd32 = vrsadub($Rss32,$Rtt32)",
2149tc_c21d7447, TypeM>, Enc_a56825 {
2150let Inst{7-5} = 0b010;
2151let Inst{13-13} = 0b0;
2152let Inst{31-21} = 0b11101000010;
2153let prefersSlot3 = 1;
2154}
2155def A2_vrsadub_acc : HInst<
2156(outs DoubleRegs:$Rxx32),
2157(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2158"$Rxx32 += vrsadub($Rss32,$Rtt32)",
2159tc_7f8ae742, TypeM>, Enc_88c16c {
2160let Inst{7-5} = 0b010;
2161let Inst{13-13} = 0b0;
2162let Inst{31-21} = 0b11101010010;
2163let prefersSlot3 = 1;
2164let Constraints = "$Rxx32 = $Rxx32in";
2165}
2166def A2_vsubb_map : HInst<
2167(outs DoubleRegs:$Rdd32),
2168(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2169"$Rdd32 = vsubb($Rss32,$Rtt32)",
2170tc_5da50c4b, TypeMAPPING> {
2171let isPseudo = 1;
2172let isCodeGenOnly = 1;
2173}
2174def A2_vsubh : HInst<
2175(outs DoubleRegs:$Rdd32),
2176(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2177"$Rdd32 = vsubh($Rtt32,$Rss32)",
2178tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2179let Inst{7-5} = 0b010;
2180let Inst{13-13} = 0b0;
2181let Inst{31-21} = 0b11010011001;
2182}
2183def A2_vsubhs : HInst<
2184(outs DoubleRegs:$Rdd32),
2185(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2186"$Rdd32 = vsubh($Rtt32,$Rss32):sat",
2187tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2188let Inst{7-5} = 0b011;
2189let Inst{13-13} = 0b0;
2190let Inst{31-21} = 0b11010011001;
2191let prefersSlot3 = 1;
2192let Defs = [USR_OVF];
2193}
2194def A2_vsubub : HInst<
2195(outs DoubleRegs:$Rdd32),
2196(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2197"$Rdd32 = vsubub($Rtt32,$Rss32)",
2198tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2199let Inst{7-5} = 0b000;
2200let Inst{13-13} = 0b0;
2201let Inst{31-21} = 0b11010011001;
2202}
2203def A2_vsububs : HInst<
2204(outs DoubleRegs:$Rdd32),
2205(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2206"$Rdd32 = vsubub($Rtt32,$Rss32):sat",
2207tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2208let Inst{7-5} = 0b001;
2209let Inst{13-13} = 0b0;
2210let Inst{31-21} = 0b11010011001;
2211let prefersSlot3 = 1;
2212let Defs = [USR_OVF];
2213}
2214def A2_vsubuhs : HInst<
2215(outs DoubleRegs:$Rdd32),
2216(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2217"$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
2218tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2219let Inst{7-5} = 0b100;
2220let Inst{13-13} = 0b0;
2221let Inst{31-21} = 0b11010011001;
2222let prefersSlot3 = 1;
2223let Defs = [USR_OVF];
2224}
2225def A2_vsubw : HInst<
2226(outs DoubleRegs:$Rdd32),
2227(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2228"$Rdd32 = vsubw($Rtt32,$Rss32)",
2229tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2230let Inst{7-5} = 0b101;
2231let Inst{13-13} = 0b0;
2232let Inst{31-21} = 0b11010011001;
2233}
2234def A2_vsubws : HInst<
2235(outs DoubleRegs:$Rdd32),
2236(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2237"$Rdd32 = vsubw($Rtt32,$Rss32):sat",
2238tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2239let Inst{7-5} = 0b110;
2240let Inst{13-13} = 0b0;
2241let Inst{31-21} = 0b11010011001;
2242let prefersSlot3 = 1;
2243let Defs = [USR_OVF];
2244}
2245def A2_xor : HInst<
2246(outs IntRegs:$Rd32),
2247(ins IntRegs:$Rs32, IntRegs:$Rt32),
2248"$Rd32 = xor($Rs32,$Rt32)",
2249tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
2250let Inst{7-5} = 0b000;
2251let Inst{13-13} = 0b0;
2252let Inst{31-21} = 0b11110001011;
2253let hasNewValue = 1;
2254let opNewValue = 0;
2255let BaseOpcode = "A2_xor";
2256let InputType = "reg";
2257let isCommutable = 1;
2258let isPredicable = 1;
2259}
2260def A2_xorp : HInst<
2261(outs DoubleRegs:$Rdd32),
2262(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2263"$Rdd32 = xor($Rss32,$Rtt32)",
2264tc_5da50c4b, TypeALU64>, Enc_a56825 {
2265let Inst{7-5} = 0b100;
2266let Inst{13-13} = 0b0;
2267let Inst{31-21} = 0b11010011111;
2268let isCommutable = 1;
2269}
2270def A2_zxtb : HInst<
2271(outs IntRegs:$Rd32),
2272(ins IntRegs:$Rs32),
2273"$Rd32 = zxtb($Rs32)",
2274tc_713b66bf, TypeALU32_2op>, PredNewRel {
2275let hasNewValue = 1;
2276let opNewValue = 0;
2277let BaseOpcode = "A2_zxtb";
2278let isPredicable = 1;
2279let isPseudo = 1;
2280let isCodeGenOnly = 1;
2281}
2282def A2_zxth : HInst<
2283(outs IntRegs:$Rd32),
2284(ins IntRegs:$Rs32),
2285"$Rd32 = zxth($Rs32)",
2286tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
2287let Inst{13-5} = 0b000000000;
2288let Inst{31-21} = 0b01110000110;
2289let hasNewValue = 1;
2290let opNewValue = 0;
2291let BaseOpcode = "A2_zxth";
2292let isPredicable = 1;
2293}
2294def A4_addp_c : HInst<
2295(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
2296(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
2297"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
2298tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
2299let Inst{7-7} = 0b0;
2300let Inst{13-13} = 0b0;
2301let Inst{31-21} = 0b11000010110;
2302let isPredicateLate = 1;
2303let Constraints = "$Px4 = $Px4in";
2304}
2305def A4_andn : HInst<
2306(outs IntRegs:$Rd32),
2307(ins IntRegs:$Rt32, IntRegs:$Rs32),
2308"$Rd32 = and($Rt32,~$Rs32)",
2309tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2310let Inst{7-5} = 0b000;
2311let Inst{13-13} = 0b0;
2312let Inst{31-21} = 0b11110001100;
2313let hasNewValue = 1;
2314let opNewValue = 0;
2315let InputType = "reg";
2316}
2317def A4_andnp : HInst<
2318(outs DoubleRegs:$Rdd32),
2319(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2320"$Rdd32 = and($Rtt32,~$Rss32)",
2321tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2322let Inst{7-5} = 0b001;
2323let Inst{13-13} = 0b0;
2324let Inst{31-21} = 0b11010011111;
2325}
2326def A4_bitsplit : HInst<
2327(outs DoubleRegs:$Rdd32),
2328(ins IntRegs:$Rs32, IntRegs:$Rt32),
2329"$Rdd32 = bitsplit($Rs32,$Rt32)",
2330tc_f34c1c21, TypeALU64>, Enc_be32a5 {
2331let Inst{7-5} = 0b000;
2332let Inst{13-13} = 0b0;
2333let Inst{31-21} = 0b11010100001;
2334let prefersSlot3 = 1;
2335}
2336def A4_bitspliti : HInst<
2337(outs DoubleRegs:$Rdd32),
2338(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2339"$Rdd32 = bitsplit($Rs32,#$Ii)",
2340tc_f34c1c21, TypeS_2op>, Enc_311abd {
2341let Inst{7-5} = 0b100;
2342let Inst{13-13} = 0b0;
2343let Inst{31-21} = 0b10001000110;
2344let prefersSlot3 = 1;
2345}
2346def A4_boundscheck : HInst<
2347(outs PredRegs:$Pd4),
2348(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
2349"$Pd4 = boundscheck($Rs32,$Rtt32)",
2350tc_4a55d03c, TypeALU64> {
2351let isPseudo = 1;
2352}
2353def A4_boundscheck_hi : HInst<
2354(outs PredRegs:$Pd4),
2355(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2356"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
2357tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2358let Inst{7-2} = 0b101000;
2359let Inst{13-13} = 0b1;
2360let Inst{31-21} = 0b11010010000;
2361}
2362def A4_boundscheck_lo : HInst<
2363(outs PredRegs:$Pd4),
2364(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2365"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
2366tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2367let Inst{7-2} = 0b100000;
2368let Inst{13-13} = 0b1;
2369let Inst{31-21} = 0b11010010000;
2370}
2371def A4_cmpbeq : HInst<
2372(outs PredRegs:$Pd4),
2373(ins IntRegs:$Rs32, IntRegs:$Rt32),
2374"$Pd4 = cmpb.eq($Rs32,$Rt32)",
2375tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2376let Inst{7-2} = 0b110000;
2377let Inst{13-13} = 0b0;
2378let Inst{31-21} = 0b11000111110;
2379let CextOpcode = "A4_cmpbeq";
2380let InputType = "reg";
2381let isCommutable = 1;
2382let isCompare = 1;
2383}
2384def A4_cmpbeqi : HInst<
2385(outs PredRegs:$Pd4),
2386(ins IntRegs:$Rs32, u8_0Imm:$Ii),
2387"$Pd4 = cmpb.eq($Rs32,#$Ii)",
2388tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2389let Inst{4-2} = 0b000;
2390let Inst{13-13} = 0b0;
2391let Inst{31-21} = 0b11011101000;
2392let CextOpcode = "A4_cmpbeq";
2393let InputType = "imm";
2394let isCommutable = 1;
2395let isCompare = 1;
2396}
2397def A4_cmpbgt : HInst<
2398(outs PredRegs:$Pd4),
2399(ins IntRegs:$Rs32, IntRegs:$Rt32),
2400"$Pd4 = cmpb.gt($Rs32,$Rt32)",
2401tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2402let Inst{7-2} = 0b010000;
2403let Inst{13-13} = 0b0;
2404let Inst{31-21} = 0b11000111110;
2405let CextOpcode = "A4_cmpbgt";
2406let InputType = "reg";
2407let isCompare = 1;
2408}
2409def A4_cmpbgti : HInst<
2410(outs PredRegs:$Pd4),
2411(ins IntRegs:$Rs32, s8_0Imm:$Ii),
2412"$Pd4 = cmpb.gt($Rs32,#$Ii)",
2413tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2414let Inst{4-2} = 0b000;
2415let Inst{13-13} = 0b0;
2416let Inst{31-21} = 0b11011101001;
2417let CextOpcode = "A4_cmpbgt";
2418let InputType = "imm";
2419let isCompare = 1;
2420}
2421def A4_cmpbgtu : HInst<
2422(outs PredRegs:$Pd4),
2423(ins IntRegs:$Rs32, IntRegs:$Rt32),
2424"$Pd4 = cmpb.gtu($Rs32,$Rt32)",
2425tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2426let Inst{7-2} = 0b111000;
2427let Inst{13-13} = 0b0;
2428let Inst{31-21} = 0b11000111110;
2429let CextOpcode = "A4_cmpbgtu";
2430let InputType = "reg";
2431let isCompare = 1;
2432}
2433def A4_cmpbgtui : HInst<
2434(outs PredRegs:$Pd4),
2435(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2436"$Pd4 = cmpb.gtu($Rs32,#$Ii)",
2437tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2438let Inst{4-2} = 0b000;
2439let Inst{13-12} = 0b00;
2440let Inst{31-21} = 0b11011101010;
2441let CextOpcode = "A4_cmpbgtu";
2442let InputType = "imm";
2443let isCompare = 1;
2444let isExtendable = 1;
2445let opExtendable = 2;
2446let isExtentSigned = 0;
2447let opExtentBits = 7;
2448let opExtentAlign = 0;
2449}
2450def A4_cmpheq : HInst<
2451(outs PredRegs:$Pd4),
2452(ins IntRegs:$Rs32, IntRegs:$Rt32),
2453"$Pd4 = cmph.eq($Rs32,$Rt32)",
2454tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2455let Inst{7-2} = 0b011000;
2456let Inst{13-13} = 0b0;
2457let Inst{31-21} = 0b11000111110;
2458let CextOpcode = "A4_cmpheq";
2459let InputType = "reg";
2460let isCommutable = 1;
2461let isCompare = 1;
2462}
2463def A4_cmpheqi : HInst<
2464(outs PredRegs:$Pd4),
2465(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2466"$Pd4 = cmph.eq($Rs32,#$Ii)",
2467tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2468let Inst{4-2} = 0b010;
2469let Inst{13-13} = 0b0;
2470let Inst{31-21} = 0b11011101000;
2471let CextOpcode = "A4_cmpheq";
2472let InputType = "imm";
2473let isCommutable = 1;
2474let isCompare = 1;
2475let isExtendable = 1;
2476let opExtendable = 2;
2477let isExtentSigned = 1;
2478let opExtentBits = 8;
2479let opExtentAlign = 0;
2480}
2481def A4_cmphgt : HInst<
2482(outs PredRegs:$Pd4),
2483(ins IntRegs:$Rs32, IntRegs:$Rt32),
2484"$Pd4 = cmph.gt($Rs32,$Rt32)",
2485tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2486let Inst{7-2} = 0b100000;
2487let Inst{13-13} = 0b0;
2488let Inst{31-21} = 0b11000111110;
2489let CextOpcode = "A4_cmphgt";
2490let InputType = "reg";
2491let isCompare = 1;
2492}
2493def A4_cmphgti : HInst<
2494(outs PredRegs:$Pd4),
2495(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2496"$Pd4 = cmph.gt($Rs32,#$Ii)",
2497tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2498let Inst{4-2} = 0b010;
2499let Inst{13-13} = 0b0;
2500let Inst{31-21} = 0b11011101001;
2501let CextOpcode = "A4_cmphgt";
2502let InputType = "imm";
2503let isCompare = 1;
2504let isExtendable = 1;
2505let opExtendable = 2;
2506let isExtentSigned = 1;
2507let opExtentBits = 8;
2508let opExtentAlign = 0;
2509}
2510def A4_cmphgtu : HInst<
2511(outs PredRegs:$Pd4),
2512(ins IntRegs:$Rs32, IntRegs:$Rt32),
2513"$Pd4 = cmph.gtu($Rs32,$Rt32)",
2514tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2515let Inst{7-2} = 0b101000;
2516let Inst{13-13} = 0b0;
2517let Inst{31-21} = 0b11000111110;
2518let CextOpcode = "A4_cmphgtu";
2519let InputType = "reg";
2520let isCompare = 1;
2521}
2522def A4_cmphgtui : HInst<
2523(outs PredRegs:$Pd4),
2524(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2525"$Pd4 = cmph.gtu($Rs32,#$Ii)",
2526tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2527let Inst{4-2} = 0b010;
2528let Inst{13-12} = 0b00;
2529let Inst{31-21} = 0b11011101010;
2530let CextOpcode = "A4_cmphgtu";
2531let InputType = "imm";
2532let isCompare = 1;
2533let isExtendable = 1;
2534let opExtendable = 2;
2535let isExtentSigned = 0;
2536let opExtentBits = 7;
2537let opExtentAlign = 0;
2538}
2539def A4_combineii : HInst<
2540(outs DoubleRegs:$Rdd32),
2541(ins s8_0Imm:$Ii, u32_0Imm:$II),
2542"$Rdd32 = combine(#$Ii,#$II)",
2543tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 {
2544let Inst{31-21} = 0b01111100100;
2545let isExtendable = 1;
2546let opExtendable = 2;
2547let isExtentSigned = 0;
2548let opExtentBits = 6;
2549let opExtentAlign = 0;
2550}
2551def A4_combineir : HInst<
2552(outs DoubleRegs:$Rdd32),
2553(ins s32_0Imm:$Ii, IntRegs:$Rs32),
2554"$Rdd32 = combine(#$Ii,$Rs32)",
2555tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2556let Inst{13-13} = 0b1;
2557let Inst{31-21} = 0b01110011001;
2558let isExtendable = 1;
2559let opExtendable = 1;
2560let isExtentSigned = 1;
2561let opExtentBits = 8;
2562let opExtentAlign = 0;
2563}
2564def A4_combineri : HInst<
2565(outs DoubleRegs:$Rdd32),
2566(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2567"$Rdd32 = combine($Rs32,#$Ii)",
2568tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2569let Inst{13-13} = 0b1;
2570let Inst{31-21} = 0b01110011000;
2571let isExtendable = 1;
2572let opExtendable = 2;
2573let isExtentSigned = 1;
2574let opExtentBits = 8;
2575let opExtentAlign = 0;
2576}
2577def A4_cround_ri : HInst<
2578(outs IntRegs:$Rd32),
2579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2580"$Rd32 = cround($Rs32,#$Ii)",
2581tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
2582let Inst{7-5} = 0b000;
2583let Inst{13-13} = 0b0;
2584let Inst{31-21} = 0b10001100111;
2585let hasNewValue = 1;
2586let opNewValue = 0;
2587let prefersSlot3 = 1;
2588}
2589def A4_cround_rr : HInst<
2590(outs IntRegs:$Rd32),
2591(ins IntRegs:$Rs32, IntRegs:$Rt32),
2592"$Rd32 = cround($Rs32,$Rt32)",
2593tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
2594let Inst{7-5} = 0b000;
2595let Inst{13-13} = 0b0;
2596let Inst{31-21} = 0b11000110110;
2597let hasNewValue = 1;
2598let opNewValue = 0;
2599let prefersSlot3 = 1;
2600}
2601def A4_ext : HInst<
2602(outs),
2603(ins u26_6Imm:$Ii),
2604"immext(#$Ii)",
2605tc_112d30d6, TypeEXTENDER>, Enc_2b518f {
2606let Inst{31-28} = 0b0000;
2607}
2608def A4_modwrapu : HInst<
2609(outs IntRegs:$Rd32),
2610(ins IntRegs:$Rs32, IntRegs:$Rt32),
2611"$Rd32 = modwrap($Rs32,$Rt32)",
2612tc_8a825db2, TypeALU64>, Enc_5ab2be {
2613let Inst{7-5} = 0b111;
2614let Inst{13-13} = 0b0;
2615let Inst{31-21} = 0b11010011111;
2616let hasNewValue = 1;
2617let opNewValue = 0;
2618let prefersSlot3 = 1;
2619}
2620def A4_orn : HInst<
2621(outs IntRegs:$Rd32),
2622(ins IntRegs:$Rt32, IntRegs:$Rs32),
2623"$Rd32 = or($Rt32,~$Rs32)",
2624tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2625let Inst{7-5} = 0b000;
2626let Inst{13-13} = 0b0;
2627let Inst{31-21} = 0b11110001101;
2628let hasNewValue = 1;
2629let opNewValue = 0;
2630let InputType = "reg";
2631}
2632def A4_ornp : HInst<
2633(outs DoubleRegs:$Rdd32),
2634(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2635"$Rdd32 = or($Rtt32,~$Rss32)",
2636tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2637let Inst{7-5} = 0b011;
2638let Inst{13-13} = 0b0;
2639let Inst{31-21} = 0b11010011111;
2640}
2641def A4_paslhf : HInst<
2642(outs IntRegs:$Rd32),
2643(ins PredRegs:$Pu4, IntRegs:$Rs32),
2644"if (!$Pu4) $Rd32 = aslh($Rs32)",
2645tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2646let Inst{7-5} = 0b000;
2647let Inst{13-10} = 0b1010;
2648let Inst{31-21} = 0b01110000000;
2649let isPredicated = 1;
2650let isPredicatedFalse = 1;
2651let hasNewValue = 1;
2652let opNewValue = 0;
2653let BaseOpcode = "A2_aslh";
2654}
2655def A4_paslhfnew : HInst<
2656(outs IntRegs:$Rd32),
2657(ins PredRegs:$Pu4, IntRegs:$Rs32),
2658"if (!$Pu4.new) $Rd32 = aslh($Rs32)",
2659tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2660let Inst{7-5} = 0b000;
2661let Inst{13-10} = 0b1011;
2662let Inst{31-21} = 0b01110000000;
2663let isPredicated = 1;
2664let isPredicatedFalse = 1;
2665let hasNewValue = 1;
2666let opNewValue = 0;
2667let isPredicatedNew = 1;
2668let BaseOpcode = "A2_aslh";
2669}
2670def A4_paslht : HInst<
2671(outs IntRegs:$Rd32),
2672(ins PredRegs:$Pu4, IntRegs:$Rs32),
2673"if ($Pu4) $Rd32 = aslh($Rs32)",
2674tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2675let Inst{7-5} = 0b000;
2676let Inst{13-10} = 0b1000;
2677let Inst{31-21} = 0b01110000000;
2678let isPredicated = 1;
2679let hasNewValue = 1;
2680let opNewValue = 0;
2681let BaseOpcode = "A2_aslh";
2682}
2683def A4_paslhtnew : HInst<
2684(outs IntRegs:$Rd32),
2685(ins PredRegs:$Pu4, IntRegs:$Rs32),
2686"if ($Pu4.new) $Rd32 = aslh($Rs32)",
2687tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2688let Inst{7-5} = 0b000;
2689let Inst{13-10} = 0b1001;
2690let Inst{31-21} = 0b01110000000;
2691let isPredicated = 1;
2692let hasNewValue = 1;
2693let opNewValue = 0;
2694let isPredicatedNew = 1;
2695let BaseOpcode = "A2_aslh";
2696}
2697def A4_pasrhf : HInst<
2698(outs IntRegs:$Rd32),
2699(ins PredRegs:$Pu4, IntRegs:$Rs32),
2700"if (!$Pu4) $Rd32 = asrh($Rs32)",
2701tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2702let Inst{7-5} = 0b000;
2703let Inst{13-10} = 0b1010;
2704let Inst{31-21} = 0b01110000001;
2705let isPredicated = 1;
2706let isPredicatedFalse = 1;
2707let hasNewValue = 1;
2708let opNewValue = 0;
2709let BaseOpcode = "A2_asrh";
2710}
2711def A4_pasrhfnew : HInst<
2712(outs IntRegs:$Rd32),
2713(ins PredRegs:$Pu4, IntRegs:$Rs32),
2714"if (!$Pu4.new) $Rd32 = asrh($Rs32)",
2715tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2716let Inst{7-5} = 0b000;
2717let Inst{13-10} = 0b1011;
2718let Inst{31-21} = 0b01110000001;
2719let isPredicated = 1;
2720let isPredicatedFalse = 1;
2721let hasNewValue = 1;
2722let opNewValue = 0;
2723let isPredicatedNew = 1;
2724let BaseOpcode = "A2_asrh";
2725}
2726def A4_pasrht : HInst<
2727(outs IntRegs:$Rd32),
2728(ins PredRegs:$Pu4, IntRegs:$Rs32),
2729"if ($Pu4) $Rd32 = asrh($Rs32)",
2730tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2731let Inst{7-5} = 0b000;
2732let Inst{13-10} = 0b1000;
2733let Inst{31-21} = 0b01110000001;
2734let isPredicated = 1;
2735let hasNewValue = 1;
2736let opNewValue = 0;
2737let BaseOpcode = "A2_asrh";
2738}
2739def A4_pasrhtnew : HInst<
2740(outs IntRegs:$Rd32),
2741(ins PredRegs:$Pu4, IntRegs:$Rs32),
2742"if ($Pu4.new) $Rd32 = asrh($Rs32)",
2743tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2744let Inst{7-5} = 0b000;
2745let Inst{13-10} = 0b1001;
2746let Inst{31-21} = 0b01110000001;
2747let isPredicated = 1;
2748let hasNewValue = 1;
2749let opNewValue = 0;
2750let isPredicatedNew = 1;
2751let BaseOpcode = "A2_asrh";
2752}
2753def A4_psxtbf : HInst<
2754(outs IntRegs:$Rd32),
2755(ins PredRegs:$Pu4, IntRegs:$Rs32),
2756"if (!$Pu4) $Rd32 = sxtb($Rs32)",
2757tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2758let Inst{7-5} = 0b000;
2759let Inst{13-10} = 0b1010;
2760let Inst{31-21} = 0b01110000101;
2761let isPredicated = 1;
2762let isPredicatedFalse = 1;
2763let hasNewValue = 1;
2764let opNewValue = 0;
2765let BaseOpcode = "A2_sxtb";
2766}
2767def A4_psxtbfnew : HInst<
2768(outs IntRegs:$Rd32),
2769(ins PredRegs:$Pu4, IntRegs:$Rs32),
2770"if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
2771tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2772let Inst{7-5} = 0b000;
2773let Inst{13-10} = 0b1011;
2774let Inst{31-21} = 0b01110000101;
2775let isPredicated = 1;
2776let isPredicatedFalse = 1;
2777let hasNewValue = 1;
2778let opNewValue = 0;
2779let isPredicatedNew = 1;
2780let BaseOpcode = "A2_sxtb";
2781}
2782def A4_psxtbt : HInst<
2783(outs IntRegs:$Rd32),
2784(ins PredRegs:$Pu4, IntRegs:$Rs32),
2785"if ($Pu4) $Rd32 = sxtb($Rs32)",
2786tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2787let Inst{7-5} = 0b000;
2788let Inst{13-10} = 0b1000;
2789let Inst{31-21} = 0b01110000101;
2790let isPredicated = 1;
2791let hasNewValue = 1;
2792let opNewValue = 0;
2793let BaseOpcode = "A2_sxtb";
2794}
2795def A4_psxtbtnew : HInst<
2796(outs IntRegs:$Rd32),
2797(ins PredRegs:$Pu4, IntRegs:$Rs32),
2798"if ($Pu4.new) $Rd32 = sxtb($Rs32)",
2799tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2800let Inst{7-5} = 0b000;
2801let Inst{13-10} = 0b1001;
2802let Inst{31-21} = 0b01110000101;
2803let isPredicated = 1;
2804let hasNewValue = 1;
2805let opNewValue = 0;
2806let isPredicatedNew = 1;
2807let BaseOpcode = "A2_sxtb";
2808}
2809def A4_psxthf : HInst<
2810(outs IntRegs:$Rd32),
2811(ins PredRegs:$Pu4, IntRegs:$Rs32),
2812"if (!$Pu4) $Rd32 = sxth($Rs32)",
2813tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2814let Inst{7-5} = 0b000;
2815let Inst{13-10} = 0b1010;
2816let Inst{31-21} = 0b01110000111;
2817let isPredicated = 1;
2818let isPredicatedFalse = 1;
2819let hasNewValue = 1;
2820let opNewValue = 0;
2821let BaseOpcode = "A2_sxth";
2822}
2823def A4_psxthfnew : HInst<
2824(outs IntRegs:$Rd32),
2825(ins PredRegs:$Pu4, IntRegs:$Rs32),
2826"if (!$Pu4.new) $Rd32 = sxth($Rs32)",
2827tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2828let Inst{7-5} = 0b000;
2829let Inst{13-10} = 0b1011;
2830let Inst{31-21} = 0b01110000111;
2831let isPredicated = 1;
2832let isPredicatedFalse = 1;
2833let hasNewValue = 1;
2834let opNewValue = 0;
2835let isPredicatedNew = 1;
2836let BaseOpcode = "A2_sxth";
2837}
2838def A4_psxtht : HInst<
2839(outs IntRegs:$Rd32),
2840(ins PredRegs:$Pu4, IntRegs:$Rs32),
2841"if ($Pu4) $Rd32 = sxth($Rs32)",
2842tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2843let Inst{7-5} = 0b000;
2844let Inst{13-10} = 0b1000;
2845let Inst{31-21} = 0b01110000111;
2846let isPredicated = 1;
2847let hasNewValue = 1;
2848let opNewValue = 0;
2849let BaseOpcode = "A2_sxth";
2850}
2851def A4_psxthtnew : HInst<
2852(outs IntRegs:$Rd32),
2853(ins PredRegs:$Pu4, IntRegs:$Rs32),
2854"if ($Pu4.new) $Rd32 = sxth($Rs32)",
2855tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2856let Inst{7-5} = 0b000;
2857let Inst{13-10} = 0b1001;
2858let Inst{31-21} = 0b01110000111;
2859let isPredicated = 1;
2860let hasNewValue = 1;
2861let opNewValue = 0;
2862let isPredicatedNew = 1;
2863let BaseOpcode = "A2_sxth";
2864}
2865def A4_pzxtbf : HInst<
2866(outs IntRegs:$Rd32),
2867(ins PredRegs:$Pu4, IntRegs:$Rs32),
2868"if (!$Pu4) $Rd32 = zxtb($Rs32)",
2869tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2870let Inst{7-5} = 0b000;
2871let Inst{13-10} = 0b1010;
2872let Inst{31-21} = 0b01110000100;
2873let isPredicated = 1;
2874let isPredicatedFalse = 1;
2875let hasNewValue = 1;
2876let opNewValue = 0;
2877let BaseOpcode = "A2_zxtb";
2878}
2879def A4_pzxtbfnew : HInst<
2880(outs IntRegs:$Rd32),
2881(ins PredRegs:$Pu4, IntRegs:$Rs32),
2882"if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
2883tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2884let Inst{7-5} = 0b000;
2885let Inst{13-10} = 0b1011;
2886let Inst{31-21} = 0b01110000100;
2887let isPredicated = 1;
2888let isPredicatedFalse = 1;
2889let hasNewValue = 1;
2890let opNewValue = 0;
2891let isPredicatedNew = 1;
2892let BaseOpcode = "A2_zxtb";
2893}
2894def A4_pzxtbt : HInst<
2895(outs IntRegs:$Rd32),
2896(ins PredRegs:$Pu4, IntRegs:$Rs32),
2897"if ($Pu4) $Rd32 = zxtb($Rs32)",
2898tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2899let Inst{7-5} = 0b000;
2900let Inst{13-10} = 0b1000;
2901let Inst{31-21} = 0b01110000100;
2902let isPredicated = 1;
2903let hasNewValue = 1;
2904let opNewValue = 0;
2905let BaseOpcode = "A2_zxtb";
2906}
2907def A4_pzxtbtnew : HInst<
2908(outs IntRegs:$Rd32),
2909(ins PredRegs:$Pu4, IntRegs:$Rs32),
2910"if ($Pu4.new) $Rd32 = zxtb($Rs32)",
2911tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2912let Inst{7-5} = 0b000;
2913let Inst{13-10} = 0b1001;
2914let Inst{31-21} = 0b01110000100;
2915let isPredicated = 1;
2916let hasNewValue = 1;
2917let opNewValue = 0;
2918let isPredicatedNew = 1;
2919let BaseOpcode = "A2_zxtb";
2920}
2921def A4_pzxthf : HInst<
2922(outs IntRegs:$Rd32),
2923(ins PredRegs:$Pu4, IntRegs:$Rs32),
2924"if (!$Pu4) $Rd32 = zxth($Rs32)",
2925tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2926let Inst{7-5} = 0b000;
2927let Inst{13-10} = 0b1010;
2928let Inst{31-21} = 0b01110000110;
2929let isPredicated = 1;
2930let isPredicatedFalse = 1;
2931let hasNewValue = 1;
2932let opNewValue = 0;
2933let BaseOpcode = "A2_zxth";
2934}
2935def A4_pzxthfnew : HInst<
2936(outs IntRegs:$Rd32),
2937(ins PredRegs:$Pu4, IntRegs:$Rs32),
2938"if (!$Pu4.new) $Rd32 = zxth($Rs32)",
2939tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2940let Inst{7-5} = 0b000;
2941let Inst{13-10} = 0b1011;
2942let Inst{31-21} = 0b01110000110;
2943let isPredicated = 1;
2944let isPredicatedFalse = 1;
2945let hasNewValue = 1;
2946let opNewValue = 0;
2947let isPredicatedNew = 1;
2948let BaseOpcode = "A2_zxth";
2949}
2950def A4_pzxtht : HInst<
2951(outs IntRegs:$Rd32),
2952(ins PredRegs:$Pu4, IntRegs:$Rs32),
2953"if ($Pu4) $Rd32 = zxth($Rs32)",
2954tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2955let Inst{7-5} = 0b000;
2956let Inst{13-10} = 0b1000;
2957let Inst{31-21} = 0b01110000110;
2958let isPredicated = 1;
2959let hasNewValue = 1;
2960let opNewValue = 0;
2961let BaseOpcode = "A2_zxth";
2962}
2963def A4_pzxthtnew : HInst<
2964(outs IntRegs:$Rd32),
2965(ins PredRegs:$Pu4, IntRegs:$Rs32),
2966"if ($Pu4.new) $Rd32 = zxth($Rs32)",
2967tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2968let Inst{7-5} = 0b000;
2969let Inst{13-10} = 0b1001;
2970let Inst{31-21} = 0b01110000110;
2971let isPredicated = 1;
2972let hasNewValue = 1;
2973let opNewValue = 0;
2974let isPredicatedNew = 1;
2975let BaseOpcode = "A2_zxth";
2976}
2977def A4_rcmpeq : HInst<
2978(outs IntRegs:$Rd32),
2979(ins IntRegs:$Rs32, IntRegs:$Rt32),
2980"$Rd32 = cmp.eq($Rs32,$Rt32)",
2981tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
2982let Inst{7-5} = 0b000;
2983let Inst{13-13} = 0b0;
2984let Inst{31-21} = 0b11110011010;
2985let hasNewValue = 1;
2986let opNewValue = 0;
2987let CextOpcode = "A4_rcmpeq";
2988let InputType = "reg";
2989let isCommutable = 1;
2990}
2991def A4_rcmpeqi : HInst<
2992(outs IntRegs:$Rd32),
2993(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2994"$Rd32 = cmp.eq($Rs32,#$Ii)",
2995tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
2996let Inst{13-13} = 0b1;
2997let Inst{31-21} = 0b01110011010;
2998let hasNewValue = 1;
2999let opNewValue = 0;
3000let CextOpcode = "A4_rcmpeqi";
3001let InputType = "imm";
3002let isExtendable = 1;
3003let opExtendable = 2;
3004let isExtentSigned = 1;
3005let opExtentBits = 8;
3006let opExtentAlign = 0;
3007}
3008def A4_rcmpneq : HInst<
3009(outs IntRegs:$Rd32),
3010(ins IntRegs:$Rs32, IntRegs:$Rt32),
3011"$Rd32 = !cmp.eq($Rs32,$Rt32)",
3012tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
3013let Inst{7-5} = 0b000;
3014let Inst{13-13} = 0b0;
3015let Inst{31-21} = 0b11110011011;
3016let hasNewValue = 1;
3017let opNewValue = 0;
3018let CextOpcode = "A4_rcmpneq";
3019let InputType = "reg";
3020let isCommutable = 1;
3021}
3022def A4_rcmpneqi : HInst<
3023(outs IntRegs:$Rd32),
3024(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3025"$Rd32 = !cmp.eq($Rs32,#$Ii)",
3026tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
3027let Inst{13-13} = 0b1;
3028let Inst{31-21} = 0b01110011011;
3029let hasNewValue = 1;
3030let opNewValue = 0;
3031let CextOpcode = "A4_rcmpeqi";
3032let InputType = "imm";
3033let isExtendable = 1;
3034let opExtendable = 2;
3035let isExtentSigned = 1;
3036let opExtentBits = 8;
3037let opExtentAlign = 0;
3038}
3039def A4_round_ri : HInst<
3040(outs IntRegs:$Rd32),
3041(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3042"$Rd32 = round($Rs32,#$Ii)",
3043tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3044let Inst{7-5} = 0b100;
3045let Inst{13-13} = 0b0;
3046let Inst{31-21} = 0b10001100111;
3047let hasNewValue = 1;
3048let opNewValue = 0;
3049let prefersSlot3 = 1;
3050}
3051def A4_round_ri_sat : HInst<
3052(outs IntRegs:$Rd32),
3053(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3054"$Rd32 = round($Rs32,#$Ii):sat",
3055tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3056let Inst{7-5} = 0b110;
3057let Inst{13-13} = 0b0;
3058let Inst{31-21} = 0b10001100111;
3059let hasNewValue = 1;
3060let opNewValue = 0;
3061let prefersSlot3 = 1;
3062let Defs = [USR_OVF];
3063}
3064def A4_round_rr : HInst<
3065(outs IntRegs:$Rd32),
3066(ins IntRegs:$Rs32, IntRegs:$Rt32),
3067"$Rd32 = round($Rs32,$Rt32)",
3068tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3069let Inst{7-5} = 0b100;
3070let Inst{13-13} = 0b0;
3071let Inst{31-21} = 0b11000110110;
3072let hasNewValue = 1;
3073let opNewValue = 0;
3074let prefersSlot3 = 1;
3075}
3076def A4_round_rr_sat : HInst<
3077(outs IntRegs:$Rd32),
3078(ins IntRegs:$Rs32, IntRegs:$Rt32),
3079"$Rd32 = round($Rs32,$Rt32):sat",
3080tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3081let Inst{7-5} = 0b110;
3082let Inst{13-13} = 0b0;
3083let Inst{31-21} = 0b11000110110;
3084let hasNewValue = 1;
3085let opNewValue = 0;
3086let prefersSlot3 = 1;
3087let Defs = [USR_OVF];
3088}
3089def A4_subp_c : HInst<
3090(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
3091(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
3092"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
3093tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
3094let Inst{7-7} = 0b0;
3095let Inst{13-13} = 0b0;
3096let Inst{31-21} = 0b11000010111;
3097let isPredicateLate = 1;
3098let Constraints = "$Px4 = $Px4in";
3099}
3100def A4_tfrcpp : HInst<
3101(outs DoubleRegs:$Rdd32),
3102(ins CtrRegs64:$Css32),
3103"$Rdd32 = $Css32",
3104tc_7476d766, TypeCR>, Enc_667b39 {
3105let Inst{13-5} = 0b000000000;
3106let Inst{31-21} = 0b01101000000;
3107}
3108def A4_tfrpcp : HInst<
3109(outs CtrRegs64:$Cdd32),
3110(ins DoubleRegs:$Rss32),
3111"$Cdd32 = $Rss32",
3112tc_49fdfd4b, TypeCR>, Enc_0ed752 {
3113let Inst{13-5} = 0b000000000;
3114let Inst{31-21} = 0b01100011001;
3115}
3116def A4_tlbmatch : HInst<
3117(outs PredRegs:$Pd4),
3118(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3119"$Pd4 = tlbmatch($Rss32,$Rt32)",
3120tc_d68dca5c, TypeALU64>, Enc_03833b {
3121let Inst{7-2} = 0b011000;
3122let Inst{13-13} = 0b1;
3123let Inst{31-21} = 0b11010010000;
3124let isPredicateLate = 1;
3125}
3126def A4_vcmpbeq_any : HInst<
3127(outs PredRegs:$Pd4),
3128(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3129"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
3130tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3131let Inst{7-2} = 0b000000;
3132let Inst{13-13} = 0b1;
3133let Inst{31-21} = 0b11010010000;
3134}
3135def A4_vcmpbeqi : HInst<
3136(outs PredRegs:$Pd4),
3137(ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
3138"$Pd4 = vcmpb.eq($Rss32,#$Ii)",
3139tc_a1297125, TypeALU64>, Enc_0d8adb {
3140let Inst{4-2} = 0b000;
3141let Inst{13-13} = 0b0;
3142let Inst{31-21} = 0b11011100000;
3143}
3144def A4_vcmpbgt : HInst<
3145(outs PredRegs:$Pd4),
3146(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3147"$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
3148tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3149let Inst{7-2} = 0b010000;
3150let Inst{13-13} = 0b1;
3151let Inst{31-21} = 0b11010010000;
3152}
3153def A4_vcmpbgti : HInst<
3154(outs PredRegs:$Pd4),
3155(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3156"$Pd4 = vcmpb.gt($Rss32,#$Ii)",
3157tc_a1297125, TypeALU64>, Enc_0d8adb {
3158let Inst{4-2} = 0b000;
3159let Inst{13-13} = 0b0;
3160let Inst{31-21} = 0b11011100001;
3161}
3162def A4_vcmpbgtui : HInst<
3163(outs PredRegs:$Pd4),
3164(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3165"$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
3166tc_a1297125, TypeALU64>, Enc_3680c2 {
3167let Inst{4-2} = 0b000;
3168let Inst{13-12} = 0b00;
3169let Inst{31-21} = 0b11011100010;
3170}
3171def A4_vcmpheqi : HInst<
3172(outs PredRegs:$Pd4),
3173(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3174"$Pd4 = vcmph.eq($Rss32,#$Ii)",
3175tc_a1297125, TypeALU64>, Enc_0d8adb {
3176let Inst{4-2} = 0b010;
3177let Inst{13-13} = 0b0;
3178let Inst{31-21} = 0b11011100000;
3179}
3180def A4_vcmphgti : HInst<
3181(outs PredRegs:$Pd4),
3182(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3183"$Pd4 = vcmph.gt($Rss32,#$Ii)",
3184tc_a1297125, TypeALU64>, Enc_0d8adb {
3185let Inst{4-2} = 0b010;
3186let Inst{13-13} = 0b0;
3187let Inst{31-21} = 0b11011100001;
3188}
3189def A4_vcmphgtui : HInst<
3190(outs PredRegs:$Pd4),
3191(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3192"$Pd4 = vcmph.gtu($Rss32,#$Ii)",
3193tc_a1297125, TypeALU64>, Enc_3680c2 {
3194let Inst{4-2} = 0b010;
3195let Inst{13-12} = 0b00;
3196let Inst{31-21} = 0b11011100010;
3197}
3198def A4_vcmpweqi : HInst<
3199(outs PredRegs:$Pd4),
3200(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3201"$Pd4 = vcmpw.eq($Rss32,#$Ii)",
3202tc_a1297125, TypeALU64>, Enc_0d8adb {
3203let Inst{4-2} = 0b100;
3204let Inst{13-13} = 0b0;
3205let Inst{31-21} = 0b11011100000;
3206}
3207def A4_vcmpwgti : HInst<
3208(outs PredRegs:$Pd4),
3209(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3210"$Pd4 = vcmpw.gt($Rss32,#$Ii)",
3211tc_a1297125, TypeALU64>, Enc_0d8adb {
3212let Inst{4-2} = 0b100;
3213let Inst{13-13} = 0b0;
3214let Inst{31-21} = 0b11011100001;
3215}
3216def A4_vcmpwgtui : HInst<
3217(outs PredRegs:$Pd4),
3218(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3219"$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
3220tc_a1297125, TypeALU64>, Enc_3680c2 {
3221let Inst{4-2} = 0b100;
3222let Inst{13-12} = 0b00;
3223let Inst{31-21} = 0b11011100010;
3224}
3225def A4_vrmaxh : HInst<
3226(outs DoubleRegs:$Rxx32),
3227(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3228"$Rxx32 = vrmaxh($Rss32,$Ru32)",
3229tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3230let Inst{7-5} = 0b001;
3231let Inst{13-13} = 0b0;
3232let Inst{31-21} = 0b11001011001;
3233let prefersSlot3 = 1;
3234let Constraints = "$Rxx32 = $Rxx32in";
3235}
3236def A4_vrmaxuh : HInst<
3237(outs DoubleRegs:$Rxx32),
3238(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3239"$Rxx32 = vrmaxuh($Rss32,$Ru32)",
3240tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3241let Inst{7-5} = 0b001;
3242let Inst{13-13} = 0b1;
3243let Inst{31-21} = 0b11001011001;
3244let prefersSlot3 = 1;
3245let Constraints = "$Rxx32 = $Rxx32in";
3246}
3247def A4_vrmaxuw : HInst<
3248(outs DoubleRegs:$Rxx32),
3249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3250"$Rxx32 = vrmaxuw($Rss32,$Ru32)",
3251tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3252let Inst{7-5} = 0b010;
3253let Inst{13-13} = 0b1;
3254let Inst{31-21} = 0b11001011001;
3255let prefersSlot3 = 1;
3256let Constraints = "$Rxx32 = $Rxx32in";
3257}
3258def A4_vrmaxw : HInst<
3259(outs DoubleRegs:$Rxx32),
3260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3261"$Rxx32 = vrmaxw($Rss32,$Ru32)",
3262tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3263let Inst{7-5} = 0b010;
3264let Inst{13-13} = 0b0;
3265let Inst{31-21} = 0b11001011001;
3266let prefersSlot3 = 1;
3267let Constraints = "$Rxx32 = $Rxx32in";
3268}
3269def A4_vrminh : HInst<
3270(outs DoubleRegs:$Rxx32),
3271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3272"$Rxx32 = vrminh($Rss32,$Ru32)",
3273tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3274let Inst{7-5} = 0b101;
3275let Inst{13-13} = 0b0;
3276let Inst{31-21} = 0b11001011001;
3277let prefersSlot3 = 1;
3278let Constraints = "$Rxx32 = $Rxx32in";
3279}
3280def A4_vrminuh : HInst<
3281(outs DoubleRegs:$Rxx32),
3282(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3283"$Rxx32 = vrminuh($Rss32,$Ru32)",
3284tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3285let Inst{7-5} = 0b101;
3286let Inst{13-13} = 0b1;
3287let Inst{31-21} = 0b11001011001;
3288let prefersSlot3 = 1;
3289let Constraints = "$Rxx32 = $Rxx32in";
3290}
3291def A4_vrminuw : HInst<
3292(outs DoubleRegs:$Rxx32),
3293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3294"$Rxx32 = vrminuw($Rss32,$Ru32)",
3295tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3296let Inst{7-5} = 0b110;
3297let Inst{13-13} = 0b1;
3298let Inst{31-21} = 0b11001011001;
3299let prefersSlot3 = 1;
3300let Constraints = "$Rxx32 = $Rxx32in";
3301}
3302def A4_vrminw : HInst<
3303(outs DoubleRegs:$Rxx32),
3304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3305"$Rxx32 = vrminw($Rss32,$Ru32)",
3306tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3307let Inst{7-5} = 0b110;
3308let Inst{13-13} = 0b0;
3309let Inst{31-21} = 0b11001011001;
3310let prefersSlot3 = 1;
3311let Constraints = "$Rxx32 = $Rxx32in";
3312}
3313def A5_ACS : HInst<
3314(outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
3315(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3316"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
3317tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> {
3318let Inst{7-7} = 0b0;
3319let Inst{13-13} = 0b0;
3320let Inst{31-21} = 0b11101010101;
3321let isPredicateLate = 1;
3322let prefersSlot3 = 1;
3323let Defs = [USR_OVF];
3324let Constraints = "$Rxx32 = $Rxx32in";
3325}
3326def A5_vaddhubs : HInst<
3327(outs IntRegs:$Rd32),
3328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3329"$Rd32 = vaddhub($Rss32,$Rtt32):sat",
3330tc_0dfac0a7, TypeS_3op>, Enc_d2216a {
3331let Inst{7-5} = 0b001;
3332let Inst{13-13} = 0b0;
3333let Inst{31-21} = 0b11000001010;
3334let hasNewValue = 1;
3335let opNewValue = 0;
3336let prefersSlot3 = 1;
3337let Defs = [USR_OVF];
3338}
3339def A6_vcmpbeq_notany : HInst<
3340(outs PredRegs:$Pd4),
3341(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3342"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
3343tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> {
3344let Inst{7-2} = 0b001000;
3345let Inst{13-13} = 0b1;
3346let Inst{31-21} = 0b11010010000;
3347}
3348def A6_vminub_RdP : HInst<
3349(outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
3350(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
3351"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
3352tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> {
3353let Inst{7-7} = 0b0;
3354let Inst{13-13} = 0b0;
3355let Inst{31-21} = 0b11101010111;
3356let isPredicateLate = 1;
3357let prefersSlot3 = 1;
3358}
3359def A7_clip : HInst<
3360(outs IntRegs:$Rd32),
3361(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3362"$Rd32 = clip($Rs32,#$Ii)",
3363tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> {
3364let Inst{7-5} = 0b101;
3365let Inst{13-13} = 0b0;
3366let Inst{31-21} = 0b10001000110;
3367let hasNewValue = 1;
3368let opNewValue = 0;
3369}
3370def A7_croundd_ri : HInst<
3371(outs DoubleRegs:$Rdd32),
3372(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
3373"$Rdd32 = cround($Rss32,#$Ii)",
3374tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> {
3375let Inst{7-5} = 0b010;
3376let Inst{31-21} = 0b10001100111;
3377let prefersSlot3 = 1;
3378}
3379def A7_croundd_rr : HInst<
3380(outs DoubleRegs:$Rdd32),
3381(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3382"$Rdd32 = cround($Rss32,$Rt32)",
3383tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> {
3384let Inst{7-5} = 0b010;
3385let Inst{13-13} = 0b0;
3386let Inst{31-21} = 0b11000110110;
3387let prefersSlot3 = 1;
3388}
3389def A7_vclip : HInst<
3390(outs DoubleRegs:$Rdd32),
3391(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
3392"$Rdd32 = vclip($Rss32,#$Ii)",
3393tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> {
3394let Inst{7-5} = 0b110;
3395let Inst{13-13} = 0b0;
3396let Inst{31-21} = 0b10001000110;
3397}
3398def C2_all8 : HInst<
3399(outs PredRegs:$Pd4),
3400(ins PredRegs:$Ps4),
3401"$Pd4 = all8($Ps4)",
3402tc_151bf368, TypeCR>, Enc_65d691 {
3403let Inst{13-2} = 0b000000000000;
3404let Inst{31-18} = 0b01101011101000;
3405}
3406def C2_and : HInst<
3407(outs PredRegs:$Pd4),
3408(ins PredRegs:$Pt4, PredRegs:$Ps4),
3409"$Pd4 = and($Pt4,$Ps4)",
3410tc_651cbe02, TypeCR>, Enc_454a26 {
3411let Inst{7-2} = 0b000000;
3412let Inst{13-10} = 0b0000;
3413let Inst{31-18} = 0b01101011000000;
3414}
3415def C2_andn : HInst<
3416(outs PredRegs:$Pd4),
3417(ins PredRegs:$Pt4, PredRegs:$Ps4),
3418"$Pd4 = and($Pt4,!$Ps4)",
3419tc_651cbe02, TypeCR>, Enc_454a26 {
3420let Inst{7-2} = 0b000000;
3421let Inst{13-10} = 0b0000;
3422let Inst{31-18} = 0b01101011011000;
3423}
3424def C2_any8 : HInst<
3425(outs PredRegs:$Pd4),
3426(ins PredRegs:$Ps4),
3427"$Pd4 = any8($Ps4)",
3428tc_151bf368, TypeCR>, Enc_65d691 {
3429let Inst{13-2} = 0b000000000000;
3430let Inst{31-18} = 0b01101011100000;
3431}
3432def C2_bitsclr : HInst<
3433(outs PredRegs:$Pd4),
3434(ins IntRegs:$Rs32, IntRegs:$Rt32),
3435"$Pd4 = bitsclr($Rs32,$Rt32)",
3436tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3437let Inst{7-2} = 0b000000;
3438let Inst{13-13} = 0b0;
3439let Inst{31-21} = 0b11000111100;
3440}
3441def C2_bitsclri : HInst<
3442(outs PredRegs:$Pd4),
3443(ins IntRegs:$Rs32, u6_0Imm:$Ii),
3444"$Pd4 = bitsclr($Rs32,#$Ii)",
3445tc_a1297125, TypeS_2op>, Enc_5d6c34 {
3446let Inst{7-2} = 0b000000;
3447let Inst{31-21} = 0b10000101100;
3448}
3449def C2_bitsset : HInst<
3450(outs PredRegs:$Pd4),
3451(ins IntRegs:$Rs32, IntRegs:$Rt32),
3452"$Pd4 = bitsset($Rs32,$Rt32)",
3453tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3454let Inst{7-2} = 0b000000;
3455let Inst{13-13} = 0b0;
3456let Inst{31-21} = 0b11000111010;
3457}
3458def C2_ccombinewf : HInst<
3459(outs DoubleRegs:$Rdd32),
3460(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3461"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3462tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3463let Inst{7-7} = 0b1;
3464let Inst{13-13} = 0b0;
3465let Inst{31-21} = 0b11111101000;
3466let isPredicated = 1;
3467let isPredicatedFalse = 1;
3468let BaseOpcode = "A2_combinew";
3469}
3470def C2_ccombinewnewf : HInst<
3471(outs DoubleRegs:$Rdd32),
3472(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3473"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3474tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3475let Inst{7-7} = 0b1;
3476let Inst{13-13} = 0b1;
3477let Inst{31-21} = 0b11111101000;
3478let isPredicated = 1;
3479let isPredicatedFalse = 1;
3480let isPredicatedNew = 1;
3481let BaseOpcode = "A2_combinew";
3482}
3483def C2_ccombinewnewt : HInst<
3484(outs DoubleRegs:$Rdd32),
3485(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3486"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3487tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3488let Inst{7-7} = 0b0;
3489let Inst{13-13} = 0b1;
3490let Inst{31-21} = 0b11111101000;
3491let isPredicated = 1;
3492let isPredicatedNew = 1;
3493let BaseOpcode = "A2_combinew";
3494}
3495def C2_ccombinewt : HInst<
3496(outs DoubleRegs:$Rdd32),
3497(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3498"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3499tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3500let Inst{7-7} = 0b0;
3501let Inst{13-13} = 0b0;
3502let Inst{31-21} = 0b11111101000;
3503let isPredicated = 1;
3504let BaseOpcode = "A2_combinew";
3505}
3506def C2_cmoveif : HInst<
3507(outs IntRegs:$Rd32),
3508(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3509"if (!$Pu4) $Rd32 = #$Ii",
3510tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3511let Inst{13-13} = 0b0;
3512let Inst{20-20} = 0b0;
3513let Inst{31-23} = 0b011111101;
3514let isPredicated = 1;
3515let isPredicatedFalse = 1;
3516let hasNewValue = 1;
3517let opNewValue = 0;
3518let BaseOpcode = "A2_tfrsi";
3519let CextOpcode = "A2_tfr";
3520let InputType = "imm";
3521let isMoveImm = 1;
3522let isExtendable = 1;
3523let opExtendable = 2;
3524let isExtentSigned = 1;
3525let opExtentBits = 12;
3526let opExtentAlign = 0;
3527}
3528def C2_cmoveit : HInst<
3529(outs IntRegs:$Rd32),
3530(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3531"if ($Pu4) $Rd32 = #$Ii",
3532tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3533let Inst{13-13} = 0b0;
3534let Inst{20-20} = 0b0;
3535let Inst{31-23} = 0b011111100;
3536let isPredicated = 1;
3537let hasNewValue = 1;
3538let opNewValue = 0;
3539let BaseOpcode = "A2_tfrsi";
3540let CextOpcode = "A2_tfr";
3541let InputType = "imm";
3542let isMoveImm = 1;
3543let isExtendable = 1;
3544let opExtendable = 2;
3545let isExtentSigned = 1;
3546let opExtentBits = 12;
3547let opExtentAlign = 0;
3548}
3549def C2_cmovenewif : HInst<
3550(outs IntRegs:$Rd32),
3551(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3552"if (!$Pu4.new) $Rd32 = #$Ii",
3553tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3554let Inst{13-13} = 0b1;
3555let Inst{20-20} = 0b0;
3556let Inst{31-23} = 0b011111101;
3557let isPredicated = 1;
3558let isPredicatedFalse = 1;
3559let hasNewValue = 1;
3560let opNewValue = 0;
3561let isPredicatedNew = 1;
3562let BaseOpcode = "A2_tfrsi";
3563let CextOpcode = "A2_tfr";
3564let InputType = "imm";
3565let isMoveImm = 1;
3566let isExtendable = 1;
3567let opExtendable = 2;
3568let isExtentSigned = 1;
3569let opExtentBits = 12;
3570let opExtentAlign = 0;
3571}
3572def C2_cmovenewit : HInst<
3573(outs IntRegs:$Rd32),
3574(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3575"if ($Pu4.new) $Rd32 = #$Ii",
3576tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3577let Inst{13-13} = 0b1;
3578let Inst{20-20} = 0b0;
3579let Inst{31-23} = 0b011111100;
3580let isPredicated = 1;
3581let hasNewValue = 1;
3582let opNewValue = 0;
3583let isPredicatedNew = 1;
3584let BaseOpcode = "A2_tfrsi";
3585let CextOpcode = "A2_tfr";
3586let InputType = "imm";
3587let isMoveImm = 1;
3588let isExtendable = 1;
3589let opExtendable = 2;
3590let isExtentSigned = 1;
3591let opExtentBits = 12;
3592let opExtentAlign = 0;
3593}
3594def C2_cmpeq : HInst<
3595(outs PredRegs:$Pd4),
3596(ins IntRegs:$Rs32, IntRegs:$Rt32),
3597"$Pd4 = cmp.eq($Rs32,$Rt32)",
3598tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3599let Inst{7-2} = 0b000000;
3600let Inst{13-13} = 0b0;
3601let Inst{31-21} = 0b11110010000;
3602let CextOpcode = "C2_cmpeq";
3603let InputType = "reg";
3604let isCommutable = 1;
3605let isCompare = 1;
3606}
3607def C2_cmpeqi : HInst<
3608(outs PredRegs:$Pd4),
3609(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3610"$Pd4 = cmp.eq($Rs32,#$Ii)",
3611tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3612let Inst{4-2} = 0b000;
3613let Inst{31-22} = 0b0111010100;
3614let CextOpcode = "C2_cmpeq";
3615let InputType = "imm";
3616let isCompare = 1;
3617let isExtendable = 1;
3618let opExtendable = 2;
3619let isExtentSigned = 1;
3620let opExtentBits = 10;
3621let opExtentAlign = 0;
3622}
3623def C2_cmpeqp : HInst<
3624(outs PredRegs:$Pd4),
3625(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3626"$Pd4 = cmp.eq($Rss32,$Rtt32)",
3627tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3628let Inst{7-2} = 0b000000;
3629let Inst{13-13} = 0b0;
3630let Inst{31-21} = 0b11010010100;
3631let isCommutable = 1;
3632let isCompare = 1;
3633}
3634def C2_cmpgei : HInst<
3635(outs PredRegs:$Pd4),
3636(ins IntRegs:$Rs32, s8_0Imm:$Ii),
3637"$Pd4 = cmp.ge($Rs32,#$Ii)",
3638tc_d33e5eee, TypeALU32_2op> {
3639let isCompare = 1;
3640let isPseudo = 1;
3641}
3642def C2_cmpgeui : HInst<
3643(outs PredRegs:$Pd4),
3644(ins IntRegs:$Rs32, u8_0Imm:$Ii),
3645"$Pd4 = cmp.geu($Rs32,#$Ii)",
3646tc_d33e5eee, TypeALU32_2op> {
3647let isCompare = 1;
3648let isPseudo = 1;
3649}
3650def C2_cmpgt : HInst<
3651(outs PredRegs:$Pd4),
3652(ins IntRegs:$Rs32, IntRegs:$Rt32),
3653"$Pd4 = cmp.gt($Rs32,$Rt32)",
3654tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3655let Inst{7-2} = 0b000000;
3656let Inst{13-13} = 0b0;
3657let Inst{31-21} = 0b11110010010;
3658let CextOpcode = "C2_cmpgt";
3659let InputType = "reg";
3660let isCompare = 1;
3661}
3662def C2_cmpgti : HInst<
3663(outs PredRegs:$Pd4),
3664(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3665"$Pd4 = cmp.gt($Rs32,#$Ii)",
3666tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3667let Inst{4-2} = 0b000;
3668let Inst{31-22} = 0b0111010101;
3669let CextOpcode = "C2_cmpgt";
3670let InputType = "imm";
3671let isCompare = 1;
3672let isExtendable = 1;
3673let opExtendable = 2;
3674let isExtentSigned = 1;
3675let opExtentBits = 10;
3676let opExtentAlign = 0;
3677}
3678def C2_cmpgtp : HInst<
3679(outs PredRegs:$Pd4),
3680(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3681"$Pd4 = cmp.gt($Rss32,$Rtt32)",
3682tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3683let Inst{7-2} = 0b010000;
3684let Inst{13-13} = 0b0;
3685let Inst{31-21} = 0b11010010100;
3686let isCompare = 1;
3687}
3688def C2_cmpgtu : HInst<
3689(outs PredRegs:$Pd4),
3690(ins IntRegs:$Rs32, IntRegs:$Rt32),
3691"$Pd4 = cmp.gtu($Rs32,$Rt32)",
3692tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3693let Inst{7-2} = 0b000000;
3694let Inst{13-13} = 0b0;
3695let Inst{31-21} = 0b11110010011;
3696let CextOpcode = "C2_cmpgtu";
3697let InputType = "reg";
3698let isCompare = 1;
3699}
3700def C2_cmpgtui : HInst<
3701(outs PredRegs:$Pd4),
3702(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3703"$Pd4 = cmp.gtu($Rs32,#$Ii)",
3704tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3705let Inst{4-2} = 0b000;
3706let Inst{31-21} = 0b01110101100;
3707let CextOpcode = "C2_cmpgtu";
3708let InputType = "imm";
3709let isCompare = 1;
3710let isExtendable = 1;
3711let opExtendable = 2;
3712let isExtentSigned = 0;
3713let opExtentBits = 9;
3714let opExtentAlign = 0;
3715}
3716def C2_cmpgtup : HInst<
3717(outs PredRegs:$Pd4),
3718(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3719"$Pd4 = cmp.gtu($Rss32,$Rtt32)",
3720tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3721let Inst{7-2} = 0b100000;
3722let Inst{13-13} = 0b0;
3723let Inst{31-21} = 0b11010010100;
3724let isCompare = 1;
3725}
3726def C2_cmplt : HInst<
3727(outs PredRegs:$Pd4),
3728(ins IntRegs:$Rs32, IntRegs:$Rt32),
3729"$Pd4 = cmp.lt($Rs32,$Rt32)",
3730tc_d33e5eee, TypeALU32_3op> {
3731let isCompare = 1;
3732let isPseudo = 1;
3733let isCodeGenOnly = 1;
3734}
3735def C2_cmpltu : HInst<
3736(outs PredRegs:$Pd4),
3737(ins IntRegs:$Rs32, IntRegs:$Rt32),
3738"$Pd4 = cmp.ltu($Rs32,$Rt32)",
3739tc_d33e5eee, TypeALU32_3op> {
3740let isCompare = 1;
3741let isPseudo = 1;
3742let isCodeGenOnly = 1;
3743}
3744def C2_mask : HInst<
3745(outs DoubleRegs:$Rdd32),
3746(ins PredRegs:$Pt4),
3747"$Rdd32 = mask($Pt4)",
3748tc_9f6cd987, TypeS_2op>, Enc_78e566 {
3749let Inst{7-5} = 0b000;
3750let Inst{13-10} = 0b0000;
3751let Inst{31-16} = 0b1000011000000000;
3752}
3753def C2_mux : HInst<
3754(outs IntRegs:$Rd32),
3755(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3756"$Rd32 = mux($Pu4,$Rs32,$Rt32)",
3757tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 {
3758let Inst{7-7} = 0b0;
3759let Inst{13-13} = 0b0;
3760let Inst{31-21} = 0b11110100000;
3761let hasNewValue = 1;
3762let opNewValue = 0;
3763let InputType = "reg";
3764}
3765def C2_muxii : HInst<
3766(outs IntRegs:$Rd32),
3767(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
3768"$Rd32 = mux($Pu4,#$Ii,#$II)",
3769tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d {
3770let Inst{31-25} = 0b0111101;
3771let hasNewValue = 1;
3772let opNewValue = 0;
3773let isExtendable = 1;
3774let opExtendable = 2;
3775let isExtentSigned = 1;
3776let opExtentBits = 8;
3777let opExtentAlign = 0;
3778}
3779def C2_muxir : HInst<
3780(outs IntRegs:$Rd32),
3781(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
3782"$Rd32 = mux($Pu4,$Rs32,#$Ii)",
3783tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3784let Inst{13-13} = 0b0;
3785let Inst{31-23} = 0b011100110;
3786let hasNewValue = 1;
3787let opNewValue = 0;
3788let InputType = "imm";
3789let isExtendable = 1;
3790let opExtendable = 3;
3791let isExtentSigned = 1;
3792let opExtentBits = 8;
3793let opExtentAlign = 0;
3794}
3795def C2_muxri : HInst<
3796(outs IntRegs:$Rd32),
3797(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
3798"$Rd32 = mux($Pu4,#$Ii,$Rs32)",
3799tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3800let Inst{13-13} = 0b0;
3801let Inst{31-23} = 0b011100111;
3802let hasNewValue = 1;
3803let opNewValue = 0;
3804let InputType = "imm";
3805let isExtendable = 1;
3806let opExtendable = 2;
3807let isExtentSigned = 1;
3808let opExtentBits = 8;
3809let opExtentAlign = 0;
3810}
3811def C2_not : HInst<
3812(outs PredRegs:$Pd4),
3813(ins PredRegs:$Ps4),
3814"$Pd4 = not($Ps4)",
3815tc_151bf368, TypeCR>, Enc_65d691 {
3816let Inst{13-2} = 0b000000000000;
3817let Inst{31-18} = 0b01101011110000;
3818}
3819def C2_or : HInst<
3820(outs PredRegs:$Pd4),
3821(ins PredRegs:$Pt4, PredRegs:$Ps4),
3822"$Pd4 = or($Pt4,$Ps4)",
3823tc_651cbe02, TypeCR>, Enc_454a26 {
3824let Inst{7-2} = 0b000000;
3825let Inst{13-10} = 0b0000;
3826let Inst{31-18} = 0b01101011001000;
3827}
3828def C2_orn : HInst<
3829(outs PredRegs:$Pd4),
3830(ins PredRegs:$Pt4, PredRegs:$Ps4),
3831"$Pd4 = or($Pt4,!$Ps4)",
3832tc_651cbe02, TypeCR>, Enc_454a26 {
3833let Inst{7-2} = 0b000000;
3834let Inst{13-10} = 0b0000;
3835let Inst{31-18} = 0b01101011111000;
3836}
3837def C2_pxfer_map : HInst<
3838(outs PredRegs:$Pd4),
3839(ins PredRegs:$Ps4),
3840"$Pd4 = $Ps4",
3841tc_651cbe02, TypeMAPPING> {
3842let isPseudo = 1;
3843let isCodeGenOnly = 1;
3844}
3845def C2_tfrpr : HInst<
3846(outs IntRegs:$Rd32),
3847(ins PredRegs:$Ps4),
3848"$Rd32 = $Ps4",
3849tc_9f6cd987, TypeS_2op>, Enc_f5e933 {
3850let Inst{13-5} = 0b000000000;
3851let Inst{31-18} = 0b10001001010000;
3852let hasNewValue = 1;
3853let opNewValue = 0;
3854}
3855def C2_tfrrp : HInst<
3856(outs PredRegs:$Pd4),
3857(ins IntRegs:$Rs32),
3858"$Pd4 = $Rs32",
3859tc_55b33fda, TypeS_2op>, Enc_48b75f {
3860let Inst{13-2} = 0b000000000000;
3861let Inst{31-21} = 0b10000101010;
3862}
3863def C2_vitpack : HInst<
3864(outs IntRegs:$Rd32),
3865(ins PredRegs:$Ps4, PredRegs:$Pt4),
3866"$Rd32 = vitpack($Ps4,$Pt4)",
3867tc_f34c1c21, TypeS_2op>, Enc_527412 {
3868let Inst{7-5} = 0b000;
3869let Inst{13-10} = 0b0000;
3870let Inst{31-18} = 0b10001001000000;
3871let hasNewValue = 1;
3872let opNewValue = 0;
3873let prefersSlot3 = 1;
3874}
3875def C2_vmux : HInst<
3876(outs DoubleRegs:$Rdd32),
3877(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3878"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
3879tc_6fc5dbea, TypeALU64>, Enc_329361 {
3880let Inst{7-7} = 0b0;
3881let Inst{13-13} = 0b0;
3882let Inst{31-21} = 0b11010001000;
3883}
3884def C2_xor : HInst<
3885(outs PredRegs:$Pd4),
3886(ins PredRegs:$Ps4, PredRegs:$Pt4),
3887"$Pd4 = xor($Ps4,$Pt4)",
3888tc_651cbe02, TypeCR>, Enc_284ebb {
3889let Inst{7-2} = 0b000000;
3890let Inst{13-10} = 0b0000;
3891let Inst{31-18} = 0b01101011010000;
3892}
3893def C4_addipc : HInst<
3894(outs IntRegs:$Rd32),
3895(ins u32_0Imm:$Ii),
3896"$Rd32 = add(pc,#$Ii)",
3897tc_3edca78f, TypeCR>, Enc_607661 {
3898let Inst{6-5} = 0b00;
3899let Inst{13-13} = 0b0;
3900let Inst{31-16} = 0b0110101001001001;
3901let hasNewValue = 1;
3902let opNewValue = 0;
3903let isExtendable = 1;
3904let opExtendable = 1;
3905let isExtentSigned = 0;
3906let opExtentBits = 6;
3907let opExtentAlign = 0;
3908}
3909def C4_and_and : HInst<
3910(outs PredRegs:$Pd4),
3911(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3912"$Pd4 = and($Ps4,and($Pt4,$Pu4))",
3913tc_a7a13fac, TypeCR>, Enc_9ac432 {
3914let Inst{5-2} = 0b0000;
3915let Inst{13-10} = 0b0000;
3916let Inst{31-18} = 0b01101011000100;
3917}
3918def C4_and_andn : HInst<
3919(outs PredRegs:$Pd4),
3920(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3921"$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
3922tc_a7a13fac, TypeCR>, Enc_9ac432 {
3923let Inst{5-2} = 0b0000;
3924let Inst{13-10} = 0b0000;
3925let Inst{31-18} = 0b01101011100100;
3926}
3927def C4_and_or : HInst<
3928(outs PredRegs:$Pd4),
3929(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3930"$Pd4 = and($Ps4,or($Pt4,$Pu4))",
3931tc_a7a13fac, TypeCR>, Enc_9ac432 {
3932let Inst{5-2} = 0b0000;
3933let Inst{13-10} = 0b0000;
3934let Inst{31-18} = 0b01101011001100;
3935}
3936def C4_and_orn : HInst<
3937(outs PredRegs:$Pd4),
3938(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3939"$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
3940tc_a7a13fac, TypeCR>, Enc_9ac432 {
3941let Inst{5-2} = 0b0000;
3942let Inst{13-10} = 0b0000;
3943let Inst{31-18} = 0b01101011101100;
3944}
3945def C4_cmplte : HInst<
3946(outs PredRegs:$Pd4),
3947(ins IntRegs:$Rs32, IntRegs:$Rt32),
3948"$Pd4 = !cmp.gt($Rs32,$Rt32)",
3949tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3950let Inst{7-2} = 0b000100;
3951let Inst{13-13} = 0b0;
3952let Inst{31-21} = 0b11110010010;
3953let CextOpcode = "C4_cmplte";
3954let InputType = "reg";
3955let isCompare = 1;
3956}
3957def C4_cmpltei : HInst<
3958(outs PredRegs:$Pd4),
3959(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3960"$Pd4 = !cmp.gt($Rs32,#$Ii)",
3961tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3962let Inst{4-2} = 0b100;
3963let Inst{31-22} = 0b0111010101;
3964let CextOpcode = "C4_cmplte";
3965let InputType = "imm";
3966let isCompare = 1;
3967let isExtendable = 1;
3968let opExtendable = 2;
3969let isExtentSigned = 1;
3970let opExtentBits = 10;
3971let opExtentAlign = 0;
3972}
3973def C4_cmplteu : HInst<
3974(outs PredRegs:$Pd4),
3975(ins IntRegs:$Rs32, IntRegs:$Rt32),
3976"$Pd4 = !cmp.gtu($Rs32,$Rt32)",
3977tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3978let Inst{7-2} = 0b000100;
3979let Inst{13-13} = 0b0;
3980let Inst{31-21} = 0b11110010011;
3981let CextOpcode = "C4_cmplteu";
3982let InputType = "reg";
3983let isCompare = 1;
3984}
3985def C4_cmplteui : HInst<
3986(outs PredRegs:$Pd4),
3987(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3988"$Pd4 = !cmp.gtu($Rs32,#$Ii)",
3989tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3990let Inst{4-2} = 0b100;
3991let Inst{31-21} = 0b01110101100;
3992let CextOpcode = "C4_cmplteu";
3993let InputType = "imm";
3994let isCompare = 1;
3995let isExtendable = 1;
3996let opExtendable = 2;
3997let isExtentSigned = 0;
3998let opExtentBits = 9;
3999let opExtentAlign = 0;
4000}
4001def C4_cmpneq : HInst<
4002(outs PredRegs:$Pd4),
4003(ins IntRegs:$Rs32, IntRegs:$Rt32),
4004"$Pd4 = !cmp.eq($Rs32,$Rt32)",
4005tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
4006let Inst{7-2} = 0b000100;
4007let Inst{13-13} = 0b0;
4008let Inst{31-21} = 0b11110010000;
4009let CextOpcode = "C4_cmpneq";
4010let InputType = "reg";
4011let isCommutable = 1;
4012let isCompare = 1;
4013}
4014def C4_cmpneqi : HInst<
4015(outs PredRegs:$Pd4),
4016(ins IntRegs:$Rs32, s32_0Imm:$Ii),
4017"$Pd4 = !cmp.eq($Rs32,#$Ii)",
4018tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
4019let Inst{4-2} = 0b100;
4020let Inst{31-22} = 0b0111010100;
4021let CextOpcode = "C4_cmpneq";
4022let InputType = "imm";
4023let isCompare = 1;
4024let isExtendable = 1;
4025let opExtendable = 2;
4026let isExtentSigned = 1;
4027let opExtentBits = 10;
4028let opExtentAlign = 0;
4029}
4030def C4_fastcorner9 : HInst<
4031(outs PredRegs:$Pd4),
4032(ins PredRegs:$Ps4, PredRegs:$Pt4),
4033"$Pd4 = fastcorner9($Ps4,$Pt4)",
4034tc_651cbe02, TypeCR>, Enc_284ebb {
4035let Inst{7-2} = 0b100100;
4036let Inst{13-10} = 0b1000;
4037let Inst{31-18} = 0b01101011000000;
4038}
4039def C4_fastcorner9_not : HInst<
4040(outs PredRegs:$Pd4),
4041(ins PredRegs:$Ps4, PredRegs:$Pt4),
4042"$Pd4 = !fastcorner9($Ps4,$Pt4)",
4043tc_651cbe02, TypeCR>, Enc_284ebb {
4044let Inst{7-2} = 0b100100;
4045let Inst{13-10} = 0b1000;
4046let Inst{31-18} = 0b01101011000100;
4047}
4048def C4_nbitsclr : HInst<
4049(outs PredRegs:$Pd4),
4050(ins IntRegs:$Rs32, IntRegs:$Rt32),
4051"$Pd4 = !bitsclr($Rs32,$Rt32)",
4052tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4053let Inst{7-2} = 0b000000;
4054let Inst{13-13} = 0b0;
4055let Inst{31-21} = 0b11000111101;
4056}
4057def C4_nbitsclri : HInst<
4058(outs PredRegs:$Pd4),
4059(ins IntRegs:$Rs32, u6_0Imm:$Ii),
4060"$Pd4 = !bitsclr($Rs32,#$Ii)",
4061tc_a1297125, TypeS_2op>, Enc_5d6c34 {
4062let Inst{7-2} = 0b000000;
4063let Inst{31-21} = 0b10000101101;
4064}
4065def C4_nbitsset : HInst<
4066(outs PredRegs:$Pd4),
4067(ins IntRegs:$Rs32, IntRegs:$Rt32),
4068"$Pd4 = !bitsset($Rs32,$Rt32)",
4069tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4070let Inst{7-2} = 0b000000;
4071let Inst{13-13} = 0b0;
4072let Inst{31-21} = 0b11000111011;
4073}
4074def C4_or_and : HInst<
4075(outs PredRegs:$Pd4),
4076(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4077"$Pd4 = or($Ps4,and($Pt4,$Pu4))",
4078tc_a7a13fac, TypeCR>, Enc_9ac432 {
4079let Inst{5-2} = 0b0000;
4080let Inst{13-10} = 0b0000;
4081let Inst{31-18} = 0b01101011010100;
4082}
4083def C4_or_andn : HInst<
4084(outs PredRegs:$Pd4),
4085(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4086"$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
4087tc_a7a13fac, TypeCR>, Enc_9ac432 {
4088let Inst{5-2} = 0b0000;
4089let Inst{13-10} = 0b0000;
4090let Inst{31-18} = 0b01101011110100;
4091}
4092def C4_or_or : HInst<
4093(outs PredRegs:$Pd4),
4094(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4095"$Pd4 = or($Ps4,or($Pt4,$Pu4))",
4096tc_a7a13fac, TypeCR>, Enc_9ac432 {
4097let Inst{5-2} = 0b0000;
4098let Inst{13-10} = 0b0000;
4099let Inst{31-18} = 0b01101011011100;
4100}
4101def C4_or_orn : HInst<
4102(outs PredRegs:$Pd4),
4103(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4104"$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
4105tc_a7a13fac, TypeCR>, Enc_9ac432 {
4106let Inst{5-2} = 0b0000;
4107let Inst{13-10} = 0b0000;
4108let Inst{31-18} = 0b01101011111100;
4109}
4110def F2_conv_d2df : HInst<
4111(outs DoubleRegs:$Rdd32),
4112(ins DoubleRegs:$Rss32),
4113"$Rdd32 = convert_d2df($Rss32)",
4114tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4115let Inst{13-5} = 0b000000011;
4116let Inst{31-21} = 0b10000000111;
4117let isFP = 1;
4118let Uses = [USR];
4119}
4120def F2_conv_d2sf : HInst<
4121(outs IntRegs:$Rd32),
4122(ins DoubleRegs:$Rss32),
4123"$Rd32 = convert_d2sf($Rss32)",
4124tc_9783714b, TypeS_2op>, Enc_90cd8b {
4125let Inst{13-5} = 0b000000001;
4126let Inst{31-21} = 0b10001000010;
4127let hasNewValue = 1;
4128let opNewValue = 0;
4129let isFP = 1;
4130let Uses = [USR];
4131}
4132def F2_conv_df2d : HInst<
4133(outs DoubleRegs:$Rdd32),
4134(ins DoubleRegs:$Rss32),
4135"$Rdd32 = convert_df2d($Rss32)",
4136tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4137let Inst{13-5} = 0b000000000;
4138let Inst{31-21} = 0b10000000111;
4139let isFP = 1;
4140let Uses = [USR];
4141}
4142def F2_conv_df2d_chop : HInst<
4143(outs DoubleRegs:$Rdd32),
4144(ins DoubleRegs:$Rss32),
4145"$Rdd32 = convert_df2d($Rss32):chop",
4146tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4147let Inst{13-5} = 0b000000110;
4148let Inst{31-21} = 0b10000000111;
4149let isFP = 1;
4150let Uses = [USR];
4151}
4152def F2_conv_df2sf : HInst<
4153(outs IntRegs:$Rd32),
4154(ins DoubleRegs:$Rss32),
4155"$Rd32 = convert_df2sf($Rss32)",
4156tc_9783714b, TypeS_2op>, Enc_90cd8b {
4157let Inst{13-5} = 0b000000001;
4158let Inst{31-21} = 0b10001000000;
4159let hasNewValue = 1;
4160let opNewValue = 0;
4161let isFP = 1;
4162let Uses = [USR];
4163}
4164def F2_conv_df2ud : HInst<
4165(outs DoubleRegs:$Rdd32),
4166(ins DoubleRegs:$Rss32),
4167"$Rdd32 = convert_df2ud($Rss32)",
4168tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4169let Inst{13-5} = 0b000000001;
4170let Inst{31-21} = 0b10000000111;
4171let isFP = 1;
4172let Uses = [USR];
4173}
4174def F2_conv_df2ud_chop : HInst<
4175(outs DoubleRegs:$Rdd32),
4176(ins DoubleRegs:$Rss32),
4177"$Rdd32 = convert_df2ud($Rss32):chop",
4178tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4179let Inst{13-5} = 0b000000111;
4180let Inst{31-21} = 0b10000000111;
4181let isFP = 1;
4182let Uses = [USR];
4183}
4184def F2_conv_df2uw : HInst<
4185(outs IntRegs:$Rd32),
4186(ins DoubleRegs:$Rss32),
4187"$Rd32 = convert_df2uw($Rss32)",
4188tc_9783714b, TypeS_2op>, Enc_90cd8b {
4189let Inst{13-5} = 0b000000001;
4190let Inst{31-21} = 0b10001000011;
4191let hasNewValue = 1;
4192let opNewValue = 0;
4193let isFP = 1;
4194let Uses = [USR];
4195}
4196def F2_conv_df2uw_chop : HInst<
4197(outs IntRegs:$Rd32),
4198(ins DoubleRegs:$Rss32),
4199"$Rd32 = convert_df2uw($Rss32):chop",
4200tc_9783714b, TypeS_2op>, Enc_90cd8b {
4201let Inst{13-5} = 0b000000001;
4202let Inst{31-21} = 0b10001000101;
4203let hasNewValue = 1;
4204let opNewValue = 0;
4205let isFP = 1;
4206let Uses = [USR];
4207}
4208def F2_conv_df2w : HInst<
4209(outs IntRegs:$Rd32),
4210(ins DoubleRegs:$Rss32),
4211"$Rd32 = convert_df2w($Rss32)",
4212tc_9783714b, TypeS_2op>, Enc_90cd8b {
4213let Inst{13-5} = 0b000000001;
4214let Inst{31-21} = 0b10001000100;
4215let hasNewValue = 1;
4216let opNewValue = 0;
4217let isFP = 1;
4218let Uses = [USR];
4219}
4220def F2_conv_df2w_chop : HInst<
4221(outs IntRegs:$Rd32),
4222(ins DoubleRegs:$Rss32),
4223"$Rd32 = convert_df2w($Rss32):chop",
4224tc_9783714b, TypeS_2op>, Enc_90cd8b {
4225let Inst{13-5} = 0b000000001;
4226let Inst{31-21} = 0b10001000111;
4227let hasNewValue = 1;
4228let opNewValue = 0;
4229let isFP = 1;
4230let Uses = [USR];
4231}
4232def F2_conv_sf2d : HInst<
4233(outs DoubleRegs:$Rdd32),
4234(ins IntRegs:$Rs32),
4235"$Rdd32 = convert_sf2d($Rs32)",
4236tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4237let Inst{13-5} = 0b000000100;
4238let Inst{31-21} = 0b10000100100;
4239let isFP = 1;
4240let Uses = [USR];
4241}
4242def F2_conv_sf2d_chop : HInst<
4243(outs DoubleRegs:$Rdd32),
4244(ins IntRegs:$Rs32),
4245"$Rdd32 = convert_sf2d($Rs32):chop",
4246tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4247let Inst{13-5} = 0b000000110;
4248let Inst{31-21} = 0b10000100100;
4249let isFP = 1;
4250let Uses = [USR];
4251}
4252def F2_conv_sf2df : HInst<
4253(outs DoubleRegs:$Rdd32),
4254(ins IntRegs:$Rs32),
4255"$Rdd32 = convert_sf2df($Rs32)",
4256tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4257let Inst{13-5} = 0b000000000;
4258let Inst{31-21} = 0b10000100100;
4259let isFP = 1;
4260let Uses = [USR];
4261}
4262def F2_conv_sf2ud : HInst<
4263(outs DoubleRegs:$Rdd32),
4264(ins IntRegs:$Rs32),
4265"$Rdd32 = convert_sf2ud($Rs32)",
4266tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4267let Inst{13-5} = 0b000000011;
4268let Inst{31-21} = 0b10000100100;
4269let isFP = 1;
4270let Uses = [USR];
4271}
4272def F2_conv_sf2ud_chop : HInst<
4273(outs DoubleRegs:$Rdd32),
4274(ins IntRegs:$Rs32),
4275"$Rdd32 = convert_sf2ud($Rs32):chop",
4276tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4277let Inst{13-5} = 0b000000101;
4278let Inst{31-21} = 0b10000100100;
4279let isFP = 1;
4280let Uses = [USR];
4281}
4282def F2_conv_sf2uw : HInst<
4283(outs IntRegs:$Rd32),
4284(ins IntRegs:$Rs32),
4285"$Rd32 = convert_sf2uw($Rs32)",
4286tc_9783714b, TypeS_2op>, Enc_5e2823 {
4287let Inst{13-5} = 0b000000000;
4288let Inst{31-21} = 0b10001011011;
4289let hasNewValue = 1;
4290let opNewValue = 0;
4291let isFP = 1;
4292let Uses = [USR];
4293}
4294def F2_conv_sf2uw_chop : HInst<
4295(outs IntRegs:$Rd32),
4296(ins IntRegs:$Rs32),
4297"$Rd32 = convert_sf2uw($Rs32):chop",
4298tc_9783714b, TypeS_2op>, Enc_5e2823 {
4299let Inst{13-5} = 0b000000001;
4300let Inst{31-21} = 0b10001011011;
4301let hasNewValue = 1;
4302let opNewValue = 0;
4303let isFP = 1;
4304let Uses = [USR];
4305}
4306def F2_conv_sf2w : HInst<
4307(outs IntRegs:$Rd32),
4308(ins IntRegs:$Rs32),
4309"$Rd32 = convert_sf2w($Rs32)",
4310tc_9783714b, TypeS_2op>, Enc_5e2823 {
4311let Inst{13-5} = 0b000000000;
4312let Inst{31-21} = 0b10001011100;
4313let hasNewValue = 1;
4314let opNewValue = 0;
4315let isFP = 1;
4316let Uses = [USR];
4317}
4318def F2_conv_sf2w_chop : HInst<
4319(outs IntRegs:$Rd32),
4320(ins IntRegs:$Rs32),
4321"$Rd32 = convert_sf2w($Rs32):chop",
4322tc_9783714b, TypeS_2op>, Enc_5e2823 {
4323let Inst{13-5} = 0b000000001;
4324let Inst{31-21} = 0b10001011100;
4325let hasNewValue = 1;
4326let opNewValue = 0;
4327let isFP = 1;
4328let Uses = [USR];
4329}
4330def F2_conv_ud2df : HInst<
4331(outs DoubleRegs:$Rdd32),
4332(ins DoubleRegs:$Rss32),
4333"$Rdd32 = convert_ud2df($Rss32)",
4334tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4335let Inst{13-5} = 0b000000010;
4336let Inst{31-21} = 0b10000000111;
4337let isFP = 1;
4338let Uses = [USR];
4339}
4340def F2_conv_ud2sf : HInst<
4341(outs IntRegs:$Rd32),
4342(ins DoubleRegs:$Rss32),
4343"$Rd32 = convert_ud2sf($Rss32)",
4344tc_9783714b, TypeS_2op>, Enc_90cd8b {
4345let Inst{13-5} = 0b000000001;
4346let Inst{31-21} = 0b10001000001;
4347let hasNewValue = 1;
4348let opNewValue = 0;
4349let isFP = 1;
4350let Uses = [USR];
4351}
4352def F2_conv_uw2df : HInst<
4353(outs DoubleRegs:$Rdd32),
4354(ins IntRegs:$Rs32),
4355"$Rdd32 = convert_uw2df($Rs32)",
4356tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4357let Inst{13-5} = 0b000000001;
4358let Inst{31-21} = 0b10000100100;
4359let isFP = 1;
4360let Uses = [USR];
4361}
4362def F2_conv_uw2sf : HInst<
4363(outs IntRegs:$Rd32),
4364(ins IntRegs:$Rs32),
4365"$Rd32 = convert_uw2sf($Rs32)",
4366tc_9783714b, TypeS_2op>, Enc_5e2823 {
4367let Inst{13-5} = 0b000000000;
4368let Inst{31-21} = 0b10001011001;
4369let hasNewValue = 1;
4370let opNewValue = 0;
4371let isFP = 1;
4372let Uses = [USR];
4373}
4374def F2_conv_w2df : HInst<
4375(outs DoubleRegs:$Rdd32),
4376(ins IntRegs:$Rs32),
4377"$Rdd32 = convert_w2df($Rs32)",
4378tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4379let Inst{13-5} = 0b000000010;
4380let Inst{31-21} = 0b10000100100;
4381let isFP = 1;
4382let Uses = [USR];
4383}
4384def F2_conv_w2sf : HInst<
4385(outs IntRegs:$Rd32),
4386(ins IntRegs:$Rs32),
4387"$Rd32 = convert_w2sf($Rs32)",
4388tc_9783714b, TypeS_2op>, Enc_5e2823 {
4389let Inst{13-5} = 0b000000000;
4390let Inst{31-21} = 0b10001011010;
4391let hasNewValue = 1;
4392let opNewValue = 0;
4393let isFP = 1;
4394let Uses = [USR];
4395}
4396def F2_dfadd : HInst<
4397(outs DoubleRegs:$Rdd32),
4398(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4399"$Rdd32 = dfadd($Rss32,$Rtt32)",
4400tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4401let Inst{7-5} = 0b011;
4402let Inst{13-13} = 0b0;
4403let Inst{31-21} = 0b11101000000;
4404let isFP = 1;
4405let Uses = [USR];
4406}
4407def F2_dfclass : HInst<
4408(outs PredRegs:$Pd4),
4409(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
4410"$Pd4 = dfclass($Rss32,#$Ii)",
4411tc_a1297125, TypeALU64>, Enc_1f19b5 {
4412let Inst{4-2} = 0b100;
4413let Inst{13-10} = 0b0000;
4414let Inst{31-21} = 0b11011100100;
4415let isFP = 1;
4416let Uses = [USR];
4417}
4418def F2_dfcmpeq : HInst<
4419(outs PredRegs:$Pd4),
4420(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4421"$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
4422tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4423let Inst{7-2} = 0b000000;
4424let Inst{13-13} = 0b0;
4425let Inst{31-21} = 0b11010010111;
4426let isFP = 1;
4427let Uses = [USR];
4428let isCompare = 1;
4429}
4430def F2_dfcmpge : HInst<
4431(outs PredRegs:$Pd4),
4432(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4433"$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
4434tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4435let Inst{7-2} = 0b010000;
4436let Inst{13-13} = 0b0;
4437let Inst{31-21} = 0b11010010111;
4438let isFP = 1;
4439let Uses = [USR];
4440let isCompare = 1;
4441}
4442def F2_dfcmpgt : HInst<
4443(outs PredRegs:$Pd4),
4444(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4445"$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
4446tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4447let Inst{7-2} = 0b001000;
4448let Inst{13-13} = 0b0;
4449let Inst{31-21} = 0b11010010111;
4450let isFP = 1;
4451let Uses = [USR];
4452let isCompare = 1;
4453}
4454def F2_dfcmpuo : HInst<
4455(outs PredRegs:$Pd4),
4456(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4457"$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
4458tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4459let Inst{7-2} = 0b011000;
4460let Inst{13-13} = 0b0;
4461let Inst{31-21} = 0b11010010111;
4462let isFP = 1;
4463let Uses = [USR];
4464let isCompare = 1;
4465}
4466def F2_dfimm_n : HInst<
4467(outs DoubleRegs:$Rdd32),
4468(ins u10_0Imm:$Ii),
4469"$Rdd32 = dfmake(#$Ii):neg",
4470tc_65279839, TypeALU64>, Enc_e6c957 {
4471let Inst{20-16} = 0b00000;
4472let Inst{31-22} = 0b1101100101;
4473let prefersSlot3 = 1;
4474}
4475def F2_dfimm_p : HInst<
4476(outs DoubleRegs:$Rdd32),
4477(ins u10_0Imm:$Ii),
4478"$Rdd32 = dfmake(#$Ii):pos",
4479tc_65279839, TypeALU64>, Enc_e6c957 {
4480let Inst{20-16} = 0b00000;
4481let Inst{31-22} = 0b1101100100;
4482let prefersSlot3 = 1;
4483}
4484def F2_dfmax : HInst<
4485(outs DoubleRegs:$Rdd32),
4486(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4487"$Rdd32 = dfmax($Rss32,$Rtt32)",
4488tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4489let Inst{7-5} = 0b011;
4490let Inst{13-13} = 0b0;
4491let Inst{31-21} = 0b11101000001;
4492let isFP = 1;
4493let prefersSlot3 = 1;
4494let Uses = [USR];
4495}
4496def F2_dfmin : HInst<
4497(outs DoubleRegs:$Rdd32),
4498(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4499"$Rdd32 = dfmin($Rss32,$Rtt32)",
4500tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4501let Inst{7-5} = 0b011;
4502let Inst{13-13} = 0b0;
4503let Inst{31-21} = 0b11101000110;
4504let isFP = 1;
4505let prefersSlot3 = 1;
4506let Uses = [USR];
4507}
4508def F2_dfmpyfix : HInst<
4509(outs DoubleRegs:$Rdd32),
4510(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4511"$Rdd32 = dfmpyfix($Rss32,$Rtt32)",
4512tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> {
4513let Inst{7-5} = 0b011;
4514let Inst{13-13} = 0b0;
4515let Inst{31-21} = 0b11101000010;
4516let isFP = 1;
4517let Uses = [USR];
4518}
4519def F2_dfmpyhh : HInst<
4520(outs DoubleRegs:$Rxx32),
4521(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4522"$Rxx32 += dfmpyhh($Rss32,$Rtt32)",
4523tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4524let Inst{7-5} = 0b011;
4525let Inst{13-13} = 0b0;
4526let Inst{31-21} = 0b11101010100;
4527let isFP = 1;
4528let Uses = [USR];
4529let Constraints = "$Rxx32 = $Rxx32in";
4530}
4531def F2_dfmpylh : HInst<
4532(outs DoubleRegs:$Rxx32),
4533(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4534"$Rxx32 += dfmpylh($Rss32,$Rtt32)",
4535tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4536let Inst{7-5} = 0b011;
4537let Inst{13-13} = 0b0;
4538let Inst{31-21} = 0b11101010000;
4539let prefersSlot3 = 1;
4540let Constraints = "$Rxx32 = $Rxx32in";
4541}
4542def F2_dfmpyll : HInst<
4543(outs DoubleRegs:$Rdd32),
4544(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4545"$Rdd32 = dfmpyll($Rss32,$Rtt32)",
4546tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> {
4547let Inst{7-5} = 0b011;
4548let Inst{13-13} = 0b0;
4549let Inst{31-21} = 0b11101000101;
4550let prefersSlot3 = 1;
4551}
4552def F2_dfsub : HInst<
4553(outs DoubleRegs:$Rdd32),
4554(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4555"$Rdd32 = dfsub($Rss32,$Rtt32)",
4556tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4557let Inst{7-5} = 0b011;
4558let Inst{13-13} = 0b0;
4559let Inst{31-21} = 0b11101000100;
4560let isFP = 1;
4561let Uses = [USR];
4562}
4563def F2_sfadd : HInst<
4564(outs IntRegs:$Rd32),
4565(ins IntRegs:$Rs32, IntRegs:$Rt32),
4566"$Rd32 = sfadd($Rs32,$Rt32)",
4567tc_02fe1c65, TypeM>, Enc_5ab2be {
4568let Inst{7-5} = 0b000;
4569let Inst{13-13} = 0b0;
4570let Inst{31-21} = 0b11101011000;
4571let hasNewValue = 1;
4572let opNewValue = 0;
4573let isFP = 1;
4574let Uses = [USR];
4575let isCommutable = 1;
4576}
4577def F2_sfclass : HInst<
4578(outs PredRegs:$Pd4),
4579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
4580"$Pd4 = sfclass($Rs32,#$Ii)",
4581tc_a1297125, TypeS_2op>, Enc_83ee64 {
4582let Inst{7-2} = 0b000000;
4583let Inst{13-13} = 0b0;
4584let Inst{31-21} = 0b10000101111;
4585let isFP = 1;
4586let Uses = [USR];
4587}
4588def F2_sfcmpeq : HInst<
4589(outs PredRegs:$Pd4),
4590(ins IntRegs:$Rs32, IntRegs:$Rt32),
4591"$Pd4 = sfcmp.eq($Rs32,$Rt32)",
4592tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4593let Inst{7-2} = 0b011000;
4594let Inst{13-13} = 0b0;
4595let Inst{31-21} = 0b11000111111;
4596let isFP = 1;
4597let Uses = [USR];
4598let isCompare = 1;
4599}
4600def F2_sfcmpge : HInst<
4601(outs PredRegs:$Pd4),
4602(ins IntRegs:$Rs32, IntRegs:$Rt32),
4603"$Pd4 = sfcmp.ge($Rs32,$Rt32)",
4604tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4605let Inst{7-2} = 0b000000;
4606let Inst{13-13} = 0b0;
4607let Inst{31-21} = 0b11000111111;
4608let isFP = 1;
4609let Uses = [USR];
4610let isCompare = 1;
4611}
4612def F2_sfcmpgt : HInst<
4613(outs PredRegs:$Pd4),
4614(ins IntRegs:$Rs32, IntRegs:$Rt32),
4615"$Pd4 = sfcmp.gt($Rs32,$Rt32)",
4616tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4617let Inst{7-2} = 0b100000;
4618let Inst{13-13} = 0b0;
4619let Inst{31-21} = 0b11000111111;
4620let isFP = 1;
4621let Uses = [USR];
4622let isCompare = 1;
4623}
4624def F2_sfcmpuo : HInst<
4625(outs PredRegs:$Pd4),
4626(ins IntRegs:$Rs32, IntRegs:$Rt32),
4627"$Pd4 = sfcmp.uo($Rs32,$Rt32)",
4628tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4629let Inst{7-2} = 0b001000;
4630let Inst{13-13} = 0b0;
4631let Inst{31-21} = 0b11000111111;
4632let isFP = 1;
4633let Uses = [USR];
4634let isCompare = 1;
4635}
4636def F2_sffixupd : HInst<
4637(outs IntRegs:$Rd32),
4638(ins IntRegs:$Rs32, IntRegs:$Rt32),
4639"$Rd32 = sffixupd($Rs32,$Rt32)",
4640tc_02fe1c65, TypeM>, Enc_5ab2be {
4641let Inst{7-5} = 0b001;
4642let Inst{13-13} = 0b0;
4643let Inst{31-21} = 0b11101011110;
4644let hasNewValue = 1;
4645let opNewValue = 0;
4646let isFP = 1;
4647}
4648def F2_sffixupn : HInst<
4649(outs IntRegs:$Rd32),
4650(ins IntRegs:$Rs32, IntRegs:$Rt32),
4651"$Rd32 = sffixupn($Rs32,$Rt32)",
4652tc_02fe1c65, TypeM>, Enc_5ab2be {
4653let Inst{7-5} = 0b000;
4654let Inst{13-13} = 0b0;
4655let Inst{31-21} = 0b11101011110;
4656let hasNewValue = 1;
4657let opNewValue = 0;
4658let isFP = 1;
4659}
4660def F2_sffixupr : HInst<
4661(outs IntRegs:$Rd32),
4662(ins IntRegs:$Rs32),
4663"$Rd32 = sffixupr($Rs32)",
4664tc_9783714b, TypeS_2op>, Enc_5e2823 {
4665let Inst{13-5} = 0b000000000;
4666let Inst{31-21} = 0b10001011101;
4667let hasNewValue = 1;
4668let opNewValue = 0;
4669let isFP = 1;
4670}
4671def F2_sffma : HInst<
4672(outs IntRegs:$Rx32),
4673(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4674"$Rx32 += sfmpy($Rs32,$Rt32)",
4675tc_9e72dc89, TypeM>, Enc_2ae154 {
4676let Inst{7-5} = 0b100;
4677let Inst{13-13} = 0b0;
4678let Inst{31-21} = 0b11101111000;
4679let hasNewValue = 1;
4680let opNewValue = 0;
4681let isFP = 1;
4682let Uses = [USR];
4683let Constraints = "$Rx32 = $Rx32in";
4684}
4685def F2_sffma_lib : HInst<
4686(outs IntRegs:$Rx32),
4687(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4688"$Rx32 += sfmpy($Rs32,$Rt32):lib",
4689tc_9e72dc89, TypeM>, Enc_2ae154 {
4690let Inst{7-5} = 0b110;
4691let Inst{13-13} = 0b0;
4692let Inst{31-21} = 0b11101111000;
4693let hasNewValue = 1;
4694let opNewValue = 0;
4695let isFP = 1;
4696let Uses = [USR];
4697let Constraints = "$Rx32 = $Rx32in";
4698}
4699def F2_sffma_sc : HInst<
4700(outs IntRegs:$Rx32),
4701(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
4702"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
4703tc_9edb7c77, TypeM>, Enc_437f33 {
4704let Inst{7-7} = 0b1;
4705let Inst{13-13} = 0b0;
4706let Inst{31-21} = 0b11101111011;
4707let hasNewValue = 1;
4708let opNewValue = 0;
4709let isFP = 1;
4710let Uses = [USR];
4711let Constraints = "$Rx32 = $Rx32in";
4712}
4713def F2_sffms : HInst<
4714(outs IntRegs:$Rx32),
4715(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4716"$Rx32 -= sfmpy($Rs32,$Rt32)",
4717tc_9e72dc89, TypeM>, Enc_2ae154 {
4718let Inst{7-5} = 0b101;
4719let Inst{13-13} = 0b0;
4720let Inst{31-21} = 0b11101111000;
4721let hasNewValue = 1;
4722let opNewValue = 0;
4723let isFP = 1;
4724let Uses = [USR];
4725let Constraints = "$Rx32 = $Rx32in";
4726}
4727def F2_sffms_lib : HInst<
4728(outs IntRegs:$Rx32),
4729(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4730"$Rx32 -= sfmpy($Rs32,$Rt32):lib",
4731tc_9e72dc89, TypeM>, Enc_2ae154 {
4732let Inst{7-5} = 0b111;
4733let Inst{13-13} = 0b0;
4734let Inst{31-21} = 0b11101111000;
4735let hasNewValue = 1;
4736let opNewValue = 0;
4737let isFP = 1;
4738let Uses = [USR];
4739let Constraints = "$Rx32 = $Rx32in";
4740}
4741def F2_sfimm_n : HInst<
4742(outs IntRegs:$Rd32),
4743(ins u10_0Imm:$Ii),
4744"$Rd32 = sfmake(#$Ii):neg",
4745tc_65279839, TypeALU64>, Enc_6c9440 {
4746let Inst{20-16} = 0b00000;
4747let Inst{31-22} = 0b1101011001;
4748let hasNewValue = 1;
4749let opNewValue = 0;
4750let prefersSlot3 = 1;
4751}
4752def F2_sfimm_p : HInst<
4753(outs IntRegs:$Rd32),
4754(ins u10_0Imm:$Ii),
4755"$Rd32 = sfmake(#$Ii):pos",
4756tc_65279839, TypeALU64>, Enc_6c9440 {
4757let Inst{20-16} = 0b00000;
4758let Inst{31-22} = 0b1101011000;
4759let hasNewValue = 1;
4760let opNewValue = 0;
4761let prefersSlot3 = 1;
4762}
4763def F2_sfinvsqrta : HInst<
4764(outs IntRegs:$Rd32, PredRegs:$Pe4),
4765(ins IntRegs:$Rs32),
4766"$Rd32,$Pe4 = sfinvsqrta($Rs32)",
4767tc_7f7f45f5, TypeS_2op>, Enc_890909 {
4768let Inst{13-7} = 0b0000000;
4769let Inst{31-21} = 0b10001011111;
4770let hasNewValue = 1;
4771let opNewValue = 0;
4772let isFP = 1;
4773let isPredicateLate = 1;
4774}
4775def F2_sfmax : HInst<
4776(outs IntRegs:$Rd32),
4777(ins IntRegs:$Rs32, IntRegs:$Rt32),
4778"$Rd32 = sfmax($Rs32,$Rt32)",
4779tc_c20701f0, TypeM>, Enc_5ab2be {
4780let Inst{7-5} = 0b000;
4781let Inst{13-13} = 0b0;
4782let Inst{31-21} = 0b11101011100;
4783let hasNewValue = 1;
4784let opNewValue = 0;
4785let isFP = 1;
4786let prefersSlot3 = 1;
4787let Uses = [USR];
4788}
4789def F2_sfmin : HInst<
4790(outs IntRegs:$Rd32),
4791(ins IntRegs:$Rs32, IntRegs:$Rt32),
4792"$Rd32 = sfmin($Rs32,$Rt32)",
4793tc_c20701f0, TypeM>, Enc_5ab2be {
4794let Inst{7-5} = 0b001;
4795let Inst{13-13} = 0b0;
4796let Inst{31-21} = 0b11101011100;
4797let hasNewValue = 1;
4798let opNewValue = 0;
4799let isFP = 1;
4800let prefersSlot3 = 1;
4801let Uses = [USR];
4802}
4803def F2_sfmpy : HInst<
4804(outs IntRegs:$Rd32),
4805(ins IntRegs:$Rs32, IntRegs:$Rt32),
4806"$Rd32 = sfmpy($Rs32,$Rt32)",
4807tc_02fe1c65, TypeM>, Enc_5ab2be {
4808let Inst{7-5} = 0b000;
4809let Inst{13-13} = 0b0;
4810let Inst{31-21} = 0b11101011010;
4811let hasNewValue = 1;
4812let opNewValue = 0;
4813let isFP = 1;
4814let Uses = [USR];
4815let isCommutable = 1;
4816}
4817def F2_sfrecipa : HInst<
4818(outs IntRegs:$Rd32, PredRegs:$Pe4),
4819(ins IntRegs:$Rs32, IntRegs:$Rt32),
4820"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
4821tc_f7569068, TypeM>, Enc_a94f3b {
4822let Inst{7-7} = 0b1;
4823let Inst{13-13} = 0b0;
4824let Inst{31-21} = 0b11101011111;
4825let hasNewValue = 1;
4826let opNewValue = 0;
4827let isFP = 1;
4828let isPredicateLate = 1;
4829}
4830def F2_sfsub : HInst<
4831(outs IntRegs:$Rd32),
4832(ins IntRegs:$Rs32, IntRegs:$Rt32),
4833"$Rd32 = sfsub($Rs32,$Rt32)",
4834tc_02fe1c65, TypeM>, Enc_5ab2be {
4835let Inst{7-5} = 0b001;
4836let Inst{13-13} = 0b0;
4837let Inst{31-21} = 0b11101011000;
4838let hasNewValue = 1;
4839let opNewValue = 0;
4840let isFP = 1;
4841let Uses = [USR];
4842}
4843def G4_tfrgcpp : HInst<
4844(outs DoubleRegs:$Rdd32),
4845(ins GuestRegs64:$Gss32),
4846"$Rdd32 = $Gss32",
4847tc_fae9dfa5, TypeCR>, Enc_0aa344 {
4848let Inst{13-5} = 0b000000000;
4849let Inst{31-21} = 0b01101000001;
4850}
4851def G4_tfrgcrr : HInst<
4852(outs IntRegs:$Rd32),
4853(ins GuestRegs:$Gs32),
4854"$Rd32 = $Gs32",
4855tc_fae9dfa5, TypeCR>, Enc_44271f {
4856let Inst{13-5} = 0b000000000;
4857let Inst{31-21} = 0b01101010001;
4858let hasNewValue = 1;
4859let opNewValue = 0;
4860}
4861def G4_tfrgpcp : HInst<
4862(outs GuestRegs64:$Gdd32),
4863(ins DoubleRegs:$Rss32),
4864"$Gdd32 = $Rss32",
4865tc_6ae3426b, TypeCR>, Enc_ed5027 {
4866let Inst{13-5} = 0b000000000;
4867let Inst{31-21} = 0b01100011000;
4868let hasNewValue = 1;
4869let opNewValue = 0;
4870}
4871def G4_tfrgrcr : HInst<
4872(outs GuestRegs:$Gd32),
4873(ins IntRegs:$Rs32),
4874"$Gd32 = $Rs32",
4875tc_6ae3426b, TypeCR>, Enc_621fba {
4876let Inst{13-5} = 0b000000000;
4877let Inst{31-21} = 0b01100010000;
4878let hasNewValue = 1;
4879let opNewValue = 0;
4880}
4881def J2_call : HInst<
4882(outs),
4883(ins a30_2Imm:$Ii),
4884"call $Ii",
4885tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel {
4886let Inst{0-0} = 0b0;
4887let Inst{31-25} = 0b0101101;
4888let isCall = 1;
4889let prefersSlot3 = 1;
4890let cofRelax2 = 1;
4891let cofMax1 = 1;
4892let Uses = [R29];
4893let Defs = [PC, R31];
4894let BaseOpcode = "J2_call";
4895let hasSideEffects = 1;
4896let isPredicable = 1;
4897let isExtendable = 1;
4898let opExtendable = 0;
4899let isExtentSigned = 1;
4900let opExtentBits = 24;
4901let opExtentAlign = 2;
4902}
4903def J2_callf : HInst<
4904(outs),
4905(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4906"if (!$Pu4) call $Ii",
4907tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4908let Inst{0-0} = 0b0;
4909let Inst{12-10} = 0b000;
4910let Inst{21-21} = 0b1;
4911let Inst{31-24} = 0b01011101;
4912let isPredicated = 1;
4913let isPredicatedFalse = 1;
4914let isCall = 1;
4915let prefersSlot3 = 1;
4916let cofRelax1 = 1;
4917let cofRelax2 = 1;
4918let cofMax1 = 1;
4919let Uses = [R29];
4920let Defs = [PC, R31];
4921let BaseOpcode = "J2_call";
4922let hasSideEffects = 1;
4923let isTaken = Inst{12};
4924let isExtendable = 1;
4925let opExtendable = 1;
4926let isExtentSigned = 1;
4927let opExtentBits = 17;
4928let opExtentAlign = 2;
4929}
4930def J2_callr : HInst<
4931(outs),
4932(ins IntRegs:$Rs32),
4933"callr $Rs32",
4934tc_362b0be2, TypeJ>, Enc_ecbcc8 {
4935let Inst{13-0} = 0b00000000000000;
4936let Inst{31-21} = 0b01010000101;
4937let isCall = 1;
4938let prefersSlot3 = 1;
4939let cofMax1 = 1;
4940let Uses = [R29];
4941let Defs = [PC, R31];
4942let hasSideEffects = 1;
4943}
4944def J2_callrf : HInst<
4945(outs),
4946(ins PredRegs:$Pu4, IntRegs:$Rs32),
4947"if (!$Pu4) callr $Rs32",
4948tc_dc51281d, TypeJ>, Enc_88d4d9 {
4949let Inst{7-0} = 0b00000000;
4950let Inst{13-10} = 0b0000;
4951let Inst{31-21} = 0b01010001001;
4952let isPredicated = 1;
4953let isPredicatedFalse = 1;
4954let isCall = 1;
4955let prefersSlot3 = 1;
4956let cofMax1 = 1;
4957let Uses = [R29];
4958let Defs = [PC, R31];
4959let hasSideEffects = 1;
4960let isTaken = Inst{12};
4961}
4962def J2_callrh : HInst<
4963(outs),
4964(ins IntRegs:$Rs32),
4965"callrh $Rs32",
4966tc_95f43c5e, TypeJ>, Enc_ecbcc8, Requires<[HasV73]> {
4967let Inst{13-0} = 0b00000000000000;
4968let Inst{31-21} = 0b01010000110;
4969let isCall = 1;
4970let prefersSlot3 = 1;
4971let cofMax1 = 1;
4972let Defs = [PC, R31];
4973}
4974def J2_callrt : HInst<
4975(outs),
4976(ins PredRegs:$Pu4, IntRegs:$Rs32),
4977"if ($Pu4) callr $Rs32",
4978tc_dc51281d, TypeJ>, Enc_88d4d9 {
4979let Inst{7-0} = 0b00000000;
4980let Inst{13-10} = 0b0000;
4981let Inst{31-21} = 0b01010001000;
4982let isPredicated = 1;
4983let isCall = 1;
4984let prefersSlot3 = 1;
4985let cofMax1 = 1;
4986let Uses = [R29];
4987let Defs = [PC, R31];
4988let hasSideEffects = 1;
4989let isTaken = Inst{12};
4990}
4991def J2_callt : HInst<
4992(outs),
4993(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4994"if ($Pu4) call $Ii",
4995tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4996let Inst{0-0} = 0b0;
4997let Inst{12-10} = 0b000;
4998let Inst{21-21} = 0b0;
4999let Inst{31-24} = 0b01011101;
5000let isPredicated = 1;
5001let isCall = 1;
5002let prefersSlot3 = 1;
5003let cofRelax1 = 1;
5004let cofRelax2 = 1;
5005let cofMax1 = 1;
5006let Uses = [R29];
5007let Defs = [PC, R31];
5008let BaseOpcode = "J2_call";
5009let hasSideEffects = 1;
5010let isTaken = Inst{12};
5011let isExtendable = 1;
5012let opExtendable = 1;
5013let isExtentSigned = 1;
5014let opExtentBits = 17;
5015let opExtentAlign = 2;
5016}
5017def J2_endloop0 : HInst<
5018(outs),
5019(ins),
5020"endloop0",
5021tc_23708a21, TypeJ> {
5022let Uses = [LC0, SA0];
5023let Defs = [LC0, P3, PC, USR];
5024let isBranch = 1;
5025let isTerminator = 1;
5026let isPseudo = 1;
5027}
5028def J2_endloop01 : HInst<
5029(outs),
5030(ins),
5031"endloop01",
5032tc_23708a21, TypeJ> {
5033let Uses = [LC0, LC1, SA0, SA1];
5034let Defs = [LC0, LC1, P3, PC, USR];
5035let isPseudo = 1;
5036}
5037def J2_endloop1 : HInst<
5038(outs),
5039(ins),
5040"endloop1",
5041tc_23708a21, TypeJ> {
5042let Uses = [LC1, SA1];
5043let Defs = [LC1, PC];
5044let isBranch = 1;
5045let isTerminator = 1;
5046let isPseudo = 1;
5047}
5048def J2_jump : HInst<
5049(outs),
5050(ins b30_2Imm:$Ii),
5051"jump $Ii",
5052tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel {
5053let Inst{0-0} = 0b0;
5054let Inst{31-25} = 0b0101100;
5055let isTerminator = 1;
5056let isBranch = 1;
5057let cofRelax2 = 1;
5058let cofMax1 = 1;
5059let Defs = [PC];
5060let BaseOpcode = "J2_jump";
5061let InputType = "imm";
5062let isBarrier = 1;
5063let isPredicable = 1;
5064let isExtendable = 1;
5065let opExtendable = 0;
5066let isExtentSigned = 1;
5067let opExtentBits = 24;
5068let opExtentAlign = 2;
5069}
5070def J2_jumpf : HInst<
5071(outs),
5072(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5073"if (!$Pu4) jump:nt $Ii",
5074tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5075let Inst{0-0} = 0b0;
5076let Inst{12-10} = 0b000;
5077let Inst{21-21} = 0b1;
5078let Inst{31-24} = 0b01011100;
5079let isPredicated = 1;
5080let isPredicatedFalse = 1;
5081let isTerminator = 1;
5082let isBranch = 1;
5083let cofRelax1 = 1;
5084let cofRelax2 = 1;
5085let cofMax1 = 1;
5086let Defs = [PC];
5087let BaseOpcode = "J2_jump";
5088let InputType = "imm";
5089let isTaken = Inst{12};
5090let isExtendable = 1;
5091let opExtendable = 1;
5092let isExtentSigned = 1;
5093let opExtentBits = 17;
5094let opExtentAlign = 2;
5095}
5096def J2_jumpf_nopred_map : HInst<
5097(outs),
5098(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5099"if (!$Pu4) jump $Ii",
5100tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5101let isPseudo = 1;
5102let isCodeGenOnly = 1;
5103}
5104def J2_jumpfnew : HInst<
5105(outs),
5106(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5107"if (!$Pu4.new) jump:nt $Ii",
5108tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5109let Inst{0-0} = 0b0;
5110let Inst{12-10} = 0b010;
5111let Inst{21-21} = 0b1;
5112let Inst{31-24} = 0b01011100;
5113let isPredicated = 1;
5114let isPredicatedFalse = 1;
5115let isTerminator = 1;
5116let isBranch = 1;
5117let isPredicatedNew = 1;
5118let cofRelax1 = 1;
5119let cofRelax2 = 1;
5120let cofMax1 = 1;
5121let Defs = [PC];
5122let BaseOpcode = "J2_jump";
5123let InputType = "imm";
5124let isTaken = Inst{12};
5125let isExtendable = 1;
5126let opExtendable = 1;
5127let isExtentSigned = 1;
5128let opExtentBits = 17;
5129let opExtentAlign = 2;
5130}
5131def J2_jumpfnewpt : HInst<
5132(outs),
5133(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5134"if (!$Pu4.new) jump:t $Ii",
5135tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5136let Inst{0-0} = 0b0;
5137let Inst{12-10} = 0b110;
5138let Inst{21-21} = 0b1;
5139let Inst{31-24} = 0b01011100;
5140let isPredicated = 1;
5141let isPredicatedFalse = 1;
5142let isTerminator = 1;
5143let isBranch = 1;
5144let isPredicatedNew = 1;
5145let cofRelax1 = 1;
5146let cofRelax2 = 1;
5147let cofMax1 = 1;
5148let Defs = [PC];
5149let BaseOpcode = "J2_jump";
5150let InputType = "imm";
5151let isTaken = Inst{12};
5152let isExtendable = 1;
5153let opExtendable = 1;
5154let isExtentSigned = 1;
5155let opExtentBits = 17;
5156let opExtentAlign = 2;
5157}
5158def J2_jumpfpt : HInst<
5159(outs),
5160(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5161"if (!$Pu4) jump:t $Ii",
5162tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5163let Inst{0-0} = 0b0;
5164let Inst{12-10} = 0b100;
5165let Inst{21-21} = 0b1;
5166let Inst{31-24} = 0b01011100;
5167let isPredicated = 1;
5168let isPredicatedFalse = 1;
5169let isTerminator = 1;
5170let isBranch = 1;
5171let cofRelax1 = 1;
5172let cofRelax2 = 1;
5173let cofMax1 = 1;
5174let Defs = [PC];
5175let BaseOpcode = "J2_jump";
5176let InputType = "imm";
5177let isTaken = Inst{12};
5178let isExtendable = 1;
5179let opExtendable = 1;
5180let isExtentSigned = 1;
5181let opExtentBits = 17;
5182let opExtentAlign = 2;
5183}
5184def J2_jumpr : HInst<
5185(outs),
5186(ins IntRegs:$Rs32),
5187"jumpr $Rs32",
5188tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel {
5189let Inst{13-0} = 0b00000000000000;
5190let Inst{31-21} = 0b01010010100;
5191let isTerminator = 1;
5192let isIndirectBranch = 1;
5193let isBranch = 1;
5194let cofMax1 = 1;
5195let Defs = [PC];
5196let BaseOpcode = "J2_jumpr";
5197let InputType = "reg";
5198let isBarrier = 1;
5199let isPredicable = 1;
5200}
5201def J2_jumprf : HInst<
5202(outs),
5203(ins PredRegs:$Pu4, IntRegs:$Rs32),
5204"if (!$Pu4) jumpr:nt $Rs32",
5205tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5206let Inst{7-0} = 0b00000000;
5207let Inst{13-10} = 0b0000;
5208let Inst{31-21} = 0b01010011011;
5209let isPredicated = 1;
5210let isPredicatedFalse = 1;
5211let isTerminator = 1;
5212let isIndirectBranch = 1;
5213let isBranch = 1;
5214let cofMax1 = 1;
5215let Defs = [PC];
5216let BaseOpcode = "J2_jumpr";
5217let InputType = "reg";
5218let isTaken = Inst{12};
5219}
5220def J2_jumprf_nopred_map : HInst<
5221(outs),
5222(ins PredRegs:$Pu4, IntRegs:$Rs32),
5223"if (!$Pu4) jumpr $Rs32",
5224tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5225let isPseudo = 1;
5226let isCodeGenOnly = 1;
5227}
5228def J2_jumprfnew : HInst<
5229(outs),
5230(ins PredRegs:$Pu4, IntRegs:$Rs32),
5231"if (!$Pu4.new) jumpr:nt $Rs32",
5232tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5233let Inst{7-0} = 0b00000000;
5234let Inst{13-10} = 0b0010;
5235let Inst{31-21} = 0b01010011011;
5236let isPredicated = 1;
5237let isPredicatedFalse = 1;
5238let isTerminator = 1;
5239let isIndirectBranch = 1;
5240let isBranch = 1;
5241let isPredicatedNew = 1;
5242let cofMax1 = 1;
5243let Defs = [PC];
5244let BaseOpcode = "J2_jumpr";
5245let InputType = "reg";
5246let isTaken = Inst{12};
5247}
5248def J2_jumprfnewpt : HInst<
5249(outs),
5250(ins PredRegs:$Pu4, IntRegs:$Rs32),
5251"if (!$Pu4.new) jumpr:t $Rs32",
5252tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5253let Inst{7-0} = 0b00000000;
5254let Inst{13-10} = 0b0110;
5255let Inst{31-21} = 0b01010011011;
5256let isPredicated = 1;
5257let isPredicatedFalse = 1;
5258let isTerminator = 1;
5259let isIndirectBranch = 1;
5260let isBranch = 1;
5261let isPredicatedNew = 1;
5262let cofMax1 = 1;
5263let Defs = [PC];
5264let BaseOpcode = "J2_jumpr";
5265let InputType = "reg";
5266let isTaken = Inst{12};
5267}
5268def J2_jumprfpt : HInst<
5269(outs),
5270(ins PredRegs:$Pu4, IntRegs:$Rs32),
5271"if (!$Pu4) jumpr:t $Rs32",
5272tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5273let Inst{7-0} = 0b00000000;
5274let Inst{13-10} = 0b0100;
5275let Inst{31-21} = 0b01010011011;
5276let isPredicated = 1;
5277let isPredicatedFalse = 1;
5278let isTerminator = 1;
5279let isIndirectBranch = 1;
5280let isBranch = 1;
5281let cofMax1 = 1;
5282let Defs = [PC];
5283let BaseOpcode = "J2_jumpr";
5284let InputType = "reg";
5285let isTaken = Inst{12};
5286}
5287def J2_jumprgtez : HInst<
5288(outs),
5289(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5290"if ($Rs32>=#0) jump:nt $Ii",
5291tc_57a55b54, TypeCR>, Enc_0fa531 {
5292let Inst{0-0} = 0b0;
5293let Inst{12-12} = 0b0;
5294let Inst{31-22} = 0b0110000101;
5295let isPredicated = 1;
5296let isTerminator = 1;
5297let isBranch = 1;
5298let isPredicatedNew = 1;
5299let cofRelax1 = 1;
5300let cofRelax2 = 1;
5301let cofMax1 = 1;
5302let Defs = [PC];
5303let isTaken = Inst{12};
5304}
5305def J2_jumprgtezpt : HInst<
5306(outs),
5307(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5308"if ($Rs32>=#0) jump:t $Ii",
5309tc_57a55b54, TypeCR>, Enc_0fa531 {
5310let Inst{0-0} = 0b0;
5311let Inst{12-12} = 0b1;
5312let Inst{31-22} = 0b0110000101;
5313let isPredicated = 1;
5314let isTerminator = 1;
5315let isBranch = 1;
5316let isPredicatedNew = 1;
5317let cofRelax1 = 1;
5318let cofRelax2 = 1;
5319let cofMax1 = 1;
5320let Defs = [PC];
5321let isTaken = Inst{12};
5322}
5323def J2_jumprh : HInst<
5324(outs),
5325(ins IntRegs:$Rs32),
5326"jumprh $Rs32",
5327tc_f97707c1, TypeJ>, Enc_ecbcc8, Requires<[HasV73]> {
5328let Inst{13-0} = 0b00000000000000;
5329let Inst{31-21} = 0b01010010110;
5330let isTerminator = 1;
5331let isIndirectBranch = 1;
5332let isBranch = 1;
5333let cofMax1 = 1;
5334let Defs = [PC];
5335}
5336def J2_jumprltez : HInst<
5337(outs),
5338(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5339"if ($Rs32<=#0) jump:nt $Ii",
5340tc_57a55b54, TypeCR>, Enc_0fa531 {
5341let Inst{0-0} = 0b0;
5342let Inst{12-12} = 0b0;
5343let Inst{31-22} = 0b0110000111;
5344let isPredicated = 1;
5345let isTerminator = 1;
5346let isBranch = 1;
5347let isPredicatedNew = 1;
5348let cofRelax1 = 1;
5349let cofRelax2 = 1;
5350let cofMax1 = 1;
5351let Defs = [PC];
5352let isTaken = Inst{12};
5353}
5354def J2_jumprltezpt : HInst<
5355(outs),
5356(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5357"if ($Rs32<=#0) jump:t $Ii",
5358tc_57a55b54, TypeCR>, Enc_0fa531 {
5359let Inst{0-0} = 0b0;
5360let Inst{12-12} = 0b1;
5361let Inst{31-22} = 0b0110000111;
5362let isPredicated = 1;
5363let isTerminator = 1;
5364let isBranch = 1;
5365let isPredicatedNew = 1;
5366let cofRelax1 = 1;
5367let cofRelax2 = 1;
5368let cofMax1 = 1;
5369let Defs = [PC];
5370let isTaken = Inst{12};
5371}
5372def J2_jumprnz : HInst<
5373(outs),
5374(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5375"if ($Rs32==#0) jump:nt $Ii",
5376tc_57a55b54, TypeCR>, Enc_0fa531 {
5377let Inst{0-0} = 0b0;
5378let Inst{12-12} = 0b0;
5379let Inst{31-22} = 0b0110000110;
5380let isPredicated = 1;
5381let isTerminator = 1;
5382let isBranch = 1;
5383let isPredicatedNew = 1;
5384let cofRelax1 = 1;
5385let cofRelax2 = 1;
5386let cofMax1 = 1;
5387let Defs = [PC];
5388let isTaken = Inst{12};
5389}
5390def J2_jumprnzpt : HInst<
5391(outs),
5392(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5393"if ($Rs32==#0) jump:t $Ii",
5394tc_57a55b54, TypeCR>, Enc_0fa531 {
5395let Inst{0-0} = 0b0;
5396let Inst{12-12} = 0b1;
5397let Inst{31-22} = 0b0110000110;
5398let isPredicated = 1;
5399let isTerminator = 1;
5400let isBranch = 1;
5401let isPredicatedNew = 1;
5402let cofRelax1 = 1;
5403let cofRelax2 = 1;
5404let cofMax1 = 1;
5405let Defs = [PC];
5406let isTaken = Inst{12};
5407}
5408def J2_jumprt : HInst<
5409(outs),
5410(ins PredRegs:$Pu4, IntRegs:$Rs32),
5411"if ($Pu4) jumpr:nt $Rs32",
5412tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5413let Inst{7-0} = 0b00000000;
5414let Inst{13-10} = 0b0000;
5415let Inst{31-21} = 0b01010011010;
5416let isPredicated = 1;
5417let isTerminator = 1;
5418let isIndirectBranch = 1;
5419let isBranch = 1;
5420let cofMax1 = 1;
5421let Defs = [PC];
5422let BaseOpcode = "J2_jumpr";
5423let InputType = "reg";
5424let isTaken = Inst{12};
5425}
5426def J2_jumprt_nopred_map : HInst<
5427(outs),
5428(ins PredRegs:$Pu4, IntRegs:$Rs32),
5429"if ($Pu4) jumpr $Rs32",
5430tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5431let isPseudo = 1;
5432let isCodeGenOnly = 1;
5433}
5434def J2_jumprtnew : HInst<
5435(outs),
5436(ins PredRegs:$Pu4, IntRegs:$Rs32),
5437"if ($Pu4.new) jumpr:nt $Rs32",
5438tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5439let Inst{7-0} = 0b00000000;
5440let Inst{13-10} = 0b0010;
5441let Inst{31-21} = 0b01010011010;
5442let isPredicated = 1;
5443let isTerminator = 1;
5444let isIndirectBranch = 1;
5445let isBranch = 1;
5446let isPredicatedNew = 1;
5447let cofMax1 = 1;
5448let Defs = [PC];
5449let BaseOpcode = "J2_jumpr";
5450let InputType = "reg";
5451let isTaken = Inst{12};
5452}
5453def J2_jumprtnewpt : HInst<
5454(outs),
5455(ins PredRegs:$Pu4, IntRegs:$Rs32),
5456"if ($Pu4.new) jumpr:t $Rs32",
5457tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5458let Inst{7-0} = 0b00000000;
5459let Inst{13-10} = 0b0110;
5460let Inst{31-21} = 0b01010011010;
5461let isPredicated = 1;
5462let isTerminator = 1;
5463let isIndirectBranch = 1;
5464let isBranch = 1;
5465let isPredicatedNew = 1;
5466let cofMax1 = 1;
5467let Defs = [PC];
5468let BaseOpcode = "J2_jumpr";
5469let InputType = "reg";
5470let isTaken = Inst{12};
5471}
5472def J2_jumprtpt : HInst<
5473(outs),
5474(ins PredRegs:$Pu4, IntRegs:$Rs32),
5475"if ($Pu4) jumpr:t $Rs32",
5476tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5477let Inst{7-0} = 0b00000000;
5478let Inst{13-10} = 0b0100;
5479let Inst{31-21} = 0b01010011010;
5480let isPredicated = 1;
5481let isTerminator = 1;
5482let isIndirectBranch = 1;
5483let isBranch = 1;
5484let cofMax1 = 1;
5485let Defs = [PC];
5486let BaseOpcode = "J2_jumpr";
5487let InputType = "reg";
5488let isTaken = Inst{12};
5489}
5490def J2_jumprz : HInst<
5491(outs),
5492(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5493"if ($Rs32!=#0) jump:nt $Ii",
5494tc_57a55b54, TypeCR>, Enc_0fa531 {
5495let Inst{0-0} = 0b0;
5496let Inst{12-12} = 0b0;
5497let Inst{31-22} = 0b0110000100;
5498let isPredicated = 1;
5499let isTerminator = 1;
5500let isBranch = 1;
5501let isPredicatedNew = 1;
5502let cofRelax1 = 1;
5503let cofRelax2 = 1;
5504let cofMax1 = 1;
5505let Defs = [PC];
5506let isTaken = Inst{12};
5507}
5508def J2_jumprzpt : HInst<
5509(outs),
5510(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5511"if ($Rs32!=#0) jump:t $Ii",
5512tc_57a55b54, TypeCR>, Enc_0fa531 {
5513let Inst{0-0} = 0b0;
5514let Inst{12-12} = 0b1;
5515let Inst{31-22} = 0b0110000100;
5516let isPredicated = 1;
5517let isTerminator = 1;
5518let isBranch = 1;
5519let isPredicatedNew = 1;
5520let cofRelax1 = 1;
5521let cofRelax2 = 1;
5522let cofMax1 = 1;
5523let Defs = [PC];
5524let isTaken = Inst{12};
5525}
5526def J2_jumpt : HInst<
5527(outs),
5528(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5529"if ($Pu4) jump:nt $Ii",
5530tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5531let Inst{0-0} = 0b0;
5532let Inst{12-10} = 0b000;
5533let Inst{21-21} = 0b0;
5534let Inst{31-24} = 0b01011100;
5535let isPredicated = 1;
5536let isTerminator = 1;
5537let isBranch = 1;
5538let cofRelax1 = 1;
5539let cofRelax2 = 1;
5540let cofMax1 = 1;
5541let Defs = [PC];
5542let BaseOpcode = "J2_jump";
5543let InputType = "imm";
5544let isTaken = Inst{12};
5545let isExtendable = 1;
5546let opExtendable = 1;
5547let isExtentSigned = 1;
5548let opExtentBits = 17;
5549let opExtentAlign = 2;
5550}
5551def J2_jumpt_nopred_map : HInst<
5552(outs),
5553(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5554"if ($Pu4) jump $Ii",
5555tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5556let isPseudo = 1;
5557let isCodeGenOnly = 1;
5558}
5559def J2_jumptnew : HInst<
5560(outs),
5561(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5562"if ($Pu4.new) jump:nt $Ii",
5563tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5564let Inst{0-0} = 0b0;
5565let Inst{12-10} = 0b010;
5566let Inst{21-21} = 0b0;
5567let Inst{31-24} = 0b01011100;
5568let isPredicated = 1;
5569let isTerminator = 1;
5570let isBranch = 1;
5571let isPredicatedNew = 1;
5572let cofRelax1 = 1;
5573let cofRelax2 = 1;
5574let cofMax1 = 1;
5575let Defs = [PC];
5576let BaseOpcode = "J2_jump";
5577let InputType = "imm";
5578let isTaken = Inst{12};
5579let isExtendable = 1;
5580let opExtendable = 1;
5581let isExtentSigned = 1;
5582let opExtentBits = 17;
5583let opExtentAlign = 2;
5584}
5585def J2_jumptnewpt : HInst<
5586(outs),
5587(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5588"if ($Pu4.new) jump:t $Ii",
5589tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5590let Inst{0-0} = 0b0;
5591let Inst{12-10} = 0b110;
5592let Inst{21-21} = 0b0;
5593let Inst{31-24} = 0b01011100;
5594let isPredicated = 1;
5595let isTerminator = 1;
5596let isBranch = 1;
5597let isPredicatedNew = 1;
5598let cofRelax1 = 1;
5599let cofRelax2 = 1;
5600let cofMax1 = 1;
5601let Defs = [PC];
5602let BaseOpcode = "J2_jump";
5603let InputType = "imm";
5604let isTaken = Inst{12};
5605let isExtendable = 1;
5606let opExtendable = 1;
5607let isExtentSigned = 1;
5608let opExtentBits = 17;
5609let opExtentAlign = 2;
5610}
5611def J2_jumptpt : HInst<
5612(outs),
5613(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5614"if ($Pu4) jump:t $Ii",
5615tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5616let Inst{0-0} = 0b0;
5617let Inst{12-10} = 0b100;
5618let Inst{21-21} = 0b0;
5619let Inst{31-24} = 0b01011100;
5620let isPredicated = 1;
5621let isTerminator = 1;
5622let isBranch = 1;
5623let cofRelax1 = 1;
5624let cofRelax2 = 1;
5625let cofMax1 = 1;
5626let Defs = [PC];
5627let BaseOpcode = "J2_jump";
5628let InputType = "imm";
5629let isTaken = Inst{12};
5630let isExtendable = 1;
5631let opExtendable = 1;
5632let isExtentSigned = 1;
5633let opExtentBits = 17;
5634let opExtentAlign = 2;
5635}
5636def J2_loop0i : HInst<
5637(outs),
5638(ins b30_2Imm:$Ii, u10_0Imm:$II),
5639"loop0($Ii,#$II)",
5640tc_1248597c, TypeCR>, Enc_4dc228 {
5641let Inst{2-2} = 0b0;
5642let Inst{13-13} = 0b0;
5643let Inst{31-21} = 0b01101001000;
5644let cofRelax1 = 1;
5645let cofRelax2 = 1;
5646let Defs = [LC0, SA0, USR];
5647let isExtendable = 1;
5648let opExtendable = 0;
5649let isExtentSigned = 1;
5650let opExtentBits = 9;
5651let opExtentAlign = 2;
5652}
5653def J2_loop0r : HInst<
5654(outs),
5655(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5656"loop0($Ii,$Rs32)",
5657tc_9406230a, TypeCR>, Enc_864a5a {
5658let Inst{2-0} = 0b000;
5659let Inst{7-5} = 0b000;
5660let Inst{13-13} = 0b0;
5661let Inst{31-21} = 0b01100000000;
5662let cofRelax1 = 1;
5663let cofRelax2 = 1;
5664let Defs = [LC0, SA0, USR];
5665let isExtendable = 1;
5666let opExtendable = 0;
5667let isExtentSigned = 1;
5668let opExtentBits = 9;
5669let opExtentAlign = 2;
5670}
5671def J2_loop1i : HInst<
5672(outs),
5673(ins b30_2Imm:$Ii, u10_0Imm:$II),
5674"loop1($Ii,#$II)",
5675tc_1248597c, TypeCR>, Enc_4dc228 {
5676let Inst{2-2} = 0b0;
5677let Inst{13-13} = 0b0;
5678let Inst{31-21} = 0b01101001001;
5679let cofRelax1 = 1;
5680let cofRelax2 = 1;
5681let Defs = [LC1, SA1];
5682let isExtendable = 1;
5683let opExtendable = 0;
5684let isExtentSigned = 1;
5685let opExtentBits = 9;
5686let opExtentAlign = 2;
5687}
5688def J2_loop1r : HInst<
5689(outs),
5690(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5691"loop1($Ii,$Rs32)",
5692tc_9406230a, TypeCR>, Enc_864a5a {
5693let Inst{2-0} = 0b000;
5694let Inst{7-5} = 0b000;
5695let Inst{13-13} = 0b0;
5696let Inst{31-21} = 0b01100000001;
5697let cofRelax1 = 1;
5698let cofRelax2 = 1;
5699let Defs = [LC1, SA1];
5700let isExtendable = 1;
5701let opExtendable = 0;
5702let isExtentSigned = 1;
5703let opExtentBits = 9;
5704let opExtentAlign = 2;
5705}
5706def J2_pause : HInst<
5707(outs),
5708(ins u10_0Imm:$Ii),
5709"pause(#$Ii)",
5710tc_d57d649c, TypeJ>, Enc_bea5da {
5711let Inst{1-0} = 0b00;
5712let Inst{7-5} = 0b000;
5713let Inst{13-13} = 0b0;
5714let Inst{31-18} = 0b01010100010000;
5715let isSolo = 1;
5716}
5717def J2_ploop1si : HInst<
5718(outs),
5719(ins b30_2Imm:$Ii, u10_0Imm:$II),
5720"p3 = sp1loop0($Ii,#$II)",
5721tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5722let Inst{2-2} = 0b0;
5723let Inst{13-13} = 0b0;
5724let Inst{31-21} = 0b01101001101;
5725let isPredicateLate = 1;
5726let cofRelax1 = 1;
5727let cofRelax2 = 1;
5728let Defs = [LC0, P3, SA0, USR];
5729let isExtendable = 1;
5730let opExtendable = 0;
5731let isExtentSigned = 1;
5732let opExtentBits = 9;
5733let opExtentAlign = 2;
5734}
5735def J2_ploop1sr : HInst<
5736(outs),
5737(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5738"p3 = sp1loop0($Ii,$Rs32)",
5739tc_6d861a95, TypeCR>, Enc_864a5a {
5740let Inst{2-0} = 0b000;
5741let Inst{7-5} = 0b000;
5742let Inst{13-13} = 0b0;
5743let Inst{31-21} = 0b01100000101;
5744let isPredicateLate = 1;
5745let cofRelax1 = 1;
5746let cofRelax2 = 1;
5747let Defs = [LC0, P3, SA0, USR];
5748let isExtendable = 1;
5749let opExtendable = 0;
5750let isExtentSigned = 1;
5751let opExtentBits = 9;
5752let opExtentAlign = 2;
5753}
5754def J2_ploop2si : HInst<
5755(outs),
5756(ins b30_2Imm:$Ii, u10_0Imm:$II),
5757"p3 = sp2loop0($Ii,#$II)",
5758tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5759let Inst{2-2} = 0b0;
5760let Inst{13-13} = 0b0;
5761let Inst{31-21} = 0b01101001110;
5762let isPredicateLate = 1;
5763let cofRelax1 = 1;
5764let cofRelax2 = 1;
5765let Defs = [LC0, P3, SA0, USR];
5766let isExtendable = 1;
5767let opExtendable = 0;
5768let isExtentSigned = 1;
5769let opExtentBits = 9;
5770let opExtentAlign = 2;
5771}
5772def J2_ploop2sr : HInst<
5773(outs),
5774(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5775"p3 = sp2loop0($Ii,$Rs32)",
5776tc_6d861a95, TypeCR>, Enc_864a5a {
5777let Inst{2-0} = 0b000;
5778let Inst{7-5} = 0b000;
5779let Inst{13-13} = 0b0;
5780let Inst{31-21} = 0b01100000110;
5781let isPredicateLate = 1;
5782let cofRelax1 = 1;
5783let cofRelax2 = 1;
5784let Defs = [LC0, P3, SA0, USR];
5785let isExtendable = 1;
5786let opExtendable = 0;
5787let isExtentSigned = 1;
5788let opExtentBits = 9;
5789let opExtentAlign = 2;
5790}
5791def J2_ploop3si : HInst<
5792(outs),
5793(ins b30_2Imm:$Ii, u10_0Imm:$II),
5794"p3 = sp3loop0($Ii,#$II)",
5795tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5796let Inst{2-2} = 0b0;
5797let Inst{13-13} = 0b0;
5798let Inst{31-21} = 0b01101001111;
5799let isPredicateLate = 1;
5800let cofRelax1 = 1;
5801let cofRelax2 = 1;
5802let Defs = [LC0, P3, SA0, USR];
5803let isExtendable = 1;
5804let opExtendable = 0;
5805let isExtentSigned = 1;
5806let opExtentBits = 9;
5807let opExtentAlign = 2;
5808}
5809def J2_ploop3sr : HInst<
5810(outs),
5811(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5812"p3 = sp3loop0($Ii,$Rs32)",
5813tc_6d861a95, TypeCR>, Enc_864a5a {
5814let Inst{2-0} = 0b000;
5815let Inst{7-5} = 0b000;
5816let Inst{13-13} = 0b0;
5817let Inst{31-21} = 0b01100000111;
5818let isPredicateLate = 1;
5819let cofRelax1 = 1;
5820let cofRelax2 = 1;
5821let Defs = [LC0, P3, SA0, USR];
5822let isExtendable = 1;
5823let opExtendable = 0;
5824let isExtentSigned = 1;
5825let opExtentBits = 9;
5826let opExtentAlign = 2;
5827}
5828def J2_rte : HInst<
5829(outs),
5830(ins),
5831"rte",
5832tc_b9bec29e, TypeJ>, Enc_e3b0c4 {
5833let Inst{13-0} = 0b00000000000000;
5834let Inst{31-16} = 0b0101011111100000;
5835let Uses = [ELR];
5836let Defs = [PC];
5837}
5838def J2_trap0 : HInst<
5839(outs),
5840(ins u8_0Imm:$Ii),
5841"trap0(#$Ii)",
5842tc_45f9d1be, TypeJ>, Enc_a51a9a {
5843let Inst{1-0} = 0b00;
5844let Inst{7-5} = 0b000;
5845let Inst{13-13} = 0b0;
5846let Inst{31-16} = 0b0101010000000000;
5847let isSolo = 1;
5848let hasSideEffects = 1;
5849}
5850def J2_trap1 : HInst<
5851(outs IntRegs:$Rx32),
5852(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
5853"trap1($Rx32,#$Ii)",
5854tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> {
5855let Inst{1-0} = 0b00;
5856let Inst{7-5} = 0b000;
5857let Inst{13-13} = 0b0;
5858let Inst{31-21} = 0b01010100100;
5859let hasNewValue = 1;
5860let opNewValue = 0;
5861let isSolo = 1;
5862let Uses = [CCR, GOSP];
5863let Defs = [CCR, GOSP, PC];
5864let hasSideEffects = 1;
5865let Constraints = "$Rx32 = $Rx32in";
5866}
5867def J2_trap1_noregmap : HInst<
5868(outs),
5869(ins u8_0Imm:$Ii),
5870"trap1(#$Ii)",
5871tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> {
5872let hasSideEffects = 1;
5873let isPseudo = 1;
5874let isCodeGenOnly = 1;
5875}
5876def J2_unpause : HInst<
5877(outs),
5878(ins),
5879"unpause",
5880tc_33e7e673, TypeJ>, Enc_e3b0c4, Requires<[HasV73]> {
5881let Inst{13-0} = 0b01000000000000;
5882let Inst{31-16} = 0b0101011111100000;
5883let isSolo = 1;
5884}
5885def J4_cmpeq_f_jumpnv_nt : HInst<
5886(outs),
5887(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5888"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5889tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5890let Inst{0-0} = 0b0;
5891let Inst{13-13} = 0b0;
5892let Inst{19-19} = 0b0;
5893let Inst{31-22} = 0b0010000001;
5894let isPredicated = 1;
5895let isPredicatedFalse = 1;
5896let isTerminator = 1;
5897let isBranch = 1;
5898let isNewValue = 1;
5899let cofMax1 = 1;
5900let isRestrictNoSlot1Store = 1;
5901let Defs = [PC];
5902let BaseOpcode = "J4_cmpeqr";
5903let isTaken = Inst{13};
5904let isExtendable = 1;
5905let opExtendable = 2;
5906let isExtentSigned = 1;
5907let opExtentBits = 11;
5908let opExtentAlign = 2;
5909let opNewValue = 0;
5910}
5911def J4_cmpeq_f_jumpnv_t : HInst<
5912(outs),
5913(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5914"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5915tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5916let Inst{0-0} = 0b0;
5917let Inst{13-13} = 0b1;
5918let Inst{19-19} = 0b0;
5919let Inst{31-22} = 0b0010000001;
5920let isPredicated = 1;
5921let isPredicatedFalse = 1;
5922let isTerminator = 1;
5923let isBranch = 1;
5924let isNewValue = 1;
5925let cofMax1 = 1;
5926let isRestrictNoSlot1Store = 1;
5927let Defs = [PC];
5928let BaseOpcode = "J4_cmpeqr";
5929let isTaken = Inst{13};
5930let isExtendable = 1;
5931let opExtendable = 2;
5932let isExtentSigned = 1;
5933let opExtentBits = 11;
5934let opExtentAlign = 2;
5935let opNewValue = 0;
5936}
5937def J4_cmpeq_fp0_jump_nt : HInst<
5938(outs),
5939(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5940"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
5941tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5942let Inst{0-0} = 0b0;
5943let Inst{13-12} = 0b00;
5944let Inst{31-22} = 0b0001010001;
5945let isPredicated = 1;
5946let isPredicatedFalse = 1;
5947let isTerminator = 1;
5948let isBranch = 1;
5949let isPredicatedNew = 1;
5950let cofRelax1 = 1;
5951let cofRelax2 = 1;
5952let cofMax1 = 1;
5953let Uses = [P0];
5954let Defs = [P0, PC];
5955let BaseOpcode = "J4_cmpeqp0";
5956let isTaken = Inst{13};
5957let isExtendable = 1;
5958let opExtendable = 2;
5959let isExtentSigned = 1;
5960let opExtentBits = 11;
5961let opExtentAlign = 2;
5962}
5963def J4_cmpeq_fp0_jump_t : HInst<
5964(outs),
5965(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5966"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
5967tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5968let Inst{0-0} = 0b0;
5969let Inst{13-12} = 0b10;
5970let Inst{31-22} = 0b0001010001;
5971let isPredicated = 1;
5972let isPredicatedFalse = 1;
5973let isTerminator = 1;
5974let isBranch = 1;
5975let isPredicatedNew = 1;
5976let cofRelax1 = 1;
5977let cofRelax2 = 1;
5978let cofMax1 = 1;
5979let Uses = [P0];
5980let Defs = [P0, PC];
5981let BaseOpcode = "J4_cmpeqp0";
5982let isTaken = Inst{13};
5983let isExtendable = 1;
5984let opExtendable = 2;
5985let isExtentSigned = 1;
5986let opExtentBits = 11;
5987let opExtentAlign = 2;
5988}
5989def J4_cmpeq_fp1_jump_nt : HInst<
5990(outs),
5991(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5992"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
5993tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5994let Inst{0-0} = 0b0;
5995let Inst{13-12} = 0b01;
5996let Inst{31-22} = 0b0001010001;
5997let isPredicated = 1;
5998let isPredicatedFalse = 1;
5999let isTerminator = 1;
6000let isBranch = 1;
6001let isPredicatedNew = 1;
6002let cofRelax1 = 1;
6003let cofRelax2 = 1;
6004let cofMax1 = 1;
6005let Uses = [P1];
6006let Defs = [P1, PC];
6007let BaseOpcode = "J4_cmpeqp1";
6008let isTaken = Inst{13};
6009let isExtendable = 1;
6010let opExtendable = 2;
6011let isExtentSigned = 1;
6012let opExtentBits = 11;
6013let opExtentAlign = 2;
6014}
6015def J4_cmpeq_fp1_jump_t : HInst<
6016(outs),
6017(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6018"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6019tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6020let Inst{0-0} = 0b0;
6021let Inst{13-12} = 0b11;
6022let Inst{31-22} = 0b0001010001;
6023let isPredicated = 1;
6024let isPredicatedFalse = 1;
6025let isTerminator = 1;
6026let isBranch = 1;
6027let isPredicatedNew = 1;
6028let cofRelax1 = 1;
6029let cofRelax2 = 1;
6030let cofMax1 = 1;
6031let Uses = [P1];
6032let Defs = [P1, PC];
6033let BaseOpcode = "J4_cmpeqp1";
6034let isTaken = Inst{13};
6035let isExtendable = 1;
6036let opExtendable = 2;
6037let isExtentSigned = 1;
6038let opExtentBits = 11;
6039let opExtentAlign = 2;
6040}
6041def J4_cmpeq_t_jumpnv_nt : HInst<
6042(outs),
6043(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6044"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
6045tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6046let Inst{0-0} = 0b0;
6047let Inst{13-13} = 0b0;
6048let Inst{19-19} = 0b0;
6049let Inst{31-22} = 0b0010000000;
6050let isPredicated = 1;
6051let isTerminator = 1;
6052let isBranch = 1;
6053let isNewValue = 1;
6054let cofMax1 = 1;
6055let isRestrictNoSlot1Store = 1;
6056let Defs = [PC];
6057let BaseOpcode = "J4_cmpeqr";
6058let isTaken = Inst{13};
6059let isExtendable = 1;
6060let opExtendable = 2;
6061let isExtentSigned = 1;
6062let opExtentBits = 11;
6063let opExtentAlign = 2;
6064let opNewValue = 0;
6065}
6066def J4_cmpeq_t_jumpnv_t : HInst<
6067(outs),
6068(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6069"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
6070tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6071let Inst{0-0} = 0b0;
6072let Inst{13-13} = 0b1;
6073let Inst{19-19} = 0b0;
6074let Inst{31-22} = 0b0010000000;
6075let isPredicated = 1;
6076let isTerminator = 1;
6077let isBranch = 1;
6078let isNewValue = 1;
6079let cofMax1 = 1;
6080let isRestrictNoSlot1Store = 1;
6081let Defs = [PC];
6082let BaseOpcode = "J4_cmpeqr";
6083let isTaken = Inst{13};
6084let isExtendable = 1;
6085let opExtendable = 2;
6086let isExtentSigned = 1;
6087let opExtentBits = 11;
6088let opExtentAlign = 2;
6089let opNewValue = 0;
6090}
6091def J4_cmpeq_tp0_jump_nt : HInst<
6092(outs),
6093(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6094"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6095tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6096let Inst{0-0} = 0b0;
6097let Inst{13-12} = 0b00;
6098let Inst{31-22} = 0b0001010000;
6099let isPredicated = 1;
6100let isTerminator = 1;
6101let isBranch = 1;
6102let isPredicatedNew = 1;
6103let cofRelax1 = 1;
6104let cofRelax2 = 1;
6105let cofMax1 = 1;
6106let Uses = [P0];
6107let Defs = [P0, PC];
6108let BaseOpcode = "J4_cmpeqp0";
6109let isTaken = Inst{13};
6110let isExtendable = 1;
6111let opExtendable = 2;
6112let isExtentSigned = 1;
6113let opExtentBits = 11;
6114let opExtentAlign = 2;
6115}
6116def J4_cmpeq_tp0_jump_t : HInst<
6117(outs),
6118(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6119"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6120tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6121let Inst{0-0} = 0b0;
6122let Inst{13-12} = 0b10;
6123let Inst{31-22} = 0b0001010000;
6124let isPredicated = 1;
6125let isTerminator = 1;
6126let isBranch = 1;
6127let isPredicatedNew = 1;
6128let cofRelax1 = 1;
6129let cofRelax2 = 1;
6130let cofMax1 = 1;
6131let Uses = [P0];
6132let Defs = [P0, PC];
6133let BaseOpcode = "J4_cmpeqp0";
6134let isTaken = Inst{13};
6135let isExtendable = 1;
6136let opExtendable = 2;
6137let isExtentSigned = 1;
6138let opExtentBits = 11;
6139let opExtentAlign = 2;
6140}
6141def J4_cmpeq_tp1_jump_nt : HInst<
6142(outs),
6143(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6144"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
6145tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6146let Inst{0-0} = 0b0;
6147let Inst{13-12} = 0b01;
6148let Inst{31-22} = 0b0001010000;
6149let isPredicated = 1;
6150let isTerminator = 1;
6151let isBranch = 1;
6152let isPredicatedNew = 1;
6153let cofRelax1 = 1;
6154let cofRelax2 = 1;
6155let cofMax1 = 1;
6156let Uses = [P1];
6157let Defs = [P1, PC];
6158let BaseOpcode = "J4_cmpeqp1";
6159let isTaken = Inst{13};
6160let isExtendable = 1;
6161let opExtendable = 2;
6162let isExtentSigned = 1;
6163let opExtentBits = 11;
6164let opExtentAlign = 2;
6165}
6166def J4_cmpeq_tp1_jump_t : HInst<
6167(outs),
6168(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6169"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6170tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6171let Inst{0-0} = 0b0;
6172let Inst{13-12} = 0b11;
6173let Inst{31-22} = 0b0001010000;
6174let isPredicated = 1;
6175let isTerminator = 1;
6176let isBranch = 1;
6177let isPredicatedNew = 1;
6178let cofRelax1 = 1;
6179let cofRelax2 = 1;
6180let cofMax1 = 1;
6181let Uses = [P1];
6182let Defs = [P1, PC];
6183let BaseOpcode = "J4_cmpeqp1";
6184let isTaken = Inst{13};
6185let isExtendable = 1;
6186let opExtendable = 2;
6187let isExtentSigned = 1;
6188let opExtentBits = 11;
6189let opExtentAlign = 2;
6190}
6191def J4_cmpeqi_f_jumpnv_nt : HInst<
6192(outs),
6193(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6194"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6195tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6196let Inst{0-0} = 0b0;
6197let Inst{13-13} = 0b0;
6198let Inst{19-19} = 0b0;
6199let Inst{31-22} = 0b0010010001;
6200let isPredicated = 1;
6201let isPredicatedFalse = 1;
6202let isTerminator = 1;
6203let isBranch = 1;
6204let isNewValue = 1;
6205let cofMax1 = 1;
6206let isRestrictNoSlot1Store = 1;
6207let Defs = [PC];
6208let BaseOpcode = "J4_cmpeqi";
6209let isTaken = Inst{13};
6210let isExtendable = 1;
6211let opExtendable = 2;
6212let isExtentSigned = 1;
6213let opExtentBits = 11;
6214let opExtentAlign = 2;
6215let opNewValue = 0;
6216}
6217def J4_cmpeqi_f_jumpnv_t : HInst<
6218(outs),
6219(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6220"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6221tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6222let Inst{0-0} = 0b0;
6223let Inst{13-13} = 0b1;
6224let Inst{19-19} = 0b0;
6225let Inst{31-22} = 0b0010010001;
6226let isPredicated = 1;
6227let isPredicatedFalse = 1;
6228let isTerminator = 1;
6229let isBranch = 1;
6230let isNewValue = 1;
6231let cofMax1 = 1;
6232let isRestrictNoSlot1Store = 1;
6233let Defs = [PC];
6234let BaseOpcode = "J4_cmpeqi";
6235let isTaken = Inst{13};
6236let isExtendable = 1;
6237let opExtendable = 2;
6238let isExtentSigned = 1;
6239let opExtentBits = 11;
6240let opExtentAlign = 2;
6241let opNewValue = 0;
6242}
6243def J4_cmpeqi_fp0_jump_nt : HInst<
6244(outs),
6245(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6246"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
6247tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6248let Inst{0-0} = 0b0;
6249let Inst{13-13} = 0b0;
6250let Inst{31-22} = 0b0001000001;
6251let isPredicated = 1;
6252let isPredicatedFalse = 1;
6253let isTerminator = 1;
6254let isBranch = 1;
6255let isPredicatedNew = 1;
6256let cofRelax1 = 1;
6257let cofRelax2 = 1;
6258let cofMax1 = 1;
6259let Uses = [P0];
6260let Defs = [P0, PC];
6261let BaseOpcode = "J4_cmpeqip0";
6262let isTaken = Inst{13};
6263let isExtendable = 1;
6264let opExtendable = 2;
6265let isExtentSigned = 1;
6266let opExtentBits = 11;
6267let opExtentAlign = 2;
6268}
6269def J4_cmpeqi_fp0_jump_t : HInst<
6270(outs),
6271(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6272"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
6273tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6274let Inst{0-0} = 0b0;
6275let Inst{13-13} = 0b1;
6276let Inst{31-22} = 0b0001000001;
6277let isPredicated = 1;
6278let isPredicatedFalse = 1;
6279let isTerminator = 1;
6280let isBranch = 1;
6281let isPredicatedNew = 1;
6282let cofRelax1 = 1;
6283let cofRelax2 = 1;
6284let cofMax1 = 1;
6285let Uses = [P0];
6286let Defs = [P0, PC];
6287let BaseOpcode = "J4_cmpeqip0";
6288let isTaken = Inst{13};
6289let isExtendable = 1;
6290let opExtendable = 2;
6291let isExtentSigned = 1;
6292let opExtentBits = 11;
6293let opExtentAlign = 2;
6294}
6295def J4_cmpeqi_fp1_jump_nt : HInst<
6296(outs),
6297(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6298"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6299tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6300let Inst{0-0} = 0b0;
6301let Inst{13-13} = 0b0;
6302let Inst{31-22} = 0b0001001001;
6303let isPredicated = 1;
6304let isPredicatedFalse = 1;
6305let isTerminator = 1;
6306let isBranch = 1;
6307let isPredicatedNew = 1;
6308let cofRelax1 = 1;
6309let cofRelax2 = 1;
6310let cofMax1 = 1;
6311let Uses = [P1];
6312let Defs = [P1, PC];
6313let BaseOpcode = "J4_cmpeqip1";
6314let isTaken = Inst{13};
6315let isExtendable = 1;
6316let opExtendable = 2;
6317let isExtentSigned = 1;
6318let opExtentBits = 11;
6319let opExtentAlign = 2;
6320}
6321def J4_cmpeqi_fp1_jump_t : HInst<
6322(outs),
6323(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6324"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
6325tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6326let Inst{0-0} = 0b0;
6327let Inst{13-13} = 0b1;
6328let Inst{31-22} = 0b0001001001;
6329let isPredicated = 1;
6330let isPredicatedFalse = 1;
6331let isTerminator = 1;
6332let isBranch = 1;
6333let isPredicatedNew = 1;
6334let cofRelax1 = 1;
6335let cofRelax2 = 1;
6336let cofMax1 = 1;
6337let Uses = [P1];
6338let Defs = [P1, PC];
6339let BaseOpcode = "J4_cmpeqip1";
6340let isTaken = Inst{13};
6341let isExtendable = 1;
6342let opExtendable = 2;
6343let isExtentSigned = 1;
6344let opExtentBits = 11;
6345let opExtentAlign = 2;
6346}
6347def J4_cmpeqi_t_jumpnv_nt : HInst<
6348(outs),
6349(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6350"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6351tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6352let Inst{0-0} = 0b0;
6353let Inst{13-13} = 0b0;
6354let Inst{19-19} = 0b0;
6355let Inst{31-22} = 0b0010010000;
6356let isPredicated = 1;
6357let isTerminator = 1;
6358let isBranch = 1;
6359let isNewValue = 1;
6360let cofMax1 = 1;
6361let isRestrictNoSlot1Store = 1;
6362let Defs = [PC];
6363let BaseOpcode = "J4_cmpeqi";
6364let isTaken = Inst{13};
6365let isExtendable = 1;
6366let opExtendable = 2;
6367let isExtentSigned = 1;
6368let opExtentBits = 11;
6369let opExtentAlign = 2;
6370let opNewValue = 0;
6371}
6372def J4_cmpeqi_t_jumpnv_t : HInst<
6373(outs),
6374(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6375"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6376tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6377let Inst{0-0} = 0b0;
6378let Inst{13-13} = 0b1;
6379let Inst{19-19} = 0b0;
6380let Inst{31-22} = 0b0010010000;
6381let isPredicated = 1;
6382let isTerminator = 1;
6383let isBranch = 1;
6384let isNewValue = 1;
6385let cofMax1 = 1;
6386let isRestrictNoSlot1Store = 1;
6387let Defs = [PC];
6388let BaseOpcode = "J4_cmpeqi";
6389let isTaken = Inst{13};
6390let isExtendable = 1;
6391let opExtendable = 2;
6392let isExtentSigned = 1;
6393let opExtentBits = 11;
6394let opExtentAlign = 2;
6395let opNewValue = 0;
6396}
6397def J4_cmpeqi_tp0_jump_nt : HInst<
6398(outs),
6399(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6400"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
6401tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6402let Inst{0-0} = 0b0;
6403let Inst{13-13} = 0b0;
6404let Inst{31-22} = 0b0001000000;
6405let isPredicated = 1;
6406let isTerminator = 1;
6407let isBranch = 1;
6408let isPredicatedNew = 1;
6409let cofRelax1 = 1;
6410let cofRelax2 = 1;
6411let cofMax1 = 1;
6412let Uses = [P0];
6413let Defs = [P0, PC];
6414let BaseOpcode = "J4_cmpeqip0";
6415let isTaken = Inst{13};
6416let isExtendable = 1;
6417let opExtendable = 2;
6418let isExtentSigned = 1;
6419let opExtentBits = 11;
6420let opExtentAlign = 2;
6421}
6422def J4_cmpeqi_tp0_jump_t : HInst<
6423(outs),
6424(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6425"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
6426tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6427let Inst{0-0} = 0b0;
6428let Inst{13-13} = 0b1;
6429let Inst{31-22} = 0b0001000000;
6430let isPredicated = 1;
6431let isTerminator = 1;
6432let isBranch = 1;
6433let isPredicatedNew = 1;
6434let cofRelax1 = 1;
6435let cofRelax2 = 1;
6436let cofMax1 = 1;
6437let Uses = [P0];
6438let Defs = [P0, PC];
6439let BaseOpcode = "J4_cmpeqip0";
6440let isTaken = Inst{13};
6441let isExtendable = 1;
6442let opExtendable = 2;
6443let isExtentSigned = 1;
6444let opExtentBits = 11;
6445let opExtentAlign = 2;
6446}
6447def J4_cmpeqi_tp1_jump_nt : HInst<
6448(outs),
6449(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6450"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
6451tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6452let Inst{0-0} = 0b0;
6453let Inst{13-13} = 0b0;
6454let Inst{31-22} = 0b0001001000;
6455let isPredicated = 1;
6456let isTerminator = 1;
6457let isBranch = 1;
6458let isPredicatedNew = 1;
6459let cofRelax1 = 1;
6460let cofRelax2 = 1;
6461let cofMax1 = 1;
6462let Uses = [P1];
6463let Defs = [P1, PC];
6464let BaseOpcode = "J4_cmpeqip1";
6465let isTaken = Inst{13};
6466let isExtendable = 1;
6467let opExtendable = 2;
6468let isExtentSigned = 1;
6469let opExtentBits = 11;
6470let opExtentAlign = 2;
6471}
6472def J4_cmpeqi_tp1_jump_t : HInst<
6473(outs),
6474(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6475"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
6476tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6477let Inst{0-0} = 0b0;
6478let Inst{13-13} = 0b1;
6479let Inst{31-22} = 0b0001001000;
6480let isPredicated = 1;
6481let isTerminator = 1;
6482let isBranch = 1;
6483let isPredicatedNew = 1;
6484let cofRelax1 = 1;
6485let cofRelax2 = 1;
6486let cofMax1 = 1;
6487let Uses = [P1];
6488let Defs = [P1, PC];
6489let BaseOpcode = "J4_cmpeqip1";
6490let isTaken = Inst{13};
6491let isExtendable = 1;
6492let opExtendable = 2;
6493let isExtentSigned = 1;
6494let opExtentBits = 11;
6495let opExtentAlign = 2;
6496}
6497def J4_cmpeqn1_f_jumpnv_nt : HInst<
6498(outs),
6499(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6500"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6501tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel {
6502let Inst{0-0} = 0b0;
6503let Inst{13-8} = 0b000000;
6504let Inst{19-19} = 0b0;
6505let Inst{31-22} = 0b0010011001;
6506let isPredicated = 1;
6507let isPredicatedFalse = 1;
6508let isTerminator = 1;
6509let isBranch = 1;
6510let isNewValue = 1;
6511let cofMax1 = 1;
6512let isRestrictNoSlot1Store = 1;
6513let Defs = [PC];
6514let BaseOpcode = "J4_cmpeqn1r";
6515let isTaken = Inst{13};
6516let isExtendable = 1;
6517let opExtendable = 2;
6518let isExtentSigned = 1;
6519let opExtentBits = 11;
6520let opExtentAlign = 2;
6521let opNewValue = 0;
6522}
6523def J4_cmpeqn1_f_jumpnv_t : HInst<
6524(outs),
6525(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6526"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6527tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel {
6528let Inst{0-0} = 0b0;
6529let Inst{13-8} = 0b100000;
6530let Inst{19-19} = 0b0;
6531let Inst{31-22} = 0b0010011001;
6532let isPredicated = 1;
6533let isPredicatedFalse = 1;
6534let isTerminator = 1;
6535let isBranch = 1;
6536let isNewValue = 1;
6537let cofMax1 = 1;
6538let isRestrictNoSlot1Store = 1;
6539let Defs = [PC];
6540let BaseOpcode = "J4_cmpeqn1r";
6541let isTaken = Inst{13};
6542let isExtendable = 1;
6543let opExtendable = 2;
6544let isExtentSigned = 1;
6545let opExtentBits = 11;
6546let opExtentAlign = 2;
6547let opNewValue = 0;
6548}
6549def J4_cmpeqn1_fp0_jump_nt : HInst<
6550(outs),
6551(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6552"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
6553tc_24f426ab, TypeCJ>, Enc_1de724, PredRel {
6554let Inst{0-0} = 0b0;
6555let Inst{13-8} = 0b000000;
6556let Inst{31-22} = 0b0001000111;
6557let isPredicated = 1;
6558let isPredicatedFalse = 1;
6559let isTerminator = 1;
6560let isBranch = 1;
6561let isPredicatedNew = 1;
6562let cofRelax1 = 1;
6563let cofRelax2 = 1;
6564let cofMax1 = 1;
6565let Uses = [P0];
6566let Defs = [P0, PC];
6567let BaseOpcode = "J4_cmpeqn1p0";
6568let isTaken = Inst{13};
6569let isExtendable = 1;
6570let opExtendable = 2;
6571let isExtentSigned = 1;
6572let opExtentBits = 11;
6573let opExtentAlign = 2;
6574}
6575def J4_cmpeqn1_fp0_jump_t : HInst<
6576(outs),
6577(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6578"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
6579tc_24f426ab, TypeCJ>, Enc_14640c, PredRel {
6580let Inst{0-0} = 0b0;
6581let Inst{13-8} = 0b100000;
6582let Inst{31-22} = 0b0001000111;
6583let isPredicated = 1;
6584let isPredicatedFalse = 1;
6585let isTerminator = 1;
6586let isBranch = 1;
6587let isPredicatedNew = 1;
6588let cofRelax1 = 1;
6589let cofRelax2 = 1;
6590let cofMax1 = 1;
6591let Uses = [P0];
6592let Defs = [P0, PC];
6593let BaseOpcode = "J4_cmpeqn1p0";
6594let isTaken = Inst{13};
6595let isExtendable = 1;
6596let opExtendable = 2;
6597let isExtentSigned = 1;
6598let opExtentBits = 11;
6599let opExtentAlign = 2;
6600}
6601def J4_cmpeqn1_fp1_jump_nt : HInst<
6602(outs),
6603(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6604"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
6605tc_24f426ab, TypeCJ>, Enc_668704, PredRel {
6606let Inst{0-0} = 0b0;
6607let Inst{13-8} = 0b000000;
6608let Inst{31-22} = 0b0001001111;
6609let isPredicated = 1;
6610let isPredicatedFalse = 1;
6611let isTerminator = 1;
6612let isBranch = 1;
6613let isPredicatedNew = 1;
6614let cofRelax1 = 1;
6615let cofRelax2 = 1;
6616let cofMax1 = 1;
6617let Uses = [P1];
6618let Defs = [P1, PC];
6619let BaseOpcode = "J4_cmpeqn1p1";
6620let isTaken = Inst{13};
6621let isExtendable = 1;
6622let opExtendable = 2;
6623let isExtentSigned = 1;
6624let opExtentBits = 11;
6625let opExtentAlign = 2;
6626}
6627def J4_cmpeqn1_fp1_jump_t : HInst<
6628(outs),
6629(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6630"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
6631tc_24f426ab, TypeCJ>, Enc_800e04, PredRel {
6632let Inst{0-0} = 0b0;
6633let Inst{13-8} = 0b100000;
6634let Inst{31-22} = 0b0001001111;
6635let isPredicated = 1;
6636let isPredicatedFalse = 1;
6637let isTerminator = 1;
6638let isBranch = 1;
6639let isPredicatedNew = 1;
6640let cofRelax1 = 1;
6641let cofRelax2 = 1;
6642let cofMax1 = 1;
6643let Uses = [P1];
6644let Defs = [P1, PC];
6645let BaseOpcode = "J4_cmpeqn1p1";
6646let isTaken = Inst{13};
6647let isExtendable = 1;
6648let opExtendable = 2;
6649let isExtentSigned = 1;
6650let opExtentBits = 11;
6651let opExtentAlign = 2;
6652}
6653def J4_cmpeqn1_t_jumpnv_nt : HInst<
6654(outs),
6655(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6656"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6657tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel {
6658let Inst{0-0} = 0b0;
6659let Inst{13-8} = 0b000000;
6660let Inst{19-19} = 0b0;
6661let Inst{31-22} = 0b0010011000;
6662let isPredicated = 1;
6663let isTerminator = 1;
6664let isBranch = 1;
6665let isNewValue = 1;
6666let cofMax1 = 1;
6667let isRestrictNoSlot1Store = 1;
6668let Defs = [PC];
6669let BaseOpcode = "J4_cmpeqn1r";
6670let isTaken = Inst{13};
6671let isExtendable = 1;
6672let opExtendable = 2;
6673let isExtentSigned = 1;
6674let opExtentBits = 11;
6675let opExtentAlign = 2;
6676let opNewValue = 0;
6677}
6678def J4_cmpeqn1_t_jumpnv_t : HInst<
6679(outs),
6680(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6681"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6682tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel {
6683let Inst{0-0} = 0b0;
6684let Inst{13-8} = 0b100000;
6685let Inst{19-19} = 0b0;
6686let Inst{31-22} = 0b0010011000;
6687let isPredicated = 1;
6688let isTerminator = 1;
6689let isBranch = 1;
6690let isNewValue = 1;
6691let cofMax1 = 1;
6692let isRestrictNoSlot1Store = 1;
6693let Defs = [PC];
6694let BaseOpcode = "J4_cmpeqn1r";
6695let isTaken = Inst{13};
6696let isExtendable = 1;
6697let opExtendable = 2;
6698let isExtentSigned = 1;
6699let opExtentBits = 11;
6700let opExtentAlign = 2;
6701let opNewValue = 0;
6702}
6703def J4_cmpeqn1_tp0_jump_nt : HInst<
6704(outs),
6705(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6706"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
6707tc_24f426ab, TypeCJ>, Enc_405228, PredRel {
6708let Inst{0-0} = 0b0;
6709let Inst{13-8} = 0b000000;
6710let Inst{31-22} = 0b0001000110;
6711let isPredicated = 1;
6712let isTerminator = 1;
6713let isBranch = 1;
6714let isPredicatedNew = 1;
6715let cofRelax1 = 1;
6716let cofRelax2 = 1;
6717let cofMax1 = 1;
6718let Uses = [P0];
6719let Defs = [P0, PC];
6720let BaseOpcode = "J4_cmpeqn1p0";
6721let isTaken = Inst{13};
6722let isExtendable = 1;
6723let opExtendable = 2;
6724let isExtentSigned = 1;
6725let opExtentBits = 11;
6726let opExtentAlign = 2;
6727}
6728def J4_cmpeqn1_tp0_jump_t : HInst<
6729(outs),
6730(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6731"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
6732tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel {
6733let Inst{0-0} = 0b0;
6734let Inst{13-8} = 0b100000;
6735let Inst{31-22} = 0b0001000110;
6736let isPredicated = 1;
6737let isTerminator = 1;
6738let isBranch = 1;
6739let isPredicatedNew = 1;
6740let cofRelax1 = 1;
6741let cofRelax2 = 1;
6742let cofMax1 = 1;
6743let Uses = [P0];
6744let Defs = [P0, PC];
6745let BaseOpcode = "J4_cmpeqn1p0";
6746let isTaken = Inst{13};
6747let isExtendable = 1;
6748let opExtendable = 2;
6749let isExtentSigned = 1;
6750let opExtentBits = 11;
6751let opExtentAlign = 2;
6752}
6753def J4_cmpeqn1_tp1_jump_nt : HInst<
6754(outs),
6755(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6756"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
6757tc_24f426ab, TypeCJ>, Enc_736575, PredRel {
6758let Inst{0-0} = 0b0;
6759let Inst{13-8} = 0b000000;
6760let Inst{31-22} = 0b0001001110;
6761let isPredicated = 1;
6762let isTerminator = 1;
6763let isBranch = 1;
6764let isPredicatedNew = 1;
6765let cofRelax1 = 1;
6766let cofRelax2 = 1;
6767let cofMax1 = 1;
6768let Uses = [P1];
6769let Defs = [P1, PC];
6770let BaseOpcode = "J4_cmpeqn1p1";
6771let isTaken = Inst{13};
6772let isExtendable = 1;
6773let opExtendable = 2;
6774let isExtentSigned = 1;
6775let opExtentBits = 11;
6776let opExtentAlign = 2;
6777}
6778def J4_cmpeqn1_tp1_jump_t : HInst<
6779(outs),
6780(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6781"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
6782tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel {
6783let Inst{0-0} = 0b0;
6784let Inst{13-8} = 0b100000;
6785let Inst{31-22} = 0b0001001110;
6786let isPredicated = 1;
6787let isTerminator = 1;
6788let isBranch = 1;
6789let isPredicatedNew = 1;
6790let cofRelax1 = 1;
6791let cofRelax2 = 1;
6792let cofMax1 = 1;
6793let Uses = [P1];
6794let Defs = [P1, PC];
6795let BaseOpcode = "J4_cmpeqn1p1";
6796let isTaken = Inst{13};
6797let isExtendable = 1;
6798let opExtendable = 2;
6799let isExtentSigned = 1;
6800let opExtentBits = 11;
6801let opExtentAlign = 2;
6802}
6803def J4_cmpgt_f_jumpnv_nt : HInst<
6804(outs),
6805(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6806"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6807tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6808let Inst{0-0} = 0b0;
6809let Inst{13-13} = 0b0;
6810let Inst{19-19} = 0b0;
6811let Inst{31-22} = 0b0010000011;
6812let isPredicated = 1;
6813let isPredicatedFalse = 1;
6814let isTerminator = 1;
6815let isBranch = 1;
6816let isNewValue = 1;
6817let cofMax1 = 1;
6818let isRestrictNoSlot1Store = 1;
6819let Defs = [PC];
6820let BaseOpcode = "J4_cmpgtr";
6821let isTaken = Inst{13};
6822let isExtendable = 1;
6823let opExtendable = 2;
6824let isExtentSigned = 1;
6825let opExtentBits = 11;
6826let opExtentAlign = 2;
6827let opNewValue = 0;
6828}
6829def J4_cmpgt_f_jumpnv_t : HInst<
6830(outs),
6831(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6832"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6833tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6834let Inst{0-0} = 0b0;
6835let Inst{13-13} = 0b1;
6836let Inst{19-19} = 0b0;
6837let Inst{31-22} = 0b0010000011;
6838let isPredicated = 1;
6839let isPredicatedFalse = 1;
6840let isTerminator = 1;
6841let isBranch = 1;
6842let isNewValue = 1;
6843let cofMax1 = 1;
6844let isRestrictNoSlot1Store = 1;
6845let Defs = [PC];
6846let BaseOpcode = "J4_cmpgtr";
6847let isTaken = Inst{13};
6848let isExtendable = 1;
6849let opExtendable = 2;
6850let isExtentSigned = 1;
6851let opExtentBits = 11;
6852let opExtentAlign = 2;
6853let opNewValue = 0;
6854}
6855def J4_cmpgt_fp0_jump_nt : HInst<
6856(outs),
6857(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6858"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
6859tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6860let Inst{0-0} = 0b0;
6861let Inst{13-12} = 0b00;
6862let Inst{31-22} = 0b0001010011;
6863let isPredicated = 1;
6864let isPredicatedFalse = 1;
6865let isTerminator = 1;
6866let isBranch = 1;
6867let isPredicatedNew = 1;
6868let cofRelax1 = 1;
6869let cofRelax2 = 1;
6870let cofMax1 = 1;
6871let Uses = [P0];
6872let Defs = [P0, PC];
6873let BaseOpcode = "J4_cmpgtp0";
6874let isTaken = Inst{13};
6875let isExtendable = 1;
6876let opExtendable = 2;
6877let isExtentSigned = 1;
6878let opExtentBits = 11;
6879let opExtentAlign = 2;
6880}
6881def J4_cmpgt_fp0_jump_t : HInst<
6882(outs),
6883(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6884"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
6885tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6886let Inst{0-0} = 0b0;
6887let Inst{13-12} = 0b10;
6888let Inst{31-22} = 0b0001010011;
6889let isPredicated = 1;
6890let isPredicatedFalse = 1;
6891let isTerminator = 1;
6892let isBranch = 1;
6893let isPredicatedNew = 1;
6894let cofRelax1 = 1;
6895let cofRelax2 = 1;
6896let cofMax1 = 1;
6897let Uses = [P0];
6898let Defs = [P0, PC];
6899let BaseOpcode = "J4_cmpgtp0";
6900let isTaken = Inst{13};
6901let isExtendable = 1;
6902let opExtendable = 2;
6903let isExtentSigned = 1;
6904let opExtentBits = 11;
6905let opExtentAlign = 2;
6906}
6907def J4_cmpgt_fp1_jump_nt : HInst<
6908(outs),
6909(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6910"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
6911tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6912let Inst{0-0} = 0b0;
6913let Inst{13-12} = 0b01;
6914let Inst{31-22} = 0b0001010011;
6915let isPredicated = 1;
6916let isPredicatedFalse = 1;
6917let isTerminator = 1;
6918let isBranch = 1;
6919let isPredicatedNew = 1;
6920let cofRelax1 = 1;
6921let cofRelax2 = 1;
6922let cofMax1 = 1;
6923let Uses = [P1];
6924let Defs = [P1, PC];
6925let BaseOpcode = "J4_cmpgtp1";
6926let isTaken = Inst{13};
6927let isExtendable = 1;
6928let opExtendable = 2;
6929let isExtentSigned = 1;
6930let opExtentBits = 11;
6931let opExtentAlign = 2;
6932}
6933def J4_cmpgt_fp1_jump_t : HInst<
6934(outs),
6935(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6936"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6937tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6938let Inst{0-0} = 0b0;
6939let Inst{13-12} = 0b11;
6940let Inst{31-22} = 0b0001010011;
6941let isPredicated = 1;
6942let isPredicatedFalse = 1;
6943let isTerminator = 1;
6944let isBranch = 1;
6945let isPredicatedNew = 1;
6946let cofRelax1 = 1;
6947let cofRelax2 = 1;
6948let cofMax1 = 1;
6949let Uses = [P1];
6950let Defs = [P1, PC];
6951let BaseOpcode = "J4_cmpgtp1";
6952let isTaken = Inst{13};
6953let isExtendable = 1;
6954let opExtendable = 2;
6955let isExtentSigned = 1;
6956let opExtentBits = 11;
6957let opExtentAlign = 2;
6958}
6959def J4_cmpgt_t_jumpnv_nt : HInst<
6960(outs),
6961(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6962"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6963tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6964let Inst{0-0} = 0b0;
6965let Inst{13-13} = 0b0;
6966let Inst{19-19} = 0b0;
6967let Inst{31-22} = 0b0010000010;
6968let isPredicated = 1;
6969let isTerminator = 1;
6970let isBranch = 1;
6971let isNewValue = 1;
6972let cofMax1 = 1;
6973let isRestrictNoSlot1Store = 1;
6974let Defs = [PC];
6975let BaseOpcode = "J4_cmpgtr";
6976let isTaken = Inst{13};
6977let isExtendable = 1;
6978let opExtendable = 2;
6979let isExtentSigned = 1;
6980let opExtentBits = 11;
6981let opExtentAlign = 2;
6982let opNewValue = 0;
6983}
6984def J4_cmpgt_t_jumpnv_t : HInst<
6985(outs),
6986(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6987"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6988tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6989let Inst{0-0} = 0b0;
6990let Inst{13-13} = 0b1;
6991let Inst{19-19} = 0b0;
6992let Inst{31-22} = 0b0010000010;
6993let isPredicated = 1;
6994let isTerminator = 1;
6995let isBranch = 1;
6996let isNewValue = 1;
6997let cofMax1 = 1;
6998let isRestrictNoSlot1Store = 1;
6999let Defs = [PC];
7000let BaseOpcode = "J4_cmpgtr";
7001let isTaken = Inst{13};
7002let isExtendable = 1;
7003let opExtendable = 2;
7004let isExtentSigned = 1;
7005let opExtentBits = 11;
7006let opExtentAlign = 2;
7007let opNewValue = 0;
7008}
7009def J4_cmpgt_tp0_jump_nt : HInst<
7010(outs),
7011(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7012"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7013tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7014let Inst{0-0} = 0b0;
7015let Inst{13-12} = 0b00;
7016let Inst{31-22} = 0b0001010010;
7017let isPredicated = 1;
7018let isTerminator = 1;
7019let isBranch = 1;
7020let isPredicatedNew = 1;
7021let cofRelax1 = 1;
7022let cofRelax2 = 1;
7023let cofMax1 = 1;
7024let Uses = [P0];
7025let Defs = [P0, PC];
7026let BaseOpcode = "J4_cmpgtp0";
7027let isTaken = Inst{13};
7028let isExtendable = 1;
7029let opExtendable = 2;
7030let isExtentSigned = 1;
7031let opExtentBits = 11;
7032let opExtentAlign = 2;
7033}
7034def J4_cmpgt_tp0_jump_t : HInst<
7035(outs),
7036(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7037"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7038tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7039let Inst{0-0} = 0b0;
7040let Inst{13-12} = 0b10;
7041let Inst{31-22} = 0b0001010010;
7042let isPredicated = 1;
7043let isTerminator = 1;
7044let isBranch = 1;
7045let isPredicatedNew = 1;
7046let cofRelax1 = 1;
7047let cofRelax2 = 1;
7048let cofMax1 = 1;
7049let Uses = [P0];
7050let Defs = [P0, PC];
7051let BaseOpcode = "J4_cmpgtp0";
7052let isTaken = Inst{13};
7053let isExtendable = 1;
7054let opExtendable = 2;
7055let isExtentSigned = 1;
7056let opExtentBits = 11;
7057let opExtentAlign = 2;
7058}
7059def J4_cmpgt_tp1_jump_nt : HInst<
7060(outs),
7061(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7062"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7063tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7064let Inst{0-0} = 0b0;
7065let Inst{13-12} = 0b01;
7066let Inst{31-22} = 0b0001010010;
7067let isPredicated = 1;
7068let isTerminator = 1;
7069let isBranch = 1;
7070let isPredicatedNew = 1;
7071let cofRelax1 = 1;
7072let cofRelax2 = 1;
7073let cofMax1 = 1;
7074let Uses = [P1];
7075let Defs = [P1, PC];
7076let BaseOpcode = "J4_cmpgtp1";
7077let isTaken = Inst{13};
7078let isExtendable = 1;
7079let opExtendable = 2;
7080let isExtentSigned = 1;
7081let opExtentBits = 11;
7082let opExtentAlign = 2;
7083}
7084def J4_cmpgt_tp1_jump_t : HInst<
7085(outs),
7086(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7087"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7088tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7089let Inst{0-0} = 0b0;
7090let Inst{13-12} = 0b11;
7091let Inst{31-22} = 0b0001010010;
7092let isPredicated = 1;
7093let isTerminator = 1;
7094let isBranch = 1;
7095let isPredicatedNew = 1;
7096let cofRelax1 = 1;
7097let cofRelax2 = 1;
7098let cofMax1 = 1;
7099let Uses = [P1];
7100let Defs = [P1, PC];
7101let BaseOpcode = "J4_cmpgtp1";
7102let isTaken = Inst{13};
7103let isExtendable = 1;
7104let opExtendable = 2;
7105let isExtentSigned = 1;
7106let opExtentBits = 11;
7107let opExtentAlign = 2;
7108}
7109def J4_cmpgti_f_jumpnv_nt : HInst<
7110(outs),
7111(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7112"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7113tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7114let Inst{0-0} = 0b0;
7115let Inst{13-13} = 0b0;
7116let Inst{19-19} = 0b0;
7117let Inst{31-22} = 0b0010010011;
7118let isPredicated = 1;
7119let isPredicatedFalse = 1;
7120let isTerminator = 1;
7121let isBranch = 1;
7122let isNewValue = 1;
7123let cofMax1 = 1;
7124let isRestrictNoSlot1Store = 1;
7125let Defs = [PC];
7126let BaseOpcode = "J4_cmpgtir";
7127let isTaken = Inst{13};
7128let isExtendable = 1;
7129let opExtendable = 2;
7130let isExtentSigned = 1;
7131let opExtentBits = 11;
7132let opExtentAlign = 2;
7133let opNewValue = 0;
7134}
7135def J4_cmpgti_f_jumpnv_t : HInst<
7136(outs),
7137(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7138"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7139tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7140let Inst{0-0} = 0b0;
7141let Inst{13-13} = 0b1;
7142let Inst{19-19} = 0b0;
7143let Inst{31-22} = 0b0010010011;
7144let isPredicated = 1;
7145let isPredicatedFalse = 1;
7146let isTerminator = 1;
7147let isBranch = 1;
7148let isNewValue = 1;
7149let cofMax1 = 1;
7150let isRestrictNoSlot1Store = 1;
7151let Defs = [PC];
7152let BaseOpcode = "J4_cmpgtir";
7153let isTaken = Inst{13};
7154let isExtendable = 1;
7155let opExtendable = 2;
7156let isExtentSigned = 1;
7157let opExtentBits = 11;
7158let opExtentAlign = 2;
7159let opNewValue = 0;
7160}
7161def J4_cmpgti_fp0_jump_nt : HInst<
7162(outs),
7163(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7164"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7165tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7166let Inst{0-0} = 0b0;
7167let Inst{13-13} = 0b0;
7168let Inst{31-22} = 0b0001000011;
7169let isPredicated = 1;
7170let isPredicatedFalse = 1;
7171let isTerminator = 1;
7172let isBranch = 1;
7173let isPredicatedNew = 1;
7174let cofRelax1 = 1;
7175let cofRelax2 = 1;
7176let cofMax1 = 1;
7177let Uses = [P0];
7178let Defs = [P0, PC];
7179let BaseOpcode = "J4_cmpgtip0";
7180let isTaken = Inst{13};
7181let isExtendable = 1;
7182let opExtendable = 2;
7183let isExtentSigned = 1;
7184let opExtentBits = 11;
7185let opExtentAlign = 2;
7186}
7187def J4_cmpgti_fp0_jump_t : HInst<
7188(outs),
7189(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7190"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
7191tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7192let Inst{0-0} = 0b0;
7193let Inst{13-13} = 0b1;
7194let Inst{31-22} = 0b0001000011;
7195let isPredicated = 1;
7196let isPredicatedFalse = 1;
7197let isTerminator = 1;
7198let isBranch = 1;
7199let isPredicatedNew = 1;
7200let cofRelax1 = 1;
7201let cofRelax2 = 1;
7202let cofMax1 = 1;
7203let Uses = [P0];
7204let Defs = [P0, PC];
7205let BaseOpcode = "J4_cmpgtip0";
7206let isTaken = Inst{13};
7207let isExtendable = 1;
7208let opExtendable = 2;
7209let isExtentSigned = 1;
7210let opExtentBits = 11;
7211let opExtentAlign = 2;
7212}
7213def J4_cmpgti_fp1_jump_nt : HInst<
7214(outs),
7215(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7216"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7217tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7218let Inst{0-0} = 0b0;
7219let Inst{13-13} = 0b0;
7220let Inst{31-22} = 0b0001001011;
7221let isPredicated = 1;
7222let isPredicatedFalse = 1;
7223let isTerminator = 1;
7224let isBranch = 1;
7225let isPredicatedNew = 1;
7226let cofRelax1 = 1;
7227let cofRelax2 = 1;
7228let cofMax1 = 1;
7229let Uses = [P1];
7230let Defs = [P1, PC];
7231let BaseOpcode = "J4_cmpgtip1";
7232let isTaken = Inst{13};
7233let isExtendable = 1;
7234let opExtendable = 2;
7235let isExtentSigned = 1;
7236let opExtentBits = 11;
7237let opExtentAlign = 2;
7238}
7239def J4_cmpgti_fp1_jump_t : HInst<
7240(outs),
7241(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7242"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
7243tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7244let Inst{0-0} = 0b0;
7245let Inst{13-13} = 0b1;
7246let Inst{31-22} = 0b0001001011;
7247let isPredicated = 1;
7248let isPredicatedFalse = 1;
7249let isTerminator = 1;
7250let isBranch = 1;
7251let isPredicatedNew = 1;
7252let cofRelax1 = 1;
7253let cofRelax2 = 1;
7254let cofMax1 = 1;
7255let Uses = [P1];
7256let Defs = [P1, PC];
7257let BaseOpcode = "J4_cmpgtip1";
7258let isTaken = Inst{13};
7259let isExtendable = 1;
7260let opExtendable = 2;
7261let isExtentSigned = 1;
7262let opExtentBits = 11;
7263let opExtentAlign = 2;
7264}
7265def J4_cmpgti_t_jumpnv_nt : HInst<
7266(outs),
7267(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7268"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7269tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7270let Inst{0-0} = 0b0;
7271let Inst{13-13} = 0b0;
7272let Inst{19-19} = 0b0;
7273let Inst{31-22} = 0b0010010010;
7274let isPredicated = 1;
7275let isTerminator = 1;
7276let isBranch = 1;
7277let isNewValue = 1;
7278let cofMax1 = 1;
7279let isRestrictNoSlot1Store = 1;
7280let Defs = [PC];
7281let BaseOpcode = "J4_cmpgtir";
7282let isTaken = Inst{13};
7283let isExtendable = 1;
7284let opExtendable = 2;
7285let isExtentSigned = 1;
7286let opExtentBits = 11;
7287let opExtentAlign = 2;
7288let opNewValue = 0;
7289}
7290def J4_cmpgti_t_jumpnv_t : HInst<
7291(outs),
7292(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7293"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7294tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7295let Inst{0-0} = 0b0;
7296let Inst{13-13} = 0b1;
7297let Inst{19-19} = 0b0;
7298let Inst{31-22} = 0b0010010010;
7299let isPredicated = 1;
7300let isTerminator = 1;
7301let isBranch = 1;
7302let isNewValue = 1;
7303let cofMax1 = 1;
7304let isRestrictNoSlot1Store = 1;
7305let Defs = [PC];
7306let BaseOpcode = "J4_cmpgtir";
7307let isTaken = Inst{13};
7308let isExtendable = 1;
7309let opExtendable = 2;
7310let isExtentSigned = 1;
7311let opExtentBits = 11;
7312let opExtentAlign = 2;
7313let opNewValue = 0;
7314}
7315def J4_cmpgti_tp0_jump_nt : HInst<
7316(outs),
7317(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7318"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
7319tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7320let Inst{0-0} = 0b0;
7321let Inst{13-13} = 0b0;
7322let Inst{31-22} = 0b0001000010;
7323let isPredicated = 1;
7324let isTerminator = 1;
7325let isBranch = 1;
7326let isPredicatedNew = 1;
7327let cofRelax1 = 1;
7328let cofRelax2 = 1;
7329let cofMax1 = 1;
7330let Uses = [P0];
7331let Defs = [P0, PC];
7332let BaseOpcode = "J4_cmpgtip0";
7333let isTaken = Inst{13};
7334let isExtendable = 1;
7335let opExtendable = 2;
7336let isExtentSigned = 1;
7337let opExtentBits = 11;
7338let opExtentAlign = 2;
7339}
7340def J4_cmpgti_tp0_jump_t : HInst<
7341(outs),
7342(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7343"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
7344tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7345let Inst{0-0} = 0b0;
7346let Inst{13-13} = 0b1;
7347let Inst{31-22} = 0b0001000010;
7348let isPredicated = 1;
7349let isTerminator = 1;
7350let isBranch = 1;
7351let isPredicatedNew = 1;
7352let cofRelax1 = 1;
7353let cofRelax2 = 1;
7354let cofMax1 = 1;
7355let Uses = [P0];
7356let Defs = [P0, PC];
7357let BaseOpcode = "J4_cmpgtip0";
7358let isTaken = Inst{13};
7359let isExtendable = 1;
7360let opExtendable = 2;
7361let isExtentSigned = 1;
7362let opExtentBits = 11;
7363let opExtentAlign = 2;
7364}
7365def J4_cmpgti_tp1_jump_nt : HInst<
7366(outs),
7367(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7368"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
7369tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7370let Inst{0-0} = 0b0;
7371let Inst{13-13} = 0b0;
7372let Inst{31-22} = 0b0001001010;
7373let isPredicated = 1;
7374let isTerminator = 1;
7375let isBranch = 1;
7376let isPredicatedNew = 1;
7377let cofRelax1 = 1;
7378let cofRelax2 = 1;
7379let cofMax1 = 1;
7380let Uses = [P1];
7381let Defs = [P1, PC];
7382let BaseOpcode = "J4_cmpgtip1";
7383let isTaken = Inst{13};
7384let isExtendable = 1;
7385let opExtendable = 2;
7386let isExtentSigned = 1;
7387let opExtentBits = 11;
7388let opExtentAlign = 2;
7389}
7390def J4_cmpgti_tp1_jump_t : HInst<
7391(outs),
7392(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7393"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
7394tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7395let Inst{0-0} = 0b0;
7396let Inst{13-13} = 0b1;
7397let Inst{31-22} = 0b0001001010;
7398let isPredicated = 1;
7399let isTerminator = 1;
7400let isBranch = 1;
7401let isPredicatedNew = 1;
7402let cofRelax1 = 1;
7403let cofRelax2 = 1;
7404let cofMax1 = 1;
7405let Uses = [P1];
7406let Defs = [P1, PC];
7407let BaseOpcode = "J4_cmpgtip1";
7408let isTaken = Inst{13};
7409let isExtendable = 1;
7410let opExtendable = 2;
7411let isExtentSigned = 1;
7412let opExtentBits = 11;
7413let opExtentAlign = 2;
7414}
7415def J4_cmpgtn1_f_jumpnv_nt : HInst<
7416(outs),
7417(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7418"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7419tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel {
7420let Inst{0-0} = 0b0;
7421let Inst{13-8} = 0b000000;
7422let Inst{19-19} = 0b0;
7423let Inst{31-22} = 0b0010011011;
7424let isPredicated = 1;
7425let isPredicatedFalse = 1;
7426let isTerminator = 1;
7427let isBranch = 1;
7428let isNewValue = 1;
7429let cofMax1 = 1;
7430let isRestrictNoSlot1Store = 1;
7431let Defs = [PC];
7432let BaseOpcode = "J4_cmpgtn1r";
7433let isTaken = Inst{13};
7434let isExtendable = 1;
7435let opExtendable = 2;
7436let isExtentSigned = 1;
7437let opExtentBits = 11;
7438let opExtentAlign = 2;
7439let opNewValue = 0;
7440}
7441def J4_cmpgtn1_f_jumpnv_t : HInst<
7442(outs),
7443(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7444"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7445tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel {
7446let Inst{0-0} = 0b0;
7447let Inst{13-8} = 0b100000;
7448let Inst{19-19} = 0b0;
7449let Inst{31-22} = 0b0010011011;
7450let isPredicated = 1;
7451let isPredicatedFalse = 1;
7452let isTerminator = 1;
7453let isBranch = 1;
7454let isNewValue = 1;
7455let cofMax1 = 1;
7456let isRestrictNoSlot1Store = 1;
7457let Defs = [PC];
7458let BaseOpcode = "J4_cmpgtn1r";
7459let isTaken = Inst{13};
7460let isExtendable = 1;
7461let opExtendable = 2;
7462let isExtentSigned = 1;
7463let opExtentBits = 11;
7464let opExtentAlign = 2;
7465let opNewValue = 0;
7466}
7467def J4_cmpgtn1_fp0_jump_nt : HInst<
7468(outs),
7469(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7470"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
7471tc_24f426ab, TypeCJ>, Enc_a42857, PredRel {
7472let Inst{0-0} = 0b0;
7473let Inst{13-8} = 0b000001;
7474let Inst{31-22} = 0b0001000111;
7475let isPredicated = 1;
7476let isPredicatedFalse = 1;
7477let isTerminator = 1;
7478let isBranch = 1;
7479let isPredicatedNew = 1;
7480let cofRelax1 = 1;
7481let cofRelax2 = 1;
7482let cofMax1 = 1;
7483let Uses = [P0];
7484let Defs = [P0, PC];
7485let BaseOpcode = "J4_cmpgtn1p0";
7486let isTaken = Inst{13};
7487let isExtendable = 1;
7488let opExtendable = 2;
7489let isExtentSigned = 1;
7490let opExtentBits = 11;
7491let opExtentAlign = 2;
7492}
7493def J4_cmpgtn1_fp0_jump_t : HInst<
7494(outs),
7495(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7496"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
7497tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel {
7498let Inst{0-0} = 0b0;
7499let Inst{13-8} = 0b100001;
7500let Inst{31-22} = 0b0001000111;
7501let isPredicated = 1;
7502let isPredicatedFalse = 1;
7503let isTerminator = 1;
7504let isBranch = 1;
7505let isPredicatedNew = 1;
7506let cofRelax1 = 1;
7507let cofRelax2 = 1;
7508let cofMax1 = 1;
7509let Uses = [P0];
7510let Defs = [P0, PC];
7511let BaseOpcode = "J4_cmpgtn1p0";
7512let isTaken = Inst{13};
7513let isExtendable = 1;
7514let opExtendable = 2;
7515let isExtentSigned = 1;
7516let opExtentBits = 11;
7517let opExtentAlign = 2;
7518}
7519def J4_cmpgtn1_fp1_jump_nt : HInst<
7520(outs),
7521(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7522"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
7523tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel {
7524let Inst{0-0} = 0b0;
7525let Inst{13-8} = 0b000001;
7526let Inst{31-22} = 0b0001001111;
7527let isPredicated = 1;
7528let isPredicatedFalse = 1;
7529let isTerminator = 1;
7530let isBranch = 1;
7531let isPredicatedNew = 1;
7532let cofRelax1 = 1;
7533let cofRelax2 = 1;
7534let cofMax1 = 1;
7535let Uses = [P1];
7536let Defs = [P1, PC];
7537let BaseOpcode = "J4_cmpgtn1p1";
7538let isTaken = Inst{13};
7539let isExtendable = 1;
7540let opExtendable = 2;
7541let isExtentSigned = 1;
7542let opExtentBits = 11;
7543let opExtentAlign = 2;
7544}
7545def J4_cmpgtn1_fp1_jump_t : HInst<
7546(outs),
7547(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7548"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
7549tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel {
7550let Inst{0-0} = 0b0;
7551let Inst{13-8} = 0b100001;
7552let Inst{31-22} = 0b0001001111;
7553let isPredicated = 1;
7554let isPredicatedFalse = 1;
7555let isTerminator = 1;
7556let isBranch = 1;
7557let isPredicatedNew = 1;
7558let cofRelax1 = 1;
7559let cofRelax2 = 1;
7560let cofMax1 = 1;
7561let Uses = [P1];
7562let Defs = [P1, PC];
7563let BaseOpcode = "J4_cmpgtn1p1";
7564let isTaken = Inst{13};
7565let isExtendable = 1;
7566let opExtendable = 2;
7567let isExtentSigned = 1;
7568let opExtentBits = 11;
7569let opExtentAlign = 2;
7570}
7571def J4_cmpgtn1_t_jumpnv_nt : HInst<
7572(outs),
7573(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7574"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7575tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel {
7576let Inst{0-0} = 0b0;
7577let Inst{13-8} = 0b000000;
7578let Inst{19-19} = 0b0;
7579let Inst{31-22} = 0b0010011010;
7580let isPredicated = 1;
7581let isTerminator = 1;
7582let isBranch = 1;
7583let isNewValue = 1;
7584let cofMax1 = 1;
7585let isRestrictNoSlot1Store = 1;
7586let Defs = [PC];
7587let BaseOpcode = "J4_cmpgtn1r";
7588let isTaken = Inst{13};
7589let isExtendable = 1;
7590let opExtendable = 2;
7591let isExtentSigned = 1;
7592let opExtentBits = 11;
7593let opExtentAlign = 2;
7594let opNewValue = 0;
7595}
7596def J4_cmpgtn1_t_jumpnv_t : HInst<
7597(outs),
7598(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7599"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7600tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel {
7601let Inst{0-0} = 0b0;
7602let Inst{13-8} = 0b100000;
7603let Inst{19-19} = 0b0;
7604let Inst{31-22} = 0b0010011010;
7605let isPredicated = 1;
7606let isTerminator = 1;
7607let isBranch = 1;
7608let isNewValue = 1;
7609let cofMax1 = 1;
7610let isRestrictNoSlot1Store = 1;
7611let Defs = [PC];
7612let BaseOpcode = "J4_cmpgtn1r";
7613let isTaken = Inst{13};
7614let isExtendable = 1;
7615let opExtendable = 2;
7616let isExtentSigned = 1;
7617let opExtentBits = 11;
7618let opExtentAlign = 2;
7619let opNewValue = 0;
7620}
7621def J4_cmpgtn1_tp0_jump_nt : HInst<
7622(outs),
7623(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7624"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
7625tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel {
7626let Inst{0-0} = 0b0;
7627let Inst{13-8} = 0b000001;
7628let Inst{31-22} = 0b0001000110;
7629let isPredicated = 1;
7630let isTerminator = 1;
7631let isBranch = 1;
7632let isPredicatedNew = 1;
7633let cofRelax1 = 1;
7634let cofRelax2 = 1;
7635let cofMax1 = 1;
7636let Uses = [P0];
7637let Defs = [P0, PC];
7638let BaseOpcode = "J4_cmpgtn1p0";
7639let isTaken = Inst{13};
7640let isExtendable = 1;
7641let opExtendable = 2;
7642let isExtentSigned = 1;
7643let opExtentBits = 11;
7644let opExtentAlign = 2;
7645}
7646def J4_cmpgtn1_tp0_jump_t : HInst<
7647(outs),
7648(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7649"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
7650tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel {
7651let Inst{0-0} = 0b0;
7652let Inst{13-8} = 0b100001;
7653let Inst{31-22} = 0b0001000110;
7654let isPredicated = 1;
7655let isTerminator = 1;
7656let isBranch = 1;
7657let isPredicatedNew = 1;
7658let cofRelax1 = 1;
7659let cofRelax2 = 1;
7660let cofMax1 = 1;
7661let Uses = [P0];
7662let Defs = [P0, PC];
7663let BaseOpcode = "J4_cmpgtn1p0";
7664let isTaken = Inst{13};
7665let isExtendable = 1;
7666let opExtendable = 2;
7667let isExtentSigned = 1;
7668let opExtentBits = 11;
7669let opExtentAlign = 2;
7670}
7671def J4_cmpgtn1_tp1_jump_nt : HInst<
7672(outs),
7673(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7674"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
7675tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel {
7676let Inst{0-0} = 0b0;
7677let Inst{13-8} = 0b000001;
7678let Inst{31-22} = 0b0001001110;
7679let isPredicated = 1;
7680let isTerminator = 1;
7681let isBranch = 1;
7682let isPredicatedNew = 1;
7683let cofRelax1 = 1;
7684let cofRelax2 = 1;
7685let cofMax1 = 1;
7686let Uses = [P1];
7687let Defs = [P1, PC];
7688let BaseOpcode = "J4_cmpgtn1p1";
7689let isTaken = Inst{13};
7690let isExtendable = 1;
7691let opExtendable = 2;
7692let isExtentSigned = 1;
7693let opExtentBits = 11;
7694let opExtentAlign = 2;
7695}
7696def J4_cmpgtn1_tp1_jump_t : HInst<
7697(outs),
7698(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7699"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
7700tc_24f426ab, TypeCJ>, Enc_178717, PredRel {
7701let Inst{0-0} = 0b0;
7702let Inst{13-8} = 0b100001;
7703let Inst{31-22} = 0b0001001110;
7704let isPredicated = 1;
7705let isTerminator = 1;
7706let isBranch = 1;
7707let isPredicatedNew = 1;
7708let cofRelax1 = 1;
7709let cofRelax2 = 1;
7710let cofMax1 = 1;
7711let Uses = [P1];
7712let Defs = [P1, PC];
7713let BaseOpcode = "J4_cmpgtn1p1";
7714let isTaken = Inst{13};
7715let isExtendable = 1;
7716let opExtendable = 2;
7717let isExtentSigned = 1;
7718let opExtentBits = 11;
7719let opExtentAlign = 2;
7720}
7721def J4_cmpgtu_f_jumpnv_nt : HInst<
7722(outs),
7723(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7724"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7725tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7726let Inst{0-0} = 0b0;
7727let Inst{13-13} = 0b0;
7728let Inst{19-19} = 0b0;
7729let Inst{31-22} = 0b0010000101;
7730let isPredicated = 1;
7731let isPredicatedFalse = 1;
7732let isTerminator = 1;
7733let isBranch = 1;
7734let isNewValue = 1;
7735let cofMax1 = 1;
7736let isRestrictNoSlot1Store = 1;
7737let Defs = [PC];
7738let BaseOpcode = "J4_cmpgtur";
7739let isTaken = Inst{13};
7740let isExtendable = 1;
7741let opExtendable = 2;
7742let isExtentSigned = 1;
7743let opExtentBits = 11;
7744let opExtentAlign = 2;
7745let opNewValue = 0;
7746}
7747def J4_cmpgtu_f_jumpnv_t : HInst<
7748(outs),
7749(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7750"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7751tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7752let Inst{0-0} = 0b0;
7753let Inst{13-13} = 0b1;
7754let Inst{19-19} = 0b0;
7755let Inst{31-22} = 0b0010000101;
7756let isPredicated = 1;
7757let isPredicatedFalse = 1;
7758let isTerminator = 1;
7759let isBranch = 1;
7760let isNewValue = 1;
7761let cofMax1 = 1;
7762let isRestrictNoSlot1Store = 1;
7763let Defs = [PC];
7764let BaseOpcode = "J4_cmpgtur";
7765let isTaken = Inst{13};
7766let isExtendable = 1;
7767let opExtendable = 2;
7768let isExtentSigned = 1;
7769let opExtentBits = 11;
7770let opExtentAlign = 2;
7771let opNewValue = 0;
7772}
7773def J4_cmpgtu_fp0_jump_nt : HInst<
7774(outs),
7775(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7776"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
7777tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7778let Inst{0-0} = 0b0;
7779let Inst{13-12} = 0b00;
7780let Inst{31-22} = 0b0001010101;
7781let isPredicated = 1;
7782let isPredicatedFalse = 1;
7783let isTerminator = 1;
7784let isBranch = 1;
7785let isPredicatedNew = 1;
7786let cofRelax1 = 1;
7787let cofRelax2 = 1;
7788let cofMax1 = 1;
7789let Uses = [P0];
7790let Defs = [P0, PC];
7791let BaseOpcode = "J4_cmpgtup0";
7792let isTaken = Inst{13};
7793let isExtendable = 1;
7794let opExtendable = 2;
7795let isExtentSigned = 1;
7796let opExtentBits = 11;
7797let opExtentAlign = 2;
7798}
7799def J4_cmpgtu_fp0_jump_t : HInst<
7800(outs),
7801(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7802"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
7803tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7804let Inst{0-0} = 0b0;
7805let Inst{13-12} = 0b10;
7806let Inst{31-22} = 0b0001010101;
7807let isPredicated = 1;
7808let isPredicatedFalse = 1;
7809let isTerminator = 1;
7810let isBranch = 1;
7811let isPredicatedNew = 1;
7812let cofRelax1 = 1;
7813let cofRelax2 = 1;
7814let cofMax1 = 1;
7815let Uses = [P0];
7816let Defs = [P0, PC];
7817let BaseOpcode = "J4_cmpgtup0";
7818let isTaken = Inst{13};
7819let isExtendable = 1;
7820let opExtendable = 2;
7821let isExtentSigned = 1;
7822let opExtentBits = 11;
7823let opExtentAlign = 2;
7824}
7825def J4_cmpgtu_fp1_jump_nt : HInst<
7826(outs),
7827(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7828"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
7829tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7830let Inst{0-0} = 0b0;
7831let Inst{13-12} = 0b01;
7832let Inst{31-22} = 0b0001010101;
7833let isPredicated = 1;
7834let isPredicatedFalse = 1;
7835let isTerminator = 1;
7836let isBranch = 1;
7837let isPredicatedNew = 1;
7838let cofRelax1 = 1;
7839let cofRelax2 = 1;
7840let cofMax1 = 1;
7841let Uses = [P1];
7842let Defs = [P1, PC];
7843let BaseOpcode = "J4_cmpgtup1";
7844let isTaken = Inst{13};
7845let isExtendable = 1;
7846let opExtendable = 2;
7847let isExtentSigned = 1;
7848let opExtentBits = 11;
7849let opExtentAlign = 2;
7850}
7851def J4_cmpgtu_fp1_jump_t : HInst<
7852(outs),
7853(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7854"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
7855tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7856let Inst{0-0} = 0b0;
7857let Inst{13-12} = 0b11;
7858let Inst{31-22} = 0b0001010101;
7859let isPredicated = 1;
7860let isPredicatedFalse = 1;
7861let isTerminator = 1;
7862let isBranch = 1;
7863let isPredicatedNew = 1;
7864let cofRelax1 = 1;
7865let cofRelax2 = 1;
7866let cofMax1 = 1;
7867let Uses = [P1];
7868let Defs = [P1, PC];
7869let BaseOpcode = "J4_cmpgtup1";
7870let isTaken = Inst{13};
7871let isExtendable = 1;
7872let opExtendable = 2;
7873let isExtentSigned = 1;
7874let opExtentBits = 11;
7875let opExtentAlign = 2;
7876}
7877def J4_cmpgtu_t_jumpnv_nt : HInst<
7878(outs),
7879(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7880"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7881tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7882let Inst{0-0} = 0b0;
7883let Inst{13-13} = 0b0;
7884let Inst{19-19} = 0b0;
7885let Inst{31-22} = 0b0010000100;
7886let isPredicated = 1;
7887let isTerminator = 1;
7888let isBranch = 1;
7889let isNewValue = 1;
7890let cofMax1 = 1;
7891let isRestrictNoSlot1Store = 1;
7892let Defs = [PC];
7893let BaseOpcode = "J4_cmpgtur";
7894let isTaken = Inst{13};
7895let isExtendable = 1;
7896let opExtendable = 2;
7897let isExtentSigned = 1;
7898let opExtentBits = 11;
7899let opExtentAlign = 2;
7900let opNewValue = 0;
7901}
7902def J4_cmpgtu_t_jumpnv_t : HInst<
7903(outs),
7904(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7905"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7906tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7907let Inst{0-0} = 0b0;
7908let Inst{13-13} = 0b1;
7909let Inst{19-19} = 0b0;
7910let Inst{31-22} = 0b0010000100;
7911let isPredicated = 1;
7912let isTerminator = 1;
7913let isBranch = 1;
7914let isNewValue = 1;
7915let cofMax1 = 1;
7916let isRestrictNoSlot1Store = 1;
7917let Defs = [PC];
7918let BaseOpcode = "J4_cmpgtur";
7919let isTaken = Inst{13};
7920let isExtendable = 1;
7921let opExtendable = 2;
7922let isExtentSigned = 1;
7923let opExtentBits = 11;
7924let opExtentAlign = 2;
7925let opNewValue = 0;
7926}
7927def J4_cmpgtu_tp0_jump_nt : HInst<
7928(outs),
7929(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7930"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7931tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7932let Inst{0-0} = 0b0;
7933let Inst{13-12} = 0b00;
7934let Inst{31-22} = 0b0001010100;
7935let isPredicated = 1;
7936let isTerminator = 1;
7937let isBranch = 1;
7938let isPredicatedNew = 1;
7939let cofRelax1 = 1;
7940let cofRelax2 = 1;
7941let cofMax1 = 1;
7942let Uses = [P0];
7943let Defs = [P0, PC];
7944let BaseOpcode = "J4_cmpgtup0";
7945let isTaken = Inst{13};
7946let isExtendable = 1;
7947let opExtendable = 2;
7948let isExtentSigned = 1;
7949let opExtentBits = 11;
7950let opExtentAlign = 2;
7951}
7952def J4_cmpgtu_tp0_jump_t : HInst<
7953(outs),
7954(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7955"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7956tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7957let Inst{0-0} = 0b0;
7958let Inst{13-12} = 0b10;
7959let Inst{31-22} = 0b0001010100;
7960let isPredicated = 1;
7961let isTerminator = 1;
7962let isBranch = 1;
7963let isPredicatedNew = 1;
7964let cofRelax1 = 1;
7965let cofRelax2 = 1;
7966let cofMax1 = 1;
7967let Uses = [P0];
7968let Defs = [P0, PC];
7969let BaseOpcode = "J4_cmpgtup0";
7970let isTaken = Inst{13};
7971let isExtendable = 1;
7972let opExtendable = 2;
7973let isExtentSigned = 1;
7974let opExtentBits = 11;
7975let opExtentAlign = 2;
7976}
7977def J4_cmpgtu_tp1_jump_nt : HInst<
7978(outs),
7979(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7980"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7981tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7982let Inst{0-0} = 0b0;
7983let Inst{13-12} = 0b01;
7984let Inst{31-22} = 0b0001010100;
7985let isPredicated = 1;
7986let isTerminator = 1;
7987let isBranch = 1;
7988let isPredicatedNew = 1;
7989let cofRelax1 = 1;
7990let cofRelax2 = 1;
7991let cofMax1 = 1;
7992let Uses = [P1];
7993let Defs = [P1, PC];
7994let BaseOpcode = "J4_cmpgtup1";
7995let isTaken = Inst{13};
7996let isExtendable = 1;
7997let opExtendable = 2;
7998let isExtentSigned = 1;
7999let opExtentBits = 11;
8000let opExtentAlign = 2;
8001}
8002def J4_cmpgtu_tp1_jump_t : HInst<
8003(outs),
8004(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
8005"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
8006tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
8007let Inst{0-0} = 0b0;
8008let Inst{13-12} = 0b11;
8009let Inst{31-22} = 0b0001010100;
8010let isPredicated = 1;
8011let isTerminator = 1;
8012let isBranch = 1;
8013let isPredicatedNew = 1;
8014let cofRelax1 = 1;
8015let cofRelax2 = 1;
8016let cofMax1 = 1;
8017let Uses = [P1];
8018let Defs = [P1, PC];
8019let BaseOpcode = "J4_cmpgtup1";
8020let isTaken = Inst{13};
8021let isExtendable = 1;
8022let opExtendable = 2;
8023let isExtentSigned = 1;
8024let opExtentBits = 11;
8025let opExtentAlign = 2;
8026}
8027def J4_cmpgtui_f_jumpnv_nt : HInst<
8028(outs),
8029(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8030"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8031tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8032let Inst{0-0} = 0b0;
8033let Inst{13-13} = 0b0;
8034let Inst{19-19} = 0b0;
8035let Inst{31-22} = 0b0010010101;
8036let isPredicated = 1;
8037let isPredicatedFalse = 1;
8038let isTerminator = 1;
8039let isBranch = 1;
8040let isNewValue = 1;
8041let cofMax1 = 1;
8042let isRestrictNoSlot1Store = 1;
8043let Defs = [PC];
8044let BaseOpcode = "J4_cmpgtuir";
8045let isTaken = Inst{13};
8046let isExtendable = 1;
8047let opExtendable = 2;
8048let isExtentSigned = 1;
8049let opExtentBits = 11;
8050let opExtentAlign = 2;
8051let opNewValue = 0;
8052}
8053def J4_cmpgtui_f_jumpnv_t : HInst<
8054(outs),
8055(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8056"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8057tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8058let Inst{0-0} = 0b0;
8059let Inst{13-13} = 0b1;
8060let Inst{19-19} = 0b0;
8061let Inst{31-22} = 0b0010010101;
8062let isPredicated = 1;
8063let isPredicatedFalse = 1;
8064let isTerminator = 1;
8065let isBranch = 1;
8066let isNewValue = 1;
8067let cofMax1 = 1;
8068let isRestrictNoSlot1Store = 1;
8069let Defs = [PC];
8070let BaseOpcode = "J4_cmpgtuir";
8071let isTaken = Inst{13};
8072let isExtendable = 1;
8073let opExtendable = 2;
8074let isExtentSigned = 1;
8075let opExtentBits = 11;
8076let opExtentAlign = 2;
8077let opNewValue = 0;
8078}
8079def J4_cmpgtui_fp0_jump_nt : HInst<
8080(outs),
8081(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8082"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
8083tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8084let Inst{0-0} = 0b0;
8085let Inst{13-13} = 0b0;
8086let Inst{31-22} = 0b0001000101;
8087let isPredicated = 1;
8088let isPredicatedFalse = 1;
8089let isTerminator = 1;
8090let isBranch = 1;
8091let isPredicatedNew = 1;
8092let cofRelax1 = 1;
8093let cofRelax2 = 1;
8094let cofMax1 = 1;
8095let Uses = [P0];
8096let Defs = [P0, PC];
8097let BaseOpcode = "J4_cmpgtuip0";
8098let isTaken = Inst{13};
8099let isExtendable = 1;
8100let opExtendable = 2;
8101let isExtentSigned = 1;
8102let opExtentBits = 11;
8103let opExtentAlign = 2;
8104}
8105def J4_cmpgtui_fp0_jump_t : HInst<
8106(outs),
8107(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8108"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
8109tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8110let Inst{0-0} = 0b0;
8111let Inst{13-13} = 0b1;
8112let Inst{31-22} = 0b0001000101;
8113let isPredicated = 1;
8114let isPredicatedFalse = 1;
8115let isTerminator = 1;
8116let isBranch = 1;
8117let isPredicatedNew = 1;
8118let cofRelax1 = 1;
8119let cofRelax2 = 1;
8120let cofMax1 = 1;
8121let Uses = [P0];
8122let Defs = [P0, PC];
8123let BaseOpcode = "J4_cmpgtuip0";
8124let isTaken = Inst{13};
8125let isExtendable = 1;
8126let opExtendable = 2;
8127let isExtentSigned = 1;
8128let opExtentBits = 11;
8129let opExtentAlign = 2;
8130}
8131def J4_cmpgtui_fp1_jump_nt : HInst<
8132(outs),
8133(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8134"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
8135tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8136let Inst{0-0} = 0b0;
8137let Inst{13-13} = 0b0;
8138let Inst{31-22} = 0b0001001101;
8139let isPredicated = 1;
8140let isPredicatedFalse = 1;
8141let isTerminator = 1;
8142let isBranch = 1;
8143let isPredicatedNew = 1;
8144let cofRelax1 = 1;
8145let cofRelax2 = 1;
8146let cofMax1 = 1;
8147let Uses = [P1];
8148let Defs = [P1, PC];
8149let BaseOpcode = "J4_cmpgtuip1";
8150let isTaken = Inst{13};
8151let isExtendable = 1;
8152let opExtendable = 2;
8153let isExtentSigned = 1;
8154let opExtentBits = 11;
8155let opExtentAlign = 2;
8156}
8157def J4_cmpgtui_fp1_jump_t : HInst<
8158(outs),
8159(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8160"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
8161tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8162let Inst{0-0} = 0b0;
8163let Inst{13-13} = 0b1;
8164let Inst{31-22} = 0b0001001101;
8165let isPredicated = 1;
8166let isPredicatedFalse = 1;
8167let isTerminator = 1;
8168let isBranch = 1;
8169let isPredicatedNew = 1;
8170let cofRelax1 = 1;
8171let cofRelax2 = 1;
8172let cofMax1 = 1;
8173let Uses = [P1];
8174let Defs = [P1, PC];
8175let BaseOpcode = "J4_cmpgtuip1";
8176let isTaken = Inst{13};
8177let isExtendable = 1;
8178let opExtendable = 2;
8179let isExtentSigned = 1;
8180let opExtentBits = 11;
8181let opExtentAlign = 2;
8182}
8183def J4_cmpgtui_t_jumpnv_nt : HInst<
8184(outs),
8185(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8186"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8187tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8188let Inst{0-0} = 0b0;
8189let Inst{13-13} = 0b0;
8190let Inst{19-19} = 0b0;
8191let Inst{31-22} = 0b0010010100;
8192let isPredicated = 1;
8193let isTerminator = 1;
8194let isBranch = 1;
8195let isNewValue = 1;
8196let cofMax1 = 1;
8197let isRestrictNoSlot1Store = 1;
8198let Defs = [PC];
8199let BaseOpcode = "J4_cmpgtuir";
8200let isTaken = Inst{13};
8201let isExtendable = 1;
8202let opExtendable = 2;
8203let isExtentSigned = 1;
8204let opExtentBits = 11;
8205let opExtentAlign = 2;
8206let opNewValue = 0;
8207}
8208def J4_cmpgtui_t_jumpnv_t : HInst<
8209(outs),
8210(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8211"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8212tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8213let Inst{0-0} = 0b0;
8214let Inst{13-13} = 0b1;
8215let Inst{19-19} = 0b0;
8216let Inst{31-22} = 0b0010010100;
8217let isPredicated = 1;
8218let isTerminator = 1;
8219let isBranch = 1;
8220let isNewValue = 1;
8221let cofMax1 = 1;
8222let isRestrictNoSlot1Store = 1;
8223let Defs = [PC];
8224let BaseOpcode = "J4_cmpgtuir";
8225let isTaken = Inst{13};
8226let isExtendable = 1;
8227let opExtendable = 2;
8228let isExtentSigned = 1;
8229let opExtentBits = 11;
8230let opExtentAlign = 2;
8231let opNewValue = 0;
8232}
8233def J4_cmpgtui_tp0_jump_nt : HInst<
8234(outs),
8235(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8236"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
8237tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8238let Inst{0-0} = 0b0;
8239let Inst{13-13} = 0b0;
8240let Inst{31-22} = 0b0001000100;
8241let isPredicated = 1;
8242let isTerminator = 1;
8243let isBranch = 1;
8244let isPredicatedNew = 1;
8245let cofRelax1 = 1;
8246let cofRelax2 = 1;
8247let cofMax1 = 1;
8248let Uses = [P0];
8249let Defs = [P0, PC];
8250let BaseOpcode = "J4_cmpgtuip0";
8251let isTaken = Inst{13};
8252let isExtendable = 1;
8253let opExtendable = 2;
8254let isExtentSigned = 1;
8255let opExtentBits = 11;
8256let opExtentAlign = 2;
8257}
8258def J4_cmpgtui_tp0_jump_t : HInst<
8259(outs),
8260(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8261"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
8262tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8263let Inst{0-0} = 0b0;
8264let Inst{13-13} = 0b1;
8265let Inst{31-22} = 0b0001000100;
8266let isPredicated = 1;
8267let isTerminator = 1;
8268let isBranch = 1;
8269let isPredicatedNew = 1;
8270let cofRelax1 = 1;
8271let cofRelax2 = 1;
8272let cofMax1 = 1;
8273let Uses = [P0];
8274let Defs = [P0, PC];
8275let BaseOpcode = "J4_cmpgtuip0";
8276let isTaken = Inst{13};
8277let isExtendable = 1;
8278let opExtendable = 2;
8279let isExtentSigned = 1;
8280let opExtentBits = 11;
8281let opExtentAlign = 2;
8282}
8283def J4_cmpgtui_tp1_jump_nt : HInst<
8284(outs),
8285(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8286"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
8287tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8288let Inst{0-0} = 0b0;
8289let Inst{13-13} = 0b0;
8290let Inst{31-22} = 0b0001001100;
8291let isPredicated = 1;
8292let isTerminator = 1;
8293let isBranch = 1;
8294let isPredicatedNew = 1;
8295let cofRelax1 = 1;
8296let cofRelax2 = 1;
8297let cofMax1 = 1;
8298let Uses = [P1];
8299let Defs = [P1, PC];
8300let BaseOpcode = "J4_cmpgtuip1";
8301let isTaken = Inst{13};
8302let isExtendable = 1;
8303let opExtendable = 2;
8304let isExtentSigned = 1;
8305let opExtentBits = 11;
8306let opExtentAlign = 2;
8307}
8308def J4_cmpgtui_tp1_jump_t : HInst<
8309(outs),
8310(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8311"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
8312tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8313let Inst{0-0} = 0b0;
8314let Inst{13-13} = 0b1;
8315let Inst{31-22} = 0b0001001100;
8316let isPredicated = 1;
8317let isTerminator = 1;
8318let isBranch = 1;
8319let isPredicatedNew = 1;
8320let cofRelax1 = 1;
8321let cofRelax2 = 1;
8322let cofMax1 = 1;
8323let Uses = [P1];
8324let Defs = [P1, PC];
8325let BaseOpcode = "J4_cmpgtuip1";
8326let isTaken = Inst{13};
8327let isExtendable = 1;
8328let opExtendable = 2;
8329let isExtentSigned = 1;
8330let opExtentBits = 11;
8331let opExtentAlign = 2;
8332}
8333def J4_cmplt_f_jumpnv_nt : HInst<
8334(outs),
8335(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8336"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8337tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8338let Inst{0-0} = 0b0;
8339let Inst{13-13} = 0b0;
8340let Inst{19-19} = 0b0;
8341let Inst{31-22} = 0b0010000111;
8342let isPredicated = 1;
8343let isPredicatedFalse = 1;
8344let isTerminator = 1;
8345let isBranch = 1;
8346let isNewValue = 1;
8347let cofMax1 = 1;
8348let isRestrictNoSlot1Store = 1;
8349let Defs = [PC];
8350let BaseOpcode = "J4_cmpltr";
8351let isTaken = Inst{13};
8352let isExtendable = 1;
8353let opExtendable = 2;
8354let isExtentSigned = 1;
8355let opExtentBits = 11;
8356let opExtentAlign = 2;
8357let opNewValue = 1;
8358}
8359def J4_cmplt_f_jumpnv_t : HInst<
8360(outs),
8361(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8362"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8363tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8364let Inst{0-0} = 0b0;
8365let Inst{13-13} = 0b1;
8366let Inst{19-19} = 0b0;
8367let Inst{31-22} = 0b0010000111;
8368let isPredicated = 1;
8369let isPredicatedFalse = 1;
8370let isTerminator = 1;
8371let isBranch = 1;
8372let isNewValue = 1;
8373let cofMax1 = 1;
8374let isRestrictNoSlot1Store = 1;
8375let Defs = [PC];
8376let BaseOpcode = "J4_cmpltr";
8377let isTaken = Inst{13};
8378let isExtendable = 1;
8379let opExtendable = 2;
8380let isExtentSigned = 1;
8381let opExtentBits = 11;
8382let opExtentAlign = 2;
8383let opNewValue = 1;
8384}
8385def J4_cmplt_t_jumpnv_nt : HInst<
8386(outs),
8387(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8388"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8389tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8390let Inst{0-0} = 0b0;
8391let Inst{13-13} = 0b0;
8392let Inst{19-19} = 0b0;
8393let Inst{31-22} = 0b0010000110;
8394let isPredicated = 1;
8395let isTerminator = 1;
8396let isBranch = 1;
8397let isNewValue = 1;
8398let cofMax1 = 1;
8399let isRestrictNoSlot1Store = 1;
8400let Defs = [PC];
8401let BaseOpcode = "J4_cmpltr";
8402let isTaken = Inst{13};
8403let isExtendable = 1;
8404let opExtendable = 2;
8405let isExtentSigned = 1;
8406let opExtentBits = 11;
8407let opExtentAlign = 2;
8408let opNewValue = 1;
8409}
8410def J4_cmplt_t_jumpnv_t : HInst<
8411(outs),
8412(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8413"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8414tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8415let Inst{0-0} = 0b0;
8416let Inst{13-13} = 0b1;
8417let Inst{19-19} = 0b0;
8418let Inst{31-22} = 0b0010000110;
8419let isPredicated = 1;
8420let isTerminator = 1;
8421let isBranch = 1;
8422let isNewValue = 1;
8423let cofMax1 = 1;
8424let isRestrictNoSlot1Store = 1;
8425let Defs = [PC];
8426let BaseOpcode = "J4_cmpltr";
8427let isTaken = Inst{13};
8428let isExtendable = 1;
8429let opExtendable = 2;
8430let isExtentSigned = 1;
8431let opExtentBits = 11;
8432let opExtentAlign = 2;
8433let opNewValue = 1;
8434}
8435def J4_cmpltu_f_jumpnv_nt : HInst<
8436(outs),
8437(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8438"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8439tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8440let Inst{0-0} = 0b0;
8441let Inst{13-13} = 0b0;
8442let Inst{19-19} = 0b0;
8443let Inst{31-22} = 0b0010001001;
8444let isPredicated = 1;
8445let isPredicatedFalse = 1;
8446let isTerminator = 1;
8447let isBranch = 1;
8448let isNewValue = 1;
8449let cofMax1 = 1;
8450let isRestrictNoSlot1Store = 1;
8451let Defs = [PC];
8452let BaseOpcode = "J4_cmpltur";
8453let isTaken = Inst{13};
8454let isExtendable = 1;
8455let opExtendable = 2;
8456let isExtentSigned = 1;
8457let opExtentBits = 11;
8458let opExtentAlign = 2;
8459let opNewValue = 1;
8460}
8461def J4_cmpltu_f_jumpnv_t : HInst<
8462(outs),
8463(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8464"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8465tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8466let Inst{0-0} = 0b0;
8467let Inst{13-13} = 0b1;
8468let Inst{19-19} = 0b0;
8469let Inst{31-22} = 0b0010001001;
8470let isPredicated = 1;
8471let isPredicatedFalse = 1;
8472let isTerminator = 1;
8473let isBranch = 1;
8474let isNewValue = 1;
8475let cofMax1 = 1;
8476let isRestrictNoSlot1Store = 1;
8477let Defs = [PC];
8478let BaseOpcode = "J4_cmpltur";
8479let isTaken = Inst{13};
8480let isExtendable = 1;
8481let opExtendable = 2;
8482let isExtentSigned = 1;
8483let opExtentBits = 11;
8484let opExtentAlign = 2;
8485let opNewValue = 1;
8486}
8487def J4_cmpltu_t_jumpnv_nt : HInst<
8488(outs),
8489(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8490"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8491tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8492let Inst{0-0} = 0b0;
8493let Inst{13-13} = 0b0;
8494let Inst{19-19} = 0b0;
8495let Inst{31-22} = 0b0010001000;
8496let isPredicated = 1;
8497let isTerminator = 1;
8498let isBranch = 1;
8499let isNewValue = 1;
8500let cofMax1 = 1;
8501let isRestrictNoSlot1Store = 1;
8502let Defs = [PC];
8503let BaseOpcode = "J4_cmpltur";
8504let isTaken = Inst{13};
8505let isExtendable = 1;
8506let opExtendable = 2;
8507let isExtentSigned = 1;
8508let opExtentBits = 11;
8509let opExtentAlign = 2;
8510let opNewValue = 1;
8511}
8512def J4_cmpltu_t_jumpnv_t : HInst<
8513(outs),
8514(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8515"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8516tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8517let Inst{0-0} = 0b0;
8518let Inst{13-13} = 0b1;
8519let Inst{19-19} = 0b0;
8520let Inst{31-22} = 0b0010001000;
8521let isPredicated = 1;
8522let isTerminator = 1;
8523let isBranch = 1;
8524let isNewValue = 1;
8525let cofMax1 = 1;
8526let isRestrictNoSlot1Store = 1;
8527let Defs = [PC];
8528let BaseOpcode = "J4_cmpltur";
8529let isTaken = Inst{13};
8530let isExtendable = 1;
8531let opExtendable = 2;
8532let isExtentSigned = 1;
8533let opExtentBits = 11;
8534let opExtentAlign = 2;
8535let opNewValue = 1;
8536}
8537def J4_hintjumpr : HInst<
8538(outs),
8539(ins IntRegs:$Rs32),
8540"hintjr($Rs32)",
8541tc_e60def48, TypeJ>, Enc_ecbcc8 {
8542let Inst{13-0} = 0b00000000000000;
8543let Inst{31-21} = 0b01010010101;
8544let isTerminator = 1;
8545let isIndirectBranch = 1;
8546let isBranch = 1;
8547let cofRelax1 = 1;
8548let cofRelax2 = 1;
8549let cofMax1 = 1;
8550}
8551def J4_jumpseti : HInst<
8552(outs GeneralSubRegs:$Rd16),
8553(ins u6_0Imm:$II, b30_2Imm:$Ii),
8554"$Rd16 = #$II ; jump $Ii",
8555tc_5502c366, TypeCJ>, Enc_9e4c3f {
8556let Inst{0-0} = 0b0;
8557let Inst{31-22} = 0b0001011000;
8558let hasNewValue = 1;
8559let opNewValue = 0;
8560let isTerminator = 1;
8561let isBranch = 1;
8562let cofRelax2 = 1;
8563let cofMax1 = 1;
8564let Defs = [PC];
8565let isExtendable = 1;
8566let opExtendable = 2;
8567let isExtentSigned = 1;
8568let opExtentBits = 11;
8569let opExtentAlign = 2;
8570}
8571def J4_jumpsetr : HInst<
8572(outs GeneralSubRegs:$Rd16),
8573(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8574"$Rd16 = $Rs16 ; jump $Ii",
8575tc_5502c366, TypeCJ>, Enc_66bce1 {
8576let Inst{0-0} = 0b0;
8577let Inst{13-12} = 0b00;
8578let Inst{31-22} = 0b0001011100;
8579let hasNewValue = 1;
8580let opNewValue = 0;
8581let isTerminator = 1;
8582let isBranch = 1;
8583let cofRelax2 = 1;
8584let cofMax1 = 1;
8585let Defs = [PC];
8586let isExtendable = 1;
8587let opExtendable = 2;
8588let isExtentSigned = 1;
8589let opExtentBits = 11;
8590let opExtentAlign = 2;
8591}
8592def J4_tstbit0_f_jumpnv_nt : HInst<
8593(outs),
8594(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8595"if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
8596tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8597let Inst{0-0} = 0b0;
8598let Inst{13-8} = 0b000000;
8599let Inst{19-19} = 0b0;
8600let Inst{31-22} = 0b0010010111;
8601let isPredicated = 1;
8602let isPredicatedFalse = 1;
8603let isTerminator = 1;
8604let isBranch = 1;
8605let isNewValue = 1;
8606let cofMax1 = 1;
8607let isRestrictNoSlot1Store = 1;
8608let Defs = [PC];
8609let isTaken = Inst{13};
8610let isExtendable = 1;
8611let opExtendable = 1;
8612let isExtentSigned = 1;
8613let opExtentBits = 11;
8614let opExtentAlign = 2;
8615let opNewValue = 0;
8616}
8617def J4_tstbit0_f_jumpnv_t : HInst<
8618(outs),
8619(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8620"if (!tstbit($Ns8.new,#0)) jump:t $Ii",
8621tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8622let Inst{0-0} = 0b0;
8623let Inst{13-8} = 0b100000;
8624let Inst{19-19} = 0b0;
8625let Inst{31-22} = 0b0010010111;
8626let isPredicated = 1;
8627let isPredicatedFalse = 1;
8628let isTerminator = 1;
8629let isBranch = 1;
8630let isNewValue = 1;
8631let cofMax1 = 1;
8632let isRestrictNoSlot1Store = 1;
8633let Defs = [PC];
8634let isTaken = Inst{13};
8635let isExtendable = 1;
8636let opExtendable = 1;
8637let isExtentSigned = 1;
8638let opExtentBits = 11;
8639let opExtentAlign = 2;
8640let opNewValue = 0;
8641}
8642def J4_tstbit0_fp0_jump_nt : HInst<
8643(outs),
8644(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8645"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
8646tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8647let Inst{0-0} = 0b0;
8648let Inst{13-8} = 0b000011;
8649let Inst{31-22} = 0b0001000111;
8650let isPredicated = 1;
8651let isPredicatedFalse = 1;
8652let isTerminator = 1;
8653let isBranch = 1;
8654let isPredicatedNew = 1;
8655let cofRelax1 = 1;
8656let cofRelax2 = 1;
8657let cofMax1 = 1;
8658let Uses = [P0];
8659let Defs = [P0, PC];
8660let isTaken = Inst{13};
8661let isExtendable = 1;
8662let opExtendable = 1;
8663let isExtentSigned = 1;
8664let opExtentBits = 11;
8665let opExtentAlign = 2;
8666}
8667def J4_tstbit0_fp0_jump_t : HInst<
8668(outs),
8669(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8670"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
8671tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8672let Inst{0-0} = 0b0;
8673let Inst{13-8} = 0b100011;
8674let Inst{31-22} = 0b0001000111;
8675let isPredicated = 1;
8676let isPredicatedFalse = 1;
8677let isTerminator = 1;
8678let isBranch = 1;
8679let isPredicatedNew = 1;
8680let cofRelax1 = 1;
8681let cofRelax2 = 1;
8682let cofMax1 = 1;
8683let Uses = [P0];
8684let Defs = [P0, PC];
8685let isTaken = Inst{13};
8686let isExtendable = 1;
8687let opExtendable = 1;
8688let isExtentSigned = 1;
8689let opExtentBits = 11;
8690let opExtentAlign = 2;
8691}
8692def J4_tstbit0_fp1_jump_nt : HInst<
8693(outs),
8694(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8695"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
8696tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8697let Inst{0-0} = 0b0;
8698let Inst{13-8} = 0b000011;
8699let Inst{31-22} = 0b0001001111;
8700let isPredicated = 1;
8701let isPredicatedFalse = 1;
8702let isTerminator = 1;
8703let isBranch = 1;
8704let isPredicatedNew = 1;
8705let cofRelax1 = 1;
8706let cofRelax2 = 1;
8707let cofMax1 = 1;
8708let Uses = [P1];
8709let Defs = [P1, PC];
8710let isTaken = Inst{13};
8711let isExtendable = 1;
8712let opExtendable = 1;
8713let isExtentSigned = 1;
8714let opExtentBits = 11;
8715let opExtentAlign = 2;
8716}
8717def J4_tstbit0_fp1_jump_t : HInst<
8718(outs),
8719(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8720"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
8721tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8722let Inst{0-0} = 0b0;
8723let Inst{13-8} = 0b100011;
8724let Inst{31-22} = 0b0001001111;
8725let isPredicated = 1;
8726let isPredicatedFalse = 1;
8727let isTerminator = 1;
8728let isBranch = 1;
8729let isPredicatedNew = 1;
8730let cofRelax1 = 1;
8731let cofRelax2 = 1;
8732let cofMax1 = 1;
8733let Uses = [P1];
8734let Defs = [P1, PC];
8735let isTaken = Inst{13};
8736let isExtendable = 1;
8737let opExtendable = 1;
8738let isExtentSigned = 1;
8739let opExtentBits = 11;
8740let opExtentAlign = 2;
8741}
8742def J4_tstbit0_t_jumpnv_nt : HInst<
8743(outs),
8744(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8745"if (tstbit($Ns8.new,#0)) jump:nt $Ii",
8746tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8747let Inst{0-0} = 0b0;
8748let Inst{13-8} = 0b000000;
8749let Inst{19-19} = 0b0;
8750let Inst{31-22} = 0b0010010110;
8751let isPredicated = 1;
8752let isTerminator = 1;
8753let isBranch = 1;
8754let isNewValue = 1;
8755let cofMax1 = 1;
8756let isRestrictNoSlot1Store = 1;
8757let Defs = [PC];
8758let isTaken = Inst{13};
8759let isExtendable = 1;
8760let opExtendable = 1;
8761let isExtentSigned = 1;
8762let opExtentBits = 11;
8763let opExtentAlign = 2;
8764let opNewValue = 0;
8765}
8766def J4_tstbit0_t_jumpnv_t : HInst<
8767(outs),
8768(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8769"if (tstbit($Ns8.new,#0)) jump:t $Ii",
8770tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8771let Inst{0-0} = 0b0;
8772let Inst{13-8} = 0b100000;
8773let Inst{19-19} = 0b0;
8774let Inst{31-22} = 0b0010010110;
8775let isPredicated = 1;
8776let isTerminator = 1;
8777let isBranch = 1;
8778let isNewValue = 1;
8779let cofMax1 = 1;
8780let isRestrictNoSlot1Store = 1;
8781let Defs = [PC];
8782let isTaken = Inst{13};
8783let isExtendable = 1;
8784let opExtendable = 1;
8785let isExtentSigned = 1;
8786let opExtentBits = 11;
8787let opExtentAlign = 2;
8788let opNewValue = 0;
8789}
8790def J4_tstbit0_tp0_jump_nt : HInst<
8791(outs),
8792(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8793"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
8794tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8795let Inst{0-0} = 0b0;
8796let Inst{13-8} = 0b000011;
8797let Inst{31-22} = 0b0001000110;
8798let isPredicated = 1;
8799let isTerminator = 1;
8800let isBranch = 1;
8801let isPredicatedNew = 1;
8802let cofRelax1 = 1;
8803let cofRelax2 = 1;
8804let cofMax1 = 1;
8805let Uses = [P0];
8806let Defs = [P0, PC];
8807let isTaken = Inst{13};
8808let isExtendable = 1;
8809let opExtendable = 1;
8810let isExtentSigned = 1;
8811let opExtentBits = 11;
8812let opExtentAlign = 2;
8813}
8814def J4_tstbit0_tp0_jump_t : HInst<
8815(outs),
8816(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8817"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
8818tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8819let Inst{0-0} = 0b0;
8820let Inst{13-8} = 0b100011;
8821let Inst{31-22} = 0b0001000110;
8822let isPredicated = 1;
8823let isTerminator = 1;
8824let isBranch = 1;
8825let isPredicatedNew = 1;
8826let cofRelax1 = 1;
8827let cofRelax2 = 1;
8828let cofMax1 = 1;
8829let Uses = [P0];
8830let Defs = [P0, PC];
8831let isTaken = Inst{13};
8832let isExtendable = 1;
8833let opExtendable = 1;
8834let isExtentSigned = 1;
8835let opExtentBits = 11;
8836let opExtentAlign = 2;
8837}
8838def J4_tstbit0_tp1_jump_nt : HInst<
8839(outs),
8840(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8841"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
8842tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8843let Inst{0-0} = 0b0;
8844let Inst{13-8} = 0b000011;
8845let Inst{31-22} = 0b0001001110;
8846let isPredicated = 1;
8847let isTerminator = 1;
8848let isBranch = 1;
8849let isPredicatedNew = 1;
8850let cofRelax1 = 1;
8851let cofRelax2 = 1;
8852let cofMax1 = 1;
8853let Uses = [P1];
8854let Defs = [P1, PC];
8855let isTaken = Inst{13};
8856let isExtendable = 1;
8857let opExtendable = 1;
8858let isExtentSigned = 1;
8859let opExtentBits = 11;
8860let opExtentAlign = 2;
8861}
8862def J4_tstbit0_tp1_jump_t : HInst<
8863(outs),
8864(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8865"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
8866tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8867let Inst{0-0} = 0b0;
8868let Inst{13-8} = 0b100011;
8869let Inst{31-22} = 0b0001001110;
8870let isPredicated = 1;
8871let isTerminator = 1;
8872let isBranch = 1;
8873let isPredicatedNew = 1;
8874let cofRelax1 = 1;
8875let cofRelax2 = 1;
8876let cofMax1 = 1;
8877let Uses = [P1];
8878let Defs = [P1, PC];
8879let isTaken = Inst{13};
8880let isExtendable = 1;
8881let opExtendable = 1;
8882let isExtentSigned = 1;
8883let opExtentBits = 11;
8884let opExtentAlign = 2;
8885}
8886def L2_deallocframe : HInst<
8887(outs DoubleRegs:$Rdd32),
8888(ins IntRegs:$Rs32),
8889"$Rdd32 = deallocframe($Rs32):raw",
8890tc_e9170fb7, TypeLD>, Enc_3a3d62 {
8891let Inst{13-5} = 0b000000000;
8892let Inst{31-21} = 0b10010000000;
8893let accessSize = DoubleWordAccess;
8894let mayLoad = 1;
8895let Uses = [FRAMEKEY];
8896let Defs = [R29];
8897}
8898def L2_loadalignb_io : HInst<
8899(outs DoubleRegs:$Ryy32),
8900(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
8901"$Ryy32 = memb_fifo($Rs32+#$Ii)",
8902tc_fedb7e19, TypeLD>, Enc_a27588 {
8903let Inst{24-21} = 0b0100;
8904let Inst{31-27} = 0b10010;
8905let addrMode = BaseImmOffset;
8906let accessSize = ByteAccess;
8907let mayLoad = 1;
8908let isExtendable = 1;
8909let opExtendable = 3;
8910let isExtentSigned = 1;
8911let opExtentBits = 11;
8912let opExtentAlign = 0;
8913let Constraints = "$Ryy32 = $Ryy32in";
8914}
8915def L2_loadalignb_pbr : HInst<
8916(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8917(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8918"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
8919tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8920let Inst{12-5} = 0b00000000;
8921let Inst{31-21} = 0b10011110100;
8922let addrMode = PostInc;
8923let accessSize = ByteAccess;
8924let mayLoad = 1;
8925let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8926}
8927def L2_loadalignb_pci : HInst<
8928(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8929(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
8930"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
8931tc_76bb5435, TypeLD>, Enc_74aef2 {
8932let Inst{12-9} = 0b0000;
8933let Inst{31-21} = 0b10011000100;
8934let addrMode = PostInc;
8935let accessSize = ByteAccess;
8936let mayLoad = 1;
8937let Uses = [CS];
8938let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8939}
8940def L2_loadalignb_pcr : HInst<
8941(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8942(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8943"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
8944tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8945let Inst{12-5} = 0b00010000;
8946let Inst{31-21} = 0b10011000100;
8947let addrMode = PostInc;
8948let accessSize = ByteAccess;
8949let mayLoad = 1;
8950let Uses = [CS];
8951let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8952}
8953def L2_loadalignb_pi : HInst<
8954(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8955(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
8956"$Ryy32 = memb_fifo($Rx32++#$Ii)",
8957tc_1c7522a8, TypeLD>, Enc_6b197f {
8958let Inst{13-9} = 0b00000;
8959let Inst{31-21} = 0b10011010100;
8960let addrMode = PostInc;
8961let accessSize = ByteAccess;
8962let mayLoad = 1;
8963let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8964}
8965def L2_loadalignb_pr : HInst<
8966(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8967(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8968"$Ryy32 = memb_fifo($Rx32++$Mu2)",
8969tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8970let Inst{12-5} = 0b00000000;
8971let Inst{31-21} = 0b10011100100;
8972let addrMode = PostInc;
8973let accessSize = ByteAccess;
8974let mayLoad = 1;
8975let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8976}
8977def L2_loadalignb_zomap : HInst<
8978(outs DoubleRegs:$Ryy32),
8979(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8980"$Ryy32 = memb_fifo($Rs32)",
8981tc_fedb7e19, TypeMAPPING> {
8982let isPseudo = 1;
8983let isCodeGenOnly = 1;
8984let Constraints = "$Ryy32 = $Ryy32in";
8985}
8986def L2_loadalignh_io : HInst<
8987(outs DoubleRegs:$Ryy32),
8988(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
8989"$Ryy32 = memh_fifo($Rs32+#$Ii)",
8990tc_fedb7e19, TypeLD>, Enc_5cd7e9 {
8991let Inst{24-21} = 0b0010;
8992let Inst{31-27} = 0b10010;
8993let addrMode = BaseImmOffset;
8994let accessSize = HalfWordAccess;
8995let mayLoad = 1;
8996let isExtendable = 1;
8997let opExtendable = 3;
8998let isExtentSigned = 1;
8999let opExtentBits = 12;
9000let opExtentAlign = 1;
9001let Constraints = "$Ryy32 = $Ryy32in";
9002}
9003def L2_loadalignh_pbr : HInst<
9004(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9005(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9006"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
9007tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9008let Inst{12-5} = 0b00000000;
9009let Inst{31-21} = 0b10011110010;
9010let addrMode = PostInc;
9011let accessSize = HalfWordAccess;
9012let mayLoad = 1;
9013let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9014}
9015def L2_loadalignh_pci : HInst<
9016(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9017(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9018"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
9019tc_76bb5435, TypeLD>, Enc_9e2e1c {
9020let Inst{12-9} = 0b0000;
9021let Inst{31-21} = 0b10011000010;
9022let addrMode = PostInc;
9023let accessSize = HalfWordAccess;
9024let mayLoad = 1;
9025let Uses = [CS];
9026let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9027}
9028def L2_loadalignh_pcr : HInst<
9029(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9030(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9031"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
9032tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9033let Inst{12-5} = 0b00010000;
9034let Inst{31-21} = 0b10011000010;
9035let addrMode = PostInc;
9036let accessSize = HalfWordAccess;
9037let mayLoad = 1;
9038let Uses = [CS];
9039let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9040}
9041def L2_loadalignh_pi : HInst<
9042(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9043(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
9044"$Ryy32 = memh_fifo($Rx32++#$Ii)",
9045tc_1c7522a8, TypeLD>, Enc_bd1cbc {
9046let Inst{13-9} = 0b00000;
9047let Inst{31-21} = 0b10011010010;
9048let addrMode = PostInc;
9049let accessSize = HalfWordAccess;
9050let mayLoad = 1;
9051let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9052}
9053def L2_loadalignh_pr : HInst<
9054(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9055(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9056"$Ryy32 = memh_fifo($Rx32++$Mu2)",
9057tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9058let Inst{12-5} = 0b00000000;
9059let Inst{31-21} = 0b10011100010;
9060let addrMode = PostInc;
9061let accessSize = HalfWordAccess;
9062let mayLoad = 1;
9063let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9064}
9065def L2_loadalignh_zomap : HInst<
9066(outs DoubleRegs:$Ryy32),
9067(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
9068"$Ryy32 = memh_fifo($Rs32)",
9069tc_fedb7e19, TypeMAPPING> {
9070let isPseudo = 1;
9071let isCodeGenOnly = 1;
9072let Constraints = "$Ryy32 = $Ryy32in";
9073}
9074def L2_loadbsw2_io : HInst<
9075(outs IntRegs:$Rd32),
9076(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9077"$Rd32 = membh($Rs32+#$Ii)",
9078tc_4222e6bf, TypeLD>, Enc_de0214 {
9079let Inst{24-21} = 0b0001;
9080let Inst{31-27} = 0b10010;
9081let hasNewValue = 1;
9082let opNewValue = 0;
9083let addrMode = BaseImmOffset;
9084let accessSize = HalfWordAccess;
9085let mayLoad = 1;
9086let isExtendable = 1;
9087let opExtendable = 2;
9088let isExtentSigned = 1;
9089let opExtentBits = 12;
9090let opExtentAlign = 1;
9091}
9092def L2_loadbsw2_pbr : HInst<
9093(outs IntRegs:$Rd32, IntRegs:$Rx32),
9094(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9095"$Rd32 = membh($Rx32++$Mu2:brev)",
9096tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9097let Inst{12-5} = 0b00000000;
9098let Inst{31-21} = 0b10011110001;
9099let hasNewValue = 1;
9100let opNewValue = 0;
9101let addrMode = PostInc;
9102let accessSize = HalfWordAccess;
9103let mayLoad = 1;
9104let Constraints = "$Rx32 = $Rx32in";
9105}
9106def L2_loadbsw2_pci : HInst<
9107(outs IntRegs:$Rd32, IntRegs:$Rx32),
9108(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9109"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
9110tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9111let Inst{12-9} = 0b0000;
9112let Inst{31-21} = 0b10011000001;
9113let hasNewValue = 1;
9114let opNewValue = 0;
9115let addrMode = PostInc;
9116let accessSize = HalfWordAccess;
9117let mayLoad = 1;
9118let Uses = [CS];
9119let Constraints = "$Rx32 = $Rx32in";
9120}
9121def L2_loadbsw2_pcr : HInst<
9122(outs IntRegs:$Rd32, IntRegs:$Rx32),
9123(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9124"$Rd32 = membh($Rx32++I:circ($Mu2))",
9125tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9126let Inst{12-5} = 0b00010000;
9127let Inst{31-21} = 0b10011000001;
9128let hasNewValue = 1;
9129let opNewValue = 0;
9130let addrMode = PostInc;
9131let accessSize = HalfWordAccess;
9132let mayLoad = 1;
9133let Uses = [CS];
9134let Constraints = "$Rx32 = $Rx32in";
9135}
9136def L2_loadbsw2_pi : HInst<
9137(outs IntRegs:$Rd32, IntRegs:$Rx32),
9138(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9139"$Rd32 = membh($Rx32++#$Ii)",
9140tc_075c8dd8, TypeLD>, Enc_152467 {
9141let Inst{13-9} = 0b00000;
9142let Inst{31-21} = 0b10011010001;
9143let hasNewValue = 1;
9144let opNewValue = 0;
9145let addrMode = PostInc;
9146let accessSize = HalfWordAccess;
9147let mayLoad = 1;
9148let Constraints = "$Rx32 = $Rx32in";
9149}
9150def L2_loadbsw2_pr : HInst<
9151(outs IntRegs:$Rd32, IntRegs:$Rx32),
9152(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9153"$Rd32 = membh($Rx32++$Mu2)",
9154tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9155let Inst{12-5} = 0b00000000;
9156let Inst{31-21} = 0b10011100001;
9157let hasNewValue = 1;
9158let opNewValue = 0;
9159let addrMode = PostInc;
9160let accessSize = HalfWordAccess;
9161let mayLoad = 1;
9162let Constraints = "$Rx32 = $Rx32in";
9163}
9164def L2_loadbsw2_zomap : HInst<
9165(outs IntRegs:$Rd32),
9166(ins IntRegs:$Rs32),
9167"$Rd32 = membh($Rs32)",
9168tc_4222e6bf, TypeMAPPING> {
9169let hasNewValue = 1;
9170let opNewValue = 0;
9171let isPseudo = 1;
9172let isCodeGenOnly = 1;
9173}
9174def L2_loadbsw4_io : HInst<
9175(outs DoubleRegs:$Rdd32),
9176(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9177"$Rdd32 = membh($Rs32+#$Ii)",
9178tc_4222e6bf, TypeLD>, Enc_2d7491 {
9179let Inst{24-21} = 0b0111;
9180let Inst{31-27} = 0b10010;
9181let addrMode = BaseImmOffset;
9182let accessSize = WordAccess;
9183let mayLoad = 1;
9184let isExtendable = 1;
9185let opExtendable = 2;
9186let isExtentSigned = 1;
9187let opExtentBits = 13;
9188let opExtentAlign = 2;
9189}
9190def L2_loadbsw4_pbr : HInst<
9191(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9192(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9193"$Rdd32 = membh($Rx32++$Mu2:brev)",
9194tc_075c8dd8, TypeLD>, Enc_7eee72 {
9195let Inst{12-5} = 0b00000000;
9196let Inst{31-21} = 0b10011110111;
9197let addrMode = PostInc;
9198let accessSize = WordAccess;
9199let mayLoad = 1;
9200let Constraints = "$Rx32 = $Rx32in";
9201}
9202def L2_loadbsw4_pci : HInst<
9203(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9204(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9205"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
9206tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9207let Inst{12-9} = 0b0000;
9208let Inst{31-21} = 0b10011000111;
9209let addrMode = PostInc;
9210let accessSize = WordAccess;
9211let mayLoad = 1;
9212let Uses = [CS];
9213let Constraints = "$Rx32 = $Rx32in";
9214}
9215def L2_loadbsw4_pcr : HInst<
9216(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9217(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9218"$Rdd32 = membh($Rx32++I:circ($Mu2))",
9219tc_075c8dd8, TypeLD>, Enc_7eee72 {
9220let Inst{12-5} = 0b00010000;
9221let Inst{31-21} = 0b10011000111;
9222let addrMode = PostInc;
9223let accessSize = WordAccess;
9224let mayLoad = 1;
9225let Uses = [CS];
9226let Constraints = "$Rx32 = $Rx32in";
9227}
9228def L2_loadbsw4_pi : HInst<
9229(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9230(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9231"$Rdd32 = membh($Rx32++#$Ii)",
9232tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9233let Inst{13-9} = 0b00000;
9234let Inst{31-21} = 0b10011010111;
9235let addrMode = PostInc;
9236let accessSize = WordAccess;
9237let mayLoad = 1;
9238let Constraints = "$Rx32 = $Rx32in";
9239}
9240def L2_loadbsw4_pr : HInst<
9241(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9242(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9243"$Rdd32 = membh($Rx32++$Mu2)",
9244tc_075c8dd8, TypeLD>, Enc_7eee72 {
9245let Inst{12-5} = 0b00000000;
9246let Inst{31-21} = 0b10011100111;
9247let addrMode = PostInc;
9248let accessSize = WordAccess;
9249let mayLoad = 1;
9250let Constraints = "$Rx32 = $Rx32in";
9251}
9252def L2_loadbsw4_zomap : HInst<
9253(outs DoubleRegs:$Rdd32),
9254(ins IntRegs:$Rs32),
9255"$Rdd32 = membh($Rs32)",
9256tc_4222e6bf, TypeMAPPING> {
9257let isPseudo = 1;
9258let isCodeGenOnly = 1;
9259}
9260def L2_loadbzw2_io : HInst<
9261(outs IntRegs:$Rd32),
9262(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9263"$Rd32 = memubh($Rs32+#$Ii)",
9264tc_4222e6bf, TypeLD>, Enc_de0214 {
9265let Inst{24-21} = 0b0011;
9266let Inst{31-27} = 0b10010;
9267let hasNewValue = 1;
9268let opNewValue = 0;
9269let addrMode = BaseImmOffset;
9270let accessSize = HalfWordAccess;
9271let mayLoad = 1;
9272let isExtendable = 1;
9273let opExtendable = 2;
9274let isExtentSigned = 1;
9275let opExtentBits = 12;
9276let opExtentAlign = 1;
9277}
9278def L2_loadbzw2_pbr : HInst<
9279(outs IntRegs:$Rd32, IntRegs:$Rx32),
9280(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9281"$Rd32 = memubh($Rx32++$Mu2:brev)",
9282tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9283let Inst{12-5} = 0b00000000;
9284let Inst{31-21} = 0b10011110011;
9285let hasNewValue = 1;
9286let opNewValue = 0;
9287let addrMode = PostInc;
9288let accessSize = HalfWordAccess;
9289let mayLoad = 1;
9290let Constraints = "$Rx32 = $Rx32in";
9291}
9292def L2_loadbzw2_pci : HInst<
9293(outs IntRegs:$Rd32, IntRegs:$Rx32),
9294(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9295"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9296tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9297let Inst{12-9} = 0b0000;
9298let Inst{31-21} = 0b10011000011;
9299let hasNewValue = 1;
9300let opNewValue = 0;
9301let addrMode = PostInc;
9302let accessSize = HalfWordAccess;
9303let mayLoad = 1;
9304let Uses = [CS];
9305let Constraints = "$Rx32 = $Rx32in";
9306}
9307def L2_loadbzw2_pcr : HInst<
9308(outs IntRegs:$Rd32, IntRegs:$Rx32),
9309(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9310"$Rd32 = memubh($Rx32++I:circ($Mu2))",
9311tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9312let Inst{12-5} = 0b00010000;
9313let Inst{31-21} = 0b10011000011;
9314let hasNewValue = 1;
9315let opNewValue = 0;
9316let addrMode = PostInc;
9317let accessSize = HalfWordAccess;
9318let mayLoad = 1;
9319let Uses = [CS];
9320let Constraints = "$Rx32 = $Rx32in";
9321}
9322def L2_loadbzw2_pi : HInst<
9323(outs IntRegs:$Rd32, IntRegs:$Rx32),
9324(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9325"$Rd32 = memubh($Rx32++#$Ii)",
9326tc_075c8dd8, TypeLD>, Enc_152467 {
9327let Inst{13-9} = 0b00000;
9328let Inst{31-21} = 0b10011010011;
9329let hasNewValue = 1;
9330let opNewValue = 0;
9331let addrMode = PostInc;
9332let accessSize = HalfWordAccess;
9333let mayLoad = 1;
9334let Constraints = "$Rx32 = $Rx32in";
9335}
9336def L2_loadbzw2_pr : HInst<
9337(outs IntRegs:$Rd32, IntRegs:$Rx32),
9338(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9339"$Rd32 = memubh($Rx32++$Mu2)",
9340tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9341let Inst{12-5} = 0b00000000;
9342let Inst{31-21} = 0b10011100011;
9343let hasNewValue = 1;
9344let opNewValue = 0;
9345let addrMode = PostInc;
9346let accessSize = HalfWordAccess;
9347let mayLoad = 1;
9348let Constraints = "$Rx32 = $Rx32in";
9349}
9350def L2_loadbzw2_zomap : HInst<
9351(outs IntRegs:$Rd32),
9352(ins IntRegs:$Rs32),
9353"$Rd32 = memubh($Rs32)",
9354tc_4222e6bf, TypeMAPPING> {
9355let hasNewValue = 1;
9356let opNewValue = 0;
9357let isPseudo = 1;
9358let isCodeGenOnly = 1;
9359}
9360def L2_loadbzw4_io : HInst<
9361(outs DoubleRegs:$Rdd32),
9362(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9363"$Rdd32 = memubh($Rs32+#$Ii)",
9364tc_4222e6bf, TypeLD>, Enc_2d7491 {
9365let Inst{24-21} = 0b0101;
9366let Inst{31-27} = 0b10010;
9367let addrMode = BaseImmOffset;
9368let accessSize = WordAccess;
9369let mayLoad = 1;
9370let isExtendable = 1;
9371let opExtendable = 2;
9372let isExtentSigned = 1;
9373let opExtentBits = 13;
9374let opExtentAlign = 2;
9375}
9376def L2_loadbzw4_pbr : HInst<
9377(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9378(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9379"$Rdd32 = memubh($Rx32++$Mu2:brev)",
9380tc_075c8dd8, TypeLD>, Enc_7eee72 {
9381let Inst{12-5} = 0b00000000;
9382let Inst{31-21} = 0b10011110101;
9383let addrMode = PostInc;
9384let accessSize = WordAccess;
9385let mayLoad = 1;
9386let Constraints = "$Rx32 = $Rx32in";
9387}
9388def L2_loadbzw4_pci : HInst<
9389(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9390(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9391"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9392tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9393let Inst{12-9} = 0b0000;
9394let Inst{31-21} = 0b10011000101;
9395let addrMode = PostInc;
9396let accessSize = WordAccess;
9397let mayLoad = 1;
9398let Uses = [CS];
9399let Constraints = "$Rx32 = $Rx32in";
9400}
9401def L2_loadbzw4_pcr : HInst<
9402(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9403(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9404"$Rdd32 = memubh($Rx32++I:circ($Mu2))",
9405tc_075c8dd8, TypeLD>, Enc_7eee72 {
9406let Inst{12-5} = 0b00010000;
9407let Inst{31-21} = 0b10011000101;
9408let addrMode = PostInc;
9409let accessSize = WordAccess;
9410let mayLoad = 1;
9411let Uses = [CS];
9412let Constraints = "$Rx32 = $Rx32in";
9413}
9414def L2_loadbzw4_pi : HInst<
9415(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9416(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9417"$Rdd32 = memubh($Rx32++#$Ii)",
9418tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9419let Inst{13-9} = 0b00000;
9420let Inst{31-21} = 0b10011010101;
9421let addrMode = PostInc;
9422let accessSize = WordAccess;
9423let mayLoad = 1;
9424let Constraints = "$Rx32 = $Rx32in";
9425}
9426def L2_loadbzw4_pr : HInst<
9427(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9428(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9429"$Rdd32 = memubh($Rx32++$Mu2)",
9430tc_075c8dd8, TypeLD>, Enc_7eee72 {
9431let Inst{12-5} = 0b00000000;
9432let Inst{31-21} = 0b10011100101;
9433let addrMode = PostInc;
9434let accessSize = WordAccess;
9435let mayLoad = 1;
9436let Constraints = "$Rx32 = $Rx32in";
9437}
9438def L2_loadbzw4_zomap : HInst<
9439(outs DoubleRegs:$Rdd32),
9440(ins IntRegs:$Rs32),
9441"$Rdd32 = memubh($Rs32)",
9442tc_4222e6bf, TypeMAPPING> {
9443let isPseudo = 1;
9444let isCodeGenOnly = 1;
9445}
9446def L2_loadrb_io : HInst<
9447(outs IntRegs:$Rd32),
9448(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9449"$Rd32 = memb($Rs32+#$Ii)",
9450tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9451let Inst{24-21} = 0b1000;
9452let Inst{31-27} = 0b10010;
9453let hasNewValue = 1;
9454let opNewValue = 0;
9455let addrMode = BaseImmOffset;
9456let accessSize = ByteAccess;
9457let mayLoad = 1;
9458let BaseOpcode = "L2_loadrb_io";
9459let CextOpcode = "L2_loadrb";
9460let isPredicable = 1;
9461let isExtendable = 1;
9462let opExtendable = 2;
9463let isExtentSigned = 1;
9464let opExtentBits = 11;
9465let opExtentAlign = 0;
9466}
9467def L2_loadrb_pbr : HInst<
9468(outs IntRegs:$Rd32, IntRegs:$Rx32),
9469(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9470"$Rd32 = memb($Rx32++$Mu2:brev)",
9471tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9472let Inst{12-5} = 0b00000000;
9473let Inst{31-21} = 0b10011111000;
9474let hasNewValue = 1;
9475let opNewValue = 0;
9476let addrMode = PostInc;
9477let accessSize = ByteAccess;
9478let mayLoad = 1;
9479let Constraints = "$Rx32 = $Rx32in";
9480}
9481def L2_loadrb_pci : HInst<
9482(outs IntRegs:$Rd32, IntRegs:$Rx32),
9483(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9484"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
9485tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9486let Inst{12-9} = 0b0000;
9487let Inst{31-21} = 0b10011001000;
9488let hasNewValue = 1;
9489let opNewValue = 0;
9490let addrMode = PostInc;
9491let accessSize = ByteAccess;
9492let mayLoad = 1;
9493let Uses = [CS];
9494let Constraints = "$Rx32 = $Rx32in";
9495}
9496def L2_loadrb_pcr : HInst<
9497(outs IntRegs:$Rd32, IntRegs:$Rx32),
9498(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9499"$Rd32 = memb($Rx32++I:circ($Mu2))",
9500tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9501let Inst{12-5} = 0b00010000;
9502let Inst{31-21} = 0b10011001000;
9503let hasNewValue = 1;
9504let opNewValue = 0;
9505let addrMode = PostInc;
9506let accessSize = ByteAccess;
9507let mayLoad = 1;
9508let Uses = [CS];
9509let Constraints = "$Rx32 = $Rx32in";
9510}
9511def L2_loadrb_pi : HInst<
9512(outs IntRegs:$Rd32, IntRegs:$Rx32),
9513(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9514"$Rd32 = memb($Rx32++#$Ii)",
9515tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9516let Inst{13-9} = 0b00000;
9517let Inst{31-21} = 0b10011011000;
9518let hasNewValue = 1;
9519let opNewValue = 0;
9520let addrMode = PostInc;
9521let accessSize = ByteAccess;
9522let mayLoad = 1;
9523let BaseOpcode = "L2_loadrb_pi";
9524let CextOpcode = "L2_loadrb";
9525let isPredicable = 1;
9526let Constraints = "$Rx32 = $Rx32in";
9527}
9528def L2_loadrb_pr : HInst<
9529(outs IntRegs:$Rd32, IntRegs:$Rx32),
9530(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9531"$Rd32 = memb($Rx32++$Mu2)",
9532tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9533let Inst{12-5} = 0b00000000;
9534let Inst{31-21} = 0b10011101000;
9535let hasNewValue = 1;
9536let opNewValue = 0;
9537let addrMode = PostInc;
9538let accessSize = ByteAccess;
9539let mayLoad = 1;
9540let Constraints = "$Rx32 = $Rx32in";
9541}
9542def L2_loadrb_zomap : HInst<
9543(outs IntRegs:$Rd32),
9544(ins IntRegs:$Rs32),
9545"$Rd32 = memb($Rs32)",
9546tc_4222e6bf, TypeMAPPING> {
9547let hasNewValue = 1;
9548let opNewValue = 0;
9549let isPseudo = 1;
9550let isCodeGenOnly = 1;
9551}
9552def L2_loadrbgp : HInst<
9553(outs IntRegs:$Rd32),
9554(ins u32_0Imm:$Ii),
9555"$Rd32 = memb(gp+#$Ii)",
9556tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9557let Inst{24-21} = 0b1000;
9558let Inst{31-27} = 0b01001;
9559let hasNewValue = 1;
9560let opNewValue = 0;
9561let accessSize = ByteAccess;
9562let mayLoad = 1;
9563let Uses = [GP];
9564let BaseOpcode = "L4_loadrb_abs";
9565let isPredicable = 1;
9566let opExtendable = 1;
9567let isExtentSigned = 0;
9568let opExtentBits = 16;
9569let opExtentAlign = 0;
9570}
9571def L2_loadrd_io : HInst<
9572(outs DoubleRegs:$Rdd32),
9573(ins IntRegs:$Rs32, s29_3Imm:$Ii),
9574"$Rdd32 = memd($Rs32+#$Ii)",
9575tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
9576let Inst{24-21} = 0b1110;
9577let Inst{31-27} = 0b10010;
9578let addrMode = BaseImmOffset;
9579let accessSize = DoubleWordAccess;
9580let mayLoad = 1;
9581let BaseOpcode = "L2_loadrd_io";
9582let CextOpcode = "L2_loadrd";
9583let isPredicable = 1;
9584let isExtendable = 1;
9585let opExtendable = 2;
9586let isExtentSigned = 1;
9587let opExtentBits = 14;
9588let opExtentAlign = 3;
9589}
9590def L2_loadrd_pbr : HInst<
9591(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9592(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9593"$Rdd32 = memd($Rx32++$Mu2:brev)",
9594tc_075c8dd8, TypeLD>, Enc_7eee72 {
9595let Inst{12-5} = 0b00000000;
9596let Inst{31-21} = 0b10011111110;
9597let addrMode = PostInc;
9598let accessSize = DoubleWordAccess;
9599let mayLoad = 1;
9600let Constraints = "$Rx32 = $Rx32in";
9601}
9602def L2_loadrd_pci : HInst<
9603(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9604(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
9605"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
9606tc_5ceb2f9e, TypeLD>, Enc_b05839 {
9607let Inst{12-9} = 0b0000;
9608let Inst{31-21} = 0b10011001110;
9609let addrMode = PostInc;
9610let accessSize = DoubleWordAccess;
9611let mayLoad = 1;
9612let Uses = [CS];
9613let Constraints = "$Rx32 = $Rx32in";
9614}
9615def L2_loadrd_pcr : HInst<
9616(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9617(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9618"$Rdd32 = memd($Rx32++I:circ($Mu2))",
9619tc_075c8dd8, TypeLD>, Enc_7eee72 {
9620let Inst{12-5} = 0b00010000;
9621let Inst{31-21} = 0b10011001110;
9622let addrMode = PostInc;
9623let accessSize = DoubleWordAccess;
9624let mayLoad = 1;
9625let Uses = [CS];
9626let Constraints = "$Rx32 = $Rx32in";
9627}
9628def L2_loadrd_pi : HInst<
9629(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9630(ins IntRegs:$Rx32in, s4_3Imm:$Ii),
9631"$Rdd32 = memd($Rx32++#$Ii)",
9632tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
9633let Inst{13-9} = 0b00000;
9634let Inst{31-21} = 0b10011011110;
9635let addrMode = PostInc;
9636let accessSize = DoubleWordAccess;
9637let mayLoad = 1;
9638let BaseOpcode = "L2_loadrd_pi";
9639let CextOpcode = "L2_loadrd";
9640let isPredicable = 1;
9641let Constraints = "$Rx32 = $Rx32in";
9642}
9643def L2_loadrd_pr : HInst<
9644(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9645(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9646"$Rdd32 = memd($Rx32++$Mu2)",
9647tc_075c8dd8, TypeLD>, Enc_7eee72 {
9648let Inst{12-5} = 0b00000000;
9649let Inst{31-21} = 0b10011101110;
9650let addrMode = PostInc;
9651let accessSize = DoubleWordAccess;
9652let mayLoad = 1;
9653let Constraints = "$Rx32 = $Rx32in";
9654}
9655def L2_loadrd_zomap : HInst<
9656(outs DoubleRegs:$Rdd32),
9657(ins IntRegs:$Rs32),
9658"$Rdd32 = memd($Rs32)",
9659tc_4222e6bf, TypeMAPPING> {
9660let isPseudo = 1;
9661let isCodeGenOnly = 1;
9662}
9663def L2_loadrdgp : HInst<
9664(outs DoubleRegs:$Rdd32),
9665(ins u29_3Imm:$Ii),
9666"$Rdd32 = memd(gp+#$Ii)",
9667tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
9668let Inst{24-21} = 0b1110;
9669let Inst{31-27} = 0b01001;
9670let accessSize = DoubleWordAccess;
9671let mayLoad = 1;
9672let Uses = [GP];
9673let BaseOpcode = "L4_loadrd_abs";
9674let isPredicable = 1;
9675let opExtendable = 1;
9676let isExtentSigned = 0;
9677let opExtentBits = 19;
9678let opExtentAlign = 3;
9679}
9680def L2_loadrh_io : HInst<
9681(outs IntRegs:$Rd32),
9682(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9683"$Rd32 = memh($Rs32+#$Ii)",
9684tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9685let Inst{24-21} = 0b1010;
9686let Inst{31-27} = 0b10010;
9687let hasNewValue = 1;
9688let opNewValue = 0;
9689let addrMode = BaseImmOffset;
9690let accessSize = HalfWordAccess;
9691let mayLoad = 1;
9692let BaseOpcode = "L2_loadrh_io";
9693let CextOpcode = "L2_loadrh";
9694let isPredicable = 1;
9695let isExtendable = 1;
9696let opExtendable = 2;
9697let isExtentSigned = 1;
9698let opExtentBits = 12;
9699let opExtentAlign = 1;
9700}
9701def L2_loadrh_pbr : HInst<
9702(outs IntRegs:$Rd32, IntRegs:$Rx32),
9703(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9704"$Rd32 = memh($Rx32++$Mu2:brev)",
9705tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9706let Inst{12-5} = 0b00000000;
9707let Inst{31-21} = 0b10011111010;
9708let hasNewValue = 1;
9709let opNewValue = 0;
9710let addrMode = PostInc;
9711let accessSize = HalfWordAccess;
9712let mayLoad = 1;
9713let Constraints = "$Rx32 = $Rx32in";
9714}
9715def L2_loadrh_pci : HInst<
9716(outs IntRegs:$Rd32, IntRegs:$Rx32),
9717(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9718"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
9719tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9720let Inst{12-9} = 0b0000;
9721let Inst{31-21} = 0b10011001010;
9722let hasNewValue = 1;
9723let opNewValue = 0;
9724let addrMode = PostInc;
9725let accessSize = HalfWordAccess;
9726let mayLoad = 1;
9727let Uses = [CS];
9728let Constraints = "$Rx32 = $Rx32in";
9729}
9730def L2_loadrh_pcr : HInst<
9731(outs IntRegs:$Rd32, IntRegs:$Rx32),
9732(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9733"$Rd32 = memh($Rx32++I:circ($Mu2))",
9734tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9735let Inst{12-5} = 0b00010000;
9736let Inst{31-21} = 0b10011001010;
9737let hasNewValue = 1;
9738let opNewValue = 0;
9739let addrMode = PostInc;
9740let accessSize = HalfWordAccess;
9741let mayLoad = 1;
9742let Uses = [CS];
9743let Constraints = "$Rx32 = $Rx32in";
9744}
9745def L2_loadrh_pi : HInst<
9746(outs IntRegs:$Rd32, IntRegs:$Rx32),
9747(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9748"$Rd32 = memh($Rx32++#$Ii)",
9749tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9750let Inst{13-9} = 0b00000;
9751let Inst{31-21} = 0b10011011010;
9752let hasNewValue = 1;
9753let opNewValue = 0;
9754let addrMode = PostInc;
9755let accessSize = HalfWordAccess;
9756let mayLoad = 1;
9757let BaseOpcode = "L2_loadrh_pi";
9758let CextOpcode = "L2_loadrh";
9759let isPredicable = 1;
9760let Constraints = "$Rx32 = $Rx32in";
9761}
9762def L2_loadrh_pr : HInst<
9763(outs IntRegs:$Rd32, IntRegs:$Rx32),
9764(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9765"$Rd32 = memh($Rx32++$Mu2)",
9766tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9767let Inst{12-5} = 0b00000000;
9768let Inst{31-21} = 0b10011101010;
9769let hasNewValue = 1;
9770let opNewValue = 0;
9771let addrMode = PostInc;
9772let accessSize = HalfWordAccess;
9773let mayLoad = 1;
9774let Constraints = "$Rx32 = $Rx32in";
9775}
9776def L2_loadrh_zomap : HInst<
9777(outs IntRegs:$Rd32),
9778(ins IntRegs:$Rs32),
9779"$Rd32 = memh($Rs32)",
9780tc_4222e6bf, TypeMAPPING> {
9781let hasNewValue = 1;
9782let opNewValue = 0;
9783let isPseudo = 1;
9784let isCodeGenOnly = 1;
9785}
9786def L2_loadrhgp : HInst<
9787(outs IntRegs:$Rd32),
9788(ins u31_1Imm:$Ii),
9789"$Rd32 = memh(gp+#$Ii)",
9790tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9791let Inst{24-21} = 0b1010;
9792let Inst{31-27} = 0b01001;
9793let hasNewValue = 1;
9794let opNewValue = 0;
9795let accessSize = HalfWordAccess;
9796let mayLoad = 1;
9797let Uses = [GP];
9798let BaseOpcode = "L4_loadrh_abs";
9799let isPredicable = 1;
9800let opExtendable = 1;
9801let isExtentSigned = 0;
9802let opExtentBits = 17;
9803let opExtentAlign = 1;
9804}
9805def L2_loadri_io : HInst<
9806(outs IntRegs:$Rd32),
9807(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9808"$Rd32 = memw($Rs32+#$Ii)",
9809tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
9810let Inst{24-21} = 0b1100;
9811let Inst{31-27} = 0b10010;
9812let hasNewValue = 1;
9813let opNewValue = 0;
9814let addrMode = BaseImmOffset;
9815let accessSize = WordAccess;
9816let mayLoad = 1;
9817let BaseOpcode = "L2_loadri_io";
9818let CextOpcode = "L2_loadri";
9819let isPredicable = 1;
9820let isExtendable = 1;
9821let opExtendable = 2;
9822let isExtentSigned = 1;
9823let opExtentBits = 13;
9824let opExtentAlign = 2;
9825}
9826def L2_loadri_pbr : HInst<
9827(outs IntRegs:$Rd32, IntRegs:$Rx32),
9828(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9829"$Rd32 = memw($Rx32++$Mu2:brev)",
9830tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9831let Inst{12-5} = 0b00000000;
9832let Inst{31-21} = 0b10011111100;
9833let hasNewValue = 1;
9834let opNewValue = 0;
9835let addrMode = PostInc;
9836let accessSize = WordAccess;
9837let mayLoad = 1;
9838let Constraints = "$Rx32 = $Rx32in";
9839}
9840def L2_loadri_pci : HInst<
9841(outs IntRegs:$Rd32, IntRegs:$Rx32),
9842(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9843"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
9844tc_5ceb2f9e, TypeLD>, Enc_27fd0e {
9845let Inst{12-9} = 0b0000;
9846let Inst{31-21} = 0b10011001100;
9847let hasNewValue = 1;
9848let opNewValue = 0;
9849let addrMode = PostInc;
9850let accessSize = WordAccess;
9851let mayLoad = 1;
9852let Uses = [CS];
9853let Constraints = "$Rx32 = $Rx32in";
9854}
9855def L2_loadri_pcr : HInst<
9856(outs IntRegs:$Rd32, IntRegs:$Rx32),
9857(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9858"$Rd32 = memw($Rx32++I:circ($Mu2))",
9859tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9860let Inst{12-5} = 0b00010000;
9861let Inst{31-21} = 0b10011001100;
9862let hasNewValue = 1;
9863let opNewValue = 0;
9864let addrMode = PostInc;
9865let accessSize = WordAccess;
9866let mayLoad = 1;
9867let Uses = [CS];
9868let Constraints = "$Rx32 = $Rx32in";
9869}
9870def L2_loadri_pi : HInst<
9871(outs IntRegs:$Rd32, IntRegs:$Rx32),
9872(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9873"$Rd32 = memw($Rx32++#$Ii)",
9874tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
9875let Inst{13-9} = 0b00000;
9876let Inst{31-21} = 0b10011011100;
9877let hasNewValue = 1;
9878let opNewValue = 0;
9879let addrMode = PostInc;
9880let accessSize = WordAccess;
9881let mayLoad = 1;
9882let BaseOpcode = "L2_loadri_pi";
9883let CextOpcode = "L2_loadri";
9884let isPredicable = 1;
9885let Constraints = "$Rx32 = $Rx32in";
9886}
9887def L2_loadri_pr : HInst<
9888(outs IntRegs:$Rd32, IntRegs:$Rx32),
9889(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9890"$Rd32 = memw($Rx32++$Mu2)",
9891tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9892let Inst{12-5} = 0b00000000;
9893let Inst{31-21} = 0b10011101100;
9894let hasNewValue = 1;
9895let opNewValue = 0;
9896let addrMode = PostInc;
9897let accessSize = WordAccess;
9898let mayLoad = 1;
9899let Constraints = "$Rx32 = $Rx32in";
9900}
9901def L2_loadri_zomap : HInst<
9902(outs IntRegs:$Rd32),
9903(ins IntRegs:$Rs32),
9904"$Rd32 = memw($Rs32)",
9905tc_4222e6bf, TypeMAPPING> {
9906let hasNewValue = 1;
9907let opNewValue = 0;
9908let isPseudo = 1;
9909let isCodeGenOnly = 1;
9910}
9911def L2_loadrigp : HInst<
9912(outs IntRegs:$Rd32),
9913(ins u30_2Imm:$Ii),
9914"$Rd32 = memw(gp+#$Ii)",
9915tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
9916let Inst{24-21} = 0b1100;
9917let Inst{31-27} = 0b01001;
9918let hasNewValue = 1;
9919let opNewValue = 0;
9920let accessSize = WordAccess;
9921let mayLoad = 1;
9922let Uses = [GP];
9923let BaseOpcode = "L4_loadri_abs";
9924let isPredicable = 1;
9925let opExtendable = 1;
9926let isExtentSigned = 0;
9927let opExtentBits = 18;
9928let opExtentAlign = 2;
9929}
9930def L2_loadrub_io : HInst<
9931(outs IntRegs:$Rd32),
9932(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9933"$Rd32 = memub($Rs32+#$Ii)",
9934tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9935let Inst{24-21} = 0b1001;
9936let Inst{31-27} = 0b10010;
9937let hasNewValue = 1;
9938let opNewValue = 0;
9939let addrMode = BaseImmOffset;
9940let accessSize = ByteAccess;
9941let mayLoad = 1;
9942let BaseOpcode = "L2_loadrub_io";
9943let CextOpcode = "L2_loadrub";
9944let isPredicable = 1;
9945let isExtendable = 1;
9946let opExtendable = 2;
9947let isExtentSigned = 1;
9948let opExtentBits = 11;
9949let opExtentAlign = 0;
9950}
9951def L2_loadrub_pbr : HInst<
9952(outs IntRegs:$Rd32, IntRegs:$Rx32),
9953(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9954"$Rd32 = memub($Rx32++$Mu2:brev)",
9955tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9956let Inst{12-5} = 0b00000000;
9957let Inst{31-21} = 0b10011111001;
9958let hasNewValue = 1;
9959let opNewValue = 0;
9960let addrMode = PostInc;
9961let accessSize = ByteAccess;
9962let mayLoad = 1;
9963let Constraints = "$Rx32 = $Rx32in";
9964}
9965def L2_loadrub_pci : HInst<
9966(outs IntRegs:$Rd32, IntRegs:$Rx32),
9967(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9968"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
9969tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9970let Inst{12-9} = 0b0000;
9971let Inst{31-21} = 0b10011001001;
9972let hasNewValue = 1;
9973let opNewValue = 0;
9974let addrMode = PostInc;
9975let accessSize = ByteAccess;
9976let mayLoad = 1;
9977let Uses = [CS];
9978let Constraints = "$Rx32 = $Rx32in";
9979}
9980def L2_loadrub_pcr : HInst<
9981(outs IntRegs:$Rd32, IntRegs:$Rx32),
9982(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9983"$Rd32 = memub($Rx32++I:circ($Mu2))",
9984tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9985let Inst{12-5} = 0b00010000;
9986let Inst{31-21} = 0b10011001001;
9987let hasNewValue = 1;
9988let opNewValue = 0;
9989let addrMode = PostInc;
9990let accessSize = ByteAccess;
9991let mayLoad = 1;
9992let Uses = [CS];
9993let Constraints = "$Rx32 = $Rx32in";
9994}
9995def L2_loadrub_pi : HInst<
9996(outs IntRegs:$Rd32, IntRegs:$Rx32),
9997(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9998"$Rd32 = memub($Rx32++#$Ii)",
9999tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
10000let Inst{13-9} = 0b00000;
10001let Inst{31-21} = 0b10011011001;
10002let hasNewValue = 1;
10003let opNewValue = 0;
10004let addrMode = PostInc;
10005let accessSize = ByteAccess;
10006let mayLoad = 1;
10007let BaseOpcode = "L2_loadrub_pi";
10008let CextOpcode = "L2_loadrub";
10009let isPredicable = 1;
10010let Constraints = "$Rx32 = $Rx32in";
10011}
10012def L2_loadrub_pr : HInst<
10013(outs IntRegs:$Rd32, IntRegs:$Rx32),
10014(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10015"$Rd32 = memub($Rx32++$Mu2)",
10016tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10017let Inst{12-5} = 0b00000000;
10018let Inst{31-21} = 0b10011101001;
10019let hasNewValue = 1;
10020let opNewValue = 0;
10021let addrMode = PostInc;
10022let accessSize = ByteAccess;
10023let mayLoad = 1;
10024let Constraints = "$Rx32 = $Rx32in";
10025}
10026def L2_loadrub_zomap : HInst<
10027(outs IntRegs:$Rd32),
10028(ins IntRegs:$Rs32),
10029"$Rd32 = memub($Rs32)",
10030tc_4222e6bf, TypeMAPPING> {
10031let hasNewValue = 1;
10032let opNewValue = 0;
10033let isPseudo = 1;
10034let isCodeGenOnly = 1;
10035}
10036def L2_loadrubgp : HInst<
10037(outs IntRegs:$Rd32),
10038(ins u32_0Imm:$Ii),
10039"$Rd32 = memub(gp+#$Ii)",
10040tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
10041let Inst{24-21} = 0b1001;
10042let Inst{31-27} = 0b01001;
10043let hasNewValue = 1;
10044let opNewValue = 0;
10045let accessSize = ByteAccess;
10046let mayLoad = 1;
10047let Uses = [GP];
10048let BaseOpcode = "L4_loadrub_abs";
10049let isPredicable = 1;
10050let opExtendable = 1;
10051let isExtentSigned = 0;
10052let opExtentBits = 16;
10053let opExtentAlign = 0;
10054}
10055def L2_loadruh_io : HInst<
10056(outs IntRegs:$Rd32),
10057(ins IntRegs:$Rs32, s31_1Imm:$Ii),
10058"$Rd32 = memuh($Rs32+#$Ii)",
10059tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
10060let Inst{24-21} = 0b1011;
10061let Inst{31-27} = 0b10010;
10062let hasNewValue = 1;
10063let opNewValue = 0;
10064let addrMode = BaseImmOffset;
10065let accessSize = HalfWordAccess;
10066let mayLoad = 1;
10067let BaseOpcode = "L2_loadruh_io";
10068let CextOpcode = "L2_loadruh";
10069let isPredicable = 1;
10070let isExtendable = 1;
10071let opExtendable = 2;
10072let isExtentSigned = 1;
10073let opExtentBits = 12;
10074let opExtentAlign = 1;
10075}
10076def L2_loadruh_pbr : HInst<
10077(outs IntRegs:$Rd32, IntRegs:$Rx32),
10078(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10079"$Rd32 = memuh($Rx32++$Mu2:brev)",
10080tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10081let Inst{12-5} = 0b00000000;
10082let Inst{31-21} = 0b10011111011;
10083let hasNewValue = 1;
10084let opNewValue = 0;
10085let addrMode = PostInc;
10086let accessSize = HalfWordAccess;
10087let mayLoad = 1;
10088let Constraints = "$Rx32 = $Rx32in";
10089}
10090def L2_loadruh_pci : HInst<
10091(outs IntRegs:$Rd32, IntRegs:$Rx32),
10092(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
10093"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
10094tc_5ceb2f9e, TypeLD>, Enc_e83554 {
10095let Inst{12-9} = 0b0000;
10096let Inst{31-21} = 0b10011001011;
10097let hasNewValue = 1;
10098let opNewValue = 0;
10099let addrMode = PostInc;
10100let accessSize = HalfWordAccess;
10101let mayLoad = 1;
10102let Uses = [CS];
10103let Constraints = "$Rx32 = $Rx32in";
10104}
10105def L2_loadruh_pcr : HInst<
10106(outs IntRegs:$Rd32, IntRegs:$Rx32),
10107(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10108"$Rd32 = memuh($Rx32++I:circ($Mu2))",
10109tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10110let Inst{12-5} = 0b00010000;
10111let Inst{31-21} = 0b10011001011;
10112let hasNewValue = 1;
10113let opNewValue = 0;
10114let addrMode = PostInc;
10115let accessSize = HalfWordAccess;
10116let mayLoad = 1;
10117let Uses = [CS];
10118let Constraints = "$Rx32 = $Rx32in";
10119}
10120def L2_loadruh_pi : HInst<
10121(outs IntRegs:$Rd32, IntRegs:$Rx32),
10122(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
10123"$Rd32 = memuh($Rx32++#$Ii)",
10124tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
10125let Inst{13-9} = 0b00000;
10126let Inst{31-21} = 0b10011011011;
10127let hasNewValue = 1;
10128let opNewValue = 0;
10129let addrMode = PostInc;
10130let accessSize = HalfWordAccess;
10131let mayLoad = 1;
10132let BaseOpcode = "L2_loadruh_pi";
10133let CextOpcode = "L2_loadruh";
10134let isPredicable = 1;
10135let Constraints = "$Rx32 = $Rx32in";
10136}
10137def L2_loadruh_pr : HInst<
10138(outs IntRegs:$Rd32, IntRegs:$Rx32),
10139(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10140"$Rd32 = memuh($Rx32++$Mu2)",
10141tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10142let Inst{12-5} = 0b00000000;
10143let Inst{31-21} = 0b10011101011;
10144let hasNewValue = 1;
10145let opNewValue = 0;
10146let addrMode = PostInc;
10147let accessSize = HalfWordAccess;
10148let mayLoad = 1;
10149let Constraints = "$Rx32 = $Rx32in";
10150}
10151def L2_loadruh_zomap : HInst<
10152(outs IntRegs:$Rd32),
10153(ins IntRegs:$Rs32),
10154"$Rd32 = memuh($Rs32)",
10155tc_4222e6bf, TypeMAPPING> {
10156let hasNewValue = 1;
10157let opNewValue = 0;
10158let isPseudo = 1;
10159let isCodeGenOnly = 1;
10160}
10161def L2_loadruhgp : HInst<
10162(outs IntRegs:$Rd32),
10163(ins u31_1Imm:$Ii),
10164"$Rd32 = memuh(gp+#$Ii)",
10165tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
10166let Inst{24-21} = 0b1011;
10167let Inst{31-27} = 0b01001;
10168let hasNewValue = 1;
10169let opNewValue = 0;
10170let accessSize = HalfWordAccess;
10171let mayLoad = 1;
10172let Uses = [GP];
10173let BaseOpcode = "L4_loadruh_abs";
10174let isPredicable = 1;
10175let opExtendable = 1;
10176let isExtentSigned = 0;
10177let opExtentBits = 17;
10178let opExtentAlign = 1;
10179}
10180def L2_loadw_aq : HInst<
10181(outs IntRegs:$Rd32),
10182(ins IntRegs:$Rs32),
10183"$Rd32 = memw_aq($Rs32)",
10184tc_2471c1c8, TypeLD>, Enc_5e2823, Requires<[HasV68]> {
10185let Inst{13-5} = 0b001000000;
10186let Inst{31-21} = 0b10010010000;
10187let hasNewValue = 1;
10188let opNewValue = 0;
10189let accessSize = WordAccess;
10190let mayLoad = 1;
10191}
10192def L2_loadw_locked : HInst<
10193(outs IntRegs:$Rd32),
10194(ins IntRegs:$Rs32),
10195"$Rd32 = memw_locked($Rs32)",
10196tc_64b00d8a, TypeLD>, Enc_5e2823 {
10197let Inst{13-5} = 0b000000000;
10198let Inst{31-21} = 0b10010010000;
10199let hasNewValue = 1;
10200let opNewValue = 0;
10201let accessSize = WordAccess;
10202let mayLoad = 1;
10203let isSoloAX = 1;
10204}
10205def L2_ploadrbf_io : HInst<
10206(outs IntRegs:$Rd32),
10207(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10208"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
10209tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10210let Inst{13-13} = 0b0;
10211let Inst{31-21} = 0b01000101000;
10212let isPredicated = 1;
10213let isPredicatedFalse = 1;
10214let hasNewValue = 1;
10215let opNewValue = 0;
10216let addrMode = BaseImmOffset;
10217let accessSize = ByteAccess;
10218let mayLoad = 1;
10219let BaseOpcode = "L2_loadrb_io";
10220let CextOpcode = "L2_loadrb";
10221let isExtendable = 1;
10222let opExtendable = 3;
10223let isExtentSigned = 0;
10224let opExtentBits = 6;
10225let opExtentAlign = 0;
10226}
10227def L2_ploadrbf_pi : HInst<
10228(outs IntRegs:$Rd32, IntRegs:$Rx32),
10229(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10230"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
10231tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10232let Inst{13-11} = 0b101;
10233let Inst{31-21} = 0b10011011000;
10234let isPredicated = 1;
10235let isPredicatedFalse = 1;
10236let hasNewValue = 1;
10237let opNewValue = 0;
10238let addrMode = PostInc;
10239let accessSize = ByteAccess;
10240let mayLoad = 1;
10241let BaseOpcode = "L2_loadrb_pi";
10242let Constraints = "$Rx32 = $Rx32in";
10243}
10244def L2_ploadrbf_zomap : HInst<
10245(outs IntRegs:$Rd32),
10246(ins PredRegs:$Pt4, IntRegs:$Rs32),
10247"if (!$Pt4) $Rd32 = memb($Rs32)",
10248tc_fedb7e19, TypeMAPPING> {
10249let hasNewValue = 1;
10250let opNewValue = 0;
10251let isPseudo = 1;
10252let isCodeGenOnly = 1;
10253}
10254def L2_ploadrbfnew_io : HInst<
10255(outs IntRegs:$Rd32),
10256(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10257"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10258tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10259let Inst{13-13} = 0b0;
10260let Inst{31-21} = 0b01000111000;
10261let isPredicated = 1;
10262let isPredicatedFalse = 1;
10263let hasNewValue = 1;
10264let opNewValue = 0;
10265let addrMode = BaseImmOffset;
10266let accessSize = ByteAccess;
10267let isPredicatedNew = 1;
10268let mayLoad = 1;
10269let BaseOpcode = "L2_loadrb_io";
10270let CextOpcode = "L2_loadrb";
10271let isExtendable = 1;
10272let opExtendable = 3;
10273let isExtentSigned = 0;
10274let opExtentBits = 6;
10275let opExtentAlign = 0;
10276}
10277def L2_ploadrbfnew_pi : HInst<
10278(outs IntRegs:$Rd32, IntRegs:$Rx32),
10279(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10280"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10281tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10282let Inst{13-11} = 0b111;
10283let Inst{31-21} = 0b10011011000;
10284let isPredicated = 1;
10285let isPredicatedFalse = 1;
10286let hasNewValue = 1;
10287let opNewValue = 0;
10288let addrMode = PostInc;
10289let accessSize = ByteAccess;
10290let isPredicatedNew = 1;
10291let mayLoad = 1;
10292let BaseOpcode = "L2_loadrb_pi";
10293let Constraints = "$Rx32 = $Rx32in";
10294}
10295def L2_ploadrbfnew_zomap : HInst<
10296(outs IntRegs:$Rd32),
10297(ins PredRegs:$Pt4, IntRegs:$Rs32),
10298"if (!$Pt4.new) $Rd32 = memb($Rs32)",
10299tc_075c8dd8, TypeMAPPING> {
10300let hasNewValue = 1;
10301let opNewValue = 0;
10302let isPseudo = 1;
10303let isCodeGenOnly = 1;
10304}
10305def L2_ploadrbt_io : HInst<
10306(outs IntRegs:$Rd32),
10307(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10308"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
10309tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10310let Inst{13-13} = 0b0;
10311let Inst{31-21} = 0b01000001000;
10312let isPredicated = 1;
10313let hasNewValue = 1;
10314let opNewValue = 0;
10315let addrMode = BaseImmOffset;
10316let accessSize = ByteAccess;
10317let mayLoad = 1;
10318let BaseOpcode = "L2_loadrb_io";
10319let CextOpcode = "L2_loadrb";
10320let isExtendable = 1;
10321let opExtendable = 3;
10322let isExtentSigned = 0;
10323let opExtentBits = 6;
10324let opExtentAlign = 0;
10325}
10326def L2_ploadrbt_pi : HInst<
10327(outs IntRegs:$Rd32, IntRegs:$Rx32),
10328(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10329"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
10330tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10331let Inst{13-11} = 0b100;
10332let Inst{31-21} = 0b10011011000;
10333let isPredicated = 1;
10334let hasNewValue = 1;
10335let opNewValue = 0;
10336let addrMode = PostInc;
10337let accessSize = ByteAccess;
10338let mayLoad = 1;
10339let BaseOpcode = "L2_loadrb_pi";
10340let Constraints = "$Rx32 = $Rx32in";
10341}
10342def L2_ploadrbt_zomap : HInst<
10343(outs IntRegs:$Rd32),
10344(ins PredRegs:$Pt4, IntRegs:$Rs32),
10345"if ($Pt4) $Rd32 = memb($Rs32)",
10346tc_fedb7e19, TypeMAPPING> {
10347let hasNewValue = 1;
10348let opNewValue = 0;
10349let isPseudo = 1;
10350let isCodeGenOnly = 1;
10351}
10352def L2_ploadrbtnew_io : HInst<
10353(outs IntRegs:$Rd32),
10354(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10355"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10356tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10357let Inst{13-13} = 0b0;
10358let Inst{31-21} = 0b01000011000;
10359let isPredicated = 1;
10360let hasNewValue = 1;
10361let opNewValue = 0;
10362let addrMode = BaseImmOffset;
10363let accessSize = ByteAccess;
10364let isPredicatedNew = 1;
10365let mayLoad = 1;
10366let BaseOpcode = "L2_loadrb_io";
10367let CextOpcode = "L2_loadrb";
10368let isExtendable = 1;
10369let opExtendable = 3;
10370let isExtentSigned = 0;
10371let opExtentBits = 6;
10372let opExtentAlign = 0;
10373}
10374def L2_ploadrbtnew_pi : HInst<
10375(outs IntRegs:$Rd32, IntRegs:$Rx32),
10376(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10377"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10378tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10379let Inst{13-11} = 0b110;
10380let Inst{31-21} = 0b10011011000;
10381let isPredicated = 1;
10382let hasNewValue = 1;
10383let opNewValue = 0;
10384let addrMode = PostInc;
10385let accessSize = ByteAccess;
10386let isPredicatedNew = 1;
10387let mayLoad = 1;
10388let BaseOpcode = "L2_loadrb_pi";
10389let Constraints = "$Rx32 = $Rx32in";
10390}
10391def L2_ploadrbtnew_zomap : HInst<
10392(outs IntRegs:$Rd32),
10393(ins PredRegs:$Pt4, IntRegs:$Rs32),
10394"if ($Pt4.new) $Rd32 = memb($Rs32)",
10395tc_075c8dd8, TypeMAPPING> {
10396let hasNewValue = 1;
10397let opNewValue = 0;
10398let isPseudo = 1;
10399let isCodeGenOnly = 1;
10400}
10401def L2_ploadrdf_io : HInst<
10402(outs DoubleRegs:$Rdd32),
10403(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10404"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10405tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10406let Inst{13-13} = 0b0;
10407let Inst{31-21} = 0b01000101110;
10408let isPredicated = 1;
10409let isPredicatedFalse = 1;
10410let addrMode = BaseImmOffset;
10411let accessSize = DoubleWordAccess;
10412let mayLoad = 1;
10413let BaseOpcode = "L2_loadrd_io";
10414let CextOpcode = "L2_loadrd";
10415let isExtendable = 1;
10416let opExtendable = 3;
10417let isExtentSigned = 0;
10418let opExtentBits = 9;
10419let opExtentAlign = 3;
10420}
10421def L2_ploadrdf_pi : HInst<
10422(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10423(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10424"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10425tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10426let Inst{13-11} = 0b101;
10427let Inst{31-21} = 0b10011011110;
10428let isPredicated = 1;
10429let isPredicatedFalse = 1;
10430let addrMode = PostInc;
10431let accessSize = DoubleWordAccess;
10432let mayLoad = 1;
10433let BaseOpcode = "L2_loadrd_pi";
10434let Constraints = "$Rx32 = $Rx32in";
10435}
10436def L2_ploadrdf_zomap : HInst<
10437(outs DoubleRegs:$Rdd32),
10438(ins PredRegs:$Pt4, IntRegs:$Rs32),
10439"if (!$Pt4) $Rdd32 = memd($Rs32)",
10440tc_fedb7e19, TypeMAPPING> {
10441let isPseudo = 1;
10442let isCodeGenOnly = 1;
10443}
10444def L2_ploadrdfnew_io : HInst<
10445(outs DoubleRegs:$Rdd32),
10446(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10447"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10448tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10449let Inst{13-13} = 0b0;
10450let Inst{31-21} = 0b01000111110;
10451let isPredicated = 1;
10452let isPredicatedFalse = 1;
10453let addrMode = BaseImmOffset;
10454let accessSize = DoubleWordAccess;
10455let isPredicatedNew = 1;
10456let mayLoad = 1;
10457let BaseOpcode = "L2_loadrd_io";
10458let CextOpcode = "L2_loadrd";
10459let isExtendable = 1;
10460let opExtendable = 3;
10461let isExtentSigned = 0;
10462let opExtentBits = 9;
10463let opExtentAlign = 3;
10464}
10465def L2_ploadrdfnew_pi : HInst<
10466(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10467(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10468"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10469tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10470let Inst{13-11} = 0b111;
10471let Inst{31-21} = 0b10011011110;
10472let isPredicated = 1;
10473let isPredicatedFalse = 1;
10474let addrMode = PostInc;
10475let accessSize = DoubleWordAccess;
10476let isPredicatedNew = 1;
10477let mayLoad = 1;
10478let BaseOpcode = "L2_loadrd_pi";
10479let Constraints = "$Rx32 = $Rx32in";
10480}
10481def L2_ploadrdfnew_zomap : HInst<
10482(outs DoubleRegs:$Rdd32),
10483(ins PredRegs:$Pt4, IntRegs:$Rs32),
10484"if (!$Pt4.new) $Rdd32 = memd($Rs32)",
10485tc_075c8dd8, TypeMAPPING> {
10486let isPseudo = 1;
10487let isCodeGenOnly = 1;
10488}
10489def L2_ploadrdt_io : HInst<
10490(outs DoubleRegs:$Rdd32),
10491(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10492"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10493tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10494let Inst{13-13} = 0b0;
10495let Inst{31-21} = 0b01000001110;
10496let isPredicated = 1;
10497let addrMode = BaseImmOffset;
10498let accessSize = DoubleWordAccess;
10499let mayLoad = 1;
10500let BaseOpcode = "L2_loadrd_io";
10501let CextOpcode = "L2_loadrd";
10502let isExtendable = 1;
10503let opExtendable = 3;
10504let isExtentSigned = 0;
10505let opExtentBits = 9;
10506let opExtentAlign = 3;
10507}
10508def L2_ploadrdt_pi : HInst<
10509(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10510(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10511"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10512tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10513let Inst{13-11} = 0b100;
10514let Inst{31-21} = 0b10011011110;
10515let isPredicated = 1;
10516let addrMode = PostInc;
10517let accessSize = DoubleWordAccess;
10518let mayLoad = 1;
10519let BaseOpcode = "L2_loadrd_pi";
10520let Constraints = "$Rx32 = $Rx32in";
10521}
10522def L2_ploadrdt_zomap : HInst<
10523(outs DoubleRegs:$Rdd32),
10524(ins PredRegs:$Pt4, IntRegs:$Rs32),
10525"if ($Pt4) $Rdd32 = memd($Rs32)",
10526tc_fedb7e19, TypeMAPPING> {
10527let isPseudo = 1;
10528let isCodeGenOnly = 1;
10529}
10530def L2_ploadrdtnew_io : HInst<
10531(outs DoubleRegs:$Rdd32),
10532(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10533"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10534tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10535let Inst{13-13} = 0b0;
10536let Inst{31-21} = 0b01000011110;
10537let isPredicated = 1;
10538let addrMode = BaseImmOffset;
10539let accessSize = DoubleWordAccess;
10540let isPredicatedNew = 1;
10541let mayLoad = 1;
10542let BaseOpcode = "L2_loadrd_io";
10543let CextOpcode = "L2_loadrd";
10544let isExtendable = 1;
10545let opExtendable = 3;
10546let isExtentSigned = 0;
10547let opExtentBits = 9;
10548let opExtentAlign = 3;
10549}
10550def L2_ploadrdtnew_pi : HInst<
10551(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10552(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10553"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10554tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10555let Inst{13-11} = 0b110;
10556let Inst{31-21} = 0b10011011110;
10557let isPredicated = 1;
10558let addrMode = PostInc;
10559let accessSize = DoubleWordAccess;
10560let isPredicatedNew = 1;
10561let mayLoad = 1;
10562let BaseOpcode = "L2_loadrd_pi";
10563let Constraints = "$Rx32 = $Rx32in";
10564}
10565def L2_ploadrdtnew_zomap : HInst<
10566(outs DoubleRegs:$Rdd32),
10567(ins PredRegs:$Pt4, IntRegs:$Rs32),
10568"if ($Pt4.new) $Rdd32 = memd($Rs32)",
10569tc_075c8dd8, TypeMAPPING> {
10570let isPseudo = 1;
10571let isCodeGenOnly = 1;
10572}
10573def L2_ploadrhf_io : HInst<
10574(outs IntRegs:$Rd32),
10575(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10576"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
10577tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10578let Inst{13-13} = 0b0;
10579let Inst{31-21} = 0b01000101010;
10580let isPredicated = 1;
10581let isPredicatedFalse = 1;
10582let hasNewValue = 1;
10583let opNewValue = 0;
10584let addrMode = BaseImmOffset;
10585let accessSize = HalfWordAccess;
10586let mayLoad = 1;
10587let BaseOpcode = "L2_loadrh_io";
10588let CextOpcode = "L2_loadrh";
10589let isExtendable = 1;
10590let opExtendable = 3;
10591let isExtentSigned = 0;
10592let opExtentBits = 7;
10593let opExtentAlign = 1;
10594}
10595def L2_ploadrhf_pi : HInst<
10596(outs IntRegs:$Rd32, IntRegs:$Rx32),
10597(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10598"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
10599tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10600let Inst{13-11} = 0b101;
10601let Inst{31-21} = 0b10011011010;
10602let isPredicated = 1;
10603let isPredicatedFalse = 1;
10604let hasNewValue = 1;
10605let opNewValue = 0;
10606let addrMode = PostInc;
10607let accessSize = HalfWordAccess;
10608let mayLoad = 1;
10609let BaseOpcode = "L2_loadrh_pi";
10610let Constraints = "$Rx32 = $Rx32in";
10611}
10612def L2_ploadrhf_zomap : HInst<
10613(outs IntRegs:$Rd32),
10614(ins PredRegs:$Pt4, IntRegs:$Rs32),
10615"if (!$Pt4) $Rd32 = memh($Rs32)",
10616tc_fedb7e19, TypeMAPPING> {
10617let hasNewValue = 1;
10618let opNewValue = 0;
10619let isPseudo = 1;
10620let isCodeGenOnly = 1;
10621}
10622def L2_ploadrhfnew_io : HInst<
10623(outs IntRegs:$Rd32),
10624(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10625"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10626tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10627let Inst{13-13} = 0b0;
10628let Inst{31-21} = 0b01000111010;
10629let isPredicated = 1;
10630let isPredicatedFalse = 1;
10631let hasNewValue = 1;
10632let opNewValue = 0;
10633let addrMode = BaseImmOffset;
10634let accessSize = HalfWordAccess;
10635let isPredicatedNew = 1;
10636let mayLoad = 1;
10637let BaseOpcode = "L2_loadrh_io";
10638let CextOpcode = "L2_loadrh";
10639let isExtendable = 1;
10640let opExtendable = 3;
10641let isExtentSigned = 0;
10642let opExtentBits = 7;
10643let opExtentAlign = 1;
10644}
10645def L2_ploadrhfnew_pi : HInst<
10646(outs IntRegs:$Rd32, IntRegs:$Rx32),
10647(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10648"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10649tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10650let Inst{13-11} = 0b111;
10651let Inst{31-21} = 0b10011011010;
10652let isPredicated = 1;
10653let isPredicatedFalse = 1;
10654let hasNewValue = 1;
10655let opNewValue = 0;
10656let addrMode = PostInc;
10657let accessSize = HalfWordAccess;
10658let isPredicatedNew = 1;
10659let mayLoad = 1;
10660let BaseOpcode = "L2_loadrh_pi";
10661let Constraints = "$Rx32 = $Rx32in";
10662}
10663def L2_ploadrhfnew_zomap : HInst<
10664(outs IntRegs:$Rd32),
10665(ins PredRegs:$Pt4, IntRegs:$Rs32),
10666"if (!$Pt4.new) $Rd32 = memh($Rs32)",
10667tc_075c8dd8, TypeMAPPING> {
10668let hasNewValue = 1;
10669let opNewValue = 0;
10670let isPseudo = 1;
10671let isCodeGenOnly = 1;
10672}
10673def L2_ploadrht_io : HInst<
10674(outs IntRegs:$Rd32),
10675(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10676"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
10677tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10678let Inst{13-13} = 0b0;
10679let Inst{31-21} = 0b01000001010;
10680let isPredicated = 1;
10681let hasNewValue = 1;
10682let opNewValue = 0;
10683let addrMode = BaseImmOffset;
10684let accessSize = HalfWordAccess;
10685let mayLoad = 1;
10686let BaseOpcode = "L2_loadrh_io";
10687let CextOpcode = "L2_loadrh";
10688let isExtendable = 1;
10689let opExtendable = 3;
10690let isExtentSigned = 0;
10691let opExtentBits = 7;
10692let opExtentAlign = 1;
10693}
10694def L2_ploadrht_pi : HInst<
10695(outs IntRegs:$Rd32, IntRegs:$Rx32),
10696(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10697"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
10698tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10699let Inst{13-11} = 0b100;
10700let Inst{31-21} = 0b10011011010;
10701let isPredicated = 1;
10702let hasNewValue = 1;
10703let opNewValue = 0;
10704let addrMode = PostInc;
10705let accessSize = HalfWordAccess;
10706let mayLoad = 1;
10707let BaseOpcode = "L2_loadrh_pi";
10708let Constraints = "$Rx32 = $Rx32in";
10709}
10710def L2_ploadrht_zomap : HInst<
10711(outs IntRegs:$Rd32),
10712(ins PredRegs:$Pt4, IntRegs:$Rs32),
10713"if ($Pt4) $Rd32 = memh($Rs32)",
10714tc_fedb7e19, TypeMAPPING> {
10715let hasNewValue = 1;
10716let opNewValue = 0;
10717let isPseudo = 1;
10718let isCodeGenOnly = 1;
10719}
10720def L2_ploadrhtnew_io : HInst<
10721(outs IntRegs:$Rd32),
10722(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10723"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10724tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10725let Inst{13-13} = 0b0;
10726let Inst{31-21} = 0b01000011010;
10727let isPredicated = 1;
10728let hasNewValue = 1;
10729let opNewValue = 0;
10730let addrMode = BaseImmOffset;
10731let accessSize = HalfWordAccess;
10732let isPredicatedNew = 1;
10733let mayLoad = 1;
10734let BaseOpcode = "L2_loadrh_io";
10735let CextOpcode = "L2_loadrh";
10736let isExtendable = 1;
10737let opExtendable = 3;
10738let isExtentSigned = 0;
10739let opExtentBits = 7;
10740let opExtentAlign = 1;
10741}
10742def L2_ploadrhtnew_pi : HInst<
10743(outs IntRegs:$Rd32, IntRegs:$Rx32),
10744(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10745"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10746tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10747let Inst{13-11} = 0b110;
10748let Inst{31-21} = 0b10011011010;
10749let isPredicated = 1;
10750let hasNewValue = 1;
10751let opNewValue = 0;
10752let addrMode = PostInc;
10753let accessSize = HalfWordAccess;
10754let isPredicatedNew = 1;
10755let mayLoad = 1;
10756let BaseOpcode = "L2_loadrh_pi";
10757let Constraints = "$Rx32 = $Rx32in";
10758}
10759def L2_ploadrhtnew_zomap : HInst<
10760(outs IntRegs:$Rd32),
10761(ins PredRegs:$Pt4, IntRegs:$Rs32),
10762"if ($Pt4.new) $Rd32 = memh($Rs32)",
10763tc_075c8dd8, TypeMAPPING> {
10764let hasNewValue = 1;
10765let opNewValue = 0;
10766let isPseudo = 1;
10767let isCodeGenOnly = 1;
10768}
10769def L2_ploadrif_io : HInst<
10770(outs IntRegs:$Rd32),
10771(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10772"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
10773tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10774let Inst{13-13} = 0b0;
10775let Inst{31-21} = 0b01000101100;
10776let isPredicated = 1;
10777let isPredicatedFalse = 1;
10778let hasNewValue = 1;
10779let opNewValue = 0;
10780let addrMode = BaseImmOffset;
10781let accessSize = WordAccess;
10782let mayLoad = 1;
10783let BaseOpcode = "L2_loadri_io";
10784let CextOpcode = "L2_loadri";
10785let isExtendable = 1;
10786let opExtendable = 3;
10787let isExtentSigned = 0;
10788let opExtentBits = 8;
10789let opExtentAlign = 2;
10790}
10791def L2_ploadrif_pi : HInst<
10792(outs IntRegs:$Rd32, IntRegs:$Rx32),
10793(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10794"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
10795tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10796let Inst{13-11} = 0b101;
10797let Inst{31-21} = 0b10011011100;
10798let isPredicated = 1;
10799let isPredicatedFalse = 1;
10800let hasNewValue = 1;
10801let opNewValue = 0;
10802let addrMode = PostInc;
10803let accessSize = WordAccess;
10804let mayLoad = 1;
10805let BaseOpcode = "L2_loadri_pi";
10806let Constraints = "$Rx32 = $Rx32in";
10807}
10808def L2_ploadrif_zomap : HInst<
10809(outs IntRegs:$Rd32),
10810(ins PredRegs:$Pt4, IntRegs:$Rs32),
10811"if (!$Pt4) $Rd32 = memw($Rs32)",
10812tc_fedb7e19, TypeMAPPING> {
10813let hasNewValue = 1;
10814let opNewValue = 0;
10815let isPseudo = 1;
10816let isCodeGenOnly = 1;
10817}
10818def L2_ploadrifnew_io : HInst<
10819(outs IntRegs:$Rd32),
10820(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10821"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10822tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10823let Inst{13-13} = 0b0;
10824let Inst{31-21} = 0b01000111100;
10825let isPredicated = 1;
10826let isPredicatedFalse = 1;
10827let hasNewValue = 1;
10828let opNewValue = 0;
10829let addrMode = BaseImmOffset;
10830let accessSize = WordAccess;
10831let isPredicatedNew = 1;
10832let mayLoad = 1;
10833let BaseOpcode = "L2_loadri_io";
10834let CextOpcode = "L2_loadri";
10835let isExtendable = 1;
10836let opExtendable = 3;
10837let isExtentSigned = 0;
10838let opExtentBits = 8;
10839let opExtentAlign = 2;
10840}
10841def L2_ploadrifnew_pi : HInst<
10842(outs IntRegs:$Rd32, IntRegs:$Rx32),
10843(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10844"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10845tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10846let Inst{13-11} = 0b111;
10847let Inst{31-21} = 0b10011011100;
10848let isPredicated = 1;
10849let isPredicatedFalse = 1;
10850let hasNewValue = 1;
10851let opNewValue = 0;
10852let addrMode = PostInc;
10853let accessSize = WordAccess;
10854let isPredicatedNew = 1;
10855let mayLoad = 1;
10856let BaseOpcode = "L2_loadri_pi";
10857let Constraints = "$Rx32 = $Rx32in";
10858}
10859def L2_ploadrifnew_zomap : HInst<
10860(outs IntRegs:$Rd32),
10861(ins PredRegs:$Pt4, IntRegs:$Rs32),
10862"if (!$Pt4.new) $Rd32 = memw($Rs32)",
10863tc_075c8dd8, TypeMAPPING> {
10864let hasNewValue = 1;
10865let opNewValue = 0;
10866let isPseudo = 1;
10867let isCodeGenOnly = 1;
10868}
10869def L2_ploadrit_io : HInst<
10870(outs IntRegs:$Rd32),
10871(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10872"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
10873tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10874let Inst{13-13} = 0b0;
10875let Inst{31-21} = 0b01000001100;
10876let isPredicated = 1;
10877let hasNewValue = 1;
10878let opNewValue = 0;
10879let addrMode = BaseImmOffset;
10880let accessSize = WordAccess;
10881let mayLoad = 1;
10882let BaseOpcode = "L2_loadri_io";
10883let CextOpcode = "L2_loadri";
10884let isExtendable = 1;
10885let opExtendable = 3;
10886let isExtentSigned = 0;
10887let opExtentBits = 8;
10888let opExtentAlign = 2;
10889}
10890def L2_ploadrit_pi : HInst<
10891(outs IntRegs:$Rd32, IntRegs:$Rx32),
10892(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10893"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
10894tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10895let Inst{13-11} = 0b100;
10896let Inst{31-21} = 0b10011011100;
10897let isPredicated = 1;
10898let hasNewValue = 1;
10899let opNewValue = 0;
10900let addrMode = PostInc;
10901let accessSize = WordAccess;
10902let mayLoad = 1;
10903let BaseOpcode = "L2_loadri_pi";
10904let Constraints = "$Rx32 = $Rx32in";
10905}
10906def L2_ploadrit_zomap : HInst<
10907(outs IntRegs:$Rd32),
10908(ins PredRegs:$Pt4, IntRegs:$Rs32),
10909"if ($Pt4) $Rd32 = memw($Rs32)",
10910tc_fedb7e19, TypeMAPPING> {
10911let hasNewValue = 1;
10912let opNewValue = 0;
10913let isPseudo = 1;
10914let isCodeGenOnly = 1;
10915}
10916def L2_ploadritnew_io : HInst<
10917(outs IntRegs:$Rd32),
10918(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10919"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10920tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10921let Inst{13-13} = 0b0;
10922let Inst{31-21} = 0b01000011100;
10923let isPredicated = 1;
10924let hasNewValue = 1;
10925let opNewValue = 0;
10926let addrMode = BaseImmOffset;
10927let accessSize = WordAccess;
10928let isPredicatedNew = 1;
10929let mayLoad = 1;
10930let BaseOpcode = "L2_loadri_io";
10931let CextOpcode = "L2_loadri";
10932let isExtendable = 1;
10933let opExtendable = 3;
10934let isExtentSigned = 0;
10935let opExtentBits = 8;
10936let opExtentAlign = 2;
10937}
10938def L2_ploadritnew_pi : HInst<
10939(outs IntRegs:$Rd32, IntRegs:$Rx32),
10940(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10941"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10942tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10943let Inst{13-11} = 0b110;
10944let Inst{31-21} = 0b10011011100;
10945let isPredicated = 1;
10946let hasNewValue = 1;
10947let opNewValue = 0;
10948let addrMode = PostInc;
10949let accessSize = WordAccess;
10950let isPredicatedNew = 1;
10951let mayLoad = 1;
10952let BaseOpcode = "L2_loadri_pi";
10953let Constraints = "$Rx32 = $Rx32in";
10954}
10955def L2_ploadritnew_zomap : HInst<
10956(outs IntRegs:$Rd32),
10957(ins PredRegs:$Pt4, IntRegs:$Rs32),
10958"if ($Pt4.new) $Rd32 = memw($Rs32)",
10959tc_075c8dd8, TypeMAPPING> {
10960let hasNewValue = 1;
10961let opNewValue = 0;
10962let isPseudo = 1;
10963let isCodeGenOnly = 1;
10964}
10965def L2_ploadrubf_io : HInst<
10966(outs IntRegs:$Rd32),
10967(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10968"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
10969tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10970let Inst{13-13} = 0b0;
10971let Inst{31-21} = 0b01000101001;
10972let isPredicated = 1;
10973let isPredicatedFalse = 1;
10974let hasNewValue = 1;
10975let opNewValue = 0;
10976let addrMode = BaseImmOffset;
10977let accessSize = ByteAccess;
10978let mayLoad = 1;
10979let BaseOpcode = "L2_loadrub_io";
10980let CextOpcode = "L2_loadrub";
10981let isExtendable = 1;
10982let opExtendable = 3;
10983let isExtentSigned = 0;
10984let opExtentBits = 6;
10985let opExtentAlign = 0;
10986}
10987def L2_ploadrubf_pi : HInst<
10988(outs IntRegs:$Rd32, IntRegs:$Rx32),
10989(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10990"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
10991tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10992let Inst{13-11} = 0b101;
10993let Inst{31-21} = 0b10011011001;
10994let isPredicated = 1;
10995let isPredicatedFalse = 1;
10996let hasNewValue = 1;
10997let opNewValue = 0;
10998let addrMode = PostInc;
10999let accessSize = ByteAccess;
11000let mayLoad = 1;
11001let BaseOpcode = "L2_loadrub_pi";
11002let Constraints = "$Rx32 = $Rx32in";
11003}
11004def L2_ploadrubf_zomap : HInst<
11005(outs IntRegs:$Rd32),
11006(ins PredRegs:$Pt4, IntRegs:$Rs32),
11007"if (!$Pt4) $Rd32 = memub($Rs32)",
11008tc_fedb7e19, TypeMAPPING> {
11009let hasNewValue = 1;
11010let opNewValue = 0;
11011let isPseudo = 1;
11012let isCodeGenOnly = 1;
11013}
11014def L2_ploadrubfnew_io : HInst<
11015(outs IntRegs:$Rd32),
11016(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11017"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
11018tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11019let Inst{13-13} = 0b0;
11020let Inst{31-21} = 0b01000111001;
11021let isPredicated = 1;
11022let isPredicatedFalse = 1;
11023let hasNewValue = 1;
11024let opNewValue = 0;
11025let addrMode = BaseImmOffset;
11026let accessSize = ByteAccess;
11027let isPredicatedNew = 1;
11028let mayLoad = 1;
11029let BaseOpcode = "L2_loadrub_io";
11030let CextOpcode = "L2_loadrub";
11031let isExtendable = 1;
11032let opExtendable = 3;
11033let isExtentSigned = 0;
11034let opExtentBits = 6;
11035let opExtentAlign = 0;
11036}
11037def L2_ploadrubfnew_pi : HInst<
11038(outs IntRegs:$Rd32, IntRegs:$Rx32),
11039(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11040"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
11041tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
11042let Inst{13-11} = 0b111;
11043let Inst{31-21} = 0b10011011001;
11044let isPredicated = 1;
11045let isPredicatedFalse = 1;
11046let hasNewValue = 1;
11047let opNewValue = 0;
11048let addrMode = PostInc;
11049let accessSize = ByteAccess;
11050let isPredicatedNew = 1;
11051let mayLoad = 1;
11052let BaseOpcode = "L2_loadrub_pi";
11053let Constraints = "$Rx32 = $Rx32in";
11054}
11055def L2_ploadrubfnew_zomap : HInst<
11056(outs IntRegs:$Rd32),
11057(ins PredRegs:$Pt4, IntRegs:$Rs32),
11058"if (!$Pt4.new) $Rd32 = memub($Rs32)",
11059tc_075c8dd8, TypeMAPPING> {
11060let hasNewValue = 1;
11061let opNewValue = 0;
11062let isPseudo = 1;
11063let isCodeGenOnly = 1;
11064}
11065def L2_ploadrubt_io : HInst<
11066(outs IntRegs:$Rd32),
11067(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11068"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
11069tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11070let Inst{13-13} = 0b0;
11071let Inst{31-21} = 0b01000001001;
11072let isPredicated = 1;
11073let hasNewValue = 1;
11074let opNewValue = 0;
11075let addrMode = BaseImmOffset;
11076let accessSize = ByteAccess;
11077let mayLoad = 1;
11078let BaseOpcode = "L2_loadrub_io";
11079let CextOpcode = "L2_loadrub";
11080let isExtendable = 1;
11081let opExtendable = 3;
11082let isExtentSigned = 0;
11083let opExtentBits = 6;
11084let opExtentAlign = 0;
11085}
11086def L2_ploadrubt_pi : HInst<
11087(outs IntRegs:$Rd32, IntRegs:$Rx32),
11088(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11089"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
11090tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
11091let Inst{13-11} = 0b100;
11092let Inst{31-21} = 0b10011011001;
11093let isPredicated = 1;
11094let hasNewValue = 1;
11095let opNewValue = 0;
11096let addrMode = PostInc;
11097let accessSize = ByteAccess;
11098let mayLoad = 1;
11099let BaseOpcode = "L2_loadrub_pi";
11100let Constraints = "$Rx32 = $Rx32in";
11101}
11102def L2_ploadrubt_zomap : HInst<
11103(outs IntRegs:$Rd32),
11104(ins PredRegs:$Pt4, IntRegs:$Rs32),
11105"if ($Pt4) $Rd32 = memub($Rs32)",
11106tc_fedb7e19, TypeMAPPING> {
11107let hasNewValue = 1;
11108let opNewValue = 0;
11109let isPseudo = 1;
11110let isCodeGenOnly = 1;
11111}
11112def L2_ploadrubtnew_io : HInst<
11113(outs IntRegs:$Rd32),
11114(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11115"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
11116tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11117let Inst{13-13} = 0b0;
11118let Inst{31-21} = 0b01000011001;
11119let isPredicated = 1;
11120let hasNewValue = 1;
11121let opNewValue = 0;
11122let addrMode = BaseImmOffset;
11123let accessSize = ByteAccess;
11124let isPredicatedNew = 1;
11125let mayLoad = 1;
11126let BaseOpcode = "L2_loadrub_io";
11127let CextOpcode = "L2_loadrub";
11128let isExtendable = 1;
11129let opExtendable = 3;
11130let isExtentSigned = 0;
11131let opExtentBits = 6;
11132let opExtentAlign = 0;
11133}
11134def L2_ploadrubtnew_pi : HInst<
11135(outs IntRegs:$Rd32, IntRegs:$Rx32),
11136(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11137"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
11138tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
11139let Inst{13-11} = 0b110;
11140let Inst{31-21} = 0b10011011001;
11141let isPredicated = 1;
11142let hasNewValue = 1;
11143let opNewValue = 0;
11144let addrMode = PostInc;
11145let accessSize = ByteAccess;
11146let isPredicatedNew = 1;
11147let mayLoad = 1;
11148let BaseOpcode = "L2_loadrub_pi";
11149let Constraints = "$Rx32 = $Rx32in";
11150}
11151def L2_ploadrubtnew_zomap : HInst<
11152(outs IntRegs:$Rd32),
11153(ins PredRegs:$Pt4, IntRegs:$Rs32),
11154"if ($Pt4.new) $Rd32 = memub($Rs32)",
11155tc_075c8dd8, TypeMAPPING> {
11156let hasNewValue = 1;
11157let opNewValue = 0;
11158let isPseudo = 1;
11159let isCodeGenOnly = 1;
11160}
11161def L2_ploadruhf_io : HInst<
11162(outs IntRegs:$Rd32),
11163(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11164"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11165tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11166let Inst{13-13} = 0b0;
11167let Inst{31-21} = 0b01000101011;
11168let isPredicated = 1;
11169let isPredicatedFalse = 1;
11170let hasNewValue = 1;
11171let opNewValue = 0;
11172let addrMode = BaseImmOffset;
11173let accessSize = HalfWordAccess;
11174let mayLoad = 1;
11175let BaseOpcode = "L2_loadruh_io";
11176let CextOpcode = "L2_loadruh";
11177let isExtendable = 1;
11178let opExtendable = 3;
11179let isExtentSigned = 0;
11180let opExtentBits = 7;
11181let opExtentAlign = 1;
11182}
11183def L2_ploadruhf_pi : HInst<
11184(outs IntRegs:$Rd32, IntRegs:$Rx32),
11185(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11186"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11187tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11188let Inst{13-11} = 0b101;
11189let Inst{31-21} = 0b10011011011;
11190let isPredicated = 1;
11191let isPredicatedFalse = 1;
11192let hasNewValue = 1;
11193let opNewValue = 0;
11194let addrMode = PostInc;
11195let accessSize = HalfWordAccess;
11196let mayLoad = 1;
11197let BaseOpcode = "L2_loadruh_pi";
11198let Constraints = "$Rx32 = $Rx32in";
11199}
11200def L2_ploadruhf_zomap : HInst<
11201(outs IntRegs:$Rd32),
11202(ins PredRegs:$Pt4, IntRegs:$Rs32),
11203"if (!$Pt4) $Rd32 = memuh($Rs32)",
11204tc_fedb7e19, TypeMAPPING> {
11205let hasNewValue = 1;
11206let opNewValue = 0;
11207let isPseudo = 1;
11208let isCodeGenOnly = 1;
11209}
11210def L2_ploadruhfnew_io : HInst<
11211(outs IntRegs:$Rd32),
11212(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11213"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11214tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11215let Inst{13-13} = 0b0;
11216let Inst{31-21} = 0b01000111011;
11217let isPredicated = 1;
11218let isPredicatedFalse = 1;
11219let hasNewValue = 1;
11220let opNewValue = 0;
11221let addrMode = BaseImmOffset;
11222let accessSize = HalfWordAccess;
11223let isPredicatedNew = 1;
11224let mayLoad = 1;
11225let BaseOpcode = "L2_loadruh_io";
11226let CextOpcode = "L2_loadruh";
11227let isExtendable = 1;
11228let opExtendable = 3;
11229let isExtentSigned = 0;
11230let opExtentBits = 7;
11231let opExtentAlign = 1;
11232}
11233def L2_ploadruhfnew_pi : HInst<
11234(outs IntRegs:$Rd32, IntRegs:$Rx32),
11235(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11236"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11237tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11238let Inst{13-11} = 0b111;
11239let Inst{31-21} = 0b10011011011;
11240let isPredicated = 1;
11241let isPredicatedFalse = 1;
11242let hasNewValue = 1;
11243let opNewValue = 0;
11244let addrMode = PostInc;
11245let accessSize = HalfWordAccess;
11246let isPredicatedNew = 1;
11247let mayLoad = 1;
11248let BaseOpcode = "L2_loadruh_pi";
11249let Constraints = "$Rx32 = $Rx32in";
11250}
11251def L2_ploadruhfnew_zomap : HInst<
11252(outs IntRegs:$Rd32),
11253(ins PredRegs:$Pt4, IntRegs:$Rs32),
11254"if (!$Pt4.new) $Rd32 = memuh($Rs32)",
11255tc_075c8dd8, TypeMAPPING> {
11256let hasNewValue = 1;
11257let opNewValue = 0;
11258let isPseudo = 1;
11259let isCodeGenOnly = 1;
11260}
11261def L2_ploadruht_io : HInst<
11262(outs IntRegs:$Rd32),
11263(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11264"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11265tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11266let Inst{13-13} = 0b0;
11267let Inst{31-21} = 0b01000001011;
11268let isPredicated = 1;
11269let hasNewValue = 1;
11270let opNewValue = 0;
11271let addrMode = BaseImmOffset;
11272let accessSize = HalfWordAccess;
11273let mayLoad = 1;
11274let BaseOpcode = "L2_loadruh_io";
11275let CextOpcode = "L2_loadruh";
11276let isExtendable = 1;
11277let opExtendable = 3;
11278let isExtentSigned = 0;
11279let opExtentBits = 7;
11280let opExtentAlign = 1;
11281}
11282def L2_ploadruht_pi : HInst<
11283(outs IntRegs:$Rd32, IntRegs:$Rx32),
11284(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11285"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11286tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11287let Inst{13-11} = 0b100;
11288let Inst{31-21} = 0b10011011011;
11289let isPredicated = 1;
11290let hasNewValue = 1;
11291let opNewValue = 0;
11292let addrMode = PostInc;
11293let accessSize = HalfWordAccess;
11294let mayLoad = 1;
11295let BaseOpcode = "L2_loadruh_pi";
11296let Constraints = "$Rx32 = $Rx32in";
11297}
11298def L2_ploadruht_zomap : HInst<
11299(outs IntRegs:$Rd32),
11300(ins PredRegs:$Pt4, IntRegs:$Rs32),
11301"if ($Pt4) $Rd32 = memuh($Rs32)",
11302tc_fedb7e19, TypeMAPPING> {
11303let hasNewValue = 1;
11304let opNewValue = 0;
11305let isPseudo = 1;
11306let isCodeGenOnly = 1;
11307}
11308def L2_ploadruhtnew_io : HInst<
11309(outs IntRegs:$Rd32),
11310(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11311"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11312tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11313let Inst{13-13} = 0b0;
11314let Inst{31-21} = 0b01000011011;
11315let isPredicated = 1;
11316let hasNewValue = 1;
11317let opNewValue = 0;
11318let addrMode = BaseImmOffset;
11319let accessSize = HalfWordAccess;
11320let isPredicatedNew = 1;
11321let mayLoad = 1;
11322let BaseOpcode = "L2_loadruh_io";
11323let CextOpcode = "L2_loadruh";
11324let isExtendable = 1;
11325let opExtendable = 3;
11326let isExtentSigned = 0;
11327let opExtentBits = 7;
11328let opExtentAlign = 1;
11329}
11330def L2_ploadruhtnew_pi : HInst<
11331(outs IntRegs:$Rd32, IntRegs:$Rx32),
11332(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11333"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11334tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11335let Inst{13-11} = 0b110;
11336let Inst{31-21} = 0b10011011011;
11337let isPredicated = 1;
11338let hasNewValue = 1;
11339let opNewValue = 0;
11340let addrMode = PostInc;
11341let accessSize = HalfWordAccess;
11342let isPredicatedNew = 1;
11343let mayLoad = 1;
11344let BaseOpcode = "L2_loadruh_pi";
11345let Constraints = "$Rx32 = $Rx32in";
11346}
11347def L2_ploadruhtnew_zomap : HInst<
11348(outs IntRegs:$Rd32),
11349(ins PredRegs:$Pt4, IntRegs:$Rs32),
11350"if ($Pt4.new) $Rd32 = memuh($Rs32)",
11351tc_075c8dd8, TypeMAPPING> {
11352let hasNewValue = 1;
11353let opNewValue = 0;
11354let isPseudo = 1;
11355let isCodeGenOnly = 1;
11356}
11357def L4_add_memopb_io : HInst<
11358(outs),
11359(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11360"memb($Rs32+#$Ii) += $Rt32",
11361tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11362let Inst{6-5} = 0b00;
11363let Inst{13-13} = 0b0;
11364let Inst{31-21} = 0b00111110000;
11365let addrMode = BaseImmOffset;
11366let accessSize = ByteAccess;
11367let mayLoad = 1;
11368let isRestrictNoSlot1Store = 1;
11369let mayStore = 1;
11370let isExtendable = 1;
11371let opExtendable = 1;
11372let isExtentSigned = 0;
11373let opExtentBits = 6;
11374let opExtentAlign = 0;
11375}
11376def L4_add_memopb_zomap : HInst<
11377(outs),
11378(ins IntRegs:$Rs32, IntRegs:$Rt32),
11379"memb($Rs32) += $Rt32",
11380tc_9bcfb2ee, TypeMAPPING> {
11381let isPseudo = 1;
11382let isCodeGenOnly = 1;
11383}
11384def L4_add_memoph_io : HInst<
11385(outs),
11386(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11387"memh($Rs32+#$Ii) += $Rt32",
11388tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11389let Inst{6-5} = 0b00;
11390let Inst{13-13} = 0b0;
11391let Inst{31-21} = 0b00111110001;
11392let addrMode = BaseImmOffset;
11393let accessSize = HalfWordAccess;
11394let mayLoad = 1;
11395let isRestrictNoSlot1Store = 1;
11396let mayStore = 1;
11397let isExtendable = 1;
11398let opExtendable = 1;
11399let isExtentSigned = 0;
11400let opExtentBits = 7;
11401let opExtentAlign = 1;
11402}
11403def L4_add_memoph_zomap : HInst<
11404(outs),
11405(ins IntRegs:$Rs32, IntRegs:$Rt32),
11406"memh($Rs32) += $Rt32",
11407tc_9bcfb2ee, TypeMAPPING> {
11408let isPseudo = 1;
11409let isCodeGenOnly = 1;
11410}
11411def L4_add_memopw_io : HInst<
11412(outs),
11413(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11414"memw($Rs32+#$Ii) += $Rt32",
11415tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11416let Inst{6-5} = 0b00;
11417let Inst{13-13} = 0b0;
11418let Inst{31-21} = 0b00111110010;
11419let addrMode = BaseImmOffset;
11420let accessSize = WordAccess;
11421let mayLoad = 1;
11422let isRestrictNoSlot1Store = 1;
11423let mayStore = 1;
11424let isExtendable = 1;
11425let opExtendable = 1;
11426let isExtentSigned = 0;
11427let opExtentBits = 8;
11428let opExtentAlign = 2;
11429}
11430def L4_add_memopw_zomap : HInst<
11431(outs),
11432(ins IntRegs:$Rs32, IntRegs:$Rt32),
11433"memw($Rs32) += $Rt32",
11434tc_9bcfb2ee, TypeMAPPING> {
11435let isPseudo = 1;
11436let isCodeGenOnly = 1;
11437}
11438def L4_and_memopb_io : HInst<
11439(outs),
11440(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11441"memb($Rs32+#$Ii) &= $Rt32",
11442tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11443let Inst{6-5} = 0b10;
11444let Inst{13-13} = 0b0;
11445let Inst{31-21} = 0b00111110000;
11446let addrMode = BaseImmOffset;
11447let accessSize = ByteAccess;
11448let mayLoad = 1;
11449let isRestrictNoSlot1Store = 1;
11450let mayStore = 1;
11451let isExtendable = 1;
11452let opExtendable = 1;
11453let isExtentSigned = 0;
11454let opExtentBits = 6;
11455let opExtentAlign = 0;
11456}
11457def L4_and_memopb_zomap : HInst<
11458(outs),
11459(ins IntRegs:$Rs32, IntRegs:$Rt32),
11460"memb($Rs32) &= $Rt32",
11461tc_9bcfb2ee, TypeMAPPING> {
11462let isPseudo = 1;
11463let isCodeGenOnly = 1;
11464}
11465def L4_and_memoph_io : HInst<
11466(outs),
11467(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11468"memh($Rs32+#$Ii) &= $Rt32",
11469tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11470let Inst{6-5} = 0b10;
11471let Inst{13-13} = 0b0;
11472let Inst{31-21} = 0b00111110001;
11473let addrMode = BaseImmOffset;
11474let accessSize = HalfWordAccess;
11475let mayLoad = 1;
11476let isRestrictNoSlot1Store = 1;
11477let mayStore = 1;
11478let isExtendable = 1;
11479let opExtendable = 1;
11480let isExtentSigned = 0;
11481let opExtentBits = 7;
11482let opExtentAlign = 1;
11483}
11484def L4_and_memoph_zomap : HInst<
11485(outs),
11486(ins IntRegs:$Rs32, IntRegs:$Rt32),
11487"memh($Rs32) &= $Rt32",
11488tc_9bcfb2ee, TypeMAPPING> {
11489let isPseudo = 1;
11490let isCodeGenOnly = 1;
11491}
11492def L4_and_memopw_io : HInst<
11493(outs),
11494(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11495"memw($Rs32+#$Ii) &= $Rt32",
11496tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11497let Inst{6-5} = 0b10;
11498let Inst{13-13} = 0b0;
11499let Inst{31-21} = 0b00111110010;
11500let addrMode = BaseImmOffset;
11501let accessSize = WordAccess;
11502let mayLoad = 1;
11503let isRestrictNoSlot1Store = 1;
11504let mayStore = 1;
11505let isExtendable = 1;
11506let opExtendable = 1;
11507let isExtentSigned = 0;
11508let opExtentBits = 8;
11509let opExtentAlign = 2;
11510}
11511def L4_and_memopw_zomap : HInst<
11512(outs),
11513(ins IntRegs:$Rs32, IntRegs:$Rt32),
11514"memw($Rs32) &= $Rt32",
11515tc_9bcfb2ee, TypeMAPPING> {
11516let isPseudo = 1;
11517let isCodeGenOnly = 1;
11518}
11519def L4_iadd_memopb_io : HInst<
11520(outs),
11521(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11522"memb($Rs32+#$Ii) += #$II",
11523tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11524let Inst{6-5} = 0b00;
11525let Inst{13-13} = 0b0;
11526let Inst{31-21} = 0b00111111000;
11527let addrMode = BaseImmOffset;
11528let accessSize = ByteAccess;
11529let mayLoad = 1;
11530let isRestrictNoSlot1Store = 1;
11531let mayStore = 1;
11532let isExtendable = 1;
11533let opExtendable = 1;
11534let isExtentSigned = 0;
11535let opExtentBits = 6;
11536let opExtentAlign = 0;
11537}
11538def L4_iadd_memopb_zomap : HInst<
11539(outs),
11540(ins IntRegs:$Rs32, u5_0Imm:$II),
11541"memb($Rs32) += #$II",
11542tc_158aa3f7, TypeMAPPING> {
11543let isPseudo = 1;
11544let isCodeGenOnly = 1;
11545}
11546def L4_iadd_memoph_io : HInst<
11547(outs),
11548(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11549"memh($Rs32+#$Ii) += #$II",
11550tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11551let Inst{6-5} = 0b00;
11552let Inst{13-13} = 0b0;
11553let Inst{31-21} = 0b00111111001;
11554let addrMode = BaseImmOffset;
11555let accessSize = HalfWordAccess;
11556let mayLoad = 1;
11557let isRestrictNoSlot1Store = 1;
11558let mayStore = 1;
11559let isExtendable = 1;
11560let opExtendable = 1;
11561let isExtentSigned = 0;
11562let opExtentBits = 7;
11563let opExtentAlign = 1;
11564}
11565def L4_iadd_memoph_zomap : HInst<
11566(outs),
11567(ins IntRegs:$Rs32, u5_0Imm:$II),
11568"memh($Rs32) += #$II",
11569tc_158aa3f7, TypeMAPPING> {
11570let isPseudo = 1;
11571let isCodeGenOnly = 1;
11572}
11573def L4_iadd_memopw_io : HInst<
11574(outs),
11575(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11576"memw($Rs32+#$Ii) += #$II",
11577tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11578let Inst{6-5} = 0b00;
11579let Inst{13-13} = 0b0;
11580let Inst{31-21} = 0b00111111010;
11581let addrMode = BaseImmOffset;
11582let accessSize = WordAccess;
11583let mayLoad = 1;
11584let isRestrictNoSlot1Store = 1;
11585let mayStore = 1;
11586let isExtendable = 1;
11587let opExtendable = 1;
11588let isExtentSigned = 0;
11589let opExtentBits = 8;
11590let opExtentAlign = 2;
11591}
11592def L4_iadd_memopw_zomap : HInst<
11593(outs),
11594(ins IntRegs:$Rs32, u5_0Imm:$II),
11595"memw($Rs32) += #$II",
11596tc_158aa3f7, TypeMAPPING> {
11597let isPseudo = 1;
11598let isCodeGenOnly = 1;
11599}
11600def L4_iand_memopb_io : HInst<
11601(outs),
11602(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11603"memb($Rs32+#$Ii) = clrbit(#$II)",
11604tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11605let Inst{6-5} = 0b10;
11606let Inst{13-13} = 0b0;
11607let Inst{31-21} = 0b00111111000;
11608let addrMode = BaseImmOffset;
11609let accessSize = ByteAccess;
11610let mayLoad = 1;
11611let isRestrictNoSlot1Store = 1;
11612let mayStore = 1;
11613let isExtendable = 1;
11614let opExtendable = 1;
11615let isExtentSigned = 0;
11616let opExtentBits = 6;
11617let opExtentAlign = 0;
11618}
11619def L4_iand_memopb_zomap : HInst<
11620(outs),
11621(ins IntRegs:$Rs32, u5_0Imm:$II),
11622"memb($Rs32) = clrbit(#$II)",
11623tc_158aa3f7, TypeMAPPING> {
11624let isPseudo = 1;
11625let isCodeGenOnly = 1;
11626}
11627def L4_iand_memoph_io : HInst<
11628(outs),
11629(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11630"memh($Rs32+#$Ii) = clrbit(#$II)",
11631tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11632let Inst{6-5} = 0b10;
11633let Inst{13-13} = 0b0;
11634let Inst{31-21} = 0b00111111001;
11635let addrMode = BaseImmOffset;
11636let accessSize = HalfWordAccess;
11637let mayLoad = 1;
11638let isRestrictNoSlot1Store = 1;
11639let mayStore = 1;
11640let isExtendable = 1;
11641let opExtendable = 1;
11642let isExtentSigned = 0;
11643let opExtentBits = 7;
11644let opExtentAlign = 1;
11645}
11646def L4_iand_memoph_zomap : HInst<
11647(outs),
11648(ins IntRegs:$Rs32, u5_0Imm:$II),
11649"memh($Rs32) = clrbit(#$II)",
11650tc_158aa3f7, TypeMAPPING> {
11651let isPseudo = 1;
11652let isCodeGenOnly = 1;
11653}
11654def L4_iand_memopw_io : HInst<
11655(outs),
11656(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11657"memw($Rs32+#$Ii) = clrbit(#$II)",
11658tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11659let Inst{6-5} = 0b10;
11660let Inst{13-13} = 0b0;
11661let Inst{31-21} = 0b00111111010;
11662let addrMode = BaseImmOffset;
11663let accessSize = WordAccess;
11664let mayLoad = 1;
11665let isRestrictNoSlot1Store = 1;
11666let mayStore = 1;
11667let isExtendable = 1;
11668let opExtendable = 1;
11669let isExtentSigned = 0;
11670let opExtentBits = 8;
11671let opExtentAlign = 2;
11672}
11673def L4_iand_memopw_zomap : HInst<
11674(outs),
11675(ins IntRegs:$Rs32, u5_0Imm:$II),
11676"memw($Rs32) = clrbit(#$II)",
11677tc_158aa3f7, TypeMAPPING> {
11678let isPseudo = 1;
11679let isCodeGenOnly = 1;
11680}
11681def L4_ior_memopb_io : HInst<
11682(outs),
11683(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11684"memb($Rs32+#$Ii) = setbit(#$II)",
11685tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11686let Inst{6-5} = 0b11;
11687let Inst{13-13} = 0b0;
11688let Inst{31-21} = 0b00111111000;
11689let addrMode = BaseImmOffset;
11690let accessSize = ByteAccess;
11691let mayLoad = 1;
11692let isRestrictNoSlot1Store = 1;
11693let mayStore = 1;
11694let isExtendable = 1;
11695let opExtendable = 1;
11696let isExtentSigned = 0;
11697let opExtentBits = 6;
11698let opExtentAlign = 0;
11699}
11700def L4_ior_memopb_zomap : HInst<
11701(outs),
11702(ins IntRegs:$Rs32, u5_0Imm:$II),
11703"memb($Rs32) = setbit(#$II)",
11704tc_158aa3f7, TypeMAPPING> {
11705let isPseudo = 1;
11706let isCodeGenOnly = 1;
11707}
11708def L4_ior_memoph_io : HInst<
11709(outs),
11710(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11711"memh($Rs32+#$Ii) = setbit(#$II)",
11712tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11713let Inst{6-5} = 0b11;
11714let Inst{13-13} = 0b0;
11715let Inst{31-21} = 0b00111111001;
11716let addrMode = BaseImmOffset;
11717let accessSize = HalfWordAccess;
11718let mayLoad = 1;
11719let isRestrictNoSlot1Store = 1;
11720let mayStore = 1;
11721let isExtendable = 1;
11722let opExtendable = 1;
11723let isExtentSigned = 0;
11724let opExtentBits = 7;
11725let opExtentAlign = 1;
11726}
11727def L4_ior_memoph_zomap : HInst<
11728(outs),
11729(ins IntRegs:$Rs32, u5_0Imm:$II),
11730"memh($Rs32) = setbit(#$II)",
11731tc_158aa3f7, TypeMAPPING> {
11732let isPseudo = 1;
11733let isCodeGenOnly = 1;
11734}
11735def L4_ior_memopw_io : HInst<
11736(outs),
11737(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11738"memw($Rs32+#$Ii) = setbit(#$II)",
11739tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11740let Inst{6-5} = 0b11;
11741let Inst{13-13} = 0b0;
11742let Inst{31-21} = 0b00111111010;
11743let addrMode = BaseImmOffset;
11744let accessSize = WordAccess;
11745let mayLoad = 1;
11746let isRestrictNoSlot1Store = 1;
11747let mayStore = 1;
11748let isExtendable = 1;
11749let opExtendable = 1;
11750let isExtentSigned = 0;
11751let opExtentBits = 8;
11752let opExtentAlign = 2;
11753}
11754def L4_ior_memopw_zomap : HInst<
11755(outs),
11756(ins IntRegs:$Rs32, u5_0Imm:$II),
11757"memw($Rs32) = setbit(#$II)",
11758tc_158aa3f7, TypeMAPPING> {
11759let isPseudo = 1;
11760let isCodeGenOnly = 1;
11761}
11762def L4_isub_memopb_io : HInst<
11763(outs),
11764(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11765"memb($Rs32+#$Ii) -= #$II",
11766tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11767let Inst{6-5} = 0b01;
11768let Inst{13-13} = 0b0;
11769let Inst{31-21} = 0b00111111000;
11770let addrMode = BaseImmOffset;
11771let accessSize = ByteAccess;
11772let mayLoad = 1;
11773let isRestrictNoSlot1Store = 1;
11774let mayStore = 1;
11775let isExtendable = 1;
11776let opExtendable = 1;
11777let isExtentSigned = 0;
11778let opExtentBits = 6;
11779let opExtentAlign = 0;
11780}
11781def L4_isub_memopb_zomap : HInst<
11782(outs),
11783(ins IntRegs:$Rs32, u5_0Imm:$II),
11784"memb($Rs32) -= #$II",
11785tc_158aa3f7, TypeMAPPING> {
11786let isPseudo = 1;
11787let isCodeGenOnly = 1;
11788}
11789def L4_isub_memoph_io : HInst<
11790(outs),
11791(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11792"memh($Rs32+#$Ii) -= #$II",
11793tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11794let Inst{6-5} = 0b01;
11795let Inst{13-13} = 0b0;
11796let Inst{31-21} = 0b00111111001;
11797let addrMode = BaseImmOffset;
11798let accessSize = HalfWordAccess;
11799let mayLoad = 1;
11800let isRestrictNoSlot1Store = 1;
11801let mayStore = 1;
11802let isExtendable = 1;
11803let opExtendable = 1;
11804let isExtentSigned = 0;
11805let opExtentBits = 7;
11806let opExtentAlign = 1;
11807}
11808def L4_isub_memoph_zomap : HInst<
11809(outs),
11810(ins IntRegs:$Rs32, u5_0Imm:$II),
11811"memh($Rs32) -= #$II",
11812tc_158aa3f7, TypeMAPPING> {
11813let isPseudo = 1;
11814let isCodeGenOnly = 1;
11815}
11816def L4_isub_memopw_io : HInst<
11817(outs),
11818(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11819"memw($Rs32+#$Ii) -= #$II",
11820tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11821let Inst{6-5} = 0b01;
11822let Inst{13-13} = 0b0;
11823let Inst{31-21} = 0b00111111010;
11824let addrMode = BaseImmOffset;
11825let accessSize = WordAccess;
11826let mayLoad = 1;
11827let isRestrictNoSlot1Store = 1;
11828let mayStore = 1;
11829let isExtendable = 1;
11830let opExtendable = 1;
11831let isExtentSigned = 0;
11832let opExtentBits = 8;
11833let opExtentAlign = 2;
11834}
11835def L4_isub_memopw_zomap : HInst<
11836(outs),
11837(ins IntRegs:$Rs32, u5_0Imm:$II),
11838"memw($Rs32) -= #$II",
11839tc_158aa3f7, TypeMAPPING> {
11840let isPseudo = 1;
11841let isCodeGenOnly = 1;
11842}
11843def L4_loadalignb_ap : HInst<
11844(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11845(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11846"$Ryy32 = memb_fifo($Re32=#$II)",
11847tc_ac65613f, TypeLD>, Enc_f394d3 {
11848let Inst{7-7} = 0b0;
11849let Inst{13-12} = 0b01;
11850let Inst{31-21} = 0b10011010100;
11851let addrMode = AbsoluteSet;
11852let accessSize = ByteAccess;
11853let mayLoad = 1;
11854let isExtended = 1;
11855let DecoderNamespace = "MustExtend";
11856let isExtendable = 1;
11857let opExtendable = 3;
11858let isExtentSigned = 0;
11859let opExtentBits = 6;
11860let opExtentAlign = 0;
11861let Constraints = "$Ryy32 = $Ryy32in";
11862}
11863def L4_loadalignb_ur : HInst<
11864(outs DoubleRegs:$Ryy32),
11865(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11866"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
11867tc_a32e03e7, TypeLD>, Enc_04c959 {
11868let Inst{12-12} = 0b1;
11869let Inst{31-21} = 0b10011100100;
11870let addrMode = BaseLongOffset;
11871let accessSize = ByteAccess;
11872let mayLoad = 1;
11873let isExtended = 1;
11874let InputType = "imm";
11875let DecoderNamespace = "MustExtend";
11876let isExtendable = 1;
11877let opExtendable = 4;
11878let isExtentSigned = 0;
11879let opExtentBits = 6;
11880let opExtentAlign = 0;
11881let Constraints = "$Ryy32 = $Ryy32in";
11882}
11883def L4_loadalignh_ap : HInst<
11884(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11885(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11886"$Ryy32 = memh_fifo($Re32=#$II)",
11887tc_ac65613f, TypeLD>, Enc_f394d3 {
11888let Inst{7-7} = 0b0;
11889let Inst{13-12} = 0b01;
11890let Inst{31-21} = 0b10011010010;
11891let addrMode = AbsoluteSet;
11892let accessSize = HalfWordAccess;
11893let mayLoad = 1;
11894let isExtended = 1;
11895let DecoderNamespace = "MustExtend";
11896let isExtendable = 1;
11897let opExtendable = 3;
11898let isExtentSigned = 0;
11899let opExtentBits = 6;
11900let opExtentAlign = 0;
11901let Constraints = "$Ryy32 = $Ryy32in";
11902}
11903def L4_loadalignh_ur : HInst<
11904(outs DoubleRegs:$Ryy32),
11905(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11906"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
11907tc_a32e03e7, TypeLD>, Enc_04c959 {
11908let Inst{12-12} = 0b1;
11909let Inst{31-21} = 0b10011100010;
11910let addrMode = BaseLongOffset;
11911let accessSize = HalfWordAccess;
11912let mayLoad = 1;
11913let isExtended = 1;
11914let InputType = "imm";
11915let DecoderNamespace = "MustExtend";
11916let isExtendable = 1;
11917let opExtendable = 4;
11918let isExtentSigned = 0;
11919let opExtentBits = 6;
11920let opExtentAlign = 0;
11921let Constraints = "$Ryy32 = $Ryy32in";
11922}
11923def L4_loadbsw2_ap : HInst<
11924(outs IntRegs:$Rd32, IntRegs:$Re32),
11925(ins u32_0Imm:$II),
11926"$Rd32 = membh($Re32=#$II)",
11927tc_822c3c68, TypeLD>, Enc_323f2d {
11928let Inst{7-7} = 0b0;
11929let Inst{13-12} = 0b01;
11930let Inst{31-21} = 0b10011010001;
11931let hasNewValue = 1;
11932let opNewValue = 0;
11933let addrMode = AbsoluteSet;
11934let accessSize = HalfWordAccess;
11935let mayLoad = 1;
11936let isExtended = 1;
11937let DecoderNamespace = "MustExtend";
11938let isExtendable = 1;
11939let opExtendable = 2;
11940let isExtentSigned = 0;
11941let opExtentBits = 6;
11942let opExtentAlign = 0;
11943}
11944def L4_loadbsw2_ur : HInst<
11945(outs IntRegs:$Rd32),
11946(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11947"$Rd32 = membh($Rt32<<#$Ii+#$II)",
11948tc_abfd9a6d, TypeLD>, Enc_4f677b {
11949let Inst{12-12} = 0b1;
11950let Inst{31-21} = 0b10011100001;
11951let hasNewValue = 1;
11952let opNewValue = 0;
11953let addrMode = BaseLongOffset;
11954let accessSize = HalfWordAccess;
11955let mayLoad = 1;
11956let isExtended = 1;
11957let InputType = "imm";
11958let DecoderNamespace = "MustExtend";
11959let isExtendable = 1;
11960let opExtendable = 3;
11961let isExtentSigned = 0;
11962let opExtentBits = 6;
11963let opExtentAlign = 0;
11964}
11965def L4_loadbsw4_ap : HInst<
11966(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11967(ins u32_0Imm:$II),
11968"$Rdd32 = membh($Re32=#$II)",
11969tc_822c3c68, TypeLD>, Enc_7fa7f6 {
11970let Inst{7-7} = 0b0;
11971let Inst{13-12} = 0b01;
11972let Inst{31-21} = 0b10011010111;
11973let addrMode = AbsoluteSet;
11974let accessSize = WordAccess;
11975let mayLoad = 1;
11976let isExtended = 1;
11977let DecoderNamespace = "MustExtend";
11978let isExtendable = 1;
11979let opExtendable = 2;
11980let isExtentSigned = 0;
11981let opExtentBits = 6;
11982let opExtentAlign = 0;
11983}
11984def L4_loadbsw4_ur : HInst<
11985(outs DoubleRegs:$Rdd32),
11986(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11987"$Rdd32 = membh($Rt32<<#$Ii+#$II)",
11988tc_abfd9a6d, TypeLD>, Enc_6185fe {
11989let Inst{12-12} = 0b1;
11990let Inst{31-21} = 0b10011100111;
11991let addrMode = BaseLongOffset;
11992let accessSize = WordAccess;
11993let mayLoad = 1;
11994let isExtended = 1;
11995let InputType = "imm";
11996let DecoderNamespace = "MustExtend";
11997let isExtendable = 1;
11998let opExtendable = 3;
11999let isExtentSigned = 0;
12000let opExtentBits = 6;
12001let opExtentAlign = 0;
12002}
12003def L4_loadbzw2_ap : HInst<
12004(outs IntRegs:$Rd32, IntRegs:$Re32),
12005(ins u32_0Imm:$II),
12006"$Rd32 = memubh($Re32=#$II)",
12007tc_822c3c68, TypeLD>, Enc_323f2d {
12008let Inst{7-7} = 0b0;
12009let Inst{13-12} = 0b01;
12010let Inst{31-21} = 0b10011010011;
12011let hasNewValue = 1;
12012let opNewValue = 0;
12013let addrMode = AbsoluteSet;
12014let accessSize = HalfWordAccess;
12015let mayLoad = 1;
12016let isExtended = 1;
12017let DecoderNamespace = "MustExtend";
12018let isExtendable = 1;
12019let opExtendable = 2;
12020let isExtentSigned = 0;
12021let opExtentBits = 6;
12022let opExtentAlign = 0;
12023}
12024def L4_loadbzw2_ur : HInst<
12025(outs IntRegs:$Rd32),
12026(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12027"$Rd32 = memubh($Rt32<<#$Ii+#$II)",
12028tc_abfd9a6d, TypeLD>, Enc_4f677b {
12029let Inst{12-12} = 0b1;
12030let Inst{31-21} = 0b10011100011;
12031let hasNewValue = 1;
12032let opNewValue = 0;
12033let addrMode = BaseLongOffset;
12034let accessSize = HalfWordAccess;
12035let mayLoad = 1;
12036let isExtended = 1;
12037let InputType = "imm";
12038let DecoderNamespace = "MustExtend";
12039let isExtendable = 1;
12040let opExtendable = 3;
12041let isExtentSigned = 0;
12042let opExtentBits = 6;
12043let opExtentAlign = 0;
12044}
12045def L4_loadbzw4_ap : HInst<
12046(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12047(ins u32_0Imm:$II),
12048"$Rdd32 = memubh($Re32=#$II)",
12049tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12050let Inst{7-7} = 0b0;
12051let Inst{13-12} = 0b01;
12052let Inst{31-21} = 0b10011010101;
12053let addrMode = AbsoluteSet;
12054let accessSize = WordAccess;
12055let mayLoad = 1;
12056let isExtended = 1;
12057let DecoderNamespace = "MustExtend";
12058let isExtendable = 1;
12059let opExtendable = 2;
12060let isExtentSigned = 0;
12061let opExtentBits = 6;
12062let opExtentAlign = 0;
12063}
12064def L4_loadbzw4_ur : HInst<
12065(outs DoubleRegs:$Rdd32),
12066(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12067"$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
12068tc_abfd9a6d, TypeLD>, Enc_6185fe {
12069let Inst{12-12} = 0b1;
12070let Inst{31-21} = 0b10011100101;
12071let addrMode = BaseLongOffset;
12072let accessSize = WordAccess;
12073let mayLoad = 1;
12074let isExtended = 1;
12075let InputType = "imm";
12076let DecoderNamespace = "MustExtend";
12077let isExtendable = 1;
12078let opExtendable = 3;
12079let isExtentSigned = 0;
12080let opExtentBits = 6;
12081let opExtentAlign = 0;
12082}
12083def L4_loadd_aq : HInst<
12084(outs DoubleRegs:$Rdd32),
12085(ins IntRegs:$Rs32),
12086"$Rdd32 = memd_aq($Rs32)",
12087tc_2471c1c8, TypeLD>, Enc_3a3d62, Requires<[HasV68]> {
12088let Inst{13-5} = 0b011000000;
12089let Inst{31-21} = 0b10010010000;
12090let accessSize = DoubleWordAccess;
12091let mayLoad = 1;
12092}
12093def L4_loadd_locked : HInst<
12094(outs DoubleRegs:$Rdd32),
12095(ins IntRegs:$Rs32),
12096"$Rdd32 = memd_locked($Rs32)",
12097tc_64b00d8a, TypeLD>, Enc_3a3d62 {
12098let Inst{13-5} = 0b010000000;
12099let Inst{31-21} = 0b10010010000;
12100let accessSize = DoubleWordAccess;
12101let mayLoad = 1;
12102let isSoloAX = 1;
12103}
12104def L4_loadrb_ap : HInst<
12105(outs IntRegs:$Rd32, IntRegs:$Re32),
12106(ins u32_0Imm:$II),
12107"$Rd32 = memb($Re32=#$II)",
12108tc_822c3c68, TypeLD>, Enc_323f2d {
12109let Inst{7-7} = 0b0;
12110let Inst{13-12} = 0b01;
12111let Inst{31-21} = 0b10011011000;
12112let hasNewValue = 1;
12113let opNewValue = 0;
12114let addrMode = AbsoluteSet;
12115let accessSize = ByteAccess;
12116let mayLoad = 1;
12117let isExtended = 1;
12118let DecoderNamespace = "MustExtend";
12119let isExtendable = 1;
12120let opExtendable = 2;
12121let isExtentSigned = 0;
12122let opExtentBits = 6;
12123let opExtentAlign = 0;
12124}
12125def L4_loadrb_rr : HInst<
12126(outs IntRegs:$Rd32),
12127(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12128"$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12129tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12130let Inst{6-5} = 0b00;
12131let Inst{31-21} = 0b00111010000;
12132let hasNewValue = 1;
12133let opNewValue = 0;
12134let addrMode = BaseRegOffset;
12135let accessSize = ByteAccess;
12136let mayLoad = 1;
12137let BaseOpcode = "L4_loadrb_rr";
12138let CextOpcode = "L2_loadrb";
12139let InputType = "reg";
12140let isPredicable = 1;
12141}
12142def L4_loadrb_ur : HInst<
12143(outs IntRegs:$Rd32),
12144(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12145"$Rd32 = memb($Rt32<<#$Ii+#$II)",
12146tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12147let Inst{12-12} = 0b1;
12148let Inst{31-21} = 0b10011101000;
12149let hasNewValue = 1;
12150let opNewValue = 0;
12151let addrMode = BaseLongOffset;
12152let accessSize = ByteAccess;
12153let mayLoad = 1;
12154let isExtended = 1;
12155let CextOpcode = "L2_loadrb";
12156let InputType = "imm";
12157let DecoderNamespace = "MustExtend";
12158let isExtendable = 1;
12159let opExtendable = 3;
12160let isExtentSigned = 0;
12161let opExtentBits = 6;
12162let opExtentAlign = 0;
12163}
12164def L4_loadrd_ap : HInst<
12165(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12166(ins u32_0Imm:$II),
12167"$Rdd32 = memd($Re32=#$II)",
12168tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12169let Inst{7-7} = 0b0;
12170let Inst{13-12} = 0b01;
12171let Inst{31-21} = 0b10011011110;
12172let addrMode = AbsoluteSet;
12173let accessSize = DoubleWordAccess;
12174let mayLoad = 1;
12175let isExtended = 1;
12176let DecoderNamespace = "MustExtend";
12177let isExtendable = 1;
12178let opExtendable = 2;
12179let isExtentSigned = 0;
12180let opExtentBits = 6;
12181let opExtentAlign = 0;
12182}
12183def L4_loadrd_rr : HInst<
12184(outs DoubleRegs:$Rdd32),
12185(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12186"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12187tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
12188let Inst{6-5} = 0b00;
12189let Inst{31-21} = 0b00111010110;
12190let addrMode = BaseRegOffset;
12191let accessSize = DoubleWordAccess;
12192let mayLoad = 1;
12193let BaseOpcode = "L4_loadrd_rr";
12194let CextOpcode = "L2_loadrd";
12195let InputType = "reg";
12196let isPredicable = 1;
12197}
12198def L4_loadrd_ur : HInst<
12199(outs DoubleRegs:$Rdd32),
12200(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12201"$Rdd32 = memd($Rt32<<#$Ii+#$II)",
12202tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
12203let Inst{12-12} = 0b1;
12204let Inst{31-21} = 0b10011101110;
12205let addrMode = BaseLongOffset;
12206let accessSize = DoubleWordAccess;
12207let mayLoad = 1;
12208let isExtended = 1;
12209let CextOpcode = "L2_loadrd";
12210let InputType = "imm";
12211let DecoderNamespace = "MustExtend";
12212let isExtendable = 1;
12213let opExtendable = 3;
12214let isExtentSigned = 0;
12215let opExtentBits = 6;
12216let opExtentAlign = 0;
12217}
12218def L4_loadrh_ap : HInst<
12219(outs IntRegs:$Rd32, IntRegs:$Re32),
12220(ins u32_0Imm:$II),
12221"$Rd32 = memh($Re32=#$II)",
12222tc_822c3c68, TypeLD>, Enc_323f2d {
12223let Inst{7-7} = 0b0;
12224let Inst{13-12} = 0b01;
12225let Inst{31-21} = 0b10011011010;
12226let hasNewValue = 1;
12227let opNewValue = 0;
12228let addrMode = AbsoluteSet;
12229let accessSize = HalfWordAccess;
12230let mayLoad = 1;
12231let isExtended = 1;
12232let DecoderNamespace = "MustExtend";
12233let isExtendable = 1;
12234let opExtendable = 2;
12235let isExtentSigned = 0;
12236let opExtentBits = 6;
12237let opExtentAlign = 0;
12238}
12239def L4_loadrh_rr : HInst<
12240(outs IntRegs:$Rd32),
12241(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12242"$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12243tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12244let Inst{6-5} = 0b00;
12245let Inst{31-21} = 0b00111010010;
12246let hasNewValue = 1;
12247let opNewValue = 0;
12248let addrMode = BaseRegOffset;
12249let accessSize = HalfWordAccess;
12250let mayLoad = 1;
12251let BaseOpcode = "L4_loadrh_rr";
12252let CextOpcode = "L2_loadrh";
12253let InputType = "reg";
12254let isPredicable = 1;
12255}
12256def L4_loadrh_ur : HInst<
12257(outs IntRegs:$Rd32),
12258(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12259"$Rd32 = memh($Rt32<<#$Ii+#$II)",
12260tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12261let Inst{12-12} = 0b1;
12262let Inst{31-21} = 0b10011101010;
12263let hasNewValue = 1;
12264let opNewValue = 0;
12265let addrMode = BaseLongOffset;
12266let accessSize = HalfWordAccess;
12267let mayLoad = 1;
12268let isExtended = 1;
12269let CextOpcode = "L2_loadrh";
12270let InputType = "imm";
12271let DecoderNamespace = "MustExtend";
12272let isExtendable = 1;
12273let opExtendable = 3;
12274let isExtentSigned = 0;
12275let opExtentBits = 6;
12276let opExtentAlign = 0;
12277}
12278def L4_loadri_ap : HInst<
12279(outs IntRegs:$Rd32, IntRegs:$Re32),
12280(ins u32_0Imm:$II),
12281"$Rd32 = memw($Re32=#$II)",
12282tc_822c3c68, TypeLD>, Enc_323f2d {
12283let Inst{7-7} = 0b0;
12284let Inst{13-12} = 0b01;
12285let Inst{31-21} = 0b10011011100;
12286let hasNewValue = 1;
12287let opNewValue = 0;
12288let addrMode = AbsoluteSet;
12289let accessSize = WordAccess;
12290let mayLoad = 1;
12291let isExtended = 1;
12292let DecoderNamespace = "MustExtend";
12293let isExtendable = 1;
12294let opExtendable = 2;
12295let isExtentSigned = 0;
12296let opExtentBits = 6;
12297let opExtentAlign = 0;
12298}
12299def L4_loadri_rr : HInst<
12300(outs IntRegs:$Rd32),
12301(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12302"$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12303tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12304let Inst{6-5} = 0b00;
12305let Inst{31-21} = 0b00111010100;
12306let hasNewValue = 1;
12307let opNewValue = 0;
12308let addrMode = BaseRegOffset;
12309let accessSize = WordAccess;
12310let mayLoad = 1;
12311let BaseOpcode = "L4_loadri_rr";
12312let CextOpcode = "L2_loadri";
12313let InputType = "reg";
12314let isPredicable = 1;
12315}
12316def L4_loadri_ur : HInst<
12317(outs IntRegs:$Rd32),
12318(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12319"$Rd32 = memw($Rt32<<#$Ii+#$II)",
12320tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12321let Inst{12-12} = 0b1;
12322let Inst{31-21} = 0b10011101100;
12323let hasNewValue = 1;
12324let opNewValue = 0;
12325let addrMode = BaseLongOffset;
12326let accessSize = WordAccess;
12327let mayLoad = 1;
12328let isExtended = 1;
12329let CextOpcode = "L2_loadri";
12330let InputType = "imm";
12331let DecoderNamespace = "MustExtend";
12332let isExtendable = 1;
12333let opExtendable = 3;
12334let isExtentSigned = 0;
12335let opExtentBits = 6;
12336let opExtentAlign = 0;
12337}
12338def L4_loadrub_ap : HInst<
12339(outs IntRegs:$Rd32, IntRegs:$Re32),
12340(ins u32_0Imm:$II),
12341"$Rd32 = memub($Re32=#$II)",
12342tc_822c3c68, TypeLD>, Enc_323f2d {
12343let Inst{7-7} = 0b0;
12344let Inst{13-12} = 0b01;
12345let Inst{31-21} = 0b10011011001;
12346let hasNewValue = 1;
12347let opNewValue = 0;
12348let addrMode = AbsoluteSet;
12349let accessSize = ByteAccess;
12350let mayLoad = 1;
12351let isExtended = 1;
12352let DecoderNamespace = "MustExtend";
12353let isExtendable = 1;
12354let opExtendable = 2;
12355let isExtentSigned = 0;
12356let opExtentBits = 6;
12357let opExtentAlign = 0;
12358}
12359def L4_loadrub_rr : HInst<
12360(outs IntRegs:$Rd32),
12361(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12362"$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12363tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12364let Inst{6-5} = 0b00;
12365let Inst{31-21} = 0b00111010001;
12366let hasNewValue = 1;
12367let opNewValue = 0;
12368let addrMode = BaseRegOffset;
12369let accessSize = ByteAccess;
12370let mayLoad = 1;
12371let BaseOpcode = "L4_loadrub_rr";
12372let CextOpcode = "L2_loadrub";
12373let InputType = "reg";
12374let isPredicable = 1;
12375}
12376def L4_loadrub_ur : HInst<
12377(outs IntRegs:$Rd32),
12378(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12379"$Rd32 = memub($Rt32<<#$Ii+#$II)",
12380tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12381let Inst{12-12} = 0b1;
12382let Inst{31-21} = 0b10011101001;
12383let hasNewValue = 1;
12384let opNewValue = 0;
12385let addrMode = BaseLongOffset;
12386let accessSize = ByteAccess;
12387let mayLoad = 1;
12388let isExtended = 1;
12389let CextOpcode = "L2_loadrub";
12390let InputType = "imm";
12391let DecoderNamespace = "MustExtend";
12392let isExtendable = 1;
12393let opExtendable = 3;
12394let isExtentSigned = 0;
12395let opExtentBits = 6;
12396let opExtentAlign = 0;
12397}
12398def L4_loadruh_ap : HInst<
12399(outs IntRegs:$Rd32, IntRegs:$Re32),
12400(ins u32_0Imm:$II),
12401"$Rd32 = memuh($Re32=#$II)",
12402tc_822c3c68, TypeLD>, Enc_323f2d {
12403let Inst{7-7} = 0b0;
12404let Inst{13-12} = 0b01;
12405let Inst{31-21} = 0b10011011011;
12406let hasNewValue = 1;
12407let opNewValue = 0;
12408let addrMode = AbsoluteSet;
12409let accessSize = HalfWordAccess;
12410let mayLoad = 1;
12411let isExtended = 1;
12412let DecoderNamespace = "MustExtend";
12413let isExtendable = 1;
12414let opExtendable = 2;
12415let isExtentSigned = 0;
12416let opExtentBits = 6;
12417let opExtentAlign = 0;
12418}
12419def L4_loadruh_rr : HInst<
12420(outs IntRegs:$Rd32),
12421(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12422"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
12423tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12424let Inst{6-5} = 0b00;
12425let Inst{31-21} = 0b00111010011;
12426let hasNewValue = 1;
12427let opNewValue = 0;
12428let addrMode = BaseRegOffset;
12429let accessSize = HalfWordAccess;
12430let mayLoad = 1;
12431let BaseOpcode = "L4_loadruh_rr";
12432let CextOpcode = "L2_loadruh";
12433let InputType = "reg";
12434let isPredicable = 1;
12435}
12436def L4_loadruh_ur : HInst<
12437(outs IntRegs:$Rd32),
12438(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12439"$Rd32 = memuh($Rt32<<#$Ii+#$II)",
12440tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12441let Inst{12-12} = 0b1;
12442let Inst{31-21} = 0b10011101011;
12443let hasNewValue = 1;
12444let opNewValue = 0;
12445let addrMode = BaseLongOffset;
12446let accessSize = HalfWordAccess;
12447let mayLoad = 1;
12448let isExtended = 1;
12449let CextOpcode = "L2_loadruh";
12450let InputType = "imm";
12451let DecoderNamespace = "MustExtend";
12452let isExtendable = 1;
12453let opExtendable = 3;
12454let isExtentSigned = 0;
12455let opExtentBits = 6;
12456let opExtentAlign = 0;
12457}
12458def L4_loadw_phys : HInst<
12459(outs IntRegs:$Rd32),
12460(ins IntRegs:$Rs32, IntRegs:$Rt32),
12461"$Rd32 = memw_phys($Rs32,$Rt32)",
12462tc_ed3f8d2a, TypeLD>, Enc_5ab2be {
12463let Inst{7-5} = 0b000;
12464let Inst{13-13} = 0b1;
12465let Inst{31-21} = 0b10010010000;
12466let hasNewValue = 1;
12467let opNewValue = 0;
12468let accessSize = WordAccess;
12469let mayLoad = 1;
12470let isSolo = 1;
12471}
12472def L4_or_memopb_io : HInst<
12473(outs),
12474(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
12475"memb($Rs32+#$Ii) |= $Rt32",
12476tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
12477let Inst{6-5} = 0b11;
12478let Inst{13-13} = 0b0;
12479let Inst{31-21} = 0b00111110000;
12480let addrMode = BaseImmOffset;
12481let accessSize = ByteAccess;
12482let mayLoad = 1;
12483let isRestrictNoSlot1Store = 1;
12484let mayStore = 1;
12485let isExtendable = 1;
12486let opExtendable = 1;
12487let isExtentSigned = 0;
12488let opExtentBits = 6;
12489let opExtentAlign = 0;
12490}
12491def L4_or_memopb_zomap : HInst<
12492(outs),
12493(ins IntRegs:$Rs32, IntRegs:$Rt32),
12494"memb($Rs32) |= $Rt32",
12495tc_9bcfb2ee, TypeMAPPING> {
12496let isPseudo = 1;
12497let isCodeGenOnly = 1;
12498}
12499def L4_or_memoph_io : HInst<
12500(outs),
12501(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
12502"memh($Rs32+#$Ii) |= $Rt32",
12503tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
12504let Inst{6-5} = 0b11;
12505let Inst{13-13} = 0b0;
12506let Inst{31-21} = 0b00111110001;
12507let addrMode = BaseImmOffset;
12508let accessSize = HalfWordAccess;
12509let mayLoad = 1;
12510let isRestrictNoSlot1Store = 1;
12511let mayStore = 1;
12512let isExtendable = 1;
12513let opExtendable = 1;
12514let isExtentSigned = 0;
12515let opExtentBits = 7;
12516let opExtentAlign = 1;
12517}
12518def L4_or_memoph_zomap : HInst<
12519(outs),
12520(ins IntRegs:$Rs32, IntRegs:$Rt32),
12521"memh($Rs32) |= $Rt32",
12522tc_9bcfb2ee, TypeMAPPING> {
12523let isPseudo = 1;
12524let isCodeGenOnly = 1;
12525}
12526def L4_or_memopw_io : HInst<
12527(outs),
12528(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
12529"memw($Rs32+#$Ii) |= $Rt32",
12530tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
12531let Inst{6-5} = 0b11;
12532let Inst{13-13} = 0b0;
12533let Inst{31-21} = 0b00111110010;
12534let addrMode = BaseImmOffset;
12535let accessSize = WordAccess;
12536let mayLoad = 1;
12537let isRestrictNoSlot1Store = 1;
12538let mayStore = 1;
12539let isExtendable = 1;
12540let opExtendable = 1;
12541let isExtentSigned = 0;
12542let opExtentBits = 8;
12543let opExtentAlign = 2;
12544}
12545def L4_or_memopw_zomap : HInst<
12546(outs),
12547(ins IntRegs:$Rs32, IntRegs:$Rt32),
12548"memw($Rs32) |= $Rt32",
12549tc_9bcfb2ee, TypeMAPPING> {
12550let isPseudo = 1;
12551let isCodeGenOnly = 1;
12552}
12553def L4_ploadrbf_abs : HInst<
12554(outs IntRegs:$Rd32),
12555(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12556"if (!$Pt4) $Rd32 = memb(#$Ii)",
12557tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12558let Inst{7-5} = 0b100;
12559let Inst{13-11} = 0b101;
12560let Inst{31-21} = 0b10011111000;
12561let isPredicated = 1;
12562let isPredicatedFalse = 1;
12563let hasNewValue = 1;
12564let opNewValue = 0;
12565let addrMode = Absolute;
12566let accessSize = ByteAccess;
12567let mayLoad = 1;
12568let isExtended = 1;
12569let BaseOpcode = "L4_loadrb_abs";
12570let CextOpcode = "L2_loadrb";
12571let DecoderNamespace = "MustExtend";
12572let isExtendable = 1;
12573let opExtendable = 2;
12574let isExtentSigned = 0;
12575let opExtentBits = 6;
12576let opExtentAlign = 0;
12577}
12578def L4_ploadrbf_rr : HInst<
12579(outs IntRegs:$Rd32),
12580(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12581"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12582tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12583let Inst{31-21} = 0b00110001000;
12584let isPredicated = 1;
12585let isPredicatedFalse = 1;
12586let hasNewValue = 1;
12587let opNewValue = 0;
12588let addrMode = BaseRegOffset;
12589let accessSize = ByteAccess;
12590let mayLoad = 1;
12591let BaseOpcode = "L4_loadrb_rr";
12592let CextOpcode = "L2_loadrb";
12593let InputType = "reg";
12594}
12595def L4_ploadrbfnew_abs : HInst<
12596(outs IntRegs:$Rd32),
12597(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12598"if (!$Pt4.new) $Rd32 = memb(#$Ii)",
12599tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12600let Inst{7-5} = 0b100;
12601let Inst{13-11} = 0b111;
12602let Inst{31-21} = 0b10011111000;
12603let isPredicated = 1;
12604let isPredicatedFalse = 1;
12605let hasNewValue = 1;
12606let opNewValue = 0;
12607let addrMode = Absolute;
12608let accessSize = ByteAccess;
12609let isPredicatedNew = 1;
12610let mayLoad = 1;
12611let isExtended = 1;
12612let BaseOpcode = "L4_loadrb_abs";
12613let CextOpcode = "L2_loadrb";
12614let DecoderNamespace = "MustExtend";
12615let isExtendable = 1;
12616let opExtendable = 2;
12617let isExtentSigned = 0;
12618let opExtentBits = 6;
12619let opExtentAlign = 0;
12620}
12621def L4_ploadrbfnew_rr : HInst<
12622(outs IntRegs:$Rd32),
12623(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12624"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12625tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12626let Inst{31-21} = 0b00110011000;
12627let isPredicated = 1;
12628let isPredicatedFalse = 1;
12629let hasNewValue = 1;
12630let opNewValue = 0;
12631let addrMode = BaseRegOffset;
12632let accessSize = ByteAccess;
12633let isPredicatedNew = 1;
12634let mayLoad = 1;
12635let BaseOpcode = "L4_loadrb_rr";
12636let CextOpcode = "L2_loadrb";
12637let InputType = "reg";
12638}
12639def L4_ploadrbt_abs : HInst<
12640(outs IntRegs:$Rd32),
12641(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12642"if ($Pt4) $Rd32 = memb(#$Ii)",
12643tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12644let Inst{7-5} = 0b100;
12645let Inst{13-11} = 0b100;
12646let Inst{31-21} = 0b10011111000;
12647let isPredicated = 1;
12648let hasNewValue = 1;
12649let opNewValue = 0;
12650let addrMode = Absolute;
12651let accessSize = ByteAccess;
12652let mayLoad = 1;
12653let isExtended = 1;
12654let BaseOpcode = "L4_loadrb_abs";
12655let CextOpcode = "L2_loadrb";
12656let DecoderNamespace = "MustExtend";
12657let isExtendable = 1;
12658let opExtendable = 2;
12659let isExtentSigned = 0;
12660let opExtentBits = 6;
12661let opExtentAlign = 0;
12662}
12663def L4_ploadrbt_rr : HInst<
12664(outs IntRegs:$Rd32),
12665(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12666"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12667tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12668let Inst{31-21} = 0b00110000000;
12669let isPredicated = 1;
12670let hasNewValue = 1;
12671let opNewValue = 0;
12672let addrMode = BaseRegOffset;
12673let accessSize = ByteAccess;
12674let mayLoad = 1;
12675let BaseOpcode = "L4_loadrb_rr";
12676let CextOpcode = "L2_loadrb";
12677let InputType = "reg";
12678}
12679def L4_ploadrbtnew_abs : HInst<
12680(outs IntRegs:$Rd32),
12681(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12682"if ($Pt4.new) $Rd32 = memb(#$Ii)",
12683tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12684let Inst{7-5} = 0b100;
12685let Inst{13-11} = 0b110;
12686let Inst{31-21} = 0b10011111000;
12687let isPredicated = 1;
12688let hasNewValue = 1;
12689let opNewValue = 0;
12690let addrMode = Absolute;
12691let accessSize = ByteAccess;
12692let isPredicatedNew = 1;
12693let mayLoad = 1;
12694let isExtended = 1;
12695let BaseOpcode = "L4_loadrb_abs";
12696let CextOpcode = "L2_loadrb";
12697let DecoderNamespace = "MustExtend";
12698let isExtendable = 1;
12699let opExtendable = 2;
12700let isExtentSigned = 0;
12701let opExtentBits = 6;
12702let opExtentAlign = 0;
12703}
12704def L4_ploadrbtnew_rr : HInst<
12705(outs IntRegs:$Rd32),
12706(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12707"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12708tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12709let Inst{31-21} = 0b00110010000;
12710let isPredicated = 1;
12711let hasNewValue = 1;
12712let opNewValue = 0;
12713let addrMode = BaseRegOffset;
12714let accessSize = ByteAccess;
12715let isPredicatedNew = 1;
12716let mayLoad = 1;
12717let BaseOpcode = "L4_loadrb_rr";
12718let CextOpcode = "L2_loadrb";
12719let InputType = "reg";
12720}
12721def L4_ploadrdf_abs : HInst<
12722(outs DoubleRegs:$Rdd32),
12723(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12724"if (!$Pt4) $Rdd32 = memd(#$Ii)",
12725tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12726let Inst{7-5} = 0b100;
12727let Inst{13-11} = 0b101;
12728let Inst{31-21} = 0b10011111110;
12729let isPredicated = 1;
12730let isPredicatedFalse = 1;
12731let addrMode = Absolute;
12732let accessSize = DoubleWordAccess;
12733let mayLoad = 1;
12734let isExtended = 1;
12735let BaseOpcode = "L4_loadrd_abs";
12736let CextOpcode = "L2_loadrd";
12737let DecoderNamespace = "MustExtend";
12738let isExtendable = 1;
12739let opExtendable = 2;
12740let isExtentSigned = 0;
12741let opExtentBits = 6;
12742let opExtentAlign = 0;
12743}
12744def L4_ploadrdf_rr : HInst<
12745(outs DoubleRegs:$Rdd32),
12746(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12747"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12748tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12749let Inst{31-21} = 0b00110001110;
12750let isPredicated = 1;
12751let isPredicatedFalse = 1;
12752let addrMode = BaseRegOffset;
12753let accessSize = DoubleWordAccess;
12754let mayLoad = 1;
12755let BaseOpcode = "L4_loadrd_rr";
12756let CextOpcode = "L2_loadrd";
12757let InputType = "reg";
12758}
12759def L4_ploadrdfnew_abs : HInst<
12760(outs DoubleRegs:$Rdd32),
12761(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12762"if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
12763tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12764let Inst{7-5} = 0b100;
12765let Inst{13-11} = 0b111;
12766let Inst{31-21} = 0b10011111110;
12767let isPredicated = 1;
12768let isPredicatedFalse = 1;
12769let addrMode = Absolute;
12770let accessSize = DoubleWordAccess;
12771let isPredicatedNew = 1;
12772let mayLoad = 1;
12773let isExtended = 1;
12774let BaseOpcode = "L4_loadrd_abs";
12775let CextOpcode = "L2_loadrd";
12776let DecoderNamespace = "MustExtend";
12777let isExtendable = 1;
12778let opExtendable = 2;
12779let isExtentSigned = 0;
12780let opExtentBits = 6;
12781let opExtentAlign = 0;
12782}
12783def L4_ploadrdfnew_rr : HInst<
12784(outs DoubleRegs:$Rdd32),
12785(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12786"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12787tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12788let Inst{31-21} = 0b00110011110;
12789let isPredicated = 1;
12790let isPredicatedFalse = 1;
12791let addrMode = BaseRegOffset;
12792let accessSize = DoubleWordAccess;
12793let isPredicatedNew = 1;
12794let mayLoad = 1;
12795let BaseOpcode = "L4_loadrd_rr";
12796let CextOpcode = "L2_loadrd";
12797let InputType = "reg";
12798}
12799def L4_ploadrdt_abs : HInst<
12800(outs DoubleRegs:$Rdd32),
12801(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12802"if ($Pt4) $Rdd32 = memd(#$Ii)",
12803tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12804let Inst{7-5} = 0b100;
12805let Inst{13-11} = 0b100;
12806let Inst{31-21} = 0b10011111110;
12807let isPredicated = 1;
12808let addrMode = Absolute;
12809let accessSize = DoubleWordAccess;
12810let mayLoad = 1;
12811let isExtended = 1;
12812let BaseOpcode = "L4_loadrd_abs";
12813let CextOpcode = "L2_loadrd";
12814let DecoderNamespace = "MustExtend";
12815let isExtendable = 1;
12816let opExtendable = 2;
12817let isExtentSigned = 0;
12818let opExtentBits = 6;
12819let opExtentAlign = 0;
12820}
12821def L4_ploadrdt_rr : HInst<
12822(outs DoubleRegs:$Rdd32),
12823(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12824"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12825tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12826let Inst{31-21} = 0b00110000110;
12827let isPredicated = 1;
12828let addrMode = BaseRegOffset;
12829let accessSize = DoubleWordAccess;
12830let mayLoad = 1;
12831let BaseOpcode = "L4_loadrd_rr";
12832let CextOpcode = "L2_loadrd";
12833let InputType = "reg";
12834}
12835def L4_ploadrdtnew_abs : HInst<
12836(outs DoubleRegs:$Rdd32),
12837(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12838"if ($Pt4.new) $Rdd32 = memd(#$Ii)",
12839tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12840let Inst{7-5} = 0b100;
12841let Inst{13-11} = 0b110;
12842let Inst{31-21} = 0b10011111110;
12843let isPredicated = 1;
12844let addrMode = Absolute;
12845let accessSize = DoubleWordAccess;
12846let isPredicatedNew = 1;
12847let mayLoad = 1;
12848let isExtended = 1;
12849let BaseOpcode = "L4_loadrd_abs";
12850let CextOpcode = "L2_loadrd";
12851let DecoderNamespace = "MustExtend";
12852let isExtendable = 1;
12853let opExtendable = 2;
12854let isExtentSigned = 0;
12855let opExtentBits = 6;
12856let opExtentAlign = 0;
12857}
12858def L4_ploadrdtnew_rr : HInst<
12859(outs DoubleRegs:$Rdd32),
12860(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12861"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12862tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12863let Inst{31-21} = 0b00110010110;
12864let isPredicated = 1;
12865let addrMode = BaseRegOffset;
12866let accessSize = DoubleWordAccess;
12867let isPredicatedNew = 1;
12868let mayLoad = 1;
12869let BaseOpcode = "L4_loadrd_rr";
12870let CextOpcode = "L2_loadrd";
12871let InputType = "reg";
12872}
12873def L4_ploadrhf_abs : HInst<
12874(outs IntRegs:$Rd32),
12875(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12876"if (!$Pt4) $Rd32 = memh(#$Ii)",
12877tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12878let Inst{7-5} = 0b100;
12879let Inst{13-11} = 0b101;
12880let Inst{31-21} = 0b10011111010;
12881let isPredicated = 1;
12882let isPredicatedFalse = 1;
12883let hasNewValue = 1;
12884let opNewValue = 0;
12885let addrMode = Absolute;
12886let accessSize = HalfWordAccess;
12887let mayLoad = 1;
12888let isExtended = 1;
12889let BaseOpcode = "L4_loadrh_abs";
12890let CextOpcode = "L2_loadrh";
12891let DecoderNamespace = "MustExtend";
12892let isExtendable = 1;
12893let opExtendable = 2;
12894let isExtentSigned = 0;
12895let opExtentBits = 6;
12896let opExtentAlign = 0;
12897}
12898def L4_ploadrhf_rr : HInst<
12899(outs IntRegs:$Rd32),
12900(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12901"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12902tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12903let Inst{31-21} = 0b00110001010;
12904let isPredicated = 1;
12905let isPredicatedFalse = 1;
12906let hasNewValue = 1;
12907let opNewValue = 0;
12908let addrMode = BaseRegOffset;
12909let accessSize = HalfWordAccess;
12910let mayLoad = 1;
12911let BaseOpcode = "L4_loadrh_rr";
12912let CextOpcode = "L2_loadrh";
12913let InputType = "reg";
12914}
12915def L4_ploadrhfnew_abs : HInst<
12916(outs IntRegs:$Rd32),
12917(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12918"if (!$Pt4.new) $Rd32 = memh(#$Ii)",
12919tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12920let Inst{7-5} = 0b100;
12921let Inst{13-11} = 0b111;
12922let Inst{31-21} = 0b10011111010;
12923let isPredicated = 1;
12924let isPredicatedFalse = 1;
12925let hasNewValue = 1;
12926let opNewValue = 0;
12927let addrMode = Absolute;
12928let accessSize = HalfWordAccess;
12929let isPredicatedNew = 1;
12930let mayLoad = 1;
12931let isExtended = 1;
12932let BaseOpcode = "L4_loadrh_abs";
12933let CextOpcode = "L2_loadrh";
12934let DecoderNamespace = "MustExtend";
12935let isExtendable = 1;
12936let opExtendable = 2;
12937let isExtentSigned = 0;
12938let opExtentBits = 6;
12939let opExtentAlign = 0;
12940}
12941def L4_ploadrhfnew_rr : HInst<
12942(outs IntRegs:$Rd32),
12943(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12944"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12945tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12946let Inst{31-21} = 0b00110011010;
12947let isPredicated = 1;
12948let isPredicatedFalse = 1;
12949let hasNewValue = 1;
12950let opNewValue = 0;
12951let addrMode = BaseRegOffset;
12952let accessSize = HalfWordAccess;
12953let isPredicatedNew = 1;
12954let mayLoad = 1;
12955let BaseOpcode = "L4_loadrh_rr";
12956let CextOpcode = "L2_loadrh";
12957let InputType = "reg";
12958}
12959def L4_ploadrht_abs : HInst<
12960(outs IntRegs:$Rd32),
12961(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12962"if ($Pt4) $Rd32 = memh(#$Ii)",
12963tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12964let Inst{7-5} = 0b100;
12965let Inst{13-11} = 0b100;
12966let Inst{31-21} = 0b10011111010;
12967let isPredicated = 1;
12968let hasNewValue = 1;
12969let opNewValue = 0;
12970let addrMode = Absolute;
12971let accessSize = HalfWordAccess;
12972let mayLoad = 1;
12973let isExtended = 1;
12974let BaseOpcode = "L4_loadrh_abs";
12975let CextOpcode = "L2_loadrh";
12976let DecoderNamespace = "MustExtend";
12977let isExtendable = 1;
12978let opExtendable = 2;
12979let isExtentSigned = 0;
12980let opExtentBits = 6;
12981let opExtentAlign = 0;
12982}
12983def L4_ploadrht_rr : HInst<
12984(outs IntRegs:$Rd32),
12985(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12986"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12987tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12988let Inst{31-21} = 0b00110000010;
12989let isPredicated = 1;
12990let hasNewValue = 1;
12991let opNewValue = 0;
12992let addrMode = BaseRegOffset;
12993let accessSize = HalfWordAccess;
12994let mayLoad = 1;
12995let BaseOpcode = "L4_loadrh_rr";
12996let CextOpcode = "L2_loadrh";
12997let InputType = "reg";
12998}
12999def L4_ploadrhtnew_abs : HInst<
13000(outs IntRegs:$Rd32),
13001(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13002"if ($Pt4.new) $Rd32 = memh(#$Ii)",
13003tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13004let Inst{7-5} = 0b100;
13005let Inst{13-11} = 0b110;
13006let Inst{31-21} = 0b10011111010;
13007let isPredicated = 1;
13008let hasNewValue = 1;
13009let opNewValue = 0;
13010let addrMode = Absolute;
13011let accessSize = HalfWordAccess;
13012let isPredicatedNew = 1;
13013let mayLoad = 1;
13014let isExtended = 1;
13015let BaseOpcode = "L4_loadrh_abs";
13016let CextOpcode = "L2_loadrh";
13017let DecoderNamespace = "MustExtend";
13018let isExtendable = 1;
13019let opExtendable = 2;
13020let isExtentSigned = 0;
13021let opExtentBits = 6;
13022let opExtentAlign = 0;
13023}
13024def L4_ploadrhtnew_rr : HInst<
13025(outs IntRegs:$Rd32),
13026(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13027"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
13028tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13029let Inst{31-21} = 0b00110010010;
13030let isPredicated = 1;
13031let hasNewValue = 1;
13032let opNewValue = 0;
13033let addrMode = BaseRegOffset;
13034let accessSize = HalfWordAccess;
13035let isPredicatedNew = 1;
13036let mayLoad = 1;
13037let BaseOpcode = "L4_loadrh_rr";
13038let CextOpcode = "L2_loadrh";
13039let InputType = "reg";
13040}
13041def L4_ploadrif_abs : HInst<
13042(outs IntRegs:$Rd32),
13043(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13044"if (!$Pt4) $Rd32 = memw(#$Ii)",
13045tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13046let Inst{7-5} = 0b100;
13047let Inst{13-11} = 0b101;
13048let Inst{31-21} = 0b10011111100;
13049let isPredicated = 1;
13050let isPredicatedFalse = 1;
13051let hasNewValue = 1;
13052let opNewValue = 0;
13053let addrMode = Absolute;
13054let accessSize = WordAccess;
13055let mayLoad = 1;
13056let isExtended = 1;
13057let BaseOpcode = "L4_loadri_abs";
13058let CextOpcode = "L2_loadri";
13059let DecoderNamespace = "MustExtend";
13060let isExtendable = 1;
13061let opExtendable = 2;
13062let isExtentSigned = 0;
13063let opExtentBits = 6;
13064let opExtentAlign = 0;
13065}
13066def L4_ploadrif_rr : HInst<
13067(outs IntRegs:$Rd32),
13068(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13069"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13070tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13071let Inst{31-21} = 0b00110001100;
13072let isPredicated = 1;
13073let isPredicatedFalse = 1;
13074let hasNewValue = 1;
13075let opNewValue = 0;
13076let addrMode = BaseRegOffset;
13077let accessSize = WordAccess;
13078let mayLoad = 1;
13079let BaseOpcode = "L4_loadri_rr";
13080let CextOpcode = "L2_loadri";
13081let InputType = "reg";
13082}
13083def L4_ploadrifnew_abs : HInst<
13084(outs IntRegs:$Rd32),
13085(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13086"if (!$Pt4.new) $Rd32 = memw(#$Ii)",
13087tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13088let Inst{7-5} = 0b100;
13089let Inst{13-11} = 0b111;
13090let Inst{31-21} = 0b10011111100;
13091let isPredicated = 1;
13092let isPredicatedFalse = 1;
13093let hasNewValue = 1;
13094let opNewValue = 0;
13095let addrMode = Absolute;
13096let accessSize = WordAccess;
13097let isPredicatedNew = 1;
13098let mayLoad = 1;
13099let isExtended = 1;
13100let BaseOpcode = "L4_loadri_abs";
13101let CextOpcode = "L2_loadri";
13102let DecoderNamespace = "MustExtend";
13103let isExtendable = 1;
13104let opExtendable = 2;
13105let isExtentSigned = 0;
13106let opExtentBits = 6;
13107let opExtentAlign = 0;
13108}
13109def L4_ploadrifnew_rr : HInst<
13110(outs IntRegs:$Rd32),
13111(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13112"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13113tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13114let Inst{31-21} = 0b00110011100;
13115let isPredicated = 1;
13116let isPredicatedFalse = 1;
13117let hasNewValue = 1;
13118let opNewValue = 0;
13119let addrMode = BaseRegOffset;
13120let accessSize = WordAccess;
13121let isPredicatedNew = 1;
13122let mayLoad = 1;
13123let BaseOpcode = "L4_loadri_rr";
13124let CextOpcode = "L2_loadri";
13125let InputType = "reg";
13126}
13127def L4_ploadrit_abs : HInst<
13128(outs IntRegs:$Rd32),
13129(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13130"if ($Pt4) $Rd32 = memw(#$Ii)",
13131tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13132let Inst{7-5} = 0b100;
13133let Inst{13-11} = 0b100;
13134let Inst{31-21} = 0b10011111100;
13135let isPredicated = 1;
13136let hasNewValue = 1;
13137let opNewValue = 0;
13138let addrMode = Absolute;
13139let accessSize = WordAccess;
13140let mayLoad = 1;
13141let isExtended = 1;
13142let BaseOpcode = "L4_loadri_abs";
13143let CextOpcode = "L2_loadri";
13144let DecoderNamespace = "MustExtend";
13145let isExtendable = 1;
13146let opExtendable = 2;
13147let isExtentSigned = 0;
13148let opExtentBits = 6;
13149let opExtentAlign = 0;
13150}
13151def L4_ploadrit_rr : HInst<
13152(outs IntRegs:$Rd32),
13153(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13154"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13155tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13156let Inst{31-21} = 0b00110000100;
13157let isPredicated = 1;
13158let hasNewValue = 1;
13159let opNewValue = 0;
13160let addrMode = BaseRegOffset;
13161let accessSize = WordAccess;
13162let mayLoad = 1;
13163let BaseOpcode = "L4_loadri_rr";
13164let CextOpcode = "L2_loadri";
13165let InputType = "reg";
13166}
13167def L4_ploadritnew_abs : HInst<
13168(outs IntRegs:$Rd32),
13169(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13170"if ($Pt4.new) $Rd32 = memw(#$Ii)",
13171tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13172let Inst{7-5} = 0b100;
13173let Inst{13-11} = 0b110;
13174let Inst{31-21} = 0b10011111100;
13175let isPredicated = 1;
13176let hasNewValue = 1;
13177let opNewValue = 0;
13178let addrMode = Absolute;
13179let accessSize = WordAccess;
13180let isPredicatedNew = 1;
13181let mayLoad = 1;
13182let isExtended = 1;
13183let BaseOpcode = "L4_loadri_abs";
13184let CextOpcode = "L2_loadri";
13185let DecoderNamespace = "MustExtend";
13186let isExtendable = 1;
13187let opExtendable = 2;
13188let isExtentSigned = 0;
13189let opExtentBits = 6;
13190let opExtentAlign = 0;
13191}
13192def L4_ploadritnew_rr : HInst<
13193(outs IntRegs:$Rd32),
13194(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13195"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13196tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13197let Inst{31-21} = 0b00110010100;
13198let isPredicated = 1;
13199let hasNewValue = 1;
13200let opNewValue = 0;
13201let addrMode = BaseRegOffset;
13202let accessSize = WordAccess;
13203let isPredicatedNew = 1;
13204let mayLoad = 1;
13205let BaseOpcode = "L4_loadri_rr";
13206let CextOpcode = "L2_loadri";
13207let InputType = "reg";
13208}
13209def L4_ploadrubf_abs : HInst<
13210(outs IntRegs:$Rd32),
13211(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13212"if (!$Pt4) $Rd32 = memub(#$Ii)",
13213tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13214let Inst{7-5} = 0b100;
13215let Inst{13-11} = 0b101;
13216let Inst{31-21} = 0b10011111001;
13217let isPredicated = 1;
13218let isPredicatedFalse = 1;
13219let hasNewValue = 1;
13220let opNewValue = 0;
13221let addrMode = Absolute;
13222let accessSize = ByteAccess;
13223let mayLoad = 1;
13224let isExtended = 1;
13225let BaseOpcode = "L4_loadrub_abs";
13226let CextOpcode = "L2_loadrub";
13227let DecoderNamespace = "MustExtend";
13228let isExtendable = 1;
13229let opExtendable = 2;
13230let isExtentSigned = 0;
13231let opExtentBits = 6;
13232let opExtentAlign = 0;
13233}
13234def L4_ploadrubf_rr : HInst<
13235(outs IntRegs:$Rd32),
13236(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13237"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13238tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13239let Inst{31-21} = 0b00110001001;
13240let isPredicated = 1;
13241let isPredicatedFalse = 1;
13242let hasNewValue = 1;
13243let opNewValue = 0;
13244let addrMode = BaseRegOffset;
13245let accessSize = ByteAccess;
13246let mayLoad = 1;
13247let BaseOpcode = "L4_loadrub_rr";
13248let CextOpcode = "L2_loadrub";
13249let InputType = "reg";
13250}
13251def L4_ploadrubfnew_abs : HInst<
13252(outs IntRegs:$Rd32),
13253(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13254"if (!$Pt4.new) $Rd32 = memub(#$Ii)",
13255tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13256let Inst{7-5} = 0b100;
13257let Inst{13-11} = 0b111;
13258let Inst{31-21} = 0b10011111001;
13259let isPredicated = 1;
13260let isPredicatedFalse = 1;
13261let hasNewValue = 1;
13262let opNewValue = 0;
13263let addrMode = Absolute;
13264let accessSize = ByteAccess;
13265let isPredicatedNew = 1;
13266let mayLoad = 1;
13267let isExtended = 1;
13268let BaseOpcode = "L4_loadrub_abs";
13269let CextOpcode = "L2_loadrub";
13270let DecoderNamespace = "MustExtend";
13271let isExtendable = 1;
13272let opExtendable = 2;
13273let isExtentSigned = 0;
13274let opExtentBits = 6;
13275let opExtentAlign = 0;
13276}
13277def L4_ploadrubfnew_rr : HInst<
13278(outs IntRegs:$Rd32),
13279(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13280"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13281tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13282let Inst{31-21} = 0b00110011001;
13283let isPredicated = 1;
13284let isPredicatedFalse = 1;
13285let hasNewValue = 1;
13286let opNewValue = 0;
13287let addrMode = BaseRegOffset;
13288let accessSize = ByteAccess;
13289let isPredicatedNew = 1;
13290let mayLoad = 1;
13291let BaseOpcode = "L4_loadrub_rr";
13292let CextOpcode = "L2_loadrub";
13293let InputType = "reg";
13294}
13295def L4_ploadrubt_abs : HInst<
13296(outs IntRegs:$Rd32),
13297(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13298"if ($Pt4) $Rd32 = memub(#$Ii)",
13299tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13300let Inst{7-5} = 0b100;
13301let Inst{13-11} = 0b100;
13302let Inst{31-21} = 0b10011111001;
13303let isPredicated = 1;
13304let hasNewValue = 1;
13305let opNewValue = 0;
13306let addrMode = Absolute;
13307let accessSize = ByteAccess;
13308let mayLoad = 1;
13309let isExtended = 1;
13310let BaseOpcode = "L4_loadrub_abs";
13311let CextOpcode = "L2_loadrub";
13312let DecoderNamespace = "MustExtend";
13313let isExtendable = 1;
13314let opExtendable = 2;
13315let isExtentSigned = 0;
13316let opExtentBits = 6;
13317let opExtentAlign = 0;
13318}
13319def L4_ploadrubt_rr : HInst<
13320(outs IntRegs:$Rd32),
13321(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13322"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13323tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13324let Inst{31-21} = 0b00110000001;
13325let isPredicated = 1;
13326let hasNewValue = 1;
13327let opNewValue = 0;
13328let addrMode = BaseRegOffset;
13329let accessSize = ByteAccess;
13330let mayLoad = 1;
13331let BaseOpcode = "L4_loadrub_rr";
13332let CextOpcode = "L2_loadrub";
13333let InputType = "reg";
13334}
13335def L4_ploadrubtnew_abs : HInst<
13336(outs IntRegs:$Rd32),
13337(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13338"if ($Pt4.new) $Rd32 = memub(#$Ii)",
13339tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13340let Inst{7-5} = 0b100;
13341let Inst{13-11} = 0b110;
13342let Inst{31-21} = 0b10011111001;
13343let isPredicated = 1;
13344let hasNewValue = 1;
13345let opNewValue = 0;
13346let addrMode = Absolute;
13347let accessSize = ByteAccess;
13348let isPredicatedNew = 1;
13349let mayLoad = 1;
13350let isExtended = 1;
13351let BaseOpcode = "L4_loadrub_abs";
13352let CextOpcode = "L2_loadrub";
13353let DecoderNamespace = "MustExtend";
13354let isExtendable = 1;
13355let opExtendable = 2;
13356let isExtentSigned = 0;
13357let opExtentBits = 6;
13358let opExtentAlign = 0;
13359}
13360def L4_ploadrubtnew_rr : HInst<
13361(outs IntRegs:$Rd32),
13362(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13363"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13364tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13365let Inst{31-21} = 0b00110010001;
13366let isPredicated = 1;
13367let hasNewValue = 1;
13368let opNewValue = 0;
13369let addrMode = BaseRegOffset;
13370let accessSize = ByteAccess;
13371let isPredicatedNew = 1;
13372let mayLoad = 1;
13373let BaseOpcode = "L4_loadrub_rr";
13374let CextOpcode = "L2_loadrub";
13375let InputType = "reg";
13376}
13377def L4_ploadruhf_abs : HInst<
13378(outs IntRegs:$Rd32),
13379(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13380"if (!$Pt4) $Rd32 = memuh(#$Ii)",
13381tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13382let Inst{7-5} = 0b100;
13383let Inst{13-11} = 0b101;
13384let Inst{31-21} = 0b10011111011;
13385let isPredicated = 1;
13386let isPredicatedFalse = 1;
13387let hasNewValue = 1;
13388let opNewValue = 0;
13389let addrMode = Absolute;
13390let accessSize = HalfWordAccess;
13391let mayLoad = 1;
13392let isExtended = 1;
13393let BaseOpcode = "L4_loadruh_abs";
13394let CextOpcode = "L2_loadruh";
13395let DecoderNamespace = "MustExtend";
13396let isExtendable = 1;
13397let opExtendable = 2;
13398let isExtentSigned = 0;
13399let opExtentBits = 6;
13400let opExtentAlign = 0;
13401}
13402def L4_ploadruhf_rr : HInst<
13403(outs IntRegs:$Rd32),
13404(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13405"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13406tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13407let Inst{31-21} = 0b00110001011;
13408let isPredicated = 1;
13409let isPredicatedFalse = 1;
13410let hasNewValue = 1;
13411let opNewValue = 0;
13412let addrMode = BaseRegOffset;
13413let accessSize = HalfWordAccess;
13414let mayLoad = 1;
13415let BaseOpcode = "L4_loadruh_rr";
13416let CextOpcode = "L2_loadruh";
13417let InputType = "reg";
13418}
13419def L4_ploadruhfnew_abs : HInst<
13420(outs IntRegs:$Rd32),
13421(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13422"if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
13423tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13424let Inst{7-5} = 0b100;
13425let Inst{13-11} = 0b111;
13426let Inst{31-21} = 0b10011111011;
13427let isPredicated = 1;
13428let isPredicatedFalse = 1;
13429let hasNewValue = 1;
13430let opNewValue = 0;
13431let addrMode = Absolute;
13432let accessSize = HalfWordAccess;
13433let isPredicatedNew = 1;
13434let mayLoad = 1;
13435let isExtended = 1;
13436let BaseOpcode = "L4_loadruh_abs";
13437let CextOpcode = "L2_loadruh";
13438let DecoderNamespace = "MustExtend";
13439let isExtendable = 1;
13440let opExtendable = 2;
13441let isExtentSigned = 0;
13442let opExtentBits = 6;
13443let opExtentAlign = 0;
13444}
13445def L4_ploadruhfnew_rr : HInst<
13446(outs IntRegs:$Rd32),
13447(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13448"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13449tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13450let Inst{31-21} = 0b00110011011;
13451let isPredicated = 1;
13452let isPredicatedFalse = 1;
13453let hasNewValue = 1;
13454let opNewValue = 0;
13455let addrMode = BaseRegOffset;
13456let accessSize = HalfWordAccess;
13457let isPredicatedNew = 1;
13458let mayLoad = 1;
13459let BaseOpcode = "L4_loadruh_rr";
13460let CextOpcode = "L2_loadruh";
13461let InputType = "reg";
13462}
13463def L4_ploadruht_abs : HInst<
13464(outs IntRegs:$Rd32),
13465(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13466"if ($Pt4) $Rd32 = memuh(#$Ii)",
13467tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13468let Inst{7-5} = 0b100;
13469let Inst{13-11} = 0b100;
13470let Inst{31-21} = 0b10011111011;
13471let isPredicated = 1;
13472let hasNewValue = 1;
13473let opNewValue = 0;
13474let addrMode = Absolute;
13475let accessSize = HalfWordAccess;
13476let mayLoad = 1;
13477let isExtended = 1;
13478let BaseOpcode = "L4_loadruh_abs";
13479let CextOpcode = "L2_loadruh";
13480let DecoderNamespace = "MustExtend";
13481let isExtendable = 1;
13482let opExtendable = 2;
13483let isExtentSigned = 0;
13484let opExtentBits = 6;
13485let opExtentAlign = 0;
13486}
13487def L4_ploadruht_rr : HInst<
13488(outs IntRegs:$Rd32),
13489(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13490"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13491tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13492let Inst{31-21} = 0b00110000011;
13493let isPredicated = 1;
13494let hasNewValue = 1;
13495let opNewValue = 0;
13496let addrMode = BaseRegOffset;
13497let accessSize = HalfWordAccess;
13498let mayLoad = 1;
13499let BaseOpcode = "L4_loadruh_rr";
13500let CextOpcode = "L2_loadruh";
13501let InputType = "reg";
13502}
13503def L4_ploadruhtnew_abs : HInst<
13504(outs IntRegs:$Rd32),
13505(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13506"if ($Pt4.new) $Rd32 = memuh(#$Ii)",
13507tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13508let Inst{7-5} = 0b100;
13509let Inst{13-11} = 0b110;
13510let Inst{31-21} = 0b10011111011;
13511let isPredicated = 1;
13512let hasNewValue = 1;
13513let opNewValue = 0;
13514let addrMode = Absolute;
13515let accessSize = HalfWordAccess;
13516let isPredicatedNew = 1;
13517let mayLoad = 1;
13518let isExtended = 1;
13519let BaseOpcode = "L4_loadruh_abs";
13520let CextOpcode = "L2_loadruh";
13521let DecoderNamespace = "MustExtend";
13522let isExtendable = 1;
13523let opExtendable = 2;
13524let isExtentSigned = 0;
13525let opExtentBits = 6;
13526let opExtentAlign = 0;
13527}
13528def L4_ploadruhtnew_rr : HInst<
13529(outs IntRegs:$Rd32),
13530(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13531"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13532tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13533let Inst{31-21} = 0b00110010011;
13534let isPredicated = 1;
13535let hasNewValue = 1;
13536let opNewValue = 0;
13537let addrMode = BaseRegOffset;
13538let accessSize = HalfWordAccess;
13539let isPredicatedNew = 1;
13540let mayLoad = 1;
13541let BaseOpcode = "L4_loadruh_rr";
13542let CextOpcode = "L2_loadruh";
13543let InputType = "reg";
13544}
13545def L4_return : HInst<
13546(outs DoubleRegs:$Rdd32),
13547(ins IntRegs:$Rs32),
13548"$Rdd32 = dealloc_return($Rs32):raw",
13549tc_40d64c94, TypeLD>, Enc_3a3d62, PredNewRel {
13550let Inst{13-5} = 0b000000000;
13551let Inst{31-21} = 0b10010110000;
13552let isTerminator = 1;
13553let isIndirectBranch = 1;
13554let accessSize = DoubleWordAccess;
13555let mayLoad = 1;
13556let cofMax1 = 1;
13557let isRestrictNoSlot1Store = 1;
13558let isReturn = 1;
13559let Uses = [FRAMEKEY];
13560let Defs = [PC, R29];
13561let BaseOpcode = "L4_return";
13562let isBarrier = 1;
13563let isPredicable = 1;
13564let isTaken = 1;
13565}
13566def L4_return_f : HInst<
13567(outs DoubleRegs:$Rdd32),
13568(ins PredRegs:$Pv4, IntRegs:$Rs32),
13569"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13570tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13571let Inst{7-5} = 0b000;
13572let Inst{13-10} = 0b1100;
13573let Inst{31-21} = 0b10010110000;
13574let isPredicated = 1;
13575let isPredicatedFalse = 1;
13576let isTerminator = 1;
13577let isIndirectBranch = 1;
13578let accessSize = DoubleWordAccess;
13579let mayLoad = 1;
13580let cofMax1 = 1;
13581let isRestrictNoSlot1Store = 1;
13582let isReturn = 1;
13583let Uses = [FRAMEKEY];
13584let Defs = [PC, R29];
13585let BaseOpcode = "L4_return";
13586let isTaken = Inst{12};
13587}
13588def L4_return_fnew_pnt : HInst<
13589(outs DoubleRegs:$Rdd32),
13590(ins PredRegs:$Pv4, IntRegs:$Rs32),
13591"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13592tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13593let Inst{7-5} = 0b000;
13594let Inst{13-10} = 0b1010;
13595let Inst{31-21} = 0b10010110000;
13596let isPredicated = 1;
13597let isPredicatedFalse = 1;
13598let isTerminator = 1;
13599let isIndirectBranch = 1;
13600let accessSize = DoubleWordAccess;
13601let isPredicatedNew = 1;
13602let mayLoad = 1;
13603let cofMax1 = 1;
13604let isRestrictNoSlot1Store = 1;
13605let isReturn = 1;
13606let Uses = [FRAMEKEY];
13607let Defs = [PC, R29];
13608let BaseOpcode = "L4_return";
13609let isTaken = Inst{12};
13610}
13611def L4_return_fnew_pt : HInst<
13612(outs DoubleRegs:$Rdd32),
13613(ins PredRegs:$Pv4, IntRegs:$Rs32),
13614"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13615tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13616let Inst{7-5} = 0b000;
13617let Inst{13-10} = 0b1110;
13618let Inst{31-21} = 0b10010110000;
13619let isPredicated = 1;
13620let isPredicatedFalse = 1;
13621let isTerminator = 1;
13622let isIndirectBranch = 1;
13623let accessSize = DoubleWordAccess;
13624let isPredicatedNew = 1;
13625let mayLoad = 1;
13626let cofMax1 = 1;
13627let isRestrictNoSlot1Store = 1;
13628let isReturn = 1;
13629let Uses = [FRAMEKEY];
13630let Defs = [PC, R29];
13631let BaseOpcode = "L4_return";
13632let isTaken = Inst{12};
13633}
13634def L4_return_map_to_raw_f : HInst<
13635(outs),
13636(ins PredRegs:$Pv4),
13637"if (!$Pv4) dealloc_return",
13638tc_df5d53f9, TypeMAPPING>, Requires<[HasV65]> {
13639let isPseudo = 1;
13640let isCodeGenOnly = 1;
13641}
13642def L4_return_map_to_raw_fnew_pnt : HInst<
13643(outs),
13644(ins PredRegs:$Pv4),
13645"if (!$Pv4.new) dealloc_return:nt",
13646tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13647let isPseudo = 1;
13648let isCodeGenOnly = 1;
13649}
13650def L4_return_map_to_raw_fnew_pt : HInst<
13651(outs),
13652(ins PredRegs:$Pv4),
13653"if (!$Pv4.new) dealloc_return:t",
13654tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13655let isPseudo = 1;
13656let isCodeGenOnly = 1;
13657}
13658def L4_return_map_to_raw_t : HInst<
13659(outs),
13660(ins PredRegs:$Pv4),
13661"if ($Pv4) dealloc_return",
13662tc_f38f92e1, TypeMAPPING>, Requires<[HasV65]> {
13663let isPseudo = 1;
13664let isCodeGenOnly = 1;
13665}
13666def L4_return_map_to_raw_tnew_pnt : HInst<
13667(outs),
13668(ins PredRegs:$Pv4),
13669"if ($Pv4.new) dealloc_return:nt",
13670tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13671let isPseudo = 1;
13672let isCodeGenOnly = 1;
13673}
13674def L4_return_map_to_raw_tnew_pt : HInst<
13675(outs),
13676(ins PredRegs:$Pv4),
13677"if ($Pv4.new) dealloc_return:t",
13678tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13679let isPseudo = 1;
13680let isCodeGenOnly = 1;
13681}
13682def L4_return_t : HInst<
13683(outs DoubleRegs:$Rdd32),
13684(ins PredRegs:$Pv4, IntRegs:$Rs32),
13685"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13686tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13687let Inst{7-5} = 0b000;
13688let Inst{13-10} = 0b0100;
13689let Inst{31-21} = 0b10010110000;
13690let isPredicated = 1;
13691let isTerminator = 1;
13692let isIndirectBranch = 1;
13693let accessSize = DoubleWordAccess;
13694let mayLoad = 1;
13695let cofMax1 = 1;
13696let isRestrictNoSlot1Store = 1;
13697let isReturn = 1;
13698let Uses = [FRAMEKEY];
13699let Defs = [PC, R29];
13700let BaseOpcode = "L4_return";
13701let isTaken = Inst{12};
13702}
13703def L4_return_tnew_pnt : HInst<
13704(outs DoubleRegs:$Rdd32),
13705(ins PredRegs:$Pv4, IntRegs:$Rs32),
13706"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13707tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13708let Inst{7-5} = 0b000;
13709let Inst{13-10} = 0b0010;
13710let Inst{31-21} = 0b10010110000;
13711let isPredicated = 1;
13712let isTerminator = 1;
13713let isIndirectBranch = 1;
13714let accessSize = DoubleWordAccess;
13715let isPredicatedNew = 1;
13716let mayLoad = 1;
13717let cofMax1 = 1;
13718let isRestrictNoSlot1Store = 1;
13719let isReturn = 1;
13720let Uses = [FRAMEKEY];
13721let Defs = [PC, R29];
13722let BaseOpcode = "L4_return";
13723let isTaken = Inst{12};
13724}
13725def L4_return_tnew_pt : HInst<
13726(outs DoubleRegs:$Rdd32),
13727(ins PredRegs:$Pv4, IntRegs:$Rs32),
13728"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13729tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13730let Inst{7-5} = 0b000;
13731let Inst{13-10} = 0b0110;
13732let Inst{31-21} = 0b10010110000;
13733let isPredicated = 1;
13734let isTerminator = 1;
13735let isIndirectBranch = 1;
13736let accessSize = DoubleWordAccess;
13737let isPredicatedNew = 1;
13738let mayLoad = 1;
13739let cofMax1 = 1;
13740let isRestrictNoSlot1Store = 1;
13741let isReturn = 1;
13742let Uses = [FRAMEKEY];
13743let Defs = [PC, R29];
13744let BaseOpcode = "L4_return";
13745let isTaken = Inst{12};
13746}
13747def L4_sub_memopb_io : HInst<
13748(outs),
13749(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
13750"memb($Rs32+#$Ii) -= $Rt32",
13751tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
13752let Inst{6-5} = 0b01;
13753let Inst{13-13} = 0b0;
13754let Inst{31-21} = 0b00111110000;
13755let addrMode = BaseImmOffset;
13756let accessSize = ByteAccess;
13757let mayLoad = 1;
13758let isRestrictNoSlot1Store = 1;
13759let mayStore = 1;
13760let isExtendable = 1;
13761let opExtendable = 1;
13762let isExtentSigned = 0;
13763let opExtentBits = 6;
13764let opExtentAlign = 0;
13765}
13766def L4_sub_memopb_zomap : HInst<
13767(outs),
13768(ins IntRegs:$Rs32, IntRegs:$Rt32),
13769"memb($Rs32) -= $Rt32",
13770tc_9bcfb2ee, TypeMAPPING> {
13771let isPseudo = 1;
13772let isCodeGenOnly = 1;
13773}
13774def L4_sub_memoph_io : HInst<
13775(outs),
13776(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
13777"memh($Rs32+#$Ii) -= $Rt32",
13778tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
13779let Inst{6-5} = 0b01;
13780let Inst{13-13} = 0b0;
13781let Inst{31-21} = 0b00111110001;
13782let addrMode = BaseImmOffset;
13783let accessSize = HalfWordAccess;
13784let mayLoad = 1;
13785let isRestrictNoSlot1Store = 1;
13786let mayStore = 1;
13787let isExtendable = 1;
13788let opExtendable = 1;
13789let isExtentSigned = 0;
13790let opExtentBits = 7;
13791let opExtentAlign = 1;
13792}
13793def L4_sub_memoph_zomap : HInst<
13794(outs),
13795(ins IntRegs:$Rs32, IntRegs:$Rt32),
13796"memh($Rs32) -= $Rt32",
13797tc_9bcfb2ee, TypeMAPPING> {
13798let isPseudo = 1;
13799let isCodeGenOnly = 1;
13800}
13801def L4_sub_memopw_io : HInst<
13802(outs),
13803(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
13804"memw($Rs32+#$Ii) -= $Rt32",
13805tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
13806let Inst{6-5} = 0b01;
13807let Inst{13-13} = 0b0;
13808let Inst{31-21} = 0b00111110010;
13809let addrMode = BaseImmOffset;
13810let accessSize = WordAccess;
13811let mayLoad = 1;
13812let isRestrictNoSlot1Store = 1;
13813let mayStore = 1;
13814let isExtendable = 1;
13815let opExtendable = 1;
13816let isExtentSigned = 0;
13817let opExtentBits = 8;
13818let opExtentAlign = 2;
13819}
13820def L4_sub_memopw_zomap : HInst<
13821(outs),
13822(ins IntRegs:$Rs32, IntRegs:$Rt32),
13823"memw($Rs32) -= $Rt32",
13824tc_9bcfb2ee, TypeMAPPING> {
13825let isPseudo = 1;
13826let isCodeGenOnly = 1;
13827}
13828def L6_deallocframe_map_to_raw : HInst<
13829(outs),
13830(ins),
13831"deallocframe",
13832tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> {
13833let isPseudo = 1;
13834let isCodeGenOnly = 1;
13835}
13836def L6_memcpy : HInst<
13837(outs),
13838(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
13839"memcpy($Rs32,$Rt32,$Mu2)",
13840tc_5944960d, TypeLD>, Enc_a75aa6, Requires<[HasV66]> {
13841let Inst{7-0} = 0b01000000;
13842let Inst{31-21} = 0b10010010000;
13843let mayLoad = 1;
13844let isSolo = 1;
13845let mayStore = 1;
13846}
13847def L6_return_map_to_raw : HInst<
13848(outs),
13849(ins),
13850"dealloc_return",
13851tc_40d64c94, TypeMAPPING>, Requires<[HasV65]> {
13852let isPseudo = 1;
13853let isCodeGenOnly = 1;
13854}
13855def M2_acci : HInst<
13856(outs IntRegs:$Rx32),
13857(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13858"$Rx32 += add($Rs32,$Rt32)",
13859tc_2c13e7f5, TypeM>, Enc_2ae154, ImmRegRel {
13860let Inst{7-5} = 0b001;
13861let Inst{13-13} = 0b0;
13862let Inst{31-21} = 0b11101111000;
13863let hasNewValue = 1;
13864let opNewValue = 0;
13865let prefersSlot3 = 1;
13866let CextOpcode = "M2_acci";
13867let InputType = "reg";
13868let Constraints = "$Rx32 = $Rx32in";
13869}
13870def M2_accii : HInst<
13871(outs IntRegs:$Rx32),
13872(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
13873"$Rx32 += add($Rs32,#$Ii)",
13874tc_2c13e7f5, TypeM>, Enc_c90aca, ImmRegRel {
13875let Inst{13-13} = 0b0;
13876let Inst{31-21} = 0b11100010000;
13877let hasNewValue = 1;
13878let opNewValue = 0;
13879let prefersSlot3 = 1;
13880let CextOpcode = "M2_acci";
13881let InputType = "imm";
13882let isExtendable = 1;
13883let opExtendable = 3;
13884let isExtentSigned = 1;
13885let opExtentBits = 8;
13886let opExtentAlign = 0;
13887let Constraints = "$Rx32 = $Rx32in";
13888}
13889def M2_cmaci_s0 : HInst<
13890(outs DoubleRegs:$Rxx32),
13891(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13892"$Rxx32 += cmpyi($Rs32,$Rt32)",
13893tc_7f8ae742, TypeM>, Enc_61f0b0 {
13894let Inst{7-5} = 0b001;
13895let Inst{13-13} = 0b0;
13896let Inst{31-21} = 0b11100111000;
13897let prefersSlot3 = 1;
13898let Constraints = "$Rxx32 = $Rxx32in";
13899}
13900def M2_cmacr_s0 : HInst<
13901(outs DoubleRegs:$Rxx32),
13902(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13903"$Rxx32 += cmpyr($Rs32,$Rt32)",
13904tc_7f8ae742, TypeM>, Enc_61f0b0 {
13905let Inst{7-5} = 0b010;
13906let Inst{13-13} = 0b0;
13907let Inst{31-21} = 0b11100111000;
13908let prefersSlot3 = 1;
13909let Constraints = "$Rxx32 = $Rxx32in";
13910}
13911def M2_cmacs_s0 : HInst<
13912(outs DoubleRegs:$Rxx32),
13913(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13914"$Rxx32 += cmpy($Rs32,$Rt32):sat",
13915tc_7f8ae742, TypeM>, Enc_61f0b0 {
13916let Inst{7-5} = 0b110;
13917let Inst{13-13} = 0b0;
13918let Inst{31-21} = 0b11100111000;
13919let prefersSlot3 = 1;
13920let Defs = [USR_OVF];
13921let Constraints = "$Rxx32 = $Rxx32in";
13922}
13923def M2_cmacs_s1 : HInst<
13924(outs DoubleRegs:$Rxx32),
13925(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13926"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
13927tc_7f8ae742, TypeM>, Enc_61f0b0 {
13928let Inst{7-5} = 0b110;
13929let Inst{13-13} = 0b0;
13930let Inst{31-21} = 0b11100111100;
13931let prefersSlot3 = 1;
13932let Defs = [USR_OVF];
13933let Constraints = "$Rxx32 = $Rxx32in";
13934}
13935def M2_cmacsc_s0 : HInst<
13936(outs DoubleRegs:$Rxx32),
13937(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13938"$Rxx32 += cmpy($Rs32,$Rt32*):sat",
13939tc_7f8ae742, TypeM>, Enc_61f0b0 {
13940let Inst{7-5} = 0b110;
13941let Inst{13-13} = 0b0;
13942let Inst{31-21} = 0b11100111010;
13943let prefersSlot3 = 1;
13944let Defs = [USR_OVF];
13945let Constraints = "$Rxx32 = $Rxx32in";
13946}
13947def M2_cmacsc_s1 : HInst<
13948(outs DoubleRegs:$Rxx32),
13949(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13950"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
13951tc_7f8ae742, TypeM>, Enc_61f0b0 {
13952let Inst{7-5} = 0b110;
13953let Inst{13-13} = 0b0;
13954let Inst{31-21} = 0b11100111110;
13955let prefersSlot3 = 1;
13956let Defs = [USR_OVF];
13957let Constraints = "$Rxx32 = $Rxx32in";
13958}
13959def M2_cmpyi_s0 : HInst<
13960(outs DoubleRegs:$Rdd32),
13961(ins IntRegs:$Rs32, IntRegs:$Rt32),
13962"$Rdd32 = cmpyi($Rs32,$Rt32)",
13963tc_c21d7447, TypeM>, Enc_be32a5 {
13964let Inst{7-5} = 0b001;
13965let Inst{13-13} = 0b0;
13966let Inst{31-21} = 0b11100101000;
13967let prefersSlot3 = 1;
13968}
13969def M2_cmpyr_s0 : HInst<
13970(outs DoubleRegs:$Rdd32),
13971(ins IntRegs:$Rs32, IntRegs:$Rt32),
13972"$Rdd32 = cmpyr($Rs32,$Rt32)",
13973tc_c21d7447, TypeM>, Enc_be32a5 {
13974let Inst{7-5} = 0b010;
13975let Inst{13-13} = 0b0;
13976let Inst{31-21} = 0b11100101000;
13977let prefersSlot3 = 1;
13978}
13979def M2_cmpyrs_s0 : HInst<
13980(outs IntRegs:$Rd32),
13981(ins IntRegs:$Rs32, IntRegs:$Rt32),
13982"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
13983tc_c21d7447, TypeM>, Enc_5ab2be {
13984let Inst{7-5} = 0b110;
13985let Inst{13-13} = 0b0;
13986let Inst{31-21} = 0b11101101001;
13987let hasNewValue = 1;
13988let opNewValue = 0;
13989let prefersSlot3 = 1;
13990let Defs = [USR_OVF];
13991}
13992def M2_cmpyrs_s1 : HInst<
13993(outs IntRegs:$Rd32),
13994(ins IntRegs:$Rs32, IntRegs:$Rt32),
13995"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
13996tc_c21d7447, TypeM>, Enc_5ab2be {
13997let Inst{7-5} = 0b110;
13998let Inst{13-13} = 0b0;
13999let Inst{31-21} = 0b11101101101;
14000let hasNewValue = 1;
14001let opNewValue = 0;
14002let prefersSlot3 = 1;
14003let Defs = [USR_OVF];
14004}
14005def M2_cmpyrsc_s0 : HInst<
14006(outs IntRegs:$Rd32),
14007(ins IntRegs:$Rs32, IntRegs:$Rt32),
14008"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
14009tc_c21d7447, TypeM>, Enc_5ab2be {
14010let Inst{7-5} = 0b110;
14011let Inst{13-13} = 0b0;
14012let Inst{31-21} = 0b11101101011;
14013let hasNewValue = 1;
14014let opNewValue = 0;
14015let prefersSlot3 = 1;
14016let Defs = [USR_OVF];
14017}
14018def M2_cmpyrsc_s1 : HInst<
14019(outs IntRegs:$Rd32),
14020(ins IntRegs:$Rs32, IntRegs:$Rt32),
14021"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
14022tc_c21d7447, TypeM>, Enc_5ab2be {
14023let Inst{7-5} = 0b110;
14024let Inst{13-13} = 0b0;
14025let Inst{31-21} = 0b11101101111;
14026let hasNewValue = 1;
14027let opNewValue = 0;
14028let prefersSlot3 = 1;
14029let Defs = [USR_OVF];
14030}
14031def M2_cmpys_s0 : HInst<
14032(outs DoubleRegs:$Rdd32),
14033(ins IntRegs:$Rs32, IntRegs:$Rt32),
14034"$Rdd32 = cmpy($Rs32,$Rt32):sat",
14035tc_c21d7447, TypeM>, Enc_be32a5 {
14036let Inst{7-5} = 0b110;
14037let Inst{13-13} = 0b0;
14038let Inst{31-21} = 0b11100101000;
14039let prefersSlot3 = 1;
14040let Defs = [USR_OVF];
14041}
14042def M2_cmpys_s1 : HInst<
14043(outs DoubleRegs:$Rdd32),
14044(ins IntRegs:$Rs32, IntRegs:$Rt32),
14045"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
14046tc_c21d7447, TypeM>, Enc_be32a5 {
14047let Inst{7-5} = 0b110;
14048let Inst{13-13} = 0b0;
14049let Inst{31-21} = 0b11100101100;
14050let prefersSlot3 = 1;
14051let Defs = [USR_OVF];
14052}
14053def M2_cmpysc_s0 : HInst<
14054(outs DoubleRegs:$Rdd32),
14055(ins IntRegs:$Rs32, IntRegs:$Rt32),
14056"$Rdd32 = cmpy($Rs32,$Rt32*):sat",
14057tc_c21d7447, TypeM>, Enc_be32a5 {
14058let Inst{7-5} = 0b110;
14059let Inst{13-13} = 0b0;
14060let Inst{31-21} = 0b11100101010;
14061let prefersSlot3 = 1;
14062let Defs = [USR_OVF];
14063}
14064def M2_cmpysc_s1 : HInst<
14065(outs DoubleRegs:$Rdd32),
14066(ins IntRegs:$Rs32, IntRegs:$Rt32),
14067"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
14068tc_c21d7447, TypeM>, Enc_be32a5 {
14069let Inst{7-5} = 0b110;
14070let Inst{13-13} = 0b0;
14071let Inst{31-21} = 0b11100101110;
14072let prefersSlot3 = 1;
14073let Defs = [USR_OVF];
14074}
14075def M2_cnacs_s0 : HInst<
14076(outs DoubleRegs:$Rxx32),
14077(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14078"$Rxx32 -= cmpy($Rs32,$Rt32):sat",
14079tc_7f8ae742, TypeM>, Enc_61f0b0 {
14080let Inst{7-5} = 0b111;
14081let Inst{13-13} = 0b0;
14082let Inst{31-21} = 0b11100111000;
14083let prefersSlot3 = 1;
14084let Defs = [USR_OVF];
14085let Constraints = "$Rxx32 = $Rxx32in";
14086}
14087def M2_cnacs_s1 : HInst<
14088(outs DoubleRegs:$Rxx32),
14089(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14090"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
14091tc_7f8ae742, TypeM>, Enc_61f0b0 {
14092let Inst{7-5} = 0b111;
14093let Inst{13-13} = 0b0;
14094let Inst{31-21} = 0b11100111100;
14095let prefersSlot3 = 1;
14096let Defs = [USR_OVF];
14097let Constraints = "$Rxx32 = $Rxx32in";
14098}
14099def M2_cnacsc_s0 : HInst<
14100(outs DoubleRegs:$Rxx32),
14101(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14102"$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
14103tc_7f8ae742, TypeM>, Enc_61f0b0 {
14104let Inst{7-5} = 0b111;
14105let Inst{13-13} = 0b0;
14106let Inst{31-21} = 0b11100111010;
14107let prefersSlot3 = 1;
14108let Defs = [USR_OVF];
14109let Constraints = "$Rxx32 = $Rxx32in";
14110}
14111def M2_cnacsc_s1 : HInst<
14112(outs DoubleRegs:$Rxx32),
14113(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14114"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
14115tc_7f8ae742, TypeM>, Enc_61f0b0 {
14116let Inst{7-5} = 0b111;
14117let Inst{13-13} = 0b0;
14118let Inst{31-21} = 0b11100111110;
14119let prefersSlot3 = 1;
14120let Defs = [USR_OVF];
14121let Constraints = "$Rxx32 = $Rxx32in";
14122}
14123def M2_dpmpyss_acc_s0 : HInst<
14124(outs DoubleRegs:$Rxx32),
14125(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14126"$Rxx32 += mpy($Rs32,$Rt32)",
14127tc_7f8ae742, TypeM>, Enc_61f0b0 {
14128let Inst{7-5} = 0b000;
14129let Inst{13-13} = 0b0;
14130let Inst{31-21} = 0b11100111000;
14131let prefersSlot3 = 1;
14132let Constraints = "$Rxx32 = $Rxx32in";
14133}
14134def M2_dpmpyss_nac_s0 : HInst<
14135(outs DoubleRegs:$Rxx32),
14136(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14137"$Rxx32 -= mpy($Rs32,$Rt32)",
14138tc_7f8ae742, TypeM>, Enc_61f0b0 {
14139let Inst{7-5} = 0b000;
14140let Inst{13-13} = 0b0;
14141let Inst{31-21} = 0b11100111001;
14142let prefersSlot3 = 1;
14143let Constraints = "$Rxx32 = $Rxx32in";
14144}
14145def M2_dpmpyss_rnd_s0 : HInst<
14146(outs IntRegs:$Rd32),
14147(ins IntRegs:$Rs32, IntRegs:$Rt32),
14148"$Rd32 = mpy($Rs32,$Rt32):rnd",
14149tc_c21d7447, TypeM>, Enc_5ab2be {
14150let Inst{7-5} = 0b001;
14151let Inst{13-13} = 0b0;
14152let Inst{31-21} = 0b11101101001;
14153let hasNewValue = 1;
14154let opNewValue = 0;
14155let prefersSlot3 = 1;
14156}
14157def M2_dpmpyss_s0 : HInst<
14158(outs DoubleRegs:$Rdd32),
14159(ins IntRegs:$Rs32, IntRegs:$Rt32),
14160"$Rdd32 = mpy($Rs32,$Rt32)",
14161tc_c21d7447, TypeM>, Enc_be32a5 {
14162let Inst{7-5} = 0b000;
14163let Inst{13-13} = 0b0;
14164let Inst{31-21} = 0b11100101000;
14165let prefersSlot3 = 1;
14166}
14167def M2_dpmpyuu_acc_s0 : HInst<
14168(outs DoubleRegs:$Rxx32),
14169(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14170"$Rxx32 += mpyu($Rs32,$Rt32)",
14171tc_7f8ae742, TypeM>, Enc_61f0b0 {
14172let Inst{7-5} = 0b000;
14173let Inst{13-13} = 0b0;
14174let Inst{31-21} = 0b11100111010;
14175let prefersSlot3 = 1;
14176let Constraints = "$Rxx32 = $Rxx32in";
14177}
14178def M2_dpmpyuu_nac_s0 : HInst<
14179(outs DoubleRegs:$Rxx32),
14180(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14181"$Rxx32 -= mpyu($Rs32,$Rt32)",
14182tc_7f8ae742, TypeM>, Enc_61f0b0 {
14183let Inst{7-5} = 0b000;
14184let Inst{13-13} = 0b0;
14185let Inst{31-21} = 0b11100111011;
14186let prefersSlot3 = 1;
14187let Constraints = "$Rxx32 = $Rxx32in";
14188}
14189def M2_dpmpyuu_s0 : HInst<
14190(outs DoubleRegs:$Rdd32),
14191(ins IntRegs:$Rs32, IntRegs:$Rt32),
14192"$Rdd32 = mpyu($Rs32,$Rt32)",
14193tc_c21d7447, TypeM>, Enc_be32a5 {
14194let Inst{7-5} = 0b000;
14195let Inst{13-13} = 0b0;
14196let Inst{31-21} = 0b11100101010;
14197let prefersSlot3 = 1;
14198}
14199def M2_hmmpyh_rs1 : HInst<
14200(outs IntRegs:$Rd32),
14201(ins IntRegs:$Rs32, IntRegs:$Rt32),
14202"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
14203tc_c21d7447, TypeM>, Enc_5ab2be {
14204let Inst{7-5} = 0b100;
14205let Inst{13-13} = 0b0;
14206let Inst{31-21} = 0b11101101101;
14207let hasNewValue = 1;
14208let opNewValue = 0;
14209let prefersSlot3 = 1;
14210let Defs = [USR_OVF];
14211}
14212def M2_hmmpyh_s1 : HInst<
14213(outs IntRegs:$Rd32),
14214(ins IntRegs:$Rs32, IntRegs:$Rt32),
14215"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
14216tc_c21d7447, TypeM>, Enc_5ab2be {
14217let Inst{7-5} = 0b000;
14218let Inst{13-13} = 0b0;
14219let Inst{31-21} = 0b11101101101;
14220let hasNewValue = 1;
14221let opNewValue = 0;
14222let prefersSlot3 = 1;
14223let Defs = [USR_OVF];
14224}
14225def M2_hmmpyl_rs1 : HInst<
14226(outs IntRegs:$Rd32),
14227(ins IntRegs:$Rs32, IntRegs:$Rt32),
14228"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
14229tc_c21d7447, TypeM>, Enc_5ab2be {
14230let Inst{7-5} = 0b100;
14231let Inst{13-13} = 0b0;
14232let Inst{31-21} = 0b11101101111;
14233let hasNewValue = 1;
14234let opNewValue = 0;
14235let prefersSlot3 = 1;
14236let Defs = [USR_OVF];
14237}
14238def M2_hmmpyl_s1 : HInst<
14239(outs IntRegs:$Rd32),
14240(ins IntRegs:$Rs32, IntRegs:$Rt32),
14241"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
14242tc_c21d7447, TypeM>, Enc_5ab2be {
14243let Inst{7-5} = 0b001;
14244let Inst{13-13} = 0b0;
14245let Inst{31-21} = 0b11101101101;
14246let hasNewValue = 1;
14247let opNewValue = 0;
14248let prefersSlot3 = 1;
14249let Defs = [USR_OVF];
14250}
14251def M2_maci : HInst<
14252(outs IntRegs:$Rx32),
14253(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14254"$Rx32 += mpyi($Rs32,$Rt32)",
14255tc_7f8ae742, TypeM>, Enc_2ae154, ImmRegRel {
14256let Inst{7-5} = 0b000;
14257let Inst{13-13} = 0b0;
14258let Inst{31-21} = 0b11101111000;
14259let hasNewValue = 1;
14260let opNewValue = 0;
14261let prefersSlot3 = 1;
14262let CextOpcode = "M2_maci";
14263let InputType = "reg";
14264let Constraints = "$Rx32 = $Rx32in";
14265}
14266def M2_macsin : HInst<
14267(outs IntRegs:$Rx32),
14268(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14269"$Rx32 -= mpyi($Rs32,#$Ii)",
14270tc_a154b476, TypeM>, Enc_c90aca {
14271let Inst{13-13} = 0b0;
14272let Inst{31-21} = 0b11100001100;
14273let hasNewValue = 1;
14274let opNewValue = 0;
14275let prefersSlot3 = 1;
14276let InputType = "imm";
14277let isExtendable = 1;
14278let opExtendable = 3;
14279let isExtentSigned = 0;
14280let opExtentBits = 8;
14281let opExtentAlign = 0;
14282let Constraints = "$Rx32 = $Rx32in";
14283}
14284def M2_macsip : HInst<
14285(outs IntRegs:$Rx32),
14286(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14287"$Rx32 += mpyi($Rs32,#$Ii)",
14288tc_a154b476, TypeM>, Enc_c90aca, ImmRegRel {
14289let Inst{13-13} = 0b0;
14290let Inst{31-21} = 0b11100001000;
14291let hasNewValue = 1;
14292let opNewValue = 0;
14293let prefersSlot3 = 1;
14294let CextOpcode = "M2_maci";
14295let InputType = "imm";
14296let isExtendable = 1;
14297let opExtendable = 3;
14298let isExtentSigned = 0;
14299let opExtentBits = 8;
14300let opExtentAlign = 0;
14301let Constraints = "$Rx32 = $Rx32in";
14302}
14303def M2_mmachs_rs0 : HInst<
14304(outs DoubleRegs:$Rxx32),
14305(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14306"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
14307tc_7f8ae742, TypeM>, Enc_88c16c {
14308let Inst{7-5} = 0b111;
14309let Inst{13-13} = 0b0;
14310let Inst{31-21} = 0b11101010001;
14311let prefersSlot3 = 1;
14312let Defs = [USR_OVF];
14313let Constraints = "$Rxx32 = $Rxx32in";
14314}
14315def M2_mmachs_rs1 : HInst<
14316(outs DoubleRegs:$Rxx32),
14317(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14318"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14319tc_7f8ae742, TypeM>, Enc_88c16c {
14320let Inst{7-5} = 0b111;
14321let Inst{13-13} = 0b0;
14322let Inst{31-21} = 0b11101010101;
14323let prefersSlot3 = 1;
14324let Defs = [USR_OVF];
14325let Constraints = "$Rxx32 = $Rxx32in";
14326}
14327def M2_mmachs_s0 : HInst<
14328(outs DoubleRegs:$Rxx32),
14329(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14330"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
14331tc_7f8ae742, TypeM>, Enc_88c16c {
14332let Inst{7-5} = 0b111;
14333let Inst{13-13} = 0b0;
14334let Inst{31-21} = 0b11101010000;
14335let prefersSlot3 = 1;
14336let Defs = [USR_OVF];
14337let Constraints = "$Rxx32 = $Rxx32in";
14338}
14339def M2_mmachs_s1 : HInst<
14340(outs DoubleRegs:$Rxx32),
14341(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14342"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
14343tc_7f8ae742, TypeM>, Enc_88c16c {
14344let Inst{7-5} = 0b111;
14345let Inst{13-13} = 0b0;
14346let Inst{31-21} = 0b11101010100;
14347let prefersSlot3 = 1;
14348let Defs = [USR_OVF];
14349let Constraints = "$Rxx32 = $Rxx32in";
14350}
14351def M2_mmacls_rs0 : HInst<
14352(outs DoubleRegs:$Rxx32),
14353(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14354"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
14355tc_7f8ae742, TypeM>, Enc_88c16c {
14356let Inst{7-5} = 0b101;
14357let Inst{13-13} = 0b0;
14358let Inst{31-21} = 0b11101010001;
14359let prefersSlot3 = 1;
14360let Defs = [USR_OVF];
14361let Constraints = "$Rxx32 = $Rxx32in";
14362}
14363def M2_mmacls_rs1 : HInst<
14364(outs DoubleRegs:$Rxx32),
14365(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14366"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14367tc_7f8ae742, TypeM>, Enc_88c16c {
14368let Inst{7-5} = 0b101;
14369let Inst{13-13} = 0b0;
14370let Inst{31-21} = 0b11101010101;
14371let prefersSlot3 = 1;
14372let Defs = [USR_OVF];
14373let Constraints = "$Rxx32 = $Rxx32in";
14374}
14375def M2_mmacls_s0 : HInst<
14376(outs DoubleRegs:$Rxx32),
14377(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14378"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
14379tc_7f8ae742, TypeM>, Enc_88c16c {
14380let Inst{7-5} = 0b101;
14381let Inst{13-13} = 0b0;
14382let Inst{31-21} = 0b11101010000;
14383let prefersSlot3 = 1;
14384let Defs = [USR_OVF];
14385let Constraints = "$Rxx32 = $Rxx32in";
14386}
14387def M2_mmacls_s1 : HInst<
14388(outs DoubleRegs:$Rxx32),
14389(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14390"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
14391tc_7f8ae742, TypeM>, Enc_88c16c {
14392let Inst{7-5} = 0b101;
14393let Inst{13-13} = 0b0;
14394let Inst{31-21} = 0b11101010100;
14395let prefersSlot3 = 1;
14396let Defs = [USR_OVF];
14397let Constraints = "$Rxx32 = $Rxx32in";
14398}
14399def M2_mmacuhs_rs0 : HInst<
14400(outs DoubleRegs:$Rxx32),
14401(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14402"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
14403tc_7f8ae742, TypeM>, Enc_88c16c {
14404let Inst{7-5} = 0b111;
14405let Inst{13-13} = 0b0;
14406let Inst{31-21} = 0b11101010011;
14407let prefersSlot3 = 1;
14408let Defs = [USR_OVF];
14409let Constraints = "$Rxx32 = $Rxx32in";
14410}
14411def M2_mmacuhs_rs1 : HInst<
14412(outs DoubleRegs:$Rxx32),
14413(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14414"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14415tc_7f8ae742, TypeM>, Enc_88c16c {
14416let Inst{7-5} = 0b111;
14417let Inst{13-13} = 0b0;
14418let Inst{31-21} = 0b11101010111;
14419let prefersSlot3 = 1;
14420let Defs = [USR_OVF];
14421let Constraints = "$Rxx32 = $Rxx32in";
14422}
14423def M2_mmacuhs_s0 : HInst<
14424(outs DoubleRegs:$Rxx32),
14425(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14426"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
14427tc_7f8ae742, TypeM>, Enc_88c16c {
14428let Inst{7-5} = 0b111;
14429let Inst{13-13} = 0b0;
14430let Inst{31-21} = 0b11101010010;
14431let prefersSlot3 = 1;
14432let Defs = [USR_OVF];
14433let Constraints = "$Rxx32 = $Rxx32in";
14434}
14435def M2_mmacuhs_s1 : HInst<
14436(outs DoubleRegs:$Rxx32),
14437(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14438"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
14439tc_7f8ae742, TypeM>, Enc_88c16c {
14440let Inst{7-5} = 0b111;
14441let Inst{13-13} = 0b0;
14442let Inst{31-21} = 0b11101010110;
14443let prefersSlot3 = 1;
14444let Defs = [USR_OVF];
14445let Constraints = "$Rxx32 = $Rxx32in";
14446}
14447def M2_mmaculs_rs0 : HInst<
14448(outs DoubleRegs:$Rxx32),
14449(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14450"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
14451tc_7f8ae742, TypeM>, Enc_88c16c {
14452let Inst{7-5} = 0b101;
14453let Inst{13-13} = 0b0;
14454let Inst{31-21} = 0b11101010011;
14455let prefersSlot3 = 1;
14456let Defs = [USR_OVF];
14457let Constraints = "$Rxx32 = $Rxx32in";
14458}
14459def M2_mmaculs_rs1 : HInst<
14460(outs DoubleRegs:$Rxx32),
14461(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14462"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14463tc_7f8ae742, TypeM>, Enc_88c16c {
14464let Inst{7-5} = 0b101;
14465let Inst{13-13} = 0b0;
14466let Inst{31-21} = 0b11101010111;
14467let prefersSlot3 = 1;
14468let Defs = [USR_OVF];
14469let Constraints = "$Rxx32 = $Rxx32in";
14470}
14471def M2_mmaculs_s0 : HInst<
14472(outs DoubleRegs:$Rxx32),
14473(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14474"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
14475tc_7f8ae742, TypeM>, Enc_88c16c {
14476let Inst{7-5} = 0b101;
14477let Inst{13-13} = 0b0;
14478let Inst{31-21} = 0b11101010010;
14479let prefersSlot3 = 1;
14480let Defs = [USR_OVF];
14481let Constraints = "$Rxx32 = $Rxx32in";
14482}
14483def M2_mmaculs_s1 : HInst<
14484(outs DoubleRegs:$Rxx32),
14485(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14486"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
14487tc_7f8ae742, TypeM>, Enc_88c16c {
14488let Inst{7-5} = 0b101;
14489let Inst{13-13} = 0b0;
14490let Inst{31-21} = 0b11101010110;
14491let prefersSlot3 = 1;
14492let Defs = [USR_OVF];
14493let Constraints = "$Rxx32 = $Rxx32in";
14494}
14495def M2_mmpyh_rs0 : HInst<
14496(outs DoubleRegs:$Rdd32),
14497(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14498"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
14499tc_c21d7447, TypeM>, Enc_a56825 {
14500let Inst{7-5} = 0b111;
14501let Inst{13-13} = 0b0;
14502let Inst{31-21} = 0b11101000001;
14503let prefersSlot3 = 1;
14504let Defs = [USR_OVF];
14505}
14506def M2_mmpyh_rs1 : HInst<
14507(outs DoubleRegs:$Rdd32),
14508(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14509"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14510tc_c21d7447, TypeM>, Enc_a56825 {
14511let Inst{7-5} = 0b111;
14512let Inst{13-13} = 0b0;
14513let Inst{31-21} = 0b11101000101;
14514let prefersSlot3 = 1;
14515let Defs = [USR_OVF];
14516}
14517def M2_mmpyh_s0 : HInst<
14518(outs DoubleRegs:$Rdd32),
14519(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14520"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
14521tc_c21d7447, TypeM>, Enc_a56825 {
14522let Inst{7-5} = 0b111;
14523let Inst{13-13} = 0b0;
14524let Inst{31-21} = 0b11101000000;
14525let prefersSlot3 = 1;
14526let Defs = [USR_OVF];
14527}
14528def M2_mmpyh_s1 : HInst<
14529(outs DoubleRegs:$Rdd32),
14530(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14531"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
14532tc_c21d7447, TypeM>, Enc_a56825 {
14533let Inst{7-5} = 0b111;
14534let Inst{13-13} = 0b0;
14535let Inst{31-21} = 0b11101000100;
14536let prefersSlot3 = 1;
14537let Defs = [USR_OVF];
14538}
14539def M2_mmpyl_rs0 : HInst<
14540(outs DoubleRegs:$Rdd32),
14541(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14542"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
14543tc_c21d7447, TypeM>, Enc_a56825 {
14544let Inst{7-5} = 0b101;
14545let Inst{13-13} = 0b0;
14546let Inst{31-21} = 0b11101000001;
14547let prefersSlot3 = 1;
14548let Defs = [USR_OVF];
14549}
14550def M2_mmpyl_rs1 : HInst<
14551(outs DoubleRegs:$Rdd32),
14552(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14553"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14554tc_c21d7447, TypeM>, Enc_a56825 {
14555let Inst{7-5} = 0b101;
14556let Inst{13-13} = 0b0;
14557let Inst{31-21} = 0b11101000101;
14558let prefersSlot3 = 1;
14559let Defs = [USR_OVF];
14560}
14561def M2_mmpyl_s0 : HInst<
14562(outs DoubleRegs:$Rdd32),
14563(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14564"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
14565tc_c21d7447, TypeM>, Enc_a56825 {
14566let Inst{7-5} = 0b101;
14567let Inst{13-13} = 0b0;
14568let Inst{31-21} = 0b11101000000;
14569let prefersSlot3 = 1;
14570let Defs = [USR_OVF];
14571}
14572def M2_mmpyl_s1 : HInst<
14573(outs DoubleRegs:$Rdd32),
14574(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14575"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
14576tc_c21d7447, TypeM>, Enc_a56825 {
14577let Inst{7-5} = 0b101;
14578let Inst{13-13} = 0b0;
14579let Inst{31-21} = 0b11101000100;
14580let prefersSlot3 = 1;
14581let Defs = [USR_OVF];
14582}
14583def M2_mmpyuh_rs0 : HInst<
14584(outs DoubleRegs:$Rdd32),
14585(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14586"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
14587tc_c21d7447, TypeM>, Enc_a56825 {
14588let Inst{7-5} = 0b111;
14589let Inst{13-13} = 0b0;
14590let Inst{31-21} = 0b11101000011;
14591let prefersSlot3 = 1;
14592let Defs = [USR_OVF];
14593}
14594def M2_mmpyuh_rs1 : HInst<
14595(outs DoubleRegs:$Rdd32),
14596(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14597"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14598tc_c21d7447, TypeM>, Enc_a56825 {
14599let Inst{7-5} = 0b111;
14600let Inst{13-13} = 0b0;
14601let Inst{31-21} = 0b11101000111;
14602let prefersSlot3 = 1;
14603let Defs = [USR_OVF];
14604}
14605def M2_mmpyuh_s0 : HInst<
14606(outs DoubleRegs:$Rdd32),
14607(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14608"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
14609tc_c21d7447, TypeM>, Enc_a56825 {
14610let Inst{7-5} = 0b111;
14611let Inst{13-13} = 0b0;
14612let Inst{31-21} = 0b11101000010;
14613let prefersSlot3 = 1;
14614let Defs = [USR_OVF];
14615}
14616def M2_mmpyuh_s1 : HInst<
14617(outs DoubleRegs:$Rdd32),
14618(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14619"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
14620tc_c21d7447, TypeM>, Enc_a56825 {
14621let Inst{7-5} = 0b111;
14622let Inst{13-13} = 0b0;
14623let Inst{31-21} = 0b11101000110;
14624let prefersSlot3 = 1;
14625let Defs = [USR_OVF];
14626}
14627def M2_mmpyul_rs0 : HInst<
14628(outs DoubleRegs:$Rdd32),
14629(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14630"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
14631tc_c21d7447, TypeM>, Enc_a56825 {
14632let Inst{7-5} = 0b101;
14633let Inst{13-13} = 0b0;
14634let Inst{31-21} = 0b11101000011;
14635let prefersSlot3 = 1;
14636let Defs = [USR_OVF];
14637}
14638def M2_mmpyul_rs1 : HInst<
14639(outs DoubleRegs:$Rdd32),
14640(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14641"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14642tc_c21d7447, TypeM>, Enc_a56825 {
14643let Inst{7-5} = 0b101;
14644let Inst{13-13} = 0b0;
14645let Inst{31-21} = 0b11101000111;
14646let prefersSlot3 = 1;
14647let Defs = [USR_OVF];
14648}
14649def M2_mmpyul_s0 : HInst<
14650(outs DoubleRegs:$Rdd32),
14651(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14652"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
14653tc_c21d7447, TypeM>, Enc_a56825 {
14654let Inst{7-5} = 0b101;
14655let Inst{13-13} = 0b0;
14656let Inst{31-21} = 0b11101000010;
14657let prefersSlot3 = 1;
14658let Defs = [USR_OVF];
14659}
14660def M2_mmpyul_s1 : HInst<
14661(outs DoubleRegs:$Rdd32),
14662(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14663"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
14664tc_c21d7447, TypeM>, Enc_a56825 {
14665let Inst{7-5} = 0b101;
14666let Inst{13-13} = 0b0;
14667let Inst{31-21} = 0b11101000110;
14668let prefersSlot3 = 1;
14669let Defs = [USR_OVF];
14670}
14671def M2_mnaci : HInst<
14672(outs IntRegs:$Rx32),
14673(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14674"$Rx32 -= mpyi($Rs32,$Rt32)",
14675tc_01e1be3b, TypeM>, Enc_2ae154, Requires<[HasV66]> {
14676let Inst{7-5} = 0b000;
14677let Inst{13-13} = 0b0;
14678let Inst{31-21} = 0b11101111100;
14679let hasNewValue = 1;
14680let opNewValue = 0;
14681let prefersSlot3 = 1;
14682let Constraints = "$Rx32 = $Rx32in";
14683}
14684def M2_mpy_acc_hh_s0 : HInst<
14685(outs IntRegs:$Rx32),
14686(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14687"$Rx32 += mpy($Rs32.h,$Rt32.h)",
14688tc_7f8ae742, TypeM>, Enc_2ae154 {
14689let Inst{7-5} = 0b011;
14690let Inst{13-13} = 0b0;
14691let Inst{31-21} = 0b11101110000;
14692let hasNewValue = 1;
14693let opNewValue = 0;
14694let prefersSlot3 = 1;
14695let Constraints = "$Rx32 = $Rx32in";
14696}
14697def M2_mpy_acc_hh_s1 : HInst<
14698(outs IntRegs:$Rx32),
14699(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14700"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
14701tc_7f8ae742, TypeM>, Enc_2ae154 {
14702let Inst{7-5} = 0b011;
14703let Inst{13-13} = 0b0;
14704let Inst{31-21} = 0b11101110100;
14705let hasNewValue = 1;
14706let opNewValue = 0;
14707let prefersSlot3 = 1;
14708let Constraints = "$Rx32 = $Rx32in";
14709}
14710def M2_mpy_acc_hl_s0 : HInst<
14711(outs IntRegs:$Rx32),
14712(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14713"$Rx32 += mpy($Rs32.h,$Rt32.l)",
14714tc_7f8ae742, TypeM>, Enc_2ae154 {
14715let Inst{7-5} = 0b010;
14716let Inst{13-13} = 0b0;
14717let Inst{31-21} = 0b11101110000;
14718let hasNewValue = 1;
14719let opNewValue = 0;
14720let prefersSlot3 = 1;
14721let Constraints = "$Rx32 = $Rx32in";
14722}
14723def M2_mpy_acc_hl_s1 : HInst<
14724(outs IntRegs:$Rx32),
14725(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14726"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
14727tc_7f8ae742, TypeM>, Enc_2ae154 {
14728let Inst{7-5} = 0b010;
14729let Inst{13-13} = 0b0;
14730let Inst{31-21} = 0b11101110100;
14731let hasNewValue = 1;
14732let opNewValue = 0;
14733let prefersSlot3 = 1;
14734let Constraints = "$Rx32 = $Rx32in";
14735}
14736def M2_mpy_acc_lh_s0 : HInst<
14737(outs IntRegs:$Rx32),
14738(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14739"$Rx32 += mpy($Rs32.l,$Rt32.h)",
14740tc_7f8ae742, TypeM>, Enc_2ae154 {
14741let Inst{7-5} = 0b001;
14742let Inst{13-13} = 0b0;
14743let Inst{31-21} = 0b11101110000;
14744let hasNewValue = 1;
14745let opNewValue = 0;
14746let prefersSlot3 = 1;
14747let Constraints = "$Rx32 = $Rx32in";
14748}
14749def M2_mpy_acc_lh_s1 : HInst<
14750(outs IntRegs:$Rx32),
14751(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14752"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
14753tc_7f8ae742, TypeM>, Enc_2ae154 {
14754let Inst{7-5} = 0b001;
14755let Inst{13-13} = 0b0;
14756let Inst{31-21} = 0b11101110100;
14757let hasNewValue = 1;
14758let opNewValue = 0;
14759let prefersSlot3 = 1;
14760let Constraints = "$Rx32 = $Rx32in";
14761}
14762def M2_mpy_acc_ll_s0 : HInst<
14763(outs IntRegs:$Rx32),
14764(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14765"$Rx32 += mpy($Rs32.l,$Rt32.l)",
14766tc_7f8ae742, TypeM>, Enc_2ae154 {
14767let Inst{7-5} = 0b000;
14768let Inst{13-13} = 0b0;
14769let Inst{31-21} = 0b11101110000;
14770let hasNewValue = 1;
14771let opNewValue = 0;
14772let prefersSlot3 = 1;
14773let Constraints = "$Rx32 = $Rx32in";
14774}
14775def M2_mpy_acc_ll_s1 : HInst<
14776(outs IntRegs:$Rx32),
14777(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14778"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
14779tc_7f8ae742, TypeM>, Enc_2ae154 {
14780let Inst{7-5} = 0b000;
14781let Inst{13-13} = 0b0;
14782let Inst{31-21} = 0b11101110100;
14783let hasNewValue = 1;
14784let opNewValue = 0;
14785let prefersSlot3 = 1;
14786let Constraints = "$Rx32 = $Rx32in";
14787}
14788def M2_mpy_acc_sat_hh_s0 : HInst<
14789(outs IntRegs:$Rx32),
14790(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14791"$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
14792tc_7f8ae742, TypeM>, Enc_2ae154 {
14793let Inst{7-5} = 0b111;
14794let Inst{13-13} = 0b0;
14795let Inst{31-21} = 0b11101110000;
14796let hasNewValue = 1;
14797let opNewValue = 0;
14798let prefersSlot3 = 1;
14799let Defs = [USR_OVF];
14800let Constraints = "$Rx32 = $Rx32in";
14801}
14802def M2_mpy_acc_sat_hh_s1 : HInst<
14803(outs IntRegs:$Rx32),
14804(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14805"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
14806tc_7f8ae742, TypeM>, Enc_2ae154 {
14807let Inst{7-5} = 0b111;
14808let Inst{13-13} = 0b0;
14809let Inst{31-21} = 0b11101110100;
14810let hasNewValue = 1;
14811let opNewValue = 0;
14812let prefersSlot3 = 1;
14813let Defs = [USR_OVF];
14814let Constraints = "$Rx32 = $Rx32in";
14815}
14816def M2_mpy_acc_sat_hl_s0 : HInst<
14817(outs IntRegs:$Rx32),
14818(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14819"$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
14820tc_7f8ae742, TypeM>, Enc_2ae154 {
14821let Inst{7-5} = 0b110;
14822let Inst{13-13} = 0b0;
14823let Inst{31-21} = 0b11101110000;
14824let hasNewValue = 1;
14825let opNewValue = 0;
14826let prefersSlot3 = 1;
14827let Defs = [USR_OVF];
14828let Constraints = "$Rx32 = $Rx32in";
14829}
14830def M2_mpy_acc_sat_hl_s1 : HInst<
14831(outs IntRegs:$Rx32),
14832(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14833"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
14834tc_7f8ae742, TypeM>, Enc_2ae154 {
14835let Inst{7-5} = 0b110;
14836let Inst{13-13} = 0b0;
14837let Inst{31-21} = 0b11101110100;
14838let hasNewValue = 1;
14839let opNewValue = 0;
14840let prefersSlot3 = 1;
14841let Defs = [USR_OVF];
14842let Constraints = "$Rx32 = $Rx32in";
14843}
14844def M2_mpy_acc_sat_lh_s0 : HInst<
14845(outs IntRegs:$Rx32),
14846(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14847"$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
14848tc_7f8ae742, TypeM>, Enc_2ae154 {
14849let Inst{7-5} = 0b101;
14850let Inst{13-13} = 0b0;
14851let Inst{31-21} = 0b11101110000;
14852let hasNewValue = 1;
14853let opNewValue = 0;
14854let prefersSlot3 = 1;
14855let Defs = [USR_OVF];
14856let Constraints = "$Rx32 = $Rx32in";
14857}
14858def M2_mpy_acc_sat_lh_s1 : HInst<
14859(outs IntRegs:$Rx32),
14860(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14861"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
14862tc_7f8ae742, TypeM>, Enc_2ae154 {
14863let Inst{7-5} = 0b101;
14864let Inst{13-13} = 0b0;
14865let Inst{31-21} = 0b11101110100;
14866let hasNewValue = 1;
14867let opNewValue = 0;
14868let prefersSlot3 = 1;
14869let Defs = [USR_OVF];
14870let Constraints = "$Rx32 = $Rx32in";
14871}
14872def M2_mpy_acc_sat_ll_s0 : HInst<
14873(outs IntRegs:$Rx32),
14874(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14875"$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
14876tc_7f8ae742, TypeM>, Enc_2ae154 {
14877let Inst{7-5} = 0b100;
14878let Inst{13-13} = 0b0;
14879let Inst{31-21} = 0b11101110000;
14880let hasNewValue = 1;
14881let opNewValue = 0;
14882let prefersSlot3 = 1;
14883let Defs = [USR_OVF];
14884let Constraints = "$Rx32 = $Rx32in";
14885}
14886def M2_mpy_acc_sat_ll_s1 : HInst<
14887(outs IntRegs:$Rx32),
14888(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14889"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
14890tc_7f8ae742, TypeM>, Enc_2ae154 {
14891let Inst{7-5} = 0b100;
14892let Inst{13-13} = 0b0;
14893let Inst{31-21} = 0b11101110100;
14894let hasNewValue = 1;
14895let opNewValue = 0;
14896let prefersSlot3 = 1;
14897let Defs = [USR_OVF];
14898let Constraints = "$Rx32 = $Rx32in";
14899}
14900def M2_mpy_hh_s0 : HInst<
14901(outs IntRegs:$Rd32),
14902(ins IntRegs:$Rs32, IntRegs:$Rt32),
14903"$Rd32 = mpy($Rs32.h,$Rt32.h)",
14904tc_c21d7447, TypeM>, Enc_5ab2be {
14905let Inst{7-5} = 0b011;
14906let Inst{13-13} = 0b0;
14907let Inst{31-21} = 0b11101100000;
14908let hasNewValue = 1;
14909let opNewValue = 0;
14910let prefersSlot3 = 1;
14911}
14912def M2_mpy_hh_s1 : HInst<
14913(outs IntRegs:$Rd32),
14914(ins IntRegs:$Rs32, IntRegs:$Rt32),
14915"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
14916tc_c21d7447, TypeM>, Enc_5ab2be {
14917let Inst{7-5} = 0b011;
14918let Inst{13-13} = 0b0;
14919let Inst{31-21} = 0b11101100100;
14920let hasNewValue = 1;
14921let opNewValue = 0;
14922let prefersSlot3 = 1;
14923}
14924def M2_mpy_hl_s0 : HInst<
14925(outs IntRegs:$Rd32),
14926(ins IntRegs:$Rs32, IntRegs:$Rt32),
14927"$Rd32 = mpy($Rs32.h,$Rt32.l)",
14928tc_c21d7447, TypeM>, Enc_5ab2be {
14929let Inst{7-5} = 0b010;
14930let Inst{13-13} = 0b0;
14931let Inst{31-21} = 0b11101100000;
14932let hasNewValue = 1;
14933let opNewValue = 0;
14934let prefersSlot3 = 1;
14935}
14936def M2_mpy_hl_s1 : HInst<
14937(outs IntRegs:$Rd32),
14938(ins IntRegs:$Rs32, IntRegs:$Rt32),
14939"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
14940tc_c21d7447, TypeM>, Enc_5ab2be {
14941let Inst{7-5} = 0b010;
14942let Inst{13-13} = 0b0;
14943let Inst{31-21} = 0b11101100100;
14944let hasNewValue = 1;
14945let opNewValue = 0;
14946let prefersSlot3 = 1;
14947}
14948def M2_mpy_lh_s0 : HInst<
14949(outs IntRegs:$Rd32),
14950(ins IntRegs:$Rs32, IntRegs:$Rt32),
14951"$Rd32 = mpy($Rs32.l,$Rt32.h)",
14952tc_c21d7447, TypeM>, Enc_5ab2be {
14953let Inst{7-5} = 0b001;
14954let Inst{13-13} = 0b0;
14955let Inst{31-21} = 0b11101100000;
14956let hasNewValue = 1;
14957let opNewValue = 0;
14958let prefersSlot3 = 1;
14959}
14960def M2_mpy_lh_s1 : HInst<
14961(outs IntRegs:$Rd32),
14962(ins IntRegs:$Rs32, IntRegs:$Rt32),
14963"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
14964tc_c21d7447, TypeM>, Enc_5ab2be {
14965let Inst{7-5} = 0b001;
14966let Inst{13-13} = 0b0;
14967let Inst{31-21} = 0b11101100100;
14968let hasNewValue = 1;
14969let opNewValue = 0;
14970let prefersSlot3 = 1;
14971}
14972def M2_mpy_ll_s0 : HInst<
14973(outs IntRegs:$Rd32),
14974(ins IntRegs:$Rs32, IntRegs:$Rt32),
14975"$Rd32 = mpy($Rs32.l,$Rt32.l)",
14976tc_c21d7447, TypeM>, Enc_5ab2be {
14977let Inst{7-5} = 0b000;
14978let Inst{13-13} = 0b0;
14979let Inst{31-21} = 0b11101100000;
14980let hasNewValue = 1;
14981let opNewValue = 0;
14982let prefersSlot3 = 1;
14983}
14984def M2_mpy_ll_s1 : HInst<
14985(outs IntRegs:$Rd32),
14986(ins IntRegs:$Rs32, IntRegs:$Rt32),
14987"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
14988tc_c21d7447, TypeM>, Enc_5ab2be {
14989let Inst{7-5} = 0b000;
14990let Inst{13-13} = 0b0;
14991let Inst{31-21} = 0b11101100100;
14992let hasNewValue = 1;
14993let opNewValue = 0;
14994let prefersSlot3 = 1;
14995}
14996def M2_mpy_nac_hh_s0 : HInst<
14997(outs IntRegs:$Rx32),
14998(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14999"$Rx32 -= mpy($Rs32.h,$Rt32.h)",
15000tc_7f8ae742, TypeM>, Enc_2ae154 {
15001let Inst{7-5} = 0b011;
15002let Inst{13-13} = 0b0;
15003let Inst{31-21} = 0b11101110001;
15004let hasNewValue = 1;
15005let opNewValue = 0;
15006let prefersSlot3 = 1;
15007let Constraints = "$Rx32 = $Rx32in";
15008}
15009def M2_mpy_nac_hh_s1 : HInst<
15010(outs IntRegs:$Rx32),
15011(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15012"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15013tc_7f8ae742, TypeM>, Enc_2ae154 {
15014let Inst{7-5} = 0b011;
15015let Inst{13-13} = 0b0;
15016let Inst{31-21} = 0b11101110101;
15017let hasNewValue = 1;
15018let opNewValue = 0;
15019let prefersSlot3 = 1;
15020let Constraints = "$Rx32 = $Rx32in";
15021}
15022def M2_mpy_nac_hl_s0 : HInst<
15023(outs IntRegs:$Rx32),
15024(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15025"$Rx32 -= mpy($Rs32.h,$Rt32.l)",
15026tc_7f8ae742, TypeM>, Enc_2ae154 {
15027let Inst{7-5} = 0b010;
15028let Inst{13-13} = 0b0;
15029let Inst{31-21} = 0b11101110001;
15030let hasNewValue = 1;
15031let opNewValue = 0;
15032let prefersSlot3 = 1;
15033let Constraints = "$Rx32 = $Rx32in";
15034}
15035def M2_mpy_nac_hl_s1 : HInst<
15036(outs IntRegs:$Rx32),
15037(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15038"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15039tc_7f8ae742, TypeM>, Enc_2ae154 {
15040let Inst{7-5} = 0b010;
15041let Inst{13-13} = 0b0;
15042let Inst{31-21} = 0b11101110101;
15043let hasNewValue = 1;
15044let opNewValue = 0;
15045let prefersSlot3 = 1;
15046let Constraints = "$Rx32 = $Rx32in";
15047}
15048def M2_mpy_nac_lh_s0 : HInst<
15049(outs IntRegs:$Rx32),
15050(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15051"$Rx32 -= mpy($Rs32.l,$Rt32.h)",
15052tc_7f8ae742, TypeM>, Enc_2ae154 {
15053let Inst{7-5} = 0b001;
15054let Inst{13-13} = 0b0;
15055let Inst{31-21} = 0b11101110001;
15056let hasNewValue = 1;
15057let opNewValue = 0;
15058let prefersSlot3 = 1;
15059let Constraints = "$Rx32 = $Rx32in";
15060}
15061def M2_mpy_nac_lh_s1 : HInst<
15062(outs IntRegs:$Rx32),
15063(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15064"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15065tc_7f8ae742, TypeM>, Enc_2ae154 {
15066let Inst{7-5} = 0b001;
15067let Inst{13-13} = 0b0;
15068let Inst{31-21} = 0b11101110101;
15069let hasNewValue = 1;
15070let opNewValue = 0;
15071let prefersSlot3 = 1;
15072let Constraints = "$Rx32 = $Rx32in";
15073}
15074def M2_mpy_nac_ll_s0 : HInst<
15075(outs IntRegs:$Rx32),
15076(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15077"$Rx32 -= mpy($Rs32.l,$Rt32.l)",
15078tc_7f8ae742, TypeM>, Enc_2ae154 {
15079let Inst{7-5} = 0b000;
15080let Inst{13-13} = 0b0;
15081let Inst{31-21} = 0b11101110001;
15082let hasNewValue = 1;
15083let opNewValue = 0;
15084let prefersSlot3 = 1;
15085let Constraints = "$Rx32 = $Rx32in";
15086}
15087def M2_mpy_nac_ll_s1 : HInst<
15088(outs IntRegs:$Rx32),
15089(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15090"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15091tc_7f8ae742, TypeM>, Enc_2ae154 {
15092let Inst{7-5} = 0b000;
15093let Inst{13-13} = 0b0;
15094let Inst{31-21} = 0b11101110101;
15095let hasNewValue = 1;
15096let opNewValue = 0;
15097let prefersSlot3 = 1;
15098let Constraints = "$Rx32 = $Rx32in";
15099}
15100def M2_mpy_nac_sat_hh_s0 : HInst<
15101(outs IntRegs:$Rx32),
15102(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15103"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
15104tc_7f8ae742, TypeM>, Enc_2ae154 {
15105let Inst{7-5} = 0b111;
15106let Inst{13-13} = 0b0;
15107let Inst{31-21} = 0b11101110001;
15108let hasNewValue = 1;
15109let opNewValue = 0;
15110let prefersSlot3 = 1;
15111let Defs = [USR_OVF];
15112let Constraints = "$Rx32 = $Rx32in";
15113}
15114def M2_mpy_nac_sat_hh_s1 : HInst<
15115(outs IntRegs:$Rx32),
15116(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15117"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
15118tc_7f8ae742, TypeM>, Enc_2ae154 {
15119let Inst{7-5} = 0b111;
15120let Inst{13-13} = 0b0;
15121let Inst{31-21} = 0b11101110101;
15122let hasNewValue = 1;
15123let opNewValue = 0;
15124let prefersSlot3 = 1;
15125let Defs = [USR_OVF];
15126let Constraints = "$Rx32 = $Rx32in";
15127}
15128def M2_mpy_nac_sat_hl_s0 : HInst<
15129(outs IntRegs:$Rx32),
15130(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15131"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
15132tc_7f8ae742, TypeM>, Enc_2ae154 {
15133let Inst{7-5} = 0b110;
15134let Inst{13-13} = 0b0;
15135let Inst{31-21} = 0b11101110001;
15136let hasNewValue = 1;
15137let opNewValue = 0;
15138let prefersSlot3 = 1;
15139let Defs = [USR_OVF];
15140let Constraints = "$Rx32 = $Rx32in";
15141}
15142def M2_mpy_nac_sat_hl_s1 : HInst<
15143(outs IntRegs:$Rx32),
15144(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15145"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
15146tc_7f8ae742, TypeM>, Enc_2ae154 {
15147let Inst{7-5} = 0b110;
15148let Inst{13-13} = 0b0;
15149let Inst{31-21} = 0b11101110101;
15150let hasNewValue = 1;
15151let opNewValue = 0;
15152let prefersSlot3 = 1;
15153let Defs = [USR_OVF];
15154let Constraints = "$Rx32 = $Rx32in";
15155}
15156def M2_mpy_nac_sat_lh_s0 : HInst<
15157(outs IntRegs:$Rx32),
15158(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15159"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
15160tc_7f8ae742, TypeM>, Enc_2ae154 {
15161let Inst{7-5} = 0b101;
15162let Inst{13-13} = 0b0;
15163let Inst{31-21} = 0b11101110001;
15164let hasNewValue = 1;
15165let opNewValue = 0;
15166let prefersSlot3 = 1;
15167let Defs = [USR_OVF];
15168let Constraints = "$Rx32 = $Rx32in";
15169}
15170def M2_mpy_nac_sat_lh_s1 : HInst<
15171(outs IntRegs:$Rx32),
15172(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15173"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
15174tc_7f8ae742, TypeM>, Enc_2ae154 {
15175let Inst{7-5} = 0b101;
15176let Inst{13-13} = 0b0;
15177let Inst{31-21} = 0b11101110101;
15178let hasNewValue = 1;
15179let opNewValue = 0;
15180let prefersSlot3 = 1;
15181let Defs = [USR_OVF];
15182let Constraints = "$Rx32 = $Rx32in";
15183}
15184def M2_mpy_nac_sat_ll_s0 : HInst<
15185(outs IntRegs:$Rx32),
15186(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15187"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
15188tc_7f8ae742, TypeM>, Enc_2ae154 {
15189let Inst{7-5} = 0b100;
15190let Inst{13-13} = 0b0;
15191let Inst{31-21} = 0b11101110001;
15192let hasNewValue = 1;
15193let opNewValue = 0;
15194let prefersSlot3 = 1;
15195let Defs = [USR_OVF];
15196let Constraints = "$Rx32 = $Rx32in";
15197}
15198def M2_mpy_nac_sat_ll_s1 : HInst<
15199(outs IntRegs:$Rx32),
15200(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15201"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
15202tc_7f8ae742, TypeM>, Enc_2ae154 {
15203let Inst{7-5} = 0b100;
15204let Inst{13-13} = 0b0;
15205let Inst{31-21} = 0b11101110101;
15206let hasNewValue = 1;
15207let opNewValue = 0;
15208let prefersSlot3 = 1;
15209let Defs = [USR_OVF];
15210let Constraints = "$Rx32 = $Rx32in";
15211}
15212def M2_mpy_rnd_hh_s0 : HInst<
15213(outs IntRegs:$Rd32),
15214(ins IntRegs:$Rs32, IntRegs:$Rt32),
15215"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
15216tc_c21d7447, TypeM>, Enc_5ab2be {
15217let Inst{7-5} = 0b011;
15218let Inst{13-13} = 0b0;
15219let Inst{31-21} = 0b11101100001;
15220let hasNewValue = 1;
15221let opNewValue = 0;
15222let prefersSlot3 = 1;
15223}
15224def M2_mpy_rnd_hh_s1 : HInst<
15225(outs IntRegs:$Rd32),
15226(ins IntRegs:$Rs32, IntRegs:$Rt32),
15227"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15228tc_c21d7447, TypeM>, Enc_5ab2be {
15229let Inst{7-5} = 0b011;
15230let Inst{13-13} = 0b0;
15231let Inst{31-21} = 0b11101100101;
15232let hasNewValue = 1;
15233let opNewValue = 0;
15234let prefersSlot3 = 1;
15235}
15236def M2_mpy_rnd_hl_s0 : HInst<
15237(outs IntRegs:$Rd32),
15238(ins IntRegs:$Rs32, IntRegs:$Rt32),
15239"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
15240tc_c21d7447, TypeM>, Enc_5ab2be {
15241let Inst{7-5} = 0b010;
15242let Inst{13-13} = 0b0;
15243let Inst{31-21} = 0b11101100001;
15244let hasNewValue = 1;
15245let opNewValue = 0;
15246let prefersSlot3 = 1;
15247}
15248def M2_mpy_rnd_hl_s1 : HInst<
15249(outs IntRegs:$Rd32),
15250(ins IntRegs:$Rs32, IntRegs:$Rt32),
15251"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15252tc_c21d7447, TypeM>, Enc_5ab2be {
15253let Inst{7-5} = 0b010;
15254let Inst{13-13} = 0b0;
15255let Inst{31-21} = 0b11101100101;
15256let hasNewValue = 1;
15257let opNewValue = 0;
15258let prefersSlot3 = 1;
15259}
15260def M2_mpy_rnd_lh_s0 : HInst<
15261(outs IntRegs:$Rd32),
15262(ins IntRegs:$Rs32, IntRegs:$Rt32),
15263"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
15264tc_c21d7447, TypeM>, Enc_5ab2be {
15265let Inst{7-5} = 0b001;
15266let Inst{13-13} = 0b0;
15267let Inst{31-21} = 0b11101100001;
15268let hasNewValue = 1;
15269let opNewValue = 0;
15270let prefersSlot3 = 1;
15271}
15272def M2_mpy_rnd_lh_s1 : HInst<
15273(outs IntRegs:$Rd32),
15274(ins IntRegs:$Rs32, IntRegs:$Rt32),
15275"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15276tc_c21d7447, TypeM>, Enc_5ab2be {
15277let Inst{7-5} = 0b001;
15278let Inst{13-13} = 0b0;
15279let Inst{31-21} = 0b11101100101;
15280let hasNewValue = 1;
15281let opNewValue = 0;
15282let prefersSlot3 = 1;
15283}
15284def M2_mpy_rnd_ll_s0 : HInst<
15285(outs IntRegs:$Rd32),
15286(ins IntRegs:$Rs32, IntRegs:$Rt32),
15287"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
15288tc_c21d7447, TypeM>, Enc_5ab2be {
15289let Inst{7-5} = 0b000;
15290let Inst{13-13} = 0b0;
15291let Inst{31-21} = 0b11101100001;
15292let hasNewValue = 1;
15293let opNewValue = 0;
15294let prefersSlot3 = 1;
15295}
15296def M2_mpy_rnd_ll_s1 : HInst<
15297(outs IntRegs:$Rd32),
15298(ins IntRegs:$Rs32, IntRegs:$Rt32),
15299"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15300tc_c21d7447, TypeM>, Enc_5ab2be {
15301let Inst{7-5} = 0b000;
15302let Inst{13-13} = 0b0;
15303let Inst{31-21} = 0b11101100101;
15304let hasNewValue = 1;
15305let opNewValue = 0;
15306let prefersSlot3 = 1;
15307}
15308def M2_mpy_sat_hh_s0 : HInst<
15309(outs IntRegs:$Rd32),
15310(ins IntRegs:$Rs32, IntRegs:$Rt32),
15311"$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
15312tc_c21d7447, TypeM>, Enc_5ab2be {
15313let Inst{7-5} = 0b111;
15314let Inst{13-13} = 0b0;
15315let Inst{31-21} = 0b11101100000;
15316let hasNewValue = 1;
15317let opNewValue = 0;
15318let prefersSlot3 = 1;
15319let Defs = [USR_OVF];
15320}
15321def M2_mpy_sat_hh_s1 : HInst<
15322(outs IntRegs:$Rd32),
15323(ins IntRegs:$Rs32, IntRegs:$Rt32),
15324"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
15325tc_c21d7447, TypeM>, Enc_5ab2be {
15326let Inst{7-5} = 0b111;
15327let Inst{13-13} = 0b0;
15328let Inst{31-21} = 0b11101100100;
15329let hasNewValue = 1;
15330let opNewValue = 0;
15331let prefersSlot3 = 1;
15332let Defs = [USR_OVF];
15333}
15334def M2_mpy_sat_hl_s0 : HInst<
15335(outs IntRegs:$Rd32),
15336(ins IntRegs:$Rs32, IntRegs:$Rt32),
15337"$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
15338tc_c21d7447, TypeM>, Enc_5ab2be {
15339let Inst{7-5} = 0b110;
15340let Inst{13-13} = 0b0;
15341let Inst{31-21} = 0b11101100000;
15342let hasNewValue = 1;
15343let opNewValue = 0;
15344let prefersSlot3 = 1;
15345let Defs = [USR_OVF];
15346}
15347def M2_mpy_sat_hl_s1 : HInst<
15348(outs IntRegs:$Rd32),
15349(ins IntRegs:$Rs32, IntRegs:$Rt32),
15350"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
15351tc_c21d7447, TypeM>, Enc_5ab2be {
15352let Inst{7-5} = 0b110;
15353let Inst{13-13} = 0b0;
15354let Inst{31-21} = 0b11101100100;
15355let hasNewValue = 1;
15356let opNewValue = 0;
15357let prefersSlot3 = 1;
15358let Defs = [USR_OVF];
15359}
15360def M2_mpy_sat_lh_s0 : HInst<
15361(outs IntRegs:$Rd32),
15362(ins IntRegs:$Rs32, IntRegs:$Rt32),
15363"$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
15364tc_c21d7447, TypeM>, Enc_5ab2be {
15365let Inst{7-5} = 0b101;
15366let Inst{13-13} = 0b0;
15367let Inst{31-21} = 0b11101100000;
15368let hasNewValue = 1;
15369let opNewValue = 0;
15370let prefersSlot3 = 1;
15371let Defs = [USR_OVF];
15372}
15373def M2_mpy_sat_lh_s1 : HInst<
15374(outs IntRegs:$Rd32),
15375(ins IntRegs:$Rs32, IntRegs:$Rt32),
15376"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
15377tc_c21d7447, TypeM>, Enc_5ab2be {
15378let Inst{7-5} = 0b101;
15379let Inst{13-13} = 0b0;
15380let Inst{31-21} = 0b11101100100;
15381let hasNewValue = 1;
15382let opNewValue = 0;
15383let prefersSlot3 = 1;
15384let Defs = [USR_OVF];
15385}
15386def M2_mpy_sat_ll_s0 : HInst<
15387(outs IntRegs:$Rd32),
15388(ins IntRegs:$Rs32, IntRegs:$Rt32),
15389"$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
15390tc_c21d7447, TypeM>, Enc_5ab2be {
15391let Inst{7-5} = 0b100;
15392let Inst{13-13} = 0b0;
15393let Inst{31-21} = 0b11101100000;
15394let hasNewValue = 1;
15395let opNewValue = 0;
15396let prefersSlot3 = 1;
15397let Defs = [USR_OVF];
15398}
15399def M2_mpy_sat_ll_s1 : HInst<
15400(outs IntRegs:$Rd32),
15401(ins IntRegs:$Rs32, IntRegs:$Rt32),
15402"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
15403tc_c21d7447, TypeM>, Enc_5ab2be {
15404let Inst{7-5} = 0b100;
15405let Inst{13-13} = 0b0;
15406let Inst{31-21} = 0b11101100100;
15407let hasNewValue = 1;
15408let opNewValue = 0;
15409let prefersSlot3 = 1;
15410let Defs = [USR_OVF];
15411}
15412def M2_mpy_sat_rnd_hh_s0 : HInst<
15413(outs IntRegs:$Rd32),
15414(ins IntRegs:$Rs32, IntRegs:$Rt32),
15415"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
15416tc_c21d7447, TypeM>, Enc_5ab2be {
15417let Inst{7-5} = 0b111;
15418let Inst{13-13} = 0b0;
15419let Inst{31-21} = 0b11101100001;
15420let hasNewValue = 1;
15421let opNewValue = 0;
15422let prefersSlot3 = 1;
15423let Defs = [USR_OVF];
15424}
15425def M2_mpy_sat_rnd_hh_s1 : HInst<
15426(outs IntRegs:$Rd32),
15427(ins IntRegs:$Rs32, IntRegs:$Rt32),
15428"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
15429tc_c21d7447, TypeM>, Enc_5ab2be {
15430let Inst{7-5} = 0b111;
15431let Inst{13-13} = 0b0;
15432let Inst{31-21} = 0b11101100101;
15433let hasNewValue = 1;
15434let opNewValue = 0;
15435let prefersSlot3 = 1;
15436let Defs = [USR_OVF];
15437}
15438def M2_mpy_sat_rnd_hl_s0 : HInst<
15439(outs IntRegs:$Rd32),
15440(ins IntRegs:$Rs32, IntRegs:$Rt32),
15441"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
15442tc_c21d7447, TypeM>, Enc_5ab2be {
15443let Inst{7-5} = 0b110;
15444let Inst{13-13} = 0b0;
15445let Inst{31-21} = 0b11101100001;
15446let hasNewValue = 1;
15447let opNewValue = 0;
15448let prefersSlot3 = 1;
15449let Defs = [USR_OVF];
15450}
15451def M2_mpy_sat_rnd_hl_s1 : HInst<
15452(outs IntRegs:$Rd32),
15453(ins IntRegs:$Rs32, IntRegs:$Rt32),
15454"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
15455tc_c21d7447, TypeM>, Enc_5ab2be {
15456let Inst{7-5} = 0b110;
15457let Inst{13-13} = 0b0;
15458let Inst{31-21} = 0b11101100101;
15459let hasNewValue = 1;
15460let opNewValue = 0;
15461let prefersSlot3 = 1;
15462let Defs = [USR_OVF];
15463}
15464def M2_mpy_sat_rnd_lh_s0 : HInst<
15465(outs IntRegs:$Rd32),
15466(ins IntRegs:$Rs32, IntRegs:$Rt32),
15467"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
15468tc_c21d7447, TypeM>, Enc_5ab2be {
15469let Inst{7-5} = 0b101;
15470let Inst{13-13} = 0b0;
15471let Inst{31-21} = 0b11101100001;
15472let hasNewValue = 1;
15473let opNewValue = 0;
15474let prefersSlot3 = 1;
15475let Defs = [USR_OVF];
15476}
15477def M2_mpy_sat_rnd_lh_s1 : HInst<
15478(outs IntRegs:$Rd32),
15479(ins IntRegs:$Rs32, IntRegs:$Rt32),
15480"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
15481tc_c21d7447, TypeM>, Enc_5ab2be {
15482let Inst{7-5} = 0b101;
15483let Inst{13-13} = 0b0;
15484let Inst{31-21} = 0b11101100101;
15485let hasNewValue = 1;
15486let opNewValue = 0;
15487let prefersSlot3 = 1;
15488let Defs = [USR_OVF];
15489}
15490def M2_mpy_sat_rnd_ll_s0 : HInst<
15491(outs IntRegs:$Rd32),
15492(ins IntRegs:$Rs32, IntRegs:$Rt32),
15493"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
15494tc_c21d7447, TypeM>, Enc_5ab2be {
15495let Inst{7-5} = 0b100;
15496let Inst{13-13} = 0b0;
15497let Inst{31-21} = 0b11101100001;
15498let hasNewValue = 1;
15499let opNewValue = 0;
15500let prefersSlot3 = 1;
15501let Defs = [USR_OVF];
15502}
15503def M2_mpy_sat_rnd_ll_s1 : HInst<
15504(outs IntRegs:$Rd32),
15505(ins IntRegs:$Rs32, IntRegs:$Rt32),
15506"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
15507tc_c21d7447, TypeM>, Enc_5ab2be {
15508let Inst{7-5} = 0b100;
15509let Inst{13-13} = 0b0;
15510let Inst{31-21} = 0b11101100101;
15511let hasNewValue = 1;
15512let opNewValue = 0;
15513let prefersSlot3 = 1;
15514let Defs = [USR_OVF];
15515}
15516def M2_mpy_up : HInst<
15517(outs IntRegs:$Rd32),
15518(ins IntRegs:$Rs32, IntRegs:$Rt32),
15519"$Rd32 = mpy($Rs32,$Rt32)",
15520tc_c21d7447, TypeM>, Enc_5ab2be {
15521let Inst{7-5} = 0b001;
15522let Inst{13-13} = 0b0;
15523let Inst{31-21} = 0b11101101000;
15524let hasNewValue = 1;
15525let opNewValue = 0;
15526let prefersSlot3 = 1;
15527}
15528def M2_mpy_up_s1 : HInst<
15529(outs IntRegs:$Rd32),
15530(ins IntRegs:$Rs32, IntRegs:$Rt32),
15531"$Rd32 = mpy($Rs32,$Rt32):<<1",
15532tc_c21d7447, TypeM>, Enc_5ab2be {
15533let Inst{7-5} = 0b010;
15534let Inst{13-13} = 0b0;
15535let Inst{31-21} = 0b11101101101;
15536let hasNewValue = 1;
15537let opNewValue = 0;
15538let prefersSlot3 = 1;
15539}
15540def M2_mpy_up_s1_sat : HInst<
15541(outs IntRegs:$Rd32),
15542(ins IntRegs:$Rs32, IntRegs:$Rt32),
15543"$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
15544tc_c21d7447, TypeM>, Enc_5ab2be {
15545let Inst{7-5} = 0b000;
15546let Inst{13-13} = 0b0;
15547let Inst{31-21} = 0b11101101111;
15548let hasNewValue = 1;
15549let opNewValue = 0;
15550let prefersSlot3 = 1;
15551let Defs = [USR_OVF];
15552}
15553def M2_mpyd_acc_hh_s0 : HInst<
15554(outs DoubleRegs:$Rxx32),
15555(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15556"$Rxx32 += mpy($Rs32.h,$Rt32.h)",
15557tc_7f8ae742, TypeM>, Enc_61f0b0 {
15558let Inst{7-5} = 0b011;
15559let Inst{13-13} = 0b0;
15560let Inst{31-21} = 0b11100110000;
15561let prefersSlot3 = 1;
15562let Constraints = "$Rxx32 = $Rxx32in";
15563}
15564def M2_mpyd_acc_hh_s1 : HInst<
15565(outs DoubleRegs:$Rxx32),
15566(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15567"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
15568tc_7f8ae742, TypeM>, Enc_61f0b0 {
15569let Inst{7-5} = 0b011;
15570let Inst{13-13} = 0b0;
15571let Inst{31-21} = 0b11100110100;
15572let prefersSlot3 = 1;
15573let Constraints = "$Rxx32 = $Rxx32in";
15574}
15575def M2_mpyd_acc_hl_s0 : HInst<
15576(outs DoubleRegs:$Rxx32),
15577(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15578"$Rxx32 += mpy($Rs32.h,$Rt32.l)",
15579tc_7f8ae742, TypeM>, Enc_61f0b0 {
15580let Inst{7-5} = 0b010;
15581let Inst{13-13} = 0b0;
15582let Inst{31-21} = 0b11100110000;
15583let prefersSlot3 = 1;
15584let Constraints = "$Rxx32 = $Rxx32in";
15585}
15586def M2_mpyd_acc_hl_s1 : HInst<
15587(outs DoubleRegs:$Rxx32),
15588(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15589"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
15590tc_7f8ae742, TypeM>, Enc_61f0b0 {
15591let Inst{7-5} = 0b010;
15592let Inst{13-13} = 0b0;
15593let Inst{31-21} = 0b11100110100;
15594let prefersSlot3 = 1;
15595let Constraints = "$Rxx32 = $Rxx32in";
15596}
15597def M2_mpyd_acc_lh_s0 : HInst<
15598(outs DoubleRegs:$Rxx32),
15599(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15600"$Rxx32 += mpy($Rs32.l,$Rt32.h)",
15601tc_7f8ae742, TypeM>, Enc_61f0b0 {
15602let Inst{7-5} = 0b001;
15603let Inst{13-13} = 0b0;
15604let Inst{31-21} = 0b11100110000;
15605let prefersSlot3 = 1;
15606let Constraints = "$Rxx32 = $Rxx32in";
15607}
15608def M2_mpyd_acc_lh_s1 : HInst<
15609(outs DoubleRegs:$Rxx32),
15610(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15611"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
15612tc_7f8ae742, TypeM>, Enc_61f0b0 {
15613let Inst{7-5} = 0b001;
15614let Inst{13-13} = 0b0;
15615let Inst{31-21} = 0b11100110100;
15616let prefersSlot3 = 1;
15617let Constraints = "$Rxx32 = $Rxx32in";
15618}
15619def M2_mpyd_acc_ll_s0 : HInst<
15620(outs DoubleRegs:$Rxx32),
15621(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15622"$Rxx32 += mpy($Rs32.l,$Rt32.l)",
15623tc_7f8ae742, TypeM>, Enc_61f0b0 {
15624let Inst{7-5} = 0b000;
15625let Inst{13-13} = 0b0;
15626let Inst{31-21} = 0b11100110000;
15627let prefersSlot3 = 1;
15628let Constraints = "$Rxx32 = $Rxx32in";
15629}
15630def M2_mpyd_acc_ll_s1 : HInst<
15631(outs DoubleRegs:$Rxx32),
15632(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15633"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
15634tc_7f8ae742, TypeM>, Enc_61f0b0 {
15635let Inst{7-5} = 0b000;
15636let Inst{13-13} = 0b0;
15637let Inst{31-21} = 0b11100110100;
15638let prefersSlot3 = 1;
15639let Constraints = "$Rxx32 = $Rxx32in";
15640}
15641def M2_mpyd_hh_s0 : HInst<
15642(outs DoubleRegs:$Rdd32),
15643(ins IntRegs:$Rs32, IntRegs:$Rt32),
15644"$Rdd32 = mpy($Rs32.h,$Rt32.h)",
15645tc_c21d7447, TypeM>, Enc_be32a5 {
15646let Inst{7-5} = 0b011;
15647let Inst{13-13} = 0b0;
15648let Inst{31-21} = 0b11100100000;
15649let prefersSlot3 = 1;
15650}
15651def M2_mpyd_hh_s1 : HInst<
15652(outs DoubleRegs:$Rdd32),
15653(ins IntRegs:$Rs32, IntRegs:$Rt32),
15654"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
15655tc_c21d7447, TypeM>, Enc_be32a5 {
15656let Inst{7-5} = 0b011;
15657let Inst{13-13} = 0b0;
15658let Inst{31-21} = 0b11100100100;
15659let prefersSlot3 = 1;
15660}
15661def M2_mpyd_hl_s0 : HInst<
15662(outs DoubleRegs:$Rdd32),
15663(ins IntRegs:$Rs32, IntRegs:$Rt32),
15664"$Rdd32 = mpy($Rs32.h,$Rt32.l)",
15665tc_c21d7447, TypeM>, Enc_be32a5 {
15666let Inst{7-5} = 0b010;
15667let Inst{13-13} = 0b0;
15668let Inst{31-21} = 0b11100100000;
15669let prefersSlot3 = 1;
15670}
15671def M2_mpyd_hl_s1 : HInst<
15672(outs DoubleRegs:$Rdd32),
15673(ins IntRegs:$Rs32, IntRegs:$Rt32),
15674"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
15675tc_c21d7447, TypeM>, Enc_be32a5 {
15676let Inst{7-5} = 0b010;
15677let Inst{13-13} = 0b0;
15678let Inst{31-21} = 0b11100100100;
15679let prefersSlot3 = 1;
15680}
15681def M2_mpyd_lh_s0 : HInst<
15682(outs DoubleRegs:$Rdd32),
15683(ins IntRegs:$Rs32, IntRegs:$Rt32),
15684"$Rdd32 = mpy($Rs32.l,$Rt32.h)",
15685tc_c21d7447, TypeM>, Enc_be32a5 {
15686let Inst{7-5} = 0b001;
15687let Inst{13-13} = 0b0;
15688let Inst{31-21} = 0b11100100000;
15689let prefersSlot3 = 1;
15690}
15691def M2_mpyd_lh_s1 : HInst<
15692(outs DoubleRegs:$Rdd32),
15693(ins IntRegs:$Rs32, IntRegs:$Rt32),
15694"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
15695tc_c21d7447, TypeM>, Enc_be32a5 {
15696let Inst{7-5} = 0b001;
15697let Inst{13-13} = 0b0;
15698let Inst{31-21} = 0b11100100100;
15699let prefersSlot3 = 1;
15700}
15701def M2_mpyd_ll_s0 : HInst<
15702(outs DoubleRegs:$Rdd32),
15703(ins IntRegs:$Rs32, IntRegs:$Rt32),
15704"$Rdd32 = mpy($Rs32.l,$Rt32.l)",
15705tc_c21d7447, TypeM>, Enc_be32a5 {
15706let Inst{7-5} = 0b000;
15707let Inst{13-13} = 0b0;
15708let Inst{31-21} = 0b11100100000;
15709let prefersSlot3 = 1;
15710}
15711def M2_mpyd_ll_s1 : HInst<
15712(outs DoubleRegs:$Rdd32),
15713(ins IntRegs:$Rs32, IntRegs:$Rt32),
15714"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
15715tc_c21d7447, TypeM>, Enc_be32a5 {
15716let Inst{7-5} = 0b000;
15717let Inst{13-13} = 0b0;
15718let Inst{31-21} = 0b11100100100;
15719let prefersSlot3 = 1;
15720}
15721def M2_mpyd_nac_hh_s0 : HInst<
15722(outs DoubleRegs:$Rxx32),
15723(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15724"$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
15725tc_7f8ae742, TypeM>, Enc_61f0b0 {
15726let Inst{7-5} = 0b011;
15727let Inst{13-13} = 0b0;
15728let Inst{31-21} = 0b11100110001;
15729let prefersSlot3 = 1;
15730let Constraints = "$Rxx32 = $Rxx32in";
15731}
15732def M2_mpyd_nac_hh_s1 : HInst<
15733(outs DoubleRegs:$Rxx32),
15734(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15735"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15736tc_7f8ae742, TypeM>, Enc_61f0b0 {
15737let Inst{7-5} = 0b011;
15738let Inst{13-13} = 0b0;
15739let Inst{31-21} = 0b11100110101;
15740let prefersSlot3 = 1;
15741let Constraints = "$Rxx32 = $Rxx32in";
15742}
15743def M2_mpyd_nac_hl_s0 : HInst<
15744(outs DoubleRegs:$Rxx32),
15745(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15746"$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
15747tc_7f8ae742, TypeM>, Enc_61f0b0 {
15748let Inst{7-5} = 0b010;
15749let Inst{13-13} = 0b0;
15750let Inst{31-21} = 0b11100110001;
15751let prefersSlot3 = 1;
15752let Constraints = "$Rxx32 = $Rxx32in";
15753}
15754def M2_mpyd_nac_hl_s1 : HInst<
15755(outs DoubleRegs:$Rxx32),
15756(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15757"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15758tc_7f8ae742, TypeM>, Enc_61f0b0 {
15759let Inst{7-5} = 0b010;
15760let Inst{13-13} = 0b0;
15761let Inst{31-21} = 0b11100110101;
15762let prefersSlot3 = 1;
15763let Constraints = "$Rxx32 = $Rxx32in";
15764}
15765def M2_mpyd_nac_lh_s0 : HInst<
15766(outs DoubleRegs:$Rxx32),
15767(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15768"$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
15769tc_7f8ae742, TypeM>, Enc_61f0b0 {
15770let Inst{7-5} = 0b001;
15771let Inst{13-13} = 0b0;
15772let Inst{31-21} = 0b11100110001;
15773let prefersSlot3 = 1;
15774let Constraints = "$Rxx32 = $Rxx32in";
15775}
15776def M2_mpyd_nac_lh_s1 : HInst<
15777(outs DoubleRegs:$Rxx32),
15778(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15779"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15780tc_7f8ae742, TypeM>, Enc_61f0b0 {
15781let Inst{7-5} = 0b001;
15782let Inst{13-13} = 0b0;
15783let Inst{31-21} = 0b11100110101;
15784let prefersSlot3 = 1;
15785let Constraints = "$Rxx32 = $Rxx32in";
15786}
15787def M2_mpyd_nac_ll_s0 : HInst<
15788(outs DoubleRegs:$Rxx32),
15789(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15790"$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
15791tc_7f8ae742, TypeM>, Enc_61f0b0 {
15792let Inst{7-5} = 0b000;
15793let Inst{13-13} = 0b0;
15794let Inst{31-21} = 0b11100110001;
15795let prefersSlot3 = 1;
15796let Constraints = "$Rxx32 = $Rxx32in";
15797}
15798def M2_mpyd_nac_ll_s1 : HInst<
15799(outs DoubleRegs:$Rxx32),
15800(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15801"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15802tc_7f8ae742, TypeM>, Enc_61f0b0 {
15803let Inst{7-5} = 0b000;
15804let Inst{13-13} = 0b0;
15805let Inst{31-21} = 0b11100110101;
15806let prefersSlot3 = 1;
15807let Constraints = "$Rxx32 = $Rxx32in";
15808}
15809def M2_mpyd_rnd_hh_s0 : HInst<
15810(outs DoubleRegs:$Rdd32),
15811(ins IntRegs:$Rs32, IntRegs:$Rt32),
15812"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
15813tc_c21d7447, TypeM>, Enc_be32a5 {
15814let Inst{7-5} = 0b011;
15815let Inst{13-13} = 0b0;
15816let Inst{31-21} = 0b11100100001;
15817let prefersSlot3 = 1;
15818}
15819def M2_mpyd_rnd_hh_s1 : HInst<
15820(outs DoubleRegs:$Rdd32),
15821(ins IntRegs:$Rs32, IntRegs:$Rt32),
15822"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15823tc_c21d7447, TypeM>, Enc_be32a5 {
15824let Inst{7-5} = 0b011;
15825let Inst{13-13} = 0b0;
15826let Inst{31-21} = 0b11100100101;
15827let prefersSlot3 = 1;
15828}
15829def M2_mpyd_rnd_hl_s0 : HInst<
15830(outs DoubleRegs:$Rdd32),
15831(ins IntRegs:$Rs32, IntRegs:$Rt32),
15832"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
15833tc_c21d7447, TypeM>, Enc_be32a5 {
15834let Inst{7-5} = 0b010;
15835let Inst{13-13} = 0b0;
15836let Inst{31-21} = 0b11100100001;
15837let prefersSlot3 = 1;
15838}
15839def M2_mpyd_rnd_hl_s1 : HInst<
15840(outs DoubleRegs:$Rdd32),
15841(ins IntRegs:$Rs32, IntRegs:$Rt32),
15842"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15843tc_c21d7447, TypeM>, Enc_be32a5 {
15844let Inst{7-5} = 0b010;
15845let Inst{13-13} = 0b0;
15846let Inst{31-21} = 0b11100100101;
15847let prefersSlot3 = 1;
15848}
15849def M2_mpyd_rnd_lh_s0 : HInst<
15850(outs DoubleRegs:$Rdd32),
15851(ins IntRegs:$Rs32, IntRegs:$Rt32),
15852"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
15853tc_c21d7447, TypeM>, Enc_be32a5 {
15854let Inst{7-5} = 0b001;
15855let Inst{13-13} = 0b0;
15856let Inst{31-21} = 0b11100100001;
15857let prefersSlot3 = 1;
15858}
15859def M2_mpyd_rnd_lh_s1 : HInst<
15860(outs DoubleRegs:$Rdd32),
15861(ins IntRegs:$Rs32, IntRegs:$Rt32),
15862"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15863tc_c21d7447, TypeM>, Enc_be32a5 {
15864let Inst{7-5} = 0b001;
15865let Inst{13-13} = 0b0;
15866let Inst{31-21} = 0b11100100101;
15867let prefersSlot3 = 1;
15868}
15869def M2_mpyd_rnd_ll_s0 : HInst<
15870(outs DoubleRegs:$Rdd32),
15871(ins IntRegs:$Rs32, IntRegs:$Rt32),
15872"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
15873tc_c21d7447, TypeM>, Enc_be32a5 {
15874let Inst{7-5} = 0b000;
15875let Inst{13-13} = 0b0;
15876let Inst{31-21} = 0b11100100001;
15877let prefersSlot3 = 1;
15878}
15879def M2_mpyd_rnd_ll_s1 : HInst<
15880(outs DoubleRegs:$Rdd32),
15881(ins IntRegs:$Rs32, IntRegs:$Rt32),
15882"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15883tc_c21d7447, TypeM>, Enc_be32a5 {
15884let Inst{7-5} = 0b000;
15885let Inst{13-13} = 0b0;
15886let Inst{31-21} = 0b11100100101;
15887let prefersSlot3 = 1;
15888}
15889def M2_mpyi : HInst<
15890(outs IntRegs:$Rd32),
15891(ins IntRegs:$Rs32, IntRegs:$Rt32),
15892"$Rd32 = mpyi($Rs32,$Rt32)",
15893tc_c21d7447, TypeM>, Enc_5ab2be, ImmRegRel {
15894let Inst{7-5} = 0b000;
15895let Inst{13-13} = 0b0;
15896let Inst{31-21} = 0b11101101000;
15897let hasNewValue = 1;
15898let opNewValue = 0;
15899let prefersSlot3 = 1;
15900let CextOpcode = "M2_mpyi";
15901let InputType = "reg";
15902}
15903def M2_mpysin : HInst<
15904(outs IntRegs:$Rd32),
15905(ins IntRegs:$Rs32, u8_0Imm:$Ii),
15906"$Rd32 = -mpyi($Rs32,#$Ii)",
15907tc_38382228, TypeM>, Enc_b8c967 {
15908let Inst{13-13} = 0b0;
15909let Inst{31-21} = 0b11100000100;
15910let hasNewValue = 1;
15911let opNewValue = 0;
15912let prefersSlot3 = 1;
15913}
15914def M2_mpysip : HInst<
15915(outs IntRegs:$Rd32),
15916(ins IntRegs:$Rs32, u32_0Imm:$Ii),
15917"$Rd32 = +mpyi($Rs32,#$Ii)",
15918tc_38382228, TypeM>, Enc_b8c967 {
15919let Inst{13-13} = 0b0;
15920let Inst{31-21} = 0b11100000000;
15921let hasNewValue = 1;
15922let opNewValue = 0;
15923let prefersSlot3 = 1;
15924let isExtendable = 1;
15925let opExtendable = 2;
15926let isExtentSigned = 0;
15927let opExtentBits = 8;
15928let opExtentAlign = 0;
15929}
15930def M2_mpysmi : HInst<
15931(outs IntRegs:$Rd32),
15932(ins IntRegs:$Rs32, m32_0Imm:$Ii),
15933"$Rd32 = mpyi($Rs32,#$Ii)",
15934tc_38382228, TypeM>, ImmRegRel {
15935let hasNewValue = 1;
15936let opNewValue = 0;
15937let CextOpcode = "M2_mpyi";
15938let InputType = "imm";
15939let isPseudo = 1;
15940let isExtendable = 1;
15941let opExtendable = 2;
15942let isExtentSigned = 1;
15943let opExtentBits = 9;
15944let opExtentAlign = 0;
15945}
15946def M2_mpysu_up : HInst<
15947(outs IntRegs:$Rd32),
15948(ins IntRegs:$Rs32, IntRegs:$Rt32),
15949"$Rd32 = mpysu($Rs32,$Rt32)",
15950tc_c21d7447, TypeM>, Enc_5ab2be {
15951let Inst{7-5} = 0b001;
15952let Inst{13-13} = 0b0;
15953let Inst{31-21} = 0b11101101011;
15954let hasNewValue = 1;
15955let opNewValue = 0;
15956let prefersSlot3 = 1;
15957}
15958def M2_mpyu_acc_hh_s0 : HInst<
15959(outs IntRegs:$Rx32),
15960(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15961"$Rx32 += mpyu($Rs32.h,$Rt32.h)",
15962tc_7f8ae742, TypeM>, Enc_2ae154 {
15963let Inst{7-5} = 0b011;
15964let Inst{13-13} = 0b0;
15965let Inst{31-21} = 0b11101110010;
15966let hasNewValue = 1;
15967let opNewValue = 0;
15968let prefersSlot3 = 1;
15969let Constraints = "$Rx32 = $Rx32in";
15970}
15971def M2_mpyu_acc_hh_s1 : HInst<
15972(outs IntRegs:$Rx32),
15973(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15974"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15975tc_7f8ae742, TypeM>, Enc_2ae154 {
15976let Inst{7-5} = 0b011;
15977let Inst{13-13} = 0b0;
15978let Inst{31-21} = 0b11101110110;
15979let hasNewValue = 1;
15980let opNewValue = 0;
15981let prefersSlot3 = 1;
15982let Constraints = "$Rx32 = $Rx32in";
15983}
15984def M2_mpyu_acc_hl_s0 : HInst<
15985(outs IntRegs:$Rx32),
15986(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15987"$Rx32 += mpyu($Rs32.h,$Rt32.l)",
15988tc_7f8ae742, TypeM>, Enc_2ae154 {
15989let Inst{7-5} = 0b010;
15990let Inst{13-13} = 0b0;
15991let Inst{31-21} = 0b11101110010;
15992let hasNewValue = 1;
15993let opNewValue = 0;
15994let prefersSlot3 = 1;
15995let Constraints = "$Rx32 = $Rx32in";
15996}
15997def M2_mpyu_acc_hl_s1 : HInst<
15998(outs IntRegs:$Rx32),
15999(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16000"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
16001tc_7f8ae742, TypeM>, Enc_2ae154 {
16002let Inst{7-5} = 0b010;
16003let Inst{13-13} = 0b0;
16004let Inst{31-21} = 0b11101110110;
16005let hasNewValue = 1;
16006let opNewValue = 0;
16007let prefersSlot3 = 1;
16008let Constraints = "$Rx32 = $Rx32in";
16009}
16010def M2_mpyu_acc_lh_s0 : HInst<
16011(outs IntRegs:$Rx32),
16012(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16013"$Rx32 += mpyu($Rs32.l,$Rt32.h)",
16014tc_7f8ae742, TypeM>, Enc_2ae154 {
16015let Inst{7-5} = 0b001;
16016let Inst{13-13} = 0b0;
16017let Inst{31-21} = 0b11101110010;
16018let hasNewValue = 1;
16019let opNewValue = 0;
16020let prefersSlot3 = 1;
16021let Constraints = "$Rx32 = $Rx32in";
16022}
16023def M2_mpyu_acc_lh_s1 : HInst<
16024(outs IntRegs:$Rx32),
16025(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16026"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16027tc_7f8ae742, TypeM>, Enc_2ae154 {
16028let Inst{7-5} = 0b001;
16029let Inst{13-13} = 0b0;
16030let Inst{31-21} = 0b11101110110;
16031let hasNewValue = 1;
16032let opNewValue = 0;
16033let prefersSlot3 = 1;
16034let Constraints = "$Rx32 = $Rx32in";
16035}
16036def M2_mpyu_acc_ll_s0 : HInst<
16037(outs IntRegs:$Rx32),
16038(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16039"$Rx32 += mpyu($Rs32.l,$Rt32.l)",
16040tc_7f8ae742, TypeM>, Enc_2ae154 {
16041let Inst{7-5} = 0b000;
16042let Inst{13-13} = 0b0;
16043let Inst{31-21} = 0b11101110010;
16044let hasNewValue = 1;
16045let opNewValue = 0;
16046let prefersSlot3 = 1;
16047let Constraints = "$Rx32 = $Rx32in";
16048}
16049def M2_mpyu_acc_ll_s1 : HInst<
16050(outs IntRegs:$Rx32),
16051(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16052"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16053tc_7f8ae742, TypeM>, Enc_2ae154 {
16054let Inst{7-5} = 0b000;
16055let Inst{13-13} = 0b0;
16056let Inst{31-21} = 0b11101110110;
16057let hasNewValue = 1;
16058let opNewValue = 0;
16059let prefersSlot3 = 1;
16060let Constraints = "$Rx32 = $Rx32in";
16061}
16062def M2_mpyu_hh_s0 : HInst<
16063(outs IntRegs:$Rd32),
16064(ins IntRegs:$Rs32, IntRegs:$Rt32),
16065"$Rd32 = mpyu($Rs32.h,$Rt32.h)",
16066tc_c21d7447, TypeM>, Enc_5ab2be {
16067let Inst{7-5} = 0b011;
16068let Inst{13-13} = 0b0;
16069let Inst{31-21} = 0b11101100010;
16070let hasNewValue = 1;
16071let opNewValue = 0;
16072let prefersSlot3 = 1;
16073}
16074def M2_mpyu_hh_s1 : HInst<
16075(outs IntRegs:$Rd32),
16076(ins IntRegs:$Rs32, IntRegs:$Rt32),
16077"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16078tc_c21d7447, TypeM>, Enc_5ab2be {
16079let Inst{7-5} = 0b011;
16080let Inst{13-13} = 0b0;
16081let Inst{31-21} = 0b11101100110;
16082let hasNewValue = 1;
16083let opNewValue = 0;
16084let prefersSlot3 = 1;
16085}
16086def M2_mpyu_hl_s0 : HInst<
16087(outs IntRegs:$Rd32),
16088(ins IntRegs:$Rs32, IntRegs:$Rt32),
16089"$Rd32 = mpyu($Rs32.h,$Rt32.l)",
16090tc_c21d7447, TypeM>, Enc_5ab2be {
16091let Inst{7-5} = 0b010;
16092let Inst{13-13} = 0b0;
16093let Inst{31-21} = 0b11101100010;
16094let hasNewValue = 1;
16095let opNewValue = 0;
16096let prefersSlot3 = 1;
16097}
16098def M2_mpyu_hl_s1 : HInst<
16099(outs IntRegs:$Rd32),
16100(ins IntRegs:$Rs32, IntRegs:$Rt32),
16101"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16102tc_c21d7447, TypeM>, Enc_5ab2be {
16103let Inst{7-5} = 0b010;
16104let Inst{13-13} = 0b0;
16105let Inst{31-21} = 0b11101100110;
16106let hasNewValue = 1;
16107let opNewValue = 0;
16108let prefersSlot3 = 1;
16109}
16110def M2_mpyu_lh_s0 : HInst<
16111(outs IntRegs:$Rd32),
16112(ins IntRegs:$Rs32, IntRegs:$Rt32),
16113"$Rd32 = mpyu($Rs32.l,$Rt32.h)",
16114tc_c21d7447, TypeM>, Enc_5ab2be {
16115let Inst{7-5} = 0b001;
16116let Inst{13-13} = 0b0;
16117let Inst{31-21} = 0b11101100010;
16118let hasNewValue = 1;
16119let opNewValue = 0;
16120let prefersSlot3 = 1;
16121}
16122def M2_mpyu_lh_s1 : HInst<
16123(outs IntRegs:$Rd32),
16124(ins IntRegs:$Rs32, IntRegs:$Rt32),
16125"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16126tc_c21d7447, TypeM>, Enc_5ab2be {
16127let Inst{7-5} = 0b001;
16128let Inst{13-13} = 0b0;
16129let Inst{31-21} = 0b11101100110;
16130let hasNewValue = 1;
16131let opNewValue = 0;
16132let prefersSlot3 = 1;
16133}
16134def M2_mpyu_ll_s0 : HInst<
16135(outs IntRegs:$Rd32),
16136(ins IntRegs:$Rs32, IntRegs:$Rt32),
16137"$Rd32 = mpyu($Rs32.l,$Rt32.l)",
16138tc_c21d7447, TypeM>, Enc_5ab2be {
16139let Inst{7-5} = 0b000;
16140let Inst{13-13} = 0b0;
16141let Inst{31-21} = 0b11101100010;
16142let hasNewValue = 1;
16143let opNewValue = 0;
16144let prefersSlot3 = 1;
16145}
16146def M2_mpyu_ll_s1 : HInst<
16147(outs IntRegs:$Rd32),
16148(ins IntRegs:$Rs32, IntRegs:$Rt32),
16149"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16150tc_c21d7447, TypeM>, Enc_5ab2be {
16151let Inst{7-5} = 0b000;
16152let Inst{13-13} = 0b0;
16153let Inst{31-21} = 0b11101100110;
16154let hasNewValue = 1;
16155let opNewValue = 0;
16156let prefersSlot3 = 1;
16157}
16158def M2_mpyu_nac_hh_s0 : HInst<
16159(outs IntRegs:$Rx32),
16160(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16161"$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
16162tc_7f8ae742, TypeM>, Enc_2ae154 {
16163let Inst{7-5} = 0b011;
16164let Inst{13-13} = 0b0;
16165let Inst{31-21} = 0b11101110011;
16166let hasNewValue = 1;
16167let opNewValue = 0;
16168let prefersSlot3 = 1;
16169let Constraints = "$Rx32 = $Rx32in";
16170}
16171def M2_mpyu_nac_hh_s1 : HInst<
16172(outs IntRegs:$Rx32),
16173(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16174"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16175tc_7f8ae742, TypeM>, Enc_2ae154 {
16176let Inst{7-5} = 0b011;
16177let Inst{13-13} = 0b0;
16178let Inst{31-21} = 0b11101110111;
16179let hasNewValue = 1;
16180let opNewValue = 0;
16181let prefersSlot3 = 1;
16182let Constraints = "$Rx32 = $Rx32in";
16183}
16184def M2_mpyu_nac_hl_s0 : HInst<
16185(outs IntRegs:$Rx32),
16186(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16187"$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
16188tc_7f8ae742, TypeM>, Enc_2ae154 {
16189let Inst{7-5} = 0b010;
16190let Inst{13-13} = 0b0;
16191let Inst{31-21} = 0b11101110011;
16192let hasNewValue = 1;
16193let opNewValue = 0;
16194let prefersSlot3 = 1;
16195let Constraints = "$Rx32 = $Rx32in";
16196}
16197def M2_mpyu_nac_hl_s1 : HInst<
16198(outs IntRegs:$Rx32),
16199(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16200"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16201tc_7f8ae742, TypeM>, Enc_2ae154 {
16202let Inst{7-5} = 0b010;
16203let Inst{13-13} = 0b0;
16204let Inst{31-21} = 0b11101110111;
16205let hasNewValue = 1;
16206let opNewValue = 0;
16207let prefersSlot3 = 1;
16208let Constraints = "$Rx32 = $Rx32in";
16209}
16210def M2_mpyu_nac_lh_s0 : HInst<
16211(outs IntRegs:$Rx32),
16212(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16213"$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
16214tc_7f8ae742, TypeM>, Enc_2ae154 {
16215let Inst{7-5} = 0b001;
16216let Inst{13-13} = 0b0;
16217let Inst{31-21} = 0b11101110011;
16218let hasNewValue = 1;
16219let opNewValue = 0;
16220let prefersSlot3 = 1;
16221let Constraints = "$Rx32 = $Rx32in";
16222}
16223def M2_mpyu_nac_lh_s1 : HInst<
16224(outs IntRegs:$Rx32),
16225(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16226"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16227tc_7f8ae742, TypeM>, Enc_2ae154 {
16228let Inst{7-5} = 0b001;
16229let Inst{13-13} = 0b0;
16230let Inst{31-21} = 0b11101110111;
16231let hasNewValue = 1;
16232let opNewValue = 0;
16233let prefersSlot3 = 1;
16234let Constraints = "$Rx32 = $Rx32in";
16235}
16236def M2_mpyu_nac_ll_s0 : HInst<
16237(outs IntRegs:$Rx32),
16238(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16239"$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
16240tc_7f8ae742, TypeM>, Enc_2ae154 {
16241let Inst{7-5} = 0b000;
16242let Inst{13-13} = 0b0;
16243let Inst{31-21} = 0b11101110011;
16244let hasNewValue = 1;
16245let opNewValue = 0;
16246let prefersSlot3 = 1;
16247let Constraints = "$Rx32 = $Rx32in";
16248}
16249def M2_mpyu_nac_ll_s1 : HInst<
16250(outs IntRegs:$Rx32),
16251(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16252"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16253tc_7f8ae742, TypeM>, Enc_2ae154 {
16254let Inst{7-5} = 0b000;
16255let Inst{13-13} = 0b0;
16256let Inst{31-21} = 0b11101110111;
16257let hasNewValue = 1;
16258let opNewValue = 0;
16259let prefersSlot3 = 1;
16260let Constraints = "$Rx32 = $Rx32in";
16261}
16262def M2_mpyu_up : HInst<
16263(outs IntRegs:$Rd32),
16264(ins IntRegs:$Rs32, IntRegs:$Rt32),
16265"$Rd32 = mpyu($Rs32,$Rt32)",
16266tc_c21d7447, TypeM>, Enc_5ab2be {
16267let Inst{7-5} = 0b001;
16268let Inst{13-13} = 0b0;
16269let Inst{31-21} = 0b11101101010;
16270let hasNewValue = 1;
16271let opNewValue = 0;
16272let prefersSlot3 = 1;
16273}
16274def M2_mpyud_acc_hh_s0 : HInst<
16275(outs DoubleRegs:$Rxx32),
16276(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16277"$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
16278tc_7f8ae742, TypeM>, Enc_61f0b0 {
16279let Inst{7-5} = 0b011;
16280let Inst{13-13} = 0b0;
16281let Inst{31-21} = 0b11100110010;
16282let prefersSlot3 = 1;
16283let Constraints = "$Rxx32 = $Rxx32in";
16284}
16285def M2_mpyud_acc_hh_s1 : HInst<
16286(outs DoubleRegs:$Rxx32),
16287(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16288"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
16289tc_7f8ae742, TypeM>, Enc_61f0b0 {
16290let Inst{7-5} = 0b011;
16291let Inst{13-13} = 0b0;
16292let Inst{31-21} = 0b11100110110;
16293let prefersSlot3 = 1;
16294let Constraints = "$Rxx32 = $Rxx32in";
16295}
16296def M2_mpyud_acc_hl_s0 : HInst<
16297(outs DoubleRegs:$Rxx32),
16298(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16299"$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
16300tc_7f8ae742, TypeM>, Enc_61f0b0 {
16301let Inst{7-5} = 0b010;
16302let Inst{13-13} = 0b0;
16303let Inst{31-21} = 0b11100110010;
16304let prefersSlot3 = 1;
16305let Constraints = "$Rxx32 = $Rxx32in";
16306}
16307def M2_mpyud_acc_hl_s1 : HInst<
16308(outs DoubleRegs:$Rxx32),
16309(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16310"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
16311tc_7f8ae742, TypeM>, Enc_61f0b0 {
16312let Inst{7-5} = 0b010;
16313let Inst{13-13} = 0b0;
16314let Inst{31-21} = 0b11100110110;
16315let prefersSlot3 = 1;
16316let Constraints = "$Rxx32 = $Rxx32in";
16317}
16318def M2_mpyud_acc_lh_s0 : HInst<
16319(outs DoubleRegs:$Rxx32),
16320(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16321"$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
16322tc_7f8ae742, TypeM>, Enc_61f0b0 {
16323let Inst{7-5} = 0b001;
16324let Inst{13-13} = 0b0;
16325let Inst{31-21} = 0b11100110010;
16326let prefersSlot3 = 1;
16327let Constraints = "$Rxx32 = $Rxx32in";
16328}
16329def M2_mpyud_acc_lh_s1 : HInst<
16330(outs DoubleRegs:$Rxx32),
16331(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16332"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16333tc_7f8ae742, TypeM>, Enc_61f0b0 {
16334let Inst{7-5} = 0b001;
16335let Inst{13-13} = 0b0;
16336let Inst{31-21} = 0b11100110110;
16337let prefersSlot3 = 1;
16338let Constraints = "$Rxx32 = $Rxx32in";
16339}
16340def M2_mpyud_acc_ll_s0 : HInst<
16341(outs DoubleRegs:$Rxx32),
16342(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16343"$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
16344tc_7f8ae742, TypeM>, Enc_61f0b0 {
16345let Inst{7-5} = 0b000;
16346let Inst{13-13} = 0b0;
16347let Inst{31-21} = 0b11100110010;
16348let prefersSlot3 = 1;
16349let Constraints = "$Rxx32 = $Rxx32in";
16350}
16351def M2_mpyud_acc_ll_s1 : HInst<
16352(outs DoubleRegs:$Rxx32),
16353(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16354"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16355tc_7f8ae742, TypeM>, Enc_61f0b0 {
16356let Inst{7-5} = 0b000;
16357let Inst{13-13} = 0b0;
16358let Inst{31-21} = 0b11100110110;
16359let prefersSlot3 = 1;
16360let Constraints = "$Rxx32 = $Rxx32in";
16361}
16362def M2_mpyud_hh_s0 : HInst<
16363(outs DoubleRegs:$Rdd32),
16364(ins IntRegs:$Rs32, IntRegs:$Rt32),
16365"$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
16366tc_c21d7447, TypeM>, Enc_be32a5 {
16367let Inst{7-5} = 0b011;
16368let Inst{13-13} = 0b0;
16369let Inst{31-21} = 0b11100100010;
16370let prefersSlot3 = 1;
16371}
16372def M2_mpyud_hh_s1 : HInst<
16373(outs DoubleRegs:$Rdd32),
16374(ins IntRegs:$Rs32, IntRegs:$Rt32),
16375"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16376tc_c21d7447, TypeM>, Enc_be32a5 {
16377let Inst{7-5} = 0b011;
16378let Inst{13-13} = 0b0;
16379let Inst{31-21} = 0b11100100110;
16380let prefersSlot3 = 1;
16381}
16382def M2_mpyud_hl_s0 : HInst<
16383(outs DoubleRegs:$Rdd32),
16384(ins IntRegs:$Rs32, IntRegs:$Rt32),
16385"$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
16386tc_c21d7447, TypeM>, Enc_be32a5 {
16387let Inst{7-5} = 0b010;
16388let Inst{13-13} = 0b0;
16389let Inst{31-21} = 0b11100100010;
16390let prefersSlot3 = 1;
16391}
16392def M2_mpyud_hl_s1 : HInst<
16393(outs DoubleRegs:$Rdd32),
16394(ins IntRegs:$Rs32, IntRegs:$Rt32),
16395"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16396tc_c21d7447, TypeM>, Enc_be32a5 {
16397let Inst{7-5} = 0b010;
16398let Inst{13-13} = 0b0;
16399let Inst{31-21} = 0b11100100110;
16400let prefersSlot3 = 1;
16401}
16402def M2_mpyud_lh_s0 : HInst<
16403(outs DoubleRegs:$Rdd32),
16404(ins IntRegs:$Rs32, IntRegs:$Rt32),
16405"$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
16406tc_c21d7447, TypeM>, Enc_be32a5 {
16407let Inst{7-5} = 0b001;
16408let Inst{13-13} = 0b0;
16409let Inst{31-21} = 0b11100100010;
16410let prefersSlot3 = 1;
16411}
16412def M2_mpyud_lh_s1 : HInst<
16413(outs DoubleRegs:$Rdd32),
16414(ins IntRegs:$Rs32, IntRegs:$Rt32),
16415"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16416tc_c21d7447, TypeM>, Enc_be32a5 {
16417let Inst{7-5} = 0b001;
16418let Inst{13-13} = 0b0;
16419let Inst{31-21} = 0b11100100110;
16420let prefersSlot3 = 1;
16421}
16422def M2_mpyud_ll_s0 : HInst<
16423(outs DoubleRegs:$Rdd32),
16424(ins IntRegs:$Rs32, IntRegs:$Rt32),
16425"$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
16426tc_c21d7447, TypeM>, Enc_be32a5 {
16427let Inst{7-5} = 0b000;
16428let Inst{13-13} = 0b0;
16429let Inst{31-21} = 0b11100100010;
16430let prefersSlot3 = 1;
16431}
16432def M2_mpyud_ll_s1 : HInst<
16433(outs DoubleRegs:$Rdd32),
16434(ins IntRegs:$Rs32, IntRegs:$Rt32),
16435"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16436tc_c21d7447, TypeM>, Enc_be32a5 {
16437let Inst{7-5} = 0b000;
16438let Inst{13-13} = 0b0;
16439let Inst{31-21} = 0b11100100110;
16440let prefersSlot3 = 1;
16441}
16442def M2_mpyud_nac_hh_s0 : HInst<
16443(outs DoubleRegs:$Rxx32),
16444(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16445"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
16446tc_7f8ae742, TypeM>, Enc_61f0b0 {
16447let Inst{7-5} = 0b011;
16448let Inst{13-13} = 0b0;
16449let Inst{31-21} = 0b11100110011;
16450let prefersSlot3 = 1;
16451let Constraints = "$Rxx32 = $Rxx32in";
16452}
16453def M2_mpyud_nac_hh_s1 : HInst<
16454(outs DoubleRegs:$Rxx32),
16455(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16456"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16457tc_7f8ae742, TypeM>, Enc_61f0b0 {
16458let Inst{7-5} = 0b011;
16459let Inst{13-13} = 0b0;
16460let Inst{31-21} = 0b11100110111;
16461let prefersSlot3 = 1;
16462let Constraints = "$Rxx32 = $Rxx32in";
16463}
16464def M2_mpyud_nac_hl_s0 : HInst<
16465(outs DoubleRegs:$Rxx32),
16466(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16467"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
16468tc_7f8ae742, TypeM>, Enc_61f0b0 {
16469let Inst{7-5} = 0b010;
16470let Inst{13-13} = 0b0;
16471let Inst{31-21} = 0b11100110011;
16472let prefersSlot3 = 1;
16473let Constraints = "$Rxx32 = $Rxx32in";
16474}
16475def M2_mpyud_nac_hl_s1 : HInst<
16476(outs DoubleRegs:$Rxx32),
16477(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16478"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16479tc_7f8ae742, TypeM>, Enc_61f0b0 {
16480let Inst{7-5} = 0b010;
16481let Inst{13-13} = 0b0;
16482let Inst{31-21} = 0b11100110111;
16483let prefersSlot3 = 1;
16484let Constraints = "$Rxx32 = $Rxx32in";
16485}
16486def M2_mpyud_nac_lh_s0 : HInst<
16487(outs DoubleRegs:$Rxx32),
16488(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16489"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
16490tc_7f8ae742, TypeM>, Enc_61f0b0 {
16491let Inst{7-5} = 0b001;
16492let Inst{13-13} = 0b0;
16493let Inst{31-21} = 0b11100110011;
16494let prefersSlot3 = 1;
16495let Constraints = "$Rxx32 = $Rxx32in";
16496}
16497def M2_mpyud_nac_lh_s1 : HInst<
16498(outs DoubleRegs:$Rxx32),
16499(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16500"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16501tc_7f8ae742, TypeM>, Enc_61f0b0 {
16502let Inst{7-5} = 0b001;
16503let Inst{13-13} = 0b0;
16504let Inst{31-21} = 0b11100110111;
16505let prefersSlot3 = 1;
16506let Constraints = "$Rxx32 = $Rxx32in";
16507}
16508def M2_mpyud_nac_ll_s0 : HInst<
16509(outs DoubleRegs:$Rxx32),
16510(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16511"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
16512tc_7f8ae742, TypeM>, Enc_61f0b0 {
16513let Inst{7-5} = 0b000;
16514let Inst{13-13} = 0b0;
16515let Inst{31-21} = 0b11100110011;
16516let prefersSlot3 = 1;
16517let Constraints = "$Rxx32 = $Rxx32in";
16518}
16519def M2_mpyud_nac_ll_s1 : HInst<
16520(outs DoubleRegs:$Rxx32),
16521(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16522"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16523tc_7f8ae742, TypeM>, Enc_61f0b0 {
16524let Inst{7-5} = 0b000;
16525let Inst{13-13} = 0b0;
16526let Inst{31-21} = 0b11100110111;
16527let prefersSlot3 = 1;
16528let Constraints = "$Rxx32 = $Rxx32in";
16529}
16530def M2_mpyui : HInst<
16531(outs IntRegs:$Rd32),
16532(ins IntRegs:$Rs32, IntRegs:$Rt32),
16533"$Rd32 = mpyui($Rs32,$Rt32)",
16534tc_c21d7447, TypeM> {
16535let hasNewValue = 1;
16536let opNewValue = 0;
16537let isPseudo = 1;
16538let isCodeGenOnly = 1;
16539}
16540def M2_nacci : HInst<
16541(outs IntRegs:$Rx32),
16542(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16543"$Rx32 -= add($Rs32,$Rt32)",
16544tc_2c13e7f5, TypeM>, Enc_2ae154 {
16545let Inst{7-5} = 0b001;
16546let Inst{13-13} = 0b0;
16547let Inst{31-21} = 0b11101111100;
16548let hasNewValue = 1;
16549let opNewValue = 0;
16550let prefersSlot3 = 1;
16551let InputType = "reg";
16552let Constraints = "$Rx32 = $Rx32in";
16553}
16554def M2_naccii : HInst<
16555(outs IntRegs:$Rx32),
16556(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
16557"$Rx32 -= add($Rs32,#$Ii)",
16558tc_2c13e7f5, TypeM>, Enc_c90aca {
16559let Inst{13-13} = 0b0;
16560let Inst{31-21} = 0b11100010100;
16561let hasNewValue = 1;
16562let opNewValue = 0;
16563let prefersSlot3 = 1;
16564let InputType = "imm";
16565let isExtendable = 1;
16566let opExtendable = 3;
16567let isExtentSigned = 1;
16568let opExtentBits = 8;
16569let opExtentAlign = 0;
16570let Constraints = "$Rx32 = $Rx32in";
16571}
16572def M2_subacc : HInst<
16573(outs IntRegs:$Rx32),
16574(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
16575"$Rx32 += sub($Rt32,$Rs32)",
16576tc_2c13e7f5, TypeM>, Enc_a568d4 {
16577let Inst{7-5} = 0b011;
16578let Inst{13-13} = 0b0;
16579let Inst{31-21} = 0b11101111000;
16580let hasNewValue = 1;
16581let opNewValue = 0;
16582let prefersSlot3 = 1;
16583let InputType = "reg";
16584let Constraints = "$Rx32 = $Rx32in";
16585}
16586def M2_vabsdiffh : HInst<
16587(outs DoubleRegs:$Rdd32),
16588(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16589"$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
16590tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16591let Inst{7-5} = 0b000;
16592let Inst{13-13} = 0b0;
16593let Inst{31-21} = 0b11101000011;
16594let prefersSlot3 = 1;
16595}
16596def M2_vabsdiffw : HInst<
16597(outs DoubleRegs:$Rdd32),
16598(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16599"$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
16600tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16601let Inst{7-5} = 0b000;
16602let Inst{13-13} = 0b0;
16603let Inst{31-21} = 0b11101000001;
16604let prefersSlot3 = 1;
16605}
16606def M2_vcmac_s0_sat_i : HInst<
16607(outs DoubleRegs:$Rxx32),
16608(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16609"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
16610tc_7f8ae742, TypeM>, Enc_88c16c {
16611let Inst{7-5} = 0b100;
16612let Inst{13-13} = 0b0;
16613let Inst{31-21} = 0b11101010010;
16614let prefersSlot3 = 1;
16615let Defs = [USR_OVF];
16616let Constraints = "$Rxx32 = $Rxx32in";
16617}
16618def M2_vcmac_s0_sat_r : HInst<
16619(outs DoubleRegs:$Rxx32),
16620(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16621"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
16622tc_7f8ae742, TypeM>, Enc_88c16c {
16623let Inst{7-5} = 0b100;
16624let Inst{13-13} = 0b0;
16625let Inst{31-21} = 0b11101010001;
16626let prefersSlot3 = 1;
16627let Defs = [USR_OVF];
16628let Constraints = "$Rxx32 = $Rxx32in";
16629}
16630def M2_vcmpy_s0_sat_i : HInst<
16631(outs DoubleRegs:$Rdd32),
16632(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16633"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
16634tc_c21d7447, TypeM>, Enc_a56825 {
16635let Inst{7-5} = 0b110;
16636let Inst{13-13} = 0b0;
16637let Inst{31-21} = 0b11101000010;
16638let prefersSlot3 = 1;
16639let Defs = [USR_OVF];
16640}
16641def M2_vcmpy_s0_sat_r : HInst<
16642(outs DoubleRegs:$Rdd32),
16643(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16644"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
16645tc_c21d7447, TypeM>, Enc_a56825 {
16646let Inst{7-5} = 0b110;
16647let Inst{13-13} = 0b0;
16648let Inst{31-21} = 0b11101000001;
16649let prefersSlot3 = 1;
16650let Defs = [USR_OVF];
16651}
16652def M2_vcmpy_s1_sat_i : HInst<
16653(outs DoubleRegs:$Rdd32),
16654(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16655"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
16656tc_c21d7447, TypeM>, Enc_a56825 {
16657let Inst{7-5} = 0b110;
16658let Inst{13-13} = 0b0;
16659let Inst{31-21} = 0b11101000110;
16660let prefersSlot3 = 1;
16661let Defs = [USR_OVF];
16662}
16663def M2_vcmpy_s1_sat_r : HInst<
16664(outs DoubleRegs:$Rdd32),
16665(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16666"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
16667tc_c21d7447, TypeM>, Enc_a56825 {
16668let Inst{7-5} = 0b110;
16669let Inst{13-13} = 0b0;
16670let Inst{31-21} = 0b11101000101;
16671let prefersSlot3 = 1;
16672let Defs = [USR_OVF];
16673}
16674def M2_vdmacs_s0 : HInst<
16675(outs DoubleRegs:$Rxx32),
16676(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16677"$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
16678tc_7f8ae742, TypeM>, Enc_88c16c {
16679let Inst{7-5} = 0b100;
16680let Inst{13-13} = 0b0;
16681let Inst{31-21} = 0b11101010000;
16682let prefersSlot3 = 1;
16683let Defs = [USR_OVF];
16684let Constraints = "$Rxx32 = $Rxx32in";
16685}
16686def M2_vdmacs_s1 : HInst<
16687(outs DoubleRegs:$Rxx32),
16688(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16689"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
16690tc_7f8ae742, TypeM>, Enc_88c16c {
16691let Inst{7-5} = 0b100;
16692let Inst{13-13} = 0b0;
16693let Inst{31-21} = 0b11101010100;
16694let prefersSlot3 = 1;
16695let Defs = [USR_OVF];
16696let Constraints = "$Rxx32 = $Rxx32in";
16697}
16698def M2_vdmpyrs_s0 : HInst<
16699(outs IntRegs:$Rd32),
16700(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16701"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
16702tc_c21d7447, TypeM>, Enc_d2216a {
16703let Inst{7-5} = 0b000;
16704let Inst{13-13} = 0b0;
16705let Inst{31-21} = 0b11101001000;
16706let hasNewValue = 1;
16707let opNewValue = 0;
16708let prefersSlot3 = 1;
16709let Defs = [USR_OVF];
16710}
16711def M2_vdmpyrs_s1 : HInst<
16712(outs IntRegs:$Rd32),
16713(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16714"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
16715tc_c21d7447, TypeM>, Enc_d2216a {
16716let Inst{7-5} = 0b000;
16717let Inst{13-13} = 0b0;
16718let Inst{31-21} = 0b11101001100;
16719let hasNewValue = 1;
16720let opNewValue = 0;
16721let prefersSlot3 = 1;
16722let Defs = [USR_OVF];
16723}
16724def M2_vdmpys_s0 : HInst<
16725(outs DoubleRegs:$Rdd32),
16726(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16727"$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
16728tc_c21d7447, TypeM>, Enc_a56825 {
16729let Inst{7-5} = 0b100;
16730let Inst{13-13} = 0b0;
16731let Inst{31-21} = 0b11101000000;
16732let prefersSlot3 = 1;
16733let Defs = [USR_OVF];
16734}
16735def M2_vdmpys_s1 : HInst<
16736(outs DoubleRegs:$Rdd32),
16737(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16738"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
16739tc_c21d7447, TypeM>, Enc_a56825 {
16740let Inst{7-5} = 0b100;
16741let Inst{13-13} = 0b0;
16742let Inst{31-21} = 0b11101000100;
16743let prefersSlot3 = 1;
16744let Defs = [USR_OVF];
16745}
16746def M2_vmac2 : HInst<
16747(outs DoubleRegs:$Rxx32),
16748(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16749"$Rxx32 += vmpyh($Rs32,$Rt32)",
16750tc_7f8ae742, TypeM>, Enc_61f0b0 {
16751let Inst{7-5} = 0b001;
16752let Inst{13-13} = 0b0;
16753let Inst{31-21} = 0b11100111001;
16754let prefersSlot3 = 1;
16755let Constraints = "$Rxx32 = $Rxx32in";
16756}
16757def M2_vmac2es : HInst<
16758(outs DoubleRegs:$Rxx32),
16759(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16760"$Rxx32 += vmpyeh($Rss32,$Rtt32)",
16761tc_7f8ae742, TypeM>, Enc_88c16c {
16762let Inst{7-5} = 0b010;
16763let Inst{13-13} = 0b0;
16764let Inst{31-21} = 0b11101010001;
16765let prefersSlot3 = 1;
16766let Constraints = "$Rxx32 = $Rxx32in";
16767}
16768def M2_vmac2es_s0 : HInst<
16769(outs DoubleRegs:$Rxx32),
16770(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16771"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
16772tc_7f8ae742, TypeM>, Enc_88c16c {
16773let Inst{7-5} = 0b110;
16774let Inst{13-13} = 0b0;
16775let Inst{31-21} = 0b11101010000;
16776let prefersSlot3 = 1;
16777let Defs = [USR_OVF];
16778let Constraints = "$Rxx32 = $Rxx32in";
16779}
16780def M2_vmac2es_s1 : HInst<
16781(outs DoubleRegs:$Rxx32),
16782(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16783"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
16784tc_7f8ae742, TypeM>, Enc_88c16c {
16785let Inst{7-5} = 0b110;
16786let Inst{13-13} = 0b0;
16787let Inst{31-21} = 0b11101010100;
16788let prefersSlot3 = 1;
16789let Defs = [USR_OVF];
16790let Constraints = "$Rxx32 = $Rxx32in";
16791}
16792def M2_vmac2s_s0 : HInst<
16793(outs DoubleRegs:$Rxx32),
16794(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16795"$Rxx32 += vmpyh($Rs32,$Rt32):sat",
16796tc_7f8ae742, TypeM>, Enc_61f0b0 {
16797let Inst{7-5} = 0b101;
16798let Inst{13-13} = 0b0;
16799let Inst{31-21} = 0b11100111000;
16800let prefersSlot3 = 1;
16801let Defs = [USR_OVF];
16802let Constraints = "$Rxx32 = $Rxx32in";
16803}
16804def M2_vmac2s_s1 : HInst<
16805(outs DoubleRegs:$Rxx32),
16806(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16807"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
16808tc_7f8ae742, TypeM>, Enc_61f0b0 {
16809let Inst{7-5} = 0b101;
16810let Inst{13-13} = 0b0;
16811let Inst{31-21} = 0b11100111100;
16812let prefersSlot3 = 1;
16813let Defs = [USR_OVF];
16814let Constraints = "$Rxx32 = $Rxx32in";
16815}
16816def M2_vmac2su_s0 : HInst<
16817(outs DoubleRegs:$Rxx32),
16818(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16819"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
16820tc_7f8ae742, TypeM>, Enc_61f0b0 {
16821let Inst{7-5} = 0b101;
16822let Inst{13-13} = 0b0;
16823let Inst{31-21} = 0b11100111011;
16824let prefersSlot3 = 1;
16825let Defs = [USR_OVF];
16826let Constraints = "$Rxx32 = $Rxx32in";
16827}
16828def M2_vmac2su_s1 : HInst<
16829(outs DoubleRegs:$Rxx32),
16830(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16831"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
16832tc_7f8ae742, TypeM>, Enc_61f0b0 {
16833let Inst{7-5} = 0b101;
16834let Inst{13-13} = 0b0;
16835let Inst{31-21} = 0b11100111111;
16836let prefersSlot3 = 1;
16837let Defs = [USR_OVF];
16838let Constraints = "$Rxx32 = $Rxx32in";
16839}
16840def M2_vmpy2es_s0 : HInst<
16841(outs DoubleRegs:$Rdd32),
16842(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16843"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
16844tc_c21d7447, TypeM>, Enc_a56825 {
16845let Inst{7-5} = 0b110;
16846let Inst{13-13} = 0b0;
16847let Inst{31-21} = 0b11101000000;
16848let prefersSlot3 = 1;
16849let Defs = [USR_OVF];
16850}
16851def M2_vmpy2es_s1 : HInst<
16852(outs DoubleRegs:$Rdd32),
16853(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16854"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
16855tc_c21d7447, TypeM>, Enc_a56825 {
16856let Inst{7-5} = 0b110;
16857let Inst{13-13} = 0b0;
16858let Inst{31-21} = 0b11101000100;
16859let prefersSlot3 = 1;
16860let Defs = [USR_OVF];
16861}
16862def M2_vmpy2s_s0 : HInst<
16863(outs DoubleRegs:$Rdd32),
16864(ins IntRegs:$Rs32, IntRegs:$Rt32),
16865"$Rdd32 = vmpyh($Rs32,$Rt32):sat",
16866tc_c21d7447, TypeM>, Enc_be32a5 {
16867let Inst{7-5} = 0b101;
16868let Inst{13-13} = 0b0;
16869let Inst{31-21} = 0b11100101000;
16870let prefersSlot3 = 1;
16871let Defs = [USR_OVF];
16872}
16873def M2_vmpy2s_s0pack : HInst<
16874(outs IntRegs:$Rd32),
16875(ins IntRegs:$Rs32, IntRegs:$Rt32),
16876"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
16877tc_c21d7447, TypeM>, Enc_5ab2be {
16878let Inst{7-5} = 0b111;
16879let Inst{13-13} = 0b0;
16880let Inst{31-21} = 0b11101101001;
16881let hasNewValue = 1;
16882let opNewValue = 0;
16883let prefersSlot3 = 1;
16884let Defs = [USR_OVF];
16885}
16886def M2_vmpy2s_s1 : HInst<
16887(outs DoubleRegs:$Rdd32),
16888(ins IntRegs:$Rs32, IntRegs:$Rt32),
16889"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
16890tc_c21d7447, TypeM>, Enc_be32a5 {
16891let Inst{7-5} = 0b101;
16892let Inst{13-13} = 0b0;
16893let Inst{31-21} = 0b11100101100;
16894let prefersSlot3 = 1;
16895let Defs = [USR_OVF];
16896}
16897def M2_vmpy2s_s1pack : HInst<
16898(outs IntRegs:$Rd32),
16899(ins IntRegs:$Rs32, IntRegs:$Rt32),
16900"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
16901tc_c21d7447, TypeM>, Enc_5ab2be {
16902let Inst{7-5} = 0b111;
16903let Inst{13-13} = 0b0;
16904let Inst{31-21} = 0b11101101101;
16905let hasNewValue = 1;
16906let opNewValue = 0;
16907let prefersSlot3 = 1;
16908let Defs = [USR_OVF];
16909}
16910def M2_vmpy2su_s0 : HInst<
16911(outs DoubleRegs:$Rdd32),
16912(ins IntRegs:$Rs32, IntRegs:$Rt32),
16913"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
16914tc_c21d7447, TypeM>, Enc_be32a5 {
16915let Inst{7-5} = 0b111;
16916let Inst{13-13} = 0b0;
16917let Inst{31-21} = 0b11100101000;
16918let prefersSlot3 = 1;
16919let Defs = [USR_OVF];
16920}
16921def M2_vmpy2su_s1 : HInst<
16922(outs DoubleRegs:$Rdd32),
16923(ins IntRegs:$Rs32, IntRegs:$Rt32),
16924"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
16925tc_c21d7447, TypeM>, Enc_be32a5 {
16926let Inst{7-5} = 0b111;
16927let Inst{13-13} = 0b0;
16928let Inst{31-21} = 0b11100101100;
16929let prefersSlot3 = 1;
16930let Defs = [USR_OVF];
16931}
16932def M2_vraddh : HInst<
16933(outs IntRegs:$Rd32),
16934(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16935"$Rd32 = vraddh($Rss32,$Rtt32)",
16936tc_c21d7447, TypeM>, Enc_d2216a {
16937let Inst{7-5} = 0b111;
16938let Inst{13-13} = 0b0;
16939let Inst{31-21} = 0b11101001001;
16940let hasNewValue = 1;
16941let opNewValue = 0;
16942let prefersSlot3 = 1;
16943}
16944def M2_vradduh : HInst<
16945(outs IntRegs:$Rd32),
16946(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16947"$Rd32 = vradduh($Rss32,$Rtt32)",
16948tc_c21d7447, TypeM>, Enc_d2216a {
16949let Inst{7-5} = 0b001;
16950let Inst{13-13} = 0b0;
16951let Inst{31-21} = 0b11101001000;
16952let hasNewValue = 1;
16953let opNewValue = 0;
16954let prefersSlot3 = 1;
16955}
16956def M2_vrcmaci_s0 : HInst<
16957(outs DoubleRegs:$Rxx32),
16958(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16959"$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
16960tc_7f8ae742, TypeM>, Enc_88c16c {
16961let Inst{7-5} = 0b000;
16962let Inst{13-13} = 0b0;
16963let Inst{31-21} = 0b11101010000;
16964let prefersSlot3 = 1;
16965let Constraints = "$Rxx32 = $Rxx32in";
16966}
16967def M2_vrcmaci_s0c : HInst<
16968(outs DoubleRegs:$Rxx32),
16969(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16970"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
16971tc_7f8ae742, TypeM>, Enc_88c16c {
16972let Inst{7-5} = 0b000;
16973let Inst{13-13} = 0b0;
16974let Inst{31-21} = 0b11101010010;
16975let prefersSlot3 = 1;
16976let Constraints = "$Rxx32 = $Rxx32in";
16977}
16978def M2_vrcmacr_s0 : HInst<
16979(outs DoubleRegs:$Rxx32),
16980(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16981"$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
16982tc_7f8ae742, TypeM>, Enc_88c16c {
16983let Inst{7-5} = 0b001;
16984let Inst{13-13} = 0b0;
16985let Inst{31-21} = 0b11101010000;
16986let prefersSlot3 = 1;
16987let Constraints = "$Rxx32 = $Rxx32in";
16988}
16989def M2_vrcmacr_s0c : HInst<
16990(outs DoubleRegs:$Rxx32),
16991(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16992"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
16993tc_7f8ae742, TypeM>, Enc_88c16c {
16994let Inst{7-5} = 0b001;
16995let Inst{13-13} = 0b0;
16996let Inst{31-21} = 0b11101010011;
16997let prefersSlot3 = 1;
16998let Constraints = "$Rxx32 = $Rxx32in";
16999}
17000def M2_vrcmpyi_s0 : HInst<
17001(outs DoubleRegs:$Rdd32),
17002(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17003"$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
17004tc_c21d7447, TypeM>, Enc_a56825 {
17005let Inst{7-5} = 0b000;
17006let Inst{13-13} = 0b0;
17007let Inst{31-21} = 0b11101000000;
17008let prefersSlot3 = 1;
17009}
17010def M2_vrcmpyi_s0c : HInst<
17011(outs DoubleRegs:$Rdd32),
17012(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17013"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
17014tc_c21d7447, TypeM>, Enc_a56825 {
17015let Inst{7-5} = 0b000;
17016let Inst{13-13} = 0b0;
17017let Inst{31-21} = 0b11101000010;
17018let prefersSlot3 = 1;
17019}
17020def M2_vrcmpyr_s0 : HInst<
17021(outs DoubleRegs:$Rdd32),
17022(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17023"$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
17024tc_c21d7447, TypeM>, Enc_a56825 {
17025let Inst{7-5} = 0b001;
17026let Inst{13-13} = 0b0;
17027let Inst{31-21} = 0b11101000000;
17028let prefersSlot3 = 1;
17029}
17030def M2_vrcmpyr_s0c : HInst<
17031(outs DoubleRegs:$Rdd32),
17032(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17033"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
17034tc_c21d7447, TypeM>, Enc_a56825 {
17035let Inst{7-5} = 0b001;
17036let Inst{13-13} = 0b0;
17037let Inst{31-21} = 0b11101000011;
17038let prefersSlot3 = 1;
17039}
17040def M2_vrcmpys_acc_s1 : HInst<
17041(outs DoubleRegs:$Rxx32),
17042(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
17043"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
17044tc_7f8ae742, TypeM> {
17045let isPseudo = 1;
17046let Constraints = "$Rxx32 = $Rxx32in";
17047}
17048def M2_vrcmpys_acc_s1_h : HInst<
17049(outs DoubleRegs:$Rxx32),
17050(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17051"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
17052tc_7f8ae742, TypeM>, Enc_88c16c {
17053let Inst{7-5} = 0b100;
17054let Inst{13-13} = 0b0;
17055let Inst{31-21} = 0b11101010101;
17056let prefersSlot3 = 1;
17057let Defs = [USR_OVF];
17058let Constraints = "$Rxx32 = $Rxx32in";
17059}
17060def M2_vrcmpys_acc_s1_l : HInst<
17061(outs DoubleRegs:$Rxx32),
17062(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17063"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17064tc_7f8ae742, TypeM>, Enc_88c16c {
17065let Inst{7-5} = 0b100;
17066let Inst{13-13} = 0b0;
17067let Inst{31-21} = 0b11101010111;
17068let prefersSlot3 = 1;
17069let Defs = [USR_OVF];
17070let Constraints = "$Rxx32 = $Rxx32in";
17071}
17072def M2_vrcmpys_s1 : HInst<
17073(outs DoubleRegs:$Rdd32),
17074(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17075"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
17076tc_c21d7447, TypeM> {
17077let isPseudo = 1;
17078}
17079def M2_vrcmpys_s1_h : HInst<
17080(outs DoubleRegs:$Rdd32),
17081(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17082"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
17083tc_c21d7447, TypeM>, Enc_a56825 {
17084let Inst{7-5} = 0b100;
17085let Inst{13-13} = 0b0;
17086let Inst{31-21} = 0b11101000101;
17087let prefersSlot3 = 1;
17088let Defs = [USR_OVF];
17089}
17090def M2_vrcmpys_s1_l : HInst<
17091(outs DoubleRegs:$Rdd32),
17092(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17093"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17094tc_c21d7447, TypeM>, Enc_a56825 {
17095let Inst{7-5} = 0b100;
17096let Inst{13-13} = 0b0;
17097let Inst{31-21} = 0b11101000111;
17098let prefersSlot3 = 1;
17099let Defs = [USR_OVF];
17100}
17101def M2_vrcmpys_s1rp : HInst<
17102(outs IntRegs:$Rd32),
17103(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17104"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
17105tc_c21d7447, TypeM> {
17106let hasNewValue = 1;
17107let opNewValue = 0;
17108let isPseudo = 1;
17109}
17110def M2_vrcmpys_s1rp_h : HInst<
17111(outs IntRegs:$Rd32),
17112(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17113"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
17114tc_c21d7447, TypeM>, Enc_d2216a {
17115let Inst{7-5} = 0b110;
17116let Inst{13-13} = 0b0;
17117let Inst{31-21} = 0b11101001101;
17118let hasNewValue = 1;
17119let opNewValue = 0;
17120let prefersSlot3 = 1;
17121let Defs = [USR_OVF];
17122}
17123def M2_vrcmpys_s1rp_l : HInst<
17124(outs IntRegs:$Rd32),
17125(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17126"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
17127tc_c21d7447, TypeM>, Enc_d2216a {
17128let Inst{7-5} = 0b111;
17129let Inst{13-13} = 0b0;
17130let Inst{31-21} = 0b11101001101;
17131let hasNewValue = 1;
17132let opNewValue = 0;
17133let prefersSlot3 = 1;
17134let Defs = [USR_OVF];
17135}
17136def M2_vrmac_s0 : HInst<
17137(outs DoubleRegs:$Rxx32),
17138(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17139"$Rxx32 += vrmpyh($Rss32,$Rtt32)",
17140tc_7f8ae742, TypeM>, Enc_88c16c {
17141let Inst{7-5} = 0b010;
17142let Inst{13-13} = 0b0;
17143let Inst{31-21} = 0b11101010000;
17144let prefersSlot3 = 1;
17145let Constraints = "$Rxx32 = $Rxx32in";
17146}
17147def M2_vrmpy_s0 : HInst<
17148(outs DoubleRegs:$Rdd32),
17149(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17150"$Rdd32 = vrmpyh($Rss32,$Rtt32)",
17151tc_c21d7447, TypeM>, Enc_a56825 {
17152let Inst{7-5} = 0b010;
17153let Inst{13-13} = 0b0;
17154let Inst{31-21} = 0b11101000000;
17155let prefersSlot3 = 1;
17156}
17157def M2_xor_xacc : HInst<
17158(outs IntRegs:$Rx32),
17159(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17160"$Rx32 ^= xor($Rs32,$Rt32)",
17161tc_a4e22bbd, TypeM>, Enc_2ae154 {
17162let Inst{7-5} = 0b011;
17163let Inst{13-13} = 0b0;
17164let Inst{31-21} = 0b11101111100;
17165let hasNewValue = 1;
17166let opNewValue = 0;
17167let prefersSlot3 = 1;
17168let InputType = "reg";
17169let Constraints = "$Rx32 = $Rx32in";
17170}
17171def M4_and_and : HInst<
17172(outs IntRegs:$Rx32),
17173(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17174"$Rx32 &= and($Rs32,$Rt32)",
17175tc_a4e22bbd, TypeM>, Enc_2ae154 {
17176let Inst{7-5} = 0b000;
17177let Inst{13-13} = 0b0;
17178let Inst{31-21} = 0b11101111010;
17179let hasNewValue = 1;
17180let opNewValue = 0;
17181let prefersSlot3 = 1;
17182let InputType = "reg";
17183let Constraints = "$Rx32 = $Rx32in";
17184}
17185def M4_and_andn : HInst<
17186(outs IntRegs:$Rx32),
17187(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17188"$Rx32 &= and($Rs32,~$Rt32)",
17189tc_a4e22bbd, TypeM>, Enc_2ae154 {
17190let Inst{7-5} = 0b001;
17191let Inst{13-13} = 0b0;
17192let Inst{31-21} = 0b11101111001;
17193let hasNewValue = 1;
17194let opNewValue = 0;
17195let prefersSlot3 = 1;
17196let InputType = "reg";
17197let Constraints = "$Rx32 = $Rx32in";
17198}
17199def M4_and_or : HInst<
17200(outs IntRegs:$Rx32),
17201(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17202"$Rx32 &= or($Rs32,$Rt32)",
17203tc_a4e22bbd, TypeM>, Enc_2ae154 {
17204let Inst{7-5} = 0b001;
17205let Inst{13-13} = 0b0;
17206let Inst{31-21} = 0b11101111010;
17207let hasNewValue = 1;
17208let opNewValue = 0;
17209let prefersSlot3 = 1;
17210let InputType = "reg";
17211let Constraints = "$Rx32 = $Rx32in";
17212}
17213def M4_and_xor : HInst<
17214(outs IntRegs:$Rx32),
17215(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17216"$Rx32 &= xor($Rs32,$Rt32)",
17217tc_a4e22bbd, TypeM>, Enc_2ae154 {
17218let Inst{7-5} = 0b010;
17219let Inst{13-13} = 0b0;
17220let Inst{31-21} = 0b11101111010;
17221let hasNewValue = 1;
17222let opNewValue = 0;
17223let prefersSlot3 = 1;
17224let InputType = "reg";
17225let Constraints = "$Rx32 = $Rx32in";
17226}
17227def M4_cmpyi_wh : HInst<
17228(outs IntRegs:$Rd32),
17229(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17230"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
17231tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17232let Inst{7-5} = 0b100;
17233let Inst{13-13} = 0b0;
17234let Inst{31-21} = 0b11000101000;
17235let hasNewValue = 1;
17236let opNewValue = 0;
17237let prefersSlot3 = 1;
17238let Defs = [USR_OVF];
17239}
17240def M4_cmpyi_whc : HInst<
17241(outs IntRegs:$Rd32),
17242(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17243"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
17244tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17245let Inst{7-5} = 0b101;
17246let Inst{13-13} = 0b0;
17247let Inst{31-21} = 0b11000101000;
17248let hasNewValue = 1;
17249let opNewValue = 0;
17250let prefersSlot3 = 1;
17251let Defs = [USR_OVF];
17252}
17253def M4_cmpyr_wh : HInst<
17254(outs IntRegs:$Rd32),
17255(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17256"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
17257tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17258let Inst{7-5} = 0b110;
17259let Inst{13-13} = 0b0;
17260let Inst{31-21} = 0b11000101000;
17261let hasNewValue = 1;
17262let opNewValue = 0;
17263let prefersSlot3 = 1;
17264let Defs = [USR_OVF];
17265}
17266def M4_cmpyr_whc : HInst<
17267(outs IntRegs:$Rd32),
17268(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17269"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
17270tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17271let Inst{7-5} = 0b111;
17272let Inst{13-13} = 0b0;
17273let Inst{31-21} = 0b11000101000;
17274let hasNewValue = 1;
17275let opNewValue = 0;
17276let prefersSlot3 = 1;
17277let Defs = [USR_OVF];
17278}
17279def M4_mac_up_s1_sat : HInst<
17280(outs IntRegs:$Rx32),
17281(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17282"$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
17283tc_7f8ae742, TypeM>, Enc_2ae154 {
17284let Inst{7-5} = 0b000;
17285let Inst{13-13} = 0b0;
17286let Inst{31-21} = 0b11101111011;
17287let hasNewValue = 1;
17288let opNewValue = 0;
17289let prefersSlot3 = 1;
17290let Defs = [USR_OVF];
17291let InputType = "reg";
17292let Constraints = "$Rx32 = $Rx32in";
17293}
17294def M4_mpyri_addi : HInst<
17295(outs IntRegs:$Rd32),
17296(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
17297"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
17298tc_a154b476, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel {
17299let Inst{31-24} = 0b11011000;
17300let hasNewValue = 1;
17301let opNewValue = 0;
17302let prefersSlot3 = 1;
17303let CextOpcode = "M4_mpyri_addr";
17304let isExtendable = 1;
17305let opExtendable = 1;
17306let isExtentSigned = 0;
17307let opExtentBits = 6;
17308let opExtentAlign = 0;
17309}
17310def M4_mpyri_addr : HInst<
17311(outs IntRegs:$Rd32),
17312(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
17313"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
17314tc_a154b476, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel {
17315let Inst{31-23} = 0b110111111;
17316let hasNewValue = 1;
17317let opNewValue = 0;
17318let prefersSlot3 = 1;
17319let CextOpcode = "M4_mpyri_addr";
17320let InputType = "imm";
17321let isExtendable = 1;
17322let opExtendable = 3;
17323let isExtentSigned = 0;
17324let opExtentBits = 6;
17325let opExtentAlign = 0;
17326}
17327def M4_mpyri_addr_u2 : HInst<
17328(outs IntRegs:$Rd32),
17329(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
17330"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17331tc_503ce0f3, TypeALU64>, Enc_277737, Requires<[UseCompound]> {
17332let Inst{31-23} = 0b110111110;
17333let hasNewValue = 1;
17334let opNewValue = 0;
17335let prefersSlot3 = 1;
17336}
17337def M4_mpyrr_addi : HInst<
17338(outs IntRegs:$Rd32),
17339(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
17340"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17341tc_7f8ae742, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel {
17342let Inst{31-23} = 0b110101110;
17343let hasNewValue = 1;
17344let opNewValue = 0;
17345let prefersSlot3 = 1;
17346let CextOpcode = "M4_mpyrr_addr";
17347let InputType = "imm";
17348let isExtendable = 1;
17349let opExtendable = 1;
17350let isExtentSigned = 0;
17351let opExtentBits = 6;
17352let opExtentAlign = 0;
17353}
17354def M4_mpyrr_addr : HInst<
17355(outs IntRegs:$Ry32),
17356(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
17357"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17358tc_7f8ae742, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel {
17359let Inst{7-5} = 0b000;
17360let Inst{13-13} = 0b0;
17361let Inst{31-21} = 0b11100011000;
17362let hasNewValue = 1;
17363let opNewValue = 0;
17364let prefersSlot3 = 1;
17365let CextOpcode = "M4_mpyrr_addr";
17366let InputType = "reg";
17367let Constraints = "$Ry32 = $Ry32in";
17368}
17369def M4_nac_up_s1_sat : HInst<
17370(outs IntRegs:$Rx32),
17371(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17372"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
17373tc_7f8ae742, TypeM>, Enc_2ae154 {
17374let Inst{7-5} = 0b001;
17375let Inst{13-13} = 0b0;
17376let Inst{31-21} = 0b11101111011;
17377let hasNewValue = 1;
17378let opNewValue = 0;
17379let prefersSlot3 = 1;
17380let Defs = [USR_OVF];
17381let InputType = "reg";
17382let Constraints = "$Rx32 = $Rx32in";
17383}
17384def M4_or_and : HInst<
17385(outs IntRegs:$Rx32),
17386(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17387"$Rx32 |= and($Rs32,$Rt32)",
17388tc_a4e22bbd, TypeM>, Enc_2ae154 {
17389let Inst{7-5} = 0b011;
17390let Inst{13-13} = 0b0;
17391let Inst{31-21} = 0b11101111010;
17392let hasNewValue = 1;
17393let opNewValue = 0;
17394let prefersSlot3 = 1;
17395let InputType = "reg";
17396let Constraints = "$Rx32 = $Rx32in";
17397}
17398def M4_or_andn : HInst<
17399(outs IntRegs:$Rx32),
17400(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17401"$Rx32 |= and($Rs32,~$Rt32)",
17402tc_a4e22bbd, TypeM>, Enc_2ae154 {
17403let Inst{7-5} = 0b000;
17404let Inst{13-13} = 0b0;
17405let Inst{31-21} = 0b11101111001;
17406let hasNewValue = 1;
17407let opNewValue = 0;
17408let prefersSlot3 = 1;
17409let InputType = "reg";
17410let Constraints = "$Rx32 = $Rx32in";
17411}
17412def M4_or_or : HInst<
17413(outs IntRegs:$Rx32),
17414(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17415"$Rx32 |= or($Rs32,$Rt32)",
17416tc_a4e22bbd, TypeM>, Enc_2ae154 {
17417let Inst{7-5} = 0b000;
17418let Inst{13-13} = 0b0;
17419let Inst{31-21} = 0b11101111110;
17420let hasNewValue = 1;
17421let opNewValue = 0;
17422let prefersSlot3 = 1;
17423let InputType = "reg";
17424let Constraints = "$Rx32 = $Rx32in";
17425}
17426def M4_or_xor : HInst<
17427(outs IntRegs:$Rx32),
17428(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17429"$Rx32 |= xor($Rs32,$Rt32)",
17430tc_a4e22bbd, TypeM>, Enc_2ae154 {
17431let Inst{7-5} = 0b001;
17432let Inst{13-13} = 0b0;
17433let Inst{31-21} = 0b11101111110;
17434let hasNewValue = 1;
17435let opNewValue = 0;
17436let prefersSlot3 = 1;
17437let InputType = "reg";
17438let Constraints = "$Rx32 = $Rx32in";
17439}
17440def M4_pmpyw : HInst<
17441(outs DoubleRegs:$Rdd32),
17442(ins IntRegs:$Rs32, IntRegs:$Rt32),
17443"$Rdd32 = pmpyw($Rs32,$Rt32)",
17444tc_c21d7447, TypeM>, Enc_be32a5 {
17445let Inst{7-5} = 0b111;
17446let Inst{13-13} = 0b0;
17447let Inst{31-21} = 0b11100101010;
17448let prefersSlot3 = 1;
17449}
17450def M4_pmpyw_acc : HInst<
17451(outs DoubleRegs:$Rxx32),
17452(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17453"$Rxx32 ^= pmpyw($Rs32,$Rt32)",
17454tc_7f8ae742, TypeM>, Enc_61f0b0 {
17455let Inst{7-5} = 0b111;
17456let Inst{13-13} = 0b0;
17457let Inst{31-21} = 0b11100111001;
17458let prefersSlot3 = 1;
17459let Constraints = "$Rxx32 = $Rxx32in";
17460}
17461def M4_vpmpyh : HInst<
17462(outs DoubleRegs:$Rdd32),
17463(ins IntRegs:$Rs32, IntRegs:$Rt32),
17464"$Rdd32 = vpmpyh($Rs32,$Rt32)",
17465tc_c21d7447, TypeM>, Enc_be32a5 {
17466let Inst{7-5} = 0b111;
17467let Inst{13-13} = 0b0;
17468let Inst{31-21} = 0b11100101110;
17469let prefersSlot3 = 1;
17470}
17471def M4_vpmpyh_acc : HInst<
17472(outs DoubleRegs:$Rxx32),
17473(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17474"$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
17475tc_7f8ae742, TypeM>, Enc_61f0b0 {
17476let Inst{7-5} = 0b111;
17477let Inst{13-13} = 0b0;
17478let Inst{31-21} = 0b11100111101;
17479let prefersSlot3 = 1;
17480let Constraints = "$Rxx32 = $Rxx32in";
17481}
17482def M4_vrmpyeh_acc_s0 : HInst<
17483(outs DoubleRegs:$Rxx32),
17484(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17485"$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
17486tc_7f8ae742, TypeM>, Enc_88c16c {
17487let Inst{7-5} = 0b110;
17488let Inst{13-13} = 0b0;
17489let Inst{31-21} = 0b11101010001;
17490let prefersSlot3 = 1;
17491let Constraints = "$Rxx32 = $Rxx32in";
17492}
17493def M4_vrmpyeh_acc_s1 : HInst<
17494(outs DoubleRegs:$Rxx32),
17495(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17496"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
17497tc_7f8ae742, TypeM>, Enc_88c16c {
17498let Inst{7-5} = 0b110;
17499let Inst{13-13} = 0b0;
17500let Inst{31-21} = 0b11101010101;
17501let prefersSlot3 = 1;
17502let Constraints = "$Rxx32 = $Rxx32in";
17503}
17504def M4_vrmpyeh_s0 : HInst<
17505(outs DoubleRegs:$Rdd32),
17506(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17507"$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
17508tc_c21d7447, TypeM>, Enc_a56825 {
17509let Inst{7-5} = 0b100;
17510let Inst{13-13} = 0b0;
17511let Inst{31-21} = 0b11101000010;
17512let prefersSlot3 = 1;
17513}
17514def M4_vrmpyeh_s1 : HInst<
17515(outs DoubleRegs:$Rdd32),
17516(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17517"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
17518tc_c21d7447, TypeM>, Enc_a56825 {
17519let Inst{7-5} = 0b100;
17520let Inst{13-13} = 0b0;
17521let Inst{31-21} = 0b11101000110;
17522let prefersSlot3 = 1;
17523}
17524def M4_vrmpyoh_acc_s0 : HInst<
17525(outs DoubleRegs:$Rxx32),
17526(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17527"$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
17528tc_7f8ae742, TypeM>, Enc_88c16c {
17529let Inst{7-5} = 0b110;
17530let Inst{13-13} = 0b0;
17531let Inst{31-21} = 0b11101010011;
17532let prefersSlot3 = 1;
17533let Constraints = "$Rxx32 = $Rxx32in";
17534}
17535def M4_vrmpyoh_acc_s1 : HInst<
17536(outs DoubleRegs:$Rxx32),
17537(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17538"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
17539tc_7f8ae742, TypeM>, Enc_88c16c {
17540let Inst{7-5} = 0b110;
17541let Inst{13-13} = 0b0;
17542let Inst{31-21} = 0b11101010111;
17543let prefersSlot3 = 1;
17544let Constraints = "$Rxx32 = $Rxx32in";
17545}
17546def M4_vrmpyoh_s0 : HInst<
17547(outs DoubleRegs:$Rdd32),
17548(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17549"$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
17550tc_c21d7447, TypeM>, Enc_a56825 {
17551let Inst{7-5} = 0b010;
17552let Inst{13-13} = 0b0;
17553let Inst{31-21} = 0b11101000001;
17554let prefersSlot3 = 1;
17555}
17556def M4_vrmpyoh_s1 : HInst<
17557(outs DoubleRegs:$Rdd32),
17558(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17559"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
17560tc_c21d7447, TypeM>, Enc_a56825 {
17561let Inst{7-5} = 0b010;
17562let Inst{13-13} = 0b0;
17563let Inst{31-21} = 0b11101000101;
17564let prefersSlot3 = 1;
17565}
17566def M4_xor_and : HInst<
17567(outs IntRegs:$Rx32),
17568(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17569"$Rx32 ^= and($Rs32,$Rt32)",
17570tc_a4e22bbd, TypeM>, Enc_2ae154 {
17571let Inst{7-5} = 0b010;
17572let Inst{13-13} = 0b0;
17573let Inst{31-21} = 0b11101111110;
17574let hasNewValue = 1;
17575let opNewValue = 0;
17576let prefersSlot3 = 1;
17577let InputType = "reg";
17578let Constraints = "$Rx32 = $Rx32in";
17579}
17580def M4_xor_andn : HInst<
17581(outs IntRegs:$Rx32),
17582(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17583"$Rx32 ^= and($Rs32,~$Rt32)",
17584tc_a4e22bbd, TypeM>, Enc_2ae154 {
17585let Inst{7-5} = 0b010;
17586let Inst{13-13} = 0b0;
17587let Inst{31-21} = 0b11101111001;
17588let hasNewValue = 1;
17589let opNewValue = 0;
17590let prefersSlot3 = 1;
17591let InputType = "reg";
17592let Constraints = "$Rx32 = $Rx32in";
17593}
17594def M4_xor_or : HInst<
17595(outs IntRegs:$Rx32),
17596(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17597"$Rx32 ^= or($Rs32,$Rt32)",
17598tc_a4e22bbd, TypeM>, Enc_2ae154 {
17599let Inst{7-5} = 0b011;
17600let Inst{13-13} = 0b0;
17601let Inst{31-21} = 0b11101111110;
17602let hasNewValue = 1;
17603let opNewValue = 0;
17604let prefersSlot3 = 1;
17605let InputType = "reg";
17606let Constraints = "$Rx32 = $Rx32in";
17607}
17608def M4_xor_xacc : HInst<
17609(outs DoubleRegs:$Rxx32),
17610(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17611"$Rxx32 ^= xor($Rss32,$Rtt32)",
17612tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
17613let Inst{7-5} = 0b000;
17614let Inst{13-13} = 0b0;
17615let Inst{31-21} = 0b11001010100;
17616let prefersSlot3 = 1;
17617let Constraints = "$Rxx32 = $Rxx32in";
17618}
17619def M5_vdmacbsu : HInst<
17620(outs DoubleRegs:$Rxx32),
17621(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17622"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
17623tc_7f8ae742, TypeM>, Enc_88c16c {
17624let Inst{7-5} = 0b001;
17625let Inst{13-13} = 0b0;
17626let Inst{31-21} = 0b11101010001;
17627let prefersSlot3 = 1;
17628let Defs = [USR_OVF];
17629let Constraints = "$Rxx32 = $Rxx32in";
17630}
17631def M5_vdmpybsu : HInst<
17632(outs DoubleRegs:$Rdd32),
17633(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17634"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
17635tc_c21d7447, TypeM>, Enc_a56825 {
17636let Inst{7-5} = 0b001;
17637let Inst{13-13} = 0b0;
17638let Inst{31-21} = 0b11101000101;
17639let prefersSlot3 = 1;
17640let Defs = [USR_OVF];
17641}
17642def M5_vmacbsu : HInst<
17643(outs DoubleRegs:$Rxx32),
17644(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17645"$Rxx32 += vmpybsu($Rs32,$Rt32)",
17646tc_7f8ae742, TypeM>, Enc_61f0b0 {
17647let Inst{7-5} = 0b001;
17648let Inst{13-13} = 0b0;
17649let Inst{31-21} = 0b11100111110;
17650let prefersSlot3 = 1;
17651let Constraints = "$Rxx32 = $Rxx32in";
17652}
17653def M5_vmacbuu : HInst<
17654(outs DoubleRegs:$Rxx32),
17655(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17656"$Rxx32 += vmpybu($Rs32,$Rt32)",
17657tc_7f8ae742, TypeM>, Enc_61f0b0 {
17658let Inst{7-5} = 0b001;
17659let Inst{13-13} = 0b0;
17660let Inst{31-21} = 0b11100111100;
17661let prefersSlot3 = 1;
17662let Constraints = "$Rxx32 = $Rxx32in";
17663}
17664def M5_vmpybsu : HInst<
17665(outs DoubleRegs:$Rdd32),
17666(ins IntRegs:$Rs32, IntRegs:$Rt32),
17667"$Rdd32 = vmpybsu($Rs32,$Rt32)",
17668tc_c21d7447, TypeM>, Enc_be32a5 {
17669let Inst{7-5} = 0b001;
17670let Inst{13-13} = 0b0;
17671let Inst{31-21} = 0b11100101010;
17672let prefersSlot3 = 1;
17673}
17674def M5_vmpybuu : HInst<
17675(outs DoubleRegs:$Rdd32),
17676(ins IntRegs:$Rs32, IntRegs:$Rt32),
17677"$Rdd32 = vmpybu($Rs32,$Rt32)",
17678tc_c21d7447, TypeM>, Enc_be32a5 {
17679let Inst{7-5} = 0b001;
17680let Inst{13-13} = 0b0;
17681let Inst{31-21} = 0b11100101100;
17682let prefersSlot3 = 1;
17683}
17684def M5_vrmacbsu : HInst<
17685(outs DoubleRegs:$Rxx32),
17686(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17687"$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
17688tc_7f8ae742, TypeM>, Enc_88c16c {
17689let Inst{7-5} = 0b001;
17690let Inst{13-13} = 0b0;
17691let Inst{31-21} = 0b11101010110;
17692let prefersSlot3 = 1;
17693let Constraints = "$Rxx32 = $Rxx32in";
17694}
17695def M5_vrmacbuu : HInst<
17696(outs DoubleRegs:$Rxx32),
17697(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17698"$Rxx32 += vrmpybu($Rss32,$Rtt32)",
17699tc_7f8ae742, TypeM>, Enc_88c16c {
17700let Inst{7-5} = 0b001;
17701let Inst{13-13} = 0b0;
17702let Inst{31-21} = 0b11101010100;
17703let prefersSlot3 = 1;
17704let Constraints = "$Rxx32 = $Rxx32in";
17705}
17706def M5_vrmpybsu : HInst<
17707(outs DoubleRegs:$Rdd32),
17708(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17709"$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
17710tc_c21d7447, TypeM>, Enc_a56825 {
17711let Inst{7-5} = 0b001;
17712let Inst{13-13} = 0b0;
17713let Inst{31-21} = 0b11101000110;
17714let prefersSlot3 = 1;
17715}
17716def M5_vrmpybuu : HInst<
17717(outs DoubleRegs:$Rdd32),
17718(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17719"$Rdd32 = vrmpybu($Rss32,$Rtt32)",
17720tc_c21d7447, TypeM>, Enc_a56825 {
17721let Inst{7-5} = 0b001;
17722let Inst{13-13} = 0b0;
17723let Inst{31-21} = 0b11101000100;
17724let prefersSlot3 = 1;
17725}
17726def M6_vabsdiffb : HInst<
17727(outs DoubleRegs:$Rdd32),
17728(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17729"$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
17730tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17731let Inst{7-5} = 0b000;
17732let Inst{13-13} = 0b0;
17733let Inst{31-21} = 0b11101000111;
17734let prefersSlot3 = 1;
17735}
17736def M6_vabsdiffub : HInst<
17737(outs DoubleRegs:$Rdd32),
17738(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17739"$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
17740tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17741let Inst{7-5} = 0b000;
17742let Inst{13-13} = 0b0;
17743let Inst{31-21} = 0b11101000101;
17744let prefersSlot3 = 1;
17745}
17746def M7_dcmpyiw : HInst<
17747(outs DoubleRegs:$Rdd32),
17748(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17749"$Rdd32 = cmpyiw($Rss32,$Rtt32)",
17750tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17751let Inst{7-5} = 0b010;
17752let Inst{13-13} = 0b0;
17753let Inst{31-21} = 0b11101000011;
17754let prefersSlot3 = 1;
17755}
17756def M7_dcmpyiw_acc : HInst<
17757(outs DoubleRegs:$Rxx32),
17758(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17759"$Rxx32 += cmpyiw($Rss32,$Rtt32)",
17760tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17761let Inst{7-5} = 0b010;
17762let Inst{13-13} = 0b0;
17763let Inst{31-21} = 0b11101010011;
17764let prefersSlot3 = 1;
17765let Constraints = "$Rxx32 = $Rxx32in";
17766}
17767def M7_dcmpyiwc : HInst<
17768(outs DoubleRegs:$Rdd32),
17769(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17770"$Rdd32 = cmpyiw($Rss32,$Rtt32*)",
17771tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17772let Inst{7-5} = 0b010;
17773let Inst{13-13} = 0b0;
17774let Inst{31-21} = 0b11101000111;
17775let prefersSlot3 = 1;
17776}
17777def M7_dcmpyiwc_acc : HInst<
17778(outs DoubleRegs:$Rxx32),
17779(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17780"$Rxx32 += cmpyiw($Rss32,$Rtt32*)",
17781tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17782let Inst{7-5} = 0b110;
17783let Inst{13-13} = 0b0;
17784let Inst{31-21} = 0b11101010010;
17785let prefersSlot3 = 1;
17786let Constraints = "$Rxx32 = $Rxx32in";
17787}
17788def M7_dcmpyrw : HInst<
17789(outs DoubleRegs:$Rdd32),
17790(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17791"$Rdd32 = cmpyrw($Rss32,$Rtt32)",
17792tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17793let Inst{7-5} = 0b010;
17794let Inst{13-13} = 0b0;
17795let Inst{31-21} = 0b11101000100;
17796let prefersSlot3 = 1;
17797}
17798def M7_dcmpyrw_acc : HInst<
17799(outs DoubleRegs:$Rxx32),
17800(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17801"$Rxx32 += cmpyrw($Rss32,$Rtt32)",
17802tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17803let Inst{7-5} = 0b010;
17804let Inst{13-13} = 0b0;
17805let Inst{31-21} = 0b11101010100;
17806let prefersSlot3 = 1;
17807let Constraints = "$Rxx32 = $Rxx32in";
17808}
17809def M7_dcmpyrwc : HInst<
17810(outs DoubleRegs:$Rdd32),
17811(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17812"$Rdd32 = cmpyrw($Rss32,$Rtt32*)",
17813tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17814let Inst{7-5} = 0b010;
17815let Inst{13-13} = 0b0;
17816let Inst{31-21} = 0b11101000110;
17817let prefersSlot3 = 1;
17818}
17819def M7_dcmpyrwc_acc : HInst<
17820(outs DoubleRegs:$Rxx32),
17821(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17822"$Rxx32 += cmpyrw($Rss32,$Rtt32*)",
17823tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17824let Inst{7-5} = 0b010;
17825let Inst{13-13} = 0b0;
17826let Inst{31-21} = 0b11101010110;
17827let prefersSlot3 = 1;
17828let Constraints = "$Rxx32 = $Rxx32in";
17829}
17830def M7_vdmpy : HInst<
17831(outs DoubleRegs:$Rdd32),
17832(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17833"$Rdd32 = vdmpyw($Rss32,$Rtt32)",
17834tc_5a4b5e58, TypeM>, Requires<[HasV67]> {
17835let isPseudo = 1;
17836let isCodeGenOnly = 1;
17837}
17838def M7_vdmpy_acc : HInst<
17839(outs DoubleRegs:$Rxx32),
17840(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17841"$Rxx32 += vdmpyw($Rss32,$Rtt32)",
17842tc_197dce51, TypeM>, Requires<[HasV67]> {
17843let isPseudo = 1;
17844let isCodeGenOnly = 1;
17845let Constraints = "$Rxx32 = $Rxx32in";
17846}
17847def M7_wcmpyiw : HInst<
17848(outs IntRegs:$Rd32),
17849(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17850"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:sat",
17851tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17852let Inst{7-5} = 0b000;
17853let Inst{13-13} = 0b0;
17854let Inst{31-21} = 0b11101001001;
17855let hasNewValue = 1;
17856let opNewValue = 0;
17857let prefersSlot3 = 1;
17858let Defs = [USR_OVF];
17859}
17860def M7_wcmpyiw_rnd : HInst<
17861(outs IntRegs:$Rd32),
17862(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17863"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:rnd:sat",
17864tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17865let Inst{7-5} = 0b000;
17866let Inst{13-13} = 0b0;
17867let Inst{31-21} = 0b11101001101;
17868let hasNewValue = 1;
17869let opNewValue = 0;
17870let prefersSlot3 = 1;
17871let Defs = [USR_OVF];
17872}
17873def M7_wcmpyiwc : HInst<
17874(outs IntRegs:$Rd32),
17875(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17876"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:sat",
17877tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17878let Inst{7-5} = 0b100;
17879let Inst{13-13} = 0b0;
17880let Inst{31-21} = 0b11101001000;
17881let hasNewValue = 1;
17882let opNewValue = 0;
17883let prefersSlot3 = 1;
17884let Defs = [USR_OVF];
17885}
17886def M7_wcmpyiwc_rnd : HInst<
17887(outs IntRegs:$Rd32),
17888(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17889"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:rnd:sat",
17890tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17891let Inst{7-5} = 0b100;
17892let Inst{13-13} = 0b0;
17893let Inst{31-21} = 0b11101001100;
17894let hasNewValue = 1;
17895let opNewValue = 0;
17896let prefersSlot3 = 1;
17897let Defs = [USR_OVF];
17898}
17899def M7_wcmpyrw : HInst<
17900(outs IntRegs:$Rd32),
17901(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17902"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:sat",
17903tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17904let Inst{7-5} = 0b000;
17905let Inst{13-13} = 0b0;
17906let Inst{31-21} = 0b11101001010;
17907let hasNewValue = 1;
17908let opNewValue = 0;
17909let prefersSlot3 = 1;
17910let Defs = [USR_OVF];
17911}
17912def M7_wcmpyrw_rnd : HInst<
17913(outs IntRegs:$Rd32),
17914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17915"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:rnd:sat",
17916tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17917let Inst{7-5} = 0b000;
17918let Inst{13-13} = 0b0;
17919let Inst{31-21} = 0b11101001110;
17920let hasNewValue = 1;
17921let opNewValue = 0;
17922let prefersSlot3 = 1;
17923let Defs = [USR_OVF];
17924}
17925def M7_wcmpyrwc : HInst<
17926(outs IntRegs:$Rd32),
17927(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17928"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:sat",
17929tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17930let Inst{7-5} = 0b000;
17931let Inst{13-13} = 0b0;
17932let Inst{31-21} = 0b11101001011;
17933let hasNewValue = 1;
17934let opNewValue = 0;
17935let prefersSlot3 = 1;
17936let Defs = [USR_OVF];
17937}
17938def M7_wcmpyrwc_rnd : HInst<
17939(outs IntRegs:$Rd32),
17940(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17941"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:rnd:sat",
17942tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17943let Inst{7-5} = 0b000;
17944let Inst{13-13} = 0b0;
17945let Inst{31-21} = 0b11101001111;
17946let hasNewValue = 1;
17947let opNewValue = 0;
17948let prefersSlot3 = 1;
17949let Defs = [USR_OVF];
17950}
17951def PS_loadrbabs : HInst<
17952(outs IntRegs:$Rd32),
17953(ins u32_0Imm:$Ii),
17954"$Rd32 = memb(#$Ii)",
17955tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17956let Inst{24-21} = 0b1000;
17957let Inst{31-27} = 0b01001;
17958let hasNewValue = 1;
17959let opNewValue = 0;
17960let addrMode = Absolute;
17961let accessSize = ByteAccess;
17962let mayLoad = 1;
17963let isExtended = 1;
17964let BaseOpcode = "L4_loadrb_abs";
17965let CextOpcode = "L2_loadrb";
17966let isPredicable = 1;
17967let DecoderNamespace = "MustExtend";
17968let isExtended = 1;
17969let opExtendable = 1;
17970let isExtentSigned = 0;
17971let opExtentBits = 16;
17972let opExtentAlign = 0;
17973}
17974def PS_loadrdabs : HInst<
17975(outs DoubleRegs:$Rdd32),
17976(ins u29_3Imm:$Ii),
17977"$Rdd32 = memd(#$Ii)",
17978tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
17979let Inst{24-21} = 0b1110;
17980let Inst{31-27} = 0b01001;
17981let addrMode = Absolute;
17982let accessSize = DoubleWordAccess;
17983let mayLoad = 1;
17984let isExtended = 1;
17985let BaseOpcode = "L4_loadrd_abs";
17986let CextOpcode = "L2_loadrd";
17987let isPredicable = 1;
17988let DecoderNamespace = "MustExtend";
17989let isExtended = 1;
17990let opExtendable = 1;
17991let isExtentSigned = 0;
17992let opExtentBits = 19;
17993let opExtentAlign = 3;
17994}
17995def PS_loadrhabs : HInst<
17996(outs IntRegs:$Rd32),
17997(ins u31_1Imm:$Ii),
17998"$Rd32 = memh(#$Ii)",
17999tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
18000let Inst{24-21} = 0b1010;
18001let Inst{31-27} = 0b01001;
18002let hasNewValue = 1;
18003let opNewValue = 0;
18004let addrMode = Absolute;
18005let accessSize = HalfWordAccess;
18006let mayLoad = 1;
18007let isExtended = 1;
18008let BaseOpcode = "L4_loadrh_abs";
18009let CextOpcode = "L2_loadrh";
18010let isPredicable = 1;
18011let DecoderNamespace = "MustExtend";
18012let isExtended = 1;
18013let opExtendable = 1;
18014let isExtentSigned = 0;
18015let opExtentBits = 17;
18016let opExtentAlign = 1;
18017}
18018def PS_loadriabs : HInst<
18019(outs IntRegs:$Rd32),
18020(ins u30_2Imm:$Ii),
18021"$Rd32 = memw(#$Ii)",
18022tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
18023let Inst{24-21} = 0b1100;
18024let Inst{31-27} = 0b01001;
18025let hasNewValue = 1;
18026let opNewValue = 0;
18027let addrMode = Absolute;
18028let accessSize = WordAccess;
18029let mayLoad = 1;
18030let isExtended = 1;
18031let BaseOpcode = "L4_loadri_abs";
18032let CextOpcode = "L2_loadri";
18033let isPredicable = 1;
18034let DecoderNamespace = "MustExtend";
18035let isExtended = 1;
18036let opExtendable = 1;
18037let isExtentSigned = 0;
18038let opExtentBits = 18;
18039let opExtentAlign = 2;
18040}
18041def PS_loadrubabs : HInst<
18042(outs IntRegs:$Rd32),
18043(ins u32_0Imm:$Ii),
18044"$Rd32 = memub(#$Ii)",
18045tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
18046let Inst{24-21} = 0b1001;
18047let Inst{31-27} = 0b01001;
18048let hasNewValue = 1;
18049let opNewValue = 0;
18050let addrMode = Absolute;
18051let accessSize = ByteAccess;
18052let mayLoad = 1;
18053let isExtended = 1;
18054let BaseOpcode = "L4_loadrub_abs";
18055let CextOpcode = "L2_loadrub";
18056let isPredicable = 1;
18057let DecoderNamespace = "MustExtend";
18058let isExtended = 1;
18059let opExtendable = 1;
18060let isExtentSigned = 0;
18061let opExtentBits = 16;
18062let opExtentAlign = 0;
18063}
18064def PS_loadruhabs : HInst<
18065(outs IntRegs:$Rd32),
18066(ins u31_1Imm:$Ii),
18067"$Rd32 = memuh(#$Ii)",
18068tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
18069let Inst{24-21} = 0b1011;
18070let Inst{31-27} = 0b01001;
18071let hasNewValue = 1;
18072let opNewValue = 0;
18073let addrMode = Absolute;
18074let accessSize = HalfWordAccess;
18075let mayLoad = 1;
18076let isExtended = 1;
18077let BaseOpcode = "L4_loadruh_abs";
18078let CextOpcode = "L2_loadruh";
18079let isPredicable = 1;
18080let DecoderNamespace = "MustExtend";
18081let isExtended = 1;
18082let opExtendable = 1;
18083let isExtentSigned = 0;
18084let opExtentBits = 17;
18085let opExtentAlign = 1;
18086}
18087def PS_storerbabs : HInst<
18088(outs),
18089(ins u32_0Imm:$Ii, IntRegs:$Rt32),
18090"memb(#$Ii) = $Rt32",
18091tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
18092let Inst{24-21} = 0b0000;
18093let Inst{31-27} = 0b01001;
18094let addrMode = Absolute;
18095let accessSize = ByteAccess;
18096let isExtended = 1;
18097let mayStore = 1;
18098let BaseOpcode = "S2_storerbabs";
18099let CextOpcode = "S2_storerb";
18100let isNVStorable = 1;
18101let isPredicable = 1;
18102let DecoderNamespace = "MustExtend";
18103let isExtended = 1;
18104let opExtendable = 0;
18105let isExtentSigned = 0;
18106let opExtentBits = 16;
18107let opExtentAlign = 0;
18108}
18109def PS_storerbnewabs : HInst<
18110(outs),
18111(ins u32_0Imm:$Ii, IntRegs:$Nt8),
18112"memb(#$Ii) = $Nt8.new",
18113tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
18114let Inst{12-11} = 0b00;
18115let Inst{24-21} = 0b0101;
18116let Inst{31-27} = 0b01001;
18117let addrMode = Absolute;
18118let accessSize = ByteAccess;
18119let isNVStore = 1;
18120let isNewValue = 1;
18121let isExtended = 1;
18122let isRestrictNoSlot1Store = 1;
18123let mayStore = 1;
18124let BaseOpcode = "S2_storerbabs";
18125let CextOpcode = "S2_storerb";
18126let isPredicable = 1;
18127let DecoderNamespace = "MustExtend";
18128let isExtended = 1;
18129let opExtendable = 0;
18130let isExtentSigned = 0;
18131let opExtentBits = 16;
18132let opExtentAlign = 0;
18133let opNewValue = 1;
18134}
18135def PS_storerdabs : HInst<
18136(outs),
18137(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
18138"memd(#$Ii) = $Rtt32",
18139tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
18140let Inst{24-21} = 0b0110;
18141let Inst{31-27} = 0b01001;
18142let addrMode = Absolute;
18143let accessSize = DoubleWordAccess;
18144let isExtended = 1;
18145let mayStore = 1;
18146let BaseOpcode = "S2_storerdabs";
18147let CextOpcode = "S2_storerd";
18148let isPredicable = 1;
18149let DecoderNamespace = "MustExtend";
18150let isExtended = 1;
18151let opExtendable = 0;
18152let isExtentSigned = 0;
18153let opExtentBits = 19;
18154let opExtentAlign = 3;
18155}
18156def PS_storerfabs : HInst<
18157(outs),
18158(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18159"memh(#$Ii) = $Rt32.h",
18160tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18161let Inst{24-21} = 0b0011;
18162let Inst{31-27} = 0b01001;
18163let addrMode = Absolute;
18164let accessSize = HalfWordAccess;
18165let isExtended = 1;
18166let mayStore = 1;
18167let BaseOpcode = "S2_storerfabs";
18168let CextOpcode = "S2_storerf";
18169let isPredicable = 1;
18170let DecoderNamespace = "MustExtend";
18171let isExtended = 1;
18172let opExtendable = 0;
18173let isExtentSigned = 0;
18174let opExtentBits = 17;
18175let opExtentAlign = 1;
18176}
18177def PS_storerhabs : HInst<
18178(outs),
18179(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18180"memh(#$Ii) = $Rt32",
18181tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18182let Inst{24-21} = 0b0010;
18183let Inst{31-27} = 0b01001;
18184let addrMode = Absolute;
18185let accessSize = HalfWordAccess;
18186let isExtended = 1;
18187let mayStore = 1;
18188let BaseOpcode = "S2_storerhabs";
18189let CextOpcode = "S2_storerh";
18190let isNVStorable = 1;
18191let isPredicable = 1;
18192let DecoderNamespace = "MustExtend";
18193let isExtended = 1;
18194let opExtendable = 0;
18195let isExtentSigned = 0;
18196let opExtentBits = 17;
18197let opExtentAlign = 1;
18198}
18199def PS_storerhnewabs : HInst<
18200(outs),
18201(ins u31_1Imm:$Ii, IntRegs:$Nt8),
18202"memh(#$Ii) = $Nt8.new",
18203tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
18204let Inst{12-11} = 0b01;
18205let Inst{24-21} = 0b0101;
18206let Inst{31-27} = 0b01001;
18207let addrMode = Absolute;
18208let accessSize = HalfWordAccess;
18209let isNVStore = 1;
18210let isNewValue = 1;
18211let isExtended = 1;
18212let isRestrictNoSlot1Store = 1;
18213let mayStore = 1;
18214let BaseOpcode = "S2_storerhabs";
18215let CextOpcode = "S2_storerh";
18216let isPredicable = 1;
18217let DecoderNamespace = "MustExtend";
18218let isExtended = 1;
18219let opExtendable = 0;
18220let isExtentSigned = 0;
18221let opExtentBits = 17;
18222let opExtentAlign = 1;
18223let opNewValue = 1;
18224}
18225def PS_storeriabs : HInst<
18226(outs),
18227(ins u30_2Imm:$Ii, IntRegs:$Rt32),
18228"memw(#$Ii) = $Rt32",
18229tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
18230let Inst{24-21} = 0b0100;
18231let Inst{31-27} = 0b01001;
18232let addrMode = Absolute;
18233let accessSize = WordAccess;
18234let isExtended = 1;
18235let mayStore = 1;
18236let BaseOpcode = "S2_storeriabs";
18237let CextOpcode = "S2_storeri";
18238let isNVStorable = 1;
18239let isPredicable = 1;
18240let DecoderNamespace = "MustExtend";
18241let isExtended = 1;
18242let opExtendable = 0;
18243let isExtentSigned = 0;
18244let opExtentBits = 18;
18245let opExtentAlign = 2;
18246}
18247def PS_storerinewabs : HInst<
18248(outs),
18249(ins u30_2Imm:$Ii, IntRegs:$Nt8),
18250"memw(#$Ii) = $Nt8.new",
18251tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
18252let Inst{12-11} = 0b10;
18253let Inst{24-21} = 0b0101;
18254let Inst{31-27} = 0b01001;
18255let addrMode = Absolute;
18256let accessSize = WordAccess;
18257let isNVStore = 1;
18258let isNewValue = 1;
18259let isExtended = 1;
18260let isRestrictNoSlot1Store = 1;
18261let mayStore = 1;
18262let BaseOpcode = "S2_storeriabs";
18263let CextOpcode = "S2_storeri";
18264let isPredicable = 1;
18265let DecoderNamespace = "MustExtend";
18266let isExtended = 1;
18267let opExtendable = 0;
18268let isExtentSigned = 0;
18269let opExtentBits = 18;
18270let opExtentAlign = 2;
18271let opNewValue = 1;
18272}
18273def R6_release_at_vi : HInst<
18274(outs),
18275(ins IntRegs:$Rs32),
18276"release($Rs32):at",
18277tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18278let Inst{7-2} = 0b000011;
18279let Inst{13-13} = 0b0;
18280let Inst{31-21} = 0b10100000111;
18281let isSolo = 1;
18282let mayStore = 1;
18283}
18284def R6_release_st_vi : HInst<
18285(outs),
18286(ins IntRegs:$Rs32),
18287"release($Rs32):st",
18288tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18289let Inst{7-2} = 0b001011;
18290let Inst{13-13} = 0b0;
18291let Inst{31-21} = 0b10100000111;
18292let isSolo = 1;
18293let mayStore = 1;
18294}
18295def S2_addasl_rrri : HInst<
18296(outs IntRegs:$Rd32),
18297(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
18298"$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
18299tc_2c13e7f5, TypeS_3op>, Enc_47ef61 {
18300let Inst{13-13} = 0b0;
18301let Inst{31-21} = 0b11000100000;
18302let hasNewValue = 1;
18303let opNewValue = 0;
18304let prefersSlot3 = 1;
18305}
18306def S2_allocframe : HInst<
18307(outs IntRegs:$Rx32),
18308(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
18309"allocframe($Rx32,#$Ii):raw",
18310tc_934753bb, TypeST>, Enc_22c845 {
18311let Inst{13-11} = 0b000;
18312let Inst{31-21} = 0b10100000100;
18313let hasNewValue = 1;
18314let opNewValue = 0;
18315let addrMode = BaseImmOffset;
18316let accessSize = DoubleWordAccess;
18317let mayStore = 1;
18318let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
18319let Defs = [R30];
18320let Constraints = "$Rx32 = $Rx32in";
18321}
18322def S2_asl_i_p : HInst<
18323(outs DoubleRegs:$Rdd32),
18324(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18325"$Rdd32 = asl($Rss32,#$Ii)",
18326tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18327let Inst{7-5} = 0b010;
18328let Inst{31-21} = 0b10000000000;
18329}
18330def S2_asl_i_p_acc : HInst<
18331(outs DoubleRegs:$Rxx32),
18332(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18333"$Rxx32 += asl($Rss32,#$Ii)",
18334tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18335let Inst{7-5} = 0b110;
18336let Inst{31-21} = 0b10000010000;
18337let prefersSlot3 = 1;
18338let Constraints = "$Rxx32 = $Rxx32in";
18339}
18340def S2_asl_i_p_and : HInst<
18341(outs DoubleRegs:$Rxx32),
18342(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18343"$Rxx32 &= asl($Rss32,#$Ii)",
18344tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18345let Inst{7-5} = 0b010;
18346let Inst{31-21} = 0b10000010010;
18347let prefersSlot3 = 1;
18348let Constraints = "$Rxx32 = $Rxx32in";
18349}
18350def S2_asl_i_p_nac : HInst<
18351(outs DoubleRegs:$Rxx32),
18352(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18353"$Rxx32 -= asl($Rss32,#$Ii)",
18354tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18355let Inst{7-5} = 0b010;
18356let Inst{31-21} = 0b10000010000;
18357let prefersSlot3 = 1;
18358let Constraints = "$Rxx32 = $Rxx32in";
18359}
18360def S2_asl_i_p_or : HInst<
18361(outs DoubleRegs:$Rxx32),
18362(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18363"$Rxx32 |= asl($Rss32,#$Ii)",
18364tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18365let Inst{7-5} = 0b110;
18366let Inst{31-21} = 0b10000010010;
18367let prefersSlot3 = 1;
18368let Constraints = "$Rxx32 = $Rxx32in";
18369}
18370def S2_asl_i_p_xacc : HInst<
18371(outs DoubleRegs:$Rxx32),
18372(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18373"$Rxx32 ^= asl($Rss32,#$Ii)",
18374tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18375let Inst{7-5} = 0b010;
18376let Inst{31-21} = 0b10000010100;
18377let prefersSlot3 = 1;
18378let Constraints = "$Rxx32 = $Rxx32in";
18379}
18380def S2_asl_i_r : HInst<
18381(outs IntRegs:$Rd32),
18382(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18383"$Rd32 = asl($Rs32,#$Ii)",
18384tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18385let Inst{7-5} = 0b010;
18386let Inst{13-13} = 0b0;
18387let Inst{31-21} = 0b10001100000;
18388let hasNewValue = 1;
18389let opNewValue = 0;
18390}
18391def S2_asl_i_r_acc : HInst<
18392(outs IntRegs:$Rx32),
18393(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18394"$Rx32 += asl($Rs32,#$Ii)",
18395tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18396let Inst{7-5} = 0b110;
18397let Inst{13-13} = 0b0;
18398let Inst{31-21} = 0b10001110000;
18399let hasNewValue = 1;
18400let opNewValue = 0;
18401let prefersSlot3 = 1;
18402let Constraints = "$Rx32 = $Rx32in";
18403}
18404def S2_asl_i_r_and : HInst<
18405(outs IntRegs:$Rx32),
18406(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18407"$Rx32 &= asl($Rs32,#$Ii)",
18408tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18409let Inst{7-5} = 0b010;
18410let Inst{13-13} = 0b0;
18411let Inst{31-21} = 0b10001110010;
18412let hasNewValue = 1;
18413let opNewValue = 0;
18414let prefersSlot3 = 1;
18415let Constraints = "$Rx32 = $Rx32in";
18416}
18417def S2_asl_i_r_nac : HInst<
18418(outs IntRegs:$Rx32),
18419(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18420"$Rx32 -= asl($Rs32,#$Ii)",
18421tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18422let Inst{7-5} = 0b010;
18423let Inst{13-13} = 0b0;
18424let Inst{31-21} = 0b10001110000;
18425let hasNewValue = 1;
18426let opNewValue = 0;
18427let prefersSlot3 = 1;
18428let Constraints = "$Rx32 = $Rx32in";
18429}
18430def S2_asl_i_r_or : HInst<
18431(outs IntRegs:$Rx32),
18432(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18433"$Rx32 |= asl($Rs32,#$Ii)",
18434tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18435let Inst{7-5} = 0b110;
18436let Inst{13-13} = 0b0;
18437let Inst{31-21} = 0b10001110010;
18438let hasNewValue = 1;
18439let opNewValue = 0;
18440let prefersSlot3 = 1;
18441let Constraints = "$Rx32 = $Rx32in";
18442}
18443def S2_asl_i_r_sat : HInst<
18444(outs IntRegs:$Rd32),
18445(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18446"$Rd32 = asl($Rs32,#$Ii):sat",
18447tc_8a825db2, TypeS_2op>, Enc_a05677 {
18448let Inst{7-5} = 0b010;
18449let Inst{13-13} = 0b0;
18450let Inst{31-21} = 0b10001100010;
18451let hasNewValue = 1;
18452let opNewValue = 0;
18453let prefersSlot3 = 1;
18454let Defs = [USR_OVF];
18455}
18456def S2_asl_i_r_xacc : HInst<
18457(outs IntRegs:$Rx32),
18458(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18459"$Rx32 ^= asl($Rs32,#$Ii)",
18460tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18461let Inst{7-5} = 0b010;
18462let Inst{13-13} = 0b0;
18463let Inst{31-21} = 0b10001110100;
18464let hasNewValue = 1;
18465let opNewValue = 0;
18466let prefersSlot3 = 1;
18467let Constraints = "$Rx32 = $Rx32in";
18468}
18469def S2_asl_i_vh : HInst<
18470(outs DoubleRegs:$Rdd32),
18471(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18472"$Rdd32 = vaslh($Rss32,#$Ii)",
18473tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18474let Inst{7-5} = 0b010;
18475let Inst{13-12} = 0b00;
18476let Inst{31-21} = 0b10000000100;
18477}
18478def S2_asl_i_vw : HInst<
18479(outs DoubleRegs:$Rdd32),
18480(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18481"$Rdd32 = vaslw($Rss32,#$Ii)",
18482tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18483let Inst{7-5} = 0b010;
18484let Inst{13-13} = 0b0;
18485let Inst{31-21} = 0b10000000010;
18486}
18487def S2_asl_r_p : HInst<
18488(outs DoubleRegs:$Rdd32),
18489(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18490"$Rdd32 = asl($Rss32,$Rt32)",
18491tc_5da50c4b, TypeS_3op>, Enc_927852 {
18492let Inst{7-5} = 0b100;
18493let Inst{13-13} = 0b0;
18494let Inst{31-21} = 0b11000011100;
18495}
18496def S2_asl_r_p_acc : HInst<
18497(outs DoubleRegs:$Rxx32),
18498(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18499"$Rxx32 += asl($Rss32,$Rt32)",
18500tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18501let Inst{7-5} = 0b100;
18502let Inst{13-13} = 0b0;
18503let Inst{31-21} = 0b11001011110;
18504let prefersSlot3 = 1;
18505let Constraints = "$Rxx32 = $Rxx32in";
18506}
18507def S2_asl_r_p_and : HInst<
18508(outs DoubleRegs:$Rxx32),
18509(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18510"$Rxx32 &= asl($Rss32,$Rt32)",
18511tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18512let Inst{7-5} = 0b100;
18513let Inst{13-13} = 0b0;
18514let Inst{31-21} = 0b11001011010;
18515let prefersSlot3 = 1;
18516let Constraints = "$Rxx32 = $Rxx32in";
18517}
18518def S2_asl_r_p_nac : HInst<
18519(outs DoubleRegs:$Rxx32),
18520(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18521"$Rxx32 -= asl($Rss32,$Rt32)",
18522tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18523let Inst{7-5} = 0b100;
18524let Inst{13-13} = 0b0;
18525let Inst{31-21} = 0b11001011100;
18526let prefersSlot3 = 1;
18527let Constraints = "$Rxx32 = $Rxx32in";
18528}
18529def S2_asl_r_p_or : HInst<
18530(outs DoubleRegs:$Rxx32),
18531(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18532"$Rxx32 |= asl($Rss32,$Rt32)",
18533tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18534let Inst{7-5} = 0b100;
18535let Inst{13-13} = 0b0;
18536let Inst{31-21} = 0b11001011000;
18537let prefersSlot3 = 1;
18538let Constraints = "$Rxx32 = $Rxx32in";
18539}
18540def S2_asl_r_p_xor : HInst<
18541(outs DoubleRegs:$Rxx32),
18542(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18543"$Rxx32 ^= asl($Rss32,$Rt32)",
18544tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18545let Inst{7-5} = 0b100;
18546let Inst{13-13} = 0b0;
18547let Inst{31-21} = 0b11001011011;
18548let prefersSlot3 = 1;
18549let Constraints = "$Rxx32 = $Rxx32in";
18550}
18551def S2_asl_r_r : HInst<
18552(outs IntRegs:$Rd32),
18553(ins IntRegs:$Rs32, IntRegs:$Rt32),
18554"$Rd32 = asl($Rs32,$Rt32)",
18555tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18556let Inst{7-5} = 0b100;
18557let Inst{13-13} = 0b0;
18558let Inst{31-21} = 0b11000110010;
18559let hasNewValue = 1;
18560let opNewValue = 0;
18561}
18562def S2_asl_r_r_acc : HInst<
18563(outs IntRegs:$Rx32),
18564(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18565"$Rx32 += asl($Rs32,$Rt32)",
18566tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18567let Inst{7-5} = 0b100;
18568let Inst{13-13} = 0b0;
18569let Inst{31-21} = 0b11001100110;
18570let hasNewValue = 1;
18571let opNewValue = 0;
18572let prefersSlot3 = 1;
18573let Constraints = "$Rx32 = $Rx32in";
18574}
18575def S2_asl_r_r_and : HInst<
18576(outs IntRegs:$Rx32),
18577(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18578"$Rx32 &= asl($Rs32,$Rt32)",
18579tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18580let Inst{7-5} = 0b100;
18581let Inst{13-13} = 0b0;
18582let Inst{31-21} = 0b11001100010;
18583let hasNewValue = 1;
18584let opNewValue = 0;
18585let prefersSlot3 = 1;
18586let Constraints = "$Rx32 = $Rx32in";
18587}
18588def S2_asl_r_r_nac : HInst<
18589(outs IntRegs:$Rx32),
18590(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18591"$Rx32 -= asl($Rs32,$Rt32)",
18592tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18593let Inst{7-5} = 0b100;
18594let Inst{13-13} = 0b0;
18595let Inst{31-21} = 0b11001100100;
18596let hasNewValue = 1;
18597let opNewValue = 0;
18598let prefersSlot3 = 1;
18599let Constraints = "$Rx32 = $Rx32in";
18600}
18601def S2_asl_r_r_or : HInst<
18602(outs IntRegs:$Rx32),
18603(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18604"$Rx32 |= asl($Rs32,$Rt32)",
18605tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18606let Inst{7-5} = 0b100;
18607let Inst{13-13} = 0b0;
18608let Inst{31-21} = 0b11001100000;
18609let hasNewValue = 1;
18610let opNewValue = 0;
18611let prefersSlot3 = 1;
18612let Constraints = "$Rx32 = $Rx32in";
18613}
18614def S2_asl_r_r_sat : HInst<
18615(outs IntRegs:$Rd32),
18616(ins IntRegs:$Rs32, IntRegs:$Rt32),
18617"$Rd32 = asl($Rs32,$Rt32):sat",
18618tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18619let Inst{7-5} = 0b100;
18620let Inst{13-13} = 0b0;
18621let Inst{31-21} = 0b11000110000;
18622let hasNewValue = 1;
18623let opNewValue = 0;
18624let prefersSlot3 = 1;
18625let Defs = [USR_OVF];
18626}
18627def S2_asl_r_vh : HInst<
18628(outs DoubleRegs:$Rdd32),
18629(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18630"$Rdd32 = vaslh($Rss32,$Rt32)",
18631tc_5da50c4b, TypeS_3op>, Enc_927852 {
18632let Inst{7-5} = 0b100;
18633let Inst{13-13} = 0b0;
18634let Inst{31-21} = 0b11000011010;
18635}
18636def S2_asl_r_vw : HInst<
18637(outs DoubleRegs:$Rdd32),
18638(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18639"$Rdd32 = vaslw($Rss32,$Rt32)",
18640tc_5da50c4b, TypeS_3op>, Enc_927852 {
18641let Inst{7-5} = 0b100;
18642let Inst{13-13} = 0b0;
18643let Inst{31-21} = 0b11000011000;
18644}
18645def S2_asr_i_p : HInst<
18646(outs DoubleRegs:$Rdd32),
18647(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18648"$Rdd32 = asr($Rss32,#$Ii)",
18649tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18650let Inst{7-5} = 0b000;
18651let Inst{31-21} = 0b10000000000;
18652}
18653def S2_asr_i_p_acc : HInst<
18654(outs DoubleRegs:$Rxx32),
18655(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18656"$Rxx32 += asr($Rss32,#$Ii)",
18657tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18658let Inst{7-5} = 0b100;
18659let Inst{31-21} = 0b10000010000;
18660let prefersSlot3 = 1;
18661let Constraints = "$Rxx32 = $Rxx32in";
18662}
18663def S2_asr_i_p_and : HInst<
18664(outs DoubleRegs:$Rxx32),
18665(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18666"$Rxx32 &= asr($Rss32,#$Ii)",
18667tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18668let Inst{7-5} = 0b000;
18669let Inst{31-21} = 0b10000010010;
18670let prefersSlot3 = 1;
18671let Constraints = "$Rxx32 = $Rxx32in";
18672}
18673def S2_asr_i_p_nac : HInst<
18674(outs DoubleRegs:$Rxx32),
18675(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18676"$Rxx32 -= asr($Rss32,#$Ii)",
18677tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18678let Inst{7-5} = 0b000;
18679let Inst{31-21} = 0b10000010000;
18680let prefersSlot3 = 1;
18681let Constraints = "$Rxx32 = $Rxx32in";
18682}
18683def S2_asr_i_p_or : HInst<
18684(outs DoubleRegs:$Rxx32),
18685(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18686"$Rxx32 |= asr($Rss32,#$Ii)",
18687tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18688let Inst{7-5} = 0b100;
18689let Inst{31-21} = 0b10000010010;
18690let prefersSlot3 = 1;
18691let Constraints = "$Rxx32 = $Rxx32in";
18692}
18693def S2_asr_i_p_rnd : HInst<
18694(outs DoubleRegs:$Rdd32),
18695(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18696"$Rdd32 = asr($Rss32,#$Ii):rnd",
18697tc_0dfac0a7, TypeS_2op>, Enc_5eac98 {
18698let Inst{7-5} = 0b111;
18699let Inst{31-21} = 0b10000000110;
18700let prefersSlot3 = 1;
18701}
18702def S2_asr_i_p_rnd_goodsyntax : HInst<
18703(outs DoubleRegs:$Rdd32),
18704(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18705"$Rdd32 = asrrnd($Rss32,#$Ii)",
18706tc_0dfac0a7, TypeS_2op> {
18707let isPseudo = 1;
18708}
18709def S2_asr_i_r : HInst<
18710(outs IntRegs:$Rd32),
18711(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18712"$Rd32 = asr($Rs32,#$Ii)",
18713tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18714let Inst{7-5} = 0b000;
18715let Inst{13-13} = 0b0;
18716let Inst{31-21} = 0b10001100000;
18717let hasNewValue = 1;
18718let opNewValue = 0;
18719}
18720def S2_asr_i_r_acc : HInst<
18721(outs IntRegs:$Rx32),
18722(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18723"$Rx32 += asr($Rs32,#$Ii)",
18724tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18725let Inst{7-5} = 0b100;
18726let Inst{13-13} = 0b0;
18727let Inst{31-21} = 0b10001110000;
18728let hasNewValue = 1;
18729let opNewValue = 0;
18730let prefersSlot3 = 1;
18731let Constraints = "$Rx32 = $Rx32in";
18732}
18733def S2_asr_i_r_and : HInst<
18734(outs IntRegs:$Rx32),
18735(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18736"$Rx32 &= asr($Rs32,#$Ii)",
18737tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18738let Inst{7-5} = 0b000;
18739let Inst{13-13} = 0b0;
18740let Inst{31-21} = 0b10001110010;
18741let hasNewValue = 1;
18742let opNewValue = 0;
18743let prefersSlot3 = 1;
18744let Constraints = "$Rx32 = $Rx32in";
18745}
18746def S2_asr_i_r_nac : HInst<
18747(outs IntRegs:$Rx32),
18748(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18749"$Rx32 -= asr($Rs32,#$Ii)",
18750tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18751let Inst{7-5} = 0b000;
18752let Inst{13-13} = 0b0;
18753let Inst{31-21} = 0b10001110000;
18754let hasNewValue = 1;
18755let opNewValue = 0;
18756let prefersSlot3 = 1;
18757let Constraints = "$Rx32 = $Rx32in";
18758}
18759def S2_asr_i_r_or : HInst<
18760(outs IntRegs:$Rx32),
18761(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18762"$Rx32 |= asr($Rs32,#$Ii)",
18763tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18764let Inst{7-5} = 0b100;
18765let Inst{13-13} = 0b0;
18766let Inst{31-21} = 0b10001110010;
18767let hasNewValue = 1;
18768let opNewValue = 0;
18769let prefersSlot3 = 1;
18770let Constraints = "$Rx32 = $Rx32in";
18771}
18772def S2_asr_i_r_rnd : HInst<
18773(outs IntRegs:$Rd32),
18774(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18775"$Rd32 = asr($Rs32,#$Ii):rnd",
18776tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
18777let Inst{7-5} = 0b000;
18778let Inst{13-13} = 0b0;
18779let Inst{31-21} = 0b10001100010;
18780let hasNewValue = 1;
18781let opNewValue = 0;
18782let prefersSlot3 = 1;
18783}
18784def S2_asr_i_r_rnd_goodsyntax : HInst<
18785(outs IntRegs:$Rd32),
18786(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18787"$Rd32 = asrrnd($Rs32,#$Ii)",
18788tc_0dfac0a7, TypeS_2op> {
18789let hasNewValue = 1;
18790let opNewValue = 0;
18791let isPseudo = 1;
18792}
18793def S2_asr_i_svw_trun : HInst<
18794(outs IntRegs:$Rd32),
18795(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18796"$Rd32 = vasrw($Rss32,#$Ii)",
18797tc_f34c1c21, TypeS_2op>, Enc_8dec2e {
18798let Inst{7-5} = 0b010;
18799let Inst{13-13} = 0b0;
18800let Inst{31-21} = 0b10001000110;
18801let hasNewValue = 1;
18802let opNewValue = 0;
18803let prefersSlot3 = 1;
18804}
18805def S2_asr_i_vh : HInst<
18806(outs DoubleRegs:$Rdd32),
18807(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18808"$Rdd32 = vasrh($Rss32,#$Ii)",
18809tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18810let Inst{7-5} = 0b000;
18811let Inst{13-12} = 0b00;
18812let Inst{31-21} = 0b10000000100;
18813}
18814def S2_asr_i_vw : HInst<
18815(outs DoubleRegs:$Rdd32),
18816(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18817"$Rdd32 = vasrw($Rss32,#$Ii)",
18818tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18819let Inst{7-5} = 0b000;
18820let Inst{13-13} = 0b0;
18821let Inst{31-21} = 0b10000000010;
18822}
18823def S2_asr_r_p : HInst<
18824(outs DoubleRegs:$Rdd32),
18825(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18826"$Rdd32 = asr($Rss32,$Rt32)",
18827tc_5da50c4b, TypeS_3op>, Enc_927852 {
18828let Inst{7-5} = 0b000;
18829let Inst{13-13} = 0b0;
18830let Inst{31-21} = 0b11000011100;
18831}
18832def S2_asr_r_p_acc : HInst<
18833(outs DoubleRegs:$Rxx32),
18834(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18835"$Rxx32 += asr($Rss32,$Rt32)",
18836tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18837let Inst{7-5} = 0b000;
18838let Inst{13-13} = 0b0;
18839let Inst{31-21} = 0b11001011110;
18840let prefersSlot3 = 1;
18841let Constraints = "$Rxx32 = $Rxx32in";
18842}
18843def S2_asr_r_p_and : HInst<
18844(outs DoubleRegs:$Rxx32),
18845(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18846"$Rxx32 &= asr($Rss32,$Rt32)",
18847tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18848let Inst{7-5} = 0b000;
18849let Inst{13-13} = 0b0;
18850let Inst{31-21} = 0b11001011010;
18851let prefersSlot3 = 1;
18852let Constraints = "$Rxx32 = $Rxx32in";
18853}
18854def S2_asr_r_p_nac : HInst<
18855(outs DoubleRegs:$Rxx32),
18856(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18857"$Rxx32 -= asr($Rss32,$Rt32)",
18858tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18859let Inst{7-5} = 0b000;
18860let Inst{13-13} = 0b0;
18861let Inst{31-21} = 0b11001011100;
18862let prefersSlot3 = 1;
18863let Constraints = "$Rxx32 = $Rxx32in";
18864}
18865def S2_asr_r_p_or : HInst<
18866(outs DoubleRegs:$Rxx32),
18867(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18868"$Rxx32 |= asr($Rss32,$Rt32)",
18869tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18870let Inst{7-5} = 0b000;
18871let Inst{13-13} = 0b0;
18872let Inst{31-21} = 0b11001011000;
18873let prefersSlot3 = 1;
18874let Constraints = "$Rxx32 = $Rxx32in";
18875}
18876def S2_asr_r_p_xor : HInst<
18877(outs DoubleRegs:$Rxx32),
18878(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18879"$Rxx32 ^= asr($Rss32,$Rt32)",
18880tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18881let Inst{7-5} = 0b000;
18882let Inst{13-13} = 0b0;
18883let Inst{31-21} = 0b11001011011;
18884let prefersSlot3 = 1;
18885let Constraints = "$Rxx32 = $Rxx32in";
18886}
18887def S2_asr_r_r : HInst<
18888(outs IntRegs:$Rd32),
18889(ins IntRegs:$Rs32, IntRegs:$Rt32),
18890"$Rd32 = asr($Rs32,$Rt32)",
18891tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18892let Inst{7-5} = 0b000;
18893let Inst{13-13} = 0b0;
18894let Inst{31-21} = 0b11000110010;
18895let hasNewValue = 1;
18896let opNewValue = 0;
18897}
18898def S2_asr_r_r_acc : HInst<
18899(outs IntRegs:$Rx32),
18900(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18901"$Rx32 += asr($Rs32,$Rt32)",
18902tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18903let Inst{7-5} = 0b000;
18904let Inst{13-13} = 0b0;
18905let Inst{31-21} = 0b11001100110;
18906let hasNewValue = 1;
18907let opNewValue = 0;
18908let prefersSlot3 = 1;
18909let Constraints = "$Rx32 = $Rx32in";
18910}
18911def S2_asr_r_r_and : HInst<
18912(outs IntRegs:$Rx32),
18913(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18914"$Rx32 &= asr($Rs32,$Rt32)",
18915tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18916let Inst{7-5} = 0b000;
18917let Inst{13-13} = 0b0;
18918let Inst{31-21} = 0b11001100010;
18919let hasNewValue = 1;
18920let opNewValue = 0;
18921let prefersSlot3 = 1;
18922let Constraints = "$Rx32 = $Rx32in";
18923}
18924def S2_asr_r_r_nac : HInst<
18925(outs IntRegs:$Rx32),
18926(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18927"$Rx32 -= asr($Rs32,$Rt32)",
18928tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18929let Inst{7-5} = 0b000;
18930let Inst{13-13} = 0b0;
18931let Inst{31-21} = 0b11001100100;
18932let hasNewValue = 1;
18933let opNewValue = 0;
18934let prefersSlot3 = 1;
18935let Constraints = "$Rx32 = $Rx32in";
18936}
18937def S2_asr_r_r_or : HInst<
18938(outs IntRegs:$Rx32),
18939(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18940"$Rx32 |= asr($Rs32,$Rt32)",
18941tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18942let Inst{7-5} = 0b000;
18943let Inst{13-13} = 0b0;
18944let Inst{31-21} = 0b11001100000;
18945let hasNewValue = 1;
18946let opNewValue = 0;
18947let prefersSlot3 = 1;
18948let Constraints = "$Rx32 = $Rx32in";
18949}
18950def S2_asr_r_r_sat : HInst<
18951(outs IntRegs:$Rd32),
18952(ins IntRegs:$Rs32, IntRegs:$Rt32),
18953"$Rd32 = asr($Rs32,$Rt32):sat",
18954tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18955let Inst{7-5} = 0b000;
18956let Inst{13-13} = 0b0;
18957let Inst{31-21} = 0b11000110000;
18958let hasNewValue = 1;
18959let opNewValue = 0;
18960let prefersSlot3 = 1;
18961let Defs = [USR_OVF];
18962}
18963def S2_asr_r_svw_trun : HInst<
18964(outs IntRegs:$Rd32),
18965(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18966"$Rd32 = vasrw($Rss32,$Rt32)",
18967tc_f34c1c21, TypeS_3op>, Enc_3d5b28 {
18968let Inst{7-5} = 0b010;
18969let Inst{13-13} = 0b0;
18970let Inst{31-21} = 0b11000101000;
18971let hasNewValue = 1;
18972let opNewValue = 0;
18973let prefersSlot3 = 1;
18974}
18975def S2_asr_r_vh : HInst<
18976(outs DoubleRegs:$Rdd32),
18977(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18978"$Rdd32 = vasrh($Rss32,$Rt32)",
18979tc_5da50c4b, TypeS_3op>, Enc_927852 {
18980let Inst{7-5} = 0b000;
18981let Inst{13-13} = 0b0;
18982let Inst{31-21} = 0b11000011010;
18983}
18984def S2_asr_r_vw : HInst<
18985(outs DoubleRegs:$Rdd32),
18986(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18987"$Rdd32 = vasrw($Rss32,$Rt32)",
18988tc_5da50c4b, TypeS_3op>, Enc_927852 {
18989let Inst{7-5} = 0b000;
18990let Inst{13-13} = 0b0;
18991let Inst{31-21} = 0b11000011000;
18992}
18993def S2_brev : HInst<
18994(outs IntRegs:$Rd32),
18995(ins IntRegs:$Rs32),
18996"$Rd32 = brev($Rs32)",
18997tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18998let Inst{13-5} = 0b000000110;
18999let Inst{31-21} = 0b10001100010;
19000let hasNewValue = 1;
19001let opNewValue = 0;
19002let prefersSlot3 = 1;
19003}
19004def S2_brevp : HInst<
19005(outs DoubleRegs:$Rdd32),
19006(ins DoubleRegs:$Rss32),
19007"$Rdd32 = brev($Rss32)",
19008tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19009let Inst{13-5} = 0b000000110;
19010let Inst{31-21} = 0b10000000110;
19011let prefersSlot3 = 1;
19012}
19013def S2_cabacdecbin : HInst<
19014(outs DoubleRegs:$Rdd32),
19015(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19016"$Rdd32 = decbin($Rss32,$Rtt32)",
19017tc_db596beb, TypeS_3op>, Enc_a56825, Requires<[UseCabac]> {
19018let Inst{7-5} = 0b110;
19019let Inst{13-13} = 0b0;
19020let Inst{31-21} = 0b11000001110;
19021let isPredicateLate = 1;
19022let prefersSlot3 = 1;
19023let Defs = [P0];
19024}
19025def S2_cl0 : HInst<
19026(outs IntRegs:$Rd32),
19027(ins IntRegs:$Rs32),
19028"$Rd32 = cl0($Rs32)",
19029tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19030let Inst{13-5} = 0b000000101;
19031let Inst{31-21} = 0b10001100000;
19032let hasNewValue = 1;
19033let opNewValue = 0;
19034let prefersSlot3 = 1;
19035}
19036def S2_cl0p : HInst<
19037(outs IntRegs:$Rd32),
19038(ins DoubleRegs:$Rss32),
19039"$Rd32 = cl0($Rss32)",
19040tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19041let Inst{13-5} = 0b000000010;
19042let Inst{31-21} = 0b10001000010;
19043let hasNewValue = 1;
19044let opNewValue = 0;
19045let prefersSlot3 = 1;
19046}
19047def S2_cl1 : HInst<
19048(outs IntRegs:$Rd32),
19049(ins IntRegs:$Rs32),
19050"$Rd32 = cl1($Rs32)",
19051tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19052let Inst{13-5} = 0b000000110;
19053let Inst{31-21} = 0b10001100000;
19054let hasNewValue = 1;
19055let opNewValue = 0;
19056let prefersSlot3 = 1;
19057}
19058def S2_cl1p : HInst<
19059(outs IntRegs:$Rd32),
19060(ins DoubleRegs:$Rss32),
19061"$Rd32 = cl1($Rss32)",
19062tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19063let Inst{13-5} = 0b000000100;
19064let Inst{31-21} = 0b10001000010;
19065let hasNewValue = 1;
19066let opNewValue = 0;
19067let prefersSlot3 = 1;
19068}
19069def S2_clb : HInst<
19070(outs IntRegs:$Rd32),
19071(ins IntRegs:$Rs32),
19072"$Rd32 = clb($Rs32)",
19073tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19074let Inst{13-5} = 0b000000100;
19075let Inst{31-21} = 0b10001100000;
19076let hasNewValue = 1;
19077let opNewValue = 0;
19078let prefersSlot3 = 1;
19079}
19080def S2_clbnorm : HInst<
19081(outs IntRegs:$Rd32),
19082(ins IntRegs:$Rs32),
19083"$Rd32 = normamt($Rs32)",
19084tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19085let Inst{13-5} = 0b000000111;
19086let Inst{31-21} = 0b10001100000;
19087let hasNewValue = 1;
19088let opNewValue = 0;
19089let prefersSlot3 = 1;
19090}
19091def S2_clbp : HInst<
19092(outs IntRegs:$Rd32),
19093(ins DoubleRegs:$Rss32),
19094"$Rd32 = clb($Rss32)",
19095tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19096let Inst{13-5} = 0b000000000;
19097let Inst{31-21} = 0b10001000010;
19098let hasNewValue = 1;
19099let opNewValue = 0;
19100let prefersSlot3 = 1;
19101}
19102def S2_clrbit_i : HInst<
19103(outs IntRegs:$Rd32),
19104(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19105"$Rd32 = clrbit($Rs32,#$Ii)",
19106tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19107let Inst{7-5} = 0b001;
19108let Inst{13-13} = 0b0;
19109let Inst{31-21} = 0b10001100110;
19110let hasNewValue = 1;
19111let opNewValue = 0;
19112}
19113def S2_clrbit_r : HInst<
19114(outs IntRegs:$Rd32),
19115(ins IntRegs:$Rs32, IntRegs:$Rt32),
19116"$Rd32 = clrbit($Rs32,$Rt32)",
19117tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19118let Inst{7-5} = 0b010;
19119let Inst{13-13} = 0b0;
19120let Inst{31-21} = 0b11000110100;
19121let hasNewValue = 1;
19122let opNewValue = 0;
19123}
19124def S2_ct0 : HInst<
19125(outs IntRegs:$Rd32),
19126(ins IntRegs:$Rs32),
19127"$Rd32 = ct0($Rs32)",
19128tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19129let Inst{13-5} = 0b000000100;
19130let Inst{31-21} = 0b10001100010;
19131let hasNewValue = 1;
19132let opNewValue = 0;
19133let prefersSlot3 = 1;
19134}
19135def S2_ct0p : HInst<
19136(outs IntRegs:$Rd32),
19137(ins DoubleRegs:$Rss32),
19138"$Rd32 = ct0($Rss32)",
19139tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19140let Inst{13-5} = 0b000000010;
19141let Inst{31-21} = 0b10001000111;
19142let hasNewValue = 1;
19143let opNewValue = 0;
19144let prefersSlot3 = 1;
19145}
19146def S2_ct1 : HInst<
19147(outs IntRegs:$Rd32),
19148(ins IntRegs:$Rs32),
19149"$Rd32 = ct1($Rs32)",
19150tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19151let Inst{13-5} = 0b000000101;
19152let Inst{31-21} = 0b10001100010;
19153let hasNewValue = 1;
19154let opNewValue = 0;
19155let prefersSlot3 = 1;
19156}
19157def S2_ct1p : HInst<
19158(outs IntRegs:$Rd32),
19159(ins DoubleRegs:$Rss32),
19160"$Rd32 = ct1($Rss32)",
19161tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19162let Inst{13-5} = 0b000000100;
19163let Inst{31-21} = 0b10001000111;
19164let hasNewValue = 1;
19165let opNewValue = 0;
19166let prefersSlot3 = 1;
19167}
19168def S2_deinterleave : HInst<
19169(outs DoubleRegs:$Rdd32),
19170(ins DoubleRegs:$Rss32),
19171"$Rdd32 = deinterleave($Rss32)",
19172tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19173let Inst{13-5} = 0b000000100;
19174let Inst{31-21} = 0b10000000110;
19175let prefersSlot3 = 1;
19176}
19177def S2_extractu : HInst<
19178(outs IntRegs:$Rd32),
19179(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19180"$Rd32 = extractu($Rs32,#$Ii,#$II)",
19181tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
19182let Inst{13-13} = 0b0;
19183let Inst{31-23} = 0b100011010;
19184let hasNewValue = 1;
19185let opNewValue = 0;
19186let prefersSlot3 = 1;
19187}
19188def S2_extractu_rp : HInst<
19189(outs IntRegs:$Rd32),
19190(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
19191"$Rd32 = extractu($Rs32,$Rtt32)",
19192tc_a08b630b, TypeS_3op>, Enc_e07374 {
19193let Inst{7-5} = 0b000;
19194let Inst{13-13} = 0b0;
19195let Inst{31-21} = 0b11001001000;
19196let hasNewValue = 1;
19197let opNewValue = 0;
19198let prefersSlot3 = 1;
19199}
19200def S2_extractup : HInst<
19201(outs DoubleRegs:$Rdd32),
19202(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19203"$Rdd32 = extractu($Rss32,#$Ii,#$II)",
19204tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
19205let Inst{31-24} = 0b10000001;
19206let prefersSlot3 = 1;
19207}
19208def S2_extractup_rp : HInst<
19209(outs DoubleRegs:$Rdd32),
19210(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19211"$Rdd32 = extractu($Rss32,$Rtt32)",
19212tc_a08b630b, TypeS_3op>, Enc_a56825 {
19213let Inst{7-5} = 0b000;
19214let Inst{13-13} = 0b0;
19215let Inst{31-21} = 0b11000001000;
19216let prefersSlot3 = 1;
19217}
19218def S2_insert : HInst<
19219(outs IntRegs:$Rx32),
19220(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19221"$Rx32 = insert($Rs32,#$Ii,#$II)",
19222tc_bb831a7c, TypeS_2op>, Enc_a1e29d {
19223let Inst{13-13} = 0b0;
19224let Inst{31-23} = 0b100011110;
19225let hasNewValue = 1;
19226let opNewValue = 0;
19227let prefersSlot3 = 1;
19228let Constraints = "$Rx32 = $Rx32in";
19229}
19230def S2_insert_rp : HInst<
19231(outs IntRegs:$Rx32),
19232(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19233"$Rx32 = insert($Rs32,$Rtt32)",
19234tc_a4e22bbd, TypeS_3op>, Enc_179b35 {
19235let Inst{7-5} = 0b000;
19236let Inst{13-13} = 0b0;
19237let Inst{31-21} = 0b11001000000;
19238let hasNewValue = 1;
19239let opNewValue = 0;
19240let prefersSlot3 = 1;
19241let Constraints = "$Rx32 = $Rx32in";
19242}
19243def S2_insertp : HInst<
19244(outs DoubleRegs:$Rxx32),
19245(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19246"$Rxx32 = insert($Rss32,#$Ii,#$II)",
19247tc_bb831a7c, TypeS_2op>, Enc_143a3c {
19248let Inst{31-24} = 0b10000011;
19249let prefersSlot3 = 1;
19250let Constraints = "$Rxx32 = $Rxx32in";
19251}
19252def S2_insertp_rp : HInst<
19253(outs DoubleRegs:$Rxx32),
19254(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19255"$Rxx32 = insert($Rss32,$Rtt32)",
19256tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
19257let Inst{7-5} = 0b000;
19258let Inst{13-13} = 0b0;
19259let Inst{31-21} = 0b11001010000;
19260let prefersSlot3 = 1;
19261let Constraints = "$Rxx32 = $Rxx32in";
19262}
19263def S2_interleave : HInst<
19264(outs DoubleRegs:$Rdd32),
19265(ins DoubleRegs:$Rss32),
19266"$Rdd32 = interleave($Rss32)",
19267tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19268let Inst{13-5} = 0b000000101;
19269let Inst{31-21} = 0b10000000110;
19270let prefersSlot3 = 1;
19271}
19272def S2_lfsp : HInst<
19273(outs DoubleRegs:$Rdd32),
19274(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19275"$Rdd32 = lfs($Rss32,$Rtt32)",
19276tc_a08b630b, TypeS_3op>, Enc_a56825 {
19277let Inst{7-5} = 0b110;
19278let Inst{13-13} = 0b0;
19279let Inst{31-21} = 0b11000001100;
19280let prefersSlot3 = 1;
19281}
19282def S2_lsl_r_p : HInst<
19283(outs DoubleRegs:$Rdd32),
19284(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19285"$Rdd32 = lsl($Rss32,$Rt32)",
19286tc_5da50c4b, TypeS_3op>, Enc_927852 {
19287let Inst{7-5} = 0b110;
19288let Inst{13-13} = 0b0;
19289let Inst{31-21} = 0b11000011100;
19290}
19291def S2_lsl_r_p_acc : HInst<
19292(outs DoubleRegs:$Rxx32),
19293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19294"$Rxx32 += lsl($Rss32,$Rt32)",
19295tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19296let Inst{7-5} = 0b110;
19297let Inst{13-13} = 0b0;
19298let Inst{31-21} = 0b11001011110;
19299let prefersSlot3 = 1;
19300let Constraints = "$Rxx32 = $Rxx32in";
19301}
19302def S2_lsl_r_p_and : HInst<
19303(outs DoubleRegs:$Rxx32),
19304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19305"$Rxx32 &= lsl($Rss32,$Rt32)",
19306tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19307let Inst{7-5} = 0b110;
19308let Inst{13-13} = 0b0;
19309let Inst{31-21} = 0b11001011010;
19310let prefersSlot3 = 1;
19311let Constraints = "$Rxx32 = $Rxx32in";
19312}
19313def S2_lsl_r_p_nac : HInst<
19314(outs DoubleRegs:$Rxx32),
19315(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19316"$Rxx32 -= lsl($Rss32,$Rt32)",
19317tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19318let Inst{7-5} = 0b110;
19319let Inst{13-13} = 0b0;
19320let Inst{31-21} = 0b11001011100;
19321let prefersSlot3 = 1;
19322let Constraints = "$Rxx32 = $Rxx32in";
19323}
19324def S2_lsl_r_p_or : HInst<
19325(outs DoubleRegs:$Rxx32),
19326(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19327"$Rxx32 |= lsl($Rss32,$Rt32)",
19328tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19329let Inst{7-5} = 0b110;
19330let Inst{13-13} = 0b0;
19331let Inst{31-21} = 0b11001011000;
19332let prefersSlot3 = 1;
19333let Constraints = "$Rxx32 = $Rxx32in";
19334}
19335def S2_lsl_r_p_xor : HInst<
19336(outs DoubleRegs:$Rxx32),
19337(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19338"$Rxx32 ^= lsl($Rss32,$Rt32)",
19339tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19340let Inst{7-5} = 0b110;
19341let Inst{13-13} = 0b0;
19342let Inst{31-21} = 0b11001011011;
19343let prefersSlot3 = 1;
19344let Constraints = "$Rxx32 = $Rxx32in";
19345}
19346def S2_lsl_r_r : HInst<
19347(outs IntRegs:$Rd32),
19348(ins IntRegs:$Rs32, IntRegs:$Rt32),
19349"$Rd32 = lsl($Rs32,$Rt32)",
19350tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19351let Inst{7-5} = 0b110;
19352let Inst{13-13} = 0b0;
19353let Inst{31-21} = 0b11000110010;
19354let hasNewValue = 1;
19355let opNewValue = 0;
19356}
19357def S2_lsl_r_r_acc : HInst<
19358(outs IntRegs:$Rx32),
19359(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19360"$Rx32 += lsl($Rs32,$Rt32)",
19361tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19362let Inst{7-5} = 0b110;
19363let Inst{13-13} = 0b0;
19364let Inst{31-21} = 0b11001100110;
19365let hasNewValue = 1;
19366let opNewValue = 0;
19367let prefersSlot3 = 1;
19368let Constraints = "$Rx32 = $Rx32in";
19369}
19370def S2_lsl_r_r_and : HInst<
19371(outs IntRegs:$Rx32),
19372(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19373"$Rx32 &= lsl($Rs32,$Rt32)",
19374tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19375let Inst{7-5} = 0b110;
19376let Inst{13-13} = 0b0;
19377let Inst{31-21} = 0b11001100010;
19378let hasNewValue = 1;
19379let opNewValue = 0;
19380let prefersSlot3 = 1;
19381let Constraints = "$Rx32 = $Rx32in";
19382}
19383def S2_lsl_r_r_nac : HInst<
19384(outs IntRegs:$Rx32),
19385(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19386"$Rx32 -= lsl($Rs32,$Rt32)",
19387tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19388let Inst{7-5} = 0b110;
19389let Inst{13-13} = 0b0;
19390let Inst{31-21} = 0b11001100100;
19391let hasNewValue = 1;
19392let opNewValue = 0;
19393let prefersSlot3 = 1;
19394let Constraints = "$Rx32 = $Rx32in";
19395}
19396def S2_lsl_r_r_or : HInst<
19397(outs IntRegs:$Rx32),
19398(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19399"$Rx32 |= lsl($Rs32,$Rt32)",
19400tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19401let Inst{7-5} = 0b110;
19402let Inst{13-13} = 0b0;
19403let Inst{31-21} = 0b11001100000;
19404let hasNewValue = 1;
19405let opNewValue = 0;
19406let prefersSlot3 = 1;
19407let Constraints = "$Rx32 = $Rx32in";
19408}
19409def S2_lsl_r_vh : HInst<
19410(outs DoubleRegs:$Rdd32),
19411(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19412"$Rdd32 = vlslh($Rss32,$Rt32)",
19413tc_5da50c4b, TypeS_3op>, Enc_927852 {
19414let Inst{7-5} = 0b110;
19415let Inst{13-13} = 0b0;
19416let Inst{31-21} = 0b11000011010;
19417}
19418def S2_lsl_r_vw : HInst<
19419(outs DoubleRegs:$Rdd32),
19420(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19421"$Rdd32 = vlslw($Rss32,$Rt32)",
19422tc_5da50c4b, TypeS_3op>, Enc_927852 {
19423let Inst{7-5} = 0b110;
19424let Inst{13-13} = 0b0;
19425let Inst{31-21} = 0b11000011000;
19426}
19427def S2_lsr_i_p : HInst<
19428(outs DoubleRegs:$Rdd32),
19429(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
19430"$Rdd32 = lsr($Rss32,#$Ii)",
19431tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
19432let Inst{7-5} = 0b001;
19433let Inst{31-21} = 0b10000000000;
19434}
19435def S2_lsr_i_p_acc : HInst<
19436(outs DoubleRegs:$Rxx32),
19437(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19438"$Rxx32 += lsr($Rss32,#$Ii)",
19439tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19440let Inst{7-5} = 0b101;
19441let Inst{31-21} = 0b10000010000;
19442let prefersSlot3 = 1;
19443let Constraints = "$Rxx32 = $Rxx32in";
19444}
19445def S2_lsr_i_p_and : HInst<
19446(outs DoubleRegs:$Rxx32),
19447(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19448"$Rxx32 &= lsr($Rss32,#$Ii)",
19449tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19450let Inst{7-5} = 0b001;
19451let Inst{31-21} = 0b10000010010;
19452let prefersSlot3 = 1;
19453let Constraints = "$Rxx32 = $Rxx32in";
19454}
19455def S2_lsr_i_p_nac : HInst<
19456(outs DoubleRegs:$Rxx32),
19457(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19458"$Rxx32 -= lsr($Rss32,#$Ii)",
19459tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19460let Inst{7-5} = 0b001;
19461let Inst{31-21} = 0b10000010000;
19462let prefersSlot3 = 1;
19463let Constraints = "$Rxx32 = $Rxx32in";
19464}
19465def S2_lsr_i_p_or : HInst<
19466(outs DoubleRegs:$Rxx32),
19467(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19468"$Rxx32 |= lsr($Rss32,#$Ii)",
19469tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19470let Inst{7-5} = 0b101;
19471let Inst{31-21} = 0b10000010010;
19472let prefersSlot3 = 1;
19473let Constraints = "$Rxx32 = $Rxx32in";
19474}
19475def S2_lsr_i_p_xacc : HInst<
19476(outs DoubleRegs:$Rxx32),
19477(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19478"$Rxx32 ^= lsr($Rss32,#$Ii)",
19479tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19480let Inst{7-5} = 0b001;
19481let Inst{31-21} = 0b10000010100;
19482let prefersSlot3 = 1;
19483let Constraints = "$Rxx32 = $Rxx32in";
19484}
19485def S2_lsr_i_r : HInst<
19486(outs IntRegs:$Rd32),
19487(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19488"$Rd32 = lsr($Rs32,#$Ii)",
19489tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19490let Inst{7-5} = 0b001;
19491let Inst{13-13} = 0b0;
19492let Inst{31-21} = 0b10001100000;
19493let hasNewValue = 1;
19494let opNewValue = 0;
19495}
19496def S2_lsr_i_r_acc : HInst<
19497(outs IntRegs:$Rx32),
19498(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19499"$Rx32 += lsr($Rs32,#$Ii)",
19500tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19501let Inst{7-5} = 0b101;
19502let Inst{13-13} = 0b0;
19503let Inst{31-21} = 0b10001110000;
19504let hasNewValue = 1;
19505let opNewValue = 0;
19506let prefersSlot3 = 1;
19507let Constraints = "$Rx32 = $Rx32in";
19508}
19509def S2_lsr_i_r_and : HInst<
19510(outs IntRegs:$Rx32),
19511(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19512"$Rx32 &= lsr($Rs32,#$Ii)",
19513tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19514let Inst{7-5} = 0b001;
19515let Inst{13-13} = 0b0;
19516let Inst{31-21} = 0b10001110010;
19517let hasNewValue = 1;
19518let opNewValue = 0;
19519let prefersSlot3 = 1;
19520let Constraints = "$Rx32 = $Rx32in";
19521}
19522def S2_lsr_i_r_nac : HInst<
19523(outs IntRegs:$Rx32),
19524(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19525"$Rx32 -= lsr($Rs32,#$Ii)",
19526tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19527let Inst{7-5} = 0b001;
19528let Inst{13-13} = 0b0;
19529let Inst{31-21} = 0b10001110000;
19530let hasNewValue = 1;
19531let opNewValue = 0;
19532let prefersSlot3 = 1;
19533let Constraints = "$Rx32 = $Rx32in";
19534}
19535def S2_lsr_i_r_or : HInst<
19536(outs IntRegs:$Rx32),
19537(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19538"$Rx32 |= lsr($Rs32,#$Ii)",
19539tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19540let Inst{7-5} = 0b101;
19541let Inst{13-13} = 0b0;
19542let Inst{31-21} = 0b10001110010;
19543let hasNewValue = 1;
19544let opNewValue = 0;
19545let prefersSlot3 = 1;
19546let Constraints = "$Rx32 = $Rx32in";
19547}
19548def S2_lsr_i_r_xacc : HInst<
19549(outs IntRegs:$Rx32),
19550(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19551"$Rx32 ^= lsr($Rs32,#$Ii)",
19552tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19553let Inst{7-5} = 0b001;
19554let Inst{13-13} = 0b0;
19555let Inst{31-21} = 0b10001110100;
19556let hasNewValue = 1;
19557let opNewValue = 0;
19558let prefersSlot3 = 1;
19559let Constraints = "$Rx32 = $Rx32in";
19560}
19561def S2_lsr_i_vh : HInst<
19562(outs DoubleRegs:$Rdd32),
19563(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
19564"$Rdd32 = vlsrh($Rss32,#$Ii)",
19565tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
19566let Inst{7-5} = 0b001;
19567let Inst{13-12} = 0b00;
19568let Inst{31-21} = 0b10000000100;
19569}
19570def S2_lsr_i_vw : HInst<
19571(outs DoubleRegs:$Rdd32),
19572(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
19573"$Rdd32 = vlsrw($Rss32,#$Ii)",
19574tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
19575let Inst{7-5} = 0b001;
19576let Inst{13-13} = 0b0;
19577let Inst{31-21} = 0b10000000010;
19578}
19579def S2_lsr_r_p : HInst<
19580(outs DoubleRegs:$Rdd32),
19581(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19582"$Rdd32 = lsr($Rss32,$Rt32)",
19583tc_5da50c4b, TypeS_3op>, Enc_927852 {
19584let Inst{7-5} = 0b010;
19585let Inst{13-13} = 0b0;
19586let Inst{31-21} = 0b11000011100;
19587}
19588def S2_lsr_r_p_acc : HInst<
19589(outs DoubleRegs:$Rxx32),
19590(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19591"$Rxx32 += lsr($Rss32,$Rt32)",
19592tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19593let Inst{7-5} = 0b010;
19594let Inst{13-13} = 0b0;
19595let Inst{31-21} = 0b11001011110;
19596let prefersSlot3 = 1;
19597let Constraints = "$Rxx32 = $Rxx32in";
19598}
19599def S2_lsr_r_p_and : HInst<
19600(outs DoubleRegs:$Rxx32),
19601(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19602"$Rxx32 &= lsr($Rss32,$Rt32)",
19603tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19604let Inst{7-5} = 0b010;
19605let Inst{13-13} = 0b0;
19606let Inst{31-21} = 0b11001011010;
19607let prefersSlot3 = 1;
19608let Constraints = "$Rxx32 = $Rxx32in";
19609}
19610def S2_lsr_r_p_nac : HInst<
19611(outs DoubleRegs:$Rxx32),
19612(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19613"$Rxx32 -= lsr($Rss32,$Rt32)",
19614tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19615let Inst{7-5} = 0b010;
19616let Inst{13-13} = 0b0;
19617let Inst{31-21} = 0b11001011100;
19618let prefersSlot3 = 1;
19619let Constraints = "$Rxx32 = $Rxx32in";
19620}
19621def S2_lsr_r_p_or : HInst<
19622(outs DoubleRegs:$Rxx32),
19623(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19624"$Rxx32 |= lsr($Rss32,$Rt32)",
19625tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19626let Inst{7-5} = 0b010;
19627let Inst{13-13} = 0b0;
19628let Inst{31-21} = 0b11001011000;
19629let prefersSlot3 = 1;
19630let Constraints = "$Rxx32 = $Rxx32in";
19631}
19632def S2_lsr_r_p_xor : HInst<
19633(outs DoubleRegs:$Rxx32),
19634(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19635"$Rxx32 ^= lsr($Rss32,$Rt32)",
19636tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19637let Inst{7-5} = 0b010;
19638let Inst{13-13} = 0b0;
19639let Inst{31-21} = 0b11001011011;
19640let prefersSlot3 = 1;
19641let Constraints = "$Rxx32 = $Rxx32in";
19642}
19643def S2_lsr_r_r : HInst<
19644(outs IntRegs:$Rd32),
19645(ins IntRegs:$Rs32, IntRegs:$Rt32),
19646"$Rd32 = lsr($Rs32,$Rt32)",
19647tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19648let Inst{7-5} = 0b010;
19649let Inst{13-13} = 0b0;
19650let Inst{31-21} = 0b11000110010;
19651let hasNewValue = 1;
19652let opNewValue = 0;
19653}
19654def S2_lsr_r_r_acc : HInst<
19655(outs IntRegs:$Rx32),
19656(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19657"$Rx32 += lsr($Rs32,$Rt32)",
19658tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19659let Inst{7-5} = 0b010;
19660let Inst{13-13} = 0b0;
19661let Inst{31-21} = 0b11001100110;
19662let hasNewValue = 1;
19663let opNewValue = 0;
19664let prefersSlot3 = 1;
19665let Constraints = "$Rx32 = $Rx32in";
19666}
19667def S2_lsr_r_r_and : HInst<
19668(outs IntRegs:$Rx32),
19669(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19670"$Rx32 &= lsr($Rs32,$Rt32)",
19671tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19672let Inst{7-5} = 0b010;
19673let Inst{13-13} = 0b0;
19674let Inst{31-21} = 0b11001100010;
19675let hasNewValue = 1;
19676let opNewValue = 0;
19677let prefersSlot3 = 1;
19678let Constraints = "$Rx32 = $Rx32in";
19679}
19680def S2_lsr_r_r_nac : HInst<
19681(outs IntRegs:$Rx32),
19682(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19683"$Rx32 -= lsr($Rs32,$Rt32)",
19684tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19685let Inst{7-5} = 0b010;
19686let Inst{13-13} = 0b0;
19687let Inst{31-21} = 0b11001100100;
19688let hasNewValue = 1;
19689let opNewValue = 0;
19690let prefersSlot3 = 1;
19691let Constraints = "$Rx32 = $Rx32in";
19692}
19693def S2_lsr_r_r_or : HInst<
19694(outs IntRegs:$Rx32),
19695(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19696"$Rx32 |= lsr($Rs32,$Rt32)",
19697tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19698let Inst{7-5} = 0b010;
19699let Inst{13-13} = 0b0;
19700let Inst{31-21} = 0b11001100000;
19701let hasNewValue = 1;
19702let opNewValue = 0;
19703let prefersSlot3 = 1;
19704let Constraints = "$Rx32 = $Rx32in";
19705}
19706def S2_lsr_r_vh : HInst<
19707(outs DoubleRegs:$Rdd32),
19708(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19709"$Rdd32 = vlsrh($Rss32,$Rt32)",
19710tc_5da50c4b, TypeS_3op>, Enc_927852 {
19711let Inst{7-5} = 0b010;
19712let Inst{13-13} = 0b0;
19713let Inst{31-21} = 0b11000011010;
19714}
19715def S2_lsr_r_vw : HInst<
19716(outs DoubleRegs:$Rdd32),
19717(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19718"$Rdd32 = vlsrw($Rss32,$Rt32)",
19719tc_5da50c4b, TypeS_3op>, Enc_927852 {
19720let Inst{7-5} = 0b010;
19721let Inst{13-13} = 0b0;
19722let Inst{31-21} = 0b11000011000;
19723}
19724def S2_mask : HInst<
19725(outs IntRegs:$Rd32),
19726(ins u5_0Imm:$Ii, u5_0Imm:$II),
19727"$Rd32 = mask(#$Ii,#$II)",
19728tc_1fcb8495, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> {
19729let Inst{13-13} = 0b1;
19730let Inst{20-16} = 0b00000;
19731let Inst{31-23} = 0b100011010;
19732let hasNewValue = 1;
19733let opNewValue = 0;
19734let prefersSlot3 = 1;
19735}
19736def S2_packhl : HInst<
19737(outs DoubleRegs:$Rdd32),
19738(ins IntRegs:$Rs32, IntRegs:$Rt32),
19739"$Rdd32 = packhl($Rs32,$Rt32)",
19740tc_713b66bf, TypeALU32_3op>, Enc_be32a5 {
19741let Inst{7-5} = 0b000;
19742let Inst{13-13} = 0b0;
19743let Inst{31-21} = 0b11110101100;
19744let InputType = "reg";
19745}
19746def S2_parityp : HInst<
19747(outs IntRegs:$Rd32),
19748(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19749"$Rd32 = parity($Rss32,$Rtt32)",
19750tc_a08b630b, TypeALU64>, Enc_d2216a {
19751let Inst{7-5} = 0b000;
19752let Inst{13-13} = 0b0;
19753let Inst{31-21} = 0b11010000000;
19754let hasNewValue = 1;
19755let opNewValue = 0;
19756let prefersSlot3 = 1;
19757}
19758def S2_pstorerbf_io : HInst<
19759(outs),
19760(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19761"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
19762tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19763let Inst{2-2} = 0b0;
19764let Inst{31-21} = 0b01000100000;
19765let isPredicated = 1;
19766let isPredicatedFalse = 1;
19767let addrMode = BaseImmOffset;
19768let accessSize = ByteAccess;
19769let mayStore = 1;
19770let BaseOpcode = "S2_storerb_io";
19771let CextOpcode = "S2_storerb";
19772let InputType = "imm";
19773let isNVStorable = 1;
19774let isExtendable = 1;
19775let opExtendable = 2;
19776let isExtentSigned = 0;
19777let opExtentBits = 6;
19778let opExtentAlign = 0;
19779}
19780def S2_pstorerbf_pi : HInst<
19781(outs IntRegs:$Rx32),
19782(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19783"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
19784tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19785let Inst{2-2} = 0b1;
19786let Inst{7-7} = 0b0;
19787let Inst{13-13} = 0b1;
19788let Inst{31-21} = 0b10101011000;
19789let isPredicated = 1;
19790let isPredicatedFalse = 1;
19791let addrMode = PostInc;
19792let accessSize = ByteAccess;
19793let mayStore = 1;
19794let BaseOpcode = "S2_storerb_pi";
19795let isNVStorable = 1;
19796let Constraints = "$Rx32 = $Rx32in";
19797}
19798def S2_pstorerbf_zomap : HInst<
19799(outs),
19800(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19801"if (!$Pv4) memb($Rs32) = $Rt32",
19802tc_8035e91f, TypeMAPPING> {
19803let isPseudo = 1;
19804let isCodeGenOnly = 1;
19805}
19806def S2_pstorerbfnew_pi : HInst<
19807(outs IntRegs:$Rx32),
19808(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19809"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19810tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19811let Inst{2-2} = 0b1;
19812let Inst{7-7} = 0b1;
19813let Inst{13-13} = 0b1;
19814let Inst{31-21} = 0b10101011000;
19815let isPredicated = 1;
19816let isPredicatedFalse = 1;
19817let addrMode = PostInc;
19818let accessSize = ByteAccess;
19819let isPredicatedNew = 1;
19820let mayStore = 1;
19821let BaseOpcode = "S2_storerb_pi";
19822let isNVStorable = 1;
19823let Constraints = "$Rx32 = $Rx32in";
19824}
19825def S2_pstorerbnewf_io : HInst<
19826(outs),
19827(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19828"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19829tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19830let Inst{2-2} = 0b0;
19831let Inst{12-11} = 0b00;
19832let Inst{31-21} = 0b01000100101;
19833let isPredicated = 1;
19834let isPredicatedFalse = 1;
19835let addrMode = BaseImmOffset;
19836let accessSize = ByteAccess;
19837let isNVStore = 1;
19838let isNewValue = 1;
19839let isRestrictNoSlot1Store = 1;
19840let mayStore = 1;
19841let BaseOpcode = "S2_storerb_io";
19842let CextOpcode = "S2_storerb";
19843let InputType = "imm";
19844let isExtendable = 1;
19845let opExtendable = 2;
19846let isExtentSigned = 0;
19847let opExtentBits = 6;
19848let opExtentAlign = 0;
19849let opNewValue = 3;
19850}
19851def S2_pstorerbnewf_pi : HInst<
19852(outs IntRegs:$Rx32),
19853(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19854"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19855tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19856let Inst{2-2} = 0b1;
19857let Inst{7-7} = 0b0;
19858let Inst{13-11} = 0b100;
19859let Inst{31-21} = 0b10101011101;
19860let isPredicated = 1;
19861let isPredicatedFalse = 1;
19862let addrMode = PostInc;
19863let accessSize = ByteAccess;
19864let isNVStore = 1;
19865let isNewValue = 1;
19866let isRestrictNoSlot1Store = 1;
19867let mayStore = 1;
19868let BaseOpcode = "S2_storerb_pi";
19869let CextOpcode = "S2_storerb";
19870let opNewValue = 4;
19871let Constraints = "$Rx32 = $Rx32in";
19872}
19873def S2_pstorerbnewf_zomap : HInst<
19874(outs),
19875(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19876"if (!$Pv4) memb($Rs32) = $Nt8.new",
19877tc_011e0e9d, TypeMAPPING> {
19878let isPseudo = 1;
19879let isCodeGenOnly = 1;
19880let opNewValue = 2;
19881}
19882def S2_pstorerbnewfnew_pi : HInst<
19883(outs IntRegs:$Rx32),
19884(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19885"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19886tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19887let Inst{2-2} = 0b1;
19888let Inst{7-7} = 0b1;
19889let Inst{13-11} = 0b100;
19890let Inst{31-21} = 0b10101011101;
19891let isPredicated = 1;
19892let isPredicatedFalse = 1;
19893let addrMode = PostInc;
19894let accessSize = ByteAccess;
19895let isNVStore = 1;
19896let isPredicatedNew = 1;
19897let isNewValue = 1;
19898let isRestrictNoSlot1Store = 1;
19899let mayStore = 1;
19900let BaseOpcode = "S2_storerb_pi";
19901let CextOpcode = "S2_storerb";
19902let opNewValue = 4;
19903let Constraints = "$Rx32 = $Rx32in";
19904}
19905def S2_pstorerbnewt_io : HInst<
19906(outs),
19907(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19908"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19909tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19910let Inst{2-2} = 0b0;
19911let Inst{12-11} = 0b00;
19912let Inst{31-21} = 0b01000000101;
19913let isPredicated = 1;
19914let addrMode = BaseImmOffset;
19915let accessSize = ByteAccess;
19916let isNVStore = 1;
19917let isNewValue = 1;
19918let isRestrictNoSlot1Store = 1;
19919let mayStore = 1;
19920let BaseOpcode = "S2_storerb_io";
19921let CextOpcode = "S2_storerb";
19922let InputType = "imm";
19923let isExtendable = 1;
19924let opExtendable = 2;
19925let isExtentSigned = 0;
19926let opExtentBits = 6;
19927let opExtentAlign = 0;
19928let opNewValue = 3;
19929}
19930def S2_pstorerbnewt_pi : HInst<
19931(outs IntRegs:$Rx32),
19932(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19933"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19934tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19935let Inst{2-2} = 0b0;
19936let Inst{7-7} = 0b0;
19937let Inst{13-11} = 0b100;
19938let Inst{31-21} = 0b10101011101;
19939let isPredicated = 1;
19940let addrMode = PostInc;
19941let accessSize = ByteAccess;
19942let isNVStore = 1;
19943let isNewValue = 1;
19944let isRestrictNoSlot1Store = 1;
19945let mayStore = 1;
19946let BaseOpcode = "S2_storerb_pi";
19947let CextOpcode = "S2_storerb";
19948let opNewValue = 4;
19949let Constraints = "$Rx32 = $Rx32in";
19950}
19951def S2_pstorerbnewt_zomap : HInst<
19952(outs),
19953(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19954"if ($Pv4) memb($Rs32) = $Nt8.new",
19955tc_011e0e9d, TypeMAPPING> {
19956let isPseudo = 1;
19957let isCodeGenOnly = 1;
19958let opNewValue = 2;
19959}
19960def S2_pstorerbnewtnew_pi : HInst<
19961(outs IntRegs:$Rx32),
19962(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19963"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19964tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19965let Inst{2-2} = 0b0;
19966let Inst{7-7} = 0b1;
19967let Inst{13-11} = 0b100;
19968let Inst{31-21} = 0b10101011101;
19969let isPredicated = 1;
19970let addrMode = PostInc;
19971let accessSize = ByteAccess;
19972let isNVStore = 1;
19973let isPredicatedNew = 1;
19974let isNewValue = 1;
19975let isRestrictNoSlot1Store = 1;
19976let mayStore = 1;
19977let BaseOpcode = "S2_storerb_pi";
19978let CextOpcode = "S2_storerb";
19979let opNewValue = 4;
19980let Constraints = "$Rx32 = $Rx32in";
19981}
19982def S2_pstorerbt_io : HInst<
19983(outs),
19984(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19985"if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
19986tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19987let Inst{2-2} = 0b0;
19988let Inst{31-21} = 0b01000000000;
19989let isPredicated = 1;
19990let addrMode = BaseImmOffset;
19991let accessSize = ByteAccess;
19992let mayStore = 1;
19993let BaseOpcode = "S2_storerb_io";
19994let CextOpcode = "S2_storerb";
19995let InputType = "imm";
19996let isNVStorable = 1;
19997let isExtendable = 1;
19998let opExtendable = 2;
19999let isExtentSigned = 0;
20000let opExtentBits = 6;
20001let opExtentAlign = 0;
20002}
20003def S2_pstorerbt_pi : HInst<
20004(outs IntRegs:$Rx32),
20005(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20006"if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
20007tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
20008let Inst{2-2} = 0b0;
20009let Inst{7-7} = 0b0;
20010let Inst{13-13} = 0b1;
20011let Inst{31-21} = 0b10101011000;
20012let isPredicated = 1;
20013let addrMode = PostInc;
20014let accessSize = ByteAccess;
20015let mayStore = 1;
20016let BaseOpcode = "S2_storerb_pi";
20017let isNVStorable = 1;
20018let Constraints = "$Rx32 = $Rx32in";
20019}
20020def S2_pstorerbt_zomap : HInst<
20021(outs),
20022(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20023"if ($Pv4) memb($Rs32) = $Rt32",
20024tc_8035e91f, TypeMAPPING> {
20025let isPseudo = 1;
20026let isCodeGenOnly = 1;
20027}
20028def S2_pstorerbtnew_pi : HInst<
20029(outs IntRegs:$Rx32),
20030(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20031"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
20032tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
20033let Inst{2-2} = 0b0;
20034let Inst{7-7} = 0b1;
20035let Inst{13-13} = 0b1;
20036let Inst{31-21} = 0b10101011000;
20037let isPredicated = 1;
20038let addrMode = PostInc;
20039let accessSize = ByteAccess;
20040let isPredicatedNew = 1;
20041let mayStore = 1;
20042let BaseOpcode = "S2_storerb_pi";
20043let isNVStorable = 1;
20044let Constraints = "$Rx32 = $Rx32in";
20045}
20046def S2_pstorerdf_io : HInst<
20047(outs),
20048(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20049"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
20050tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20051let Inst{2-2} = 0b0;
20052let Inst{31-21} = 0b01000100110;
20053let isPredicated = 1;
20054let isPredicatedFalse = 1;
20055let addrMode = BaseImmOffset;
20056let accessSize = DoubleWordAccess;
20057let mayStore = 1;
20058let BaseOpcode = "S2_storerd_io";
20059let CextOpcode = "S2_storerd";
20060let InputType = "imm";
20061let isExtendable = 1;
20062let opExtendable = 2;
20063let isExtentSigned = 0;
20064let opExtentBits = 9;
20065let opExtentAlign = 3;
20066}
20067def S2_pstorerdf_pi : HInst<
20068(outs IntRegs:$Rx32),
20069(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20070"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
20071tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20072let Inst{2-2} = 0b1;
20073let Inst{7-7} = 0b0;
20074let Inst{13-13} = 0b1;
20075let Inst{31-21} = 0b10101011110;
20076let isPredicated = 1;
20077let isPredicatedFalse = 1;
20078let addrMode = PostInc;
20079let accessSize = DoubleWordAccess;
20080let mayStore = 1;
20081let BaseOpcode = "S2_storerd_pi";
20082let CextOpcode = "S2_storerd";
20083let Constraints = "$Rx32 = $Rx32in";
20084}
20085def S2_pstorerdf_zomap : HInst<
20086(outs),
20087(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20088"if (!$Pv4) memd($Rs32) = $Rtt32",
20089tc_8035e91f, TypeMAPPING> {
20090let isPseudo = 1;
20091let isCodeGenOnly = 1;
20092}
20093def S2_pstorerdfnew_pi : HInst<
20094(outs IntRegs:$Rx32),
20095(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20096"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20097tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20098let Inst{2-2} = 0b1;
20099let Inst{7-7} = 0b1;
20100let Inst{13-13} = 0b1;
20101let Inst{31-21} = 0b10101011110;
20102let isPredicated = 1;
20103let isPredicatedFalse = 1;
20104let addrMode = PostInc;
20105let accessSize = DoubleWordAccess;
20106let isPredicatedNew = 1;
20107let mayStore = 1;
20108let BaseOpcode = "S2_storerd_pi";
20109let CextOpcode = "S2_storerd";
20110let Constraints = "$Rx32 = $Rx32in";
20111}
20112def S2_pstorerdt_io : HInst<
20113(outs),
20114(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20115"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
20116tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20117let Inst{2-2} = 0b0;
20118let Inst{31-21} = 0b01000000110;
20119let isPredicated = 1;
20120let addrMode = BaseImmOffset;
20121let accessSize = DoubleWordAccess;
20122let mayStore = 1;
20123let BaseOpcode = "S2_storerd_io";
20124let CextOpcode = "S2_storerd";
20125let InputType = "imm";
20126let isExtendable = 1;
20127let opExtendable = 2;
20128let isExtentSigned = 0;
20129let opExtentBits = 9;
20130let opExtentAlign = 3;
20131}
20132def S2_pstorerdt_pi : HInst<
20133(outs IntRegs:$Rx32),
20134(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20135"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
20136tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20137let Inst{2-2} = 0b0;
20138let Inst{7-7} = 0b0;
20139let Inst{13-13} = 0b1;
20140let Inst{31-21} = 0b10101011110;
20141let isPredicated = 1;
20142let addrMode = PostInc;
20143let accessSize = DoubleWordAccess;
20144let mayStore = 1;
20145let BaseOpcode = "S2_storerd_pi";
20146let CextOpcode = "S2_storerd";
20147let Constraints = "$Rx32 = $Rx32in";
20148}
20149def S2_pstorerdt_zomap : HInst<
20150(outs),
20151(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20152"if ($Pv4) memd($Rs32) = $Rtt32",
20153tc_8035e91f, TypeMAPPING> {
20154let isPseudo = 1;
20155let isCodeGenOnly = 1;
20156}
20157def S2_pstorerdtnew_pi : HInst<
20158(outs IntRegs:$Rx32),
20159(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20160"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20161tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20162let Inst{2-2} = 0b0;
20163let Inst{7-7} = 0b1;
20164let Inst{13-13} = 0b1;
20165let Inst{31-21} = 0b10101011110;
20166let isPredicated = 1;
20167let addrMode = PostInc;
20168let accessSize = DoubleWordAccess;
20169let isPredicatedNew = 1;
20170let mayStore = 1;
20171let BaseOpcode = "S2_storerd_pi";
20172let CextOpcode = "S2_storerd";
20173let Constraints = "$Rx32 = $Rx32in";
20174}
20175def S2_pstorerff_io : HInst<
20176(outs),
20177(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20178"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20179tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20180let Inst{2-2} = 0b0;
20181let Inst{31-21} = 0b01000100011;
20182let isPredicated = 1;
20183let isPredicatedFalse = 1;
20184let addrMode = BaseImmOffset;
20185let accessSize = HalfWordAccess;
20186let mayStore = 1;
20187let BaseOpcode = "S2_storerf_io";
20188let CextOpcode = "S2_storerf";
20189let InputType = "imm";
20190let isExtendable = 1;
20191let opExtendable = 2;
20192let isExtentSigned = 0;
20193let opExtentBits = 7;
20194let opExtentAlign = 1;
20195}
20196def S2_pstorerff_pi : HInst<
20197(outs IntRegs:$Rx32),
20198(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20199"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20200tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20201let Inst{2-2} = 0b1;
20202let Inst{7-7} = 0b0;
20203let Inst{13-13} = 0b1;
20204let Inst{31-21} = 0b10101011011;
20205let isPredicated = 1;
20206let isPredicatedFalse = 1;
20207let addrMode = PostInc;
20208let accessSize = HalfWordAccess;
20209let mayStore = 1;
20210let BaseOpcode = "S2_storerf_pi";
20211let CextOpcode = "S2_storerf";
20212let Constraints = "$Rx32 = $Rx32in";
20213}
20214def S2_pstorerff_zomap : HInst<
20215(outs),
20216(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20217"if (!$Pv4) memh($Rs32) = $Rt32.h",
20218tc_8035e91f, TypeMAPPING> {
20219let isPseudo = 1;
20220let isCodeGenOnly = 1;
20221}
20222def S2_pstorerffnew_pi : HInst<
20223(outs IntRegs:$Rx32),
20224(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20225"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20226tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20227let Inst{2-2} = 0b1;
20228let Inst{7-7} = 0b1;
20229let Inst{13-13} = 0b1;
20230let Inst{31-21} = 0b10101011011;
20231let isPredicated = 1;
20232let isPredicatedFalse = 1;
20233let addrMode = PostInc;
20234let accessSize = HalfWordAccess;
20235let isPredicatedNew = 1;
20236let mayStore = 1;
20237let BaseOpcode = "S2_storerf_pi";
20238let CextOpcode = "S2_storerf";
20239let Constraints = "$Rx32 = $Rx32in";
20240}
20241def S2_pstorerft_io : HInst<
20242(outs),
20243(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20244"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20245tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20246let Inst{2-2} = 0b0;
20247let Inst{31-21} = 0b01000000011;
20248let isPredicated = 1;
20249let addrMode = BaseImmOffset;
20250let accessSize = HalfWordAccess;
20251let mayStore = 1;
20252let BaseOpcode = "S2_storerf_io";
20253let CextOpcode = "S2_storerf";
20254let InputType = "imm";
20255let isExtendable = 1;
20256let opExtendable = 2;
20257let isExtentSigned = 0;
20258let opExtentBits = 7;
20259let opExtentAlign = 1;
20260}
20261def S2_pstorerft_pi : HInst<
20262(outs IntRegs:$Rx32),
20263(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20264"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20265tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20266let Inst{2-2} = 0b0;
20267let Inst{7-7} = 0b0;
20268let Inst{13-13} = 0b1;
20269let Inst{31-21} = 0b10101011011;
20270let isPredicated = 1;
20271let addrMode = PostInc;
20272let accessSize = HalfWordAccess;
20273let mayStore = 1;
20274let BaseOpcode = "S2_storerf_pi";
20275let CextOpcode = "S2_storerf";
20276let Constraints = "$Rx32 = $Rx32in";
20277}
20278def S2_pstorerft_zomap : HInst<
20279(outs),
20280(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20281"if ($Pv4) memh($Rs32) = $Rt32.h",
20282tc_8035e91f, TypeMAPPING> {
20283let isPseudo = 1;
20284let isCodeGenOnly = 1;
20285}
20286def S2_pstorerftnew_pi : HInst<
20287(outs IntRegs:$Rx32),
20288(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20289"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20290tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20291let Inst{2-2} = 0b0;
20292let Inst{7-7} = 0b1;
20293let Inst{13-13} = 0b1;
20294let Inst{31-21} = 0b10101011011;
20295let isPredicated = 1;
20296let addrMode = PostInc;
20297let accessSize = HalfWordAccess;
20298let isPredicatedNew = 1;
20299let mayStore = 1;
20300let BaseOpcode = "S2_storerf_pi";
20301let CextOpcode = "S2_storerf";
20302let Constraints = "$Rx32 = $Rx32in";
20303}
20304def S2_pstorerhf_io : HInst<
20305(outs),
20306(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20307"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
20308tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20309let Inst{2-2} = 0b0;
20310let Inst{31-21} = 0b01000100010;
20311let isPredicated = 1;
20312let isPredicatedFalse = 1;
20313let addrMode = BaseImmOffset;
20314let accessSize = HalfWordAccess;
20315let mayStore = 1;
20316let BaseOpcode = "S2_storerh_io";
20317let CextOpcode = "S2_storerh";
20318let InputType = "imm";
20319let isNVStorable = 1;
20320let isExtendable = 1;
20321let opExtendable = 2;
20322let isExtentSigned = 0;
20323let opExtentBits = 7;
20324let opExtentAlign = 1;
20325}
20326def S2_pstorerhf_pi : HInst<
20327(outs IntRegs:$Rx32),
20328(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20329"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
20330tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20331let Inst{2-2} = 0b1;
20332let Inst{7-7} = 0b0;
20333let Inst{13-13} = 0b1;
20334let Inst{31-21} = 0b10101011010;
20335let isPredicated = 1;
20336let isPredicatedFalse = 1;
20337let addrMode = PostInc;
20338let accessSize = HalfWordAccess;
20339let mayStore = 1;
20340let BaseOpcode = "S2_storerh_pi";
20341let isNVStorable = 1;
20342let Constraints = "$Rx32 = $Rx32in";
20343}
20344def S2_pstorerhf_zomap : HInst<
20345(outs),
20346(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20347"if (!$Pv4) memh($Rs32) = $Rt32",
20348tc_8035e91f, TypeMAPPING> {
20349let isPseudo = 1;
20350let isCodeGenOnly = 1;
20351}
20352def S2_pstorerhfnew_pi : HInst<
20353(outs IntRegs:$Rx32),
20354(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20355"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20356tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20357let Inst{2-2} = 0b1;
20358let Inst{7-7} = 0b1;
20359let Inst{13-13} = 0b1;
20360let Inst{31-21} = 0b10101011010;
20361let isPredicated = 1;
20362let isPredicatedFalse = 1;
20363let addrMode = PostInc;
20364let accessSize = HalfWordAccess;
20365let isPredicatedNew = 1;
20366let mayStore = 1;
20367let BaseOpcode = "S2_storerh_pi";
20368let isNVStorable = 1;
20369let Constraints = "$Rx32 = $Rx32in";
20370}
20371def S2_pstorerhnewf_io : HInst<
20372(outs),
20373(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20374"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20375tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20376let Inst{2-2} = 0b0;
20377let Inst{12-11} = 0b01;
20378let Inst{31-21} = 0b01000100101;
20379let isPredicated = 1;
20380let isPredicatedFalse = 1;
20381let addrMode = BaseImmOffset;
20382let accessSize = HalfWordAccess;
20383let isNVStore = 1;
20384let isNewValue = 1;
20385let isRestrictNoSlot1Store = 1;
20386let mayStore = 1;
20387let BaseOpcode = "S2_storerh_io";
20388let CextOpcode = "S2_storerh";
20389let InputType = "imm";
20390let isExtendable = 1;
20391let opExtendable = 2;
20392let isExtentSigned = 0;
20393let opExtentBits = 7;
20394let opExtentAlign = 1;
20395let opNewValue = 3;
20396}
20397def S2_pstorerhnewf_pi : HInst<
20398(outs IntRegs:$Rx32),
20399(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20400"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20401tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20402let Inst{2-2} = 0b1;
20403let Inst{7-7} = 0b0;
20404let Inst{13-11} = 0b101;
20405let Inst{31-21} = 0b10101011101;
20406let isPredicated = 1;
20407let isPredicatedFalse = 1;
20408let addrMode = PostInc;
20409let accessSize = HalfWordAccess;
20410let isNVStore = 1;
20411let isNewValue = 1;
20412let isRestrictNoSlot1Store = 1;
20413let mayStore = 1;
20414let BaseOpcode = "S2_storerh_pi";
20415let CextOpcode = "S2_storerh";
20416let opNewValue = 4;
20417let Constraints = "$Rx32 = $Rx32in";
20418}
20419def S2_pstorerhnewf_zomap : HInst<
20420(outs),
20421(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20422"if (!$Pv4) memh($Rs32) = $Nt8.new",
20423tc_011e0e9d, TypeMAPPING> {
20424let isPseudo = 1;
20425let isCodeGenOnly = 1;
20426let opNewValue = 2;
20427}
20428def S2_pstorerhnewfnew_pi : HInst<
20429(outs IntRegs:$Rx32),
20430(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20431"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20432tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20433let Inst{2-2} = 0b1;
20434let Inst{7-7} = 0b1;
20435let Inst{13-11} = 0b101;
20436let Inst{31-21} = 0b10101011101;
20437let isPredicated = 1;
20438let isPredicatedFalse = 1;
20439let addrMode = PostInc;
20440let accessSize = HalfWordAccess;
20441let isNVStore = 1;
20442let isPredicatedNew = 1;
20443let isNewValue = 1;
20444let isRestrictNoSlot1Store = 1;
20445let mayStore = 1;
20446let BaseOpcode = "S2_storerh_pi";
20447let CextOpcode = "S2_storerh";
20448let opNewValue = 4;
20449let Constraints = "$Rx32 = $Rx32in";
20450}
20451def S2_pstorerhnewt_io : HInst<
20452(outs),
20453(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20454"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20455tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20456let Inst{2-2} = 0b0;
20457let Inst{12-11} = 0b01;
20458let Inst{31-21} = 0b01000000101;
20459let isPredicated = 1;
20460let addrMode = BaseImmOffset;
20461let accessSize = HalfWordAccess;
20462let isNVStore = 1;
20463let isNewValue = 1;
20464let isRestrictNoSlot1Store = 1;
20465let mayStore = 1;
20466let BaseOpcode = "S2_storerh_io";
20467let CextOpcode = "S2_storerh";
20468let InputType = "imm";
20469let isExtendable = 1;
20470let opExtendable = 2;
20471let isExtentSigned = 0;
20472let opExtentBits = 7;
20473let opExtentAlign = 1;
20474let opNewValue = 3;
20475}
20476def S2_pstorerhnewt_pi : HInst<
20477(outs IntRegs:$Rx32),
20478(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20479"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20480tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20481let Inst{2-2} = 0b0;
20482let Inst{7-7} = 0b0;
20483let Inst{13-11} = 0b101;
20484let Inst{31-21} = 0b10101011101;
20485let isPredicated = 1;
20486let addrMode = PostInc;
20487let accessSize = HalfWordAccess;
20488let isNVStore = 1;
20489let isNewValue = 1;
20490let isRestrictNoSlot1Store = 1;
20491let mayStore = 1;
20492let BaseOpcode = "S2_storerh_pi";
20493let CextOpcode = "S2_storerh";
20494let opNewValue = 4;
20495let Constraints = "$Rx32 = $Rx32in";
20496}
20497def S2_pstorerhnewt_zomap : HInst<
20498(outs),
20499(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20500"if ($Pv4) memh($Rs32) = $Nt8.new",
20501tc_011e0e9d, TypeMAPPING> {
20502let isPseudo = 1;
20503let isCodeGenOnly = 1;
20504let opNewValue = 2;
20505}
20506def S2_pstorerhnewtnew_pi : HInst<
20507(outs IntRegs:$Rx32),
20508(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20509"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20510tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20511let Inst{2-2} = 0b0;
20512let Inst{7-7} = 0b1;
20513let Inst{13-11} = 0b101;
20514let Inst{31-21} = 0b10101011101;
20515let isPredicated = 1;
20516let addrMode = PostInc;
20517let accessSize = HalfWordAccess;
20518let isNVStore = 1;
20519let isPredicatedNew = 1;
20520let isNewValue = 1;
20521let isRestrictNoSlot1Store = 1;
20522let mayStore = 1;
20523let BaseOpcode = "S2_storerh_pi";
20524let CextOpcode = "S2_storerh";
20525let opNewValue = 4;
20526let Constraints = "$Rx32 = $Rx32in";
20527}
20528def S2_pstorerht_io : HInst<
20529(outs),
20530(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20531"if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
20532tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20533let Inst{2-2} = 0b0;
20534let Inst{31-21} = 0b01000000010;
20535let isPredicated = 1;
20536let addrMode = BaseImmOffset;
20537let accessSize = HalfWordAccess;
20538let mayStore = 1;
20539let BaseOpcode = "S2_storerh_io";
20540let CextOpcode = "S2_storerh";
20541let InputType = "imm";
20542let isNVStorable = 1;
20543let isExtendable = 1;
20544let opExtendable = 2;
20545let isExtentSigned = 0;
20546let opExtentBits = 7;
20547let opExtentAlign = 1;
20548}
20549def S2_pstorerht_pi : HInst<
20550(outs IntRegs:$Rx32),
20551(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20552"if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
20553tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20554let Inst{2-2} = 0b0;
20555let Inst{7-7} = 0b0;
20556let Inst{13-13} = 0b1;
20557let Inst{31-21} = 0b10101011010;
20558let isPredicated = 1;
20559let addrMode = PostInc;
20560let accessSize = HalfWordAccess;
20561let mayStore = 1;
20562let BaseOpcode = "S2_storerh_pi";
20563let isNVStorable = 1;
20564let Constraints = "$Rx32 = $Rx32in";
20565}
20566def S2_pstorerht_zomap : HInst<
20567(outs),
20568(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20569"if ($Pv4) memh($Rs32) = $Rt32",
20570tc_8035e91f, TypeMAPPING> {
20571let isPseudo = 1;
20572let isCodeGenOnly = 1;
20573}
20574def S2_pstorerhtnew_pi : HInst<
20575(outs IntRegs:$Rx32),
20576(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20577"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20578tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20579let Inst{2-2} = 0b0;
20580let Inst{7-7} = 0b1;
20581let Inst{13-13} = 0b1;
20582let Inst{31-21} = 0b10101011010;
20583let isPredicated = 1;
20584let addrMode = PostInc;
20585let accessSize = HalfWordAccess;
20586let isPredicatedNew = 1;
20587let mayStore = 1;
20588let BaseOpcode = "S2_storerh_pi";
20589let isNVStorable = 1;
20590let Constraints = "$Rx32 = $Rx32in";
20591}
20592def S2_pstorerif_io : HInst<
20593(outs),
20594(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20595"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
20596tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20597let Inst{2-2} = 0b0;
20598let Inst{31-21} = 0b01000100100;
20599let isPredicated = 1;
20600let isPredicatedFalse = 1;
20601let addrMode = BaseImmOffset;
20602let accessSize = WordAccess;
20603let mayStore = 1;
20604let BaseOpcode = "S2_storeri_io";
20605let CextOpcode = "S2_storeri";
20606let InputType = "imm";
20607let isNVStorable = 1;
20608let isExtendable = 1;
20609let opExtendable = 2;
20610let isExtentSigned = 0;
20611let opExtentBits = 8;
20612let opExtentAlign = 2;
20613}
20614def S2_pstorerif_pi : HInst<
20615(outs IntRegs:$Rx32),
20616(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20617"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
20618tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20619let Inst{2-2} = 0b1;
20620let Inst{7-7} = 0b0;
20621let Inst{13-13} = 0b1;
20622let Inst{31-21} = 0b10101011100;
20623let isPredicated = 1;
20624let isPredicatedFalse = 1;
20625let addrMode = PostInc;
20626let accessSize = WordAccess;
20627let mayStore = 1;
20628let BaseOpcode = "S2_storeri_pi";
20629let isNVStorable = 1;
20630let Constraints = "$Rx32 = $Rx32in";
20631}
20632def S2_pstorerif_zomap : HInst<
20633(outs),
20634(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20635"if (!$Pv4) memw($Rs32) = $Rt32",
20636tc_8035e91f, TypeMAPPING> {
20637let isPseudo = 1;
20638let isCodeGenOnly = 1;
20639}
20640def S2_pstorerifnew_pi : HInst<
20641(outs IntRegs:$Rx32),
20642(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20643"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20644tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20645let Inst{2-2} = 0b1;
20646let Inst{7-7} = 0b1;
20647let Inst{13-13} = 0b1;
20648let Inst{31-21} = 0b10101011100;
20649let isPredicated = 1;
20650let isPredicatedFalse = 1;
20651let addrMode = PostInc;
20652let accessSize = WordAccess;
20653let isPredicatedNew = 1;
20654let mayStore = 1;
20655let BaseOpcode = "S2_storeri_pi";
20656let CextOpcode = "S2_storeri";
20657let isNVStorable = 1;
20658let Constraints = "$Rx32 = $Rx32in";
20659}
20660def S2_pstorerinewf_io : HInst<
20661(outs),
20662(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20663"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20664tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20665let Inst{2-2} = 0b0;
20666let Inst{12-11} = 0b10;
20667let Inst{31-21} = 0b01000100101;
20668let isPredicated = 1;
20669let isPredicatedFalse = 1;
20670let addrMode = BaseImmOffset;
20671let accessSize = WordAccess;
20672let isNVStore = 1;
20673let isNewValue = 1;
20674let isRestrictNoSlot1Store = 1;
20675let mayStore = 1;
20676let BaseOpcode = "S2_storeri_io";
20677let CextOpcode = "S2_storeri";
20678let InputType = "imm";
20679let isExtendable = 1;
20680let opExtendable = 2;
20681let isExtentSigned = 0;
20682let opExtentBits = 8;
20683let opExtentAlign = 2;
20684let opNewValue = 3;
20685}
20686def S2_pstorerinewf_pi : HInst<
20687(outs IntRegs:$Rx32),
20688(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20689"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20690tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20691let Inst{2-2} = 0b1;
20692let Inst{7-7} = 0b0;
20693let Inst{13-11} = 0b110;
20694let Inst{31-21} = 0b10101011101;
20695let isPredicated = 1;
20696let isPredicatedFalse = 1;
20697let addrMode = PostInc;
20698let accessSize = WordAccess;
20699let isNVStore = 1;
20700let isNewValue = 1;
20701let isRestrictNoSlot1Store = 1;
20702let mayStore = 1;
20703let BaseOpcode = "S2_storeri_pi";
20704let CextOpcode = "S2_storeri";
20705let opNewValue = 4;
20706let Constraints = "$Rx32 = $Rx32in";
20707}
20708def S2_pstorerinewf_zomap : HInst<
20709(outs),
20710(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20711"if (!$Pv4) memw($Rs32) = $Nt8.new",
20712tc_011e0e9d, TypeMAPPING> {
20713let isPseudo = 1;
20714let isCodeGenOnly = 1;
20715let opNewValue = 2;
20716}
20717def S2_pstorerinewfnew_pi : HInst<
20718(outs IntRegs:$Rx32),
20719(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20720"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20721tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20722let Inst{2-2} = 0b1;
20723let Inst{7-7} = 0b1;
20724let Inst{13-11} = 0b110;
20725let Inst{31-21} = 0b10101011101;
20726let isPredicated = 1;
20727let isPredicatedFalse = 1;
20728let addrMode = PostInc;
20729let accessSize = WordAccess;
20730let isNVStore = 1;
20731let isPredicatedNew = 1;
20732let isNewValue = 1;
20733let isRestrictNoSlot1Store = 1;
20734let mayStore = 1;
20735let BaseOpcode = "S2_storeri_pi";
20736let CextOpcode = "S2_storeri";
20737let opNewValue = 4;
20738let Constraints = "$Rx32 = $Rx32in";
20739}
20740def S2_pstorerinewt_io : HInst<
20741(outs),
20742(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20743"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20744tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20745let Inst{2-2} = 0b0;
20746let Inst{12-11} = 0b10;
20747let Inst{31-21} = 0b01000000101;
20748let isPredicated = 1;
20749let addrMode = BaseImmOffset;
20750let accessSize = WordAccess;
20751let isNVStore = 1;
20752let isNewValue = 1;
20753let isRestrictNoSlot1Store = 1;
20754let mayStore = 1;
20755let BaseOpcode = "S2_storeri_io";
20756let CextOpcode = "S2_storeri";
20757let InputType = "imm";
20758let isExtendable = 1;
20759let opExtendable = 2;
20760let isExtentSigned = 0;
20761let opExtentBits = 8;
20762let opExtentAlign = 2;
20763let opNewValue = 3;
20764}
20765def S2_pstorerinewt_pi : HInst<
20766(outs IntRegs:$Rx32),
20767(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20768"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20769tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20770let Inst{2-2} = 0b0;
20771let Inst{7-7} = 0b0;
20772let Inst{13-11} = 0b110;
20773let Inst{31-21} = 0b10101011101;
20774let isPredicated = 1;
20775let addrMode = PostInc;
20776let accessSize = WordAccess;
20777let isNVStore = 1;
20778let isNewValue = 1;
20779let isRestrictNoSlot1Store = 1;
20780let mayStore = 1;
20781let BaseOpcode = "S2_storeri_pi";
20782let CextOpcode = "S2_storeri";
20783let opNewValue = 4;
20784let Constraints = "$Rx32 = $Rx32in";
20785}
20786def S2_pstorerinewt_zomap : HInst<
20787(outs),
20788(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20789"if ($Pv4) memw($Rs32) = $Nt8.new",
20790tc_011e0e9d, TypeMAPPING> {
20791let isPseudo = 1;
20792let isCodeGenOnly = 1;
20793let opNewValue = 2;
20794}
20795def S2_pstorerinewtnew_pi : HInst<
20796(outs IntRegs:$Rx32),
20797(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20798"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20799tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20800let Inst{2-2} = 0b0;
20801let Inst{7-7} = 0b1;
20802let Inst{13-11} = 0b110;
20803let Inst{31-21} = 0b10101011101;
20804let isPredicated = 1;
20805let addrMode = PostInc;
20806let accessSize = WordAccess;
20807let isNVStore = 1;
20808let isPredicatedNew = 1;
20809let isNewValue = 1;
20810let isRestrictNoSlot1Store = 1;
20811let mayStore = 1;
20812let BaseOpcode = "S2_storeri_pi";
20813let CextOpcode = "S2_storeri";
20814let opNewValue = 4;
20815let Constraints = "$Rx32 = $Rx32in";
20816}
20817def S2_pstorerit_io : HInst<
20818(outs),
20819(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20820"if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
20821tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20822let Inst{2-2} = 0b0;
20823let Inst{31-21} = 0b01000000100;
20824let isPredicated = 1;
20825let addrMode = BaseImmOffset;
20826let accessSize = WordAccess;
20827let mayStore = 1;
20828let BaseOpcode = "S2_storeri_io";
20829let CextOpcode = "S2_storeri";
20830let InputType = "imm";
20831let isNVStorable = 1;
20832let isExtendable = 1;
20833let opExtendable = 2;
20834let isExtentSigned = 0;
20835let opExtentBits = 8;
20836let opExtentAlign = 2;
20837}
20838def S2_pstorerit_pi : HInst<
20839(outs IntRegs:$Rx32),
20840(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20841"if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
20842tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20843let Inst{2-2} = 0b0;
20844let Inst{7-7} = 0b0;
20845let Inst{13-13} = 0b1;
20846let Inst{31-21} = 0b10101011100;
20847let isPredicated = 1;
20848let addrMode = PostInc;
20849let accessSize = WordAccess;
20850let mayStore = 1;
20851let BaseOpcode = "S2_storeri_pi";
20852let isNVStorable = 1;
20853let Constraints = "$Rx32 = $Rx32in";
20854}
20855def S2_pstorerit_zomap : HInst<
20856(outs),
20857(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20858"if ($Pv4) memw($Rs32) = $Rt32",
20859tc_8035e91f, TypeMAPPING> {
20860let isPseudo = 1;
20861let isCodeGenOnly = 1;
20862}
20863def S2_pstoreritnew_pi : HInst<
20864(outs IntRegs:$Rx32),
20865(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20866"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20867tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20868let Inst{2-2} = 0b0;
20869let Inst{7-7} = 0b1;
20870let Inst{13-13} = 0b1;
20871let Inst{31-21} = 0b10101011100;
20872let isPredicated = 1;
20873let addrMode = PostInc;
20874let accessSize = WordAccess;
20875let isPredicatedNew = 1;
20876let mayStore = 1;
20877let BaseOpcode = "S2_storeri_pi";
20878let isNVStorable = 1;
20879let Constraints = "$Rx32 = $Rx32in";
20880}
20881def S2_setbit_i : HInst<
20882(outs IntRegs:$Rd32),
20883(ins IntRegs:$Rs32, u5_0Imm:$Ii),
20884"$Rd32 = setbit($Rs32,#$Ii)",
20885tc_5da50c4b, TypeS_2op>, Enc_a05677 {
20886let Inst{7-5} = 0b000;
20887let Inst{13-13} = 0b0;
20888let Inst{31-21} = 0b10001100110;
20889let hasNewValue = 1;
20890let opNewValue = 0;
20891}
20892def S2_setbit_r : HInst<
20893(outs IntRegs:$Rd32),
20894(ins IntRegs:$Rs32, IntRegs:$Rt32),
20895"$Rd32 = setbit($Rs32,$Rt32)",
20896tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
20897let Inst{7-5} = 0b000;
20898let Inst{13-13} = 0b0;
20899let Inst{31-21} = 0b11000110100;
20900let hasNewValue = 1;
20901let opNewValue = 0;
20902}
20903def S2_shuffeb : HInst<
20904(outs DoubleRegs:$Rdd32),
20905(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20906"$Rdd32 = shuffeb($Rss32,$Rtt32)",
20907tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20908let Inst{7-5} = 0b010;
20909let Inst{13-13} = 0b0;
20910let Inst{31-21} = 0b11000001000;
20911}
20912def S2_shuffeh : HInst<
20913(outs DoubleRegs:$Rdd32),
20914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20915"$Rdd32 = shuffeh($Rss32,$Rtt32)",
20916tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20917let Inst{7-5} = 0b110;
20918let Inst{13-13} = 0b0;
20919let Inst{31-21} = 0b11000001000;
20920}
20921def S2_shuffob : HInst<
20922(outs DoubleRegs:$Rdd32),
20923(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20924"$Rdd32 = shuffob($Rtt32,$Rss32)",
20925tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20926let Inst{7-5} = 0b100;
20927let Inst{13-13} = 0b0;
20928let Inst{31-21} = 0b11000001000;
20929}
20930def S2_shuffoh : HInst<
20931(outs DoubleRegs:$Rdd32),
20932(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20933"$Rdd32 = shuffoh($Rtt32,$Rss32)",
20934tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20935let Inst{7-5} = 0b000;
20936let Inst{13-13} = 0b0;
20937let Inst{31-21} = 0b11000001100;
20938}
20939def S2_storerb_io : HInst<
20940(outs),
20941(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
20942"memb($Rs32+#$Ii) = $Rt32",
20943tc_ae5babd7, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
20944let Inst{24-21} = 0b1000;
20945let Inst{31-27} = 0b10100;
20946let addrMode = BaseImmOffset;
20947let accessSize = ByteAccess;
20948let mayStore = 1;
20949let BaseOpcode = "S2_storerb_io";
20950let CextOpcode = "S2_storerb";
20951let InputType = "imm";
20952let isNVStorable = 1;
20953let isPredicable = 1;
20954let isExtendable = 1;
20955let opExtendable = 1;
20956let isExtentSigned = 1;
20957let opExtentBits = 11;
20958let opExtentAlign = 0;
20959}
20960def S2_storerb_pbr : HInst<
20961(outs IntRegs:$Rx32),
20962(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20963"memb($Rx32++$Mu2:brev) = $Rt32",
20964tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20965let Inst{7-0} = 0b00000000;
20966let Inst{31-21} = 0b10101111000;
20967let addrMode = PostInc;
20968let accessSize = ByteAccess;
20969let mayStore = 1;
20970let BaseOpcode = "S2_storerb_pbr";
20971let isNVStorable = 1;
20972let Constraints = "$Rx32 = $Rx32in";
20973}
20974def S2_storerb_pci : HInst<
20975(outs IntRegs:$Rx32),
20976(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20977"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20978tc_b4dc7630, TypeST>, Enc_b15941, AddrModeRel {
20979let Inst{2-0} = 0b000;
20980let Inst{7-7} = 0b0;
20981let Inst{31-21} = 0b10101001000;
20982let addrMode = PostInc;
20983let accessSize = ByteAccess;
20984let mayStore = 1;
20985let Uses = [CS];
20986let BaseOpcode = "S2_storerb_pci";
20987let isNVStorable = 1;
20988let Constraints = "$Rx32 = $Rx32in";
20989}
20990def S2_storerb_pcr : HInst<
20991(outs IntRegs:$Rx32),
20992(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20993"memb($Rx32++I:circ($Mu2)) = $Rt32",
20994tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20995let Inst{7-0} = 0b00000010;
20996let Inst{31-21} = 0b10101001000;
20997let addrMode = PostInc;
20998let accessSize = ByteAccess;
20999let mayStore = 1;
21000let Uses = [CS];
21001let BaseOpcode = "S2_storerb_pcr";
21002let isNVStorable = 1;
21003let Constraints = "$Rx32 = $Rx32in";
21004}
21005def S2_storerb_pi : HInst<
21006(outs IntRegs:$Rx32),
21007(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
21008"memb($Rx32++#$Ii) = $Rt32",
21009tc_a2b365d2, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
21010let Inst{2-0} = 0b000;
21011let Inst{7-7} = 0b0;
21012let Inst{13-13} = 0b0;
21013let Inst{31-21} = 0b10101011000;
21014let addrMode = PostInc;
21015let accessSize = ByteAccess;
21016let mayStore = 1;
21017let BaseOpcode = "S2_storerb_pi";
21018let CextOpcode = "S2_storerb";
21019let isNVStorable = 1;
21020let isPredicable = 1;
21021let Constraints = "$Rx32 = $Rx32in";
21022}
21023def S2_storerb_pr : HInst<
21024(outs IntRegs:$Rx32),
21025(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21026"memb($Rx32++$Mu2) = $Rt32",
21027tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21028let Inst{7-0} = 0b00000000;
21029let Inst{31-21} = 0b10101101000;
21030let addrMode = PostInc;
21031let accessSize = ByteAccess;
21032let mayStore = 1;
21033let BaseOpcode = "S2_storerb_pr";
21034let isNVStorable = 1;
21035let Constraints = "$Rx32 = $Rx32in";
21036}
21037def S2_storerb_zomap : HInst<
21038(outs),
21039(ins IntRegs:$Rs32, IntRegs:$Rt32),
21040"memb($Rs32) = $Rt32",
21041tc_ae5babd7, TypeMAPPING> {
21042let isPseudo = 1;
21043let isCodeGenOnly = 1;
21044}
21045def S2_storerbgp : HInst<
21046(outs),
21047(ins u32_0Imm:$Ii, IntRegs:$Rt32),
21048"memb(gp+#$Ii) = $Rt32",
21049tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
21050let Inst{24-21} = 0b0000;
21051let Inst{31-27} = 0b01001;
21052let accessSize = ByteAccess;
21053let mayStore = 1;
21054let Uses = [GP];
21055let BaseOpcode = "S2_storerbabs";
21056let isNVStorable = 1;
21057let isPredicable = 1;
21058let opExtendable = 0;
21059let isExtentSigned = 0;
21060let opExtentBits = 16;
21061let opExtentAlign = 0;
21062}
21063def S2_storerbnew_io : HInst<
21064(outs),
21065(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
21066"memb($Rs32+#$Ii) = $Nt8.new",
21067tc_5deb5e47, TypeST>, Enc_4df4e9, AddrModeRel {
21068let Inst{12-11} = 0b00;
21069let Inst{24-21} = 0b1101;
21070let Inst{31-27} = 0b10100;
21071let addrMode = BaseImmOffset;
21072let accessSize = ByteAccess;
21073let isNVStore = 1;
21074let isNewValue = 1;
21075let isRestrictNoSlot1Store = 1;
21076let mayStore = 1;
21077let BaseOpcode = "S2_storerb_io";
21078let CextOpcode = "S2_storerb";
21079let InputType = "imm";
21080let isPredicable = 1;
21081let isExtendable = 1;
21082let opExtendable = 1;
21083let isExtentSigned = 1;
21084let opExtentBits = 11;
21085let opExtentAlign = 0;
21086let opNewValue = 2;
21087}
21088def S2_storerbnew_pbr : HInst<
21089(outs IntRegs:$Rx32),
21090(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21091"memb($Rx32++$Mu2:brev) = $Nt8.new",
21092tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21093let Inst{7-0} = 0b00000000;
21094let Inst{12-11} = 0b00;
21095let Inst{31-21} = 0b10101111101;
21096let addrMode = PostInc;
21097let accessSize = ByteAccess;
21098let isNVStore = 1;
21099let isNewValue = 1;
21100let isRestrictNoSlot1Store = 1;
21101let mayStore = 1;
21102let BaseOpcode = "S2_storerb_pbr";
21103let opNewValue = 3;
21104let Constraints = "$Rx32 = $Rx32in";
21105}
21106def S2_storerbnew_pci : HInst<
21107(outs IntRegs:$Rx32),
21108(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21109"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21110tc_addc37a8, TypeST>, Enc_96ce4f, AddrModeRel {
21111let Inst{2-0} = 0b000;
21112let Inst{7-7} = 0b0;
21113let Inst{12-11} = 0b00;
21114let Inst{31-21} = 0b10101001101;
21115let addrMode = PostInc;
21116let accessSize = ByteAccess;
21117let isNVStore = 1;
21118let isNewValue = 1;
21119let isRestrictNoSlot1Store = 1;
21120let mayStore = 1;
21121let Uses = [CS];
21122let BaseOpcode = "S2_storerb_pci";
21123let opNewValue = 4;
21124let Constraints = "$Rx32 = $Rx32in";
21125}
21126def S2_storerbnew_pcr : HInst<
21127(outs IntRegs:$Rx32),
21128(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21129"memb($Rx32++I:circ($Mu2)) = $Nt8.new",
21130tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21131let Inst{7-0} = 0b00000010;
21132let Inst{12-11} = 0b00;
21133let Inst{31-21} = 0b10101001101;
21134let addrMode = PostInc;
21135let accessSize = ByteAccess;
21136let isNVStore = 1;
21137let isNewValue = 1;
21138let isRestrictNoSlot1Store = 1;
21139let mayStore = 1;
21140let Uses = [CS];
21141let BaseOpcode = "S2_storerb_pcr";
21142let opNewValue = 3;
21143let Constraints = "$Rx32 = $Rx32in";
21144}
21145def S2_storerbnew_pi : HInst<
21146(outs IntRegs:$Rx32),
21147(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
21148"memb($Rx32++#$Ii) = $Nt8.new",
21149tc_92240447, TypeST>, Enc_c7cd90, AddrModeRel {
21150let Inst{2-0} = 0b000;
21151let Inst{7-7} = 0b0;
21152let Inst{13-11} = 0b000;
21153let Inst{31-21} = 0b10101011101;
21154let addrMode = PostInc;
21155let accessSize = ByteAccess;
21156let isNVStore = 1;
21157let isNewValue = 1;
21158let isRestrictNoSlot1Store = 1;
21159let mayStore = 1;
21160let BaseOpcode = "S2_storerb_pi";
21161let isNVStorable = 1;
21162let isPredicable = 1;
21163let opNewValue = 3;
21164let Constraints = "$Rx32 = $Rx32in";
21165}
21166def S2_storerbnew_pr : HInst<
21167(outs IntRegs:$Rx32),
21168(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21169"memb($Rx32++$Mu2) = $Nt8.new",
21170tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21171let Inst{7-0} = 0b00000000;
21172let Inst{12-11} = 0b00;
21173let Inst{31-21} = 0b10101101101;
21174let addrMode = PostInc;
21175let accessSize = ByteAccess;
21176let isNVStore = 1;
21177let isNewValue = 1;
21178let isRestrictNoSlot1Store = 1;
21179let mayStore = 1;
21180let BaseOpcode = "S2_storerb_pr";
21181let opNewValue = 3;
21182let Constraints = "$Rx32 = $Rx32in";
21183}
21184def S2_storerbnew_zomap : HInst<
21185(outs),
21186(ins IntRegs:$Rs32, IntRegs:$Nt8),
21187"memb($Rs32) = $Nt8.new",
21188tc_5deb5e47, TypeMAPPING> {
21189let isPseudo = 1;
21190let isCodeGenOnly = 1;
21191let opNewValue = 1;
21192}
21193def S2_storerbnewgp : HInst<
21194(outs),
21195(ins u32_0Imm:$Ii, IntRegs:$Nt8),
21196"memb(gp+#$Ii) = $Nt8.new",
21197tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
21198let Inst{12-11} = 0b00;
21199let Inst{24-21} = 0b0101;
21200let Inst{31-27} = 0b01001;
21201let accessSize = ByteAccess;
21202let isNVStore = 1;
21203let isNewValue = 1;
21204let isRestrictNoSlot1Store = 1;
21205let mayStore = 1;
21206let Uses = [GP];
21207let BaseOpcode = "S2_storerbabs";
21208let isPredicable = 1;
21209let opExtendable = 0;
21210let isExtentSigned = 0;
21211let opExtentBits = 16;
21212let opExtentAlign = 0;
21213let opNewValue = 1;
21214}
21215def S2_storerd_io : HInst<
21216(outs),
21217(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
21218"memd($Rs32+#$Ii) = $Rtt32",
21219tc_ae5babd7, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
21220let Inst{24-21} = 0b1110;
21221let Inst{31-27} = 0b10100;
21222let addrMode = BaseImmOffset;
21223let accessSize = DoubleWordAccess;
21224let mayStore = 1;
21225let BaseOpcode = "S2_storerd_io";
21226let CextOpcode = "S2_storerd";
21227let InputType = "imm";
21228let isPredicable = 1;
21229let isExtendable = 1;
21230let opExtendable = 1;
21231let isExtentSigned = 1;
21232let opExtentBits = 14;
21233let opExtentAlign = 3;
21234}
21235def S2_storerd_pbr : HInst<
21236(outs IntRegs:$Rx32),
21237(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21238"memd($Rx32++$Mu2:brev) = $Rtt32",
21239tc_a2b365d2, TypeST>, Enc_928ca1 {
21240let Inst{7-0} = 0b00000000;
21241let Inst{31-21} = 0b10101111110;
21242let addrMode = PostInc;
21243let accessSize = DoubleWordAccess;
21244let mayStore = 1;
21245let Constraints = "$Rx32 = $Rx32in";
21246}
21247def S2_storerd_pci : HInst<
21248(outs IntRegs:$Rx32),
21249(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21250"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
21251tc_b4dc7630, TypeST>, Enc_395cc4 {
21252let Inst{2-0} = 0b000;
21253let Inst{7-7} = 0b0;
21254let Inst{31-21} = 0b10101001110;
21255let addrMode = PostInc;
21256let accessSize = DoubleWordAccess;
21257let mayStore = 1;
21258let Uses = [CS];
21259let Constraints = "$Rx32 = $Rx32in";
21260}
21261def S2_storerd_pcr : HInst<
21262(outs IntRegs:$Rx32),
21263(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21264"memd($Rx32++I:circ($Mu2)) = $Rtt32",
21265tc_a2b365d2, TypeST>, Enc_928ca1 {
21266let Inst{7-0} = 0b00000010;
21267let Inst{31-21} = 0b10101001110;
21268let addrMode = PostInc;
21269let accessSize = DoubleWordAccess;
21270let mayStore = 1;
21271let Uses = [CS];
21272let Constraints = "$Rx32 = $Rx32in";
21273}
21274def S2_storerd_pi : HInst<
21275(outs IntRegs:$Rx32),
21276(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
21277"memd($Rx32++#$Ii) = $Rtt32",
21278tc_a2b365d2, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
21279let Inst{2-0} = 0b000;
21280let Inst{7-7} = 0b0;
21281let Inst{13-13} = 0b0;
21282let Inst{31-21} = 0b10101011110;
21283let addrMode = PostInc;
21284let accessSize = DoubleWordAccess;
21285let mayStore = 1;
21286let BaseOpcode = "S2_storerd_pi";
21287let CextOpcode = "S2_storerd";
21288let isPredicable = 1;
21289let Constraints = "$Rx32 = $Rx32in";
21290}
21291def S2_storerd_pr : HInst<
21292(outs IntRegs:$Rx32),
21293(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21294"memd($Rx32++$Mu2) = $Rtt32",
21295tc_a2b365d2, TypeST>, Enc_928ca1 {
21296let Inst{7-0} = 0b00000000;
21297let Inst{31-21} = 0b10101101110;
21298let addrMode = PostInc;
21299let accessSize = DoubleWordAccess;
21300let mayStore = 1;
21301let Constraints = "$Rx32 = $Rx32in";
21302}
21303def S2_storerd_zomap : HInst<
21304(outs),
21305(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
21306"memd($Rs32) = $Rtt32",
21307tc_ae5babd7, TypeMAPPING> {
21308let isPseudo = 1;
21309let isCodeGenOnly = 1;
21310}
21311def S2_storerdgp : HInst<
21312(outs),
21313(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
21314"memd(gp+#$Ii) = $Rtt32",
21315tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
21316let Inst{24-21} = 0b0110;
21317let Inst{31-27} = 0b01001;
21318let accessSize = DoubleWordAccess;
21319let mayStore = 1;
21320let Uses = [GP];
21321let BaseOpcode = "S2_storerdabs";
21322let isPredicable = 1;
21323let opExtendable = 0;
21324let isExtentSigned = 0;
21325let opExtentBits = 19;
21326let opExtentAlign = 3;
21327}
21328def S2_storerf_io : HInst<
21329(outs),
21330(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21331"memh($Rs32+#$Ii) = $Rt32.h",
21332tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21333let Inst{24-21} = 0b1011;
21334let Inst{31-27} = 0b10100;
21335let addrMode = BaseImmOffset;
21336let accessSize = HalfWordAccess;
21337let mayStore = 1;
21338let BaseOpcode = "S2_storerf_io";
21339let CextOpcode = "S2_storerf";
21340let InputType = "imm";
21341let isPredicable = 1;
21342let isExtendable = 1;
21343let opExtendable = 1;
21344let isExtentSigned = 1;
21345let opExtentBits = 12;
21346let opExtentAlign = 1;
21347}
21348def S2_storerf_pbr : HInst<
21349(outs IntRegs:$Rx32),
21350(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21351"memh($Rx32++$Mu2:brev) = $Rt32.h",
21352tc_a2b365d2, TypeST>, Enc_d5c73f {
21353let Inst{7-0} = 0b00000000;
21354let Inst{31-21} = 0b10101111011;
21355let addrMode = PostInc;
21356let accessSize = HalfWordAccess;
21357let mayStore = 1;
21358let Constraints = "$Rx32 = $Rx32in";
21359}
21360def S2_storerf_pci : HInst<
21361(outs IntRegs:$Rx32),
21362(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21363"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
21364tc_b4dc7630, TypeST>, Enc_935d9b {
21365let Inst{2-0} = 0b000;
21366let Inst{7-7} = 0b0;
21367let Inst{31-21} = 0b10101001011;
21368let addrMode = PostInc;
21369let accessSize = HalfWordAccess;
21370let mayStore = 1;
21371let Uses = [CS];
21372let Constraints = "$Rx32 = $Rx32in";
21373}
21374def S2_storerf_pcr : HInst<
21375(outs IntRegs:$Rx32),
21376(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21377"memh($Rx32++I:circ($Mu2)) = $Rt32.h",
21378tc_a2b365d2, TypeST>, Enc_d5c73f {
21379let Inst{7-0} = 0b00000010;
21380let Inst{31-21} = 0b10101001011;
21381let addrMode = PostInc;
21382let accessSize = HalfWordAccess;
21383let mayStore = 1;
21384let Uses = [CS];
21385let Constraints = "$Rx32 = $Rx32in";
21386}
21387def S2_storerf_pi : HInst<
21388(outs IntRegs:$Rx32),
21389(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21390"memh($Rx32++#$Ii) = $Rt32.h",
21391tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21392let Inst{2-0} = 0b000;
21393let Inst{7-7} = 0b0;
21394let Inst{13-13} = 0b0;
21395let Inst{31-21} = 0b10101011011;
21396let addrMode = PostInc;
21397let accessSize = HalfWordAccess;
21398let mayStore = 1;
21399let BaseOpcode = "S2_storerf_pi";
21400let CextOpcode = "S2_storerf";
21401let isPredicable = 1;
21402let Constraints = "$Rx32 = $Rx32in";
21403}
21404def S2_storerf_pr : HInst<
21405(outs IntRegs:$Rx32),
21406(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21407"memh($Rx32++$Mu2) = $Rt32.h",
21408tc_a2b365d2, TypeST>, Enc_d5c73f {
21409let Inst{7-0} = 0b00000000;
21410let Inst{31-21} = 0b10101101011;
21411let addrMode = PostInc;
21412let accessSize = HalfWordAccess;
21413let mayStore = 1;
21414let Constraints = "$Rx32 = $Rx32in";
21415}
21416def S2_storerf_zomap : HInst<
21417(outs),
21418(ins IntRegs:$Rs32, IntRegs:$Rt32),
21419"memh($Rs32) = $Rt32.h",
21420tc_ae5babd7, TypeMAPPING> {
21421let isPseudo = 1;
21422let isCodeGenOnly = 1;
21423}
21424def S2_storerfgp : HInst<
21425(outs),
21426(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21427"memh(gp+#$Ii) = $Rt32.h",
21428tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21429let Inst{24-21} = 0b0011;
21430let Inst{31-27} = 0b01001;
21431let accessSize = HalfWordAccess;
21432let mayStore = 1;
21433let Uses = [GP];
21434let BaseOpcode = "S2_storerfabs";
21435let isPredicable = 1;
21436let opExtendable = 0;
21437let isExtentSigned = 0;
21438let opExtentBits = 17;
21439let opExtentAlign = 1;
21440}
21441def S2_storerh_io : HInst<
21442(outs),
21443(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21444"memh($Rs32+#$Ii) = $Rt32",
21445tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21446let Inst{24-21} = 0b1010;
21447let Inst{31-27} = 0b10100;
21448let addrMode = BaseImmOffset;
21449let accessSize = HalfWordAccess;
21450let mayStore = 1;
21451let BaseOpcode = "S2_storerh_io";
21452let CextOpcode = "S2_storerh";
21453let InputType = "imm";
21454let isNVStorable = 1;
21455let isPredicable = 1;
21456let isExtendable = 1;
21457let opExtendable = 1;
21458let isExtentSigned = 1;
21459let opExtentBits = 12;
21460let opExtentAlign = 1;
21461}
21462def S2_storerh_pbr : HInst<
21463(outs IntRegs:$Rx32),
21464(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21465"memh($Rx32++$Mu2:brev) = $Rt32",
21466tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21467let Inst{7-0} = 0b00000000;
21468let Inst{31-21} = 0b10101111010;
21469let addrMode = PostInc;
21470let accessSize = HalfWordAccess;
21471let mayStore = 1;
21472let BaseOpcode = "S2_storerh_pbr";
21473let isNVStorable = 1;
21474let Constraints = "$Rx32 = $Rx32in";
21475}
21476def S2_storerh_pci : HInst<
21477(outs IntRegs:$Rx32),
21478(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21479"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21480tc_b4dc7630, TypeST>, Enc_935d9b, AddrModeRel {
21481let Inst{2-0} = 0b000;
21482let Inst{7-7} = 0b0;
21483let Inst{31-21} = 0b10101001010;
21484let addrMode = PostInc;
21485let accessSize = HalfWordAccess;
21486let mayStore = 1;
21487let Uses = [CS];
21488let BaseOpcode = "S2_storerh_pci";
21489let isNVStorable = 1;
21490let Constraints = "$Rx32 = $Rx32in";
21491}
21492def S2_storerh_pcr : HInst<
21493(outs IntRegs:$Rx32),
21494(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21495"memh($Rx32++I:circ($Mu2)) = $Rt32",
21496tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21497let Inst{7-0} = 0b00000010;
21498let Inst{31-21} = 0b10101001010;
21499let addrMode = PostInc;
21500let accessSize = HalfWordAccess;
21501let mayStore = 1;
21502let Uses = [CS];
21503let BaseOpcode = "S2_storerh_pcr";
21504let isNVStorable = 1;
21505let Constraints = "$Rx32 = $Rx32in";
21506}
21507def S2_storerh_pi : HInst<
21508(outs IntRegs:$Rx32),
21509(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21510"memh($Rx32++#$Ii) = $Rt32",
21511tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21512let Inst{2-0} = 0b000;
21513let Inst{7-7} = 0b0;
21514let Inst{13-13} = 0b0;
21515let Inst{31-21} = 0b10101011010;
21516let addrMode = PostInc;
21517let accessSize = HalfWordAccess;
21518let mayStore = 1;
21519let BaseOpcode = "S2_storerh_pi";
21520let CextOpcode = "S2_storerh";
21521let isNVStorable = 1;
21522let isPredicable = 1;
21523let Constraints = "$Rx32 = $Rx32in";
21524}
21525def S2_storerh_pr : HInst<
21526(outs IntRegs:$Rx32),
21527(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21528"memh($Rx32++$Mu2) = $Rt32",
21529tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21530let Inst{7-0} = 0b00000000;
21531let Inst{31-21} = 0b10101101010;
21532let addrMode = PostInc;
21533let accessSize = HalfWordAccess;
21534let mayStore = 1;
21535let BaseOpcode = "S2_storerh_pr";
21536let isNVStorable = 1;
21537let Constraints = "$Rx32 = $Rx32in";
21538}
21539def S2_storerh_zomap : HInst<
21540(outs),
21541(ins IntRegs:$Rs32, IntRegs:$Rt32),
21542"memh($Rs32) = $Rt32",
21543tc_ae5babd7, TypeMAPPING> {
21544let isPseudo = 1;
21545let isCodeGenOnly = 1;
21546}
21547def S2_storerhgp : HInst<
21548(outs),
21549(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21550"memh(gp+#$Ii) = $Rt32",
21551tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21552let Inst{24-21} = 0b0010;
21553let Inst{31-27} = 0b01001;
21554let accessSize = HalfWordAccess;
21555let mayStore = 1;
21556let Uses = [GP];
21557let BaseOpcode = "S2_storerhabs";
21558let isNVStorable = 1;
21559let isPredicable = 1;
21560let opExtendable = 0;
21561let isExtentSigned = 0;
21562let opExtentBits = 17;
21563let opExtentAlign = 1;
21564}
21565def S2_storerhnew_io : HInst<
21566(outs),
21567(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
21568"memh($Rs32+#$Ii) = $Nt8.new",
21569tc_5deb5e47, TypeST>, Enc_0d8870, AddrModeRel {
21570let Inst{12-11} = 0b01;
21571let Inst{24-21} = 0b1101;
21572let Inst{31-27} = 0b10100;
21573let addrMode = BaseImmOffset;
21574let accessSize = HalfWordAccess;
21575let isNVStore = 1;
21576let isNewValue = 1;
21577let isRestrictNoSlot1Store = 1;
21578let mayStore = 1;
21579let BaseOpcode = "S2_storerh_io";
21580let CextOpcode = "S2_storerh";
21581let InputType = "imm";
21582let isPredicable = 1;
21583let isExtendable = 1;
21584let opExtendable = 1;
21585let isExtentSigned = 1;
21586let opExtentBits = 12;
21587let opExtentAlign = 1;
21588let opNewValue = 2;
21589}
21590def S2_storerhnew_pbr : HInst<
21591(outs IntRegs:$Rx32),
21592(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21593"memh($Rx32++$Mu2:brev) = $Nt8.new",
21594tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21595let Inst{7-0} = 0b00000000;
21596let Inst{12-11} = 0b01;
21597let Inst{31-21} = 0b10101111101;
21598let addrMode = PostInc;
21599let accessSize = HalfWordAccess;
21600let isNVStore = 1;
21601let isNewValue = 1;
21602let isRestrictNoSlot1Store = 1;
21603let mayStore = 1;
21604let BaseOpcode = "S2_storerh_pbr";
21605let opNewValue = 3;
21606let Constraints = "$Rx32 = $Rx32in";
21607}
21608def S2_storerhnew_pci : HInst<
21609(outs IntRegs:$Rx32),
21610(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21611"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21612tc_addc37a8, TypeST>, Enc_91b9fe, AddrModeRel {
21613let Inst{2-0} = 0b000;
21614let Inst{7-7} = 0b0;
21615let Inst{12-11} = 0b01;
21616let Inst{31-21} = 0b10101001101;
21617let addrMode = PostInc;
21618let accessSize = HalfWordAccess;
21619let isNVStore = 1;
21620let isNewValue = 1;
21621let isRestrictNoSlot1Store = 1;
21622let mayStore = 1;
21623let Uses = [CS];
21624let BaseOpcode = "S2_storerh_pci";
21625let opNewValue = 4;
21626let Constraints = "$Rx32 = $Rx32in";
21627}
21628def S2_storerhnew_pcr : HInst<
21629(outs IntRegs:$Rx32),
21630(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21631"memh($Rx32++I:circ($Mu2)) = $Nt8.new",
21632tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21633let Inst{7-0} = 0b00000010;
21634let Inst{12-11} = 0b01;
21635let Inst{31-21} = 0b10101001101;
21636let addrMode = PostInc;
21637let accessSize = HalfWordAccess;
21638let isNVStore = 1;
21639let isNewValue = 1;
21640let isRestrictNoSlot1Store = 1;
21641let mayStore = 1;
21642let Uses = [CS];
21643let BaseOpcode = "S2_storerh_pcr";
21644let opNewValue = 3;
21645let Constraints = "$Rx32 = $Rx32in";
21646}
21647def S2_storerhnew_pi : HInst<
21648(outs IntRegs:$Rx32),
21649(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
21650"memh($Rx32++#$Ii) = $Nt8.new",
21651tc_92240447, TypeST>, Enc_e26546, AddrModeRel {
21652let Inst{2-0} = 0b000;
21653let Inst{7-7} = 0b0;
21654let Inst{13-11} = 0b001;
21655let Inst{31-21} = 0b10101011101;
21656let addrMode = PostInc;
21657let accessSize = HalfWordAccess;
21658let isNVStore = 1;
21659let isNewValue = 1;
21660let isRestrictNoSlot1Store = 1;
21661let mayStore = 1;
21662let BaseOpcode = "S2_storerh_pi";
21663let isNVStorable = 1;
21664let isPredicable = 1;
21665let opNewValue = 3;
21666let Constraints = "$Rx32 = $Rx32in";
21667}
21668def S2_storerhnew_pr : HInst<
21669(outs IntRegs:$Rx32),
21670(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21671"memh($Rx32++$Mu2) = $Nt8.new",
21672tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21673let Inst{7-0} = 0b00000000;
21674let Inst{12-11} = 0b01;
21675let Inst{31-21} = 0b10101101101;
21676let addrMode = PostInc;
21677let accessSize = HalfWordAccess;
21678let isNVStore = 1;
21679let isNewValue = 1;
21680let isRestrictNoSlot1Store = 1;
21681let mayStore = 1;
21682let BaseOpcode = "S2_storerh_pr";
21683let opNewValue = 3;
21684let Constraints = "$Rx32 = $Rx32in";
21685}
21686def S2_storerhnew_zomap : HInst<
21687(outs),
21688(ins IntRegs:$Rs32, IntRegs:$Nt8),
21689"memh($Rs32) = $Nt8.new",
21690tc_5deb5e47, TypeMAPPING> {
21691let isPseudo = 1;
21692let isCodeGenOnly = 1;
21693let opNewValue = 1;
21694}
21695def S2_storerhnewgp : HInst<
21696(outs),
21697(ins u31_1Imm:$Ii, IntRegs:$Nt8),
21698"memh(gp+#$Ii) = $Nt8.new",
21699tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
21700let Inst{12-11} = 0b01;
21701let Inst{24-21} = 0b0101;
21702let Inst{31-27} = 0b01001;
21703let accessSize = HalfWordAccess;
21704let isNVStore = 1;
21705let isNewValue = 1;
21706let isRestrictNoSlot1Store = 1;
21707let mayStore = 1;
21708let Uses = [GP];
21709let BaseOpcode = "S2_storerhabs";
21710let isPredicable = 1;
21711let opExtendable = 0;
21712let isExtentSigned = 0;
21713let opExtentBits = 17;
21714let opExtentAlign = 1;
21715let opNewValue = 1;
21716}
21717def S2_storeri_io : HInst<
21718(outs),
21719(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
21720"memw($Rs32+#$Ii) = $Rt32",
21721tc_ae5babd7, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
21722let Inst{24-21} = 0b1100;
21723let Inst{31-27} = 0b10100;
21724let addrMode = BaseImmOffset;
21725let accessSize = WordAccess;
21726let mayStore = 1;
21727let BaseOpcode = "S2_storeri_io";
21728let CextOpcode = "S2_storeri";
21729let InputType = "imm";
21730let isNVStorable = 1;
21731let isPredicable = 1;
21732let isExtendable = 1;
21733let opExtendable = 1;
21734let isExtentSigned = 1;
21735let opExtentBits = 13;
21736let opExtentAlign = 2;
21737}
21738def S2_storeri_pbr : HInst<
21739(outs IntRegs:$Rx32),
21740(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21741"memw($Rx32++$Mu2:brev) = $Rt32",
21742tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21743let Inst{7-0} = 0b00000000;
21744let Inst{31-21} = 0b10101111100;
21745let addrMode = PostInc;
21746let accessSize = WordAccess;
21747let mayStore = 1;
21748let BaseOpcode = "S2_storeri_pbr";
21749let isNVStorable = 1;
21750let Constraints = "$Rx32 = $Rx32in";
21751}
21752def S2_storeri_pci : HInst<
21753(outs IntRegs:$Rx32),
21754(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21755"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21756tc_b4dc7630, TypeST>, Enc_79b8c8, AddrModeRel {
21757let Inst{2-0} = 0b000;
21758let Inst{7-7} = 0b0;
21759let Inst{31-21} = 0b10101001100;
21760let addrMode = PostInc;
21761let accessSize = WordAccess;
21762let mayStore = 1;
21763let Uses = [CS];
21764let BaseOpcode = "S2_storeri_pci";
21765let isNVStorable = 1;
21766let Constraints = "$Rx32 = $Rx32in";
21767}
21768def S2_storeri_pcr : HInst<
21769(outs IntRegs:$Rx32),
21770(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21771"memw($Rx32++I:circ($Mu2)) = $Rt32",
21772tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21773let Inst{7-0} = 0b00000010;
21774let Inst{31-21} = 0b10101001100;
21775let addrMode = PostInc;
21776let accessSize = WordAccess;
21777let mayStore = 1;
21778let Uses = [CS];
21779let BaseOpcode = "S2_storeri_pcr";
21780let isNVStorable = 1;
21781let Constraints = "$Rx32 = $Rx32in";
21782}
21783def S2_storeri_pi : HInst<
21784(outs IntRegs:$Rx32),
21785(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
21786"memw($Rx32++#$Ii) = $Rt32",
21787tc_a2b365d2, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
21788let Inst{2-0} = 0b000;
21789let Inst{7-7} = 0b0;
21790let Inst{13-13} = 0b0;
21791let Inst{31-21} = 0b10101011100;
21792let addrMode = PostInc;
21793let accessSize = WordAccess;
21794let mayStore = 1;
21795let BaseOpcode = "S2_storeri_pi";
21796let CextOpcode = "S2_storeri";
21797let isNVStorable = 1;
21798let isPredicable = 1;
21799let Constraints = "$Rx32 = $Rx32in";
21800}
21801def S2_storeri_pr : HInst<
21802(outs IntRegs:$Rx32),
21803(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21804"memw($Rx32++$Mu2) = $Rt32",
21805tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21806let Inst{7-0} = 0b00000000;
21807let Inst{31-21} = 0b10101101100;
21808let addrMode = PostInc;
21809let accessSize = WordAccess;
21810let mayStore = 1;
21811let BaseOpcode = "S2_storeri_pr";
21812let isNVStorable = 1;
21813let Constraints = "$Rx32 = $Rx32in";
21814}
21815def S2_storeri_zomap : HInst<
21816(outs),
21817(ins IntRegs:$Rs32, IntRegs:$Rt32),
21818"memw($Rs32) = $Rt32",
21819tc_ae5babd7, TypeMAPPING> {
21820let isPseudo = 1;
21821let isCodeGenOnly = 1;
21822}
21823def S2_storerigp : HInst<
21824(outs),
21825(ins u30_2Imm:$Ii, IntRegs:$Rt32),
21826"memw(gp+#$Ii) = $Rt32",
21827tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
21828let Inst{24-21} = 0b0100;
21829let Inst{31-27} = 0b01001;
21830let accessSize = WordAccess;
21831let mayStore = 1;
21832let Uses = [GP];
21833let BaseOpcode = "S2_storeriabs";
21834let isNVStorable = 1;
21835let isPredicable = 1;
21836let opExtendable = 0;
21837let isExtentSigned = 0;
21838let opExtentBits = 18;
21839let opExtentAlign = 2;
21840}
21841def S2_storerinew_io : HInst<
21842(outs),
21843(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
21844"memw($Rs32+#$Ii) = $Nt8.new",
21845tc_5deb5e47, TypeST>, Enc_690862, AddrModeRel {
21846let Inst{12-11} = 0b10;
21847let Inst{24-21} = 0b1101;
21848let Inst{31-27} = 0b10100;
21849let addrMode = BaseImmOffset;
21850let accessSize = WordAccess;
21851let isNVStore = 1;
21852let isNewValue = 1;
21853let isRestrictNoSlot1Store = 1;
21854let mayStore = 1;
21855let BaseOpcode = "S2_storeri_io";
21856let CextOpcode = "S2_storeri";
21857let InputType = "imm";
21858let isPredicable = 1;
21859let isExtendable = 1;
21860let opExtendable = 1;
21861let isExtentSigned = 1;
21862let opExtentBits = 13;
21863let opExtentAlign = 2;
21864let opNewValue = 2;
21865}
21866def S2_storerinew_pbr : HInst<
21867(outs IntRegs:$Rx32),
21868(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21869"memw($Rx32++$Mu2:brev) = $Nt8.new",
21870tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21871let Inst{7-0} = 0b00000000;
21872let Inst{12-11} = 0b10;
21873let Inst{31-21} = 0b10101111101;
21874let addrMode = PostInc;
21875let accessSize = WordAccess;
21876let isNVStore = 1;
21877let isNewValue = 1;
21878let isRestrictNoSlot1Store = 1;
21879let mayStore = 1;
21880let BaseOpcode = "S2_storeri_pbr";
21881let opNewValue = 3;
21882let Constraints = "$Rx32 = $Rx32in";
21883}
21884def S2_storerinew_pci : HInst<
21885(outs IntRegs:$Rx32),
21886(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21887"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21888tc_addc37a8, TypeST>, Enc_3f97c8, AddrModeRel {
21889let Inst{2-0} = 0b000;
21890let Inst{7-7} = 0b0;
21891let Inst{12-11} = 0b10;
21892let Inst{31-21} = 0b10101001101;
21893let addrMode = PostInc;
21894let accessSize = WordAccess;
21895let isNVStore = 1;
21896let isNewValue = 1;
21897let isRestrictNoSlot1Store = 1;
21898let mayStore = 1;
21899let Uses = [CS];
21900let BaseOpcode = "S2_storeri_pci";
21901let opNewValue = 4;
21902let Constraints = "$Rx32 = $Rx32in";
21903}
21904def S2_storerinew_pcr : HInst<
21905(outs IntRegs:$Rx32),
21906(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21907"memw($Rx32++I:circ($Mu2)) = $Nt8.new",
21908tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21909let Inst{7-0} = 0b00000010;
21910let Inst{12-11} = 0b10;
21911let Inst{31-21} = 0b10101001101;
21912let addrMode = PostInc;
21913let accessSize = WordAccess;
21914let isNVStore = 1;
21915let isNewValue = 1;
21916let isRestrictNoSlot1Store = 1;
21917let mayStore = 1;
21918let Uses = [CS];
21919let BaseOpcode = "S2_storeri_pcr";
21920let opNewValue = 3;
21921let Constraints = "$Rx32 = $Rx32in";
21922}
21923def S2_storerinew_pi : HInst<
21924(outs IntRegs:$Rx32),
21925(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
21926"memw($Rx32++#$Ii) = $Nt8.new",
21927tc_92240447, TypeST>, Enc_223005, AddrModeRel {
21928let Inst{2-0} = 0b000;
21929let Inst{7-7} = 0b0;
21930let Inst{13-11} = 0b010;
21931let Inst{31-21} = 0b10101011101;
21932let addrMode = PostInc;
21933let accessSize = WordAccess;
21934let isNVStore = 1;
21935let isNewValue = 1;
21936let isRestrictNoSlot1Store = 1;
21937let mayStore = 1;
21938let BaseOpcode = "S2_storeri_pi";
21939let isPredicable = 1;
21940let opNewValue = 3;
21941let Constraints = "$Rx32 = $Rx32in";
21942}
21943def S2_storerinew_pr : HInst<
21944(outs IntRegs:$Rx32),
21945(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21946"memw($Rx32++$Mu2) = $Nt8.new",
21947tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21948let Inst{7-0} = 0b00000000;
21949let Inst{12-11} = 0b10;
21950let Inst{31-21} = 0b10101101101;
21951let addrMode = PostInc;
21952let accessSize = WordAccess;
21953let isNVStore = 1;
21954let isNewValue = 1;
21955let isRestrictNoSlot1Store = 1;
21956let mayStore = 1;
21957let BaseOpcode = "S2_storeri_pr";
21958let opNewValue = 3;
21959let Constraints = "$Rx32 = $Rx32in";
21960}
21961def S2_storerinew_zomap : HInst<
21962(outs),
21963(ins IntRegs:$Rs32, IntRegs:$Nt8),
21964"memw($Rs32) = $Nt8.new",
21965tc_5deb5e47, TypeMAPPING> {
21966let isPseudo = 1;
21967let isCodeGenOnly = 1;
21968let opNewValue = 1;
21969}
21970def S2_storerinewgp : HInst<
21971(outs),
21972(ins u30_2Imm:$Ii, IntRegs:$Nt8),
21973"memw(gp+#$Ii) = $Nt8.new",
21974tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
21975let Inst{12-11} = 0b10;
21976let Inst{24-21} = 0b0101;
21977let Inst{31-27} = 0b01001;
21978let accessSize = WordAccess;
21979let isNVStore = 1;
21980let isNewValue = 1;
21981let isRestrictNoSlot1Store = 1;
21982let mayStore = 1;
21983let Uses = [GP];
21984let BaseOpcode = "S2_storeriabs";
21985let isPredicable = 1;
21986let opExtendable = 0;
21987let isExtentSigned = 0;
21988let opExtentBits = 18;
21989let opExtentAlign = 2;
21990let opNewValue = 1;
21991}
21992def S2_storew_locked : HInst<
21993(outs PredRegs:$Pd4),
21994(ins IntRegs:$Rs32, IntRegs:$Rt32),
21995"memw_locked($Rs32,$Pd4) = $Rt32",
21996tc_6f42bc60, TypeST>, Enc_c2b48e {
21997let Inst{7-2} = 0b000000;
21998let Inst{13-13} = 0b0;
21999let Inst{31-21} = 0b10100000101;
22000let accessSize = WordAccess;
22001let isPredicateLate = 1;
22002let isSoloAX = 1;
22003let mayStore = 1;
22004}
22005def S2_storew_rl_at_vi : HInst<
22006(outs),
22007(ins IntRegs:$Rs32, IntRegs:$Rt32),
22008"memw_rl($Rs32):at = $Rt32",
22009tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
22010let Inst{7-2} = 0b000010;
22011let Inst{13-13} = 0b0;
22012let Inst{31-21} = 0b10100000101;
22013let accessSize = WordAccess;
22014let isSolo = 1;
22015let mayStore = 1;
22016}
22017def S2_storew_rl_st_vi : HInst<
22018(outs),
22019(ins IntRegs:$Rs32, IntRegs:$Rt32),
22020"memw_rl($Rs32):st = $Rt32",
22021tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
22022let Inst{7-2} = 0b001010;
22023let Inst{13-13} = 0b0;
22024let Inst{31-21} = 0b10100000101;
22025let accessSize = WordAccess;
22026let isSolo = 1;
22027let mayStore = 1;
22028}
22029def S2_svsathb : HInst<
22030(outs IntRegs:$Rd32),
22031(ins IntRegs:$Rs32),
22032"$Rd32 = vsathb($Rs32)",
22033tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22034let Inst{13-5} = 0b000000000;
22035let Inst{31-21} = 0b10001100100;
22036let hasNewValue = 1;
22037let opNewValue = 0;
22038let Defs = [USR_OVF];
22039}
22040def S2_svsathub : HInst<
22041(outs IntRegs:$Rd32),
22042(ins IntRegs:$Rs32),
22043"$Rd32 = vsathub($Rs32)",
22044tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22045let Inst{13-5} = 0b000000010;
22046let Inst{31-21} = 0b10001100100;
22047let hasNewValue = 1;
22048let opNewValue = 0;
22049let Defs = [USR_OVF];
22050}
22051def S2_tableidxb : HInst<
22052(outs IntRegs:$Rx32),
22053(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22054"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
22055tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22056let Inst{31-22} = 0b1000011100;
22057let hasNewValue = 1;
22058let opNewValue = 0;
22059let prefersSlot3 = 1;
22060let Constraints = "$Rx32 = $Rx32in";
22061}
22062def S2_tableidxb_goodsyntax : HInst<
22063(outs IntRegs:$Rx32),
22064(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22065"$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
22066tc_bb831a7c, TypeS_2op> {
22067let hasNewValue = 1;
22068let opNewValue = 0;
22069let isPseudo = 1;
22070let isCodeGenOnly = 1;
22071let Constraints = "$Rx32 = $Rx32in";
22072}
22073def S2_tableidxd : HInst<
22074(outs IntRegs:$Rx32),
22075(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22076"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
22077tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22078let Inst{31-22} = 0b1000011111;
22079let hasNewValue = 1;
22080let opNewValue = 0;
22081let prefersSlot3 = 1;
22082let Constraints = "$Rx32 = $Rx32in";
22083}
22084def S2_tableidxd_goodsyntax : HInst<
22085(outs IntRegs:$Rx32),
22086(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22087"$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
22088tc_bb831a7c, TypeS_2op> {
22089let hasNewValue = 1;
22090let opNewValue = 0;
22091let isPseudo = 1;
22092let Constraints = "$Rx32 = $Rx32in";
22093}
22094def S2_tableidxh : HInst<
22095(outs IntRegs:$Rx32),
22096(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22097"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
22098tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22099let Inst{31-22} = 0b1000011101;
22100let hasNewValue = 1;
22101let opNewValue = 0;
22102let prefersSlot3 = 1;
22103let Constraints = "$Rx32 = $Rx32in";
22104}
22105def S2_tableidxh_goodsyntax : HInst<
22106(outs IntRegs:$Rx32),
22107(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22108"$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
22109tc_bb831a7c, TypeS_2op> {
22110let hasNewValue = 1;
22111let opNewValue = 0;
22112let isPseudo = 1;
22113let Constraints = "$Rx32 = $Rx32in";
22114}
22115def S2_tableidxw : HInst<
22116(outs IntRegs:$Rx32),
22117(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22118"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
22119tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22120let Inst{31-22} = 0b1000011110;
22121let hasNewValue = 1;
22122let opNewValue = 0;
22123let prefersSlot3 = 1;
22124let Constraints = "$Rx32 = $Rx32in";
22125}
22126def S2_tableidxw_goodsyntax : HInst<
22127(outs IntRegs:$Rx32),
22128(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22129"$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
22130tc_bb831a7c, TypeS_2op> {
22131let hasNewValue = 1;
22132let opNewValue = 0;
22133let isPseudo = 1;
22134let Constraints = "$Rx32 = $Rx32in";
22135}
22136def S2_togglebit_i : HInst<
22137(outs IntRegs:$Rd32),
22138(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22139"$Rd32 = togglebit($Rs32,#$Ii)",
22140tc_5da50c4b, TypeS_2op>, Enc_a05677 {
22141let Inst{7-5} = 0b010;
22142let Inst{13-13} = 0b0;
22143let Inst{31-21} = 0b10001100110;
22144let hasNewValue = 1;
22145let opNewValue = 0;
22146}
22147def S2_togglebit_r : HInst<
22148(outs IntRegs:$Rd32),
22149(ins IntRegs:$Rs32, IntRegs:$Rt32),
22150"$Rd32 = togglebit($Rs32,$Rt32)",
22151tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
22152let Inst{7-5} = 0b100;
22153let Inst{13-13} = 0b0;
22154let Inst{31-21} = 0b11000110100;
22155let hasNewValue = 1;
22156let opNewValue = 0;
22157}
22158def S2_tstbit_i : HInst<
22159(outs PredRegs:$Pd4),
22160(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22161"$Pd4 = tstbit($Rs32,#$Ii)",
22162tc_a1297125, TypeS_2op>, Enc_83ee64 {
22163let Inst{7-2} = 0b000000;
22164let Inst{13-13} = 0b0;
22165let Inst{31-21} = 0b10000101000;
22166}
22167def S2_tstbit_r : HInst<
22168(outs PredRegs:$Pd4),
22169(ins IntRegs:$Rs32, IntRegs:$Rt32),
22170"$Pd4 = tstbit($Rs32,$Rt32)",
22171tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22172let Inst{7-2} = 0b000000;
22173let Inst{13-13} = 0b0;
22174let Inst{31-21} = 0b11000111000;
22175}
22176def S2_valignib : HInst<
22177(outs DoubleRegs:$Rdd32),
22178(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
22179"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
22180tc_6fc5dbea, TypeS_3op>, Enc_729ff7 {
22181let Inst{13-13} = 0b0;
22182let Inst{31-21} = 0b11000000000;
22183}
22184def S2_valignrb : HInst<
22185(outs DoubleRegs:$Rdd32),
22186(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
22187"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
22188tc_6fc5dbea, TypeS_3op>, Enc_8c6530 {
22189let Inst{7-7} = 0b0;
22190let Inst{13-13} = 0b0;
22191let Inst{31-21} = 0b11000010000;
22192}
22193def S2_vcnegh : HInst<
22194(outs DoubleRegs:$Rdd32),
22195(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22196"$Rdd32 = vcnegh($Rss32,$Rt32)",
22197tc_8a825db2, TypeS_3op>, Enc_927852 {
22198let Inst{7-5} = 0b010;
22199let Inst{13-13} = 0b0;
22200let Inst{31-21} = 0b11000011110;
22201let prefersSlot3 = 1;
22202let Defs = [USR_OVF];
22203}
22204def S2_vcrotate : HInst<
22205(outs DoubleRegs:$Rdd32),
22206(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22207"$Rdd32 = vcrotate($Rss32,$Rt32)",
22208tc_0dfac0a7, TypeS_3op>, Enc_927852 {
22209let Inst{7-5} = 0b000;
22210let Inst{13-13} = 0b0;
22211let Inst{31-21} = 0b11000011110;
22212let prefersSlot3 = 1;
22213let Defs = [USR_OVF];
22214}
22215def S2_vrcnegh : HInst<
22216(outs DoubleRegs:$Rxx32),
22217(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
22218"$Rxx32 += vrcnegh($Rss32,$Rt32)",
22219tc_7f8ae742, TypeS_3op>, Enc_1aa186 {
22220let Inst{7-5} = 0b111;
22221let Inst{13-13} = 0b1;
22222let Inst{31-21} = 0b11001011001;
22223let prefersSlot3 = 1;
22224let Constraints = "$Rxx32 = $Rxx32in";
22225}
22226def S2_vrndpackwh : HInst<
22227(outs IntRegs:$Rd32),
22228(ins DoubleRegs:$Rss32),
22229"$Rd32 = vrndwh($Rss32)",
22230tc_e3d699e3, TypeS_2op>, Enc_90cd8b {
22231let Inst{13-5} = 0b000000100;
22232let Inst{31-21} = 0b10001000100;
22233let hasNewValue = 1;
22234let opNewValue = 0;
22235let prefersSlot3 = 1;
22236}
22237def S2_vrndpackwhs : HInst<
22238(outs IntRegs:$Rd32),
22239(ins DoubleRegs:$Rss32),
22240"$Rd32 = vrndwh($Rss32):sat",
22241tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
22242let Inst{13-5} = 0b000000110;
22243let Inst{31-21} = 0b10001000100;
22244let hasNewValue = 1;
22245let opNewValue = 0;
22246let prefersSlot3 = 1;
22247let Defs = [USR_OVF];
22248}
22249def S2_vsathb : HInst<
22250(outs IntRegs:$Rd32),
22251(ins DoubleRegs:$Rss32),
22252"$Rd32 = vsathb($Rss32)",
22253tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22254let Inst{13-5} = 0b000000110;
22255let Inst{31-21} = 0b10001000000;
22256let hasNewValue = 1;
22257let opNewValue = 0;
22258let Defs = [USR_OVF];
22259}
22260def S2_vsathb_nopack : HInst<
22261(outs DoubleRegs:$Rdd32),
22262(ins DoubleRegs:$Rss32),
22263"$Rdd32 = vsathb($Rss32)",
22264tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22265let Inst{13-5} = 0b000000111;
22266let Inst{31-21} = 0b10000000000;
22267let Defs = [USR_OVF];
22268}
22269def S2_vsathub : HInst<
22270(outs IntRegs:$Rd32),
22271(ins DoubleRegs:$Rss32),
22272"$Rd32 = vsathub($Rss32)",
22273tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22274let Inst{13-5} = 0b000000000;
22275let Inst{31-21} = 0b10001000000;
22276let hasNewValue = 1;
22277let opNewValue = 0;
22278let Defs = [USR_OVF];
22279}
22280def S2_vsathub_nopack : HInst<
22281(outs DoubleRegs:$Rdd32),
22282(ins DoubleRegs:$Rss32),
22283"$Rdd32 = vsathub($Rss32)",
22284tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22285let Inst{13-5} = 0b000000100;
22286let Inst{31-21} = 0b10000000000;
22287let Defs = [USR_OVF];
22288}
22289def S2_vsatwh : HInst<
22290(outs IntRegs:$Rd32),
22291(ins DoubleRegs:$Rss32),
22292"$Rd32 = vsatwh($Rss32)",
22293tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22294let Inst{13-5} = 0b000000010;
22295let Inst{31-21} = 0b10001000000;
22296let hasNewValue = 1;
22297let opNewValue = 0;
22298let Defs = [USR_OVF];
22299}
22300def S2_vsatwh_nopack : HInst<
22301(outs DoubleRegs:$Rdd32),
22302(ins DoubleRegs:$Rss32),
22303"$Rdd32 = vsatwh($Rss32)",
22304tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22305let Inst{13-5} = 0b000000110;
22306let Inst{31-21} = 0b10000000000;
22307let Defs = [USR_OVF];
22308}
22309def S2_vsatwuh : HInst<
22310(outs IntRegs:$Rd32),
22311(ins DoubleRegs:$Rss32),
22312"$Rd32 = vsatwuh($Rss32)",
22313tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22314let Inst{13-5} = 0b000000100;
22315let Inst{31-21} = 0b10001000000;
22316let hasNewValue = 1;
22317let opNewValue = 0;
22318let Defs = [USR_OVF];
22319}
22320def S2_vsatwuh_nopack : HInst<
22321(outs DoubleRegs:$Rdd32),
22322(ins DoubleRegs:$Rss32),
22323"$Rdd32 = vsatwuh($Rss32)",
22324tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22325let Inst{13-5} = 0b000000101;
22326let Inst{31-21} = 0b10000000000;
22327let Defs = [USR_OVF];
22328}
22329def S2_vsplatrb : HInst<
22330(outs IntRegs:$Rd32),
22331(ins IntRegs:$Rs32),
22332"$Rd32 = vsplatb($Rs32)",
22333tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22334let Inst{13-5} = 0b000000111;
22335let Inst{31-21} = 0b10001100010;
22336let hasNewValue = 1;
22337let opNewValue = 0;
22338let isAsCheapAsAMove = 1;
22339let isReMaterializable = 1;
22340}
22341def S2_vsplatrh : HInst<
22342(outs DoubleRegs:$Rdd32),
22343(ins IntRegs:$Rs32),
22344"$Rdd32 = vsplath($Rs32)",
22345tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22346let Inst{13-5} = 0b000000010;
22347let Inst{31-21} = 0b10000100010;
22348let isAsCheapAsAMove = 1;
22349let isReMaterializable = 1;
22350}
22351def S2_vspliceib : HInst<
22352(outs DoubleRegs:$Rdd32),
22353(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
22354"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
22355tc_6fc5dbea, TypeS_3op>, Enc_d50cd3 {
22356let Inst{13-13} = 0b0;
22357let Inst{31-21} = 0b11000000100;
22358}
22359def S2_vsplicerb : HInst<
22360(outs DoubleRegs:$Rdd32),
22361(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
22362"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
22363tc_6fc5dbea, TypeS_3op>, Enc_dbd70c {
22364let Inst{7-7} = 0b0;
22365let Inst{13-13} = 0b0;
22366let Inst{31-21} = 0b11000010100;
22367}
22368def S2_vsxtbh : HInst<
22369(outs DoubleRegs:$Rdd32),
22370(ins IntRegs:$Rs32),
22371"$Rdd32 = vsxtbh($Rs32)",
22372tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22373let Inst{13-5} = 0b000000000;
22374let Inst{31-21} = 0b10000100000;
22375let isAsCheapAsAMove = 1;
22376let isReMaterializable = 1;
22377}
22378def S2_vsxthw : HInst<
22379(outs DoubleRegs:$Rdd32),
22380(ins IntRegs:$Rs32),
22381"$Rdd32 = vsxthw($Rs32)",
22382tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22383let Inst{13-5} = 0b000000100;
22384let Inst{31-21} = 0b10000100000;
22385let isAsCheapAsAMove = 1;
22386let isReMaterializable = 1;
22387}
22388def S2_vtrunehb : HInst<
22389(outs IntRegs:$Rd32),
22390(ins DoubleRegs:$Rss32),
22391"$Rd32 = vtrunehb($Rss32)",
22392tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22393let Inst{13-5} = 0b000000010;
22394let Inst{31-21} = 0b10001000100;
22395let hasNewValue = 1;
22396let opNewValue = 0;
22397}
22398def S2_vtrunewh : HInst<
22399(outs DoubleRegs:$Rdd32),
22400(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22401"$Rdd32 = vtrunewh($Rss32,$Rtt32)",
22402tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22403let Inst{7-5} = 0b010;
22404let Inst{13-13} = 0b0;
22405let Inst{31-21} = 0b11000001100;
22406}
22407def S2_vtrunohb : HInst<
22408(outs IntRegs:$Rd32),
22409(ins DoubleRegs:$Rss32),
22410"$Rd32 = vtrunohb($Rss32)",
22411tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22412let Inst{13-5} = 0b000000000;
22413let Inst{31-21} = 0b10001000100;
22414let hasNewValue = 1;
22415let opNewValue = 0;
22416}
22417def S2_vtrunowh : HInst<
22418(outs DoubleRegs:$Rdd32),
22419(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22420"$Rdd32 = vtrunowh($Rss32,$Rtt32)",
22421tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22422let Inst{7-5} = 0b100;
22423let Inst{13-13} = 0b0;
22424let Inst{31-21} = 0b11000001100;
22425}
22426def S2_vzxtbh : HInst<
22427(outs DoubleRegs:$Rdd32),
22428(ins IntRegs:$Rs32),
22429"$Rdd32 = vzxtbh($Rs32)",
22430tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22431let Inst{13-5} = 0b000000010;
22432let Inst{31-21} = 0b10000100000;
22433let isAsCheapAsAMove = 1;
22434let isReMaterializable = 1;
22435}
22436def S2_vzxthw : HInst<
22437(outs DoubleRegs:$Rdd32),
22438(ins IntRegs:$Rs32),
22439"$Rdd32 = vzxthw($Rs32)",
22440tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22441let Inst{13-5} = 0b000000110;
22442let Inst{31-21} = 0b10000100000;
22443let isAsCheapAsAMove = 1;
22444let isReMaterializable = 1;
22445}
22446def S4_addaddi : HInst<
22447(outs IntRegs:$Rd32),
22448(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
22449"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
22450tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
22451let Inst{31-23} = 0b110110110;
22452let hasNewValue = 1;
22453let opNewValue = 0;
22454let prefersSlot3 = 1;
22455let isExtendable = 1;
22456let opExtendable = 3;
22457let isExtentSigned = 1;
22458let opExtentBits = 6;
22459let opExtentAlign = 0;
22460}
22461def S4_addi_asl_ri : HInst<
22462(outs IntRegs:$Rx32),
22463(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22464"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
22465tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22466let Inst{2-0} = 0b100;
22467let Inst{4-4} = 0b0;
22468let Inst{31-24} = 0b11011110;
22469let hasNewValue = 1;
22470let opNewValue = 0;
22471let prefersSlot3 = 1;
22472let isExtendable = 1;
22473let opExtendable = 1;
22474let isExtentSigned = 0;
22475let opExtentBits = 8;
22476let opExtentAlign = 0;
22477let Constraints = "$Rx32 = $Rx32in";
22478}
22479def S4_addi_lsr_ri : HInst<
22480(outs IntRegs:$Rx32),
22481(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22482"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
22483tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22484let Inst{2-0} = 0b100;
22485let Inst{4-4} = 0b1;
22486let Inst{31-24} = 0b11011110;
22487let hasNewValue = 1;
22488let opNewValue = 0;
22489let prefersSlot3 = 1;
22490let isExtendable = 1;
22491let opExtendable = 1;
22492let isExtentSigned = 0;
22493let opExtentBits = 8;
22494let opExtentAlign = 0;
22495let Constraints = "$Rx32 = $Rx32in";
22496}
22497def S4_andi_asl_ri : HInst<
22498(outs IntRegs:$Rx32),
22499(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22500"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
22501tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22502let Inst{2-0} = 0b000;
22503let Inst{4-4} = 0b0;
22504let Inst{31-24} = 0b11011110;
22505let hasNewValue = 1;
22506let opNewValue = 0;
22507let prefersSlot3 = 1;
22508let isExtendable = 1;
22509let opExtendable = 1;
22510let isExtentSigned = 0;
22511let opExtentBits = 8;
22512let opExtentAlign = 0;
22513let Constraints = "$Rx32 = $Rx32in";
22514}
22515def S4_andi_lsr_ri : HInst<
22516(outs IntRegs:$Rx32),
22517(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22518"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
22519tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22520let Inst{2-0} = 0b000;
22521let Inst{4-4} = 0b1;
22522let Inst{31-24} = 0b11011110;
22523let hasNewValue = 1;
22524let opNewValue = 0;
22525let prefersSlot3 = 1;
22526let isExtendable = 1;
22527let opExtendable = 1;
22528let isExtentSigned = 0;
22529let opExtentBits = 8;
22530let opExtentAlign = 0;
22531let Constraints = "$Rx32 = $Rx32in";
22532}
22533def S4_clbaddi : HInst<
22534(outs IntRegs:$Rd32),
22535(ins IntRegs:$Rs32, s6_0Imm:$Ii),
22536"$Rd32 = add(clb($Rs32),#$Ii)",
22537tc_a08b630b, TypeS_2op>, Enc_9fae8a {
22538let Inst{7-5} = 0b000;
22539let Inst{31-21} = 0b10001100001;
22540let hasNewValue = 1;
22541let opNewValue = 0;
22542let prefersSlot3 = 1;
22543}
22544def S4_clbpaddi : HInst<
22545(outs IntRegs:$Rd32),
22546(ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
22547"$Rd32 = add(clb($Rss32),#$Ii)",
22548tc_a08b630b, TypeS_2op>, Enc_a1640c {
22549let Inst{7-5} = 0b010;
22550let Inst{31-21} = 0b10001000011;
22551let hasNewValue = 1;
22552let opNewValue = 0;
22553let prefersSlot3 = 1;
22554}
22555def S4_clbpnorm : HInst<
22556(outs IntRegs:$Rd32),
22557(ins DoubleRegs:$Rss32),
22558"$Rd32 = normamt($Rss32)",
22559tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
22560let Inst{13-5} = 0b000000000;
22561let Inst{31-21} = 0b10001000011;
22562let hasNewValue = 1;
22563let opNewValue = 0;
22564let prefersSlot3 = 1;
22565}
22566def S4_extract : HInst<
22567(outs IntRegs:$Rd32),
22568(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
22569"$Rd32 = extract($Rs32,#$Ii,#$II)",
22570tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
22571let Inst{13-13} = 0b0;
22572let Inst{31-23} = 0b100011011;
22573let hasNewValue = 1;
22574let opNewValue = 0;
22575let prefersSlot3 = 1;
22576}
22577def S4_extract_rp : HInst<
22578(outs IntRegs:$Rd32),
22579(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
22580"$Rd32 = extract($Rs32,$Rtt32)",
22581tc_a08b630b, TypeS_3op>, Enc_e07374 {
22582let Inst{7-5} = 0b010;
22583let Inst{13-13} = 0b0;
22584let Inst{31-21} = 0b11001001000;
22585let hasNewValue = 1;
22586let opNewValue = 0;
22587let prefersSlot3 = 1;
22588}
22589def S4_extractp : HInst<
22590(outs DoubleRegs:$Rdd32),
22591(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
22592"$Rdd32 = extract($Rss32,#$Ii,#$II)",
22593tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
22594let Inst{31-24} = 0b10001010;
22595let prefersSlot3 = 1;
22596}
22597def S4_extractp_rp : HInst<
22598(outs DoubleRegs:$Rdd32),
22599(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22600"$Rdd32 = extract($Rss32,$Rtt32)",
22601tc_a08b630b, TypeS_3op>, Enc_a56825 {
22602let Inst{7-5} = 0b100;
22603let Inst{13-13} = 0b0;
22604let Inst{31-21} = 0b11000001110;
22605let prefersSlot3 = 1;
22606}
22607def S4_lsli : HInst<
22608(outs IntRegs:$Rd32),
22609(ins s6_0Imm:$Ii, IntRegs:$Rt32),
22610"$Rd32 = lsl(#$Ii,$Rt32)",
22611tc_5da50c4b, TypeS_3op>, Enc_fef969 {
22612let Inst{7-6} = 0b11;
22613let Inst{13-13} = 0b0;
22614let Inst{31-21} = 0b11000110100;
22615let hasNewValue = 1;
22616let opNewValue = 0;
22617}
22618def S4_ntstbit_i : HInst<
22619(outs PredRegs:$Pd4),
22620(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22621"$Pd4 = !tstbit($Rs32,#$Ii)",
22622tc_a1297125, TypeS_2op>, Enc_83ee64 {
22623let Inst{7-2} = 0b000000;
22624let Inst{13-13} = 0b0;
22625let Inst{31-21} = 0b10000101001;
22626}
22627def S4_ntstbit_r : HInst<
22628(outs PredRegs:$Pd4),
22629(ins IntRegs:$Rs32, IntRegs:$Rt32),
22630"$Pd4 = !tstbit($Rs32,$Rt32)",
22631tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22632let Inst{7-2} = 0b000000;
22633let Inst{13-13} = 0b0;
22634let Inst{31-21} = 0b11000111001;
22635}
22636def S4_or_andi : HInst<
22637(outs IntRegs:$Rx32),
22638(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22639"$Rx32 |= and($Rs32,#$Ii)",
22640tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22641let Inst{31-22} = 0b1101101000;
22642let hasNewValue = 1;
22643let opNewValue = 0;
22644let prefersSlot3 = 1;
22645let InputType = "imm";
22646let isExtendable = 1;
22647let opExtendable = 3;
22648let isExtentSigned = 1;
22649let opExtentBits = 10;
22650let opExtentAlign = 0;
22651let Constraints = "$Rx32 = $Rx32in";
22652}
22653def S4_or_andix : HInst<
22654(outs IntRegs:$Rx32),
22655(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
22656"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22657tc_a4e22bbd, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> {
22658let Inst{31-22} = 0b1101101001;
22659let hasNewValue = 1;
22660let opNewValue = 0;
22661let prefersSlot3 = 1;
22662let isExtendable = 1;
22663let opExtendable = 3;
22664let isExtentSigned = 1;
22665let opExtentBits = 10;
22666let opExtentAlign = 0;
22667let Constraints = "$Rx32 = $Rx32in";
22668}
22669def S4_or_ori : HInst<
22670(outs IntRegs:$Rx32),
22671(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22672"$Rx32 |= or($Rs32,#$Ii)",
22673tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22674let Inst{31-22} = 0b1101101010;
22675let hasNewValue = 1;
22676let opNewValue = 0;
22677let prefersSlot3 = 1;
22678let InputType = "imm";
22679let isExtendable = 1;
22680let opExtendable = 3;
22681let isExtentSigned = 1;
22682let opExtentBits = 10;
22683let opExtentAlign = 0;
22684let Constraints = "$Rx32 = $Rx32in";
22685}
22686def S4_ori_asl_ri : HInst<
22687(outs IntRegs:$Rx32),
22688(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22689"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22690tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22691let Inst{2-0} = 0b010;
22692let Inst{4-4} = 0b0;
22693let Inst{31-24} = 0b11011110;
22694let hasNewValue = 1;
22695let opNewValue = 0;
22696let prefersSlot3 = 1;
22697let isExtendable = 1;
22698let opExtendable = 1;
22699let isExtentSigned = 0;
22700let opExtentBits = 8;
22701let opExtentAlign = 0;
22702let Constraints = "$Rx32 = $Rx32in";
22703}
22704def S4_ori_lsr_ri : HInst<
22705(outs IntRegs:$Rx32),
22706(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22707"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22708tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22709let Inst{2-0} = 0b010;
22710let Inst{4-4} = 0b1;
22711let Inst{31-24} = 0b11011110;
22712let hasNewValue = 1;
22713let opNewValue = 0;
22714let prefersSlot3 = 1;
22715let isExtendable = 1;
22716let opExtendable = 1;
22717let isExtentSigned = 0;
22718let opExtentBits = 8;
22719let opExtentAlign = 0;
22720let Constraints = "$Rx32 = $Rx32in";
22721}
22722def S4_parity : HInst<
22723(outs IntRegs:$Rd32),
22724(ins IntRegs:$Rs32, IntRegs:$Rt32),
22725"$Rd32 = parity($Rs32,$Rt32)",
22726tc_a08b630b, TypeALU64>, Enc_5ab2be {
22727let Inst{7-5} = 0b000;
22728let Inst{13-13} = 0b0;
22729let Inst{31-21} = 0b11010101111;
22730let hasNewValue = 1;
22731let opNewValue = 0;
22732let prefersSlot3 = 1;
22733}
22734def S4_pstorerbf_abs : HInst<
22735(outs),
22736(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22737"if (!$Pv4) memb(#$Ii) = $Rt32",
22738tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
22739let Inst{2-2} = 0b1;
22740let Inst{7-7} = 0b1;
22741let Inst{13-13} = 0b0;
22742let Inst{31-18} = 0b10101111000000;
22743let isPredicated = 1;
22744let isPredicatedFalse = 1;
22745let addrMode = Absolute;
22746let accessSize = ByteAccess;
22747let isExtended = 1;
22748let mayStore = 1;
22749let BaseOpcode = "S2_storerbabs";
22750let CextOpcode = "S2_storerb";
22751let isNVStorable = 1;
22752let DecoderNamespace = "MustExtend";
22753let isExtendable = 1;
22754let opExtendable = 1;
22755let isExtentSigned = 0;
22756let opExtentBits = 6;
22757let opExtentAlign = 0;
22758}
22759def S4_pstorerbf_rr : HInst<
22760(outs),
22761(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22762"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22763tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
22764let Inst{31-21} = 0b00110101000;
22765let isPredicated = 1;
22766let isPredicatedFalse = 1;
22767let addrMode = BaseRegOffset;
22768let accessSize = ByteAccess;
22769let mayStore = 1;
22770let BaseOpcode = "S4_storerb_rr";
22771let CextOpcode = "S2_storerb";
22772let InputType = "reg";
22773let isNVStorable = 1;
22774}
22775def S4_pstorerbfnew_abs : HInst<
22776(outs),
22777(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22778"if (!$Pv4.new) memb(#$Ii) = $Rt32",
22779tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
22780let Inst{2-2} = 0b1;
22781let Inst{7-7} = 0b1;
22782let Inst{13-13} = 0b1;
22783let Inst{31-18} = 0b10101111000000;
22784let isPredicated = 1;
22785let isPredicatedFalse = 1;
22786let addrMode = Absolute;
22787let accessSize = ByteAccess;
22788let isPredicatedNew = 1;
22789let isExtended = 1;
22790let mayStore = 1;
22791let BaseOpcode = "S2_storerbabs";
22792let CextOpcode = "S2_storerb";
22793let isNVStorable = 1;
22794let DecoderNamespace = "MustExtend";
22795let isExtendable = 1;
22796let opExtendable = 1;
22797let isExtentSigned = 0;
22798let opExtentBits = 6;
22799let opExtentAlign = 0;
22800}
22801def S4_pstorerbfnew_io : HInst<
22802(outs),
22803(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22804"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22805tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22806let Inst{2-2} = 0b0;
22807let Inst{31-21} = 0b01000110000;
22808let isPredicated = 1;
22809let isPredicatedFalse = 1;
22810let addrMode = BaseImmOffset;
22811let accessSize = ByteAccess;
22812let isPredicatedNew = 1;
22813let mayStore = 1;
22814let BaseOpcode = "S2_storerb_io";
22815let CextOpcode = "S2_storerb";
22816let InputType = "imm";
22817let isNVStorable = 1;
22818let isExtendable = 1;
22819let opExtendable = 2;
22820let isExtentSigned = 0;
22821let opExtentBits = 6;
22822let opExtentAlign = 0;
22823}
22824def S4_pstorerbfnew_rr : HInst<
22825(outs),
22826(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22827"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22828tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
22829let Inst{31-21} = 0b00110111000;
22830let isPredicated = 1;
22831let isPredicatedFalse = 1;
22832let addrMode = BaseRegOffset;
22833let accessSize = ByteAccess;
22834let isPredicatedNew = 1;
22835let mayStore = 1;
22836let BaseOpcode = "S4_storerb_rr";
22837let CextOpcode = "S2_storerb";
22838let InputType = "reg";
22839let isNVStorable = 1;
22840}
22841def S4_pstorerbfnew_zomap : HInst<
22842(outs),
22843(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22844"if (!$Pv4.new) memb($Rs32) = $Rt32",
22845tc_a2b365d2, TypeMAPPING> {
22846let isPseudo = 1;
22847let isCodeGenOnly = 1;
22848}
22849def S4_pstorerbnewf_abs : HInst<
22850(outs),
22851(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22852"if (!$Pv4) memb(#$Ii) = $Nt8.new",
22853tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22854let Inst{2-2} = 0b1;
22855let Inst{7-7} = 0b1;
22856let Inst{13-11} = 0b000;
22857let Inst{31-18} = 0b10101111101000;
22858let isPredicated = 1;
22859let isPredicatedFalse = 1;
22860let addrMode = Absolute;
22861let accessSize = ByteAccess;
22862let isNVStore = 1;
22863let isNewValue = 1;
22864let isExtended = 1;
22865let isRestrictNoSlot1Store = 1;
22866let mayStore = 1;
22867let BaseOpcode = "S2_storerbabs";
22868let CextOpcode = "S2_storerb";
22869let DecoderNamespace = "MustExtend";
22870let isExtendable = 1;
22871let opExtendable = 1;
22872let isExtentSigned = 0;
22873let opExtentBits = 6;
22874let opExtentAlign = 0;
22875let opNewValue = 2;
22876}
22877def S4_pstorerbnewf_rr : HInst<
22878(outs),
22879(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22880"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22881tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22882let Inst{4-3} = 0b00;
22883let Inst{31-21} = 0b00110101101;
22884let isPredicated = 1;
22885let isPredicatedFalse = 1;
22886let addrMode = BaseRegOffset;
22887let accessSize = ByteAccess;
22888let isNVStore = 1;
22889let isNewValue = 1;
22890let isRestrictNoSlot1Store = 1;
22891let mayStore = 1;
22892let BaseOpcode = "S4_storerb_rr";
22893let CextOpcode = "S2_storerb";
22894let InputType = "reg";
22895let opNewValue = 4;
22896}
22897def S4_pstorerbnewfnew_abs : HInst<
22898(outs),
22899(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22900"if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
22901tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22902let Inst{2-2} = 0b1;
22903let Inst{7-7} = 0b1;
22904let Inst{13-11} = 0b100;
22905let Inst{31-18} = 0b10101111101000;
22906let isPredicated = 1;
22907let isPredicatedFalse = 1;
22908let addrMode = Absolute;
22909let accessSize = ByteAccess;
22910let isNVStore = 1;
22911let isPredicatedNew = 1;
22912let isNewValue = 1;
22913let isExtended = 1;
22914let isRestrictNoSlot1Store = 1;
22915let mayStore = 1;
22916let BaseOpcode = "S2_storerbabs";
22917let CextOpcode = "S2_storerb";
22918let DecoderNamespace = "MustExtend";
22919let isExtendable = 1;
22920let opExtendable = 1;
22921let isExtentSigned = 0;
22922let opExtentBits = 6;
22923let opExtentAlign = 0;
22924let opNewValue = 2;
22925}
22926def S4_pstorerbnewfnew_io : HInst<
22927(outs),
22928(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22929"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22930tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
22931let Inst{2-2} = 0b0;
22932let Inst{12-11} = 0b00;
22933let Inst{31-21} = 0b01000110101;
22934let isPredicated = 1;
22935let isPredicatedFalse = 1;
22936let addrMode = BaseImmOffset;
22937let accessSize = ByteAccess;
22938let isNVStore = 1;
22939let isPredicatedNew = 1;
22940let isNewValue = 1;
22941let isRestrictNoSlot1Store = 1;
22942let mayStore = 1;
22943let BaseOpcode = "S2_storerb_io";
22944let CextOpcode = "S2_storerb";
22945let InputType = "imm";
22946let isExtendable = 1;
22947let opExtendable = 2;
22948let isExtentSigned = 0;
22949let opExtentBits = 6;
22950let opExtentAlign = 0;
22951let opNewValue = 3;
22952}
22953def S4_pstorerbnewfnew_rr : HInst<
22954(outs),
22955(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22956"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22957tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
22958let Inst{4-3} = 0b00;
22959let Inst{31-21} = 0b00110111101;
22960let isPredicated = 1;
22961let isPredicatedFalse = 1;
22962let addrMode = BaseRegOffset;
22963let accessSize = ByteAccess;
22964let isNVStore = 1;
22965let isPredicatedNew = 1;
22966let isNewValue = 1;
22967let isRestrictNoSlot1Store = 1;
22968let mayStore = 1;
22969let BaseOpcode = "S4_storerb_rr";
22970let CextOpcode = "S2_storerb";
22971let InputType = "reg";
22972let opNewValue = 4;
22973}
22974def S4_pstorerbnewfnew_zomap : HInst<
22975(outs),
22976(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22977"if (!$Pv4.new) memb($Rs32) = $Nt8.new",
22978tc_92240447, TypeMAPPING> {
22979let isPseudo = 1;
22980let isCodeGenOnly = 1;
22981let opNewValue = 2;
22982}
22983def S4_pstorerbnewt_abs : HInst<
22984(outs),
22985(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22986"if ($Pv4) memb(#$Ii) = $Nt8.new",
22987tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22988let Inst{2-2} = 0b0;
22989let Inst{7-7} = 0b1;
22990let Inst{13-11} = 0b000;
22991let Inst{31-18} = 0b10101111101000;
22992let isPredicated = 1;
22993let addrMode = Absolute;
22994let accessSize = ByteAccess;
22995let isNVStore = 1;
22996let isNewValue = 1;
22997let isExtended = 1;
22998let isRestrictNoSlot1Store = 1;
22999let mayStore = 1;
23000let BaseOpcode = "S2_storerbabs";
23001let CextOpcode = "S2_storerb";
23002let DecoderNamespace = "MustExtend";
23003let isExtendable = 1;
23004let opExtendable = 1;
23005let isExtentSigned = 0;
23006let opExtentBits = 6;
23007let opExtentAlign = 0;
23008let opNewValue = 2;
23009}
23010def S4_pstorerbnewt_rr : HInst<
23011(outs),
23012(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23013"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23014tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23015let Inst{4-3} = 0b00;
23016let Inst{31-21} = 0b00110100101;
23017let isPredicated = 1;
23018let addrMode = BaseRegOffset;
23019let accessSize = ByteAccess;
23020let isNVStore = 1;
23021let isNewValue = 1;
23022let isRestrictNoSlot1Store = 1;
23023let mayStore = 1;
23024let BaseOpcode = "S4_storerb_rr";
23025let CextOpcode = "S2_storerb";
23026let InputType = "reg";
23027let opNewValue = 4;
23028}
23029def S4_pstorerbnewtnew_abs : HInst<
23030(outs),
23031(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23032"if ($Pv4.new) memb(#$Ii) = $Nt8.new",
23033tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23034let Inst{2-2} = 0b0;
23035let Inst{7-7} = 0b1;
23036let Inst{13-11} = 0b100;
23037let Inst{31-18} = 0b10101111101000;
23038let isPredicated = 1;
23039let addrMode = Absolute;
23040let accessSize = ByteAccess;
23041let isNVStore = 1;
23042let isPredicatedNew = 1;
23043let isNewValue = 1;
23044let isExtended = 1;
23045let isRestrictNoSlot1Store = 1;
23046let mayStore = 1;
23047let BaseOpcode = "S2_storerbabs";
23048let CextOpcode = "S2_storerb";
23049let DecoderNamespace = "MustExtend";
23050let isExtendable = 1;
23051let opExtendable = 1;
23052let isExtentSigned = 0;
23053let opExtentBits = 6;
23054let opExtentAlign = 0;
23055let opNewValue = 2;
23056}
23057def S4_pstorerbnewtnew_io : HInst<
23058(outs),
23059(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
23060"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
23061tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
23062let Inst{2-2} = 0b0;
23063let Inst{12-11} = 0b00;
23064let Inst{31-21} = 0b01000010101;
23065let isPredicated = 1;
23066let addrMode = BaseImmOffset;
23067let accessSize = ByteAccess;
23068let isNVStore = 1;
23069let isPredicatedNew = 1;
23070let isNewValue = 1;
23071let isRestrictNoSlot1Store = 1;
23072let mayStore = 1;
23073let BaseOpcode = "S2_storerb_io";
23074let CextOpcode = "S2_storerb";
23075let InputType = "imm";
23076let isExtendable = 1;
23077let opExtendable = 2;
23078let isExtentSigned = 0;
23079let opExtentBits = 6;
23080let opExtentAlign = 0;
23081let opNewValue = 3;
23082}
23083def S4_pstorerbnewtnew_rr : HInst<
23084(outs),
23085(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23086"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23087tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23088let Inst{4-3} = 0b00;
23089let Inst{31-21} = 0b00110110101;
23090let isPredicated = 1;
23091let addrMode = BaseRegOffset;
23092let accessSize = ByteAccess;
23093let isNVStore = 1;
23094let isPredicatedNew = 1;
23095let isNewValue = 1;
23096let isRestrictNoSlot1Store = 1;
23097let mayStore = 1;
23098let BaseOpcode = "S4_storerb_rr";
23099let CextOpcode = "S2_storerb";
23100let InputType = "reg";
23101let opNewValue = 4;
23102}
23103def S4_pstorerbnewtnew_zomap : HInst<
23104(outs),
23105(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23106"if ($Pv4.new) memb($Rs32) = $Nt8.new",
23107tc_92240447, TypeMAPPING> {
23108let isPseudo = 1;
23109let isCodeGenOnly = 1;
23110let opNewValue = 2;
23111}
23112def S4_pstorerbt_abs : HInst<
23113(outs),
23114(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23115"if ($Pv4) memb(#$Ii) = $Rt32",
23116tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23117let Inst{2-2} = 0b0;
23118let Inst{7-7} = 0b1;
23119let Inst{13-13} = 0b0;
23120let Inst{31-18} = 0b10101111000000;
23121let isPredicated = 1;
23122let addrMode = Absolute;
23123let accessSize = ByteAccess;
23124let isExtended = 1;
23125let mayStore = 1;
23126let BaseOpcode = "S2_storerbabs";
23127let CextOpcode = "S2_storerb";
23128let isNVStorable = 1;
23129let DecoderNamespace = "MustExtend";
23130let isExtendable = 1;
23131let opExtendable = 1;
23132let isExtentSigned = 0;
23133let opExtentBits = 6;
23134let opExtentAlign = 0;
23135}
23136def S4_pstorerbt_rr : HInst<
23137(outs),
23138(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23139"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23140tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23141let Inst{31-21} = 0b00110100000;
23142let isPredicated = 1;
23143let addrMode = BaseRegOffset;
23144let accessSize = ByteAccess;
23145let mayStore = 1;
23146let BaseOpcode = "S4_storerb_rr";
23147let CextOpcode = "S2_storerb";
23148let InputType = "reg";
23149let isNVStorable = 1;
23150}
23151def S4_pstorerbtnew_abs : HInst<
23152(outs),
23153(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23154"if ($Pv4.new) memb(#$Ii) = $Rt32",
23155tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23156let Inst{2-2} = 0b0;
23157let Inst{7-7} = 0b1;
23158let Inst{13-13} = 0b1;
23159let Inst{31-18} = 0b10101111000000;
23160let isPredicated = 1;
23161let addrMode = Absolute;
23162let accessSize = ByteAccess;
23163let isPredicatedNew = 1;
23164let isExtended = 1;
23165let mayStore = 1;
23166let BaseOpcode = "S2_storerbabs";
23167let CextOpcode = "S2_storerb";
23168let isNVStorable = 1;
23169let DecoderNamespace = "MustExtend";
23170let isExtendable = 1;
23171let opExtendable = 1;
23172let isExtentSigned = 0;
23173let opExtentBits = 6;
23174let opExtentAlign = 0;
23175}
23176def S4_pstorerbtnew_io : HInst<
23177(outs),
23178(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
23179"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
23180tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
23181let Inst{2-2} = 0b0;
23182let Inst{31-21} = 0b01000010000;
23183let isPredicated = 1;
23184let addrMode = BaseImmOffset;
23185let accessSize = ByteAccess;
23186let isPredicatedNew = 1;
23187let mayStore = 1;
23188let BaseOpcode = "S2_storerb_io";
23189let CextOpcode = "S2_storerb";
23190let InputType = "imm";
23191let isNVStorable = 1;
23192let isExtendable = 1;
23193let opExtendable = 2;
23194let isExtentSigned = 0;
23195let opExtentBits = 6;
23196let opExtentAlign = 0;
23197}
23198def S4_pstorerbtnew_rr : HInst<
23199(outs),
23200(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23201"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23202tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23203let Inst{31-21} = 0b00110110000;
23204let isPredicated = 1;
23205let addrMode = BaseRegOffset;
23206let accessSize = ByteAccess;
23207let isPredicatedNew = 1;
23208let mayStore = 1;
23209let BaseOpcode = "S4_storerb_rr";
23210let CextOpcode = "S2_storerb";
23211let InputType = "reg";
23212let isNVStorable = 1;
23213}
23214def S4_pstorerbtnew_zomap : HInst<
23215(outs),
23216(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23217"if ($Pv4.new) memb($Rs32) = $Rt32",
23218tc_a2b365d2, TypeMAPPING> {
23219let isPseudo = 1;
23220let isCodeGenOnly = 1;
23221}
23222def S4_pstorerdf_abs : HInst<
23223(outs),
23224(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23225"if (!$Pv4) memd(#$Ii) = $Rtt32",
23226tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23227let Inst{2-2} = 0b1;
23228let Inst{7-7} = 0b1;
23229let Inst{13-13} = 0b0;
23230let Inst{31-18} = 0b10101111110000;
23231let isPredicated = 1;
23232let isPredicatedFalse = 1;
23233let addrMode = Absolute;
23234let accessSize = DoubleWordAccess;
23235let isExtended = 1;
23236let mayStore = 1;
23237let BaseOpcode = "S2_storerdabs";
23238let CextOpcode = "S2_storerd";
23239let DecoderNamespace = "MustExtend";
23240let isExtendable = 1;
23241let opExtendable = 1;
23242let isExtentSigned = 0;
23243let opExtentBits = 6;
23244let opExtentAlign = 0;
23245}
23246def S4_pstorerdf_rr : HInst<
23247(outs),
23248(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23249"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23250tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23251let Inst{31-21} = 0b00110101110;
23252let isPredicated = 1;
23253let isPredicatedFalse = 1;
23254let addrMode = BaseRegOffset;
23255let accessSize = DoubleWordAccess;
23256let mayStore = 1;
23257let BaseOpcode = "S2_storerd_rr";
23258let CextOpcode = "S2_storerd";
23259let InputType = "reg";
23260}
23261def S4_pstorerdfnew_abs : HInst<
23262(outs),
23263(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23264"if (!$Pv4.new) memd(#$Ii) = $Rtt32",
23265tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23266let Inst{2-2} = 0b1;
23267let Inst{7-7} = 0b1;
23268let Inst{13-13} = 0b1;
23269let Inst{31-18} = 0b10101111110000;
23270let isPredicated = 1;
23271let isPredicatedFalse = 1;
23272let addrMode = Absolute;
23273let accessSize = DoubleWordAccess;
23274let isPredicatedNew = 1;
23275let isExtended = 1;
23276let mayStore = 1;
23277let BaseOpcode = "S2_storerdabs";
23278let CextOpcode = "S2_storerd";
23279let DecoderNamespace = "MustExtend";
23280let isExtendable = 1;
23281let opExtendable = 1;
23282let isExtentSigned = 0;
23283let opExtentBits = 6;
23284let opExtentAlign = 0;
23285}
23286def S4_pstorerdfnew_io : HInst<
23287(outs),
23288(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23289"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23290tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23291let Inst{2-2} = 0b0;
23292let Inst{31-21} = 0b01000110110;
23293let isPredicated = 1;
23294let isPredicatedFalse = 1;
23295let addrMode = BaseImmOffset;
23296let accessSize = DoubleWordAccess;
23297let isPredicatedNew = 1;
23298let mayStore = 1;
23299let BaseOpcode = "S2_storerd_io";
23300let CextOpcode = "S2_storerd";
23301let InputType = "imm";
23302let isExtendable = 1;
23303let opExtendable = 2;
23304let isExtentSigned = 0;
23305let opExtentBits = 9;
23306let opExtentAlign = 3;
23307}
23308def S4_pstorerdfnew_rr : HInst<
23309(outs),
23310(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23311"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23312tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23313let Inst{31-21} = 0b00110111110;
23314let isPredicated = 1;
23315let isPredicatedFalse = 1;
23316let addrMode = BaseRegOffset;
23317let accessSize = DoubleWordAccess;
23318let isPredicatedNew = 1;
23319let mayStore = 1;
23320let BaseOpcode = "S2_storerd_rr";
23321let CextOpcode = "S2_storerd";
23322let InputType = "reg";
23323}
23324def S4_pstorerdfnew_zomap : HInst<
23325(outs),
23326(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23327"if (!$Pv4.new) memd($Rs32) = $Rtt32",
23328tc_a2b365d2, TypeMAPPING> {
23329let isPseudo = 1;
23330let isCodeGenOnly = 1;
23331}
23332def S4_pstorerdt_abs : HInst<
23333(outs),
23334(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23335"if ($Pv4) memd(#$Ii) = $Rtt32",
23336tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23337let Inst{2-2} = 0b0;
23338let Inst{7-7} = 0b1;
23339let Inst{13-13} = 0b0;
23340let Inst{31-18} = 0b10101111110000;
23341let isPredicated = 1;
23342let addrMode = Absolute;
23343let accessSize = DoubleWordAccess;
23344let isExtended = 1;
23345let mayStore = 1;
23346let BaseOpcode = "S2_storerdabs";
23347let CextOpcode = "S2_storerd";
23348let DecoderNamespace = "MustExtend";
23349let isExtendable = 1;
23350let opExtendable = 1;
23351let isExtentSigned = 0;
23352let opExtentBits = 6;
23353let opExtentAlign = 0;
23354}
23355def S4_pstorerdt_rr : HInst<
23356(outs),
23357(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23358"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23359tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23360let Inst{31-21} = 0b00110100110;
23361let isPredicated = 1;
23362let addrMode = BaseRegOffset;
23363let accessSize = DoubleWordAccess;
23364let mayStore = 1;
23365let BaseOpcode = "S2_storerd_rr";
23366let CextOpcode = "S2_storerd";
23367let InputType = "reg";
23368}
23369def S4_pstorerdtnew_abs : HInst<
23370(outs),
23371(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23372"if ($Pv4.new) memd(#$Ii) = $Rtt32",
23373tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23374let Inst{2-2} = 0b0;
23375let Inst{7-7} = 0b1;
23376let Inst{13-13} = 0b1;
23377let Inst{31-18} = 0b10101111110000;
23378let isPredicated = 1;
23379let addrMode = Absolute;
23380let accessSize = DoubleWordAccess;
23381let isPredicatedNew = 1;
23382let isExtended = 1;
23383let mayStore = 1;
23384let BaseOpcode = "S2_storerdabs";
23385let CextOpcode = "S2_storerd";
23386let DecoderNamespace = "MustExtend";
23387let isExtendable = 1;
23388let opExtendable = 1;
23389let isExtentSigned = 0;
23390let opExtentBits = 6;
23391let opExtentAlign = 0;
23392}
23393def S4_pstorerdtnew_io : HInst<
23394(outs),
23395(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23396"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23397tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23398let Inst{2-2} = 0b0;
23399let Inst{31-21} = 0b01000010110;
23400let isPredicated = 1;
23401let addrMode = BaseImmOffset;
23402let accessSize = DoubleWordAccess;
23403let isPredicatedNew = 1;
23404let mayStore = 1;
23405let BaseOpcode = "S2_storerd_io";
23406let CextOpcode = "S2_storerd";
23407let InputType = "imm";
23408let isExtendable = 1;
23409let opExtendable = 2;
23410let isExtentSigned = 0;
23411let opExtentBits = 9;
23412let opExtentAlign = 3;
23413}
23414def S4_pstorerdtnew_rr : HInst<
23415(outs),
23416(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23417"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23418tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23419let Inst{31-21} = 0b00110110110;
23420let isPredicated = 1;
23421let addrMode = BaseRegOffset;
23422let accessSize = DoubleWordAccess;
23423let isPredicatedNew = 1;
23424let mayStore = 1;
23425let BaseOpcode = "S2_storerd_rr";
23426let CextOpcode = "S2_storerd";
23427let InputType = "reg";
23428}
23429def S4_pstorerdtnew_zomap : HInst<
23430(outs),
23431(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23432"if ($Pv4.new) memd($Rs32) = $Rtt32",
23433tc_a2b365d2, TypeMAPPING> {
23434let isPseudo = 1;
23435let isCodeGenOnly = 1;
23436}
23437def S4_pstorerff_abs : HInst<
23438(outs),
23439(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23440"if (!$Pv4) memh(#$Ii) = $Rt32.h",
23441tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23442let Inst{2-2} = 0b1;
23443let Inst{7-7} = 0b1;
23444let Inst{13-13} = 0b0;
23445let Inst{31-18} = 0b10101111011000;
23446let isPredicated = 1;
23447let isPredicatedFalse = 1;
23448let addrMode = Absolute;
23449let accessSize = HalfWordAccess;
23450let isExtended = 1;
23451let mayStore = 1;
23452let BaseOpcode = "S2_storerfabs";
23453let CextOpcode = "S2_storerf";
23454let DecoderNamespace = "MustExtend";
23455let isExtendable = 1;
23456let opExtendable = 1;
23457let isExtentSigned = 0;
23458let opExtentBits = 6;
23459let opExtentAlign = 0;
23460}
23461def S4_pstorerff_rr : HInst<
23462(outs),
23463(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23464"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23465tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23466let Inst{31-21} = 0b00110101011;
23467let isPredicated = 1;
23468let isPredicatedFalse = 1;
23469let addrMode = BaseRegOffset;
23470let accessSize = HalfWordAccess;
23471let mayStore = 1;
23472let BaseOpcode = "S4_storerf_rr";
23473let CextOpcode = "S2_storerf";
23474let InputType = "reg";
23475}
23476def S4_pstorerffnew_abs : HInst<
23477(outs),
23478(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23479"if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
23480tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23481let Inst{2-2} = 0b1;
23482let Inst{7-7} = 0b1;
23483let Inst{13-13} = 0b1;
23484let Inst{31-18} = 0b10101111011000;
23485let isPredicated = 1;
23486let isPredicatedFalse = 1;
23487let addrMode = Absolute;
23488let accessSize = HalfWordAccess;
23489let isPredicatedNew = 1;
23490let isExtended = 1;
23491let mayStore = 1;
23492let BaseOpcode = "S2_storerfabs";
23493let CextOpcode = "S2_storerf";
23494let DecoderNamespace = "MustExtend";
23495let isExtendable = 1;
23496let opExtendable = 1;
23497let isExtentSigned = 0;
23498let opExtentBits = 6;
23499let opExtentAlign = 0;
23500}
23501def S4_pstorerffnew_io : HInst<
23502(outs),
23503(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23504"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23505tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23506let Inst{2-2} = 0b0;
23507let Inst{31-21} = 0b01000110011;
23508let isPredicated = 1;
23509let isPredicatedFalse = 1;
23510let addrMode = BaseImmOffset;
23511let accessSize = HalfWordAccess;
23512let isPredicatedNew = 1;
23513let mayStore = 1;
23514let BaseOpcode = "S2_storerf_io";
23515let CextOpcode = "S2_storerf";
23516let InputType = "imm";
23517let isExtendable = 1;
23518let opExtendable = 2;
23519let isExtentSigned = 0;
23520let opExtentBits = 7;
23521let opExtentAlign = 1;
23522}
23523def S4_pstorerffnew_rr : HInst<
23524(outs),
23525(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23526"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23527tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23528let Inst{31-21} = 0b00110111011;
23529let isPredicated = 1;
23530let isPredicatedFalse = 1;
23531let addrMode = BaseRegOffset;
23532let accessSize = HalfWordAccess;
23533let isPredicatedNew = 1;
23534let mayStore = 1;
23535let BaseOpcode = "S4_storerf_rr";
23536let CextOpcode = "S2_storerf";
23537let InputType = "reg";
23538}
23539def S4_pstorerffnew_zomap : HInst<
23540(outs),
23541(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23542"if (!$Pv4.new) memh($Rs32) = $Rt32.h",
23543tc_a2b365d2, TypeMAPPING> {
23544let isPseudo = 1;
23545let isCodeGenOnly = 1;
23546}
23547def S4_pstorerft_abs : HInst<
23548(outs),
23549(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23550"if ($Pv4) memh(#$Ii) = $Rt32.h",
23551tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23552let Inst{2-2} = 0b0;
23553let Inst{7-7} = 0b1;
23554let Inst{13-13} = 0b0;
23555let Inst{31-18} = 0b10101111011000;
23556let isPredicated = 1;
23557let addrMode = Absolute;
23558let accessSize = HalfWordAccess;
23559let isExtended = 1;
23560let mayStore = 1;
23561let BaseOpcode = "S2_storerfabs";
23562let CextOpcode = "S2_storerf";
23563let DecoderNamespace = "MustExtend";
23564let isExtendable = 1;
23565let opExtendable = 1;
23566let isExtentSigned = 0;
23567let opExtentBits = 6;
23568let opExtentAlign = 0;
23569}
23570def S4_pstorerft_rr : HInst<
23571(outs),
23572(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23573"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23574tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23575let Inst{31-21} = 0b00110100011;
23576let isPredicated = 1;
23577let addrMode = BaseRegOffset;
23578let accessSize = HalfWordAccess;
23579let mayStore = 1;
23580let BaseOpcode = "S4_storerf_rr";
23581let CextOpcode = "S2_storerf";
23582let InputType = "reg";
23583}
23584def S4_pstorerftnew_abs : HInst<
23585(outs),
23586(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23587"if ($Pv4.new) memh(#$Ii) = $Rt32.h",
23588tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23589let Inst{2-2} = 0b0;
23590let Inst{7-7} = 0b1;
23591let Inst{13-13} = 0b1;
23592let Inst{31-18} = 0b10101111011000;
23593let isPredicated = 1;
23594let addrMode = Absolute;
23595let accessSize = HalfWordAccess;
23596let isPredicatedNew = 1;
23597let isExtended = 1;
23598let mayStore = 1;
23599let BaseOpcode = "S2_storerfabs";
23600let CextOpcode = "S2_storerf";
23601let DecoderNamespace = "MustExtend";
23602let isExtendable = 1;
23603let opExtendable = 1;
23604let isExtentSigned = 0;
23605let opExtentBits = 6;
23606let opExtentAlign = 0;
23607}
23608def S4_pstorerftnew_io : HInst<
23609(outs),
23610(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23611"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23612tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23613let Inst{2-2} = 0b0;
23614let Inst{31-21} = 0b01000010011;
23615let isPredicated = 1;
23616let addrMode = BaseImmOffset;
23617let accessSize = HalfWordAccess;
23618let isPredicatedNew = 1;
23619let mayStore = 1;
23620let BaseOpcode = "S2_storerf_io";
23621let CextOpcode = "S2_storerf";
23622let InputType = "imm";
23623let isExtendable = 1;
23624let opExtendable = 2;
23625let isExtentSigned = 0;
23626let opExtentBits = 7;
23627let opExtentAlign = 1;
23628}
23629def S4_pstorerftnew_rr : HInst<
23630(outs),
23631(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23632"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23633tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23634let Inst{31-21} = 0b00110110011;
23635let isPredicated = 1;
23636let addrMode = BaseRegOffset;
23637let accessSize = HalfWordAccess;
23638let isPredicatedNew = 1;
23639let mayStore = 1;
23640let BaseOpcode = "S4_storerf_rr";
23641let CextOpcode = "S2_storerf";
23642let InputType = "reg";
23643}
23644def S4_pstorerftnew_zomap : HInst<
23645(outs),
23646(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23647"if ($Pv4.new) memh($Rs32) = $Rt32.h",
23648tc_a2b365d2, TypeMAPPING> {
23649let isPseudo = 1;
23650let isCodeGenOnly = 1;
23651}
23652def S4_pstorerhf_abs : HInst<
23653(outs),
23654(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23655"if (!$Pv4) memh(#$Ii) = $Rt32",
23656tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23657let Inst{2-2} = 0b1;
23658let Inst{7-7} = 0b1;
23659let Inst{13-13} = 0b0;
23660let Inst{31-18} = 0b10101111010000;
23661let isPredicated = 1;
23662let isPredicatedFalse = 1;
23663let addrMode = Absolute;
23664let accessSize = HalfWordAccess;
23665let isExtended = 1;
23666let mayStore = 1;
23667let BaseOpcode = "S2_storerhabs";
23668let CextOpcode = "S2_storerh";
23669let isNVStorable = 1;
23670let DecoderNamespace = "MustExtend";
23671let isExtendable = 1;
23672let opExtendable = 1;
23673let isExtentSigned = 0;
23674let opExtentBits = 6;
23675let opExtentAlign = 0;
23676}
23677def S4_pstorerhf_rr : HInst<
23678(outs),
23679(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23680"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23681tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23682let Inst{31-21} = 0b00110101010;
23683let isPredicated = 1;
23684let isPredicatedFalse = 1;
23685let addrMode = BaseRegOffset;
23686let accessSize = HalfWordAccess;
23687let mayStore = 1;
23688let BaseOpcode = "S2_storerh_rr";
23689let CextOpcode = "S2_storerh";
23690let InputType = "reg";
23691let isNVStorable = 1;
23692}
23693def S4_pstorerhfnew_abs : HInst<
23694(outs),
23695(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23696"if (!$Pv4.new) memh(#$Ii) = $Rt32",
23697tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23698let Inst{2-2} = 0b1;
23699let Inst{7-7} = 0b1;
23700let Inst{13-13} = 0b1;
23701let Inst{31-18} = 0b10101111010000;
23702let isPredicated = 1;
23703let isPredicatedFalse = 1;
23704let addrMode = Absolute;
23705let accessSize = HalfWordAccess;
23706let isPredicatedNew = 1;
23707let isExtended = 1;
23708let mayStore = 1;
23709let BaseOpcode = "S2_storerhabs";
23710let CextOpcode = "S2_storerh";
23711let isNVStorable = 1;
23712let DecoderNamespace = "MustExtend";
23713let isExtendable = 1;
23714let opExtendable = 1;
23715let isExtentSigned = 0;
23716let opExtentBits = 6;
23717let opExtentAlign = 0;
23718}
23719def S4_pstorerhfnew_io : HInst<
23720(outs),
23721(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23722"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23723tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23724let Inst{2-2} = 0b0;
23725let Inst{31-21} = 0b01000110010;
23726let isPredicated = 1;
23727let isPredicatedFalse = 1;
23728let addrMode = BaseImmOffset;
23729let accessSize = HalfWordAccess;
23730let isPredicatedNew = 1;
23731let mayStore = 1;
23732let BaseOpcode = "S2_storerh_io";
23733let CextOpcode = "S2_storerh";
23734let InputType = "imm";
23735let isNVStorable = 1;
23736let isExtendable = 1;
23737let opExtendable = 2;
23738let isExtentSigned = 0;
23739let opExtentBits = 7;
23740let opExtentAlign = 1;
23741}
23742def S4_pstorerhfnew_rr : HInst<
23743(outs),
23744(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23745"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23746tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23747let Inst{31-21} = 0b00110111010;
23748let isPredicated = 1;
23749let isPredicatedFalse = 1;
23750let addrMode = BaseRegOffset;
23751let accessSize = HalfWordAccess;
23752let isPredicatedNew = 1;
23753let mayStore = 1;
23754let BaseOpcode = "S2_storerh_rr";
23755let CextOpcode = "S2_storerh";
23756let InputType = "reg";
23757let isNVStorable = 1;
23758}
23759def S4_pstorerhfnew_zomap : HInst<
23760(outs),
23761(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23762"if (!$Pv4.new) memh($Rs32) = $Rt32",
23763tc_a2b365d2, TypeMAPPING> {
23764let isPseudo = 1;
23765let isCodeGenOnly = 1;
23766}
23767def S4_pstorerhnewf_abs : HInst<
23768(outs),
23769(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23770"if (!$Pv4) memh(#$Ii) = $Nt8.new",
23771tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23772let Inst{2-2} = 0b1;
23773let Inst{7-7} = 0b1;
23774let Inst{13-11} = 0b001;
23775let Inst{31-18} = 0b10101111101000;
23776let isPredicated = 1;
23777let isPredicatedFalse = 1;
23778let addrMode = Absolute;
23779let accessSize = HalfWordAccess;
23780let isNVStore = 1;
23781let isNewValue = 1;
23782let isExtended = 1;
23783let isRestrictNoSlot1Store = 1;
23784let mayStore = 1;
23785let BaseOpcode = "S2_storerhabs";
23786let CextOpcode = "S2_storerh";
23787let DecoderNamespace = "MustExtend";
23788let isExtendable = 1;
23789let opExtendable = 1;
23790let isExtentSigned = 0;
23791let opExtentBits = 6;
23792let opExtentAlign = 0;
23793let opNewValue = 2;
23794}
23795def S4_pstorerhnewf_rr : HInst<
23796(outs),
23797(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23798"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23799tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23800let Inst{4-3} = 0b01;
23801let Inst{31-21} = 0b00110101101;
23802let isPredicated = 1;
23803let isPredicatedFalse = 1;
23804let addrMode = BaseRegOffset;
23805let accessSize = HalfWordAccess;
23806let isNVStore = 1;
23807let isNewValue = 1;
23808let isRestrictNoSlot1Store = 1;
23809let mayStore = 1;
23810let BaseOpcode = "S2_storerh_rr";
23811let CextOpcode = "S2_storerh";
23812let InputType = "reg";
23813let opNewValue = 4;
23814}
23815def S4_pstorerhnewfnew_abs : HInst<
23816(outs),
23817(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23818"if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
23819tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23820let Inst{2-2} = 0b1;
23821let Inst{7-7} = 0b1;
23822let Inst{13-11} = 0b101;
23823let Inst{31-18} = 0b10101111101000;
23824let isPredicated = 1;
23825let isPredicatedFalse = 1;
23826let addrMode = Absolute;
23827let accessSize = HalfWordAccess;
23828let isNVStore = 1;
23829let isPredicatedNew = 1;
23830let isNewValue = 1;
23831let isExtended = 1;
23832let isRestrictNoSlot1Store = 1;
23833let mayStore = 1;
23834let BaseOpcode = "S2_storerhabs";
23835let CextOpcode = "S2_storerh";
23836let DecoderNamespace = "MustExtend";
23837let isExtendable = 1;
23838let opExtendable = 1;
23839let isExtentSigned = 0;
23840let opExtentBits = 6;
23841let opExtentAlign = 0;
23842let opNewValue = 2;
23843}
23844def S4_pstorerhnewfnew_io : HInst<
23845(outs),
23846(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23847"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23848tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23849let Inst{2-2} = 0b0;
23850let Inst{12-11} = 0b01;
23851let Inst{31-21} = 0b01000110101;
23852let isPredicated = 1;
23853let isPredicatedFalse = 1;
23854let addrMode = BaseImmOffset;
23855let accessSize = HalfWordAccess;
23856let isNVStore = 1;
23857let isPredicatedNew = 1;
23858let isNewValue = 1;
23859let isRestrictNoSlot1Store = 1;
23860let mayStore = 1;
23861let BaseOpcode = "S2_storerh_io";
23862let CextOpcode = "S2_storerh";
23863let InputType = "imm";
23864let isExtendable = 1;
23865let opExtendable = 2;
23866let isExtentSigned = 0;
23867let opExtentBits = 7;
23868let opExtentAlign = 1;
23869let opNewValue = 3;
23870}
23871def S4_pstorerhnewfnew_rr : HInst<
23872(outs),
23873(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23874"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23875tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23876let Inst{4-3} = 0b01;
23877let Inst{31-21} = 0b00110111101;
23878let isPredicated = 1;
23879let isPredicatedFalse = 1;
23880let addrMode = BaseRegOffset;
23881let accessSize = HalfWordAccess;
23882let isNVStore = 1;
23883let isPredicatedNew = 1;
23884let isNewValue = 1;
23885let isRestrictNoSlot1Store = 1;
23886let mayStore = 1;
23887let BaseOpcode = "S2_storerh_rr";
23888let CextOpcode = "S2_storerh";
23889let InputType = "reg";
23890let opNewValue = 4;
23891}
23892def S4_pstorerhnewfnew_zomap : HInst<
23893(outs),
23894(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23895"if (!$Pv4.new) memh($Rs32) = $Nt8.new",
23896tc_92240447, TypeMAPPING> {
23897let isPseudo = 1;
23898let isCodeGenOnly = 1;
23899let opNewValue = 2;
23900}
23901def S4_pstorerhnewt_abs : HInst<
23902(outs),
23903(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23904"if ($Pv4) memh(#$Ii) = $Nt8.new",
23905tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23906let Inst{2-2} = 0b0;
23907let Inst{7-7} = 0b1;
23908let Inst{13-11} = 0b001;
23909let Inst{31-18} = 0b10101111101000;
23910let isPredicated = 1;
23911let addrMode = Absolute;
23912let accessSize = HalfWordAccess;
23913let isNVStore = 1;
23914let isNewValue = 1;
23915let isExtended = 1;
23916let isRestrictNoSlot1Store = 1;
23917let mayStore = 1;
23918let BaseOpcode = "S2_storerhabs";
23919let CextOpcode = "S2_storerh";
23920let DecoderNamespace = "MustExtend";
23921let isExtendable = 1;
23922let opExtendable = 1;
23923let isExtentSigned = 0;
23924let opExtentBits = 6;
23925let opExtentAlign = 0;
23926let opNewValue = 2;
23927}
23928def S4_pstorerhnewt_rr : HInst<
23929(outs),
23930(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23931"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23932tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23933let Inst{4-3} = 0b01;
23934let Inst{31-21} = 0b00110100101;
23935let isPredicated = 1;
23936let addrMode = BaseRegOffset;
23937let accessSize = HalfWordAccess;
23938let isNVStore = 1;
23939let isNewValue = 1;
23940let isRestrictNoSlot1Store = 1;
23941let mayStore = 1;
23942let BaseOpcode = "S2_storerh_rr";
23943let CextOpcode = "S2_storerh";
23944let InputType = "reg";
23945let opNewValue = 4;
23946}
23947def S4_pstorerhnewtnew_abs : HInst<
23948(outs),
23949(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23950"if ($Pv4.new) memh(#$Ii) = $Nt8.new",
23951tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23952let Inst{2-2} = 0b0;
23953let Inst{7-7} = 0b1;
23954let Inst{13-11} = 0b101;
23955let Inst{31-18} = 0b10101111101000;
23956let isPredicated = 1;
23957let addrMode = Absolute;
23958let accessSize = HalfWordAccess;
23959let isNVStore = 1;
23960let isPredicatedNew = 1;
23961let isNewValue = 1;
23962let isExtended = 1;
23963let isRestrictNoSlot1Store = 1;
23964let mayStore = 1;
23965let BaseOpcode = "S2_storerhabs";
23966let CextOpcode = "S2_storerh";
23967let DecoderNamespace = "MustExtend";
23968let isExtendable = 1;
23969let opExtendable = 1;
23970let isExtentSigned = 0;
23971let opExtentBits = 6;
23972let opExtentAlign = 0;
23973let opNewValue = 2;
23974}
23975def S4_pstorerhnewtnew_io : HInst<
23976(outs),
23977(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23978"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23979tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23980let Inst{2-2} = 0b0;
23981let Inst{12-11} = 0b01;
23982let Inst{31-21} = 0b01000010101;
23983let isPredicated = 1;
23984let addrMode = BaseImmOffset;
23985let accessSize = HalfWordAccess;
23986let isNVStore = 1;
23987let isPredicatedNew = 1;
23988let isNewValue = 1;
23989let isRestrictNoSlot1Store = 1;
23990let mayStore = 1;
23991let BaseOpcode = "S2_storerh_io";
23992let CextOpcode = "S2_storerh";
23993let InputType = "imm";
23994let isExtendable = 1;
23995let opExtendable = 2;
23996let isExtentSigned = 0;
23997let opExtentBits = 7;
23998let opExtentAlign = 1;
23999let opNewValue = 3;
24000}
24001def S4_pstorerhnewtnew_rr : HInst<
24002(outs),
24003(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24004"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24005tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24006let Inst{4-3} = 0b01;
24007let Inst{31-21} = 0b00110110101;
24008let isPredicated = 1;
24009let addrMode = BaseRegOffset;
24010let accessSize = HalfWordAccess;
24011let isNVStore = 1;
24012let isPredicatedNew = 1;
24013let isNewValue = 1;
24014let isRestrictNoSlot1Store = 1;
24015let mayStore = 1;
24016let BaseOpcode = "S2_storerh_rr";
24017let CextOpcode = "S2_storerh";
24018let InputType = "reg";
24019let opNewValue = 4;
24020}
24021def S4_pstorerhnewtnew_zomap : HInst<
24022(outs),
24023(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24024"if ($Pv4.new) memh($Rs32) = $Nt8.new",
24025tc_92240447, TypeMAPPING> {
24026let isPseudo = 1;
24027let isCodeGenOnly = 1;
24028let opNewValue = 2;
24029}
24030def S4_pstorerht_abs : HInst<
24031(outs),
24032(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24033"if ($Pv4) memh(#$Ii) = $Rt32",
24034tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24035let Inst{2-2} = 0b0;
24036let Inst{7-7} = 0b1;
24037let Inst{13-13} = 0b0;
24038let Inst{31-18} = 0b10101111010000;
24039let isPredicated = 1;
24040let addrMode = Absolute;
24041let accessSize = HalfWordAccess;
24042let isExtended = 1;
24043let mayStore = 1;
24044let BaseOpcode = "S2_storerhabs";
24045let CextOpcode = "S2_storerh";
24046let isNVStorable = 1;
24047let DecoderNamespace = "MustExtend";
24048let isExtendable = 1;
24049let opExtendable = 1;
24050let isExtentSigned = 0;
24051let opExtentBits = 6;
24052let opExtentAlign = 0;
24053}
24054def S4_pstorerht_rr : HInst<
24055(outs),
24056(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24057"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24058tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24059let Inst{31-21} = 0b00110100010;
24060let isPredicated = 1;
24061let addrMode = BaseRegOffset;
24062let accessSize = HalfWordAccess;
24063let mayStore = 1;
24064let BaseOpcode = "S2_storerh_rr";
24065let CextOpcode = "S2_storerh";
24066let InputType = "reg";
24067let isNVStorable = 1;
24068}
24069def S4_pstorerhtnew_abs : HInst<
24070(outs),
24071(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24072"if ($Pv4.new) memh(#$Ii) = $Rt32",
24073tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24074let Inst{2-2} = 0b0;
24075let Inst{7-7} = 0b1;
24076let Inst{13-13} = 0b1;
24077let Inst{31-18} = 0b10101111010000;
24078let isPredicated = 1;
24079let addrMode = Absolute;
24080let accessSize = HalfWordAccess;
24081let isPredicatedNew = 1;
24082let isExtended = 1;
24083let mayStore = 1;
24084let BaseOpcode = "S2_storerhabs";
24085let CextOpcode = "S2_storerh";
24086let isNVStorable = 1;
24087let DecoderNamespace = "MustExtend";
24088let isExtendable = 1;
24089let opExtendable = 1;
24090let isExtentSigned = 0;
24091let opExtentBits = 6;
24092let opExtentAlign = 0;
24093}
24094def S4_pstorerhtnew_io : HInst<
24095(outs),
24096(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
24097"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
24098tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
24099let Inst{2-2} = 0b0;
24100let Inst{31-21} = 0b01000010010;
24101let isPredicated = 1;
24102let addrMode = BaseImmOffset;
24103let accessSize = HalfWordAccess;
24104let isPredicatedNew = 1;
24105let mayStore = 1;
24106let BaseOpcode = "S2_storerh_io";
24107let CextOpcode = "S2_storerh";
24108let InputType = "imm";
24109let isNVStorable = 1;
24110let isExtendable = 1;
24111let opExtendable = 2;
24112let isExtentSigned = 0;
24113let opExtentBits = 7;
24114let opExtentAlign = 1;
24115}
24116def S4_pstorerhtnew_rr : HInst<
24117(outs),
24118(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24119"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24120tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24121let Inst{31-21} = 0b00110110010;
24122let isPredicated = 1;
24123let addrMode = BaseRegOffset;
24124let accessSize = HalfWordAccess;
24125let isPredicatedNew = 1;
24126let mayStore = 1;
24127let BaseOpcode = "S2_storerh_rr";
24128let CextOpcode = "S2_storerh";
24129let InputType = "reg";
24130let isNVStorable = 1;
24131}
24132def S4_pstorerhtnew_zomap : HInst<
24133(outs),
24134(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24135"if ($Pv4.new) memh($Rs32) = $Rt32",
24136tc_a2b365d2, TypeMAPPING> {
24137let isPseudo = 1;
24138let isCodeGenOnly = 1;
24139}
24140def S4_pstorerif_abs : HInst<
24141(outs),
24142(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24143"if (!$Pv4) memw(#$Ii) = $Rt32",
24144tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24145let Inst{2-2} = 0b1;
24146let Inst{7-7} = 0b1;
24147let Inst{13-13} = 0b0;
24148let Inst{31-18} = 0b10101111100000;
24149let isPredicated = 1;
24150let isPredicatedFalse = 1;
24151let addrMode = Absolute;
24152let accessSize = WordAccess;
24153let isExtended = 1;
24154let mayStore = 1;
24155let BaseOpcode = "S2_storeriabs";
24156let CextOpcode = "S2_storeri";
24157let isNVStorable = 1;
24158let DecoderNamespace = "MustExtend";
24159let isExtendable = 1;
24160let opExtendable = 1;
24161let isExtentSigned = 0;
24162let opExtentBits = 6;
24163let opExtentAlign = 0;
24164}
24165def S4_pstorerif_rr : HInst<
24166(outs),
24167(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24168"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24169tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24170let Inst{31-21} = 0b00110101100;
24171let isPredicated = 1;
24172let isPredicatedFalse = 1;
24173let addrMode = BaseRegOffset;
24174let accessSize = WordAccess;
24175let mayStore = 1;
24176let BaseOpcode = "S2_storeri_rr";
24177let CextOpcode = "S2_storeri";
24178let InputType = "reg";
24179let isNVStorable = 1;
24180}
24181def S4_pstorerifnew_abs : HInst<
24182(outs),
24183(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24184"if (!$Pv4.new) memw(#$Ii) = $Rt32",
24185tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24186let Inst{2-2} = 0b1;
24187let Inst{7-7} = 0b1;
24188let Inst{13-13} = 0b1;
24189let Inst{31-18} = 0b10101111100000;
24190let isPredicated = 1;
24191let isPredicatedFalse = 1;
24192let addrMode = Absolute;
24193let accessSize = WordAccess;
24194let isPredicatedNew = 1;
24195let isExtended = 1;
24196let mayStore = 1;
24197let BaseOpcode = "S2_storeriabs";
24198let CextOpcode = "S2_storeri";
24199let isNVStorable = 1;
24200let DecoderNamespace = "MustExtend";
24201let isExtendable = 1;
24202let opExtendable = 1;
24203let isExtentSigned = 0;
24204let opExtentBits = 6;
24205let opExtentAlign = 0;
24206}
24207def S4_pstorerifnew_io : HInst<
24208(outs),
24209(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24210"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24211tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24212let Inst{2-2} = 0b0;
24213let Inst{31-21} = 0b01000110100;
24214let isPredicated = 1;
24215let isPredicatedFalse = 1;
24216let addrMode = BaseImmOffset;
24217let accessSize = WordAccess;
24218let isPredicatedNew = 1;
24219let mayStore = 1;
24220let BaseOpcode = "S2_storeri_io";
24221let CextOpcode = "S2_storeri";
24222let InputType = "imm";
24223let isNVStorable = 1;
24224let isExtendable = 1;
24225let opExtendable = 2;
24226let isExtentSigned = 0;
24227let opExtentBits = 8;
24228let opExtentAlign = 2;
24229}
24230def S4_pstorerifnew_rr : HInst<
24231(outs),
24232(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24233"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24234tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24235let Inst{31-21} = 0b00110111100;
24236let isPredicated = 1;
24237let isPredicatedFalse = 1;
24238let addrMode = BaseRegOffset;
24239let accessSize = WordAccess;
24240let isPredicatedNew = 1;
24241let mayStore = 1;
24242let BaseOpcode = "S2_storeri_rr";
24243let CextOpcode = "S2_storeri";
24244let InputType = "reg";
24245let isNVStorable = 1;
24246}
24247def S4_pstorerifnew_zomap : HInst<
24248(outs),
24249(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24250"if (!$Pv4.new) memw($Rs32) = $Rt32",
24251tc_a2b365d2, TypeMAPPING> {
24252let isPseudo = 1;
24253let isCodeGenOnly = 1;
24254}
24255def S4_pstorerinewf_abs : HInst<
24256(outs),
24257(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24258"if (!$Pv4) memw(#$Ii) = $Nt8.new",
24259tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24260let Inst{2-2} = 0b1;
24261let Inst{7-7} = 0b1;
24262let Inst{13-11} = 0b010;
24263let Inst{31-18} = 0b10101111101000;
24264let isPredicated = 1;
24265let isPredicatedFalse = 1;
24266let addrMode = Absolute;
24267let accessSize = WordAccess;
24268let isNVStore = 1;
24269let isNewValue = 1;
24270let isExtended = 1;
24271let isRestrictNoSlot1Store = 1;
24272let mayStore = 1;
24273let BaseOpcode = "S2_storeriabs";
24274let CextOpcode = "S2_storeri";
24275let DecoderNamespace = "MustExtend";
24276let isExtendable = 1;
24277let opExtendable = 1;
24278let isExtentSigned = 0;
24279let opExtentBits = 6;
24280let opExtentAlign = 0;
24281let opNewValue = 2;
24282}
24283def S4_pstorerinewf_rr : HInst<
24284(outs),
24285(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24286"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24287tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24288let Inst{4-3} = 0b10;
24289let Inst{31-21} = 0b00110101101;
24290let isPredicated = 1;
24291let isPredicatedFalse = 1;
24292let addrMode = BaseRegOffset;
24293let accessSize = WordAccess;
24294let isNVStore = 1;
24295let isNewValue = 1;
24296let isRestrictNoSlot1Store = 1;
24297let mayStore = 1;
24298let BaseOpcode = "S2_storeri_rr";
24299let CextOpcode = "S2_storeri";
24300let InputType = "reg";
24301let opNewValue = 4;
24302}
24303def S4_pstorerinewfnew_abs : HInst<
24304(outs),
24305(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24306"if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
24307tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24308let Inst{2-2} = 0b1;
24309let Inst{7-7} = 0b1;
24310let Inst{13-11} = 0b110;
24311let Inst{31-18} = 0b10101111101000;
24312let isPredicated = 1;
24313let isPredicatedFalse = 1;
24314let addrMode = Absolute;
24315let accessSize = WordAccess;
24316let isNVStore = 1;
24317let isPredicatedNew = 1;
24318let isNewValue = 1;
24319let isExtended = 1;
24320let isRestrictNoSlot1Store = 1;
24321let mayStore = 1;
24322let BaseOpcode = "S2_storeriabs";
24323let CextOpcode = "S2_storeri";
24324let DecoderNamespace = "MustExtend";
24325let isExtendable = 1;
24326let opExtendable = 1;
24327let isExtentSigned = 0;
24328let opExtentBits = 6;
24329let opExtentAlign = 0;
24330let opNewValue = 2;
24331}
24332def S4_pstorerinewfnew_io : HInst<
24333(outs),
24334(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24335"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24336tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24337let Inst{2-2} = 0b0;
24338let Inst{12-11} = 0b10;
24339let Inst{31-21} = 0b01000110101;
24340let isPredicated = 1;
24341let isPredicatedFalse = 1;
24342let addrMode = BaseImmOffset;
24343let accessSize = WordAccess;
24344let isNVStore = 1;
24345let isPredicatedNew = 1;
24346let isNewValue = 1;
24347let isRestrictNoSlot1Store = 1;
24348let mayStore = 1;
24349let BaseOpcode = "S2_storeri_io";
24350let CextOpcode = "S2_storeri";
24351let InputType = "imm";
24352let isExtendable = 1;
24353let opExtendable = 2;
24354let isExtentSigned = 0;
24355let opExtentBits = 8;
24356let opExtentAlign = 2;
24357let opNewValue = 3;
24358}
24359def S4_pstorerinewfnew_rr : HInst<
24360(outs),
24361(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24362"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24363tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24364let Inst{4-3} = 0b10;
24365let Inst{31-21} = 0b00110111101;
24366let isPredicated = 1;
24367let isPredicatedFalse = 1;
24368let addrMode = BaseRegOffset;
24369let accessSize = WordAccess;
24370let isNVStore = 1;
24371let isPredicatedNew = 1;
24372let isNewValue = 1;
24373let isRestrictNoSlot1Store = 1;
24374let mayStore = 1;
24375let BaseOpcode = "S2_storeri_rr";
24376let CextOpcode = "S2_storeri";
24377let InputType = "reg";
24378let opNewValue = 4;
24379}
24380def S4_pstorerinewfnew_zomap : HInst<
24381(outs),
24382(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24383"if (!$Pv4.new) memw($Rs32) = $Nt8.new",
24384tc_92240447, TypeMAPPING> {
24385let isPseudo = 1;
24386let isCodeGenOnly = 1;
24387let opNewValue = 2;
24388}
24389def S4_pstorerinewt_abs : HInst<
24390(outs),
24391(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24392"if ($Pv4) memw(#$Ii) = $Nt8.new",
24393tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24394let Inst{2-2} = 0b0;
24395let Inst{7-7} = 0b1;
24396let Inst{13-11} = 0b010;
24397let Inst{31-18} = 0b10101111101000;
24398let isPredicated = 1;
24399let addrMode = Absolute;
24400let accessSize = WordAccess;
24401let isNVStore = 1;
24402let isNewValue = 1;
24403let isExtended = 1;
24404let isRestrictNoSlot1Store = 1;
24405let mayStore = 1;
24406let BaseOpcode = "S2_storeriabs";
24407let CextOpcode = "S2_storeri";
24408let DecoderNamespace = "MustExtend";
24409let isExtendable = 1;
24410let opExtendable = 1;
24411let isExtentSigned = 0;
24412let opExtentBits = 6;
24413let opExtentAlign = 0;
24414let opNewValue = 2;
24415}
24416def S4_pstorerinewt_rr : HInst<
24417(outs),
24418(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24419"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24420tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24421let Inst{4-3} = 0b10;
24422let Inst{31-21} = 0b00110100101;
24423let isPredicated = 1;
24424let addrMode = BaseRegOffset;
24425let accessSize = WordAccess;
24426let isNVStore = 1;
24427let isNewValue = 1;
24428let isRestrictNoSlot1Store = 1;
24429let mayStore = 1;
24430let BaseOpcode = "S2_storeri_rr";
24431let CextOpcode = "S2_storeri";
24432let InputType = "reg";
24433let opNewValue = 4;
24434}
24435def S4_pstorerinewtnew_abs : HInst<
24436(outs),
24437(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24438"if ($Pv4.new) memw(#$Ii) = $Nt8.new",
24439tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24440let Inst{2-2} = 0b0;
24441let Inst{7-7} = 0b1;
24442let Inst{13-11} = 0b110;
24443let Inst{31-18} = 0b10101111101000;
24444let isPredicated = 1;
24445let addrMode = Absolute;
24446let accessSize = WordAccess;
24447let isNVStore = 1;
24448let isPredicatedNew = 1;
24449let isNewValue = 1;
24450let isExtended = 1;
24451let isRestrictNoSlot1Store = 1;
24452let mayStore = 1;
24453let BaseOpcode = "S2_storeriabs";
24454let CextOpcode = "S2_storeri";
24455let DecoderNamespace = "MustExtend";
24456let isExtendable = 1;
24457let opExtendable = 1;
24458let isExtentSigned = 0;
24459let opExtentBits = 6;
24460let opExtentAlign = 0;
24461let opNewValue = 2;
24462}
24463def S4_pstorerinewtnew_io : HInst<
24464(outs),
24465(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24466"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24467tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24468let Inst{2-2} = 0b0;
24469let Inst{12-11} = 0b10;
24470let Inst{31-21} = 0b01000010101;
24471let isPredicated = 1;
24472let addrMode = BaseImmOffset;
24473let accessSize = WordAccess;
24474let isNVStore = 1;
24475let isPredicatedNew = 1;
24476let isNewValue = 1;
24477let isRestrictNoSlot1Store = 1;
24478let mayStore = 1;
24479let BaseOpcode = "S2_storeri_io";
24480let CextOpcode = "S2_storeri";
24481let InputType = "imm";
24482let isExtendable = 1;
24483let opExtendable = 2;
24484let isExtentSigned = 0;
24485let opExtentBits = 8;
24486let opExtentAlign = 2;
24487let opNewValue = 3;
24488}
24489def S4_pstorerinewtnew_rr : HInst<
24490(outs),
24491(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24492"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24493tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24494let Inst{4-3} = 0b10;
24495let Inst{31-21} = 0b00110110101;
24496let isPredicated = 1;
24497let addrMode = BaseRegOffset;
24498let accessSize = WordAccess;
24499let isNVStore = 1;
24500let isPredicatedNew = 1;
24501let isNewValue = 1;
24502let isRestrictNoSlot1Store = 1;
24503let mayStore = 1;
24504let BaseOpcode = "S2_storeri_rr";
24505let CextOpcode = "S2_storeri";
24506let InputType = "reg";
24507let opNewValue = 4;
24508}
24509def S4_pstorerinewtnew_zomap : HInst<
24510(outs),
24511(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24512"if ($Pv4.new) memw($Rs32) = $Nt8.new",
24513tc_92240447, TypeMAPPING> {
24514let isPseudo = 1;
24515let isCodeGenOnly = 1;
24516let opNewValue = 2;
24517}
24518def S4_pstorerit_abs : HInst<
24519(outs),
24520(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24521"if ($Pv4) memw(#$Ii) = $Rt32",
24522tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24523let Inst{2-2} = 0b0;
24524let Inst{7-7} = 0b1;
24525let Inst{13-13} = 0b0;
24526let Inst{31-18} = 0b10101111100000;
24527let isPredicated = 1;
24528let addrMode = Absolute;
24529let accessSize = WordAccess;
24530let isExtended = 1;
24531let mayStore = 1;
24532let BaseOpcode = "S2_storeriabs";
24533let CextOpcode = "S2_storeri";
24534let isNVStorable = 1;
24535let DecoderNamespace = "MustExtend";
24536let isExtendable = 1;
24537let opExtendable = 1;
24538let isExtentSigned = 0;
24539let opExtentBits = 6;
24540let opExtentAlign = 0;
24541}
24542def S4_pstorerit_rr : HInst<
24543(outs),
24544(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24545"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24546tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24547let Inst{31-21} = 0b00110100100;
24548let isPredicated = 1;
24549let addrMode = BaseRegOffset;
24550let accessSize = WordAccess;
24551let mayStore = 1;
24552let BaseOpcode = "S2_storeri_rr";
24553let CextOpcode = "S2_storeri";
24554let InputType = "reg";
24555let isNVStorable = 1;
24556}
24557def S4_pstoreritnew_abs : HInst<
24558(outs),
24559(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24560"if ($Pv4.new) memw(#$Ii) = $Rt32",
24561tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24562let Inst{2-2} = 0b0;
24563let Inst{7-7} = 0b1;
24564let Inst{13-13} = 0b1;
24565let Inst{31-18} = 0b10101111100000;
24566let isPredicated = 1;
24567let addrMode = Absolute;
24568let accessSize = WordAccess;
24569let isPredicatedNew = 1;
24570let isExtended = 1;
24571let mayStore = 1;
24572let BaseOpcode = "S2_storeriabs";
24573let CextOpcode = "S2_storeri";
24574let isNVStorable = 1;
24575let DecoderNamespace = "MustExtend";
24576let isExtendable = 1;
24577let opExtendable = 1;
24578let isExtentSigned = 0;
24579let opExtentBits = 6;
24580let opExtentAlign = 0;
24581}
24582def S4_pstoreritnew_io : HInst<
24583(outs),
24584(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24585"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24586tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24587let Inst{2-2} = 0b0;
24588let Inst{31-21} = 0b01000010100;
24589let isPredicated = 1;
24590let addrMode = BaseImmOffset;
24591let accessSize = WordAccess;
24592let isPredicatedNew = 1;
24593let mayStore = 1;
24594let BaseOpcode = "S2_storeri_io";
24595let CextOpcode = "S2_storeri";
24596let InputType = "imm";
24597let isNVStorable = 1;
24598let isExtendable = 1;
24599let opExtendable = 2;
24600let isExtentSigned = 0;
24601let opExtentBits = 8;
24602let opExtentAlign = 2;
24603}
24604def S4_pstoreritnew_rr : HInst<
24605(outs),
24606(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24607"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24608tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24609let Inst{31-21} = 0b00110110100;
24610let isPredicated = 1;
24611let addrMode = BaseRegOffset;
24612let accessSize = WordAccess;
24613let isPredicatedNew = 1;
24614let mayStore = 1;
24615let BaseOpcode = "S2_storeri_rr";
24616let CextOpcode = "S2_storeri";
24617let InputType = "reg";
24618let isNVStorable = 1;
24619}
24620def S4_pstoreritnew_zomap : HInst<
24621(outs),
24622(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24623"if ($Pv4.new) memw($Rs32) = $Rt32",
24624tc_a2b365d2, TypeMAPPING> {
24625let isPseudo = 1;
24626let isCodeGenOnly = 1;
24627}
24628def S4_stored_locked : HInst<
24629(outs PredRegs:$Pd4),
24630(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24631"memd_locked($Rs32,$Pd4) = $Rtt32",
24632tc_6f42bc60, TypeST>, Enc_d7dc10 {
24633let Inst{7-2} = 0b000000;
24634let Inst{13-13} = 0b0;
24635let Inst{31-21} = 0b10100000111;
24636let accessSize = DoubleWordAccess;
24637let isPredicateLate = 1;
24638let isSoloAX = 1;
24639let mayStore = 1;
24640}
24641def S4_stored_rl_at_vi : HInst<
24642(outs),
24643(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24644"memd_rl($Rs32):at = $Rtt32",
24645tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24646let Inst{7-2} = 0b000010;
24647let Inst{13-13} = 0b0;
24648let Inst{31-21} = 0b10100000111;
24649let accessSize = DoubleWordAccess;
24650let isSolo = 1;
24651let mayStore = 1;
24652}
24653def S4_stored_rl_st_vi : HInst<
24654(outs),
24655(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24656"memd_rl($Rs32):st = $Rtt32",
24657tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24658let Inst{7-2} = 0b001010;
24659let Inst{13-13} = 0b0;
24660let Inst{31-21} = 0b10100000111;
24661let accessSize = DoubleWordAccess;
24662let isSolo = 1;
24663let mayStore = 1;
24664}
24665def S4_storeirb_io : HInst<
24666(outs),
24667(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24668"memb($Rs32+#$Ii) = #$II",
24669tc_7c31e19a, TypeST>, Enc_8203bb, PredNewRel {
24670let Inst{31-21} = 0b00111100000;
24671let addrMode = BaseImmOffset;
24672let accessSize = ByteAccess;
24673let mayStore = 1;
24674let BaseOpcode = "S4_storeirb_io";
24675let CextOpcode = "S2_storerb";
24676let InputType = "imm";
24677let isPredicable = 1;
24678let isExtendable = 1;
24679let opExtendable = 2;
24680let isExtentSigned = 1;
24681let opExtentBits = 8;
24682let opExtentAlign = 0;
24683}
24684def S4_storeirb_zomap : HInst<
24685(outs),
24686(ins IntRegs:$Rs32, s8_0Imm:$II),
24687"memb($Rs32) = #$II",
24688tc_7c31e19a, TypeMAPPING> {
24689let isPseudo = 1;
24690let isCodeGenOnly = 1;
24691}
24692def S4_storeirbf_io : HInst<
24693(outs),
24694(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24695"if (!$Pv4) memb($Rs32+#$Ii) = #$II",
24696tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24697let Inst{31-21} = 0b00111000100;
24698let isPredicated = 1;
24699let isPredicatedFalse = 1;
24700let addrMode = BaseImmOffset;
24701let accessSize = ByteAccess;
24702let mayStore = 1;
24703let BaseOpcode = "S4_storeirb_io";
24704let CextOpcode = "S2_storerb";
24705let InputType = "imm";
24706let isExtendable = 1;
24707let opExtendable = 3;
24708let isExtentSigned = 1;
24709let opExtentBits = 6;
24710let opExtentAlign = 0;
24711}
24712def S4_storeirbf_zomap : HInst<
24713(outs),
24714(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24715"if (!$Pv4) memb($Rs32) = #$II",
24716tc_d03278fd, TypeMAPPING> {
24717let isPseudo = 1;
24718let isCodeGenOnly = 1;
24719}
24720def S4_storeirbfnew_io : HInst<
24721(outs),
24722(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24723"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
24724tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24725let Inst{31-21} = 0b00111001100;
24726let isPredicated = 1;
24727let isPredicatedFalse = 1;
24728let addrMode = BaseImmOffset;
24729let accessSize = ByteAccess;
24730let isPredicatedNew = 1;
24731let mayStore = 1;
24732let BaseOpcode = "S4_storeirb_io";
24733let CextOpcode = "S2_storerb";
24734let InputType = "imm";
24735let isExtendable = 1;
24736let opExtendable = 3;
24737let isExtentSigned = 1;
24738let opExtentBits = 6;
24739let opExtentAlign = 0;
24740}
24741def S4_storeirbfnew_zomap : HInst<
24742(outs),
24743(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24744"if (!$Pv4.new) memb($Rs32) = #$II",
24745tc_65cbd974, TypeMAPPING> {
24746let isPseudo = 1;
24747let isCodeGenOnly = 1;
24748}
24749def S4_storeirbt_io : HInst<
24750(outs),
24751(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24752"if ($Pv4) memb($Rs32+#$Ii) = #$II",
24753tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24754let Inst{31-21} = 0b00111000000;
24755let isPredicated = 1;
24756let addrMode = BaseImmOffset;
24757let accessSize = ByteAccess;
24758let mayStore = 1;
24759let BaseOpcode = "S4_storeirb_io";
24760let CextOpcode = "S2_storerb";
24761let InputType = "imm";
24762let isExtendable = 1;
24763let opExtendable = 3;
24764let isExtentSigned = 1;
24765let opExtentBits = 6;
24766let opExtentAlign = 0;
24767}
24768def S4_storeirbt_zomap : HInst<
24769(outs),
24770(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24771"if ($Pv4) memb($Rs32) = #$II",
24772tc_d03278fd, TypeMAPPING> {
24773let isPseudo = 1;
24774let isCodeGenOnly = 1;
24775}
24776def S4_storeirbtnew_io : HInst<
24777(outs),
24778(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24779"if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
24780tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24781let Inst{31-21} = 0b00111001000;
24782let isPredicated = 1;
24783let addrMode = BaseImmOffset;
24784let accessSize = ByteAccess;
24785let isPredicatedNew = 1;
24786let mayStore = 1;
24787let BaseOpcode = "S4_storeirb_io";
24788let CextOpcode = "S2_storerb";
24789let InputType = "imm";
24790let isExtendable = 1;
24791let opExtendable = 3;
24792let isExtentSigned = 1;
24793let opExtentBits = 6;
24794let opExtentAlign = 0;
24795}
24796def S4_storeirbtnew_zomap : HInst<
24797(outs),
24798(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24799"if ($Pv4.new) memb($Rs32) = #$II",
24800tc_65cbd974, TypeMAPPING> {
24801let isPseudo = 1;
24802let isCodeGenOnly = 1;
24803}
24804def S4_storeirh_io : HInst<
24805(outs),
24806(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24807"memh($Rs32+#$Ii) = #$II",
24808tc_7c31e19a, TypeST>, Enc_a803e0, PredNewRel {
24809let Inst{31-21} = 0b00111100001;
24810let addrMode = BaseImmOffset;
24811let accessSize = HalfWordAccess;
24812let mayStore = 1;
24813let BaseOpcode = "S4_storeirh_io";
24814let CextOpcode = "S2_storerh";
24815let InputType = "imm";
24816let isPredicable = 1;
24817let isExtendable = 1;
24818let opExtendable = 2;
24819let isExtentSigned = 1;
24820let opExtentBits = 8;
24821let opExtentAlign = 0;
24822}
24823def S4_storeirh_zomap : HInst<
24824(outs),
24825(ins IntRegs:$Rs32, s8_0Imm:$II),
24826"memh($Rs32) = #$II",
24827tc_7c31e19a, TypeMAPPING> {
24828let isPseudo = 1;
24829let isCodeGenOnly = 1;
24830}
24831def S4_storeirhf_io : HInst<
24832(outs),
24833(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24834"if (!$Pv4) memh($Rs32+#$Ii) = #$II",
24835tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24836let Inst{31-21} = 0b00111000101;
24837let isPredicated = 1;
24838let isPredicatedFalse = 1;
24839let addrMode = BaseImmOffset;
24840let accessSize = HalfWordAccess;
24841let mayStore = 1;
24842let BaseOpcode = "S4_storeirh_io";
24843let CextOpcode = "S2_storerh";
24844let InputType = "imm";
24845let isExtendable = 1;
24846let opExtendable = 3;
24847let isExtentSigned = 1;
24848let opExtentBits = 6;
24849let opExtentAlign = 0;
24850}
24851def S4_storeirhf_zomap : HInst<
24852(outs),
24853(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24854"if (!$Pv4) memh($Rs32) = #$II",
24855tc_d03278fd, TypeMAPPING> {
24856let isPseudo = 1;
24857let isCodeGenOnly = 1;
24858}
24859def S4_storeirhfnew_io : HInst<
24860(outs),
24861(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24862"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
24863tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24864let Inst{31-21} = 0b00111001101;
24865let isPredicated = 1;
24866let isPredicatedFalse = 1;
24867let addrMode = BaseImmOffset;
24868let accessSize = HalfWordAccess;
24869let isPredicatedNew = 1;
24870let mayStore = 1;
24871let BaseOpcode = "S4_storeirh_io";
24872let CextOpcode = "S2_storerh";
24873let InputType = "imm";
24874let isExtendable = 1;
24875let opExtendable = 3;
24876let isExtentSigned = 1;
24877let opExtentBits = 6;
24878let opExtentAlign = 0;
24879}
24880def S4_storeirhfnew_zomap : HInst<
24881(outs),
24882(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24883"if (!$Pv4.new) memh($Rs32) = #$II",
24884tc_65cbd974, TypeMAPPING> {
24885let isPseudo = 1;
24886let isCodeGenOnly = 1;
24887}
24888def S4_storeirht_io : HInst<
24889(outs),
24890(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24891"if ($Pv4) memh($Rs32+#$Ii) = #$II",
24892tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24893let Inst{31-21} = 0b00111000001;
24894let isPredicated = 1;
24895let addrMode = BaseImmOffset;
24896let accessSize = HalfWordAccess;
24897let mayStore = 1;
24898let BaseOpcode = "S4_storeirh_io";
24899let CextOpcode = "S2_storerh";
24900let InputType = "imm";
24901let isExtendable = 1;
24902let opExtendable = 3;
24903let isExtentSigned = 1;
24904let opExtentBits = 6;
24905let opExtentAlign = 0;
24906}
24907def S4_storeirht_zomap : HInst<
24908(outs),
24909(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24910"if ($Pv4) memh($Rs32) = #$II",
24911tc_d03278fd, TypeMAPPING> {
24912let isPseudo = 1;
24913let isCodeGenOnly = 1;
24914}
24915def S4_storeirhtnew_io : HInst<
24916(outs),
24917(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24918"if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
24919tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24920let Inst{31-21} = 0b00111001001;
24921let isPredicated = 1;
24922let addrMode = BaseImmOffset;
24923let accessSize = HalfWordAccess;
24924let isPredicatedNew = 1;
24925let mayStore = 1;
24926let BaseOpcode = "S4_storeirh_io";
24927let CextOpcode = "S2_storerh";
24928let InputType = "imm";
24929let isExtendable = 1;
24930let opExtendable = 3;
24931let isExtentSigned = 1;
24932let opExtentBits = 6;
24933let opExtentAlign = 0;
24934}
24935def S4_storeirhtnew_zomap : HInst<
24936(outs),
24937(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24938"if ($Pv4.new) memh($Rs32) = #$II",
24939tc_65cbd974, TypeMAPPING> {
24940let isPseudo = 1;
24941let isCodeGenOnly = 1;
24942}
24943def S4_storeiri_io : HInst<
24944(outs),
24945(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24946"memw($Rs32+#$Ii) = #$II",
24947tc_7c31e19a, TypeST>, Enc_f37377, PredNewRel {
24948let Inst{31-21} = 0b00111100010;
24949let addrMode = BaseImmOffset;
24950let accessSize = WordAccess;
24951let mayStore = 1;
24952let BaseOpcode = "S4_storeiri_io";
24953let CextOpcode = "S2_storeri";
24954let InputType = "imm";
24955let isPredicable = 1;
24956let isExtendable = 1;
24957let opExtendable = 2;
24958let isExtentSigned = 1;
24959let opExtentBits = 8;
24960let opExtentAlign = 0;
24961}
24962def S4_storeiri_zomap : HInst<
24963(outs),
24964(ins IntRegs:$Rs32, s8_0Imm:$II),
24965"memw($Rs32) = #$II",
24966tc_7c31e19a, TypeMAPPING> {
24967let isPseudo = 1;
24968let isCodeGenOnly = 1;
24969}
24970def S4_storeirif_io : HInst<
24971(outs),
24972(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24973"if (!$Pv4) memw($Rs32+#$Ii) = #$II",
24974tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24975let Inst{31-21} = 0b00111000110;
24976let isPredicated = 1;
24977let isPredicatedFalse = 1;
24978let addrMode = BaseImmOffset;
24979let accessSize = WordAccess;
24980let mayStore = 1;
24981let BaseOpcode = "S4_storeiri_io";
24982let CextOpcode = "S2_storeri";
24983let InputType = "imm";
24984let isExtendable = 1;
24985let opExtendable = 3;
24986let isExtentSigned = 1;
24987let opExtentBits = 6;
24988let opExtentAlign = 0;
24989}
24990def S4_storeirif_zomap : HInst<
24991(outs),
24992(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24993"if (!$Pv4) memw($Rs32) = #$II",
24994tc_d03278fd, TypeMAPPING> {
24995let isPseudo = 1;
24996let isCodeGenOnly = 1;
24997}
24998def S4_storeirifnew_io : HInst<
24999(outs),
25000(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
25001"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
25002tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
25003let Inst{31-21} = 0b00111001110;
25004let isPredicated = 1;
25005let isPredicatedFalse = 1;
25006let addrMode = BaseImmOffset;
25007let accessSize = WordAccess;
25008let isPredicatedNew = 1;
25009let mayStore = 1;
25010let BaseOpcode = "S4_storeiri_io";
25011let CextOpcode = "S2_storeri";
25012let InputType = "imm";
25013let isExtendable = 1;
25014let opExtendable = 3;
25015let isExtentSigned = 1;
25016let opExtentBits = 6;
25017let opExtentAlign = 0;
25018}
25019def S4_storeirifnew_zomap : HInst<
25020(outs),
25021(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
25022"if (!$Pv4.new) memw($Rs32) = #$II",
25023tc_65cbd974, TypeMAPPING> {
25024let isPseudo = 1;
25025let isCodeGenOnly = 1;
25026}
25027def S4_storeirit_io : HInst<
25028(outs),
25029(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
25030"if ($Pv4) memw($Rs32+#$Ii) = #$II",
25031tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
25032let Inst{31-21} = 0b00111000010;
25033let isPredicated = 1;
25034let addrMode = BaseImmOffset;
25035let accessSize = WordAccess;
25036let mayStore = 1;
25037let BaseOpcode = "S4_storeiri_io";
25038let CextOpcode = "S2_storeri";
25039let InputType = "imm";
25040let isExtendable = 1;
25041let opExtendable = 3;
25042let isExtentSigned = 1;
25043let opExtentBits = 6;
25044let opExtentAlign = 0;
25045}
25046def S4_storeirit_zomap : HInst<
25047(outs),
25048(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
25049"if ($Pv4) memw($Rs32) = #$II",
25050tc_d03278fd, TypeMAPPING> {
25051let isPseudo = 1;
25052let isCodeGenOnly = 1;
25053}
25054def S4_storeiritnew_io : HInst<
25055(outs),
25056(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
25057"if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
25058tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
25059let Inst{31-21} = 0b00111001010;
25060let isPredicated = 1;
25061let addrMode = BaseImmOffset;
25062let accessSize = WordAccess;
25063let isPredicatedNew = 1;
25064let mayStore = 1;
25065let BaseOpcode = "S4_storeiri_io";
25066let CextOpcode = "S2_storeri";
25067let InputType = "imm";
25068let isExtendable = 1;
25069let opExtendable = 3;
25070let isExtentSigned = 1;
25071let opExtentBits = 6;
25072let opExtentAlign = 0;
25073}
25074def S4_storeiritnew_zomap : HInst<
25075(outs),
25076(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
25077"if ($Pv4.new) memw($Rs32) = #$II",
25078tc_65cbd974, TypeMAPPING> {
25079let isPseudo = 1;
25080let isCodeGenOnly = 1;
25081}
25082def S4_storerb_ap : HInst<
25083(outs IntRegs:$Re32),
25084(ins u32_0Imm:$II, IntRegs:$Rt32),
25085"memb($Re32=#$II) = $Rt32",
25086tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25087let Inst{7-6} = 0b10;
25088let Inst{13-13} = 0b0;
25089let Inst{31-21} = 0b10101011000;
25090let addrMode = AbsoluteSet;
25091let accessSize = ByteAccess;
25092let isExtended = 1;
25093let mayStore = 1;
25094let BaseOpcode = "S2_storerb_ap";
25095let isNVStorable = 1;
25096let DecoderNamespace = "MustExtend";
25097let isExtendable = 1;
25098let opExtendable = 1;
25099let isExtentSigned = 0;
25100let opExtentBits = 6;
25101let opExtentAlign = 0;
25102}
25103def S4_storerb_rr : HInst<
25104(outs),
25105(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25106"memb($Rs32+$Ru32<<#$Ii) = $Rt32",
25107tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25108let Inst{6-5} = 0b00;
25109let Inst{31-21} = 0b00111011000;
25110let addrMode = BaseRegOffset;
25111let accessSize = ByteAccess;
25112let mayStore = 1;
25113let BaseOpcode = "S4_storerb_rr";
25114let CextOpcode = "S2_storerb";
25115let InputType = "reg";
25116let isNVStorable = 1;
25117let isPredicable = 1;
25118}
25119def S4_storerb_ur : HInst<
25120(outs),
25121(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25122"memb($Ru32<<#$Ii+#$II) = $Rt32",
25123tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25124let Inst{7-7} = 0b1;
25125let Inst{31-21} = 0b10101101000;
25126let addrMode = BaseLongOffset;
25127let accessSize = ByteAccess;
25128let isExtended = 1;
25129let mayStore = 1;
25130let BaseOpcode = "S4_storerb_ur";
25131let CextOpcode = "S2_storerb";
25132let InputType = "imm";
25133let isNVStorable = 1;
25134let DecoderNamespace = "MustExtend";
25135let isExtendable = 1;
25136let opExtendable = 2;
25137let isExtentSigned = 0;
25138let opExtentBits = 6;
25139let opExtentAlign = 0;
25140}
25141def S4_storerbnew_ap : HInst<
25142(outs IntRegs:$Re32),
25143(ins u32_0Imm:$II, IntRegs:$Nt8),
25144"memb($Re32=#$II) = $Nt8.new",
25145tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25146let Inst{7-6} = 0b10;
25147let Inst{13-11} = 0b000;
25148let Inst{31-21} = 0b10101011101;
25149let addrMode = AbsoluteSet;
25150let accessSize = ByteAccess;
25151let isNVStore = 1;
25152let isNewValue = 1;
25153let isExtended = 1;
25154let isRestrictNoSlot1Store = 1;
25155let mayStore = 1;
25156let BaseOpcode = "S2_storerb_ap";
25157let DecoderNamespace = "MustExtend";
25158let isExtendable = 1;
25159let opExtendable = 1;
25160let isExtentSigned = 0;
25161let opExtentBits = 6;
25162let opExtentAlign = 0;
25163let opNewValue = 2;
25164}
25165def S4_storerbnew_rr : HInst<
25166(outs),
25167(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25168"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25169tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25170let Inst{6-3} = 0b0000;
25171let Inst{31-21} = 0b00111011101;
25172let addrMode = BaseRegOffset;
25173let accessSize = ByteAccess;
25174let isNVStore = 1;
25175let isNewValue = 1;
25176let isRestrictNoSlot1Store = 1;
25177let mayStore = 1;
25178let BaseOpcode = "S4_storerb_rr";
25179let CextOpcode = "S2_storerb";
25180let InputType = "reg";
25181let isPredicable = 1;
25182let opNewValue = 3;
25183}
25184def S4_storerbnew_ur : HInst<
25185(outs),
25186(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25187"memb($Ru32<<#$Ii+#$II) = $Nt8.new",
25188tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25189let Inst{7-7} = 0b1;
25190let Inst{12-11} = 0b00;
25191let Inst{31-21} = 0b10101101101;
25192let addrMode = BaseLongOffset;
25193let accessSize = ByteAccess;
25194let isNVStore = 1;
25195let isNewValue = 1;
25196let isExtended = 1;
25197let isRestrictNoSlot1Store = 1;
25198let mayStore = 1;
25199let BaseOpcode = "S4_storerb_ur";
25200let CextOpcode = "S2_storerb";
25201let DecoderNamespace = "MustExtend";
25202let isExtendable = 1;
25203let opExtendable = 2;
25204let isExtentSigned = 0;
25205let opExtentBits = 6;
25206let opExtentAlign = 0;
25207let opNewValue = 3;
25208}
25209def S4_storerd_ap : HInst<
25210(outs IntRegs:$Re32),
25211(ins u32_0Imm:$II, DoubleRegs:$Rtt32),
25212"memd($Re32=#$II) = $Rtt32",
25213tc_bb07f2c5, TypeST>, Enc_c7a204 {
25214let Inst{7-6} = 0b10;
25215let Inst{13-13} = 0b0;
25216let Inst{31-21} = 0b10101011110;
25217let addrMode = AbsoluteSet;
25218let accessSize = DoubleWordAccess;
25219let isExtended = 1;
25220let mayStore = 1;
25221let BaseOpcode = "S4_storerd_ap";
25222let DecoderNamespace = "MustExtend";
25223let isExtendable = 1;
25224let opExtendable = 1;
25225let isExtentSigned = 0;
25226let opExtentBits = 6;
25227let opExtentAlign = 0;
25228}
25229def S4_storerd_rr : HInst<
25230(outs),
25231(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
25232"memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
25233tc_280f7fe1, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
25234let Inst{6-5} = 0b00;
25235let Inst{31-21} = 0b00111011110;
25236let addrMode = BaseRegOffset;
25237let accessSize = DoubleWordAccess;
25238let mayStore = 1;
25239let BaseOpcode = "S2_storerd_rr";
25240let CextOpcode = "S2_storerd";
25241let InputType = "reg";
25242let isPredicable = 1;
25243}
25244def S4_storerd_ur : HInst<
25245(outs),
25246(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
25247"memd($Ru32<<#$Ii+#$II) = $Rtt32",
25248tc_887d1bb7, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
25249let Inst{7-7} = 0b1;
25250let Inst{31-21} = 0b10101101110;
25251let addrMode = BaseLongOffset;
25252let accessSize = DoubleWordAccess;
25253let isExtended = 1;
25254let mayStore = 1;
25255let BaseOpcode = "S2_storerd_ur";
25256let CextOpcode = "S2_storerd";
25257let InputType = "imm";
25258let DecoderNamespace = "MustExtend";
25259let isExtendable = 1;
25260let opExtendable = 2;
25261let isExtentSigned = 0;
25262let opExtentBits = 6;
25263let opExtentAlign = 0;
25264}
25265def S4_storerf_ap : HInst<
25266(outs IntRegs:$Re32),
25267(ins u32_0Imm:$II, IntRegs:$Rt32),
25268"memh($Re32=#$II) = $Rt32.h",
25269tc_bb07f2c5, TypeST>, Enc_8bcba4 {
25270let Inst{7-6} = 0b10;
25271let Inst{13-13} = 0b0;
25272let Inst{31-21} = 0b10101011011;
25273let addrMode = AbsoluteSet;
25274let accessSize = HalfWordAccess;
25275let isExtended = 1;
25276let mayStore = 1;
25277let BaseOpcode = "S4_storerf_ap";
25278let DecoderNamespace = "MustExtend";
25279let isExtendable = 1;
25280let opExtendable = 1;
25281let isExtentSigned = 0;
25282let opExtentBits = 6;
25283let opExtentAlign = 0;
25284}
25285def S4_storerf_rr : HInst<
25286(outs),
25287(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25288"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
25289tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25290let Inst{6-5} = 0b00;
25291let Inst{31-21} = 0b00111011011;
25292let addrMode = BaseRegOffset;
25293let accessSize = HalfWordAccess;
25294let mayStore = 1;
25295let BaseOpcode = "S4_storerf_rr";
25296let CextOpcode = "S2_storerf";
25297let InputType = "reg";
25298let isPredicable = 1;
25299}
25300def S4_storerf_ur : HInst<
25301(outs),
25302(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25303"memh($Ru32<<#$Ii+#$II) = $Rt32.h",
25304tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25305let Inst{7-7} = 0b1;
25306let Inst{31-21} = 0b10101101011;
25307let addrMode = BaseLongOffset;
25308let accessSize = HalfWordAccess;
25309let isExtended = 1;
25310let mayStore = 1;
25311let BaseOpcode = "S4_storerf_rr";
25312let CextOpcode = "S2_storerf";
25313let InputType = "imm";
25314let DecoderNamespace = "MustExtend";
25315let isExtendable = 1;
25316let opExtendable = 2;
25317let isExtentSigned = 0;
25318let opExtentBits = 6;
25319let opExtentAlign = 0;
25320}
25321def S4_storerh_ap : HInst<
25322(outs IntRegs:$Re32),
25323(ins u32_0Imm:$II, IntRegs:$Rt32),
25324"memh($Re32=#$II) = $Rt32",
25325tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25326let Inst{7-6} = 0b10;
25327let Inst{13-13} = 0b0;
25328let Inst{31-21} = 0b10101011010;
25329let addrMode = AbsoluteSet;
25330let accessSize = HalfWordAccess;
25331let isExtended = 1;
25332let mayStore = 1;
25333let BaseOpcode = "S2_storerh_ap";
25334let isNVStorable = 1;
25335let DecoderNamespace = "MustExtend";
25336let isExtendable = 1;
25337let opExtendable = 1;
25338let isExtentSigned = 0;
25339let opExtentBits = 6;
25340let opExtentAlign = 0;
25341}
25342def S4_storerh_rr : HInst<
25343(outs),
25344(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25345"memh($Rs32+$Ru32<<#$Ii) = $Rt32",
25346tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25347let Inst{6-5} = 0b00;
25348let Inst{31-21} = 0b00111011010;
25349let addrMode = BaseRegOffset;
25350let accessSize = HalfWordAccess;
25351let mayStore = 1;
25352let BaseOpcode = "S2_storerh_rr";
25353let CextOpcode = "S2_storerh";
25354let InputType = "reg";
25355let isNVStorable = 1;
25356let isPredicable = 1;
25357}
25358def S4_storerh_ur : HInst<
25359(outs),
25360(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25361"memh($Ru32<<#$Ii+#$II) = $Rt32",
25362tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25363let Inst{7-7} = 0b1;
25364let Inst{31-21} = 0b10101101010;
25365let addrMode = BaseLongOffset;
25366let accessSize = HalfWordAccess;
25367let isExtended = 1;
25368let mayStore = 1;
25369let BaseOpcode = "S2_storerh_ur";
25370let CextOpcode = "S2_storerh";
25371let InputType = "imm";
25372let isNVStorable = 1;
25373let DecoderNamespace = "MustExtend";
25374let isExtendable = 1;
25375let opExtendable = 2;
25376let isExtentSigned = 0;
25377let opExtentBits = 6;
25378let opExtentAlign = 0;
25379}
25380def S4_storerhnew_ap : HInst<
25381(outs IntRegs:$Re32),
25382(ins u32_0Imm:$II, IntRegs:$Nt8),
25383"memh($Re32=#$II) = $Nt8.new",
25384tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25385let Inst{7-6} = 0b10;
25386let Inst{13-11} = 0b001;
25387let Inst{31-21} = 0b10101011101;
25388let addrMode = AbsoluteSet;
25389let accessSize = HalfWordAccess;
25390let isNVStore = 1;
25391let isNewValue = 1;
25392let isExtended = 1;
25393let isRestrictNoSlot1Store = 1;
25394let mayStore = 1;
25395let BaseOpcode = "S2_storerh_ap";
25396let DecoderNamespace = "MustExtend";
25397let isExtendable = 1;
25398let opExtendable = 1;
25399let isExtentSigned = 0;
25400let opExtentBits = 6;
25401let opExtentAlign = 0;
25402let opNewValue = 2;
25403}
25404def S4_storerhnew_rr : HInst<
25405(outs),
25406(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25407"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25408tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25409let Inst{6-3} = 0b0001;
25410let Inst{31-21} = 0b00111011101;
25411let addrMode = BaseRegOffset;
25412let accessSize = HalfWordAccess;
25413let isNVStore = 1;
25414let isNewValue = 1;
25415let isRestrictNoSlot1Store = 1;
25416let mayStore = 1;
25417let BaseOpcode = "S2_storerh_rr";
25418let CextOpcode = "S2_storerh";
25419let InputType = "reg";
25420let isPredicable = 1;
25421let opNewValue = 3;
25422}
25423def S4_storerhnew_ur : HInst<
25424(outs),
25425(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25426"memh($Ru32<<#$Ii+#$II) = $Nt8.new",
25427tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25428let Inst{7-7} = 0b1;
25429let Inst{12-11} = 0b01;
25430let Inst{31-21} = 0b10101101101;
25431let addrMode = BaseLongOffset;
25432let accessSize = HalfWordAccess;
25433let isNVStore = 1;
25434let isNewValue = 1;
25435let isExtended = 1;
25436let isRestrictNoSlot1Store = 1;
25437let mayStore = 1;
25438let BaseOpcode = "S2_storerh_ur";
25439let CextOpcode = "S2_storerh";
25440let DecoderNamespace = "MustExtend";
25441let isExtendable = 1;
25442let opExtendable = 2;
25443let isExtentSigned = 0;
25444let opExtentBits = 6;
25445let opExtentAlign = 0;
25446let opNewValue = 3;
25447}
25448def S4_storeri_ap : HInst<
25449(outs IntRegs:$Re32),
25450(ins u32_0Imm:$II, IntRegs:$Rt32),
25451"memw($Re32=#$II) = $Rt32",
25452tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25453let Inst{7-6} = 0b10;
25454let Inst{13-13} = 0b0;
25455let Inst{31-21} = 0b10101011100;
25456let addrMode = AbsoluteSet;
25457let accessSize = WordAccess;
25458let isExtended = 1;
25459let mayStore = 1;
25460let BaseOpcode = "S2_storeri_ap";
25461let isNVStorable = 1;
25462let DecoderNamespace = "MustExtend";
25463let isExtendable = 1;
25464let opExtendable = 1;
25465let isExtentSigned = 0;
25466let opExtentBits = 6;
25467let opExtentAlign = 0;
25468}
25469def S4_storeri_rr : HInst<
25470(outs),
25471(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25472"memw($Rs32+$Ru32<<#$Ii) = $Rt32",
25473tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25474let Inst{6-5} = 0b00;
25475let Inst{31-21} = 0b00111011100;
25476let addrMode = BaseRegOffset;
25477let accessSize = WordAccess;
25478let mayStore = 1;
25479let BaseOpcode = "S2_storeri_rr";
25480let CextOpcode = "S2_storeri";
25481let InputType = "reg";
25482let isNVStorable = 1;
25483let isPredicable = 1;
25484}
25485def S4_storeri_ur : HInst<
25486(outs),
25487(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25488"memw($Ru32<<#$Ii+#$II) = $Rt32",
25489tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25490let Inst{7-7} = 0b1;
25491let Inst{31-21} = 0b10101101100;
25492let addrMode = BaseLongOffset;
25493let accessSize = WordAccess;
25494let isExtended = 1;
25495let mayStore = 1;
25496let BaseOpcode = "S2_storeri_ur";
25497let CextOpcode = "S2_storeri";
25498let InputType = "imm";
25499let isNVStorable = 1;
25500let DecoderNamespace = "MustExtend";
25501let isExtendable = 1;
25502let opExtendable = 2;
25503let isExtentSigned = 0;
25504let opExtentBits = 6;
25505let opExtentAlign = 0;
25506}
25507def S4_storerinew_ap : HInst<
25508(outs IntRegs:$Re32),
25509(ins u32_0Imm:$II, IntRegs:$Nt8),
25510"memw($Re32=#$II) = $Nt8.new",
25511tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25512let Inst{7-6} = 0b10;
25513let Inst{13-11} = 0b010;
25514let Inst{31-21} = 0b10101011101;
25515let addrMode = AbsoluteSet;
25516let accessSize = WordAccess;
25517let isNVStore = 1;
25518let isNewValue = 1;
25519let isExtended = 1;
25520let isRestrictNoSlot1Store = 1;
25521let mayStore = 1;
25522let BaseOpcode = "S2_storeri_ap";
25523let DecoderNamespace = "MustExtend";
25524let isExtendable = 1;
25525let opExtendable = 1;
25526let isExtentSigned = 0;
25527let opExtentBits = 6;
25528let opExtentAlign = 0;
25529let opNewValue = 2;
25530}
25531def S4_storerinew_rr : HInst<
25532(outs),
25533(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25534"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25535tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25536let Inst{6-3} = 0b0010;
25537let Inst{31-21} = 0b00111011101;
25538let addrMode = BaseRegOffset;
25539let accessSize = WordAccess;
25540let isNVStore = 1;
25541let isNewValue = 1;
25542let isRestrictNoSlot1Store = 1;
25543let mayStore = 1;
25544let BaseOpcode = "S2_storeri_rr";
25545let CextOpcode = "S2_storeri";
25546let InputType = "reg";
25547let isPredicable = 1;
25548let opNewValue = 3;
25549}
25550def S4_storerinew_ur : HInst<
25551(outs),
25552(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25553"memw($Ru32<<#$Ii+#$II) = $Nt8.new",
25554tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25555let Inst{7-7} = 0b1;
25556let Inst{12-11} = 0b10;
25557let Inst{31-21} = 0b10101101101;
25558let addrMode = BaseLongOffset;
25559let accessSize = WordAccess;
25560let isNVStore = 1;
25561let isNewValue = 1;
25562let isExtended = 1;
25563let isRestrictNoSlot1Store = 1;
25564let mayStore = 1;
25565let BaseOpcode = "S2_storeri_ur";
25566let CextOpcode = "S2_storeri";
25567let DecoderNamespace = "MustExtend";
25568let isExtendable = 1;
25569let opExtendable = 2;
25570let isExtentSigned = 0;
25571let opExtentBits = 6;
25572let opExtentAlign = 0;
25573let opNewValue = 3;
25574}
25575def S4_subaddi : HInst<
25576(outs IntRegs:$Rd32),
25577(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
25578"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
25579tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
25580let Inst{31-23} = 0b110110111;
25581let hasNewValue = 1;
25582let opNewValue = 0;
25583let prefersSlot3 = 1;
25584let isExtendable = 1;
25585let opExtendable = 2;
25586let isExtentSigned = 1;
25587let opExtentBits = 6;
25588let opExtentAlign = 0;
25589}
25590def S4_subi_asl_ri : HInst<
25591(outs IntRegs:$Rx32),
25592(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25593"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
25594tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25595let Inst{2-0} = 0b110;
25596let Inst{4-4} = 0b0;
25597let Inst{31-24} = 0b11011110;
25598let hasNewValue = 1;
25599let opNewValue = 0;
25600let prefersSlot3 = 1;
25601let isExtendable = 1;
25602let opExtendable = 1;
25603let isExtentSigned = 0;
25604let opExtentBits = 8;
25605let opExtentAlign = 0;
25606let Constraints = "$Rx32 = $Rx32in";
25607}
25608def S4_subi_lsr_ri : HInst<
25609(outs IntRegs:$Rx32),
25610(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25611"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
25612tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25613let Inst{2-0} = 0b110;
25614let Inst{4-4} = 0b1;
25615let Inst{31-24} = 0b11011110;
25616let hasNewValue = 1;
25617let opNewValue = 0;
25618let prefersSlot3 = 1;
25619let isExtendable = 1;
25620let opExtendable = 1;
25621let isExtentSigned = 0;
25622let opExtentBits = 8;
25623let opExtentAlign = 0;
25624let Constraints = "$Rx32 = $Rx32in";
25625}
25626def S4_vrcrotate : HInst<
25627(outs DoubleRegs:$Rdd32),
25628(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25629"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
25630tc_f0cdeccf, TypeS_3op>, Enc_645d54 {
25631let Inst{7-6} = 0b11;
25632let Inst{31-21} = 0b11000011110;
25633let prefersSlot3 = 1;
25634}
25635def S4_vrcrotate_acc : HInst<
25636(outs DoubleRegs:$Rxx32),
25637(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25638"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
25639tc_a38c45dc, TypeS_3op>, Enc_b72622 {
25640let Inst{7-6} = 0b00;
25641let Inst{31-21} = 0b11001011101;
25642let prefersSlot3 = 1;
25643let Constraints = "$Rxx32 = $Rxx32in";
25644}
25645def S4_vxaddsubh : HInst<
25646(outs DoubleRegs:$Rdd32),
25647(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25648"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
25649tc_8a825db2, TypeS_3op>, Enc_a56825 {
25650let Inst{7-5} = 0b100;
25651let Inst{13-13} = 0b0;
25652let Inst{31-21} = 0b11000001010;
25653let prefersSlot3 = 1;
25654let Defs = [USR_OVF];
25655}
25656def S4_vxaddsubhr : HInst<
25657(outs DoubleRegs:$Rdd32),
25658(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25659"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
25660tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25661let Inst{7-5} = 0b000;
25662let Inst{13-13} = 0b0;
25663let Inst{31-21} = 0b11000001110;
25664let prefersSlot3 = 1;
25665let Defs = [USR_OVF];
25666}
25667def S4_vxaddsubw : HInst<
25668(outs DoubleRegs:$Rdd32),
25669(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25670"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
25671tc_8a825db2, TypeS_3op>, Enc_a56825 {
25672let Inst{7-5} = 0b000;
25673let Inst{13-13} = 0b0;
25674let Inst{31-21} = 0b11000001010;
25675let prefersSlot3 = 1;
25676let Defs = [USR_OVF];
25677}
25678def S4_vxsubaddh : HInst<
25679(outs DoubleRegs:$Rdd32),
25680(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25681"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
25682tc_8a825db2, TypeS_3op>, Enc_a56825 {
25683let Inst{7-5} = 0b110;
25684let Inst{13-13} = 0b0;
25685let Inst{31-21} = 0b11000001010;
25686let prefersSlot3 = 1;
25687let Defs = [USR_OVF];
25688}
25689def S4_vxsubaddhr : HInst<
25690(outs DoubleRegs:$Rdd32),
25691(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25692"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
25693tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25694let Inst{7-5} = 0b010;
25695let Inst{13-13} = 0b0;
25696let Inst{31-21} = 0b11000001110;
25697let prefersSlot3 = 1;
25698let Defs = [USR_OVF];
25699}
25700def S4_vxsubaddw : HInst<
25701(outs DoubleRegs:$Rdd32),
25702(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25703"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
25704tc_8a825db2, TypeS_3op>, Enc_a56825 {
25705let Inst{7-5} = 0b010;
25706let Inst{13-13} = 0b0;
25707let Inst{31-21} = 0b11000001010;
25708let prefersSlot3 = 1;
25709let Defs = [USR_OVF];
25710}
25711def S5_asrhub_rnd_sat : HInst<
25712(outs IntRegs:$Rd32),
25713(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25714"$Rd32 = vasrhub($Rss32,#$Ii):raw",
25715tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25716let Inst{7-5} = 0b100;
25717let Inst{13-12} = 0b00;
25718let Inst{31-21} = 0b10001000011;
25719let hasNewValue = 1;
25720let opNewValue = 0;
25721let prefersSlot3 = 1;
25722let Defs = [USR_OVF];
25723}
25724def S5_asrhub_rnd_sat_goodsyntax : HInst<
25725(outs IntRegs:$Rd32),
25726(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25727"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
25728tc_0dfac0a7, TypeS_2op> {
25729let hasNewValue = 1;
25730let opNewValue = 0;
25731let isPseudo = 1;
25732}
25733def S5_asrhub_sat : HInst<
25734(outs IntRegs:$Rd32),
25735(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25736"$Rd32 = vasrhub($Rss32,#$Ii):sat",
25737tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25738let Inst{7-5} = 0b101;
25739let Inst{13-12} = 0b00;
25740let Inst{31-21} = 0b10001000011;
25741let hasNewValue = 1;
25742let opNewValue = 0;
25743let prefersSlot3 = 1;
25744let Defs = [USR_OVF];
25745}
25746def S5_popcountp : HInst<
25747(outs IntRegs:$Rd32),
25748(ins DoubleRegs:$Rss32),
25749"$Rd32 = popcount($Rss32)",
25750tc_d3632d88, TypeS_2op>, Enc_90cd8b {
25751let Inst{13-5} = 0b000000011;
25752let Inst{31-21} = 0b10001000011;
25753let hasNewValue = 1;
25754let opNewValue = 0;
25755let prefersSlot3 = 1;
25756}
25757def S5_vasrhrnd : HInst<
25758(outs DoubleRegs:$Rdd32),
25759(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25760"$Rdd32 = vasrh($Rss32,#$Ii):raw",
25761tc_0dfac0a7, TypeS_2op>, Enc_12b6e9 {
25762let Inst{7-5} = 0b000;
25763let Inst{13-12} = 0b00;
25764let Inst{31-21} = 0b10000000001;
25765let prefersSlot3 = 1;
25766}
25767def S5_vasrhrnd_goodsyntax : HInst<
25768(outs DoubleRegs:$Rdd32),
25769(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25770"$Rdd32 = vasrh($Rss32,#$Ii):rnd",
25771tc_0dfac0a7, TypeS_2op> {
25772let isPseudo = 1;
25773}
25774def S6_allocframe_to_raw : HInst<
25775(outs),
25776(ins u11_3Imm:$Ii),
25777"allocframe(#$Ii)",
25778tc_934753bb, TypeMAPPING>, Requires<[HasV65]> {
25779let isPseudo = 1;
25780let isCodeGenOnly = 1;
25781}
25782def S6_rol_i_p : HInst<
25783(outs DoubleRegs:$Rdd32),
25784(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
25785"$Rdd32 = rol($Rss32,#$Ii)",
25786tc_407e96f9, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> {
25787let Inst{7-5} = 0b011;
25788let Inst{31-21} = 0b10000000000;
25789}
25790def S6_rol_i_p_acc : HInst<
25791(outs DoubleRegs:$Rxx32),
25792(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25793"$Rxx32 += rol($Rss32,#$Ii)",
25794tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25795let Inst{7-5} = 0b111;
25796let Inst{31-21} = 0b10000010000;
25797let prefersSlot3 = 1;
25798let Constraints = "$Rxx32 = $Rxx32in";
25799}
25800def S6_rol_i_p_and : HInst<
25801(outs DoubleRegs:$Rxx32),
25802(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25803"$Rxx32 &= rol($Rss32,#$Ii)",
25804tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25805let Inst{7-5} = 0b011;
25806let Inst{31-21} = 0b10000010010;
25807let prefersSlot3 = 1;
25808let Constraints = "$Rxx32 = $Rxx32in";
25809}
25810def S6_rol_i_p_nac : HInst<
25811(outs DoubleRegs:$Rxx32),
25812(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25813"$Rxx32 -= rol($Rss32,#$Ii)",
25814tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25815let Inst{7-5} = 0b011;
25816let Inst{31-21} = 0b10000010000;
25817let prefersSlot3 = 1;
25818let Constraints = "$Rxx32 = $Rxx32in";
25819}
25820def S6_rol_i_p_or : HInst<
25821(outs DoubleRegs:$Rxx32),
25822(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25823"$Rxx32 |= rol($Rss32,#$Ii)",
25824tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25825let Inst{7-5} = 0b111;
25826let Inst{31-21} = 0b10000010010;
25827let prefersSlot3 = 1;
25828let Constraints = "$Rxx32 = $Rxx32in";
25829}
25830def S6_rol_i_p_xacc : HInst<
25831(outs DoubleRegs:$Rxx32),
25832(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25833"$Rxx32 ^= rol($Rss32,#$Ii)",
25834tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25835let Inst{7-5} = 0b011;
25836let Inst{31-21} = 0b10000010100;
25837let prefersSlot3 = 1;
25838let Constraints = "$Rxx32 = $Rxx32in";
25839}
25840def S6_rol_i_r : HInst<
25841(outs IntRegs:$Rd32),
25842(ins IntRegs:$Rs32, u5_0Imm:$Ii),
25843"$Rd32 = rol($Rs32,#$Ii)",
25844tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV60]> {
25845let Inst{7-5} = 0b011;
25846let Inst{13-13} = 0b0;
25847let Inst{31-21} = 0b10001100000;
25848let hasNewValue = 1;
25849let opNewValue = 0;
25850}
25851def S6_rol_i_r_acc : HInst<
25852(outs IntRegs:$Rx32),
25853(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25854"$Rx32 += rol($Rs32,#$Ii)",
25855tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25856let Inst{7-5} = 0b111;
25857let Inst{13-13} = 0b0;
25858let Inst{31-21} = 0b10001110000;
25859let hasNewValue = 1;
25860let opNewValue = 0;
25861let prefersSlot3 = 1;
25862let Constraints = "$Rx32 = $Rx32in";
25863}
25864def S6_rol_i_r_and : HInst<
25865(outs IntRegs:$Rx32),
25866(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25867"$Rx32 &= rol($Rs32,#$Ii)",
25868tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25869let Inst{7-5} = 0b011;
25870let Inst{13-13} = 0b0;
25871let Inst{31-21} = 0b10001110010;
25872let hasNewValue = 1;
25873let opNewValue = 0;
25874let prefersSlot3 = 1;
25875let Constraints = "$Rx32 = $Rx32in";
25876}
25877def S6_rol_i_r_nac : HInst<
25878(outs IntRegs:$Rx32),
25879(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25880"$Rx32 -= rol($Rs32,#$Ii)",
25881tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25882let Inst{7-5} = 0b011;
25883let Inst{13-13} = 0b0;
25884let Inst{31-21} = 0b10001110000;
25885let hasNewValue = 1;
25886let opNewValue = 0;
25887let prefersSlot3 = 1;
25888let Constraints = "$Rx32 = $Rx32in";
25889}
25890def S6_rol_i_r_or : HInst<
25891(outs IntRegs:$Rx32),
25892(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25893"$Rx32 |= rol($Rs32,#$Ii)",
25894tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25895let Inst{7-5} = 0b111;
25896let Inst{13-13} = 0b0;
25897let Inst{31-21} = 0b10001110010;
25898let hasNewValue = 1;
25899let opNewValue = 0;
25900let prefersSlot3 = 1;
25901let Constraints = "$Rx32 = $Rx32in";
25902}
25903def S6_rol_i_r_xacc : HInst<
25904(outs IntRegs:$Rx32),
25905(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25906"$Rx32 ^= rol($Rs32,#$Ii)",
25907tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25908let Inst{7-5} = 0b011;
25909let Inst{13-13} = 0b0;
25910let Inst{31-21} = 0b10001110100;
25911let hasNewValue = 1;
25912let opNewValue = 0;
25913let prefersSlot3 = 1;
25914let Constraints = "$Rx32 = $Rx32in";
25915}
25916def S6_vsplatrbp : HInst<
25917(outs DoubleRegs:$Rdd32),
25918(ins IntRegs:$Rs32),
25919"$Rdd32 = vsplatb($Rs32)",
25920tc_ef921005, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> {
25921let Inst{13-5} = 0b000000100;
25922let Inst{31-21} = 0b10000100010;
25923}
25924def S6_vtrunehb_ppp : HInst<
25925(outs DoubleRegs:$Rdd32),
25926(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25927"$Rdd32 = vtrunehb($Rss32,$Rtt32)",
25928tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25929let Inst{7-5} = 0b011;
25930let Inst{13-13} = 0b0;
25931let Inst{31-21} = 0b11000001100;
25932}
25933def S6_vtrunohb_ppp : HInst<
25934(outs DoubleRegs:$Rdd32),
25935(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25936"$Rdd32 = vtrunohb($Rss32,$Rtt32)",
25937tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25938let Inst{7-5} = 0b101;
25939let Inst{13-13} = 0b0;
25940let Inst{31-21} = 0b11000001100;
25941}
25942def SA1_addi : HInst<
25943(outs GeneralSubRegs:$Rx16),
25944(ins GeneralSubRegs:$Rx16in, s32_0Imm:$Ii),
25945"$Rx16 = add($Rx16in,#$Ii)",
25946tc_5b347363, TypeSUBINSN>, Enc_93af4c {
25947let Inst{12-11} = 0b00;
25948let hasNewValue = 1;
25949let opNewValue = 0;
25950let AsmVariantName = "NonParsable";
25951let DecoderNamespace = "SUBINSN_A";
25952let isExtendable = 1;
25953let opExtendable = 2;
25954let isExtentSigned = 1;
25955let opExtentBits = 7;
25956let opExtentAlign = 0;
25957let Constraints = "$Rx16 = $Rx16in";
25958}
25959def SA1_addrx : HInst<
25960(outs GeneralSubRegs:$Rx16),
25961(ins GeneralSubRegs:$Rx16in, GeneralSubRegs:$Rs16),
25962"$Rx16 = add($Rx16in,$Rs16)",
25963tc_5b347363, TypeSUBINSN>, Enc_0527db {
25964let Inst{12-8} = 0b11000;
25965let hasNewValue = 1;
25966let opNewValue = 0;
25967let AsmVariantName = "NonParsable";
25968let DecoderNamespace = "SUBINSN_A";
25969let Constraints = "$Rx16 = $Rx16in";
25970}
25971def SA1_addsp : HInst<
25972(outs GeneralSubRegs:$Rd16),
25973(ins u6_2Imm:$Ii),
25974"$Rd16 = add(r29,#$Ii)",
25975tc_3d14a17b, TypeSUBINSN>, Enc_2df31d {
25976let Inst{12-10} = 0b011;
25977let hasNewValue = 1;
25978let opNewValue = 0;
25979let AsmVariantName = "NonParsable";
25980let Uses = [R29];
25981let DecoderNamespace = "SUBINSN_A";
25982}
25983def SA1_and1 : HInst<
25984(outs GeneralSubRegs:$Rd16),
25985(ins GeneralSubRegs:$Rs16),
25986"$Rd16 = and($Rs16,#1)",
25987tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
25988let Inst{12-8} = 0b10010;
25989let hasNewValue = 1;
25990let opNewValue = 0;
25991let AsmVariantName = "NonParsable";
25992let DecoderNamespace = "SUBINSN_A";
25993}
25994def SA1_clrf : HInst<
25995(outs GeneralSubRegs:$Rd16),
25996(ins),
25997"if (!p0) $Rd16 = #0",
25998tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25999let Inst{12-4} = 0b110100111;
26000let isPredicated = 1;
26001let isPredicatedFalse = 1;
26002let hasNewValue = 1;
26003let opNewValue = 0;
26004let AsmVariantName = "NonParsable";
26005let Uses = [P0];
26006let DecoderNamespace = "SUBINSN_A";
26007}
26008def SA1_clrfnew : HInst<
26009(outs GeneralSubRegs:$Rd16),
26010(ins),
26011"if (!p0.new) $Rd16 = #0",
26012tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
26013let Inst{12-4} = 0b110100101;
26014let isPredicated = 1;
26015let isPredicatedFalse = 1;
26016let hasNewValue = 1;
26017let opNewValue = 0;
26018let AsmVariantName = "NonParsable";
26019let isPredicatedNew = 1;
26020let Uses = [P0];
26021let DecoderNamespace = "SUBINSN_A";
26022}
26023def SA1_clrt : HInst<
26024(outs GeneralSubRegs:$Rd16),
26025(ins),
26026"if (p0) $Rd16 = #0",
26027tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
26028let Inst{12-4} = 0b110100110;
26029let isPredicated = 1;
26030let hasNewValue = 1;
26031let opNewValue = 0;
26032let AsmVariantName = "NonParsable";
26033let Uses = [P0];
26034let DecoderNamespace = "SUBINSN_A";
26035}
26036def SA1_clrtnew : HInst<
26037(outs GeneralSubRegs:$Rd16),
26038(ins),
26039"if (p0.new) $Rd16 = #0",
26040tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
26041let Inst{12-4} = 0b110100100;
26042let isPredicated = 1;
26043let hasNewValue = 1;
26044let opNewValue = 0;
26045let AsmVariantName = "NonParsable";
26046let isPredicatedNew = 1;
26047let Uses = [P0];
26048let DecoderNamespace = "SUBINSN_A";
26049}
26050def SA1_cmpeqi : HInst<
26051(outs),
26052(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
26053"p0 = cmp.eq($Rs16,#$Ii)",
26054tc_59a7822c, TypeSUBINSN>, Enc_63eaeb {
26055let Inst{3-2} = 0b00;
26056let Inst{12-8} = 0b11001;
26057let AsmVariantName = "NonParsable";
26058let Defs = [P0];
26059let DecoderNamespace = "SUBINSN_A";
26060}
26061def SA1_combine0i : HInst<
26062(outs GeneralDoubleLow8Regs:$Rdd8),
26063(ins u2_0Imm:$Ii),
26064"$Rdd8 = combine(#0,#$Ii)",
26065tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26066let Inst{4-3} = 0b00;
26067let Inst{12-7} = 0b111000;
26068let hasNewValue = 1;
26069let opNewValue = 0;
26070let AsmVariantName = "NonParsable";
26071let DecoderNamespace = "SUBINSN_A";
26072}
26073def SA1_combine1i : HInst<
26074(outs GeneralDoubleLow8Regs:$Rdd8),
26075(ins u2_0Imm:$Ii),
26076"$Rdd8 = combine(#1,#$Ii)",
26077tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26078let Inst{4-3} = 0b01;
26079let Inst{12-7} = 0b111000;
26080let hasNewValue = 1;
26081let opNewValue = 0;
26082let AsmVariantName = "NonParsable";
26083let DecoderNamespace = "SUBINSN_A";
26084}
26085def SA1_combine2i : HInst<
26086(outs GeneralDoubleLow8Regs:$Rdd8),
26087(ins u2_0Imm:$Ii),
26088"$Rdd8 = combine(#2,#$Ii)",
26089tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26090let Inst{4-3} = 0b10;
26091let Inst{12-7} = 0b111000;
26092let hasNewValue = 1;
26093let opNewValue = 0;
26094let AsmVariantName = "NonParsable";
26095let DecoderNamespace = "SUBINSN_A";
26096}
26097def SA1_combine3i : HInst<
26098(outs GeneralDoubleLow8Regs:$Rdd8),
26099(ins u2_0Imm:$Ii),
26100"$Rdd8 = combine(#3,#$Ii)",
26101tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26102let Inst{4-3} = 0b11;
26103let Inst{12-7} = 0b111000;
26104let hasNewValue = 1;
26105let opNewValue = 0;
26106let AsmVariantName = "NonParsable";
26107let DecoderNamespace = "SUBINSN_A";
26108}
26109def SA1_combinerz : HInst<
26110(outs GeneralDoubleLow8Regs:$Rdd8),
26111(ins GeneralSubRegs:$Rs16),
26112"$Rdd8 = combine($Rs16,#0)",
26113tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26114let Inst{3-3} = 0b1;
26115let Inst{12-8} = 0b11101;
26116let hasNewValue = 1;
26117let opNewValue = 0;
26118let AsmVariantName = "NonParsable";
26119let DecoderNamespace = "SUBINSN_A";
26120}
26121def SA1_combinezr : HInst<
26122(outs GeneralDoubleLow8Regs:$Rdd8),
26123(ins GeneralSubRegs:$Rs16),
26124"$Rdd8 = combine(#0,$Rs16)",
26125tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26126let Inst{3-3} = 0b0;
26127let Inst{12-8} = 0b11101;
26128let hasNewValue = 1;
26129let opNewValue = 0;
26130let AsmVariantName = "NonParsable";
26131let DecoderNamespace = "SUBINSN_A";
26132}
26133def SA1_dec : HInst<
26134(outs GeneralSubRegs:$Rd16),
26135(ins GeneralSubRegs:$Rs16, n1Const:$n1),
26136"$Rd16 = add($Rs16,#$n1)",
26137tc_5b347363, TypeSUBINSN>, Enc_ee5ed0 {
26138let Inst{12-8} = 0b10011;
26139let hasNewValue = 1;
26140let opNewValue = 0;
26141let AsmVariantName = "NonParsable";
26142let DecoderNamespace = "SUBINSN_A";
26143}
26144def SA1_inc : HInst<
26145(outs GeneralSubRegs:$Rd16),
26146(ins GeneralSubRegs:$Rs16),
26147"$Rd16 = add($Rs16,#1)",
26148tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26149let Inst{12-8} = 0b10001;
26150let hasNewValue = 1;
26151let opNewValue = 0;
26152let AsmVariantName = "NonParsable";
26153let DecoderNamespace = "SUBINSN_A";
26154}
26155def SA1_seti : HInst<
26156(outs GeneralSubRegs:$Rd16),
26157(ins u32_0Imm:$Ii),
26158"$Rd16 = #$Ii",
26159tc_3d14a17b, TypeSUBINSN>, Enc_e39bb2 {
26160let Inst{12-10} = 0b010;
26161let hasNewValue = 1;
26162let opNewValue = 0;
26163let AsmVariantName = "NonParsable";
26164let DecoderNamespace = "SUBINSN_A";
26165let isExtendable = 1;
26166let opExtendable = 1;
26167let isExtentSigned = 0;
26168let opExtentBits = 6;
26169let opExtentAlign = 0;
26170}
26171def SA1_setin1 : HInst<
26172(outs GeneralSubRegs:$Rd16),
26173(ins n1Const:$n1),
26174"$Rd16 = #$n1",
26175tc_3d14a17b, TypeSUBINSN>, Enc_7a0ea6 {
26176let Inst{12-4} = 0b110100000;
26177let hasNewValue = 1;
26178let opNewValue = 0;
26179let AsmVariantName = "NonParsable";
26180let DecoderNamespace = "SUBINSN_A";
26181}
26182def SA1_sxtb : HInst<
26183(outs GeneralSubRegs:$Rd16),
26184(ins GeneralSubRegs:$Rs16),
26185"$Rd16 = sxtb($Rs16)",
26186tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26187let Inst{12-8} = 0b10101;
26188let hasNewValue = 1;
26189let opNewValue = 0;
26190let AsmVariantName = "NonParsable";
26191let DecoderNamespace = "SUBINSN_A";
26192}
26193def SA1_sxth : HInst<
26194(outs GeneralSubRegs:$Rd16),
26195(ins GeneralSubRegs:$Rs16),
26196"$Rd16 = sxth($Rs16)",
26197tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26198let Inst{12-8} = 0b10100;
26199let hasNewValue = 1;
26200let opNewValue = 0;
26201let AsmVariantName = "NonParsable";
26202let DecoderNamespace = "SUBINSN_A";
26203}
26204def SA1_tfr : HInst<
26205(outs GeneralSubRegs:$Rd16),
26206(ins GeneralSubRegs:$Rs16),
26207"$Rd16 = $Rs16",
26208tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26209let Inst{12-8} = 0b10000;
26210let hasNewValue = 1;
26211let opNewValue = 0;
26212let AsmVariantName = "NonParsable";
26213let DecoderNamespace = "SUBINSN_A";
26214}
26215def SA1_zxtb : HInst<
26216(outs GeneralSubRegs:$Rd16),
26217(ins GeneralSubRegs:$Rs16),
26218"$Rd16 = and($Rs16,#255)",
26219tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26220let Inst{12-8} = 0b10111;
26221let hasNewValue = 1;
26222let opNewValue = 0;
26223let AsmVariantName = "NonParsable";
26224let DecoderNamespace = "SUBINSN_A";
26225}
26226def SA1_zxth : HInst<
26227(outs GeneralSubRegs:$Rd16),
26228(ins GeneralSubRegs:$Rs16),
26229"$Rd16 = zxth($Rs16)",
26230tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26231let Inst{12-8} = 0b10110;
26232let hasNewValue = 1;
26233let opNewValue = 0;
26234let AsmVariantName = "NonParsable";
26235let DecoderNamespace = "SUBINSN_A";
26236}
26237def SL1_loadri_io : HInst<
26238(outs GeneralSubRegs:$Rd16),
26239(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26240"$Rd16 = memw($Rs16+#$Ii)",
26241tc_4222e6bf, TypeSUBINSN>, Enc_53dca9 {
26242let Inst{12-12} = 0b0;
26243let hasNewValue = 1;
26244let opNewValue = 0;
26245let addrMode = BaseImmOffset;
26246let accessSize = WordAccess;
26247let AsmVariantName = "NonParsable";
26248let mayLoad = 1;
26249let DecoderNamespace = "SUBINSN_L1";
26250}
26251def SL1_loadrub_io : HInst<
26252(outs GeneralSubRegs:$Rd16),
26253(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26254"$Rd16 = memub($Rs16+#$Ii)",
26255tc_4222e6bf, TypeSUBINSN>, Enc_c175d0 {
26256let Inst{12-12} = 0b1;
26257let hasNewValue = 1;
26258let opNewValue = 0;
26259let addrMode = BaseImmOffset;
26260let accessSize = ByteAccess;
26261let AsmVariantName = "NonParsable";
26262let mayLoad = 1;
26263let DecoderNamespace = "SUBINSN_L1";
26264}
26265def SL2_deallocframe : HInst<
26266(outs),
26267(ins),
26268"deallocframe",
26269tc_937dd41c, TypeSUBINSN>, Enc_e3b0c4 {
26270let Inst{12-0} = 0b1111100000000;
26271let accessSize = DoubleWordAccess;
26272let AsmVariantName = "NonParsable";
26273let mayLoad = 1;
26274let Uses = [FRAMEKEY, R30];
26275let Defs = [R29, R30, R31];
26276let DecoderNamespace = "SUBINSN_L2";
26277}
26278def SL2_jumpr31 : HInst<
26279(outs),
26280(ins),
26281"jumpr r31",
26282tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26283let Inst{12-0} = 0b1111111000000;
26284let isTerminator = 1;
26285let isIndirectBranch = 1;
26286let AsmVariantName = "NonParsable";
26287let cofMax1 = 1;
26288let isReturn = 1;
26289let Uses = [R31];
26290let Defs = [PC];
26291let DecoderNamespace = "SUBINSN_L2";
26292}
26293def SL2_jumpr31_f : HInst<
26294(outs),
26295(ins),
26296"if (!p0) jumpr r31",
26297tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26298let Inst{12-0} = 0b1111111000101;
26299let isPredicated = 1;
26300let isPredicatedFalse = 1;
26301let isTerminator = 1;
26302let isIndirectBranch = 1;
26303let AsmVariantName = "NonParsable";
26304let cofMax1 = 1;
26305let isReturn = 1;
26306let Uses = [P0, R31];
26307let Defs = [PC];
26308let isTaken = Inst{4};
26309let DecoderNamespace = "SUBINSN_L2";
26310}
26311def SL2_jumpr31_fnew : HInst<
26312(outs),
26313(ins),
26314"if (!p0.new) jumpr:nt r31",
26315tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26316let Inst{12-0} = 0b1111111000111;
26317let isPredicated = 1;
26318let isPredicatedFalse = 1;
26319let isTerminator = 1;
26320let isIndirectBranch = 1;
26321let AsmVariantName = "NonParsable";
26322let isPredicatedNew = 1;
26323let cofMax1 = 1;
26324let isReturn = 1;
26325let Uses = [P0, R31];
26326let Defs = [PC];
26327let isTaken = Inst{4};
26328let DecoderNamespace = "SUBINSN_L2";
26329}
26330def SL2_jumpr31_t : HInst<
26331(outs),
26332(ins),
26333"if (p0) jumpr r31",
26334tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26335let Inst{12-0} = 0b1111111000100;
26336let isPredicated = 1;
26337let isTerminator = 1;
26338let isIndirectBranch = 1;
26339let AsmVariantName = "NonParsable";
26340let cofMax1 = 1;
26341let isReturn = 1;
26342let Uses = [P0, R31];
26343let Defs = [PC];
26344let isTaken = Inst{4};
26345let DecoderNamespace = "SUBINSN_L2";
26346}
26347def SL2_jumpr31_tnew : HInst<
26348(outs),
26349(ins),
26350"if (p0.new) jumpr:nt r31",
26351tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26352let Inst{12-0} = 0b1111111000110;
26353let isPredicated = 1;
26354let isTerminator = 1;
26355let isIndirectBranch = 1;
26356let AsmVariantName = "NonParsable";
26357let isPredicatedNew = 1;
26358let cofMax1 = 1;
26359let isReturn = 1;
26360let Uses = [P0, R31];
26361let Defs = [PC];
26362let isTaken = Inst{4};
26363let DecoderNamespace = "SUBINSN_L2";
26364}
26365def SL2_loadrb_io : HInst<
26366(outs GeneralSubRegs:$Rd16),
26367(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
26368"$Rd16 = memb($Rs16+#$Ii)",
26369tc_4222e6bf, TypeSUBINSN>, Enc_2fbf3c {
26370let Inst{12-11} = 0b10;
26371let hasNewValue = 1;
26372let opNewValue = 0;
26373let addrMode = BaseImmOffset;
26374let accessSize = ByteAccess;
26375let AsmVariantName = "NonParsable";
26376let mayLoad = 1;
26377let DecoderNamespace = "SUBINSN_L2";
26378}
26379def SL2_loadrd_sp : HInst<
26380(outs GeneralDoubleLow8Regs:$Rdd8),
26381(ins u5_3Imm:$Ii),
26382"$Rdd8 = memd(r29+#$Ii)",
26383tc_8a6d0d94, TypeSUBINSN>, Enc_86a14b {
26384let Inst{12-8} = 0b11110;
26385let hasNewValue = 1;
26386let opNewValue = 0;
26387let addrMode = BaseImmOffset;
26388let accessSize = DoubleWordAccess;
26389let AsmVariantName = "NonParsable";
26390let mayLoad = 1;
26391let Uses = [R29];
26392let DecoderNamespace = "SUBINSN_L2";
26393}
26394def SL2_loadrh_io : HInst<
26395(outs GeneralSubRegs:$Rd16),
26396(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26397"$Rd16 = memh($Rs16+#$Ii)",
26398tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26399let Inst{12-11} = 0b00;
26400let hasNewValue = 1;
26401let opNewValue = 0;
26402let addrMode = BaseImmOffset;
26403let accessSize = HalfWordAccess;
26404let AsmVariantName = "NonParsable";
26405let mayLoad = 1;
26406let DecoderNamespace = "SUBINSN_L2";
26407}
26408def SL2_loadri_sp : HInst<
26409(outs GeneralSubRegs:$Rd16),
26410(ins u5_2Imm:$Ii),
26411"$Rd16 = memw(r29+#$Ii)",
26412tc_8a6d0d94, TypeSUBINSN>, Enc_51635c {
26413let Inst{12-9} = 0b1110;
26414let hasNewValue = 1;
26415let opNewValue = 0;
26416let addrMode = BaseImmOffset;
26417let accessSize = WordAccess;
26418let AsmVariantName = "NonParsable";
26419let mayLoad = 1;
26420let Uses = [R29];
26421let DecoderNamespace = "SUBINSN_L2";
26422}
26423def SL2_loadruh_io : HInst<
26424(outs GeneralSubRegs:$Rd16),
26425(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26426"$Rd16 = memuh($Rs16+#$Ii)",
26427tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26428let Inst{12-11} = 0b01;
26429let hasNewValue = 1;
26430let opNewValue = 0;
26431let addrMode = BaseImmOffset;
26432let accessSize = HalfWordAccess;
26433let AsmVariantName = "NonParsable";
26434let mayLoad = 1;
26435let DecoderNamespace = "SUBINSN_L2";
26436}
26437def SL2_return : HInst<
26438(outs),
26439(ins),
26440"dealloc_return",
26441tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26442let Inst{12-0} = 0b1111101000000;
26443let isTerminator = 1;
26444let isIndirectBranch = 1;
26445let accessSize = DoubleWordAccess;
26446let AsmVariantName = "NonParsable";
26447let mayLoad = 1;
26448let cofMax1 = 1;
26449let isRestrictNoSlot1Store = 1;
26450let isReturn = 1;
26451let Uses = [FRAMEKEY, R30];
26452let Defs = [PC, R29, R30, R31];
26453let DecoderNamespace = "SUBINSN_L2";
26454}
26455def SL2_return_f : HInst<
26456(outs),
26457(ins),
26458"if (!p0) dealloc_return",
26459tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26460let Inst{12-0} = 0b1111101000101;
26461let isPredicated = 1;
26462let isPredicatedFalse = 1;
26463let isTerminator = 1;
26464let isIndirectBranch = 1;
26465let accessSize = DoubleWordAccess;
26466let AsmVariantName = "NonParsable";
26467let mayLoad = 1;
26468let cofMax1 = 1;
26469let isRestrictNoSlot1Store = 1;
26470let isReturn = 1;
26471let Uses = [FRAMEKEY, P0, R30];
26472let Defs = [PC, R29, R30, R31];
26473let isTaken = Inst{4};
26474let DecoderNamespace = "SUBINSN_L2";
26475}
26476def SL2_return_fnew : HInst<
26477(outs),
26478(ins),
26479"if (!p0.new) dealloc_return:nt",
26480tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26481let Inst{12-0} = 0b1111101000111;
26482let isPredicated = 1;
26483let isPredicatedFalse = 1;
26484let isTerminator = 1;
26485let isIndirectBranch = 1;
26486let accessSize = DoubleWordAccess;
26487let AsmVariantName = "NonParsable";
26488let isPredicatedNew = 1;
26489let mayLoad = 1;
26490let cofMax1 = 1;
26491let isRestrictNoSlot1Store = 1;
26492let isReturn = 1;
26493let Uses = [FRAMEKEY, P0, R30];
26494let Defs = [PC, R29, R30, R31];
26495let isTaken = Inst{4};
26496let DecoderNamespace = "SUBINSN_L2";
26497}
26498def SL2_return_t : HInst<
26499(outs),
26500(ins),
26501"if (p0) dealloc_return",
26502tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26503let Inst{12-0} = 0b1111101000100;
26504let isPredicated = 1;
26505let isTerminator = 1;
26506let isIndirectBranch = 1;
26507let accessSize = DoubleWordAccess;
26508let AsmVariantName = "NonParsable";
26509let mayLoad = 1;
26510let cofMax1 = 1;
26511let isRestrictNoSlot1Store = 1;
26512let isReturn = 1;
26513let Uses = [FRAMEKEY, P0, R30];
26514let Defs = [PC, R29, R30, R31];
26515let isTaken = Inst{4};
26516let DecoderNamespace = "SUBINSN_L2";
26517}
26518def SL2_return_tnew : HInst<
26519(outs),
26520(ins),
26521"if (p0.new) dealloc_return:nt",
26522tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26523let Inst{12-0} = 0b1111101000110;
26524let isPredicated = 1;
26525let isTerminator = 1;
26526let isIndirectBranch = 1;
26527let accessSize = DoubleWordAccess;
26528let AsmVariantName = "NonParsable";
26529let isPredicatedNew = 1;
26530let mayLoad = 1;
26531let cofMax1 = 1;
26532let isRestrictNoSlot1Store = 1;
26533let isReturn = 1;
26534let Uses = [FRAMEKEY, P0, R30];
26535let Defs = [PC, R29, R30, R31];
26536let isTaken = Inst{4};
26537let DecoderNamespace = "SUBINSN_L2";
26538}
26539def SS1_storeb_io : HInst<
26540(outs),
26541(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
26542"memb($Rs16+#$Ii) = $Rt16",
26543tc_ae5babd7, TypeSUBINSN>, Enc_b38ffc {
26544let Inst{12-12} = 0b1;
26545let addrMode = BaseImmOffset;
26546let accessSize = ByteAccess;
26547let AsmVariantName = "NonParsable";
26548let mayStore = 1;
26549let DecoderNamespace = "SUBINSN_S1";
26550}
26551def SS1_storew_io : HInst<
26552(outs),
26553(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
26554"memw($Rs16+#$Ii) = $Rt16",
26555tc_ae5babd7, TypeSUBINSN>, Enc_f55a0c {
26556let Inst{12-12} = 0b0;
26557let addrMode = BaseImmOffset;
26558let accessSize = WordAccess;
26559let AsmVariantName = "NonParsable";
26560let mayStore = 1;
26561let DecoderNamespace = "SUBINSN_S1";
26562}
26563def SS2_allocframe : HInst<
26564(outs),
26565(ins u5_3Imm:$Ii),
26566"allocframe(#$Ii)",
26567tc_1242dc2a, TypeSUBINSN>, Enc_6f70ca {
26568let Inst{3-0} = 0b0000;
26569let Inst{12-9} = 0b1110;
26570let addrMode = BaseImmOffset;
26571let accessSize = DoubleWordAccess;
26572let AsmVariantName = "NonParsable";
26573let mayStore = 1;
26574let Uses = [FRAMEKEY, FRAMELIMIT, R29, R30, R31];
26575let Defs = [R29, R30];
26576let DecoderNamespace = "SUBINSN_S2";
26577}
26578def SS2_storebi0 : HInst<
26579(outs),
26580(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26581"memb($Rs16+#$Ii) = #0",
26582tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26583let Inst{12-8} = 0b10010;
26584let addrMode = BaseImmOffset;
26585let accessSize = ByteAccess;
26586let AsmVariantName = "NonParsable";
26587let mayStore = 1;
26588let DecoderNamespace = "SUBINSN_S2";
26589}
26590def SS2_storebi1 : HInst<
26591(outs),
26592(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26593"memb($Rs16+#$Ii) = #1",
26594tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26595let Inst{12-8} = 0b10011;
26596let addrMode = BaseImmOffset;
26597let accessSize = ByteAccess;
26598let AsmVariantName = "NonParsable";
26599let mayStore = 1;
26600let DecoderNamespace = "SUBINSN_S2";
26601}
26602def SS2_stored_sp : HInst<
26603(outs),
26604(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
26605"memd(r29+#$Ii) = $Rtt8",
26606tc_0655b949, TypeSUBINSN>, Enc_b8309d {
26607let Inst{12-9} = 0b0101;
26608let addrMode = BaseImmOffset;
26609let accessSize = DoubleWordAccess;
26610let AsmVariantName = "NonParsable";
26611let mayStore = 1;
26612let Uses = [R29];
26613let DecoderNamespace = "SUBINSN_S2";
26614}
26615def SS2_storeh_io : HInst<
26616(outs),
26617(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
26618"memh($Rs16+#$Ii) = $Rt16",
26619tc_ae5babd7, TypeSUBINSN>, Enc_625deb {
26620let Inst{12-11} = 0b00;
26621let addrMode = BaseImmOffset;
26622let accessSize = HalfWordAccess;
26623let AsmVariantName = "NonParsable";
26624let mayStore = 1;
26625let DecoderNamespace = "SUBINSN_S2";
26626}
26627def SS2_storew_sp : HInst<
26628(outs),
26629(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
26630"memw(r29+#$Ii) = $Rt16",
26631tc_0655b949, TypeSUBINSN>, Enc_87c142 {
26632let Inst{12-9} = 0b0100;
26633let addrMode = BaseImmOffset;
26634let accessSize = WordAccess;
26635let AsmVariantName = "NonParsable";
26636let mayStore = 1;
26637let Uses = [R29];
26638let DecoderNamespace = "SUBINSN_S2";
26639}
26640def SS2_storewi0 : HInst<
26641(outs),
26642(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26643"memw($Rs16+#$Ii) = #0",
26644tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26645let Inst{12-8} = 0b10000;
26646let addrMode = BaseImmOffset;
26647let accessSize = WordAccess;
26648let AsmVariantName = "NonParsable";
26649let mayStore = 1;
26650let DecoderNamespace = "SUBINSN_S2";
26651}
26652def SS2_storewi1 : HInst<
26653(outs),
26654(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26655"memw($Rs16+#$Ii) = #1",
26656tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26657let Inst{12-8} = 0b10001;
26658let addrMode = BaseImmOffset;
26659let accessSize = WordAccess;
26660let AsmVariantName = "NonParsable";
26661let mayStore = 1;
26662let DecoderNamespace = "SUBINSN_S2";
26663}
26664def V6_MAP_equb : HInst<
26665(outs HvxQR:$Qd4),
26666(ins HvxVR:$Vu32, HvxVR:$Vv32),
26667"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
26668PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26669let hasNewValue = 1;
26670let opNewValue = 0;
26671let isCVI = 1;
26672let isPseudo = 1;
26673let isCodeGenOnly = 1;
26674let DecoderNamespace = "EXT_mmvec";
26675}
26676def V6_MAP_equb_and : HInst<
26677(outs HvxQR:$Qx4),
26678(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26679"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
26680PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26681let isCVI = 1;
26682let isPseudo = 1;
26683let isCodeGenOnly = 1;
26684let DecoderNamespace = "EXT_mmvec";
26685let Constraints = "$Qx4 = $Qx4in";
26686}
26687def V6_MAP_equb_ior : HInst<
26688(outs HvxQR:$Qx4),
26689(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26690"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
26691PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26692let isAccumulator = 1;
26693let isCVI = 1;
26694let isPseudo = 1;
26695let isCodeGenOnly = 1;
26696let DecoderNamespace = "EXT_mmvec";
26697let Constraints = "$Qx4 = $Qx4in";
26698}
26699def V6_MAP_equb_xor : HInst<
26700(outs HvxQR:$Qx4),
26701(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26702"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
26703PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26704let isCVI = 1;
26705let isPseudo = 1;
26706let isCodeGenOnly = 1;
26707let DecoderNamespace = "EXT_mmvec";
26708let Constraints = "$Qx4 = $Qx4in";
26709}
26710def V6_MAP_equh : HInst<
26711(outs HvxQR:$Qd4),
26712(ins HvxVR:$Vu32, HvxVR:$Vv32),
26713"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
26714PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26715let hasNewValue = 1;
26716let opNewValue = 0;
26717let isCVI = 1;
26718let isPseudo = 1;
26719let isCodeGenOnly = 1;
26720let DecoderNamespace = "EXT_mmvec";
26721}
26722def V6_MAP_equh_and : HInst<
26723(outs HvxQR:$Qx4),
26724(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26725"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
26726PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26727let isCVI = 1;
26728let isPseudo = 1;
26729let isCodeGenOnly = 1;
26730let DecoderNamespace = "EXT_mmvec";
26731let Constraints = "$Qx4 = $Qx4in";
26732}
26733def V6_MAP_equh_ior : HInst<
26734(outs HvxQR:$Qx4),
26735(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26736"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
26737PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26738let isAccumulator = 1;
26739let isCVI = 1;
26740let isPseudo = 1;
26741let isCodeGenOnly = 1;
26742let DecoderNamespace = "EXT_mmvec";
26743let Constraints = "$Qx4 = $Qx4in";
26744}
26745def V6_MAP_equh_xor : HInst<
26746(outs HvxQR:$Qx4),
26747(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26748"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
26749PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26750let isCVI = 1;
26751let isPseudo = 1;
26752let isCodeGenOnly = 1;
26753let DecoderNamespace = "EXT_mmvec";
26754let Constraints = "$Qx4 = $Qx4in";
26755}
26756def V6_MAP_equw : HInst<
26757(outs HvxQR:$Qd4),
26758(ins HvxVR:$Vu32, HvxVR:$Vv32),
26759"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
26760PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26761let hasNewValue = 1;
26762let opNewValue = 0;
26763let isCVI = 1;
26764let isPseudo = 1;
26765let isCodeGenOnly = 1;
26766let DecoderNamespace = "EXT_mmvec";
26767}
26768def V6_MAP_equw_and : HInst<
26769(outs HvxQR:$Qx4),
26770(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26771"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
26772PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26773let isCVI = 1;
26774let isPseudo = 1;
26775let isCodeGenOnly = 1;
26776let DecoderNamespace = "EXT_mmvec";
26777let Constraints = "$Qx4 = $Qx4in";
26778}
26779def V6_MAP_equw_ior : HInst<
26780(outs HvxQR:$Qx4),
26781(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26782"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
26783PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26784let isAccumulator = 1;
26785let isCVI = 1;
26786let isPseudo = 1;
26787let isCodeGenOnly = 1;
26788let DecoderNamespace = "EXT_mmvec";
26789let Constraints = "$Qx4 = $Qx4in";
26790}
26791def V6_MAP_equw_xor : HInst<
26792(outs HvxQR:$Qx4),
26793(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26794"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
26795PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26796let isCVI = 1;
26797let isPseudo = 1;
26798let isCodeGenOnly = 1;
26799let DecoderNamespace = "EXT_mmvec";
26800let Constraints = "$Qx4 = $Qx4in";
26801}
26802def V6_dbl_ld0 : HInst<
26803(outs HvxWR:$Vdd32),
26804(ins IntRegs:$Rt32),
26805"$Vdd32 = vmem($Rt32)",
26806PSEUDO, TypeMAPPING>, Requires<[UseHVXV73]> {
26807let hasNewValue = 1;
26808let opNewValue = 0;
26809let isCVLoad = 1;
26810let isCVI = 1;
26811let mayLoad = 1;
26812let isPseudo = 1;
26813let isCodeGenOnly = 1;
26814let DecoderNamespace = "EXT_mmvec";
26815}
26816def V6_dbl_st0 : HInst<
26817(outs),
26818(ins IntRegs:$Rt32, HvxWR:$Vss32),
26819"vmem($Rt32) = $Vss32",
26820PSEUDO, TypeMAPPING>, Requires<[UseHVXV73]> {
26821let isCVI = 1;
26822let mayStore = 1;
26823let isPseudo = 1;
26824let isCodeGenOnly = 1;
26825let DecoderNamespace = "EXT_mmvec";
26826}
26827def V6_extractw : HInst<
26828(outs IntRegs:$Rd32),
26829(ins HvxVR:$Vu32, IntRegs:$Rs32),
26830"$Rd32 = vextract($Vu32,$Rs32)",
26831tc_540c3da3, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
26832let Inst{7-5} = 0b001;
26833let Inst{13-13} = 0b0;
26834let Inst{31-21} = 0b10010010000;
26835let hasNewValue = 1;
26836let opNewValue = 0;
26837let isCVI = 1;
26838let isHVXALU = 1;
26839let isHVXALU2SRC = 1;
26840let isSolo = 1;
26841let mayLoad = 1;
26842let DecoderNamespace = "EXT_mmvec";
26843}
26844def V6_extractw_alt : HInst<
26845(outs IntRegs:$Rd32),
26846(ins HvxVR:$Vu32, IntRegs:$Rs32),
26847"$Rd32.w = vextract($Vu32,$Rs32)",
26848PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26849let hasNewValue = 1;
26850let opNewValue = 0;
26851let isCVI = 1;
26852let isPseudo = 1;
26853let isCodeGenOnly = 1;
26854let DecoderNamespace = "EXT_mmvec";
26855}
26856def V6_hi : HInst<
26857(outs HvxVR:$Vd32),
26858(ins HvxWR:$Vss32),
26859"$Vd32 = hi($Vss32)",
26860CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26861let hasNewValue = 1;
26862let opNewValue = 0;
26863let isCVI = 1;
26864let isPseudo = 1;
26865let DecoderNamespace = "EXT_mmvec";
26866}
26867def V6_ld0 : HInst<
26868(outs HvxVR:$Vd32),
26869(ins IntRegs:$Rt32),
26870"$Vd32 = vmem($Rt32)",
26871PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26872let hasNewValue = 1;
26873let opNewValue = 0;
26874let isCVI = 1;
26875let isPseudo = 1;
26876let isCodeGenOnly = 1;
26877let DecoderNamespace = "EXT_mmvec";
26878}
26879def V6_ldcnp0 : HInst<
26880(outs HvxVR:$Vd32),
26881(ins PredRegs:$Pv4, IntRegs:$Rt32),
26882"if (!$Pv4) $Vd32.cur = vmem($Rt32)",
26883PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26884let hasNewValue = 1;
26885let opNewValue = 0;
26886let isCVI = 1;
26887let isPseudo = 1;
26888let isCodeGenOnly = 1;
26889let DecoderNamespace = "EXT_mmvec";
26890}
26891def V6_ldcnpnt0 : HInst<
26892(outs HvxVR:$Vd32),
26893(ins PredRegs:$Pv4, IntRegs:$Rt32),
26894"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
26895PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26896let hasNewValue = 1;
26897let opNewValue = 0;
26898let isCVI = 1;
26899let isPseudo = 1;
26900let isCodeGenOnly = 1;
26901let DecoderNamespace = "EXT_mmvec";
26902}
26903def V6_ldcp0 : HInst<
26904(outs HvxVR:$Vd32),
26905(ins PredRegs:$Pv4, IntRegs:$Rt32),
26906"if ($Pv4) $Vd32.cur = vmem($Rt32)",
26907PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26908let hasNewValue = 1;
26909let opNewValue = 0;
26910let isCVI = 1;
26911let isPseudo = 1;
26912let isCodeGenOnly = 1;
26913let DecoderNamespace = "EXT_mmvec";
26914}
26915def V6_ldcpnt0 : HInst<
26916(outs HvxVR:$Vd32),
26917(ins PredRegs:$Pv4, IntRegs:$Rt32),
26918"if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
26919PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26920let hasNewValue = 1;
26921let opNewValue = 0;
26922let isCVI = 1;
26923let isPseudo = 1;
26924let isCodeGenOnly = 1;
26925let DecoderNamespace = "EXT_mmvec";
26926}
26927def V6_ldnp0 : HInst<
26928(outs HvxVR:$Vd32),
26929(ins PredRegs:$Pv4, IntRegs:$Rt32),
26930"if (!$Pv4) $Vd32 = vmem($Rt32)",
26931PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26932let hasNewValue = 1;
26933let opNewValue = 0;
26934let isCVI = 1;
26935let isPseudo = 1;
26936let isCodeGenOnly = 1;
26937let DecoderNamespace = "EXT_mmvec";
26938}
26939def V6_ldnpnt0 : HInst<
26940(outs HvxVR:$Vd32),
26941(ins PredRegs:$Pv4, IntRegs:$Rt32),
26942"if (!$Pv4) $Vd32 = vmem($Rt32):nt",
26943PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26944let hasNewValue = 1;
26945let opNewValue = 0;
26946let isCVI = 1;
26947let isPseudo = 1;
26948let isCodeGenOnly = 1;
26949let DecoderNamespace = "EXT_mmvec";
26950}
26951def V6_ldnt0 : HInst<
26952(outs HvxVR:$Vd32),
26953(ins IntRegs:$Rt32),
26954"$Vd32 = vmem($Rt32):nt",
26955PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26956let hasNewValue = 1;
26957let opNewValue = 0;
26958let isCVI = 1;
26959let isPseudo = 1;
26960let isCodeGenOnly = 1;
26961let DecoderNamespace = "EXT_mmvec";
26962}
26963def V6_ldp0 : HInst<
26964(outs HvxVR:$Vd32),
26965(ins PredRegs:$Pv4, IntRegs:$Rt32),
26966"if ($Pv4) $Vd32 = vmem($Rt32)",
26967PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26968let hasNewValue = 1;
26969let opNewValue = 0;
26970let isCVI = 1;
26971let isPseudo = 1;
26972let isCodeGenOnly = 1;
26973let DecoderNamespace = "EXT_mmvec";
26974}
26975def V6_ldpnt0 : HInst<
26976(outs HvxVR:$Vd32),
26977(ins PredRegs:$Pv4, IntRegs:$Rt32),
26978"if ($Pv4) $Vd32 = vmem($Rt32):nt",
26979PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26980let hasNewValue = 1;
26981let opNewValue = 0;
26982let isCVI = 1;
26983let isPseudo = 1;
26984let isCodeGenOnly = 1;
26985let DecoderNamespace = "EXT_mmvec";
26986}
26987def V6_ldtnp0 : HInst<
26988(outs HvxVR:$Vd32),
26989(ins PredRegs:$Pv4, IntRegs:$Rt32),
26990"if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
26991PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26992let hasNewValue = 1;
26993let opNewValue = 0;
26994let isCVI = 1;
26995let isPseudo = 1;
26996let isCodeGenOnly = 1;
26997let DecoderNamespace = "EXT_mmvec";
26998}
26999def V6_ldtnpnt0 : HInst<
27000(outs HvxVR:$Vd32),
27001(ins PredRegs:$Pv4, IntRegs:$Rt32),
27002"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
27003PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
27004let hasNewValue = 1;
27005let opNewValue = 0;
27006let isCVI = 1;
27007let isPseudo = 1;
27008let isCodeGenOnly = 1;
27009let DecoderNamespace = "EXT_mmvec";
27010}
27011def V6_ldtp0 : HInst<
27012(outs HvxVR:$Vd32),
27013(ins PredRegs:$Pv4, IntRegs:$Rt32),
27014"if ($Pv4) $Vd32.tmp = vmem($Rt32)",
27015PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
27016let hasNewValue = 1;
27017let opNewValue = 0;
27018let isCVI = 1;
27019let isPseudo = 1;
27020let isCodeGenOnly = 1;
27021let DecoderNamespace = "EXT_mmvec";
27022}
27023def V6_ldtpnt0 : HInst<
27024(outs HvxVR:$Vd32),
27025(ins PredRegs:$Pv4, IntRegs:$Rt32),
27026"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
27027PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
27028let hasNewValue = 1;
27029let opNewValue = 0;
27030let isCVI = 1;
27031let isPseudo = 1;
27032let isCodeGenOnly = 1;
27033let DecoderNamespace = "EXT_mmvec";
27034}
27035def V6_ldu0 : HInst<
27036(outs HvxVR:$Vd32),
27037(ins IntRegs:$Rt32),
27038"$Vd32 = vmemu($Rt32)",
27039PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
27040let hasNewValue = 1;
27041let opNewValue = 0;
27042let isCVI = 1;
27043let isPseudo = 1;
27044let isCodeGenOnly = 1;
27045let DecoderNamespace = "EXT_mmvec";
27046}
27047def V6_lo : HInst<
27048(outs HvxVR:$Vd32),
27049(ins HvxWR:$Vss32),
27050"$Vd32 = lo($Vss32)",
27051CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
27052let hasNewValue = 1;
27053let opNewValue = 0;
27054let isCVI = 1;
27055let isPseudo = 1;
27056let DecoderNamespace = "EXT_mmvec";
27057}
27058def V6_lvsplatb : HInst<
27059(outs HvxVR:$Vd32),
27060(ins IntRegs:$Rt32),
27061"$Vd32.b = vsplat($Rt32)",
27062tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
27063let Inst{13-5} = 0b000000010;
27064let Inst{31-21} = 0b00011001110;
27065let hasNewValue = 1;
27066let opNewValue = 0;
27067let isCVI = 1;
27068let DecoderNamespace = "EXT_mmvec";
27069}
27070def V6_lvsplath : HInst<
27071(outs HvxVR:$Vd32),
27072(ins IntRegs:$Rt32),
27073"$Vd32.h = vsplat($Rt32)",
27074tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
27075let Inst{13-5} = 0b000000001;
27076let Inst{31-21} = 0b00011001110;
27077let hasNewValue = 1;
27078let opNewValue = 0;
27079let isCVI = 1;
27080let DecoderNamespace = "EXT_mmvec";
27081}
27082def V6_lvsplatw : HInst<
27083(outs HvxVR:$Vd32),
27084(ins IntRegs:$Rt32),
27085"$Vd32 = vsplat($Rt32)",
27086tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
27087let Inst{13-5} = 0b000000001;
27088let Inst{31-21} = 0b00011001101;
27089let hasNewValue = 1;
27090let opNewValue = 0;
27091let isCVI = 1;
27092let DecoderNamespace = "EXT_mmvec";
27093}
27094def V6_pred_and : HInst<
27095(outs HvxQR:$Qd4),
27096(ins HvxQR:$Qs4, HvxQR:$Qt4),
27097"$Qd4 = and($Qs4,$Qt4)",
27098tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27099let Inst{7-2} = 0b000000;
27100let Inst{13-10} = 0b0000;
27101let Inst{21-16} = 0b000011;
27102let Inst{31-24} = 0b00011110;
27103let hasNewValue = 1;
27104let opNewValue = 0;
27105let isCVI = 1;
27106let DecoderNamespace = "EXT_mmvec";
27107}
27108def V6_pred_and_n : HInst<
27109(outs HvxQR:$Qd4),
27110(ins HvxQR:$Qs4, HvxQR:$Qt4),
27111"$Qd4 = and($Qs4,!$Qt4)",
27112tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27113let Inst{7-2} = 0b000101;
27114let Inst{13-10} = 0b0000;
27115let Inst{21-16} = 0b000011;
27116let Inst{31-24} = 0b00011110;
27117let hasNewValue = 1;
27118let opNewValue = 0;
27119let isCVI = 1;
27120let DecoderNamespace = "EXT_mmvec";
27121}
27122def V6_pred_not : HInst<
27123(outs HvxQR:$Qd4),
27124(ins HvxQR:$Qs4),
27125"$Qd4 = not($Qs4)",
27126tc_0ec46cf9, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
27127let Inst{7-2} = 0b000010;
27128let Inst{13-10} = 0b0000;
27129let Inst{31-16} = 0b0001111000000011;
27130let hasNewValue = 1;
27131let opNewValue = 0;
27132let isCVI = 1;
27133let isHVXALU = 1;
27134let isHVXALU2SRC = 1;
27135let DecoderNamespace = "EXT_mmvec";
27136}
27137def V6_pred_or : HInst<
27138(outs HvxQR:$Qd4),
27139(ins HvxQR:$Qs4, HvxQR:$Qt4),
27140"$Qd4 = or($Qs4,$Qt4)",
27141tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27142let Inst{7-2} = 0b000001;
27143let Inst{13-10} = 0b0000;
27144let Inst{21-16} = 0b000011;
27145let Inst{31-24} = 0b00011110;
27146let hasNewValue = 1;
27147let opNewValue = 0;
27148let isCVI = 1;
27149let DecoderNamespace = "EXT_mmvec";
27150}
27151def V6_pred_or_n : HInst<
27152(outs HvxQR:$Qd4),
27153(ins HvxQR:$Qs4, HvxQR:$Qt4),
27154"$Qd4 = or($Qs4,!$Qt4)",
27155tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27156let Inst{7-2} = 0b000100;
27157let Inst{13-10} = 0b0000;
27158let Inst{21-16} = 0b000011;
27159let Inst{31-24} = 0b00011110;
27160let hasNewValue = 1;
27161let opNewValue = 0;
27162let isCVI = 1;
27163let DecoderNamespace = "EXT_mmvec";
27164}
27165def V6_pred_scalar2 : HInst<
27166(outs HvxQR:$Qd4),
27167(ins IntRegs:$Rt32),
27168"$Qd4 = vsetq($Rt32)",
27169tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
27170let Inst{13-2} = 0b000000010001;
27171let Inst{31-21} = 0b00011001101;
27172let hasNewValue = 1;
27173let opNewValue = 0;
27174let isCVI = 1;
27175let DecoderNamespace = "EXT_mmvec";
27176}
27177def V6_pred_scalar2v2 : HInst<
27178(outs HvxQR:$Qd4),
27179(ins IntRegs:$Rt32),
27180"$Qd4 = vsetq2($Rt32)",
27181tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
27182let Inst{13-2} = 0b000000010011;
27183let Inst{31-21} = 0b00011001101;
27184let hasNewValue = 1;
27185let opNewValue = 0;
27186let isCVI = 1;
27187let DecoderNamespace = "EXT_mmvec";
27188}
27189def V6_pred_xor : HInst<
27190(outs HvxQR:$Qd4),
27191(ins HvxQR:$Qs4, HvxQR:$Qt4),
27192"$Qd4 = xor($Qs4,$Qt4)",
27193tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27194let Inst{7-2} = 0b000011;
27195let Inst{13-10} = 0b0000;
27196let Inst{21-16} = 0b000011;
27197let Inst{31-24} = 0b00011110;
27198let hasNewValue = 1;
27199let opNewValue = 0;
27200let isCVI = 1;
27201let DecoderNamespace = "EXT_mmvec";
27202}
27203def V6_shuffeqh : HInst<
27204(outs HvxQR:$Qd4),
27205(ins HvxQR:$Qs4, HvxQR:$Qt4),
27206"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
27207tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27208let Inst{7-2} = 0b000110;
27209let Inst{13-10} = 0b0000;
27210let Inst{21-16} = 0b000011;
27211let Inst{31-24} = 0b00011110;
27212let hasNewValue = 1;
27213let opNewValue = 0;
27214let isCVI = 1;
27215let DecoderNamespace = "EXT_mmvec";
27216}
27217def V6_shuffeqw : HInst<
27218(outs HvxQR:$Qd4),
27219(ins HvxQR:$Qs4, HvxQR:$Qt4),
27220"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
27221tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27222let Inst{7-2} = 0b000111;
27223let Inst{13-10} = 0b0000;
27224let Inst{21-16} = 0b000011;
27225let Inst{31-24} = 0b00011110;
27226let hasNewValue = 1;
27227let opNewValue = 0;
27228let isCVI = 1;
27229let DecoderNamespace = "EXT_mmvec";
27230}
27231def V6_st0 : HInst<
27232(outs),
27233(ins IntRegs:$Rt32, HvxVR:$Vs32),
27234"vmem($Rt32) = $Vs32",
27235PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27236let isCVI = 1;
27237let isPseudo = 1;
27238let isCodeGenOnly = 1;
27239let DecoderNamespace = "EXT_mmvec";
27240}
27241def V6_stn0 : HInst<
27242(outs),
27243(ins IntRegs:$Rt32, HvxVR:$Os8),
27244"vmem($Rt32) = $Os8.new",
27245PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27246let isCVI = 1;
27247let isPseudo = 1;
27248let isCodeGenOnly = 1;
27249let DecoderNamespace = "EXT_mmvec";
27250let opNewValue = 1;
27251}
27252def V6_stnnt0 : HInst<
27253(outs),
27254(ins IntRegs:$Rt32, HvxVR:$Os8),
27255"vmem($Rt32):nt = $Os8.new",
27256PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27257let isCVI = 1;
27258let isPseudo = 1;
27259let isCodeGenOnly = 1;
27260let DecoderNamespace = "EXT_mmvec";
27261let opNewValue = 1;
27262}
27263def V6_stnp0 : HInst<
27264(outs),
27265(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27266"if (!$Pv4) vmem($Rt32) = $Vs32",
27267PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27268let isCVI = 1;
27269let isPseudo = 1;
27270let isCodeGenOnly = 1;
27271let DecoderNamespace = "EXT_mmvec";
27272}
27273def V6_stnpnt0 : HInst<
27274(outs),
27275(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27276"if (!$Pv4) vmem($Rt32):nt = $Vs32",
27277PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27278let isCVI = 1;
27279let isPseudo = 1;
27280let isCodeGenOnly = 1;
27281let DecoderNamespace = "EXT_mmvec";
27282}
27283def V6_stnq0 : HInst<
27284(outs),
27285(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27286"if (!$Qv4) vmem($Rt32) = $Vs32",
27287PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27288let isCVI = 1;
27289let isPseudo = 1;
27290let isCodeGenOnly = 1;
27291let DecoderNamespace = "EXT_mmvec";
27292}
27293def V6_stnqnt0 : HInst<
27294(outs),
27295(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27296"if (!$Qv4) vmem($Rt32):nt = $Vs32",
27297PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27298let isCVI = 1;
27299let isPseudo = 1;
27300let isCodeGenOnly = 1;
27301let DecoderNamespace = "EXT_mmvec";
27302}
27303def V6_stnt0 : HInst<
27304(outs),
27305(ins IntRegs:$Rt32, HvxVR:$Vs32),
27306"vmem($Rt32):nt = $Vs32",
27307PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27308let isCVI = 1;
27309let isPseudo = 1;
27310let isCodeGenOnly = 1;
27311let DecoderNamespace = "EXT_mmvec";
27312}
27313def V6_stp0 : HInst<
27314(outs),
27315(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27316"if ($Pv4) vmem($Rt32) = $Vs32",
27317PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27318let isCVI = 1;
27319let isPseudo = 1;
27320let isCodeGenOnly = 1;
27321let DecoderNamespace = "EXT_mmvec";
27322}
27323def V6_stpnt0 : HInst<
27324(outs),
27325(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27326"if ($Pv4) vmem($Rt32):nt = $Vs32",
27327PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27328let isCVI = 1;
27329let isPseudo = 1;
27330let isCodeGenOnly = 1;
27331let DecoderNamespace = "EXT_mmvec";
27332}
27333def V6_stq0 : HInst<
27334(outs),
27335(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27336"if ($Qv4) vmem($Rt32) = $Vs32",
27337PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27338let isCVI = 1;
27339let isPseudo = 1;
27340let isCodeGenOnly = 1;
27341let DecoderNamespace = "EXT_mmvec";
27342}
27343def V6_stqnt0 : HInst<
27344(outs),
27345(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27346"if ($Qv4) vmem($Rt32):nt = $Vs32",
27347PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27348let isCVI = 1;
27349let isPseudo = 1;
27350let isCodeGenOnly = 1;
27351let DecoderNamespace = "EXT_mmvec";
27352}
27353def V6_stu0 : HInst<
27354(outs),
27355(ins IntRegs:$Rt32, HvxVR:$Vs32),
27356"vmemu($Rt32) = $Vs32",
27357PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27358let isCVI = 1;
27359let isPseudo = 1;
27360let isCodeGenOnly = 1;
27361let DecoderNamespace = "EXT_mmvec";
27362}
27363def V6_stunp0 : HInst<
27364(outs),
27365(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27366"if (!$Pv4) vmemu($Rt32) = $Vs32",
27367PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27368let isCVI = 1;
27369let isPseudo = 1;
27370let isCodeGenOnly = 1;
27371let DecoderNamespace = "EXT_mmvec";
27372}
27373def V6_stup0 : HInst<
27374(outs),
27375(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27376"if ($Pv4) vmemu($Rt32) = $Vs32",
27377PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27378let isCVI = 1;
27379let isPseudo = 1;
27380let isCodeGenOnly = 1;
27381let DecoderNamespace = "EXT_mmvec";
27382}
27383def V6_v10mpyubs10 : HInst<
27384(outs HvxWR:$Vdd32),
27385(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u1_0Imm:$Ii),
27386"$Vdd32.w = v10mpy($Vuu32.ub,$Vvv32.b,#$Ii)",
27387tc_f175e046, TypeCVI_VX>, Requires<[UseHVXV69]> {
27388let hasNewValue = 1;
27389let opNewValue = 0;
27390let isCVI = 1;
27391let isPseudo = 1;
27392let DecoderNamespace = "EXT_mmvec";
27393}
27394def V6_v10mpyubs10_vxx : HInst<
27395(outs HvxWR:$Vxx32),
27396(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u1_0Imm:$Ii),
27397"$Vxx32.w += v10mpy($Vuu32.ub,$Vvv32.b,#$Ii)",
27398tc_4942646a, TypeCVI_VX>, Requires<[UseHVXV69]> {
27399let hasNewValue = 1;
27400let opNewValue = 0;
27401let isAccumulator = 1;
27402let isCVI = 1;
27403let isPseudo = 1;
27404let DecoderNamespace = "EXT_mmvec";
27405let Constraints = "$Vxx32 = $Vxx32in";
27406}
27407def V6_v6mpyhubs10 : HInst<
27408(outs HvxWR:$Vdd32),
27409(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27410"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27411tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27412let Inst{7-7} = 0b1;
27413let Inst{13-13} = 0b1;
27414let Inst{31-21} = 0b00011111010;
27415let hasNewValue = 1;
27416let opNewValue = 0;
27417let isCVI = 1;
27418let DecoderNamespace = "EXT_mmvec";
27419}
27420def V6_v6mpyhubs10_alt : HInst<
27421(outs HvxWR:$Vdd32),
27422(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27423"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):h",
27424PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27425let hasNewValue = 1;
27426let opNewValue = 0;
27427let isCVI = 1;
27428let isPseudo = 1;
27429let isCodeGenOnly = 1;
27430let DecoderNamespace = "EXT_mmvec";
27431}
27432def V6_v6mpyhubs10_vxx : HInst<
27433(outs HvxWR:$Vxx32),
27434(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27435"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27436tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27437let Inst{7-7} = 0b1;
27438let Inst{13-13} = 0b1;
27439let Inst{31-21} = 0b00011111001;
27440let hasNewValue = 1;
27441let opNewValue = 0;
27442let isAccumulator = 1;
27443let isCVI = 1;
27444let DecoderNamespace = "EXT_mmvec";
27445let Constraints = "$Vxx32 = $Vxx32in";
27446}
27447def V6_v6mpyvubs10 : HInst<
27448(outs HvxWR:$Vdd32),
27449(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27450"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27451tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27452let Inst{7-7} = 0b0;
27453let Inst{13-13} = 0b1;
27454let Inst{31-21} = 0b00011111010;
27455let hasNewValue = 1;
27456let opNewValue = 0;
27457let isCVI = 1;
27458let DecoderNamespace = "EXT_mmvec";
27459}
27460def V6_v6mpyvubs10_alt : HInst<
27461(outs HvxWR:$Vdd32),
27462(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27463"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):v",
27464PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27465let hasNewValue = 1;
27466let opNewValue = 0;
27467let isCVI = 1;
27468let isPseudo = 1;
27469let isCodeGenOnly = 1;
27470let DecoderNamespace = "EXT_mmvec";
27471}
27472def V6_v6mpyvubs10_vxx : HInst<
27473(outs HvxWR:$Vxx32),
27474(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27475"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27476tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27477let Inst{7-7} = 0b0;
27478let Inst{13-13} = 0b1;
27479let Inst{31-21} = 0b00011111001;
27480let hasNewValue = 1;
27481let opNewValue = 0;
27482let isAccumulator = 1;
27483let isCVI = 1;
27484let DecoderNamespace = "EXT_mmvec";
27485let Constraints = "$Vxx32 = $Vxx32in";
27486}
27487def V6_vL32Ub_ai : HInst<
27488(outs HvxVR:$Vd32),
27489(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27490"$Vd32 = vmemu($Rt32+#$Ii)",
27491tc_a7e6707d, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]>, PostInc_BaseImm {
27492let Inst{7-5} = 0b111;
27493let Inst{12-11} = 0b00;
27494let Inst{31-21} = 0b00101000000;
27495let hasNewValue = 1;
27496let opNewValue = 0;
27497let addrMode = BaseImmOffset;
27498let accessSize = HVXVectorAccess;
27499let isCVLoad = 1;
27500let isCVI = 1;
27501let mayLoad = 1;
27502let isRestrictNoSlot1Store = 1;
27503let BaseOpcode = "V6_vL32Ub_ai";
27504let CextOpcode = "V6_vL32Ub";
27505let DecoderNamespace = "EXT_mmvec";
27506}
27507def V6_vL32Ub_pi : HInst<
27508(outs HvxVR:$Vd32, IntRegs:$Rx32),
27509(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27510"$Vd32 = vmemu($Rx32++#$Ii)",
27511tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]>, PostInc_BaseImm {
27512let Inst{7-5} = 0b111;
27513let Inst{13-11} = 0b000;
27514let Inst{31-21} = 0b00101001000;
27515let hasNewValue = 1;
27516let opNewValue = 0;
27517let addrMode = PostInc;
27518let accessSize = HVXVectorAccess;
27519let isCVLoad = 1;
27520let isCVI = 1;
27521let mayLoad = 1;
27522let isRestrictNoSlot1Store = 1;
27523let BaseOpcode = "V6_vL32b_pi";
27524let CextOpcode = "V6_vL32Ub";
27525let DecoderNamespace = "EXT_mmvec";
27526let Constraints = "$Rx32 = $Rx32in";
27527}
27528def V6_vL32Ub_ppu : HInst<
27529(outs HvxVR:$Vd32, IntRegs:$Rx32),
27530(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27531"$Vd32 = vmemu($Rx32++$Mu2)",
27532tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
27533let Inst{12-5} = 0b00000111;
27534let Inst{31-21} = 0b00101011000;
27535let hasNewValue = 1;
27536let opNewValue = 0;
27537let addrMode = PostInc;
27538let accessSize = HVXVectorAccess;
27539let isCVLoad = 1;
27540let isCVI = 1;
27541let mayLoad = 1;
27542let isRestrictNoSlot1Store = 1;
27543let DecoderNamespace = "EXT_mmvec";
27544let Constraints = "$Rx32 = $Rx32in";
27545}
27546def V6_vL32b_ai : HInst<
27547(outs HvxVR:$Vd32),
27548(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27549"$Vd32 = vmem($Rt32+#$Ii)",
27550tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27551let Inst{7-5} = 0b000;
27552let Inst{12-11} = 0b00;
27553let Inst{31-21} = 0b00101000000;
27554let hasNewValue = 1;
27555let opNewValue = 0;
27556let addrMode = BaseImmOffset;
27557let accessSize = HVXVectorAccess;
27558let isCVLoad = 1;
27559let isCVI = 1;
27560let isHVXALU = 1;
27561let mayLoad = 1;
27562let isRestrictNoSlot1Store = 1;
27563let BaseOpcode = "V6_vL32b_ai";
27564let CextOpcode = "V6_vL32b";
27565let isCVLoadable = 1;
27566let isPredicable = 1;
27567let DecoderNamespace = "EXT_mmvec";
27568}
27569def V6_vL32b_cur_ai : HInst<
27570(outs HvxVR:$Vd32),
27571(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27572"$Vd32.cur = vmem($Rt32+#$Ii)",
27573tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27574let Inst{7-5} = 0b001;
27575let Inst{12-11} = 0b00;
27576let Inst{31-21} = 0b00101000000;
27577let hasNewValue = 1;
27578let opNewValue = 0;
27579let addrMode = BaseImmOffset;
27580let accessSize = HVXVectorAccess;
27581let isCVLoad = 1;
27582let isCVI = 1;
27583let CVINew = 1;
27584let isHVXALU = 1;
27585let mayLoad = 1;
27586let isRestrictNoSlot1Store = 1;
27587let BaseOpcode = "V6_vL32b_cur_ai";
27588let CextOpcode = "V6_vL32b_cur";
27589let isPredicable = 1;
27590let DecoderNamespace = "EXT_mmvec";
27591}
27592def V6_vL32b_cur_npred_ai : HInst<
27593(outs HvxVR:$Vd32),
27594(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27595"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27596tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27597let Inst{7-5} = 0b101;
27598let Inst{31-21} = 0b00101000100;
27599let isPredicated = 1;
27600let isPredicatedFalse = 1;
27601let hasNewValue = 1;
27602let opNewValue = 0;
27603let addrMode = BaseImmOffset;
27604let accessSize = HVXVectorAccess;
27605let isCVLoad = 1;
27606let isCVI = 1;
27607let CVINew = 1;
27608let isHVXALU = 1;
27609let mayLoad = 1;
27610let isRestrictNoSlot1Store = 1;
27611let BaseOpcode = "V6_vL32b_cur_ai";
27612let DecoderNamespace = "EXT_mmvec";
27613}
27614def V6_vL32b_cur_npred_pi : HInst<
27615(outs HvxVR:$Vd32, IntRegs:$Rx32),
27616(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27617"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27618tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27619let Inst{7-5} = 0b101;
27620let Inst{13-13} = 0b0;
27621let Inst{31-21} = 0b00101001100;
27622let isPredicated = 1;
27623let isPredicatedFalse = 1;
27624let hasNewValue = 1;
27625let opNewValue = 0;
27626let addrMode = PostInc;
27627let accessSize = HVXVectorAccess;
27628let isCVLoad = 1;
27629let isCVI = 1;
27630let CVINew = 1;
27631let isHVXALU = 1;
27632let mayLoad = 1;
27633let isRestrictNoSlot1Store = 1;
27634let BaseOpcode = "V6_vL32b_cur_pi";
27635let DecoderNamespace = "EXT_mmvec";
27636let Constraints = "$Rx32 = $Rx32in";
27637}
27638def V6_vL32b_cur_npred_ppu : HInst<
27639(outs HvxVR:$Vd32, IntRegs:$Rx32),
27640(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27641"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27642tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27643let Inst{10-5} = 0b000101;
27644let Inst{31-21} = 0b00101011100;
27645let isPredicated = 1;
27646let isPredicatedFalse = 1;
27647let hasNewValue = 1;
27648let opNewValue = 0;
27649let addrMode = PostInc;
27650let accessSize = HVXVectorAccess;
27651let isCVLoad = 1;
27652let isCVI = 1;
27653let CVINew = 1;
27654let isHVXALU = 1;
27655let mayLoad = 1;
27656let isRestrictNoSlot1Store = 1;
27657let BaseOpcode = "V6_vL32b_cur_ppu";
27658let DecoderNamespace = "EXT_mmvec";
27659let Constraints = "$Rx32 = $Rx32in";
27660}
27661def V6_vL32b_cur_pi : HInst<
27662(outs HvxVR:$Vd32, IntRegs:$Rx32),
27663(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27664"$Vd32.cur = vmem($Rx32++#$Ii)",
27665tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27666let Inst{7-5} = 0b001;
27667let Inst{13-11} = 0b000;
27668let Inst{31-21} = 0b00101001000;
27669let hasNewValue = 1;
27670let opNewValue = 0;
27671let addrMode = PostInc;
27672let accessSize = HVXVectorAccess;
27673let isCVLoad = 1;
27674let isCVI = 1;
27675let CVINew = 1;
27676let isHVXALU = 1;
27677let mayLoad = 1;
27678let isRestrictNoSlot1Store = 1;
27679let BaseOpcode = "V6_vL32b_cur_pi";
27680let CextOpcode = "V6_vL32b_cur";
27681let isPredicable = 1;
27682let DecoderNamespace = "EXT_mmvec";
27683let Constraints = "$Rx32 = $Rx32in";
27684}
27685def V6_vL32b_cur_ppu : HInst<
27686(outs HvxVR:$Vd32, IntRegs:$Rx32),
27687(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27688"$Vd32.cur = vmem($Rx32++$Mu2)",
27689tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27690let Inst{12-5} = 0b00000001;
27691let Inst{31-21} = 0b00101011000;
27692let hasNewValue = 1;
27693let opNewValue = 0;
27694let addrMode = PostInc;
27695let accessSize = HVXVectorAccess;
27696let isCVLoad = 1;
27697let isCVI = 1;
27698let CVINew = 1;
27699let isHVXALU = 1;
27700let mayLoad = 1;
27701let isRestrictNoSlot1Store = 1;
27702let BaseOpcode = "V6_vL32b_cur_ppu";
27703let isPredicable = 1;
27704let DecoderNamespace = "EXT_mmvec";
27705let Constraints = "$Rx32 = $Rx32in";
27706}
27707def V6_vL32b_cur_pred_ai : HInst<
27708(outs HvxVR:$Vd32),
27709(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27710"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27711tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27712let Inst{7-5} = 0b100;
27713let Inst{31-21} = 0b00101000100;
27714let isPredicated = 1;
27715let hasNewValue = 1;
27716let opNewValue = 0;
27717let addrMode = BaseImmOffset;
27718let accessSize = HVXVectorAccess;
27719let isCVLoad = 1;
27720let isCVI = 1;
27721let CVINew = 1;
27722let isHVXALU = 1;
27723let mayLoad = 1;
27724let isRestrictNoSlot1Store = 1;
27725let BaseOpcode = "V6_vL32b_cur_ai";
27726let DecoderNamespace = "EXT_mmvec";
27727}
27728def V6_vL32b_cur_pred_pi : HInst<
27729(outs HvxVR:$Vd32, IntRegs:$Rx32),
27730(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27731"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27732tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27733let Inst{7-5} = 0b100;
27734let Inst{13-13} = 0b0;
27735let Inst{31-21} = 0b00101001100;
27736let isPredicated = 1;
27737let hasNewValue = 1;
27738let opNewValue = 0;
27739let addrMode = PostInc;
27740let accessSize = HVXVectorAccess;
27741let isCVLoad = 1;
27742let isCVI = 1;
27743let CVINew = 1;
27744let isHVXALU = 1;
27745let mayLoad = 1;
27746let isRestrictNoSlot1Store = 1;
27747let BaseOpcode = "V6_vL32b_cur_pi";
27748let DecoderNamespace = "EXT_mmvec";
27749let Constraints = "$Rx32 = $Rx32in";
27750}
27751def V6_vL32b_cur_pred_ppu : HInst<
27752(outs HvxVR:$Vd32, IntRegs:$Rx32),
27753(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27754"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27755tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27756let Inst{10-5} = 0b000100;
27757let Inst{31-21} = 0b00101011100;
27758let isPredicated = 1;
27759let hasNewValue = 1;
27760let opNewValue = 0;
27761let addrMode = PostInc;
27762let accessSize = HVXVectorAccess;
27763let isCVLoad = 1;
27764let isCVI = 1;
27765let CVINew = 1;
27766let isHVXALU = 1;
27767let mayLoad = 1;
27768let isRestrictNoSlot1Store = 1;
27769let BaseOpcode = "V6_vL32b_cur_ppu";
27770let DecoderNamespace = "EXT_mmvec";
27771let Constraints = "$Rx32 = $Rx32in";
27772}
27773def V6_vL32b_npred_ai : HInst<
27774(outs HvxVR:$Vd32),
27775(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27776"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27777tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27778let Inst{7-5} = 0b011;
27779let Inst{31-21} = 0b00101000100;
27780let isPredicated = 1;
27781let isPredicatedFalse = 1;
27782let hasNewValue = 1;
27783let opNewValue = 0;
27784let addrMode = BaseImmOffset;
27785let accessSize = HVXVectorAccess;
27786let isCVLoad = 1;
27787let isCVI = 1;
27788let isHVXALU = 1;
27789let mayLoad = 1;
27790let isRestrictNoSlot1Store = 1;
27791let BaseOpcode = "V6_vL32b_ai";
27792let DecoderNamespace = "EXT_mmvec";
27793}
27794def V6_vL32b_npred_pi : HInst<
27795(outs HvxVR:$Vd32, IntRegs:$Rx32),
27796(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27797"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27798tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27799let Inst{7-5} = 0b011;
27800let Inst{13-13} = 0b0;
27801let Inst{31-21} = 0b00101001100;
27802let isPredicated = 1;
27803let isPredicatedFalse = 1;
27804let hasNewValue = 1;
27805let opNewValue = 0;
27806let addrMode = PostInc;
27807let accessSize = HVXVectorAccess;
27808let isCVLoad = 1;
27809let isCVI = 1;
27810let isHVXALU = 1;
27811let mayLoad = 1;
27812let isRestrictNoSlot1Store = 1;
27813let BaseOpcode = "V6_vL32b_pi";
27814let DecoderNamespace = "EXT_mmvec";
27815let Constraints = "$Rx32 = $Rx32in";
27816}
27817def V6_vL32b_npred_ppu : HInst<
27818(outs HvxVR:$Vd32, IntRegs:$Rx32),
27819(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27820"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27821tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27822let Inst{10-5} = 0b000011;
27823let Inst{31-21} = 0b00101011100;
27824let isPredicated = 1;
27825let isPredicatedFalse = 1;
27826let hasNewValue = 1;
27827let opNewValue = 0;
27828let addrMode = PostInc;
27829let accessSize = HVXVectorAccess;
27830let isCVLoad = 1;
27831let isCVI = 1;
27832let isHVXALU = 1;
27833let mayLoad = 1;
27834let isRestrictNoSlot1Store = 1;
27835let BaseOpcode = "V6_vL32b_ppu";
27836let DecoderNamespace = "EXT_mmvec";
27837let Constraints = "$Rx32 = $Rx32in";
27838}
27839def V6_vL32b_nt_ai : HInst<
27840(outs HvxVR:$Vd32),
27841(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27842"$Vd32 = vmem($Rt32+#$Ii):nt",
27843tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27844let Inst{7-5} = 0b000;
27845let Inst{12-11} = 0b00;
27846let Inst{31-21} = 0b00101000010;
27847let hasNewValue = 1;
27848let opNewValue = 0;
27849let addrMode = BaseImmOffset;
27850let accessSize = HVXVectorAccess;
27851let isCVLoad = 1;
27852let isCVI = 1;
27853let isHVXALU = 1;
27854let mayLoad = 1;
27855let isNonTemporal = 1;
27856let isRestrictNoSlot1Store = 1;
27857let BaseOpcode = "V6_vL32b_nt_ai";
27858let CextOpcode = "V6_vL32b_nt";
27859let isCVLoadable = 1;
27860let isPredicable = 1;
27861let DecoderNamespace = "EXT_mmvec";
27862}
27863def V6_vL32b_nt_cur_ai : HInst<
27864(outs HvxVR:$Vd32),
27865(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27866"$Vd32.cur = vmem($Rt32+#$Ii):nt",
27867tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27868let Inst{7-5} = 0b001;
27869let Inst{12-11} = 0b00;
27870let Inst{31-21} = 0b00101000010;
27871let hasNewValue = 1;
27872let opNewValue = 0;
27873let addrMode = BaseImmOffset;
27874let accessSize = HVXVectorAccess;
27875let isCVLoad = 1;
27876let isCVI = 1;
27877let CVINew = 1;
27878let isHVXALU = 1;
27879let mayLoad = 1;
27880let isNonTemporal = 1;
27881let isRestrictNoSlot1Store = 1;
27882let BaseOpcode = "V6_vL32b_nt_cur_ai";
27883let CextOpcode = "V6_vL32b_nt_cur";
27884let isPredicable = 1;
27885let DecoderNamespace = "EXT_mmvec";
27886}
27887def V6_vL32b_nt_cur_npred_ai : HInst<
27888(outs HvxVR:$Vd32),
27889(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27890"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27891tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27892let Inst{7-5} = 0b101;
27893let Inst{31-21} = 0b00101000110;
27894let isPredicated = 1;
27895let isPredicatedFalse = 1;
27896let hasNewValue = 1;
27897let opNewValue = 0;
27898let addrMode = BaseImmOffset;
27899let accessSize = HVXVectorAccess;
27900let isCVLoad = 1;
27901let isCVI = 1;
27902let CVINew = 1;
27903let isHVXALU = 1;
27904let mayLoad = 1;
27905let isNonTemporal = 1;
27906let isRestrictNoSlot1Store = 1;
27907let BaseOpcode = "V6_vL32b_nt_cur_ai";
27908let DecoderNamespace = "EXT_mmvec";
27909}
27910def V6_vL32b_nt_cur_npred_pi : HInst<
27911(outs HvxVR:$Vd32, IntRegs:$Rx32),
27912(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27913"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27914tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27915let Inst{7-5} = 0b101;
27916let Inst{13-13} = 0b0;
27917let Inst{31-21} = 0b00101001110;
27918let isPredicated = 1;
27919let isPredicatedFalse = 1;
27920let hasNewValue = 1;
27921let opNewValue = 0;
27922let addrMode = PostInc;
27923let accessSize = HVXVectorAccess;
27924let isCVLoad = 1;
27925let isCVI = 1;
27926let CVINew = 1;
27927let isHVXALU = 1;
27928let mayLoad = 1;
27929let isNonTemporal = 1;
27930let isRestrictNoSlot1Store = 1;
27931let BaseOpcode = "V6_vL32b_nt_cur_pi";
27932let DecoderNamespace = "EXT_mmvec";
27933let Constraints = "$Rx32 = $Rx32in";
27934}
27935def V6_vL32b_nt_cur_npred_ppu : HInst<
27936(outs HvxVR:$Vd32, IntRegs:$Rx32),
27937(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27938"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27939tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27940let Inst{10-5} = 0b000101;
27941let Inst{31-21} = 0b00101011110;
27942let isPredicated = 1;
27943let isPredicatedFalse = 1;
27944let hasNewValue = 1;
27945let opNewValue = 0;
27946let addrMode = PostInc;
27947let accessSize = HVXVectorAccess;
27948let isCVLoad = 1;
27949let isCVI = 1;
27950let CVINew = 1;
27951let isHVXALU = 1;
27952let mayLoad = 1;
27953let isNonTemporal = 1;
27954let isRestrictNoSlot1Store = 1;
27955let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27956let DecoderNamespace = "EXT_mmvec";
27957let Constraints = "$Rx32 = $Rx32in";
27958}
27959def V6_vL32b_nt_cur_pi : HInst<
27960(outs HvxVR:$Vd32, IntRegs:$Rx32),
27961(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27962"$Vd32.cur = vmem($Rx32++#$Ii):nt",
27963tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
27964let Inst{7-5} = 0b001;
27965let Inst{13-11} = 0b000;
27966let Inst{31-21} = 0b00101001010;
27967let hasNewValue = 1;
27968let opNewValue = 0;
27969let addrMode = PostInc;
27970let accessSize = HVXVectorAccess;
27971let isCVLoad = 1;
27972let isCVI = 1;
27973let CVINew = 1;
27974let isHVXALU = 1;
27975let mayLoad = 1;
27976let isNonTemporal = 1;
27977let isRestrictNoSlot1Store = 1;
27978let BaseOpcode = "V6_vL32b_nt_cur_pi";
27979let CextOpcode = "V6_vL32b_nt_cur";
27980let isPredicable = 1;
27981let DecoderNamespace = "EXT_mmvec";
27982let Constraints = "$Rx32 = $Rx32in";
27983}
27984def V6_vL32b_nt_cur_ppu : HInst<
27985(outs HvxVR:$Vd32, IntRegs:$Rx32),
27986(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27987"$Vd32.cur = vmem($Rx32++$Mu2):nt",
27988tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27989let Inst{12-5} = 0b00000001;
27990let Inst{31-21} = 0b00101011010;
27991let hasNewValue = 1;
27992let opNewValue = 0;
27993let addrMode = PostInc;
27994let accessSize = HVXVectorAccess;
27995let isCVLoad = 1;
27996let isCVI = 1;
27997let CVINew = 1;
27998let isHVXALU = 1;
27999let mayLoad = 1;
28000let isNonTemporal = 1;
28001let isRestrictNoSlot1Store = 1;
28002let BaseOpcode = "V6_vL32b_nt_cur_ppu";
28003let isPredicable = 1;
28004let DecoderNamespace = "EXT_mmvec";
28005let Constraints = "$Rx32 = $Rx32in";
28006}
28007def V6_vL32b_nt_cur_pred_ai : HInst<
28008(outs HvxVR:$Vd32),
28009(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28010"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
28011tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28012let Inst{7-5} = 0b100;
28013let Inst{31-21} = 0b00101000110;
28014let isPredicated = 1;
28015let hasNewValue = 1;
28016let opNewValue = 0;
28017let addrMode = BaseImmOffset;
28018let accessSize = HVXVectorAccess;
28019let isCVLoad = 1;
28020let isCVI = 1;
28021let CVINew = 1;
28022let isHVXALU = 1;
28023let mayLoad = 1;
28024let isNonTemporal = 1;
28025let isRestrictNoSlot1Store = 1;
28026let BaseOpcode = "V6_vL32b_nt_cur_ai";
28027let DecoderNamespace = "EXT_mmvec";
28028}
28029def V6_vL32b_nt_cur_pred_pi : HInst<
28030(outs HvxVR:$Vd32, IntRegs:$Rx32),
28031(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28032"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
28033tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28034let Inst{7-5} = 0b100;
28035let Inst{13-13} = 0b0;
28036let Inst{31-21} = 0b00101001110;
28037let isPredicated = 1;
28038let hasNewValue = 1;
28039let opNewValue = 0;
28040let addrMode = PostInc;
28041let accessSize = HVXVectorAccess;
28042let isCVLoad = 1;
28043let isCVI = 1;
28044let CVINew = 1;
28045let isHVXALU = 1;
28046let mayLoad = 1;
28047let isNonTemporal = 1;
28048let isRestrictNoSlot1Store = 1;
28049let BaseOpcode = "V6_vL32b_nt_cur_pi";
28050let DecoderNamespace = "EXT_mmvec";
28051let Constraints = "$Rx32 = $Rx32in";
28052}
28053def V6_vL32b_nt_cur_pred_ppu : HInst<
28054(outs HvxVR:$Vd32, IntRegs:$Rx32),
28055(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28056"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
28057tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28058let Inst{10-5} = 0b000100;
28059let Inst{31-21} = 0b00101011110;
28060let isPredicated = 1;
28061let hasNewValue = 1;
28062let opNewValue = 0;
28063let addrMode = PostInc;
28064let accessSize = HVXVectorAccess;
28065let isCVLoad = 1;
28066let isCVI = 1;
28067let CVINew = 1;
28068let isHVXALU = 1;
28069let mayLoad = 1;
28070let isNonTemporal = 1;
28071let isRestrictNoSlot1Store = 1;
28072let BaseOpcode = "V6_vL32b_nt_cur_ppu";
28073let DecoderNamespace = "EXT_mmvec";
28074let Constraints = "$Rx32 = $Rx32in";
28075}
28076def V6_vL32b_nt_npred_ai : HInst<
28077(outs HvxVR:$Vd32),
28078(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28079"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
28080tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28081let Inst{7-5} = 0b011;
28082let Inst{31-21} = 0b00101000110;
28083let isPredicated = 1;
28084let isPredicatedFalse = 1;
28085let hasNewValue = 1;
28086let opNewValue = 0;
28087let addrMode = BaseImmOffset;
28088let accessSize = HVXVectorAccess;
28089let isCVLoad = 1;
28090let isCVI = 1;
28091let isHVXALU = 1;
28092let mayLoad = 1;
28093let isNonTemporal = 1;
28094let isRestrictNoSlot1Store = 1;
28095let BaseOpcode = "V6_vL32b_nt_ai";
28096let DecoderNamespace = "EXT_mmvec";
28097}
28098def V6_vL32b_nt_npred_pi : HInst<
28099(outs HvxVR:$Vd32, IntRegs:$Rx32),
28100(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28101"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
28102tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28103let Inst{7-5} = 0b011;
28104let Inst{13-13} = 0b0;
28105let Inst{31-21} = 0b00101001110;
28106let isPredicated = 1;
28107let isPredicatedFalse = 1;
28108let hasNewValue = 1;
28109let opNewValue = 0;
28110let addrMode = PostInc;
28111let accessSize = HVXVectorAccess;
28112let isCVLoad = 1;
28113let isCVI = 1;
28114let isHVXALU = 1;
28115let mayLoad = 1;
28116let isNonTemporal = 1;
28117let isRestrictNoSlot1Store = 1;
28118let BaseOpcode = "V6_vL32b_nt_pi";
28119let DecoderNamespace = "EXT_mmvec";
28120let Constraints = "$Rx32 = $Rx32in";
28121}
28122def V6_vL32b_nt_npred_ppu : HInst<
28123(outs HvxVR:$Vd32, IntRegs:$Rx32),
28124(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28125"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28126tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28127let Inst{10-5} = 0b000011;
28128let Inst{31-21} = 0b00101011110;
28129let isPredicated = 1;
28130let isPredicatedFalse = 1;
28131let hasNewValue = 1;
28132let opNewValue = 0;
28133let addrMode = PostInc;
28134let accessSize = HVXVectorAccess;
28135let isCVLoad = 1;
28136let isCVI = 1;
28137let isHVXALU = 1;
28138let mayLoad = 1;
28139let isNonTemporal = 1;
28140let isRestrictNoSlot1Store = 1;
28141let BaseOpcode = "V6_vL32b_nt_ppu";
28142let DecoderNamespace = "EXT_mmvec";
28143let Constraints = "$Rx32 = $Rx32in";
28144}
28145def V6_vL32b_nt_pi : HInst<
28146(outs HvxVR:$Vd32, IntRegs:$Rx32),
28147(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28148"$Vd32 = vmem($Rx32++#$Ii):nt",
28149tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28150let Inst{7-5} = 0b000;
28151let Inst{13-11} = 0b000;
28152let Inst{31-21} = 0b00101001010;
28153let hasNewValue = 1;
28154let opNewValue = 0;
28155let addrMode = PostInc;
28156let accessSize = HVXVectorAccess;
28157let isCVLoad = 1;
28158let isCVI = 1;
28159let isHVXALU = 1;
28160let mayLoad = 1;
28161let isNonTemporal = 1;
28162let isRestrictNoSlot1Store = 1;
28163let BaseOpcode = "V6_vL32b_nt_pi";
28164let CextOpcode = "V6_vL32b_nt";
28165let isCVLoadable = 1;
28166let isPredicable = 1;
28167let DecoderNamespace = "EXT_mmvec";
28168let Constraints = "$Rx32 = $Rx32in";
28169}
28170def V6_vL32b_nt_ppu : HInst<
28171(outs HvxVR:$Vd32, IntRegs:$Rx32),
28172(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28173"$Vd32 = vmem($Rx32++$Mu2):nt",
28174tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28175let Inst{12-5} = 0b00000000;
28176let Inst{31-21} = 0b00101011010;
28177let hasNewValue = 1;
28178let opNewValue = 0;
28179let addrMode = PostInc;
28180let accessSize = HVXVectorAccess;
28181let isCVLoad = 1;
28182let isCVI = 1;
28183let isHVXALU = 1;
28184let mayLoad = 1;
28185let isNonTemporal = 1;
28186let isRestrictNoSlot1Store = 1;
28187let BaseOpcode = "V6_vL32b_nt_ppu";
28188let isCVLoadable = 1;
28189let isPredicable = 1;
28190let DecoderNamespace = "EXT_mmvec";
28191let Constraints = "$Rx32 = $Rx32in";
28192}
28193def V6_vL32b_nt_pred_ai : HInst<
28194(outs HvxVR:$Vd32),
28195(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28196"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
28197tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28198let Inst{7-5} = 0b010;
28199let Inst{31-21} = 0b00101000110;
28200let isPredicated = 1;
28201let hasNewValue = 1;
28202let opNewValue = 0;
28203let addrMode = BaseImmOffset;
28204let accessSize = HVXVectorAccess;
28205let isCVLoad = 1;
28206let isCVI = 1;
28207let isHVXALU = 1;
28208let mayLoad = 1;
28209let isNonTemporal = 1;
28210let isRestrictNoSlot1Store = 1;
28211let BaseOpcode = "V6_vL32b_nt_ai";
28212let DecoderNamespace = "EXT_mmvec";
28213}
28214def V6_vL32b_nt_pred_pi : HInst<
28215(outs HvxVR:$Vd32, IntRegs:$Rx32),
28216(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28217"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
28218tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28219let Inst{7-5} = 0b010;
28220let Inst{13-13} = 0b0;
28221let Inst{31-21} = 0b00101001110;
28222let isPredicated = 1;
28223let hasNewValue = 1;
28224let opNewValue = 0;
28225let addrMode = PostInc;
28226let accessSize = HVXVectorAccess;
28227let isCVLoad = 1;
28228let isCVI = 1;
28229let isHVXALU = 1;
28230let mayLoad = 1;
28231let isNonTemporal = 1;
28232let isRestrictNoSlot1Store = 1;
28233let BaseOpcode = "V6_vL32b_nt_pi";
28234let DecoderNamespace = "EXT_mmvec";
28235let Constraints = "$Rx32 = $Rx32in";
28236}
28237def V6_vL32b_nt_pred_ppu : HInst<
28238(outs HvxVR:$Vd32, IntRegs:$Rx32),
28239(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28240"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28241tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28242let Inst{10-5} = 0b000010;
28243let Inst{31-21} = 0b00101011110;
28244let isPredicated = 1;
28245let hasNewValue = 1;
28246let opNewValue = 0;
28247let addrMode = PostInc;
28248let accessSize = HVXVectorAccess;
28249let isCVLoad = 1;
28250let isCVI = 1;
28251let isHVXALU = 1;
28252let mayLoad = 1;
28253let isNonTemporal = 1;
28254let isRestrictNoSlot1Store = 1;
28255let BaseOpcode = "V6_vL32b_nt_ppu";
28256let DecoderNamespace = "EXT_mmvec";
28257let Constraints = "$Rx32 = $Rx32in";
28258}
28259def V6_vL32b_nt_tmp_ai : HInst<
28260(outs HvxVR:$Vd32),
28261(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28262"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
28263tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28264let Inst{7-5} = 0b010;
28265let Inst{12-11} = 0b00;
28266let Inst{31-21} = 0b00101000010;
28267let hasNewValue = 1;
28268let opNewValue = 0;
28269let addrMode = BaseImmOffset;
28270let accessSize = HVXVectorAccess;
28271let isCVLoad = 1;
28272let isCVI = 1;
28273let hasHvxTmp = 1;
28274let mayLoad = 1;
28275let isNonTemporal = 1;
28276let isRestrictNoSlot1Store = 1;
28277let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28278let CextOpcode = "V6_vL32b_nt_tmp";
28279let isPredicable = 1;
28280let DecoderNamespace = "EXT_mmvec";
28281}
28282def V6_vL32b_nt_tmp_npred_ai : HInst<
28283(outs HvxVR:$Vd32),
28284(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28285"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28286tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28287let Inst{7-5} = 0b111;
28288let Inst{31-21} = 0b00101000110;
28289let isPredicated = 1;
28290let isPredicatedFalse = 1;
28291let hasNewValue = 1;
28292let opNewValue = 0;
28293let addrMode = BaseImmOffset;
28294let accessSize = HVXVectorAccess;
28295let isCVLoad = 1;
28296let isCVI = 1;
28297let hasHvxTmp = 1;
28298let mayLoad = 1;
28299let isNonTemporal = 1;
28300let isRestrictNoSlot1Store = 1;
28301let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28302let DecoderNamespace = "EXT_mmvec";
28303}
28304def V6_vL32b_nt_tmp_npred_pi : HInst<
28305(outs HvxVR:$Vd32, IntRegs:$Rx32),
28306(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28307"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28308tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28309let Inst{7-5} = 0b111;
28310let Inst{13-13} = 0b0;
28311let Inst{31-21} = 0b00101001110;
28312let isPredicated = 1;
28313let isPredicatedFalse = 1;
28314let hasNewValue = 1;
28315let opNewValue = 0;
28316let addrMode = PostInc;
28317let accessSize = HVXVectorAccess;
28318let isCVLoad = 1;
28319let isCVI = 1;
28320let hasHvxTmp = 1;
28321let mayLoad = 1;
28322let isNonTemporal = 1;
28323let isRestrictNoSlot1Store = 1;
28324let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28325let DecoderNamespace = "EXT_mmvec";
28326let Constraints = "$Rx32 = $Rx32in";
28327}
28328def V6_vL32b_nt_tmp_npred_ppu : HInst<
28329(outs HvxVR:$Vd32, IntRegs:$Rx32),
28330(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28331"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28332tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28333let Inst{10-5} = 0b000111;
28334let Inst{31-21} = 0b00101011110;
28335let isPredicated = 1;
28336let isPredicatedFalse = 1;
28337let hasNewValue = 1;
28338let opNewValue = 0;
28339let addrMode = PostInc;
28340let accessSize = HVXVectorAccess;
28341let isCVLoad = 1;
28342let isCVI = 1;
28343let hasHvxTmp = 1;
28344let mayLoad = 1;
28345let isNonTemporal = 1;
28346let isRestrictNoSlot1Store = 1;
28347let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28348let DecoderNamespace = "EXT_mmvec";
28349let Constraints = "$Rx32 = $Rx32in";
28350}
28351def V6_vL32b_nt_tmp_pi : HInst<
28352(outs HvxVR:$Vd32, IntRegs:$Rx32),
28353(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28354"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
28355tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28356let Inst{7-5} = 0b010;
28357let Inst{13-11} = 0b000;
28358let Inst{31-21} = 0b00101001010;
28359let hasNewValue = 1;
28360let opNewValue = 0;
28361let addrMode = PostInc;
28362let accessSize = HVXVectorAccess;
28363let isCVLoad = 1;
28364let isCVI = 1;
28365let hasHvxTmp = 1;
28366let mayLoad = 1;
28367let isNonTemporal = 1;
28368let isRestrictNoSlot1Store = 1;
28369let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28370let CextOpcode = "V6_vL32b_nt_tmp";
28371let isPredicable = 1;
28372let DecoderNamespace = "EXT_mmvec";
28373let Constraints = "$Rx32 = $Rx32in";
28374}
28375def V6_vL32b_nt_tmp_ppu : HInst<
28376(outs HvxVR:$Vd32, IntRegs:$Rx32),
28377(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28378"$Vd32.tmp = vmem($Rx32++$Mu2):nt",
28379tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28380let Inst{12-5} = 0b00000010;
28381let Inst{31-21} = 0b00101011010;
28382let hasNewValue = 1;
28383let opNewValue = 0;
28384let addrMode = PostInc;
28385let accessSize = HVXVectorAccess;
28386let isCVLoad = 1;
28387let isCVI = 1;
28388let hasHvxTmp = 1;
28389let mayLoad = 1;
28390let isNonTemporal = 1;
28391let isRestrictNoSlot1Store = 1;
28392let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28393let isPredicable = 1;
28394let DecoderNamespace = "EXT_mmvec";
28395let Constraints = "$Rx32 = $Rx32in";
28396}
28397def V6_vL32b_nt_tmp_pred_ai : HInst<
28398(outs HvxVR:$Vd32),
28399(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28400"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28401tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28402let Inst{7-5} = 0b110;
28403let Inst{31-21} = 0b00101000110;
28404let isPredicated = 1;
28405let hasNewValue = 1;
28406let opNewValue = 0;
28407let addrMode = BaseImmOffset;
28408let accessSize = HVXVectorAccess;
28409let isCVLoad = 1;
28410let isCVI = 1;
28411let hasHvxTmp = 1;
28412let mayLoad = 1;
28413let isNonTemporal = 1;
28414let isRestrictNoSlot1Store = 1;
28415let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28416let DecoderNamespace = "EXT_mmvec";
28417}
28418def V6_vL32b_nt_tmp_pred_pi : HInst<
28419(outs HvxVR:$Vd32, IntRegs:$Rx32),
28420(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28421"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28422tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28423let Inst{7-5} = 0b110;
28424let Inst{13-13} = 0b0;
28425let Inst{31-21} = 0b00101001110;
28426let isPredicated = 1;
28427let hasNewValue = 1;
28428let opNewValue = 0;
28429let addrMode = PostInc;
28430let accessSize = HVXVectorAccess;
28431let isCVLoad = 1;
28432let isCVI = 1;
28433let hasHvxTmp = 1;
28434let mayLoad = 1;
28435let isNonTemporal = 1;
28436let isRestrictNoSlot1Store = 1;
28437let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28438let DecoderNamespace = "EXT_mmvec";
28439let Constraints = "$Rx32 = $Rx32in";
28440}
28441def V6_vL32b_nt_tmp_pred_ppu : HInst<
28442(outs HvxVR:$Vd32, IntRegs:$Rx32),
28443(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28444"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28445tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28446let Inst{10-5} = 0b000110;
28447let Inst{31-21} = 0b00101011110;
28448let isPredicated = 1;
28449let hasNewValue = 1;
28450let opNewValue = 0;
28451let addrMode = PostInc;
28452let accessSize = HVXVectorAccess;
28453let isCVLoad = 1;
28454let isCVI = 1;
28455let hasHvxTmp = 1;
28456let mayLoad = 1;
28457let isNonTemporal = 1;
28458let isRestrictNoSlot1Store = 1;
28459let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28460let DecoderNamespace = "EXT_mmvec";
28461let Constraints = "$Rx32 = $Rx32in";
28462}
28463def V6_vL32b_pi : HInst<
28464(outs HvxVR:$Vd32, IntRegs:$Rx32),
28465(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28466"$Vd32 = vmem($Rx32++#$Ii)",
28467tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28468let Inst{7-5} = 0b000;
28469let Inst{13-11} = 0b000;
28470let Inst{31-21} = 0b00101001000;
28471let hasNewValue = 1;
28472let opNewValue = 0;
28473let addrMode = PostInc;
28474let accessSize = HVXVectorAccess;
28475let isCVLoad = 1;
28476let isCVI = 1;
28477let isHVXALU = 1;
28478let mayLoad = 1;
28479let isRestrictNoSlot1Store = 1;
28480let BaseOpcode = "V6_vL32b_pi";
28481let CextOpcode = "V6_vL32b";
28482let isCVLoadable = 1;
28483let isPredicable = 1;
28484let DecoderNamespace = "EXT_mmvec";
28485let Constraints = "$Rx32 = $Rx32in";
28486}
28487def V6_vL32b_ppu : HInst<
28488(outs HvxVR:$Vd32, IntRegs:$Rx32),
28489(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28490"$Vd32 = vmem($Rx32++$Mu2)",
28491tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28492let Inst{12-5} = 0b00000000;
28493let Inst{31-21} = 0b00101011000;
28494let hasNewValue = 1;
28495let opNewValue = 0;
28496let addrMode = PostInc;
28497let accessSize = HVXVectorAccess;
28498let isCVLoad = 1;
28499let isCVI = 1;
28500let isHVXALU = 1;
28501let mayLoad = 1;
28502let isRestrictNoSlot1Store = 1;
28503let BaseOpcode = "V6_vL32b_ppu";
28504let isCVLoadable = 1;
28505let isPredicable = 1;
28506let DecoderNamespace = "EXT_mmvec";
28507let Constraints = "$Rx32 = $Rx32in";
28508}
28509def V6_vL32b_pred_ai : HInst<
28510(outs HvxVR:$Vd32),
28511(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28512"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
28513tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28514let Inst{7-5} = 0b010;
28515let Inst{31-21} = 0b00101000100;
28516let isPredicated = 1;
28517let hasNewValue = 1;
28518let opNewValue = 0;
28519let addrMode = BaseImmOffset;
28520let accessSize = HVXVectorAccess;
28521let isCVLoad = 1;
28522let isCVI = 1;
28523let isHVXALU = 1;
28524let mayLoad = 1;
28525let isRestrictNoSlot1Store = 1;
28526let BaseOpcode = "V6_vL32b_ai";
28527let DecoderNamespace = "EXT_mmvec";
28528}
28529def V6_vL32b_pred_pi : HInst<
28530(outs HvxVR:$Vd32, IntRegs:$Rx32),
28531(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28532"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
28533tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28534let Inst{7-5} = 0b010;
28535let Inst{13-13} = 0b0;
28536let Inst{31-21} = 0b00101001100;
28537let isPredicated = 1;
28538let hasNewValue = 1;
28539let opNewValue = 0;
28540let addrMode = PostInc;
28541let accessSize = HVXVectorAccess;
28542let isCVLoad = 1;
28543let isCVI = 1;
28544let isHVXALU = 1;
28545let mayLoad = 1;
28546let isRestrictNoSlot1Store = 1;
28547let BaseOpcode = "V6_vL32b_pi";
28548let DecoderNamespace = "EXT_mmvec";
28549let Constraints = "$Rx32 = $Rx32in";
28550}
28551def V6_vL32b_pred_ppu : HInst<
28552(outs HvxVR:$Vd32, IntRegs:$Rx32),
28553(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28554"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
28555tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28556let Inst{10-5} = 0b000010;
28557let Inst{31-21} = 0b00101011100;
28558let isPredicated = 1;
28559let hasNewValue = 1;
28560let opNewValue = 0;
28561let addrMode = PostInc;
28562let accessSize = HVXVectorAccess;
28563let isCVLoad = 1;
28564let isCVI = 1;
28565let isHVXALU = 1;
28566let mayLoad = 1;
28567let isRestrictNoSlot1Store = 1;
28568let BaseOpcode = "V6_vL32b_ppu";
28569let DecoderNamespace = "EXT_mmvec";
28570let Constraints = "$Rx32 = $Rx32in";
28571}
28572def V6_vL32b_tmp_ai : HInst<
28573(outs HvxVR:$Vd32),
28574(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28575"$Vd32.tmp = vmem($Rt32+#$Ii)",
28576tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28577let Inst{7-5} = 0b010;
28578let Inst{12-11} = 0b00;
28579let Inst{31-21} = 0b00101000000;
28580let hasNewValue = 1;
28581let opNewValue = 0;
28582let addrMode = BaseImmOffset;
28583let accessSize = HVXVectorAccess;
28584let isCVLoad = 1;
28585let isCVI = 1;
28586let hasHvxTmp = 1;
28587let mayLoad = 1;
28588let isRestrictNoSlot1Store = 1;
28589let BaseOpcode = "V6_vL32b_tmp_ai";
28590let CextOpcode = "V6_vL32b_tmp";
28591let isPredicable = 1;
28592let DecoderNamespace = "EXT_mmvec";
28593}
28594def V6_vL32b_tmp_npred_ai : HInst<
28595(outs HvxVR:$Vd32),
28596(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28597"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28598tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28599let Inst{7-5} = 0b111;
28600let Inst{31-21} = 0b00101000100;
28601let isPredicated = 1;
28602let isPredicatedFalse = 1;
28603let hasNewValue = 1;
28604let opNewValue = 0;
28605let addrMode = BaseImmOffset;
28606let accessSize = HVXVectorAccess;
28607let isCVLoad = 1;
28608let isCVI = 1;
28609let hasHvxTmp = 1;
28610let mayLoad = 1;
28611let isRestrictNoSlot1Store = 1;
28612let BaseOpcode = "V6_vL32b_tmp_ai";
28613let DecoderNamespace = "EXT_mmvec";
28614}
28615def V6_vL32b_tmp_npred_pi : HInst<
28616(outs HvxVR:$Vd32, IntRegs:$Rx32),
28617(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28618"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28619tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28620let Inst{7-5} = 0b111;
28621let Inst{13-13} = 0b0;
28622let Inst{31-21} = 0b00101001100;
28623let isPredicated = 1;
28624let isPredicatedFalse = 1;
28625let hasNewValue = 1;
28626let opNewValue = 0;
28627let addrMode = PostInc;
28628let accessSize = HVXVectorAccess;
28629let isCVLoad = 1;
28630let isCVI = 1;
28631let hasHvxTmp = 1;
28632let mayLoad = 1;
28633let isRestrictNoSlot1Store = 1;
28634let BaseOpcode = "V6_vL32b_tmp_pi";
28635let DecoderNamespace = "EXT_mmvec";
28636let Constraints = "$Rx32 = $Rx32in";
28637}
28638def V6_vL32b_tmp_npred_ppu : HInst<
28639(outs HvxVR:$Vd32, IntRegs:$Rx32),
28640(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28641"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28642tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28643let Inst{10-5} = 0b000111;
28644let Inst{31-21} = 0b00101011100;
28645let isPredicated = 1;
28646let isPredicatedFalse = 1;
28647let hasNewValue = 1;
28648let opNewValue = 0;
28649let addrMode = PostInc;
28650let accessSize = HVXVectorAccess;
28651let isCVLoad = 1;
28652let isCVI = 1;
28653let hasHvxTmp = 1;
28654let mayLoad = 1;
28655let isRestrictNoSlot1Store = 1;
28656let BaseOpcode = "V6_vL32b_tmp_ppu";
28657let DecoderNamespace = "EXT_mmvec";
28658let Constraints = "$Rx32 = $Rx32in";
28659}
28660def V6_vL32b_tmp_pi : HInst<
28661(outs HvxVR:$Vd32, IntRegs:$Rx32),
28662(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28663"$Vd32.tmp = vmem($Rx32++#$Ii)",
28664tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel, PostInc_BaseImm {
28665let Inst{7-5} = 0b010;
28666let Inst{13-11} = 0b000;
28667let Inst{31-21} = 0b00101001000;
28668let hasNewValue = 1;
28669let opNewValue = 0;
28670let addrMode = PostInc;
28671let accessSize = HVXVectorAccess;
28672let isCVLoad = 1;
28673let isCVI = 1;
28674let hasHvxTmp = 1;
28675let mayLoad = 1;
28676let isRestrictNoSlot1Store = 1;
28677let BaseOpcode = "V6_vL32b_tmp_pi";
28678let CextOpcode = "V6_vL32b_tmp";
28679let isPredicable = 1;
28680let DecoderNamespace = "EXT_mmvec";
28681let Constraints = "$Rx32 = $Rx32in";
28682}
28683def V6_vL32b_tmp_ppu : HInst<
28684(outs HvxVR:$Vd32, IntRegs:$Rx32),
28685(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28686"$Vd32.tmp = vmem($Rx32++$Mu2)",
28687tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28688let Inst{12-5} = 0b00000010;
28689let Inst{31-21} = 0b00101011000;
28690let hasNewValue = 1;
28691let opNewValue = 0;
28692let addrMode = PostInc;
28693let accessSize = HVXVectorAccess;
28694let isCVLoad = 1;
28695let isCVI = 1;
28696let hasHvxTmp = 1;
28697let mayLoad = 1;
28698let isRestrictNoSlot1Store = 1;
28699let BaseOpcode = "V6_vL32b_tmp_ppu";
28700let isPredicable = 1;
28701let DecoderNamespace = "EXT_mmvec";
28702let Constraints = "$Rx32 = $Rx32in";
28703}
28704def V6_vL32b_tmp_pred_ai : HInst<
28705(outs HvxVR:$Vd32),
28706(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28707"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28708tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28709let Inst{7-5} = 0b110;
28710let Inst{31-21} = 0b00101000100;
28711let isPredicated = 1;
28712let hasNewValue = 1;
28713let opNewValue = 0;
28714let addrMode = BaseImmOffset;
28715let accessSize = HVXVectorAccess;
28716let isCVLoad = 1;
28717let isCVI = 1;
28718let hasHvxTmp = 1;
28719let mayLoad = 1;
28720let isRestrictNoSlot1Store = 1;
28721let BaseOpcode = "V6_vL32b_tmp_ai";
28722let DecoderNamespace = "EXT_mmvec";
28723}
28724def V6_vL32b_tmp_pred_pi : HInst<
28725(outs HvxVR:$Vd32, IntRegs:$Rx32),
28726(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28727"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28728tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28729let Inst{7-5} = 0b110;
28730let Inst{13-13} = 0b0;
28731let Inst{31-21} = 0b00101001100;
28732let isPredicated = 1;
28733let hasNewValue = 1;
28734let opNewValue = 0;
28735let addrMode = PostInc;
28736let accessSize = HVXVectorAccess;
28737let isCVLoad = 1;
28738let isCVI = 1;
28739let hasHvxTmp = 1;
28740let mayLoad = 1;
28741let isRestrictNoSlot1Store = 1;
28742let BaseOpcode = "V6_vL32b_tmp_pi";
28743let DecoderNamespace = "EXT_mmvec";
28744let Constraints = "$Rx32 = $Rx32in";
28745}
28746def V6_vL32b_tmp_pred_ppu : HInst<
28747(outs HvxVR:$Vd32, IntRegs:$Rx32),
28748(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28749"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28750tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28751let Inst{10-5} = 0b000110;
28752let Inst{31-21} = 0b00101011100;
28753let isPredicated = 1;
28754let hasNewValue = 1;
28755let opNewValue = 0;
28756let addrMode = PostInc;
28757let accessSize = HVXVectorAccess;
28758let isCVLoad = 1;
28759let isCVI = 1;
28760let hasHvxTmp = 1;
28761let mayLoad = 1;
28762let isRestrictNoSlot1Store = 1;
28763let BaseOpcode = "V6_vL32b_tmp_ppu";
28764let DecoderNamespace = "EXT_mmvec";
28765let Constraints = "$Rx32 = $Rx32in";
28766}
28767def V6_vS32Ub_ai : HInst<
28768(outs),
28769(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28770"vmemu($Rt32+#$Ii) = $Vs32",
28771tc_f21e8abb, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28772let Inst{7-5} = 0b111;
28773let Inst{12-11} = 0b00;
28774let Inst{31-21} = 0b00101000001;
28775let addrMode = BaseImmOffset;
28776let accessSize = HVXVectorAccess;
28777let isCVI = 1;
28778let mayStore = 1;
28779let BaseOpcode = "V6_vS32Ub_ai";
28780let CextOpcode = "V6_vS32Ub";
28781let isPredicable = 1;
28782let DecoderNamespace = "EXT_mmvec";
28783}
28784def V6_vS32Ub_npred_ai : HInst<
28785(outs),
28786(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28787"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28788tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28789let Inst{7-5} = 0b111;
28790let Inst{31-21} = 0b00101000101;
28791let isPredicated = 1;
28792let isPredicatedFalse = 1;
28793let addrMode = BaseImmOffset;
28794let accessSize = HVXVectorAccess;
28795let isCVI = 1;
28796let mayStore = 1;
28797let BaseOpcode = "V6_vS32Ub_ai";
28798let DecoderNamespace = "EXT_mmvec";
28799}
28800def V6_vS32Ub_npred_pi : HInst<
28801(outs IntRegs:$Rx32),
28802(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28803"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28804tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28805let Inst{7-5} = 0b111;
28806let Inst{13-13} = 0b0;
28807let Inst{31-21} = 0b00101001101;
28808let isPredicated = 1;
28809let isPredicatedFalse = 1;
28810let addrMode = PostInc;
28811let accessSize = HVXVectorAccess;
28812let isCVI = 1;
28813let mayStore = 1;
28814let BaseOpcode = "V6_vS32Ub_pi";
28815let DecoderNamespace = "EXT_mmvec";
28816let Constraints = "$Rx32 = $Rx32in";
28817}
28818def V6_vS32Ub_npred_ppu : HInst<
28819(outs IntRegs:$Rx32),
28820(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28821"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28822tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28823let Inst{10-5} = 0b000111;
28824let Inst{31-21} = 0b00101011101;
28825let isPredicated = 1;
28826let isPredicatedFalse = 1;
28827let addrMode = PostInc;
28828let accessSize = HVXVectorAccess;
28829let isCVI = 1;
28830let mayStore = 1;
28831let BaseOpcode = "V6_vS32Ub_ppu";
28832let DecoderNamespace = "EXT_mmvec";
28833let Constraints = "$Rx32 = $Rx32in";
28834}
28835def V6_vS32Ub_pi : HInst<
28836(outs IntRegs:$Rx32),
28837(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28838"vmemu($Rx32++#$Ii) = $Vs32",
28839tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28840let Inst{7-5} = 0b111;
28841let Inst{13-11} = 0b000;
28842let Inst{31-21} = 0b00101001001;
28843let addrMode = PostInc;
28844let accessSize = HVXVectorAccess;
28845let isCVI = 1;
28846let mayStore = 1;
28847let BaseOpcode = "V6_vS32Ub_pi";
28848let CextOpcode = "V6_vS32Ub";
28849let isPredicable = 1;
28850let DecoderNamespace = "EXT_mmvec";
28851let Constraints = "$Rx32 = $Rx32in";
28852}
28853def V6_vS32Ub_ppu : HInst<
28854(outs IntRegs:$Rx32),
28855(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28856"vmemu($Rx32++$Mu2) = $Vs32",
28857tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28858let Inst{12-5} = 0b00000111;
28859let Inst{31-21} = 0b00101011001;
28860let addrMode = PostInc;
28861let accessSize = HVXVectorAccess;
28862let isCVI = 1;
28863let mayStore = 1;
28864let BaseOpcode = "V6_vS32Ub_ppu";
28865let isPredicable = 1;
28866let DecoderNamespace = "EXT_mmvec";
28867let Constraints = "$Rx32 = $Rx32in";
28868}
28869def V6_vS32Ub_pred_ai : HInst<
28870(outs),
28871(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28872"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28873tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28874let Inst{7-5} = 0b110;
28875let Inst{31-21} = 0b00101000101;
28876let isPredicated = 1;
28877let addrMode = BaseImmOffset;
28878let accessSize = HVXVectorAccess;
28879let isCVI = 1;
28880let mayStore = 1;
28881let BaseOpcode = "V6_vS32Ub_ai";
28882let DecoderNamespace = "EXT_mmvec";
28883}
28884def V6_vS32Ub_pred_pi : HInst<
28885(outs IntRegs:$Rx32),
28886(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28887"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28888tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28889let Inst{7-5} = 0b110;
28890let Inst{13-13} = 0b0;
28891let Inst{31-21} = 0b00101001101;
28892let isPredicated = 1;
28893let addrMode = PostInc;
28894let accessSize = HVXVectorAccess;
28895let isCVI = 1;
28896let mayStore = 1;
28897let BaseOpcode = "V6_vS32Ub_pi";
28898let DecoderNamespace = "EXT_mmvec";
28899let Constraints = "$Rx32 = $Rx32in";
28900}
28901def V6_vS32Ub_pred_ppu : HInst<
28902(outs IntRegs:$Rx32),
28903(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28904"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28905tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28906let Inst{10-5} = 0b000110;
28907let Inst{31-21} = 0b00101011101;
28908let isPredicated = 1;
28909let addrMode = PostInc;
28910let accessSize = HVXVectorAccess;
28911let isCVI = 1;
28912let mayStore = 1;
28913let BaseOpcode = "V6_vS32Ub_ppu";
28914let DecoderNamespace = "EXT_mmvec";
28915let Constraints = "$Rx32 = $Rx32in";
28916}
28917def V6_vS32b_ai : HInst<
28918(outs),
28919(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28920"vmem($Rt32+#$Ii) = $Vs32",
28921tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28922let Inst{7-5} = 0b000;
28923let Inst{12-11} = 0b00;
28924let Inst{31-21} = 0b00101000001;
28925let addrMode = BaseImmOffset;
28926let accessSize = HVXVectorAccess;
28927let isCVI = 1;
28928let isHVXALU = 1;
28929let mayStore = 1;
28930let BaseOpcode = "V6_vS32b_ai";
28931let CextOpcode = "V6_vS32b";
28932let isNVStorable = 1;
28933let isPredicable = 1;
28934let DecoderNamespace = "EXT_mmvec";
28935}
28936def V6_vS32b_new_ai : HInst<
28937(outs),
28938(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28939"vmem($Rt32+#$Ii) = $Os8.new",
28940tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
28941let Inst{7-3} = 0b00100;
28942let Inst{12-11} = 0b00;
28943let Inst{31-21} = 0b00101000001;
28944let addrMode = BaseImmOffset;
28945let accessSize = HVXVectorAccess;
28946let isNVStore = 1;
28947let isCVI = 1;
28948let CVINew = 1;
28949let isNewValue = 1;
28950let mayStore = 1;
28951let BaseOpcode = "V6_vS32b_ai";
28952let CextOpcode = "V6_vS32b_new";
28953let isPredicable = 1;
28954let DecoderNamespace = "EXT_mmvec";
28955let opNewValue = 2;
28956}
28957def V6_vS32b_new_npred_ai : HInst<
28958(outs),
28959(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28960"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28961tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28962let Inst{7-3} = 0b01101;
28963let Inst{31-21} = 0b00101000101;
28964let isPredicated = 1;
28965let isPredicatedFalse = 1;
28966let addrMode = BaseImmOffset;
28967let accessSize = HVXVectorAccess;
28968let isNVStore = 1;
28969let isCVI = 1;
28970let CVINew = 1;
28971let isNewValue = 1;
28972let mayStore = 1;
28973let BaseOpcode = "V6_vS32b_ai";
28974let DecoderNamespace = "EXT_mmvec";
28975let opNewValue = 3;
28976}
28977def V6_vS32b_new_npred_pi : HInst<
28978(outs IntRegs:$Rx32),
28979(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28980"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28981tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28982let Inst{7-3} = 0b01101;
28983let Inst{13-13} = 0b0;
28984let Inst{31-21} = 0b00101001101;
28985let isPredicated = 1;
28986let isPredicatedFalse = 1;
28987let addrMode = PostInc;
28988let accessSize = HVXVectorAccess;
28989let isNVStore = 1;
28990let isCVI = 1;
28991let CVINew = 1;
28992let isNewValue = 1;
28993let mayStore = 1;
28994let BaseOpcode = "V6_vS32b_pi";
28995let DecoderNamespace = "EXT_mmvec";
28996let opNewValue = 4;
28997let Constraints = "$Rx32 = $Rx32in";
28998}
28999def V6_vS32b_new_npred_ppu : HInst<
29000(outs IntRegs:$Rx32),
29001(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29002"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
29003tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29004let Inst{10-3} = 0b00001101;
29005let Inst{31-21} = 0b00101011101;
29006let isPredicated = 1;
29007let isPredicatedFalse = 1;
29008let addrMode = PostInc;
29009let accessSize = HVXVectorAccess;
29010let isNVStore = 1;
29011let isCVI = 1;
29012let CVINew = 1;
29013let isNewValue = 1;
29014let mayStore = 1;
29015let BaseOpcode = "V6_vS32b_ppu";
29016let DecoderNamespace = "EXT_mmvec";
29017let opNewValue = 4;
29018let Constraints = "$Rx32 = $Rx32in";
29019}
29020def V6_vS32b_new_pi : HInst<
29021(outs IntRegs:$Rx32),
29022(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29023"vmem($Rx32++#$Ii) = $Os8.new",
29024tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29025let Inst{7-3} = 0b00100;
29026let Inst{13-11} = 0b000;
29027let Inst{31-21} = 0b00101001001;
29028let addrMode = PostInc;
29029let accessSize = HVXVectorAccess;
29030let isNVStore = 1;
29031let isCVI = 1;
29032let CVINew = 1;
29033let isNewValue = 1;
29034let mayStore = 1;
29035let BaseOpcode = "V6_vS32b_pi";
29036let CextOpcode = "V6_vS32b_new";
29037let isPredicable = 1;
29038let DecoderNamespace = "EXT_mmvec";
29039let opNewValue = 3;
29040let Constraints = "$Rx32 = $Rx32in";
29041}
29042def V6_vS32b_new_ppu : HInst<
29043(outs IntRegs:$Rx32),
29044(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29045"vmem($Rx32++$Mu2) = $Os8.new",
29046tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
29047let Inst{12-3} = 0b0000000100;
29048let Inst{31-21} = 0b00101011001;
29049let addrMode = PostInc;
29050let accessSize = HVXVectorAccess;
29051let isNVStore = 1;
29052let isCVI = 1;
29053let CVINew = 1;
29054let isNewValue = 1;
29055let mayStore = 1;
29056let BaseOpcode = "V6_vS32b_ppu";
29057let isPredicable = 1;
29058let DecoderNamespace = "EXT_mmvec";
29059let opNewValue = 3;
29060let Constraints = "$Rx32 = $Rx32in";
29061}
29062def V6_vS32b_new_pred_ai : HInst<
29063(outs),
29064(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29065"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
29066tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29067let Inst{7-3} = 0b01000;
29068let Inst{31-21} = 0b00101000101;
29069let isPredicated = 1;
29070let addrMode = BaseImmOffset;
29071let accessSize = HVXVectorAccess;
29072let isNVStore = 1;
29073let isCVI = 1;
29074let CVINew = 1;
29075let isNewValue = 1;
29076let mayStore = 1;
29077let BaseOpcode = "V6_vS32b_ai";
29078let DecoderNamespace = "EXT_mmvec";
29079let opNewValue = 3;
29080}
29081def V6_vS32b_new_pred_pi : HInst<
29082(outs IntRegs:$Rx32),
29083(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29084"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
29085tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29086let Inst{7-3} = 0b01000;
29087let Inst{13-13} = 0b0;
29088let Inst{31-21} = 0b00101001101;
29089let isPredicated = 1;
29090let addrMode = PostInc;
29091let accessSize = HVXVectorAccess;
29092let isNVStore = 1;
29093let isCVI = 1;
29094let CVINew = 1;
29095let isNewValue = 1;
29096let mayStore = 1;
29097let BaseOpcode = "V6_vS32b_pi";
29098let DecoderNamespace = "EXT_mmvec";
29099let opNewValue = 4;
29100let Constraints = "$Rx32 = $Rx32in";
29101}
29102def V6_vS32b_new_pred_ppu : HInst<
29103(outs IntRegs:$Rx32),
29104(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29105"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
29106tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29107let Inst{10-3} = 0b00001000;
29108let Inst{31-21} = 0b00101011101;
29109let isPredicated = 1;
29110let addrMode = PostInc;
29111let accessSize = HVXVectorAccess;
29112let isNVStore = 1;
29113let isCVI = 1;
29114let CVINew = 1;
29115let isNewValue = 1;
29116let mayStore = 1;
29117let BaseOpcode = "V6_vS32b_ppu";
29118let DecoderNamespace = "EXT_mmvec";
29119let opNewValue = 4;
29120let Constraints = "$Rx32 = $Rx32in";
29121}
29122def V6_vS32b_npred_ai : HInst<
29123(outs),
29124(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29125"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
29126tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29127let Inst{7-5} = 0b001;
29128let Inst{31-21} = 0b00101000101;
29129let isPredicated = 1;
29130let isPredicatedFalse = 1;
29131let addrMode = BaseImmOffset;
29132let accessSize = HVXVectorAccess;
29133let isCVI = 1;
29134let isHVXALU = 1;
29135let mayStore = 1;
29136let BaseOpcode = "V6_vS32b_ai";
29137let isNVStorable = 1;
29138let DecoderNamespace = "EXT_mmvec";
29139}
29140def V6_vS32b_npred_pi : HInst<
29141(outs IntRegs:$Rx32),
29142(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29143"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
29144tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29145let Inst{7-5} = 0b001;
29146let Inst{13-13} = 0b0;
29147let Inst{31-21} = 0b00101001101;
29148let isPredicated = 1;
29149let isPredicatedFalse = 1;
29150let addrMode = PostInc;
29151let accessSize = HVXVectorAccess;
29152let isCVI = 1;
29153let isHVXALU = 1;
29154let mayStore = 1;
29155let BaseOpcode = "V6_vS32b_pi";
29156let isNVStorable = 1;
29157let DecoderNamespace = "EXT_mmvec";
29158let Constraints = "$Rx32 = $Rx32in";
29159}
29160def V6_vS32b_npred_ppu : HInst<
29161(outs IntRegs:$Rx32),
29162(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29163"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
29164tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29165let Inst{10-5} = 0b000001;
29166let Inst{31-21} = 0b00101011101;
29167let isPredicated = 1;
29168let isPredicatedFalse = 1;
29169let addrMode = PostInc;
29170let accessSize = HVXVectorAccess;
29171let isCVI = 1;
29172let isHVXALU = 1;
29173let mayStore = 1;
29174let BaseOpcode = "V6_vS32b_ppu";
29175let isNVStorable = 1;
29176let DecoderNamespace = "EXT_mmvec";
29177let Constraints = "$Rx32 = $Rx32in";
29178}
29179def V6_vS32b_nqpred_ai : HInst<
29180(outs),
29181(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29182"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
29183tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29184let Inst{7-5} = 0b001;
29185let Inst{31-21} = 0b00101000100;
29186let addrMode = BaseImmOffset;
29187let accessSize = HVXVectorAccess;
29188let isCVI = 1;
29189let isHVXALU = 1;
29190let mayStore = 1;
29191let DecoderNamespace = "EXT_mmvec";
29192}
29193def V6_vS32b_nqpred_pi : HInst<
29194(outs IntRegs:$Rx32),
29195(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29196"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
29197tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29198let Inst{7-5} = 0b001;
29199let Inst{13-13} = 0b0;
29200let Inst{31-21} = 0b00101001100;
29201let addrMode = PostInc;
29202let accessSize = HVXVectorAccess;
29203let isCVI = 1;
29204let isHVXALU = 1;
29205let mayStore = 1;
29206let DecoderNamespace = "EXT_mmvec";
29207let Constraints = "$Rx32 = $Rx32in";
29208}
29209def V6_vS32b_nqpred_ppu : HInst<
29210(outs IntRegs:$Rx32),
29211(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29212"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
29213tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29214let Inst{10-5} = 0b000001;
29215let Inst{31-21} = 0b00101011100;
29216let addrMode = PostInc;
29217let accessSize = HVXVectorAccess;
29218let isCVI = 1;
29219let isHVXALU = 1;
29220let mayStore = 1;
29221let DecoderNamespace = "EXT_mmvec";
29222let Constraints = "$Rx32 = $Rx32in";
29223}
29224def V6_vS32b_nt_ai : HInst<
29225(outs),
29226(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29227"vmem($Rt32+#$Ii):nt = $Vs32",
29228tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29229let Inst{7-5} = 0b000;
29230let Inst{12-11} = 0b00;
29231let Inst{31-21} = 0b00101000011;
29232let addrMode = BaseImmOffset;
29233let accessSize = HVXVectorAccess;
29234let isCVI = 1;
29235let isHVXALU = 1;
29236let isNonTemporal = 1;
29237let mayStore = 1;
29238let BaseOpcode = "V6_vS32b_ai";
29239let CextOpcode = "V6_vS32b_nt";
29240let isNVStorable = 1;
29241let isPredicable = 1;
29242let DecoderNamespace = "EXT_mmvec";
29243}
29244def V6_vS32b_nt_new_ai : HInst<
29245(outs),
29246(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29247"vmem($Rt32+#$Ii):nt = $Os8.new",
29248tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29249let Inst{7-3} = 0b00100;
29250let Inst{12-11} = 0b00;
29251let Inst{31-21} = 0b00101000011;
29252let addrMode = BaseImmOffset;
29253let accessSize = HVXVectorAccess;
29254let isNVStore = 1;
29255let isCVI = 1;
29256let CVINew = 1;
29257let isNewValue = 1;
29258let isNonTemporal = 1;
29259let mayStore = 1;
29260let BaseOpcode = "V6_vS32b_ai";
29261let CextOpcode = "V6_vS32b_nt_new";
29262let isPredicable = 1;
29263let DecoderNamespace = "EXT_mmvec";
29264let opNewValue = 2;
29265}
29266def V6_vS32b_nt_new_npred_ai : HInst<
29267(outs),
29268(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29269"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29270tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29271let Inst{7-3} = 0b01111;
29272let Inst{31-21} = 0b00101000111;
29273let isPredicated = 1;
29274let isPredicatedFalse = 1;
29275let addrMode = BaseImmOffset;
29276let accessSize = HVXVectorAccess;
29277let isNVStore = 1;
29278let isCVI = 1;
29279let CVINew = 1;
29280let isNewValue = 1;
29281let isNonTemporal = 1;
29282let mayStore = 1;
29283let BaseOpcode = "V6_vS32b_ai";
29284let DecoderNamespace = "EXT_mmvec";
29285let opNewValue = 3;
29286}
29287def V6_vS32b_nt_new_npred_pi : HInst<
29288(outs IntRegs:$Rx32),
29289(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29290"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29291tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29292let Inst{7-3} = 0b01111;
29293let Inst{13-13} = 0b0;
29294let Inst{31-21} = 0b00101001111;
29295let isPredicated = 1;
29296let isPredicatedFalse = 1;
29297let addrMode = PostInc;
29298let accessSize = HVXVectorAccess;
29299let isNVStore = 1;
29300let isCVI = 1;
29301let CVINew = 1;
29302let isNewValue = 1;
29303let isNonTemporal = 1;
29304let mayStore = 1;
29305let BaseOpcode = "V6_vS32b_pi";
29306let DecoderNamespace = "EXT_mmvec";
29307let opNewValue = 4;
29308let Constraints = "$Rx32 = $Rx32in";
29309}
29310def V6_vS32b_nt_new_npred_ppu : HInst<
29311(outs IntRegs:$Rx32),
29312(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29313"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29314tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29315let Inst{10-3} = 0b00001111;
29316let Inst{31-21} = 0b00101011111;
29317let isPredicated = 1;
29318let isPredicatedFalse = 1;
29319let addrMode = PostInc;
29320let accessSize = HVXVectorAccess;
29321let isNVStore = 1;
29322let isCVI = 1;
29323let CVINew = 1;
29324let isNewValue = 1;
29325let isNonTemporal = 1;
29326let mayStore = 1;
29327let BaseOpcode = "V6_vS32b_ppu";
29328let DecoderNamespace = "EXT_mmvec";
29329let opNewValue = 4;
29330let Constraints = "$Rx32 = $Rx32in";
29331}
29332def V6_vS32b_nt_new_pi : HInst<
29333(outs IntRegs:$Rx32),
29334(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29335"vmem($Rx32++#$Ii):nt = $Os8.new",
29336tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29337let Inst{7-3} = 0b00100;
29338let Inst{13-11} = 0b000;
29339let Inst{31-21} = 0b00101001011;
29340let addrMode = PostInc;
29341let accessSize = HVXVectorAccess;
29342let isNVStore = 1;
29343let isCVI = 1;
29344let CVINew = 1;
29345let isNewValue = 1;
29346let isNonTemporal = 1;
29347let mayStore = 1;
29348let BaseOpcode = "V6_vS32b_pi";
29349let CextOpcode = "V6_vS32b_nt_new";
29350let isPredicable = 1;
29351let DecoderNamespace = "EXT_mmvec";
29352let opNewValue = 3;
29353let Constraints = "$Rx32 = $Rx32in";
29354}
29355def V6_vS32b_nt_new_ppu : HInst<
29356(outs IntRegs:$Rx32),
29357(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29358"vmem($Rx32++$Mu2):nt = $Os8.new",
29359tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
29360let Inst{12-3} = 0b0000000100;
29361let Inst{31-21} = 0b00101011011;
29362let addrMode = PostInc;
29363let accessSize = HVXVectorAccess;
29364let isNVStore = 1;
29365let isCVI = 1;
29366let CVINew = 1;
29367let isNewValue = 1;
29368let isNonTemporal = 1;
29369let mayStore = 1;
29370let BaseOpcode = "V6_vS32b_ppu";
29371let isPredicable = 1;
29372let DecoderNamespace = "EXT_mmvec";
29373let opNewValue = 3;
29374let Constraints = "$Rx32 = $Rx32in";
29375}
29376def V6_vS32b_nt_new_pred_ai : HInst<
29377(outs),
29378(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29379"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29380tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29381let Inst{7-3} = 0b01010;
29382let Inst{31-21} = 0b00101000111;
29383let isPredicated = 1;
29384let addrMode = BaseImmOffset;
29385let accessSize = HVXVectorAccess;
29386let isNVStore = 1;
29387let isCVI = 1;
29388let CVINew = 1;
29389let isNewValue = 1;
29390let isNonTemporal = 1;
29391let mayStore = 1;
29392let BaseOpcode = "V6_vS32b_ai";
29393let DecoderNamespace = "EXT_mmvec";
29394let opNewValue = 3;
29395}
29396def V6_vS32b_nt_new_pred_pi : HInst<
29397(outs IntRegs:$Rx32),
29398(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29399"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29400tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29401let Inst{7-3} = 0b01010;
29402let Inst{13-13} = 0b0;
29403let Inst{31-21} = 0b00101001111;
29404let isPredicated = 1;
29405let addrMode = PostInc;
29406let accessSize = HVXVectorAccess;
29407let isNVStore = 1;
29408let isCVI = 1;
29409let CVINew = 1;
29410let isNewValue = 1;
29411let isNonTemporal = 1;
29412let mayStore = 1;
29413let BaseOpcode = "V6_vS32b_pi";
29414let DecoderNamespace = "EXT_mmvec";
29415let opNewValue = 4;
29416let Constraints = "$Rx32 = $Rx32in";
29417}
29418def V6_vS32b_nt_new_pred_ppu : HInst<
29419(outs IntRegs:$Rx32),
29420(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29421"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29422tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29423let Inst{10-3} = 0b00001010;
29424let Inst{31-21} = 0b00101011111;
29425let isPredicated = 1;
29426let addrMode = PostInc;
29427let accessSize = HVXVectorAccess;
29428let isNVStore = 1;
29429let isCVI = 1;
29430let CVINew = 1;
29431let isNewValue = 1;
29432let isNonTemporal = 1;
29433let mayStore = 1;
29434let BaseOpcode = "V6_vS32b_ppu";
29435let DecoderNamespace = "EXT_mmvec";
29436let opNewValue = 4;
29437let Constraints = "$Rx32 = $Rx32in";
29438}
29439def V6_vS32b_nt_npred_ai : HInst<
29440(outs),
29441(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29442"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29443tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29444let Inst{7-5} = 0b001;
29445let Inst{31-21} = 0b00101000111;
29446let isPredicated = 1;
29447let isPredicatedFalse = 1;
29448let addrMode = BaseImmOffset;
29449let accessSize = HVXVectorAccess;
29450let isCVI = 1;
29451let isHVXALU = 1;
29452let isNonTemporal = 1;
29453let mayStore = 1;
29454let BaseOpcode = "V6_vS32b_ai";
29455let isNVStorable = 1;
29456let DecoderNamespace = "EXT_mmvec";
29457}
29458def V6_vS32b_nt_npred_pi : HInst<
29459(outs IntRegs:$Rx32),
29460(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29461"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29462tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29463let Inst{7-5} = 0b001;
29464let Inst{13-13} = 0b0;
29465let Inst{31-21} = 0b00101001111;
29466let isPredicated = 1;
29467let isPredicatedFalse = 1;
29468let addrMode = PostInc;
29469let accessSize = HVXVectorAccess;
29470let isCVI = 1;
29471let isHVXALU = 1;
29472let isNonTemporal = 1;
29473let mayStore = 1;
29474let BaseOpcode = "V6_vS32b_pi";
29475let isNVStorable = 1;
29476let DecoderNamespace = "EXT_mmvec";
29477let Constraints = "$Rx32 = $Rx32in";
29478}
29479def V6_vS32b_nt_npred_ppu : HInst<
29480(outs IntRegs:$Rx32),
29481(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29482"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29483tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29484let Inst{10-5} = 0b000001;
29485let Inst{31-21} = 0b00101011111;
29486let isPredicated = 1;
29487let isPredicatedFalse = 1;
29488let addrMode = PostInc;
29489let accessSize = HVXVectorAccess;
29490let isCVI = 1;
29491let isHVXALU = 1;
29492let isNonTemporal = 1;
29493let mayStore = 1;
29494let BaseOpcode = "V6_vS32b_ppu";
29495let isNVStorable = 1;
29496let DecoderNamespace = "EXT_mmvec";
29497let Constraints = "$Rx32 = $Rx32in";
29498}
29499def V6_vS32b_nt_nqpred_ai : HInst<
29500(outs),
29501(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29502"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29503tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29504let Inst{7-5} = 0b001;
29505let Inst{31-21} = 0b00101000110;
29506let addrMode = BaseImmOffset;
29507let accessSize = HVXVectorAccess;
29508let isCVI = 1;
29509let isHVXALU = 1;
29510let isNonTemporal = 1;
29511let mayStore = 1;
29512let DecoderNamespace = "EXT_mmvec";
29513}
29514def V6_vS32b_nt_nqpred_pi : HInst<
29515(outs IntRegs:$Rx32),
29516(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29517"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29518tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29519let Inst{7-5} = 0b001;
29520let Inst{13-13} = 0b0;
29521let Inst{31-21} = 0b00101001110;
29522let addrMode = PostInc;
29523let accessSize = HVXVectorAccess;
29524let isCVI = 1;
29525let isHVXALU = 1;
29526let isNonTemporal = 1;
29527let mayStore = 1;
29528let DecoderNamespace = "EXT_mmvec";
29529let Constraints = "$Rx32 = $Rx32in";
29530}
29531def V6_vS32b_nt_nqpred_ppu : HInst<
29532(outs IntRegs:$Rx32),
29533(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29534"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29535tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29536let Inst{10-5} = 0b000001;
29537let Inst{31-21} = 0b00101011110;
29538let addrMode = PostInc;
29539let accessSize = HVXVectorAccess;
29540let isCVI = 1;
29541let isHVXALU = 1;
29542let isNonTemporal = 1;
29543let mayStore = 1;
29544let DecoderNamespace = "EXT_mmvec";
29545let Constraints = "$Rx32 = $Rx32in";
29546}
29547def V6_vS32b_nt_pi : HInst<
29548(outs IntRegs:$Rx32),
29549(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29550"vmem($Rx32++#$Ii):nt = $Vs32",
29551tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29552let Inst{7-5} = 0b000;
29553let Inst{13-11} = 0b000;
29554let Inst{31-21} = 0b00101001011;
29555let addrMode = PostInc;
29556let accessSize = HVXVectorAccess;
29557let isCVI = 1;
29558let isHVXALU = 1;
29559let isNonTemporal = 1;
29560let mayStore = 1;
29561let BaseOpcode = "V6_vS32b_pi";
29562let CextOpcode = "V6_vS32b_nt";
29563let isNVStorable = 1;
29564let isPredicable = 1;
29565let DecoderNamespace = "EXT_mmvec";
29566let Constraints = "$Rx32 = $Rx32in";
29567}
29568def V6_vS32b_nt_ppu : HInst<
29569(outs IntRegs:$Rx32),
29570(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29571"vmem($Rx32++$Mu2):nt = $Vs32",
29572tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29573let Inst{12-5} = 0b00000000;
29574let Inst{31-21} = 0b00101011011;
29575let addrMode = PostInc;
29576let accessSize = HVXVectorAccess;
29577let isCVI = 1;
29578let isHVXALU = 1;
29579let isNonTemporal = 1;
29580let mayStore = 1;
29581let BaseOpcode = "V6_vS32b_ppu";
29582let isNVStorable = 1;
29583let isPredicable = 1;
29584let DecoderNamespace = "EXT_mmvec";
29585let Constraints = "$Rx32 = $Rx32in";
29586}
29587def V6_vS32b_nt_pred_ai : HInst<
29588(outs),
29589(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29590"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29591tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29592let Inst{7-5} = 0b000;
29593let Inst{31-21} = 0b00101000111;
29594let isPredicated = 1;
29595let addrMode = BaseImmOffset;
29596let accessSize = HVXVectorAccess;
29597let isCVI = 1;
29598let isHVXALU = 1;
29599let isNonTemporal = 1;
29600let mayStore = 1;
29601let BaseOpcode = "V6_vS32b_ai";
29602let isNVStorable = 1;
29603let DecoderNamespace = "EXT_mmvec";
29604}
29605def V6_vS32b_nt_pred_pi : HInst<
29606(outs IntRegs:$Rx32),
29607(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29608"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29609tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29610let Inst{7-5} = 0b000;
29611let Inst{13-13} = 0b0;
29612let Inst{31-21} = 0b00101001111;
29613let isPredicated = 1;
29614let addrMode = PostInc;
29615let accessSize = HVXVectorAccess;
29616let isCVI = 1;
29617let isHVXALU = 1;
29618let isNonTemporal = 1;
29619let mayStore = 1;
29620let BaseOpcode = "V6_vS32b_pi";
29621let isNVStorable = 1;
29622let DecoderNamespace = "EXT_mmvec";
29623let Constraints = "$Rx32 = $Rx32in";
29624}
29625def V6_vS32b_nt_pred_ppu : HInst<
29626(outs IntRegs:$Rx32),
29627(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29628"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29629tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29630let Inst{10-5} = 0b000000;
29631let Inst{31-21} = 0b00101011111;
29632let isPredicated = 1;
29633let addrMode = PostInc;
29634let accessSize = HVXVectorAccess;
29635let isCVI = 1;
29636let isHVXALU = 1;
29637let isNonTemporal = 1;
29638let mayStore = 1;
29639let BaseOpcode = "V6_vS32b_ppu";
29640let isNVStorable = 1;
29641let DecoderNamespace = "EXT_mmvec";
29642let Constraints = "$Rx32 = $Rx32in";
29643}
29644def V6_vS32b_nt_qpred_ai : HInst<
29645(outs),
29646(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29647"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29648tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29649let Inst{7-5} = 0b000;
29650let Inst{31-21} = 0b00101000110;
29651let addrMode = BaseImmOffset;
29652let accessSize = HVXVectorAccess;
29653let isCVI = 1;
29654let isHVXALU = 1;
29655let isNonTemporal = 1;
29656let mayStore = 1;
29657let DecoderNamespace = "EXT_mmvec";
29658}
29659def V6_vS32b_nt_qpred_pi : HInst<
29660(outs IntRegs:$Rx32),
29661(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29662"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29663tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29664let Inst{7-5} = 0b000;
29665let Inst{13-13} = 0b0;
29666let Inst{31-21} = 0b00101001110;
29667let addrMode = PostInc;
29668let accessSize = HVXVectorAccess;
29669let isCVI = 1;
29670let isHVXALU = 1;
29671let isNonTemporal = 1;
29672let mayStore = 1;
29673let DecoderNamespace = "EXT_mmvec";
29674let Constraints = "$Rx32 = $Rx32in";
29675}
29676def V6_vS32b_nt_qpred_ppu : HInst<
29677(outs IntRegs:$Rx32),
29678(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29679"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29680tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29681let Inst{10-5} = 0b000000;
29682let Inst{31-21} = 0b00101011110;
29683let addrMode = PostInc;
29684let accessSize = HVXVectorAccess;
29685let isCVI = 1;
29686let isHVXALU = 1;
29687let isNonTemporal = 1;
29688let mayStore = 1;
29689let DecoderNamespace = "EXT_mmvec";
29690let Constraints = "$Rx32 = $Rx32in";
29691}
29692def V6_vS32b_pi : HInst<
29693(outs IntRegs:$Rx32),
29694(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29695"vmem($Rx32++#$Ii) = $Vs32",
29696tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel, PostInc_BaseImm {
29697let Inst{7-5} = 0b000;
29698let Inst{13-11} = 0b000;
29699let Inst{31-21} = 0b00101001001;
29700let addrMode = PostInc;
29701let accessSize = HVXVectorAccess;
29702let isCVI = 1;
29703let isHVXALU = 1;
29704let mayStore = 1;
29705let BaseOpcode = "V6_vS32b_pi";
29706let CextOpcode = "V6_vS32b";
29707let isNVStorable = 1;
29708let isPredicable = 1;
29709let DecoderNamespace = "EXT_mmvec";
29710let Constraints = "$Rx32 = $Rx32in";
29711}
29712def V6_vS32b_ppu : HInst<
29713(outs IntRegs:$Rx32),
29714(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29715"vmem($Rx32++$Mu2) = $Vs32",
29716tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29717let Inst{12-5} = 0b00000000;
29718let Inst{31-21} = 0b00101011001;
29719let addrMode = PostInc;
29720let accessSize = HVXVectorAccess;
29721let isCVI = 1;
29722let isHVXALU = 1;
29723let mayStore = 1;
29724let BaseOpcode = "V6_vS32b_ppu";
29725let isNVStorable = 1;
29726let isPredicable = 1;
29727let DecoderNamespace = "EXT_mmvec";
29728let Constraints = "$Rx32 = $Rx32in";
29729}
29730def V6_vS32b_pred_ai : HInst<
29731(outs),
29732(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29733"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
29734tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29735let Inst{7-5} = 0b000;
29736let Inst{31-21} = 0b00101000101;
29737let isPredicated = 1;
29738let addrMode = BaseImmOffset;
29739let accessSize = HVXVectorAccess;
29740let isCVI = 1;
29741let isHVXALU = 1;
29742let mayStore = 1;
29743let BaseOpcode = "V6_vS32b_ai";
29744let isNVStorable = 1;
29745let DecoderNamespace = "EXT_mmvec";
29746}
29747def V6_vS32b_pred_pi : HInst<
29748(outs IntRegs:$Rx32),
29749(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29750"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
29751tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29752let Inst{7-5} = 0b000;
29753let Inst{13-13} = 0b0;
29754let Inst{31-21} = 0b00101001101;
29755let isPredicated = 1;
29756let addrMode = PostInc;
29757let accessSize = HVXVectorAccess;
29758let isCVI = 1;
29759let isHVXALU = 1;
29760let mayStore = 1;
29761let BaseOpcode = "V6_vS32b_pi";
29762let isNVStorable = 1;
29763let DecoderNamespace = "EXT_mmvec";
29764let Constraints = "$Rx32 = $Rx32in";
29765}
29766def V6_vS32b_pred_ppu : HInst<
29767(outs IntRegs:$Rx32),
29768(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29769"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
29770tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29771let Inst{10-5} = 0b000000;
29772let Inst{31-21} = 0b00101011101;
29773let isPredicated = 1;
29774let addrMode = PostInc;
29775let accessSize = HVXVectorAccess;
29776let isCVI = 1;
29777let isHVXALU = 1;
29778let mayStore = 1;
29779let BaseOpcode = "V6_vS32b_ppu";
29780let isNVStorable = 1;
29781let DecoderNamespace = "EXT_mmvec";
29782let Constraints = "$Rx32 = $Rx32in";
29783}
29784def V6_vS32b_qpred_ai : HInst<
29785(outs),
29786(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29787"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
29788tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29789let Inst{7-5} = 0b000;
29790let Inst{31-21} = 0b00101000100;
29791let addrMode = BaseImmOffset;
29792let accessSize = HVXVectorAccess;
29793let isCVI = 1;
29794let isHVXALU = 1;
29795let mayStore = 1;
29796let DecoderNamespace = "EXT_mmvec";
29797}
29798def V6_vS32b_qpred_pi : HInst<
29799(outs IntRegs:$Rx32),
29800(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29801"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
29802tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29803let Inst{7-5} = 0b000;
29804let Inst{13-13} = 0b0;
29805let Inst{31-21} = 0b00101001100;
29806let addrMode = PostInc;
29807let accessSize = HVXVectorAccess;
29808let isCVI = 1;
29809let isHVXALU = 1;
29810let mayStore = 1;
29811let DecoderNamespace = "EXT_mmvec";
29812let Constraints = "$Rx32 = $Rx32in";
29813}
29814def V6_vS32b_qpred_ppu : HInst<
29815(outs IntRegs:$Rx32),
29816(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29817"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
29818tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29819let Inst{10-5} = 0b000000;
29820let Inst{31-21} = 0b00101011100;
29821let addrMode = PostInc;
29822let accessSize = HVXVectorAccess;
29823let isCVI = 1;
29824let isHVXALU = 1;
29825let mayStore = 1;
29826let DecoderNamespace = "EXT_mmvec";
29827let Constraints = "$Rx32 = $Rx32in";
29828}
29829def V6_vS32b_srls_ai : HInst<
29830(outs),
29831(ins IntRegs:$Rt32, s4_0Imm:$Ii),
29832"vmem($Rt32+#$Ii):scatter_release",
29833tc_3ce09744, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
29834let Inst{7-0} = 0b00101000;
29835let Inst{12-11} = 0b00;
29836let Inst{31-21} = 0b00101000001;
29837let addrMode = BaseImmOffset;
29838let accessSize = HVXVectorAccess;
29839let isCVI = 1;
29840let CVINew = 1;
29841let mayStore = 1;
29842let DecoderNamespace = "EXT_mmvec";
29843}
29844def V6_vS32b_srls_pi : HInst<
29845(outs IntRegs:$Rx32),
29846(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
29847"vmem($Rx32++#$Ii):scatter_release",
29848tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
29849let Inst{7-0} = 0b00101000;
29850let Inst{13-11} = 0b000;
29851let Inst{31-21} = 0b00101001001;
29852let addrMode = PostInc;
29853let accessSize = HVXVectorAccess;
29854let isCVI = 1;
29855let CVINew = 1;
29856let mayStore = 1;
29857let DecoderNamespace = "EXT_mmvec";
29858let Constraints = "$Rx32 = $Rx32in";
29859}
29860def V6_vS32b_srls_ppu : HInst<
29861(outs IntRegs:$Rx32),
29862(ins IntRegs:$Rx32in, ModRegs:$Mu2),
29863"vmem($Rx32++$Mu2):scatter_release",
29864tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
29865let Inst{12-0} = 0b0000000101000;
29866let Inst{31-21} = 0b00101011001;
29867let addrMode = PostInc;
29868let accessSize = HVXVectorAccess;
29869let isCVI = 1;
29870let CVINew = 1;
29871let mayStore = 1;
29872let DecoderNamespace = "EXT_mmvec";
29873let Constraints = "$Rx32 = $Rx32in";
29874}
29875def V6_vabs_hf : HInst<
29876(outs HvxVR:$Vd32),
29877(ins HvxVR:$Vu32),
29878"$Vd32.hf = vabs($Vu32.hf)",
29879tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
29880let Inst{7-5} = 0b100;
29881let Inst{13-13} = 0b1;
29882let Inst{31-16} = 0b0001111000000110;
29883let hasNewValue = 1;
29884let opNewValue = 0;
29885let isCVI = 1;
29886let DecoderNamespace = "EXT_mmvec";
29887}
29888def V6_vabs_sf : HInst<
29889(outs HvxVR:$Vd32),
29890(ins HvxVR:$Vu32),
29891"$Vd32.sf = vabs($Vu32.sf)",
29892tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
29893let Inst{7-5} = 0b101;
29894let Inst{13-13} = 0b1;
29895let Inst{31-16} = 0b0001111000000110;
29896let hasNewValue = 1;
29897let opNewValue = 0;
29898let isCVI = 1;
29899let DecoderNamespace = "EXT_mmvec";
29900}
29901def V6_vabsb : HInst<
29902(outs HvxVR:$Vd32),
29903(ins HvxVR:$Vu32),
29904"$Vd32.b = vabs($Vu32.b)",
29905tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29906let Inst{7-5} = 0b100;
29907let Inst{13-13} = 0b0;
29908let Inst{31-16} = 0b0001111000000001;
29909let hasNewValue = 1;
29910let opNewValue = 0;
29911let isCVI = 1;
29912let isHVXALU = 1;
29913let isHVXALU2SRC = 1;
29914let DecoderNamespace = "EXT_mmvec";
29915}
29916def V6_vabsb_alt : HInst<
29917(outs HvxVR:$Vd32),
29918(ins HvxVR:$Vu32),
29919"$Vd32 = vabsb($Vu32)",
29920PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29921let hasNewValue = 1;
29922let opNewValue = 0;
29923let isCVI = 1;
29924let isPseudo = 1;
29925let isCodeGenOnly = 1;
29926let DecoderNamespace = "EXT_mmvec";
29927}
29928def V6_vabsb_sat : HInst<
29929(outs HvxVR:$Vd32),
29930(ins HvxVR:$Vu32),
29931"$Vd32.b = vabs($Vu32.b):sat",
29932tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29933let Inst{7-5} = 0b101;
29934let Inst{13-13} = 0b0;
29935let Inst{31-16} = 0b0001111000000001;
29936let hasNewValue = 1;
29937let opNewValue = 0;
29938let isCVI = 1;
29939let isHVXALU = 1;
29940let isHVXALU2SRC = 1;
29941let DecoderNamespace = "EXT_mmvec";
29942}
29943def V6_vabsb_sat_alt : HInst<
29944(outs HvxVR:$Vd32),
29945(ins HvxVR:$Vu32),
29946"$Vd32 = vabsb($Vu32):sat",
29947PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29948let hasNewValue = 1;
29949let opNewValue = 0;
29950let isCVI = 1;
29951let isPseudo = 1;
29952let isCodeGenOnly = 1;
29953let DecoderNamespace = "EXT_mmvec";
29954}
29955def V6_vabsdiffh : HInst<
29956(outs HvxVR:$Vd32),
29957(ins HvxVR:$Vu32, HvxVR:$Vv32),
29958"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
29959tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29960let Inst{7-5} = 0b001;
29961let Inst{13-13} = 0b0;
29962let Inst{31-21} = 0b00011100110;
29963let hasNewValue = 1;
29964let opNewValue = 0;
29965let isCVI = 1;
29966let DecoderNamespace = "EXT_mmvec";
29967}
29968def V6_vabsdiffh_alt : HInst<
29969(outs HvxVR:$Vd32),
29970(ins HvxVR:$Vu32, HvxVR:$Vv32),
29971"$Vd32 = vabsdiffh($Vu32,$Vv32)",
29972PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29973let hasNewValue = 1;
29974let opNewValue = 0;
29975let isCVI = 1;
29976let isPseudo = 1;
29977let isCodeGenOnly = 1;
29978let DecoderNamespace = "EXT_mmvec";
29979}
29980def V6_vabsdiffub : HInst<
29981(outs HvxVR:$Vd32),
29982(ins HvxVR:$Vu32, HvxVR:$Vv32),
29983"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
29984tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29985let Inst{7-5} = 0b000;
29986let Inst{13-13} = 0b0;
29987let Inst{31-21} = 0b00011100110;
29988let hasNewValue = 1;
29989let opNewValue = 0;
29990let isCVI = 1;
29991let DecoderNamespace = "EXT_mmvec";
29992}
29993def V6_vabsdiffub_alt : HInst<
29994(outs HvxVR:$Vd32),
29995(ins HvxVR:$Vu32, HvxVR:$Vv32),
29996"$Vd32 = vabsdiffub($Vu32,$Vv32)",
29997PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29998let hasNewValue = 1;
29999let opNewValue = 0;
30000let isCVI = 1;
30001let isPseudo = 1;
30002let isCodeGenOnly = 1;
30003let DecoderNamespace = "EXT_mmvec";
30004}
30005def V6_vabsdiffuh : HInst<
30006(outs HvxVR:$Vd32),
30007(ins HvxVR:$Vu32, HvxVR:$Vv32),
30008"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
30009tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
30010let Inst{7-5} = 0b010;
30011let Inst{13-13} = 0b0;
30012let Inst{31-21} = 0b00011100110;
30013let hasNewValue = 1;
30014let opNewValue = 0;
30015let isCVI = 1;
30016let DecoderNamespace = "EXT_mmvec";
30017}
30018def V6_vabsdiffuh_alt : HInst<
30019(outs HvxVR:$Vd32),
30020(ins HvxVR:$Vu32, HvxVR:$Vv32),
30021"$Vd32 = vabsdiffuh($Vu32,$Vv32)",
30022PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30023let hasNewValue = 1;
30024let opNewValue = 0;
30025let isCVI = 1;
30026let isPseudo = 1;
30027let isCodeGenOnly = 1;
30028let DecoderNamespace = "EXT_mmvec";
30029}
30030def V6_vabsdiffw : HInst<
30031(outs HvxVR:$Vd32),
30032(ins HvxVR:$Vu32, HvxVR:$Vv32),
30033"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
30034tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
30035let Inst{7-5} = 0b011;
30036let Inst{13-13} = 0b0;
30037let Inst{31-21} = 0b00011100110;
30038let hasNewValue = 1;
30039let opNewValue = 0;
30040let isCVI = 1;
30041let DecoderNamespace = "EXT_mmvec";
30042}
30043def V6_vabsdiffw_alt : HInst<
30044(outs HvxVR:$Vd32),
30045(ins HvxVR:$Vu32, HvxVR:$Vv32),
30046"$Vd32 = vabsdiffw($Vu32,$Vv32)",
30047PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30048let hasNewValue = 1;
30049let opNewValue = 0;
30050let isCVI = 1;
30051let isPseudo = 1;
30052let isCodeGenOnly = 1;
30053let DecoderNamespace = "EXT_mmvec";
30054}
30055def V6_vabsh : HInst<
30056(outs HvxVR:$Vd32),
30057(ins HvxVR:$Vu32),
30058"$Vd32.h = vabs($Vu32.h)",
30059tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30060let Inst{7-5} = 0b000;
30061let Inst{13-13} = 0b0;
30062let Inst{31-16} = 0b0001111000000000;
30063let hasNewValue = 1;
30064let opNewValue = 0;
30065let isCVI = 1;
30066let isHVXALU = 1;
30067let isHVXALU2SRC = 1;
30068let DecoderNamespace = "EXT_mmvec";
30069}
30070def V6_vabsh_alt : HInst<
30071(outs HvxVR:$Vd32),
30072(ins HvxVR:$Vu32),
30073"$Vd32 = vabsh($Vu32)",
30074PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30075let hasNewValue = 1;
30076let opNewValue = 0;
30077let isCVI = 1;
30078let isPseudo = 1;
30079let isCodeGenOnly = 1;
30080let DecoderNamespace = "EXT_mmvec";
30081}
30082def V6_vabsh_sat : HInst<
30083(outs HvxVR:$Vd32),
30084(ins HvxVR:$Vu32),
30085"$Vd32.h = vabs($Vu32.h):sat",
30086tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30087let Inst{7-5} = 0b001;
30088let Inst{13-13} = 0b0;
30089let Inst{31-16} = 0b0001111000000000;
30090let hasNewValue = 1;
30091let opNewValue = 0;
30092let isCVI = 1;
30093let isHVXALU = 1;
30094let isHVXALU2SRC = 1;
30095let DecoderNamespace = "EXT_mmvec";
30096}
30097def V6_vabsh_sat_alt : HInst<
30098(outs HvxVR:$Vd32),
30099(ins HvxVR:$Vu32),
30100"$Vd32 = vabsh($Vu32):sat",
30101PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30102let hasNewValue = 1;
30103let opNewValue = 0;
30104let isCVI = 1;
30105let isPseudo = 1;
30106let isCodeGenOnly = 1;
30107let DecoderNamespace = "EXT_mmvec";
30108}
30109def V6_vabsub_alt : HInst<
30110(outs HvxVR:$Vd32),
30111(ins HvxVR:$Vu32),
30112"$Vd32.ub = vabs($Vu32.b)",
30113tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
30114let hasNewValue = 1;
30115let opNewValue = 0;
30116let isCVI = 1;
30117let isPseudo = 1;
30118let isCodeGenOnly = 1;
30119let DecoderNamespace = "EXT_mmvec";
30120}
30121def V6_vabsuh_alt : HInst<
30122(outs HvxVR:$Vd32),
30123(ins HvxVR:$Vu32),
30124"$Vd32.uh = vabs($Vu32.h)",
30125tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
30126let hasNewValue = 1;
30127let opNewValue = 0;
30128let isCVI = 1;
30129let isPseudo = 1;
30130let isCodeGenOnly = 1;
30131let DecoderNamespace = "EXT_mmvec";
30132}
30133def V6_vabsuw_alt : HInst<
30134(outs HvxVR:$Vd32),
30135(ins HvxVR:$Vu32),
30136"$Vd32.uw = vabs($Vu32.w)",
30137tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
30138let hasNewValue = 1;
30139let opNewValue = 0;
30140let isCVI = 1;
30141let isPseudo = 1;
30142let isCodeGenOnly = 1;
30143let DecoderNamespace = "EXT_mmvec";
30144}
30145def V6_vabsw : HInst<
30146(outs HvxVR:$Vd32),
30147(ins HvxVR:$Vu32),
30148"$Vd32.w = vabs($Vu32.w)",
30149tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30150let Inst{7-5} = 0b010;
30151let Inst{13-13} = 0b0;
30152let Inst{31-16} = 0b0001111000000000;
30153let hasNewValue = 1;
30154let opNewValue = 0;
30155let isCVI = 1;
30156let isHVXALU = 1;
30157let isHVXALU2SRC = 1;
30158let DecoderNamespace = "EXT_mmvec";
30159}
30160def V6_vabsw_alt : HInst<
30161(outs HvxVR:$Vd32),
30162(ins HvxVR:$Vu32),
30163"$Vd32 = vabsw($Vu32)",
30164PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30165let hasNewValue = 1;
30166let opNewValue = 0;
30167let isCVI = 1;
30168let isPseudo = 1;
30169let isCodeGenOnly = 1;
30170let DecoderNamespace = "EXT_mmvec";
30171}
30172def V6_vabsw_sat : HInst<
30173(outs HvxVR:$Vd32),
30174(ins HvxVR:$Vu32),
30175"$Vd32.w = vabs($Vu32.w):sat",
30176tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
30177let Inst{7-5} = 0b011;
30178let Inst{13-13} = 0b0;
30179let Inst{31-16} = 0b0001111000000000;
30180let hasNewValue = 1;
30181let opNewValue = 0;
30182let isCVI = 1;
30183let isHVXALU = 1;
30184let isHVXALU2SRC = 1;
30185let DecoderNamespace = "EXT_mmvec";
30186}
30187def V6_vabsw_sat_alt : HInst<
30188(outs HvxVR:$Vd32),
30189(ins HvxVR:$Vu32),
30190"$Vd32 = vabsw($Vu32):sat",
30191PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30192let hasNewValue = 1;
30193let opNewValue = 0;
30194let isCVI = 1;
30195let isPseudo = 1;
30196let isCodeGenOnly = 1;
30197let DecoderNamespace = "EXT_mmvec";
30198}
30199def V6_vadd_hf : HInst<
30200(outs HvxVR:$Vd32),
30201(ins HvxVR:$Vu32, HvxVR:$Vv32),
30202"$Vd32.qf16 = vadd($Vu32.hf,$Vv32.hf)",
30203tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30204let Inst{7-5} = 0b011;
30205let Inst{13-13} = 0b1;
30206let Inst{31-21} = 0b00011111011;
30207let hasNewValue = 1;
30208let opNewValue = 0;
30209let isCVI = 1;
30210let DecoderNamespace = "EXT_mmvec";
30211}
30212def V6_vadd_hf_hf : HInst<
30213(outs HvxVR:$Vd32),
30214(ins HvxVR:$Vu32, HvxVR:$Vv32),
30215"$Vd32.hf = vadd($Vu32.hf,$Vv32.hf)",
30216tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30217let Inst{7-5} = 0b111;
30218let Inst{13-13} = 0b1;
30219let Inst{31-21} = 0b00011111101;
30220let hasNewValue = 1;
30221let opNewValue = 0;
30222let isCVI = 1;
30223let DecoderNamespace = "EXT_mmvec";
30224}
30225def V6_vadd_qf16 : HInst<
30226(outs HvxVR:$Vd32),
30227(ins HvxVR:$Vu32, HvxVR:$Vv32),
30228"$Vd32.qf16 = vadd($Vu32.qf16,$Vv32.qf16)",
30229tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30230let Inst{7-5} = 0b010;
30231let Inst{13-13} = 0b1;
30232let Inst{31-21} = 0b00011111011;
30233let hasNewValue = 1;
30234let opNewValue = 0;
30235let isCVI = 1;
30236let DecoderNamespace = "EXT_mmvec";
30237}
30238def V6_vadd_qf16_mix : HInst<
30239(outs HvxVR:$Vd32),
30240(ins HvxVR:$Vu32, HvxVR:$Vv32),
30241"$Vd32.qf16 = vadd($Vu32.qf16,$Vv32.hf)",
30242tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30243let Inst{7-5} = 0b100;
30244let Inst{13-13} = 0b1;
30245let Inst{31-21} = 0b00011111011;
30246let hasNewValue = 1;
30247let opNewValue = 0;
30248let isCVI = 1;
30249let DecoderNamespace = "EXT_mmvec";
30250}
30251def V6_vadd_qf32 : HInst<
30252(outs HvxVR:$Vd32),
30253(ins HvxVR:$Vu32, HvxVR:$Vv32),
30254"$Vd32.qf32 = vadd($Vu32.qf32,$Vv32.qf32)",
30255tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30256let Inst{7-5} = 0b000;
30257let Inst{13-13} = 0b1;
30258let Inst{31-21} = 0b00011111101;
30259let hasNewValue = 1;
30260let opNewValue = 0;
30261let isCVI = 1;
30262let DecoderNamespace = "EXT_mmvec";
30263}
30264def V6_vadd_qf32_mix : HInst<
30265(outs HvxVR:$Vd32),
30266(ins HvxVR:$Vu32, HvxVR:$Vv32),
30267"$Vd32.qf32 = vadd($Vu32.qf32,$Vv32.sf)",
30268tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30269let Inst{7-5} = 0b010;
30270let Inst{13-13} = 0b1;
30271let Inst{31-21} = 0b00011111101;
30272let hasNewValue = 1;
30273let opNewValue = 0;
30274let isCVI = 1;
30275let DecoderNamespace = "EXT_mmvec";
30276}
30277def V6_vadd_sf : HInst<
30278(outs HvxVR:$Vd32),
30279(ins HvxVR:$Vu32, HvxVR:$Vv32),
30280"$Vd32.qf32 = vadd($Vu32.sf,$Vv32.sf)",
30281tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
30282let Inst{7-5} = 0b001;
30283let Inst{13-13} = 0b1;
30284let Inst{31-21} = 0b00011111101;
30285let hasNewValue = 1;
30286let opNewValue = 0;
30287let isCVI = 1;
30288let DecoderNamespace = "EXT_mmvec";
30289}
30290def V6_vadd_sf_bf : HInst<
30291(outs HvxWR:$Vdd32),
30292(ins HvxVR:$Vu32, HvxVR:$Vv32),
30293"$Vdd32.sf = vadd($Vu32.bf,$Vv32.bf)",
30294tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV73,UseHVXIEEEFP]> {
30295let Inst{7-5} = 0b110;
30296let Inst{13-13} = 0b1;
30297let Inst{31-21} = 0b00011101010;
30298let hasNewValue = 1;
30299let opNewValue = 0;
30300let isCVI = 1;
30301let DecoderNamespace = "EXT_mmvec";
30302}
30303def V6_vadd_sf_hf : HInst<
30304(outs HvxWR:$Vdd32),
30305(ins HvxVR:$Vu32, HvxVR:$Vv32),
30306"$Vdd32.sf = vadd($Vu32.hf,$Vv32.hf)",
30307tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30308let Inst{7-5} = 0b100;
30309let Inst{13-13} = 0b1;
30310let Inst{31-21} = 0b00011111100;
30311let hasNewValue = 1;
30312let opNewValue = 0;
30313let isCVI = 1;
30314let DecoderNamespace = "EXT_mmvec";
30315}
30316def V6_vadd_sf_sf : HInst<
30317(outs HvxVR:$Vd32),
30318(ins HvxVR:$Vu32, HvxVR:$Vv32),
30319"$Vd32.sf = vadd($Vu32.sf,$Vv32.sf)",
30320tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
30321let Inst{7-5} = 0b110;
30322let Inst{13-13} = 0b1;
30323let Inst{31-21} = 0b00011111100;
30324let hasNewValue = 1;
30325let opNewValue = 0;
30326let isCVI = 1;
30327let DecoderNamespace = "EXT_mmvec";
30328}
30329def V6_vaddb : HInst<
30330(outs HvxVR:$Vd32),
30331(ins HvxVR:$Vu32, HvxVR:$Vv32),
30332"$Vd32.b = vadd($Vu32.b,$Vv32.b)",
30333tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30334let Inst{7-5} = 0b110;
30335let Inst{13-13} = 0b0;
30336let Inst{31-21} = 0b00011111101;
30337let hasNewValue = 1;
30338let opNewValue = 0;
30339let isCVI = 1;
30340let isHVXALU = 1;
30341let isHVXALU2SRC = 1;
30342let DecoderNamespace = "EXT_mmvec";
30343}
30344def V6_vaddb_alt : HInst<
30345(outs HvxVR:$Vd32),
30346(ins HvxVR:$Vu32, HvxVR:$Vv32),
30347"$Vd32 = vaddb($Vu32,$Vv32)",
30348PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30349let hasNewValue = 1;
30350let opNewValue = 0;
30351let isCVI = 1;
30352let isPseudo = 1;
30353let isCodeGenOnly = 1;
30354let DecoderNamespace = "EXT_mmvec";
30355}
30356def V6_vaddb_dv : HInst<
30357(outs HvxWR:$Vdd32),
30358(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30359"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
30360tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30361let Inst{7-5} = 0b100;
30362let Inst{13-13} = 0b0;
30363let Inst{31-21} = 0b00011100011;
30364let hasNewValue = 1;
30365let opNewValue = 0;
30366let isCVI = 1;
30367let DecoderNamespace = "EXT_mmvec";
30368}
30369def V6_vaddb_dv_alt : HInst<
30370(outs HvxWR:$Vdd32),
30371(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30372"$Vdd32 = vaddb($Vuu32,$Vvv32)",
30373PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30374let hasNewValue = 1;
30375let opNewValue = 0;
30376let isCVI = 1;
30377let isPseudo = 1;
30378let isCodeGenOnly = 1;
30379let DecoderNamespace = "EXT_mmvec";
30380}
30381def V6_vaddbnq : HInst<
30382(outs HvxVR:$Vx32),
30383(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30384"if (!$Qv4) $Vx32.b += $Vu32.b",
30385tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30386let Inst{7-5} = 0b011;
30387let Inst{13-13} = 0b1;
30388let Inst{21-16} = 0b000001;
30389let Inst{31-24} = 0b00011110;
30390let hasNewValue = 1;
30391let opNewValue = 0;
30392let isAccumulator = 1;
30393let isCVI = 1;
30394let isHVXALU = 1;
30395let isHVXALU2SRC = 1;
30396let DecoderNamespace = "EXT_mmvec";
30397let Constraints = "$Vx32 = $Vx32in";
30398}
30399def V6_vaddbnq_alt : HInst<
30400(outs HvxVR:$Vx32),
30401(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30402"if (!$Qv4.b) $Vx32.b += $Vu32.b",
30403PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30404let hasNewValue = 1;
30405let opNewValue = 0;
30406let isAccumulator = 1;
30407let isCVI = 1;
30408let isPseudo = 1;
30409let isCodeGenOnly = 1;
30410let DecoderNamespace = "EXT_mmvec";
30411let Constraints = "$Vx32 = $Vx32in";
30412}
30413def V6_vaddbq : HInst<
30414(outs HvxVR:$Vx32),
30415(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30416"if ($Qv4) $Vx32.b += $Vu32.b",
30417tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30418let Inst{7-5} = 0b000;
30419let Inst{13-13} = 0b1;
30420let Inst{21-16} = 0b000001;
30421let Inst{31-24} = 0b00011110;
30422let hasNewValue = 1;
30423let opNewValue = 0;
30424let isAccumulator = 1;
30425let isCVI = 1;
30426let isHVXALU = 1;
30427let isHVXALU2SRC = 1;
30428let DecoderNamespace = "EXT_mmvec";
30429let Constraints = "$Vx32 = $Vx32in";
30430}
30431def V6_vaddbq_alt : HInst<
30432(outs HvxVR:$Vx32),
30433(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30434"if ($Qv4.b) $Vx32.b += $Vu32.b",
30435PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30436let hasNewValue = 1;
30437let opNewValue = 0;
30438let isAccumulator = 1;
30439let isCVI = 1;
30440let isPseudo = 1;
30441let isCodeGenOnly = 1;
30442let DecoderNamespace = "EXT_mmvec";
30443let Constraints = "$Vx32 = $Vx32in";
30444}
30445def V6_vaddbsat : HInst<
30446(outs HvxVR:$Vd32),
30447(ins HvxVR:$Vu32, HvxVR:$Vv32),
30448"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
30449tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30450let Inst{7-5} = 0b000;
30451let Inst{13-13} = 0b0;
30452let Inst{31-21} = 0b00011111000;
30453let hasNewValue = 1;
30454let opNewValue = 0;
30455let isCVI = 1;
30456let isHVXALU = 1;
30457let isHVXALU2SRC = 1;
30458let DecoderNamespace = "EXT_mmvec";
30459}
30460def V6_vaddbsat_alt : HInst<
30461(outs HvxVR:$Vd32),
30462(ins HvxVR:$Vu32, HvxVR:$Vv32),
30463"$Vd32 = vaddb($Vu32,$Vv32):sat",
30464PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30465let hasNewValue = 1;
30466let opNewValue = 0;
30467let isCVI = 1;
30468let isPseudo = 1;
30469let isCodeGenOnly = 1;
30470let DecoderNamespace = "EXT_mmvec";
30471}
30472def V6_vaddbsat_dv : HInst<
30473(outs HvxWR:$Vdd32),
30474(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30475"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
30476tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
30477let Inst{7-5} = 0b000;
30478let Inst{13-13} = 0b0;
30479let Inst{31-21} = 0b00011110101;
30480let hasNewValue = 1;
30481let opNewValue = 0;
30482let isCVI = 1;
30483let DecoderNamespace = "EXT_mmvec";
30484}
30485def V6_vaddbsat_dv_alt : HInst<
30486(outs HvxWR:$Vdd32),
30487(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30488"$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
30489PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30490let hasNewValue = 1;
30491let opNewValue = 0;
30492let isCVI = 1;
30493let isPseudo = 1;
30494let isCodeGenOnly = 1;
30495let DecoderNamespace = "EXT_mmvec";
30496}
30497def V6_vaddcarry : HInst<
30498(outs HvxVR:$Vd32, HvxQR:$Qx4),
30499(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
30500"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
30501tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
30502let Inst{7-7} = 0b0;
30503let Inst{13-13} = 0b1;
30504let Inst{31-21} = 0b00011100101;
30505let hasNewValue = 1;
30506let opNewValue = 0;
30507let isCVI = 1;
30508let isHVXALU = 1;
30509let isHVXALU2SRC = 1;
30510let DecoderNamespace = "EXT_mmvec";
30511let Constraints = "$Qx4 = $Qx4in";
30512}
30513def V6_vaddcarryo : HInst<
30514(outs HvxVR:$Vd32, HvxQR:$Qe4),
30515(ins HvxVR:$Vu32, HvxVR:$Vv32),
30516"$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry",
30517tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
30518let Inst{7-7} = 0b0;
30519let Inst{13-13} = 0b1;
30520let Inst{31-21} = 0b00011101101;
30521let hasNewValue = 1;
30522let opNewValue = 0;
30523let isCVI = 1;
30524let isHVXALU = 1;
30525let isHVXALU2SRC = 1;
30526let DecoderNamespace = "EXT_mmvec";
30527}
30528def V6_vaddcarrysat : HInst<
30529(outs HvxVR:$Vd32),
30530(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qs4),
30531"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qs4):carry:sat",
30532tc_257f6f7c, TypeCVI_VA>, Enc_e0820b, Requires<[UseHVXV66]> {
30533let Inst{7-7} = 0b0;
30534let Inst{13-13} = 0b1;
30535let Inst{31-21} = 0b00011101100;
30536let hasNewValue = 1;
30537let opNewValue = 0;
30538let isCVI = 1;
30539let isHVXALU = 1;
30540let isHVXALU2SRC = 1;
30541let DecoderNamespace = "EXT_mmvec";
30542}
30543def V6_vaddclbh : HInst<
30544(outs HvxVR:$Vd32),
30545(ins HvxVR:$Vu32, HvxVR:$Vv32),
30546"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
30547tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30548let Inst{7-5} = 0b000;
30549let Inst{13-13} = 0b1;
30550let Inst{31-21} = 0b00011111000;
30551let hasNewValue = 1;
30552let opNewValue = 0;
30553let isCVI = 1;
30554let DecoderNamespace = "EXT_mmvec";
30555}
30556def V6_vaddclbw : HInst<
30557(outs HvxVR:$Vd32),
30558(ins HvxVR:$Vu32, HvxVR:$Vv32),
30559"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
30560tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30561let Inst{7-5} = 0b001;
30562let Inst{13-13} = 0b1;
30563let Inst{31-21} = 0b00011111000;
30564let hasNewValue = 1;
30565let opNewValue = 0;
30566let isCVI = 1;
30567let DecoderNamespace = "EXT_mmvec";
30568}
30569def V6_vaddh : HInst<
30570(outs HvxVR:$Vd32),
30571(ins HvxVR:$Vu32, HvxVR:$Vv32),
30572"$Vd32.h = vadd($Vu32.h,$Vv32.h)",
30573tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30574let Inst{7-5} = 0b111;
30575let Inst{13-13} = 0b0;
30576let Inst{31-21} = 0b00011111101;
30577let hasNewValue = 1;
30578let opNewValue = 0;
30579let isCVI = 1;
30580let isHVXALU = 1;
30581let isHVXALU2SRC = 1;
30582let DecoderNamespace = "EXT_mmvec";
30583}
30584def V6_vaddh_alt : HInst<
30585(outs HvxVR:$Vd32),
30586(ins HvxVR:$Vu32, HvxVR:$Vv32),
30587"$Vd32 = vaddh($Vu32,$Vv32)",
30588PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30589let hasNewValue = 1;
30590let opNewValue = 0;
30591let isCVI = 1;
30592let isPseudo = 1;
30593let isCodeGenOnly = 1;
30594let DecoderNamespace = "EXT_mmvec";
30595}
30596def V6_vaddh_dv : HInst<
30597(outs HvxWR:$Vdd32),
30598(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30599"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
30600tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30601let Inst{7-5} = 0b101;
30602let Inst{13-13} = 0b0;
30603let Inst{31-21} = 0b00011100011;
30604let hasNewValue = 1;
30605let opNewValue = 0;
30606let isCVI = 1;
30607let DecoderNamespace = "EXT_mmvec";
30608}
30609def V6_vaddh_dv_alt : HInst<
30610(outs HvxWR:$Vdd32),
30611(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30612"$Vdd32 = vaddh($Vuu32,$Vvv32)",
30613PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30614let hasNewValue = 1;
30615let opNewValue = 0;
30616let isCVI = 1;
30617let isPseudo = 1;
30618let isCodeGenOnly = 1;
30619let DecoderNamespace = "EXT_mmvec";
30620}
30621def V6_vaddhnq : HInst<
30622(outs HvxVR:$Vx32),
30623(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30624"if (!$Qv4) $Vx32.h += $Vu32.h",
30625tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30626let Inst{7-5} = 0b100;
30627let Inst{13-13} = 0b1;
30628let Inst{21-16} = 0b000001;
30629let Inst{31-24} = 0b00011110;
30630let hasNewValue = 1;
30631let opNewValue = 0;
30632let isAccumulator = 1;
30633let isCVI = 1;
30634let isHVXALU = 1;
30635let isHVXALU2SRC = 1;
30636let DecoderNamespace = "EXT_mmvec";
30637let Constraints = "$Vx32 = $Vx32in";
30638}
30639def V6_vaddhnq_alt : HInst<
30640(outs HvxVR:$Vx32),
30641(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30642"if (!$Qv4.h) $Vx32.h += $Vu32.h",
30643PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30644let hasNewValue = 1;
30645let opNewValue = 0;
30646let isAccumulator = 1;
30647let isCVI = 1;
30648let isPseudo = 1;
30649let isCodeGenOnly = 1;
30650let DecoderNamespace = "EXT_mmvec";
30651let Constraints = "$Vx32 = $Vx32in";
30652}
30653def V6_vaddhq : HInst<
30654(outs HvxVR:$Vx32),
30655(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30656"if ($Qv4) $Vx32.h += $Vu32.h",
30657tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30658let Inst{7-5} = 0b001;
30659let Inst{13-13} = 0b1;
30660let Inst{21-16} = 0b000001;
30661let Inst{31-24} = 0b00011110;
30662let hasNewValue = 1;
30663let opNewValue = 0;
30664let isAccumulator = 1;
30665let isCVI = 1;
30666let isHVXALU = 1;
30667let isHVXALU2SRC = 1;
30668let DecoderNamespace = "EXT_mmvec";
30669let Constraints = "$Vx32 = $Vx32in";
30670}
30671def V6_vaddhq_alt : HInst<
30672(outs HvxVR:$Vx32),
30673(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30674"if ($Qv4.h) $Vx32.h += $Vu32.h",
30675PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30676let hasNewValue = 1;
30677let opNewValue = 0;
30678let isAccumulator = 1;
30679let isCVI = 1;
30680let isPseudo = 1;
30681let isCodeGenOnly = 1;
30682let DecoderNamespace = "EXT_mmvec";
30683let Constraints = "$Vx32 = $Vx32in";
30684}
30685def V6_vaddhsat : HInst<
30686(outs HvxVR:$Vd32),
30687(ins HvxVR:$Vu32, HvxVR:$Vv32),
30688"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
30689tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30690let Inst{7-5} = 0b011;
30691let Inst{13-13} = 0b0;
30692let Inst{31-21} = 0b00011100010;
30693let hasNewValue = 1;
30694let opNewValue = 0;
30695let isCVI = 1;
30696let isHVXALU = 1;
30697let isHVXALU2SRC = 1;
30698let DecoderNamespace = "EXT_mmvec";
30699}
30700def V6_vaddhsat_alt : HInst<
30701(outs HvxVR:$Vd32),
30702(ins HvxVR:$Vu32, HvxVR:$Vv32),
30703"$Vd32 = vaddh($Vu32,$Vv32):sat",
30704PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30705let hasNewValue = 1;
30706let opNewValue = 0;
30707let isCVI = 1;
30708let isPseudo = 1;
30709let isCodeGenOnly = 1;
30710let DecoderNamespace = "EXT_mmvec";
30711}
30712def V6_vaddhsat_dv : HInst<
30713(outs HvxWR:$Vdd32),
30714(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30715"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
30716tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30717let Inst{7-5} = 0b001;
30718let Inst{13-13} = 0b0;
30719let Inst{31-21} = 0b00011100100;
30720let hasNewValue = 1;
30721let opNewValue = 0;
30722let isCVI = 1;
30723let DecoderNamespace = "EXT_mmvec";
30724}
30725def V6_vaddhsat_dv_alt : HInst<
30726(outs HvxWR:$Vdd32),
30727(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30728"$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
30729PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30730let hasNewValue = 1;
30731let opNewValue = 0;
30732let isCVI = 1;
30733let isPseudo = 1;
30734let isCodeGenOnly = 1;
30735let DecoderNamespace = "EXT_mmvec";
30736}
30737def V6_vaddhw : HInst<
30738(outs HvxWR:$Vdd32),
30739(ins HvxVR:$Vu32, HvxVR:$Vv32),
30740"$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
30741tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30742let Inst{7-5} = 0b100;
30743let Inst{13-13} = 0b0;
30744let Inst{31-21} = 0b00011100101;
30745let hasNewValue = 1;
30746let opNewValue = 0;
30747let isCVI = 1;
30748let DecoderNamespace = "EXT_mmvec";
30749}
30750def V6_vaddhw_acc : HInst<
30751(outs HvxWR:$Vxx32),
30752(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30753"$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
30754tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30755let Inst{7-5} = 0b010;
30756let Inst{13-13} = 0b1;
30757let Inst{31-21} = 0b00011100001;
30758let hasNewValue = 1;
30759let opNewValue = 0;
30760let isAccumulator = 1;
30761let isCVI = 1;
30762let DecoderNamespace = "EXT_mmvec";
30763let Constraints = "$Vxx32 = $Vxx32in";
30764}
30765def V6_vaddhw_acc_alt : HInst<
30766(outs HvxWR:$Vxx32),
30767(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30768"$Vxx32 += vaddh($Vu32,$Vv32)",
30769PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30770let hasNewValue = 1;
30771let opNewValue = 0;
30772let isAccumulator = 1;
30773let isCVI = 1;
30774let isPseudo = 1;
30775let isCodeGenOnly = 1;
30776let DecoderNamespace = "EXT_mmvec";
30777let Constraints = "$Vxx32 = $Vxx32in";
30778}
30779def V6_vaddhw_alt : HInst<
30780(outs HvxWR:$Vdd32),
30781(ins HvxVR:$Vu32, HvxVR:$Vv32),
30782"$Vdd32 = vaddh($Vu32,$Vv32)",
30783PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30784let hasNewValue = 1;
30785let opNewValue = 0;
30786let isCVI = 1;
30787let isPseudo = 1;
30788let isCodeGenOnly = 1;
30789let DecoderNamespace = "EXT_mmvec";
30790}
30791def V6_vaddubh : HInst<
30792(outs HvxWR:$Vdd32),
30793(ins HvxVR:$Vu32, HvxVR:$Vv32),
30794"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
30795tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30796let Inst{7-5} = 0b010;
30797let Inst{13-13} = 0b0;
30798let Inst{31-21} = 0b00011100101;
30799let hasNewValue = 1;
30800let opNewValue = 0;
30801let isCVI = 1;
30802let DecoderNamespace = "EXT_mmvec";
30803}
30804def V6_vaddubh_acc : HInst<
30805(outs HvxWR:$Vxx32),
30806(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30807"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
30808tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30809let Inst{7-5} = 0b101;
30810let Inst{13-13} = 0b1;
30811let Inst{31-21} = 0b00011100010;
30812let hasNewValue = 1;
30813let opNewValue = 0;
30814let isAccumulator = 1;
30815let isCVI = 1;
30816let DecoderNamespace = "EXT_mmvec";
30817let Constraints = "$Vxx32 = $Vxx32in";
30818}
30819def V6_vaddubh_acc_alt : HInst<
30820(outs HvxWR:$Vxx32),
30821(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30822"$Vxx32 += vaddub($Vu32,$Vv32)",
30823PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30824let hasNewValue = 1;
30825let opNewValue = 0;
30826let isAccumulator = 1;
30827let isCVI = 1;
30828let isPseudo = 1;
30829let isCodeGenOnly = 1;
30830let DecoderNamespace = "EXT_mmvec";
30831let Constraints = "$Vxx32 = $Vxx32in";
30832}
30833def V6_vaddubh_alt : HInst<
30834(outs HvxWR:$Vdd32),
30835(ins HvxVR:$Vu32, HvxVR:$Vv32),
30836"$Vdd32 = vaddub($Vu32,$Vv32)",
30837PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30838let hasNewValue = 1;
30839let opNewValue = 0;
30840let isCVI = 1;
30841let isPseudo = 1;
30842let isCodeGenOnly = 1;
30843let DecoderNamespace = "EXT_mmvec";
30844}
30845def V6_vaddubsat : HInst<
30846(outs HvxVR:$Vd32),
30847(ins HvxVR:$Vu32, HvxVR:$Vv32),
30848"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
30849tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30850let Inst{7-5} = 0b001;
30851let Inst{13-13} = 0b0;
30852let Inst{31-21} = 0b00011100010;
30853let hasNewValue = 1;
30854let opNewValue = 0;
30855let isCVI = 1;
30856let isHVXALU = 1;
30857let isHVXALU2SRC = 1;
30858let DecoderNamespace = "EXT_mmvec";
30859}
30860def V6_vaddubsat_alt : HInst<
30861(outs HvxVR:$Vd32),
30862(ins HvxVR:$Vu32, HvxVR:$Vv32),
30863"$Vd32 = vaddub($Vu32,$Vv32):sat",
30864PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30865let hasNewValue = 1;
30866let opNewValue = 0;
30867let isCVI = 1;
30868let isPseudo = 1;
30869let isCodeGenOnly = 1;
30870let DecoderNamespace = "EXT_mmvec";
30871}
30872def V6_vaddubsat_dv : HInst<
30873(outs HvxWR:$Vdd32),
30874(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30875"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
30876tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30877let Inst{7-5} = 0b111;
30878let Inst{13-13} = 0b0;
30879let Inst{31-21} = 0b00011100011;
30880let hasNewValue = 1;
30881let opNewValue = 0;
30882let isCVI = 1;
30883let DecoderNamespace = "EXT_mmvec";
30884}
30885def V6_vaddubsat_dv_alt : HInst<
30886(outs HvxWR:$Vdd32),
30887(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30888"$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
30889PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30890let hasNewValue = 1;
30891let opNewValue = 0;
30892let isCVI = 1;
30893let isPseudo = 1;
30894let isCodeGenOnly = 1;
30895let DecoderNamespace = "EXT_mmvec";
30896}
30897def V6_vaddububb_sat : HInst<
30898(outs HvxVR:$Vd32),
30899(ins HvxVR:$Vu32, HvxVR:$Vv32),
30900"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
30901tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30902let Inst{7-5} = 0b100;
30903let Inst{13-13} = 0b0;
30904let Inst{31-21} = 0b00011110101;
30905let hasNewValue = 1;
30906let opNewValue = 0;
30907let isCVI = 1;
30908let isHVXALU = 1;
30909let isHVXALU2SRC = 1;
30910let DecoderNamespace = "EXT_mmvec";
30911}
30912def V6_vadduhsat : HInst<
30913(outs HvxVR:$Vd32),
30914(ins HvxVR:$Vu32, HvxVR:$Vv32),
30915"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
30916tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30917let Inst{7-5} = 0b010;
30918let Inst{13-13} = 0b0;
30919let Inst{31-21} = 0b00011100010;
30920let hasNewValue = 1;
30921let opNewValue = 0;
30922let isCVI = 1;
30923let isHVXALU = 1;
30924let isHVXALU2SRC = 1;
30925let DecoderNamespace = "EXT_mmvec";
30926}
30927def V6_vadduhsat_alt : HInst<
30928(outs HvxVR:$Vd32),
30929(ins HvxVR:$Vu32, HvxVR:$Vv32),
30930"$Vd32 = vadduh($Vu32,$Vv32):sat",
30931PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30932let hasNewValue = 1;
30933let opNewValue = 0;
30934let isCVI = 1;
30935let isPseudo = 1;
30936let isCodeGenOnly = 1;
30937let DecoderNamespace = "EXT_mmvec";
30938}
30939def V6_vadduhsat_dv : HInst<
30940(outs HvxWR:$Vdd32),
30941(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30942"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
30943tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30944let Inst{7-5} = 0b000;
30945let Inst{13-13} = 0b0;
30946let Inst{31-21} = 0b00011100100;
30947let hasNewValue = 1;
30948let opNewValue = 0;
30949let isCVI = 1;
30950let DecoderNamespace = "EXT_mmvec";
30951}
30952def V6_vadduhsat_dv_alt : HInst<
30953(outs HvxWR:$Vdd32),
30954(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30955"$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
30956PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30957let hasNewValue = 1;
30958let opNewValue = 0;
30959let isCVI = 1;
30960let isPseudo = 1;
30961let isCodeGenOnly = 1;
30962let DecoderNamespace = "EXT_mmvec";
30963}
30964def V6_vadduhw : HInst<
30965(outs HvxWR:$Vdd32),
30966(ins HvxVR:$Vu32, HvxVR:$Vv32),
30967"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
30968tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30969let Inst{7-5} = 0b011;
30970let Inst{13-13} = 0b0;
30971let Inst{31-21} = 0b00011100101;
30972let hasNewValue = 1;
30973let opNewValue = 0;
30974let isCVI = 1;
30975let DecoderNamespace = "EXT_mmvec";
30976}
30977def V6_vadduhw_acc : HInst<
30978(outs HvxWR:$Vxx32),
30979(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30980"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
30981tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30982let Inst{7-5} = 0b100;
30983let Inst{13-13} = 0b1;
30984let Inst{31-21} = 0b00011100010;
30985let hasNewValue = 1;
30986let opNewValue = 0;
30987let isAccumulator = 1;
30988let isCVI = 1;
30989let DecoderNamespace = "EXT_mmvec";
30990let Constraints = "$Vxx32 = $Vxx32in";
30991}
30992def V6_vadduhw_acc_alt : HInst<
30993(outs HvxWR:$Vxx32),
30994(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30995"$Vxx32 += vadduh($Vu32,$Vv32)",
30996PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30997let hasNewValue = 1;
30998let opNewValue = 0;
30999let isAccumulator = 1;
31000let isCVI = 1;
31001let isPseudo = 1;
31002let isCodeGenOnly = 1;
31003let DecoderNamespace = "EXT_mmvec";
31004let Constraints = "$Vxx32 = $Vxx32in";
31005}
31006def V6_vadduhw_alt : HInst<
31007(outs HvxWR:$Vdd32),
31008(ins HvxVR:$Vu32, HvxVR:$Vv32),
31009"$Vdd32 = vadduh($Vu32,$Vv32)",
31010PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31011let hasNewValue = 1;
31012let opNewValue = 0;
31013let isCVI = 1;
31014let isPseudo = 1;
31015let isCodeGenOnly = 1;
31016let DecoderNamespace = "EXT_mmvec";
31017}
31018def V6_vadduwsat : HInst<
31019(outs HvxVR:$Vd32),
31020(ins HvxVR:$Vu32, HvxVR:$Vv32),
31021"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
31022tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
31023let Inst{7-5} = 0b001;
31024let Inst{13-13} = 0b0;
31025let Inst{31-21} = 0b00011111011;
31026let hasNewValue = 1;
31027let opNewValue = 0;
31028let isCVI = 1;
31029let isHVXALU = 1;
31030let isHVXALU2SRC = 1;
31031let DecoderNamespace = "EXT_mmvec";
31032}
31033def V6_vadduwsat_alt : HInst<
31034(outs HvxVR:$Vd32),
31035(ins HvxVR:$Vu32, HvxVR:$Vv32),
31036"$Vd32 = vadduw($Vu32,$Vv32):sat",
31037PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31038let hasNewValue = 1;
31039let opNewValue = 0;
31040let isCVI = 1;
31041let isPseudo = 1;
31042let isCodeGenOnly = 1;
31043let DecoderNamespace = "EXT_mmvec";
31044}
31045def V6_vadduwsat_dv : HInst<
31046(outs HvxWR:$Vdd32),
31047(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31048"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
31049tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
31050let Inst{7-5} = 0b010;
31051let Inst{13-13} = 0b0;
31052let Inst{31-21} = 0b00011110101;
31053let hasNewValue = 1;
31054let opNewValue = 0;
31055let isCVI = 1;
31056let DecoderNamespace = "EXT_mmvec";
31057}
31058def V6_vadduwsat_dv_alt : HInst<
31059(outs HvxWR:$Vdd32),
31060(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31061"$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
31062PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31063let hasNewValue = 1;
31064let opNewValue = 0;
31065let isCVI = 1;
31066let isPseudo = 1;
31067let isCodeGenOnly = 1;
31068let DecoderNamespace = "EXT_mmvec";
31069}
31070def V6_vaddw : HInst<
31071(outs HvxVR:$Vd32),
31072(ins HvxVR:$Vu32, HvxVR:$Vv32),
31073"$Vd32.w = vadd($Vu32.w,$Vv32.w)",
31074tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31075let Inst{7-5} = 0b000;
31076let Inst{13-13} = 0b0;
31077let Inst{31-21} = 0b00011100010;
31078let hasNewValue = 1;
31079let opNewValue = 0;
31080let isCVI = 1;
31081let isHVXALU = 1;
31082let isHVXALU2SRC = 1;
31083let DecoderNamespace = "EXT_mmvec";
31084}
31085def V6_vaddw_alt : HInst<
31086(outs HvxVR:$Vd32),
31087(ins HvxVR:$Vu32, HvxVR:$Vv32),
31088"$Vd32 = vaddw($Vu32,$Vv32)",
31089PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31090let hasNewValue = 1;
31091let opNewValue = 0;
31092let isCVI = 1;
31093let isPseudo = 1;
31094let isCodeGenOnly = 1;
31095let DecoderNamespace = "EXT_mmvec";
31096}
31097def V6_vaddw_dv : HInst<
31098(outs HvxWR:$Vdd32),
31099(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31100"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
31101tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
31102let Inst{7-5} = 0b110;
31103let Inst{13-13} = 0b0;
31104let Inst{31-21} = 0b00011100011;
31105let hasNewValue = 1;
31106let opNewValue = 0;
31107let isCVI = 1;
31108let DecoderNamespace = "EXT_mmvec";
31109}
31110def V6_vaddw_dv_alt : HInst<
31111(outs HvxWR:$Vdd32),
31112(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31113"$Vdd32 = vaddw($Vuu32,$Vvv32)",
31114PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31115let hasNewValue = 1;
31116let opNewValue = 0;
31117let isCVI = 1;
31118let isPseudo = 1;
31119let isCodeGenOnly = 1;
31120let DecoderNamespace = "EXT_mmvec";
31121}
31122def V6_vaddwnq : HInst<
31123(outs HvxVR:$Vx32),
31124(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31125"if (!$Qv4) $Vx32.w += $Vu32.w",
31126tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
31127let Inst{7-5} = 0b101;
31128let Inst{13-13} = 0b1;
31129let Inst{21-16} = 0b000001;
31130let Inst{31-24} = 0b00011110;
31131let hasNewValue = 1;
31132let opNewValue = 0;
31133let isAccumulator = 1;
31134let isCVI = 1;
31135let isHVXALU = 1;
31136let isHVXALU2SRC = 1;
31137let DecoderNamespace = "EXT_mmvec";
31138let Constraints = "$Vx32 = $Vx32in";
31139}
31140def V6_vaddwnq_alt : HInst<
31141(outs HvxVR:$Vx32),
31142(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31143"if (!$Qv4.w) $Vx32.w += $Vu32.w",
31144PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31145let hasNewValue = 1;
31146let opNewValue = 0;
31147let isAccumulator = 1;
31148let isCVI = 1;
31149let isPseudo = 1;
31150let isCodeGenOnly = 1;
31151let DecoderNamespace = "EXT_mmvec";
31152let Constraints = "$Vx32 = $Vx32in";
31153}
31154def V6_vaddwq : HInst<
31155(outs HvxVR:$Vx32),
31156(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31157"if ($Qv4) $Vx32.w += $Vu32.w",
31158tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
31159let Inst{7-5} = 0b010;
31160let Inst{13-13} = 0b1;
31161let Inst{21-16} = 0b000001;
31162let Inst{31-24} = 0b00011110;
31163let hasNewValue = 1;
31164let opNewValue = 0;
31165let isAccumulator = 1;
31166let isCVI = 1;
31167let isHVXALU = 1;
31168let isHVXALU2SRC = 1;
31169let DecoderNamespace = "EXT_mmvec";
31170let Constraints = "$Vx32 = $Vx32in";
31171}
31172def V6_vaddwq_alt : HInst<
31173(outs HvxVR:$Vx32),
31174(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
31175"if ($Qv4.w) $Vx32.w += $Vu32.w",
31176PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31177let hasNewValue = 1;
31178let opNewValue = 0;
31179let isAccumulator = 1;
31180let isCVI = 1;
31181let isPseudo = 1;
31182let isCodeGenOnly = 1;
31183let DecoderNamespace = "EXT_mmvec";
31184let Constraints = "$Vx32 = $Vx32in";
31185}
31186def V6_vaddwsat : HInst<
31187(outs HvxVR:$Vd32),
31188(ins HvxVR:$Vu32, HvxVR:$Vv32),
31189"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
31190tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31191let Inst{7-5} = 0b100;
31192let Inst{13-13} = 0b0;
31193let Inst{31-21} = 0b00011100010;
31194let hasNewValue = 1;
31195let opNewValue = 0;
31196let isCVI = 1;
31197let isHVXALU = 1;
31198let isHVXALU2SRC = 1;
31199let DecoderNamespace = "EXT_mmvec";
31200}
31201def V6_vaddwsat_alt : HInst<
31202(outs HvxVR:$Vd32),
31203(ins HvxVR:$Vu32, HvxVR:$Vv32),
31204"$Vd32 = vaddw($Vu32,$Vv32):sat",
31205PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31206let hasNewValue = 1;
31207let opNewValue = 0;
31208let isCVI = 1;
31209let isPseudo = 1;
31210let isCodeGenOnly = 1;
31211let DecoderNamespace = "EXT_mmvec";
31212}
31213def V6_vaddwsat_dv : HInst<
31214(outs HvxWR:$Vdd32),
31215(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31216"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
31217tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
31218let Inst{7-5} = 0b010;
31219let Inst{13-13} = 0b0;
31220let Inst{31-21} = 0b00011100100;
31221let hasNewValue = 1;
31222let opNewValue = 0;
31223let isCVI = 1;
31224let DecoderNamespace = "EXT_mmvec";
31225}
31226def V6_vaddwsat_dv_alt : HInst<
31227(outs HvxWR:$Vdd32),
31228(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
31229"$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
31230PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31231let hasNewValue = 1;
31232let opNewValue = 0;
31233let isCVI = 1;
31234let isPseudo = 1;
31235let isCodeGenOnly = 1;
31236let DecoderNamespace = "EXT_mmvec";
31237}
31238def V6_valignb : HInst<
31239(outs HvxVR:$Vd32),
31240(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31241"$Vd32 = valign($Vu32,$Vv32,$Rt8)",
31242tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
31243let Inst{7-5} = 0b000;
31244let Inst{13-13} = 0b0;
31245let Inst{31-24} = 0b00011011;
31246let hasNewValue = 1;
31247let opNewValue = 0;
31248let isCVI = 1;
31249let DecoderNamespace = "EXT_mmvec";
31250}
31251def V6_valignbi : HInst<
31252(outs HvxVR:$Vd32),
31253(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
31254"$Vd32 = valign($Vu32,$Vv32,#$Ii)",
31255tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
31256let Inst{13-13} = 0b1;
31257let Inst{31-21} = 0b00011110001;
31258let hasNewValue = 1;
31259let opNewValue = 0;
31260let isCVI = 1;
31261let DecoderNamespace = "EXT_mmvec";
31262}
31263def V6_vand : HInst<
31264(outs HvxVR:$Vd32),
31265(ins HvxVR:$Vu32, HvxVR:$Vv32),
31266"$Vd32 = vand($Vu32,$Vv32)",
31267tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31268let Inst{7-5} = 0b101;
31269let Inst{13-13} = 0b0;
31270let Inst{31-21} = 0b00011100001;
31271let hasNewValue = 1;
31272let opNewValue = 0;
31273let isCVI = 1;
31274let isHVXALU = 1;
31275let isHVXALU2SRC = 1;
31276let DecoderNamespace = "EXT_mmvec";
31277}
31278def V6_vandnqrt : HInst<
31279(outs HvxVR:$Vd32),
31280(ins HvxQR:$Qu4, IntRegs:$Rt32),
31281"$Vd32 = vand(!$Qu4,$Rt32)",
31282tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV62]> {
31283let Inst{7-5} = 0b101;
31284let Inst{13-10} = 0b0001;
31285let Inst{31-21} = 0b00011001101;
31286let hasNewValue = 1;
31287let opNewValue = 0;
31288let isCVI = 1;
31289let DecoderNamespace = "EXT_mmvec";
31290}
31291def V6_vandnqrt_acc : HInst<
31292(outs HvxVR:$Vx32),
31293(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31294"$Vx32 |= vand(!$Qu4,$Rt32)",
31295tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV62]> {
31296let Inst{7-5} = 0b011;
31297let Inst{13-10} = 0b1001;
31298let Inst{31-21} = 0b00011001011;
31299let hasNewValue = 1;
31300let opNewValue = 0;
31301let isAccumulator = 1;
31302let isCVI = 1;
31303let DecoderNamespace = "EXT_mmvec";
31304let Constraints = "$Vx32 = $Vx32in";
31305}
31306def V6_vandnqrt_acc_alt : HInst<
31307(outs HvxVR:$Vx32),
31308(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31309"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
31310PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31311let hasNewValue = 1;
31312let opNewValue = 0;
31313let isAccumulator = 1;
31314let isCVI = 1;
31315let isPseudo = 1;
31316let isCodeGenOnly = 1;
31317let DecoderNamespace = "EXT_mmvec";
31318let Constraints = "$Vx32 = $Vx32in";
31319}
31320def V6_vandnqrt_alt : HInst<
31321(outs HvxVR:$Vd32),
31322(ins HvxQR:$Qu4, IntRegs:$Rt32),
31323"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
31324PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
31325let hasNewValue = 1;
31326let opNewValue = 0;
31327let isCVI = 1;
31328let isPseudo = 1;
31329let isCodeGenOnly = 1;
31330let DecoderNamespace = "EXT_mmvec";
31331}
31332def V6_vandqrt : HInst<
31333(outs HvxVR:$Vd32),
31334(ins HvxQR:$Qu4, IntRegs:$Rt32),
31335"$Vd32 = vand($Qu4,$Rt32)",
31336tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
31337let Inst{7-5} = 0b101;
31338let Inst{13-10} = 0b0000;
31339let Inst{31-21} = 0b00011001101;
31340let hasNewValue = 1;
31341let opNewValue = 0;
31342let isCVI = 1;
31343let DecoderNamespace = "EXT_mmvec";
31344}
31345def V6_vandqrt_acc : HInst<
31346(outs HvxVR:$Vx32),
31347(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31348"$Vx32 |= vand($Qu4,$Rt32)",
31349tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
31350let Inst{7-5} = 0b011;
31351let Inst{13-10} = 0b1000;
31352let Inst{31-21} = 0b00011001011;
31353let hasNewValue = 1;
31354let opNewValue = 0;
31355let isAccumulator = 1;
31356let isCVI = 1;
31357let DecoderNamespace = "EXT_mmvec";
31358let Constraints = "$Vx32 = $Vx32in";
31359}
31360def V6_vandqrt_acc_alt : HInst<
31361(outs HvxVR:$Vx32),
31362(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
31363"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
31364PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31365let hasNewValue = 1;
31366let opNewValue = 0;
31367let isAccumulator = 1;
31368let isCVI = 1;
31369let isPseudo = 1;
31370let isCodeGenOnly = 1;
31371let DecoderNamespace = "EXT_mmvec";
31372let Constraints = "$Vx32 = $Vx32in";
31373}
31374def V6_vandqrt_alt : HInst<
31375(outs HvxVR:$Vd32),
31376(ins HvxQR:$Qu4, IntRegs:$Rt32),
31377"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
31378PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31379let hasNewValue = 1;
31380let opNewValue = 0;
31381let isCVI = 1;
31382let isPseudo = 1;
31383let isCodeGenOnly = 1;
31384let DecoderNamespace = "EXT_mmvec";
31385}
31386def V6_vandvnqv : HInst<
31387(outs HvxVR:$Vd32),
31388(ins HvxQR:$Qv4, HvxVR:$Vu32),
31389"$Vd32 = vand(!$Qv4,$Vu32)",
31390tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31391let Inst{7-5} = 0b001;
31392let Inst{13-13} = 0b1;
31393let Inst{21-16} = 0b000011;
31394let Inst{31-24} = 0b00011110;
31395let hasNewValue = 1;
31396let opNewValue = 0;
31397let isCVI = 1;
31398let isHVXALU = 1;
31399let isHVXALU2SRC = 1;
31400let DecoderNamespace = "EXT_mmvec";
31401}
31402def V6_vandvqv : HInst<
31403(outs HvxVR:$Vd32),
31404(ins HvxQR:$Qv4, HvxVR:$Vu32),
31405"$Vd32 = vand($Qv4,$Vu32)",
31406tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31407let Inst{7-5} = 0b000;
31408let Inst{13-13} = 0b1;
31409let Inst{21-16} = 0b000011;
31410let Inst{31-24} = 0b00011110;
31411let hasNewValue = 1;
31412let opNewValue = 0;
31413let isCVI = 1;
31414let isHVXALU = 1;
31415let isHVXALU2SRC = 1;
31416let DecoderNamespace = "EXT_mmvec";
31417}
31418def V6_vandvrt : HInst<
31419(outs HvxQR:$Qd4),
31420(ins HvxVR:$Vu32, IntRegs:$Rt32),
31421"$Qd4 = vand($Vu32,$Rt32)",
31422tc_ac4046bc, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
31423let Inst{7-2} = 0b010010;
31424let Inst{13-13} = 0b0;
31425let Inst{31-21} = 0b00011001101;
31426let hasNewValue = 1;
31427let opNewValue = 0;
31428let isCVI = 1;
31429let DecoderNamespace = "EXT_mmvec";
31430}
31431def V6_vandvrt_acc : HInst<
31432(outs HvxQR:$Qx4),
31433(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31434"$Qx4 |= vand($Vu32,$Rt32)",
31435tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
31436let Inst{7-2} = 0b100000;
31437let Inst{13-13} = 0b1;
31438let Inst{31-21} = 0b00011001011;
31439let isAccumulator = 1;
31440let isCVI = 1;
31441let DecoderNamespace = "EXT_mmvec";
31442let Constraints = "$Qx4 = $Qx4in";
31443}
31444def V6_vandvrt_acc_alt : HInst<
31445(outs HvxQR:$Qx4),
31446(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31447"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
31448PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31449let isAccumulator = 1;
31450let isCVI = 1;
31451let isPseudo = 1;
31452let isCodeGenOnly = 1;
31453let DecoderNamespace = "EXT_mmvec";
31454let Constraints = "$Qx4 = $Qx4in";
31455}
31456def V6_vandvrt_alt : HInst<
31457(outs HvxQR:$Qd4),
31458(ins HvxVR:$Vu32, IntRegs:$Rt32),
31459"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
31460PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31461let hasNewValue = 1;
31462let opNewValue = 0;
31463let isCVI = 1;
31464let isPseudo = 1;
31465let isCodeGenOnly = 1;
31466let DecoderNamespace = "EXT_mmvec";
31467}
31468def V6_vaslh : HInst<
31469(outs HvxVR:$Vd32),
31470(ins HvxVR:$Vu32, IntRegs:$Rt32),
31471"$Vd32.h = vasl($Vu32.h,$Rt32)",
31472tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31473let Inst{7-5} = 0b000;
31474let Inst{13-13} = 0b0;
31475let Inst{31-21} = 0b00011001100;
31476let hasNewValue = 1;
31477let opNewValue = 0;
31478let isCVI = 1;
31479let DecoderNamespace = "EXT_mmvec";
31480}
31481def V6_vaslh_acc : HInst<
31482(outs HvxVR:$Vx32),
31483(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31484"$Vx32.h += vasl($Vu32.h,$Rt32)",
31485tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31486let Inst{7-5} = 0b101;
31487let Inst{13-13} = 0b1;
31488let Inst{31-21} = 0b00011001101;
31489let hasNewValue = 1;
31490let opNewValue = 0;
31491let isAccumulator = 1;
31492let isCVI = 1;
31493let DecoderNamespace = "EXT_mmvec";
31494let Constraints = "$Vx32 = $Vx32in";
31495}
31496def V6_vaslh_acc_alt : HInst<
31497(outs HvxVR:$Vx32),
31498(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31499"$Vx32 += vaslh($Vu32,$Rt32)",
31500PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31501let hasNewValue = 1;
31502let opNewValue = 0;
31503let isAccumulator = 1;
31504let isCVI = 1;
31505let isPseudo = 1;
31506let isCodeGenOnly = 1;
31507let DecoderNamespace = "EXT_mmvec";
31508let Constraints = "$Vx32 = $Vx32in";
31509}
31510def V6_vaslh_alt : HInst<
31511(outs HvxVR:$Vd32),
31512(ins HvxVR:$Vu32, IntRegs:$Rt32),
31513"$Vd32 = vaslh($Vu32,$Rt32)",
31514PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31515let hasNewValue = 1;
31516let opNewValue = 0;
31517let isCVI = 1;
31518let isPseudo = 1;
31519let isCodeGenOnly = 1;
31520let DecoderNamespace = "EXT_mmvec";
31521}
31522def V6_vaslhv : HInst<
31523(outs HvxVR:$Vd32),
31524(ins HvxVR:$Vu32, HvxVR:$Vv32),
31525"$Vd32.h = vasl($Vu32.h,$Vv32.h)",
31526tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31527let Inst{7-5} = 0b101;
31528let Inst{13-13} = 0b0;
31529let Inst{31-21} = 0b00011111101;
31530let hasNewValue = 1;
31531let opNewValue = 0;
31532let isCVI = 1;
31533let DecoderNamespace = "EXT_mmvec";
31534}
31535def V6_vaslhv_alt : HInst<
31536(outs HvxVR:$Vd32),
31537(ins HvxVR:$Vu32, HvxVR:$Vv32),
31538"$Vd32 = vaslh($Vu32,$Vv32)",
31539PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31540let hasNewValue = 1;
31541let opNewValue = 0;
31542let isCVI = 1;
31543let isPseudo = 1;
31544let isCodeGenOnly = 1;
31545let DecoderNamespace = "EXT_mmvec";
31546}
31547def V6_vaslw : HInst<
31548(outs HvxVR:$Vd32),
31549(ins HvxVR:$Vu32, IntRegs:$Rt32),
31550"$Vd32.w = vasl($Vu32.w,$Rt32)",
31551tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31552let Inst{7-5} = 0b111;
31553let Inst{13-13} = 0b0;
31554let Inst{31-21} = 0b00011001011;
31555let hasNewValue = 1;
31556let opNewValue = 0;
31557let isCVI = 1;
31558let DecoderNamespace = "EXT_mmvec";
31559}
31560def V6_vaslw_acc : HInst<
31561(outs HvxVR:$Vx32),
31562(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31563"$Vx32.w += vasl($Vu32.w,$Rt32)",
31564tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31565let Inst{7-5} = 0b010;
31566let Inst{13-13} = 0b1;
31567let Inst{31-21} = 0b00011001011;
31568let hasNewValue = 1;
31569let opNewValue = 0;
31570let isAccumulator = 1;
31571let isCVI = 1;
31572let DecoderNamespace = "EXT_mmvec";
31573let Constraints = "$Vx32 = $Vx32in";
31574}
31575def V6_vaslw_acc_alt : HInst<
31576(outs HvxVR:$Vx32),
31577(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31578"$Vx32 += vaslw($Vu32,$Rt32)",
31579PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31580let hasNewValue = 1;
31581let opNewValue = 0;
31582let isAccumulator = 1;
31583let isCVI = 1;
31584let isPseudo = 1;
31585let isCodeGenOnly = 1;
31586let DecoderNamespace = "EXT_mmvec";
31587let Constraints = "$Vx32 = $Vx32in";
31588}
31589def V6_vaslw_alt : HInst<
31590(outs HvxVR:$Vd32),
31591(ins HvxVR:$Vu32, IntRegs:$Rt32),
31592"$Vd32 = vaslw($Vu32,$Rt32)",
31593PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31594let hasNewValue = 1;
31595let opNewValue = 0;
31596let isCVI = 1;
31597let isPseudo = 1;
31598let isCodeGenOnly = 1;
31599let DecoderNamespace = "EXT_mmvec";
31600}
31601def V6_vaslwv : HInst<
31602(outs HvxVR:$Vd32),
31603(ins HvxVR:$Vu32, HvxVR:$Vv32),
31604"$Vd32.w = vasl($Vu32.w,$Vv32.w)",
31605tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31606let Inst{7-5} = 0b100;
31607let Inst{13-13} = 0b0;
31608let Inst{31-21} = 0b00011111101;
31609let hasNewValue = 1;
31610let opNewValue = 0;
31611let isCVI = 1;
31612let DecoderNamespace = "EXT_mmvec";
31613}
31614def V6_vaslwv_alt : HInst<
31615(outs HvxVR:$Vd32),
31616(ins HvxVR:$Vu32, HvxVR:$Vv32),
31617"$Vd32 = vaslw($Vu32,$Vv32)",
31618PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31619let hasNewValue = 1;
31620let opNewValue = 0;
31621let isCVI = 1;
31622let isPseudo = 1;
31623let isCodeGenOnly = 1;
31624let DecoderNamespace = "EXT_mmvec";
31625}
31626def V6_vasr_into : HInst<
31627(outs HvxWR:$Vxx32),
31628(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31629"$Vxx32.w = vasrinto($Vu32.w,$Vv32.w)",
31630tc_df80eeb0, TypeCVI_VP_VS>, Enc_3fc427, Requires<[UseHVXV66]> {
31631let Inst{7-5} = 0b111;
31632let Inst{13-13} = 0b1;
31633let Inst{31-21} = 0b00011010101;
31634let hasNewValue = 1;
31635let opNewValue = 0;
31636let isCVI = 1;
31637let DecoderNamespace = "EXT_mmvec";
31638let Constraints = "$Vxx32 = $Vxx32in";
31639}
31640def V6_vasr_into_alt : HInst<
31641(outs HvxWR:$Vxx32),
31642(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31643"$Vxx32 = vasrinto($Vu32,$Vv32)",
31644PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
31645let hasNewValue = 1;
31646let opNewValue = 0;
31647let isCVI = 1;
31648let isPseudo = 1;
31649let isCodeGenOnly = 1;
31650let DecoderNamespace = "EXT_mmvec";
31651let Constraints = "$Vxx32 = $Vxx32in";
31652}
31653def V6_vasrh : HInst<
31654(outs HvxVR:$Vd32),
31655(ins HvxVR:$Vu32, IntRegs:$Rt32),
31656"$Vd32.h = vasr($Vu32.h,$Rt32)",
31657tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31658let Inst{7-5} = 0b110;
31659let Inst{13-13} = 0b0;
31660let Inst{31-21} = 0b00011001011;
31661let hasNewValue = 1;
31662let opNewValue = 0;
31663let isCVI = 1;
31664let DecoderNamespace = "EXT_mmvec";
31665}
31666def V6_vasrh_acc : HInst<
31667(outs HvxVR:$Vx32),
31668(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31669"$Vx32.h += vasr($Vu32.h,$Rt32)",
31670tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31671let Inst{7-5} = 0b111;
31672let Inst{13-13} = 0b1;
31673let Inst{31-21} = 0b00011001100;
31674let hasNewValue = 1;
31675let opNewValue = 0;
31676let isAccumulator = 1;
31677let isCVI = 1;
31678let DecoderNamespace = "EXT_mmvec";
31679let Constraints = "$Vx32 = $Vx32in";
31680}
31681def V6_vasrh_acc_alt : HInst<
31682(outs HvxVR:$Vx32),
31683(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31684"$Vx32 += vasrh($Vu32,$Rt32)",
31685PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31686let hasNewValue = 1;
31687let opNewValue = 0;
31688let isAccumulator = 1;
31689let isCVI = 1;
31690let isPseudo = 1;
31691let isCodeGenOnly = 1;
31692let DecoderNamespace = "EXT_mmvec";
31693let Constraints = "$Vx32 = $Vx32in";
31694}
31695def V6_vasrh_alt : HInst<
31696(outs HvxVR:$Vd32),
31697(ins HvxVR:$Vu32, IntRegs:$Rt32),
31698"$Vd32 = vasrh($Vu32,$Rt32)",
31699PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31700let hasNewValue = 1;
31701let opNewValue = 0;
31702let isCVI = 1;
31703let isPseudo = 1;
31704let isCodeGenOnly = 1;
31705let DecoderNamespace = "EXT_mmvec";
31706}
31707def V6_vasrhbrndsat : HInst<
31708(outs HvxVR:$Vd32),
31709(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31710"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31711tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31712let Inst{7-5} = 0b000;
31713let Inst{13-13} = 0b1;
31714let Inst{31-24} = 0b00011011;
31715let hasNewValue = 1;
31716let opNewValue = 0;
31717let isCVI = 1;
31718let DecoderNamespace = "EXT_mmvec";
31719}
31720def V6_vasrhbsat : HInst<
31721(outs HvxVR:$Vd32),
31722(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31723"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31724tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31725let Inst{7-5} = 0b000;
31726let Inst{13-13} = 0b0;
31727let Inst{31-24} = 0b00011000;
31728let hasNewValue = 1;
31729let opNewValue = 0;
31730let isCVI = 1;
31731let DecoderNamespace = "EXT_mmvec";
31732}
31733def V6_vasrhubrndsat : HInst<
31734(outs HvxVR:$Vd32),
31735(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31736"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31737tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31738let Inst{7-5} = 0b111;
31739let Inst{13-13} = 0b0;
31740let Inst{31-24} = 0b00011011;
31741let hasNewValue = 1;
31742let opNewValue = 0;
31743let isCVI = 1;
31744let DecoderNamespace = "EXT_mmvec";
31745}
31746def V6_vasrhubsat : HInst<
31747(outs HvxVR:$Vd32),
31748(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31749"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31750tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31751let Inst{7-5} = 0b110;
31752let Inst{13-13} = 0b0;
31753let Inst{31-24} = 0b00011011;
31754let hasNewValue = 1;
31755let opNewValue = 0;
31756let isCVI = 1;
31757let DecoderNamespace = "EXT_mmvec";
31758}
31759def V6_vasrhv : HInst<
31760(outs HvxVR:$Vd32),
31761(ins HvxVR:$Vu32, HvxVR:$Vv32),
31762"$Vd32.h = vasr($Vu32.h,$Vv32.h)",
31763tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31764let Inst{7-5} = 0b011;
31765let Inst{13-13} = 0b0;
31766let Inst{31-21} = 0b00011111101;
31767let hasNewValue = 1;
31768let opNewValue = 0;
31769let isCVI = 1;
31770let DecoderNamespace = "EXT_mmvec";
31771}
31772def V6_vasrhv_alt : HInst<
31773(outs HvxVR:$Vd32),
31774(ins HvxVR:$Vu32, HvxVR:$Vv32),
31775"$Vd32 = vasrh($Vu32,$Vv32)",
31776PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31777let hasNewValue = 1;
31778let opNewValue = 0;
31779let isCVI = 1;
31780let isPseudo = 1;
31781let isCodeGenOnly = 1;
31782let DecoderNamespace = "EXT_mmvec";
31783}
31784def V6_vasruhubrndsat : HInst<
31785(outs HvxVR:$Vd32),
31786(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31787"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
31788tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31789let Inst{7-5} = 0b111;
31790let Inst{13-13} = 0b0;
31791let Inst{31-24} = 0b00011000;
31792let hasNewValue = 1;
31793let opNewValue = 0;
31794let isCVI = 1;
31795let DecoderNamespace = "EXT_mmvec";
31796}
31797def V6_vasruhubsat : HInst<
31798(outs HvxVR:$Vd32),
31799(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31800"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
31801tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31802let Inst{7-5} = 0b101;
31803let Inst{13-13} = 0b1;
31804let Inst{31-24} = 0b00011000;
31805let hasNewValue = 1;
31806let opNewValue = 0;
31807let isCVI = 1;
31808let DecoderNamespace = "EXT_mmvec";
31809}
31810def V6_vasruwuhrndsat : HInst<
31811(outs HvxVR:$Vd32),
31812(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31813"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
31814tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31815let Inst{7-5} = 0b001;
31816let Inst{13-13} = 0b0;
31817let Inst{31-24} = 0b00011000;
31818let hasNewValue = 1;
31819let opNewValue = 0;
31820let isCVI = 1;
31821let DecoderNamespace = "EXT_mmvec";
31822}
31823def V6_vasruwuhsat : HInst<
31824(outs HvxVR:$Vd32),
31825(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31826"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
31827tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31828let Inst{7-5} = 0b100;
31829let Inst{13-13} = 0b1;
31830let Inst{31-24} = 0b00011000;
31831let hasNewValue = 1;
31832let opNewValue = 0;
31833let isCVI = 1;
31834let DecoderNamespace = "EXT_mmvec";
31835}
31836def V6_vasrvuhubrndsat : HInst<
31837(outs HvxVR:$Vd32),
31838(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31839"$Vd32.ub = vasr($Vuu32.uh,$Vv32.ub):rnd:sat",
31840tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31841let Inst{7-5} = 0b011;
31842let Inst{13-13} = 0b0;
31843let Inst{31-21} = 0b00011101000;
31844let hasNewValue = 1;
31845let opNewValue = 0;
31846let isCVI = 1;
31847let hasUnaryRestriction = 1;
31848let DecoderNamespace = "EXT_mmvec";
31849}
31850def V6_vasrvuhubsat : HInst<
31851(outs HvxVR:$Vd32),
31852(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31853"$Vd32.ub = vasr($Vuu32.uh,$Vv32.ub):sat",
31854tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31855let Inst{7-5} = 0b010;
31856let Inst{13-13} = 0b0;
31857let Inst{31-21} = 0b00011101000;
31858let hasNewValue = 1;
31859let opNewValue = 0;
31860let isCVI = 1;
31861let hasUnaryRestriction = 1;
31862let DecoderNamespace = "EXT_mmvec";
31863}
31864def V6_vasrvwuhrndsat : HInst<
31865(outs HvxVR:$Vd32),
31866(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31867"$Vd32.uh = vasr($Vuu32.w,$Vv32.uh):rnd:sat",
31868tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31869let Inst{7-5} = 0b001;
31870let Inst{13-13} = 0b0;
31871let Inst{31-21} = 0b00011101000;
31872let hasNewValue = 1;
31873let opNewValue = 0;
31874let isCVI = 1;
31875let hasUnaryRestriction = 1;
31876let DecoderNamespace = "EXT_mmvec";
31877}
31878def V6_vasrvwuhsat : HInst<
31879(outs HvxVR:$Vd32),
31880(ins HvxWR:$Vuu32, HvxVR:$Vv32),
31881"$Vd32.uh = vasr($Vuu32.w,$Vv32.uh):sat",
31882tc_05ca8cfd, TypeCVI_VS>, Enc_de5ea0, Requires<[UseHVXV69]> {
31883let Inst{7-5} = 0b000;
31884let Inst{13-13} = 0b0;
31885let Inst{31-21} = 0b00011101000;
31886let hasNewValue = 1;
31887let opNewValue = 0;
31888let isCVI = 1;
31889let hasUnaryRestriction = 1;
31890let DecoderNamespace = "EXT_mmvec";
31891}
31892def V6_vasrw : HInst<
31893(outs HvxVR:$Vd32),
31894(ins HvxVR:$Vu32, IntRegs:$Rt32),
31895"$Vd32.w = vasr($Vu32.w,$Rt32)",
31896tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31897let Inst{7-5} = 0b101;
31898let Inst{13-13} = 0b0;
31899let Inst{31-21} = 0b00011001011;
31900let hasNewValue = 1;
31901let opNewValue = 0;
31902let isCVI = 1;
31903let DecoderNamespace = "EXT_mmvec";
31904}
31905def V6_vasrw_acc : HInst<
31906(outs HvxVR:$Vx32),
31907(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31908"$Vx32.w += vasr($Vu32.w,$Rt32)",
31909tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31910let Inst{7-5} = 0b101;
31911let Inst{13-13} = 0b1;
31912let Inst{31-21} = 0b00011001011;
31913let hasNewValue = 1;
31914let opNewValue = 0;
31915let isAccumulator = 1;
31916let isCVI = 1;
31917let DecoderNamespace = "EXT_mmvec";
31918let Constraints = "$Vx32 = $Vx32in";
31919}
31920def V6_vasrw_acc_alt : HInst<
31921(outs HvxVR:$Vx32),
31922(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31923"$Vx32 += vasrw($Vu32,$Rt32)",
31924PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31925let hasNewValue = 1;
31926let opNewValue = 0;
31927let isAccumulator = 1;
31928let isCVI = 1;
31929let isPseudo = 1;
31930let isCodeGenOnly = 1;
31931let DecoderNamespace = "EXT_mmvec";
31932let Constraints = "$Vx32 = $Vx32in";
31933}
31934def V6_vasrw_alt : HInst<
31935(outs HvxVR:$Vd32),
31936(ins HvxVR:$Vu32, IntRegs:$Rt32),
31937"$Vd32 = vasrw($Vu32,$Rt32)",
31938PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31939let hasNewValue = 1;
31940let opNewValue = 0;
31941let isCVI = 1;
31942let isPseudo = 1;
31943let isCodeGenOnly = 1;
31944let DecoderNamespace = "EXT_mmvec";
31945}
31946def V6_vasrwh : HInst<
31947(outs HvxVR:$Vd32),
31948(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31949"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
31950tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31951let Inst{7-5} = 0b010;
31952let Inst{13-13} = 0b0;
31953let Inst{31-24} = 0b00011011;
31954let hasNewValue = 1;
31955let opNewValue = 0;
31956let isCVI = 1;
31957let DecoderNamespace = "EXT_mmvec";
31958}
31959def V6_vasrwhrndsat : HInst<
31960(outs HvxVR:$Vd32),
31961(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31962"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31963tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31964let Inst{7-5} = 0b100;
31965let Inst{13-13} = 0b0;
31966let Inst{31-24} = 0b00011011;
31967let hasNewValue = 1;
31968let opNewValue = 0;
31969let isCVI = 1;
31970let DecoderNamespace = "EXT_mmvec";
31971}
31972def V6_vasrwhsat : HInst<
31973(outs HvxVR:$Vd32),
31974(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31975"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31976tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31977let Inst{7-5} = 0b011;
31978let Inst{13-13} = 0b0;
31979let Inst{31-24} = 0b00011011;
31980let hasNewValue = 1;
31981let opNewValue = 0;
31982let isCVI = 1;
31983let DecoderNamespace = "EXT_mmvec";
31984}
31985def V6_vasrwuhrndsat : HInst<
31986(outs HvxVR:$Vd32),
31987(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31988"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31989tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31990let Inst{7-5} = 0b010;
31991let Inst{13-13} = 0b0;
31992let Inst{31-24} = 0b00011000;
31993let hasNewValue = 1;
31994let opNewValue = 0;
31995let isCVI = 1;
31996let DecoderNamespace = "EXT_mmvec";
31997}
31998def V6_vasrwuhsat : HInst<
31999(outs HvxVR:$Vd32),
32000(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32001"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
32002tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
32003let Inst{7-5} = 0b101;
32004let Inst{13-13} = 0b0;
32005let Inst{31-24} = 0b00011011;
32006let hasNewValue = 1;
32007let opNewValue = 0;
32008let isCVI = 1;
32009let DecoderNamespace = "EXT_mmvec";
32010}
32011def V6_vasrwv : HInst<
32012(outs HvxVR:$Vd32),
32013(ins HvxVR:$Vu32, HvxVR:$Vv32),
32014"$Vd32.w = vasr($Vu32.w,$Vv32.w)",
32015tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
32016let Inst{7-5} = 0b000;
32017let Inst{13-13} = 0b0;
32018let Inst{31-21} = 0b00011111101;
32019let hasNewValue = 1;
32020let opNewValue = 0;
32021let isCVI = 1;
32022let DecoderNamespace = "EXT_mmvec";
32023}
32024def V6_vasrwv_alt : HInst<
32025(outs HvxVR:$Vd32),
32026(ins HvxVR:$Vu32, HvxVR:$Vv32),
32027"$Vd32 = vasrw($Vu32,$Vv32)",
32028PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32029let hasNewValue = 1;
32030let opNewValue = 0;
32031let isCVI = 1;
32032let isPseudo = 1;
32033let isCodeGenOnly = 1;
32034let DecoderNamespace = "EXT_mmvec";
32035}
32036def V6_vassign : HInst<
32037(outs HvxVR:$Vd32),
32038(ins HvxVR:$Vu32),
32039"$Vd32 = $Vu32",
32040tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
32041let Inst{7-5} = 0b111;
32042let Inst{13-13} = 0b1;
32043let Inst{31-16} = 0b0001111000000011;
32044let hasNewValue = 1;
32045let opNewValue = 0;
32046let isCVI = 1;
32047let isHVXALU = 1;
32048let DecoderNamespace = "EXT_mmvec";
32049}
32050def V6_vassign_fp : HInst<
32051(outs HvxVR:$Vd32),
32052(ins HvxVR:$Vu32),
32053"$Vd32.w = vfmv($Vu32.w)",
32054tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32055let Inst{7-5} = 0b001;
32056let Inst{13-13} = 0b1;
32057let Inst{31-16} = 0b0001111000000110;
32058let hasNewValue = 1;
32059let opNewValue = 0;
32060let isCVI = 1;
32061let DecoderNamespace = "EXT_mmvec";
32062}
32063def V6_vassign_tmp : HInst<
32064(outs HvxVR:$Vd32),
32065(ins HvxVR:$Vu32),
32066"$Vd32.tmp = $Vu32",
32067tc_e2fdd6e6, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV69]> {
32068let Inst{7-5} = 0b110;
32069let Inst{13-13} = 0b0;
32070let Inst{31-16} = 0b0001111000000001;
32071let hasNewValue = 1;
32072let opNewValue = 0;
32073let isCVI = 1;
32074let hasHvxTmp = 1;
32075let DecoderNamespace = "EXT_mmvec";
32076}
32077def V6_vassignp : HInst<
32078(outs HvxWR:$Vdd32),
32079(ins HvxWR:$Vuu32),
32080"$Vdd32 = $Vuu32",
32081CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
32082let hasNewValue = 1;
32083let opNewValue = 0;
32084let isCVI = 1;
32085let isPseudo = 1;
32086let DecoderNamespace = "EXT_mmvec";
32087}
32088def V6_vavgb : HInst<
32089(outs HvxVR:$Vd32),
32090(ins HvxVR:$Vu32, HvxVR:$Vv32),
32091"$Vd32.b = vavg($Vu32.b,$Vv32.b)",
32092tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32093let Inst{7-5} = 0b100;
32094let Inst{13-13} = 0b1;
32095let Inst{31-21} = 0b00011111000;
32096let hasNewValue = 1;
32097let opNewValue = 0;
32098let isCVI = 1;
32099let isHVXALU = 1;
32100let isHVXALU2SRC = 1;
32101let DecoderNamespace = "EXT_mmvec";
32102}
32103def V6_vavgb_alt : HInst<
32104(outs HvxVR:$Vd32),
32105(ins HvxVR:$Vu32, HvxVR:$Vv32),
32106"$Vd32 = vavgb($Vu32,$Vv32)",
32107PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32108let hasNewValue = 1;
32109let opNewValue = 0;
32110let isCVI = 1;
32111let isPseudo = 1;
32112let isCodeGenOnly = 1;
32113let DecoderNamespace = "EXT_mmvec";
32114}
32115def V6_vavgbrnd : HInst<
32116(outs HvxVR:$Vd32),
32117(ins HvxVR:$Vu32, HvxVR:$Vv32),
32118"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
32119tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32120let Inst{7-5} = 0b101;
32121let Inst{13-13} = 0b1;
32122let Inst{31-21} = 0b00011111000;
32123let hasNewValue = 1;
32124let opNewValue = 0;
32125let isCVI = 1;
32126let isHVXALU = 1;
32127let isHVXALU2SRC = 1;
32128let DecoderNamespace = "EXT_mmvec";
32129}
32130def V6_vavgbrnd_alt : HInst<
32131(outs HvxVR:$Vd32),
32132(ins HvxVR:$Vu32, HvxVR:$Vv32),
32133"$Vd32 = vavgb($Vu32,$Vv32):rnd",
32134PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32135let hasNewValue = 1;
32136let opNewValue = 0;
32137let isCVI = 1;
32138let isPseudo = 1;
32139let isCodeGenOnly = 1;
32140let DecoderNamespace = "EXT_mmvec";
32141}
32142def V6_vavgh : HInst<
32143(outs HvxVR:$Vd32),
32144(ins HvxVR:$Vu32, HvxVR:$Vv32),
32145"$Vd32.h = vavg($Vu32.h,$Vv32.h)",
32146tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32147let Inst{7-5} = 0b110;
32148let Inst{13-13} = 0b0;
32149let Inst{31-21} = 0b00011100110;
32150let hasNewValue = 1;
32151let opNewValue = 0;
32152let isCVI = 1;
32153let isHVXALU = 1;
32154let isHVXALU2SRC = 1;
32155let DecoderNamespace = "EXT_mmvec";
32156}
32157def V6_vavgh_alt : HInst<
32158(outs HvxVR:$Vd32),
32159(ins HvxVR:$Vu32, HvxVR:$Vv32),
32160"$Vd32 = vavgh($Vu32,$Vv32)",
32161PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32162let hasNewValue = 1;
32163let opNewValue = 0;
32164let isCVI = 1;
32165let isPseudo = 1;
32166let isCodeGenOnly = 1;
32167let DecoderNamespace = "EXT_mmvec";
32168}
32169def V6_vavghrnd : HInst<
32170(outs HvxVR:$Vd32),
32171(ins HvxVR:$Vu32, HvxVR:$Vv32),
32172"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
32173tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32174let Inst{7-5} = 0b101;
32175let Inst{13-13} = 0b0;
32176let Inst{31-21} = 0b00011100111;
32177let hasNewValue = 1;
32178let opNewValue = 0;
32179let isCVI = 1;
32180let isHVXALU = 1;
32181let isHVXALU2SRC = 1;
32182let DecoderNamespace = "EXT_mmvec";
32183}
32184def V6_vavghrnd_alt : HInst<
32185(outs HvxVR:$Vd32),
32186(ins HvxVR:$Vu32, HvxVR:$Vv32),
32187"$Vd32 = vavgh($Vu32,$Vv32):rnd",
32188PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32189let hasNewValue = 1;
32190let opNewValue = 0;
32191let isCVI = 1;
32192let isPseudo = 1;
32193let isCodeGenOnly = 1;
32194let DecoderNamespace = "EXT_mmvec";
32195}
32196def V6_vavgub : HInst<
32197(outs HvxVR:$Vd32),
32198(ins HvxVR:$Vu32, HvxVR:$Vv32),
32199"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
32200tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32201let Inst{7-5} = 0b100;
32202let Inst{13-13} = 0b0;
32203let Inst{31-21} = 0b00011100110;
32204let hasNewValue = 1;
32205let opNewValue = 0;
32206let isCVI = 1;
32207let isHVXALU = 1;
32208let isHVXALU2SRC = 1;
32209let DecoderNamespace = "EXT_mmvec";
32210}
32211def V6_vavgub_alt : HInst<
32212(outs HvxVR:$Vd32),
32213(ins HvxVR:$Vu32, HvxVR:$Vv32),
32214"$Vd32 = vavgub($Vu32,$Vv32)",
32215PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32216let hasNewValue = 1;
32217let opNewValue = 0;
32218let isCVI = 1;
32219let isPseudo = 1;
32220let isCodeGenOnly = 1;
32221let DecoderNamespace = "EXT_mmvec";
32222}
32223def V6_vavgubrnd : HInst<
32224(outs HvxVR:$Vd32),
32225(ins HvxVR:$Vu32, HvxVR:$Vv32),
32226"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
32227tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32228let Inst{7-5} = 0b011;
32229let Inst{13-13} = 0b0;
32230let Inst{31-21} = 0b00011100111;
32231let hasNewValue = 1;
32232let opNewValue = 0;
32233let isCVI = 1;
32234let isHVXALU = 1;
32235let isHVXALU2SRC = 1;
32236let DecoderNamespace = "EXT_mmvec";
32237}
32238def V6_vavgubrnd_alt : HInst<
32239(outs HvxVR:$Vd32),
32240(ins HvxVR:$Vu32, HvxVR:$Vv32),
32241"$Vd32 = vavgub($Vu32,$Vv32):rnd",
32242PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32243let hasNewValue = 1;
32244let opNewValue = 0;
32245let isCVI = 1;
32246let isPseudo = 1;
32247let isCodeGenOnly = 1;
32248let DecoderNamespace = "EXT_mmvec";
32249}
32250def V6_vavguh : HInst<
32251(outs HvxVR:$Vd32),
32252(ins HvxVR:$Vu32, HvxVR:$Vv32),
32253"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
32254tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32255let Inst{7-5} = 0b101;
32256let Inst{13-13} = 0b0;
32257let Inst{31-21} = 0b00011100110;
32258let hasNewValue = 1;
32259let opNewValue = 0;
32260let isCVI = 1;
32261let isHVXALU = 1;
32262let isHVXALU2SRC = 1;
32263let DecoderNamespace = "EXT_mmvec";
32264}
32265def V6_vavguh_alt : HInst<
32266(outs HvxVR:$Vd32),
32267(ins HvxVR:$Vu32, HvxVR:$Vv32),
32268"$Vd32 = vavguh($Vu32,$Vv32)",
32269PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32270let hasNewValue = 1;
32271let opNewValue = 0;
32272let isCVI = 1;
32273let isPseudo = 1;
32274let isCodeGenOnly = 1;
32275let DecoderNamespace = "EXT_mmvec";
32276}
32277def V6_vavguhrnd : HInst<
32278(outs HvxVR:$Vd32),
32279(ins HvxVR:$Vu32, HvxVR:$Vv32),
32280"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
32281tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32282let Inst{7-5} = 0b100;
32283let Inst{13-13} = 0b0;
32284let Inst{31-21} = 0b00011100111;
32285let hasNewValue = 1;
32286let opNewValue = 0;
32287let isCVI = 1;
32288let isHVXALU = 1;
32289let isHVXALU2SRC = 1;
32290let DecoderNamespace = "EXT_mmvec";
32291}
32292def V6_vavguhrnd_alt : HInst<
32293(outs HvxVR:$Vd32),
32294(ins HvxVR:$Vu32, HvxVR:$Vv32),
32295"$Vd32 = vavguh($Vu32,$Vv32):rnd",
32296PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32297let hasNewValue = 1;
32298let opNewValue = 0;
32299let isCVI = 1;
32300let isPseudo = 1;
32301let isCodeGenOnly = 1;
32302let DecoderNamespace = "EXT_mmvec";
32303}
32304def V6_vavguw : HInst<
32305(outs HvxVR:$Vd32),
32306(ins HvxVR:$Vu32, HvxVR:$Vv32),
32307"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
32308tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32309let Inst{7-5} = 0b010;
32310let Inst{13-13} = 0b1;
32311let Inst{31-21} = 0b00011111000;
32312let hasNewValue = 1;
32313let opNewValue = 0;
32314let isCVI = 1;
32315let isHVXALU = 1;
32316let isHVXALU2SRC = 1;
32317let DecoderNamespace = "EXT_mmvec";
32318}
32319def V6_vavguw_alt : HInst<
32320(outs HvxVR:$Vd32),
32321(ins HvxVR:$Vu32, HvxVR:$Vv32),
32322"$Vd32 = vavguw($Vu32,$Vv32)",
32323PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32324let hasNewValue = 1;
32325let opNewValue = 0;
32326let isCVI = 1;
32327let isPseudo = 1;
32328let isCodeGenOnly = 1;
32329let DecoderNamespace = "EXT_mmvec";
32330}
32331def V6_vavguwrnd : HInst<
32332(outs HvxVR:$Vd32),
32333(ins HvxVR:$Vu32, HvxVR:$Vv32),
32334"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
32335tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
32336let Inst{7-5} = 0b011;
32337let Inst{13-13} = 0b1;
32338let Inst{31-21} = 0b00011111000;
32339let hasNewValue = 1;
32340let opNewValue = 0;
32341let isCVI = 1;
32342let isHVXALU = 1;
32343let isHVXALU2SRC = 1;
32344let DecoderNamespace = "EXT_mmvec";
32345}
32346def V6_vavguwrnd_alt : HInst<
32347(outs HvxVR:$Vd32),
32348(ins HvxVR:$Vu32, HvxVR:$Vv32),
32349"$Vd32 = vavguw($Vu32,$Vv32):rnd",
32350PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
32351let hasNewValue = 1;
32352let opNewValue = 0;
32353let isCVI = 1;
32354let isPseudo = 1;
32355let isCodeGenOnly = 1;
32356let DecoderNamespace = "EXT_mmvec";
32357}
32358def V6_vavgw : HInst<
32359(outs HvxVR:$Vd32),
32360(ins HvxVR:$Vu32, HvxVR:$Vv32),
32361"$Vd32.w = vavg($Vu32.w,$Vv32.w)",
32362tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32363let Inst{7-5} = 0b111;
32364let Inst{13-13} = 0b0;
32365let Inst{31-21} = 0b00011100110;
32366let hasNewValue = 1;
32367let opNewValue = 0;
32368let isCVI = 1;
32369let isHVXALU = 1;
32370let isHVXALU2SRC = 1;
32371let DecoderNamespace = "EXT_mmvec";
32372}
32373def V6_vavgw_alt : HInst<
32374(outs HvxVR:$Vd32),
32375(ins HvxVR:$Vu32, HvxVR:$Vv32),
32376"$Vd32 = vavgw($Vu32,$Vv32)",
32377PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32378let hasNewValue = 1;
32379let opNewValue = 0;
32380let isCVI = 1;
32381let isPseudo = 1;
32382let isCodeGenOnly = 1;
32383let DecoderNamespace = "EXT_mmvec";
32384}
32385def V6_vavgwrnd : HInst<
32386(outs HvxVR:$Vd32),
32387(ins HvxVR:$Vu32, HvxVR:$Vv32),
32388"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
32389tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
32390let Inst{7-5} = 0b110;
32391let Inst{13-13} = 0b0;
32392let Inst{31-21} = 0b00011100111;
32393let hasNewValue = 1;
32394let opNewValue = 0;
32395let isCVI = 1;
32396let isHVXALU = 1;
32397let isHVXALU2SRC = 1;
32398let DecoderNamespace = "EXT_mmvec";
32399}
32400def V6_vavgwrnd_alt : HInst<
32401(outs HvxVR:$Vd32),
32402(ins HvxVR:$Vu32, HvxVR:$Vv32),
32403"$Vd32 = vavgw($Vu32,$Vv32):rnd",
32404PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32405let hasNewValue = 1;
32406let opNewValue = 0;
32407let isCVI = 1;
32408let isPseudo = 1;
32409let isCodeGenOnly = 1;
32410let DecoderNamespace = "EXT_mmvec";
32411}
32412def V6_vccombine : HInst<
32413(outs HvxWR:$Vdd32),
32414(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
32415"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
32416tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
32417let Inst{7-7} = 0b0;
32418let Inst{13-13} = 0b0;
32419let Inst{31-21} = 0b00011010011;
32420let isPredicated = 1;
32421let hasNewValue = 1;
32422let opNewValue = 0;
32423let isCVI = 1;
32424let DecoderNamespace = "EXT_mmvec";
32425}
32426def V6_vcl0h : HInst<
32427(outs HvxVR:$Vd32),
32428(ins HvxVR:$Vu32),
32429"$Vd32.uh = vcl0($Vu32.uh)",
32430tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
32431let Inst{7-5} = 0b111;
32432let Inst{13-13} = 0b0;
32433let Inst{31-16} = 0b0001111000000010;
32434let hasNewValue = 1;
32435let opNewValue = 0;
32436let isCVI = 1;
32437let DecoderNamespace = "EXT_mmvec";
32438}
32439def V6_vcl0h_alt : HInst<
32440(outs HvxVR:$Vd32),
32441(ins HvxVR:$Vu32),
32442"$Vd32 = vcl0h($Vu32)",
32443PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32444let hasNewValue = 1;
32445let opNewValue = 0;
32446let isCVI = 1;
32447let isPseudo = 1;
32448let isCodeGenOnly = 1;
32449let DecoderNamespace = "EXT_mmvec";
32450}
32451def V6_vcl0w : HInst<
32452(outs HvxVR:$Vd32),
32453(ins HvxVR:$Vu32),
32454"$Vd32.uw = vcl0($Vu32.uw)",
32455tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
32456let Inst{7-5} = 0b101;
32457let Inst{13-13} = 0b0;
32458let Inst{31-16} = 0b0001111000000010;
32459let hasNewValue = 1;
32460let opNewValue = 0;
32461let isCVI = 1;
32462let DecoderNamespace = "EXT_mmvec";
32463}
32464def V6_vcl0w_alt : HInst<
32465(outs HvxVR:$Vd32),
32466(ins HvxVR:$Vu32),
32467"$Vd32 = vcl0w($Vu32)",
32468PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32469let hasNewValue = 1;
32470let opNewValue = 0;
32471let isCVI = 1;
32472let isPseudo = 1;
32473let isCodeGenOnly = 1;
32474let DecoderNamespace = "EXT_mmvec";
32475}
32476def V6_vcmov : HInst<
32477(outs HvxVR:$Vd32),
32478(ins PredRegs:$Ps4, HvxVR:$Vu32),
32479"if ($Ps4) $Vd32 = $Vu32",
32480tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
32481let Inst{7-7} = 0b0;
32482let Inst{13-13} = 0b0;
32483let Inst{31-16} = 0b0001101000000000;
32484let isPredicated = 1;
32485let hasNewValue = 1;
32486let opNewValue = 0;
32487let isCVI = 1;
32488let isHVXALU = 1;
32489let DecoderNamespace = "EXT_mmvec";
32490}
32491def V6_vcombine : HInst<
32492(outs HvxWR:$Vdd32),
32493(ins HvxVR:$Vu32, HvxVR:$Vv32),
32494"$Vdd32 = vcombine($Vu32,$Vv32)",
32495tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
32496let Inst{7-5} = 0b111;
32497let Inst{13-13} = 0b0;
32498let Inst{31-21} = 0b00011111010;
32499let hasNewValue = 1;
32500let opNewValue = 0;
32501let isCVI = 1;
32502let isRegSequence = 1;
32503let DecoderNamespace = "EXT_mmvec";
32504}
32505def V6_vcombine_tmp : HInst<
32506(outs HvxWR:$Vdd32),
32507(ins HvxVR:$Vu32, HvxVR:$Vv32),
32508"$Vdd32.tmp = vcombine($Vu32,$Vv32)",
32509tc_531b383c, TypeCVI_VX>, Enc_71bb9b, Requires<[UseHVXV69]> {
32510let Inst{7-5} = 0b111;
32511let Inst{13-13} = 0b0;
32512let Inst{31-21} = 0b00011110101;
32513let hasNewValue = 1;
32514let opNewValue = 0;
32515let isCVI = 1;
32516let hasHvxTmp = 1;
32517let DecoderNamespace = "EXT_mmvec";
32518}
32519def V6_vconv_h_hf : HInst<
32520(outs HvxVR:$Vd32),
32521(ins HvxVR:$Vu32),
32522"$Vd32.h = $Vu32.hf",
32523tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32524let Inst{7-5} = 0b010;
32525let Inst{13-13} = 0b1;
32526let Inst{31-16} = 0b0001111000000101;
32527let hasNewValue = 1;
32528let opNewValue = 0;
32529let isCVI = 1;
32530let DecoderNamespace = "EXT_mmvec";
32531}
32532def V6_vconv_hf_h : HInst<
32533(outs HvxVR:$Vd32),
32534(ins HvxVR:$Vu32),
32535"$Vd32.hf = $Vu32.h",
32536tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32537let Inst{7-5} = 0b100;
32538let Inst{13-13} = 0b1;
32539let Inst{31-16} = 0b0001111000000101;
32540let hasNewValue = 1;
32541let opNewValue = 0;
32542let isCVI = 1;
32543let DecoderNamespace = "EXT_mmvec";
32544}
32545def V6_vconv_hf_qf16 : HInst<
32546(outs HvxVR:$Vd32),
32547(ins HvxVR:$Vu32),
32548"$Vd32.hf = $Vu32.qf16",
32549tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV68,UseHVXQFloat]> {
32550let Inst{7-5} = 0b011;
32551let Inst{13-13} = 0b1;
32552let Inst{31-16} = 0b0001111000000100;
32553let hasNewValue = 1;
32554let opNewValue = 0;
32555let isCVI = 1;
32556let DecoderNamespace = "EXT_mmvec";
32557}
32558def V6_vconv_hf_qf32 : HInst<
32559(outs HvxVR:$Vd32),
32560(ins HvxWR:$Vuu32),
32561"$Vd32.hf = $Vuu32.qf32",
32562tc_51d0ecc3, TypeCVI_VS>, Enc_a33d04, Requires<[UseHVXV68,UseHVXQFloat]> {
32563let Inst{7-5} = 0b110;
32564let Inst{13-13} = 0b1;
32565let Inst{31-16} = 0b0001111000000100;
32566let hasNewValue = 1;
32567let opNewValue = 0;
32568let isCVI = 1;
32569let DecoderNamespace = "EXT_mmvec";
32570}
32571def V6_vconv_sf_qf32 : HInst<
32572(outs HvxVR:$Vd32),
32573(ins HvxVR:$Vu32),
32574"$Vd32.sf = $Vu32.qf32",
32575tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV68,UseHVXQFloat]> {
32576let Inst{7-5} = 0b000;
32577let Inst{13-13} = 0b1;
32578let Inst{31-16} = 0b0001111000000100;
32579let hasNewValue = 1;
32580let opNewValue = 0;
32581let isCVI = 1;
32582let DecoderNamespace = "EXT_mmvec";
32583}
32584def V6_vconv_sf_w : HInst<
32585(outs HvxVR:$Vd32),
32586(ins HvxVR:$Vu32),
32587"$Vd32.sf = $Vu32.w",
32588tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32589let Inst{7-5} = 0b011;
32590let Inst{13-13} = 0b1;
32591let Inst{31-16} = 0b0001111000000101;
32592let hasNewValue = 1;
32593let opNewValue = 0;
32594let isCVI = 1;
32595let DecoderNamespace = "EXT_mmvec";
32596}
32597def V6_vconv_w_sf : HInst<
32598(outs HvxVR:$Vd32),
32599(ins HvxVR:$Vu32),
32600"$Vd32.w = $Vu32.sf",
32601tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV73]> {
32602let Inst{7-5} = 0b001;
32603let Inst{13-13} = 0b1;
32604let Inst{31-16} = 0b0001111000000101;
32605let hasNewValue = 1;
32606let opNewValue = 0;
32607let isCVI = 1;
32608let DecoderNamespace = "EXT_mmvec";
32609}
32610def V6_vcvt_b_hf : HInst<
32611(outs HvxVR:$Vd32),
32612(ins HvxVR:$Vu32, HvxVR:$Vv32),
32613"$Vd32.b = vcvt($Vu32.hf,$Vv32.hf)",
32614tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32615let Inst{7-5} = 0b110;
32616let Inst{13-13} = 0b1;
32617let Inst{31-21} = 0b00011111110;
32618let hasNewValue = 1;
32619let opNewValue = 0;
32620let isCVI = 1;
32621let DecoderNamespace = "EXT_mmvec";
32622}
32623def V6_vcvt_bf_sf : HInst<
32624(outs HvxVR:$Vd32),
32625(ins HvxVR:$Vu32, HvxVR:$Vv32),
32626"$Vd32.bf = vcvt($Vu32.sf,$Vv32.sf)",
32627tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV73,UseHVXIEEEFP]> {
32628let Inst{7-5} = 0b011;
32629let Inst{13-13} = 0b1;
32630let Inst{31-21} = 0b00011101010;
32631let hasNewValue = 1;
32632let opNewValue = 0;
32633let isCVI = 1;
32634let DecoderNamespace = "EXT_mmvec";
32635}
32636def V6_vcvt_h_hf : HInst<
32637(outs HvxVR:$Vd32),
32638(ins HvxVR:$Vu32),
32639"$Vd32.h = vcvt($Vu32.hf)",
32640tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32641let Inst{7-5} = 0b000;
32642let Inst{13-13} = 0b1;
32643let Inst{31-16} = 0b0001111000000110;
32644let hasNewValue = 1;
32645let opNewValue = 0;
32646let isCVI = 1;
32647let DecoderNamespace = "EXT_mmvec";
32648}
32649def V6_vcvt_hf_b : HInst<
32650(outs HvxWR:$Vdd32),
32651(ins HvxVR:$Vu32),
32652"$Vdd32.hf = vcvt($Vu32.b)",
32653tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32654let Inst{7-5} = 0b010;
32655let Inst{13-13} = 0b1;
32656let Inst{31-16} = 0b0001111000000100;
32657let hasNewValue = 1;
32658let opNewValue = 0;
32659let isCVI = 1;
32660let DecoderNamespace = "EXT_mmvec";
32661}
32662def V6_vcvt_hf_h : HInst<
32663(outs HvxVR:$Vd32),
32664(ins HvxVR:$Vu32),
32665"$Vd32.hf = vcvt($Vu32.h)",
32666tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32667let Inst{7-5} = 0b111;
32668let Inst{13-13} = 0b1;
32669let Inst{31-16} = 0b0001111000000100;
32670let hasNewValue = 1;
32671let opNewValue = 0;
32672let isCVI = 1;
32673let DecoderNamespace = "EXT_mmvec";
32674}
32675def V6_vcvt_hf_sf : HInst<
32676(outs HvxVR:$Vd32),
32677(ins HvxVR:$Vu32, HvxVR:$Vv32),
32678"$Vd32.hf = vcvt($Vu32.sf,$Vv32.sf)",
32679tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32680let Inst{7-5} = 0b001;
32681let Inst{13-13} = 0b1;
32682let Inst{31-21} = 0b00011111011;
32683let hasNewValue = 1;
32684let opNewValue = 0;
32685let isCVI = 1;
32686let DecoderNamespace = "EXT_mmvec";
32687}
32688def V6_vcvt_hf_ub : HInst<
32689(outs HvxWR:$Vdd32),
32690(ins HvxVR:$Vu32),
32691"$Vdd32.hf = vcvt($Vu32.ub)",
32692tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32693let Inst{7-5} = 0b001;
32694let Inst{13-13} = 0b1;
32695let Inst{31-16} = 0b0001111000000100;
32696let hasNewValue = 1;
32697let opNewValue = 0;
32698let isCVI = 1;
32699let DecoderNamespace = "EXT_mmvec";
32700}
32701def V6_vcvt_hf_uh : HInst<
32702(outs HvxVR:$Vd32),
32703(ins HvxVR:$Vu32),
32704"$Vd32.hf = vcvt($Vu32.uh)",
32705tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32706let Inst{7-5} = 0b101;
32707let Inst{13-13} = 0b1;
32708let Inst{31-16} = 0b0001111000000100;
32709let hasNewValue = 1;
32710let opNewValue = 0;
32711let isCVI = 1;
32712let DecoderNamespace = "EXT_mmvec";
32713}
32714def V6_vcvt_sf_hf : HInst<
32715(outs HvxWR:$Vdd32),
32716(ins HvxVR:$Vu32),
32717"$Vdd32.sf = vcvt($Vu32.hf)",
32718tc_0afc8be9, TypeCVI_VX_DV>, Enc_dd766a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32719let Inst{7-5} = 0b100;
32720let Inst{13-13} = 0b1;
32721let Inst{31-16} = 0b0001111000000100;
32722let hasNewValue = 1;
32723let opNewValue = 0;
32724let isCVI = 1;
32725let DecoderNamespace = "EXT_mmvec";
32726}
32727def V6_vcvt_ub_hf : HInst<
32728(outs HvxVR:$Vd32),
32729(ins HvxVR:$Vu32, HvxVR:$Vv32),
32730"$Vd32.ub = vcvt($Vu32.hf,$Vv32.hf)",
32731tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32732let Inst{7-5} = 0b101;
32733let Inst{13-13} = 0b1;
32734let Inst{31-21} = 0b00011111110;
32735let hasNewValue = 1;
32736let opNewValue = 0;
32737let isCVI = 1;
32738let DecoderNamespace = "EXT_mmvec";
32739}
32740def V6_vcvt_uh_hf : HInst<
32741(outs HvxVR:$Vd32),
32742(ins HvxVR:$Vu32),
32743"$Vd32.uh = vcvt($Vu32.hf)",
32744tc_3c8c15d0, TypeCVI_VX>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32745let Inst{7-5} = 0b000;
32746let Inst{13-13} = 0b1;
32747let Inst{31-16} = 0b0001111000000101;
32748let hasNewValue = 1;
32749let opNewValue = 0;
32750let isCVI = 1;
32751let DecoderNamespace = "EXT_mmvec";
32752}
32753def V6_vd0 : HInst<
32754(outs HvxVR:$Vd32),
32755(ins),
32756"$Vd32 = #0",
32757CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
32758let hasNewValue = 1;
32759let opNewValue = 0;
32760let isCVI = 1;
32761let isPseudo = 1;
32762let isCodeGenOnly = 1;
32763let DecoderNamespace = "EXT_mmvec";
32764}
32765def V6_vdd0 : HInst<
32766(outs HvxWR:$Vdd32),
32767(ins),
32768"$Vdd32 = #0",
32769tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> {
32770let hasNewValue = 1;
32771let opNewValue = 0;
32772let isCVI = 1;
32773let isPseudo = 1;
32774let isCodeGenOnly = 1;
32775let DecoderNamespace = "EXT_mmvec";
32776}
32777def V6_vdeal : HInst<
32778(outs HvxVR:$Vy32, HvxVR:$Vx32),
32779(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
32780"vdeal($Vy32,$Vx32,$Rt32)",
32781tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
32782let Inst{7-5} = 0b010;
32783let Inst{13-13} = 0b1;
32784let Inst{31-21} = 0b00011001111;
32785let hasNewValue = 1;
32786let opNewValue = 0;
32787let hasNewValue2 = 1;
32788let opNewValue2 = 1;
32789let isCVI = 1;
32790let DecoderNamespace = "EXT_mmvec";
32791let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
32792}
32793def V6_vdealb : HInst<
32794(outs HvxVR:$Vd32),
32795(ins HvxVR:$Vu32),
32796"$Vd32.b = vdeal($Vu32.b)",
32797tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32798let Inst{7-5} = 0b111;
32799let Inst{13-13} = 0b0;
32800let Inst{31-16} = 0b0001111000000000;
32801let hasNewValue = 1;
32802let opNewValue = 0;
32803let isCVI = 1;
32804let DecoderNamespace = "EXT_mmvec";
32805}
32806def V6_vdealb4w : HInst<
32807(outs HvxVR:$Vd32),
32808(ins HvxVR:$Vu32, HvxVR:$Vv32),
32809"$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
32810tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32811let Inst{7-5} = 0b111;
32812let Inst{13-13} = 0b0;
32813let Inst{31-21} = 0b00011111001;
32814let hasNewValue = 1;
32815let opNewValue = 0;
32816let isCVI = 1;
32817let DecoderNamespace = "EXT_mmvec";
32818}
32819def V6_vdealb4w_alt : HInst<
32820(outs HvxVR:$Vd32),
32821(ins HvxVR:$Vu32, HvxVR:$Vv32),
32822"$Vd32 = vdealb4w($Vu32,$Vv32)",
32823PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32824let hasNewValue = 1;
32825let opNewValue = 0;
32826let isCVI = 1;
32827let isPseudo = 1;
32828let isCodeGenOnly = 1;
32829let DecoderNamespace = "EXT_mmvec";
32830}
32831def V6_vdealb_alt : HInst<
32832(outs HvxVR:$Vd32),
32833(ins HvxVR:$Vu32),
32834"$Vd32 = vdealb($Vu32)",
32835PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32836let hasNewValue = 1;
32837let opNewValue = 0;
32838let isCVI = 1;
32839let isPseudo = 1;
32840let isCodeGenOnly = 1;
32841let DecoderNamespace = "EXT_mmvec";
32842}
32843def V6_vdealh : HInst<
32844(outs HvxVR:$Vd32),
32845(ins HvxVR:$Vu32),
32846"$Vd32.h = vdeal($Vu32.h)",
32847tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32848let Inst{7-5} = 0b110;
32849let Inst{13-13} = 0b0;
32850let Inst{31-16} = 0b0001111000000000;
32851let hasNewValue = 1;
32852let opNewValue = 0;
32853let isCVI = 1;
32854let DecoderNamespace = "EXT_mmvec";
32855}
32856def V6_vdealh_alt : HInst<
32857(outs HvxVR:$Vd32),
32858(ins HvxVR:$Vu32),
32859"$Vd32 = vdealh($Vu32)",
32860PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32861let hasNewValue = 1;
32862let opNewValue = 0;
32863let isCVI = 1;
32864let isPseudo = 1;
32865let isCodeGenOnly = 1;
32866let DecoderNamespace = "EXT_mmvec";
32867}
32868def V6_vdealvdd : HInst<
32869(outs HvxWR:$Vdd32),
32870(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32871"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
32872tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
32873let Inst{7-5} = 0b100;
32874let Inst{13-13} = 0b1;
32875let Inst{31-24} = 0b00011011;
32876let hasNewValue = 1;
32877let opNewValue = 0;
32878let isCVI = 1;
32879let DecoderNamespace = "EXT_mmvec";
32880}
32881def V6_vdelta : HInst<
32882(outs HvxVR:$Vd32),
32883(ins HvxVR:$Vu32, HvxVR:$Vv32),
32884"$Vd32 = vdelta($Vu32,$Vv32)",
32885tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32886let Inst{7-5} = 0b001;
32887let Inst{13-13} = 0b0;
32888let Inst{31-21} = 0b00011111001;
32889let hasNewValue = 1;
32890let opNewValue = 0;
32891let isCVI = 1;
32892let DecoderNamespace = "EXT_mmvec";
32893}
32894def V6_vdmpy_sf_hf : HInst<
32895(outs HvxVR:$Vd32),
32896(ins HvxVR:$Vu32, HvxVR:$Vv32),
32897"$Vd32.sf = vdmpy($Vu32.hf,$Vv32.hf)",
32898tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32899let Inst{7-5} = 0b110;
32900let Inst{13-13} = 0b1;
32901let Inst{31-21} = 0b00011111101;
32902let hasNewValue = 1;
32903let opNewValue = 0;
32904let isCVI = 1;
32905let DecoderNamespace = "EXT_mmvec";
32906}
32907def V6_vdmpy_sf_hf_acc : HInst<
32908(outs HvxVR:$Vx32),
32909(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
32910"$Vx32.sf += vdmpy($Vu32.hf,$Vv32.hf)",
32911tc_a19b9305, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
32912let Inst{7-5} = 0b011;
32913let Inst{13-13} = 0b1;
32914let Inst{31-21} = 0b00011100010;
32915let hasNewValue = 1;
32916let opNewValue = 0;
32917let isAccumulator = 1;
32918let isCVI = 1;
32919let DecoderNamespace = "EXT_mmvec";
32920let Constraints = "$Vx32 = $Vx32in";
32921}
32922def V6_vdmpybus : HInst<
32923(outs HvxVR:$Vd32),
32924(ins HvxVR:$Vu32, IntRegs:$Rt32),
32925"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
32926tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32927let Inst{7-5} = 0b110;
32928let Inst{13-13} = 0b0;
32929let Inst{31-21} = 0b00011001000;
32930let hasNewValue = 1;
32931let opNewValue = 0;
32932let isCVI = 1;
32933let DecoderNamespace = "EXT_mmvec";
32934}
32935def V6_vdmpybus_acc : HInst<
32936(outs HvxVR:$Vx32),
32937(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32938"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
32939tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32940let Inst{7-5} = 0b110;
32941let Inst{13-13} = 0b1;
32942let Inst{31-21} = 0b00011001000;
32943let hasNewValue = 1;
32944let opNewValue = 0;
32945let isAccumulator = 1;
32946let isCVI = 1;
32947let DecoderNamespace = "EXT_mmvec";
32948let Constraints = "$Vx32 = $Vx32in";
32949}
32950def V6_vdmpybus_acc_alt : HInst<
32951(outs HvxVR:$Vx32),
32952(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32953"$Vx32 += vdmpybus($Vu32,$Rt32)",
32954PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32955let hasNewValue = 1;
32956let opNewValue = 0;
32957let isAccumulator = 1;
32958let isCVI = 1;
32959let isPseudo = 1;
32960let isCodeGenOnly = 1;
32961let DecoderNamespace = "EXT_mmvec";
32962let Constraints = "$Vx32 = $Vx32in";
32963}
32964def V6_vdmpybus_alt : HInst<
32965(outs HvxVR:$Vd32),
32966(ins HvxVR:$Vu32, IntRegs:$Rt32),
32967"$Vd32 = vdmpybus($Vu32,$Rt32)",
32968PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32969let hasNewValue = 1;
32970let opNewValue = 0;
32971let isCVI = 1;
32972let isPseudo = 1;
32973let isCodeGenOnly = 1;
32974let DecoderNamespace = "EXT_mmvec";
32975}
32976def V6_vdmpybus_dv : HInst<
32977(outs HvxWR:$Vdd32),
32978(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32979"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
32980tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32981let Inst{7-5} = 0b111;
32982let Inst{13-13} = 0b0;
32983let Inst{31-21} = 0b00011001000;
32984let hasNewValue = 1;
32985let opNewValue = 0;
32986let isCVI = 1;
32987let DecoderNamespace = "EXT_mmvec";
32988}
32989def V6_vdmpybus_dv_acc : HInst<
32990(outs HvxWR:$Vxx32),
32991(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32992"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
32993tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32994let Inst{7-5} = 0b111;
32995let Inst{13-13} = 0b1;
32996let Inst{31-21} = 0b00011001000;
32997let hasNewValue = 1;
32998let opNewValue = 0;
32999let isAccumulator = 1;
33000let isCVI = 1;
33001let DecoderNamespace = "EXT_mmvec";
33002let Constraints = "$Vxx32 = $Vxx32in";
33003}
33004def V6_vdmpybus_dv_acc_alt : HInst<
33005(outs HvxWR:$Vxx32),
33006(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33007"$Vxx32 += vdmpybus($Vuu32,$Rt32)",
33008PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33009let hasNewValue = 1;
33010let opNewValue = 0;
33011let isAccumulator = 1;
33012let isCVI = 1;
33013let isPseudo = 1;
33014let isCodeGenOnly = 1;
33015let DecoderNamespace = "EXT_mmvec";
33016let Constraints = "$Vxx32 = $Vxx32in";
33017}
33018def V6_vdmpybus_dv_alt : HInst<
33019(outs HvxWR:$Vdd32),
33020(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33021"$Vdd32 = vdmpybus($Vuu32,$Rt32)",
33022PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33023let hasNewValue = 1;
33024let opNewValue = 0;
33025let isCVI = 1;
33026let isPseudo = 1;
33027let isCodeGenOnly = 1;
33028let DecoderNamespace = "EXT_mmvec";
33029}
33030def V6_vdmpyhb : HInst<
33031(outs HvxVR:$Vd32),
33032(ins HvxVR:$Vu32, IntRegs:$Rt32),
33033"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
33034tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33035let Inst{7-5} = 0b010;
33036let Inst{13-13} = 0b0;
33037let Inst{31-21} = 0b00011001000;
33038let hasNewValue = 1;
33039let opNewValue = 0;
33040let isCVI = 1;
33041let DecoderNamespace = "EXT_mmvec";
33042}
33043def V6_vdmpyhb_acc : HInst<
33044(outs HvxVR:$Vx32),
33045(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33046"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
33047tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33048let Inst{7-5} = 0b011;
33049let Inst{13-13} = 0b1;
33050let Inst{31-21} = 0b00011001000;
33051let hasNewValue = 1;
33052let opNewValue = 0;
33053let isAccumulator = 1;
33054let isCVI = 1;
33055let DecoderNamespace = "EXT_mmvec";
33056let Constraints = "$Vx32 = $Vx32in";
33057}
33058def V6_vdmpyhb_acc_alt : HInst<
33059(outs HvxVR:$Vx32),
33060(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33061"$Vx32 += vdmpyhb($Vu32,$Rt32)",
33062PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33063let hasNewValue = 1;
33064let opNewValue = 0;
33065let isAccumulator = 1;
33066let isCVI = 1;
33067let isPseudo = 1;
33068let isCodeGenOnly = 1;
33069let DecoderNamespace = "EXT_mmvec";
33070let Constraints = "$Vx32 = $Vx32in";
33071}
33072def V6_vdmpyhb_alt : HInst<
33073(outs HvxVR:$Vd32),
33074(ins HvxVR:$Vu32, IntRegs:$Rt32),
33075"$Vd32 = vdmpyhb($Vu32,$Rt32)",
33076PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33077let hasNewValue = 1;
33078let opNewValue = 0;
33079let isCVI = 1;
33080let isPseudo = 1;
33081let isCodeGenOnly = 1;
33082let DecoderNamespace = "EXT_mmvec";
33083}
33084def V6_vdmpyhb_dv : HInst<
33085(outs HvxWR:$Vdd32),
33086(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33087"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
33088tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33089let Inst{7-5} = 0b100;
33090let Inst{13-13} = 0b0;
33091let Inst{31-21} = 0b00011001001;
33092let hasNewValue = 1;
33093let opNewValue = 0;
33094let isCVI = 1;
33095let DecoderNamespace = "EXT_mmvec";
33096}
33097def V6_vdmpyhb_dv_acc : HInst<
33098(outs HvxWR:$Vxx32),
33099(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33100"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
33101tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33102let Inst{7-5} = 0b100;
33103let Inst{13-13} = 0b1;
33104let Inst{31-21} = 0b00011001001;
33105let hasNewValue = 1;
33106let opNewValue = 0;
33107let isAccumulator = 1;
33108let isCVI = 1;
33109let DecoderNamespace = "EXT_mmvec";
33110let Constraints = "$Vxx32 = $Vxx32in";
33111}
33112def V6_vdmpyhb_dv_acc_alt : HInst<
33113(outs HvxWR:$Vxx32),
33114(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33115"$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
33116PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33117let hasNewValue = 1;
33118let opNewValue = 0;
33119let isAccumulator = 1;
33120let isCVI = 1;
33121let isPseudo = 1;
33122let isCodeGenOnly = 1;
33123let DecoderNamespace = "EXT_mmvec";
33124let Constraints = "$Vxx32 = $Vxx32in";
33125}
33126def V6_vdmpyhb_dv_alt : HInst<
33127(outs HvxWR:$Vdd32),
33128(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33129"$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
33130PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33131let hasNewValue = 1;
33132let opNewValue = 0;
33133let isCVI = 1;
33134let isPseudo = 1;
33135let isCodeGenOnly = 1;
33136let DecoderNamespace = "EXT_mmvec";
33137}
33138def V6_vdmpyhisat : HInst<
33139(outs HvxVR:$Vd32),
33140(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33141"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
33142tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
33143let Inst{7-5} = 0b011;
33144let Inst{13-13} = 0b0;
33145let Inst{31-21} = 0b00011001001;
33146let hasNewValue = 1;
33147let opNewValue = 0;
33148let isCVI = 1;
33149let DecoderNamespace = "EXT_mmvec";
33150}
33151def V6_vdmpyhisat_acc : HInst<
33152(outs HvxVR:$Vx32),
33153(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33154"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
33155tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
33156let Inst{7-5} = 0b010;
33157let Inst{13-13} = 0b1;
33158let Inst{31-21} = 0b00011001001;
33159let hasNewValue = 1;
33160let opNewValue = 0;
33161let isAccumulator = 1;
33162let isCVI = 1;
33163let DecoderNamespace = "EXT_mmvec";
33164let Constraints = "$Vx32 = $Vx32in";
33165}
33166def V6_vdmpyhisat_acc_alt : HInst<
33167(outs HvxVR:$Vx32),
33168(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33169"$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
33170PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33171let hasNewValue = 1;
33172let opNewValue = 0;
33173let isAccumulator = 1;
33174let isCVI = 1;
33175let isPseudo = 1;
33176let isCodeGenOnly = 1;
33177let DecoderNamespace = "EXT_mmvec";
33178let Constraints = "$Vx32 = $Vx32in";
33179}
33180def V6_vdmpyhisat_alt : HInst<
33181(outs HvxVR:$Vd32),
33182(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33183"$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
33184PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33185let hasNewValue = 1;
33186let opNewValue = 0;
33187let isCVI = 1;
33188let isPseudo = 1;
33189let isCodeGenOnly = 1;
33190let DecoderNamespace = "EXT_mmvec";
33191}
33192def V6_vdmpyhsat : HInst<
33193(outs HvxVR:$Vd32),
33194(ins HvxVR:$Vu32, IntRegs:$Rt32),
33195"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
33196tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33197let Inst{7-5} = 0b010;
33198let Inst{13-13} = 0b0;
33199let Inst{31-21} = 0b00011001001;
33200let hasNewValue = 1;
33201let opNewValue = 0;
33202let isCVI = 1;
33203let DecoderNamespace = "EXT_mmvec";
33204}
33205def V6_vdmpyhsat_acc : HInst<
33206(outs HvxVR:$Vx32),
33207(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33208"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
33209tc_72e2b393, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33210let Inst{7-5} = 0b011;
33211let Inst{13-13} = 0b1;
33212let Inst{31-21} = 0b00011001001;
33213let hasNewValue = 1;
33214let opNewValue = 0;
33215let isAccumulator = 1;
33216let isCVI = 1;
33217let DecoderNamespace = "EXT_mmvec";
33218let Constraints = "$Vx32 = $Vx32in";
33219}
33220def V6_vdmpyhsat_acc_alt : HInst<
33221(outs HvxVR:$Vx32),
33222(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33223"$Vx32 += vdmpyh($Vu32,$Rt32):sat",
33224PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33225let hasNewValue = 1;
33226let opNewValue = 0;
33227let isAccumulator = 1;
33228let isCVI = 1;
33229let isPseudo = 1;
33230let isCodeGenOnly = 1;
33231let DecoderNamespace = "EXT_mmvec";
33232let Constraints = "$Vx32 = $Vx32in";
33233}
33234def V6_vdmpyhsat_alt : HInst<
33235(outs HvxVR:$Vd32),
33236(ins HvxVR:$Vu32, IntRegs:$Rt32),
33237"$Vd32 = vdmpyh($Vu32,$Rt32):sat",
33238PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33239let hasNewValue = 1;
33240let opNewValue = 0;
33241let isCVI = 1;
33242let isPseudo = 1;
33243let isCodeGenOnly = 1;
33244let DecoderNamespace = "EXT_mmvec";
33245}
33246def V6_vdmpyhsuisat : HInst<
33247(outs HvxVR:$Vd32),
33248(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33249"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
33250tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
33251let Inst{7-5} = 0b001;
33252let Inst{13-13} = 0b0;
33253let Inst{31-21} = 0b00011001001;
33254let hasNewValue = 1;
33255let opNewValue = 0;
33256let isCVI = 1;
33257let DecoderNamespace = "EXT_mmvec";
33258}
33259def V6_vdmpyhsuisat_acc : HInst<
33260(outs HvxVR:$Vx32),
33261(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33262"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
33263tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
33264let Inst{7-5} = 0b001;
33265let Inst{13-13} = 0b1;
33266let Inst{31-21} = 0b00011001001;
33267let hasNewValue = 1;
33268let opNewValue = 0;
33269let isAccumulator = 1;
33270let isCVI = 1;
33271let DecoderNamespace = "EXT_mmvec";
33272let Constraints = "$Vx32 = $Vx32in";
33273}
33274def V6_vdmpyhsuisat_acc_alt : HInst<
33275(outs HvxVR:$Vx32),
33276(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33277"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
33278PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33279let hasNewValue = 1;
33280let opNewValue = 0;
33281let isAccumulator = 1;
33282let isCVI = 1;
33283let isPseudo = 1;
33284let isCodeGenOnly = 1;
33285let DecoderNamespace = "EXT_mmvec";
33286let Constraints = "$Vx32 = $Vx32in";
33287}
33288def V6_vdmpyhsuisat_alt : HInst<
33289(outs HvxVR:$Vd32),
33290(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33291"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
33292PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33293let hasNewValue = 1;
33294let opNewValue = 0;
33295let isCVI = 1;
33296let isPseudo = 1;
33297let isCodeGenOnly = 1;
33298let DecoderNamespace = "EXT_mmvec";
33299}
33300def V6_vdmpyhsusat : HInst<
33301(outs HvxVR:$Vd32),
33302(ins HvxVR:$Vu32, IntRegs:$Rt32),
33303"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
33304tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
33305let Inst{7-5} = 0b000;
33306let Inst{13-13} = 0b0;
33307let Inst{31-21} = 0b00011001001;
33308let hasNewValue = 1;
33309let opNewValue = 0;
33310let isCVI = 1;
33311let DecoderNamespace = "EXT_mmvec";
33312}
33313def V6_vdmpyhsusat_acc : HInst<
33314(outs HvxVR:$Vx32),
33315(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33316"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
33317tc_72e2b393, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
33318let Inst{7-5} = 0b000;
33319let Inst{13-13} = 0b1;
33320let Inst{31-21} = 0b00011001001;
33321let hasNewValue = 1;
33322let opNewValue = 0;
33323let isAccumulator = 1;
33324let isCVI = 1;
33325let DecoderNamespace = "EXT_mmvec";
33326let Constraints = "$Vx32 = $Vx32in";
33327}
33328def V6_vdmpyhsusat_acc_alt : HInst<
33329(outs HvxVR:$Vx32),
33330(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
33331"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
33332PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33333let hasNewValue = 1;
33334let opNewValue = 0;
33335let isAccumulator = 1;
33336let isCVI = 1;
33337let isPseudo = 1;
33338let isCodeGenOnly = 1;
33339let DecoderNamespace = "EXT_mmvec";
33340let Constraints = "$Vx32 = $Vx32in";
33341}
33342def V6_vdmpyhsusat_alt : HInst<
33343(outs HvxVR:$Vd32),
33344(ins HvxVR:$Vu32, IntRegs:$Rt32),
33345"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
33346PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33347let hasNewValue = 1;
33348let opNewValue = 0;
33349let isCVI = 1;
33350let isPseudo = 1;
33351let isCodeGenOnly = 1;
33352let DecoderNamespace = "EXT_mmvec";
33353}
33354def V6_vdmpyhvsat : HInst<
33355(outs HvxVR:$Vd32),
33356(ins HvxVR:$Vu32, HvxVR:$Vv32),
33357"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
33358tc_73efe966, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
33359let Inst{7-5} = 0b011;
33360let Inst{13-13} = 0b0;
33361let Inst{31-21} = 0b00011100000;
33362let hasNewValue = 1;
33363let opNewValue = 0;
33364let isCVI = 1;
33365let DecoderNamespace = "EXT_mmvec";
33366}
33367def V6_vdmpyhvsat_acc : HInst<
33368(outs HvxVR:$Vx32),
33369(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33370"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
33371tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
33372let Inst{7-5} = 0b011;
33373let Inst{13-13} = 0b1;
33374let Inst{31-21} = 0b00011100000;
33375let hasNewValue = 1;
33376let opNewValue = 0;
33377let isAccumulator = 1;
33378let isCVI = 1;
33379let DecoderNamespace = "EXT_mmvec";
33380let Constraints = "$Vx32 = $Vx32in";
33381}
33382def V6_vdmpyhvsat_acc_alt : HInst<
33383(outs HvxVR:$Vx32),
33384(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
33385"$Vx32 += vdmpyh($Vu32,$Vv32):sat",
33386PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33387let hasNewValue = 1;
33388let opNewValue = 0;
33389let isAccumulator = 1;
33390let isCVI = 1;
33391let isPseudo = 1;
33392let isCodeGenOnly = 1;
33393let DecoderNamespace = "EXT_mmvec";
33394let Constraints = "$Vx32 = $Vx32in";
33395}
33396def V6_vdmpyhvsat_alt : HInst<
33397(outs HvxVR:$Vd32),
33398(ins HvxVR:$Vu32, HvxVR:$Vv32),
33399"$Vd32 = vdmpyh($Vu32,$Vv32):sat",
33400PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33401let hasNewValue = 1;
33402let opNewValue = 0;
33403let isCVI = 1;
33404let isPseudo = 1;
33405let isCodeGenOnly = 1;
33406let DecoderNamespace = "EXT_mmvec";
33407}
33408def V6_vdsaduh : HInst<
33409(outs HvxWR:$Vdd32),
33410(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33411"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
33412tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33413let Inst{7-5} = 0b101;
33414let Inst{13-13} = 0b0;
33415let Inst{31-21} = 0b00011001000;
33416let hasNewValue = 1;
33417let opNewValue = 0;
33418let isCVI = 1;
33419let DecoderNamespace = "EXT_mmvec";
33420}
33421def V6_vdsaduh_acc : HInst<
33422(outs HvxWR:$Vxx32),
33423(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33424"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
33425tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33426let Inst{7-5} = 0b000;
33427let Inst{13-13} = 0b1;
33428let Inst{31-21} = 0b00011001011;
33429let hasNewValue = 1;
33430let opNewValue = 0;
33431let isAccumulator = 1;
33432let isCVI = 1;
33433let DecoderNamespace = "EXT_mmvec";
33434let Constraints = "$Vxx32 = $Vxx32in";
33435}
33436def V6_vdsaduh_acc_alt : HInst<
33437(outs HvxWR:$Vxx32),
33438(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33439"$Vxx32 += vdsaduh($Vuu32,$Rt32)",
33440PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33441let hasNewValue = 1;
33442let opNewValue = 0;
33443let isAccumulator = 1;
33444let isCVI = 1;
33445let isPseudo = 1;
33446let isCodeGenOnly = 1;
33447let DecoderNamespace = "EXT_mmvec";
33448let Constraints = "$Vxx32 = $Vxx32in";
33449}
33450def V6_vdsaduh_alt : HInst<
33451(outs HvxWR:$Vdd32),
33452(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33453"$Vdd32 = vdsaduh($Vuu32,$Rt32)",
33454PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33455let hasNewValue = 1;
33456let opNewValue = 0;
33457let isCVI = 1;
33458let isPseudo = 1;
33459let isCodeGenOnly = 1;
33460let DecoderNamespace = "EXT_mmvec";
33461}
33462def V6_veqb : HInst<
33463(outs HvxQR:$Qd4),
33464(ins HvxVR:$Vu32, HvxVR:$Vv32),
33465"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
33466tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33467let Inst{7-2} = 0b000000;
33468let Inst{13-13} = 0b0;
33469let Inst{31-21} = 0b00011111100;
33470let hasNewValue = 1;
33471let opNewValue = 0;
33472let isCVI = 1;
33473let isHVXALU = 1;
33474let isHVXALU2SRC = 1;
33475let DecoderNamespace = "EXT_mmvec";
33476}
33477def V6_veqb_and : HInst<
33478(outs HvxQR:$Qx4),
33479(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33480"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
33481tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33482let Inst{7-2} = 0b000000;
33483let Inst{13-13} = 0b1;
33484let Inst{31-21} = 0b00011100100;
33485let isCVI = 1;
33486let isHVXALU = 1;
33487let isHVXALU2SRC = 1;
33488let DecoderNamespace = "EXT_mmvec";
33489let Constraints = "$Qx4 = $Qx4in";
33490}
33491def V6_veqb_or : HInst<
33492(outs HvxQR:$Qx4),
33493(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33494"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
33495tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33496let Inst{7-2} = 0b010000;
33497let Inst{13-13} = 0b1;
33498let Inst{31-21} = 0b00011100100;
33499let isAccumulator = 1;
33500let isCVI = 1;
33501let isHVXALU = 1;
33502let isHVXALU2SRC = 1;
33503let DecoderNamespace = "EXT_mmvec";
33504let Constraints = "$Qx4 = $Qx4in";
33505}
33506def V6_veqb_xor : HInst<
33507(outs HvxQR:$Qx4),
33508(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33509"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
33510tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33511let Inst{7-2} = 0b100000;
33512let Inst{13-13} = 0b1;
33513let Inst{31-21} = 0b00011100100;
33514let isCVI = 1;
33515let isHVXALU = 1;
33516let isHVXALU2SRC = 1;
33517let DecoderNamespace = "EXT_mmvec";
33518let Constraints = "$Qx4 = $Qx4in";
33519}
33520def V6_veqh : HInst<
33521(outs HvxQR:$Qd4),
33522(ins HvxVR:$Vu32, HvxVR:$Vv32),
33523"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
33524tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33525let Inst{7-2} = 0b000001;
33526let Inst{13-13} = 0b0;
33527let Inst{31-21} = 0b00011111100;
33528let hasNewValue = 1;
33529let opNewValue = 0;
33530let isCVI = 1;
33531let isHVXALU = 1;
33532let isHVXALU2SRC = 1;
33533let DecoderNamespace = "EXT_mmvec";
33534}
33535def V6_veqh_and : HInst<
33536(outs HvxQR:$Qx4),
33537(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33538"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
33539tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33540let Inst{7-2} = 0b000001;
33541let Inst{13-13} = 0b1;
33542let Inst{31-21} = 0b00011100100;
33543let isCVI = 1;
33544let isHVXALU = 1;
33545let isHVXALU2SRC = 1;
33546let DecoderNamespace = "EXT_mmvec";
33547let Constraints = "$Qx4 = $Qx4in";
33548}
33549def V6_veqh_or : HInst<
33550(outs HvxQR:$Qx4),
33551(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33552"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
33553tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33554let Inst{7-2} = 0b010001;
33555let Inst{13-13} = 0b1;
33556let Inst{31-21} = 0b00011100100;
33557let isAccumulator = 1;
33558let isCVI = 1;
33559let isHVXALU = 1;
33560let isHVXALU2SRC = 1;
33561let DecoderNamespace = "EXT_mmvec";
33562let Constraints = "$Qx4 = $Qx4in";
33563}
33564def V6_veqh_xor : HInst<
33565(outs HvxQR:$Qx4),
33566(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33567"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
33568tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33569let Inst{7-2} = 0b100001;
33570let Inst{13-13} = 0b1;
33571let Inst{31-21} = 0b00011100100;
33572let isCVI = 1;
33573let isHVXALU = 1;
33574let isHVXALU2SRC = 1;
33575let DecoderNamespace = "EXT_mmvec";
33576let Constraints = "$Qx4 = $Qx4in";
33577}
33578def V6_veqw : HInst<
33579(outs HvxQR:$Qd4),
33580(ins HvxVR:$Vu32, HvxVR:$Vv32),
33581"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
33582tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33583let Inst{7-2} = 0b000010;
33584let Inst{13-13} = 0b0;
33585let Inst{31-21} = 0b00011111100;
33586let hasNewValue = 1;
33587let opNewValue = 0;
33588let isCVI = 1;
33589let isHVXALU = 1;
33590let isHVXALU2SRC = 1;
33591let DecoderNamespace = "EXT_mmvec";
33592}
33593def V6_veqw_and : HInst<
33594(outs HvxQR:$Qx4),
33595(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33596"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
33597tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33598let Inst{7-2} = 0b000010;
33599let Inst{13-13} = 0b1;
33600let Inst{31-21} = 0b00011100100;
33601let isCVI = 1;
33602let isHVXALU = 1;
33603let isHVXALU2SRC = 1;
33604let DecoderNamespace = "EXT_mmvec";
33605let Constraints = "$Qx4 = $Qx4in";
33606}
33607def V6_veqw_or : HInst<
33608(outs HvxQR:$Qx4),
33609(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33610"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
33611tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33612let Inst{7-2} = 0b010010;
33613let Inst{13-13} = 0b1;
33614let Inst{31-21} = 0b00011100100;
33615let isAccumulator = 1;
33616let isCVI = 1;
33617let isHVXALU = 1;
33618let isHVXALU2SRC = 1;
33619let DecoderNamespace = "EXT_mmvec";
33620let Constraints = "$Qx4 = $Qx4in";
33621}
33622def V6_veqw_xor : HInst<
33623(outs HvxQR:$Qx4),
33624(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33625"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
33626tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33627let Inst{7-2} = 0b100010;
33628let Inst{13-13} = 0b1;
33629let Inst{31-21} = 0b00011100100;
33630let isCVI = 1;
33631let isHVXALU = 1;
33632let isHVXALU2SRC = 1;
33633let DecoderNamespace = "EXT_mmvec";
33634let Constraints = "$Qx4 = $Qx4in";
33635}
33636def V6_vfmax_hf : HInst<
33637(outs HvxVR:$Vd32),
33638(ins HvxVR:$Vu32, HvxVR:$Vv32),
33639"$Vd32.hf = vfmax($Vu32.hf,$Vv32.hf)",
33640tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33641let Inst{7-5} = 0b010;
33642let Inst{13-13} = 0b1;
33643let Inst{31-21} = 0b00011100011;
33644let hasNewValue = 1;
33645let opNewValue = 0;
33646let isCVI = 1;
33647let DecoderNamespace = "EXT_mmvec";
33648}
33649def V6_vfmax_sf : HInst<
33650(outs HvxVR:$Vd32),
33651(ins HvxVR:$Vu32, HvxVR:$Vv32),
33652"$Vd32.sf = vfmax($Vu32.sf,$Vv32.sf)",
33653tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33654let Inst{7-5} = 0b011;
33655let Inst{13-13} = 0b1;
33656let Inst{31-21} = 0b00011100011;
33657let hasNewValue = 1;
33658let opNewValue = 0;
33659let isCVI = 1;
33660let DecoderNamespace = "EXT_mmvec";
33661}
33662def V6_vfmin_hf : HInst<
33663(outs HvxVR:$Vd32),
33664(ins HvxVR:$Vu32, HvxVR:$Vv32),
33665"$Vd32.hf = vfmin($Vu32.hf,$Vv32.hf)",
33666tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33667let Inst{7-5} = 0b000;
33668let Inst{13-13} = 0b1;
33669let Inst{31-21} = 0b00011100011;
33670let hasNewValue = 1;
33671let opNewValue = 0;
33672let isCVI = 1;
33673let DecoderNamespace = "EXT_mmvec";
33674}
33675def V6_vfmin_sf : HInst<
33676(outs HvxVR:$Vd32),
33677(ins HvxVR:$Vu32, HvxVR:$Vv32),
33678"$Vd32.sf = vfmin($Vu32.sf,$Vv32.sf)",
33679tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33680let Inst{7-5} = 0b001;
33681let Inst{13-13} = 0b1;
33682let Inst{31-21} = 0b00011100011;
33683let hasNewValue = 1;
33684let opNewValue = 0;
33685let isCVI = 1;
33686let DecoderNamespace = "EXT_mmvec";
33687}
33688def V6_vfneg_hf : HInst<
33689(outs HvxVR:$Vd32),
33690(ins HvxVR:$Vu32),
33691"$Vd32.hf = vfneg($Vu32.hf)",
33692tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33693let Inst{7-5} = 0b010;
33694let Inst{13-13} = 0b1;
33695let Inst{31-16} = 0b0001111000000110;
33696let hasNewValue = 1;
33697let opNewValue = 0;
33698let isCVI = 1;
33699let DecoderNamespace = "EXT_mmvec";
33700}
33701def V6_vfneg_sf : HInst<
33702(outs HvxVR:$Vd32),
33703(ins HvxVR:$Vu32),
33704"$Vd32.sf = vfneg($Vu32.sf)",
33705tc_5cdf8c84, TypeCVI_VX_LATE>, Enc_e7581c, Requires<[UseHVXV68,UseHVXIEEEFP]> {
33706let Inst{7-5} = 0b011;
33707let Inst{13-13} = 0b1;
33708let Inst{31-16} = 0b0001111000000110;
33709let hasNewValue = 1;
33710let opNewValue = 0;
33711let isCVI = 1;
33712let DecoderNamespace = "EXT_mmvec";
33713}
33714def V6_vgathermh : HInst<
33715(outs),
33716(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33717"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33718tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
33719let Inst{12-5} = 0b00001000;
33720let Inst{31-21} = 0b00101111000;
33721let hasNewValue = 1;
33722let opNewValue = 0;
33723let accessSize = HalfWordAccess;
33724let isCVLoad = 1;
33725let isCVI = 1;
33726let isHVXALU = 1;
33727let mayLoad = 1;
33728let Defs = [VTMP];
33729let DecoderNamespace = "EXT_mmvec";
33730}
33731def V6_vgathermhq : HInst<
33732(outs),
33733(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33734"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
33735tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
33736let Inst{12-7} = 0b001010;
33737let Inst{31-21} = 0b00101111000;
33738let hasNewValue = 1;
33739let opNewValue = 0;
33740let accessSize = HalfWordAccess;
33741let isCVLoad = 1;
33742let isCVI = 1;
33743let isHVXALU = 1;
33744let mayLoad = 1;
33745let Defs = [VTMP];
33746let DecoderNamespace = "EXT_mmvec";
33747}
33748def V6_vgathermhw : HInst<
33749(outs),
33750(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
33751"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33752tc_7095ecba, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> {
33753let Inst{12-5} = 0b00010000;
33754let Inst{31-21} = 0b00101111000;
33755let hasNewValue = 1;
33756let opNewValue = 0;
33757let accessSize = HalfWordAccess;
33758let isCVLoad = 1;
33759let isCVI = 1;
33760let mayLoad = 1;
33761let Defs = [VTMP];
33762let DecoderNamespace = "EXT_mmvec";
33763}
33764def V6_vgathermhwq : HInst<
33765(outs),
33766(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
33767"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
33768tc_a69eeee1, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> {
33769let Inst{12-7} = 0b001100;
33770let Inst{31-21} = 0b00101111000;
33771let hasNewValue = 1;
33772let opNewValue = 0;
33773let accessSize = HalfWordAccess;
33774let isCVLoad = 1;
33775let isCVI = 1;
33776let mayLoad = 1;
33777let Defs = [VTMP];
33778let DecoderNamespace = "EXT_mmvec";
33779}
33780def V6_vgathermw : HInst<
33781(outs),
33782(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33783"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
33784tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
33785let Inst{12-5} = 0b00000000;
33786let Inst{31-21} = 0b00101111000;
33787let hasNewValue = 1;
33788let opNewValue = 0;
33789let accessSize = WordAccess;
33790let isCVLoad = 1;
33791let isCVI = 1;
33792let isHVXALU = 1;
33793let mayLoad = 1;
33794let Defs = [VTMP];
33795let DecoderNamespace = "EXT_mmvec";
33796}
33797def V6_vgathermwq : HInst<
33798(outs),
33799(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
33800"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
33801tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
33802let Inst{12-7} = 0b001000;
33803let Inst{31-21} = 0b00101111000;
33804let hasNewValue = 1;
33805let opNewValue = 0;
33806let accessSize = WordAccess;
33807let isCVLoad = 1;
33808let isCVI = 1;
33809let isHVXALU = 1;
33810let mayLoad = 1;
33811let Defs = [VTMP];
33812let DecoderNamespace = "EXT_mmvec";
33813}
33814def V6_vgtb : HInst<
33815(outs HvxQR:$Qd4),
33816(ins HvxVR:$Vu32, HvxVR:$Vv32),
33817"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
33818tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33819let Inst{7-2} = 0b000100;
33820let Inst{13-13} = 0b0;
33821let Inst{31-21} = 0b00011111100;
33822let hasNewValue = 1;
33823let opNewValue = 0;
33824let isCVI = 1;
33825let isHVXALU = 1;
33826let isHVXALU2SRC = 1;
33827let DecoderNamespace = "EXT_mmvec";
33828}
33829def V6_vgtb_and : HInst<
33830(outs HvxQR:$Qx4),
33831(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33832"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
33833tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33834let Inst{7-2} = 0b000100;
33835let Inst{13-13} = 0b1;
33836let Inst{31-21} = 0b00011100100;
33837let isCVI = 1;
33838let isHVXALU = 1;
33839let isHVXALU2SRC = 1;
33840let DecoderNamespace = "EXT_mmvec";
33841let Constraints = "$Qx4 = $Qx4in";
33842}
33843def V6_vgtb_or : HInst<
33844(outs HvxQR:$Qx4),
33845(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33846"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
33847tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33848let Inst{7-2} = 0b010100;
33849let Inst{13-13} = 0b1;
33850let Inst{31-21} = 0b00011100100;
33851let isAccumulator = 1;
33852let isCVI = 1;
33853let isHVXALU = 1;
33854let isHVXALU2SRC = 1;
33855let DecoderNamespace = "EXT_mmvec";
33856let Constraints = "$Qx4 = $Qx4in";
33857}
33858def V6_vgtb_xor : HInst<
33859(outs HvxQR:$Qx4),
33860(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33861"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
33862tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33863let Inst{7-2} = 0b100100;
33864let Inst{13-13} = 0b1;
33865let Inst{31-21} = 0b00011100100;
33866let isCVI = 1;
33867let isHVXALU = 1;
33868let isHVXALU2SRC = 1;
33869let DecoderNamespace = "EXT_mmvec";
33870let Constraints = "$Qx4 = $Qx4in";
33871}
33872def V6_vgtbf : HInst<
33873(outs HvxQR:$Qd4),
33874(ins HvxVR:$Vu32, HvxVR:$Vv32),
33875"$Qd4 = vcmp.gt($Vu32.bf,$Vv32.bf)",
33876tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV73,UseHVXQFloat]> {
33877let Inst{7-2} = 0b011110;
33878let Inst{13-13} = 0b1;
33879let Inst{31-21} = 0b00011100100;
33880let hasNewValue = 1;
33881let opNewValue = 0;
33882let isCVI = 1;
33883let isHVXALU = 1;
33884let isHVXALU2SRC = 1;
33885let DecoderNamespace = "EXT_mmvec";
33886}
33887def V6_vgtbf_and : HInst<
33888(outs HvxQR:$Qx4),
33889(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33890"$Qx4 &= vcmp.gt($Vu32.bf,$Vv32.bf)",
33891tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV73,UseHVXQFloat]> {
33892let Inst{7-2} = 0b110100;
33893let Inst{13-13} = 0b1;
33894let Inst{31-21} = 0b00011100100;
33895let isCVI = 1;
33896let isHVXALU = 1;
33897let isHVXALU2SRC = 1;
33898let DecoderNamespace = "EXT_mmvec";
33899let Constraints = "$Qx4 = $Qx4in";
33900}
33901def V6_vgtbf_or : HInst<
33902(outs HvxQR:$Qx4),
33903(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33904"$Qx4 |= vcmp.gt($Vu32.bf,$Vv32.bf)",
33905tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV73,UseHVXQFloat]> {
33906let Inst{7-2} = 0b001110;
33907let Inst{13-13} = 0b1;
33908let Inst{31-21} = 0b00011100100;
33909let isAccumulator = 1;
33910let isCVI = 1;
33911let isHVXALU = 1;
33912let isHVXALU2SRC = 1;
33913let DecoderNamespace = "EXT_mmvec";
33914let Constraints = "$Qx4 = $Qx4in";
33915}
33916def V6_vgtbf_xor : HInst<
33917(outs HvxQR:$Qx4),
33918(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33919"$Qx4 ^= vcmp.gt($Vu32.bf,$Vv32.bf)",
33920tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV73,UseHVXQFloat]> {
33921let Inst{7-2} = 0b111100;
33922let Inst{13-13} = 0b1;
33923let Inst{31-21} = 0b00011100100;
33924let isCVI = 1;
33925let isHVXALU = 1;
33926let isHVXALU2SRC = 1;
33927let DecoderNamespace = "EXT_mmvec";
33928let Constraints = "$Qx4 = $Qx4in";
33929}
33930def V6_vgth : HInst<
33931(outs HvxQR:$Qd4),
33932(ins HvxVR:$Vu32, HvxVR:$Vv32),
33933"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
33934tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33935let Inst{7-2} = 0b000101;
33936let Inst{13-13} = 0b0;
33937let Inst{31-21} = 0b00011111100;
33938let hasNewValue = 1;
33939let opNewValue = 0;
33940let isCVI = 1;
33941let isHVXALU = 1;
33942let isHVXALU2SRC = 1;
33943let DecoderNamespace = "EXT_mmvec";
33944}
33945def V6_vgth_and : HInst<
33946(outs HvxQR:$Qx4),
33947(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33948"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
33949tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33950let Inst{7-2} = 0b000101;
33951let Inst{13-13} = 0b1;
33952let Inst{31-21} = 0b00011100100;
33953let isCVI = 1;
33954let isHVXALU = 1;
33955let isHVXALU2SRC = 1;
33956let DecoderNamespace = "EXT_mmvec";
33957let Constraints = "$Qx4 = $Qx4in";
33958}
33959def V6_vgth_or : HInst<
33960(outs HvxQR:$Qx4),
33961(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33962"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
33963tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33964let Inst{7-2} = 0b010101;
33965let Inst{13-13} = 0b1;
33966let Inst{31-21} = 0b00011100100;
33967let isAccumulator = 1;
33968let isCVI = 1;
33969let isHVXALU = 1;
33970let isHVXALU2SRC = 1;
33971let DecoderNamespace = "EXT_mmvec";
33972let Constraints = "$Qx4 = $Qx4in";
33973}
33974def V6_vgth_xor : HInst<
33975(outs HvxQR:$Qx4),
33976(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33977"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
33978tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33979let Inst{7-2} = 0b100101;
33980let Inst{13-13} = 0b1;
33981let Inst{31-21} = 0b00011100100;
33982let isCVI = 1;
33983let isHVXALU = 1;
33984let isHVXALU2SRC = 1;
33985let DecoderNamespace = "EXT_mmvec";
33986let Constraints = "$Qx4 = $Qx4in";
33987}
33988def V6_vgthf : HInst<
33989(outs HvxQR:$Qd4),
33990(ins HvxVR:$Vu32, HvxVR:$Vv32),
33991"$Qd4 = vcmp.gt($Vu32.hf,$Vv32.hf)",
33992tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
33993let Inst{7-2} = 0b011101;
33994let Inst{13-13} = 0b1;
33995let Inst{31-21} = 0b00011100100;
33996let hasNewValue = 1;
33997let opNewValue = 0;
33998let isCVI = 1;
33999let isHVXALU = 1;
34000let isHVXALU2SRC = 1;
34001let DecoderNamespace = "EXT_mmvec";
34002}
34003def V6_vgthf_and : HInst<
34004(outs HvxQR:$Qx4),
34005(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34006"$Qx4 &= vcmp.gt($Vu32.hf,$Vv32.hf)",
34007tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34008let Inst{7-2} = 0b110011;
34009let Inst{13-13} = 0b1;
34010let Inst{31-21} = 0b00011100100;
34011let isCVI = 1;
34012let isHVXALU = 1;
34013let isHVXALU2SRC = 1;
34014let DecoderNamespace = "EXT_mmvec";
34015let Constraints = "$Qx4 = $Qx4in";
34016}
34017def V6_vgthf_or : HInst<
34018(outs HvxQR:$Qx4),
34019(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34020"$Qx4 |= vcmp.gt($Vu32.hf,$Vv32.hf)",
34021tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34022let Inst{7-2} = 0b001101;
34023let Inst{13-13} = 0b1;
34024let Inst{31-21} = 0b00011100100;
34025let isAccumulator = 1;
34026let isCVI = 1;
34027let isHVXALU = 1;
34028let isHVXALU2SRC = 1;
34029let DecoderNamespace = "EXT_mmvec";
34030let Constraints = "$Qx4 = $Qx4in";
34031}
34032def V6_vgthf_xor : HInst<
34033(outs HvxQR:$Qx4),
34034(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34035"$Qx4 ^= vcmp.gt($Vu32.hf,$Vv32.hf)",
34036tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34037let Inst{7-2} = 0b111011;
34038let Inst{13-13} = 0b1;
34039let Inst{31-21} = 0b00011100100;
34040let isCVI = 1;
34041let isHVXALU = 1;
34042let isHVXALU2SRC = 1;
34043let DecoderNamespace = "EXT_mmvec";
34044let Constraints = "$Qx4 = $Qx4in";
34045}
34046def V6_vgtsf : HInst<
34047(outs HvxQR:$Qd4),
34048(ins HvxVR:$Vu32, HvxVR:$Vv32),
34049"$Qd4 = vcmp.gt($Vu32.sf,$Vv32.sf)",
34050tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34051let Inst{7-2} = 0b011100;
34052let Inst{13-13} = 0b1;
34053let Inst{31-21} = 0b00011100100;
34054let hasNewValue = 1;
34055let opNewValue = 0;
34056let isCVI = 1;
34057let isHVXALU = 1;
34058let isHVXALU2SRC = 1;
34059let DecoderNamespace = "EXT_mmvec";
34060}
34061def V6_vgtsf_and : HInst<
34062(outs HvxQR:$Qx4),
34063(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34064"$Qx4 &= vcmp.gt($Vu32.sf,$Vv32.sf)",
34065tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34066let Inst{7-2} = 0b110010;
34067let Inst{13-13} = 0b1;
34068let Inst{31-21} = 0b00011100100;
34069let isCVI = 1;
34070let isHVXALU = 1;
34071let isHVXALU2SRC = 1;
34072let DecoderNamespace = "EXT_mmvec";
34073let Constraints = "$Qx4 = $Qx4in";
34074}
34075def V6_vgtsf_or : HInst<
34076(outs HvxQR:$Qx4),
34077(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34078"$Qx4 |= vcmp.gt($Vu32.sf,$Vv32.sf)",
34079tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34080let Inst{7-2} = 0b001100;
34081let Inst{13-13} = 0b1;
34082let Inst{31-21} = 0b00011100100;
34083let isAccumulator = 1;
34084let isCVI = 1;
34085let isHVXALU = 1;
34086let isHVXALU2SRC = 1;
34087let DecoderNamespace = "EXT_mmvec";
34088let Constraints = "$Qx4 = $Qx4in";
34089}
34090def V6_vgtsf_xor : HInst<
34091(outs HvxQR:$Qx4),
34092(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34093"$Qx4 ^= vcmp.gt($Vu32.sf,$Vv32.sf)",
34094tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV68,UseHVXFloatingPoint]> {
34095let Inst{7-2} = 0b111010;
34096let Inst{13-13} = 0b1;
34097let Inst{31-21} = 0b00011100100;
34098let isCVI = 1;
34099let isHVXALU = 1;
34100let isHVXALU2SRC = 1;
34101let DecoderNamespace = "EXT_mmvec";
34102let Constraints = "$Qx4 = $Qx4in";
34103}
34104def V6_vgtub : HInst<
34105(outs HvxQR:$Qd4),
34106(ins HvxVR:$Vu32, HvxVR:$Vv32),
34107"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
34108tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34109let Inst{7-2} = 0b001000;
34110let Inst{13-13} = 0b0;
34111let Inst{31-21} = 0b00011111100;
34112let hasNewValue = 1;
34113let opNewValue = 0;
34114let isCVI = 1;
34115let isHVXALU = 1;
34116let isHVXALU2SRC = 1;
34117let DecoderNamespace = "EXT_mmvec";
34118}
34119def V6_vgtub_and : HInst<
34120(outs HvxQR:$Qx4),
34121(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34122"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
34123tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34124let Inst{7-2} = 0b001000;
34125let Inst{13-13} = 0b1;
34126let Inst{31-21} = 0b00011100100;
34127let isCVI = 1;
34128let isHVXALU = 1;
34129let isHVXALU2SRC = 1;
34130let DecoderNamespace = "EXT_mmvec";
34131let Constraints = "$Qx4 = $Qx4in";
34132}
34133def V6_vgtub_or : HInst<
34134(outs HvxQR:$Qx4),
34135(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34136"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
34137tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34138let Inst{7-2} = 0b011000;
34139let Inst{13-13} = 0b1;
34140let Inst{31-21} = 0b00011100100;
34141let isAccumulator = 1;
34142let isCVI = 1;
34143let isHVXALU = 1;
34144let isHVXALU2SRC = 1;
34145let DecoderNamespace = "EXT_mmvec";
34146let Constraints = "$Qx4 = $Qx4in";
34147}
34148def V6_vgtub_xor : HInst<
34149(outs HvxQR:$Qx4),
34150(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34151"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
34152tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34153let Inst{7-2} = 0b101000;
34154let Inst{13-13} = 0b1;
34155let Inst{31-21} = 0b00011100100;
34156let isCVI = 1;
34157let isHVXALU = 1;
34158let isHVXALU2SRC = 1;
34159let DecoderNamespace = "EXT_mmvec";
34160let Constraints = "$Qx4 = $Qx4in";
34161}
34162def V6_vgtuh : HInst<
34163(outs HvxQR:$Qd4),
34164(ins HvxVR:$Vu32, HvxVR:$Vv32),
34165"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
34166tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34167let Inst{7-2} = 0b001001;
34168let Inst{13-13} = 0b0;
34169let Inst{31-21} = 0b00011111100;
34170let hasNewValue = 1;
34171let opNewValue = 0;
34172let isCVI = 1;
34173let isHVXALU = 1;
34174let isHVXALU2SRC = 1;
34175let DecoderNamespace = "EXT_mmvec";
34176}
34177def V6_vgtuh_and : HInst<
34178(outs HvxQR:$Qx4),
34179(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34180"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
34181tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34182let Inst{7-2} = 0b001001;
34183let Inst{13-13} = 0b1;
34184let Inst{31-21} = 0b00011100100;
34185let isCVI = 1;
34186let isHVXALU = 1;
34187let isHVXALU2SRC = 1;
34188let DecoderNamespace = "EXT_mmvec";
34189let Constraints = "$Qx4 = $Qx4in";
34190}
34191def V6_vgtuh_or : HInst<
34192(outs HvxQR:$Qx4),
34193(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34194"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
34195tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34196let Inst{7-2} = 0b011001;
34197let Inst{13-13} = 0b1;
34198let Inst{31-21} = 0b00011100100;
34199let isAccumulator = 1;
34200let isCVI = 1;
34201let isHVXALU = 1;
34202let isHVXALU2SRC = 1;
34203let DecoderNamespace = "EXT_mmvec";
34204let Constraints = "$Qx4 = $Qx4in";
34205}
34206def V6_vgtuh_xor : HInst<
34207(outs HvxQR:$Qx4),
34208(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34209"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
34210tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34211let Inst{7-2} = 0b101001;
34212let Inst{13-13} = 0b1;
34213let Inst{31-21} = 0b00011100100;
34214let isCVI = 1;
34215let isHVXALU = 1;
34216let isHVXALU2SRC = 1;
34217let DecoderNamespace = "EXT_mmvec";
34218let Constraints = "$Qx4 = $Qx4in";
34219}
34220def V6_vgtuw : HInst<
34221(outs HvxQR:$Qd4),
34222(ins HvxVR:$Vu32, HvxVR:$Vv32),
34223"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
34224tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34225let Inst{7-2} = 0b001010;
34226let Inst{13-13} = 0b0;
34227let Inst{31-21} = 0b00011111100;
34228let hasNewValue = 1;
34229let opNewValue = 0;
34230let isCVI = 1;
34231let isHVXALU = 1;
34232let isHVXALU2SRC = 1;
34233let DecoderNamespace = "EXT_mmvec";
34234}
34235def V6_vgtuw_and : HInst<
34236(outs HvxQR:$Qx4),
34237(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34238"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
34239tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34240let Inst{7-2} = 0b001010;
34241let Inst{13-13} = 0b1;
34242let Inst{31-21} = 0b00011100100;
34243let isCVI = 1;
34244let isHVXALU = 1;
34245let isHVXALU2SRC = 1;
34246let DecoderNamespace = "EXT_mmvec";
34247let Constraints = "$Qx4 = $Qx4in";
34248}
34249def V6_vgtuw_or : HInst<
34250(outs HvxQR:$Qx4),
34251(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34252"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
34253tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34254let Inst{7-2} = 0b011010;
34255let Inst{13-13} = 0b1;
34256let Inst{31-21} = 0b00011100100;
34257let isAccumulator = 1;
34258let isCVI = 1;
34259let isHVXALU = 1;
34260let isHVXALU2SRC = 1;
34261let DecoderNamespace = "EXT_mmvec";
34262let Constraints = "$Qx4 = $Qx4in";
34263}
34264def V6_vgtuw_xor : HInst<
34265(outs HvxQR:$Qx4),
34266(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34267"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
34268tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34269let Inst{7-2} = 0b101010;
34270let Inst{13-13} = 0b1;
34271let Inst{31-21} = 0b00011100100;
34272let isCVI = 1;
34273let isHVXALU = 1;
34274let isHVXALU2SRC = 1;
34275let DecoderNamespace = "EXT_mmvec";
34276let Constraints = "$Qx4 = $Qx4in";
34277}
34278def V6_vgtw : HInst<
34279(outs HvxQR:$Qd4),
34280(ins HvxVR:$Vu32, HvxVR:$Vv32),
34281"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
34282tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
34283let Inst{7-2} = 0b000110;
34284let Inst{13-13} = 0b0;
34285let Inst{31-21} = 0b00011111100;
34286let hasNewValue = 1;
34287let opNewValue = 0;
34288let isCVI = 1;
34289let isHVXALU = 1;
34290let isHVXALU2SRC = 1;
34291let DecoderNamespace = "EXT_mmvec";
34292}
34293def V6_vgtw_and : HInst<
34294(outs HvxQR:$Qx4),
34295(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34296"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
34297tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34298let Inst{7-2} = 0b000110;
34299let Inst{13-13} = 0b1;
34300let Inst{31-21} = 0b00011100100;
34301let isCVI = 1;
34302let isHVXALU = 1;
34303let isHVXALU2SRC = 1;
34304let DecoderNamespace = "EXT_mmvec";
34305let Constraints = "$Qx4 = $Qx4in";
34306}
34307def V6_vgtw_or : HInst<
34308(outs HvxQR:$Qx4),
34309(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34310"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
34311tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34312let Inst{7-2} = 0b010110;
34313let Inst{13-13} = 0b1;
34314let Inst{31-21} = 0b00011100100;
34315let isAccumulator = 1;
34316let isCVI = 1;
34317let isHVXALU = 1;
34318let isHVXALU2SRC = 1;
34319let DecoderNamespace = "EXT_mmvec";
34320let Constraints = "$Qx4 = $Qx4in";
34321}
34322def V6_vgtw_xor : HInst<
34323(outs HvxQR:$Qx4),
34324(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
34325"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
34326tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
34327let Inst{7-2} = 0b100110;
34328let Inst{13-13} = 0b1;
34329let Inst{31-21} = 0b00011100100;
34330let isCVI = 1;
34331let isHVXALU = 1;
34332let isHVXALU2SRC = 1;
34333let DecoderNamespace = "EXT_mmvec";
34334let Constraints = "$Qx4 = $Qx4in";
34335}
34336def V6_vhist : HInst<
34337(outs),
34338(ins),
34339"vhist",
34340tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
34341let Inst{13-0} = 0b10000010000000;
34342let Inst{31-16} = 0b0001111000000000;
34343let isCVI = 1;
34344let DecoderNamespace = "EXT_mmvec";
34345}
34346def V6_vhistq : HInst<
34347(outs),
34348(ins HvxQR:$Qv4),
34349"vhist($Qv4)",
34350tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
34351let Inst{13-0} = 0b10000010000000;
34352let Inst{21-16} = 0b000010;
34353let Inst{31-24} = 0b00011110;
34354let isCVI = 1;
34355let DecoderNamespace = "EXT_mmvec";
34356}
34357def V6_vinsertwr : HInst<
34358(outs HvxVR:$Vx32),
34359(ins HvxVR:$Vx32in, IntRegs:$Rt32),
34360"$Vx32.w = vinsert($Rt32)",
34361tc_ac4046bc, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
34362let Inst{13-5} = 0b100000001;
34363let Inst{31-21} = 0b00011001101;
34364let hasNewValue = 1;
34365let opNewValue = 0;
34366let isCVI = 1;
34367let DecoderNamespace = "EXT_mmvec";
34368let Constraints = "$Vx32 = $Vx32in";
34369}
34370def V6_vlalignb : HInst<
34371(outs HvxVR:$Vd32),
34372(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34373"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
34374tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
34375let Inst{7-5} = 0b001;
34376let Inst{13-13} = 0b0;
34377let Inst{31-24} = 0b00011011;
34378let hasNewValue = 1;
34379let opNewValue = 0;
34380let isCVI = 1;
34381let DecoderNamespace = "EXT_mmvec";
34382}
34383def V6_vlalignbi : HInst<
34384(outs HvxVR:$Vd32),
34385(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34386"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
34387tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
34388let Inst{13-13} = 0b1;
34389let Inst{31-21} = 0b00011110011;
34390let hasNewValue = 1;
34391let opNewValue = 0;
34392let isCVI = 1;
34393let DecoderNamespace = "EXT_mmvec";
34394}
34395def V6_vlsrb : HInst<
34396(outs HvxVR:$Vd32),
34397(ins HvxVR:$Vu32, IntRegs:$Rt32),
34398"$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
34399tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
34400let Inst{7-5} = 0b011;
34401let Inst{13-13} = 0b0;
34402let Inst{31-21} = 0b00011001100;
34403let hasNewValue = 1;
34404let opNewValue = 0;
34405let isCVI = 1;
34406let DecoderNamespace = "EXT_mmvec";
34407}
34408def V6_vlsrh : HInst<
34409(outs HvxVR:$Vd32),
34410(ins HvxVR:$Vu32, IntRegs:$Rt32),
34411"$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
34412tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
34413let Inst{7-5} = 0b010;
34414let Inst{13-13} = 0b0;
34415let Inst{31-21} = 0b00011001100;
34416let hasNewValue = 1;
34417let opNewValue = 0;
34418let isCVI = 1;
34419let DecoderNamespace = "EXT_mmvec";
34420}
34421def V6_vlsrh_alt : HInst<
34422(outs HvxVR:$Vd32),
34423(ins HvxVR:$Vu32, IntRegs:$Rt32),
34424"$Vd32 = vlsrh($Vu32,$Rt32)",
34425PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34426let hasNewValue = 1;
34427let opNewValue = 0;
34428let isCVI = 1;
34429let isPseudo = 1;
34430let isCodeGenOnly = 1;
34431let DecoderNamespace = "EXT_mmvec";
34432}
34433def V6_vlsrhv : HInst<
34434(outs HvxVR:$Vd32),
34435(ins HvxVR:$Vu32, HvxVR:$Vv32),
34436"$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
34437tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
34438let Inst{7-5} = 0b010;
34439let Inst{13-13} = 0b0;
34440let Inst{31-21} = 0b00011111101;
34441let hasNewValue = 1;
34442let opNewValue = 0;
34443let isCVI = 1;
34444let DecoderNamespace = "EXT_mmvec";
34445}
34446def V6_vlsrhv_alt : HInst<
34447(outs HvxVR:$Vd32),
34448(ins HvxVR:$Vu32, HvxVR:$Vv32),
34449"$Vd32 = vlsrh($Vu32,$Vv32)",
34450PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34451let hasNewValue = 1;
34452let opNewValue = 0;
34453let isCVI = 1;
34454let isPseudo = 1;
34455let isCodeGenOnly = 1;
34456let DecoderNamespace = "EXT_mmvec";
34457}
34458def V6_vlsrw : HInst<
34459(outs HvxVR:$Vd32),
34460(ins HvxVR:$Vu32, IntRegs:$Rt32),
34461"$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
34462tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
34463let Inst{7-5} = 0b001;
34464let Inst{13-13} = 0b0;
34465let Inst{31-21} = 0b00011001100;
34466let hasNewValue = 1;
34467let opNewValue = 0;
34468let isCVI = 1;
34469let DecoderNamespace = "EXT_mmvec";
34470}
34471def V6_vlsrw_alt : HInst<
34472(outs HvxVR:$Vd32),
34473(ins HvxVR:$Vu32, IntRegs:$Rt32),
34474"$Vd32 = vlsrw($Vu32,$Rt32)",
34475PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34476let hasNewValue = 1;
34477let opNewValue = 0;
34478let isCVI = 1;
34479let isPseudo = 1;
34480let isCodeGenOnly = 1;
34481let DecoderNamespace = "EXT_mmvec";
34482}
34483def V6_vlsrwv : HInst<
34484(outs HvxVR:$Vd32),
34485(ins HvxVR:$Vu32, HvxVR:$Vv32),
34486"$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
34487tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
34488let Inst{7-5} = 0b001;
34489let Inst{13-13} = 0b0;
34490let Inst{31-21} = 0b00011111101;
34491let hasNewValue = 1;
34492let opNewValue = 0;
34493let isCVI = 1;
34494let DecoderNamespace = "EXT_mmvec";
34495}
34496def V6_vlsrwv_alt : HInst<
34497(outs HvxVR:$Vd32),
34498(ins HvxVR:$Vu32, HvxVR:$Vv32),
34499"$Vd32 = vlsrw($Vu32,$Vv32)",
34500PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34501let hasNewValue = 1;
34502let opNewValue = 0;
34503let isCVI = 1;
34504let isPseudo = 1;
34505let isCodeGenOnly = 1;
34506let DecoderNamespace = "EXT_mmvec";
34507}
34508def V6_vlut4 : HInst<
34509(outs HvxVR:$Vd32),
34510(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
34511"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
34512tc_f1de44ef, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
34513let Inst{7-5} = 0b100;
34514let Inst{13-13} = 0b0;
34515let Inst{31-21} = 0b00011001011;
34516let hasNewValue = 1;
34517let opNewValue = 0;
34518let isCVI = 1;
34519let DecoderNamespace = "EXT_mmvec";
34520}
34521def V6_vlutvvb : HInst<
34522(outs HvxVR:$Vd32),
34523(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34524"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
34525tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
34526let Inst{7-5} = 0b001;
34527let Inst{13-13} = 0b1;
34528let Inst{31-24} = 0b00011011;
34529let hasNewValue = 1;
34530let opNewValue = 0;
34531let isCVI = 1;
34532let DecoderNamespace = "EXT_mmvec";
34533}
34534def V6_vlutvvb_nm : HInst<
34535(outs HvxVR:$Vd32),
34536(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34537"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
34538tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
34539let Inst{7-5} = 0b011;
34540let Inst{13-13} = 0b0;
34541let Inst{31-24} = 0b00011000;
34542let hasNewValue = 1;
34543let opNewValue = 0;
34544let isCVI = 1;
34545let DecoderNamespace = "EXT_mmvec";
34546}
34547def V6_vlutvvb_oracc : HInst<
34548(outs HvxVR:$Vx32),
34549(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34550"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
34551tc_9d1dc972, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
34552let Inst{7-5} = 0b101;
34553let Inst{13-13} = 0b1;
34554let Inst{31-24} = 0b00011011;
34555let hasNewValue = 1;
34556let opNewValue = 0;
34557let isAccumulator = 1;
34558let isCVI = 1;
34559let DecoderNamespace = "EXT_mmvec";
34560let Constraints = "$Vx32 = $Vx32in";
34561}
34562def V6_vlutvvb_oracci : HInst<
34563(outs HvxVR:$Vx32),
34564(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34565"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
34566tc_9d1dc972, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
34567let Inst{13-13} = 0b1;
34568let Inst{31-21} = 0b00011100110;
34569let hasNewValue = 1;
34570let opNewValue = 0;
34571let isAccumulator = 1;
34572let isCVI = 1;
34573let DecoderNamespace = "EXT_mmvec";
34574let Constraints = "$Vx32 = $Vx32in";
34575}
34576def V6_vlutvvbi : HInst<
34577(outs HvxVR:$Vd32),
34578(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34579"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
34580tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
34581let Inst{13-13} = 0b0;
34582let Inst{31-21} = 0b00011110001;
34583let hasNewValue = 1;
34584let opNewValue = 0;
34585let isCVI = 1;
34586let DecoderNamespace = "EXT_mmvec";
34587}
34588def V6_vlutvwh : HInst<
34589(outs HvxWR:$Vdd32),
34590(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34591"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
34592tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
34593let Inst{7-5} = 0b110;
34594let Inst{13-13} = 0b1;
34595let Inst{31-24} = 0b00011011;
34596let hasNewValue = 1;
34597let opNewValue = 0;
34598let isCVI = 1;
34599let DecoderNamespace = "EXT_mmvec";
34600}
34601def V6_vlutvwh_nm : HInst<
34602(outs HvxWR:$Vdd32),
34603(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34604"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
34605tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
34606let Inst{7-5} = 0b100;
34607let Inst{13-13} = 0b0;
34608let Inst{31-24} = 0b00011000;
34609let hasNewValue = 1;
34610let opNewValue = 0;
34611let isCVI = 1;
34612let DecoderNamespace = "EXT_mmvec";
34613}
34614def V6_vlutvwh_oracc : HInst<
34615(outs HvxWR:$Vxx32),
34616(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
34617"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
34618tc_9d1dc972, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
34619let Inst{7-5} = 0b111;
34620let Inst{13-13} = 0b1;
34621let Inst{31-24} = 0b00011011;
34622let hasNewValue = 1;
34623let opNewValue = 0;
34624let isAccumulator = 1;
34625let isCVI = 1;
34626let DecoderNamespace = "EXT_mmvec";
34627let Constraints = "$Vxx32 = $Vxx32in";
34628}
34629def V6_vlutvwh_oracci : HInst<
34630(outs HvxWR:$Vxx32),
34631(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34632"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
34633tc_9d1dc972, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
34634let Inst{13-13} = 0b1;
34635let Inst{31-21} = 0b00011100111;
34636let hasNewValue = 1;
34637let opNewValue = 0;
34638let isAccumulator = 1;
34639let isCVI = 1;
34640let DecoderNamespace = "EXT_mmvec";
34641let Constraints = "$Vxx32 = $Vxx32in";
34642}
34643def V6_vlutvwhi : HInst<
34644(outs HvxWR:$Vdd32),
34645(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
34646"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
34647tc_87adc037, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
34648let Inst{13-13} = 0b0;
34649let Inst{31-21} = 0b00011110011;
34650let hasNewValue = 1;
34651let opNewValue = 0;
34652let isCVI = 1;
34653let DecoderNamespace = "EXT_mmvec";
34654}
34655def V6_vmax_bf : HInst<
34656(outs HvxVR:$Vd32),
34657(ins HvxVR:$Vu32, HvxVR:$Vv32),
34658"$Vd32.bf = vmax($Vu32.bf,$Vv32.bf)",
34659tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV73,UseHVXIEEEFP]> {
34660let Inst{7-5} = 0b111;
34661let Inst{13-13} = 0b1;
34662let Inst{31-21} = 0b00011101010;
34663let hasNewValue = 1;
34664let opNewValue = 0;
34665let isCVI = 1;
34666let DecoderNamespace = "EXT_mmvec";
34667}
34668def V6_vmax_hf : HInst<
34669(outs HvxVR:$Vd32),
34670(ins HvxVR:$Vu32, HvxVR:$Vv32),
34671"$Vd32.hf = vmax($Vu32.hf,$Vv32.hf)",
34672tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34673let Inst{7-5} = 0b011;
34674let Inst{13-13} = 0b1;
34675let Inst{31-21} = 0b00011111110;
34676let hasNewValue = 1;
34677let opNewValue = 0;
34678let isCVI = 1;
34679let isHVXALU = 1;
34680let isHVXALU2SRC = 1;
34681let DecoderNamespace = "EXT_mmvec";
34682}
34683def V6_vmax_sf : HInst<
34684(outs HvxVR:$Vd32),
34685(ins HvxVR:$Vu32, HvxVR:$Vv32),
34686"$Vd32.sf = vmax($Vu32.sf,$Vv32.sf)",
34687tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34688let Inst{7-5} = 0b001;
34689let Inst{13-13} = 0b1;
34690let Inst{31-21} = 0b00011111110;
34691let hasNewValue = 1;
34692let opNewValue = 0;
34693let isCVI = 1;
34694let isHVXALU = 1;
34695let isHVXALU2SRC = 1;
34696let DecoderNamespace = "EXT_mmvec";
34697}
34698def V6_vmaxb : HInst<
34699(outs HvxVR:$Vd32),
34700(ins HvxVR:$Vu32, HvxVR:$Vv32),
34701"$Vd32.b = vmax($Vu32.b,$Vv32.b)",
34702tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
34703let Inst{7-5} = 0b101;
34704let Inst{13-13} = 0b0;
34705let Inst{31-21} = 0b00011111001;
34706let hasNewValue = 1;
34707let opNewValue = 0;
34708let isCVI = 1;
34709let isHVXALU = 1;
34710let isHVXALU2SRC = 1;
34711let DecoderNamespace = "EXT_mmvec";
34712}
34713def V6_vmaxb_alt : HInst<
34714(outs HvxVR:$Vd32),
34715(ins HvxVR:$Vu32, HvxVR:$Vv32),
34716"$Vd32 = vmaxb($Vu32,$Vv32)",
34717PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34718let hasNewValue = 1;
34719let opNewValue = 0;
34720let isCVI = 1;
34721let isPseudo = 1;
34722let isCodeGenOnly = 1;
34723let DecoderNamespace = "EXT_mmvec";
34724}
34725def V6_vmaxh : HInst<
34726(outs HvxVR:$Vd32),
34727(ins HvxVR:$Vu32, HvxVR:$Vv32),
34728"$Vd32.h = vmax($Vu32.h,$Vv32.h)",
34729tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34730let Inst{7-5} = 0b111;
34731let Inst{13-13} = 0b0;
34732let Inst{31-21} = 0b00011111000;
34733let hasNewValue = 1;
34734let opNewValue = 0;
34735let isCVI = 1;
34736let isHVXALU = 1;
34737let isHVXALU2SRC = 1;
34738let DecoderNamespace = "EXT_mmvec";
34739}
34740def V6_vmaxh_alt : HInst<
34741(outs HvxVR:$Vd32),
34742(ins HvxVR:$Vu32, HvxVR:$Vv32),
34743"$Vd32 = vmaxh($Vu32,$Vv32)",
34744PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34745let hasNewValue = 1;
34746let opNewValue = 0;
34747let isCVI = 1;
34748let isPseudo = 1;
34749let isCodeGenOnly = 1;
34750let DecoderNamespace = "EXT_mmvec";
34751}
34752def V6_vmaxub : HInst<
34753(outs HvxVR:$Vd32),
34754(ins HvxVR:$Vu32, HvxVR:$Vv32),
34755"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
34756tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34757let Inst{7-5} = 0b101;
34758let Inst{13-13} = 0b0;
34759let Inst{31-21} = 0b00011111000;
34760let hasNewValue = 1;
34761let opNewValue = 0;
34762let isCVI = 1;
34763let isHVXALU = 1;
34764let isHVXALU2SRC = 1;
34765let DecoderNamespace = "EXT_mmvec";
34766}
34767def V6_vmaxub_alt : HInst<
34768(outs HvxVR:$Vd32),
34769(ins HvxVR:$Vu32, HvxVR:$Vv32),
34770"$Vd32 = vmaxub($Vu32,$Vv32)",
34771PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34772let hasNewValue = 1;
34773let opNewValue = 0;
34774let isCVI = 1;
34775let isPseudo = 1;
34776let isCodeGenOnly = 1;
34777let DecoderNamespace = "EXT_mmvec";
34778}
34779def V6_vmaxuh : HInst<
34780(outs HvxVR:$Vd32),
34781(ins HvxVR:$Vu32, HvxVR:$Vv32),
34782"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
34783tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34784let Inst{7-5} = 0b110;
34785let Inst{13-13} = 0b0;
34786let Inst{31-21} = 0b00011111000;
34787let hasNewValue = 1;
34788let opNewValue = 0;
34789let isCVI = 1;
34790let isHVXALU = 1;
34791let isHVXALU2SRC = 1;
34792let DecoderNamespace = "EXT_mmvec";
34793}
34794def V6_vmaxuh_alt : HInst<
34795(outs HvxVR:$Vd32),
34796(ins HvxVR:$Vu32, HvxVR:$Vv32),
34797"$Vd32 = vmaxuh($Vu32,$Vv32)",
34798PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34799let hasNewValue = 1;
34800let opNewValue = 0;
34801let isCVI = 1;
34802let isPseudo = 1;
34803let isCodeGenOnly = 1;
34804let DecoderNamespace = "EXT_mmvec";
34805}
34806def V6_vmaxw : HInst<
34807(outs HvxVR:$Vd32),
34808(ins HvxVR:$Vu32, HvxVR:$Vv32),
34809"$Vd32.w = vmax($Vu32.w,$Vv32.w)",
34810tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34811let Inst{7-5} = 0b000;
34812let Inst{13-13} = 0b0;
34813let Inst{31-21} = 0b00011111001;
34814let hasNewValue = 1;
34815let opNewValue = 0;
34816let isCVI = 1;
34817let isHVXALU = 1;
34818let isHVXALU2SRC = 1;
34819let DecoderNamespace = "EXT_mmvec";
34820}
34821def V6_vmaxw_alt : HInst<
34822(outs HvxVR:$Vd32),
34823(ins HvxVR:$Vu32, HvxVR:$Vv32),
34824"$Vd32 = vmaxw($Vu32,$Vv32)",
34825PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34826let hasNewValue = 1;
34827let opNewValue = 0;
34828let isCVI = 1;
34829let isPseudo = 1;
34830let isCodeGenOnly = 1;
34831let DecoderNamespace = "EXT_mmvec";
34832}
34833def V6_vmin_bf : HInst<
34834(outs HvxVR:$Vd32),
34835(ins HvxVR:$Vu32, HvxVR:$Vv32),
34836"$Vd32.bf = vmin($Vu32.bf,$Vv32.bf)",
34837tc_cda936da, TypeCVI_VX_LATE>, Enc_45364e, Requires<[UseHVXV73,UseHVXIEEEFP]> {
34838let Inst{7-5} = 0b000;
34839let Inst{13-13} = 0b1;
34840let Inst{31-21} = 0b00011101010;
34841let hasNewValue = 1;
34842let opNewValue = 0;
34843let isCVI = 1;
34844let DecoderNamespace = "EXT_mmvec";
34845}
34846def V6_vmin_hf : HInst<
34847(outs HvxVR:$Vd32),
34848(ins HvxVR:$Vu32, HvxVR:$Vv32),
34849"$Vd32.hf = vmin($Vu32.hf,$Vv32.hf)",
34850tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34851let Inst{7-5} = 0b100;
34852let Inst{13-13} = 0b1;
34853let Inst{31-21} = 0b00011111110;
34854let hasNewValue = 1;
34855let opNewValue = 0;
34856let isCVI = 1;
34857let isHVXALU = 1;
34858let isHVXALU2SRC = 1;
34859let DecoderNamespace = "EXT_mmvec";
34860}
34861def V6_vmin_sf : HInst<
34862(outs HvxVR:$Vd32),
34863(ins HvxVR:$Vu32, HvxVR:$Vv32),
34864"$Vd32.sf = vmin($Vu32.sf,$Vv32.sf)",
34865tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
34866let Inst{7-5} = 0b010;
34867let Inst{13-13} = 0b1;
34868let Inst{31-21} = 0b00011111110;
34869let hasNewValue = 1;
34870let opNewValue = 0;
34871let isCVI = 1;
34872let isHVXALU = 1;
34873let isHVXALU2SRC = 1;
34874let DecoderNamespace = "EXT_mmvec";
34875}
34876def V6_vminb : HInst<
34877(outs HvxVR:$Vd32),
34878(ins HvxVR:$Vu32, HvxVR:$Vv32),
34879"$Vd32.b = vmin($Vu32.b,$Vv32.b)",
34880tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
34881let Inst{7-5} = 0b100;
34882let Inst{13-13} = 0b0;
34883let Inst{31-21} = 0b00011111001;
34884let hasNewValue = 1;
34885let opNewValue = 0;
34886let isCVI = 1;
34887let isHVXALU = 1;
34888let isHVXALU2SRC = 1;
34889let DecoderNamespace = "EXT_mmvec";
34890}
34891def V6_vminb_alt : HInst<
34892(outs HvxVR:$Vd32),
34893(ins HvxVR:$Vu32, HvxVR:$Vv32),
34894"$Vd32 = vminb($Vu32,$Vv32)",
34895PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34896let hasNewValue = 1;
34897let opNewValue = 0;
34898let isCVI = 1;
34899let isPseudo = 1;
34900let isCodeGenOnly = 1;
34901let DecoderNamespace = "EXT_mmvec";
34902}
34903def V6_vminh : HInst<
34904(outs HvxVR:$Vd32),
34905(ins HvxVR:$Vu32, HvxVR:$Vv32),
34906"$Vd32.h = vmin($Vu32.h,$Vv32.h)",
34907tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34908let Inst{7-5} = 0b011;
34909let Inst{13-13} = 0b0;
34910let Inst{31-21} = 0b00011111000;
34911let hasNewValue = 1;
34912let opNewValue = 0;
34913let isCVI = 1;
34914let isHVXALU = 1;
34915let isHVXALU2SRC = 1;
34916let DecoderNamespace = "EXT_mmvec";
34917}
34918def V6_vminh_alt : HInst<
34919(outs HvxVR:$Vd32),
34920(ins HvxVR:$Vu32, HvxVR:$Vv32),
34921"$Vd32 = vminh($Vu32,$Vv32)",
34922PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34923let hasNewValue = 1;
34924let opNewValue = 0;
34925let isCVI = 1;
34926let isPseudo = 1;
34927let isCodeGenOnly = 1;
34928let DecoderNamespace = "EXT_mmvec";
34929}
34930def V6_vminub : HInst<
34931(outs HvxVR:$Vd32),
34932(ins HvxVR:$Vu32, HvxVR:$Vv32),
34933"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
34934tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34935let Inst{7-5} = 0b001;
34936let Inst{13-13} = 0b0;
34937let Inst{31-21} = 0b00011111000;
34938let hasNewValue = 1;
34939let opNewValue = 0;
34940let isCVI = 1;
34941let isHVXALU = 1;
34942let isHVXALU2SRC = 1;
34943let DecoderNamespace = "EXT_mmvec";
34944}
34945def V6_vminub_alt : HInst<
34946(outs HvxVR:$Vd32),
34947(ins HvxVR:$Vu32, HvxVR:$Vv32),
34948"$Vd32 = vminub($Vu32,$Vv32)",
34949PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34950let hasNewValue = 1;
34951let opNewValue = 0;
34952let isCVI = 1;
34953let isPseudo = 1;
34954let isCodeGenOnly = 1;
34955let DecoderNamespace = "EXT_mmvec";
34956}
34957def V6_vminuh : HInst<
34958(outs HvxVR:$Vd32),
34959(ins HvxVR:$Vu32, HvxVR:$Vv32),
34960"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
34961tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34962let Inst{7-5} = 0b010;
34963let Inst{13-13} = 0b0;
34964let Inst{31-21} = 0b00011111000;
34965let hasNewValue = 1;
34966let opNewValue = 0;
34967let isCVI = 1;
34968let isHVXALU = 1;
34969let isHVXALU2SRC = 1;
34970let DecoderNamespace = "EXT_mmvec";
34971}
34972def V6_vminuh_alt : HInst<
34973(outs HvxVR:$Vd32),
34974(ins HvxVR:$Vu32, HvxVR:$Vv32),
34975"$Vd32 = vminuh($Vu32,$Vv32)",
34976PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34977let hasNewValue = 1;
34978let opNewValue = 0;
34979let isCVI = 1;
34980let isPseudo = 1;
34981let isCodeGenOnly = 1;
34982let DecoderNamespace = "EXT_mmvec";
34983}
34984def V6_vminw : HInst<
34985(outs HvxVR:$Vd32),
34986(ins HvxVR:$Vu32, HvxVR:$Vv32),
34987"$Vd32.w = vmin($Vu32.w,$Vv32.w)",
34988tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
34989let Inst{7-5} = 0b100;
34990let Inst{13-13} = 0b0;
34991let Inst{31-21} = 0b00011111000;
34992let hasNewValue = 1;
34993let opNewValue = 0;
34994let isCVI = 1;
34995let isHVXALU = 1;
34996let isHVXALU2SRC = 1;
34997let DecoderNamespace = "EXT_mmvec";
34998}
34999def V6_vminw_alt : HInst<
35000(outs HvxVR:$Vd32),
35001(ins HvxVR:$Vu32, HvxVR:$Vv32),
35002"$Vd32 = vminw($Vu32,$Vv32)",
35003PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35004let hasNewValue = 1;
35005let opNewValue = 0;
35006let isCVI = 1;
35007let isPseudo = 1;
35008let isCodeGenOnly = 1;
35009let DecoderNamespace = "EXT_mmvec";
35010}
35011def V6_vmpabus : HInst<
35012(outs HvxWR:$Vdd32),
35013(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35014"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
35015tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
35016let Inst{7-5} = 0b110;
35017let Inst{13-13} = 0b0;
35018let Inst{31-21} = 0b00011001001;
35019let hasNewValue = 1;
35020let opNewValue = 0;
35021let isCVI = 1;
35022let DecoderNamespace = "EXT_mmvec";
35023}
35024def V6_vmpabus_acc : HInst<
35025(outs HvxWR:$Vxx32),
35026(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35027"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
35028tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
35029let Inst{7-5} = 0b110;
35030let Inst{13-13} = 0b1;
35031let Inst{31-21} = 0b00011001001;
35032let hasNewValue = 1;
35033let opNewValue = 0;
35034let isAccumulator = 1;
35035let isCVI = 1;
35036let DecoderNamespace = "EXT_mmvec";
35037let Constraints = "$Vxx32 = $Vxx32in";
35038}
35039def V6_vmpabus_acc_alt : HInst<
35040(outs HvxWR:$Vxx32),
35041(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35042"$Vxx32 += vmpabus($Vuu32,$Rt32)",
35043PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35044let hasNewValue = 1;
35045let opNewValue = 0;
35046let isAccumulator = 1;
35047let isCVI = 1;
35048let isPseudo = 1;
35049let isCodeGenOnly = 1;
35050let DecoderNamespace = "EXT_mmvec";
35051let Constraints = "$Vxx32 = $Vxx32in";
35052}
35053def V6_vmpabus_alt : HInst<
35054(outs HvxWR:$Vdd32),
35055(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35056"$Vdd32 = vmpabus($Vuu32,$Rt32)",
35057PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35058let hasNewValue = 1;
35059let opNewValue = 0;
35060let isCVI = 1;
35061let isPseudo = 1;
35062let isCodeGenOnly = 1;
35063let DecoderNamespace = "EXT_mmvec";
35064}
35065def V6_vmpabusv : HInst<
35066(outs HvxWR:$Vdd32),
35067(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35068"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
35069tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
35070let Inst{7-5} = 0b011;
35071let Inst{13-13} = 0b0;
35072let Inst{31-21} = 0b00011100001;
35073let hasNewValue = 1;
35074let opNewValue = 0;
35075let isCVI = 1;
35076let DecoderNamespace = "EXT_mmvec";
35077}
35078def V6_vmpabusv_alt : HInst<
35079(outs HvxWR:$Vdd32),
35080(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35081"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
35082PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35083let hasNewValue = 1;
35084let opNewValue = 0;
35085let isCVI = 1;
35086let isPseudo = 1;
35087let isCodeGenOnly = 1;
35088let DecoderNamespace = "EXT_mmvec";
35089}
35090def V6_vmpabuu : HInst<
35091(outs HvxWR:$Vdd32),
35092(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35093"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
35094tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
35095let Inst{7-5} = 0b011;
35096let Inst{13-13} = 0b0;
35097let Inst{31-21} = 0b00011001011;
35098let hasNewValue = 1;
35099let opNewValue = 0;
35100let isCVI = 1;
35101let DecoderNamespace = "EXT_mmvec";
35102}
35103def V6_vmpabuu_acc : HInst<
35104(outs HvxWR:$Vxx32),
35105(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35106"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
35107tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
35108let Inst{7-5} = 0b100;
35109let Inst{13-13} = 0b1;
35110let Inst{31-21} = 0b00011001101;
35111let hasNewValue = 1;
35112let opNewValue = 0;
35113let isAccumulator = 1;
35114let isCVI = 1;
35115let DecoderNamespace = "EXT_mmvec";
35116let Constraints = "$Vxx32 = $Vxx32in";
35117}
35118def V6_vmpabuu_acc_alt : HInst<
35119(outs HvxWR:$Vxx32),
35120(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35121"$Vxx32 += vmpabuu($Vuu32,$Rt32)",
35122PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35123let hasNewValue = 1;
35124let opNewValue = 0;
35125let isAccumulator = 1;
35126let isCVI = 1;
35127let isPseudo = 1;
35128let isCodeGenOnly = 1;
35129let DecoderNamespace = "EXT_mmvec";
35130let Constraints = "$Vxx32 = $Vxx32in";
35131}
35132def V6_vmpabuu_alt : HInst<
35133(outs HvxWR:$Vdd32),
35134(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35135"$Vdd32 = vmpabuu($Vuu32,$Rt32)",
35136PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35137let hasNewValue = 1;
35138let opNewValue = 0;
35139let isCVI = 1;
35140let isPseudo = 1;
35141let isCodeGenOnly = 1;
35142let DecoderNamespace = "EXT_mmvec";
35143}
35144def V6_vmpabuuv : HInst<
35145(outs HvxWR:$Vdd32),
35146(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35147"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
35148tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
35149let Inst{7-5} = 0b111;
35150let Inst{13-13} = 0b0;
35151let Inst{31-21} = 0b00011100111;
35152let hasNewValue = 1;
35153let opNewValue = 0;
35154let isCVI = 1;
35155let DecoderNamespace = "EXT_mmvec";
35156}
35157def V6_vmpabuuv_alt : HInst<
35158(outs HvxWR:$Vdd32),
35159(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
35160"$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
35161PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35162let hasNewValue = 1;
35163let opNewValue = 0;
35164let isCVI = 1;
35165let isPseudo = 1;
35166let isCodeGenOnly = 1;
35167let DecoderNamespace = "EXT_mmvec";
35168}
35169def V6_vmpahb : HInst<
35170(outs HvxWR:$Vdd32),
35171(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35172"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
35173tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
35174let Inst{7-5} = 0b111;
35175let Inst{13-13} = 0b0;
35176let Inst{31-21} = 0b00011001001;
35177let hasNewValue = 1;
35178let opNewValue = 0;
35179let isCVI = 1;
35180let DecoderNamespace = "EXT_mmvec";
35181}
35182def V6_vmpahb_acc : HInst<
35183(outs HvxWR:$Vxx32),
35184(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35185"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
35186tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
35187let Inst{7-5} = 0b111;
35188let Inst{13-13} = 0b1;
35189let Inst{31-21} = 0b00011001001;
35190let hasNewValue = 1;
35191let opNewValue = 0;
35192let isAccumulator = 1;
35193let isCVI = 1;
35194let DecoderNamespace = "EXT_mmvec";
35195let Constraints = "$Vxx32 = $Vxx32in";
35196}
35197def V6_vmpahb_acc_alt : HInst<
35198(outs HvxWR:$Vxx32),
35199(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35200"$Vxx32 += vmpahb($Vuu32,$Rt32)",
35201PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35202let hasNewValue = 1;
35203let opNewValue = 0;
35204let isAccumulator = 1;
35205let isCVI = 1;
35206let isPseudo = 1;
35207let isCodeGenOnly = 1;
35208let DecoderNamespace = "EXT_mmvec";
35209let Constraints = "$Vxx32 = $Vxx32in";
35210}
35211def V6_vmpahb_alt : HInst<
35212(outs HvxWR:$Vdd32),
35213(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35214"$Vdd32 = vmpahb($Vuu32,$Rt32)",
35215PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35216let hasNewValue = 1;
35217let opNewValue = 0;
35218let isCVI = 1;
35219let isPseudo = 1;
35220let isCodeGenOnly = 1;
35221let DecoderNamespace = "EXT_mmvec";
35222}
35223def V6_vmpahhsat : HInst<
35224(outs HvxVR:$Vx32),
35225(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35226"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
35227tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
35228let Inst{7-5} = 0b100;
35229let Inst{13-13} = 0b1;
35230let Inst{31-21} = 0b00011001100;
35231let hasNewValue = 1;
35232let opNewValue = 0;
35233let isCVI = 1;
35234let DecoderNamespace = "EXT_mmvec";
35235let Constraints = "$Vx32 = $Vx32in";
35236}
35237def V6_vmpauhb : HInst<
35238(outs HvxWR:$Vdd32),
35239(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35240"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
35241tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
35242let Inst{7-5} = 0b101;
35243let Inst{13-13} = 0b0;
35244let Inst{31-21} = 0b00011001100;
35245let hasNewValue = 1;
35246let opNewValue = 0;
35247let isCVI = 1;
35248let DecoderNamespace = "EXT_mmvec";
35249}
35250def V6_vmpauhb_acc : HInst<
35251(outs HvxWR:$Vxx32),
35252(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35253"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
35254tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
35255let Inst{7-5} = 0b010;
35256let Inst{13-13} = 0b1;
35257let Inst{31-21} = 0b00011001100;
35258let hasNewValue = 1;
35259let opNewValue = 0;
35260let isAccumulator = 1;
35261let isCVI = 1;
35262let DecoderNamespace = "EXT_mmvec";
35263let Constraints = "$Vxx32 = $Vxx32in";
35264}
35265def V6_vmpauhb_acc_alt : HInst<
35266(outs HvxWR:$Vxx32),
35267(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
35268"$Vxx32 += vmpauhb($Vuu32,$Rt32)",
35269PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35270let hasNewValue = 1;
35271let opNewValue = 0;
35272let isAccumulator = 1;
35273let isCVI = 1;
35274let isPseudo = 1;
35275let isCodeGenOnly = 1;
35276let DecoderNamespace = "EXT_mmvec";
35277let Constraints = "$Vxx32 = $Vxx32in";
35278}
35279def V6_vmpauhb_alt : HInst<
35280(outs HvxWR:$Vdd32),
35281(ins HvxWR:$Vuu32, IntRegs:$Rt32),
35282"$Vdd32 = vmpauhb($Vuu32,$Rt32)",
35283PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
35284let hasNewValue = 1;
35285let opNewValue = 0;
35286let isCVI = 1;
35287let isPseudo = 1;
35288let isCodeGenOnly = 1;
35289let DecoderNamespace = "EXT_mmvec";
35290}
35291def V6_vmpauhuhsat : HInst<
35292(outs HvxVR:$Vx32),
35293(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35294"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
35295tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
35296let Inst{7-5} = 0b101;
35297let Inst{13-13} = 0b1;
35298let Inst{31-21} = 0b00011001100;
35299let hasNewValue = 1;
35300let opNewValue = 0;
35301let isCVI = 1;
35302let DecoderNamespace = "EXT_mmvec";
35303let Constraints = "$Vx32 = $Vx32in";
35304}
35305def V6_vmpsuhuhsat : HInst<
35306(outs HvxVR:$Vx32),
35307(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35308"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
35309tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
35310let Inst{7-5} = 0b110;
35311let Inst{13-13} = 0b1;
35312let Inst{31-21} = 0b00011001100;
35313let hasNewValue = 1;
35314let opNewValue = 0;
35315let isCVI = 1;
35316let DecoderNamespace = "EXT_mmvec";
35317let Constraints = "$Vx32 = $Vx32in";
35318}
35319def V6_vmpy_hf_hf : HInst<
35320(outs HvxVR:$Vd32),
35321(ins HvxVR:$Vu32, HvxVR:$Vv32),
35322"$Vd32.hf = vmpy($Vu32.hf,$Vv32.hf)",
35323tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35324let Inst{7-5} = 0b011;
35325let Inst{13-13} = 0b1;
35326let Inst{31-21} = 0b00011111100;
35327let hasNewValue = 1;
35328let opNewValue = 0;
35329let isCVI = 1;
35330let DecoderNamespace = "EXT_mmvec";
35331}
35332def V6_vmpy_hf_hf_acc : HInst<
35333(outs HvxVR:$Vx32),
35334(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35335"$Vx32.hf += vmpy($Vu32.hf,$Vv32.hf)",
35336tc_a19b9305, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35337let Inst{7-5} = 0b010;
35338let Inst{13-13} = 0b1;
35339let Inst{31-21} = 0b00011100010;
35340let hasNewValue = 1;
35341let opNewValue = 0;
35342let isAccumulator = 1;
35343let isCVI = 1;
35344let DecoderNamespace = "EXT_mmvec";
35345let Constraints = "$Vx32 = $Vx32in";
35346}
35347def V6_vmpy_qf16 : HInst<
35348(outs HvxVR:$Vd32),
35349(ins HvxVR:$Vu32, HvxVR:$Vv32),
35350"$Vd32.qf16 = vmpy($Vu32.qf16,$Vv32.qf16)",
35351tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35352let Inst{7-5} = 0b011;
35353let Inst{13-13} = 0b1;
35354let Inst{31-21} = 0b00011111111;
35355let hasNewValue = 1;
35356let opNewValue = 0;
35357let isCVI = 1;
35358let DecoderNamespace = "EXT_mmvec";
35359}
35360def V6_vmpy_qf16_hf : HInst<
35361(outs HvxVR:$Vd32),
35362(ins HvxVR:$Vu32, HvxVR:$Vv32),
35363"$Vd32.qf16 = vmpy($Vu32.hf,$Vv32.hf)",
35364tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35365let Inst{7-5} = 0b100;
35366let Inst{13-13} = 0b1;
35367let Inst{31-21} = 0b00011111111;
35368let hasNewValue = 1;
35369let opNewValue = 0;
35370let isCVI = 1;
35371let DecoderNamespace = "EXT_mmvec";
35372}
35373def V6_vmpy_qf16_mix_hf : HInst<
35374(outs HvxVR:$Vd32),
35375(ins HvxVR:$Vu32, HvxVR:$Vv32),
35376"$Vd32.qf16 = vmpy($Vu32.qf16,$Vv32.hf)",
35377tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35378let Inst{7-5} = 0b101;
35379let Inst{13-13} = 0b1;
35380let Inst{31-21} = 0b00011111111;
35381let hasNewValue = 1;
35382let opNewValue = 0;
35383let isCVI = 1;
35384let DecoderNamespace = "EXT_mmvec";
35385}
35386def V6_vmpy_qf32 : HInst<
35387(outs HvxVR:$Vd32),
35388(ins HvxVR:$Vu32, HvxVR:$Vv32),
35389"$Vd32.qf32 = vmpy($Vu32.qf32,$Vv32.qf32)",
35390tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35391let Inst{7-5} = 0b000;
35392let Inst{13-13} = 0b1;
35393let Inst{31-21} = 0b00011111111;
35394let hasNewValue = 1;
35395let opNewValue = 0;
35396let isCVI = 1;
35397let DecoderNamespace = "EXT_mmvec";
35398}
35399def V6_vmpy_qf32_hf : HInst<
35400(outs HvxWR:$Vdd32),
35401(ins HvxVR:$Vu32, HvxVR:$Vv32),
35402"$Vdd32.qf32 = vmpy($Vu32.hf,$Vv32.hf)",
35403tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
35404let Inst{7-5} = 0b111;
35405let Inst{13-13} = 0b1;
35406let Inst{31-21} = 0b00011111111;
35407let hasNewValue = 1;
35408let opNewValue = 0;
35409let isCVI = 1;
35410let DecoderNamespace = "EXT_mmvec";
35411}
35412def V6_vmpy_qf32_mix_hf : HInst<
35413(outs HvxWR:$Vdd32),
35414(ins HvxVR:$Vu32, HvxVR:$Vv32),
35415"$Vdd32.qf32 = vmpy($Vu32.qf16,$Vv32.hf)",
35416tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
35417let Inst{7-5} = 0b000;
35418let Inst{13-13} = 0b1;
35419let Inst{31-21} = 0b00011111100;
35420let hasNewValue = 1;
35421let opNewValue = 0;
35422let isCVI = 1;
35423let DecoderNamespace = "EXT_mmvec";
35424}
35425def V6_vmpy_qf32_qf16 : HInst<
35426(outs HvxWR:$Vdd32),
35427(ins HvxVR:$Vu32, HvxVR:$Vv32),
35428"$Vdd32.qf32 = vmpy($Vu32.qf16,$Vv32.qf16)",
35429tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXQFloat]> {
35430let Inst{7-5} = 0b110;
35431let Inst{13-13} = 0b1;
35432let Inst{31-21} = 0b00011111111;
35433let hasNewValue = 1;
35434let opNewValue = 0;
35435let isCVI = 1;
35436let DecoderNamespace = "EXT_mmvec";
35437}
35438def V6_vmpy_qf32_sf : HInst<
35439(outs HvxVR:$Vd32),
35440(ins HvxVR:$Vu32, HvxVR:$Vv32),
35441"$Vd32.qf32 = vmpy($Vu32.sf,$Vv32.sf)",
35442tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
35443let Inst{7-5} = 0b001;
35444let Inst{13-13} = 0b1;
35445let Inst{31-21} = 0b00011111111;
35446let hasNewValue = 1;
35447let opNewValue = 0;
35448let isCVI = 1;
35449let DecoderNamespace = "EXT_mmvec";
35450}
35451def V6_vmpy_sf_bf : HInst<
35452(outs HvxWR:$Vdd32),
35453(ins HvxVR:$Vu32, HvxVR:$Vv32),
35454"$Vdd32.sf = vmpy($Vu32.bf,$Vv32.bf)",
35455tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV73,UseHVXIEEEFP]> {
35456let Inst{7-5} = 0b100;
35457let Inst{13-13} = 0b1;
35458let Inst{31-21} = 0b00011101010;
35459let hasNewValue = 1;
35460let opNewValue = 0;
35461let isCVI = 1;
35462let DecoderNamespace = "EXT_mmvec";
35463}
35464def V6_vmpy_sf_bf_acc : HInst<
35465(outs HvxWR:$Vxx32),
35466(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35467"$Vxx32.sf += vmpy($Vu32.bf,$Vv32.bf)",
35468tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV73,UseHVXIEEEFP]> {
35469let Inst{7-5} = 0b000;
35470let Inst{13-13} = 0b1;
35471let Inst{31-21} = 0b00011101000;
35472let hasNewValue = 1;
35473let opNewValue = 0;
35474let isAccumulator = 1;
35475let isCVI = 1;
35476let DecoderNamespace = "EXT_mmvec";
35477let Constraints = "$Vxx32 = $Vxx32in";
35478}
35479def V6_vmpy_sf_hf : HInst<
35480(outs HvxWR:$Vdd32),
35481(ins HvxVR:$Vu32, HvxVR:$Vv32),
35482"$Vdd32.sf = vmpy($Vu32.hf,$Vv32.hf)",
35483tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35484let Inst{7-5} = 0b010;
35485let Inst{13-13} = 0b1;
35486let Inst{31-21} = 0b00011111100;
35487let hasNewValue = 1;
35488let opNewValue = 0;
35489let isCVI = 1;
35490let DecoderNamespace = "EXT_mmvec";
35491}
35492def V6_vmpy_sf_hf_acc : HInst<
35493(outs HvxWR:$Vxx32),
35494(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35495"$Vxx32.sf += vmpy($Vu32.hf,$Vv32.hf)",
35496tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35497let Inst{7-5} = 0b001;
35498let Inst{13-13} = 0b1;
35499let Inst{31-21} = 0b00011100010;
35500let hasNewValue = 1;
35501let opNewValue = 0;
35502let isAccumulator = 1;
35503let isCVI = 1;
35504let DecoderNamespace = "EXT_mmvec";
35505let Constraints = "$Vxx32 = $Vxx32in";
35506}
35507def V6_vmpy_sf_sf : HInst<
35508(outs HvxVR:$Vd32),
35509(ins HvxVR:$Vu32, HvxVR:$Vv32),
35510"$Vd32.sf = vmpy($Vu32.sf,$Vv32.sf)",
35511tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
35512let Inst{7-5} = 0b001;
35513let Inst{13-13} = 0b1;
35514let Inst{31-21} = 0b00011111100;
35515let hasNewValue = 1;
35516let opNewValue = 0;
35517let isCVI = 1;
35518let DecoderNamespace = "EXT_mmvec";
35519}
35520def V6_vmpybus : HInst<
35521(outs HvxWR:$Vdd32),
35522(ins HvxVR:$Vu32, IntRegs:$Rt32),
35523"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
35524tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35525let Inst{7-5} = 0b101;
35526let Inst{13-13} = 0b0;
35527let Inst{31-21} = 0b00011001001;
35528let hasNewValue = 1;
35529let opNewValue = 0;
35530let isCVI = 1;
35531let DecoderNamespace = "EXT_mmvec";
35532}
35533def V6_vmpybus_acc : HInst<
35534(outs HvxWR:$Vxx32),
35535(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35536"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
35537tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35538let Inst{7-5} = 0b101;
35539let Inst{13-13} = 0b1;
35540let Inst{31-21} = 0b00011001001;
35541let hasNewValue = 1;
35542let opNewValue = 0;
35543let isAccumulator = 1;
35544let isCVI = 1;
35545let DecoderNamespace = "EXT_mmvec";
35546let Constraints = "$Vxx32 = $Vxx32in";
35547}
35548def V6_vmpybus_acc_alt : HInst<
35549(outs HvxWR:$Vxx32),
35550(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35551"$Vxx32 += vmpybus($Vu32,$Rt32)",
35552PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35553let hasNewValue = 1;
35554let opNewValue = 0;
35555let isAccumulator = 1;
35556let isCVI = 1;
35557let isPseudo = 1;
35558let isCodeGenOnly = 1;
35559let DecoderNamespace = "EXT_mmvec";
35560let Constraints = "$Vxx32 = $Vxx32in";
35561}
35562def V6_vmpybus_alt : HInst<
35563(outs HvxWR:$Vdd32),
35564(ins HvxVR:$Vu32, IntRegs:$Rt32),
35565"$Vdd32 = vmpybus($Vu32,$Rt32)",
35566PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35567let hasNewValue = 1;
35568let opNewValue = 0;
35569let isCVI = 1;
35570let isPseudo = 1;
35571let isCodeGenOnly = 1;
35572let DecoderNamespace = "EXT_mmvec";
35573}
35574def V6_vmpybusv : HInst<
35575(outs HvxWR:$Vdd32),
35576(ins HvxVR:$Vu32, HvxVR:$Vv32),
35577"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
35578tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35579let Inst{7-5} = 0b110;
35580let Inst{13-13} = 0b0;
35581let Inst{31-21} = 0b00011100000;
35582let hasNewValue = 1;
35583let opNewValue = 0;
35584let isCVI = 1;
35585let DecoderNamespace = "EXT_mmvec";
35586}
35587def V6_vmpybusv_acc : HInst<
35588(outs HvxWR:$Vxx32),
35589(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35590"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
35591tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35592let Inst{7-5} = 0b110;
35593let Inst{13-13} = 0b1;
35594let Inst{31-21} = 0b00011100000;
35595let hasNewValue = 1;
35596let opNewValue = 0;
35597let isAccumulator = 1;
35598let isCVI = 1;
35599let DecoderNamespace = "EXT_mmvec";
35600let Constraints = "$Vxx32 = $Vxx32in";
35601}
35602def V6_vmpybusv_acc_alt : HInst<
35603(outs HvxWR:$Vxx32),
35604(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35605"$Vxx32 += vmpybus($Vu32,$Vv32)",
35606PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35607let hasNewValue = 1;
35608let opNewValue = 0;
35609let isAccumulator = 1;
35610let isCVI = 1;
35611let isPseudo = 1;
35612let isCodeGenOnly = 1;
35613let DecoderNamespace = "EXT_mmvec";
35614let Constraints = "$Vxx32 = $Vxx32in";
35615}
35616def V6_vmpybusv_alt : HInst<
35617(outs HvxWR:$Vdd32),
35618(ins HvxVR:$Vu32, HvxVR:$Vv32),
35619"$Vdd32 = vmpybus($Vu32,$Vv32)",
35620PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35621let hasNewValue = 1;
35622let opNewValue = 0;
35623let isCVI = 1;
35624let isPseudo = 1;
35625let isCodeGenOnly = 1;
35626let DecoderNamespace = "EXT_mmvec";
35627}
35628def V6_vmpybv : HInst<
35629(outs HvxWR:$Vdd32),
35630(ins HvxVR:$Vu32, HvxVR:$Vv32),
35631"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
35632tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35633let Inst{7-5} = 0b100;
35634let Inst{13-13} = 0b0;
35635let Inst{31-21} = 0b00011100000;
35636let hasNewValue = 1;
35637let opNewValue = 0;
35638let isCVI = 1;
35639let DecoderNamespace = "EXT_mmvec";
35640}
35641def V6_vmpybv_acc : HInst<
35642(outs HvxWR:$Vxx32),
35643(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35644"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
35645tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35646let Inst{7-5} = 0b100;
35647let Inst{13-13} = 0b1;
35648let Inst{31-21} = 0b00011100000;
35649let hasNewValue = 1;
35650let opNewValue = 0;
35651let isAccumulator = 1;
35652let isCVI = 1;
35653let DecoderNamespace = "EXT_mmvec";
35654let Constraints = "$Vxx32 = $Vxx32in";
35655}
35656def V6_vmpybv_acc_alt : HInst<
35657(outs HvxWR:$Vxx32),
35658(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35659"$Vxx32 += vmpyb($Vu32,$Vv32)",
35660PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35661let hasNewValue = 1;
35662let opNewValue = 0;
35663let isAccumulator = 1;
35664let isCVI = 1;
35665let isPseudo = 1;
35666let isCodeGenOnly = 1;
35667let DecoderNamespace = "EXT_mmvec";
35668let Constraints = "$Vxx32 = $Vxx32in";
35669}
35670def V6_vmpybv_alt : HInst<
35671(outs HvxWR:$Vdd32),
35672(ins HvxVR:$Vu32, HvxVR:$Vv32),
35673"$Vdd32 = vmpyb($Vu32,$Vv32)",
35674PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35675let hasNewValue = 1;
35676let opNewValue = 0;
35677let isCVI = 1;
35678let isPseudo = 1;
35679let isCodeGenOnly = 1;
35680let DecoderNamespace = "EXT_mmvec";
35681}
35682def V6_vmpyewuh : HInst<
35683(outs HvxVR:$Vd32),
35684(ins HvxVR:$Vu32, HvxVR:$Vv32),
35685"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
35686tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35687let Inst{7-5} = 0b101;
35688let Inst{13-13} = 0b0;
35689let Inst{31-21} = 0b00011111111;
35690let hasNewValue = 1;
35691let opNewValue = 0;
35692let isCVI = 1;
35693let DecoderNamespace = "EXT_mmvec";
35694}
35695def V6_vmpyewuh_64 : HInst<
35696(outs HvxWR:$Vdd32),
35697(ins HvxVR:$Vu32, HvxVR:$Vv32),
35698"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
35699tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
35700let Inst{7-5} = 0b110;
35701let Inst{13-13} = 0b0;
35702let Inst{31-21} = 0b00011110101;
35703let hasNewValue = 1;
35704let opNewValue = 0;
35705let isCVI = 1;
35706let DecoderNamespace = "EXT_mmvec";
35707}
35708def V6_vmpyewuh_alt : HInst<
35709(outs HvxVR:$Vd32),
35710(ins HvxVR:$Vu32, HvxVR:$Vv32),
35711"$Vd32 = vmpyewuh($Vu32,$Vv32)",
35712PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35713let hasNewValue = 1;
35714let opNewValue = 0;
35715let isCVI = 1;
35716let isPseudo = 1;
35717let isCodeGenOnly = 1;
35718let DecoderNamespace = "EXT_mmvec";
35719}
35720def V6_vmpyh : HInst<
35721(outs HvxWR:$Vdd32),
35722(ins HvxVR:$Vu32, IntRegs:$Rt32),
35723"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
35724tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35725let Inst{7-5} = 0b000;
35726let Inst{13-13} = 0b0;
35727let Inst{31-21} = 0b00011001010;
35728let hasNewValue = 1;
35729let opNewValue = 0;
35730let isCVI = 1;
35731let DecoderNamespace = "EXT_mmvec";
35732}
35733def V6_vmpyh_acc : HInst<
35734(outs HvxWR:$Vxx32),
35735(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35736"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
35737tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
35738let Inst{7-5} = 0b110;
35739let Inst{13-13} = 0b1;
35740let Inst{31-21} = 0b00011001101;
35741let hasNewValue = 1;
35742let opNewValue = 0;
35743let isAccumulator = 1;
35744let isCVI = 1;
35745let DecoderNamespace = "EXT_mmvec";
35746let Constraints = "$Vxx32 = $Vxx32in";
35747}
35748def V6_vmpyh_acc_alt : HInst<
35749(outs HvxWR:$Vxx32),
35750(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35751"$Vxx32 += vmpyh($Vu32,$Rt32)",
35752PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35753let hasNewValue = 1;
35754let opNewValue = 0;
35755let isAccumulator = 1;
35756let isCVI = 1;
35757let isPseudo = 1;
35758let isCodeGenOnly = 1;
35759let DecoderNamespace = "EXT_mmvec";
35760let Constraints = "$Vxx32 = $Vxx32in";
35761}
35762def V6_vmpyh_alt : HInst<
35763(outs HvxWR:$Vdd32),
35764(ins HvxVR:$Vu32, IntRegs:$Rt32),
35765"$Vdd32 = vmpyh($Vu32,$Rt32)",
35766PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35767let hasNewValue = 1;
35768let opNewValue = 0;
35769let isCVI = 1;
35770let isPseudo = 1;
35771let isCodeGenOnly = 1;
35772let DecoderNamespace = "EXT_mmvec";
35773}
35774def V6_vmpyhsat_acc : HInst<
35775(outs HvxWR:$Vxx32),
35776(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35777"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
35778tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35779let Inst{7-5} = 0b000;
35780let Inst{13-13} = 0b1;
35781let Inst{31-21} = 0b00011001010;
35782let hasNewValue = 1;
35783let opNewValue = 0;
35784let isAccumulator = 1;
35785let isCVI = 1;
35786let DecoderNamespace = "EXT_mmvec";
35787let Constraints = "$Vxx32 = $Vxx32in";
35788}
35789def V6_vmpyhsat_acc_alt : HInst<
35790(outs HvxWR:$Vxx32),
35791(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35792"$Vxx32 += vmpyh($Vu32,$Rt32):sat",
35793PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35794let hasNewValue = 1;
35795let opNewValue = 0;
35796let isAccumulator = 1;
35797let isCVI = 1;
35798let isPseudo = 1;
35799let isCodeGenOnly = 1;
35800let DecoderNamespace = "EXT_mmvec";
35801let Constraints = "$Vxx32 = $Vxx32in";
35802}
35803def V6_vmpyhsrs : HInst<
35804(outs HvxVR:$Vd32),
35805(ins HvxVR:$Vu32, IntRegs:$Rt32),
35806"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
35807tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35808let Inst{7-5} = 0b010;
35809let Inst{13-13} = 0b0;
35810let Inst{31-21} = 0b00011001010;
35811let hasNewValue = 1;
35812let opNewValue = 0;
35813let isCVI = 1;
35814let DecoderNamespace = "EXT_mmvec";
35815}
35816def V6_vmpyhsrs_alt : HInst<
35817(outs HvxVR:$Vd32),
35818(ins HvxVR:$Vu32, IntRegs:$Rt32),
35819"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
35820PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35821let hasNewValue = 1;
35822let opNewValue = 0;
35823let isCVI = 1;
35824let isPseudo = 1;
35825let isCodeGenOnly = 1;
35826let DecoderNamespace = "EXT_mmvec";
35827}
35828def V6_vmpyhss : HInst<
35829(outs HvxVR:$Vd32),
35830(ins HvxVR:$Vu32, IntRegs:$Rt32),
35831"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
35832tc_dcca380f, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35833let Inst{7-5} = 0b001;
35834let Inst{13-13} = 0b0;
35835let Inst{31-21} = 0b00011001010;
35836let hasNewValue = 1;
35837let opNewValue = 0;
35838let isCVI = 1;
35839let DecoderNamespace = "EXT_mmvec";
35840}
35841def V6_vmpyhss_alt : HInst<
35842(outs HvxVR:$Vd32),
35843(ins HvxVR:$Vu32, IntRegs:$Rt32),
35844"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
35845PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35846let hasNewValue = 1;
35847let opNewValue = 0;
35848let isCVI = 1;
35849let isPseudo = 1;
35850let isCodeGenOnly = 1;
35851let DecoderNamespace = "EXT_mmvec";
35852}
35853def V6_vmpyhus : HInst<
35854(outs HvxWR:$Vdd32),
35855(ins HvxVR:$Vu32, HvxVR:$Vv32),
35856"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
35857tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35858let Inst{7-5} = 0b010;
35859let Inst{13-13} = 0b0;
35860let Inst{31-21} = 0b00011100001;
35861let hasNewValue = 1;
35862let opNewValue = 0;
35863let isCVI = 1;
35864let DecoderNamespace = "EXT_mmvec";
35865}
35866def V6_vmpyhus_acc : HInst<
35867(outs HvxWR:$Vxx32),
35868(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35869"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
35870tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35871let Inst{7-5} = 0b001;
35872let Inst{13-13} = 0b1;
35873let Inst{31-21} = 0b00011100001;
35874let hasNewValue = 1;
35875let opNewValue = 0;
35876let isAccumulator = 1;
35877let isCVI = 1;
35878let DecoderNamespace = "EXT_mmvec";
35879let Constraints = "$Vxx32 = $Vxx32in";
35880}
35881def V6_vmpyhus_acc_alt : HInst<
35882(outs HvxWR:$Vxx32),
35883(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35884"$Vxx32 += vmpyhus($Vu32,$Vv32)",
35885PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35886let hasNewValue = 1;
35887let opNewValue = 0;
35888let isAccumulator = 1;
35889let isCVI = 1;
35890let isPseudo = 1;
35891let isCodeGenOnly = 1;
35892let DecoderNamespace = "EXT_mmvec";
35893let Constraints = "$Vxx32 = $Vxx32in";
35894}
35895def V6_vmpyhus_alt : HInst<
35896(outs HvxWR:$Vdd32),
35897(ins HvxVR:$Vu32, HvxVR:$Vv32),
35898"$Vdd32 = vmpyhus($Vu32,$Vv32)",
35899PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35900let hasNewValue = 1;
35901let opNewValue = 0;
35902let isCVI = 1;
35903let isPseudo = 1;
35904let isCodeGenOnly = 1;
35905let DecoderNamespace = "EXT_mmvec";
35906}
35907def V6_vmpyhv : HInst<
35908(outs HvxWR:$Vdd32),
35909(ins HvxVR:$Vu32, HvxVR:$Vv32),
35910"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
35911tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35912let Inst{7-5} = 0b111;
35913let Inst{13-13} = 0b0;
35914let Inst{31-21} = 0b00011100000;
35915let hasNewValue = 1;
35916let opNewValue = 0;
35917let isCVI = 1;
35918let DecoderNamespace = "EXT_mmvec";
35919}
35920def V6_vmpyhv_acc : HInst<
35921(outs HvxWR:$Vxx32),
35922(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35923"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
35924tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35925let Inst{7-5} = 0b111;
35926let Inst{13-13} = 0b1;
35927let Inst{31-21} = 0b00011100000;
35928let hasNewValue = 1;
35929let opNewValue = 0;
35930let isAccumulator = 1;
35931let isCVI = 1;
35932let DecoderNamespace = "EXT_mmvec";
35933let Constraints = "$Vxx32 = $Vxx32in";
35934}
35935def V6_vmpyhv_acc_alt : HInst<
35936(outs HvxWR:$Vxx32),
35937(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35938"$Vxx32 += vmpyh($Vu32,$Vv32)",
35939PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35940let hasNewValue = 1;
35941let opNewValue = 0;
35942let isAccumulator = 1;
35943let isCVI = 1;
35944let isPseudo = 1;
35945let isCodeGenOnly = 1;
35946let DecoderNamespace = "EXT_mmvec";
35947let Constraints = "$Vxx32 = $Vxx32in";
35948}
35949def V6_vmpyhv_alt : HInst<
35950(outs HvxWR:$Vdd32),
35951(ins HvxVR:$Vu32, HvxVR:$Vv32),
35952"$Vdd32 = vmpyh($Vu32,$Vv32)",
35953PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35954let hasNewValue = 1;
35955let opNewValue = 0;
35956let isCVI = 1;
35957let isPseudo = 1;
35958let isCodeGenOnly = 1;
35959let DecoderNamespace = "EXT_mmvec";
35960}
35961def V6_vmpyhvsrs : HInst<
35962(outs HvxVR:$Vd32),
35963(ins HvxVR:$Vu32, HvxVR:$Vv32),
35964"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
35965tc_73efe966, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35966let Inst{7-5} = 0b001;
35967let Inst{13-13} = 0b0;
35968let Inst{31-21} = 0b00011100001;
35969let hasNewValue = 1;
35970let opNewValue = 0;
35971let isCVI = 1;
35972let DecoderNamespace = "EXT_mmvec";
35973}
35974def V6_vmpyhvsrs_alt : HInst<
35975(outs HvxVR:$Vd32),
35976(ins HvxVR:$Vu32, HvxVR:$Vv32),
35977"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
35978PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35979let hasNewValue = 1;
35980let opNewValue = 0;
35981let isCVI = 1;
35982let isPseudo = 1;
35983let isCodeGenOnly = 1;
35984let DecoderNamespace = "EXT_mmvec";
35985}
35986def V6_vmpyieoh : HInst<
35987(outs HvxVR:$Vd32),
35988(ins HvxVR:$Vu32, HvxVR:$Vv32),
35989"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
35990tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35991let Inst{7-5} = 0b000;
35992let Inst{13-13} = 0b0;
35993let Inst{31-21} = 0b00011111011;
35994let hasNewValue = 1;
35995let opNewValue = 0;
35996let isCVI = 1;
35997let DecoderNamespace = "EXT_mmvec";
35998}
35999def V6_vmpyiewh_acc : HInst<
36000(outs HvxVR:$Vx32),
36001(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36002"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
36003tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36004let Inst{7-5} = 0b000;
36005let Inst{13-13} = 0b1;
36006let Inst{31-21} = 0b00011100010;
36007let hasNewValue = 1;
36008let opNewValue = 0;
36009let isAccumulator = 1;
36010let isCVI = 1;
36011let DecoderNamespace = "EXT_mmvec";
36012let Constraints = "$Vx32 = $Vx32in";
36013}
36014def V6_vmpyiewh_acc_alt : HInst<
36015(outs HvxVR:$Vx32),
36016(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36017"$Vx32 += vmpyiewh($Vu32,$Vv32)",
36018PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36019let hasNewValue = 1;
36020let opNewValue = 0;
36021let isAccumulator = 1;
36022let isCVI = 1;
36023let isPseudo = 1;
36024let isCodeGenOnly = 1;
36025let DecoderNamespace = "EXT_mmvec";
36026let Constraints = "$Vx32 = $Vx32in";
36027}
36028def V6_vmpyiewuh : HInst<
36029(outs HvxVR:$Vd32),
36030(ins HvxVR:$Vu32, HvxVR:$Vv32),
36031"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
36032tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36033let Inst{7-5} = 0b000;
36034let Inst{13-13} = 0b0;
36035let Inst{31-21} = 0b00011111110;
36036let hasNewValue = 1;
36037let opNewValue = 0;
36038let isCVI = 1;
36039let DecoderNamespace = "EXT_mmvec";
36040}
36041def V6_vmpyiewuh_acc : HInst<
36042(outs HvxVR:$Vx32),
36043(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36044"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
36045tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36046let Inst{7-5} = 0b101;
36047let Inst{13-13} = 0b1;
36048let Inst{31-21} = 0b00011100001;
36049let hasNewValue = 1;
36050let opNewValue = 0;
36051let isAccumulator = 1;
36052let isCVI = 1;
36053let DecoderNamespace = "EXT_mmvec";
36054let Constraints = "$Vx32 = $Vx32in";
36055}
36056def V6_vmpyiewuh_acc_alt : HInst<
36057(outs HvxVR:$Vx32),
36058(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36059"$Vx32 += vmpyiewuh($Vu32,$Vv32)",
36060PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36061let hasNewValue = 1;
36062let opNewValue = 0;
36063let isAccumulator = 1;
36064let isCVI = 1;
36065let isPseudo = 1;
36066let isCodeGenOnly = 1;
36067let DecoderNamespace = "EXT_mmvec";
36068let Constraints = "$Vx32 = $Vx32in";
36069}
36070def V6_vmpyiewuh_alt : HInst<
36071(outs HvxVR:$Vd32),
36072(ins HvxVR:$Vu32, HvxVR:$Vv32),
36073"$Vd32 = vmpyiewuh($Vu32,$Vv32)",
36074PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36075let hasNewValue = 1;
36076let opNewValue = 0;
36077let isCVI = 1;
36078let isPseudo = 1;
36079let isCodeGenOnly = 1;
36080let DecoderNamespace = "EXT_mmvec";
36081}
36082def V6_vmpyih : HInst<
36083(outs HvxVR:$Vd32),
36084(ins HvxVR:$Vu32, HvxVR:$Vv32),
36085"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
36086tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36087let Inst{7-5} = 0b100;
36088let Inst{13-13} = 0b0;
36089let Inst{31-21} = 0b00011100001;
36090let hasNewValue = 1;
36091let opNewValue = 0;
36092let isCVI = 1;
36093let DecoderNamespace = "EXT_mmvec";
36094}
36095def V6_vmpyih_acc : HInst<
36096(outs HvxVR:$Vx32),
36097(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36098"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
36099tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36100let Inst{7-5} = 0b100;
36101let Inst{13-13} = 0b1;
36102let Inst{31-21} = 0b00011100001;
36103let hasNewValue = 1;
36104let opNewValue = 0;
36105let isAccumulator = 1;
36106let isCVI = 1;
36107let DecoderNamespace = "EXT_mmvec";
36108let Constraints = "$Vx32 = $Vx32in";
36109}
36110def V6_vmpyih_acc_alt : HInst<
36111(outs HvxVR:$Vx32),
36112(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36113"$Vx32 += vmpyih($Vu32,$Vv32)",
36114PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36115let hasNewValue = 1;
36116let opNewValue = 0;
36117let isAccumulator = 1;
36118let isCVI = 1;
36119let isPseudo = 1;
36120let isCodeGenOnly = 1;
36121let DecoderNamespace = "EXT_mmvec";
36122let Constraints = "$Vx32 = $Vx32in";
36123}
36124def V6_vmpyih_alt : HInst<
36125(outs HvxVR:$Vd32),
36126(ins HvxVR:$Vu32, HvxVR:$Vv32),
36127"$Vd32 = vmpyih($Vu32,$Vv32)",
36128PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36129let hasNewValue = 1;
36130let opNewValue = 0;
36131let isCVI = 1;
36132let isPseudo = 1;
36133let isCodeGenOnly = 1;
36134let DecoderNamespace = "EXT_mmvec";
36135}
36136def V6_vmpyihb : HInst<
36137(outs HvxVR:$Vd32),
36138(ins HvxVR:$Vu32, IntRegs:$Rt32),
36139"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
36140tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
36141let Inst{7-5} = 0b000;
36142let Inst{13-13} = 0b0;
36143let Inst{31-21} = 0b00011001011;
36144let hasNewValue = 1;
36145let opNewValue = 0;
36146let isCVI = 1;
36147let DecoderNamespace = "EXT_mmvec";
36148}
36149def V6_vmpyihb_acc : HInst<
36150(outs HvxVR:$Vx32),
36151(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36152"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
36153tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
36154let Inst{7-5} = 0b001;
36155let Inst{13-13} = 0b1;
36156let Inst{31-21} = 0b00011001011;
36157let hasNewValue = 1;
36158let opNewValue = 0;
36159let isAccumulator = 1;
36160let isCVI = 1;
36161let DecoderNamespace = "EXT_mmvec";
36162let Constraints = "$Vx32 = $Vx32in";
36163}
36164def V6_vmpyihb_acc_alt : HInst<
36165(outs HvxVR:$Vx32),
36166(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36167"$Vx32 += vmpyihb($Vu32,$Rt32)",
36168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36169let hasNewValue = 1;
36170let opNewValue = 0;
36171let isAccumulator = 1;
36172let isCVI = 1;
36173let isPseudo = 1;
36174let isCodeGenOnly = 1;
36175let DecoderNamespace = "EXT_mmvec";
36176let Constraints = "$Vx32 = $Vx32in";
36177}
36178def V6_vmpyihb_alt : HInst<
36179(outs HvxVR:$Vd32),
36180(ins HvxVR:$Vu32, IntRegs:$Rt32),
36181"$Vd32 = vmpyihb($Vu32,$Rt32)",
36182PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36183let hasNewValue = 1;
36184let opNewValue = 0;
36185let isCVI = 1;
36186let isPseudo = 1;
36187let isCodeGenOnly = 1;
36188let DecoderNamespace = "EXT_mmvec";
36189}
36190def V6_vmpyiowh : HInst<
36191(outs HvxVR:$Vd32),
36192(ins HvxVR:$Vu32, HvxVR:$Vv32),
36193"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
36194tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36195let Inst{7-5} = 0b001;
36196let Inst{13-13} = 0b0;
36197let Inst{31-21} = 0b00011111110;
36198let hasNewValue = 1;
36199let opNewValue = 0;
36200let isCVI = 1;
36201let DecoderNamespace = "EXT_mmvec";
36202}
36203def V6_vmpyiowh_alt : HInst<
36204(outs HvxVR:$Vd32),
36205(ins HvxVR:$Vu32, HvxVR:$Vv32),
36206"$Vd32 = vmpyiowh($Vu32,$Vv32)",
36207PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36208let hasNewValue = 1;
36209let opNewValue = 0;
36210let isCVI = 1;
36211let isPseudo = 1;
36212let isCodeGenOnly = 1;
36213let DecoderNamespace = "EXT_mmvec";
36214}
36215def V6_vmpyiwb : HInst<
36216(outs HvxVR:$Vd32),
36217(ins HvxVR:$Vu32, IntRegs:$Rt32),
36218"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
36219tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
36220let Inst{7-5} = 0b000;
36221let Inst{13-13} = 0b0;
36222let Inst{31-21} = 0b00011001101;
36223let hasNewValue = 1;
36224let opNewValue = 0;
36225let isCVI = 1;
36226let DecoderNamespace = "EXT_mmvec";
36227}
36228def V6_vmpyiwb_acc : HInst<
36229(outs HvxVR:$Vx32),
36230(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36231"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
36232tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
36233let Inst{7-5} = 0b010;
36234let Inst{13-13} = 0b1;
36235let Inst{31-21} = 0b00011001010;
36236let hasNewValue = 1;
36237let opNewValue = 0;
36238let isAccumulator = 1;
36239let isCVI = 1;
36240let DecoderNamespace = "EXT_mmvec";
36241let Constraints = "$Vx32 = $Vx32in";
36242}
36243def V6_vmpyiwb_acc_alt : HInst<
36244(outs HvxVR:$Vx32),
36245(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36246"$Vx32 += vmpyiwb($Vu32,$Rt32)",
36247PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36248let hasNewValue = 1;
36249let opNewValue = 0;
36250let isAccumulator = 1;
36251let isCVI = 1;
36252let isPseudo = 1;
36253let isCodeGenOnly = 1;
36254let DecoderNamespace = "EXT_mmvec";
36255let Constraints = "$Vx32 = $Vx32in";
36256}
36257def V6_vmpyiwb_alt : HInst<
36258(outs HvxVR:$Vd32),
36259(ins HvxVR:$Vu32, IntRegs:$Rt32),
36260"$Vd32 = vmpyiwb($Vu32,$Rt32)",
36261PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36262let hasNewValue = 1;
36263let opNewValue = 0;
36264let isCVI = 1;
36265let isPseudo = 1;
36266let isCodeGenOnly = 1;
36267let DecoderNamespace = "EXT_mmvec";
36268}
36269def V6_vmpyiwh : HInst<
36270(outs HvxVR:$Vd32),
36271(ins HvxVR:$Vu32, IntRegs:$Rt32),
36272"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
36273tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
36274let Inst{7-5} = 0b111;
36275let Inst{13-13} = 0b0;
36276let Inst{31-21} = 0b00011001100;
36277let hasNewValue = 1;
36278let opNewValue = 0;
36279let isCVI = 1;
36280let DecoderNamespace = "EXT_mmvec";
36281}
36282def V6_vmpyiwh_acc : HInst<
36283(outs HvxVR:$Vx32),
36284(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36285"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
36286tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
36287let Inst{7-5} = 0b011;
36288let Inst{13-13} = 0b1;
36289let Inst{31-21} = 0b00011001010;
36290let hasNewValue = 1;
36291let opNewValue = 0;
36292let isAccumulator = 1;
36293let isCVI = 1;
36294let DecoderNamespace = "EXT_mmvec";
36295let Constraints = "$Vx32 = $Vx32in";
36296}
36297def V6_vmpyiwh_acc_alt : HInst<
36298(outs HvxVR:$Vx32),
36299(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36300"$Vx32 += vmpyiwh($Vu32,$Rt32)",
36301PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36302let hasNewValue = 1;
36303let opNewValue = 0;
36304let isAccumulator = 1;
36305let isCVI = 1;
36306let isPseudo = 1;
36307let isCodeGenOnly = 1;
36308let DecoderNamespace = "EXT_mmvec";
36309let Constraints = "$Vx32 = $Vx32in";
36310}
36311def V6_vmpyiwh_alt : HInst<
36312(outs HvxVR:$Vd32),
36313(ins HvxVR:$Vu32, IntRegs:$Rt32),
36314"$Vd32 = vmpyiwh($Vu32,$Rt32)",
36315PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36316let hasNewValue = 1;
36317let opNewValue = 0;
36318let isCVI = 1;
36319let isPseudo = 1;
36320let isCodeGenOnly = 1;
36321let DecoderNamespace = "EXT_mmvec";
36322}
36323def V6_vmpyiwub : HInst<
36324(outs HvxVR:$Vd32),
36325(ins HvxVR:$Vu32, IntRegs:$Rt32),
36326"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
36327tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
36328let Inst{7-5} = 0b110;
36329let Inst{13-13} = 0b0;
36330let Inst{31-21} = 0b00011001100;
36331let hasNewValue = 1;
36332let opNewValue = 0;
36333let isCVI = 1;
36334let DecoderNamespace = "EXT_mmvec";
36335}
36336def V6_vmpyiwub_acc : HInst<
36337(outs HvxVR:$Vx32),
36338(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36339"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
36340tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
36341let Inst{7-5} = 0b001;
36342let Inst{13-13} = 0b1;
36343let Inst{31-21} = 0b00011001100;
36344let hasNewValue = 1;
36345let opNewValue = 0;
36346let isAccumulator = 1;
36347let isCVI = 1;
36348let DecoderNamespace = "EXT_mmvec";
36349let Constraints = "$Vx32 = $Vx32in";
36350}
36351def V6_vmpyiwub_acc_alt : HInst<
36352(outs HvxVR:$Vx32),
36353(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36354"$Vx32 += vmpyiwub($Vu32,$Rt32)",
36355PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36356let hasNewValue = 1;
36357let opNewValue = 0;
36358let isAccumulator = 1;
36359let isCVI = 1;
36360let isPseudo = 1;
36361let isCodeGenOnly = 1;
36362let DecoderNamespace = "EXT_mmvec";
36363let Constraints = "$Vx32 = $Vx32in";
36364}
36365def V6_vmpyiwub_alt : HInst<
36366(outs HvxVR:$Vd32),
36367(ins HvxVR:$Vu32, IntRegs:$Rt32),
36368"$Vd32 = vmpyiwub($Vu32,$Rt32)",
36369PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36370let hasNewValue = 1;
36371let opNewValue = 0;
36372let isCVI = 1;
36373let isPseudo = 1;
36374let isCodeGenOnly = 1;
36375let DecoderNamespace = "EXT_mmvec";
36376}
36377def V6_vmpyowh : HInst<
36378(outs HvxVR:$Vd32),
36379(ins HvxVR:$Vu32, HvxVR:$Vv32),
36380"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
36381tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36382let Inst{7-5} = 0b111;
36383let Inst{13-13} = 0b0;
36384let Inst{31-21} = 0b00011111111;
36385let hasNewValue = 1;
36386let opNewValue = 0;
36387let isCVI = 1;
36388let DecoderNamespace = "EXT_mmvec";
36389}
36390def V6_vmpyowh_64_acc : HInst<
36391(outs HvxWR:$Vxx32),
36392(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36393"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
36394tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
36395let Inst{7-5} = 0b011;
36396let Inst{13-13} = 0b1;
36397let Inst{31-21} = 0b00011100001;
36398let hasNewValue = 1;
36399let opNewValue = 0;
36400let isAccumulator = 1;
36401let isCVI = 1;
36402let DecoderNamespace = "EXT_mmvec";
36403let Constraints = "$Vxx32 = $Vxx32in";
36404}
36405def V6_vmpyowh_alt : HInst<
36406(outs HvxVR:$Vd32),
36407(ins HvxVR:$Vu32, HvxVR:$Vv32),
36408"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
36409PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36410let hasNewValue = 1;
36411let opNewValue = 0;
36412let isCVI = 1;
36413let isPseudo = 1;
36414let isCodeGenOnly = 1;
36415let DecoderNamespace = "EXT_mmvec";
36416}
36417def V6_vmpyowh_rnd : HInst<
36418(outs HvxVR:$Vd32),
36419(ins HvxVR:$Vu32, HvxVR:$Vv32),
36420"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
36421tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
36422let Inst{7-5} = 0b000;
36423let Inst{13-13} = 0b0;
36424let Inst{31-21} = 0b00011111010;
36425let hasNewValue = 1;
36426let opNewValue = 0;
36427let isCVI = 1;
36428let DecoderNamespace = "EXT_mmvec";
36429}
36430def V6_vmpyowh_rnd_alt : HInst<
36431(outs HvxVR:$Vd32),
36432(ins HvxVR:$Vu32, HvxVR:$Vv32),
36433"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
36434PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36435let hasNewValue = 1;
36436let opNewValue = 0;
36437let isCVI = 1;
36438let isPseudo = 1;
36439let isCodeGenOnly = 1;
36440let DecoderNamespace = "EXT_mmvec";
36441}
36442def V6_vmpyowh_rnd_sacc : HInst<
36443(outs HvxVR:$Vx32),
36444(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36445"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
36446tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36447let Inst{7-5} = 0b111;
36448let Inst{13-13} = 0b1;
36449let Inst{31-21} = 0b00011100001;
36450let hasNewValue = 1;
36451let opNewValue = 0;
36452let isAccumulator = 1;
36453let isCVI = 1;
36454let DecoderNamespace = "EXT_mmvec";
36455let Constraints = "$Vx32 = $Vx32in";
36456}
36457def V6_vmpyowh_rnd_sacc_alt : HInst<
36458(outs HvxVR:$Vx32),
36459(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36460"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
36461PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36462let hasNewValue = 1;
36463let opNewValue = 0;
36464let isAccumulator = 1;
36465let isCVI = 1;
36466let isPseudo = 1;
36467let DecoderNamespace = "EXT_mmvec";
36468let Constraints = "$Vx32 = $Vx32in";
36469}
36470def V6_vmpyowh_sacc : HInst<
36471(outs HvxVR:$Vx32),
36472(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36473"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
36474tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36475let Inst{7-5} = 0b110;
36476let Inst{13-13} = 0b1;
36477let Inst{31-21} = 0b00011100001;
36478let hasNewValue = 1;
36479let opNewValue = 0;
36480let isAccumulator = 1;
36481let isCVI = 1;
36482let DecoderNamespace = "EXT_mmvec";
36483let Constraints = "$Vx32 = $Vx32in";
36484}
36485def V6_vmpyowh_sacc_alt : HInst<
36486(outs HvxVR:$Vx32),
36487(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36488"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
36489PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36490let hasNewValue = 1;
36491let opNewValue = 0;
36492let isAccumulator = 1;
36493let isCVI = 1;
36494let isPseudo = 1;
36495let DecoderNamespace = "EXT_mmvec";
36496let Constraints = "$Vx32 = $Vx32in";
36497}
36498def V6_vmpyub : HInst<
36499(outs HvxWR:$Vdd32),
36500(ins HvxVR:$Vu32, IntRegs:$Rt32),
36501"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
36502tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
36503let Inst{7-5} = 0b000;
36504let Inst{13-13} = 0b0;
36505let Inst{31-21} = 0b00011001110;
36506let hasNewValue = 1;
36507let opNewValue = 0;
36508let isCVI = 1;
36509let DecoderNamespace = "EXT_mmvec";
36510}
36511def V6_vmpyub_acc : HInst<
36512(outs HvxWR:$Vxx32),
36513(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36514"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
36515tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
36516let Inst{7-5} = 0b000;
36517let Inst{13-13} = 0b1;
36518let Inst{31-21} = 0b00011001100;
36519let hasNewValue = 1;
36520let opNewValue = 0;
36521let isAccumulator = 1;
36522let isCVI = 1;
36523let DecoderNamespace = "EXT_mmvec";
36524let Constraints = "$Vxx32 = $Vxx32in";
36525}
36526def V6_vmpyub_acc_alt : HInst<
36527(outs HvxWR:$Vxx32),
36528(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36529"$Vxx32 += vmpyub($Vu32,$Rt32)",
36530PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36531let hasNewValue = 1;
36532let opNewValue = 0;
36533let isAccumulator = 1;
36534let isCVI = 1;
36535let isPseudo = 1;
36536let isCodeGenOnly = 1;
36537let DecoderNamespace = "EXT_mmvec";
36538let Constraints = "$Vxx32 = $Vxx32in";
36539}
36540def V6_vmpyub_alt : HInst<
36541(outs HvxWR:$Vdd32),
36542(ins HvxVR:$Vu32, IntRegs:$Rt32),
36543"$Vdd32 = vmpyub($Vu32,$Rt32)",
36544PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36545let hasNewValue = 1;
36546let opNewValue = 0;
36547let isCVI = 1;
36548let isPseudo = 1;
36549let isCodeGenOnly = 1;
36550let DecoderNamespace = "EXT_mmvec";
36551}
36552def V6_vmpyubv : HInst<
36553(outs HvxWR:$Vdd32),
36554(ins HvxVR:$Vu32, HvxVR:$Vv32),
36555"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
36556tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36557let Inst{7-5} = 0b101;
36558let Inst{13-13} = 0b0;
36559let Inst{31-21} = 0b00011100000;
36560let hasNewValue = 1;
36561let opNewValue = 0;
36562let isCVI = 1;
36563let DecoderNamespace = "EXT_mmvec";
36564}
36565def V6_vmpyubv_acc : HInst<
36566(outs HvxWR:$Vxx32),
36567(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36568"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
36569tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
36570let Inst{7-5} = 0b101;
36571let Inst{13-13} = 0b1;
36572let Inst{31-21} = 0b00011100000;
36573let hasNewValue = 1;
36574let opNewValue = 0;
36575let isAccumulator = 1;
36576let isCVI = 1;
36577let DecoderNamespace = "EXT_mmvec";
36578let Constraints = "$Vxx32 = $Vxx32in";
36579}
36580def V6_vmpyubv_acc_alt : HInst<
36581(outs HvxWR:$Vxx32),
36582(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36583"$Vxx32 += vmpyub($Vu32,$Vv32)",
36584PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36585let hasNewValue = 1;
36586let opNewValue = 0;
36587let isAccumulator = 1;
36588let isCVI = 1;
36589let isPseudo = 1;
36590let isCodeGenOnly = 1;
36591let DecoderNamespace = "EXT_mmvec";
36592let Constraints = "$Vxx32 = $Vxx32in";
36593}
36594def V6_vmpyubv_alt : HInst<
36595(outs HvxWR:$Vdd32),
36596(ins HvxVR:$Vu32, HvxVR:$Vv32),
36597"$Vdd32 = vmpyub($Vu32,$Vv32)",
36598PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36599let hasNewValue = 1;
36600let opNewValue = 0;
36601let isCVI = 1;
36602let isPseudo = 1;
36603let isCodeGenOnly = 1;
36604let DecoderNamespace = "EXT_mmvec";
36605}
36606def V6_vmpyuh : HInst<
36607(outs HvxWR:$Vdd32),
36608(ins HvxVR:$Vu32, IntRegs:$Rt32),
36609"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
36610tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
36611let Inst{7-5} = 0b011;
36612let Inst{13-13} = 0b0;
36613let Inst{31-21} = 0b00011001010;
36614let hasNewValue = 1;
36615let opNewValue = 0;
36616let isCVI = 1;
36617let DecoderNamespace = "EXT_mmvec";
36618}
36619def V6_vmpyuh_acc : HInst<
36620(outs HvxWR:$Vxx32),
36621(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36622"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
36623tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
36624let Inst{7-5} = 0b001;
36625let Inst{13-13} = 0b1;
36626let Inst{31-21} = 0b00011001010;
36627let hasNewValue = 1;
36628let opNewValue = 0;
36629let isAccumulator = 1;
36630let isCVI = 1;
36631let DecoderNamespace = "EXT_mmvec";
36632let Constraints = "$Vxx32 = $Vxx32in";
36633}
36634def V6_vmpyuh_acc_alt : HInst<
36635(outs HvxWR:$Vxx32),
36636(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36637"$Vxx32 += vmpyuh($Vu32,$Rt32)",
36638PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36639let hasNewValue = 1;
36640let opNewValue = 0;
36641let isAccumulator = 1;
36642let isCVI = 1;
36643let isPseudo = 1;
36644let isCodeGenOnly = 1;
36645let DecoderNamespace = "EXT_mmvec";
36646let Constraints = "$Vxx32 = $Vxx32in";
36647}
36648def V6_vmpyuh_alt : HInst<
36649(outs HvxWR:$Vdd32),
36650(ins HvxVR:$Vu32, IntRegs:$Rt32),
36651"$Vdd32 = vmpyuh($Vu32,$Rt32)",
36652PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36653let hasNewValue = 1;
36654let opNewValue = 0;
36655let isCVI = 1;
36656let isPseudo = 1;
36657let isCodeGenOnly = 1;
36658let DecoderNamespace = "EXT_mmvec";
36659}
36660def V6_vmpyuhe : HInst<
36661(outs HvxVR:$Vd32),
36662(ins HvxVR:$Vu32, IntRegs:$Rt32),
36663"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
36664tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
36665let Inst{7-5} = 0b010;
36666let Inst{13-13} = 0b0;
36667let Inst{31-21} = 0b00011001011;
36668let hasNewValue = 1;
36669let opNewValue = 0;
36670let isCVI = 1;
36671let DecoderNamespace = "EXT_mmvec";
36672}
36673def V6_vmpyuhe_acc : HInst<
36674(outs HvxVR:$Vx32),
36675(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36676"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
36677tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
36678let Inst{7-5} = 0b011;
36679let Inst{13-13} = 0b1;
36680let Inst{31-21} = 0b00011001100;
36681let hasNewValue = 1;
36682let opNewValue = 0;
36683let isAccumulator = 1;
36684let isCVI = 1;
36685let DecoderNamespace = "EXT_mmvec";
36686let Constraints = "$Vx32 = $Vx32in";
36687}
36688def V6_vmpyuhv : HInst<
36689(outs HvxWR:$Vdd32),
36690(ins HvxVR:$Vu32, HvxVR:$Vv32),
36691"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
36692tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
36693let Inst{7-5} = 0b000;
36694let Inst{13-13} = 0b0;
36695let Inst{31-21} = 0b00011100001;
36696let hasNewValue = 1;
36697let opNewValue = 0;
36698let isCVI = 1;
36699let DecoderNamespace = "EXT_mmvec";
36700}
36701def V6_vmpyuhv_acc : HInst<
36702(outs HvxWR:$Vxx32),
36703(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36704"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
36705tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
36706let Inst{7-5} = 0b000;
36707let Inst{13-13} = 0b1;
36708let Inst{31-21} = 0b00011100001;
36709let hasNewValue = 1;
36710let opNewValue = 0;
36711let isAccumulator = 1;
36712let isCVI = 1;
36713let DecoderNamespace = "EXT_mmvec";
36714let Constraints = "$Vxx32 = $Vxx32in";
36715}
36716def V6_vmpyuhv_acc_alt : HInst<
36717(outs HvxWR:$Vxx32),
36718(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36719"$Vxx32 += vmpyuh($Vu32,$Vv32)",
36720PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36721let hasNewValue = 1;
36722let opNewValue = 0;
36723let isAccumulator = 1;
36724let isCVI = 1;
36725let isPseudo = 1;
36726let isCodeGenOnly = 1;
36727let DecoderNamespace = "EXT_mmvec";
36728let Constraints = "$Vxx32 = $Vxx32in";
36729}
36730def V6_vmpyuhv_alt : HInst<
36731(outs HvxWR:$Vdd32),
36732(ins HvxVR:$Vu32, HvxVR:$Vv32),
36733"$Vdd32 = vmpyuh($Vu32,$Vv32)",
36734PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36735let hasNewValue = 1;
36736let opNewValue = 0;
36737let isCVI = 1;
36738let isPseudo = 1;
36739let isCodeGenOnly = 1;
36740let DecoderNamespace = "EXT_mmvec";
36741}
36742def V6_vmpyuhvs : HInst<
36743(outs HvxVR:$Vd32),
36744(ins HvxVR:$Vu32, HvxVR:$Vv32),
36745"$Vd32.uh = vmpy($Vu32.uh,$Vv32.uh):>>16",
36746tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV69]> {
36747let Inst{7-5} = 0b111;
36748let Inst{13-13} = 0b1;
36749let Inst{31-21} = 0b00011111110;
36750let hasNewValue = 1;
36751let opNewValue = 0;
36752let isCVI = 1;
36753let DecoderNamespace = "EXT_mmvec";
36754}
36755def V6_vmux : HInst<
36756(outs HvxVR:$Vd32),
36757(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
36758"$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
36759tc_257f6f7c, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
36760let Inst{7-7} = 0b0;
36761let Inst{13-13} = 0b1;
36762let Inst{31-21} = 0b00011110111;
36763let hasNewValue = 1;
36764let opNewValue = 0;
36765let isCVI = 1;
36766let isHVXALU = 1;
36767let isHVXALU2SRC = 1;
36768let DecoderNamespace = "EXT_mmvec";
36769}
36770def V6_vnavgb : HInst<
36771(outs HvxVR:$Vd32),
36772(ins HvxVR:$Vu32, HvxVR:$Vv32),
36773"$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
36774tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
36775let Inst{7-5} = 0b110;
36776let Inst{13-13} = 0b1;
36777let Inst{31-21} = 0b00011111000;
36778let hasNewValue = 1;
36779let opNewValue = 0;
36780let isCVI = 1;
36781let isHVXALU = 1;
36782let isHVXALU2SRC = 1;
36783let DecoderNamespace = "EXT_mmvec";
36784}
36785def V6_vnavgb_alt : HInst<
36786(outs HvxVR:$Vd32),
36787(ins HvxVR:$Vu32, HvxVR:$Vv32),
36788"$Vd32 = vnavgb($Vu32,$Vv32)",
36789PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36790let hasNewValue = 1;
36791let opNewValue = 0;
36792let isCVI = 1;
36793let isPseudo = 1;
36794let isCodeGenOnly = 1;
36795let DecoderNamespace = "EXT_mmvec";
36796}
36797def V6_vnavgh : HInst<
36798(outs HvxVR:$Vd32),
36799(ins HvxVR:$Vu32, HvxVR:$Vv32),
36800"$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
36801tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36802let Inst{7-5} = 0b001;
36803let Inst{13-13} = 0b0;
36804let Inst{31-21} = 0b00011100111;
36805let hasNewValue = 1;
36806let opNewValue = 0;
36807let isCVI = 1;
36808let isHVXALU = 1;
36809let isHVXALU2SRC = 1;
36810let DecoderNamespace = "EXT_mmvec";
36811}
36812def V6_vnavgh_alt : HInst<
36813(outs HvxVR:$Vd32),
36814(ins HvxVR:$Vu32, HvxVR:$Vv32),
36815"$Vd32 = vnavgh($Vu32,$Vv32)",
36816PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36817let hasNewValue = 1;
36818let opNewValue = 0;
36819let isCVI = 1;
36820let isPseudo = 1;
36821let isCodeGenOnly = 1;
36822let DecoderNamespace = "EXT_mmvec";
36823}
36824def V6_vnavgub : HInst<
36825(outs HvxVR:$Vd32),
36826(ins HvxVR:$Vu32, HvxVR:$Vv32),
36827"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
36828tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36829let Inst{7-5} = 0b000;
36830let Inst{13-13} = 0b0;
36831let Inst{31-21} = 0b00011100111;
36832let hasNewValue = 1;
36833let opNewValue = 0;
36834let isCVI = 1;
36835let isHVXALU = 1;
36836let isHVXALU2SRC = 1;
36837let DecoderNamespace = "EXT_mmvec";
36838}
36839def V6_vnavgub_alt : HInst<
36840(outs HvxVR:$Vd32),
36841(ins HvxVR:$Vu32, HvxVR:$Vv32),
36842"$Vd32 = vnavgub($Vu32,$Vv32)",
36843PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36844let hasNewValue = 1;
36845let opNewValue = 0;
36846let isCVI = 1;
36847let isPseudo = 1;
36848let isCodeGenOnly = 1;
36849let DecoderNamespace = "EXT_mmvec";
36850}
36851def V6_vnavgw : HInst<
36852(outs HvxVR:$Vd32),
36853(ins HvxVR:$Vu32, HvxVR:$Vv32),
36854"$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
36855tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36856let Inst{7-5} = 0b010;
36857let Inst{13-13} = 0b0;
36858let Inst{31-21} = 0b00011100111;
36859let hasNewValue = 1;
36860let opNewValue = 0;
36861let isCVI = 1;
36862let isHVXALU = 1;
36863let isHVXALU2SRC = 1;
36864let DecoderNamespace = "EXT_mmvec";
36865}
36866def V6_vnavgw_alt : HInst<
36867(outs HvxVR:$Vd32),
36868(ins HvxVR:$Vu32, HvxVR:$Vv32),
36869"$Vd32 = vnavgw($Vu32,$Vv32)",
36870PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36871let hasNewValue = 1;
36872let opNewValue = 0;
36873let isCVI = 1;
36874let isPseudo = 1;
36875let isCodeGenOnly = 1;
36876let DecoderNamespace = "EXT_mmvec";
36877}
36878def V6_vnccombine : HInst<
36879(outs HvxWR:$Vdd32),
36880(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
36881"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
36882tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
36883let Inst{7-7} = 0b0;
36884let Inst{13-13} = 0b0;
36885let Inst{31-21} = 0b00011010010;
36886let isPredicated = 1;
36887let isPredicatedFalse = 1;
36888let hasNewValue = 1;
36889let opNewValue = 0;
36890let isCVI = 1;
36891let DecoderNamespace = "EXT_mmvec";
36892}
36893def V6_vncmov : HInst<
36894(outs HvxVR:$Vd32),
36895(ins PredRegs:$Ps4, HvxVR:$Vu32),
36896"if (!$Ps4) $Vd32 = $Vu32",
36897tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
36898let Inst{7-7} = 0b0;
36899let Inst{13-13} = 0b0;
36900let Inst{31-16} = 0b0001101000100000;
36901let isPredicated = 1;
36902let isPredicatedFalse = 1;
36903let hasNewValue = 1;
36904let opNewValue = 0;
36905let isCVI = 1;
36906let isHVXALU = 1;
36907let DecoderNamespace = "EXT_mmvec";
36908}
36909def V6_vnormamth : HInst<
36910(outs HvxVR:$Vd32),
36911(ins HvxVR:$Vu32),
36912"$Vd32.h = vnormamt($Vu32.h)",
36913tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
36914let Inst{7-5} = 0b101;
36915let Inst{13-13} = 0b0;
36916let Inst{31-16} = 0b0001111000000011;
36917let hasNewValue = 1;
36918let opNewValue = 0;
36919let isCVI = 1;
36920let DecoderNamespace = "EXT_mmvec";
36921}
36922def V6_vnormamth_alt : HInst<
36923(outs HvxVR:$Vd32),
36924(ins HvxVR:$Vu32),
36925"$Vd32 = vnormamth($Vu32)",
36926PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36927let hasNewValue = 1;
36928let opNewValue = 0;
36929let isCVI = 1;
36930let isPseudo = 1;
36931let isCodeGenOnly = 1;
36932let DecoderNamespace = "EXT_mmvec";
36933}
36934def V6_vnormamtw : HInst<
36935(outs HvxVR:$Vd32),
36936(ins HvxVR:$Vu32),
36937"$Vd32.w = vnormamt($Vu32.w)",
36938tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
36939let Inst{7-5} = 0b100;
36940let Inst{13-13} = 0b0;
36941let Inst{31-16} = 0b0001111000000011;
36942let hasNewValue = 1;
36943let opNewValue = 0;
36944let isCVI = 1;
36945let DecoderNamespace = "EXT_mmvec";
36946}
36947def V6_vnormamtw_alt : HInst<
36948(outs HvxVR:$Vd32),
36949(ins HvxVR:$Vu32),
36950"$Vd32 = vnormamtw($Vu32)",
36951PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36952let hasNewValue = 1;
36953let opNewValue = 0;
36954let isCVI = 1;
36955let isPseudo = 1;
36956let isCodeGenOnly = 1;
36957let DecoderNamespace = "EXT_mmvec";
36958}
36959def V6_vnot : HInst<
36960(outs HvxVR:$Vd32),
36961(ins HvxVR:$Vu32),
36962"$Vd32 = vnot($Vu32)",
36963tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
36964let Inst{7-5} = 0b100;
36965let Inst{13-13} = 0b0;
36966let Inst{31-16} = 0b0001111000000000;
36967let hasNewValue = 1;
36968let opNewValue = 0;
36969let isCVI = 1;
36970let isHVXALU = 1;
36971let isHVXALU2SRC = 1;
36972let DecoderNamespace = "EXT_mmvec";
36973}
36974def V6_vor : HInst<
36975(outs HvxVR:$Vd32),
36976(ins HvxVR:$Vu32, HvxVR:$Vv32),
36977"$Vd32 = vor($Vu32,$Vv32)",
36978tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36979let Inst{7-5} = 0b110;
36980let Inst{13-13} = 0b0;
36981let Inst{31-21} = 0b00011100001;
36982let hasNewValue = 1;
36983let opNewValue = 0;
36984let isCVI = 1;
36985let isHVXALU = 1;
36986let isHVXALU2SRC = 1;
36987let DecoderNamespace = "EXT_mmvec";
36988}
36989def V6_vpackeb : HInst<
36990(outs HvxVR:$Vd32),
36991(ins HvxVR:$Vu32, HvxVR:$Vv32),
36992"$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
36993tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
36994let Inst{7-5} = 0b010;
36995let Inst{13-13} = 0b0;
36996let Inst{31-21} = 0b00011111110;
36997let hasNewValue = 1;
36998let opNewValue = 0;
36999let isCVI = 1;
37000let DecoderNamespace = "EXT_mmvec";
37001}
37002def V6_vpackeb_alt : HInst<
37003(outs HvxVR:$Vd32),
37004(ins HvxVR:$Vu32, HvxVR:$Vv32),
37005"$Vd32 = vpackeb($Vu32,$Vv32)",
37006PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37007let hasNewValue = 1;
37008let opNewValue = 0;
37009let isCVI = 1;
37010let isPseudo = 1;
37011let isCodeGenOnly = 1;
37012let DecoderNamespace = "EXT_mmvec";
37013}
37014def V6_vpackeh : HInst<
37015(outs HvxVR:$Vd32),
37016(ins HvxVR:$Vu32, HvxVR:$Vv32),
37017"$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
37018tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37019let Inst{7-5} = 0b011;
37020let Inst{13-13} = 0b0;
37021let Inst{31-21} = 0b00011111110;
37022let hasNewValue = 1;
37023let opNewValue = 0;
37024let isCVI = 1;
37025let DecoderNamespace = "EXT_mmvec";
37026}
37027def V6_vpackeh_alt : HInst<
37028(outs HvxVR:$Vd32),
37029(ins HvxVR:$Vu32, HvxVR:$Vv32),
37030"$Vd32 = vpackeh($Vu32,$Vv32)",
37031PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37032let hasNewValue = 1;
37033let opNewValue = 0;
37034let isCVI = 1;
37035let isPseudo = 1;
37036let isCodeGenOnly = 1;
37037let DecoderNamespace = "EXT_mmvec";
37038}
37039def V6_vpackhb_sat : HInst<
37040(outs HvxVR:$Vd32),
37041(ins HvxVR:$Vu32, HvxVR:$Vv32),
37042"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
37043tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37044let Inst{7-5} = 0b110;
37045let Inst{13-13} = 0b0;
37046let Inst{31-21} = 0b00011111110;
37047let hasNewValue = 1;
37048let opNewValue = 0;
37049let isCVI = 1;
37050let DecoderNamespace = "EXT_mmvec";
37051}
37052def V6_vpackhb_sat_alt : HInst<
37053(outs HvxVR:$Vd32),
37054(ins HvxVR:$Vu32, HvxVR:$Vv32),
37055"$Vd32 = vpackhb($Vu32,$Vv32):sat",
37056PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37057let hasNewValue = 1;
37058let opNewValue = 0;
37059let isCVI = 1;
37060let isPseudo = 1;
37061let isCodeGenOnly = 1;
37062let DecoderNamespace = "EXT_mmvec";
37063}
37064def V6_vpackhub_sat : HInst<
37065(outs HvxVR:$Vd32),
37066(ins HvxVR:$Vu32, HvxVR:$Vv32),
37067"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
37068tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37069let Inst{7-5} = 0b101;
37070let Inst{13-13} = 0b0;
37071let Inst{31-21} = 0b00011111110;
37072let hasNewValue = 1;
37073let opNewValue = 0;
37074let isCVI = 1;
37075let DecoderNamespace = "EXT_mmvec";
37076}
37077def V6_vpackhub_sat_alt : HInst<
37078(outs HvxVR:$Vd32),
37079(ins HvxVR:$Vu32, HvxVR:$Vv32),
37080"$Vd32 = vpackhub($Vu32,$Vv32):sat",
37081PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37082let hasNewValue = 1;
37083let opNewValue = 0;
37084let isCVI = 1;
37085let isPseudo = 1;
37086let isCodeGenOnly = 1;
37087let DecoderNamespace = "EXT_mmvec";
37088}
37089def V6_vpackob : HInst<
37090(outs HvxVR:$Vd32),
37091(ins HvxVR:$Vu32, HvxVR:$Vv32),
37092"$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
37093tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37094let Inst{7-5} = 0b001;
37095let Inst{13-13} = 0b0;
37096let Inst{31-21} = 0b00011111111;
37097let hasNewValue = 1;
37098let opNewValue = 0;
37099let isCVI = 1;
37100let DecoderNamespace = "EXT_mmvec";
37101}
37102def V6_vpackob_alt : HInst<
37103(outs HvxVR:$Vd32),
37104(ins HvxVR:$Vu32, HvxVR:$Vv32),
37105"$Vd32 = vpackob($Vu32,$Vv32)",
37106PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37107let hasNewValue = 1;
37108let opNewValue = 0;
37109let isCVI = 1;
37110let isPseudo = 1;
37111let isCodeGenOnly = 1;
37112let DecoderNamespace = "EXT_mmvec";
37113}
37114def V6_vpackoh : HInst<
37115(outs HvxVR:$Vd32),
37116(ins HvxVR:$Vu32, HvxVR:$Vv32),
37117"$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
37118tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37119let Inst{7-5} = 0b010;
37120let Inst{13-13} = 0b0;
37121let Inst{31-21} = 0b00011111111;
37122let hasNewValue = 1;
37123let opNewValue = 0;
37124let isCVI = 1;
37125let DecoderNamespace = "EXT_mmvec";
37126}
37127def V6_vpackoh_alt : HInst<
37128(outs HvxVR:$Vd32),
37129(ins HvxVR:$Vu32, HvxVR:$Vv32),
37130"$Vd32 = vpackoh($Vu32,$Vv32)",
37131PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37132let hasNewValue = 1;
37133let opNewValue = 0;
37134let isCVI = 1;
37135let isPseudo = 1;
37136let isCodeGenOnly = 1;
37137let DecoderNamespace = "EXT_mmvec";
37138}
37139def V6_vpackwh_sat : HInst<
37140(outs HvxVR:$Vd32),
37141(ins HvxVR:$Vu32, HvxVR:$Vv32),
37142"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
37143tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37144let Inst{7-5} = 0b000;
37145let Inst{13-13} = 0b0;
37146let Inst{31-21} = 0b00011111111;
37147let hasNewValue = 1;
37148let opNewValue = 0;
37149let isCVI = 1;
37150let DecoderNamespace = "EXT_mmvec";
37151}
37152def V6_vpackwh_sat_alt : HInst<
37153(outs HvxVR:$Vd32),
37154(ins HvxVR:$Vu32, HvxVR:$Vv32),
37155"$Vd32 = vpackwh($Vu32,$Vv32):sat",
37156PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37157let hasNewValue = 1;
37158let opNewValue = 0;
37159let isCVI = 1;
37160let isPseudo = 1;
37161let isCodeGenOnly = 1;
37162let DecoderNamespace = "EXT_mmvec";
37163}
37164def V6_vpackwuh_sat : HInst<
37165(outs HvxVR:$Vd32),
37166(ins HvxVR:$Vu32, HvxVR:$Vv32),
37167"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
37168tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37169let Inst{7-5} = 0b111;
37170let Inst{13-13} = 0b0;
37171let Inst{31-21} = 0b00011111110;
37172let hasNewValue = 1;
37173let opNewValue = 0;
37174let isCVI = 1;
37175let DecoderNamespace = "EXT_mmvec";
37176}
37177def V6_vpackwuh_sat_alt : HInst<
37178(outs HvxVR:$Vd32),
37179(ins HvxVR:$Vu32, HvxVR:$Vv32),
37180"$Vd32 = vpackwuh($Vu32,$Vv32):sat",
37181PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37182let hasNewValue = 1;
37183let opNewValue = 0;
37184let isCVI = 1;
37185let isPseudo = 1;
37186let isCodeGenOnly = 1;
37187let DecoderNamespace = "EXT_mmvec";
37188}
37189def V6_vpopcounth : HInst<
37190(outs HvxVR:$Vd32),
37191(ins HvxVR:$Vu32),
37192"$Vd32.h = vpopcount($Vu32.h)",
37193tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
37194let Inst{7-5} = 0b110;
37195let Inst{13-13} = 0b0;
37196let Inst{31-16} = 0b0001111000000010;
37197let hasNewValue = 1;
37198let opNewValue = 0;
37199let isCVI = 1;
37200let DecoderNamespace = "EXT_mmvec";
37201}
37202def V6_vpopcounth_alt : HInst<
37203(outs HvxVR:$Vd32),
37204(ins HvxVR:$Vu32),
37205"$Vd32 = vpopcounth($Vu32)",
37206PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37207let hasNewValue = 1;
37208let opNewValue = 0;
37209let isCVI = 1;
37210let isPseudo = 1;
37211let isCodeGenOnly = 1;
37212let DecoderNamespace = "EXT_mmvec";
37213}
37214def V6_vprefixqb : HInst<
37215(outs HvxVR:$Vd32),
37216(ins HvxQR:$Qv4),
37217"$Vd32.b = prefixsum($Qv4)",
37218tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
37219let Inst{13-5} = 0b100000010;
37220let Inst{21-16} = 0b000011;
37221let Inst{31-24} = 0b00011110;
37222let hasNewValue = 1;
37223let opNewValue = 0;
37224let isCVI = 1;
37225let DecoderNamespace = "EXT_mmvec";
37226}
37227def V6_vprefixqh : HInst<
37228(outs HvxVR:$Vd32),
37229(ins HvxQR:$Qv4),
37230"$Vd32.h = prefixsum($Qv4)",
37231tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
37232let Inst{13-5} = 0b100001010;
37233let Inst{21-16} = 0b000011;
37234let Inst{31-24} = 0b00011110;
37235let hasNewValue = 1;
37236let opNewValue = 0;
37237let isCVI = 1;
37238let DecoderNamespace = "EXT_mmvec";
37239}
37240def V6_vprefixqw : HInst<
37241(outs HvxVR:$Vd32),
37242(ins HvxQR:$Qv4),
37243"$Vd32.w = prefixsum($Qv4)",
37244tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
37245let Inst{13-5} = 0b100010010;
37246let Inst{21-16} = 0b000011;
37247let Inst{31-24} = 0b00011110;
37248let hasNewValue = 1;
37249let opNewValue = 0;
37250let isCVI = 1;
37251let DecoderNamespace = "EXT_mmvec";
37252}
37253def V6_vrdelta : HInst<
37254(outs HvxVR:$Vd32),
37255(ins HvxVR:$Vu32, HvxVR:$Vv32),
37256"$Vd32 = vrdelta($Vu32,$Vv32)",
37257tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
37258let Inst{7-5} = 0b011;
37259let Inst{13-13} = 0b0;
37260let Inst{31-21} = 0b00011111001;
37261let hasNewValue = 1;
37262let opNewValue = 0;
37263let isCVI = 1;
37264let DecoderNamespace = "EXT_mmvec";
37265}
37266def V6_vrmpybub_rtt : HInst<
37267(outs HvxWR:$Vdd32),
37268(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37269"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
37270tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
37271let Inst{7-5} = 0b101;
37272let Inst{13-13} = 0b0;
37273let Inst{31-21} = 0b00011001110;
37274let hasNewValue = 1;
37275let opNewValue = 0;
37276let isCVI = 1;
37277let DecoderNamespace = "EXT_mmvec";
37278}
37279def V6_vrmpybub_rtt_acc : HInst<
37280(outs HvxWR:$Vxx32),
37281(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37282"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
37283tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
37284let Inst{7-5} = 0b000;
37285let Inst{13-13} = 0b1;
37286let Inst{31-21} = 0b00011001101;
37287let hasNewValue = 1;
37288let opNewValue = 0;
37289let isAccumulator = 1;
37290let isCVI = 1;
37291let DecoderNamespace = "EXT_mmvec";
37292let Constraints = "$Vxx32 = $Vxx32in";
37293}
37294def V6_vrmpybub_rtt_acc_alt : HInst<
37295(outs HvxWR:$Vxx32),
37296(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37297"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
37298PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37299let hasNewValue = 1;
37300let opNewValue = 0;
37301let isAccumulator = 1;
37302let isCVI = 1;
37303let isPseudo = 1;
37304let isCodeGenOnly = 1;
37305let DecoderNamespace = "EXT_mmvec";
37306let Constraints = "$Vxx32 = $Vxx32in";
37307}
37308def V6_vrmpybub_rtt_alt : HInst<
37309(outs HvxWR:$Vdd32),
37310(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37311"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
37312PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37313let hasNewValue = 1;
37314let opNewValue = 0;
37315let isCVI = 1;
37316let isPseudo = 1;
37317let isCodeGenOnly = 1;
37318let DecoderNamespace = "EXT_mmvec";
37319}
37320def V6_vrmpybus : HInst<
37321(outs HvxVR:$Vd32),
37322(ins HvxVR:$Vu32, IntRegs:$Rt32),
37323"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
37324tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
37325let Inst{7-5} = 0b100;
37326let Inst{13-13} = 0b0;
37327let Inst{31-21} = 0b00011001000;
37328let hasNewValue = 1;
37329let opNewValue = 0;
37330let isCVI = 1;
37331let DecoderNamespace = "EXT_mmvec";
37332}
37333def V6_vrmpybus_acc : HInst<
37334(outs HvxVR:$Vx32),
37335(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37336"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
37337tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
37338let Inst{7-5} = 0b101;
37339let Inst{13-13} = 0b1;
37340let Inst{31-21} = 0b00011001000;
37341let hasNewValue = 1;
37342let opNewValue = 0;
37343let isAccumulator = 1;
37344let isCVI = 1;
37345let DecoderNamespace = "EXT_mmvec";
37346let Constraints = "$Vx32 = $Vx32in";
37347}
37348def V6_vrmpybus_acc_alt : HInst<
37349(outs HvxVR:$Vx32),
37350(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37351"$Vx32 += vrmpybus($Vu32,$Rt32)",
37352PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37353let hasNewValue = 1;
37354let opNewValue = 0;
37355let isAccumulator = 1;
37356let isCVI = 1;
37357let isPseudo = 1;
37358let isCodeGenOnly = 1;
37359let DecoderNamespace = "EXT_mmvec";
37360let Constraints = "$Vx32 = $Vx32in";
37361}
37362def V6_vrmpybus_alt : HInst<
37363(outs HvxVR:$Vd32),
37364(ins HvxVR:$Vu32, IntRegs:$Rt32),
37365"$Vd32 = vrmpybus($Vu32,$Rt32)",
37366PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37367let hasNewValue = 1;
37368let opNewValue = 0;
37369let isCVI = 1;
37370let isPseudo = 1;
37371let isCodeGenOnly = 1;
37372let DecoderNamespace = "EXT_mmvec";
37373}
37374def V6_vrmpybusi : HInst<
37375(outs HvxWR:$Vdd32),
37376(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37377"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
37378tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
37379let Inst{7-6} = 0b10;
37380let Inst{13-13} = 0b0;
37381let Inst{31-21} = 0b00011001010;
37382let hasNewValue = 1;
37383let opNewValue = 0;
37384let isCVI = 1;
37385let DecoderNamespace = "EXT_mmvec";
37386}
37387def V6_vrmpybusi_acc : HInst<
37388(outs HvxWR:$Vxx32),
37389(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37390"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
37391tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
37392let Inst{7-6} = 0b10;
37393let Inst{13-13} = 0b1;
37394let Inst{31-21} = 0b00011001010;
37395let hasNewValue = 1;
37396let opNewValue = 0;
37397let isAccumulator = 1;
37398let isCVI = 1;
37399let DecoderNamespace = "EXT_mmvec";
37400let Constraints = "$Vxx32 = $Vxx32in";
37401}
37402def V6_vrmpybusi_acc_alt : HInst<
37403(outs HvxWR:$Vxx32),
37404(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37405"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
37406PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37407let hasNewValue = 1;
37408let opNewValue = 0;
37409let isAccumulator = 1;
37410let isCVI = 1;
37411let isPseudo = 1;
37412let isCodeGenOnly = 1;
37413let DecoderNamespace = "EXT_mmvec";
37414let Constraints = "$Vxx32 = $Vxx32in";
37415}
37416def V6_vrmpybusi_alt : HInst<
37417(outs HvxWR:$Vdd32),
37418(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37419"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
37420PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37421let hasNewValue = 1;
37422let opNewValue = 0;
37423let isCVI = 1;
37424let isPseudo = 1;
37425let isCodeGenOnly = 1;
37426let DecoderNamespace = "EXT_mmvec";
37427}
37428def V6_vrmpybusv : HInst<
37429(outs HvxVR:$Vd32),
37430(ins HvxVR:$Vu32, HvxVR:$Vv32),
37431"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
37432tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
37433let Inst{7-5} = 0b010;
37434let Inst{13-13} = 0b0;
37435let Inst{31-21} = 0b00011100000;
37436let hasNewValue = 1;
37437let opNewValue = 0;
37438let isCVI = 1;
37439let DecoderNamespace = "EXT_mmvec";
37440}
37441def V6_vrmpybusv_acc : HInst<
37442(outs HvxVR:$Vx32),
37443(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37444"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
37445tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
37446let Inst{7-5} = 0b010;
37447let Inst{13-13} = 0b1;
37448let Inst{31-21} = 0b00011100000;
37449let hasNewValue = 1;
37450let opNewValue = 0;
37451let isAccumulator = 1;
37452let isCVI = 1;
37453let DecoderNamespace = "EXT_mmvec";
37454let Constraints = "$Vx32 = $Vx32in";
37455}
37456def V6_vrmpybusv_acc_alt : HInst<
37457(outs HvxVR:$Vx32),
37458(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37459"$Vx32 += vrmpybus($Vu32,$Vv32)",
37460PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37461let hasNewValue = 1;
37462let opNewValue = 0;
37463let isAccumulator = 1;
37464let isCVI = 1;
37465let isPseudo = 1;
37466let isCodeGenOnly = 1;
37467let DecoderNamespace = "EXT_mmvec";
37468let Constraints = "$Vx32 = $Vx32in";
37469}
37470def V6_vrmpybusv_alt : HInst<
37471(outs HvxVR:$Vd32),
37472(ins HvxVR:$Vu32, HvxVR:$Vv32),
37473"$Vd32 = vrmpybus($Vu32,$Vv32)",
37474PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37475let hasNewValue = 1;
37476let opNewValue = 0;
37477let isCVI = 1;
37478let isPseudo = 1;
37479let isCodeGenOnly = 1;
37480let DecoderNamespace = "EXT_mmvec";
37481}
37482def V6_vrmpybv : HInst<
37483(outs HvxVR:$Vd32),
37484(ins HvxVR:$Vu32, HvxVR:$Vv32),
37485"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
37486tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
37487let Inst{7-5} = 0b001;
37488let Inst{13-13} = 0b0;
37489let Inst{31-21} = 0b00011100000;
37490let hasNewValue = 1;
37491let opNewValue = 0;
37492let isCVI = 1;
37493let DecoderNamespace = "EXT_mmvec";
37494}
37495def V6_vrmpybv_acc : HInst<
37496(outs HvxVR:$Vx32),
37497(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37498"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
37499tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
37500let Inst{7-5} = 0b001;
37501let Inst{13-13} = 0b1;
37502let Inst{31-21} = 0b00011100000;
37503let hasNewValue = 1;
37504let opNewValue = 0;
37505let isAccumulator = 1;
37506let isCVI = 1;
37507let DecoderNamespace = "EXT_mmvec";
37508let Constraints = "$Vx32 = $Vx32in";
37509}
37510def V6_vrmpybv_acc_alt : HInst<
37511(outs HvxVR:$Vx32),
37512(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37513"$Vx32 += vrmpyb($Vu32,$Vv32)",
37514PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37515let hasNewValue = 1;
37516let opNewValue = 0;
37517let isAccumulator = 1;
37518let isCVI = 1;
37519let isPseudo = 1;
37520let isCodeGenOnly = 1;
37521let DecoderNamespace = "EXT_mmvec";
37522let Constraints = "$Vx32 = $Vx32in";
37523}
37524def V6_vrmpybv_alt : HInst<
37525(outs HvxVR:$Vd32),
37526(ins HvxVR:$Vu32, HvxVR:$Vv32),
37527"$Vd32 = vrmpyb($Vu32,$Vv32)",
37528PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37529let hasNewValue = 1;
37530let opNewValue = 0;
37531let isCVI = 1;
37532let isPseudo = 1;
37533let isCodeGenOnly = 1;
37534let DecoderNamespace = "EXT_mmvec";
37535}
37536def V6_vrmpyub : HInst<
37537(outs HvxVR:$Vd32),
37538(ins HvxVR:$Vu32, IntRegs:$Rt32),
37539"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
37540tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
37541let Inst{7-5} = 0b011;
37542let Inst{13-13} = 0b0;
37543let Inst{31-21} = 0b00011001000;
37544let hasNewValue = 1;
37545let opNewValue = 0;
37546let isCVI = 1;
37547let DecoderNamespace = "EXT_mmvec";
37548}
37549def V6_vrmpyub_acc : HInst<
37550(outs HvxVR:$Vx32),
37551(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37552"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
37553tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
37554let Inst{7-5} = 0b100;
37555let Inst{13-13} = 0b1;
37556let Inst{31-21} = 0b00011001000;
37557let hasNewValue = 1;
37558let opNewValue = 0;
37559let isAccumulator = 1;
37560let isCVI = 1;
37561let DecoderNamespace = "EXT_mmvec";
37562let Constraints = "$Vx32 = $Vx32in";
37563}
37564def V6_vrmpyub_acc_alt : HInst<
37565(outs HvxVR:$Vx32),
37566(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
37567"$Vx32 += vrmpyub($Vu32,$Rt32)",
37568PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37569let hasNewValue = 1;
37570let opNewValue = 0;
37571let isAccumulator = 1;
37572let isCVI = 1;
37573let isPseudo = 1;
37574let isCodeGenOnly = 1;
37575let DecoderNamespace = "EXT_mmvec";
37576let Constraints = "$Vx32 = $Vx32in";
37577}
37578def V6_vrmpyub_alt : HInst<
37579(outs HvxVR:$Vd32),
37580(ins HvxVR:$Vu32, IntRegs:$Rt32),
37581"$Vd32 = vrmpyub($Vu32,$Rt32)",
37582PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37583let hasNewValue = 1;
37584let opNewValue = 0;
37585let isCVI = 1;
37586let isPseudo = 1;
37587let isCodeGenOnly = 1;
37588let DecoderNamespace = "EXT_mmvec";
37589}
37590def V6_vrmpyub_rtt : HInst<
37591(outs HvxWR:$Vdd32),
37592(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37593"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
37594tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
37595let Inst{7-5} = 0b100;
37596let Inst{13-13} = 0b0;
37597let Inst{31-21} = 0b00011001110;
37598let hasNewValue = 1;
37599let opNewValue = 0;
37600let isCVI = 1;
37601let DecoderNamespace = "EXT_mmvec";
37602}
37603def V6_vrmpyub_rtt_acc : HInst<
37604(outs HvxWR:$Vxx32),
37605(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37606"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
37607tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
37608let Inst{7-5} = 0b111;
37609let Inst{13-13} = 0b1;
37610let Inst{31-21} = 0b00011001101;
37611let hasNewValue = 1;
37612let opNewValue = 0;
37613let isAccumulator = 1;
37614let isCVI = 1;
37615let DecoderNamespace = "EXT_mmvec";
37616let Constraints = "$Vxx32 = $Vxx32in";
37617}
37618def V6_vrmpyub_rtt_acc_alt : HInst<
37619(outs HvxWR:$Vxx32),
37620(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
37621"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
37622PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37623let hasNewValue = 1;
37624let opNewValue = 0;
37625let isAccumulator = 1;
37626let isCVI = 1;
37627let isPseudo = 1;
37628let isCodeGenOnly = 1;
37629let DecoderNamespace = "EXT_mmvec";
37630let Constraints = "$Vxx32 = $Vxx32in";
37631}
37632def V6_vrmpyub_rtt_alt : HInst<
37633(outs HvxWR:$Vdd32),
37634(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
37635"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
37636PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37637let hasNewValue = 1;
37638let opNewValue = 0;
37639let isCVI = 1;
37640let isPseudo = 1;
37641let isCodeGenOnly = 1;
37642let DecoderNamespace = "EXT_mmvec";
37643}
37644def V6_vrmpyubi : HInst<
37645(outs HvxWR:$Vdd32),
37646(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37647"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
37648tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
37649let Inst{7-6} = 0b11;
37650let Inst{13-13} = 0b0;
37651let Inst{31-21} = 0b00011001101;
37652let hasNewValue = 1;
37653let opNewValue = 0;
37654let isCVI = 1;
37655let DecoderNamespace = "EXT_mmvec";
37656}
37657def V6_vrmpyubi_acc : HInst<
37658(outs HvxWR:$Vxx32),
37659(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37660"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
37661tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
37662let Inst{7-6} = 0b11;
37663let Inst{13-13} = 0b1;
37664let Inst{31-21} = 0b00011001011;
37665let hasNewValue = 1;
37666let opNewValue = 0;
37667let isAccumulator = 1;
37668let isCVI = 1;
37669let DecoderNamespace = "EXT_mmvec";
37670let Constraints = "$Vxx32 = $Vxx32in";
37671}
37672def V6_vrmpyubi_acc_alt : HInst<
37673(outs HvxWR:$Vxx32),
37674(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37675"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
37676PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37677let hasNewValue = 1;
37678let opNewValue = 0;
37679let isAccumulator = 1;
37680let isCVI = 1;
37681let isPseudo = 1;
37682let isCodeGenOnly = 1;
37683let DecoderNamespace = "EXT_mmvec";
37684let Constraints = "$Vxx32 = $Vxx32in";
37685}
37686def V6_vrmpyubi_alt : HInst<
37687(outs HvxWR:$Vdd32),
37688(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
37689"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
37690PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37691let hasNewValue = 1;
37692let opNewValue = 0;
37693let isCVI = 1;
37694let isPseudo = 1;
37695let isCodeGenOnly = 1;
37696let DecoderNamespace = "EXT_mmvec";
37697}
37698def V6_vrmpyubv : HInst<
37699(outs HvxVR:$Vd32),
37700(ins HvxVR:$Vu32, HvxVR:$Vv32),
37701"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
37702tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
37703let Inst{7-5} = 0b000;
37704let Inst{13-13} = 0b0;
37705let Inst{31-21} = 0b00011100000;
37706let hasNewValue = 1;
37707let opNewValue = 0;
37708let isCVI = 1;
37709let DecoderNamespace = "EXT_mmvec";
37710}
37711def V6_vrmpyubv_acc : HInst<
37712(outs HvxVR:$Vx32),
37713(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37714"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
37715tc_37820f4c, TypeCVI_VX>, Enc_a7341a, Requires<[UseHVXV60]> {
37716let Inst{7-5} = 0b000;
37717let Inst{13-13} = 0b1;
37718let Inst{31-21} = 0b00011100000;
37719let hasNewValue = 1;
37720let opNewValue = 0;
37721let isAccumulator = 1;
37722let isCVI = 1;
37723let DecoderNamespace = "EXT_mmvec";
37724let Constraints = "$Vx32 = $Vx32in";
37725}
37726def V6_vrmpyubv_acc_alt : HInst<
37727(outs HvxVR:$Vx32),
37728(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
37729"$Vx32 += vrmpyub($Vu32,$Vv32)",
37730PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37731let hasNewValue = 1;
37732let opNewValue = 0;
37733let isAccumulator = 1;
37734let isCVI = 1;
37735let isPseudo = 1;
37736let isCodeGenOnly = 1;
37737let DecoderNamespace = "EXT_mmvec";
37738let Constraints = "$Vx32 = $Vx32in";
37739}
37740def V6_vrmpyubv_alt : HInst<
37741(outs HvxVR:$Vd32),
37742(ins HvxVR:$Vu32, HvxVR:$Vv32),
37743"$Vd32 = vrmpyub($Vu32,$Vv32)",
37744PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37745let hasNewValue = 1;
37746let opNewValue = 0;
37747let isCVI = 1;
37748let isPseudo = 1;
37749let isCodeGenOnly = 1;
37750let DecoderNamespace = "EXT_mmvec";
37751}
37752def V6_vrmpyzbb_rt : HInst<
37753(outs HvxVQR:$Vdddd32),
37754(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37755"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.b)",
37756tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37757let Inst{7-5} = 0b000;
37758let Inst{13-13} = 0b0;
37759let Inst{31-19} = 0b0001100111101;
37760let hasNewValue = 1;
37761let opNewValue = 0;
37762let isCVI = 1;
37763let DecoderNamespace = "EXT_mmvec";
37764}
37765def V6_vrmpyzbb_rt_acc : HInst<
37766(outs HvxVQR:$Vyyyy32),
37767(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37768"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.b)",
37769tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37770let Inst{7-5} = 0b010;
37771let Inst{13-13} = 0b1;
37772let Inst{31-19} = 0b0001100111000;
37773let hasNewValue = 1;
37774let opNewValue = 0;
37775let isAccumulator = 1;
37776let isCVI = 1;
37777let DecoderNamespace = "EXT_mmvec";
37778let Constraints = "$Vyyyy32 = $Vyyyy32in";
37779}
37780def V6_vrmpyzbb_rx : HInst<
37781(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37782(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37783"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)",
37784tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37785let Inst{7-5} = 0b000;
37786let Inst{13-13} = 0b0;
37787let Inst{31-19} = 0b0001100111100;
37788let hasNewValue = 1;
37789let opNewValue = 0;
37790let isCVI = 1;
37791let DecoderNamespace = "EXT_mmvec";
37792let Constraints = "$Rx8 = $Rx8in";
37793}
37794def V6_vrmpyzbb_rx_acc : HInst<
37795(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37796(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37797"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)",
37798tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37799let Inst{7-5} = 0b010;
37800let Inst{13-13} = 0b1;
37801let Inst{31-19} = 0b0001100111001;
37802let hasNewValue = 1;
37803let opNewValue = 0;
37804let isAccumulator = 1;
37805let isCVI = 1;
37806let DecoderNamespace = "EXT_mmvec";
37807let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37808}
37809def V6_vrmpyzbub_rt : HInst<
37810(outs HvxVQR:$Vdddd32),
37811(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37812"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.ub)",
37813tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37814let Inst{7-5} = 0b010;
37815let Inst{13-13} = 0b0;
37816let Inst{31-19} = 0b0001100111111;
37817let hasNewValue = 1;
37818let opNewValue = 0;
37819let isCVI = 1;
37820let DecoderNamespace = "EXT_mmvec";
37821}
37822def V6_vrmpyzbub_rt_acc : HInst<
37823(outs HvxVQR:$Vyyyy32),
37824(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37825"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.ub)",
37826tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37827let Inst{7-5} = 0b001;
37828let Inst{13-13} = 0b1;
37829let Inst{31-19} = 0b0001100111010;
37830let hasNewValue = 1;
37831let opNewValue = 0;
37832let isAccumulator = 1;
37833let isCVI = 1;
37834let DecoderNamespace = "EXT_mmvec";
37835let Constraints = "$Vyyyy32 = $Vyyyy32in";
37836}
37837def V6_vrmpyzbub_rx : HInst<
37838(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37839(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37840"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)",
37841tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37842let Inst{7-5} = 0b010;
37843let Inst{13-13} = 0b0;
37844let Inst{31-19} = 0b0001100111110;
37845let hasNewValue = 1;
37846let opNewValue = 0;
37847let isCVI = 1;
37848let DecoderNamespace = "EXT_mmvec";
37849let Constraints = "$Rx8 = $Rx8in";
37850}
37851def V6_vrmpyzbub_rx_acc : HInst<
37852(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37853(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37854"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)",
37855tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37856let Inst{7-5} = 0b001;
37857let Inst{13-13} = 0b1;
37858let Inst{31-19} = 0b0001100111011;
37859let hasNewValue = 1;
37860let opNewValue = 0;
37861let isAccumulator = 1;
37862let isCVI = 1;
37863let DecoderNamespace = "EXT_mmvec";
37864let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37865}
37866def V6_vrmpyzcb_rt : HInst<
37867(outs HvxVQR:$Vdddd32),
37868(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37869"$Vdddd32.w = vr16mpyz($Vu32.c,$Rt8.b)",
37870tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37871let Inst{7-5} = 0b001;
37872let Inst{13-13} = 0b0;
37873let Inst{31-19} = 0b0001100111101;
37874let hasNewValue = 1;
37875let opNewValue = 0;
37876let isCVI = 1;
37877let DecoderNamespace = "EXT_mmvec";
37878}
37879def V6_vrmpyzcb_rt_acc : HInst<
37880(outs HvxVQR:$Vyyyy32),
37881(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37882"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rt8.b)",
37883tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37884let Inst{7-5} = 0b011;
37885let Inst{13-13} = 0b1;
37886let Inst{31-19} = 0b0001100111000;
37887let hasNewValue = 1;
37888let opNewValue = 0;
37889let isAccumulator = 1;
37890let isCVI = 1;
37891let DecoderNamespace = "EXT_mmvec";
37892let Constraints = "$Vyyyy32 = $Vyyyy32in";
37893}
37894def V6_vrmpyzcb_rx : HInst<
37895(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37896(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37897"$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)",
37898tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37899let Inst{7-5} = 0b001;
37900let Inst{13-13} = 0b0;
37901let Inst{31-19} = 0b0001100111100;
37902let hasNewValue = 1;
37903let opNewValue = 0;
37904let isCVI = 1;
37905let DecoderNamespace = "EXT_mmvec";
37906let Constraints = "$Rx8 = $Rx8in";
37907}
37908def V6_vrmpyzcb_rx_acc : HInst<
37909(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37910(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37911"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)",
37912tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37913let Inst{7-5} = 0b011;
37914let Inst{13-13} = 0b1;
37915let Inst{31-19} = 0b0001100111001;
37916let hasNewValue = 1;
37917let opNewValue = 0;
37918let isAccumulator = 1;
37919let isCVI = 1;
37920let DecoderNamespace = "EXT_mmvec";
37921let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37922}
37923def V6_vrmpyzcbs_rt : HInst<
37924(outs HvxVQR:$Vdddd32),
37925(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37926"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rt8.b)",
37927tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37928let Inst{7-5} = 0b010;
37929let Inst{13-13} = 0b0;
37930let Inst{31-19} = 0b0001100111101;
37931let hasNewValue = 1;
37932let opNewValue = 0;
37933let isCVI = 1;
37934let DecoderNamespace = "EXT_mmvec";
37935}
37936def V6_vrmpyzcbs_rt_acc : HInst<
37937(outs HvxVQR:$Vyyyy32),
37938(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37939"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rt8.b)",
37940tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37941let Inst{7-5} = 0b001;
37942let Inst{13-13} = 0b1;
37943let Inst{31-19} = 0b0001100111000;
37944let hasNewValue = 1;
37945let opNewValue = 0;
37946let isAccumulator = 1;
37947let isCVI = 1;
37948let DecoderNamespace = "EXT_mmvec";
37949let Constraints = "$Vyyyy32 = $Vyyyy32in";
37950}
37951def V6_vrmpyzcbs_rx : HInst<
37952(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
37953(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37954"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)",
37955tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
37956let Inst{7-5} = 0b010;
37957let Inst{13-13} = 0b0;
37958let Inst{31-19} = 0b0001100111100;
37959let hasNewValue = 1;
37960let opNewValue = 0;
37961let isCVI = 1;
37962let DecoderNamespace = "EXT_mmvec";
37963let Constraints = "$Rx8 = $Rx8in";
37964}
37965def V6_vrmpyzcbs_rx_acc : HInst<
37966(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
37967(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
37968"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)",
37969tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
37970let Inst{7-5} = 0b001;
37971let Inst{13-13} = 0b1;
37972let Inst{31-19} = 0b0001100111001;
37973let hasNewValue = 1;
37974let opNewValue = 0;
37975let isAccumulator = 1;
37976let isCVI = 1;
37977let DecoderNamespace = "EXT_mmvec";
37978let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
37979}
37980def V6_vrmpyznb_rt : HInst<
37981(outs HvxVQR:$Vdddd32),
37982(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
37983"$Vdddd32.w = vr8mpyz($Vu32.n,$Rt8.b)",
37984tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
37985let Inst{7-5} = 0b000;
37986let Inst{13-13} = 0b0;
37987let Inst{31-19} = 0b0001100111111;
37988let hasNewValue = 1;
37989let opNewValue = 0;
37990let isCVI = 1;
37991let DecoderNamespace = "EXT_mmvec";
37992}
37993def V6_vrmpyznb_rt_acc : HInst<
37994(outs HvxVQR:$Vyyyy32),
37995(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
37996"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rt8.b)",
37997tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
37998let Inst{7-5} = 0b010;
37999let Inst{13-13} = 0b1;
38000let Inst{31-19} = 0b0001100111010;
38001let hasNewValue = 1;
38002let opNewValue = 0;
38003let isAccumulator = 1;
38004let isCVI = 1;
38005let DecoderNamespace = "EXT_mmvec";
38006let Constraints = "$Vyyyy32 = $Vyyyy32in";
38007}
38008def V6_vrmpyznb_rx : HInst<
38009(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
38010(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
38011"$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)",
38012tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
38013let Inst{7-5} = 0b000;
38014let Inst{13-13} = 0b0;
38015let Inst{31-19} = 0b0001100111110;
38016let hasNewValue = 1;
38017let opNewValue = 0;
38018let isCVI = 1;
38019let DecoderNamespace = "EXT_mmvec";
38020let Constraints = "$Rx8 = $Rx8in";
38021}
38022def V6_vrmpyznb_rx_acc : HInst<
38023(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
38024(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
38025"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)",
38026tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
38027let Inst{7-5} = 0b010;
38028let Inst{13-13} = 0b1;
38029let Inst{31-19} = 0b0001100111011;
38030let hasNewValue = 1;
38031let opNewValue = 0;
38032let isAccumulator = 1;
38033let isCVI = 1;
38034let DecoderNamespace = "EXT_mmvec";
38035let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
38036}
38037def V6_vror : HInst<
38038(outs HvxVR:$Vd32),
38039(ins HvxVR:$Vu32, IntRegs:$Rt32),
38040"$Vd32 = vror($Vu32,$Rt32)",
38041tc_6e7fa133, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
38042let Inst{7-5} = 0b001;
38043let Inst{13-13} = 0b0;
38044let Inst{31-21} = 0b00011001011;
38045let hasNewValue = 1;
38046let opNewValue = 0;
38047let isCVI = 1;
38048let DecoderNamespace = "EXT_mmvec";
38049}
38050def V6_vrotr : HInst<
38051(outs HvxVR:$Vd32),
38052(ins HvxVR:$Vu32, HvxVR:$Vv32),
38053"$Vd32.uw = vrotr($Vu32.uw,$Vv32.uw)",
38054tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV66]> {
38055let Inst{7-5} = 0b111;
38056let Inst{13-13} = 0b1;
38057let Inst{31-21} = 0b00011010100;
38058let hasNewValue = 1;
38059let opNewValue = 0;
38060let isCVI = 1;
38061let DecoderNamespace = "EXT_mmvec";
38062}
38063def V6_vrotr_alt : HInst<
38064(outs HvxVR:$Vd32),
38065(ins HvxVR:$Vu32, HvxVR:$Vv32),
38066"$Vd32 = vrotr($Vu32,$Vv32)",
38067PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
38068let hasNewValue = 1;
38069let opNewValue = 0;
38070let isCVI = 1;
38071let isPseudo = 1;
38072let isCodeGenOnly = 1;
38073let DecoderNamespace = "EXT_mmvec";
38074}
38075def V6_vroundhb : HInst<
38076(outs HvxVR:$Vd32),
38077(ins HvxVR:$Vu32, HvxVR:$Vv32),
38078"$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
38079tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38080let Inst{7-5} = 0b110;
38081let Inst{13-13} = 0b0;
38082let Inst{31-21} = 0b00011111011;
38083let hasNewValue = 1;
38084let opNewValue = 0;
38085let isCVI = 1;
38086let DecoderNamespace = "EXT_mmvec";
38087}
38088def V6_vroundhb_alt : HInst<
38089(outs HvxVR:$Vd32),
38090(ins HvxVR:$Vu32, HvxVR:$Vv32),
38091"$Vd32 = vroundhb($Vu32,$Vv32):sat",
38092PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38093let hasNewValue = 1;
38094let opNewValue = 0;
38095let isCVI = 1;
38096let isPseudo = 1;
38097let isCodeGenOnly = 1;
38098let DecoderNamespace = "EXT_mmvec";
38099}
38100def V6_vroundhub : HInst<
38101(outs HvxVR:$Vd32),
38102(ins HvxVR:$Vu32, HvxVR:$Vv32),
38103"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
38104tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38105let Inst{7-5} = 0b111;
38106let Inst{13-13} = 0b0;
38107let Inst{31-21} = 0b00011111011;
38108let hasNewValue = 1;
38109let opNewValue = 0;
38110let isCVI = 1;
38111let DecoderNamespace = "EXT_mmvec";
38112}
38113def V6_vroundhub_alt : HInst<
38114(outs HvxVR:$Vd32),
38115(ins HvxVR:$Vu32, HvxVR:$Vv32),
38116"$Vd32 = vroundhub($Vu32,$Vv32):sat",
38117PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38118let hasNewValue = 1;
38119let opNewValue = 0;
38120let isCVI = 1;
38121let isPseudo = 1;
38122let isCodeGenOnly = 1;
38123let DecoderNamespace = "EXT_mmvec";
38124}
38125def V6_vrounduhub : HInst<
38126(outs HvxVR:$Vd32),
38127(ins HvxVR:$Vu32, HvxVR:$Vv32),
38128"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
38129tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
38130let Inst{7-5} = 0b011;
38131let Inst{13-13} = 0b0;
38132let Inst{31-21} = 0b00011111111;
38133let hasNewValue = 1;
38134let opNewValue = 0;
38135let isCVI = 1;
38136let DecoderNamespace = "EXT_mmvec";
38137}
38138def V6_vrounduhub_alt : HInst<
38139(outs HvxVR:$Vd32),
38140(ins HvxVR:$Vu32, HvxVR:$Vv32),
38141"$Vd32 = vrounduhub($Vu32,$Vv32):sat",
38142PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38143let hasNewValue = 1;
38144let opNewValue = 0;
38145let isCVI = 1;
38146let isPseudo = 1;
38147let isCodeGenOnly = 1;
38148let DecoderNamespace = "EXT_mmvec";
38149}
38150def V6_vrounduwuh : HInst<
38151(outs HvxVR:$Vd32),
38152(ins HvxVR:$Vu32, HvxVR:$Vv32),
38153"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
38154tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
38155let Inst{7-5} = 0b100;
38156let Inst{13-13} = 0b0;
38157let Inst{31-21} = 0b00011111111;
38158let hasNewValue = 1;
38159let opNewValue = 0;
38160let isCVI = 1;
38161let DecoderNamespace = "EXT_mmvec";
38162}
38163def V6_vrounduwuh_alt : HInst<
38164(outs HvxVR:$Vd32),
38165(ins HvxVR:$Vu32, HvxVR:$Vv32),
38166"$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
38167PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38168let hasNewValue = 1;
38169let opNewValue = 0;
38170let isCVI = 1;
38171let isPseudo = 1;
38172let isCodeGenOnly = 1;
38173let DecoderNamespace = "EXT_mmvec";
38174}
38175def V6_vroundwh : HInst<
38176(outs HvxVR:$Vd32),
38177(ins HvxVR:$Vu32, HvxVR:$Vv32),
38178"$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
38179tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38180let Inst{7-5} = 0b100;
38181let Inst{13-13} = 0b0;
38182let Inst{31-21} = 0b00011111011;
38183let hasNewValue = 1;
38184let opNewValue = 0;
38185let isCVI = 1;
38186let DecoderNamespace = "EXT_mmvec";
38187}
38188def V6_vroundwh_alt : HInst<
38189(outs HvxVR:$Vd32),
38190(ins HvxVR:$Vu32, HvxVR:$Vv32),
38191"$Vd32 = vroundwh($Vu32,$Vv32):sat",
38192PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38193let hasNewValue = 1;
38194let opNewValue = 0;
38195let isCVI = 1;
38196let isPseudo = 1;
38197let isCodeGenOnly = 1;
38198let DecoderNamespace = "EXT_mmvec";
38199}
38200def V6_vroundwuh : HInst<
38201(outs HvxVR:$Vd32),
38202(ins HvxVR:$Vu32, HvxVR:$Vv32),
38203"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
38204tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
38205let Inst{7-5} = 0b101;
38206let Inst{13-13} = 0b0;
38207let Inst{31-21} = 0b00011111011;
38208let hasNewValue = 1;
38209let opNewValue = 0;
38210let isCVI = 1;
38211let DecoderNamespace = "EXT_mmvec";
38212}
38213def V6_vroundwuh_alt : HInst<
38214(outs HvxVR:$Vd32),
38215(ins HvxVR:$Vu32, HvxVR:$Vv32),
38216"$Vd32 = vroundwuh($Vu32,$Vv32):sat",
38217PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38218let hasNewValue = 1;
38219let opNewValue = 0;
38220let isCVI = 1;
38221let isPseudo = 1;
38222let isCodeGenOnly = 1;
38223let DecoderNamespace = "EXT_mmvec";
38224}
38225def V6_vrsadubi : HInst<
38226(outs HvxWR:$Vdd32),
38227(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38228"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
38229tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
38230let Inst{7-6} = 0b11;
38231let Inst{13-13} = 0b0;
38232let Inst{31-21} = 0b00011001010;
38233let hasNewValue = 1;
38234let opNewValue = 0;
38235let isCVI = 1;
38236let DecoderNamespace = "EXT_mmvec";
38237}
38238def V6_vrsadubi_acc : HInst<
38239(outs HvxWR:$Vxx32),
38240(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38241"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
38242tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
38243let Inst{7-6} = 0b11;
38244let Inst{13-13} = 0b1;
38245let Inst{31-21} = 0b00011001010;
38246let hasNewValue = 1;
38247let opNewValue = 0;
38248let isAccumulator = 1;
38249let isCVI = 1;
38250let DecoderNamespace = "EXT_mmvec";
38251let Constraints = "$Vxx32 = $Vxx32in";
38252}
38253def V6_vrsadubi_acc_alt : HInst<
38254(outs HvxWR:$Vxx32),
38255(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38256"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
38257PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38258let hasNewValue = 1;
38259let opNewValue = 0;
38260let isAccumulator = 1;
38261let isCVI = 1;
38262let isPseudo = 1;
38263let isCodeGenOnly = 1;
38264let DecoderNamespace = "EXT_mmvec";
38265let Constraints = "$Vxx32 = $Vxx32in";
38266}
38267def V6_vrsadubi_alt : HInst<
38268(outs HvxWR:$Vdd32),
38269(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
38270"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
38271PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38272let hasNewValue = 1;
38273let opNewValue = 0;
38274let isCVI = 1;
38275let isPseudo = 1;
38276let isCodeGenOnly = 1;
38277let DecoderNamespace = "EXT_mmvec";
38278}
38279def V6_vsatdw : HInst<
38280(outs HvxVR:$Vd32),
38281(ins HvxVR:$Vu32, HvxVR:$Vv32),
38282"$Vd32.w = vsatdw($Vu32.w,$Vv32.w)",
38283tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV66]> {
38284let Inst{7-5} = 0b111;
38285let Inst{13-13} = 0b1;
38286let Inst{31-21} = 0b00011101100;
38287let hasNewValue = 1;
38288let opNewValue = 0;
38289let isCVI = 1;
38290let isHVXALU = 1;
38291let isHVXALU2SRC = 1;
38292let DecoderNamespace = "EXT_mmvec";
38293}
38294def V6_vsathub : HInst<
38295(outs HvxVR:$Vd32),
38296(ins HvxVR:$Vu32, HvxVR:$Vv32),
38297"$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
38298tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38299let Inst{7-5} = 0b010;
38300let Inst{13-13} = 0b0;
38301let Inst{31-21} = 0b00011111011;
38302let hasNewValue = 1;
38303let opNewValue = 0;
38304let isCVI = 1;
38305let isHVXALU = 1;
38306let isHVXALU2SRC = 1;
38307let DecoderNamespace = "EXT_mmvec";
38308}
38309def V6_vsathub_alt : HInst<
38310(outs HvxVR:$Vd32),
38311(ins HvxVR:$Vu32, HvxVR:$Vv32),
38312"$Vd32 = vsathub($Vu32,$Vv32)",
38313PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38314let hasNewValue = 1;
38315let opNewValue = 0;
38316let isCVI = 1;
38317let isPseudo = 1;
38318let isCodeGenOnly = 1;
38319let DecoderNamespace = "EXT_mmvec";
38320}
38321def V6_vsatuwuh : HInst<
38322(outs HvxVR:$Vd32),
38323(ins HvxVR:$Vu32, HvxVR:$Vv32),
38324"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
38325tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
38326let Inst{7-5} = 0b110;
38327let Inst{13-13} = 0b0;
38328let Inst{31-21} = 0b00011111001;
38329let hasNewValue = 1;
38330let opNewValue = 0;
38331let isCVI = 1;
38332let isHVXALU = 1;
38333let isHVXALU2SRC = 1;
38334let DecoderNamespace = "EXT_mmvec";
38335}
38336def V6_vsatuwuh_alt : HInst<
38337(outs HvxVR:$Vd32),
38338(ins HvxVR:$Vu32, HvxVR:$Vv32),
38339"$Vd32 = vsatuwuh($Vu32,$Vv32)",
38340PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
38341let hasNewValue = 1;
38342let opNewValue = 0;
38343let isCVI = 1;
38344let isPseudo = 1;
38345let isCodeGenOnly = 1;
38346let DecoderNamespace = "EXT_mmvec";
38347}
38348def V6_vsatwh : HInst<
38349(outs HvxVR:$Vd32),
38350(ins HvxVR:$Vu32, HvxVR:$Vv32),
38351"$Vd32.h = vsat($Vu32.w,$Vv32.w)",
38352tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38353let Inst{7-5} = 0b011;
38354let Inst{13-13} = 0b0;
38355let Inst{31-21} = 0b00011111011;
38356let hasNewValue = 1;
38357let opNewValue = 0;
38358let isCVI = 1;
38359let isHVXALU = 1;
38360let isHVXALU2SRC = 1;
38361let DecoderNamespace = "EXT_mmvec";
38362}
38363def V6_vsatwh_alt : HInst<
38364(outs HvxVR:$Vd32),
38365(ins HvxVR:$Vu32, HvxVR:$Vv32),
38366"$Vd32 = vsatwh($Vu32,$Vv32)",
38367PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38368let hasNewValue = 1;
38369let opNewValue = 0;
38370let isCVI = 1;
38371let isPseudo = 1;
38372let isCodeGenOnly = 1;
38373let DecoderNamespace = "EXT_mmvec";
38374}
38375def V6_vsb : HInst<
38376(outs HvxWR:$Vdd32),
38377(ins HvxVR:$Vu32),
38378"$Vdd32.h = vsxt($Vu32.b)",
38379tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38380let Inst{7-5} = 0b011;
38381let Inst{13-13} = 0b0;
38382let Inst{31-16} = 0b0001111000000010;
38383let hasNewValue = 1;
38384let opNewValue = 0;
38385let isCVI = 1;
38386let DecoderNamespace = "EXT_mmvec";
38387}
38388def V6_vsb_alt : HInst<
38389(outs HvxWR:$Vdd32),
38390(ins HvxVR:$Vu32),
38391"$Vdd32 = vsxtb($Vu32)",
38392PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38393let hasNewValue = 1;
38394let opNewValue = 0;
38395let isCVI = 1;
38396let isPseudo = 1;
38397let isCodeGenOnly = 1;
38398let DecoderNamespace = "EXT_mmvec";
38399}
38400def V6_vscattermh : HInst<
38401(outs),
38402(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38403"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
38404tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38405let Inst{7-5} = 0b001;
38406let Inst{31-21} = 0b00101111001;
38407let accessSize = HalfWordAccess;
38408let isCVI = 1;
38409let isHVXALU = 1;
38410let isHVXALU2SRC = 1;
38411let mayStore = 1;
38412let DecoderNamespace = "EXT_mmvec";
38413}
38414def V6_vscattermh_add : HInst<
38415(outs),
38416(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38417"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
38418tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38419let Inst{7-5} = 0b101;
38420let Inst{31-21} = 0b00101111001;
38421let accessSize = HalfWordAccess;
38422let isAccumulator = 1;
38423let isCVI = 1;
38424let isHVXALU = 1;
38425let isHVXALU2SRC = 1;
38426let mayStore = 1;
38427let DecoderNamespace = "EXT_mmvec";
38428}
38429def V6_vscattermh_add_alt : HInst<
38430(outs),
38431(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38432"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
38433PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38434let isAccumulator = 1;
38435let isCVI = 1;
38436let isPseudo = 1;
38437let isCodeGenOnly = 1;
38438let DecoderNamespace = "EXT_mmvec";
38439}
38440def V6_vscattermh_alt : HInst<
38441(outs),
38442(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38443"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
38444PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38445let isCVI = 1;
38446let isPseudo = 1;
38447let isCodeGenOnly = 1;
38448let DecoderNamespace = "EXT_mmvec";
38449}
38450def V6_vscattermhq : HInst<
38451(outs),
38452(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38453"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
38454tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
38455let Inst{7-7} = 0b1;
38456let Inst{31-21} = 0b00101111100;
38457let accessSize = HalfWordAccess;
38458let isCVI = 1;
38459let isHVXALU = 1;
38460let isHVXALU2SRC = 1;
38461let mayStore = 1;
38462let DecoderNamespace = "EXT_mmvec";
38463}
38464def V6_vscattermhq_alt : HInst<
38465(outs),
38466(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38467"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
38468PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38469let isCVI = 1;
38470let isPseudo = 1;
38471let isCodeGenOnly = 1;
38472let DecoderNamespace = "EXT_mmvec";
38473}
38474def V6_vscattermhw : HInst<
38475(outs),
38476(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38477"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
38478tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
38479let Inst{7-5} = 0b010;
38480let Inst{31-21} = 0b00101111001;
38481let accessSize = HalfWordAccess;
38482let isCVI = 1;
38483let mayStore = 1;
38484let DecoderNamespace = "EXT_mmvec";
38485}
38486def V6_vscattermhw_add : HInst<
38487(outs),
38488(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38489"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
38490tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
38491let Inst{7-5} = 0b110;
38492let Inst{31-21} = 0b00101111001;
38493let accessSize = HalfWordAccess;
38494let isAccumulator = 1;
38495let isCVI = 1;
38496let mayStore = 1;
38497let DecoderNamespace = "EXT_mmvec";
38498}
38499def V6_vscattermhwq : HInst<
38500(outs),
38501(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38502"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
38503tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
38504let Inst{7-7} = 0b0;
38505let Inst{31-21} = 0b00101111101;
38506let accessSize = HalfWordAccess;
38507let isCVI = 1;
38508let mayStore = 1;
38509let DecoderNamespace = "EXT_mmvec";
38510}
38511def V6_vscattermw : HInst<
38512(outs),
38513(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38514"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
38515tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38516let Inst{7-5} = 0b000;
38517let Inst{31-21} = 0b00101111001;
38518let accessSize = WordAccess;
38519let isCVI = 1;
38520let isHVXALU = 1;
38521let isHVXALU2SRC = 1;
38522let mayStore = 1;
38523let DecoderNamespace = "EXT_mmvec";
38524}
38525def V6_vscattermw_add : HInst<
38526(outs),
38527(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38528"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
38529tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
38530let Inst{7-5} = 0b100;
38531let Inst{31-21} = 0b00101111001;
38532let accessSize = WordAccess;
38533let isAccumulator = 1;
38534let isCVI = 1;
38535let isHVXALU = 1;
38536let isHVXALU2SRC = 1;
38537let mayStore = 1;
38538let DecoderNamespace = "EXT_mmvec";
38539}
38540def V6_vscattermw_add_alt : HInst<
38541(outs),
38542(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38543"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
38544PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38545let isAccumulator = 1;
38546let isCVI = 1;
38547let isPseudo = 1;
38548let isCodeGenOnly = 1;
38549let DecoderNamespace = "EXT_mmvec";
38550}
38551def V6_vscattermw_alt : HInst<
38552(outs),
38553(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38554"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
38555PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38556let isCVI = 1;
38557let isPseudo = 1;
38558let isCodeGenOnly = 1;
38559let DecoderNamespace = "EXT_mmvec";
38560}
38561def V6_vscattermwh_add_alt : HInst<
38562(outs),
38563(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38564"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
38565PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38566let isAccumulator = 1;
38567let isCVI = 1;
38568let isPseudo = 1;
38569let isCodeGenOnly = 1;
38570let DecoderNamespace = "EXT_mmvec";
38571}
38572def V6_vscattermwh_alt : HInst<
38573(outs),
38574(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38575"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
38576PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38577let isCVI = 1;
38578let isPseudo = 1;
38579let isCodeGenOnly = 1;
38580let DecoderNamespace = "EXT_mmvec";
38581}
38582def V6_vscattermwhq_alt : HInst<
38583(outs),
38584(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
38585"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
38586PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38587let isCVI = 1;
38588let isPseudo = 1;
38589let isCodeGenOnly = 1;
38590let DecoderNamespace = "EXT_mmvec";
38591}
38592def V6_vscattermwq : HInst<
38593(outs),
38594(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38595"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
38596tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
38597let Inst{7-7} = 0b0;
38598let Inst{31-21} = 0b00101111100;
38599let accessSize = WordAccess;
38600let isCVI = 1;
38601let isHVXALU = 1;
38602let isHVXALU2SRC = 1;
38603let mayStore = 1;
38604let DecoderNamespace = "EXT_mmvec";
38605}
38606def V6_vscattermwq_alt : HInst<
38607(outs),
38608(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
38609"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
38610PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
38611let isCVI = 1;
38612let isPseudo = 1;
38613let isCodeGenOnly = 1;
38614let DecoderNamespace = "EXT_mmvec";
38615}
38616def V6_vsh : HInst<
38617(outs HvxWR:$Vdd32),
38618(ins HvxVR:$Vu32),
38619"$Vdd32.w = vsxt($Vu32.h)",
38620tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38621let Inst{7-5} = 0b100;
38622let Inst{13-13} = 0b0;
38623let Inst{31-16} = 0b0001111000000010;
38624let hasNewValue = 1;
38625let opNewValue = 0;
38626let isCVI = 1;
38627let DecoderNamespace = "EXT_mmvec";
38628}
38629def V6_vsh_alt : HInst<
38630(outs HvxWR:$Vdd32),
38631(ins HvxVR:$Vu32),
38632"$Vdd32 = vsxth($Vu32)",
38633PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38634let hasNewValue = 1;
38635let opNewValue = 0;
38636let isCVI = 1;
38637let isPseudo = 1;
38638let isCodeGenOnly = 1;
38639let DecoderNamespace = "EXT_mmvec";
38640}
38641def V6_vshufeh : HInst<
38642(outs HvxVR:$Vd32),
38643(ins HvxVR:$Vu32, HvxVR:$Vv32),
38644"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
38645tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38646let Inst{7-5} = 0b011;
38647let Inst{13-13} = 0b0;
38648let Inst{31-21} = 0b00011111010;
38649let hasNewValue = 1;
38650let opNewValue = 0;
38651let isCVI = 1;
38652let isHVXALU = 1;
38653let isHVXALU2SRC = 1;
38654let DecoderNamespace = "EXT_mmvec";
38655}
38656def V6_vshufeh_alt : HInst<
38657(outs HvxVR:$Vd32),
38658(ins HvxVR:$Vu32, HvxVR:$Vv32),
38659"$Vd32 = vshuffeh($Vu32,$Vv32)",
38660PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38661let hasNewValue = 1;
38662let opNewValue = 0;
38663let isCVI = 1;
38664let isPseudo = 1;
38665let isCodeGenOnly = 1;
38666let DecoderNamespace = "EXT_mmvec";
38667}
38668def V6_vshuff : HInst<
38669(outs HvxVR:$Vy32, HvxVR:$Vx32),
38670(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
38671"vshuff($Vy32,$Vx32,$Rt32)",
38672tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
38673let Inst{7-5} = 0b001;
38674let Inst{13-13} = 0b1;
38675let Inst{31-21} = 0b00011001111;
38676let hasNewValue = 1;
38677let opNewValue = 0;
38678let hasNewValue2 = 1;
38679let opNewValue2 = 1;
38680let isCVI = 1;
38681let DecoderNamespace = "EXT_mmvec";
38682let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
38683}
38684def V6_vshuffb : HInst<
38685(outs HvxVR:$Vd32),
38686(ins HvxVR:$Vu32),
38687"$Vd32.b = vshuff($Vu32.b)",
38688tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
38689let Inst{7-5} = 0b000;
38690let Inst{13-13} = 0b0;
38691let Inst{31-16} = 0b0001111000000010;
38692let hasNewValue = 1;
38693let opNewValue = 0;
38694let isCVI = 1;
38695let DecoderNamespace = "EXT_mmvec";
38696}
38697def V6_vshuffb_alt : HInst<
38698(outs HvxVR:$Vd32),
38699(ins HvxVR:$Vu32),
38700"$Vd32 = vshuffb($Vu32)",
38701PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38702let hasNewValue = 1;
38703let opNewValue = 0;
38704let isCVI = 1;
38705let isPseudo = 1;
38706let isCodeGenOnly = 1;
38707let DecoderNamespace = "EXT_mmvec";
38708}
38709def V6_vshuffeb : HInst<
38710(outs HvxVR:$Vd32),
38711(ins HvxVR:$Vu32, HvxVR:$Vv32),
38712"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
38713tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38714let Inst{7-5} = 0b001;
38715let Inst{13-13} = 0b0;
38716let Inst{31-21} = 0b00011111010;
38717let hasNewValue = 1;
38718let opNewValue = 0;
38719let isCVI = 1;
38720let isHVXALU = 1;
38721let isHVXALU2SRC = 1;
38722let DecoderNamespace = "EXT_mmvec";
38723}
38724def V6_vshuffeb_alt : HInst<
38725(outs HvxVR:$Vd32),
38726(ins HvxVR:$Vu32, HvxVR:$Vv32),
38727"$Vd32 = vshuffeb($Vu32,$Vv32)",
38728PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38729let hasNewValue = 1;
38730let opNewValue = 0;
38731let isCVI = 1;
38732let isPseudo = 1;
38733let isCodeGenOnly = 1;
38734let DecoderNamespace = "EXT_mmvec";
38735}
38736def V6_vshuffh : HInst<
38737(outs HvxVR:$Vd32),
38738(ins HvxVR:$Vu32),
38739"$Vd32.h = vshuff($Vu32.h)",
38740tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
38741let Inst{7-5} = 0b111;
38742let Inst{13-13} = 0b0;
38743let Inst{31-16} = 0b0001111000000001;
38744let hasNewValue = 1;
38745let opNewValue = 0;
38746let isCVI = 1;
38747let DecoderNamespace = "EXT_mmvec";
38748}
38749def V6_vshuffh_alt : HInst<
38750(outs HvxVR:$Vd32),
38751(ins HvxVR:$Vu32),
38752"$Vd32 = vshuffh($Vu32)",
38753PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38754let hasNewValue = 1;
38755let opNewValue = 0;
38756let isCVI = 1;
38757let isPseudo = 1;
38758let isCodeGenOnly = 1;
38759let DecoderNamespace = "EXT_mmvec";
38760}
38761def V6_vshuffob : HInst<
38762(outs HvxVR:$Vd32),
38763(ins HvxVR:$Vu32, HvxVR:$Vv32),
38764"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
38765tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38766let Inst{7-5} = 0b010;
38767let Inst{13-13} = 0b0;
38768let Inst{31-21} = 0b00011111010;
38769let hasNewValue = 1;
38770let opNewValue = 0;
38771let isCVI = 1;
38772let isHVXALU = 1;
38773let isHVXALU2SRC = 1;
38774let DecoderNamespace = "EXT_mmvec";
38775}
38776def V6_vshuffob_alt : HInst<
38777(outs HvxVR:$Vd32),
38778(ins HvxVR:$Vu32, HvxVR:$Vv32),
38779"$Vd32 = vshuffob($Vu32,$Vv32)",
38780PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38781let hasNewValue = 1;
38782let opNewValue = 0;
38783let isCVI = 1;
38784let isPseudo = 1;
38785let isCodeGenOnly = 1;
38786let DecoderNamespace = "EXT_mmvec";
38787}
38788def V6_vshuffvdd : HInst<
38789(outs HvxWR:$Vdd32),
38790(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
38791"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
38792tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
38793let Inst{7-5} = 0b011;
38794let Inst{13-13} = 0b1;
38795let Inst{31-24} = 0b00011011;
38796let hasNewValue = 1;
38797let opNewValue = 0;
38798let isCVI = 1;
38799let DecoderNamespace = "EXT_mmvec";
38800}
38801def V6_vshufoeb : HInst<
38802(outs HvxWR:$Vdd32),
38803(ins HvxVR:$Vu32, HvxVR:$Vv32),
38804"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
38805tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38806let Inst{7-5} = 0b110;
38807let Inst{13-13} = 0b0;
38808let Inst{31-21} = 0b00011111010;
38809let hasNewValue = 1;
38810let opNewValue = 0;
38811let isCVI = 1;
38812let DecoderNamespace = "EXT_mmvec";
38813}
38814def V6_vshufoeb_alt : HInst<
38815(outs HvxWR:$Vdd32),
38816(ins HvxVR:$Vu32, HvxVR:$Vv32),
38817"$Vdd32 = vshuffoeb($Vu32,$Vv32)",
38818PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38819let hasNewValue = 1;
38820let opNewValue = 0;
38821let isCVI = 1;
38822let isPseudo = 1;
38823let isCodeGenOnly = 1;
38824let DecoderNamespace = "EXT_mmvec";
38825}
38826def V6_vshufoeh : HInst<
38827(outs HvxWR:$Vdd32),
38828(ins HvxVR:$Vu32, HvxVR:$Vv32),
38829"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
38830tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
38831let Inst{7-5} = 0b101;
38832let Inst{13-13} = 0b0;
38833let Inst{31-21} = 0b00011111010;
38834let hasNewValue = 1;
38835let opNewValue = 0;
38836let isCVI = 1;
38837let DecoderNamespace = "EXT_mmvec";
38838}
38839def V6_vshufoeh_alt : HInst<
38840(outs HvxWR:$Vdd32),
38841(ins HvxVR:$Vu32, HvxVR:$Vv32),
38842"$Vdd32 = vshuffoeh($Vu32,$Vv32)",
38843PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38844let hasNewValue = 1;
38845let opNewValue = 0;
38846let isCVI = 1;
38847let isPseudo = 1;
38848let isCodeGenOnly = 1;
38849let DecoderNamespace = "EXT_mmvec";
38850}
38851def V6_vshufoh : HInst<
38852(outs HvxVR:$Vd32),
38853(ins HvxVR:$Vu32, HvxVR:$Vv32),
38854"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
38855tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38856let Inst{7-5} = 0b100;
38857let Inst{13-13} = 0b0;
38858let Inst{31-21} = 0b00011111010;
38859let hasNewValue = 1;
38860let opNewValue = 0;
38861let isCVI = 1;
38862let isHVXALU = 1;
38863let isHVXALU2SRC = 1;
38864let DecoderNamespace = "EXT_mmvec";
38865}
38866def V6_vshufoh_alt : HInst<
38867(outs HvxVR:$Vd32),
38868(ins HvxVR:$Vu32, HvxVR:$Vv32),
38869"$Vd32 = vshuffoh($Vu32,$Vv32)",
38870PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38871let hasNewValue = 1;
38872let opNewValue = 0;
38873let isCVI = 1;
38874let isPseudo = 1;
38875let isCodeGenOnly = 1;
38876let DecoderNamespace = "EXT_mmvec";
38877}
38878def V6_vsub_hf : HInst<
38879(outs HvxVR:$Vd32),
38880(ins HvxVR:$Vu32, HvxVR:$Vv32),
38881"$Vd32.qf16 = vsub($Vu32.hf,$Vv32.hf)",
38882tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38883let Inst{7-5} = 0b110;
38884let Inst{13-13} = 0b1;
38885let Inst{31-21} = 0b00011111011;
38886let hasNewValue = 1;
38887let opNewValue = 0;
38888let isCVI = 1;
38889let DecoderNamespace = "EXT_mmvec";
38890}
38891def V6_vsub_hf_hf : HInst<
38892(outs HvxVR:$Vd32),
38893(ins HvxVR:$Vu32, HvxVR:$Vv32),
38894"$Vd32.hf = vsub($Vu32.hf,$Vv32.hf)",
38895tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38896let Inst{7-5} = 0b000;
38897let Inst{13-13} = 0b1;
38898let Inst{31-21} = 0b00011111011;
38899let hasNewValue = 1;
38900let opNewValue = 0;
38901let isCVI = 1;
38902let DecoderNamespace = "EXT_mmvec";
38903}
38904def V6_vsub_qf16 : HInst<
38905(outs HvxVR:$Vd32),
38906(ins HvxVR:$Vu32, HvxVR:$Vv32),
38907"$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.qf16)",
38908tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38909let Inst{7-5} = 0b101;
38910let Inst{13-13} = 0b1;
38911let Inst{31-21} = 0b00011111011;
38912let hasNewValue = 1;
38913let opNewValue = 0;
38914let isCVI = 1;
38915let DecoderNamespace = "EXT_mmvec";
38916}
38917def V6_vsub_qf16_mix : HInst<
38918(outs HvxVR:$Vd32),
38919(ins HvxVR:$Vu32, HvxVR:$Vv32),
38920"$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.hf)",
38921tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38922let Inst{7-5} = 0b111;
38923let Inst{13-13} = 0b1;
38924let Inst{31-21} = 0b00011111011;
38925let hasNewValue = 1;
38926let opNewValue = 0;
38927let isCVI = 1;
38928let DecoderNamespace = "EXT_mmvec";
38929}
38930def V6_vsub_qf32 : HInst<
38931(outs HvxVR:$Vd32),
38932(ins HvxVR:$Vu32, HvxVR:$Vv32),
38933"$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.qf32)",
38934tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38935let Inst{7-5} = 0b011;
38936let Inst{13-13} = 0b1;
38937let Inst{31-21} = 0b00011111101;
38938let hasNewValue = 1;
38939let opNewValue = 0;
38940let isCVI = 1;
38941let DecoderNamespace = "EXT_mmvec";
38942}
38943def V6_vsub_qf32_mix : HInst<
38944(outs HvxVR:$Vd32),
38945(ins HvxVR:$Vu32, HvxVR:$Vv32),
38946"$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.sf)",
38947tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38948let Inst{7-5} = 0b101;
38949let Inst{13-13} = 0b1;
38950let Inst{31-21} = 0b00011111101;
38951let hasNewValue = 1;
38952let opNewValue = 0;
38953let isCVI = 1;
38954let DecoderNamespace = "EXT_mmvec";
38955}
38956def V6_vsub_sf : HInst<
38957(outs HvxVR:$Vd32),
38958(ins HvxVR:$Vu32, HvxVR:$Vv32),
38959"$Vd32.qf32 = vsub($Vu32.sf,$Vv32.sf)",
38960tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV68,UseHVXQFloat]> {
38961let Inst{7-5} = 0b100;
38962let Inst{13-13} = 0b1;
38963let Inst{31-21} = 0b00011111101;
38964let hasNewValue = 1;
38965let opNewValue = 0;
38966let isCVI = 1;
38967let DecoderNamespace = "EXT_mmvec";
38968}
38969def V6_vsub_sf_bf : HInst<
38970(outs HvxWR:$Vdd32),
38971(ins HvxVR:$Vu32, HvxVR:$Vv32),
38972"$Vdd32.sf = vsub($Vu32.bf,$Vv32.bf)",
38973tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV73,UseHVXIEEEFP]> {
38974let Inst{7-5} = 0b101;
38975let Inst{13-13} = 0b1;
38976let Inst{31-21} = 0b00011101010;
38977let hasNewValue = 1;
38978let opNewValue = 0;
38979let isCVI = 1;
38980let DecoderNamespace = "EXT_mmvec";
38981}
38982def V6_vsub_sf_hf : HInst<
38983(outs HvxWR:$Vdd32),
38984(ins HvxVR:$Vu32, HvxVR:$Vv32),
38985"$Vdd32.sf = vsub($Vu32.hf,$Vv32.hf)",
38986tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV68,UseHVXIEEEFP]> {
38987let Inst{7-5} = 0b101;
38988let Inst{13-13} = 0b1;
38989let Inst{31-21} = 0b00011111100;
38990let hasNewValue = 1;
38991let opNewValue = 0;
38992let isCVI = 1;
38993let DecoderNamespace = "EXT_mmvec";
38994}
38995def V6_vsub_sf_sf : HInst<
38996(outs HvxVR:$Vd32),
38997(ins HvxVR:$Vu32, HvxVR:$Vv32),
38998"$Vd32.sf = vsub($Vu32.sf,$Vv32.sf)",
38999tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV68,UseHVXIEEEFP]> {
39000let Inst{7-5} = 0b111;
39001let Inst{13-13} = 0b1;
39002let Inst{31-21} = 0b00011111100;
39003let hasNewValue = 1;
39004let opNewValue = 0;
39005let isCVI = 1;
39006let DecoderNamespace = "EXT_mmvec";
39007}
39008def V6_vsubb : HInst<
39009(outs HvxVR:$Vd32),
39010(ins HvxVR:$Vu32, HvxVR:$Vv32),
39011"$Vd32.b = vsub($Vu32.b,$Vv32.b)",
39012tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39013let Inst{7-5} = 0b101;
39014let Inst{13-13} = 0b0;
39015let Inst{31-21} = 0b00011100010;
39016let hasNewValue = 1;
39017let opNewValue = 0;
39018let isCVI = 1;
39019let isHVXALU = 1;
39020let isHVXALU2SRC = 1;
39021let DecoderNamespace = "EXT_mmvec";
39022}
39023def V6_vsubb_alt : HInst<
39024(outs HvxVR:$Vd32),
39025(ins HvxVR:$Vu32, HvxVR:$Vv32),
39026"$Vd32 = vsubb($Vu32,$Vv32)",
39027PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39028let hasNewValue = 1;
39029let opNewValue = 0;
39030let isCVI = 1;
39031let isPseudo = 1;
39032let isCodeGenOnly = 1;
39033let DecoderNamespace = "EXT_mmvec";
39034}
39035def V6_vsubb_dv : HInst<
39036(outs HvxWR:$Vdd32),
39037(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39038"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
39039tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39040let Inst{7-5} = 0b011;
39041let Inst{13-13} = 0b0;
39042let Inst{31-21} = 0b00011100100;
39043let hasNewValue = 1;
39044let opNewValue = 0;
39045let isCVI = 1;
39046let DecoderNamespace = "EXT_mmvec";
39047}
39048def V6_vsubb_dv_alt : HInst<
39049(outs HvxWR:$Vdd32),
39050(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39051"$Vdd32 = vsubb($Vuu32,$Vvv32)",
39052PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39053let hasNewValue = 1;
39054let opNewValue = 0;
39055let isCVI = 1;
39056let isPseudo = 1;
39057let isCodeGenOnly = 1;
39058let DecoderNamespace = "EXT_mmvec";
39059}
39060def V6_vsubbnq : HInst<
39061(outs HvxVR:$Vx32),
39062(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39063"if (!$Qv4) $Vx32.b -= $Vu32.b",
39064tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39065let Inst{7-5} = 0b001;
39066let Inst{13-13} = 0b1;
39067let Inst{21-16} = 0b000010;
39068let Inst{31-24} = 0b00011110;
39069let hasNewValue = 1;
39070let opNewValue = 0;
39071let isCVI = 1;
39072let isHVXALU = 1;
39073let isHVXALU2SRC = 1;
39074let DecoderNamespace = "EXT_mmvec";
39075let Constraints = "$Vx32 = $Vx32in";
39076}
39077def V6_vsubbnq_alt : HInst<
39078(outs HvxVR:$Vx32),
39079(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39080"if (!$Qv4.b) $Vx32.b -= $Vu32.b",
39081PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39082let hasNewValue = 1;
39083let opNewValue = 0;
39084let isCVI = 1;
39085let isPseudo = 1;
39086let isCodeGenOnly = 1;
39087let DecoderNamespace = "EXT_mmvec";
39088let Constraints = "$Vx32 = $Vx32in";
39089}
39090def V6_vsubbq : HInst<
39091(outs HvxVR:$Vx32),
39092(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39093"if ($Qv4) $Vx32.b -= $Vu32.b",
39094tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39095let Inst{7-5} = 0b110;
39096let Inst{13-13} = 0b1;
39097let Inst{21-16} = 0b000001;
39098let Inst{31-24} = 0b00011110;
39099let hasNewValue = 1;
39100let opNewValue = 0;
39101let isCVI = 1;
39102let isHVXALU = 1;
39103let isHVXALU2SRC = 1;
39104let DecoderNamespace = "EXT_mmvec";
39105let Constraints = "$Vx32 = $Vx32in";
39106}
39107def V6_vsubbq_alt : HInst<
39108(outs HvxVR:$Vx32),
39109(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39110"if ($Qv4.b) $Vx32.b -= $Vu32.b",
39111PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39112let hasNewValue = 1;
39113let opNewValue = 0;
39114let isCVI = 1;
39115let isPseudo = 1;
39116let isCodeGenOnly = 1;
39117let DecoderNamespace = "EXT_mmvec";
39118let Constraints = "$Vx32 = $Vx32in";
39119}
39120def V6_vsubbsat : HInst<
39121(outs HvxVR:$Vd32),
39122(ins HvxVR:$Vu32, HvxVR:$Vv32),
39123"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
39124tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
39125let Inst{7-5} = 0b010;
39126let Inst{13-13} = 0b0;
39127let Inst{31-21} = 0b00011111001;
39128let hasNewValue = 1;
39129let opNewValue = 0;
39130let isCVI = 1;
39131let isHVXALU = 1;
39132let isHVXALU2SRC = 1;
39133let DecoderNamespace = "EXT_mmvec";
39134}
39135def V6_vsubbsat_alt : HInst<
39136(outs HvxVR:$Vd32),
39137(ins HvxVR:$Vu32, HvxVR:$Vv32),
39138"$Vd32 = vsubb($Vu32,$Vv32):sat",
39139PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39140let hasNewValue = 1;
39141let opNewValue = 0;
39142let isCVI = 1;
39143let isPseudo = 1;
39144let isCodeGenOnly = 1;
39145let DecoderNamespace = "EXT_mmvec";
39146}
39147def V6_vsubbsat_dv : HInst<
39148(outs HvxWR:$Vdd32),
39149(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39150"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
39151tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
39152let Inst{7-5} = 0b001;
39153let Inst{13-13} = 0b0;
39154let Inst{31-21} = 0b00011110101;
39155let hasNewValue = 1;
39156let opNewValue = 0;
39157let isCVI = 1;
39158let DecoderNamespace = "EXT_mmvec";
39159}
39160def V6_vsubbsat_dv_alt : HInst<
39161(outs HvxWR:$Vdd32),
39162(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39163"$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
39164PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39165let hasNewValue = 1;
39166let opNewValue = 0;
39167let isCVI = 1;
39168let isPseudo = 1;
39169let isCodeGenOnly = 1;
39170let DecoderNamespace = "EXT_mmvec";
39171}
39172def V6_vsubcarry : HInst<
39173(outs HvxVR:$Vd32, HvxQR:$Qx4),
39174(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
39175"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
39176tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
39177let Inst{7-7} = 0b1;
39178let Inst{13-13} = 0b1;
39179let Inst{31-21} = 0b00011100101;
39180let hasNewValue = 1;
39181let opNewValue = 0;
39182let isCVI = 1;
39183let isHVXALU = 1;
39184let isHVXALU2SRC = 1;
39185let DecoderNamespace = "EXT_mmvec";
39186let Constraints = "$Qx4 = $Qx4in";
39187}
39188def V6_vsubcarryo : HInst<
39189(outs HvxVR:$Vd32, HvxQR:$Qe4),
39190(ins HvxVR:$Vu32, HvxVR:$Vv32),
39191"$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry",
39192tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
39193let Inst{7-7} = 0b1;
39194let Inst{13-13} = 0b1;
39195let Inst{31-21} = 0b00011101101;
39196let hasNewValue = 1;
39197let opNewValue = 0;
39198let isCVI = 1;
39199let isHVXALU = 1;
39200let isHVXALU2SRC = 1;
39201let DecoderNamespace = "EXT_mmvec";
39202}
39203def V6_vsubh : HInst<
39204(outs HvxVR:$Vd32),
39205(ins HvxVR:$Vu32, HvxVR:$Vv32),
39206"$Vd32.h = vsub($Vu32.h,$Vv32.h)",
39207tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39208let Inst{7-5} = 0b110;
39209let Inst{13-13} = 0b0;
39210let Inst{31-21} = 0b00011100010;
39211let hasNewValue = 1;
39212let opNewValue = 0;
39213let isCVI = 1;
39214let isHVXALU = 1;
39215let isHVXALU2SRC = 1;
39216let DecoderNamespace = "EXT_mmvec";
39217}
39218def V6_vsubh_alt : HInst<
39219(outs HvxVR:$Vd32),
39220(ins HvxVR:$Vu32, HvxVR:$Vv32),
39221"$Vd32 = vsubh($Vu32,$Vv32)",
39222PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39223let hasNewValue = 1;
39224let opNewValue = 0;
39225let isCVI = 1;
39226let isPseudo = 1;
39227let isCodeGenOnly = 1;
39228let DecoderNamespace = "EXT_mmvec";
39229}
39230def V6_vsubh_dv : HInst<
39231(outs HvxWR:$Vdd32),
39232(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39233"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
39234tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39235let Inst{7-5} = 0b100;
39236let Inst{13-13} = 0b0;
39237let Inst{31-21} = 0b00011100100;
39238let hasNewValue = 1;
39239let opNewValue = 0;
39240let isCVI = 1;
39241let DecoderNamespace = "EXT_mmvec";
39242}
39243def V6_vsubh_dv_alt : HInst<
39244(outs HvxWR:$Vdd32),
39245(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39246"$Vdd32 = vsubh($Vuu32,$Vvv32)",
39247PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39248let hasNewValue = 1;
39249let opNewValue = 0;
39250let isCVI = 1;
39251let isPseudo = 1;
39252let isCodeGenOnly = 1;
39253let DecoderNamespace = "EXT_mmvec";
39254}
39255def V6_vsubhnq : HInst<
39256(outs HvxVR:$Vx32),
39257(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39258"if (!$Qv4) $Vx32.h -= $Vu32.h",
39259tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39260let Inst{7-5} = 0b010;
39261let Inst{13-13} = 0b1;
39262let Inst{21-16} = 0b000010;
39263let Inst{31-24} = 0b00011110;
39264let hasNewValue = 1;
39265let opNewValue = 0;
39266let isCVI = 1;
39267let isHVXALU = 1;
39268let isHVXALU2SRC = 1;
39269let DecoderNamespace = "EXT_mmvec";
39270let Constraints = "$Vx32 = $Vx32in";
39271}
39272def V6_vsubhnq_alt : HInst<
39273(outs HvxVR:$Vx32),
39274(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39275"if (!$Qv4.h) $Vx32.h -= $Vu32.h",
39276PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39277let hasNewValue = 1;
39278let opNewValue = 0;
39279let isCVI = 1;
39280let isPseudo = 1;
39281let isCodeGenOnly = 1;
39282let DecoderNamespace = "EXT_mmvec";
39283let Constraints = "$Vx32 = $Vx32in";
39284}
39285def V6_vsubhq : HInst<
39286(outs HvxVR:$Vx32),
39287(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39288"if ($Qv4) $Vx32.h -= $Vu32.h",
39289tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39290let Inst{7-5} = 0b111;
39291let Inst{13-13} = 0b1;
39292let Inst{21-16} = 0b000001;
39293let Inst{31-24} = 0b00011110;
39294let hasNewValue = 1;
39295let opNewValue = 0;
39296let isCVI = 1;
39297let isHVXALU = 1;
39298let isHVXALU2SRC = 1;
39299let DecoderNamespace = "EXT_mmvec";
39300let Constraints = "$Vx32 = $Vx32in";
39301}
39302def V6_vsubhq_alt : HInst<
39303(outs HvxVR:$Vx32),
39304(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39305"if ($Qv4.h) $Vx32.h -= $Vu32.h",
39306PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39307let hasNewValue = 1;
39308let opNewValue = 0;
39309let isCVI = 1;
39310let isPseudo = 1;
39311let isCodeGenOnly = 1;
39312let DecoderNamespace = "EXT_mmvec";
39313let Constraints = "$Vx32 = $Vx32in";
39314}
39315def V6_vsubhsat : HInst<
39316(outs HvxVR:$Vd32),
39317(ins HvxVR:$Vu32, HvxVR:$Vv32),
39318"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
39319tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39320let Inst{7-5} = 0b010;
39321let Inst{13-13} = 0b0;
39322let Inst{31-21} = 0b00011100011;
39323let hasNewValue = 1;
39324let opNewValue = 0;
39325let isCVI = 1;
39326let isHVXALU = 1;
39327let isHVXALU2SRC = 1;
39328let DecoderNamespace = "EXT_mmvec";
39329}
39330def V6_vsubhsat_alt : HInst<
39331(outs HvxVR:$Vd32),
39332(ins HvxVR:$Vu32, HvxVR:$Vv32),
39333"$Vd32 = vsubh($Vu32,$Vv32):sat",
39334PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39335let hasNewValue = 1;
39336let opNewValue = 0;
39337let isCVI = 1;
39338let isPseudo = 1;
39339let isCodeGenOnly = 1;
39340let DecoderNamespace = "EXT_mmvec";
39341}
39342def V6_vsubhsat_dv : HInst<
39343(outs HvxWR:$Vdd32),
39344(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39345"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
39346tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39347let Inst{7-5} = 0b000;
39348let Inst{13-13} = 0b0;
39349let Inst{31-21} = 0b00011100101;
39350let hasNewValue = 1;
39351let opNewValue = 0;
39352let isCVI = 1;
39353let DecoderNamespace = "EXT_mmvec";
39354}
39355def V6_vsubhsat_dv_alt : HInst<
39356(outs HvxWR:$Vdd32),
39357(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39358"$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
39359PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39360let hasNewValue = 1;
39361let opNewValue = 0;
39362let isCVI = 1;
39363let isPseudo = 1;
39364let isCodeGenOnly = 1;
39365let DecoderNamespace = "EXT_mmvec";
39366}
39367def V6_vsubhw : HInst<
39368(outs HvxWR:$Vdd32),
39369(ins HvxVR:$Vu32, HvxVR:$Vv32),
39370"$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
39371tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
39372let Inst{7-5} = 0b111;
39373let Inst{13-13} = 0b0;
39374let Inst{31-21} = 0b00011100101;
39375let hasNewValue = 1;
39376let opNewValue = 0;
39377let isCVI = 1;
39378let DecoderNamespace = "EXT_mmvec";
39379}
39380def V6_vsubhw_alt : HInst<
39381(outs HvxWR:$Vdd32),
39382(ins HvxVR:$Vu32, HvxVR:$Vv32),
39383"$Vdd32 = vsubh($Vu32,$Vv32)",
39384PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39385let hasNewValue = 1;
39386let opNewValue = 0;
39387let isCVI = 1;
39388let isPseudo = 1;
39389let isCodeGenOnly = 1;
39390let DecoderNamespace = "EXT_mmvec";
39391}
39392def V6_vsububh : HInst<
39393(outs HvxWR:$Vdd32),
39394(ins HvxVR:$Vu32, HvxVR:$Vv32),
39395"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
39396tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
39397let Inst{7-5} = 0b101;
39398let Inst{13-13} = 0b0;
39399let Inst{31-21} = 0b00011100101;
39400let hasNewValue = 1;
39401let opNewValue = 0;
39402let isCVI = 1;
39403let DecoderNamespace = "EXT_mmvec";
39404}
39405def V6_vsububh_alt : HInst<
39406(outs HvxWR:$Vdd32),
39407(ins HvxVR:$Vu32, HvxVR:$Vv32),
39408"$Vdd32 = vsubub($Vu32,$Vv32)",
39409PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39410let hasNewValue = 1;
39411let opNewValue = 0;
39412let isCVI = 1;
39413let isPseudo = 1;
39414let isCodeGenOnly = 1;
39415let DecoderNamespace = "EXT_mmvec";
39416}
39417def V6_vsububsat : HInst<
39418(outs HvxVR:$Vd32),
39419(ins HvxVR:$Vu32, HvxVR:$Vv32),
39420"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
39421tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39422let Inst{7-5} = 0b000;
39423let Inst{13-13} = 0b0;
39424let Inst{31-21} = 0b00011100011;
39425let hasNewValue = 1;
39426let opNewValue = 0;
39427let isCVI = 1;
39428let isHVXALU = 1;
39429let isHVXALU2SRC = 1;
39430let DecoderNamespace = "EXT_mmvec";
39431}
39432def V6_vsububsat_alt : HInst<
39433(outs HvxVR:$Vd32),
39434(ins HvxVR:$Vu32, HvxVR:$Vv32),
39435"$Vd32 = vsubub($Vu32,$Vv32):sat",
39436PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39437let hasNewValue = 1;
39438let opNewValue = 0;
39439let isCVI = 1;
39440let isPseudo = 1;
39441let isCodeGenOnly = 1;
39442let DecoderNamespace = "EXT_mmvec";
39443}
39444def V6_vsububsat_dv : HInst<
39445(outs HvxWR:$Vdd32),
39446(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39447"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
39448tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39449let Inst{7-5} = 0b110;
39450let Inst{13-13} = 0b0;
39451let Inst{31-21} = 0b00011100100;
39452let hasNewValue = 1;
39453let opNewValue = 0;
39454let isCVI = 1;
39455let DecoderNamespace = "EXT_mmvec";
39456}
39457def V6_vsububsat_dv_alt : HInst<
39458(outs HvxWR:$Vdd32),
39459(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39460"$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
39461PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39462let hasNewValue = 1;
39463let opNewValue = 0;
39464let isCVI = 1;
39465let isPseudo = 1;
39466let isCodeGenOnly = 1;
39467let DecoderNamespace = "EXT_mmvec";
39468}
39469def V6_vsubububb_sat : HInst<
39470(outs HvxVR:$Vd32),
39471(ins HvxVR:$Vu32, HvxVR:$Vv32),
39472"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
39473tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
39474let Inst{7-5} = 0b101;
39475let Inst{13-13} = 0b0;
39476let Inst{31-21} = 0b00011110101;
39477let hasNewValue = 1;
39478let opNewValue = 0;
39479let isCVI = 1;
39480let isHVXALU = 1;
39481let isHVXALU2SRC = 1;
39482let DecoderNamespace = "EXT_mmvec";
39483}
39484def V6_vsubuhsat : HInst<
39485(outs HvxVR:$Vd32),
39486(ins HvxVR:$Vu32, HvxVR:$Vv32),
39487"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
39488tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39489let Inst{7-5} = 0b001;
39490let Inst{13-13} = 0b0;
39491let Inst{31-21} = 0b00011100011;
39492let hasNewValue = 1;
39493let opNewValue = 0;
39494let isCVI = 1;
39495let isHVXALU = 1;
39496let isHVXALU2SRC = 1;
39497let DecoderNamespace = "EXT_mmvec";
39498}
39499def V6_vsubuhsat_alt : HInst<
39500(outs HvxVR:$Vd32),
39501(ins HvxVR:$Vu32, HvxVR:$Vv32),
39502"$Vd32 = vsubuh($Vu32,$Vv32):sat",
39503PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39504let hasNewValue = 1;
39505let opNewValue = 0;
39506let isCVI = 1;
39507let isPseudo = 1;
39508let isCodeGenOnly = 1;
39509let DecoderNamespace = "EXT_mmvec";
39510}
39511def V6_vsubuhsat_dv : HInst<
39512(outs HvxWR:$Vdd32),
39513(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39514"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
39515tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39516let Inst{7-5} = 0b111;
39517let Inst{13-13} = 0b0;
39518let Inst{31-21} = 0b00011100100;
39519let hasNewValue = 1;
39520let opNewValue = 0;
39521let isCVI = 1;
39522let DecoderNamespace = "EXT_mmvec";
39523}
39524def V6_vsubuhsat_dv_alt : HInst<
39525(outs HvxWR:$Vdd32),
39526(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39527"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
39528PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39529let hasNewValue = 1;
39530let opNewValue = 0;
39531let isCVI = 1;
39532let isPseudo = 1;
39533let isCodeGenOnly = 1;
39534let DecoderNamespace = "EXT_mmvec";
39535}
39536def V6_vsubuhw : HInst<
39537(outs HvxWR:$Vdd32),
39538(ins HvxVR:$Vu32, HvxVR:$Vv32),
39539"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
39540tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
39541let Inst{7-5} = 0b110;
39542let Inst{13-13} = 0b0;
39543let Inst{31-21} = 0b00011100101;
39544let hasNewValue = 1;
39545let opNewValue = 0;
39546let isCVI = 1;
39547let DecoderNamespace = "EXT_mmvec";
39548}
39549def V6_vsubuhw_alt : HInst<
39550(outs HvxWR:$Vdd32),
39551(ins HvxVR:$Vu32, HvxVR:$Vv32),
39552"$Vdd32 = vsubuh($Vu32,$Vv32)",
39553PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39554let hasNewValue = 1;
39555let opNewValue = 0;
39556let isCVI = 1;
39557let isPseudo = 1;
39558let isCodeGenOnly = 1;
39559let DecoderNamespace = "EXT_mmvec";
39560}
39561def V6_vsubuwsat : HInst<
39562(outs HvxVR:$Vd32),
39563(ins HvxVR:$Vu32, HvxVR:$Vv32),
39564"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
39565tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
39566let Inst{7-5} = 0b100;
39567let Inst{13-13} = 0b0;
39568let Inst{31-21} = 0b00011111110;
39569let hasNewValue = 1;
39570let opNewValue = 0;
39571let isCVI = 1;
39572let isHVXALU = 1;
39573let isHVXALU2SRC = 1;
39574let DecoderNamespace = "EXT_mmvec";
39575}
39576def V6_vsubuwsat_alt : HInst<
39577(outs HvxVR:$Vd32),
39578(ins HvxVR:$Vu32, HvxVR:$Vv32),
39579"$Vd32 = vsubuw($Vu32,$Vv32):sat",
39580PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39581let hasNewValue = 1;
39582let opNewValue = 0;
39583let isCVI = 1;
39584let isPseudo = 1;
39585let isCodeGenOnly = 1;
39586let DecoderNamespace = "EXT_mmvec";
39587}
39588def V6_vsubuwsat_dv : HInst<
39589(outs HvxWR:$Vdd32),
39590(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39591"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
39592tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
39593let Inst{7-5} = 0b011;
39594let Inst{13-13} = 0b0;
39595let Inst{31-21} = 0b00011110101;
39596let hasNewValue = 1;
39597let opNewValue = 0;
39598let isCVI = 1;
39599let DecoderNamespace = "EXT_mmvec";
39600}
39601def V6_vsubuwsat_dv_alt : HInst<
39602(outs HvxWR:$Vdd32),
39603(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39604"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
39605PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
39606let hasNewValue = 1;
39607let opNewValue = 0;
39608let isCVI = 1;
39609let isPseudo = 1;
39610let isCodeGenOnly = 1;
39611let DecoderNamespace = "EXT_mmvec";
39612}
39613def V6_vsubw : HInst<
39614(outs HvxVR:$Vd32),
39615(ins HvxVR:$Vu32, HvxVR:$Vv32),
39616"$Vd32.w = vsub($Vu32.w,$Vv32.w)",
39617tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39618let Inst{7-5} = 0b111;
39619let Inst{13-13} = 0b0;
39620let Inst{31-21} = 0b00011100010;
39621let hasNewValue = 1;
39622let opNewValue = 0;
39623let isCVI = 1;
39624let isHVXALU = 1;
39625let isHVXALU2SRC = 1;
39626let DecoderNamespace = "EXT_mmvec";
39627}
39628def V6_vsubw_alt : HInst<
39629(outs HvxVR:$Vd32),
39630(ins HvxVR:$Vu32, HvxVR:$Vv32),
39631"$Vd32 = vsubw($Vu32,$Vv32)",
39632PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39633let hasNewValue = 1;
39634let opNewValue = 0;
39635let isCVI = 1;
39636let isPseudo = 1;
39637let isCodeGenOnly = 1;
39638let DecoderNamespace = "EXT_mmvec";
39639}
39640def V6_vsubw_dv : HInst<
39641(outs HvxWR:$Vdd32),
39642(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39643"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
39644tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39645let Inst{7-5} = 0b101;
39646let Inst{13-13} = 0b0;
39647let Inst{31-21} = 0b00011100100;
39648let hasNewValue = 1;
39649let opNewValue = 0;
39650let isCVI = 1;
39651let DecoderNamespace = "EXT_mmvec";
39652}
39653def V6_vsubw_dv_alt : HInst<
39654(outs HvxWR:$Vdd32),
39655(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39656"$Vdd32 = vsubw($Vuu32,$Vvv32)",
39657PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39658let hasNewValue = 1;
39659let opNewValue = 0;
39660let isCVI = 1;
39661let isPseudo = 1;
39662let isCodeGenOnly = 1;
39663let DecoderNamespace = "EXT_mmvec";
39664}
39665def V6_vsubwnq : HInst<
39666(outs HvxVR:$Vx32),
39667(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39668"if (!$Qv4) $Vx32.w -= $Vu32.w",
39669tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39670let Inst{7-5} = 0b011;
39671let Inst{13-13} = 0b1;
39672let Inst{21-16} = 0b000010;
39673let Inst{31-24} = 0b00011110;
39674let hasNewValue = 1;
39675let opNewValue = 0;
39676let isCVI = 1;
39677let isHVXALU = 1;
39678let isHVXALU2SRC = 1;
39679let DecoderNamespace = "EXT_mmvec";
39680let Constraints = "$Vx32 = $Vx32in";
39681}
39682def V6_vsubwnq_alt : HInst<
39683(outs HvxVR:$Vx32),
39684(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39685"if (!$Qv4.w) $Vx32.w -= $Vu32.w",
39686PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39687let hasNewValue = 1;
39688let opNewValue = 0;
39689let isCVI = 1;
39690let isPseudo = 1;
39691let isCodeGenOnly = 1;
39692let DecoderNamespace = "EXT_mmvec";
39693let Constraints = "$Vx32 = $Vx32in";
39694}
39695def V6_vsubwq : HInst<
39696(outs HvxVR:$Vx32),
39697(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39698"if ($Qv4) $Vx32.w -= $Vu32.w",
39699tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
39700let Inst{7-5} = 0b000;
39701let Inst{13-13} = 0b1;
39702let Inst{21-16} = 0b000010;
39703let Inst{31-24} = 0b00011110;
39704let hasNewValue = 1;
39705let opNewValue = 0;
39706let isCVI = 1;
39707let isHVXALU = 1;
39708let isHVXALU2SRC = 1;
39709let DecoderNamespace = "EXT_mmvec";
39710let Constraints = "$Vx32 = $Vx32in";
39711}
39712def V6_vsubwq_alt : HInst<
39713(outs HvxVR:$Vx32),
39714(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
39715"if ($Qv4.w) $Vx32.w -= $Vu32.w",
39716PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39717let hasNewValue = 1;
39718let opNewValue = 0;
39719let isCVI = 1;
39720let isPseudo = 1;
39721let isCodeGenOnly = 1;
39722let DecoderNamespace = "EXT_mmvec";
39723let Constraints = "$Vx32 = $Vx32in";
39724}
39725def V6_vsubwsat : HInst<
39726(outs HvxVR:$Vd32),
39727(ins HvxVR:$Vu32, HvxVR:$Vv32),
39728"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
39729tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
39730let Inst{7-5} = 0b011;
39731let Inst{13-13} = 0b0;
39732let Inst{31-21} = 0b00011100011;
39733let hasNewValue = 1;
39734let opNewValue = 0;
39735let isCVI = 1;
39736let isHVXALU = 1;
39737let isHVXALU2SRC = 1;
39738let DecoderNamespace = "EXT_mmvec";
39739}
39740def V6_vsubwsat_alt : HInst<
39741(outs HvxVR:$Vd32),
39742(ins HvxVR:$Vu32, HvxVR:$Vv32),
39743"$Vd32 = vsubw($Vu32,$Vv32):sat",
39744PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39745let hasNewValue = 1;
39746let opNewValue = 0;
39747let isCVI = 1;
39748let isPseudo = 1;
39749let isCodeGenOnly = 1;
39750let DecoderNamespace = "EXT_mmvec";
39751}
39752def V6_vsubwsat_dv : HInst<
39753(outs HvxWR:$Vdd32),
39754(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39755"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
39756tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
39757let Inst{7-5} = 0b001;
39758let Inst{13-13} = 0b0;
39759let Inst{31-21} = 0b00011100101;
39760let hasNewValue = 1;
39761let opNewValue = 0;
39762let isCVI = 1;
39763let DecoderNamespace = "EXT_mmvec";
39764}
39765def V6_vsubwsat_dv_alt : HInst<
39766(outs HvxWR:$Vdd32),
39767(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
39768"$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
39769PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39770let hasNewValue = 1;
39771let opNewValue = 0;
39772let isCVI = 1;
39773let isPseudo = 1;
39774let isCodeGenOnly = 1;
39775let DecoderNamespace = "EXT_mmvec";
39776}
39777def V6_vswap : HInst<
39778(outs HvxWR:$Vdd32),
39779(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
39780"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
39781tc_71646d06, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
39782let Inst{7-7} = 0b0;
39783let Inst{13-13} = 0b1;
39784let Inst{31-21} = 0b00011110101;
39785let hasNewValue = 1;
39786let opNewValue = 0;
39787let isCVI = 1;
39788let DecoderNamespace = "EXT_mmvec";
39789}
39790def V6_vtmpyb : HInst<
39791(outs HvxWR:$Vdd32),
39792(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39793"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
39794tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39795let Inst{7-5} = 0b000;
39796let Inst{13-13} = 0b0;
39797let Inst{31-21} = 0b00011001000;
39798let hasNewValue = 1;
39799let opNewValue = 0;
39800let isCVI = 1;
39801let DecoderNamespace = "EXT_mmvec";
39802}
39803def V6_vtmpyb_acc : HInst<
39804(outs HvxWR:$Vxx32),
39805(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39806"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
39807tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39808let Inst{7-5} = 0b000;
39809let Inst{13-13} = 0b1;
39810let Inst{31-21} = 0b00011001000;
39811let hasNewValue = 1;
39812let opNewValue = 0;
39813let isAccumulator = 1;
39814let isCVI = 1;
39815let DecoderNamespace = "EXT_mmvec";
39816let Constraints = "$Vxx32 = $Vxx32in";
39817}
39818def V6_vtmpyb_acc_alt : HInst<
39819(outs HvxWR:$Vxx32),
39820(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39821"$Vxx32 += vtmpyb($Vuu32,$Rt32)",
39822PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39823let hasNewValue = 1;
39824let opNewValue = 0;
39825let isAccumulator = 1;
39826let isCVI = 1;
39827let isPseudo = 1;
39828let isCodeGenOnly = 1;
39829let DecoderNamespace = "EXT_mmvec";
39830let Constraints = "$Vxx32 = $Vxx32in";
39831}
39832def V6_vtmpyb_alt : HInst<
39833(outs HvxWR:$Vdd32),
39834(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39835"$Vdd32 = vtmpyb($Vuu32,$Rt32)",
39836PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39837let hasNewValue = 1;
39838let opNewValue = 0;
39839let isCVI = 1;
39840let isPseudo = 1;
39841let isCodeGenOnly = 1;
39842let DecoderNamespace = "EXT_mmvec";
39843}
39844def V6_vtmpybus : HInst<
39845(outs HvxWR:$Vdd32),
39846(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39847"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
39848tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39849let Inst{7-5} = 0b001;
39850let Inst{13-13} = 0b0;
39851let Inst{31-21} = 0b00011001000;
39852let hasNewValue = 1;
39853let opNewValue = 0;
39854let isCVI = 1;
39855let DecoderNamespace = "EXT_mmvec";
39856}
39857def V6_vtmpybus_acc : HInst<
39858(outs HvxWR:$Vxx32),
39859(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39860"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
39861tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39862let Inst{7-5} = 0b001;
39863let Inst{13-13} = 0b1;
39864let Inst{31-21} = 0b00011001000;
39865let hasNewValue = 1;
39866let opNewValue = 0;
39867let isAccumulator = 1;
39868let isCVI = 1;
39869let DecoderNamespace = "EXT_mmvec";
39870let Constraints = "$Vxx32 = $Vxx32in";
39871}
39872def V6_vtmpybus_acc_alt : HInst<
39873(outs HvxWR:$Vxx32),
39874(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39875"$Vxx32 += vtmpybus($Vuu32,$Rt32)",
39876PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39877let hasNewValue = 1;
39878let opNewValue = 0;
39879let isAccumulator = 1;
39880let isCVI = 1;
39881let isPseudo = 1;
39882let isCodeGenOnly = 1;
39883let DecoderNamespace = "EXT_mmvec";
39884let Constraints = "$Vxx32 = $Vxx32in";
39885}
39886def V6_vtmpybus_alt : HInst<
39887(outs HvxWR:$Vdd32),
39888(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39889"$Vdd32 = vtmpybus($Vuu32,$Rt32)",
39890PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39891let hasNewValue = 1;
39892let opNewValue = 0;
39893let isCVI = 1;
39894let isPseudo = 1;
39895let isCodeGenOnly = 1;
39896let DecoderNamespace = "EXT_mmvec";
39897}
39898def V6_vtmpyhb : HInst<
39899(outs HvxWR:$Vdd32),
39900(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39901"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
39902tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
39903let Inst{7-5} = 0b100;
39904let Inst{13-13} = 0b0;
39905let Inst{31-21} = 0b00011001101;
39906let hasNewValue = 1;
39907let opNewValue = 0;
39908let isCVI = 1;
39909let DecoderNamespace = "EXT_mmvec";
39910}
39911def V6_vtmpyhb_acc : HInst<
39912(outs HvxWR:$Vxx32),
39913(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39914"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
39915tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
39916let Inst{7-5} = 0b010;
39917let Inst{13-13} = 0b1;
39918let Inst{31-21} = 0b00011001000;
39919let hasNewValue = 1;
39920let opNewValue = 0;
39921let isAccumulator = 1;
39922let isCVI = 1;
39923let DecoderNamespace = "EXT_mmvec";
39924let Constraints = "$Vxx32 = $Vxx32in";
39925}
39926def V6_vtmpyhb_acc_alt : HInst<
39927(outs HvxWR:$Vxx32),
39928(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
39929"$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
39930PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39931let hasNewValue = 1;
39932let opNewValue = 0;
39933let isAccumulator = 1;
39934let isCVI = 1;
39935let isPseudo = 1;
39936let isCodeGenOnly = 1;
39937let DecoderNamespace = "EXT_mmvec";
39938let Constraints = "$Vxx32 = $Vxx32in";
39939}
39940def V6_vtmpyhb_alt : HInst<
39941(outs HvxWR:$Vdd32),
39942(ins HvxWR:$Vuu32, IntRegs:$Rt32),
39943"$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
39944PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39945let hasNewValue = 1;
39946let opNewValue = 0;
39947let isCVI = 1;
39948let isPseudo = 1;
39949let isCodeGenOnly = 1;
39950let DecoderNamespace = "EXT_mmvec";
39951}
39952def V6_vtran2x2_map : HInst<
39953(outs HvxVR:$Vy32, HvxVR:$Vx32),
39954(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
39955"vtrans2x2($Vy32,$Vx32,$Rt32)",
39956PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39957let hasNewValue = 1;
39958let opNewValue = 0;
39959let hasNewValue2 = 1;
39960let opNewValue2 = 1;
39961let isCVI = 1;
39962let isPseudo = 1;
39963let isCodeGenOnly = 1;
39964let DecoderNamespace = "EXT_mmvec";
39965let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
39966}
39967def V6_vunpackb : HInst<
39968(outs HvxWR:$Vdd32),
39969(ins HvxVR:$Vu32),
39970"$Vdd32.h = vunpack($Vu32.b)",
39971tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39972let Inst{7-5} = 0b010;
39973let Inst{13-13} = 0b0;
39974let Inst{31-16} = 0b0001111000000001;
39975let hasNewValue = 1;
39976let opNewValue = 0;
39977let isCVI = 1;
39978let DecoderNamespace = "EXT_mmvec";
39979}
39980def V6_vunpackb_alt : HInst<
39981(outs HvxWR:$Vdd32),
39982(ins HvxVR:$Vu32),
39983"$Vdd32 = vunpackb($Vu32)",
39984PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
39985let hasNewValue = 1;
39986let opNewValue = 0;
39987let isCVI = 1;
39988let isPseudo = 1;
39989let isCodeGenOnly = 1;
39990let DecoderNamespace = "EXT_mmvec";
39991}
39992def V6_vunpackh : HInst<
39993(outs HvxWR:$Vdd32),
39994(ins HvxVR:$Vu32),
39995"$Vdd32.w = vunpack($Vu32.h)",
39996tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
39997let Inst{7-5} = 0b011;
39998let Inst{13-13} = 0b0;
39999let Inst{31-16} = 0b0001111000000001;
40000let hasNewValue = 1;
40001let opNewValue = 0;
40002let isCVI = 1;
40003let DecoderNamespace = "EXT_mmvec";
40004}
40005def V6_vunpackh_alt : HInst<
40006(outs HvxWR:$Vdd32),
40007(ins HvxVR:$Vu32),
40008"$Vdd32 = vunpackh($Vu32)",
40009PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40010let hasNewValue = 1;
40011let opNewValue = 0;
40012let isCVI = 1;
40013let isPseudo = 1;
40014let isCodeGenOnly = 1;
40015let DecoderNamespace = "EXT_mmvec";
40016}
40017def V6_vunpackob : HInst<
40018(outs HvxWR:$Vxx32),
40019(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
40020"$Vxx32.h |= vunpacko($Vu32.b)",
40021tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
40022let Inst{7-5} = 0b000;
40023let Inst{13-13} = 0b1;
40024let Inst{31-16} = 0b0001111000000000;
40025let hasNewValue = 1;
40026let opNewValue = 0;
40027let isAccumulator = 1;
40028let isCVI = 1;
40029let DecoderNamespace = "EXT_mmvec";
40030let Constraints = "$Vxx32 = $Vxx32in";
40031}
40032def V6_vunpackob_alt : HInst<
40033(outs HvxWR:$Vxx32),
40034(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
40035"$Vxx32 |= vunpackob($Vu32)",
40036PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40037let hasNewValue = 1;
40038let opNewValue = 0;
40039let isAccumulator = 1;
40040let isCVI = 1;
40041let isPseudo = 1;
40042let DecoderNamespace = "EXT_mmvec";
40043let Constraints = "$Vxx32 = $Vxx32in";
40044}
40045def V6_vunpackoh : HInst<
40046(outs HvxWR:$Vxx32),
40047(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
40048"$Vxx32.w |= vunpacko($Vu32.h)",
40049tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
40050let Inst{7-5} = 0b001;
40051let Inst{13-13} = 0b1;
40052let Inst{31-16} = 0b0001111000000000;
40053let hasNewValue = 1;
40054let opNewValue = 0;
40055let isAccumulator = 1;
40056let isCVI = 1;
40057let DecoderNamespace = "EXT_mmvec";
40058let Constraints = "$Vxx32 = $Vxx32in";
40059}
40060def V6_vunpackoh_alt : HInst<
40061(outs HvxWR:$Vxx32),
40062(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
40063"$Vxx32 |= vunpackoh($Vu32)",
40064PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40065let hasNewValue = 1;
40066let opNewValue = 0;
40067let isAccumulator = 1;
40068let isCVI = 1;
40069let isPseudo = 1;
40070let isCodeGenOnly = 1;
40071let DecoderNamespace = "EXT_mmvec";
40072let Constraints = "$Vxx32 = $Vxx32in";
40073}
40074def V6_vunpackub : HInst<
40075(outs HvxWR:$Vdd32),
40076(ins HvxVR:$Vu32),
40077"$Vdd32.uh = vunpack($Vu32.ub)",
40078tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
40079let Inst{7-5} = 0b000;
40080let Inst{13-13} = 0b0;
40081let Inst{31-16} = 0b0001111000000001;
40082let hasNewValue = 1;
40083let opNewValue = 0;
40084let isCVI = 1;
40085let DecoderNamespace = "EXT_mmvec";
40086}
40087def V6_vunpackub_alt : HInst<
40088(outs HvxWR:$Vdd32),
40089(ins HvxVR:$Vu32),
40090"$Vdd32 = vunpackub($Vu32)",
40091PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40092let hasNewValue = 1;
40093let opNewValue = 0;
40094let isCVI = 1;
40095let isPseudo = 1;
40096let isCodeGenOnly = 1;
40097let DecoderNamespace = "EXT_mmvec";
40098}
40099def V6_vunpackuh : HInst<
40100(outs HvxWR:$Vdd32),
40101(ins HvxVR:$Vu32),
40102"$Vdd32.uw = vunpack($Vu32.uh)",
40103tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
40104let Inst{7-5} = 0b001;
40105let Inst{13-13} = 0b0;
40106let Inst{31-16} = 0b0001111000000001;
40107let hasNewValue = 1;
40108let opNewValue = 0;
40109let isCVI = 1;
40110let DecoderNamespace = "EXT_mmvec";
40111}
40112def V6_vunpackuh_alt : HInst<
40113(outs HvxWR:$Vdd32),
40114(ins HvxVR:$Vu32),
40115"$Vdd32 = vunpackuh($Vu32)",
40116PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40117let hasNewValue = 1;
40118let opNewValue = 0;
40119let isCVI = 1;
40120let isPseudo = 1;
40121let isCodeGenOnly = 1;
40122let DecoderNamespace = "EXT_mmvec";
40123}
40124def V6_vwhist128 : HInst<
40125(outs),
40126(ins),
40127"vwhist128",
40128tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
40129let Inst{13-0} = 0b10010010000000;
40130let Inst{31-16} = 0b0001111000000000;
40131let isCVI = 1;
40132let DecoderNamespace = "EXT_mmvec";
40133}
40134def V6_vwhist128m : HInst<
40135(outs),
40136(ins u1_0Imm:$Ii),
40137"vwhist128(#$Ii)",
40138tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
40139let Inst{7-0} = 0b10000000;
40140let Inst{13-9} = 0b10011;
40141let Inst{31-16} = 0b0001111000000000;
40142let isCVI = 1;
40143let DecoderNamespace = "EXT_mmvec";
40144}
40145def V6_vwhist128q : HInst<
40146(outs),
40147(ins HvxQR:$Qv4),
40148"vwhist128($Qv4)",
40149tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
40150let Inst{13-0} = 0b10010010000000;
40151let Inst{21-16} = 0b000010;
40152let Inst{31-24} = 0b00011110;
40153let isCVI = 1;
40154let DecoderNamespace = "EXT_mmvec";
40155}
40156def V6_vwhist128qm : HInst<
40157(outs),
40158(ins HvxQR:$Qv4, u1_0Imm:$Ii),
40159"vwhist128($Qv4,#$Ii)",
40160tc_767c4e9d, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
40161let Inst{7-0} = 0b10000000;
40162let Inst{13-9} = 0b10011;
40163let Inst{21-16} = 0b000010;
40164let Inst{31-24} = 0b00011110;
40165let isCVI = 1;
40166let DecoderNamespace = "EXT_mmvec";
40167}
40168def V6_vwhist256 : HInst<
40169(outs),
40170(ins),
40171"vwhist256",
40172tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
40173let Inst{13-0} = 0b10001010000000;
40174let Inst{31-16} = 0b0001111000000000;
40175let isCVI = 1;
40176let DecoderNamespace = "EXT_mmvec";
40177}
40178def V6_vwhist256_sat : HInst<
40179(outs),
40180(ins),
40181"vwhist256:sat",
40182tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
40183let Inst{13-0} = 0b10001110000000;
40184let Inst{31-16} = 0b0001111000000000;
40185let isCVI = 1;
40186let DecoderNamespace = "EXT_mmvec";
40187}
40188def V6_vwhist256q : HInst<
40189(outs),
40190(ins HvxQR:$Qv4),
40191"vwhist256($Qv4)",
40192tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
40193let Inst{13-0} = 0b10001010000000;
40194let Inst{21-16} = 0b000010;
40195let Inst{31-24} = 0b00011110;
40196let isCVI = 1;
40197let DecoderNamespace = "EXT_mmvec";
40198}
40199def V6_vwhist256q_sat : HInst<
40200(outs),
40201(ins HvxQR:$Qv4),
40202"vwhist256($Qv4):sat",
40203tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
40204let Inst{13-0} = 0b10001110000000;
40205let Inst{21-16} = 0b000010;
40206let Inst{31-24} = 0b00011110;
40207let isCVI = 1;
40208let DecoderNamespace = "EXT_mmvec";
40209}
40210def V6_vxor : HInst<
40211(outs HvxVR:$Vd32),
40212(ins HvxVR:$Vu32, HvxVR:$Vv32),
40213"$Vd32 = vxor($Vu32,$Vv32)",
40214tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
40215let Inst{7-5} = 0b111;
40216let Inst{13-13} = 0b0;
40217let Inst{31-21} = 0b00011100001;
40218let hasNewValue = 1;
40219let opNewValue = 0;
40220let isCVI = 1;
40221let isHVXALU = 1;
40222let isHVXALU2SRC = 1;
40223let DecoderNamespace = "EXT_mmvec";
40224}
40225def V6_vzb : HInst<
40226(outs HvxWR:$Vdd32),
40227(ins HvxVR:$Vu32),
40228"$Vdd32.uh = vzxt($Vu32.ub)",
40229tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
40230let Inst{7-5} = 0b001;
40231let Inst{13-13} = 0b0;
40232let Inst{31-16} = 0b0001111000000010;
40233let hasNewValue = 1;
40234let opNewValue = 0;
40235let isCVI = 1;
40236let DecoderNamespace = "EXT_mmvec";
40237}
40238def V6_vzb_alt : HInst<
40239(outs HvxWR:$Vdd32),
40240(ins HvxVR:$Vu32),
40241"$Vdd32 = vzxtb($Vu32)",
40242PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40243let hasNewValue = 1;
40244let opNewValue = 0;
40245let isCVI = 1;
40246let isPseudo = 1;
40247let isCodeGenOnly = 1;
40248let DecoderNamespace = "EXT_mmvec";
40249}
40250def V6_vzh : HInst<
40251(outs HvxWR:$Vdd32),
40252(ins HvxVR:$Vu32),
40253"$Vdd32.uw = vzxt($Vu32.uh)",
40254tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
40255let Inst{7-5} = 0b010;
40256let Inst{13-13} = 0b0;
40257let Inst{31-16} = 0b0001111000000010;
40258let hasNewValue = 1;
40259let opNewValue = 0;
40260let isCVI = 1;
40261let DecoderNamespace = "EXT_mmvec";
40262}
40263def V6_vzh_alt : HInst<
40264(outs HvxWR:$Vdd32),
40265(ins HvxVR:$Vu32),
40266"$Vdd32 = vzxth($Vu32)",
40267PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
40268let hasNewValue = 1;
40269let opNewValue = 0;
40270let isCVI = 1;
40271let isPseudo = 1;
40272let isCodeGenOnly = 1;
40273let DecoderNamespace = "EXT_mmvec";
40274}
40275def V6_zLd_ai : HInst<
40276(outs),
40277(ins IntRegs:$Rt32, s4_0Imm:$Ii),
40278"z = vmem($Rt32+#$Ii)",
40279tc_e699ae41, TypeCVI_ZW>, Enc_ff3442, Requires<[UseHVXV66,UseZReg]>, PostInc_BaseImm {
40280let Inst{7-0} = 0b00000000;
40281let Inst{12-11} = 0b00;
40282let Inst{31-21} = 0b00101100000;
40283let addrMode = BaseImmOffset;
40284let isCVI = 1;
40285let mayLoad = 1;
40286let isRestrictNoSlot1Store = 1;
40287let CextOpcode = "V6_zLd";
40288let DecoderNamespace = "EXT_mmvec";
40289}
40290def V6_zLd_pi : HInst<
40291(outs IntRegs:$Rx32),
40292(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
40293"z = vmem($Rx32++#$Ii)",
40294tc_a0dbea28, TypeCVI_ZW>, Enc_6c9ee0, Requires<[UseHVXV66,UseZReg]>, PostInc_BaseImm {
40295let Inst{7-0} = 0b00000000;
40296let Inst{13-11} = 0b000;
40297let Inst{31-21} = 0b00101101000;
40298let addrMode = PostInc;
40299let isCVI = 1;
40300let mayLoad = 1;
40301let isRestrictNoSlot1Store = 1;
40302let CextOpcode = "V6_zLd";
40303let DecoderNamespace = "EXT_mmvec";
40304let Constraints = "$Rx32 = $Rx32in";
40305}
40306def V6_zLd_ppu : HInst<
40307(outs IntRegs:$Rx32),
40308(ins IntRegs:$Rx32in, ModRegs:$Mu2),
40309"z = vmem($Rx32++$Mu2)",
40310tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> {
40311let Inst{12-0} = 0b0000000000001;
40312let Inst{31-21} = 0b00101101000;
40313let addrMode = PostInc;
40314let isCVI = 1;
40315let mayLoad = 1;
40316let isRestrictNoSlot1Store = 1;
40317let DecoderNamespace = "EXT_mmvec";
40318let Constraints = "$Rx32 = $Rx32in";
40319}
40320def V6_zLd_pred_ai : HInst<
40321(outs),
40322(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
40323"if ($Pv4) z = vmem($Rt32+#$Ii)",
40324tc_dd5b0695, TypeCVI_ZW>, Enc_ef601b, Requires<[UseHVXV66,UseZReg]> {
40325let Inst{7-0} = 0b00000000;
40326let Inst{31-21} = 0b00101100100;
40327let isPredicated = 1;
40328let addrMode = BaseImmOffset;
40329let isCVI = 1;
40330let mayLoad = 1;
40331let isRestrictNoSlot1Store = 1;
40332let DecoderNamespace = "EXT_mmvec";
40333}
40334def V6_zLd_pred_pi : HInst<
40335(outs IntRegs:$Rx32),
40336(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
40337"if ($Pv4) z = vmem($Rx32++#$Ii)",
40338tc_3ad719fb, TypeCVI_ZW>, Enc_6baed4, Requires<[UseHVXV66,UseZReg]> {
40339let Inst{7-0} = 0b00000000;
40340let Inst{13-13} = 0b0;
40341let Inst{31-21} = 0b00101101100;
40342let isPredicated = 1;
40343let addrMode = PostInc;
40344let isCVI = 1;
40345let mayLoad = 1;
40346let isRestrictNoSlot1Store = 1;
40347let DecoderNamespace = "EXT_mmvec";
40348let Constraints = "$Rx32 = $Rx32in";
40349}
40350def V6_zLd_pred_ppu : HInst<
40351(outs IntRegs:$Rx32),
40352(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
40353"if ($Pv4) z = vmem($Rx32++$Mu2)",
40354tc_3ad719fb, TypeCVI_ZW>, Enc_691712, Requires<[UseHVXV66,UseZReg]> {
40355let Inst{10-0} = 0b00000000001;
40356let Inst{31-21} = 0b00101101100;
40357let isPredicated = 1;
40358let addrMode = PostInc;
40359let isCVI = 1;
40360let mayLoad = 1;
40361let isRestrictNoSlot1Store = 1;
40362let DecoderNamespace = "EXT_mmvec";
40363let Constraints = "$Rx32 = $Rx32in";
40364}
40365def V6_zextract : HInst<
40366(outs HvxVR:$Vd32),
40367(ins IntRegs:$Rt32),
40368"$Vd32 = zextract($Rt32)",
40369tc_5bf8afbb, TypeCVI_VP>, Enc_a5ed8a, Requires<[UseHVXV66,UseZReg]> {
40370let Inst{13-5} = 0b000001001;
40371let Inst{31-21} = 0b00011001101;
40372let hasNewValue = 1;
40373let opNewValue = 0;
40374let isCVI = 1;
40375let DecoderNamespace = "EXT_mmvec";
40376}
40377def V6_zld0 : HInst<
40378(outs),
40379(ins IntRegs:$Rt32),
40380"z = vmem($Rt32)",
40381PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
40382let isCVI = 1;
40383let isPseudo = 1;
40384let isCodeGenOnly = 1;
40385let DecoderNamespace = "EXT_mmvec";
40386}
40387def V6_zldp0 : HInst<
40388(outs),
40389(ins PredRegs:$Pv4, IntRegs:$Rt32),
40390"if ($Pv4) z = vmem($Rt32)",
40391PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
40392let isCVI = 1;
40393let isPseudo = 1;
40394let isCodeGenOnly = 1;
40395let DecoderNamespace = "EXT_mmvec";
40396}
40397def Y2_barrier : HInst<
40398(outs),
40399(ins),
40400"barrier",
40401tc_77f94a5e, TypeST>, Enc_e3b0c4 {
40402let Inst{13-0} = 0b00000000000000;
40403let Inst{31-16} = 0b1010100000000000;
40404let isSoloAX = 1;
40405let hasSideEffects = 1;
40406}
40407def Y2_break : HInst<
40408(outs),
40409(ins),
40410"brkpt",
40411tc_55255f2b, TypeCR>, Enc_e3b0c4 {
40412let Inst{13-0} = 0b00000000000000;
40413let Inst{31-16} = 0b0110110000100000;
40414let isSolo = 1;
40415}
40416def Y2_ciad : HInst<
40417(outs),
40418(ins IntRegs:$Rs32),
40419"ciad($Rs32)",
40420tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40421let Inst{13-0} = 0b00000001100000;
40422let Inst{31-21} = 0b01100100000;
40423let isSoloAX = 1;
40424}
40425def Y2_crswap0 : HInst<
40426(outs IntRegs:$Rx32),
40427(ins IntRegs:$Rx32in),
40428"crswap($Rx32,sgp0)",
40429tc_7dc63b5c, TypeCR>, Enc_403871 {
40430let Inst{13-0} = 0b00000000000000;
40431let Inst{31-21} = 0b01100101000;
40432let hasNewValue = 1;
40433let opNewValue = 0;
40434let Uses = [SGP0];
40435let Defs = [SGP0];
40436let Constraints = "$Rx32 = $Rx32in";
40437}
40438def Y2_crswap_old : HInst<
40439(outs IntRegs:$Rx32),
40440(ins IntRegs:$Rx32in),
40441"crswap($Rx32,sgp)",
40442tc_7dc63b5c, TypeMAPPING> {
40443let hasNewValue = 1;
40444let opNewValue = 0;
40445let isPseudo = 1;
40446let isCodeGenOnly = 1;
40447let Constraints = "$Rx32 = $Rx32in";
40448}
40449def Y2_cswi : HInst<
40450(outs),
40451(ins IntRegs:$Rs32),
40452"cswi($Rs32)",
40453tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40454let Inst{13-0} = 0b00000000100000;
40455let Inst{31-21} = 0b01100100000;
40456let isSoloAX = 1;
40457}
40458def Y2_dccleana : HInst<
40459(outs),
40460(ins IntRegs:$Rs32),
40461"dccleana($Rs32)",
40462tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40463let Inst{13-0} = 0b00000000000000;
40464let Inst{31-21} = 0b10100000000;
40465let isRestrictSlot1AOK = 1;
40466let hasSideEffects = 1;
40467}
40468def Y2_dccleanidx : HInst<
40469(outs),
40470(ins IntRegs:$Rs32),
40471"dccleanidx($Rs32)",
40472tc_d234b61a, TypeST>, Enc_ecbcc8 {
40473let Inst{13-0} = 0b00000000000000;
40474let Inst{31-21} = 0b10100010001;
40475let isSoloAX = 1;
40476}
40477def Y2_dccleaninva : HInst<
40478(outs),
40479(ins IntRegs:$Rs32),
40480"dccleaninva($Rs32)",
40481tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40482let Inst{13-0} = 0b00000000000000;
40483let Inst{31-21} = 0b10100000010;
40484let isRestrictSlot1AOK = 1;
40485let hasSideEffects = 1;
40486}
40487def Y2_dccleaninvidx : HInst<
40488(outs),
40489(ins IntRegs:$Rs32),
40490"dccleaninvidx($Rs32)",
40491tc_d234b61a, TypeST>, Enc_ecbcc8 {
40492let Inst{13-0} = 0b00000000000000;
40493let Inst{31-21} = 0b10100010011;
40494let isSoloAX = 1;
40495}
40496def Y2_dcfetch : HInst<
40497(outs),
40498(ins IntRegs:$Rs32),
40499"dcfetch($Rs32)",
40500tc_d45ba9cd, TypeMAPPING> {
40501let hasSideEffects = 1;
40502let isPseudo = 1;
40503let isCodeGenOnly = 1;
40504}
40505def Y2_dcfetchbo : HInst<
40506(outs),
40507(ins IntRegs:$Rs32, u11_3Imm:$Ii),
40508"dcfetch($Rs32+#$Ii)",
40509tc_2237d952, TypeLD>, Enc_2d829e {
40510let Inst{13-11} = 0b000;
40511let Inst{31-21} = 0b10010100000;
40512let addrMode = BaseImmOffset;
40513let isRestrictNoSlot1Store = 1;
40514let hasSideEffects = 1;
40515}
40516def Y2_dcinva : HInst<
40517(outs),
40518(ins IntRegs:$Rs32),
40519"dcinva($Rs32)",
40520tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40521let Inst{13-0} = 0b00000000000000;
40522let Inst{31-21} = 0b10100000001;
40523let isRestrictSlot1AOK = 1;
40524let hasSideEffects = 1;
40525}
40526def Y2_dcinvidx : HInst<
40527(outs),
40528(ins IntRegs:$Rs32),
40529"dcinvidx($Rs32)",
40530tc_d234b61a, TypeST>, Enc_ecbcc8 {
40531let Inst{13-0} = 0b00000000000000;
40532let Inst{31-21} = 0b10100010010;
40533let isSoloAX = 1;
40534}
40535def Y2_dckill : HInst<
40536(outs),
40537(ins),
40538"dckill",
40539tc_78f87ed3, TypeST>, Enc_e3b0c4 {
40540let Inst{13-0} = 0b00000000000000;
40541let Inst{31-16} = 0b1010001000000000;
40542let isSolo = 1;
40543}
40544def Y2_dctagr : HInst<
40545(outs IntRegs:$Rd32),
40546(ins IntRegs:$Rs32),
40547"$Rd32 = dctagr($Rs32)",
40548tc_a724463d, TypeST>, Enc_5e2823 {
40549let Inst{13-5} = 0b000000000;
40550let Inst{31-21} = 0b10100100001;
40551let hasNewValue = 1;
40552let opNewValue = 0;
40553let isSoloAX = 1;
40554}
40555def Y2_dctagw : HInst<
40556(outs),
40557(ins IntRegs:$Rs32, IntRegs:$Rt32),
40558"dctagw($Rs32,$Rt32)",
40559tc_6fb52018, TypeST>, Enc_ca3887 {
40560let Inst{7-0} = 0b00000000;
40561let Inst{13-13} = 0b0;
40562let Inst{31-21} = 0b10100100000;
40563let isSolo = 1;
40564}
40565def Y2_dczeroa : HInst<
40566(outs),
40567(ins IntRegs:$Rs32),
40568"dczeroa($Rs32)",
40569tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
40570let Inst{13-0} = 0b00000000000000;
40571let Inst{31-21} = 0b10100000110;
40572let isRestrictSlot1AOK = 1;
40573let mayStore = 1;
40574let hasSideEffects = 1;
40575}
40576def Y2_getimask : HInst<
40577(outs IntRegs:$Rd32),
40578(ins IntRegs:$Rs32),
40579"$Rd32 = getimask($Rs32)",
40580tc_46c18ecf, TypeCR>, Enc_5e2823 {
40581let Inst{13-5} = 0b000000000;
40582let Inst{31-21} = 0b01100110000;
40583let hasNewValue = 1;
40584let opNewValue = 0;
40585let isSoloAX = 1;
40586}
40587def Y2_iassignr : HInst<
40588(outs IntRegs:$Rd32),
40589(ins IntRegs:$Rs32),
40590"$Rd32 = iassignr($Rs32)",
40591tc_46c18ecf, TypeCR>, Enc_5e2823 {
40592let Inst{13-5} = 0b000000000;
40593let Inst{31-21} = 0b01100110011;
40594let hasNewValue = 1;
40595let opNewValue = 0;
40596let isSoloAX = 1;
40597}
40598def Y2_iassignw : HInst<
40599(outs),
40600(ins IntRegs:$Rs32),
40601"iassignw($Rs32)",
40602tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40603let Inst{13-0} = 0b00000001000000;
40604let Inst{31-21} = 0b01100100000;
40605let isSoloAX = 1;
40606}
40607def Y2_icdatar : HInst<
40608(outs IntRegs:$Rd32),
40609(ins IntRegs:$Rs32),
40610"$Rd32 = icdatar($Rs32)",
40611tc_9b20a062, TypeJ>, Enc_5e2823 {
40612let Inst{13-5} = 0b000000000;
40613let Inst{31-21} = 0b01010101101;
40614let hasNewValue = 1;
40615let opNewValue = 0;
40616let isSolo = 1;
40617}
40618def Y2_icdataw : HInst<
40619(outs),
40620(ins IntRegs:$Rs32, IntRegs:$Rt32),
40621"icdataw($Rs32,$Rt32)",
40622tc_5a222e89, TypeJ>, Enc_ca3887, Requires<[HasV66]> {
40623let Inst{7-0} = 0b00000000;
40624let Inst{13-13} = 0b1;
40625let Inst{31-21} = 0b01010101110;
40626let isSolo = 1;
40627}
40628def Y2_icinva : HInst<
40629(outs),
40630(ins IntRegs:$Rs32),
40631"icinva($Rs32)",
40632tc_0ba0d5da, TypeJ>, Enc_ecbcc8 {
40633let Inst{13-0} = 0b00000000000000;
40634let Inst{31-21} = 0b01010110110;
40635let isSolo = 1;
40636}
40637def Y2_icinvidx : HInst<
40638(outs),
40639(ins IntRegs:$Rs32),
40640"icinvidx($Rs32)",
40641tc_7d6a2568, TypeJ>, Enc_ecbcc8 {
40642let Inst{13-0} = 0b00100000000000;
40643let Inst{31-21} = 0b01010110110;
40644let isSolo = 1;
40645}
40646def Y2_ickill : HInst<
40647(outs),
40648(ins),
40649"ickill",
40650tc_b9bec29e, TypeJ>, Enc_e3b0c4 {
40651let Inst{13-0} = 0b01000000000000;
40652let Inst{31-16} = 0b0101011011000000;
40653let isSolo = 1;
40654}
40655def Y2_ictagr : HInst<
40656(outs IntRegs:$Rd32),
40657(ins IntRegs:$Rs32),
40658"$Rd32 = ictagr($Rs32)",
40659tc_759e57be, TypeJ>, Enc_5e2823 {
40660let Inst{13-5} = 0b000000000;
40661let Inst{31-21} = 0b01010101111;
40662let hasNewValue = 1;
40663let opNewValue = 0;
40664let isSolo = 1;
40665}
40666def Y2_ictagw : HInst<
40667(outs),
40668(ins IntRegs:$Rs32, IntRegs:$Rt32),
40669"ictagw($Rs32,$Rt32)",
40670tc_139ef484, TypeJ>, Enc_ca3887 {
40671let Inst{7-0} = 0b00000000;
40672let Inst{13-13} = 0b0;
40673let Inst{31-21} = 0b01010101110;
40674let isSolo = 1;
40675}
40676def Y2_isync : HInst<
40677(outs),
40678(ins),
40679"isync",
40680tc_9b34f5e0, TypeJ>, Enc_e3b0c4 {
40681let Inst{13-0} = 0b00000000000010;
40682let Inst{31-16} = 0b0101011111000000;
40683let isSolo = 1;
40684}
40685def Y2_k0lock : HInst<
40686(outs),
40687(ins),
40688"k0lock",
40689tc_7f58404a, TypeCR>, Enc_e3b0c4 {
40690let Inst{13-0} = 0b00000001100000;
40691let Inst{31-16} = 0b0110110000100000;
40692let isSolo = 1;
40693}
40694def Y2_k0unlock : HInst<
40695(outs),
40696(ins),
40697"k0unlock",
40698tc_7f58404a, TypeCR>, Enc_e3b0c4 {
40699let Inst{13-0} = 0b00000010000000;
40700let Inst{31-16} = 0b0110110000100000;
40701let isSolo = 1;
40702}
40703def Y2_k1lock_map : HInst<
40704(outs),
40705(ins),
40706"k1lock",
40707PSEUDO, TypeMAPPING>, Requires<[HasV65]> {
40708let isPseudo = 1;
40709let isCodeGenOnly = 1;
40710}
40711def Y2_k1unlock_map : HInst<
40712(outs),
40713(ins),
40714"k1unlock",
40715PSEUDO, TypeMAPPING>, Requires<[HasV65]> {
40716let isPseudo = 1;
40717let isCodeGenOnly = 1;
40718}
40719def Y2_l2cleaninvidx : HInst<
40720(outs),
40721(ins IntRegs:$Rs32),
40722"l2cleaninvidx($Rs32)",
40723tc_d234b61a, TypeST>, Enc_ecbcc8 {
40724let Inst{13-0} = 0b00000000000000;
40725let Inst{31-21} = 0b10101000011;
40726let isSoloAX = 1;
40727}
40728def Y2_l2kill : HInst<
40729(outs),
40730(ins),
40731"l2kill",
40732tc_b3d46584, TypeST>, Enc_e3b0c4 {
40733let Inst{13-0} = 0b00000000000000;
40734let Inst{31-16} = 0b1010100000100000;
40735let isSolo = 1;
40736}
40737def Y2_resume : HInst<
40738(outs),
40739(ins IntRegs:$Rs32),
40740"resume($Rs32)",
40741tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40742let Inst{13-0} = 0b00000000100000;
40743let Inst{31-21} = 0b01100100010;
40744let isSolo = 1;
40745}
40746def Y2_setimask : HInst<
40747(outs),
40748(ins PredRegs:$Pt4, IntRegs:$Rs32),
40749"setimask($Pt4,$Rs32)",
40750tc_d71ea8fa, TypeCR>, Enc_9e9047 {
40751let Inst{7-0} = 0b00000000;
40752let Inst{13-10} = 0b0000;
40753let Inst{31-21} = 0b01100100100;
40754let isSoloAX = 1;
40755}
40756def Y2_setprio : HInst<
40757(outs),
40758(ins PredRegs:$Pt4, IntRegs:$Rs32),
40759"setprio($Pt4,$Rs32)",
40760tc_d71ea8fa, TypeCR>, Enc_9e9047, Requires<[HasV66]> {
40761let Inst{7-0} = 0b00100000;
40762let Inst{13-10} = 0b0000;
40763let Inst{31-21} = 0b01100100100;
40764}
40765def Y2_start : HInst<
40766(outs),
40767(ins IntRegs:$Rs32),
40768"start($Rs32)",
40769tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40770let Inst{13-0} = 0b00000000100000;
40771let Inst{31-21} = 0b01100100011;
40772let isSolo = 1;
40773}
40774def Y2_stop : HInst<
40775(outs),
40776(ins IntRegs:$Rs32),
40777"stop($Rs32)",
40778tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40779let Inst{13-0} = 0b00000000000000;
40780let Inst{31-21} = 0b01100100011;
40781let isSolo = 1;
40782}
40783def Y2_swi : HInst<
40784(outs),
40785(ins IntRegs:$Rs32),
40786"swi($Rs32)",
40787tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40788let Inst{13-0} = 0b00000000000000;
40789let Inst{31-21} = 0b01100100000;
40790let isSoloAX = 1;
40791}
40792def Y2_syncht : HInst<
40793(outs),
40794(ins),
40795"syncht",
40796tc_77f94a5e, TypeST>, Enc_e3b0c4 {
40797let Inst{13-0} = 0b00000000000000;
40798let Inst{31-16} = 0b1010100001000000;
40799let isSolo = 1;
40800}
40801def Y2_tfrscrr : HInst<
40802(outs IntRegs:$Rd32),
40803(ins SysRegs:$Ss128),
40804"$Rd32 = $Ss128",
40805tc_fae9dfa5, TypeCR>, Enc_7d1542 {
40806let Inst{13-5} = 0b000000000;
40807let Inst{31-23} = 0b011011101;
40808let hasNewValue = 1;
40809let opNewValue = 0;
40810}
40811def Y2_tfrsrcr : HInst<
40812(outs SysRegs:$Sd128),
40813(ins IntRegs:$Rs32),
40814"$Sd128 = $Rs32",
40815tc_6ae3426b, TypeCR>, Enc_8f7633 {
40816let Inst{13-7} = 0b0000000;
40817let Inst{31-21} = 0b01100111000;
40818let hasNewValue = 1;
40819let opNewValue = 0;
40820}
40821def Y2_tlblock : HInst<
40822(outs),
40823(ins),
40824"tlblock",
40825tc_7f58404a, TypeCR>, Enc_e3b0c4 {
40826let Inst{13-0} = 0b00000000100000;
40827let Inst{31-16} = 0b0110110000100000;
40828let isSolo = 1;
40829}
40830def Y2_tlbp : HInst<
40831(outs IntRegs:$Rd32),
40832(ins IntRegs:$Rs32),
40833"$Rd32 = tlbp($Rs32)",
40834tc_6aa823ab, TypeCR>, Enc_5e2823 {
40835let Inst{13-5} = 0b000000000;
40836let Inst{31-21} = 0b01101100100;
40837let hasNewValue = 1;
40838let opNewValue = 0;
40839let isSolo = 1;
40840}
40841def Y2_tlbr : HInst<
40842(outs DoubleRegs:$Rdd32),
40843(ins IntRegs:$Rs32),
40844"$Rdd32 = tlbr($Rs32)",
40845tc_6aa823ab, TypeCR>, Enc_3a3d62 {
40846let Inst{13-5} = 0b000000000;
40847let Inst{31-21} = 0b01101100010;
40848let isSolo = 1;
40849}
40850def Y2_tlbunlock : HInst<
40851(outs),
40852(ins),
40853"tlbunlock",
40854tc_7f58404a, TypeCR>, Enc_e3b0c4 {
40855let Inst{13-0} = 0b00000001000000;
40856let Inst{31-16} = 0b0110110000100000;
40857let isSolo = 1;
40858}
40859def Y2_tlbw : HInst<
40860(outs),
40861(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
40862"tlbw($Rss32,$Rt32)",
40863tc_b2196a3f, TypeCR>, Enc_46f33d {
40864let Inst{7-0} = 0b00000000;
40865let Inst{13-13} = 0b0;
40866let Inst{31-21} = 0b01101100000;
40867let isSolo = 1;
40868}
40869def Y2_wait : HInst<
40870(outs),
40871(ins IntRegs:$Rs32),
40872"wait($Rs32)",
40873tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> {
40874let Inst{13-0} = 0b00000000000000;
40875let Inst{31-21} = 0b01100100010;
40876let isSolo = 1;
40877}
40878def Y4_crswap1 : HInst<
40879(outs IntRegs:$Rx32),
40880(ins IntRegs:$Rx32in),
40881"crswap($Rx32,sgp1)",
40882tc_7dc63b5c, TypeCR>, Enc_403871 {
40883let Inst{13-0} = 0b00000000000000;
40884let Inst{31-21} = 0b01100101001;
40885let hasNewValue = 1;
40886let opNewValue = 0;
40887let Uses = [SGP1];
40888let Defs = [SGP1];
40889let Constraints = "$Rx32 = $Rx32in";
40890}
40891def Y4_crswap10 : HInst<
40892(outs DoubleRegs:$Rxx32),
40893(ins DoubleRegs:$Rxx32in, sgp10Const:$sgp10),
40894"crswap($Rxx32,$sgp10)",
40895tc_27106296, TypeCR>, Enc_d0fe02 {
40896let Inst{13-0} = 0b00000000000000;
40897let Inst{31-21} = 0b01101101100;
40898let Uses = [SGP0, SGP1];
40899let Defs = [SGP0, SGP1];
40900let Constraints = "$Rxx32 = $Rxx32in";
40901}
40902def Y4_l2fetch : HInst<
40903(outs),
40904(ins IntRegs:$Rs32, IntRegs:$Rt32),
40905"l2fetch($Rs32,$Rt32)",
40906tc_a3070909, TypeST>, Enc_ca3887 {
40907let Inst{7-0} = 0b00000000;
40908let Inst{13-13} = 0b0;
40909let Inst{31-21} = 0b10100110000;
40910let isSoloAX = 1;
40911let hasSideEffects = 1;
40912let mayStore = 1;
40913}
40914def Y4_l2tagr : HInst<
40915(outs IntRegs:$Rd32),
40916(ins IntRegs:$Rs32),
40917"$Rd32 = l2tagr($Rs32)",
40918tc_a724463d, TypeST>, Enc_5e2823 {
40919let Inst{13-5} = 0b000000000;
40920let Inst{31-21} = 0b10100100011;
40921let hasNewValue = 1;
40922let opNewValue = 0;
40923let isSoloAX = 1;
40924}
40925def Y4_l2tagw : HInst<
40926(outs),
40927(ins IntRegs:$Rs32, IntRegs:$Rt32),
40928"l2tagw($Rs32,$Rt32)",
40929tc_512b1653, TypeST>, Enc_ca3887 {
40930let Inst{7-0} = 0b00000000;
40931let Inst{13-13} = 0b0;
40932let Inst{31-21} = 0b10100100010;
40933let isSolo = 1;
40934}
40935def Y4_nmi : HInst<
40936(outs),
40937(ins IntRegs:$Rs32),
40938"nmi($Rs32)",
40939tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40940let Inst{13-0} = 0b00000001000000;
40941let Inst{31-21} = 0b01100100011;
40942let isSolo = 1;
40943}
40944def Y4_siad : HInst<
40945(outs),
40946(ins IntRegs:$Rs32),
40947"siad($Rs32)",
40948tc_0a43be35, TypeCR>, Enc_ecbcc8 {
40949let Inst{13-0} = 0b00000001100000;
40950let Inst{31-21} = 0b01100100100;
40951let isSoloAX = 1;
40952}
40953def Y4_tfrscpp : HInst<
40954(outs DoubleRegs:$Rdd32),
40955(ins SysRegs64:$Sss128),
40956"$Rdd32 = $Sss128",
40957tc_fae9dfa5, TypeCR>, Enc_e32517 {
40958let Inst{13-5} = 0b000000000;
40959let Inst{31-23} = 0b011011110;
40960}
40961def Y4_tfrspcp : HInst<
40962(outs SysRegs64:$Sdd128),
40963(ins DoubleRegs:$Rss32),
40964"$Sdd128 = $Rss32",
40965tc_6ae3426b, TypeCR>, Enc_a705fc {
40966let Inst{13-7} = 0b0000000;
40967let Inst{31-21} = 0b01101101000;
40968let hasNewValue = 1;
40969let opNewValue = 0;
40970}
40971def Y4_trace : HInst<
40972(outs),
40973(ins IntRegs:$Rs32),
40974"trace($Rs32)",
40975tc_d7718fbe, TypeCR>, Enc_ecbcc8 {
40976let Inst{13-0} = 0b00000000000000;
40977let Inst{31-21} = 0b01100010010;
40978let isSoloAX = 1;
40979}
40980def Y5_ctlbw : HInst<
40981(outs IntRegs:$Rd32),
40982(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
40983"$Rd32 = ctlbw($Rss32,$Rt32)",
40984tc_bb78483e, TypeCR>, Enc_3d5b28 {
40985let Inst{7-5} = 0b000;
40986let Inst{13-13} = 0b0;
40987let Inst{31-21} = 0b01101100110;
40988let hasNewValue = 1;
40989let opNewValue = 0;
40990let isSolo = 1;
40991}
40992def Y5_l2cleanidx : HInst<
40993(outs),
40994(ins IntRegs:$Rs32),
40995"l2cleanidx($Rs32)",
40996tc_d234b61a, TypeST>, Enc_ecbcc8 {
40997let Inst{13-0} = 0b00000000000000;
40998let Inst{31-21} = 0b10100110001;
40999let isSoloAX = 1;
41000}
41001def Y5_l2fetch : HInst<
41002(outs),
41003(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
41004"l2fetch($Rs32,$Rtt32)",
41005tc_a3070909, TypeST>, Enc_e6abcf {
41006let Inst{7-0} = 0b00000000;
41007let Inst{13-13} = 0b0;
41008let Inst{31-21} = 0b10100110100;
41009let isSoloAX = 1;
41010let hasSideEffects = 1;
41011let mayStore = 1;
41012}
41013def Y5_l2gclean : HInst<
41014(outs),
41015(ins),
41016"l2gclean",
41017tc_b3d46584, TypeST>, Enc_e3b0c4 {
41018let Inst{13-0} = 0b01000000000000;
41019let Inst{31-16} = 0b1010100000100000;
41020let isSolo = 1;
41021}
41022def Y5_l2gcleaninv : HInst<
41023(outs),
41024(ins),
41025"l2gcleaninv",
41026tc_b3d46584, TypeST>, Enc_e3b0c4 {
41027let Inst{13-0} = 0b01100000000000;
41028let Inst{31-16} = 0b1010100000100000;
41029let isSolo = 1;
41030}
41031def Y5_l2gunlock : HInst<
41032(outs),
41033(ins),
41034"l2gunlock",
41035tc_b3d46584, TypeST>, Enc_e3b0c4 {
41036let Inst{13-0} = 0b00100000000000;
41037let Inst{31-16} = 0b1010100000100000;
41038let isSolo = 1;
41039}
41040def Y5_l2invidx : HInst<
41041(outs),
41042(ins IntRegs:$Rs32),
41043"l2invidx($Rs32)",
41044tc_d234b61a, TypeST>, Enc_ecbcc8 {
41045let Inst{13-0} = 0b00000000000000;
41046let Inst{31-21} = 0b10100110010;
41047let isSoloAX = 1;
41048}
41049def Y5_l2locka : HInst<
41050(outs PredRegs:$Pd4),
41051(ins IntRegs:$Rs32),
41052"$Pd4 = l2locka($Rs32)",
41053tc_a724463d, TypeST>, Enc_48b75f {
41054let Inst{13-2} = 0b100000000000;
41055let Inst{31-21} = 0b10100000111;
41056let isPredicateLate = 1;
41057let isSoloAX = 1;
41058}
41059def Y5_l2unlocka : HInst<
41060(outs),
41061(ins IntRegs:$Rs32),
41062"l2unlocka($Rs32)",
41063tc_d234b61a, TypeST>, Enc_ecbcc8 {
41064let Inst{13-0} = 0b00000000000000;
41065let Inst{31-21} = 0b10100110011;
41066let isSoloAX = 1;
41067}
41068def Y5_tlbasidi : HInst<
41069(outs),
41070(ins IntRegs:$Rs32),
41071"tlbinvasid($Rs32)",
41072tc_54f0cee2, TypeCR>, Enc_ecbcc8 {
41073let Inst{13-0} = 0b00000000000000;
41074let Inst{31-21} = 0b01101100101;
41075let isSolo = 1;
41076}
41077def Y5_tlboc : HInst<
41078(outs IntRegs:$Rd32),
41079(ins DoubleRegs:$Rss32),
41080"$Rd32 = tlboc($Rss32)",
41081tc_6aa823ab, TypeCR>, Enc_90cd8b {
41082let Inst{13-5} = 0b000000000;
41083let Inst{31-21} = 0b01101100111;
41084let hasNewValue = 1;
41085let opNewValue = 0;
41086let isSolo = 1;
41087}
41088def Y6_diag : HInst<
41089(outs),
41090(ins IntRegs:$Rs32),
41091"diag($Rs32)",
41092tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV67]> {
41093let Inst{13-0} = 0b00000000100000;
41094let Inst{31-21} = 0b01100010010;
41095}
41096def Y6_diag0 : HInst<
41097(outs),
41098(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
41099"diag0($Rss32,$Rtt32)",
41100tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
41101let Inst{7-0} = 0b01000000;
41102let Inst{13-13} = 0b0;
41103let Inst{31-21} = 0b01100010010;
41104}
41105def Y6_diag1 : HInst<
41106(outs),
41107(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
41108"diag1($Rss32,$Rtt32)",
41109tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
41110let Inst{7-0} = 0b01100000;
41111let Inst{13-13} = 0b0;
41112let Inst{31-21} = 0b01100010010;
41113}
41114def Y6_dmlink : HInst<
41115(outs),
41116(ins IntRegs:$Rs32, IntRegs:$Rt32),
41117"dmlink($Rs32,$Rt32)",
41118tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
41119let Inst{7-0} = 0b01000000;
41120let Inst{13-13} = 0b0;
41121let Inst{31-21} = 0b10100110000;
41122let hasSideEffects = 1;
41123let isSolo = 1;
41124let mayStore = 1;
41125}
41126def Y6_dmpause : HInst<
41127(outs IntRegs:$Rd32),
41128(ins),
41129"$Rd32 = dmpause",
41130tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
41131let Inst{13-5} = 0b000000011;
41132let Inst{31-16} = 0b1010100000000000;
41133let hasNewValue = 1;
41134let opNewValue = 0;
41135let hasSideEffects = 1;
41136let isSolo = 1;
41137}
41138def Y6_dmpoll : HInst<
41139(outs IntRegs:$Rd32),
41140(ins),
41141"$Rd32 = dmpoll",
41142tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
41143let Inst{13-5} = 0b000000010;
41144let Inst{31-16} = 0b1010100000000000;
41145let hasNewValue = 1;
41146let opNewValue = 0;
41147let hasSideEffects = 1;
41148let isSolo = 1;
41149}
41150def Y6_dmresume : HInst<
41151(outs),
41152(ins IntRegs:$Rs32),
41153"dmresume($Rs32)",
41154tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
41155let Inst{13-0} = 0b00000010000000;
41156let Inst{31-21} = 0b10100110000;
41157let hasSideEffects = 1;
41158let isSolo = 1;
41159}
41160def Y6_dmstart : HInst<
41161(outs),
41162(ins IntRegs:$Rs32),
41163"dmstart($Rs32)",
41164tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
41165let Inst{13-0} = 0b00000000100000;
41166let Inst{31-21} = 0b10100110000;
41167let hasSideEffects = 1;
41168let isSolo = 1;
41169}
41170def Y6_dmwait : HInst<
41171(outs IntRegs:$Rd32),
41172(ins),
41173"$Rd32 = dmwait",
41174tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
41175let Inst{13-5} = 0b000000001;
41176let Inst{31-16} = 0b1010100000000000;
41177let hasNewValue = 1;
41178let opNewValue = 0;
41179let hasSideEffects = 1;
41180let isSolo = 1;
41181}
41182def Y6_l2gcleaninvpa : HInst<
41183(outs),
41184(ins DoubleRegs:$Rtt32),
41185"l2gcleaninv($Rtt32)",
41186tc_7c28bd7e, TypeST>, Enc_598f6c {
41187let Inst{7-0} = 0b00000000;
41188let Inst{13-13} = 0b0;
41189let Inst{31-16} = 0b1010011011000000;
41190let isSolo = 1;
41191}
41192def Y6_l2gcleanpa : HInst<
41193(outs),
41194(ins DoubleRegs:$Rtt32),
41195"l2gclean($Rtt32)",
41196tc_7c28bd7e, TypeST>, Enc_598f6c {
41197let Inst{7-0} = 0b00000000;
41198let Inst{13-13} = 0b0;
41199let Inst{31-16} = 0b1010011010100000;
41200let isSolo = 1;
41201}
41202def dep_A2_addsat : HInst<
41203(outs IntRegs:$Rd32),
41204(ins IntRegs:$Rs32, IntRegs:$Rt32),
41205"$Rd32 = add($Rs32,$Rt32):sat:deprecated",
41206tc_8a825db2, TypeALU64>, Enc_5ab2be {
41207let Inst{7-5} = 0b000;
41208let Inst{13-13} = 0b0;
41209let Inst{31-21} = 0b11010101100;
41210let hasNewValue = 1;
41211let opNewValue = 0;
41212let prefersSlot3 = 1;
41213let Defs = [USR_OVF];
41214}
41215def dep_A2_subsat : HInst<
41216(outs IntRegs:$Rd32),
41217(ins IntRegs:$Rt32, IntRegs:$Rs32),
41218"$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
41219tc_8a825db2, TypeALU64>, Enc_bd6011 {
41220let Inst{7-5} = 0b100;
41221let Inst{13-13} = 0b0;
41222let Inst{31-21} = 0b11010101100;
41223let hasNewValue = 1;
41224let opNewValue = 0;
41225let prefersSlot3 = 1;
41226let Defs = [USR_OVF];
41227}
41228def dep_S2_packhl : HInst<
41229(outs DoubleRegs:$Rdd32),
41230(ins IntRegs:$Rs32, IntRegs:$Rt32),
41231"$Rdd32 = packhl($Rs32,$Rt32):deprecated",
41232tc_5da50c4b, TypeALU64>, Enc_be32a5 {
41233let Inst{7-5} = 0b000;
41234let Inst{13-13} = 0b0;
41235let Inst{31-21} = 0b11010100000;
41236}
41237def dup_A2_add : HInst<
41238(outs IntRegs:$Rd32),
41239(ins IntRegs:$Rs32, IntRegs:$Rt32),
41240"$Rd32 = add($Rs32,$Rt32)",
41241tc_388f9897, TypeALU32_3op>, Requires<[HasV73]> {
41242let hasNewValue = 1;
41243let opNewValue = 0;
41244let AsmVariantName = "NonParsable";
41245let isPseudo = 1;
41246}
41247def dup_A2_addi : HInst<
41248(outs IntRegs:$Rd32),
41249(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41250"$Rd32 = add($Rs32,#$Ii)",
41251tc_388f9897, TypeALU32_ADDI>, Requires<[HasV73]> {
41252let hasNewValue = 1;
41253let opNewValue = 0;
41254let AsmVariantName = "NonParsable";
41255let isPseudo = 1;
41256let isExtendable = 1;
41257let opExtendable = 2;
41258let isExtentSigned = 1;
41259let opExtentBits = 16;
41260let opExtentAlign = 0;
41261}
41262def dup_A2_andir : HInst<
41263(outs IntRegs:$Rd32),
41264(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41265"$Rd32 = and($Rs32,#$Ii)",
41266tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41267let hasNewValue = 1;
41268let opNewValue = 0;
41269let AsmVariantName = "NonParsable";
41270let isPseudo = 1;
41271let isExtendable = 1;
41272let opExtendable = 2;
41273let isExtentSigned = 1;
41274let opExtentBits = 10;
41275let opExtentAlign = 0;
41276}
41277def dup_A2_combineii : HInst<
41278(outs DoubleRegs:$Rdd32),
41279(ins s32_0Imm:$Ii, s8_0Imm:$II),
41280"$Rdd32 = combine(#$Ii,#$II)",
41281tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41282let AsmVariantName = "NonParsable";
41283let isPseudo = 1;
41284let isExtendable = 1;
41285let opExtendable = 1;
41286let isExtentSigned = 1;
41287let opExtentBits = 8;
41288let opExtentAlign = 0;
41289}
41290def dup_A2_sxtb : HInst<
41291(outs IntRegs:$Rd32),
41292(ins IntRegs:$Rs32),
41293"$Rd32 = sxtb($Rs32)",
41294tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
41295let hasNewValue = 1;
41296let opNewValue = 0;
41297let AsmVariantName = "NonParsable";
41298let isPseudo = 1;
41299}
41300def dup_A2_sxth : HInst<
41301(outs IntRegs:$Rd32),
41302(ins IntRegs:$Rs32),
41303"$Rd32 = sxth($Rs32)",
41304tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
41305let hasNewValue = 1;
41306let opNewValue = 0;
41307let AsmVariantName = "NonParsable";
41308let isPseudo = 1;
41309}
41310def dup_A2_tfr : HInst<
41311(outs IntRegs:$Rd32),
41312(ins IntRegs:$Rs32),
41313"$Rd32 = $Rs32",
41314tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
41315let hasNewValue = 1;
41316let opNewValue = 0;
41317let AsmVariantName = "NonParsable";
41318let isPseudo = 1;
41319}
41320def dup_A2_tfrsi : HInst<
41321(outs IntRegs:$Rd32),
41322(ins s32_0Imm:$Ii),
41323"$Rd32 = #$Ii",
41324tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
41325let hasNewValue = 1;
41326let opNewValue = 0;
41327let AsmVariantName = "NonParsable";
41328let isPseudo = 1;
41329let isExtendable = 1;
41330let opExtendable = 1;
41331let isExtentSigned = 1;
41332let opExtentBits = 16;
41333let opExtentAlign = 0;
41334}
41335def dup_A2_zxtb : HInst<
41336(outs IntRegs:$Rd32),
41337(ins IntRegs:$Rs32),
41338"$Rd32 = zxtb($Rs32)",
41339PSEUDO, TypeMAPPING>, Requires<[HasV73]> {
41340let hasNewValue = 1;
41341let opNewValue = 0;
41342let AsmVariantName = "NonParsable";
41343let isPseudo = 1;
41344}
41345def dup_A2_zxth : HInst<
41346(outs IntRegs:$Rd32),
41347(ins IntRegs:$Rs32),
41348"$Rd32 = zxth($Rs32)",
41349tc_9124c04f, TypeALU32_2op>, Requires<[HasV73]> {
41350let hasNewValue = 1;
41351let opNewValue = 0;
41352let AsmVariantName = "NonParsable";
41353let isPseudo = 1;
41354}
41355def dup_A4_combineii : HInst<
41356(outs DoubleRegs:$Rdd32),
41357(ins s8_0Imm:$Ii, u32_0Imm:$II),
41358"$Rdd32 = combine(#$Ii,#$II)",
41359tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41360let AsmVariantName = "NonParsable";
41361let isPseudo = 1;
41362let isExtendable = 1;
41363let opExtendable = 2;
41364let isExtentSigned = 0;
41365let opExtentBits = 6;
41366let opExtentAlign = 0;
41367}
41368def dup_A4_combineir : HInst<
41369(outs DoubleRegs:$Rdd32),
41370(ins s32_0Imm:$Ii, IntRegs:$Rs32),
41371"$Rdd32 = combine(#$Ii,$Rs32)",
41372tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41373let AsmVariantName = "NonParsable";
41374let isPseudo = 1;
41375let isExtendable = 1;
41376let opExtendable = 1;
41377let isExtentSigned = 1;
41378let opExtentBits = 8;
41379let opExtentAlign = 0;
41380}
41381def dup_A4_combineri : HInst<
41382(outs DoubleRegs:$Rdd32),
41383(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41384"$Rdd32 = combine($Rs32,#$Ii)",
41385tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41386let AsmVariantName = "NonParsable";
41387let isPseudo = 1;
41388let isExtendable = 1;
41389let opExtendable = 2;
41390let isExtentSigned = 1;
41391let opExtentBits = 8;
41392let opExtentAlign = 0;
41393}
41394def dup_C2_cmoveif : HInst<
41395(outs IntRegs:$Rd32),
41396(ins PredRegs:$Pu4, s32_0Imm:$Ii),
41397"if (!$Pu4) $Rd32 = #$Ii",
41398tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41399let isPredicated = 1;
41400let isPredicatedFalse = 1;
41401let hasNewValue = 1;
41402let opNewValue = 0;
41403let AsmVariantName = "NonParsable";
41404let isPseudo = 1;
41405let isExtendable = 1;
41406let opExtendable = 2;
41407let isExtentSigned = 1;
41408let opExtentBits = 12;
41409let opExtentAlign = 0;
41410}
41411def dup_C2_cmoveit : HInst<
41412(outs IntRegs:$Rd32),
41413(ins PredRegs:$Pu4, s32_0Imm:$Ii),
41414"if ($Pu4) $Rd32 = #$Ii",
41415tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41416let isPredicated = 1;
41417let hasNewValue = 1;
41418let opNewValue = 0;
41419let AsmVariantName = "NonParsable";
41420let isPseudo = 1;
41421let isExtendable = 1;
41422let opExtendable = 2;
41423let isExtentSigned = 1;
41424let opExtentBits = 12;
41425let opExtentAlign = 0;
41426}
41427def dup_C2_cmovenewif : HInst<
41428(outs IntRegs:$Rd32),
41429(ins PredRegs:$Pu4, s32_0Imm:$Ii),
41430"if (!$Pu4.new) $Rd32 = #$Ii",
41431tc_4ac61d92, TypeALU32_2op>, Requires<[HasV73]> {
41432let isPredicated = 1;
41433let isPredicatedFalse = 1;
41434let hasNewValue = 1;
41435let opNewValue = 0;
41436let AsmVariantName = "NonParsable";
41437let isPredicatedNew = 1;
41438let isPseudo = 1;
41439let isExtendable = 1;
41440let opExtendable = 2;
41441let isExtentSigned = 1;
41442let opExtentBits = 12;
41443let opExtentAlign = 0;
41444}
41445def dup_C2_cmovenewit : HInst<
41446(outs IntRegs:$Rd32),
41447(ins PredRegs:$Pu4, s32_0Imm:$Ii),
41448"if ($Pu4.new) $Rd32 = #$Ii",
41449tc_4ac61d92, TypeALU32_2op>, Requires<[HasV73]> {
41450let isPredicated = 1;
41451let hasNewValue = 1;
41452let opNewValue = 0;
41453let AsmVariantName = "NonParsable";
41454let isPredicatedNew = 1;
41455let isPseudo = 1;
41456let isExtendable = 1;
41457let opExtendable = 2;
41458let isExtentSigned = 1;
41459let opExtentBits = 12;
41460let opExtentAlign = 0;
41461}
41462def dup_C2_cmpeqi : HInst<
41463(outs PredRegs:$Pd4),
41464(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41465"$Pd4 = cmp.eq($Rs32,#$Ii)",
41466tc_388f9897, TypeALU32_2op>, Requires<[HasV73]> {
41467let AsmVariantName = "NonParsable";
41468let isPseudo = 1;
41469let isExtendable = 1;
41470let opExtendable = 2;
41471let isExtentSigned = 1;
41472let opExtentBits = 10;
41473let opExtentAlign = 0;
41474}
41475def dup_L2_deallocframe : HInst<
41476(outs DoubleRegs:$Rdd32),
41477(ins IntRegs:$Rs32),
41478"$Rdd32 = deallocframe($Rs32):raw",
41479tc_aee6250c, TypeLD>, Requires<[HasV73]> {
41480let accessSize = DoubleWordAccess;
41481let AsmVariantName = "NonParsable";
41482let mayLoad = 1;
41483let Uses = [FRAMEKEY];
41484let Defs = [R29];
41485let isPseudo = 1;
41486}
41487def dup_L2_loadrb_io : HInst<
41488(outs IntRegs:$Rd32),
41489(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41490"$Rd32 = memb($Rs32+#$Ii)",
41491tc_eed07714, TypeLD>, Requires<[HasV73]> {
41492let hasNewValue = 1;
41493let opNewValue = 0;
41494let addrMode = BaseImmOffset;
41495let accessSize = ByteAccess;
41496let AsmVariantName = "NonParsable";
41497let mayLoad = 1;
41498let isPseudo = 1;
41499let isExtendable = 1;
41500let opExtendable = 2;
41501let isExtentSigned = 1;
41502let opExtentBits = 11;
41503let opExtentAlign = 0;
41504}
41505def dup_L2_loadrd_io : HInst<
41506(outs DoubleRegs:$Rdd32),
41507(ins IntRegs:$Rs32, s29_3Imm:$Ii),
41508"$Rdd32 = memd($Rs32+#$Ii)",
41509tc_eed07714, TypeLD>, Requires<[HasV73]> {
41510let addrMode = BaseImmOffset;
41511let accessSize = DoubleWordAccess;
41512let AsmVariantName = "NonParsable";
41513let mayLoad = 1;
41514let isPseudo = 1;
41515let isExtendable = 1;
41516let opExtendable = 2;
41517let isExtentSigned = 1;
41518let opExtentBits = 14;
41519let opExtentAlign = 3;
41520}
41521def dup_L2_loadrh_io : HInst<
41522(outs IntRegs:$Rd32),
41523(ins IntRegs:$Rs32, s31_1Imm:$Ii),
41524"$Rd32 = memh($Rs32+#$Ii)",
41525tc_eed07714, TypeLD>, Requires<[HasV73]> {
41526let hasNewValue = 1;
41527let opNewValue = 0;
41528let addrMode = BaseImmOffset;
41529let accessSize = HalfWordAccess;
41530let AsmVariantName = "NonParsable";
41531let mayLoad = 1;
41532let isPseudo = 1;
41533let isExtendable = 1;
41534let opExtendable = 2;
41535let isExtentSigned = 1;
41536let opExtentBits = 12;
41537let opExtentAlign = 1;
41538}
41539def dup_L2_loadri_io : HInst<
41540(outs IntRegs:$Rd32),
41541(ins IntRegs:$Rs32, s30_2Imm:$Ii),
41542"$Rd32 = memw($Rs32+#$Ii)",
41543tc_eed07714, TypeLD>, Requires<[HasV73]> {
41544let hasNewValue = 1;
41545let opNewValue = 0;
41546let addrMode = BaseImmOffset;
41547let accessSize = WordAccess;
41548let AsmVariantName = "NonParsable";
41549let mayLoad = 1;
41550let isPseudo = 1;
41551let isExtendable = 1;
41552let opExtendable = 2;
41553let isExtentSigned = 1;
41554let opExtentBits = 13;
41555let opExtentAlign = 2;
41556}
41557def dup_L2_loadrub_io : HInst<
41558(outs IntRegs:$Rd32),
41559(ins IntRegs:$Rs32, s32_0Imm:$Ii),
41560"$Rd32 = memub($Rs32+#$Ii)",
41561tc_eed07714, TypeLD>, Requires<[HasV73]> {
41562let hasNewValue = 1;
41563let opNewValue = 0;
41564let addrMode = BaseImmOffset;
41565let accessSize = ByteAccess;
41566let AsmVariantName = "NonParsable";
41567let mayLoad = 1;
41568let isPseudo = 1;
41569let isExtendable = 1;
41570let opExtendable = 2;
41571let isExtentSigned = 1;
41572let opExtentBits = 11;
41573let opExtentAlign = 0;
41574}
41575def dup_L2_loadruh_io : HInst<
41576(outs IntRegs:$Rd32),
41577(ins IntRegs:$Rs32, s31_1Imm:$Ii),
41578"$Rd32 = memuh($Rs32+#$Ii)",
41579tc_eed07714, TypeLD>, Requires<[HasV73]> {
41580let hasNewValue = 1;
41581let opNewValue = 0;
41582let addrMode = BaseImmOffset;
41583let accessSize = HalfWordAccess;
41584let AsmVariantName = "NonParsable";
41585let mayLoad = 1;
41586let isPseudo = 1;
41587let isExtendable = 1;
41588let opExtendable = 2;
41589let isExtentSigned = 1;
41590let opExtentBits = 12;
41591let opExtentAlign = 1;
41592}
41593def dup_S2_allocframe : HInst<
41594(outs IntRegs:$Rx32),
41595(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
41596"allocframe($Rx32,#$Ii):raw",
41597tc_74a42bda, TypeST>, Requires<[HasV73]> {
41598let hasNewValue = 1;
41599let opNewValue = 0;
41600let addrMode = BaseImmOffset;
41601let accessSize = DoubleWordAccess;
41602let AsmVariantName = "NonParsable";
41603let mayStore = 1;
41604let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
41605let Defs = [R30];
41606let isPseudo = 1;
41607let Constraints = "$Rx32 = $Rx32in";
41608}
41609def dup_S2_storerb_io : HInst<
41610(outs),
41611(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
41612"memb($Rs32+#$Ii) = $Rt32",
41613tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41614let addrMode = BaseImmOffset;
41615let accessSize = ByteAccess;
41616let AsmVariantName = "NonParsable";
41617let mayStore = 1;
41618let isPseudo = 1;
41619let isExtendable = 1;
41620let opExtendable = 1;
41621let isExtentSigned = 1;
41622let opExtentBits = 11;
41623let opExtentAlign = 0;
41624}
41625def dup_S2_storerd_io : HInst<
41626(outs),
41627(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
41628"memd($Rs32+#$Ii) = $Rtt32",
41629tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41630let addrMode = BaseImmOffset;
41631let accessSize = DoubleWordAccess;
41632let AsmVariantName = "NonParsable";
41633let mayStore = 1;
41634let isPseudo = 1;
41635let isExtendable = 1;
41636let opExtendable = 1;
41637let isExtentSigned = 1;
41638let opExtentBits = 14;
41639let opExtentAlign = 3;
41640}
41641def dup_S2_storerh_io : HInst<
41642(outs),
41643(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
41644"memh($Rs32+#$Ii) = $Rt32",
41645tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41646let addrMode = BaseImmOffset;
41647let accessSize = HalfWordAccess;
41648let AsmVariantName = "NonParsable";
41649let mayStore = 1;
41650let isPseudo = 1;
41651let isExtendable = 1;
41652let opExtendable = 1;
41653let isExtentSigned = 1;
41654let opExtentBits = 12;
41655let opExtentAlign = 1;
41656}
41657def dup_S2_storeri_io : HInst<
41658(outs),
41659(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
41660"memw($Rs32+#$Ii) = $Rt32",
41661tc_a9edeffa, TypeST>, Requires<[HasV73]> {
41662let addrMode = BaseImmOffset;
41663let accessSize = WordAccess;
41664let AsmVariantName = "NonParsable";
41665let mayStore = 1;
41666let isPseudo = 1;
41667let isExtendable = 1;
41668let opExtendable = 1;
41669let isExtentSigned = 1;
41670let opExtentBits = 13;
41671let opExtentAlign = 2;
41672}
41673def dup_S4_storeirb_io : HInst<
41674(outs),
41675(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
41676"memb($Rs32+#$Ii) = #$II",
41677tc_838c4d7a, TypeV4LDST>, Requires<[HasV73]> {
41678let addrMode = BaseImmOffset;
41679let accessSize = ByteAccess;
41680let AsmVariantName = "NonParsable";
41681let mayStore = 1;
41682let isPseudo = 1;
41683let isExtendable = 1;
41684let opExtendable = 2;
41685let isExtentSigned = 1;
41686let opExtentBits = 8;
41687let opExtentAlign = 0;
41688}
41689def dup_S4_storeiri_io : HInst<
41690(outs),
41691(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
41692"memw($Rs32+#$Ii) = #$II",
41693tc_838c4d7a, TypeV4LDST>, Requires<[HasV73]> {
41694let addrMode = BaseImmOffset;
41695let accessSize = WordAccess;
41696let AsmVariantName = "NonParsable";
41697let mayStore = 1;
41698let isPseudo = 1;
41699let isExtendable = 1;
41700let opExtendable = 2;
41701let isExtentSigned = 1;
41702let opExtentBits = 8;
41703let opExtentAlign = 0;
41704}
41705